xxmrglw

VSX Vector Merge Low Word

xxmrglw XT, XA, XB

Merges low words from two VSRs.

Details

Merges the low-order words (words 2 and 3) from VSX registers XA and XB into XT, interleaving them as: XT[0:31] ← XA[64:95], XT[32:63] ← XB[64:95], XT[64:95] ← XA[96:127], XT[96:127] ← XB[96:127]. This is a VSX instruction with no condition register or status flag updates.

Pseudocode Operation

XT[0:31] ← XA[64:95]
XT[32:63] ← XB[64:95]
XT[64:95] ← XA[96:127]
XT[96:127] ← XB[96:127]

Programming Note

The xxmrglw instruction is commonly used for merging specific word elements from two VSX vectors into a new vector. Ensure that the VSX facility is enabled by checking and setting the appropriate bit in the MSR register. This instruction operates on 128-bit vectors, so source and destination registers must be properly aligned. Be cautious of potential exceptions if the VSX facility is not available or if there are alignment issues with the vector registers.

Example

xxmrglw vs1, vs2, vs3

Encoding

Binary Layout
60
0
XT
6
XA
11
XB
16
82
21
 
Format XX3-form
Opcode 0xF0000190
Extension VSX
Registers Altered MSR

Operands

  • XT
    Target
  • XA
    Src A
  • XB
    Src B