vsubcuw

Vector Subtract Carryout Unsigned Word

vsubcuw vD, vA, vB

Subtracts the unsigned integer values in word elements of two vector registers and writes the result to another vector register, along with the carry-out.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

1408

21:31

Format VX-form

Opcode 0x10000580

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vsubcuw vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vsubcuw, the unsigned integer value in word element i of VSR[VRB+32] is subtracted from the unsigned integer value in word element i of VSR[VRA+32]. The complement of the borrow out of bit 0 of the 32-bit difference is zero-extended to 32 bits and placed into word element i of VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ←EXTZ(VSR[VRA+32].word[i])
    src2 ←EXTZ(¬VSR[VRB+32].word[i])
    VSR[VRT+32].word[i] ←EXTZ32((src1+src2+1) >> 32)
end

Programming Note

The vsubcuw instruction performs an unsigned subtraction with carryout on each word element of the input vectors. It is useful for operations requiring precise control over overflow handling. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation does not require any specific alignment, but inputs must be correctly aligned to 128-bit boundaries as per standard vector register usage.