xsdivqpo

VSX Scalar Divide Quad-Precision Odd

xsdivqpo vD, vA, vB

Used for Quad-Precision arithmetic on hardware that splits quads.

Details

Divides the odd (high-order) portion of a 128-bit quad-precision floating-point value in VSR vA by the odd portion in VSR vB, placing the result in VSR vD. This instruction is used on systems that split quad-precision operands into even/odd register pairs. FPSCR exception flags are updated, including division-by-zero detection (ZX). Requires VSX support.

Pseudocode Operation

vD ← (vA / vB) as quad-precision (odd portion operation)
FPSCR[XX,ZX,OX,UX,VXIDI,VXISI] ← updated based on operation result

Programming Note

The xsdivqpo instruction performs a scalar divide operation on two quad-precision floating-point values, rounding the result to the nearest odd integer when there is a tie. Ensure that VSX is enabled in the MSR register; otherwise, an exception will be raised. Be cautious with division by zero, as it results in infinity or NaN depending on the sign of the dividend.

Example

xsdivqpo vd, va, vb

Encoding

Binary Layout
63
0
vD
6
vA
11
vB
16
548
21
/
31
 
Format X-form
Opcode 0xFC000448
Extension VSX
Registers Altered FPSCR, MSR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B