mfsrin

Move From Segment Register Indirect

mfsrin RT, RB

Indirect read of segment register using RB.

Encoding

Binary Layout

31

0:5

RT

6:10

/

11:15

RB

16:20

659

21:30

/

31

 

Format X-form

Opcode 0x7C000526

Extension Base

Operands

• RT
  Target
• RB
  Effective Addr

Example

mfsrin r3, r5

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Move the contents of the segment register selected by bits 0-3 of GPR RB into GPR RT. This is an indirect read of the 32-bit segment register and is not available in 64-bit mode. No status fields are affected.

Operation

SR_index ← RB[0:3]
RT ← SR[SR_index]