What's new

What has been added and fixed, newest first. Follow in a feed reader

  1. Decode AMD GPU instructions

    The decoder now reads 32, 64 and 96-bit AMDGPU instructions for a GPU generation you choose, with every field broken out and register numbers where they can be read reliably. Paste bytes as LLVM prints them or dwords as llvm-objdump does. Checked against LLVM's own assembler tests: 25,923 instructions decoded, none to the wrong instruction.

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  2. Search from your browser's address bar

    Add instructionsets.com as a search engine and type an instruction straight into the address bar. A single exact match opens its page, and anything else is listed in full. Pressing Enter in any search box on the site now shows every result instead of only the first ten.

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  3. This page, and a feed to follow it

    Changes to the site are listed here and published as an RSS feed, so a feed reader can tell you when something is added or fixed.

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  4. PowerISA extended mnemonics show every form

    69 PowerISA pages printed blank cells in their Extended Mnemonics table. Every form is shown now, and where the source gives no equivalent instruction the page says so rather than leaving a gap.

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  5. New note: measuring the reference instead of the data

    How the accuracy of this reference was measured against its own vendor specifications, the 18 wrong RISC-V encodings that turned up, and the four times the audit itself was the problem.

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  6. A way to reach us from every page

    Report an error, ask a question or suggest something from the Contact page. The form opens your own email app with the message ready to send.

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  7. Comparison destinations, and bit diagrams that show every field

    AMDGPU comparisons (v_cmp_) now list the vcc destination they write. Bit diagrams wrap instead of scrolling sideways, which had hidden part of most ARM diagrams on a desktop screen.

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  8. Bit layouts for 1,514 AMDGPU instructions

    Taken from AMD's machine-readable ISA specification, each checked by rebuilding one of AMD's own encoding identifiers from the instruction's opcode. Opcodes change between GPU generations, so each diagram names its generation and says where the others differ.

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  9. Operands for 1,635 AMDGPU instructions

    Named and in order, with whether each is read or written, from AMD's machine-readable ISA specification. AMDGPU pages with no operand list went from 910 to 142.

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  10. Pages that fit a phone, and a search shortcut

    Instruction pages no longer run wider than a phone screen, wide tables scroll inside their panel, Ctrl+K or / jumps to search, and table headers sort from the keyboard.

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  11. 28 new cross-architecture comparisons

    19 comparisons of how x86, ARM, RISC-V and PowerISA each express the same operation, including where one has no instruction for it, and 9 of NVIDIA PTX against AMDGPU.

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  12. Instruction word decoder

    Paste a 32-bit ARM or RISC-V instruction word and get the instruction with every field broken out. It carries only the 908 encodings whose bit pattern rebuilds their own opcode, so it declines rather than guesses.

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  13. The whole dataset, in the public domain

    Every instruction record on the site, as JSON and JSONL under CC0. Use it for anything: no permission and no attribution needed.

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  14. Accuracy measured against the vendor manuals

    A published audit of how well the data agrees with the vendor specifications. It found 18 wrong RISC-V encodings, which were fixed.

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