v_ffbh_i32 GPU Native ISA AMD Vector

Vector Arithmetic

v_ffbh_i32

Count the number of leading bits that are the same as the sign bit of a vector input and store the result into a vector register.

Also written as v_cls_i32. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
0111111
31:25
VDST
24:17
00101111
16:9
SRC0
8:0
 

The ENC_VOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 47 in OP rebuilds 0x7E005E00, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 2 (opcode 59), AMD RDNA 1 (opcode 59). The same in AMD CDNA 3, AMD CDNA 2, AMD CDNA 1.

Format VOP1
Width 32 bits
Opcode 47
Identifier 0x7E005E00

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR, FMT_NUM_I32)
  • SRC0
    Read. N/A Data format: N/A (OPR_SRC, FMT_NUM_I32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP1 encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related PTX Concepts

Find Most-Significant Set Bit ↗
equivalent with restrictions
bfind (PTX)

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Count the number of leading bits that are the same as the sign bit of a vector input and store the result into a vector register. Store -1 if all input bits are the same.

Semantics

D0.i32 = -1; // Set if all bits are the same for i in 1 : 31 do // Search from MSB if S0.i32[31 - i] != S0.i32[31] then D0.i32 = i; break endif endfor

Example

V_FFBH_I32(0x00000000) => 0xffffffff
V_FFBH_I32(0x40000000) => 1
V_FFBH_I32(0x80000000) => 1
V_FFBH_I32(0x0fffffff) => 4

Reproduced from AMD's official "AMD Instinct MI300" ISA Reference Guide for technical accuracy.

Sources