v_ffbh_u32 GPU Native ISA AMD Vector

Vector Arithmetic

v_ffbh_u32

Count the number of leading "0" bits before the first "1" in a vector input and store the result into a vector register.

Also written as v_clz_i32_u32. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
0111111
31:25
VDST
24:17
00101101
16:9
SRC0
8:0
 

The ENC_VOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 45 in OP rebuilds 0x7E005A00, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 2 (opcode 57), AMD RDNA 1 (opcode 57). The same in AMD CDNA 3, AMD CDNA 2, AMD CDNA 1.

Format VOP1
Width 32 bits
Opcode 45
Identifier 0x7E005A00

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR, FMT_NUM_I32)
  • SRC0
    Read. N/A Data format: N/A (OPR_SRC, FMT_NUM_U32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP1 encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related PTX Concepts

Count Leading Zeros ↗
equivalent with restrictions
clz (PTX)
Find Most-Significant Set Bit ↗
equivalent with restrictions
bfind (PTX)

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Count the number of leading "0" bits before the first "1" in a vector input and store the result into a vector register. Store -1 if there are no "1" bits.

Semantics

D0.i32 = -1; // Set if no ones are found for i in 0 : 31 do // Search from MSB if S0.u32[31 - i] == 1'1U then D0.i32 = i; break endif endfor

Example

V_FFBH_U32(0x00000000) => 0xffffffff
V_FFBH_U32(0x800000ff) => 0
V_FFBH_U32(0x100000ff) => 3
V_FFBH_U32(0x0000ffff) => 16

Reproduced from AMD's official "AMD Instinct MI300" ISA Reference Guide for technical accuracy.

Sources