v_ffbh_u32 GPU Native ISA AMD Vector

V FFBH U32 Vector Arithmetic

v_ffbh_u32

Count the number of leading "0" bits before the first "1" in a vector input and store the result into a vector register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP1) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP1
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related PTX Concepts

Count Leading Zeros ↗
equivalent with restrictions
clz (PTX)
Find Most-Significant Set Bit ↗
equivalent with restrictions
bfind (PTX)

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Count the number of leading "0" bits before the first "1" in a vector input and store the result into a vector register. Store -1 if there are no "1" bits.

Semantics

D0.i32 = -1; // Set if no ones are found for i in 0 : 31 do // Search from MSB if S0.u32[31 - i] == 1'1U then D0.i32 = i; break endif endfor

Example

V_FFBH_U32(0x00000000) => 0xffffffff
V_FFBH_U32(0x800000ff) => 0
V_FFBH_U32(0x100000ff) => 3
V_FFBH_U32(0x0000ffff) => 16

Reproduced from AMD's official "AMD Instinct MI300" ISA Reference Guide for technical accuracy.

Sources