clz GPU Virtual ISA NVIDIA

Count Leading Zeros Integer Arithmetic Instructions

clz.type d, a;

Count the number of leading zero bits in an integer operand.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 2.0
Minimum Target sm_20

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
clz.type d, a; b32, b64 sm_20 Count leading zeros.

Operands

  • d
    Destination register (u32)
  • a
    Source operand

At a Glance

Data Types b32, b64

Related AMDGPU Concepts

Count Leading Zeros ↗
equivalent with restrictions
s_flbit_i32 (AMDGPU)
v_ffbh_u32 (AMDGPU)

Related

More in Integer Arithmetic Instructions

Reference

NVIDIA PTX ISA

Description

Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d. Operand a has the instruction type, and destination d has type.u32. For.b32 type, the number of leading zeros is between 0 and 32, inclusively. For.b64 type, the number of leading zeros is between 0 and 64, inclusively.

Semantics

d = number of leading 0-bits in a, counted from the most-significant bit.

Examples

clz.b32  d, a;
clz.b64  cnt, X;  // cnt is .u32

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources