bfe GPU Virtual ISA NVIDIA

bfe Integer Arithmetic Instructions

bfe.type d, a, b, c;

Extract bit field from a and place the zero or sign-extended result in d.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 2.0
Minimum Target sm_20

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
bfe.type d, a, b, c; sm_20 Extract bit field from a and place the zero or sign-extended result in d. Source b gives the bit field starting bit position, and source c gives the bit field length in bits. (see the official PTX ISA docs for the full description)

Operands

  • d
    Destination register
  • a
    Source operand
  • b
    Source operand
  • c
    Source operand

At a Glance

Data Types -

Related AMDGPU Concepts

Bit-Field Extract ↗
equivalent with restrictions
v_bfe_u32 (AMDGPU)
v_bfe_i32 (AMDGPU)
s_bfe_u32 (AMDGPU)

Related

More in Integer Arithmetic Instructions

Reference

NVIDIA PTX ISA

Description

Extract bit field from a and place the zero or sign-extended result in d. Source b gives the bit field starting bit position, and source c gives the bit field length in bits. Operands a and d have the same type as the instruction type. Operands b and c are type.u32, but are restricted to the 8-bit value range 0..255. The sign bit of the extracted field is defined as:.u32,.u64: zero.s32,.s64: msb of input a if the extracted field extends beyond the msb of a msb of extracted field, otherwise If the bit field length is zero, the result is zero. The destination d is padded with the sign bit of the extracted field. (see the official PTX ISA docs for the full description)

Semantics

msb = (.type==.u32 || .type==.s32) ? 31 : 63; pos = b & 0xff; // pos restricted to 0..255 range len = c & 0xff; // len restricted to 0..255 range if (.type==.u32 || .type==.u64 || len==0) sbit = 0; else sbit = a[min(pos+len-1,msb)]; d = 0; for (i=0; i<=msb; i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit; }

Examples

bfe.b32  d,a,start,len;

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources