s_bfe_u32 GPU Native ISA AMD Scalar

S BFE U32 Scalar Arithmetic

s_bfe_u32

Extract an unsigned bitfield from the first input using field offset and size encoded in the second input, store the result into a scalar register…

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (SOP2) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format SOP2
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related PTX Concepts

Bit-Field Extract ↗
equivalent with restrictions
bfe (PTX)

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Description

Extract an unsigned bitfield from the first input using field offset and size encoded in the second input, store the result into a scalar register and set SCC iff the result is nonzero.

Semantics

D0.u32 = ((S0.u32 >> S1[4 : 0].u32) & ((1U << S1[22 : 16].u32) - 1U)); SCC = D0.u32 != 0U

Example

s_bfe_u32 s0, 0, s2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources