s_ashr_i32 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_ashr_i32

Given a shift count in the second scalar input, calculate the arithmetic shift right (preserving sign bit) of the first scalar input, store the…

Encoding

Binary Layout (AMD CDNA 5)
10
31:30
0001100
29:23
SDST
22:16
SSRC1
15:8
SSRC0
7:0
 

The ENC_SOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 12 in OP rebuilds 0x86000000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 32), AMD CDNA 3 (opcode 32), AMD CDNA 2 (opcode 32), AMD CDNA 1 (opcode 32), AMD RDNA 2 (opcode 34), AMD RDNA 1 (opcode 34). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOP2
Width 32 bits
Opcode 12
Identifier 0x86000000

Operands

  • SDST
    Written. All scalar destination operands. Data format: Signed 32-bit integral data. (OPR_SDST, FMT_NUM_I32)
  • SSRC0
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: Signed 32-bit integral data. (OPR_SSRC, FMT_NUM_I32)
  • SSRC1
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: Unsigned 32-bit integral data. (OPR_SSRC, FMT_NUM_U32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP2 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related PTX Concepts

Arithmetic Shift Right ↗
equivalent with restrictions
shr (PTX)

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Description

Given a shift count in the second scalar input, calculate the arithmetic shift right (preserving sign bit) of the first scalar input, store the result into a scalar register and set SCC iff the result is nonzero.

Semantics

D0.i32 = 32'I(signext(S0.i32) >> S1[4 : 0].u32); SCC = D0.i32 != 0

Example

s_ashr_i32 s0, 0, s2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources