s_ashr_i32 GPU Native ISA AMD Scalar

S ASHR I32 Scalar Arithmetic

s_ashr_i32

Given a shift count in the second scalar input, calculate the arithmetic shift right (preserving sign bit) of the first scalar input, store the…

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (SOP2) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format SOP2
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related PTX Concepts

Arithmetic Shift Right ↗
equivalent with restrictions
shr (PTX)

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Description

Given a shift count in the second scalar input, calculate the arithmetic shift right (preserving sign bit) of the first scalar input, store the result into a scalar register and set SCC iff the result is nonzero.

Semantics

D0.i32 = 32'I(signext(S0.i32) >> S1[4 : 0].u32); SCC = D0.i32 != 0

Example

s_ashr_i32 s0, 0, s2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources