s_alloc_vgpr GPU Native ISA AMD Scalar

Scalar Arithmetic

s_alloc_vgpr

Attempt to set the wave's VGPR allocation to the specified number of VGPRs (or greater).

Encoding

Binary Layout (AMD CDNA 5)
101111101
31:23
SDST
22:16
01010011
15:8
SSRC0
7:0
 

The ENC_SOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 83 in OP rebuilds 0xBE805300, an identifier AMD lists for this encoding. The same in AMD RDNA 4.

Format SOP1
Width 32 bits
Opcode 83
Identifier 0xBE805300

Operands

  • SSRC0
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: 32 bits of arbitrary data. (OPR_SSRC, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Description

Attempt to set the wave's VGPR allocation to the specified number of VGPRs (or greater). The desired VGPR count may be specified as a constant or in an SGPR. The request is rounded up to the next block size so a successful allocation may include more than the requested number of VGPRs.

Example

s_alloc_vgpr 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx13_asm_sop1.s). Not from an AMD document, and not authored here.

Sources