s_absdiff_i32 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_absdiff_i32

Calculate the absolute value of difference between two scalar inputs, store the result into a scalar register and set SCC iff the result is nonzero.

Encoding

Binary Layout (AMD CDNA 5)
10
31:30
0000110
29:23
SDST
22:16
SSRC1
15:8
SSRC0
7:0
 

The ENC_SOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 6 in OP rebuilds 0x83000000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 42), AMD CDNA 3 (opcode 42), AMD CDNA 2 (opcode 42), AMD CDNA 1 (opcode 42), AMD RDNA 2 (opcode 44), AMD RDNA 1 (opcode 44). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOP2
Width 32 bits
Opcode 6
Identifier 0x83000000

Operands

  • SDST
    Written. All scalar destination operands. Data format: Signed 32-bit integral data. (OPR_SDST, FMT_NUM_I32)
  • SSRC0
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: Signed 32-bit integral data. (OPR_SSRC, FMT_NUM_I32)
  • SSRC1
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: Signed 32-bit integral data. (OPR_SSRC, FMT_NUM_I32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP2 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

D0.i32 = S0.i32 - S1.i32; if D0.i32 < 0 then D0.i32 = -D0.i32 endif; SCC = D0.i32 != 0

Example

S_ABSDIFF_I32(0x00000002, 0x00000005) => 0x00000003
S_ABSDIFF_I32(0xffffffff, 0x00000000) => 0x00000001
S_ABSDIFF_I32(0x80000000, 0x00000000) => 0x80000000     // Note: result is negative!
S_ABSDIFF_I32(0x80000000, 0x00000001) => 0x7fffffff

Reproduced from AMD's official "AMD Instinct MI300" ISA Reference Guide for technical accuracy.

Sources