s_addc_u32 GPU Native ISA AMD Scalar

S ADDC U32 Scalar Arithmetic

s_addc_u32

Add two unsigned 32-bit integer inputs and a carry-in bit from SCC, store the result into a scalar register and store the carry-out bit into SCC.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (SOP2) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format SOP2
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related PTX Concepts

Add with Carry-In ↗
equivalent with restrictions
addc (PTX)

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

tmp = 64'U(S0.u32) + 64'U(S1.u32) + SCC.u64; SCC = tmp >= 0x100000000ULL ? 1'1U : 1'0U; // unsigned overflow or carry-out for S_ADDC_U32. D0.u32 = tmp.u32

Example

s_addc_u32 s0, 0, s2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources