s_addc_u32 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_addc_u32

Add two unsigned 32-bit integer inputs and a carry-in bit from SCC, store the result into a scalar register and store the carry-out bit into SCC.

Also written as s_add_co_ci_u32. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
10
31:30
0000100
29:23
SDST
22:16
SSRC1
15:8
SSRC0
7:0
 

The ENC_SOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 4 in OP rebuilds 0x82000000, an identifier AMD lists for this encoding. The same in the other 7 generations that define it.

Format SOP2
Width 32 bits
Opcode 4
Identifier 0x82000000

Operands

  • SDST
    Written. N/A Data format: N/A (OPR_SDST, FMT_NUM_U32)
  • SSRC0
    Read. N/A Data format: N/A (OPR_SSRC, FMT_NUM_U32)
  • SSRC1
    Read. N/A Data format: N/A (OPR_SSRC, FMT_NUM_U32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP2 encoding (AMD CDNA 4).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related PTX Concepts

Add with Carry-In ↗
equivalent with restrictions
addc (PTX)

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

tmp = 64'U(S0.u32) + 64'U(S1.u32) + SCC.u64; SCC = tmp >= 0x100000000ULL ? 1'1U : 1'0U; // unsigned overflow or carry-out for S_ADDC_U32. D0.u32 = tmp.u32

Example

s_addc_u32 s0, 0, s2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources