s_addk_co_i32 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_addk_co_i32

Add a scalar input and the sign extension of a literal 16-bit constant, store the result into a scalar register and store the carry-out bit into SCC.

Also written as s_addk_i32. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 5)
1011
31:28
01111
27:23
SDST
22:16
SIMM16
15:0
 

The ENC_SOPK layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 15 in OP rebuilds 0xB7800000, an identifier AMD lists for this encoding. The same in AMD RDNA 4.

Format SOPK
Width 32 bits
Opcode 15
Identifier 0xB7800000

Operands

  • SDST
    Written. All scalar destination operands. Data format: Signed 32-bit integral data. (OPR_SDST, FMT_NUM_I32)
  • SIMM16
    Read. 16-bit integer constant. Data format: Signed 16-bit integral data. (OPR_SIMM16, FMT_NUM_I16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPK encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Example

s_addk_co_i32 s0, 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx13_asm_sopk.s). Not from an AMD document, and not authored here.

Sources