s_bcnt1_i32_b32 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_bcnt1_i32_b32

Count the number of "1" bits in a scalar input, store the result into a scalar register and set SCC iff the result is nonzero.

Encoding

Binary Layout (AMD CDNA 5)
101111101
31:23
SDST
22:16
00011000
15:8
SSRC0
7:0
 

The ENC_SOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 24 in OP rebuilds 0xBE801800, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 12), AMD CDNA 3 (opcode 12), AMD CDNA 2 (opcode 12), AMD CDNA 1 (opcode 12), AMD RDNA 2 (opcode 15), AMD RDNA 1 (opcode 15). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOP1
Width 32 bits
Opcode 24
Identifier 0xBE801800

Operands

  • SDST
    Written. All scalar destination operands. Data format: Signed 32-bit integral data. (OPR_SDST, FMT_NUM_I32)
  • SSRC0
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: Unsigned 32-bit integral data. (OPR_SSRC, FMT_NUM_U32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

tmp = 0; for i in 0 : 31 do tmp += S0.u32[i] == 1'1U ? 1 : 0 endfor; D0.i32 = tmp; SCC = D0.u32 != 0U

Example

S_BCNT1_I32_B32(0x00000000) => 0
S_BCNT1_I32_B32(0xcccccccc) => 16
S_BCNT1_I32_B32(0xffffffff) => 32

Reproduced from AMD's official "AMD Instinct MI300" ISA Reference Guide for technical accuracy.

Sources