s_bfe_i64 GPU Native ISA AMD Scalar
S BFE I64 Scalar Arithmetic
s_bfe_i64
Extract a signed bitfield from the first input using field offset and size encoded in the second input, store the result into a scalar register and…
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (SOP2)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in Scalar Arithmetic
Reference
AMDGPU / GFX ISA
Description
Extract a signed bitfield from the first input using field offset and size encoded in the second input, store the result into a scalar register and set SCC iff the result is nonzero.
Semantics
tmp.i64 = ((S0.i64 >> S1[5 : 0].u32) & ((1LL << S1[22 : 16].u32) - 1LL));
D0.i64 = signext_from_bit(tmp.i64, S1[22 : 16].u32);
SCC = D0.i64 != 0LL
Example
s_bfe_i64 s[0:1], 0, s4A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 105. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project