s_bfe_i64 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_bfe_i64

Extract a signed bitfield from the first input using field offset and size encoded in the second input, store the result into a scalar register and…

Encoding

Binary Layout (AMD CDNA 5)
10
31:30
0101001
29:23
SDST
22:16
SSRC1
15:8
SSRC0
7:0
 

The ENC_SOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 41 in OP rebuilds 0x94800000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 40), AMD CDNA 3 (opcode 40), AMD CDNA 2 (opcode 40), AMD CDNA 1 (opcode 40), AMD RDNA 2 (opcode 42), AMD RDNA 1 (opcode 42). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOP2
Width 32 bits
Opcode 41
Identifier 0x94800000

Operands

  • SDST
    Written. All scalar destination operands. Data format: Signed 64-bit integral data. (OPR_SDST, FMT_NUM_I64)
  • SSRC0
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: Signed 64-bit integral data. (OPR_SSRC, FMT_NUM_I64)
  • SSRC1
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: Unsigned 32-bit integral data. (OPR_SSRC, FMT_NUM_U32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP2 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Description

Extract a signed bitfield from the first input using field offset and size encoded in the second input, store the result into a scalar register and set SCC iff the result is nonzero.

Semantics

tmp.i64 = ((S0.i64 >> S1[5 : 0].u32) & ((1LL << S1[22 : 16].u32) - 1LL)); D0.i64 = signext_from_bit(tmp.i64, S1[22 : 16].u32); SCC = D0.i64 != 0LL

Example

s_bfe_i64 s[0:1], 0, s4

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources