s_bfm_b32 GPU Native ISA AMD Scalar
S BFM B32 Scalar Arithmetic
s_bfm_b32
Calculate a bitfield mask given a field offset and size and store the result in a scalar register.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (SOP2)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in Scalar Arithmetic
Reference
AMDGPU / GFX ISA
Semantics
D0.u32 = (((1U << S0[4 : 0].u32) - 1U) << S1[4 : 0].u32)
Example
s_bfm_b32 s0, 0, s2A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 104. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project