s_barrier_signal_isfirst GPU Native ISA AMD Scalar

Scalar Arithmetic

s_barrier_signal_isfirst

Signal that a wave has arrived at a barrier and set SCC to indicate if this is the first wave to signal the barrier.

Encoding

Binary Layout (AMD CDNA 5)
101111101
31:23
SDST
22:16
01001111
15:8
SSRC0
7:0
 

The ENC_SOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 79 in OP rebuilds 0xBE804F00, an identifier AMD lists for this encoding. The same in AMD RDNA 4.

Format SOP1
Width 32 bits
Opcode 79
Identifier 0xBE804F00

Operands

  • SSRC0
    Read. N/A Data format: 32 bits of arbitrary data. (OPR_SSRC_BARRIER_ID, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Description

Signal that a wave has arrived at a barrier and set SCC to indicate if this is the first wave to signal the barrier. The argument specifies which barrier to signal.

Example

s_barrier_signal_isfirst 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx13_asm_sop1.s). Not from an AMD document, and not authored here.

Sources