s_andn2_b64 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_andn2_b64

Calculate bitwise AND with the first input and the negation of the second input, store the result into a scalar register and set SCC if the result is…

Also written as s_and_not1_b64. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
10
31:30
0010011
29:23
SDST
22:16
SSRC1
15:8
SSRC0
7:0
 

The ENC_SOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 19 in OP rebuilds 0x89800000, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 2 (opcode 21), AMD RDNA 1 (opcode 21). The same in AMD CDNA 3, AMD CDNA 2, AMD CDNA 1.

Format SOP2
Width 32 bits
Opcode 19
Identifier 0x89800000

Operands

  • SDST
    Written. N/A Data format: N/A (OPR_SDST, FMT_NUM_U64)
  • SSRC0
    Read. N/A Data format: N/A (OPR_SSRC, FMT_NUM_U64)
  • SSRC1
    Read. N/A Data format: N/A (OPR_SSRC, FMT_NUM_U64)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP2 encoding (AMD CDNA 4).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Description

Calculate bitwise AND with the first input and the negation of the second input, store the result into a scalar register and set SCC if the result is nonzero.

Semantics

D0.u64 = (S0.u64 & ~S1.u64); SCC = D0.u64 != 0ULL

Example

s_andn2_b64 s[0:1], 0, s[4:5]

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources