s_add_u32 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_add_u32 SDST, S0, S1

Add two 32-bit unsigned scalar operands, wavefront-uniform.

Also written as s_add_co_u32. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
10
31:30
0000000
29:23
SDST
22:16
SSRC1
15:8
SSRC0
7:0
 

The ENC_SOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 0 in OP rebuilds 0x80000000, an identifier AMD lists for this encoding. The same in the other 7 generations that define it.

Format SOP2
Width 32 bits
Opcode 0
Identifier 0x80000000
Execution Unit Scalar ALU
Register Classes SGPR

Operands

  • SDST
    Destination SGPR
  • S0
    First source SGPR/constant
  • S1
    Second source SGPR/constant

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Integer Addition ↗
equivalent with restrictions
add (PTX)
Add with Carry-Out ↗
equivalent with restrictions
add.cc (PTX)

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Description

Add two unsigned 32-bit integer inputs, store the result into a scalar register and store the carry-out bit into SCC.

Semantics

SDST = S0.u32 + S1.u32; SCC = carry-out.

Example

s_add_u32  s2, s0, s1   // s2 = s0 + s1 (scalar, whole wavefront)

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources