Integer Addition Arithmetic

Add two integer operands of matching or implied width, optionally with saturation.

Vendor-Neutral Definition

d = a + b, evaluated at the operand's integer width; signed forms may support saturating variants that clamp on overflow instead of wrapping.
⚠️ Cross-vendor mappings describe semantic relationships and are not guaranteed one-to-one compiler translations.
equivalent with restrictions Both compute d = a + b for integer operands; AMDGPU splits this into a scalar (whole-wavefront-uniform) form and a per-lane vector form where PTX has one generic add.
Property NVIDIA PTX AMDGPU
Instruction add s_add_u32, v_add_u32
ISA Layer Virtual Native
Data Types bf16, bf16x2, f16, f16x2, f32, f64, s16, s32, s64, u16, u32, u64 u32
Version / Target Introduced PTX ISA 1.0 gfx942/gfx1100, gfx942/gfx1100

Important Differences

  • AMDGPU exposes separate scalar (s_add_u32, SGPR, wavefront-uniform) and vector (v_add_u32, per-lane VGPR) instructions; PTX's add is always per-thread, with no direct analogue of the scalar-unit form.
  • Overflow/carry-out is read from SCC (scalar) or VCC (vector) on AMDGPU rather than expressed as a saturating '.sat' modifier on the add itself as in PTX.

Source Evidence

Verification method: documentation