Decode an instruction word
Paste a 32-bit word as hex or binary. It is matched against 908 encodings across ARM and RISC-V, and every field is broken out with its bit range and value.
Try 0xFFF04013 (RISC-V) or 0xD2800000 (ARM).
Why one word can match several instructions
A bare 32-bit word is genuinely ambiguous. The same bits mean different
things in different architectures, and some encodings fix very little:
RISC-V LUI pins only its 7-bit opcode, so one word in 32 really
is a valid LUI. Matches are ranked by how many bits each
encoding fixes, and that count is shown, so a weak match is visible as a
weak match rather than presented as an answer. Narrow by architecture if you
already know the target.
What it will not do
An encoding is only listed here if its documented bit pattern rebuilds the opcode the dataset already stores for it. That check admits 908 of 1,692 candidate records, and the rest are left out rather than decoded on a guess: a wrong field width does not fail loudly, it returns a confident wrong answer, which in a reference is worse than returning nothing.
So no match does not mean invalid. It means the word does not match anything in the verified set. x86 is absent because its instructions are variable length rather than one 32-bit word, PowerISA because its patterns record field values in decimal without fixed widths, and AMDGPU because those records carry no bit pattern at all.
The data behind this is public domain, and how its accuracy was measured is in ACCURACY.md.