The dataset
Every instruction on this site, as data you can download and use. 6,468 records across six architectures, released into the public domain under CC0 1.0. Use it for anything, including commercially. No permission, no attribution, no conditions. Credit is welcome but is not required.
Download
| File | Contents | Size |
|---|---|---|
| ACCURACY.md | How accuracy was measured, and what was not | 32 KB |
| LICENSE | The CC0 dedication and what it does not cover | 2 KB |
| README.md | Dataset card | 2 KB |
| amdgpu.json | AMDGPU records only | 8.9 MB |
| arm.json | ARM records only | 2.4 MB |
| instructions.jsonl | Every record, one JSON object per line | 12.1 MB |
| manifest.json | Counts, excluded fields, SHA-256 checksums | 2 KB |
| powerisa.json | POWERISA records only | 2.4 MB |
| ptx.json | PTX records only | 479 KB |
| riscv.json | RISCV records only | 912 KB |
| x86.json | X86 records only | 1.2 MB |
Want one instruction rather than the lot? The API serves these same records, one URL per mnemonic.
What a record contains
mnemonic, architecture, summary,
description, syntax, operands,
encoding (format, bit pattern, hex opcode),
pseudocode, extension, and an example where one exists.
AMDGPU records also carry aliases, the other names AMD's
specification gives the same instruction.
Accuracy, and what is not measured
The data was extracted from vendor specifications by a language model and then repaired, so accuracy is measured rather than assumed. Sampling records against the vendor specifications themselves gives mnemonic corroboration of 97.9% for x86, 96.3% for ARM and RISC-V, and 94.0% for PowerISA. RISC-V encodings agree with their own bit patterns on all 546 checkable records, after 23 defects were found and fixed.
ARM's encodings are audited in full, not sampled: all 1,145 records, against the encoding diagrams in Arm's own machine-readable specification. That found 13 defective records (1.1%). All are repaired, and 1,096 now match Arm's diagrams exactly; 23 cannot be checked against the release used.
PTX and AMDGPU, 2,632 of the 6,468 records (40.7%), are measured on different terms. Neither vendor reference is vendored here, and both datasets were imported programmatically from the very sources they are checked against. So their sampled mnemonic checks, 99.5% for PTX and 100% for a 300-record AMDGPU sample, measure fidelity to source rather than independent corroboration, and mean less than PowerISA's 94.0%. PTX is a virtual ISA with no binary encoding, so the opcode checks do not apply to it and only its mnemonics are checked. AMDGPU's bit layouts are checked in full against LLVM's assembler, which did not supply them: 27,921 lines decode to the instruction LLVM assembled and none to a different one. Those lines exercise 1,443 of the 3,644 layouts in the nine generations LLVM's tests cover, and the newest generation, CDNA 5, not at all.
Two limits are worth stating plainly. Semantic correctness of the prose and pseudocode is not measured at all, for any architecture. And PTX has only its mnemonic check, while AMDGPU's encodings are checked only where LLVM's tests reach. Treat the figures as a lower bound, and check anything safety critical against the vendor's own manual.
The full method, including nine corrections made to the audit itself, is in ACCURACY.md, which ships with the dataset.
What is not included
8.78 MB of verbatim vendor manual text, most of it Intel's, is removed before release. It was reproduced on this site as a technical reference, but it is not ours to place in the public domain. Every record keeps its own summary, description, pseudocode, operands and encoding. Instruction sets, mnemonics and trademarks remain the property of Intel, AMD, Arm, IBM/OpenPOWER, RISC-V International and NVIDIA.