Summary: Convert from a double-precision float input to a signed 32-bit integer value and store the result into a vector register.

0.5ULP accuracy, out-of-range floating point values (including infinity) saturate. NAN is converted to 0. Generation of the INEXACT exception is controlled by the CLAMP bit. INEXACT exceptions are enabled for this conversion iff CLAMP == 1.


Summary: Convert from a signed 16-bit integer input to a signed 32-bit integer value using sign extension and store the result into a vector register.


Summary: Convert from a half-precision float input to a signed normalized short and store the result into a vector register.

0.5ULP accuracy, supports rounding, exception flags and saturation, denormals are supported.


Summary: Convert from a half-precision float input to an unsigned normalized short and store the result into a vector register.


Convert from a signed 4-bit integer input to a single-precision float value using an offset table and store the result into a vector register. Used for interpolation in shader. Lookup table on S0[3:0]: S0 binary Result 1000 -0.5000f 1001 -0.4375f 1010 -0.3750f 1011 -0.3125f 1100 -0.2500f 1101 -0.1875f 1110 -0.1250f 1111 -0.0625f 0000 +0.0000f 0001 +0.0625f 0010 +0.1250f 0011 +0.1875f 0100 +0.2500f 0101 +0.3125f 0110 +0.3750f 0111 +0.4375f

declare CVT_OFF_TABLE : 32'F[16];
D0.f32 = CVT_OFF_TABLE[S0.u32[3 : 0]]


Summary: Convert from two single-precision float inputs to a packed BF16 value and store the result into a vector register.


Summary: AMDGPU VOP1 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Convert from two single-precision float inputs to a packed BF8 float value with round to nearest even semantics and store the result into 16 bits of…

Convert from two single-precision float inputs to a packed BF8 float value with round to nearest even semantics and store the result into 16 bits of a vector register using OPSEL.

prev_mode = ROUND_MODE;
ROUND_MODE = ROUND_NEAREST_EVEN;
if OPSEL[3].u32 == 0U then
VGPR[laneId][VDST.u32][15 : 0].b16 = { f32_to_bf8(S1.f32), f32_to_bf8(S0.f32) };
// D0[31:16] are preserved
else
VGPR[laneId][VDST.u32][31 : 16].b16 = { f32_to_bf8(S1.f32), f32_to_bf8(S0.f32) };
// D0[15:0] are preserved
endif;
ROUND_MODE = prev_mode

Round to nearest even. Ignores OMOD and clamp.


Summary: Convert from two single-precision float inputs to a packed half-precision value and store the result into a vector register.


Summary: Convert from a packed 2-component BF8 float input to a packed single-precision float value and store the result into a vector register.

SDWA encoding allows SRC0_SEL to control which word of S0 is converted. Only the WORD selects of SRC0_SEL are legal. If this instruction is not encoded in SDWA then WORD0 is implied.


Summary: AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Convert from a packed 2-component FP8 float input to a packed single-precision float value and store the result into a vector register.


Summary: Convert from two single-precision float inputs to a packed FP8 float value with round to nearest even semantics and store the result into 16 bits of…

Convert from two single-precision float inputs to a packed FP8 float value with round to nearest even semantics and store the result into 16 bits of a vector register using OPSEL.

prev_mode = ROUND_MODE;
ROUND_MODE = ROUND_NEAREST_EVEN;
if OPSEL[3].u32 == 0U then
VGPR[laneId][VDST.u32][15 : 0].b16 = { f32_to_fp8(S1.f32), f32_to_fp8(S0.f32) };
// D0[31:16] are preserved
else
VGPR[laneId][VDST.u32][31 : 16].b16 = { f32_to_fp8(S1.f32), f32_to_fp8(S0.f32) };
// D0[15:0] are preserved
endif;
ROUND_MODE = prev_mode


Summary: AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Convert two single-precision float inputs into a packed signed 16-bit integer value and store the result into a vector register.


Summary: Convert from two signed 32-bit integer inputs to a packed signed 16-bit integer value and store the result into a vector register.


Summary: Convert from two half-precision float inputs to a packed signed normalized short and store the result into a vector register.


Summary: Convert from two single-precision float inputs to a packed signed normalized short and store the result into a vector register.


Summary: Convert from two half-precision float inputs to a packed unsigned normalized short and store the result into a vector register.


Summary: Convert from two single-precision float inputs to a packed unsigned normalized short and store the result into a vector register.


Summary: Convert two single-precision float inputs into a packed unsigned 16-bit integer value and store the result into a vector register.


Summary: Convert from two unsigned 32-bit integer inputs to a packed unsigned 16-bit integer value and store the result into a vector register.


Summary: Convert a single-precision float value from the first input to an unsigned 8-bit integer value and pack the result into one byte of the third input…

Convert a single-precision float value from the first input to an unsigned 8-bit integer value and pack the result into one byte of the third input using the second input as a byte select. Store the result into a vector register.


Summary: Convert a single-precision float value in the first input to an unsigned 8-bit integer value and store the result into one byte of the destination…

Convert a single-precision float value in the first input to an unsigned 8-bit integer value and store the result into one byte of the destination register using the second input as a byte select.


Summary: Convert two single-precision float inputs to a packed half-precision float value using round toward zero semantics (ignore the current rounding…

Convert two single-precision float inputs to a packed half-precision float value using round toward zero semantics (ignore the current rounding mode), and store the result into a vector register.


Summary: Convert from a single-precision float input to a signed 32-bit integer value using round to nearest integer semantics (ignore the default rounding…

Convert from a single-precision float input to a signed 32-bit integer value using round to nearest integer semantics (ignore the default rounding mode) and store the result into a vector register.

0.5ULP accuracy, denormals are supported.


Summary: AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Scale packed 16-component single-precision float vectors from two source inputs using the exponent provided by the third single-precision float…

Scale packed 16-component single-precision float vectors from two source inputs using the exponent provided by the third single-precision float input, then convert the values to a packed 32-component BF6 float value. Store the result into a vector register.


Scale packed 16-component single-precision float vectors from two source inputs using the exponent provided by the third single-precision float input, then convert the values to a packed 32-component FP6 float value. Store the result into a vector register.


Summary: Convert from a BF8 float input to a half-precision float value, then scale the value using the exponent provided by the second single-precision float…

Convert from a BF8 float input to a half-precision float value, then scale the value using the exponent provided by the second single-precision float input. Store the result into a vector register. The value to convert is loaded from 8 bits of the input using OPSEL[1:0] to determine which byte to read.


Summary: Convert from an FP8 float input to a half-precision float value, then scale the value using the exponent provided by the second single-precision…

Convert from an FP8 float input to a half-precision float value, then scale the value using the exponent provided by the second single-precision float input. Store the result into a vector register. The value to convert is loaded from 8 bits of the input using OPSEL[1:0] to determine which byte to read.


Summary: Convert from a BF8 float input to a single-precision float value, then scale the value using the exponent provided by the second single-precision…

Convert from a BF8 float input to a single-precision float value, then scale the value using the exponent provided by the second single-precision float input. Store the result into a vector register. The value to convert is loaded from 8 bits of the input using OPSEL[1:0] to determine which byte to read.


Summary: Convert from an FP8 float input to a single-precision float value, then scale the value using the exponent provided by the second single-precision…

Convert from an FP8 float input to a single-precision float value, then scale the value using the exponent provided by the second single-precision float input. Store the result into a vector register. The value to convert is loaded from 8 bits of the input using OPSEL[1:0] to determine which byte to read.


Summary: AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Convert from a packed 32-component BF6 float input to a packed BF16 float value, then scale the packed values using the exponent provided by the…

Convert from a packed 32-component BF6 float input to a packed BF16 float value, then scale the packed values using the exponent provided by the second single-precision float input. Store the result into a vector register.


Summary: Convert from a packed 32-component FP6 float input to a packed BF16 float value, then scale the packed values using the exponent provided by the…

Convert from a packed 32-component FP6 float input to a packed BF16 float value, then scale the packed values using the exponent provided by the second single-precision float input. Store the result into a vector register.


Summary: Scale a packed 32-component BF16 float input using the exponent provided by the second single-precision float input, then convert the values to a…

Scale a packed 32-component BF16 float input using the exponent provided by the second single-precision float input, then convert the values to a packed 32-component BF6 float value. Store the result into a vector register.


Summary: Scale a packed 32-component half-precision float input using the exponent provided by the second single-precision float input, then convert the…

Scale a packed 32-component half-precision float input using the exponent provided by the second single-precision float input, then convert the values to a packed 32-component BF6 float value. Store the result into a vector register.


Summary: Convert from a packed 32-component BF6 float input to a packed half-precision float value, then scale the packed values using the exponent provided…

Convert from a packed 32-component BF6 float input to a packed half-precision float value, then scale the packed values using the exponent provided by the second single-precision float input. Store the result into a vector register.


Summary: Convert from a packed 32-component FP6 float input to a packed half-precision float value, then scale the packed values using the exponent provided…

Convert from a packed 32-component FP6 float input to a packed half-precision float value, then scale the packed values using the exponent provided by the second single-precision float input. Store the result into a vector register.


Summary: Convert from a packed 32-component BF6 float input to a packed single-precision float value, then scale the packed values using the exponent provided…

Convert from a packed 32-component BF6 float input to a packed single-precision float value, then scale the packed values using the exponent provided by the second single-precision float input. Store the result into a vector register.


Summary: Convert from a packed 32-component FP6 float input to a packed single-precision float value, then scale the packed values using the exponent provided…

Convert from a packed 32-component FP6 float input to a packed single-precision float value, then scale the packed values using the exponent provided by the second single-precision float input. Store the result into a vector register.


Scale a packed 32-component BF16 float input using the exponent provided by the second single-precision float input, then convert the values to a packed 32-component FP6 float value. Store the result into a vector register.


Scale a packed 32-component half-precision float input using the exponent provided by the second single-precision float input, then convert the values to a packed 32-component FP6 float value. Store the result into a vector register.


Summary: Convert from a packed 2-component BF8 float input to a packed BF16 float value, then scale the packed values using the exponent provided by the…

Convert from a packed 2-component BF8 float input to a packed BF16 float value, then scale the packed values using the exponent provided by the second single-precision float input. Store the result into a vector register.


Summary: Convert from a packed 2-component FP4 float input to a packed BF16 float value, then scale the packed values using the exponent provided by the…

Convert from a packed 2-component FP4 float input to a packed BF16 float value, then scale the packed values using the exponent provided by the second single-precision float input. Store the result into a vector register. The value to convert is loaded from 8 bits of the input using OPSEL[1:0] to determine which byte to read.


Summary: Convert from a packed 2-component FP8 float input to a packed BF16 float value, then scale the packed values using the exponent provided by the…

Convert from a packed 2-component FP8 float input to a packed BF16 float value, then scale the packed values using the exponent provided by the second single-precision float input. Store the result into a vector register.


Summary: Scale a packed 2-component BF16 float input using the exponent provided by the second single-precision float input, then convert the values to a…

Scale a packed 2-component BF16 float input using the exponent provided by the second single-precision float input, then convert the values to a packed BF8 float value with round toward nearest even semantics. Store the result into 16 bits of a vector register using OPSEL.


Summary: Scale a packed 2-component half-precision float input using the exponent provided by the second single-precision float input, then convert the values…

Scale a packed 2-component half-precision float input using the exponent provided by the second single-precision float input, then convert the values to a packed BF8 float value with round toward nearest even semantics. Store the result into 16 bits of a vector register using OPSEL.


Summary: Scale two single-precision float inputs using the exponent provided by the third single-precision float input, then convert the values to a packed…

Scale two single-precision float inputs using the exponent provided by the third single-precision float input, then convert the values to a packed BF8 float value with round toward nearest even semantics. Store the result into 16 bits of a vector register using OPSEL.


Summary: Convert from a packed 2-component BF8 float input to a packed half-precision float value, then scale the packed values using the exponent provided by…

Convert from a packed 2-component BF8 float input to a packed half-precision float value, then scale the packed values using the exponent provided by the second single-precision float input. Store the result into a vector register.


Summary: Convert from a packed 2-component FP4 float input to a packed half-precision float value, then scale the packed values using the exponent provided by…

Convert from a packed 2-component FP4 float input to a packed half-precision float value, then scale the packed values using the exponent provided by the second single-precision float input. Store the result into a vector register. The value to convert is loaded from 8 bits of the input using OPSEL[1:0] to determine which byte to read.


Summary: Convert from a packed 2-component FP8 float input to a packed half-precision float value, then scale the packed values using the exponent provided by…

Convert from a packed 2-component FP8 float input to a packed half-precision float value, then scale the packed values using the exponent provided by the second single-precision float input. Store the result into a vector register.


Summary: Convert from a packed 2-component BF8 float input to a packed single-precision float value, then scale the packed values using the exponent provided…

Convert from a packed 2-component BF8 float input to a packed single-precision float value, then scale the packed values using the exponent provided by the second single-precision float input. Store the result into a vector register.


Summary: Convert from a packed 2-component FP4 float input to a packed single-precision float value, then scale the packed values using the exponent provided…

Convert from a packed 2-component FP4 float input to a packed single-precision float value, then scale the packed values using the exponent provided by the second single-precision float input. Store the result into a vector register. The value to convert is loaded from 8 bits of the input using OPSEL[1:0] to determine which byte to read.


Summary: Convert from a packed 2-component FP8 float input to a packed single-precision float value, then scale the packed values using the exponent provided…

Convert from a packed 2-component FP8 float input to a packed single-precision float value, then scale the packed values using the exponent provided by the second single-precision float input. Store the result into a vector register.


Scale a packed 2-component BF16 float input using the exponent provided by the second single-precision float input, then convert the values to a packed FP4 float value with round toward nearest even semantics. Store the result into 8 bits of a vector register using OPSEL[3:2] to determine which byte of the destination to overwrite.


Scale a packed 2-component half-precision float input using the exponent provided by the second single-precision float input, then convert the values to a packed FP4 float value with round toward nearest even semantics. Store the result into 8 bits of a vector register using OPSEL[3:2] to determine which byte of the destination to overwrite.


Scale two single-precision float inputs using the exponent provided by the third single-precision float input, then convert the values to a packed FP4 float value with round toward nearest even semantics. Store the result into 8 bits of a vector register using OPSEL[3:2] to determine which byte of the destination to overwrite.


Scale a packed 2-component BF16 float input using the exponent provided by the second single-precision float input, then convert the values to a packed FP8 float value with round toward nearest even semantics. Store the result into 16 bits of a vector register using OPSEL.


Scale a packed 2-component half-precision float input using the exponent provided by the second single-precision float input, then convert the values to a packed FP8 float value with round toward nearest even semantics. Store the result into 16 bits of a vector register using OPSEL.


Scale two single-precision float inputs using the exponent provided by the third single-precision float input, then convert the values to a packed FP8 float value with round toward nearest even semantics. Store the result into 16 bits of a vector register using OPSEL.


Summary: Scale a BF16 float input using the exponent provided by the third single-precision float input, then convert the values to a BF8 float value with…

Scale a BF16 float input using the exponent provided by the third single-precision float input, then convert the values to a BF8 float value with stochastic rounding using seed data from the second input. Store the result into 8 bits of a vector register using OPSEL[3:2] to determine which byte of the destination to overwrite.


Summary: Scale a half-precision float input using the exponent provided by the third single-precision float input, then convert the values to a BF8 float…

Scale a half-precision float input using the exponent provided by the third single-precision float input, then convert the values to a BF8 float value with stochastic rounding using seed data from the second input. Store the result into 8 bits of a vector register using OPSEL[3:2] to determine which byte of the destination to overwrite.


Summary: Scale a single-precision float input using the exponent provided by the third single-precision float input, then convert the values to a BF8 float…

Scale a single-precision float input using the exponent provided by the third single-precision float input, then convert the values to a BF8 float value with stochastic rounding using seed data from the second input. Store the result into 8 bits of a vector register using OPSEL[3:2] to determine which byte of the destination to overwrite.


Summary: Scale a BF16 float input using the exponent provided by the third single-precision float input, then convert the values to an FP8 float value with…

Scale a BF16 float input using the exponent provided by the third single-precision float input, then convert the values to an FP8 float value with stochastic rounding using seed data from the second input. Store the result into 8 bits of a vector register using OPSEL[3:2] to determine which byte of the destination to overwrite.


Summary: Scale a half-precision float input using the exponent provided by the third single-precision float input, then convert the values to an FP8 float…

Scale a half-precision float input using the exponent provided by the third single-precision float input, then convert the values to an FP8 float value with stochastic rounding using seed data from the second input. Store the result into 8 bits of a vector register using OPSEL[3:2] to determine which byte of the destination to overwrite.


Summary: Scale a single-precision float input using the exponent provided by the third single-precision float input, then convert the values to an FP8 float…

Scale a single-precision float input using the exponent provided by the third single-precision float input, then convert the values to an FP8 float value with stochastic rounding using seed data from the second input. Store the result into 8 bits of a vector register using OPSEL[3:2] to determine which byte of the destination to overwrite.


Summary: AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Scale a packed 32-component BF16 float input using the exponent provided by the third single-precision float input, then convert the values to a…

Scale a packed 32-component BF16 float input using the exponent provided by the third single-precision float input, then convert the values to a packed 32-component BF6 float value with stochastic rounding using seed data from the second input. Store the result into a vector register.


Summary: Scale a packed 32-component half-precision float input using the exponent provided by the third single-precision float input, then convert the values…

Scale a packed 32-component half-precision float input using the exponent provided by the third single-precision float input, then convert the values to a packed 32-component BF6 float value with stochastic rounding using seed data from the second input. Store the result into a vector register.


Summary: Scale a packed 32-component single-precision float input using the exponent provided by the third single-precision float input, then convert the…

Scale a packed 32-component single-precision float input using the exponent provided by the third single-precision float input, then convert the values to a packed 32-component BF6 float value with stochastic rounding using seed data from the second input. Store the result into a vector register.


Scale a packed 32-component BF16 float input using the exponent provided by the third single-precision float input, then convert the values to a packed 32-component FP6 float value with stochastic rounding using seed data from the second input. Store the result into a vector register.


Scale a packed 32-component half-precision float input using the exponent provided by the third single-precision float input, then convert the values to a packed 32-component FP6 float value with stochastic rounding using seed data from the second input. Store the result into a vector register.


Scale a packed 32-component single-precision float input using the exponent provided by the third single-precision float input, then convert the values to a packed 32-component FP6 float value with stochastic rounding using seed data from the second input. Store the result into a vector register.


Summary: Scale a packed 2-component BF16 float input using the exponent provided by the third single-precision float input, then convert the values to a…

Scale a packed 2-component BF16 float input using the exponent provided by the third single-precision float input, then convert the values to a packed FP4 float value with stochastic rounding using seed data from the second input. Store the result into 8 bits of a vector register using OPSEL[3:2] to determine which byte of the destination to overwrite.


Summary: Scale a packed 2-component half-precision float input using the exponent provided by the third single-precision float input, then convert the values…

Scale a packed 2-component half-precision float input using the exponent provided by the third single-precision float input, then convert the values to a packed FP4 float value with stochastic rounding using seed data from the second input. Store the result into 8 bits of a vector register using OPSEL[3:2] to determine which byte of the destination to overwrite.


Convert from a single-precision float input to a BF16 value with stochastic rounding using seed data from the second input. Store the result into 16 bits of a vector register using OPSEL to determine which word of the destination to overwrite.


Convert from a single-precision float input to a BF8 value with stochastic rounding using seed data from the second input. Store the result into 8 bits of a vector register using OPSEL to determine which byte of the destination to overwrite.

prev_mode = ROUND_MODE;
ROUND_MODE = ROUND_NEAREST_EVEN;
s = sign(S0.f32);
e = exponent(S0.f32);
m = 23'U(32'U(23'B(mantissa(S0.f32))) + S1[31 : 11].u32);
tmp = float32(s, e, m);
// Add stochastic value to mantissa, wrap around on overflow
if OPSEL[3 : 2].u2 == 2'0U then
VGPR[laneId][VDST.u32][7 : 0].bf8 = f32_to_bf8(tmp.f32)
elsif OPSEL[3 : 2].u2 == 2'1U then
VGPR[laneId][VDST.u32][15 : 8].bf8 = f32_to_bf8(tmp.f32)
elsif OPSEL[3 : 2].u2 == 2'2U then
VGPR[laneId][VDST.u32][23 : 16].bf8 = f32_to_bf8(tmp.f32)
else
VGPR[laneId][VDST.u32][31 : 24].bf8 = f32_to_bf8(tmp.f32)
endif;
// Unwritten bytes of D are preserved.
ROUND_MODE = prev_mode

Stochastic rounding. Ignores OMOD and clamp.


Convert from a single-precision float input to a half-precision value with stochastic rounding using seed data from the second input. Store the result into 16 bits of a vector register using OPSEL to determine which word of the destination to overwrite.


Convert from a single-precision float input to an FP8 value with stochastic rounding using seed data from the second input. Store the result into 8 bits of a vector register using OPSEL to determine which byte of the destination to overwrite.

prev_mode = ROUND_MODE;
ROUND_MODE = ROUND_NEAREST_EVEN;
s = sign(S0.f32);
e = exponent(S0.f32);
m = 23'U(32'U(23'B(mantissa(S0.f32))) + S1[31 : 12].u32);
tmp = float32(s, e, m);
// Add stochastic value to mantissa, wrap around on overflow
if OPSEL[3 : 2].u2 == 2'0U then
VGPR[laneId][VDST.u32][7 : 0].fp8 = f32_to_fp8(tmp.f32)
elsif OPSEL[3 : 2].u2 == 2'1U then
VGPR[laneId][VDST.u32][15 : 8].fp8 = f32_to_fp8(tmp.f32)
elsif OPSEL[3 : 2].u2 == 2'2U then
VGPR[laneId][VDST.u32][23 : 16].fp8 = f32_to_fp8(tmp.f32)
else
VGPR[laneId][VDST.u32][31 : 24].fp8 = f32_to_fp8(tmp.f32)
endif;
// Unwritten bytes of D are preserved.
ROUND_MODE = prev_mode


Summary: AMDGPU VOP3 vector instruction operating on f16/f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Convert from a half-precision float input to an unsigned 16-bit integer value and store the result into a vector register.

1ULP accuracy, supports rounding, exception flags and saturation. FP16 denormals are accepted. Conversion is done with truncation. Generation of the INEXACT exception is controlled by the CLAMP bit. INEXACT exceptions are enabled for this conversion iff CLAMP == 1.


Summary: Convert from a single-precision float input to an unsigned 32-bit integer value and store the result into a vector register.

1ULP accuracy, out-of-range floating point values (including infinity) saturate. NAN is converted to 0. Generation of the INEXACT exception is controlled by the CLAMP bit. INEXACT exceptions are enabled for this conversion iff CLAMP == 1.


Summary: Convert from a double-precision float input to an unsigned 32-bit integer value and store the result into a vector register.


Summary: Convert from an unsigned 16-bit integer input to an unsigned 32-bit integer value using zero extension and store the result into a vector register.


Summary: Given a half-precision float quotient in the first input, a denominator in the second input and a numerator in the third input, detect and apply…

Given a half-precision float quotient in the first input, a denominator in the second input and a numerator in the third input, detect and apply corner cases related to division, including divide by zero, NaN inputs and overflow, and modify the quotient accordingly. Generate any invalid, denormal and divide-by-zero exceptions that are a result of the division. Store the modified quotient into a vector register. This operation handles corner cases in a division macro such as divide by zero and NaN inputs. This operation is well defined when the quotient is approximately equal to the numerator divided by the denominator. Other inputs produce a predictable result but may not be mathematically useful.

This operation is the final step of a high precision division macro and handles all exceptional cases of division. If OPSEL[3] is 0 Result is written to 16 LSBs of destination VGPR and hi 16 bits are preserved. If OPSEL[3] is 1 Result is written to 16 MSBs of destination VGPR and lo 16 bits are preserved.


Summary: AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Given a single-precision float quotient in the first input, a denominator in the second input and a numerator in the third input, detect and apply…

Given a single-precision float quotient in the first input, a denominator in the second input and a numerator in the third input, detect and apply corner cases related to division, including divide by zero, NaN inputs and overflow, and modify the quotient accordingly. Generate any invalid, denormal and divide-by-zero exceptions that are a result of the division. Store the modified quotient into a vector register. This operation handles corner cases in a division macro such as divide by zero and NaN inputs. This operation is well defined when the quotient is approximately equal to the numerator divided by the denominator. Other inputs produce a predictable result but may not be mathematically useful.

This operation is the final step of a high precision division macro and handles all exceptional cases of division.


Summary: Given a double-precision float quotient in the first input, a denominator in the second input and a numerator in the third input, detect and apply…

Given a double-precision float quotient in the first input, a denominator in the second input and a numerator in the third input, detect and apply corner cases related to division, including divide by zero, NaN inputs and overflow, and modify the quotient accordingly. Generate any invalid, denormal and divide-by-zero exceptions that are a result of the division. Store the modified quotient into a vector register. This operation handles corner cases in a division macro such as divide by zero and NaN inputs. This operation is well defined when the quotient is approximately equal to the numerator divided by the denominator. Other inputs produce a predictable result but may not be mathematically useful.

sign_out = (sign(S1.f64) ^ sign(S2.f64));
if isNAN(S2.f64) then
D0.f64 = cvtToQuietNAN(S2.f64)
elsif isNAN(S1.f64) then
D0.f64 = cvtToQuietNAN(S1.f64)
elsif ((S1.f64 == 0.0) && (S2.f64 == 0.0)) then
// 0/0
D0.f64 = 64'F(0xfff8000000000000LL)
elsif ((abs(S1.f64) == +INF) && (abs(S2.f64) == +INF)) then
// inf/inf
D0.f64 = 64'F(0xfff8000000000000LL)
elsif ((S1.f64 == 0.0) || (abs(S2.f64) == +INF)) then
// x/0, or inf/y
D0.f64 = sign_out ? -INF : +INF
elsif ((abs(S1.f64) == +INF) || (S2.f64 == 0.0)) then
// x/inf, 0/y
D0.f64 = sign_out ? -0.0 : 0.0
elsif exponent(S2.f64) - exponent(S1.f64) < -1075 then
D0.f64 = sign_out ? -UNDERFLOW_F64 : UNDERFLOW_F64
elsif exponent(S1.f64) == 2047 then
D0.f64 = sign_out ? -OVERFLOW_F64 : OVERFLOW_F64
else
D0.f64 = sign_out ? -abs(S0.f64) : abs(S0.f64)
endif


Summary: Half precision division fixup. Has non-standard rule for OPSEL.

S0 = Quotient, S1 = Denominator, S2 = Numerator.
Given a numerator, denominator, and quotient from a divide, this opcode detects and applies specific case
numerics, touching up the quotient if necessary. This opcode also generates invalid, denorm and divide by
zero exceptions caused by the division.
sign_out = (sign(S1.f16) ^ sign(S2.f16));
if isNAN(64'F(S2.f16)) then
tmp = cvtToQuietNAN(64'F(S2.f16))
elsif isNAN(64'F(S1.f16)) then
tmp = cvtToQuietNAN(64'F(S1.f16))
elsif ((64'F(S1.f16) == 0.0) && (64'F(S2.f16) == 0.0)) then
// 0/0
tmp = 16'F(0xfe00)
elsif ((64'F(abs(S1.f16)) == +INF) && (64'F(abs(S2.f16)) == +INF)) then
// inf/inf
tmp = 16'F(0xfe00)
elsif ((64'F(S1.f16) == 0.0) || (64'F(abs(S2.f16)) == +INF)) then
// x/0, or inf/y
tmp = sign_out ? -INF : +INF
elsif ((64'F(abs(S1.f16)) == +INF) || (64'F(S2.f16) == 0.0)) then
// x/inf, 0/y
tmp = sign_out ? -0.0 : 0.0
else
tmp = sign_out ? -abs(S0.f16) : abs(S0.f16)
endif;
if OPSEL.u4[3] then
D0 = { tmp.f16, D0[15 : 0] }
else
D0 = { 16'0, tmp.f16 }
endif


Summary: Multiply two single-precision float inputs and add a third input using fused multiply add, then scale the exponent of the result by a fixed factor if…

Multiply two single-precision float inputs and add a third input using fused multiply add, then scale the exponent of the result by a fixed factor if the vector condition code is set. Store the result into a vector register. This operation is designed for use in floating point division macros and relies on V_DIV_SCALE_F32 to set the vector condition code iff the quotient requires post-scaling.

Input denormals are not flushed but output flushing is allowed. V_DIV_SCALE_F32, V_DIV_FMAS_F32 and V_DIV_FIXUP_F32 are all designed for use in a high precision division macro that utilizes V_RCP_F32 and V_MUL_F32 to compute the approximate result and then applies two steps of the Newton-Raphson method to converge to the quotient. If subnormal terms appear during this calculation then a loss of precision occurs. This loss of precision can be avoided by scaling the inputs and then post-scaling the quotient after Newton-Raphson is applied.


Summary: Multiply two double-precision float inputs and add a third input using fused multiply add, then scale the exponent of the result by a fixed factor if…

Multiply two double-precision float inputs and add a third input using fused multiply add, then scale the exponent of the result by a fixed factor if the vector condition code is set. Store the result into a vector register. This operation is designed for use in floating point division macros and relies on V_DIV_SCALE_F64 to set the vector condition code iff the quotient requires post-scaling.

v_div_fmas_f64 v[5:6], -1, -exec, |exec|

Input denormals are not flushed but output flushing is allowed. V_DIV_SCALE_F64, V_DIV_FMAS_F64 and V_DIV_FIXUP_F64 are all designed for use in a high precision division macro that utilizes V_RCP_F64 and V_MUL_F64 to compute the approximate result and then applies two steps of the Newton-Raphson method to converge to the quotient. If subnormal terms appear during this calculation then a loss of precision occurs. This loss of precision can be avoided by scaling the inputs and then post-scaling the quotient after Newton-Raphson is applied.


Summary: Given a single-precision float value to scale in the first input, a denominator in the second input and a numerator in the third input, scale the…

Given a single-precision float value to scale in the first input, a denominator in the second input and a numerator in the third input, scale the first input for division if required to avoid subnormal terms appearing during application of the Newton-Raphson correction method. Store the scaled result into a vector register and set the vector condition code iff post-scaling is required. This operation is designed for use in a high precision division macro. The first input should be the same value as either the second or third input; other scale values produce predictable results but may not be mathematically useful. The vector condition code is used by V_DIV_FMAS_F32 to determine if the quotient requires post-scaling.

VCC = 0x0LL;
if ((64'F(S2.f32) == 0.0) || (64'F(S1.f32) == 0.0)) then
D0.f32 = NAN.f32
elsif exponent(S2.f32) - exponent(S1.f32) >= 96 then
// N/D near MAX_FLOAT_F32
VCC = 0x1LL;
if S0.f32 == S1.f32 then
// Only scale the denominator
D0.f32 = ldexp(S0.f32, 64)
endif
elsif S1.f32 == DENORM.f32 then
D0.f32 = ldexp(S0.f32, 64)
elsif ((1.0 / 64'F(S1.f32) == DENORM.f64) && (S2.f32 / S1.f32 == DENORM.f32)) then
VCC = 0x1LL;
if S0.f32 == S1.f32 then
// Only scale the denominator
D0.f32 = ldexp(S0.f32, 64)
endif
elsif 1.0 / 64'F(S1.f32) == DENORM.f64 then
D0.f32 = ldexp(S0.f32, -64)
elsif S2.f32 / S1.f32 == DENORM.f32 then
VCC = 0x1LL;
if S0.f32 == S2.f32 then
// Only scale the numerator
D0.f32 = ldexp(S0.f32, 64)
endif
elsif exponent(S2.f32) <= 23 then
// Numerator is tiny
D0.f32 = ldexp(S0.f32, 64)
endif

V_DIV_SCALE_F32, V_DIV_FMAS_F32 and V_DIV_FIXUP_F32 are all designed for use in a high precision division macro that utilizes V_RCP_F32 and V_MUL_F32 to compute the approximate result and then applies two steps of the Newton-Raphson method to converge to the quotient. If subnormal terms appear during this calculation then a loss of precision occurs. This loss of precision can be avoided by scaling the inputs and then post-scaling the quotient after Newton-Raphson is applied.


Summary: Given a double-precision float value to scale in the first input, a denominator in the second input and a numerator in the third input, scale the…

Given a double-precision float value to scale in the first input, a denominator in the second input and a numerator in the third input, scale the first input for division if required to avoid subnormal terms appearing during application of the Newton-Raphson correction method. Store the scaled result into a vector register and set the vector condition code iff post-scaling is required. This operation is designed for use in a high precision division macro. The first input should be the same value as either the second or third input; other scale values produce predictable results but may not be mathematically useful. The vector condition code is used by V_DIV_FMAS_F64 to determine if the quotient requires post-scaling.

VCC = 0x0LL;
if ((S2.f64 == 0.0) || (S1.f64 == 0.0)) then
D0.f64 = NAN.f64
elsif exponent(S2.f64) - exponent(S1.f64) >= 768 then
// N/D near MAX_FLOAT_F64
VCC = 0x1LL;
if S0.f64 == S1.f64 then
// Only scale the denominator
D0.f64 = ldexp(S0.f64, 128)
endif
elsif S1.f64 == DENORM.f64 then
D0.f64 = ldexp(S0.f64, 128)
elsif ((1.0 / S1.f64 == DENORM.f64) && (S2.f64 / S1.f64 == DENORM.f64)) then
VCC = 0x1LL;
if S0.f64 == S1.f64 then
// Only scale the denominator
D0.f64 = ldexp(S0.f64, 128)
endif
elsif 1.0 / S1.f64 == DENORM.f64 then
D0.f64 = ldexp(S0.f64, -128)
elsif S2.f64 / S1.f64 == DENORM.f64 then
VCC = 0x1LL;
if S0.f64 == S2.f64 then
// Only scale the numerator
D0.f64 = ldexp(S0.f64, 128)
endif
elsif exponent(S2.f64) <= 53 then
// Numerator is tiny
D0.f64 = ldexp(S0.f64, 128)
endif

V_DIV_SCALE_F64, V_DIV_FMAS_F64 and V_DIV_FIXUP_F64 are all designed for use in a high precision division macro that utilizes V_RCP_F64 and V_MUL_F64 to compute the approximate result and then applies two steps of the Newton-Raphson method to converge to the quotient. If subnormal terms appear during this calculation then a loss of precision occurs. This loss of precision can be avoided by scaling the inputs and then post-scaling the quotient after Newton-Raphson is applied.


Summary: Compute the dot product of two packed 2-D BF16 float inputs, add the third input and store the result into a vector register.


Summary: Compute the dot product of two packed 2-D half-precision float inputs, add the third input and store the result into a vector register.


Summary: Compute the dot product of two packed 2-D signed 16-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from…

Compute the dot product of two packed 2-D signed 16-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from the third input and store the result into a vector register.


Summary: Compute the dot product of two packed 2-D unsigned 16-bit integer inputs in the unsigned 32-bit integer domain, add an unsigned 32-bit integer value…

Compute the dot product of two packed 2-D unsigned 16-bit integer inputs in the unsigned 32-bit integer domain, add an unsigned 32-bit integer value from the third input and store the result into a vector register.


Summary: Compute the dot product of two packed 2-D BF16 float inputs in the single-precision float domain and accumulate with the single-precision float value…

Compute the dot product of two packed 2-D BF16 float inputs in the single-precision float domain and accumulate with the single-precision float value in the destination register.


Summary: Compute the dot product of two packed 2-D half-precision float inputs in the single-precision float domain and accumulate with the single-precision…

Compute the dot product of two packed 2-D half-precision float inputs in the single-precision float domain and accumulate with the single-precision float value in the destination register.


Summary: Compute the dot product of two packed 2-D signed 16-bit integer inputs in the signed 32-bit integer domain and accumulate with the signed 32-bit…

Compute the dot product of two packed 2-D signed 16-bit integer inputs in the signed 32-bit integer domain and accumulate with the signed 32-bit integer value in the destination register.


Summary: Compute the dot product of two packed 4-D BF8 float inputs in the single-precision float domain, add a single-precision float value from the third…

Compute the dot product of two packed 4-D BF8 float inputs in the single-precision float domain, add a single-precision float value from the third input and store the result into a vector register.


Summary: Compute the dot product of a packed 4-D BF8 float input and a packed 4-D FP8 float input in the single-precision float domain, add a single-precision…

Compute the dot product of a packed 4-D BF8 float input and a packed 4-D FP8 float input in the single-precision float domain, add a single-precision float value from the third input and store the result into a vector register.


Summary: Compute the dot product of a packed 4-D FP8 float input and a packed 4-D BF8 float input in the single-precision float domain, add a single-precision…

Compute the dot product of a packed 4-D FP8 float input and a packed 4-D BF8 float input in the single-precision float domain, add a single-precision float value from the third input and store the result into a vector register.


Summary: Compute the dot product of two packed 4-D FP8 float inputs in the single-precision float domain, add a single-precision float value from the third…

Compute the dot product of two packed 4-D FP8 float inputs in the single-precision float domain, add a single-precision float value from the third input and store the result into a vector register.


Summary: Compute the dot product of two packed 4-D signed 8-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from the…

Compute the dot product of two packed 4-D signed 8-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from the third input and store the result into a vector register.


Summary: Compute the dot product of two packed 4-D signed or unsigned 8-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer…

Compute the dot product of two packed 4-D signed or unsigned 8-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from the third input and store the result into a vector register.


Summary: Compute the dot product of two packed 4-D unsigned 8-bit integer inputs in the unsigned 32-bit integer domain, add an unsigned 32-bit integer value…

Compute the dot product of two packed 4-D unsigned 8-bit integer inputs in the unsigned 32-bit integer domain, add an unsigned 32-bit integer value from the third input and store the result into a vector register.


Summary: Compute the dot product of two packed 4-D signed 8-bit integer inputs in the signed 32-bit integer domain and accumulate with the signed 32-bit…

Compute the dot product of two packed 4-D signed 8-bit integer inputs in the signed 32-bit integer domain and accumulate with the signed 32-bit integer value in the destination register.


Summary: Compute the dot product of two packed 8-D signed 4-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from the…

Compute the dot product of two packed 8-D signed 4-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from the third input and store the result into a vector register.


Summary: Compute the dot product of two packed 8-D signed or unsigned 4-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer…

Compute the dot product of two packed 8-D signed or unsigned 4-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from the third input and store the result into a vector register.


Summary: Compute the dot product of two packed 8-D unsigned 4-bit integer inputs in the unsigned 32-bit integer domain, add an unsigned 32-bit integer value…

Compute the dot product of two packed 8-D unsigned 4-bit integer inputs in the unsigned 32-bit integer domain, add an unsigned 32-bit integer value from the third input and store the result into a vector register.


Summary: Compute the dot product of two packed 8-D signed 4-bit integer inputs in the signed 32-bit integer domain and accumulate with the signed 32-bit…

Compute the dot product of two packed 8-D signed 4-bit integer inputs in the signed 32-bit integer domain and accumulate with the signed 32-bit integer value in the destination register.


Summary: AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Calculate 2 raised to the power of the half-precision float input and store the result into a vector register.


Summary: Calculate 2 raised to the power of the single-precision float input and store the result into a vector register.


Summary: AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Count the number of leading bits that are the same as the sign bit of a vector input and store the result into a vector register. Store -1 if all input bits are the same.

D0.i32 = -1;
// Set if all bits are the same
for i in 1 : 31 do
// Search from MSB
if S0.i32[31 - i] != S0.i32[31] then
D0.i32 = i;
break
endif
endfor


Count the number of leading "0" bits before the first "1" in a vector input and store the result into a vector register. Store -1 if there are no "1" bits.

D0.i32 = -1;
// Set if no ones are found
for i in 0 : 31 do
// Search from MSB
if S0.u32[31 - i] == 1'1U then
D0.i32 = i;
break
endif
endfor


Count the number of trailing "0" bits before the first "1" in a vector input and store the result into a vector register. Store -1 if there are no "1" bits in the input.

D0.i32 = -1;
// Set if no ones are found
for i in 0 : 31 do
// Search from LSB
if S0.u32[i] == 1'1U then
D0.i32 = i;
break
endif
endfor


Summary: Round the half-precision float input down to previous integer and store the result in floating point format into a vector register.


Summary: Round the single-precision float input down to previous integer and store the result in floating point format into a vector register.


Summary: Round the double-precision float input down to previous integer and store the result in floating point format into a vector register.


Summary: Multiply and add single-precision values. Follows DX9 rules where 0.0 times anything produces 0.0.


Summary: Multiply two half-precision float inputs and add a third input using fused multiply add, and store the result into a vector register.

0.5ULP accuracy, denormals are supported. If OPSEL[3] is 0 Result is written to 16 LSBs of destination VGPR and hi 16 bits are preserved. If OPSEL[3] is 1 Result is written to 16 MSBs of destination VGPR and lo 16 bits are preserved.


Summary: AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Per-lane single-precision fused multiply-add.

Multiply two single-precision float inputs and add a third input using fused multiply add, and store the result into a vector register.

VDST[lane] = round_once(S0[lane].f32 * S1[lane].f32 + S2[lane].f32) for each active lane.


Summary: Multiply two double-precision float inputs and add a third input using fused multiply add, and store the result into a vector register.


Summary: Fused half precision multiply add. Implements IEEE rules and non-standard rule for OPSEL.


Summary: AMDGPU VOP3P vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU VOP3P vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Multiply two inputs and add a third input using fused multiply add where the inputs are a mix of half-precision float and single-precision float…

Multiply two inputs and add a third input using fused multiply add where the inputs are a mix of half-precision float and single-precision float values. Store the result into a vector register.


Summary: AMDGPU VOP3P vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Multiply two inputs and add a third input using fused multiply add where the inputs are a mix of half-precision float and single-precision float values. Convert the result to a half-precision float. Store the result into the high bits of a vector register.


Multiply two inputs and add a third input using fused multiply add where the inputs are a mix of half-precision float and single-precision float values. Convert the result to a half-precision float. Store the result into the low bits of a vector register.


Summary: Multiply two half-precision float inputs and add a literal constant using fused multiply add, and store the result into a vector register.


Summary: AMDGPU VOP2 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Multiply two single-precision float inputs and add a literal constant using fused multiply add, and store the result into a vector register.

This opcode cannot use the VOP3 encoding and cannot use input/output modifiers.


Summary: AMDGPU VOP2 vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Multiply two half-precision float inputs and accumulate the result into the destination register using fused multiply add.


Summary: Multiply two floating point inputs and accumulate the result into the destination register using fused multiply add.


Summary: Multiply two single-precision values and accumulate the result with the destination. Follows DX9 rules where 0.0 times anything produces 0.0.


Summary: Multiply a half-precision float input with a literal constant and add a second half-precision float input using fused multiply add, and store the…

Multiply a half-precision float input with a literal constant and add a second half-precision float input using fused multiply add, and store the result into a vector register.


Summary: Multiply a single-precision float input with a literal constant and add a second single-precision float input using fused multiply add, and store the…

Multiply a single-precision float input with a literal constant and add a second single-precision float input using fused multiply add, and store the result into a vector register.


Summary: Compute the fractional portion of a half-precision float input and store the result in floating point format into a vector register.

0.5ULP accuracy, denormals are accepted. This is intended to comply with the DX specification of fract where the function behaves like an extension of integer modulus; be aware this may differ from how fract() is defined in other domains. For example: fract(- 1.2) = 0.8 in DX.


Summary: Compute the fractional portion of a single-precision float input and store the result in floating point format into a vector register.

0.5ULP accuracy, denormals are accepted. This is intended to comply with the DX specification of fract where the function behaves like an extension of integer modulus; be aware this may differ from how fract() is defined in other domains. For example: fract(- 1.2) = 0.8 in DX. Obey round mode, result clamped to 0x3f7fffff.


Summary: Compute the fractional portion of a double-precision float input and store the result in floating point format into a vector register.

0.5ULP accuracy, denormals are accepted. This is intended to comply with the DX specification of fract where the function behaves like an extension of integer modulus; be aware this may differ from how fract() is defined in other domains. For example: fract(- 1.2) = 0.8 in DX. Obey round mode, result clamped to 0x3fefffffffffffff.


Summary: Extract the exponent of a half-precision float input and store the result as a signed 16-bit integer into a vector register.

This operation satisfies the invariant S0.f16 = significand * (2 ** exponent). See also V_FREXP_MANT_F16, which returns the significand. See the C library function frexp() for more information.


Summary: Extract the exponent of a single-precision float input and store the result as a signed 32-bit integer into a vector register.

This operation satisfies the invariant S0.f32 = significand * (2 ** exponent). See also V_FREXP_MANT_F32, which returns the significand. See the C library function frexp() for more information.


Summary: Extract the exponent of a double-precision float input and store the result as a signed 32-bit integer into a vector register.

This operation satisfies the invariant S0.f64 = significand * (2 ** exponent). See also V_FREXP_MANT_F64, which returns the significand. See the C library function frexp() for more information.


Summary: Extract the binary significand, or mantissa, of a half-precision float input and store the result as a half- precision float into a vector register.

This operation satisfies the invariant S0.f16 = significand * (2 ** exponent). Result range is in (-1.0,-0.5][0.5,1.0) in normal cases. See also V_FREXP_EXP_I16_F16, which returns integer exponent. See the C library function frexp() for more information.


Summary: Extract the binary significand, or mantissa, of a single-precision float input and store the result as a single- precision float into a vector…

Extract the binary significand, or mantissa, of a single-precision float input and store the result as a single- precision float into a vector register.

This operation satisfies the invariant S0.f32 = significand * (2 ** exponent). Result range is in (-1.0,-0.5][0.5,1.0) in normal cases. See also V_FREXP_EXP_I32_F32, which returns integer exponent. See the C library function frexp() for more information.


Summary: Extract the binary significand, or mantissa, of a double-precision float input and store the result as a double- precision float into a vector…

Extract the binary significand, or mantissa, of a double-precision float input and store the result as a double- precision float into a vector register.

This operation satisfies the invariant S0.f64 = significand * (2 ** exponent). Result range is in (-1.0,-0.5][0.5,1.0) in normal cases. See also V_FREXP_EXP_I32_F64, which returns integer exponent. See the C library function frexp() for more information.


Summary: Given an attribute specifier and a parameter ID (P0, P10 or P20), load one of the parameter values from the local data share into a vector register.


Summary: Given a half-precision float P10 parameter of an attribute, a single-precision float I coordinate and a half-precision float P0 parameter as inputs…

Given a half-precision float P10 parameter of an attribute, a single-precision float I coordinate and a half-precision float P0 parameter as inputs, compute the first part of parameter interpolation and store the intermediate result in single-precision float format into a vector register. Use V_INTERP_P2_F16_F32 to complete the operation.


Summary: Given the P10 parameter of an attribute, the I coordinate and the P0 parameter as single-precision float inputs, compute the first part of parameter…

Given the P10 parameter of an attribute, the I coordinate and the P0 parameter as single-precision float inputs, compute the first part of parameter interpolation and store the intermediate result into a vector register. Use V_INTERP_P2_F32 to complete the operation.


Given a half-precision float P10 parameter of an attribute, a single-precision float I coordinate and a half-precision float P0 parameter as inputs, compute the first part of parameter interpolation using round toward zero semantics and store the intermediate result in single-precision float format into a vector register. Use V_INTERP_P2_RTZ_F16_F32 to complete the operation.


Summary: Given the I coordinate in a vector register and an attribute specifier, load parameter data from the local data share, compute the first part of…

Given the I coordinate in a vector register and an attribute specifier, load parameter data from the local data share, compute the first part of parameter interpolation and store the intermediate result into a vector register. Use V_INTERP_P2_F32 to complete the operation.


Summary: Given a single-precision float I coordinate in a vector register and an attribute specifier, load two half-precision float parameter values from the…

Given a single-precision float I coordinate in a vector register and an attribute specifier, load two half-precision float parameter values from the local data share, compute the first part of parameter interpolation and store the intermediate result into a vector register. Use V_INTERP_P2_F16 to complete the operation.


Summary: Given a single-precision float I coordinate in a vector register, a half-precision float P0 value in another vector register, and an attribute…

Given a single-precision float I coordinate in a vector register, a half-precision float P0 value in another vector register, and an attribute specifier, load a half-precision float parameter value from the local data share, compute the first part of parameter interpolation and store the intermediate result into a vector register. Use V_INTERP_P2_F16 to complete the operation.


Summary: Given a single-precision float J coordinate in a vector register, an attribute specifier and the result of a prior V_INTERP_P1_F32 in another vector…

Given a single-precision float J coordinate in a vector register, an attribute specifier and the result of a prior V_INTERP_P1_F32 in another vector register, load a half-precision float parameter value from the local data share, compute the second part of parameter interpolation and store the final result as a half-precision float value into a vector register.


Summary: Given a half-precision float P20 parameter of an attribute, a single-precision float J coordinate and the result of a prior V_INTERP_P10_F16_F32…

Given a half-precision float P20 parameter of an attribute, a single-precision float J coordinate and the result of a prior V_INTERP_P10_F16_F32 instruction as inputs, compute the second part of parameter interpolation and store the final result into a vector register.


Summary: AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Given the J coordinate in a vector register, an attribute specifier and the result of a prior V_INTERP_P1_F32 in the destination vector register…

Given the J coordinate in a vector register, an attribute specifier and the result of a prior V_INTERP_P1_F32 in the destination vector register, load parameter data from the local data share, compute the second part of parameter interpolation and store the final result into a vector register.


Summary: Half-precision interpolation.

Half-precision interpolation.


Summary: Given a half-precision float P20 parameter of an attribute, a single-precision float J coordinate and the result of a prior V_INTERP_P10_RTZ_F16_F32…

Given a half-precision float P20 parameter of an attribute, a single-precision float J coordinate and the result of a prior V_INTERP_P10_RTZ_F16_F32 instruction as inputs, compute the second part of parameter interpolation using round toward zero semantics and store the final result into a vector register.


Summary: Multiply the first input, a floating point value, by an integral power of 2 specified in the second input, a signed integer value, and store the…

Multiply the first input, a floating point value, by an integral power of 2 specified in the second input, a signed integer value, and store the floating point result into a vector register.

Compare with the ldexp() function in C. Note that the S1 has a format of f16 since floating point literal constants are interpreted as 16 bit value for this opcode.


Summary: AMDGPU VOP2 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Average two 4-D vectors stored as packed bytes in the first two inputs with rounding control provided by the third input, then store the result into…

Average two 4-D vectors stored as packed bytes in the first two inputs with rounding control provided by the third input, then store the result into a vector register. Each byte in the third input acts as a rounding mode for the corresponding element; if the LSB is set then 0.5 rounds up, otherwise 0.5 truncates.


Summary: AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Calculate the base 2 logarithm of the half-precision float input and store the result into a vector register.


Summary: Calculate the base 2 logarithm of the single-precision float input and store the result into a vector register.


Summary: AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Given a shift count in the second input, calculate the logical shift left of the first input, then add the third input to the intermediate result…

Given a shift count in the second input, calculate the logical shift left of the first input, then add the third input to the intermediate result, then store the final result into a vector register.


Given a shift count in the second input, calculate the logical shift left of the first input, then add the third input to the intermediate result, then store the final result into a vector register. For this opcode the shift count must be between 0 and 4, higher shift counts are unsupported.

The design treats unsupported shift counts as a shift of zero.


Summary: AMDGPU VOP2 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU VOP3 vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Given a shift count in the second input, calculate the logical shift left of the first input, then calculate the bitwise OR of the intermediate…

Given a shift count in the second input, calculate the logical shift left of the first input, then calculate the bitwise OR of the intermediate result and the third input, then store the final result into a vector register.


Summary: Given a shift count in the first vector input, calculate the logical shift left of the second vector input and store the result into a vector…

Given a shift count in the first vector input, calculate the logical shift left of the second vector input and store the result into a vector register.


Summary: AMDGPU VOP2 vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Given a shift count in the first vector input, calculate the logical shift right of the second vector input and store the result into a vector…

Given a shift count in the first vector input, calculate the logical shift right of the second vector input and store the result into a vector register.


Summary: Multiply two floating point inputs and accumulate the result into the destination register. Implements IEEE rules and non-standard rule for OPSEL.

Supports round mode, exception flags, saturation.


Summary: Multiply two floating point inputs and accumulate the result into the destination register.


Summary: Multiply and add single-precision values, accumulate with destination. Follows DX9 rules where 0.0 times anything produces 0.0.


Summary: Multiply two signed integer inputs, add a third signed integer input, store the result into a 64-bit vector register and store the overflow/carryout…

Multiply two signed integer inputs, add a third signed integer input, store the result into a 64-bit vector register and store the overflow/carryout into a scalar mask register.


Summary: Multiply two unsigned integer inputs, add a third unsigned integer input, store the result into a 64-bit vector register and store the…

Multiply two unsigned integer inputs, add a third unsigned integer input, store the result into a 64-bit vector register and store the overflow/carryout into a scalar mask register.


Summary: Multiply two half-precision float inputs and add a third input, and store the result into a vector register.

Supports round mode, exception flags, saturation. 1ULP accuracy, denormals are flushed. If OPSEL[3] is 0 Result is written to 16 LSBs of destination VGPR and hi 16 bits are preserved. If OPSEL[3] is 1 Result is written to 16 MSBs of destination VGPR and lo 16 bits are preserved.


Summary: AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Multiply two single-precision float inputs and add a third input, and store the result into a vector register.


Summary: Multiply two signed 16-bit integer inputs, add a signed 16-bit integer value from a third input, and store the result into a vector register.

Supports saturation (signed 16-bit integer domain). If OPSEL[3] is 0 the result is written to 16 LSBs of destination VGPR and the high 16 bits are preserved. If OPSEL[3] is 1 the result is written to 16 MSBs of destination VGPR and the low 16 bits are preserved.


Summary: AMDGPU VOP3 vector instruction operating on i16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Multiply two signed 16-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from a third input, and store the…

Multiply two signed 16-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from a third input, and store the result as a signed 32-bit integer into a vector register.


Summary: Multiply two signed 24-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from a third input, and store the…

Multiply two signed 24-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from a third input, and store the result as a signed 32-bit integer into a vector register.


In VOP3 the VCC destination may be an arbitrary SGPR-pair.


Summary: Multiply add of FP16 values. Implements IEEE rules and non-standard rule for OPSEL.

Supports round mode, exception flags, saturation. If OPSEL[3] is 0 Result is written to 16 LSBs of destination VGPR and hi 16 bits are written as 0 (this is different from V_MAD_F16). If OPSEL[3] is 1 Result is written to 16 MSBs of destination VGPR and lo 16 bits are preserved.


Summary: Multiply and add single-precision values. Follows DX9 rules where 0.0 times anything produces 0.0.


Summary: Multiply add of signed short values. Has non-standard rule for OPSEL.

Supports saturation (signed 16-bit integer domain). If OPSEL[3] is 0 Result is written to 16 LSBs of destination VGPR and hi 16 bits are written as 0 (this is different from V_MAD_I16). If OPSEL[3] is 1 Result is written to 16 MSBs of destination VGPR and lo 16 bits are preserved.


Summary: Multiply add of unsigned short values. Has non-standard rule for OPSEL.

Supports saturation (unsigned 16-bit integer domain). If OPSEL[3] is 0 Result is written to 16 LSBs of destination VGPR and hi 16 bits are written as 0 (this is different from V_MAD_U16). If OPSEL[3] is 1 Result is written to 16 MSBs of destination VGPR and lo 16 bits are preserved.


Multiply two inputs and add a third input where the inputs are a mix of half-precision float and single- precision float values. Store the result into a vector register.

Size and location of the three inputs are controlled by { OPSEL_HI[i], OPSEL[i] }: 0=src[31:0], 1=src[31:0],
2=src[15:0], 3=src[31:16]. For MIX opcodes the NEG_HI instruction field acts as an absolute-value modifier
for the three inputs.
declare in : 32'F[3];
declare S : 32'B[3];
for i in 0 : 2 do
if !OPSEL_HI.u3[i] then
in[i] = S[i].f32
elsif OPSEL.u3[i] then
in[i] = f16_to_f32(S[i][31 : 16].f16)
else
in[i] = f16_to_f32(S[i][15 : 0].f16)
endif
endfor;
D0[31 : 0].f32 = in[0] * in[1] + in[2]


Multiply two inputs and add a third input where the inputs are a mix of half-precision float and single- precision float values. Convert the result to a half-precision float. Store the result into the high bits of a vector register.

Size and location of the three inputs are controlled by { OPSEL_HI[i], OPSEL[i] }: 0=src[31:0], 1=src[31:0],
2=src[15:0], 3=src[31:16]. For MIX opcodes the NEG_HI instruction field acts as an absolute-value modifier
for the three inputs.
declare in : 32'F[3];
declare S : 32'B[3];
for i in 0 : 2 do
if !OPSEL_HI.u3[i] then
in[i] = S[i].f32
elsif OPSEL.u3[i] then
in[i] = f16_to_f32(S[i][31 : 16].f16)
else
in[i] = f16_to_f32(S[i][15 : 0].f16)
endif
endfor;
D0[31 : 16].f16 = f32_to_f16(in[0] * in[1] + in[2])


Multiply two inputs and add a third input where the inputs are a mix of half-precision float and single- precision float values. Convert the result to a half-precision float. Store the result into the low bits of a vector register.

Size and location of the three inputs are controlled by { OPSEL_HI[i], OPSEL[i] }: 0=src[31:0], 1=src[31:0],
2=src[15:0], 3=src[31:16]. For MIX opcodes the NEG_HI instruction field acts as an absolute-value modifier
for the three inputs.
declare in : 32'F[3];
declare S : 32'B[3];
for i in 0 : 2 do
if !OPSEL_HI.u3[i] then
in[i] = S[i].f32
elsif OPSEL.u3[i] then
in[i] = f16_to_f32(S[i][31 : 16].f16)
else
in[i] = f16_to_f32(S[i][15 : 0].f16)
endif
endfor;
D0[15 : 0].f16 = f32_to_f16(in[0] * in[1] + in[2])


Summary: AMDGPU VOP3 vector instruction operating on i32/i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU VOP3 vector instruction operating on u32/u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Multiply two unsigned 16-bit integer inputs, add an unsigned 16-bit integer value from a third input, and store the result into a vector register.

Supports saturation (unsigned 16-bit integer domain). If OPSEL[3] is 0 the result is written to 16 LSBs of destination VGPR and the high 16 bits are preserved. If OPSEL[3] is 1 the result is written to 16 MSBs of destination VGPR and the low 16 bits are preserved.


Summary: AMDGPU VOP3 vector instruction operating on u16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU VOP3 vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Multiply two unsigned 16-bit integer inputs in the unsigned 32-bit integer domain, add an unsigned 32-bit integer value from a third input, and store…

Multiply two unsigned 16-bit integer inputs in the unsigned 32-bit integer domain, add an unsigned 32-bit integer value from a third input, and store the result as an unsigned 32-bit integer into a vector register.


Summary: Multiply two unsigned 24-bit integer inputs in the unsigned 32-bit integer domain, add a unsigned 32-bit integer value from a third input, and store…

Multiply two unsigned 24-bit integer inputs in the unsigned 32-bit integer domain, add a unsigned 32-bit integer value from a third input, and store the result as an unsigned 32-bit integer into a vector register.


Summary: Multiply two unsigned integer inputs, add a third unsigned integer input, store the result into a 64-bit vector register and store the…


Summary: Multiply two floating point inputs and add a literal constant, and store the result into a vector register. Implements IEEE rules.

This opcode cannot use the VOP3 encoding and cannot use input/output modifiers. Supports round mode, exception flags, saturation.


Summary: Multiply two floating point inputs and add a literal constant, and store the result into a vector register.


Multiply a floating point input with a literal constant and add a second floating point input, and store the result into a vector register. Implements IEEE rules.


Multiply a floating point input with a literal constant and add a second floating point input, and store the result into a vector register.


Summary: Select the maximum of three half-precision float inputs and store the selected value into a vector register.


Summary: Select the maximum of three single-precision float inputs and store the selected value into a vector register.


Summary: Select the maximum of three signed 16-bit integer inputs and store the selected value into a vector register.


Summary: Select the maximum of three signed 32-bit integer inputs and store the selected value into a vector register.


Summary: Select the IEEE maximumNumber() of three half-precision float inputs and store the selected value into a vector register.


Summary: Select the IEEE maximumNumber() of three single-precision float inputs and store the selected value into a vector register.


Summary: Select the maximum of three unsigned 16-bit integer inputs and store the selected value into a vector register.


Summary: Select the maximum of three unsigned 32-bit integer inputs and store the selected value into a vector register.


Summary: AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Select the maximum of two half-precision float inputs and store the result into a vector register.

IEEE compliant. Supports denormals, round mode, exception flags, saturation.


Summary: Select the maximum of two single-precision float inputs and store the result into a vector register.


Summary: Select the maximum of two double-precision float inputs and store the selected value into a vector register.


Summary: Select the maximum of two signed 16-bit integer inputs and store the selected value into a vector register.


Summary: Select the maximum of two signed 32-bit integer inputs and store the selected value into a vector register.


Summary: AMDGPU VOP3 vector instruction operating on i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU VOP2 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Select the IEEE maximumNumber() of two half-precision float inputs and store the selected value into a vector register.


Summary: Select the IEEE maximumNumber() of two single-precision float inputs and store the selected value into a vector register.


Summary: Select the IEEE maximumNumber() of two double-precision float inputs and store the selected value into a vector register.


Summary: Select the maximum of two unsigned 16-bit integer inputs and store the selected value into a vector register.


Summary: Select the maximum of two unsigned 32-bit integer inputs and store the selected value into a vector register.


Summary: AMDGPU VOP3 vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Select the IEEE maximum() of three half-precision float inputs and store the selected value into a vector register.


Summary: Select the IEEE maximum() of three single-precision float inputs and store the result into a vector register.


Summary: Select the IEEE maximum() of two half-precision float inputs and store the selected value into a vector register.


Summary: Select the IEEE maximum() of two single-precision float inputs and store the selected value into a vector register.


Summary: Select the IEEE maximum() of two double-precision float inputs and store the selected value into a vector register.


Summary: Select the IEEE maximum() of the first two half-precision float inputs and then select the IEEE minimum() of that result and third half-precision…

Select the IEEE maximum() of the first two half-precision float inputs and then select the IEEE minimum() of that result and third half-precision float input. Store the final result into a vector register.


Summary: Select the IEEE maximum() of the first two single-precision float inputs and then select the IEEE minimum() of that result and third single-precision…

Select the IEEE maximum() of the first two single-precision float inputs and then select the IEEE minimum() of that result and third single-precision float input. Store the final result into a vector register.


Select the maximum of the first two half-precision float inputs and then select the minimum of that result and third half-precision float input. Store the final result into a vector register.


Select the maximum of the first two single-precision float inputs and then select the minimum of that result and third single-precision float input. Store the final result into a vector register.


Select the maximum of the first two signed 32-bit integer inputs and then select the minimum of that result and third signed 32-bit integer input. Store the final result into a vector register.


Summary: Select the IEEE maximumNumber() of the first two half-precision float inputs and then select the IEEE minimumNumber() of that result and third…

Select the IEEE maximumNumber() of the first two half-precision float inputs and then select the IEEE minimumNumber() of that result and third half-precision float input. Store the final result into a vector register.


Summary: Select the IEEE maximumNumber() of the first two single-precision float inputs and then select the IEEE minimumNumber() of that result and third…

Select the IEEE maximumNumber() of the first two single-precision float inputs and then select the IEEE minimumNumber() of that result and third single-precision float input. Store the final result into a vector register.


Select the maximum of the first two unsigned 32-bit integer inputs and then select the minimum of that result and third unsigned 32-bit integer input. Store the final result into a vector register.


For each lane 32 <= N < 64, examine the N least significant bits of the first input and count how many of those bits are "1". For lane positions 0 <= N < 32 no bits are examined and the count is zero. Add this count to the value in the second input and store the result into a vector register.


For each lane 0 <= N < 32, examine the N least significant bits of the first input and count how many of those bits are "1". For each lane 32 <= N < 64, all "1" bits in the first input are counted. Add this count to the value in the second input and store the result into a vector register.


Summary: Select the median of three half-precision float values and store the selected value into a vector register.


Summary: Select the median of three single-precision float values and store the selected value into a vector register.


Summary: Select the median of three signed 16-bit integer values and store the selected value into a vector register.


Summary: Select the median of three signed 32-bit integer values and store the selected value into a vector register.


Summary: Select the median of three half-precision float inputs and store the selected value into a vector register.


Summary: Select the median of three single-precision float inputs and store the selected value into a vector register.


Summary: Select the median of three unsigned 16-bit integer values and store the selected value into a vector register.


Summary: Select the median of three unsigned 32-bit integer values and store the selected value into a vector register.


Summary: Multiply the 16x128 matrix in the first input by the 128x16 matrix in the second input and add the 16x16 matrix in the third input using fused…

Multiply the 16x128 matrix in the first input by the 128x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.


Summary: Multiply the 16x16 matrix in the first input by the 16x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply…

Multiply the 16x16 matrix in the first input by the 16x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.

D = A (16x16) * B (16x16) + C (16x16)
Each operand contains a single matrix whose elements are distributed across all lanes of the wave. A single
matrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher
performance.
Matrices A and B are BF16 float format. Matrices C and D are single-precision float format.


D = A (16x16) * B (16x16) + C (16x16)
Each operand contains a single matrix whose elements are distributed across all lanes of the wave. A single
matrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher
performance.
Matrices A and B are half-precision float format. Matrices C and D are single-precision float format.


Summary: Matrix-fused-multiply-add: cooperative 16x16x16 matrix-multiply-accumulate on matrix-core hardware, fp16 inputs, fp32 accumulate.

D

Accumulator fragment (destination, VGPR range)

C

Accumulator fragment (input, VGPR range)

D = A * B + C for a 16x16x16 tile, computed cooperatively across the wavefront; operand fragments are distributed across lanes per a hardware-defined layout specific to the MFMA family and target.

Matrix-core (MFMA) instructions are a CDNA-family feature; gfx1100 (RDNA3) does not implement this specific MFMA variant - see the AMDGPU landing page's target compatibility notes.


Summary: Multiply the 16x1 matrix in the first input by the 1x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply…

Multiply the 16x1 matrix in the first input by the 1x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.

D = A (16x1) * B (1x16) + C (16x16)
This instruction performs 4 matrix multiplies. Each operand contains 4 matrices back to back, and each matrix
has elements distributed across all lanes of the wave. Each matrix multiple is computed and the row-column
dot products are distributed across the vector ALU for higher performance. The result matrices are stored
back-to-back in the destination vector registers.
Matrices A and B are single-precision float format. Matrices C and D are single-precision float format.


Summary: Multiply the 16x32 matrix in the first input by the 32x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply…

Multiply the 16x32 matrix in the first input by the 32x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.


Summary: Multiply the 16x4 matrix in the first input by the 4x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply…

Multiply the 16x4 matrix in the first input by the 4x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.

D = A (16x4) * B (4x16) + C (16x16)
This instruction performs 4 matrix multiplies. Each operand contains 4 matrices back to back, and each matrix
has elements distributed across all lanes of the wave. Each matrix multiple is computed and the row-column
dot products are distributed across the vector ALU for higher performance. The result matrices are stored
back-to-back in the destination vector registers.
Matrices A and B are BF16 float format. Matrices C and D are single-precision float format.


D = A (16x4) * B (4x16) + C (16x16)
This instruction performs 4 matrix multiplies. Each operand contains 4 matrices back to back, and each matrix
has elements distributed across all lanes of the wave. Each matrix multiple is computed and the row-column
dot products are distributed across the vector ALU for higher performance. The result matrices are stored
back-to-back in the destination vector registers.
Matrices A and B are half-precision float format. Matrices C and D are single-precision float format.


D = A (16x4) * B (4x16) + C (16x16)
Each operand contains a single matrix whose elements are distributed across all lanes of the wave. A single
matrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher
performance.
Matrices A and B are single-precision float format. Matrices C and D are single-precision float format.


Summary: Multiply the 16x8 matrix in the first input by the 8x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply…

Multiply the 16x8 matrix in the first input by the 8x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.

D = A (16x8) * B (8x16) + C (16x16)
Each operand contains a single matrix whose elements are distributed across all lanes of the wave. A single
matrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher
performance.
Matrices A and B are single-precision float format. Matrices C and D are single-precision float format. XF32 is a
FP32 operation with FP32 inputs and outputs but implemented at reduced intermediate precision where
mantissa is truncated to 10 bits (not including leading 1 for non-zero values) and results are accumulated into
FP32 value with 23 bit mantissa.


Summary: Multiply the 32x16 matrix in the first input by the 16x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply…

Multiply the 32x16 matrix in the first input by the 16x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.


Summary: Multiply the 32x1 matrix in the first input by the 1x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply…

Multiply the 32x1 matrix in the first input by the 1x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.

D = A (32x1) * B (1x32) + C (32x32)
This instruction performs 2 matrix multiplies. Each operand contains 2 matrices back to back, and each matrix
has elements distributed across all lanes of the wave. Each matrix multiple is computed and the row-column
dot products are distributed across the vector ALU for higher performance. The result matrices are stored
back-to-back in the destination vector registers.
Matrices A and B are single-precision float format. Matrices C and D are single-precision float format.


Summary: Multiply the 32x2 matrix in the first input by the 2x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply…

Multiply the 32x2 matrix in the first input by the 2x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.

D = A (32x2) * B (2x32) + C (32x32)
Each operand contains a single matrix whose elements are distributed across all lanes of the wave. A single
matrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher
performance.
Matrices A and B are single-precision float format. Matrices C and D are single-precision float format.


Summary: Multiply the 32x4 matrix in the first input by the 4x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply…

Multiply the 32x4 matrix in the first input by the 4x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.

D = A (32x4) * B (4x32) + C (32x32)
This instruction performs 2 matrix multiplies. Each operand contains 2 matrices back to back, and each matrix
has elements distributed across all lanes of the wave. Each matrix multiple is computed and the row-column
dot products are distributed across the vector ALU for higher performance. The result matrices are stored
back-to-back in the destination vector registers.
Matrices A and B are BF16 float format. Matrices C and D are single-precision float format.


D = A (32x4) * B (4x32) + C (32x32)
This instruction performs 2 matrix multiplies. Each operand contains 2 matrices back to back, and each matrix
has elements distributed across all lanes of the wave. Each matrix multiple is computed and the row-column
dot products are distributed across the vector ALU for higher performance. The result matrices are stored
back-to-back in the destination vector registers.
Matrices A and B are half-precision float format. Matrices C and D are single-precision float format.


D = A (32x4) * B (4x32) + C (32x32)
Each operand contains a single matrix whose elements are distributed across all lanes of the wave. A single
matrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher
performance.
Matrices A and B are single-precision float format. Matrices C and D are single-precision float format.


Summary: Multiply the 32x64 matrix in the first input by the 64x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply…

Multiply the 32x64 matrix in the first input by the 64x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.


Summary: Multiply the 32x8 matrix in the first input by the 8x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply…

Multiply the 32x8 matrix in the first input by the 8x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.

D = A (32x8) * B (8x32) + C (32x32)
Each operand contains a single matrix whose elements are distributed across all lanes of the wave. A single
matrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher
performance.
Matrices A and B are BF16 float format. Matrices C and D are single-precision float format.


D = A (32x8) * B (8x32) + C (32x32)
Each operand contains a single matrix whose elements are distributed across all lanes of the wave. A single
matrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher
performance.
Matrices A and B are half-precision float format. Matrices C and D are single-precision float format.


Multiply the 4x1 matrix in the first input by the 1x4 matrix in the second input and add the 4x4 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.

D = A (4x1) * B (1x4) + C (4x4)
This instruction performs 16 matrix multiplies. Each operand contains 16 matrices back to back, and each
matrix has elements distributed across all lanes of the wave. Each matrix multiple is computed and the row-column dot products are distributed across the vector ALU for higher performance. The result matrices are
stored back-to-back in the destination vector registers.
Matrices A and B are single-precision float format. Matrices C and D are single-precision float format.


Multiply the 4x4 matrix in the first input by the 4x4 matrix in the second input and add the 4x4 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.

D = A (4x4) * B (4x4) + C (4x4)
This instruction performs 16 matrix multiplies. Each operand contains 16 matrices back to back, and each
matrix has elements distributed across all lanes of the wave. Each matrix multiple is computed and the row-column dot products are distributed across the vector ALU for higher performance. The result matrices are
stored back-to-back in the destination vector registers.
Matrices A and B are BF16 float format. Matrices C and D are single-precision float format.


D = A (4x4) * B (4x4) + C (4x4)
This instruction performs 16 matrix multiplies. Each operand contains 16 matrices back to back, and each
matrix has elements distributed across all lanes of the wave. Each matrix multiple is computed and the row-column dot products are distributed across the vector ALU for higher performance. The result matrices are
stored back-to-back in the destination vector registers.
Matrices A and B are half-precision float format. Matrices C and D are single-precision float format.


D = A (16x4) * B (4x16) + C (16x16)
Each operand contains a single matrix whose elements are distributed across all lanes of the wave. A single
matrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher
performance.
Matrices A and B are double-precision float format. Matrices C and D are double-precision float format.


D = A (4x4) * B (4x4) + C (4x4)
This instruction performs 4 matrix multiplies. Each operand contains 4 matrices back to back, and each matrix
has elements distributed across all lanes of the wave. Each matrix multiple is computed and the row-column
dot products are distributed across the vector ALU for higher performance. The result matrices are stored
back-to-back in the destination vector registers.
Matrices A and B are double-precision float format. Matrices C and D are double-precision float format.


D = A (16x32) * B (32x16) + C (16x16)
Each operand contains a single matrix whose elements are distributed across all lanes of the wave. A single
matrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher
performance.
Matrices A and B are signed 8-bit integer format. Matrices C and D are signed 32-bit integer format.


D = A (16x4) * B (4x16) + C (16x16)
This instruction performs 4 matrix multiplies. Each operand contains 4 matrices back to back, and each matrix
has elements distributed across all lanes of the wave. Each matrix multiple is computed and the row-column
dot products are distributed across the vector ALU for higher performance. The result matrices are stored
back-to-back in the destination vector registers.
Matrices A and B are signed 8-bit integer format. Matrices C and D are signed 32-bit integer format.


Summary: Multiply the 16x64 matrix in the first input by the 64x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply…

Multiply the 16x64 matrix in the first input by the 64x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.


D = A (32x16) * B (16x32) + C (32x32)
Each operand contains a single matrix whose elements are distributed across all lanes of the wave. A single
matrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher
performance.
Matrices A and B are signed 8-bit integer format. Matrices C and D are signed 32-bit integer format.