Summary: Negates each doubleword integer.

Computes the two's complement negation (0 - value) of each doubleword (64-bit) element in the source vector and writes the result to the target vector. No status register updates occur.

The vnegd instruction is used to negate each doubleword element in a vector. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. This operation is performed on 64-bit elements, so ensure proper alignment and size of the vectors involved.


Summary: Moves a GPR field to a single CR field.

Moves a single condition register field from a GPR to the condition register, using FXM as a mask to select which CR field (CR0-CR7) receives the update. The FXM field must have only one bit set to specify a single CR field; CR bits outside the selected field are unchanged.

// Move GPR bits [0:31] to CR field selected by FXM
for i in 0 to 7:
  if FXM[i] = 1 then
    CR[i*4:(i+1)*4] ← RS[i*4:(i+1)*4]

The mtocrf instruction is used to transfer a specific field from the Condition Register (CR) to a general-purpose register. Ensure that exactly one bit in the FXM field is set to avoid undefined behavior of the Condition Register. This instruction operates at user privilege level and does not generate exceptions under normal conditions.


Summary: Moves a single CR field to a GPR.

Moves a single condition register field to a GPR, using FXM as a mask to select which CR field (CR0-CR7) is read. The FXM field must have only one bit set; the selected 4-bit CR field is placed in bits [0:3] of RT, with all other GPR bits zeroed.

// Move CR field selected by FXM to GPR bits [0:31]
RT ← 0
for i in 0 to 7:
  if FXM[i] = 1 then
    RT[i*4:(i+1)*4] ← CR[i*4:(i+1)*4]

The mfocrf instruction is used to extract a specific condition register field into a general-purpose register. Ensure that exactly one bit in the FXM field is set to avoid undefined behavior. This instruction operates at user privilege level and does not generate exceptions under normal conditions.


Summary: Computes the two's complement negation of a register (0 - RT).

result ← -(RA)
RT ← result
if OE = 1 then
  if RA = 0x8000_0000_0000_0000 then
    XER[OV] ← 1; XER[SO] ← 1
  else
    XER[OV] ← 0
if Rc = 1 then
  CR0 ← record_result(result)

Computes the two's complement negation (0 - RA) of the source register and stores the result in RT. If OE=1, sets OV and SO in XER on signed overflow (when RA=0x8000_0000_0000_0000). When Rc=1, updates CR0 based on the result.

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.


Summary: Performs a bitwise OR operation on the contents of two registers and places the result in a third register.

RA ← RS | RB
if Rc = 1 then CR0 ← (RA = 0, RA < 0, RA > 0, SO)

Performs a bitwise OR operation on two general-purpose registers and stores the result in a third register. This is a base category instruction that operates on the full 64-bit register width. If Rc=1, the instruction updates CR0 based on the result.

Warning: Other forms of or Rx,Rx,Rx that are not described in this section and in Section 4.3.3 may also cause program priority to change. Use of these forms should be avoided except when software explicitly intends to alter program priority. If a no-op is needed, the preferred no-op (ori 0,0,0) should be used.


Summary: Performs a bitwise OR operation between the contents of a register and an immediate value, placing the result in another register.

Performs a bitwise OR between a general-purpose register and a 16-bit unsigned immediate value, storing the result in another register. This is a base category instruction with no condition register or status updates.

Warning: Other forms of ori Rx,Rx,0 that are not described in this section may also have micro-architectural effects on program execution. Use of these forms should be avoided except when software needs the associated micro-architectural effects.

Programming Note: This no-op is intended to be used by software for providing protection against the Spectre class of transient execution attacks by restricting eventually discarded out-of-order execution effects with transient register values, which may compromise confidential data via other covert channels.


Summary: Performs a bitwise OR with a 16-bit immediate shifted left by 16 bits.

Performs a bitwise OR between a general-purpose register and a 16-bit unsigned immediate value shifted left by 16 bits, storing the result in another register. This is a base category instruction used to set high-order bits with no condition register updates.

The oris instruction is commonly used to set specific bits in a register by ORing it with an immediate value. Be cautious of overflow if UI exceeds the upper limit, as it will be truncated. This instruction operates at user privilege level and does not generate exceptions under normal circumstances.


Summary: Counts the number of set bits (1s) in a 64-bit register.

Counts the number of set bits (population count) in a 64-bit general-purpose register and stores the count in another register. This is a base category instruction that produces the count of 1-bits across the entire doubleword with no condition register or status updates.

The popcntd instruction is useful for counting the number of set bits (1s) in a 64-bit value. It operates on each doubleword independently, so if you're working with 128-bit values, ensure that both halves are processed separately. This instruction does not require any special alignment and can be executed at user privilege level. Be cautious when using this instruction in performance-critical sections, as it may have varying execution times depending on the input data.


Summary: Counts the number of set bits (1s) in the lower 32 bits of a register.

Counts the number of set bits in the lower 32 bits of a general-purpose register and stores the count in another register. This is a base category instruction that produces the count of 1-bits in the word, with the upper 32 bits of the result cleared and no condition register or status updates.

The popcntw instruction is useful for counting the number of set bits (1s) in a 32-bit word. It operates on each 32-bit segment of the source register, making it ideal for bit manipulation tasks where population count is needed. Ensure that the source and destination registers are properly aligned to avoid unexpected behavior. This instruction does not require any special privileges and will execute without exceptions if the operands are valid.


Summary: Invalidates TLB entries on the local processor based on Process ID (PID).

Invalidates TLB entries on the local processor based on Process ID and address criteria specified by the T field. This is an embedded category, privileged instruction that performs no condition register updates but modifies TLB state; behavior depends on the processor's memory management architecture.

Invalidate TLB entries matching: T field type, EA = (RA), PID = MMUPID, based on processor implementation


Summary: Loads a word and sends decoration sideband signals to the bus.

Loads a 32-bit word from memory at an address computed from two general-purpose registers and transmits sideband decoration signals. This is an embedded category instruction used in specialized memory systems with no condition register or status updates.

EA ← RA + RB
RT ← [EA][32:63]
Send decoration signals on memory bus


Summary: Stores a word and sends decoration sideband signals.

Stores a 32-bit word from a general-purpose register to memory at an address computed from two other registers and transmits sideband decoration signals. This is an embedded category instruction used in specialized memory systems with no condition register or status updates.

EA ← RA + RB
[EA][32:63] ← RS
Send decoration signals on memory bus


Summary: Enters embedded hypervisor privileged state.

Enters embedded hypervisor privileged state, allowing execution of hypervisor-privileged instructions. This instruction is only available in embedded processor implementations and requires hypervisor privilege level. No condition registers or status fields are affected by this instruction.

if not in hypervisor mode then
  raise Hypervisor Privilege exception
else
  enter hypervisor privileged state based on OC field


Summary: Synchronizes memory accesses (Alias for sync).

Provides full memory synchronization for embedded processors, equivalent to sync with no operands. This instruction ensures all prior loads and stores are globally visible before any subsequent memory accesses are initiated. No condition registers or status fields are affected.

wait until all prior memory accesses complete
wait until all prior memory accesses are globally visible


Summary: Adds the contents of two registers and places the result in a third register.

RT ← RA + RB
if OE = 1 then
  if overflow then XER[OV] ← 1; XER[SO] ← 1
if Rc = 1 then
  CR0 ← (RT < 0) || (RT > 0) || (RT = 0) || XER[SO]

Adds the values in registers RA and RB and places the result in RT. If OE=1, sets XER[SO] and XER[OV] on signed overflow. If Rc=1, updates CR0 to reflect the result (LT, GT, EQ, SO). No exception is raised on overflow unless OE=1.

add, add., and subf are the preferred instructions...


Summary: Adds the contents of two registers and a carry bit, placing the result in a target register.

if 'addc' then
    RT <- (RA) + (RB)
else if 'addc.' then
    RT <- (RA) + (RB)
    if Rc=1 then update CR0
else if 'addco' then
    RT <- (RA) + (RB)
    if OE=1 then update XER[SO], XER[OV]
else if 'addco.' then
    RT <- (RA) + (RB)
    if Rc=1 then update CR0
    if OE=1 then update XER[SO], XER[OV]

The sum (RA) + (RB) is placed into register RT.


Summary: Adds two registers plus the current Carry bit.

RT ← RA + RB + XER[CA]
if OE = 1 then
  if overflow then XER[OV] ← 1; XER[SO] ← 1
if result > 2^64-1 or result < -2^64 then XER[CA] ← 1 else XER[CA] ← 0
if Rc = 1 then
  CR0 ← (RT < 0) || (RT > 0) || (RT = 0) || XER[SO]

Adds the values in registers RA and RB plus the Carry bit from XER and places the result in RT. If OE=1, sets XER[SO] and XER[OV] on signed overflow. If Rc=1, updates CR0 based on the result. This instruction is used for multi-precision arithmetic.


Summary: Adds a signed immediate value to the contents of a register and places the result in another register.

Adds the signed 16-bit immediate value SI to the contents of register RA (or 0 if RA=0) and stores the result in RT. This instruction does not affect any condition registers or XER flags, and no overflow checking is performed.

addi, addis, add, and subf are the preferred instructions for addition and subtraction, because they set few status bits.


Summary: Adds an immediate to a register and updates the Carry bit.

The sum (RA) + SI is placed into register RT.

The `addic` instruction adds an immediate value to a register and sets the carry bit in the XER. It's commonly used for arithmetic operations where overflow detection is needed. Ensure that the immediate value fits within 16 bits, as it is sign-extended before addition. This instruction operates at user privilege level.


Summary: Adds an immediate, updates Carry, and updates Condition Register Field 0 (CR0).

RT ← RA + sign_extend(SI)
if RT > 2^64-1 or RT < -2^64 then XER[CA] ← 1 else XER[CA] ← 0
CR0 ← (RT < 0) || (RT > 0) || (RT = 0) || XER[SO]

Adds the signed 16-bit immediate SI to register RA and stores the result in RT, updating the Carry bit in XER and CR0. The '.' suffix indicates that CR0 is updated based on the result (LT, GT, EQ, SO). The Carry flag reflects whether the addition produced a result greater than 2^64-1.

The addic instruction is useful for adding an immediate value to a register while also handling potential overflow by setting the carry flag. Be cautious of overflow conditions that may affect subsequent operations. The result and comparison are recorded in separate registers, so ensure proper register management to avoid unintended data loss.


Summary: Adds an immediate value shifted left by 16 bits to the contents of a register and places the result in another register.

SIMM

16-bit signed immediate value shifted left by 16 bits

Adds the signed 16-bit immediate SI shifted left by 16 bits to register RA (or 0 if RA=0) and stores the result in RT. This is commonly used to load the high-order 16 bits of a 32-bit constant. No condition registers or XER flags are affected.

The addis instruction is commonly used for loading large immediate values into a register by shifting the 16-bit immediate value left by 16 bits and adding it to the contents of another register. If RA is zero, the instruction effectively sign-extends the immediate value and places it in RT. This instruction does not require any special privileges and can be used at any privilege level. However, developers should ensure that the immediate value does not cause overflow when shifted and added, as this could lead to unexpected results.


Summary: Adds the contents of a register and a constant minus one, with optional overflow exception.

The sum (RA) + CA - 1 is placed into register RT. The carry bit (CA) is used in the calculation.


Summary: Adds a register, 0, and the Carry bit.

RT ← RA + 0 + XER[CA]
if OE = 1 then
  (OV, CA) ← overflow and carry results
if Rc = 1 then
  CR0 ← (RT == 0, RT < 0, RT > 0, XER[SO])

Adds the value in RA, zero, and the Carry bit (XER[CA]), storing the result in RT. This instruction is commonly used to propagate a carry or decrement by one when combined with other arithmetic operations. Condition register CR0 is updated if Rc=1; overflow is recorded in XER[OV] if OE=1.


Summary: Performs a bitwise AND operation on the contents of two registers and places the result into another register.

if 'and' then
    RT <- (RS) & (RB)
else if 'and.' then
    RT <- (RS) & (RB)

The contents of register RS are ANDed with the contents of register RB and the result is placed into register RA.

Some forms of and Rx, Rx, Rx provide special functions; see Section 11.3 of Book III.


Summary: Performs a bitwise AND between RS and the one's complement of RB.

RA ← RS & ~RB
if Rc = 1 then
  CR0 ← (RA == 0, RA < 0, RA > 0, XER[SO])

Performs a bitwise AND between RS and the one's complement (bitwise NOT) of RB, storing the result in RA. This is equivalent to RS AND (NOT RB). Condition register CR0 is updated if Rc=1.


Summary: Performs a bitwise AND operation between the contents of a register and an immediate value, and updates the condition register.

The contents of register RS are ANDed with 480 || UI and the result is placed into register RA. The first three bits of CR Field 0 are set as described in Section 3.3.8.

The andi. instruction performs a bitwise AND operation between the contents of register RS and an immediate value UI, storing the result in RA. It also updates CR0 to reflect if the result is zero or not. Ensure that the immediate value fits within 16 bits as it is zero-extended to 32 bits before the operation.


Summary: Performs a bitwise AND between a register and a 16-bit immediate shifted left by 16 bits. Always updates CR0.

Performs a bitwise AND between RS and UI shifted left by 16 bits, storing the result in RA. The immediate operand is treated as unsigned and positioned in bits 16-31 of a 32-bit value with bits 0-15 cleared. Condition register CR0 is always updated regardless of the Rc bit (the dot indicates this behavior).

The andis. instruction is useful for masking or clearing specific bits in a register by shifting an immediate value left by 5 bits before performing the AND operation. Be cautious with alignment as it affects performance; ensure that the immediate value does not exceed 31 to avoid unexpected results. This instruction operates at user privilege level and can generate exceptions if RA is an invalid register. The result of the operation sets CR0, which can be used for conditional branching.


Summary: Adds 34-bit immediate.

Adds a 34-bit sign-extended immediate to RA (or 0 if RA=0) and stores the result in RT. The immediate is formed by concatenating prefix and suffix fields across a 64-bit prefixed instruction pair. When R=0, the offset is absolute; when R=1, it is PC-relative. This is a privileged Base extension instruction for 64-bit processors.

if R = 1 then
  RT ← (RA | 0 if RA=0) + sign_extend(SI, 34) + CIA
else
  RT ← (RA | 0 if RA=0) + sign_extend(SI, 34)

The paddi instruction is commonly used for loading addresses or small immediate values into registers. Be cautious with alignment; ensure that the immediate value does not cause overflow, which could lead to unexpected results. This instruction operates at user privilege level and does not generate exceptions under normal circumstances.


Summary: Pseudo-instruction for paddi with R=1. Loads the address of a label.

RT ← CIA + sign_extend(label_offset, 34)

Pseudo-instruction that loads the address of a label into RT. It is an assembly-time alias for 'paddi RT, 0, label, 1', where R=1 selects PC-relative addressing. This is a 64-bit prefixed instruction available only on compatible processors.

The pla instruction is used to load the address of a label into a register, effectively calculating the absolute address of the target. This is useful for setting up pointers or addresses dynamically. Ensure that the label is correctly defined and accessible in your code. The instruction operates at the same privilege level as the current execution context.


Summary: Loads a 64-bit value from memory using a 34-bit immediate offset (PC-relative or absolute).

if R = 1 then
  EA ← (RA | 0 if RA=0) + sign_extend(D34, 34) + CIA
else
  EA ← (RA | 0 if RA=0) + sign_extend(D34, 34)
RT ← [EA]

Loads a 64-bit doubleword from memory at the address calculated from RA plus a 34-bit immediate displacement, storing the result in RT. When R=1, the displacement is PC-relative; when R=0, it is treated as absolute. This is a 64-bit prefixed instruction from the Prefixed extension.

The pld instruction is commonly used for loading doubleword data from memory into a register. Ensure the base address and offset are correctly calculated to avoid accessing invalid memory locations. This instruction operates at user privilege level unless specified otherwise.


Summary: Stores a 64-bit value to memory using a 34-bit immediate offset.

if R = 1 then
  EA ← (RA | 0 if RA=0) + sign_extend(D34, 34) + CIA
else
  EA ← (RA | 0 if RA=0) + sign_extend(D34, 34)
[EA] ← RS

The pststd instruction stores a doubleword from the source register to memory. It uses the Program Counter (PC) or an effective address calculated from the base register and displacement. Ensure proper alignment for optimal performance; unaligned accesses may incur penalties. This instruction operates at user privilege level.

Stores a 64-bit doubleword from RS to memory at the address calculated from RA plus a 34-bit immediate displacement. When R=1, the displacement is PC-relative; when R=0, it is treated as absolute. This is a 64-bit prefixed instruction from the Prefixed extension.


Summary: Loads a 32-bit word and zero-extends it to 64 bits, using a 34-bit offset.

if R = 1 then
  EA ← (RA | 0 if RA=0) + sign_extend(D34, 34) + CIA
else
  EA ← (RA | 0 if RA=0) + sign_extend(D34, 34)
RT ← zero_extend([EA]0:31, 64)

Loads a 32-bit word from memory at the address calculated from RA plus a 34-bit immediate displacement, zero-extends it to 64 bits, and stores the result in RT. When R=1, the displacement is PC-relative; when R=0, it is treated as absolute. This is a 64-bit prefixed instruction from the Prefixed extension.

Use plwz when loading a word from memory into a 64-bit register with zero extension. Ensure the EA (Effective Address) is correctly calculated using the prefix and suffix fields. This instruction operates at user privilege level.


Summary: Loads a byte and zero-extends it, using a 34-bit offset.

Loads a single byte from memory at the address formed by adding the 34-bit signed displacement D34 to the base register RA, zero-extends it to 64 bits, and stores the result in RT. This is a prefixed instruction using the MLS:D-form encoding with a 34-bit effective address offset. No condition flags are affected.

The plbz instruction is used to load a single byte from memory and zero-extend it to fill the entire register. Ensure that the effective address (EA) is properly aligned for optimal performance, although misalignment does not cause an exception. This instruction operates at user privilege level.


Prefixed Masked VSX Vector BFloat16 Ger (Rank-2 Update)

Summary: Matrix Multiply Assist (MMA) instruction. Computes ACC <- ACC + (A * B) using BF16 inputs.

1 | 3 | PMSK | XMSK | YMSK | 0 | 59 | AT | / | XA | XB | XO | AX | BX | /

acc ← ACC[AT]
for i in 0..1 do
  for j in 0..3 do
    if XMSK[i] = 1 ∧ YMSK[j] = 1 then
      acc[i,j] ← acc[i,j] + (BF16(XA[i]) × BF16(XB[j]))
ACC[AT] ← acc
CR6 ← saturation_status(acc)

Prefixed MMA instruction that performs a masked rank-2 generalized matrix multiply using BFloat16 inputs. Computes ACC(AT) ← ACC(AT) + (A × B) with element-wise masking via XMSK (for rows of A) and YMSK (for columns of B). Requires MMA support and VSX category. Updates CR6 to reflect accumulator saturation status.

The pmxvbf16ger2 instruction is useful for performing matrix operations on bfloat16 data types with masking, allowing selective computation based on a mask. Ensure that the input vectors and accumulator are properly aligned to avoid performance penalties. This instruction operates at the user privilege level and will raise an exception if the result exceeds the 32-bit signed integer range, requiring saturation handling.


Summary: Performs an arbitrary 3-input boolean logic function (LUT3) on vectors. The 8-bit immediate 'IMM' defines the truth table.

for i in 0..127 do
  selector ← (XC[i] || XB[i] || XA[i])
  XT[i] ← IMM[selector]
end for

VSX instruction that performs a three-input lookup-table (LUT3) boolean operation on 128-bit vectors. The 8-bit immediate IMM encodes a truth table; for each bit position, the corresponding bit is determined by treating the three input bits (from XA, XB, XC) as a 3-bit selector into IMM. Requires VSX support; no condition flags are affected.

The xxeval instruction is used to perform complex logical operations on vector registers.


Summary: Divides the contents of two registers and places the quotient into a target register.

For divw, the 32-bit dividend is (RA)32:63. The 32-bit divisor is (RB)32:63. The 32-bit quotient is placed into RT32:63. The contents of RT0:31 are undefined.

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.


Summary: Divides the lower 32 bits of RA by the lower 32 bits of RB (Unsigned).

dividend ← (RA)[32:63]
divisor ← (RB)[32:63]
if divisor = 0 then
  quotient ← undefined
else
  quotient ← dividend ÷ divisor
RT ← (0)32 || quotient
if Rc = 1 then
  CR0 ← (quotient = 0) || (quotient < 0) || (quotient > 0) || SO

Divides the lower 32 bits of RA (treated as unsigned) by the lower 32 bits of RB (treated as unsigned) and places the 32-bit quotient in RT with the upper 32 bits of RT set to zero. If RB is zero, RT is undefined and no exception is raised (wrap-on-overflow behavior). When Rc=1, CR0 is updated based on the result; OE is reserved and must be 0.


dividend0:63 ←(RA)
divisor0:63 ←(RB)
RT ←dividend ÷ divisor

For divd, the 64-bit dividend is (RA) and the 64-bit divisor is (RB). The 64-bit quotient is placed into register RT. Both operands and the quotient are interpreted as signed integers.


Summary: Divides the 64-bit value in RA by the 64-bit value in RB (Unsigned).

dividend ← (RA)
divisor ← (RB)
if divisor = 0 then
  quotient ← undefined
else
  quotient ← dividend ÷ divisor
RT ← quotient
if Rc = 1 then
  CR0 ← (quotient = 0) || (quotient < 0) || (quotient > 0) || SO

Divides the full 64-bit value in RA (treated as unsigned) by the full 64-bit value in RB (treated as unsigned) and places the 64-bit quotient in RT. If RB is zero, RT is undefined and no exception is raised. When Rc=1, CR0 is updated based on the result; OE is reserved and must be 0.


Summary: Zeros out an entire cache block (usually 128 bytes) in memory. Critical for optimizing memory clears (memset).

EA ← (RA) + (RB)
block_start ← EA & ~(cache_block_size - 1)
for addr in block_start to block_start + cache_block_size - 1 step word_size do
  [addr] ← 0
end for

Data cache instruction that writes zeros to an entire cache block (typically 128 bytes) in memory at the effective address formed by RA + RB. The block is zero-filled and typically written back or marked clean in the cache. This is a memory hint instruction; no general-purpose registers are modified and no condition flags are affected.

dcbz does not cause the block to exist in the data cache if the block is in storage that is Caching Inhibited. For storage that is neither Write Through Required nor Caching Inhibited, dcbz provides an efficient means of setting blocks of storage to zero. It can be used to initialize large areas of such storage, in a manner that is likely to consume less memory bandwidth than an equivalent sequence of Store instructions. For storage that is either Write Through Required or Caching Inhibited, dcbz is likely to take significantly longer to execute than an equivalent sequence of Store instructions.


Summary: Hints to the hardware to prefetch the cache block at the specified address into the cache.

EA ← (RA) + (RB)
Prefetch_cache_block(EA, touch_hint=TH)

Data cache prefetch hint that loads the cache block at effective address RA + RB into the data cache with streaming characteristics controlled by the TH field. Variants (dcbtt, dcbna, dcbtds) provide transient, non-allocating, and data stream hints. This is a memory hint with no side effects on registers or condition flags; the prefetch is advisory and may be ignored.

To maximize the utility of the Depth control mechanism, the architecture provides a hierarchy of three ways to program it. The DPFD field in the LPCR is used by the provisory/firmware to set a safe or appropriate default depth for unaware operating systems and applications. The DPFD field in the DSCR may be initialized by the aware OS and overwritten by an application via the OS-provided service when per stream control is unnecessary or unaffordable.


Summary: Flushes the cache block from the data cache to main memory and invalidates it. Used for DMA coherency.

EA ← (RA) + (RB)
block_start ← EA & ~(cache_block_size - 1)
Flush_and_invalidate_cache_block(block_start, level=L)

Data cache flush instruction that writes back and invalidates the cache block at effective address RA + RB to ensure coherency with main memory. Variants (dcbfl, dcbflp, dcbfps, dcbstps) control the level and scope of the flush operation. The L field (if present) selects the cache level. No general-purpose registers are modified and no condition flags are affected.

dcbf serves as both a basic and an extended mnemonic. The Assembler will recognize a dcbf mnemonic with three operands as the basic form, and a dcbf mnemonic with two operands as the extended form. In the extended form the L operand is omitted and assumed to be 0.
dcbf with L=1 can be used to provide a hint that a block in this processor’s data cache will not be reused soon.
dcbf with L=3 can be used to flush a block from the processor’s primary data cache but reduce the latency of a subsequent access. For example, the block may be evicted from the primary data cache but a copy retained in a lower level of the cache hierarchy.


Summary: Writes the cache block to main memory if it is modified (Clean), but keeps it in the cache.

EA ← (RA) + (RB)
CacheBlock ← CacheBlock at EA
if CacheBlock.Modified then
  WriteToMemory(CacheBlock)
  CacheBlock.Modified ← 0
end if

Writes a cache block containing the byte addressed by RA+RB to main memory if the block is modified, then keeps the block in the cache in a clean state. This instruction is used to synchronize cache contents with memory without invalidating the cache line. No condition registers or status fields are affected.

Data Cache Block Store to Persistent Storage is encoded as a variant of Data Cache Block Flush. The extended mnemonic (dcbstps) indicates the intended function.


Summary: Clears a 512-bit Accumulator register (composed of 4 VSRs) to zero.

Clears the 512-bit accumulator register AT (which consists of four 128-bit VSRs) to all zeros. This instruction is part of the MMA (Matrix Multiply Assist) extension and provides a fast way to initialize an accumulator before a sequence of matrix operations. No condition registers or status fields are affected.

This instruction zeroes out all elements of the specified VSX accumulator. Ensure that VSX is enabled in the MSR register before using this instruction; otherwise, a VSX_Unavailable exception will be raised. This operation is useful for initializing accumulators or resetting them between operations.


Summary: Copies data from 4 adjacent VSRs into an Accumulator.

Copies data from four consecutive VSRs (VSR[4×AT], VSR[4×AT+1], VSR[4×AT+2], VSR[4×AT+3]) into the 512-bit accumulator AT. This instruction transfers vector data from the VSR file into MMA accumulator state. This instruction requires MMA support and does not affect any condition registers or status fields.

Ensure VSX is enabled in the MSR before using xxmtacc; otherwise, a VSX_Unavailable exception will occur. This instruction moves data from four consecutive vector scalar registers into the accumulator, so verify register allocation to avoid unintended data movement.


Summary: Copies data from an Accumulator back to 4 adjacent VSRs.

For xxmfacc, the contents of row i of ACC[AS] are placed into VSR[4×AS+i]. The contents of ACC[0] will be undefined after the first execution, which can degrade performance on subsequent executions.

if MSR.VSX=0 then VSX_Unavailable()
for each integer value i from 0 to 3 do
    VSR[4×AS+i] ← ACC[AS][i]

During extended periods of execution when there isn't any active use of the accumulators and VSX Vector GER instructions, hardware may deactivate these facilities for power savings. Once deactivated, while any attempted execution of any xxmfacc, xxmtacc, xxsetaccz, or VSX Vector GER instruction will cause these facilities to become reactivated, this reactivation causes significant delay beyond the normal execution of these instructions. This delay can be avoided by periodically issuing an xxmfacc with AS=0 instruction during extended times that the facilities are not being used to keep the facilities activated. Since the contents of ACC[0] will be undefined after the first execution, performance on subsequent executions of xxmfacc 0 can be expected to be degraded compared to performance when the contents of ACC[0] are defined. As such, to keep the facilities activated, xxmfacc 0 should be used with attention to performance implications.


VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update)

Summary: Performs an 8-bit integer outer product (GER) and accumulates into a 512-bit register.

Performs a rank-4 outer product of two 8-bit signed/unsigned integer vectors, accumulating the result into the 512-bit accumulator AT. The operation treats elements of XA and XB as 8-bit integers, computes pairwise products, and accumulates them into 32-bit or 64-bit result lanes within the accumulator. This MMA instruction does not affect condition registers or status fields.

for i = 0 to 15 do
  for j = 0 to 15 do
    ACC[AT][4×(i×16+j)] ← ACC[AT][4×(i×16+j)] + (int8)XA[8×i:8×i+7] × (int8)XB[8×j:8×j+7]
  end for
end for

The xvi8ger4 instruction requires the VSX facility to be enabled in the MSR register. It performs a rank-4 update on VSX vector elements, multiplying and accumulating 8-bit signed/unsigned integers based on specified masks. Ensure that the VSX feature is available and properly configured before using this instruction.


VSX Vector Integer 8-bit GER (Rank-4 Update) Plus/Plus

Summary: Signed/Unsigned variations of 8-bit matrix multiply accumulate.

Performs a rank-4 outer product accumulation of two 8-bit integer vectors, with sign/unsignedness controlled by inline suffix bits. The accumulate step uses saturating or wrapping semantics depending on configuration. This MMA instruction does not affect condition registers or status fields.

for i = 0 to 15 do
  for j = 0 to 15 do
    prod ← (int8)XA[8×i:8×i+7] × (int8)XB[8×j:8×j+7]
    ACC[AT][4×(i×16+j)] ← ACC[AT][4×(i×16+j)] + prod
  end for
end for

This instruction is commonly used in matrix operations where rank-4 updates are required. Ensure that the input vectors VSR[XA] and VSR[XB] are properly aligned to avoid performance penalties. The result is automatically chopped to fit into a 32-bit signed integer, so be cautious of overflow if intermediate results exceed this range.


VSX Vector Integer 16-bit GER (Rank-2 Update)

Summary: Performs a rank-2 update of the contents of two registers and updates the condition register.

For xvi16ger2, the sum of the contents of register RA and RB is placed into register RT.

if MSR.VSX=0 then VSX_Unavailable()

PMSK ←0b11
XMSK ←0b1111
YMSK ←0b1111

do i = 0 to 3
   do j = 0 to 3
      if XMSK.bit[i] & YMSK.bit[j] then do
         prod0 ←(PMSK.bit[0]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].hword[0]) *
                                       EXTS(VSR[32×BX+B].word[j].hword[0])
         prod1 ←(PMSK.bit[1]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].hword[1]) *
                                       EXTS(VSR[32×BX+B].word[j].hword[1])

         psum ←prod0 + prod1

         ACC[AT][i].word[j] ←CHOP32(psum)
      end
      else
         ACC[AT][i][j] ←0x0000_0000
   end
end

The xvi16ger2 instruction performs a 16-bit integer GER (Rank-2 Update) operation on VSX registers. Ensure that the VSX facility is enabled by checking and setting the MSR.VSX bit. The instruction processes 4x4 matrices of halfwords, multiplying corresponding elements and accumulating the results. Be cautious with overflow conditions as the products are summed without intermediate overflow checks. This instruction operates at the user privilege level and will raise an exception if VSX is unavailable.


VSX Vector Integer 16-bit GER (Rank-2 Update) Saturate

Summary: Performs a vectorized signed integer multiply and accumulate operation with saturation.

The instruction performs a vectorized signed integer multiply and accumulate operation with saturation. It multiplies the elements of two vectors and accumulates the results into a destination vector, saturating any overflow values.

if MSR.VSX=0 then VSX_Unavailable()

PMSK ←0b11
XMSK ←0b1111
YMSK ←0b1111
sat_flag ←0

do i = 0 to 3
do j = 0 to 3
   if XMSK.bit[i] & YMSK.bit[j] then do
      prod0 ←(PMSK.bit[0]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].hword[0]) * EXTS(VSR[32×BX+B].word[j].hword[0])
      prod1 ←(PMSK.bit[1]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].hword[1]) * EXTS(VSR[32×BX+B].word[j].hword[1])

      psum ←prod0 + prod1

      ACC[AT][i].word[j] ←si32_CLAMP( psum )

      if sat_flag=1 then VSCR.SAT ←1
   end
   else
      ACC[AT][i][j] ←0x0000_0000
end
end

This instruction is commonly used for vectorized operations involving 16-bit integer multiplication and accumulation with saturation. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. Be cautious of overflow conditions, as they will be saturated, which might affect the precision of your results. The instruction operates on 128-bit vectors, so ensure proper alignment for optimal performance.


Summary: Performs a vector floating-point general element-wise rank-2 update operation.

Performs a rank-2 outer product of two FP16 (half-precision floating-point) vectors, accumulating the result into the 512-bit accumulator AT. Each element of XA is multiplied by each element of XB, and products are summed across appropriate lanes. This MMA instruction requires floating-point support and does not modify condition registers or status fields.

for i = 0 to 31 do
  for j = 0 to 31 do
    ACC[AT][result_lane] ← ACC[AT][result_lane] + (fp16)XA[16×i:16×i+15] × (fp16)XB[16×j:16×j+15]
  end for
end for

The xvf16ger2 instruction is useful for performing matrix operations in VSX registers, specifically for rank-2 update accumulations. Ensure that the input matrices are correctly aligned and that the destination accumulator register is properly initialized to avoid incorrect results. This instruction operates at a high privilege level and may raise exceptions if the operands are not valid bfloat16 values.


Summary: Performs BFloat16 (Brain Float) matrix multiply accumulate.

Performs a rank-2 outer product of two BFloat16 (Brain Float) vectors, accumulating results into the 512-bit accumulator AT. BFloat16 is a truncated 32-bit floating-point format used in machine-learning workloads. This MMA instruction does not affect condition registers or status fields.

The xvbf16ger2 instruction is used for performing a rank-2 update on the accumulator using bfloat16 values from two VSX registers. Ensure that the input registers are properly aligned and that the operation does not exceed the bounds of the accumulator to avoid saturation issues. This instruction operates at privilege level 0.

for i = 0 to 31 do
  for j = 0 to 31 do
    ACC[AT][result_lane] ← ACC[AT][result_lane] + (bf16)XA[16×i:16×i+15] × (bf16)XB[16×j:16×j+15]
  end for
end for


Summary: Performs a vector floating-point general element-wise reduction with rank-1 update.

Performs a rank-1 outer product of two FP32 (single-precision floating-point) vectors, accumulating the result into the 512-bit accumulator AT. This reduction-style MMA operation multiplies corresponding FP32 elements and accumulates the products with appropriate rounding and exception behavior. No condition registers or status fields are modified.

for i = 0 to 15 do
  for j = 0 to 15 do
    prod ← (fp32)XA[32×i:32×i+31] × (fp32)XB[32×j:32×j+31]
    ACC[AT][result_lane] ← ACC[AT][result_lane] + prod
  end for
end for

The xvf32ger instruction is commonly used for matrix operations, specifically rank-1 updates. Ensure that the input matrices in VSR[XA] and VSR[XB] are correctly aligned and formatted as 4x2 matrices to avoid incorrect results. This operation requires floating-point precision and may raise exceptions if inputs are out of range or if there are NaNs or infinities involved.


Summary: Performs a vector floating-point general element-wise reduction on 64-bit elements.

Performs a rank-1 update of a 4×4 matrix accumulator using 64-bit floating-point elements from two VSX source registers. This MMA instruction computes the outer product of two vectors (each with 2 double-precision elements, implicitly extended) and accumulates the result into the 512-bit accumulator AT. No condition register or status flags are affected.

The xvf64ger instruction is commonly used for performing matrix operations in scientific computing and linear algebra. Ensure that the input vectors X and Y are properly aligned to avoid performance penalties. This instruction operates at user privilege level, but improper use can lead to undefined behavior if the accumulator register is not correctly initialized.


Prefixed Masked VSX Vector Integer 8-bit GER

Summary: Masked version of 8-bit integer MMA.

Prefixed masked version of the 8-bit integer matrix multiply-accumulate (MMA) instruction. Performs a rank-1 update of a 4×4 matrix accumulator using masked 8-bit integer elements, where XMSK controls which columns of XA participate and YMSK controls which rows of XB participate. No condition register or status flags are affected; this is a privileged MMA extension instruction.

for i in 0..3:
  for j in 0..3:
    if (XMSK[i] == 1) & (YMSK[j] == 1):
      AT[i][j] ← AT[i][j] + (XA[i] × XB[j]) (8-bit signed × 8-bit signed → 32-bit result)

This instruction is useful for performing efficient matrix multiplication on 8-bit signed integers with masking. Ensure that the mask registers (XMSK, YMSK, PMSK) are correctly set to control which elements participate in the accumulation. The operation requires VSX registers, so ensure they are properly aligned and accessible at the privilege level required by your application. Be cautious of potential overflow when accumulating products, as the result is chopped to 32 bits.


Summary: Masked version of Double-Precision MMA.

Prefixed masked version of the 64-bit floating-point matrix multiply-accumulate (MMA) instruction. Performs a rank-1 update of a 4×4 matrix accumulator using masked 64-bit floating-point elements, where XMSK controls which columns of XA participate and YMSK controls which rows of XB participate. No condition register or status flags are affected; this is a privileged MMA extension instruction.

The pmxvf64ger instruction is useful for performing masked outer product accumulation on floating-point vectors. Ensure that the mask registers XMSK and YMSK are correctly set to control which elements of the input vectors XAp and XB participate in the computation. This instruction operates at a privilege level that allows access to VSX (Vector Scalar Extensions) and requires proper alignment of the input and accumulator vectors for optimal performance.


Summary: Counts the number of trailing zeros in the low 32-bits.

Counts the number of trailing zero bits in the low 32 bits of general-purpose register RS and stores the count in RA. The count ranges from 0 to 32; if all 32 bits are zero, the result is 32. No condition register or status flags are affected.

count ← 0
for i in 0..31:
  if RS[32+i] == 0 then count ← count + 1
  else break
RA ← count

The cnttzw instruction is useful for quickly determining the number of trailing zeros in a word, which can be helpful in bit manipulation tasks. Be cautious with Rc=1 as it modifies CR0 based on the result, affecting subsequent conditional operations. Ensure that the input register (RS) is correctly aligned and contains valid data to avoid unexpected results.


Summary: Counts the number of trailing zeros in 64-bits.

Counts the number of trailing zero bits in the full 64-bit general-purpose register RS and stores the count in RA. The count ranges from 0 to 64; if all 64 bits are zero, the result is 64. No condition register or status flags are affected.

count ← 0
for i in 0..63:
  if RS[i] == 0 then count ← count + 1
  else break
RA ← count

The cnttzd instruction is useful for quickly determining the position of the least significant set bit in a 64-bit value. It operates efficiently on any aligned doubleword, but be cautious with unaligned data as it may lead to unexpected results or exceptions. This instruction can be executed at user privilege level without requiring special permissions.


Branch Conditional to Target Address Register

Summary: Conditional branch based on the contents of the Condition Register and the Count Register.

bctar BO,BI,BH                    (LK=0)

Performs a conditional branch to the target address held in the Target Address Register (TAR). The branch condition is determined by the values of the Branch Options (BO) field and the Condition Register bit (BI). The Count Register may also influence the branch condition depending on BO. No status flags are updated; the instruction may update the Link Register if suffixed with LK=1.

if condition(BO, BI, CTR) then
  NIA ← TAR
else
  NIA ← CIA + 4

In some systems, the system software will restrict usage of the bctar[l] instruction to only selected programs. If an attempt is made to execute the instruction when it is not available, the system error handler will be invoked.

bctar 20, 0, BH                    (LK=0)


Summary: Moves a GPR value to the TAR.

Move To Target Address Register. Extended mnemonic for MTSPR (mtspr 815,RS). Copies register RS into the Target Address Register (TAR).

The mttar instruction is used to copy a value from a general-purpose register (RS) into the Target Address Register (TAR). This register is typically used in conjunction with address translation operations. Ensure that the source register contains the correct address value before executing this instruction, as incorrect values can lead to unpredictable behavior or exceptions. This operation requires supervisor privilege level.


Summary: Reads the TAR into a GPR.

Move From Target Address Register. Extended mnemonic for MFSPR (mfspr RT,815). Copies the Target Address Register (TAR) into register RT.

The mftar instruction is used to copy the value of the Target Address Register (TAR) into a general-purpose register. This is typically done in contexts where precise control over branch targets or speculative execution is required. Ensure that the destination register RT is properly aligned and accessible at the privilege level executing the instruction, as accessing certain registers may require supervisor or hypervisor privileges.


Summary: Compares a byte value in one register to see if it falls within a range defined by another register.

Compares a byte value from RA against a range defined by two bytes in RB, setting the Condition Register field BF with the comparison result. The L field controls whether the comparison is unsigned (L=0) or signed (L=1). The instruction writes only the specified CR field; CR0 is not affected unless BF designates CR0.

byte_val ← RA[56:63]
range_low ← RB[56:63]
range_high ← RB[48:55]
if L == 0 then
  // unsigned comparison
  result ← (byte_val >= range_low) & (byte_val <= range_high)
else
  // signed comparison
  result ← (byte_val[signed] >= range_low[signed]) & (byte_val[signed] <= range_high[signed])
CR[BF] ← (result, 0, 0, 0)

cmprb is useful for implementing character typing functions such as isalpha(), isdigit(), isupper(), and islower() that are implemented using one or two range compares of the character. A single-range compare can be implemented with an addi to load the upper and lower bounds in the range, such as isdigit(). A combination of addi-addis can be used to set up 2 ranges, such as for isalpha().


Summary: Paste operation that updates CR0 to indicate success/fail.

A privileged operation that pastes data into a target addressed by RA, with control information from RB. The record form (Rc=1) updates CR0 to reflect the success or failure of the paste operation. This instruction is used in conjunction with copy-paste semantics for atomic data movement and synchronization in a multithreaded environment.

status ← paste_operation(RA, RB)
if Rc == 1 then
  CR0[LT] ← 0
  CR0[GT] ← 0
  CR0[EQ] ← (status == success)
  CR0[SO] ← 0

The paste instruction is used to transfer data from the copy buffer to memory. Ensure that RA and RB are correctly set to calculate the effective address (EA). If L=1, metadata in the copy buffer will be cleared before posting. Handle errors by checking CR0 for error codes.


Summary: Stores a quadword from a register to memory if a reservation exists and the conditions are met.

RSp

Source General Purpose Register containing the data to be stored

The stqcx. instruction stores a quadword from RSp to memory at the effective address (EA) calculated as RA + RB, but only if a reservation exists for that location and the reservation length is 16 bytes. If the reservation does not exist or the conditions are not met, no store is performed.

if RA = 0 then
    b ← 0
else
    b ← (RA)
EA ← b + (RB)
if RESERVE then
    if RESERVE_LENGTH = 16 and RESERVE_ADDR = real_addr(EA) then
        MEM(EA, 16) ← (RSp)
        undefined_case ← 0
        store_performed ← 1
    else
        z ← smallest real page size supported by implementation
        if RESERVE_ADDR ÷ z = real_addr(EA) ÷ z then
            undefined_case ← 1
        else
            undefined_case ← 0
            store_performed ← 0
else
    undefined_case ← 0
    store_performed ← 0
if undefined_case then
    u1 ← undefined 1-bit value
    if u1 then
        MEM(EA, 16) ← (RSp)
    u2 ← undefined 1-bit value
    CR0 ← 0b00 || u2 || XERSO
else
    CR0 ← 0b00 || store_performed || XERSO
RESERVE ← 0

Succeeds only if a valid reservation exists on the target address. Sets CR0[EQ] to 1 on success, 0 on failure. Must always be used in a retry loop that re-executes the load-reserve instruction on failure.


Summary: Loads 128 bits into two adjacent GPRs (Even/Odd pair).

For lq, the quadword in storage addressed by EA is loaded into an even-odd pair of GPRs. In Big-Endian mode, the even-numbered GPR is loaded with the doubleword from storage addressed by EA and the odd-numbered GPR is loaded with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed by EA.

if 'lq' then
    EA ← (RA|0) + EXTS64(DQ||0b0000)
    if Big-Endian byte ordering then
        RTp||RTp+1 ← MEM(EA,16)
    if Little-Endian byte ordering then
        RTp||RTp+1 ← MEM(EA,16)

The lq and stq instructions exist primarily to permit software to access quadwords in storage “atomically”.


Summary: Stores a quadword from two general-purpose registers into memory.

Stores a 128-bit quadword from two consecutive general-purpose registers (RSp and RSp+1) into memory at the address formed by adding the base register (RA) and a 16-byte-aligned displacement. The displacement is a signed 12-bit value left-shifted by 4 bits, providing a range of ±2048 bytes on a 16-byte boundary. This instruction does not modify the condition register or status flags.

EA ← if RA = 0 then 0 else GPR[RA]
EA ← EA + EXTS(DQ || 0b0000)
MEM(EA, 16) ← GPR[RSp] || GPR[RSp+1]

In versions of the architecture prior to V. 2.07, this instruction was privileged.


Summary: Loads 16-bit halfword using 34-bit offset.

Loads a 16-bit halfword from memory using a 34-bit signed offset (split between prefix and suffix) and zero-extends the loaded value into the target register. The effective address is computed from a base register or the program counter (determined by the R bit), and both absolute and PC-relative modes are supported. This is a two-instruction prefixed load with no condition register or status flag effects.

D ← EXTS(D0 || D1)
EA ← if R = 0 then (if RA = 0 then 0 else GPR[RA]) + D else CIA + D
RT ← (0)^48 || MEM(EA, 2)


Summary: Loads 16-bit halfword (Sign Extended) using 34-bit offset.

Loads a 16-bit halfword from memory using a 34-bit signed offset (split between prefix and suffix), sign-extends the loaded value to 64 bits, and stores the result in the target register. The effective address is computed from a base register or the program counter (determined by the R bit), supporting both absolute and PC-relative addressing modes. This is a two-instruction prefixed load with no condition register or status flag effects.

D ← EXTS(D0 || D1)
EA ← if R = 0 then (if RA = 0 then 0 else GPR[RA]) + D else CIA + D
RT ← EXTS(MEM(EA, 2))

The plha instruction is commonly used for loading a halfword from memory into the upper half of a register while zeroing out the lower half. Ensure that the base and index registers are correctly set to avoid incorrect memory access. This instruction operates at user privilege level and may raise an exception if the effective address is invalid or if there's a protection fault.


Summary: Loads 32-bit word (Sign Extended) using 34-bit offset.

Loads a 32-bit word from memory using a 34-bit signed offset (split between prefix and suffix), sign-extends the loaded value to 64 bits, and stores the result in the target register. The effective address is computed from a base register or the program counter (determined by the R bit), supporting both absolute and PC-relative addressing modes. This is a two-instruction prefixed load with no condition register or status flag effects.

D ← EXTS(D0 || D1)
EA ← if R = 0 then (if RA = 0 then 0 else GPR[RA]) + D else CIA + D
RT ← EXTS(MEM(EA, 4))

The plwa instruction is commonly used for loading a word from memory into a register while ensuring the upper 32 bits are zeroed. Ensure that the base address in RA and the offset in RB are correctly set to avoid incorrect memory access. This instruction operates at user privilege level and will raise an exception if the effective address is out of bounds or if there is a protection fault.


Summary: Stores byte using 34-bit offset.

Stores the least significant byte of the source register to memory using a 34-bit signed offset (split between prefix and suffix). The effective address is computed from a base register or the program counter (determined by the R bit), supporting both absolute and PC-relative addressing modes. This is a two-instruction prefixed store with no condition register or status flag effects.

D ← EXTS(D0 || D1)
EA ← if R = 0 then (if RA = 0 then 0 else GPR[RA]) + D else CIA + D
MEM(EA, 1) ← GPR[RS][56:63]

The pstb instruction is useful for storing a single byte from the uppermost byte of a register into memory. Ensure that RA and RB are correctly set to avoid incorrect memory addresses. This instruction operates at user privilege level and can raise an exception if the EA is out of bounds or if there's a protection fault.


Summary: Stores halfword using 34-bit offset.

Stores the least significant 16 bits of the source register to memory using a 34-bit signed offset (split between prefix and suffix). The effective address is computed from a base register or the program counter (determined by the R bit), supporting both absolute and PC-relative addressing modes. This is a two-instruction prefixed store with no condition register or status flag effects.

D ← EXTS(D0 || D1)
EA ← if R = 0 then (if RA = 0 then 0 else GPR[RA]) + D else CIA + D
MEM(EA, 2) ← GPR[RS][48:63]

The psth instruction is used to store the lower half of a doubleword from register RS into memory. It's important to ensure that RA and RB are correctly set to calculate the effective address. If RA is zero, the base address is considered as zero. This instruction operates at user privilege level and can raise an exception if there's a memory access violation.


Summary: Stores word using 34-bit offset.

Stores the least significant 32 bits of the source register to memory using a 34-bit signed offset (split between prefix and suffix). The effective address is computed from a base register or the program counter (determined by the R bit), supporting both absolute and PC-relative addressing modes. This is a two-instruction prefixed store with no condition register or status flag effects.

D ← EXTS(D0 || D1)
EA ← if R = 0 then (if RA = 0 then 0 else GPR[RA]) + D else CIA + D
MEM(EA, 4) ← GPR[RS][32:63]

The pstw instruction is used to store a word from a source register into memory. It supports different addressing modes based on the prefix field and privilege level. Ensure that the base address in RA is properly aligned for optimal performance, and be cautious of potential exceptions if the EA calculation results in an invalid address.


VSX Scalar Convert Unsigned Doubleword to Quad-Precision

Summary: Converts 64-bit Unsigned Integer to 128-bit Float.

Converts an unsigned 64-bit doubleword value from the source VSR into a 128-bit IEEE 754 quadruple-precision (quad) floating-point value and stores the result in the target VSR. This VSX scalar operation uses the default rounding mode from FPSCR and updates the floating-point status and control register (FPSCR) with exception flags if applicable. The instruction requires VSX facility enablement.

FRT ← ConvertUnsignedIntegerToQuadPrecision(FRB[0:63], FPSCR[RN])
FPSCR ← UpdateFlags(FPSCR)

This instruction is used to convert an unsigned doubleword integer into a quad-precision floating-point format. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking and setting the MSR.VSX bit. The conversion may alter the FPSCR register fields, so be aware of potential precision flags. This operation does not raise exceptions for normal input ranges.


VSX Scalar Convert Signed Doubleword to Quad-Precision

Summary: Converts a signed doubleword integer from VSR[VRB+32] to quad-precision floating-point in VSR[VRT+32].

The instruction converts the signed integer value in doubleword element 0 of VSR[VRB+32] to quad-precision floating-point format and stores it in VSR[VRT+32]. The FPSCR.FPRF, FPSCR.FR, and FPSCR.FI fields are updated accordingly.

if MSR.VSX=0 then VSX_Unavailable()
src ← bfp_CONVERT_FROM_SI64(VSR[VRB+32].dword[0])
result ← bfp128_CONVERT_FROM_BFP(src)
VSR[VRT+32] ← result
FPSCR.FPRF ← fprf_CLASS_BFP128(result)
FPSCR.FR ← 0
FPSCR.FI ← 0

This instruction is commonly used for converting signed integers to quad-precision floating-point numbers in VSX registers. Ensure that the VSX facility is enabled (MSR.VSX=1) to avoid exceptions. The conversion respects standard rounding rules, and the FPSCR flags are updated accordingly. Be cautious of potential overflow or underflow conditions when dealing with very large or small integers.


VSX Scalar Convert Quad-Precision to Double

Summary: Converts a quad-precision floating-point value to a double-precision floating-point value with round-to-even rounding.

Converts a 128-bit quad-precision floating-point value in VSR vB to a 64-bit double-precision floating-point value, placing the result in the low 64 bits of VSR vD using round-to-even rounding. FPSCR exception flags (XX, ZX, OX, UX) are updated based on the conversion result. Requires VSX support.

vD[0:63] ← ConvertQuadPrecisionToDoublePrecision(vB[0:127])
FPSCR[XX,ZX,OX,UX] ← updated based on conversion result

This instruction is used to convert a quad-precision floating-point number to a double-precision floating-point number. Ensure that the VSX facility is enabled in the MSR register, as attempting to use this instruction when VSX is unavailable will result in an exception. The conversion respects the rounding mode specified in the FPSCR register, and any exceptions such as invalid operation (VXSNAN), overflow (OX), underflow (UX), or inexact (XX) are recorded in the FPSCR. The result is stored in the first doubleword of the destination vector register, with the second doubleword set to zero.


Summary: Used for Quad-Precision arithmetic on hardware that splits quads.

Adds the odd (high-order) portions of two 128-bit quad-precision floating-point values in VSRs vA and vB, placing the result in VSR vD. This instruction is used on systems that split quad-precision operands into even/odd register pairs. FPSCR exception flags are updated based on the operation result. Requires VSX support.

vD ← (vA + vB) as quad-precision (odd portion operation)
FPSCR[XX,ZX,OX,UX,VXISI] ← updated based on operation result

The xsaddqpo instruction is used for adding two quad-precision floating-point numbers using the round-to-odd rounding mode. Ensure that the input operands are correctly aligned and that the VSX registers are properly set up. This instruction operates at a privilege level that allows access to floating-point operations, and it may raise exceptions if invalid operations occur, such as signaling NaNs or infinities. Performance can be impacted by the precision of the operation and the current rounding mode settings in the FPSCR register.


Subtracts the odd (high-order) portion of a 128-bit quad-precision floating-point value in VSR vB from the odd portion in VSR vA, placing the result in VSR vD. This instruction is used on systems that split quad-precision operands into even/odd register pairs. FPSCR exception flags are updated based on the operation result. Requires VSX support.

vD ← (vA - vB) as quad-precision (odd portion operation)
FPSCR[XX,ZX,OX,UX,VXISI] ← updated based on operation result

This instruction is commonly used for precise floating-point arithmetic operations in scientific computing. Be cautious of NaN handling; if src2 is a Quiet NaN, it will propagate as the result without performing any subtraction. Ensure that inputs are properly aligned to avoid alignment faults. This operation requires FPSCR for exception flags and rounding modes.


Divides the odd (high-order) portion of a 128-bit quad-precision floating-point value in VSR vA by the odd portion in VSR vB, placing the result in VSR vD. This instruction is used on systems that split quad-precision operands into even/odd register pairs. FPSCR exception flags are updated, including division-by-zero detection (ZX). Requires VSX support.

vD ← (vA / vB) as quad-precision (odd portion operation)
FPSCR[XX,ZX,OX,UX,VXIDI,VXISI] ← updated based on operation result

The xsdivqpo instruction performs a scalar divide operation on two quad-precision floating-point values, rounding the result to the nearest odd integer when there is a tie. Ensure that VSX is enabled in the MSR register; otherwise, an exception will be raised. Be cautious with division by zero, as it results in infinity or NaN depending on the sign of the dividend.


VSX Scalar Square Root Quad-Precision Odd

Computes the square root of the odd (high-order) portion of a 128-bit quad-precision floating-point value in VSR vB, placing the result in VSR vD. This instruction is used on systems that split quad-precision operands into even/odd register pairs. FPSCR exception flags are updated based on the operation result. Requires VSX support.

vD ← sqrt(vB) as quad-precision (odd portion operation)
FPSCR[XX,ZX,OX,UX,VXSQRT] ← updated based on operation result

The xssqrtqpo instruction is used to compute the square root of a quad-precision floating-point value using the Round to Odd rounding mode. It handles signaling NaNs by raising an Invalid Operation exception and setting VXSNAN in the FPSCR. Ensure that the input is properly aligned and check the FPSCR for exceptions after execution.


VSX Scalar Round Quad-Precision to Integer

Summary: Rounds a quad-precision floating-point value in VRB to an integer and places the result in VRT.

Rounds a 128-bit quad-precision floating-point value in VSR vB to an integer value using rounding mode R, placing the result back in VSR vD as a quad-precision value. The rounding mode R is encoded in bit 31 (0=round-to-nearest-even, 1=round-toward-zero). FPSCR exception flags (XX, ZX) are updated based on the rounding operation. Requires VSX support.

rmode ← (R == 0) ? RoundToNearestEven : RoundTowardZero
vD ← RoundToInteger(vB, rmode) as quad-precision
FPSCR[XX,ZX] ← updated based on rounding result

The xsrqpi instruction is used to round a quad-precision floating-point value to an integer. Ensure that the VSX feature is enabled in the MSR register. Be cautious with NaN values, as they can trigger exceptions and set specific flags. The rounding mode is determined by the RMC field and the FPSCR.RN setting when R=0.


VSX Scalar Round Quad-Precision to Integer Extended

Summary: Rounds a Quad float to a Quad integer (Exact).

Rounds a quad-precision floating-point value in FRB to a quad-precision integer, placing the result in FRT. The rounding mode is specified by the R operand. FPSCR is updated with exceptions; this is a VSX instruction requiring VSX support.

let temp ← RoundToQuadInt(FRB, R)
FRT ← temp
FPSCR[FPRF, XX, ZX, UX, OX] ← updated based on operation

The xsrqpix instruction is used to round a quad-precision floating-point number to an integer. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register, as attempting to use this instruction when VSX is unavailable will result in an exception. The rounding mode is determined by the FPSCR register, and the instruction handles special cases like NaNs by setting appropriate flags in the FPSCR.


Summary: Copies a float register (Pseudo: for FRB).

The contents of register FRB are placed into register FRT.

The fmr instruction is used to copy the contents of one floating-point register (FRB) to another (FRT). It does not alter any special registers unless Rc=1, in which case it updates CR1. Ensure that both source and destination registers are properly aligned for optimal performance.


Summary: Computes absolute value of a float.

Computes the absolute value of a double-precision floating-point number in FRB and places the result in FRT. The sign bit is cleared while all other bits remain unchanged. No exception flags are set.

The fabs instruction is commonly used when you need to ensure that a floating-point number is positive without altering its magnitude. Be cautious with NaN (Not-a-Number) values, as fabs will return a quiet NaN if the input is a signaling NaN. This instruction operates at user privilege level and does not raise exceptions for normal inputs; however, it respects the rounding mode set in the FPSCR register.


Summary: Negates a float.

Negates a double-precision floating-point number in FRB by flipping the sign bit and places the result in FRT. No exception flags are set.

The fneg instruction is commonly used to change the sign of a floating-point number. Ensure that the source register (FRA) contains a valid floating-point value before executing this instruction. The result is stored in the target register (FRT), which must be distinct from FRA. This operation does not affect any special registers like FPSCR unless there are exceptions such as invalid operations or overflow.


Summary: Computes negative absolute value of a float.

Computes the negative absolute value of a double-precision floating-point number in FRB and places the result in FRT. The sign bit is set to 1 while all other bits are taken from the absolute value. No exception flags are set.

The fnabs instruction is useful for converting a positive floating-point number to its negative counterpart while maintaining its magnitude. Ensure that the input register (FRB) contains a valid floating-point value; otherwise, the result may be undefined. This operation does not affect the FPSCR register, so no exception flags are set based on the input value.


Summary: Copies sign from FRB to FRA.

Copies the sign bit from FRB to FRA, placing the result in FRT. The magnitude of FRA is preserved while the sign is replaced by that of FRB. No exception flags are set.

Use fcpsgn to change the sign of a floating-point number without altering its magnitude. Ensure both source and target registers are properly aligned and accessible. This instruction operates at user privilege level but may raise exceptions if operands are invalid or if there are precision issues.


Summary: Selects FRA if FRC >= 0, else FRB (Optional).

Selects between FRA and FRB based on the sign of FRC: if FRC ≥ 0, the result is FRA; otherwise, the result is FRB. The optional dot (.) form sets CR1 based on the result's FPRF. This is an optional category instruction.

if FRC ≥ 0.0 then
  FRT ← FRA
else
  FRT ← FRB
if Rc = 1 then CR1 ← FPRF(FRT)

Warning: Care must be taken in using fsel if IEEE compatibility is required, or if the values being tested can be NaNs or infinities.


Summary: Computes the square root of a floating-point number.

The square root of the floating-point operand in register FRB is placed into register FRT. If the most significant bit of the resultant significand is not 1, the result is normalized. The result is rounded to the target precision under control of RN and placed into register FRT.

if FRB < 0 then
    FRT ← QNaN
    if VE = 1 then raise VXSQRT exception
else
    FRT ← sqrt(FRB)
    if most significant bit of FRT's significand is not 1 then normalize FRT
    round FRT to target precision under control of RN
end if
FPSCR.FPRF ← class and sign of FRT
if VE = 1 and result is invalid operation exception then raise VXSQRT exception

The fsqrt instruction computes the square root of a floating-point number. It handles negative inputs by returning a quiet NaN (QNaN) and may raise an exception if enabled. Ensure the input is non-negative to avoid unexpected results. The result is normalized and rounded according to the current rounding mode, which can affect precision.


Summary: Computes square root (Single).

Computes the square root of a single-precision floating-point value in FRB and places the double-precision result in FRT. FPSCR exception flags (XX, ZX, UX, OX, VXSQRT) are updated appropriately.

FRT ← sqrt(FRB)
FPSCR[FPRF, XX, ZX, UX, OX, VXSQRT] ← updated based on operation

The fsqrts instruction is commonly used for calculating the square root of single-precision floating-point numbers. Ensure that the input register FRB contains a valid single-precision float; otherwise, the result may be undefined or trigger an exception. The instruction operates at user privilege level and does not require any specific ordering or alignment of data. Be aware of rounding modes controlled by RN, as they can affect the precision of the result.


Summary: Multiplies two floating-point values and subtracts a third.

Performs a fused multiply-subtract operation: (FRA × FRC) - FRB in extended precision, then rounds to double-precision and places the result in FRT. FPSCR exception flags and FPRF are updated; this provides higher precision than separate multiply and subtract instructions.

FRT ← Round((FRA × FRC) - FRB)
FPSCR[FPRF, XX, ZX, UX, OX, VXISI] ← updated based on operation

The fmsub instruction is useful for performing fused multiply-subtract operations, which can help reduce rounding errors. Ensure that the input registers are properly aligned and contain valid floating-point numbers to avoid exceptions. This operation requires FPSCR to manage precision and exception flags.


Summary: Performs a floating-point negative multiply-add operation.

The operation FRT ←- ( [(FRA)×(FRC)] + (FRB) ) is performed. The result is negated and placed into register FRT.

FRT ←- ( [(FRA)×(FRC)] + (FRB) )
if 'fnmadd.' then
    update CR1 and FPSCR fields

The fnmadd instruction is useful for performing a negated multiply-add operation on floating-point numbers. Ensure that the input registers FRA, FRC, and FRB are correctly aligned and contain valid floating-point values to avoid exceptions. If using the 'fnmadd.' form, be aware that it updates CR1 and FPSCR, which can affect subsequent conditional operations or exception handling.


Summary: -(A*C - B)

Floating Negative Multiply-Subtract computes -(A*C - B) using fused multiply-subtract, where the intermediate product is not rounded. The result is rounded to the target precision according to the current rounding mode in FPSCR. FPSCR is updated with FPRF, FR, FI, and exception flags based on the result.

FRT ← -((FRA × FRC) - FRB)
Update FPSCR[FPRF, FR, FI, exception flags]

The fnmsub instruction is commonly used in scenarios requiring efficient floating-point arithmetic operations, such as in scientific computations or graphics processing. Ensure that the input registers FRA, FRC, and FRB are properly aligned to avoid precision loss. Be aware of potential exceptions like underflow or overflow, which can be managed by checking the FPSCR register after execution.


Summary: Rounds the contents of a floating-point register to single-precision.

The floating-point operand in register FRB is rounded to single-precision using the rounding mode specified by RN and placed into register FRT.

if (FRB)1:11 < 897 and (FRB)1:63 > 0 then
    if FPSCRUE = 0 then goto Disabled Exponent Underflow
    if FPSCRUE = 1 then goto Enabled Exponent Underflow
end

if (FRB)1:11 > 1150 and (FRB)1:11 < 2047 then
    if FPSCROE = 0 then goto Disabled Exponent Overflow
    if FPSCROE = 1 then goto Enabled Exponent Overflow
end

if (FRB)1:11 > 896 and (FRB)1:11 < 1151 then goto Normal Operand

if (FRB)1:63 = 0 then goto Zero Operand

if (FRB)1:11 = 2047 then
    if (FRB)12:63 = 0 then goto Infinity Operand
    if (FRB)12 = 1 then goto QNaN Operand
    if (FRB)12 = 0 and (FRB)13:63 > 0 then goto SNaN Operand
end

Disabled Exponent Underflow:
    sign ←(FRB)0
    if (FRB)1:11 = 0 then
        exp ←-1022
        frac0:52 ←0b0 || (FRB)12:63
    end
    if (FRB)1:11 > 0 then
        exp ←(FRB)1:11 -1023
        frac0:52 ←0b1 || (FRB)12:63
    end
    Denormalize operand:
        G || R || X ←0b000
        do while exp < -126
            exp ←exp + 1
            frac0:52 || G || R || X ←0b0 || frac0:52 || G || (R | X)
        end
    FPSCRUX ←(frac24:52 || G || R || X) > 0
    Round Single(sign,exp,frac0:52,G,R,X)
    FPSCRXX ←FPSCRXX | FPSCRFI

FPSCR (FPRF FR FI FX OX UX XX VXSNAN), CR1

The frsp instruction rounds a double-precision floating-point number to single precision. It handles various cases like underflow, overflow, and NaNs, setting appropriate flags in the FPSCR register. Ensure that the input register FRB is correctly set before calling this instruction.


Floating Convert with round Double-Precision To Signed Doubleword format X-form (Rc=0)

Summary: Converts a double-precision floating-point value to a signed 64-bit integer using rounding.

Let src be the double-precision floating-point value in FRB. If src is a NaN, then the result is 0x8000_0000_0000_0000, VXCVI is set to 1, and if src is an SNaN, VXSNAN is set to 1. Otherwise, src is rounded to a floating-point integer using the rounding mode specified by RN. If the rounded value is greater than 263-1, then the result is 0x7FFF_FFFF_FFFF_FFFF and VXCVI is set to 1. Otherwise, if the rounded value is less than -263, then the result is 0x8000_0000_0000_0000 and VXCVI is set to 1. Otherwise, the result is the rounded value converted to 64-bit signed-integer format, and XX is set to 1 if the result is inexact. If an enabled Invalid Operation Exception does not occur, then the result is placed into FRT.

if src is a NaN then
    FRT <- 0x8000_0000_0000_0000
    VXCVI <- 1
    if src is an SNaN then VXSNAN <- 1
else
    rounded_value <- round(src, RN)
    if rounded_value > 263-1 then
        FRT <- 0x7FFF_FFFF_FFFF_FFFF
        VXCVI <- 1
    else if rounded_value < -263 then
        FRT <- 0x8000_0000_0000_0000
        VXCVI <- 1
    else
        FRT <- convert_to_signed_integer(rounded_value)
        XX <- is_inexact(FRT)
if not enabled Invalid Operation Exception then
    place result into FRT

FPSCR, (FR, FI, FX, XX, VXSNAN, VXCVI), CR1, (if, Rc=1), CR0

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.


Summary: Converts Double to 64-bit Int (Truncate).

Floating Convert to Integer Doubleword with Round to Zero converts the double-precision floating-point value in FRB to a signed 64-bit integer, truncating toward zero (round-to-zero), and places the result in FRT as a floating-point representation. FPSCR is updated with FPRF, FR, and FI flags; exception flags (XX, ZX) are set if applicable.

FRT ← (int64_t)truncate(FRB)
Update FPSCR[FPRF, FR, FI, XX, ZX]

The fctidz instruction converts a double-precision floating-point value to a signed 64-bit integer, rounding towards zero. If the source value is NaN, it returns 0x8000_0000_0000_0000 and sets VXCVI to 1. If the rounded value exceeds the range of a 64-bit signed integer, it saturates to either 0x7FFF_FFFF_FFFF_FFFF or 0x8000_0000_0000_0000.


Summary: Converts Double to 32-bit Int (Truncate).

Floating Convert to Integer Word with Round to Zero converts the double-precision floating-point value in FRB to a signed 32-bit integer, truncating toward zero, and places the result in FRT as a floating-point representation. FPSCR is updated with FPRF, FR, and FI flags; exception flags (XX, ZX) are set if applicable.

FRT ← (int32_t)truncate(FRB)
Update FPSCR[FPRF, FR, FI, XX, ZX]

The fctiwz instruction is commonly used for converting floating-point numbers to integers with truncation. Be cautious of NaN inputs, which will result in zero and set VXCVI; SNaNs also set VXSNAN. Ensure the input is within the 32-bit signed integer range to avoid saturation. This instruction operates at user privilege level.


Floating Convert with round Signed Doubleword to Double-Precision format

Summary: Converts a signed doubleword integer to a double-precision floating-point number.

The 64-bit signed fixed-point operand in register FRB is converted to an infinitely precise floating-point integer. The result of the conversion is rounded to double-precision, using the rounding mode specified by RN, and placed into register FRT.

if 'fcfid' then
    FRT <- (FRB) converted to double-precision floating-point integer
    round result using RN
    if Rc=1 then update CR1

Converting a signed integer word to double-precision floating-point can be accomplished by loading the word from storage using Load Float Word Algebraic Indexed and then using fcfid.


Floating Convert with round Signed Doubleword to Single-Precision format

Summary: Converts a 64-bit signed fixed-point operand in register FRB to single-precision floating-point.

The 64-bit signed fixed-point operand in register FRB is converted to an infinitely precise floating-point integer. The result of the conversion is rounded to single-precision, using the rounding mode specified by RN, and placed into register FRT.

FPSCR (FPRF, FR, FI, FX, XX), CR1 (if Rc=1)

Converting a signed integer word to single-precision floating-point can be accomplished by loading the word from storage using Load Float Word Algebraic and then using fcfids.

FRT ← ConvertToFloat(FRB, RN)
SetFlags(FPRF, FR, FI)


Summary: Converts 64-bit Unsigned Int to Double.

Floating Convert from Unsigned Integer Doubleword converts the unsigned 64-bit integer held in FRB to a double-precision floating-point value and places the result in FRT. The conversion uses the current rounding mode in FPSCR. FPSCR is updated with FPRF, FR, and FI flags.

FRT ← (double)(uint64_t)FRB
Update FPSCR[FPRF, FR, FI]

The fcfidu instruction converts a 64-bit unsigned integer to a double-precision floating-point value. Be cautious of NaN inputs, which will result in zero with VXCVI set. Ensure the source register contains valid data; otherwise, unexpected results may occur. This instruction operates at user privilege level.


Summary: Converts 64-bit Unsigned Int to Single.

Floating Convert from Unsigned Integer Doubleword Single converts the unsigned 64-bit integer held in FRB to a single-precision floating-point value and places the result in FRT. The conversion uses the current rounding mode in FPSCR. FPSCR is updated with FPRF, FR, and FI flags.

FRT ← (float)(uint64_t)FRB
Update FPSCR[FPRF, FR, FI]

The fcfidus instruction is used to convert a 64-bit unsigned integer from one register to a single-precision floating-point number in another register. Ensure the source register contains a valid unsigned integer and that the rounding mode specified by RN is appropriate for your application. This instruction alters several fields in the FPSCR, so be aware of potential flag changes that may affect subsequent operations.


Summary: Loads a 128-bit vector from memory into a Vector Register. Address must be 16-byte aligned (bits 60-63 of effective address are ignored).

Load Vector Indexed loads a 128-bit vector from memory at the address computed from RA and RB, placing the result in VRT. The effective address must be 16-byte aligned; the low 4 bits of the computed address are ignored. This is a VMX/AltiVec instruction requiring the Vector facility to be enabled.

The Load Vector Element instructions load the specified element into the same location in the target register as the location into which it would be loaded using the Load Vector instruction.


Summary: Stores a quadword from a vector register to memory at an address formed by adding two general-purpose registers.

if MSR.VEC=0 then
    Vector_Unavailable()
EA ←((RA=0) ? 0 : GPR[RA]) + GPR[RB]
EA ←EA & 0xFFFF_FFFF_FFFF_FFF0
MEM(EA, 16) ←VSR[VRS+32]

The contents of VSR[VRS+32] are placed into the quad-word in storage at address EA, which is the result of ANDing 0xFFFF_FFFF_FFFF_FFF0 with the sum (RA|0) + (RB).

The stvx instruction stores a vector register into memory. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register if necessary. The effective address (EA) must be aligned to a 16-byte boundary, as indicated by the AND operation with 0xFFFF_FFFF_FFFF_FFF0. This instruction operates at user privilege level but will raise an exception if the Vector Facility is not available.


Summary: Subtracts the contents of two vector registers and updates the result in another vector register.

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ←EXTZ(VSR[VRA+32].word[i])
    src2 ←EXTZ(VSR[VRB+32].word[i])
    VSR[VRT+32].word[i] ←CHOP32(src1 + ¬src2 + 1)
end

For vsubuwm, each word element in VSR[VRB+32] is subtracted from the corresponding word element in VSR[VRA+32]. The low-order 32 bits of the result are placed into the corresponding word element in VSR[VRT+32].

This instruction performs unsigned word modulo subtraction on vector registers. Ensure that the Vector Facility is enabled by checking and setting the appropriate bit in the MSR register. Be cautious of potential overflow conditions, as this operation does not handle carry-out explicitly. The operation is performed on 32-bit words, so ensure proper alignment if dealing with larger data types.


Summary: Copies a single word element from the source vector into all four word elements of the destination.

word ← VRB[4×UIM : 4×UIM+31]
VRT[0:31] ← word
VRT[32:63] ← word
VRT[64:95] ← word
VRT[96:127] ← word

Vector Splat Word copies a single word element (32 bits) from the source vector VRB at position UIM into all four word elements of the destination vector VRT. UIM selects one of the four words (0-3) in the source. This is a VMX/AltiVec instruction.

The vspltw instruction is used to replicate a selected word from one vector register into all words of another vector register. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. The index 'b' is derived by concatenating the UIM field with four zeros, and it specifies which 32-bit word to replicate. This instruction operates at the user privilege level.


Summary: The signature AltiVec instruction. Constructs a new vector by selecting bytes from two source vectors based on a permute control vector.

for i ← 0 to 15
  control ← VRC[8×i : 8×i+4]
  if control < 16 then
    VRT[8×i : 8×i+7] ← VRA[8×control : 8×control+7]
  else
    VRT[8×i : 8×i+7] ← VRB[8×(control-16) : 8×(control-16)+7]

Vector Permute constructs a new 128-bit vector in VRT by selecting bytes from two source vectors (VRA and VRB) using a permute control vector VRC. Bytes 0-15 of the result come from VRA, bytes 16-31 from VRB; the low 5 bits of each byte in VRC index into the 32-byte concatenated source. This is the signature VMX/AltiVec instruction and requires the Vector facility.

See the Programming Notes with the Load Vector for Shift Left and Load Vector for Shift Right instructions on page 266 for examples of uses of vperm.


Summary: Shifts each of the four words in vA left by the number of bits specified in the corresponding word of vB.

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ← VSR[VRA+32].word[i]
    src2 ← VSR[VRB+32].word[i].bit[27:31]
    VSR[VRT+32].word[i] ← src1 << src2

For vslw, each word element of VSR[VRA+32] is shifted left by the number of bits specified in the low-order 5 bits of the corresponding word element of VSR[VRB+32].

The vslw instruction shifts each word element of the source vector left by a specified number of bits. Ensure that the shift amount is within the range 0-31 to avoid undefined behavior. This operation requires the Vector Facility to be enabled in the MSR register; otherwise, it will raise an exception.


Summary: Compares each word of two vector registers and sets the corresponding word in the target register to all 1s if they are equal, otherwise all 0s.

if MSR.VEC=0 then Vector_Unavailable()

all_true ←1
all_false ←1
do i = 0 to 3
   src1 ←VSR[VRA+32].word[i]
   src2 ←VSR[VRB+32].word[i]
   if src1 = src2 then do
      VSR[VRT+32].word[i] ←0xFFFF_FFFF
      all_false ←0
   end
   else do
      VSR[VRT+32].word[i] ←0x0000_0000
      all_true ←0
   end
end
do i = 0 to 3
   src1 ←VSR[VRA+32].word[i]
   src2 ←VSR[VRB+32].word[i]
   if src1 = src2 then do
      VSR[VRT+32].word[i] ←0xFFFF_FFFF
      all_false ←0
   end
   else do
      VSR[VRT+32].word[i] ←0x0000_0000
      all_true ←0
   end
end
if Rc=1 then
   CR.field[6] ←all_true || 0b0 || all_false || 0b0

For vcmpequw, each word of VSR[VRA+32] is compared with the corresponding word of VSR[VRB+32]. If they are equal, the corresponding word in VSR[VRT+32] is set to 0xFFFF_FFFF; otherwise, it is set to 0x0000_0000.


Summary: Bitwise selection. copies bits from vA if the corresponding bit in vC is 0, or from vB if vC is 1. (Like 'mux').

for i in 0 to 127:
  if vC[i] = 0 then vD[i] ← vA[i]
  else vD[i] ← vB[i]

Performs bitwise selection from two source vectors based on a control vector. For each bit position, copies the bit from vA if the corresponding bit in vC is 0, or from vB if vC is 1. This is a three-operand mux operation. No condition registers or status flags are affected.

The vsel instruction requires the Vector Facility to be enabled in the MSR. Ensure that VRA, VRB, and VRC are properly aligned and contain valid data. The result is stored in VRT, so ensure it is not being used elsewhere in your computation until the operation completes.


Summary: Loads a 128-bit vector from memory into a VSX register. Does NOT require 16-byte alignment (unlike lvx).

if MSR.VSX=0 then VSX_Unavailable()
EA ←((RA=0) ? 0 : GPR[RA]) + GPR[RB]
for i from 0 to 1 do
    VSR[32×TX+T].dword[i] ←MEM(EA+8×i, 8)

The contents of the byte in storage at address EA+8×i+7 are placed into byte element 7 of load_data. When Little-Endian byte ordering is employed, the contents of the doubleword in storage at address EA+8×i are placed into load_data in such an order that; the contents of the byte in storage at address EA+8×i are placed into byte element 7 of load_data, and so forth until the contents of the byte in storage at address EA+8×i+7 are placed into byte element 0 of load_data. For each integer value i from 0 to 1, do the following.

lxvd2x, lxvw4x, lxvh8x, lxvb16x, and lxvx exhibit identical behavior in Big-Endian mode.


Summary: Stores a 128-bit VSX register to memory. Does NOT require alignment.

Stores a 128-bit VSX register to memory at the address computed from the base and index registers. The address is the sum of RA and RB (or 0 if RA = 0). Unlike some VSX store instructions, this instruction does not require natural alignment. No condition registers or status flags are affected.

stxvd2x, stxvw4x, stxvh8x, stxvb16x, and stxvx exhibit identical behavior in Big-Endian mode.


Summary: Adds the contents of two double-precision floating-point elements from two vector registers and places the result into a target vector register.

if MSR.VSX=0 then VSX_Unavailable()

ex_flag ←0b0
do i = 0 to 1
    reset_xflags()
    src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[i])
    src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])
    v    ←bfp_ADD(src1,src2)
    rnd  ←bfp_ROUND_TO_BFP64(0b0,FPSCR.RN,v)
    vresult.dword[i] ←bfp64_CONVERT_FROM_BFP(rnd)

    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    if vxisi_flag=1 then SetFX(FPSCR.VXISI)
    if ox_flag=1 then SetFX(FPSCR.OX)
    if ux_flag=1 then SetFX(FPSCR.UX)
    if xx_flag=1 then SetFX(FPSCR.XX)

    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vxisi_flag) | (FPSCR.OE & ox_flag) | (FPSCR.UE & ux_flag) | (FPSCR.XE & xx_flag)
end

if ex_flag=0 then VSR[32×TX+T] ←vresult

For xvadddp, the sum of the contents of doubleword element i of VSR[XA] and VSR[XB] is placed into doubleword element i of VSR[XT].

This instruction is commonly used for adding two double-precision floating-point numbers stored in VSX registers. Ensure that the VSX facility is enabled by checking and setting the MSR.VSX bit. Be aware of potential exceptions such as NaNs or infinities, which can set flags in the FPSCR register. The operation respects the rounding mode specified in FPSCR.RN.


VSX Vector Multiply-Add Double-Precision

Summary: Performs a double-precision floating-point multiply-add operation on vector elements.

if MSR.VSX=0 then VSX_Unavailable()
ex_flag ←0b0
do i = 0 to 1
    reset_xflags()
    src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[i])
    src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×TX+T].dword[i])
    src3 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])
    v   ←bfp_MULTIPLY_ADD(src1,src3,src2)
    rnd ←bfp_ROUND_TO_BFP64(0b0,FPSCR.RN,v)
    vresult.dword[i] ←bfp64_CONVERT_FROM_BFP(rnd)
    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    if vximz_flag=1 then SetFX(FPSCR.VXIMZ)
    if vxisi_flag=1 then SetFX(FPSCR.VXISI)
    if ox_flag=1 then SetFX(FPSCR.OX)
    if ux_flag=1 then SetFX(FPSCR.UX)
    if xx_flag=1 then SetFX(FPSCR.XX)
    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vximz_flag) | (FPSCR.VE & vxisi_flag) | (FPSCR.OE & ox_flag) | (FPSCR.UE & ux_flag) | (FPSCR.XE & xx_flag)
end
if ex_flag=0 then VSR[32×TX+T] ←result

For xvmaddadp, the double-precision floating-point operand in doubleword element i of VSR[XA] is multiplied by the double-precision floating-point operand in doubleword element i of VSR[XB], and then added to the double-precision floating-point operand in doubleword element i of VSR[XT]. The result is normalized and rounded to double precision.

This instruction is commonly used for performing vectorized floating-point operations in parallel, which can significantly speed up computations involving large datasets. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking and setting the appropriate bits in the MSR register. Be cautious of potential exceptions such as NaNs or infinities, which can trigger flags in the FPSCR register. The instruction operates on double-precision floating-point numbers, so ensure proper alignment and data types to avoid undefined behavior.


Summary: Selects two doublewords from the four available in source registers XA and XB based on a 2-bit selector.

Selects two 64-bit doublewords from source registers XA and XB and places them in target register XT. The 2-bit selector DM controls which doubleword is chosen: bits [1:0] of DM select from XA for the high half of XT, and bits [3:2] select from XB for the low half. No condition registers or status flags are affected.

The xxpermdi instruction is used to permute doublewords from two VSX registers into a third register based on an immediate value. Ensure that the VSX facility is enabled in the MSR register; otherwise, a VSX_Unavailable exception will be raised. The immediate value DM controls which doubleword elements are selected from VSR[XB] for placement in VSR[XT].


Summary: Adds two double-precision floating-point values from vector scalar registers and stores the result in a target vector scalar register.

XT[0:63] ← unchanged
XT[64:127] ← XA[64:127] + XB[64:127]
FPSCR ← updated based on operation and rounding

Adds two double-precision floating-point scalar values held in the least-significant 64 bits of VSX registers XA and XB. The result is placed in the least-significant 64 bits of XT; the high 64 bits of XT are unchanged. Floating-point exceptions and FPSCR flags (VX, OX, UX, etc.) are updated according to the result and rounding mode.

Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.


Summary: Subtracts the contents of two DFP registers and places the result in another DFP register.

The DFP operand in FRB[p] is subtracted from the DFP operand in FRA[p]. The result is rounded to the target-format precision under control of DRN (bits 29:31 of the FPSCR). An appropriate form of the rounded result is selected based on the ideal exponent and is placed in FRT[p]. The ideal exponent is the smaller exponent of the two source operands.

if 'dsub' then
    FRT[p] <- (FRA[p]) - (FRB[p])

FPSCR, FPRF, FR, FI, FX, OX, UX, XX, VXSNAN, VXISI, CR1

The dsub instruction performs a decimal subtraction between two DFP operands. Ensure that both operands are properly aligned and formatted according to the target precision specified in the FPSCR register. Be aware of potential rounding errors based on the current rounding mode set in DRN, and check for any exceptions or flags (like VXSNAN) that may indicate invalid operations or special results.


Summary: Divides the contents of two decimal floating-point registers and places the result in a target register.

The DFP operand in FRA is divided by the DFP operand in FRB. The result is rounded to the target-format precision under control of the DRN (bits 29:31 of the FPSCR). An appropriate form of the rounded result is selected based on the ideal exponent and is placed in FRT.

if 'ddiv' then
    FRT <- (FRA) / (FRB)
    if Rc=1 then
        CR1 <- result of comparison

The ddiv instruction performs a decimal division, rounding the result according to the precision control bits in FPSCR. Ensure that operands are properly aligned and check for division by zero or overflow conditions, which may trigger exceptions. The result can be compared if Rc is set, updating CR1 accordingly.


Summary: Compares two DFP operands and sets the CR field to indicate the result.

Compares two decimal floating-point numbers and updates the specified condition register field. The comparison treats quiet NaNs as unordered (unlike ordered compare). The result sets the Less Than, Greater Than, Equal, or Unordered bits in the target CR field. No other status flags are affected.

if FRA is NaN or FRB is NaN then
  CR[BF] ← 0b0001  (Unordered)
else if FRA < FRB then
  CR[BF] ← 0b1000  (Less Than)
else if FRA > FRB then
  CR[BF] ← 0b0100  (Greater Than)
else
  CR[BF] ← 0b0010  (Equal)

The dcmpu instruction is used to compare two decimal floating-point numbers. It sets the condition register field BF based on the comparison result, which can be less than (FL), greater than (FG), equal to (FE), or unordered (FU) if either operand is NaN. Ensure that both operands are properly aligned and valid DFP values to avoid undefined behavior.


Summary: Compares two decimal floating-point operands and updates the condition register.

The DFP operand in FRA is compared to the DFP operand in FRB. The result of the compare is placed into CR field BF and the FPCC.

dcmpo[q] are treated as Floating-Point instructions in terms of resource availability.


Summary: Converts DFP Short (32-bit compressed) to DFP Long (64-bit).

The DFP short operand in bits 32:63 of FRB is converted to DFP long format and the converted result is placed into FRT. The sign of the result is the same as the sign of the source operand. The ideal exponent is the exponent of the source operand.

Note that DFP short format is a storage-only format. Therefore, conversion of a short SNaN to long format will not cause an exception and the SNaN is preserved. Subsequent operation on that SNaN in long format will cause an exception.


Summary: Rounds DFP Long (64-bit) to DFP Short (32-bit compressed).

The DFP long operand in FRB is converted and rounded to DFP short format. The DFP short value is extended on the left with zeros to form a 64-bit entity and placed into FRT. The sign of the result is the same as the sign of the source operand.

if 'drsp' then
    FRT <- (FRB) rounded to DFP short format
    if Rc=1 then
        CR0, CR1 <- updated based on result

Note that DFP short format is a storage-only format. Therefore, conversion of a long SNaN to short for mat will not cause an exception.


Summary: Converts a 64-bit integer to DFP.

Converts a 64-bit signed integer from FRB to a decimal floating-point value and places it in FRT. The integer is interpreted as a two's-complement 64-bit value. The result is an exact representation in the decimal floating-point format. FPSCR is updated if the integer is out of range for DFP.

integer_value ← FRB[0:63] (signed)
FRT ← convert_to_DFP(integer_value)
FPSCR ← updated based on conversion result


Summary: Converts a decimal floating-point number to a fixed-point integer.

The DFP operand in FRB is rounded to an integer value and placed into FRT in the 64-bit signed binary integer format. The sign of the result is the same as the sign of the source operand, except when the source operand is a NaN or a zero.

if 'dctfix' then
    FRT <- round(FRB)
else if 'dctfix.' then
    FRT <- round(FRB)
    CR1 <- result of comparison

FPSCR (FPRF, FR, FI, FX, VXSNAN, VXCVI, XX), CR1 (if Rc=1)

It is recommended that software pre-round the operand to a floating-point integral using drintx[q] or drintn[q] if a rounding mode other than the current rounding mode specified by DRN is needed.


Summary: Encodes a DFP number into BCD format.

Encodes a decimal floating-point number in FRB into Binary Coded Decimal (BCD) format and places the result in FRT. The sign control field S determines how the sign is encoded. This instruction handles conversion of the coefficient and exponent into BCD representation. FPSCR is updated based on invalid operations.

dfp_value ← FRB
sign ← extract_sign(dfp_value)
coefficient ← extract_coefficient(dfp_value)
exponent ← extract_exponent(dfp_value)
bcd_result ← encode_to_bcd(sign, coefficient, exponent, S)
FRT ← bcd_result
FPSCR ← updated based on encoding result

The denbcd instruction is used to convert a Binary-Coded Decimal (BCD) value into Data-Packed Decimal (DPD) format. Ensure that the input BCD value in FRB is correctly formatted and aligned as required by the instruction. This operation does not raise exceptions for valid inputs but may require careful handling of special cases like overflow or invalid data.


Summary: Converts a portion of the significand of a DFP operand to a signed or unsigned BCD number.

The rightmost 16 digits of the significand (32 digits for ddedpdq) is converted to an unsigned BCD number and the result is placed into FRT[p].

if 'ddedpd' then
    if SP = 0 then
        FRT <- unsigned BCD conversion of rightmost 16 digits of FRB[p]
    else if SP = 1 then
        FRT <- signed BCD conversion of rightmost 15 digits of FRB[p] with the same sign as FRB[p]
    end if

FPSCR, (FPRF, FX, VXCVI), FPSCR, (FR, set, to, 0), CR1, (if, Rc=1), CR0

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.


Summary: Combines a sign/coefficient from FRA and exponent from FRB.

Combines a sign and coefficient from FRA with an exponent from FRB to form a decimal floating-point result in FRT. FRA provides the mantissa/coefficient; FRB provides the exponent. The instruction reconstructs a DFP value from its components. FPSCR is updated if the result is invalid or out of range.

coefficient ← extract_mantissa(FRA)
Sign ← extract_sign(FRA)
exponent ← extract_exponent_field(FRB)
FRT ← compose_DFP(Sign, coefficient, exponent)
FPSCR ← updated based on composition result

The diex instruction is used to adjust the exponent of a decimal floating-point number by inserting the exponent from one operand (FRA) into another (FRB). Ensure that both operands are properly aligned and in the correct format to avoid exceptions. This operation requires FPSCR to manage rounding modes and exception flags.