Summary: Stores two registers if exclusive monitor matches.

Conditionally stores two consecutive 32-bit words from Wt1 and Wt2 to memory at addresses Xn and Xn+4 if the exclusive monitor for that address range is marked exclusive; writes the store status (0=success, 1=failure) to Ws. No condition flags are affected. AArch64-only instruction that interacts with the exclusive monitor and may generate exception faults.

address ← Xn
if ExclusiveMonitorMatch(address, DWORD) then
  [address, 4] ← Wt1[31:0]
  [address + 4, 4] ← Wt2[31:0]
  Ws ← 0
  ClearExclusiveMonitor(address)
else
  Ws ← 1


Summary: Subtracts extended register from register.

SUB <Wd|Wsp>, <Wn|Wsp>, <Wm> {, <extend> {#<amount>}}

Wn

First source / base 32-bit integer register

Wm

Second source / offset 32-bit integer register

Subtracts an extended 32-bit register value from a 32-bit register and writes the result to the destination register. Sets the N, Z, C, V condition flags based on the result. AArch64-only instruction; supports sign/zero extension of Wm with optional left shift (0-4).

offset ← ExtendValue(Wm, option, imm3)
result ← Wn - offset
Wd ← result[31:0]
N ← result[31]
Z ← (result == 0)
C ← (unsigned_result == result)
V ← SignedOverflow(Wn, offset, result)


Summary: Subtracts immediate from register.

SUB <Wd|Wsp>, <Wn|Wsp>, #<imm> {, lsl #<shift>}

Subtracts a 12-bit immediate value (optionally shifted left by 0 or 12 bits) from the 32-bit source register and writes the result to the destination register. The condition flags (N, Z, C, V) are not affected. This instruction executes in AArch64 state and requires no special privileges.


Summary: Subtracts shifted register from register.

SUB <Wd>, <Wn>, <Wm> {, <shift> #<amount>}

Subtracts the value in the second source register (optionally shifted) from the first source register and writes the result to the destination register. The shift can be LSL, LSR, ASR, or ROR by an amount specified in the immediate field. The condition flags (N, Z, C, V) are not affected. This instruction executes in AArch64 state and requires no special privileges.

shift_amount ← imm6; shifted_Wm ← ApplyShift(Wm, shift_type, shift_amount); Wd ← Wn - shifted_Wm


Summary: Subtracts extended register and updates flags.

SUBS <Wd>, <Wn|Wsp>, <Wm> {, <extend> {#<amount>}}

Subtracts an extended register (with optional shift) from the source register and updates all condition flags. The second operand is sign- or zero-extended based on the extend type before shifting. The N, Z, C, and V flags are set according to the result. This instruction executes in AArch64 state and requires no special privileges.

extended_Wm ← ExtendRegister(Wm, option); shifted_Wm ← extended_Wm << imm3; result ← Wn - shifted_Wm; Wd ← result; N ← result[31]; Z ← (result == 0); C ← BorrowFrom(Wn, shifted_Wm); V ← OverflowFrom(Wn, shifted_Wm, result)


Summary: Subtracts immediate and updates flags.

SUBS <Wd>, <Wn|Wsp>, #<imm> {, lsl #<shift>}

Subtracts a 12-bit immediate value (optionally shifted left by 0 or 12 bits) from the source register and updates all condition flags. The N, Z, C, and V flags are set according to the result. This instruction executes in AArch64 state and requires no special privileges.

imm_val ← (imm12 << (sh * 12)); result ← Wn - imm_val; Wd ← result; N ← result[31]; Z ← (result == 0); C ← BorrowFrom(Wn, imm_val); V ← OverflowFrom(Wn, imm_val, result)


Summary: Subtracts shifted register and updates flags.

SUBS <Wd>, <Wn>, <Wm> {, <shift> #<amount>}

Subtracts the value in the second source register (optionally shifted) from the first source register and updates all condition flags. The shift can be LSL, LSR, ASR, or ROR by an amount specified in the immediate field. The N, Z, C, and V flags are set according to the result. This instruction executes in AArch64 state and requires no special privileges.

shift_amount ← imm6; shifted_Wm ← ApplyShift(Wm, shift_type, shift_amount); result ← Wn - shifted_Wm; Wd ← result; N ← result[31]; Z ← (result == 0); C ← BorrowFrom(Wn, shifted_Wm); V ← OverflowFrom(Wn, shifted_Wm, result)


Summary: Causes a Supervisor Call exception (to EL1).

Generates a Supervisor Call exception, transitioning from the current privilege level to EL1 and saving the return address in ELR_EL1. The immediate is stored in the ESR_EL1 for handling software. AArch64-only exception-generating instruction; the immediate operand is conventionally used to identify the requested system service.

ELR_EL1 ← PC
ESR_EL1.ISS[15:0] ← imm16
ESR_EL1.EC ← 0b010001
PSTATE.DAIF ← PSTATE.DAIF OR 0b1111
PC ← ExceptionVectorAddress(EL1, SVC)


Summary: Executes a system instruction (cache/TLB maintenance).

Executes a system instruction that performs cache, TLB, or other system maintenance operations based on op1, Cn, Cm, and op2 fields. The optional Xt operand transfers data to/from a system register. This instruction is AArch64-only and typically requires EL1 or higher privilege level. No arithmetic flags are affected; execution may cause synchronization side effects.

IMPLEMENTATION_DEFINED system operation based on (op1, Cn, Cm, op2); if Xt is present then Xt ← system_register_value or system_register_value ← Xt


Summary: Branches if specified bit is 1.

Tests the bit at position imm in register Wt|Xt; if the bit is 1 (non-zero), branches to label. The bit position is specified by b5:imm14 (6-bit total index). This is an AArch64-only instruction. No arithmetic flags are modified by the test itself; the branch updates PC.

bit_index ← (b5 << 5) | imm14; if (Wt|Xt)[bit_index] == 1 then PC ← label


Summary: Branches if specified bit is 0.

Tests the bit at position imm in register Wt|Xt; if the bit is 0 (zero), branches to label. The bit position is specified by b5:imm14 (6-bit total index). This is an AArch64-only instruction. No arithmetic flags are modified by the test itself; the branch updates PC.

bit_index ← (b5 << 5) | imm14; if (Wt|Xt)[bit_index] == 0 then PC ← label


Summary: Extracts/Inserts bitfield (Zero Extend).

Extracts a bitfield from Wn (or Xn in 64-bit variant) and zero-extends it into Wd (or Xd). The bitfield is selected by rotating right by immr positions and then masking imms bits. No arithmetic flags are affected. This is AArch64-only and commonly used for zero-extension of bit ranges.

width ← size; elem ← (Wn >> immr) | (Wn << (width - immr)); mask ← (1 << (imms + 1)) - 1; Wd ← elem & mask; Wd[63:32] ← 0


Summary: Divides two unsigned registers.

Divides the unsigned 32-bit value in Wn by the unsigned 32-bit value in Wm, writing the quotient to Wd. Division by zero produces zero in Wd (no exception). This is AArch64-only. No arithmetic flags (N, Z, C, V) are affected.

if Wm == 0 then Wd ← 0 else Wd ← Wn / Wm


Summary: Multiplies two 32-bit regs, adds to 64-bit reg (Unsigned).

Multiplies the unsigned 32-bit values in Wn and Wm as an unsigned product (64-bit intermediate), then adds the 64-bit value in Xa, storing the 64-bit result in Xd. This is AArch64-only. No arithmetic flags are affected.


Summary: Calculates (Xa - (Wn * Wm)) (Unsigned 64-bit).

Multiplies the unsigned 32-bit values in Wn and Wm as an unsigned product (64-bit intermediate), then subtracts it from the 64-bit value in Xa, storing the 64-bit result in Xd. This is AArch64-only. No arithmetic flags are affected.


Summary: Multiplies two 64-bit registers, keeps high 64 bits (Unsigned).

Xn

First source / base 64-bit integer register

Xm

Second source / offset 64-bit integer register

Multiplies the unsigned 64-bit values in Xn and Xm, treating both as unsigned integers, and stores the high 64 bits of the 128-bit product in Xd. This is AArch64-only. No arithmetic flags are affected.


Vector Load Multiple (3-Element Structure)

Summary: Loads three-element structures (e.g., RGB) and de-interleaves them into three registers.

Rn

First source / base general-purpose register

Loads three-element interleaved structures from memory and de-interleaves them into three consecutive NEON registers. The instruction reads (3 × element_size × 8) bits from the address in Rn, distributing elements across three registers. Condition flags (N, Z, C, V) are unaffected. Execution is restricted to A32/T32 with NEON extension; post-index writeback to Rn is optional.

address ← Rn
for i = 0 to 7 do
  element_size_bits ← size_in_bits(size)
  Vd[i] ← [address + (i * element_size_bits / 8)]
  Vd+1[i] ← [address + (i * element_size_bits / 8) + (element_size_bits / 8)]
  Vd+2[i] ← [address + (i * element_size_bits / 8) + (2 * element_size_bits / 8)]
if (writeback) then
  Rn ← Rn + (3 * 8 * element_size_bits / 8)


Vector Load Multiple (4-Element Structure)

Summary: Loads four-element structures (e.g., RGBA) and de-interleaves them into four registers.

Loads four-element interleaved structures from memory and de-interleaves them into four consecutive NEON registers. The instruction reads (4 × element_size × 8) bits from the address in Rn, distributing elements across four registers. Condition flags (N, Z, C, V) are unaffected. Execution is restricted to A32/T32 with NEON extension; post-index writeback to Rn is optional.

address ← Rn
for i = 0 to 7 do
  element_size_bits ← size_in_bits(size)
  Vd[i] ← [address + (i * element_size_bits / 8)]
  Vd+1[i] ← [address + (i * element_size_bits / 8) + (element_size_bits / 8)]
  Vd+2[i] ← [address + (i * element_size_bits / 8) + (2 * element_size_bits / 8)]
  Vd+3[i] ← [address + (i * element_size_bits / 8) + (3 * element_size_bits / 8)]
if (writeback) then
  Rn ← Rn + (4 * 8 * element_size_bits / 8)


Vector Store Multiple (3-Element Structure)

Summary: Interleaves and stores three registers into memory (e.g., RGB).

Interleaves and stores three NEON registers into memory as three-element structures. The instruction reads from three consecutive registers and interleaves their elements before writing (3 × element_size × 8) bits to the address in Rn. Condition flags (N, Z, C, V) are unaffected. Execution is restricted to A32/T32 with NEON extension; post-index writeback to Rn is optional.

address ← Rn
for i = 0 to 7 do
  element_size_bits ← size_in_bits(size)
  [address + (i * element_size_bits / 8)] ← Vd[i]
  [address + (i * element_size_bits / 8) + (element_size_bits / 8)] ← Vd+1[i]
  [address + (i * element_size_bits / 8) + (2 * element_size_bits / 8)] ← Vd+2[i]
if (writeback) then
  Rn ← Rn + (3 * 8 * element_size_bits / 8)


Vector Store Multiple (4-Element Structure)

Summary: Interleaves and stores four registers into memory (e.g., RGBA).

111101000 | D | 0 | 0 | Rn | Vd | itype | size | align | Rm

Interleaves and stores four NEON registers into memory as four-element structures. The instruction reads from four consecutive registers and interleaves their elements before writing (4 × element_size × 8) bits to the address in Rn. Condition flags (N, Z, C, V) are unaffected. Execution is restricted to A32/T32 with NEON extension; post-index writeback to Rn is optional.

address ← Rn
for i = 0 to 7 do
  element_size_bits ← size_in_bits(size)
  [address + (i * element_size_bits / 8)] ← Vd[i]
  [address + (i * element_size_bits / 8) + (element_size_bits / 8)] ← Vd+1[i]
  [address + (i * element_size_bits / 8) + (2 * element_size_bits / 8)] ← Vd+2[i]
  [address + (i * element_size_bits / 8) + (3 * element_size_bits / 8)] ← Vd+3[i]
if (writeback) then
  Rn ← Rn + (4 * 8 * element_size_bits / 8)


Summary: Inserts elements into a vector using a table lookup.

Performs a table lookup and extension: for each byte index in Dm, looks up the corresponding byte in the table (1-4 registers starting at Vn) and inserts it into the corresponding position in Dd, leaving unmapped indices unchanged in Dd. Condition flags (N, Z, C, V) are unaffected. Execution is restricted to A32/T32 with NEON extension; out-of-range indices preserve the original element in Dd.

for i = 0 to 15 do
  index ← Dm.byte[i]
  if (index < (len + 1) * 16) then
    table_reg ← Vn + (index / 16)
    element_offset ← index mod 16
    Dd.byte[i] ← [table_reg].byte[element_offset]
  else
    Dd.byte[i] ← Dd.byte[i]


Summary: Computes Vd = Vd + (Vn * Vm) with single rounding.

Fused multiply-accumulate: computes Qd = Qd + (Qn × Qm) on 32-bit floating-point elements with a single rounding operation, improving precision over separate multiply and add. Condition flags (N, Z, C, V) are unaffected. Execution is restricted to A32/T32 with VFPv4 (NEON) extension; operates on 128-bit quad registers.

for i = 0 to 3 do
  Qd[i] ← round_to_nearest(Qd[i] + (Qn[i] × Qm[i]))


Summary: Computes Vd = Vd - (Vn * Vm) with single rounding.

Fused multiply-subtract: computes Qd = Qd - (Qn × Qm) on 32-bit floating-point elements with a single rounding operation, improving precision over separate multiply and subtract. Condition flags (N, Z, C, V) are unaffected. Execution is restricted to A32/T32 with VFPv4 (NEON) extension; operates on 128-bit quad registers.

for i = 0 to 3 do
  Qd[i] ← round_to_nearest(Qd[i] - (Qn[i] × Qm[i]))


Vector Fused Negated Multiply Accumulate

Summary: Computes Vd = Vd - (Vn * Vm).

Sd

Destination 32-bit floating-point register

Sn

First source 32-bit floating-point register

Sm

Second source 32-bit floating-point register

Fused negated multiply-accumulate: computes Sd = Sd - (Sn × Sm) on 32-bit floating-point values with a single rounding operation. Condition flags (N, Z, C, V) are unaffected. Execution is restricted to A32/T32 with VFPv4 (scalar floating-point) extension; operates on 32-bit single-precision registers.


Summary: Computes Vd = -Vd + (Vn * Vm).

Vector Fused Negated Multiply Subtract computes the negation of the destination plus the product of two operands: Sd = -Sd + (Sn * Sm). This is a single fused operation that performs multiplication and subtraction with only one rounding step, improving precision over separate operations. The instruction is available in VFPv4 and operates on 32-bit single-precision floating-point values. Condition flags (N, Z, C, V) are not affected; floating-point exception flags may be set based on the result.


Summary: Newton-Raphson step for reciprocal refinement: (2 - Vn * Vm).

Vector Reciprocal Step performs a Newton-Raphson step for reciprocal refinement on 32-bit floating-point SIMD elements: Qd = 2.0 - (Qn * Qm). This operation is typically used iteratively to refine reciprocal approximations. The instruction operates on 128-bit SIMD registers, processing multiple 32-bit float elements in parallel. No integer flags are affected; floating-point exception flags may be set based on the results.

for i = 0 to 3
  Qd[i] ← 2.0 - (Qn[i] * Qm[i])


Summary: Newton-Raphson step for reciprocal sqrt refinement: (3 - Vn * Vm) / 2.

Vector Reciprocal Square Root Step performs a Newton-Raphson step for reciprocal square root refinement on 32-bit floating-point SIMD elements: Qd = (3.0 - (Qn * Qm)) / 2.0. This operation is typically used iteratively to refine reciprocal square root approximations. The instruction operates on 128-bit SIMD registers, processing multiple 32-bit float elements in parallel. No integer flags are affected; floating-point exception flags may be set based on the results.


Summary: Adds adjacent pairs and accumulates into wide destination.

Vector Pairwise Add and Accumulate Long adds adjacent pairs of elements from the source register and accumulates the results into the destination register, which is widened. The data type and element size are specified by the size field; both signed and unsigned variants exist. No condition flags are affected. The destination elements are wider than the source elements to accommodate the accumulated sums.

for i = 0 to (pairs_in_Qm - 1)
  Qd[i] ← Qd[i] + (Qm[2*i] + Qm[2*i+1])


Summary: Adds adjacent pairs and produces wide result.

Vector Pairwise Add Long adds adjacent pairs of elements from the source register and produces a widened result in the destination register. The data type and element size are specified by the size field; both signed and unsigned variants exist. No condition flags are affected. The destination elements are wider than the source elements to accommodate the pair sums.

for i = 0 to (pairs_in_Qm - 1)
  Qd[i] ← Qm[2*i] + Qm[2*i+1]


Summary: Swaps the contents of two vectors.

Vector Swap exchanges the entire contents of two SIMD registers. The register sizes (64-bit or 128-bit) are determined by the Q bit in the encoding. This is a data movement operation with no arithmetic or comparison; no condition flags are affected.


Summary: Returns larger value, handling NaNs per IEEE 754-2008.

Vector Maximum Number returns the larger of two 32-bit floating-point values for each lane, handling NaN operands according to IEEE 754-2008 semantics (if one operand is NaN, the non-NaN value is returned). The instruction operates on 128-bit SIMD registers, processing multiple 32-bit float elements in parallel. No integer flags are affected; floating-point exception flags may be set based on the results.

for i = 0 to 3
  if isNaN(Qn[i]) and not isNaN(Qm[i])
    Qd[i] ← Qm[i]
  else if isNaN(Qm[i]) and not isNaN(Qn[i])
    Qd[i] ← Qn[i]
  else
    Qd[i] ← max(Qn[i], Qm[i])


Summary: Returns smaller value, handling NaNs per IEEE 754-2008.

Vector Minimum Number returns the smaller of two 32-bit floating-point values for each lane, handling NaN operands according to IEEE 754-2008 semantics (if one operand is NaN, the non-NaN value is returned). The instruction operates on 128-bit SIMD registers, processing multiple 32-bit float elements in parallel. No integer flags are affected; floating-point exception flags may be set based on the results.

for i = 0 to 3
  if isNaN(Qn[i]) and not isNaN(Qm[i])
    Qd[i] ← Qm[i]
  else if isNaN(Qm[i]) and not isNaN(Qn[i])
    Qd[i] ← Qn[i]
  else
    Qd[i] ← min(Qn[i], Qm[i])


Summary: Converts float to integer, rounding to nearest.

Converts each floating-point element in the source Q register to a signed or unsigned integer, rounding towards positive infinity (towards +∞), and writes the results to the destination Q register. This is a vector operation where each lane is independently converted. No NEON flags are modified; results follow IEEE 754 rounding semantics. This instruction requires NEON support and executes in AArch32 state (T32/A32).

for i ← 0 to (128 / element_width) - 1 do; element ← Qm[i]; integer_result ← ConvertToInteger(element, RoundTowardsPlusInfinity, unsigned); Qd[i] ← integer_result; end


Vector Convert to Integer (Nearest Even)

Summary: Converts float to integer, rounding to nearest even.

Converts each floating-point element in the source Q register to a signed or unsigned integer, rounding to nearest even (banker's rounding), and writes the results to the destination Q register. This is a vector operation where each lane is independently converted. No NEON flags are modified; results follow IEEE 754 rounding semantics. This instruction requires NEON support and executes in AArch32 state (T32/A32).

for i ← 0 to (128 / element_width) - 1 do; element ← Qm[i]; integer_result ← ConvertToInteger(element, RoundToNearestEven, unsigned); Qd[i] ← integer_result; end


Vector Convert to Integer (Plus Infinity)

Summary: Converts float to integer, rounding towards +Inf (Ceil).

Converts each floating-point element in the source Q register to a signed or unsigned integer, rounding towards positive infinity (ceiling), and writes the results to the destination Q register. This is a vector operation where each lane is independently converted. No NEON flags are modified; results follow IEEE 754 rounding semantics. This instruction requires NEON support and executes in AArch32 state (T32/A32).


Vector Convert to Integer (Minus Infinity)

Summary: Converts float to integer, rounding towards -Inf (Floor).

Converts floating-point values in a NEON vector to signed integers, rounding towards negative infinity (floor). This is a NEON SIMD instruction that operates on 32-bit floating-point elements and produces integer results. No condition flags are affected by this instruction.

for i = 0 to elements-1
  Qd[i] ← RoundTowardsMinusInfinity(Qm[i])


Summary: Rounds float to integral float (Nearest).

Rounds each 32-bit floating-point element in the source vector to the nearest integer value, using round-to-nearest (ties away from zero) rounding mode, and writes the result as a floating-point value to the destination vector. This instruction does not modify the condition flags. Available in A32/T32 with NEON extension.

for i = 0 to 3
  Qd[i] ← RoundToNearest(Qm[i])
end for


Vector Round Floating-Point (Nearest Even)

Summary: Rounds float to integral float (Nearest Even).

Rounds each 32-bit floating-point element in the source vector to the nearest integer value, using round-to-nearest-even (banker's rounding) rounding mode, and writes the result as a floating-point value to the destination vector. This instruction does not modify the condition flags. Available in A32/T32 with NEON extension.

for i = 0 to 3
  Qd[i] ← RoundToNearestEven(Qm[i])
end for


Summary: Rounds float to integral float (Towards Zero).

Rounds each 32-bit floating-point element in the source vector towards zero to an integer value, and writes the result as a floating-point value to the destination vector. This instruction does not modify the condition flags. Available in A32/T32 with NEON extension.

for i = 0 to 3
  Qd[i] ← RoundTowardsZero(Qm[i])
end for


Summary: Selects elements from Dn or Dm based on condition flags (predicated VFP).

Conditionally selects the 32-bit floating-point value from either Sn or Sm based on the current state of the condition flags and writes it to Sd. The condition code (cc) embedded in the instruction determines which flag combination is tested. This instruction does not modify condition flags. Available in A32/T32 with VFP extension.

if ConditionHolds(cc) then
  Sd ← Sn
else
  Sd ← Sm
end if


Summary: Performs one round of AES encryption (AArch32).

Performs a single round of AES encryption (SubBytes, ShiftRows, MixColumns, and AddRoundKey stages) on the 128-bit data block in Qd using the 128-bit round key in Qm. The result is written back to Qd. This instruction does not modify the condition flags. Available in A32/T32 with Crypto extension and requires AES feature.

state ← Qd
round_key ← Qm
state ← SubBytes(state)
state ← ShiftRows(state)
state ← MixColumns(state)
state ← AddRoundKey(state, round_key)
Qd ← state


Summary: Performs one round of AES decryption (AArch32).

Performs a single round of AES decryption (InvShiftRows, InvSubBytes, AddRoundKey, and InvMixColumns stages) on the 128-bit data block in Qd using the 128-bit round key in Qm. The result is written back to Qd. This instruction does not modify the condition flags. Available in A32/T32 with Crypto extension and requires AES feature.

state ← Qd
round_key ← Qm
state ← InvShiftRows(state)
state ← InvSubBytes(state)
state ← AddRoundKey(state, round_key)
state ← InvMixColumns(state)
Qd ← state


Summary: AES Mix Columns transformation.

Applies the AES MixColumns (forward) transformation to each column of the 128-bit state in Qm and writes the result to Qd. This transformation is equivalent to one round's MixColumns operation and is used in key expansion during AES encryption. This instruction does not modify the condition flags. Available in A32/T32 with Crypto extension and requires AES feature.


Summary: AES Inverse Mix Columns transformation.

Applies the AES Inverse MixColumns (inverse) transformation to each column of the 128-bit state in Qm and writes the result to Qd. This transformation reverses the forward MixColumns operation and is used in equivalent inverse cipher key expansion during AES decryption. This instruction does not modify the condition flags. Available in A32/T32 with Crypto extension and requires AES feature.


Summary: SHA1 hash update (Choose).

SHA1 Choose function: updates SHA1 hash state by computing the Choose operation on 32-bit elements. This instruction performs a cryptographic hash round step specific to SHA1 and is part of the ARM Cryptographic Extension. No condition flags are affected. Available in A32 and T32 with Crypto extension support.


Summary: Updates SHA1 hash state.

SHA1 Hash Update: performs the final hash update step in the SHA1 algorithm by processing the hash state. This instruction computes the SHA1 hash finalization on four 32-bit words in parallel. No condition flags are affected. Available in A32 and T32 with Crypto extension support.


Summary: SHA1 hash update (Majority).

SHA1 Majority function: updates SHA1 hash state by computing the Majority operation on 32-bit elements. This instruction performs a cryptographic hash round step specific to SHA1 and is part of the ARM Cryptographic Extension. No condition flags are affected. Available in A32 and T32 with Crypto extension support.


Summary: SHA1 hash update (Parity).

SHA1 Parity function: updates SHA1 hash state by computing the Parity operation on 32-bit elements. This instruction performs a cryptographic hash round step specific to SHA1 and is part of the ARM Cryptographic Extension. No condition flags are affected. Available in A32 and T32 with Crypto extension support.


Summary: CRC32 checksum update (Byte).

CRC32 Checksum Update (Byte): accumulates a 32-bit CRC checksum by processing a single byte from the input. Rd is updated with CRC32(Rn, Rm[7:0]) using the standard CRC32 polynomial. No condition flags are affected. Subject to condition code in A32; available in A32 only with CRC extension.


Summary: CRC32 checksum update (Word).

CRC32 Checksum Update (Word): accumulates a 32-bit CRC checksum by processing a full 32-bit word from the input. Rd is updated with CRC32(Rn, Rm[31:0]) using the standard CRC32 polynomial. No condition flags are affected. Subject to condition code in A32; available in A32 only with CRC extension.


Summary: Calls the Secure Monitor (EL3).

Secure Monitor Call: a synchronous exception that transitions execution to the Secure Monitor at EL3 to handle a secure service request. The immediate value encodes the SMC ID for the handler. This instruction requires Secure state; execution in Non-secure state is subject to the SMCNC trap. Subject to condition code in A32.

exception_taken ← 'SMC'
ELR_EL3 ← PC + 4
SPSR_EL3 ← CPSR
CPSR.M ← '10110' (Monitor mode)
PC ← VECTOR_SMC


Summary: Loads a word with Acquire semantics.

Rt

Transfer general-purpose register (load/store)

Load Acquire: loads a 32-bit word from memory with Acquire semantics, ensuring memory synchronization and preventing subsequent memory operations from being reordered before this load. The address is computed from Rn (no offset). No condition flags are affected. Subject to condition code in A32; available in A32 with Atomic extension.


Summary: Stores a word with Release semantics.

Stores a 32-bit word to memory with Release semantics, ensuring all prior memory operations are visible to other observers before the store completes. No condition flags are affected. This is an A32-only instruction that provides atomic release semantics for synchronization.

address ← Rn
MemoryOrder ← Release
[address] ← Rt[31:0]
DRAIN_RELEASE_BARRIER()


Summary: Loads a word with Acquire Exclusive semantics.

Loads a 32-bit word from memory with Acquire Exclusive semantics, allowing subsequent memory operations to observe earlier loads and stores. The processor acquires exclusive access to the address for potential paired store-exclusive. No condition flags are affected. This is an A32-only instruction.

address ← Rn
MemoryOrder ← Acquire
Rt ← [address]
SET_EXCLUSIVE_MONITOR(address)
DRAIN_ACQUIRE_BARRIER()


Summary: Stores a word with Release Exclusive semantics.

Atomically stores a 32-bit word to memory with Release semantics and exclusive access, writing status to Rd. This A32 instruction is used for inter-processor synchronization and memory ordering. The status register Rd is written with 0 on success or 1 on failure; no condition flags are affected.

if ExclusiveAccess[Rn] then
  [Rn] ← Rt
  Rd ← 0
  ClearExclusiveAccess()
else
  Rd ← 1


Summary: Computes dot product of BFloat16 elements, accumulating to Float32 (NEON).

Computes the dot product of BFloat16 pairs from two NEON vectors and accumulates the Float32 result into the destination vector. Requires FEAT_BF16. No flags are affected. Operates on 128-bit NEON vectors with BFloat16 source elements.

for i = 0 to elements-1 do
  product ← BF16_to_F32(Vn[2*i]) × BF16_to_F32(Vm[2*i]) +
            BF16_to_F32(Vn[2*i+1]) × BF16_to_F32(Vm[2*i+1])
  Vd[i] ← Vd[i] + product
end for


BFloat16 Matrix Multiply-Accumulate (NEON)

Summary: Performs 2x2 matrix multiplication on BFloat16 tiles (NEON).

Performs a 2×2 matrix multiply-accumulate operation on BFloat16 tiles, accumulating the result into Float32 elements of the destination vector. Requires FEAT_BF16. No flags are affected. Operates on 128-bit NEON vectors.

for i = 0 to 1 do
  for j = 0 to 1 do
    sum ← Vd[i*2+j]
    for k = 0 to 1 do
      sum ← sum + (BF16_to_F32(Vn[i*2+k]) × BF16_to_F32(Vm[k*2+j]))
    end for
    Vd[i*2+j] ← sum
  end for
end for


Summary: Converts Float32 to BFloat16 (Lower Half).

Converts Float32 values from the first half of the source vector to BFloat16 format and stores them in the lower half of the destination vector, leaving the upper half unchanged. Requires FEAT_BF16. No flags are affected. Operates on NEON vectors.

for i = 0 to 3 do
  Vd[i] ← F32_to_BF16(Vn[i])
end for
Vd[8:4] ← Vd[8:4]  // Upper half unchanged


Summary: Converts Float32 to BFloat16 (Upper Half).

Converts Float32 values from the source vector to BFloat16 format and stores them in the upper half of the destination vector, leaving the lower half unchanged. Requires FEAT_BF16. No flags are affected. Operates on NEON vectors.

for i = 0 to 3 do
  Vd[i+4] ← F32_to_BF16(Vn[i])
end for
Vd[3:0] ← Vd[3:0]  // Lower half unchanged


Signed Integer Matrix Multiply-Accumulate (NEON)

Summary: Performs 2x2 matrix multiplication on Signed Int8 tiles.

Performs a 2×2 signed integer matrix multiply-accumulate operation on Int8 tiles, accumulating the result into Int32 elements of the destination vector. Requires FEAT_I8MM. No flags are affected. Operates on 128-bit NEON vectors.

for i = 0 to 1 do
  for j = 0 to 1 do
    sum ← Vd[i*4+j*4 : i*4+j*4+31]
    for k = 0 to 1 do
      sum ← sum + (SignExtend(Vn[i*4+k*4 : i*4+k*4+7]) × SignExtend(Vm[k*4+j*4 : k*4+j*4+7]))
    end for
    Vd[i*4+j*4 : i*4+j*4+31] ← sum
  end for
end for


Unsigned Integer Matrix Multiply-Accumulate (NEON)

Summary: Performs 2x2 matrix multiplication on Unsigned Int8 tiles.

Performs a 2×2 unsigned integer matrix multiply-accumulate operation on Int8 tiles, accumulating the result into Int32 elements of the destination vector. Requires FEAT_I8MM. No flags are affected. Operates on 128-bit NEON vectors.

for i = 0 to 1 do
  for j = 0 to 1 do
    sum ← Vd[i*4+j*4 : i*4+j*4+31]
    for k = 0 to 1 do
      sum ← sum + (ZeroExtend(Vn[i*4+k*4 : i*4+k*4+7]) × ZeroExtend(Vm[k*4+j*4 : k*4+j*4+7]))
    end for
    Vd[i*4+j*4 : i*4+j*4+31] ← sum
  end for
end for


Unsigned-Signed Matrix Multiply-Accumulate (NEON)

Summary: Matrix multiply Unsigned Int8 with Signed Int8.

Performs an unsigned-signed 8-bit integer matrix multiply-accumulate operation, multiplying unsigned Int8 elements from Vn with signed Int8 elements from Vm and accumulating the results into Vd. This instruction operates on 128-bit NEON vectors and requires the FEAT_I8MM (Advanced SIMD and Floating-point Extension 2) architectural feature. No condition flags are affected; this is an AArch64-only instruction.

for e = 0 to (128 / 32) - 1
  Vd[e] ← Vd[e] + (Vn[4×e:4×e+3] × Vm[4×e:4×e+3])
  // Each element is 32-bit int32, products of 4×uint8 × 4×sint8


Summary: Dot product of Unsigned Int8 and Signed Int8.

Performs an unsigned-signed 8-bit integer dot product, multiplying unsigned Int8 elements from Vn with signed Int8 elements from Vm and accumulating into 32-bit integer lanes of Vd. This instruction operates on 128-bit NEON vectors and requires the FEAT_I8MM architectural feature. No condition flags are affected; this is an AArch64-only instruction.

for e = 0 to (128 / 32) - 1
  Vd[e] ← Vd[e] + (uint(Vn[4×e]) × sint(Vm[4×e]) +
                   uint(Vn[4×e+1]) × sint(Vm[4×e+1]) +
                   uint(Vn[4×e+2]) × sint(Vm[4×e+2]) +
                   uint(Vn[4×e+3]) × sint(Vm[4×e+3]))
  // Each Vd[e] is a 32-bit signed result


Summary: Dot product of Signed Int8 and Unsigned Int8 (Indexed).

Performs a signed-unsigned 8-bit integer dot product with an indexed operand, multiplying signed Int8 elements from Vn with unsigned Int8 elements from a specific 32-bit lane of Vm and accumulating into 32-bit integer lanes of Vd. This instruction operates on 128-bit NEON vectors and requires the FEAT_I8MM architectural feature. No condition flags are affected; this is an AArch64-only instruction.

// Vm is indexed; extract the 32-bit lane containing 4 unsigned Int8 values
for e = 0 to (128 / 32) - 1
  lane_data ← Vm[32×index + 0 : 32×index + 31]
  Vd[e] ← Vd[e] + (sint(Vn[4×e]) × uint(lane_data[7:0]) +
                   sint(Vn[4×e+1]) × uint(lane_data[15:8]) +
                   sint(Vn[4×e+2]) × uint(lane_data[23:16]) +
                   sint(Vn[4×e+3]) × uint(lane_data[31:24]))
  // Each Vd[e] is a 32-bit signed result


Move to Two Registers from System Register (128-bit)

Summary: Reads a 128-bit system register into two general-purpose registers.

Reads a 128-bit system register into two consecutive 64-bit general-purpose registers (Xt and Xt+1). This is an AArch64-only instruction requiring FEAT_SYSREG128 and may require elevated privilege depending on the system register being accessed. No condition flags are affected.

Xt ← SYSREG[sysreg][63:0]
Xt+1 ← SYSREG[sysreg][127:64]


Move Two Registers to System Register (128-bit)

Summary: Writes two general-purpose registers into a 128-bit system register.

Writes two consecutive 64-bit general-purpose registers (Xt and Xt+1) into a 128-bit system register. This is an AArch64-only instruction requiring FEAT_SYSREG128 and may require elevated privilege depending on the system register being accessed. No condition flags are affected.

SYSREG[sysreg][63:0] ← Xt
SYSREG[sysreg][127:64] ← Xt+1


Summary: Inserts a random Allocation Tag into a pointer (MTE).

Inserts a randomly selected Allocation Tag into a pointer held in Xn or SP, optionally excluding tags specified by a mask in Xm, and stores the result in Xd or SP. This instruction is only available in AArch64 and requires the MTE (Memory Tagging Extension) feature. The random tag selection is unpredictable from software perspective; no condition flags are affected.

if Xm is not present then
  exclude_mask ← 0x0000000000000000
else
  exclude_mask ← Xm
tag ← random_tag_not_in(exclude_mask)
Xd ← (Xn & ~0xF000000000000000) | (tag << 56)


Summary: Calculates a mask of excluded tags (MTE).

Calculates the intersection of an Allocation Tag mask (tags excluded from Xm) with tags that are NOT present in the pointer Xn, returning a 16-bit mask of valid alternative tags in Xd. This instruction is only available in AArch64 and requires the MTE feature. No condition flags are affected.

ptr_tag ← (Xn >> 56) & 0xF
exclude_mask ← Xm & 0xFFFF
valid_tags ← ~exclude_mask & 0xFFFF
// Return mask of tags that are both valid (not excluded) and different from current tag
Xd ← valid_tags & ~(1 << ptr_tag)


Summary: Loads the Allocation Tag from memory.

Xt

Transfer 64-bit integer register (load/store)

Loads the Allocation Tag from a 16-byte granule in memory at address [Xn + simm] and places it into the tag field (bits [59:56]) of Xt, with the lower 56 bits zeroed. This instruction is only available in AArch64 and requires the MTE feature. The simm9 immediate is scaled by 16 (granule size). No condition flags are affected.

address ← Xn + (simm << 4)  // simm is a signed 9-bit value, scaled by 16
memory_tag ← load_tag_from_memory(address)
Xt ← (memory_tag << 56) & 0xF000000000000000


Summary: Stores the Allocation Tag to memory.

Stores the Allocation Tag from Xt (bits [59:56]) into the tag storage of a 16-byte granule at address [Xn + simm]. This instruction is only available in AArch64 and requires the MTE feature. The simm9 immediate is scaled by 16. Data in the granule is not modified. No condition flags are affected.

address ← Xn + (simm << 4)  // simm is a signed 9-bit value, scaled by 16
tag_to_store ← (Xt >> 56) & 0xF
store_tag_to_memory(address, tag_to_store)


Summary: Stores the Allocation Tag and zeros the data granule.

Stores the Allocation Tag from Xt (bits [59:56]) into tag storage at address [Xn + simm] and simultaneously zeros all 16 bytes of the data granule at that address. This instruction is only available in AArch64 and requires the MTE feature. The simm9 immediate is scaled by 16. No condition flags are affected; this is a combined tag-write and memory-zero operation.

address ← Xn + (simm << 4)  // simm is a signed 9-bit value, scaled by 16
tag_to_store ← (Xt >> 56) & 0xF
store_tag_to_memory(address, tag_to_store)
for i = 0 to 15
  memory[address + i] ← 0


Summary: Stores the Allocation Tag to two memory granules.

Stores the Allocation Tag from Xt to two consecutive 16-byte memory granules at [Xn + offset]. The offset is scaled by 16. Both granules receive the same tag. No condition flags are affected. AArch64-only; requires MTE extension.

address ← Xn + (SignExtend(imm9, 9) << 4)
tag ← GetAllocationTag(Xt)
memory[address] ← memory[address] with tag set to tag
memory[address + 16] ← memory[address + 16] with tag set to tag


Summary: Stores Tag and two 64-bit data values.

Stores the Allocation Tag to a 16-byte memory address and simultaneously stores two 64-bit values from Xt and Xt2 (the pair register following Xt). The tag is derived from Xt, and the offset is scaled by 16. This instruction requires MTE support, does not modify the condition flags, and operates only in AArch64 execution state.

address ← (Xn | SP) + (simm7 << 4)
tag ← Xt[3:0]
memory[address:address+7] ← Xt[63:0]
memory[address+8:address+15] ← Xt2[63:0]
memory[address][3:0] ← tag


Summary: Subtracts pointers ignoring Tags.

Subtracts the pointer in Xm from the pointer in Xn, removing any Allocation Tags from both operands before performing the subtraction. The result is stored in Xd. This instruction does not modify the condition flags and operates only in AArch64 execution state with MTE support.


Summary: Signs a pointer in Xd using Key A and modifier Xm (or SP).

Signs the pointer in Xd using the Instruction key A and a modifier from Xn or SP, storing the Pointer Authentication Code (PAC) in the high bits of Xd. The instruction does not modify the condition flags and operates only in AArch64 execution state with PAC support. The operation is implementation-defined; a PACIA PACIASP variant uses SP as the modifier when Xn is omitted.

modifier ← Xn | SP
Xd ← AddPAC(Xd, modifier, key_a, instruction_key)


Summary: Signs a pointer in Xd using Key B.

Signs the pointer in Xd using the Instruction key B and a modifier from Xn or SP, storing the Pointer Authentication Code (PAC) in the high bits of Xd. The instruction does not modify the condition flags and operates only in AArch64 execution state with PAC support. The operation is implementation-defined; a PACIB PACIBSP variant uses SP as the modifier when Xn is omitted.

modifier ← Xn | SP
Xd ← AddPAC(Xd, modifier, key_b, instruction_key)


Summary: Signs a data pointer using Key A.

Signs the data pointer in Xd using the Data key A and a modifier from Xn or SP, storing the Pointer Authentication Code (PAC) in the high bits of Xd. The instruction does not modify the condition flags and operates only in AArch64 execution state with PAC support. The operation is implementation-defined and typically used for signing data pointers rather than instruction pointers.

modifier ← Xn | SP
Xd ← AddPAC(Xd, modifier, key_a, data_key)


Summary: Signs a data pointer using Key B.

Signs the data pointer in Xd using the Data key B and a modifier from Xn or SP, storing the Pointer Authentication Code (PAC) in the high bits of Xd. The instruction does not modify the condition flags and operates only in AArch64 execution state with PAC support. The operation is implementation-defined and typically used for signing data pointers rather than instruction pointers.

modifier ← Xn | SP
Xd ← AddPAC(Xd, modifier, key_b, data_key)


Summary: Authenticates a pointer signed with Key A. Corrupts pointer if failed.

Authenticates a 64-bit pointer in Xd using Key A and a modifier from Xn or SP. If authentication fails, the pointer is corrupted with a known bit pattern. This instruction is AArch64-only and requires the PAC (Pointer Authentication Code) extension. It does not affect the condition flags (N, Z, C, V) but may generate an exception if executed in an inappropriate context.

authenticated_pointer ← AuthenticatePointer(Xd, Xn, KeyA)
if authentication_fails then
  Xd ← corrupted_value
else
  Xd ← authenticated_pointer
end if


Summary: Authenticates a pointer signed with Key B.

Authenticates a 64-bit pointer in Xd using Key B and a modifier from Xn or SP. If authentication fails, the pointer is corrupted with a known bit pattern. This instruction is AArch64-only and requires the PAC (Pointer Authentication Code) extension. It does not affect the condition flags (N, Z, C, V) but may generate an exception if executed in an inappropriate context.

authenticated_pointer ← AuthenticatePointer(Xd, Xn, KeyB)
if authentication_fails then
  Xd ← corrupted_value
else
  Xd ← authenticated_pointer
end if


Strip Pointer Authentication Code (Inst)

Summary: Removes the PAC signature from an instruction pointer.

Strips the Pointer Authentication Code from a 64-bit instruction pointer in Xd without verifying the signature. This instruction is AArch64-only and requires the PAC extension. The condition flags (N, Z, C, V) are not affected, and the operation is not privileged.


Strip Pointer Authentication Code (Data)

Summary: Removes the PAC signature from a data pointer.

Strips the Pointer Authentication Code from a 64-bit data pointer in Xd without verifying the signature. This instruction is AArch64-only and requires the PAC extension. The condition flags (N, Z, C, V) are not affected, and the operation is not privileged.


Summary: Loads a value, authenticating the address with Key A.

Loads a 64-bit value from memory using an address authenticated with Pointer Authentication Code (PAC) using Key A. The address is computed from a base register and a signed 9-bit immediate offset. This AArch64-only instruction requires PAC support and will generate an Authentication Failure exception if authentication fails; no condition flags are affected.

address ← Xn|SP + (simm9 << 3)
authenticated_address ← AuthenticateAddressA(address)
Xt ← [authenticated_address]


Summary: Loads a value, authenticating the address with Key B.

Loads a 64-bit value from memory using an address authenticated with Pointer Authentication Code (PAC) using Key B. The address is computed from a base register and a signed 9-bit immediate offset. This AArch64-only instruction requires PAC support and will generate an Authentication Failure exception if authentication fails; no condition flags are affected.

address ← Xn|SP + (simm9 << 3)
authenticated_address ← AuthenticateAddressB(address)
Xt ← [authenticated_address]


Summary: Marks a valid target for indirect branches (Guard against JOP/ROP).

Marks a valid branch target for indirect branch instructions, providing defense against Jump-Oriented Programming (JOP) and Return-Oriented Programming (ROP) attacks. This instruction is AArch64-only and requires the BTI (Branch Target Identification) extension. It does not affect condition flags and acts as a hint; execution continues to the next instruction.

if not_valid_branch_target and branch_target_enforcement_enabled then
  GenerateException(BTYPE_mismatch)
else
  NOP
end if


Summary: Reads a random number from hardware entropy source.

Reads a 64-bit random number from the system's hardware entropy source and writes it to Xt. This instruction is AArch64-only and requires the FEAT_RNG extension. It does not modify condition flags and may set the C flag to indicate failure (entropy unavailable), depending on implementation.

Xt ← HardwareRandomNumber()
if entropy_available then
  C ← 0
else
  C ← 1
end if


Summary: Reads a random number and requests reseed.

Reads a 64-bit random number from the hardware entropy source, writes it to Xt, and requests a reseed of the entropy generator. This instruction is AArch64-only and requires the FEAT_RNG extension. It may set the C flag to indicate entropy availability, similar to RNDR.

Xt ← HardwareRandomNumber()
RequestReseed(entropy_generator)
if entropy_available then
  C ← 0
else
  C ← 1
end if


Summary: Inverts the C (Carry) flag.

Inverts the Carry flag (C) in the condition flags register. This instruction is AArch64-only and requires the FEAT_FlagM extension. All other condition flags (N, Z, V) remain unchanged. The operation is not privileged.


Summary: Rotates a register and inserts bits into the Process State flags.

Rotates the 64-bit value in Xn right by shift bits, then uses the mask to selectively update PSTATE condition flags (N, Z, C, V). Each bit set in mask causes the corresponding rotated bit to update the corresponding flag. AArch64-only; requires FEAT_FlagM. Does not update any other registers.

rotated ← ROR(Xn, shift); if mask<3> then N ← rotated<63>; if mask<2> then Z ← (rotated<width-1:0> == 0); if mask<1> then C ← rotated<0>; if mask<0> then V ← rotated<1>;


Summary: Sets PSTATE flags based on 8-bit operand.

Sets PSTATE condition flags (N, Z, C, V) based on the lower 8 bits of the 32-bit source register Wn, interpreting them as a signed 8-bit value. AArch64-only; requires FEAT_FlagM. N is set if bit 7 of Wn is set; Z is set if the lower 8 bits are zero; C and V are cleared.


Summary: Sets PSTATE flags based on 16-bit operand.

Sets PSTATE condition flags (N, Z, C, V) based on the lower 16 bits of the 32-bit source register Wn, interpreting them as a signed 16-bit value. AArch64-only; requires FEAT_FlagM. N is set if bit 15 of Wn is set; Z is set if the lower 16 bits are zero; C and V are cleared.


Summary: Converts double to signed 32-bit integer with JS rounding semantics.

Converts the 64-bit floating-point value in Dn to a signed 32-bit integer in Wd using JavaScript rounding semantics (round toward zero, with special handling for NaN and out-of-range values). AArch64-only; requires FEAT_JSCVT. Sets the C flag to 1 if the input is out of range or NaN, otherwise clears it. Other flags are not affected.

if IsNaN(Dn) or (Dn > 2^31 - 1) or (Dn < -2^31) then Wd ← 0; C ← 1; else Wd ← SignedSaturate(RoundTowardZero(Dn), 32); C ← 0;


Summary: Extracts bits from a register and sign-extends them.

Extracts a bitfield of width bits starting at position lsb from Rn, sign-extends the extracted value, and writes it to Rd. A32 instruction; available in all A32 processor modes. Does not affect PSTATE flags. The condition code suffix controls execution.

extracted ← Rn<(lsb + width - 1):lsb>; if extracted<(width - 1)> == 1 then Rd ← SignExtend(extracted, width) else Rd ← ZeroExtend(extracted, width);


Summary: Extracts bits from a register and zero-extends them.

Extracts a bitfield of width bits starting at position lsb from Rn, zero-extends the extracted value, and writes it to Rd. A32 instruction; available in all A32 processor modes. Does not affect PSTATE flags. The condition code suffix controls execution.

extracted ← Rn<(lsb + width - 1):lsb>; Rd ← ZeroExtend(extracted, width);


Summary: Sign-extends the low byte (8-bits) to 32-bits.

Rm

Second source / offset general-purpose register

Sign-extends the low byte of Rm into the full 32-bit word in Rd, with optional pre-rotation of Rm by 0, 8, 16, or 24 bits. This is an A32 instruction that does not affect any condition flags. The rotation is applied before the sign extension.

rotated ← ROR(Rm, rotation)
Rd ← SignExtend(rotated[7:0], 32)


Summary: Sign-extends the low halfword (16-bits) to 32-bits.

Sign-extends the low halfword of Rm into the full 32-bit word in Rd, with optional pre-rotation of Rm by 0, 8, 16, or 24 bits. This is an A32 instruction that does not affect any condition flags. The rotation is applied before the sign extension.

rotated ← ROR(Rm, rotation)
Rd ← SignExtend(rotated[15:0], 32)


Summary: Sign-extends two bytes to two halfwords.

Sign-extends the two low bytes (bits 7:0 and 15:8) of Rm to two 16-bit halfwords in Rd, with an optional rotation applied to Rm before extraction. A32 instruction; requires DSP extension. Does not affect PSTATE flags. The condition code suffix controls execution.

rotated ← ROR(Rm, rotation); Rd<15:0> ← SignExtend(rotated<7:0>, 16); Rd<31:16> ← SignExtend(rotated<15:8>, 16);


Summary: Zero-extends the low byte to 32-bits.

Zero-extends the low byte (bits [7:0]) of Rm to the full 32-bit width and stores the result in Rd. An optional rotation (0°, 90°, 180°, or 270°) can be applied to Rm before the extension. No condition flags are affected by this instruction. A32 only; executes in User and Privileged modes.

rotated ← ROR(Rm, rotation * 8)
Rd ← ZeroExtend(rotated[7:0], 32)


Summary: Zero-extends the low halfword to 32-bits.

Zero-extends the low halfword (bits [15:0]) of Rm to the full 32-bit width and stores the result in Rd. An optional rotation (0°, 90°, 180°, or 270°) can be applied to Rm before the extension. No condition flags are affected by this instruction. A32 only; executes in User and Privileged modes.

rotated ← ROR(Rm, rotation * 8)
Rd ← ZeroExtend(rotated[15:0], 32)


Summary: Zero-extends two bytes to two halfwords.

Zero-extends the two low bytes (bits 7:0 and 15:8) of Rm to two 16-bit halfwords in Rd, with an optional rotation applied to Rm before extraction. A32 instruction; requires DSP extension. Does not affect PSTATE flags. The condition code suffix controls execution.

rotated ← ROR(Rm, rotation); Rd<15:0> ← ZeroExtend(rotated<7:0>, 16); Rd<31:16> ← ZeroExtend(rotated<15:8>, 16);


Summary: Saturates a signed value to a specified bit width.

Saturates a signed integer to a specified bit width. The instruction shifts the source value by an optional amount, then saturates the result to a signed range defined by the saturation position. Sets the Q flag if saturation occurs; N, Z, C, V flags are unaffected. A32-only instruction requiring DSP extension.

shifted ← Rm << shift_amount
sat_range ← 2^(imm-1) - 1
if shifted > sat_range then
  Rd ← sat_range
  Q ← 1
else if shifted < -(2^(imm-1)) then
  Rd ← -(2^(imm-1))
  Q ← 1
else
  Rd ← shifted


Summary: Saturates an unsigned value to a specified bit width.

Saturates an unsigned integer to a specified bit width. The instruction shifts the source value by an optional amount, then saturates the result to an unsigned range [0, 2^imm-1]. Sets the Q flag if saturation occurs; N, Z, C, V flags are unaffected. A32-only instruction requiring DSP extension.

shifted ← Rm << shift_amount
sat_max ← 2^imm - 1
if shifted > sat_max then
  Rd ← sat_max
  Q ← 1
else if shifted < 0 then
  Rd ← 0
  Q ← 1
else
  Rd ← shifted


Summary: Saturates two signed 16-bit values.

Saturates two signed 16-bit halfword values packed in a register to a specified bit width. The upper and lower 16-bit values are independently saturated to the range [-(2^(imm-1)), 2^(imm-1)-1]. Sets the Q flag if either halfword saturates; N, Z, C, V flags are unaffected. A32-only instruction requiring DSP extension.

lower_hw ← Rm[15:0] (signed)
upper_hw ← Rm[31:16] (signed)
sat_range ← 2^(imm-1) - 1
sat_min ← -(2^(imm-1))
if lower_hw > sat_range or lower_hw < sat_min then
  Rd[15:0] ← Clamp(lower_hw, sat_min, sat_range)
  Q ← 1
else
  Rd[15:0] ← lower_hw
if upper_hw > sat_range or upper_hw < sat_min then
  Rd[31:16] ← Clamp(upper_hw, sat_min, sat_range)
  Q ← 1
else
  Rd[31:16] ← upper_hw


Summary: Saturates two unsigned 16-bit values.

Saturates two unsigned 16-bit halfword values packed in a register to a specified bit width. The upper and lower 16-bit values are independently saturated to the range [0, 2^imm-1]. Sets the Q flag if either halfword saturates; N, Z, C, V flags are unaffected. A32-only instruction requiring DSP extension.

lower_hw ← Rm[15:0] (unsigned)
upper_hw ← Rm[31:16] (unsigned)
sat_max ← 2^imm - 1
if lower_hw > sat_max then
  Rd[15:0] ← sat_max
  Q ← 1
else
  Rd[15:0] ← lower_hw
if upper_hw > sat_max then
  Rd[31:16] ← sat_max
  Q ← 1
else
  Rd[31:16] ← upper_hw


Summary: Combines bottom half of Rn with top half of shifted Rm.

PKHBT<c> <Rd>, <Rn>, <Rm> {, LSL #<imm>}

Packs the bottom halfword of Rn with the top halfword of (Rm shifted left). Assembles a 32-bit result by taking bits [15:0] from Rn and bits [31:16] from the shifted Rm. Condition flags N, Z, C, V are unaffected. A32-only instruction requiring DSP extension.

Rd[15:0] ← Rn[15:0]
shifted_rm ← Rm << shift_imm
Rd[31:16] ← shifted_rm[31:16]


Summary: Combines top half of Rn with bottom half of shifted Rm.

PKHTB<c> <Rd>, <Rn>, <Rm> {, ASR #<imm>}

Packs the top halfword of Rn with the bottom halfword of (Rm shifted right). Assembles a 32-bit result by taking bits [31:16] from Rn and bits [15:0] from the shifted Rm. Condition flags N, Z, C, V are unaffected. A32-only instruction requiring DSP extension.

shifted_rm ← Rm >> shift_imm
Rd[15:0] ← shifted_rm[15:0]
Rd[31:16] ← Rn[31:16]


Summary: Parallel add of two signed 16-bit halfwords.

Performs two independent parallel signed 16-bit additions: the high halfword of Rn is added to the high halfword of Rm, and the low halfword of Rn is added to the low halfword of Rm; results are stored in the corresponding halfwords of Rd. The CPSR GE[3:0] flags are updated to reflect signed overflow in each halfword; N, Z, C, V are unaffected. A32 only; requires DSP extension; executes in User and Privileged modes.


Summary: Parallel add of two unsigned 16-bit halfwords.

Performs two independent parallel unsigned 16-bit additions: the high halfword of Rn is added to the high halfword of Rm, and the low halfword of Rn is added to the low halfword of Rm; results are stored in the corresponding halfwords of Rd. The CPSR GE[3:0] flags are updated to reflect unsigned overflow (carry-out) in each halfword; N, Z, C, V are unaffected. A32 only; requires DSP extension; executes in User and Privileged modes.


Summary: Parallel add of four signed 8-bit bytes.

Performs four independent parallel signed 8-bit additions, one for each byte of Rn and Rm; results are stored in the corresponding bytes of Rd. The CPSR GE[3:0] flags are updated to reflect signed overflow in each byte; N, Z, C, V are unaffected. A32 only; requires DSP extension; executes in User and Privileged modes.


Summary: Parallel add of four unsigned 8-bit bytes.

Performs four independent parallel unsigned 8-bit additions, one for each byte of Rn and Rm; results are stored in the corresponding bytes of Rd. The CPSR GE[3:0] flags are updated to reflect unsigned overflow (carry-out) in each byte; N, Z, C, V are unaffected. A32 only; requires DSP extension; executes in User and Privileged modes.


Summary: Parallel sub of two signed 16-bit halfwords.

Performs two independent parallel signed 16-bit subtractions: the high halfword of Rm is subtracted from the high halfword of Rn, and the low halfword of Rm is subtracted from the low halfword of Rn; results are stored in the corresponding halfwords of Rd. The CPSR GE[3:0] flags are updated to reflect signed borrow in each halfword; N, Z, C, V are unaffected. A32 only; requires DSP extension; executes in User and Privileged modes.


Summary: Parallel sub of two unsigned 16-bit halfwords.

Performs two independent parallel unsigned 16-bit subtractions: the high halfword of Rm is subtracted from the high halfword of Rn, and the low halfword of Rm is subtracted from the low halfword of Rn; results are stored in the corresponding halfwords of Rd. The CPSR GE[3:0] flags are updated to reflect unsigned borrow (no carry-out) in each halfword; N, Z, C, V are unaffected. A32 only; requires DSP extension; executes in User and Privileged modes.


Summary: Computes sum of absolute differences of bytes (Video Codec).

Computes the unsigned sum of absolute differences of four byte-wide values. Treats Rn and Rm as four unsigned bytes each, computes the absolute difference for each byte pair, sums them, and stores the result in Rd. Condition flags N, Z, C, V are unaffected. A32-only instruction requiring DSP extension; commonly used in video codec applications.


Unsigned Sum of Absolute Differences Accumulate

Summary: USAD8 plus accumulator.

Computes the unsigned sum of absolute differences of four byte-wide values and adds an accumulator. Treats Rn and Rm as four unsigned bytes each, computes absolute differences for each byte pair, sums them, and adds the value in Ra to produce the result stored in Rd. Condition flags N, Z, C, V are unaffected. A32-only instruction requiring DSP extension.


Summary: Multiplies and returns the top 32-bits of the 64-bit result.

Signed Most Significant Word Multiply performs a signed 32×32-bit multiply and returns the upper 32 bits of the 64-bit result in Rd. This is commonly used for fixed-point arithmetic and fast DSP operations. No condition flags are affected. Available in A32 instruction set with DSP extension; the optional R suffix rounds the result by adding 0x80000000 before truncation.

product ← SignedMul(Rn, Rm)
Rd ← (product[63:32])


Summary: SMMUL + Accumulate.

Signed Most Significant Word Multiply Accumulate computes the signed product of Rn and Rm, extracts the upper 32 bits, and adds the accumulator register Ra to produce the final result stored in Rd. This combines multiplication and accumulation in a single instruction, useful for DSP and filtering operations. No condition flags are affected. Available in A32 instruction set with DSP extension; the optional R suffix applies rounding.

product ← SignedMul(Rn, Rm)
Rd ← Ra + (product[63:32])


Summary: Adds two floating-point values.

Adds two single-precision floating-point values (Sn + Sm) and stores the result in Sd. This VFP instruction operates on 32-bit IEEE 754 single-precision operands. The condition flags (N, Z, C, V) are updated based on the floating-point result according to the FPSCR. Execution is conditional based on the <c> condition code and requires VFP extension support in A32/T32 modes.


Summary: Adds two double-precision floating-point values.

Adds two double-precision floating-point values (Dn + Dm) and stores the result in Dd. This VFP instruction operates on 64-bit IEEE 754 double-precision operands. The condition flags (N, Z, C, V) are updated based on the floating-point result according to the FPSCR. Execution is conditional based on the <c> condition code and requires VFP extension support in A32/T32 modes.


Summary: Subtracts two floating-point values.

Subtracts two single-precision floating-point values (Sn - Sm) and stores the result in Sd. This VFP instruction operates on 32-bit IEEE 754 single-precision operands. The condition flags (N, Z, C, V) are updated based on the floating-point result according to the FPSCR. Execution is conditional based on the <c> condition code and requires VFP extension support in A32/T32 modes.


Summary: Multiplies two floating-point values.

Vector Multiply (VFP) performs single-precision floating-point multiplication of Sn and Sm, storing the result in Sd. The operation follows IEEE 754 semantics, updating the FPSCR exception flags (IXC, OFC, UFC, IOC, DZC) based on the result but not affecting the ARM condition flags N, Z, C, V. Available in A32/T32 with VFP extension; execution is conditional based on the condition code suffix.

Sd ← FP_Multiply(Sn, Sm)
FPSCR ← updated with floating-point exception flags


Summary: Divides two floating-point values.

Divides two single-precision floating-point values (Sn / Sm) and stores the result in Sd. This VFP instruction performs floating-point division on 32-bit IEEE 754 single-precision operands. The condition flags (N, Z, C, V) are updated based on the floating-point result according to the FPSCR; division by zero generates a floating-point exception or returns infinity depending on exception settings. Execution is conditional based on the <c> condition code and requires VFP extension support in A32/T32 modes.

Sd ← Sn / Sm
FPSCR.NZCV ← FP_CC(result)
if (Sm == 0.0) then FP_Exception(DivideByZero)


Summary: Sd = Sd + (Sn * Sm).

Vector Multiply Accumulate (VFP) computes Sn × Sm and adds the result to Sd, storing the final value back in Sd. The operation follows IEEE 754 semantics with rounding and exception handling controlled by FPSCR, updating floating-point exception flags but not ARM condition flags. Available in A32/T32 with VFP extension; execution is conditional based on the condition code suffix.

product ← FP_Multiply(Sn, Sm)
Sd ← FP_Add(Sd, product)
FPSCR ← updated with floating-point exception flags


Summary: Sd = Sd - (Sn * Sm).

Multiplies two single-precision floating-point values and subtracts the result from the destination (Sd ← Sd - (Sn × Sm)). This VFP instruction performs a fused multiply-subtract operation on 32-bit IEEE 754 single-precision operands, with Sd serving as both accumulator and destination. The condition flags (N, Z, C, V) are updated based on the final floating-point result according to the FPSCR. Execution is conditional based on the <c> condition code and requires VFP extension support in A32/T32 modes.

Sd ← Sd - (Sn × Sm)
FPSCR.NZCV ← FP_CC(result)


Summary: Sd = -(Sn * Sm).

Vector Negated Multiply (VFP) computes the negation of Sn × Sm and stores the result in Sd. This is equivalent to multiplying then negating, and follows IEEE 754 semantics for the intermediate product, with sign negation applied afterward. FPSCR exception flags are updated but ARM condition flags N, Z, C, V are not affected. Available in A32/T32 with VFP extension; execution is conditional based on the condition code suffix.

product ← FP_Multiply(Sn, Sm)
Sd ← FP_Negate(product)
FPSCR ← updated with floating-point exception flags


Summary: Calculates absolute value.

Vector Absolute Value (VFP) computes the absolute value of Sm by clearing the sign bit and storing the result in Sd. This is a unary floating-point operation that follows IEEE 754 semantics, updating FPSCR exception flags but not affecting ARM condition flags. Available in A32/T32 with VFP extension; execution is conditional based on the condition code suffix.

Sd ← FP_AbsoluteValue(Sm)
FPSCR ← updated with floating-point exception flags


Summary: Negates the value.

Vector Negate (VFP) negates the value in Sm by inverting the sign bit and stores the result in Sd. This is a unary floating-point operation that follows IEEE 754 semantics, affecting only the sign bit and updating FPSCR exception flags but not ARM condition flags. Available in A32/T32 with VFP extension; execution is conditional based on the condition code suffix.

Sd ← FP_Negate(Sm)
FPSCR ← updated with floating-point exception flags


Summary: Calculates square root.

Vector Square Root (VFP) computes the square root of Sm using IEEE 754 semantics and stores the result in Sd. This unary floating-point operation may raise exceptions for invalid operands (negative inputs) or precision issues, updating FPSCR exception flags but not affecting ARM condition flags. Available in A32/T32 with VFP extension; execution is conditional based on the condition code suffix.

Sd ← FP_SquareRoot(Sm)
FPSCR ← updated with floating-point exception flags


Summary: Compares two floating-point values.

Compares two single-precision floating-point values in VFP registers and sets the FPSCR condition flags (N, Z, C, V) based on the comparison result. The comparison is quiet (does not raise exceptions for NaN operands). Executed in A32/T32 with VFP extension; condition flags are updated in the floating-point status and control register (FPSCR), not the general-purpose condition flags.

result ← compare(Sd, Sm)
FPSCR.N ← result.N
FPSCR.Z ← result.Z
FPSCR.C ← result.C
FPSCR.V ← result.V


Summary: Compares values and raises exception on NaN.

Compares two single-precision floating-point values in VFP registers and sets the FPSCR condition flags (N, Z, C, V) based on the comparison result. Unlike VCMP, this variant raises an Invalid Operation exception if either operand is NaN (signaling comparison). Executed in A32/T32 with VFP extension; exception behavior depends on FPSCR exception-enable bits.

if Sd is NaN or Sm is NaN then
  if FPSCR.IXE then raise InvalidOperationException
result ← compare(Sd, Sm)
FPSCR.N ← result.N
FPSCR.Z ← result.Z
FPSCR.C ← result.C
FPSCR.V ← result.V


Summary: Converts float to signed/unsigned integer.

Converts a single-precision floating-point value to a signed or unsigned 32-bit integer and stores the result in Sd. This VFP instruction performs floating-point-to-integer conversion with rounding behavior controlled by the FPSCR rounding mode. The condition flags are not updated; conversion errors (overflow, invalid operand) may set exception bits in the FPSCR depending on exception configuration. Execution is conditional based on the <c> condition code and requires VFP extension support in A32/T32 modes.

result ← Convert_F32_to_Int32(Sm, signed/unsigned, rounding_mode)
Sd ← result
if (overflow or invalid) then FP_Exception_or_Saturate()


Summary: Moves data between VFP registers.

Moves (copies) a single-precision floating-point value from one VFP register to another (Sd ← Sm). This is a pure register-to-register transfer with no arithmetic; it preserves the bit pattern including NaN payloads and sign. Condition flags are not affected. Execution is conditional based on the <c> condition code and requires VFP extension support in A32/T32 modes.


Summary: Moves data between Core registers (R) and VFP registers (S).

Moves a 32-bit value between a core integer register (Rt) and a VFP single-precision register (Sn). The instruction transfers the bit pattern without interpretation; a floating-point value moved to a core register is treated as raw bits. Condition flags are not affected. Execution is conditional based on the <c> condition code and requires VFP extension support in A32/T32 modes.


Summary: Loads a floating-point register from memory.

Loads a single-precision floating-point value from memory into a VFP register using a PC-relative or register-relative address with an optional offset. The memory access uses the address [Rn ± (imm8 << 2)]. Executed in A32/T32 with VFP extension; no condition flags are affected.

offset ← ZeroExtend(imm8) << 2
if U == 1 then
  address ← Rn + offset
else
  address ← Rn - offset
Sd ← [address]


Summary: Stores a floating-point register to memory.

Stores a single-precision floating-point value from a VFP register to memory using a register-relative address with an optional offset. The memory access uses the address [Rn ± (imm8 << 2)]. Executed in A32/T32 with VFP extension; no condition flags are affected.

offset ← ZeroExtend(imm8) << 2
if U == 1 then
  address ← Rn + offset
else
  address ← Rn - offset
[address] ← Sd


Summary: Pops VFP registers from the stack (Alias for VLDMIA SP!).

Pops VFP floating-point registers from the stack by loading them from memory at the address in SP, then post-incrementing SP. This is an alias for VLDMIA SP! (VFP Load Multiple with post-index). The condition flags (N, Z, C, V) are unaffected by this instruction. Execution is restricted to A32 and T32 instruction sets with VFP extension enabled.

address ← SP; for each register in list (in ascending order): register ← [address]; address ← address + 4 or 8 (depending on register width); SP ← address;


Summary: Pushes VFP registers to the stack (Alias for VSTMDB SP!).

Pushes VFP floating-point registers onto the stack by decrementing SP and storing them to memory. This is an alias for VSTMDB SP! (VFP Store Multiple with pre-decrement). The condition flags (N, Z, C, V) are unaffected by this instruction. Execution is restricted to A32 and T32 instruction sets with VFP extension enabled.

address ← SP; for each register in list (in descending order): address ← address - 4 or 8 (depending on register width); [address] ← register; SP ← address;


Summary: Thumb-2 32-bit add with carry (Access high registers/large constants).

Flexible second operand (register or shifted register)

Adds Rn and Operand2 plus the Carry flag value, storing the result in Rd. If S=1, the N, Z, C, V flags are updated based on the result; otherwise flags are unaffected. This is a Thumb-2 32-bit instruction that allows use of high registers (R8-R15) and larger constant operands than 16-bit Thumb ADC.

result ← Rn + Operand2 + C; Rd ← result; if S == 1 then: N ← result[31]; Z ← (result == 0); C ← CarryOut(Rn, Operand2, C); V ← OverflowFrom(Rn, Operand2, C);


Summary: Thumb-2 32-bit add.

Adds Rn and Operand2, storing the result in Rd. If S=1, the N, Z, C, V flags are updated based on the result; otherwise flags are unaffected. This is a Thumb-2 32-bit instruction that allows use of high registers (R8-R15) and larger constant operands than 16-bit Thumb ADD.

result ← Rn + Operand2; Rd ← result; if S == 1 then: N ← result[31]; Z ← (result == 0); C ← CarryOut(Rn, Operand2); V ← OverflowFrom(Rn, Operand2);


Summary: Thumb-2 32-bit subtract.

Subtracts Operand2 from Rn, storing the result in Rd. If S=1, the N, Z, C, V flags are updated based on the result; otherwise flags are unaffected. This is a Thumb-2 32-bit instruction that allows use of high registers (R8-R15) and larger constant operands than 16-bit Thumb SUB.

result ← Rn - Operand2; Rd ← result; if S == 1 then: N ← result[31]; Z ← (result == 0); C ← NOT BorrowFrom(Rn, Operand2); V ← OverflowFrom(Rn, -Operand2);


Summary: Thumb-2 32-bit subtract with carry.

Subtracts Operand2 and the inverted Carry flag from Rn, storing the result in Rd. If S=1, the N, Z, C, V flags are updated based on the result; otherwise flags are unaffected. This is a Thumb-2 32-bit instruction used for multi-word arithmetic with carry propagation.

result ← Rn - Operand2 - (NOT C); Rd ← result; if S == 1 then: N ← result[31]; Z ← (result == 0); C ← NOT BorrowFrom(Rn, Operand2, NOT C); V ← OverflowFrom(Rn, -Operand2, NOT C);


Summary: Thumb-2 32-bit reverse subtract.

Reverse-subtracts Rn from Operand2, storing the result in Rd (computes Operand2 - Rn). If S=1, the N, Z, C, V flags are updated based on the result; otherwise flags are unaffected. This is a Thumb-2 32-bit instruction allowing negation and complex arithmetic patterns.

result ← Operand2 - Rn; Rd ← result; if S == 1 then: N ← result[31]; Z ← (result == 0); C ← NOT BorrowFrom(Operand2, Rn); V ← OverflowFrom(Operand2, -Rn);


Summary: Thumb-2 32-bit AND.

Performs a bitwise AND of Rn and the shifted Operand2, storing the result in Rd. In Thumb-2, this is a 32-bit instruction that can update the condition flags (N, Z, C) when the S bit is set; V is unaffected. The operand2 can be a register with optional shift or an immediate value.

result ← Rn AND Operand2
Rd ← result
if S == 1 then
  CPSR.N ← result[31]
  CPSR.Z ← (result == 0)
  CPSR.C ← CarryOut(Operand2)
else
  CPSR.C ← CPSR.C


Summary: Thumb-2 32-bit OR.

Performs a bitwise OR of Rn and the shifted Operand2, storing the result in Rd. In Thumb-2, this is a 32-bit instruction that can update the condition flags (N, Z, C) when the S bit is set; V is unaffected. The operand2 can be a register with optional shift or an immediate value.

result ← Rn OR Operand2
Rd ← result
if S == 1 then
  CPSR.N ← result[31]
  CPSR.Z ← (result == 0)
  CPSR.C ← CarryOut(Operand2)
else
  CPSR.C ← CPSR.C


Summary: Thumb-2 32-bit XOR.

Performs a bitwise exclusive-OR (XOR) of Rn and the shifted Operand2, storing the result in Rd. In Thumb-2, this is a 32-bit instruction that can update the condition flags (N, Z, C) when the S bit is set; V is unaffected. The operand2 can be a register with optional shift or an immediate value.

result ← Rn XOR Operand2
Rd ← result
if S == 1 then
  CPSR.N ← result[31]
  CPSR.Z ← (result == 0)
  CPSR.C ← CarryOut(Operand2)
else
  CPSR.C ← CPSR.C


Summary: Thumb-2 32-bit AND NOT.

Performs a bitwise AND of Rn with the bitwise NOT of the shifted Operand2, effectively clearing bits in Rn where Operand2 has set bits. In Thumb-2, this is a 32-bit instruction that can update the condition flags (N, Z, C) when the S bit is set; V is unaffected. The operand2 can be a register with optional shift or an immediate value.

result ← Rn AND NOT Operand2
Rd ← result
if S == 1 then
  CPSR.N ← result[31]
  CPSR.Z ← (result == 0)
  CPSR.C ← CarryOut(Operand2)
else
  CPSR.C ← CPSR.C


Summary: Thumb-2 32-bit OR NOT.

Bitwise OR NOT: computes Rd = Rn | ~Operand2, performing a logical OR between Rn and the bitwise NOT of Operand2. The N and Z flags are updated based on the result; C is updated by the shifter; V is unaffected. This is a Thumb-2 (32-bit) instruction available in T32 execution state.

result ← Rn | (NOT Operand2)
Rd ← result
N ← result[31]
Z ← (result == 0)
C ← CarryOut(NOT Operand2)
V ← unchanged


Summary: Thumb-2 32-bit Move.

Moves Operand2 into Rd without affecting any flags (the S bit is fixed to 0 in this variant). This is a Thumb-2 32-bit instruction that allows encoding of larger immediates (via modified immediate) and access to high registers (R8-R15), providing greater flexibility than 16-bit Thumb MOV.


Summary: Thumb-2 32-bit Move Inverse.

Thumb-2 32-bit bitwise NOT: Rd ← NOT(Operand2). The second operand can be a register or a shifted register. If the S suffix is present, the condition flags N and Z are updated based on the result, and C is updated from the shifter carry-out; V is unaffected. Execution state: T32 only.

result ← NOT(Operand2)
Rd ← result
if S then
  N ← result[31]
  Z ← (result == 0)
  C ← shifter_carry_out


Summary: Thumb-2 32-bit Test (AND and update flags).

Test (AND and update flags): computes the bitwise AND of Rn and Operand2, updating the N and Z flags based on the result without writing to a destination register. C is updated by the shifter; V is unaffected. This is a Thumb-2 (32-bit) instruction available in T32 execution state.

result ← Rn AND Operand2
N ← result[31]
Z ← (result == 0)
C ← CarryOut(Operand2)
V ← unchanged


Summary: Thumb-2 32-bit Test Equivalence (XOR and update flags).

Test Equivalence (XOR and update flags): computes the bitwise XOR of Rn and Operand2, updating the N and Z flags based on the result without writing to a destination register. C is updated by the shifter; V is unaffected. This is a Thumb-2 (32-bit) instruction available in T32 execution state.

result ← Rn XOR Operand2
N ← result[31]
Z ← (result == 0)
C ← CarryOut(Operand2)
V ← unchanged


Summary: Thumb-2 32-bit Compare (Subtract and update flags).

Compare (Subtract and update flags): computes Rn - Operand2, updating the N, Z, C, and V flags based on the result without writing to a destination register. This is a Thumb-2 (32-bit) instruction available in T32 execution state and is commonly used to set condition flags for subsequent conditional branches.

result ← Rn - Operand2
N ← result[31]
Z ← (result == 0)
C ← NOT BorrowFrom(Rn - Operand2)
V ← OverflowFrom(Rn - Operand2)


Summary: Thumb-2 32-bit Compare Negative (Add and update flags).

Compare Negative (Add and update flags): computes Rn + Operand2, updating the N, Z, C, and V flags based on the result without writing to a destination register. This is a Thumb-2 (32-bit) instruction available in T32 execution state and is commonly used to compare a register against the negation of a value.

result ← Rn + Operand2
N ← result[31]
Z ← (result == 0)
C ← CarryOut(Rn + Operand2)
V ← OverflowFrom(Rn + Operand2)


Summary: Initiates a coprocessor data processing operation.

CDP<c> <coproc>, <opc1>, <CRd>, <CRn>, <CRm>, <opc2>

cond | 1110 | opc1 | CRn | CRd | coproc | opc2 | 0 | CRm

Coprocessor Data Processing: initiates a data processing operation in the specified coprocessor using three coprocessor registers and two operation codes. The instruction is conditional based on the condition field and does not modify processor flags. This is an A32 instruction restricted to privileged execution states in systems with a coprocessor.

if ConditionPassed() then
  Coprocessor[coproc].DataProcessing(opc1, CRd, CRn, CRm, opc2)


Summary: Initiates a coprocessor operation (Extension encoding).

CDP2<c> <coproc>, <opc1>, <CRd>, <CRn>, <CRm>, <opc2>

11111110 | opc1 | CRn | CRd | coproc | opc2 | 0 | CRm

Coprocessor Data Processing 2 (unconditional extension): initiates a data processing operation in the specified coprocessor using three coprocessor registers and two operation codes. Unlike CDP, this instruction is unconditional and uses the extension encoding (always executes). Restricted to privileged execution states in systems with a coprocessor.

Coprocessor[coproc].DataProcessing(opc1, CRd, CRn, CRm, opc2)


Move to Coprocessor from Register 2 (A32)

Summary: Writes a general-purpose register to a coprocessor (Extension encoding).

MCR2<c> <coproc>, <opc1>, <Rt>, <CRn>, <CRm>{, <opc2>}

11111110 | opc1 | 0 | CRn | Rt | coproc | opc2 | 1 | CRm

A32 coprocessor data transfer (extension encoding): writes the general-purpose register Rt to the coprocessor coproc, register CRm, with operation codes opc1 and opc2. Does not modify condition flags. Execution state: A32 only; requires coprocessor support. May cause an Undefined Instruction exception if the coprocessor does not exist.


Move to Register from Coprocessor 2 (A32)

Summary: Reads a coprocessor register into a general-purpose register (Extension encoding).

MRC2<c> <coproc>, <opc1>, <Rt>, <CRn>, <CRm>{, <opc2>}

11111110 | opc1 | 1 | CRn | Rt | coproc | opc2 | 1 | CRm

A32 coprocessor data transfer (extension encoding): reads a coprocessor register (CRn, CRm) from coproc into the general-purpose register Rt. The opc1 and opc2 fields specify the operation. Does not modify condition flags. Execution state: A32 only; requires coprocessor support. May cause an Undefined Instruction exception if the coprocessor does not exist.

Rt ← Coprocessor[coproc].CRn[opc1] or Coprocessor[coproc].CRm[opc2]


Move to Coprocessor from Two Registers 2 (A32)

Summary: Writes two registers to a coprocessor (Extension encoding).

MCRR2<c> <coproc>, <opc1>, <Rt>, <Rt2>, <CRm>

Second transfer register (load/store pair)

A32 coprocessor data transfer (extension encoding): writes two general-purpose registers (Rt, Rt2) to the coprocessor coproc, coprocessor register CRm, with operation code opc1. Does not modify condition flags. Execution state: A32 only; requires coprocessor support. May cause an Undefined Instruction exception if the coprocessor does not exist.


Move to Two Registers from Coprocessor 2 (A32)

Summary: Reads a coprocessor register into two registers (Extension encoding).

MRRC2<c> <coproc>, <opc1>, <Rt>, <Rt2>, <CRm>

A32 coprocessor data transfer (extension encoding): reads a 64-bit value from coprocessor coproc register CRm into two general-purpose registers (Rt, Rt2), with operation code opc1. Does not modify condition flags. Execution state: A32 only; requires coprocessor support. May cause an Undefined Instruction exception if the coprocessor does not exist.


Summary: Loads memory into a coprocessor (Extension encoding).

1111110 | P | U | N | W | 1 | Rn | CRd | coproc | imm8

Load Coprocessor 2 (unconditional extension): loads a word or multiple words from memory into a coprocessor register, with the memory address computed from Rn plus an optional offset. The P, U, W bits control pre/post-indexing and writeback; the instruction is unconditional and uses the extension encoding. Restricted to privileged execution states and requires a coprocessor.

if P == 0 and W == 1 then
  address ← Rn
  Rn ← Rn + (if U then imm8 << 2 else -(imm8 << 2))
else if P == 1 then
  address ← Rn + (if U then imm8 << 2 else -(imm8 << 2))
  if W == 1 then Rn ← address
Coprocessor[coproc].LoadFromMemory(CRd, address)


Summary: Stores coprocessor contents to memory (Extension encoding).

1111110 | P | U | N | W | 0 | Rn | CRd | coproc | imm8

Stores coprocessor data to memory using an extension encoding (STC2 variant). The instruction computes an address from base register Rn and an offset (imm8 scaled by 4), and writes coprocessor register CRd to that memory location. The P, U, N, W bits control pre/post-indexing, up/down offset direction, narrow/wide transfer, and write-back. Condition flags are not affected.

if ConditionPassed() then
  address ← ComputeAddress(Rn, imm8, P, U, W)
  memory[address] ← CP[coproc, CRd]
  if W == 1 then Rn ← address


Summary: Shifts register right by 1, inserting Carry flag into MSB.

A32 Rotate Right with Extend by 1: Rd ← (C : Rm)[32:1], where the Carry flag is shifted into the MSB and the LSB is shifted out to C. If the S suffix is present, N and Z are updated from the result, and C is updated from the shifted-out bit; V is unaffected. Execution state: A32 only.

shifted_result ← (C : Rm)[32:1]
Rd ← shifted_result
if S then
  N ← shifted_result[31]
  Z ← (shifted_result == 0)
  C ← Rm[0]


Summary: Thumb-2 32-bit Rotate Right with Extend.

Thumb-2 32-bit Rotate Right with Extend by 1: Rd ← (C : Rm)[32:1], where the Carry flag is rotated into the MSB and the LSB is shifted out to C. If the S suffix is present, N and Z are updated from the result, and C is updated from the shifted-out bit; V is unaffected. Execution state: T32 only.


Summary: Thumb-2 32-bit Unconditional Branch (large range).

Thumb-2 32-bit unconditional branch with large range (±16 MB). Computes the target address by sign-extending the immediate offset (formed from S, imm10, J1, J2, imm11) and adding it to PC. No condition flags are affected; no registers are modified except PC.

if ConditionPassed() then
  offset ← SignExtend(S || imm10 || J1 || J2 || imm11, 24)
  PC ← PC + (offset << 1)


Summary: Thumb-2 32-bit Branch with Link.

Thumb-2 32-bit branch with link and large range (±16 MB). Stores return address (next instruction) in LR and branches to the target computed from the S, imm10, J1, J2, imm11 fields. No condition flags are affected.

if ConditionPassed() then
  LR ← PC + 4 | 1
  offset ← SignExtend(S || imm10 || J1 || J2 || imm11, 24)
  PC ← PC + (offset << 1)


Summary: Thumb-2 32-bit ADR.

Thumb-2 32-bit form PC-relative address: Rd ← PC + offset, where the offset is computed from the immediate fields encoded as a 12-bit modified immediate. The assembler calculates the label-relative offset and encodes it. Does not modify condition flags. Execution state: T32 only.

offset ← expand_12bit_imm(i : imm3 : imm8)
Rd ← Align(PC, 4) + offset


Summary: Thumb-2 32-bit Load Word.

Load a 32-bit word from memory at address [Rn + imm12] into Rt. The immediate offset is unsigned and ranges from 0 to 4095 bytes. Condition flags (N, Z, C, V) are not affected. T32 (Thumb-2) instruction only.

address ← Rn + ZeroExtend(imm12, 32);
Rt ← [address]<31:0>;


Summary: Thumb-2 32-bit Load Byte.

Load an 8-bit byte from memory at address [Rn + imm12] into Rt, zero-extending to 32 bits. The immediate offset is unsigned and ranges from 0 to 4095 bytes. Condition flags (N, Z, C, V) are not affected. T32 (Thumb-2) instruction only.

address ← Rn + ZeroExtend(imm12, 32);
Rt ← ZeroExtend([address]<7:0>, 32);


Summary: Thumb-2 32-bit Load Halfword.

Load a 16-bit halfword from memory at address [Rn + imm12] into Rt, zero-extending to 32 bits. The immediate offset is unsigned and ranges from 0 to 4095 bytes; the halfword must be 2-byte aligned. Condition flags (N, Z, C, V) are not affected. T32 (Thumb-2) instruction only.

address ← Rn + ZeroExtend(imm12, 32);
Rt ← ZeroExtend([address]<15:0>, 32);


Summary: Thumb-2 32-bit Load Signed Byte.

Load an 8-bit signed byte from memory at address [Rn + imm12] into Rt, sign-extending to 32 bits. The immediate offset is unsigned and ranges from 0 to 4095 bytes. Condition flags (N, Z, C, V) are not affected. T32 (Thumb-2) instruction only.

address ← Rn + ZeroExtend(imm12, 32);
Rt ← SignExtend([address]<7:0>, 32);


Summary: Thumb-2 32-bit Load Signed Halfword.

Load a 16-bit signed halfword from memory at address [Rn + imm12] into Rt, sign-extending to 32 bits. The immediate offset is unsigned and ranges from 0 to 4095 bytes; the halfword must be 2-byte aligned. Condition flags (N, Z, C, V) are not affected. T32 (Thumb-2) instruction only.

address ← Rn + ZeroExtend(imm12, 32);
Rt ← SignExtend([address]<15:0>, 32);


Summary: Thumb-2 32-bit Store Word.

Store a 32-bit word from Rt to memory at address [Rn + imm12]. The immediate offset is unsigned and ranges from 0 to 4095 bytes. Condition flags (N, Z, C, V) are not affected. T32 (Thumb-2) instruction only.

address ← Rn + ZeroExtend(imm12, 32);
[address]<31:0> ← Rt;


Summary: Thumb-2 32-bit Store Byte.

Store the lowest 8 bits of Rt to memory at address [Rn + imm12]. The immediate offset is unsigned and ranges from 0 to 4095 bytes. Condition flags (N, Z, C, V) are not affected. T32 (Thumb-2) instruction only.

address ← Rn + ZeroExtend(imm12, 32);
[address]<7:0> ← Rt<7:0>;


Summary: Thumb-2 32-bit Store Halfword.

Store the lowest 16 bits of Rt to memory at address [Rn + imm12]. The immediate offset is unsigned and ranges from 0 to 4095 bytes; the halfword must be 2-byte aligned. Condition flags (N, Z, C, V) are not affected. T32 (Thumb-2) instruction only.

address ← Rn + ZeroExtend(imm12, 32);
[address]<15:0> ← Rt<15:0>;


Summary: Thumb-2 32-bit Load Multiple.

Load Multiple (32-bit Thumb-2 encoding) loads a list of general-purpose registers from consecutive memory locations starting at the address in Rn. If the writeback bit (!) is set, Rn is updated to point to the first address after the loaded data. No flags are affected by this instruction. Execution is restricted to T32 (Thumb-2) state.

address ← Rn
for each register in registers (in increasing order):
  register ← [address]
  address ← address + 4
if writeback:
  Rn ← address


Summary: Thumb-2 32-bit Store Multiple.

Store Multiple (32-bit Thumb-2 encoding) stores a list of general-purpose registers to consecutive memory locations starting at the address in Rn. If the writeback bit (!) is set, Rn is updated to point to the first address after the stored data. No flags are affected by this instruction. Execution is restricted to T32 (Thumb-2) state.

address ← Rn
for each register in registers (in increasing order):
  [address] ← register
  address ← address + 4
if writeback:
  Rn ← address


Summary: Thumb-2 32-bit Pop.

Thumb-2 32-bit pop instruction that loads multiple general-purpose registers from the stack. Loads the registers listed in the register list from memory at [SP], [SP+4], etc., and increments SP by 4×(number of registers). If PC is in the register list, it is loaded and execution jumps to that address.

for i = 0 to 15
  if registers[i] == 1 then
    Ri ← memory[SP]
    SP ← SP + 4
if registers[15] == 1 then
  PC ← R15


Summary: Thumb-2 32-bit Push.

Thumb-2 32-bit push instruction that stores multiple general-purpose registers to the stack. Decrements SP by 4×(number of registers) and stores each register in the list to memory in ascending order of register number. This is equivalent to STMDB SP!, <registers>.

SP ← SP - 4 * PopCount(registers)
for i = 0 to 15
  if registers[i] == 1 then
    memory[SP + 4*(count_of_set_bits_below_i)] ← Ri


Summary: Computes absolute difference and adds to accumulator.

NEON Vector Absolute Difference and Accumulate: computes the absolute difference between corresponding elements in Qn and Qm, then adds the results to the corresponding elements in Qd (accumulation). The data type (dt) determined by sz (8, 16, 32 bits) specifies element width. NEON flags (FPSCR) are not modified; no general condition flags are affected.

for i = 0 to num_elements(Qd, dt) - 1
  diff ← abs(Qn[i] - Qm[i])
  Qd[i] ← Qd[i] + diff


Summary: Computes absolute difference between elements.

NEON Vector Absolute Difference: computes the absolute difference between corresponding elements in Qn and Qm and stores results in Qd. The data type (dt) determined by sz specifies element width (8, 16, or 32 bits). NEON flags are not modified; no general condition flags are affected.

for i = 0 to num_elements(Qd, dt) - 1
  Qd[i] ← abs(Qn[i] - Qm[i])


Summary: Calculates absolute value of integer/float elements.

NEON Vector Absolute Value: computes the absolute value of each element in Qm and stores the result in Qd. Supports integer (8, 16, 32 bits) and floating-point (32 bits) data types as specified by sz. NEON flags are not modified; no general condition flags are affected.

for i = 0 to num_elements(Qd, dt) - 1
  Qd[i] ← abs(Qm[i])


Summary: Adds integer elements of two vectors.

Vector Add (Integer) performs element-wise addition of two NEON 128-bit registers, adding corresponding integer elements of size 8, 16, 32, or 64 bits. The instruction executes in Q-register (128-bit) mode and wraps on overflow without setting flags. This is a NEON SIMD instruction available in both A32 and T32 states when NEON is supported.

for each element i in Qd:
  Qd[i] ← Qn[i] + Qm[i]


Summary: Adds 2N-bit elements, selects high N-bits for result.

Adds corresponding 2N-bit elements from two 128-bit NEON registers, then selects the high N bits of each result and stores them as N-bit elements in the destination 64-bit register. This instruction performs unsigned or signed addition at 2× the element width, then narrows the result. No flags are affected.

for i = 0 to pairs-1
  Dd[i] ← (Qn[i] + Qm[i])[2*N-1:N]


Summary: Adds N-bit elements, producing 2N-bit results.

Adds corresponding N-bit elements from two 64-bit NEON registers and produces 2N-bit results stored in a 128-bit register. This instruction performs widening addition, doubling the element width and producing twice as many result bits. No flags are affected.

for i = 0 to pairs-1
  Qd[i] ← Dn[i] + Dm[i]


Summary: Adds N-bit vector to 2N-bit vector.

Adds a 64-bit vector of N-bit elements to a 128-bit vector of 2N-bit elements, with the narrow operand implicitly widened before addition. The result is stored in the 128-bit destination. This instruction combines widening and addition in a single operation. No flags are affected.

for i = 0 to pairs-1
  Qd[i] ← Qn[i] + widen(Dm[i])


Summary: Bitwise AND of two vectors.

Performs bitwise AND on corresponding bits of two 128-bit NEON registers and stores the result in the destination register. This instruction is data-type agnostic and operates on the bit patterns directly. No flags are affected.


Summary: ANDs Vd with NOT of Vm (Vd & ~Vm).

Performs bitwise AND of the first operand with the bitwise NOT of the second operand (Qd ← Qn AND NOT Qm), storing the result in the destination register. This clears bits in Qn where the corresponding bits in Qm are set. No flags are affected.


Summary: Inserts bits from Vm into Vd where Vn (mask) is 0.

Selectively inserts bits from Qm into Qd where the corresponding bits in Qn (the mask) are 0. Where mask bits are 1, the original Qd bits are retained. This is a masked insert operation. No flags are affected.

for i = 0 to 127
  if Qn[i] == 0 then Qd[i] ← Qm[i]


Summary: Inserts bits from Vm into Vd where Vn (mask) is 1.

Selectively inserts bits from Qm into Qd where the corresponding bits in Qn (the mask) are 1. Where mask bits are 0, the original Qd bits are retained. This is the complement of VBIF. No flags are affected.

for i = 0 to 127
  if Qn[i] == 1 then Qd[i] ← Qm[i]


Summary: Selects bits from Vn or Vm based on Vd (mask).

Performs a bit-select operation using Qd as the mask: selects bits from Qn where Qd bits are 1 and from Qm where Qd bits are 0. The result is stored in Qd. This implements the operation Qd ← (Qd AND Qn) OR (NOT Qd AND Qm). No flags are affected.

for i = 0 to 127
  if Qd[i] == 1 then Qd[i] ← Qn[i] else Qd[i] ← Qm[i]


Summary: Sets destination bits to all 1s if elements equal, else 0s.

Vector Compare Equal performs element-wise equality comparison on 128-bit SIMD registers. For each element in Qn and Qm, if they are equal, the corresponding element in Qd is set to all 1s; otherwise, it is set to all 0s. No condition flags are affected. This is a NEON instruction available in both A32 and T32 states.

for i = 0 to (128 / element_size) - 1 do
  if Qn[i] == Qm[i] then
    Qd[i] ← all_ones
  else
    Qd[i] ← all_zeros
  end if
end for


Summary: Compares elements (>=) and sets result mask.

Vector Compare Greater Than or Equal performs signed element-wise comparison on 128-bit SIMD registers. For each element in Qn, if it is greater than or equal to the corresponding element in Qm, the result element in Qd is set to all 1s; otherwise, it is set to all 0s. No condition flags are affected. This is a NEON instruction available in both A32 and T32 states.

for i = 0 to (128 / element_size) - 1 do
  if Qn[i] >= Qm[i] then
    Qd[i] ← all_ones
  else
    Qd[i] ← all_zeros
  end if
end for


Summary: Compares elements (>) and sets result mask.

Vector Compare Greater Than performs signed element-wise comparison on 128-bit SIMD registers. For each element in Qn, if it is strictly greater than the corresponding element in Qm, the result element in Qd is set to all 1s; otherwise, it is set to all 0s. No condition flags are affected. This is a NEON instruction available in both A32 and T32 states.

for i = 0 to (128 / element_size) - 1 do
  if Qn[i] > Qm[i] then
    Qd[i] ← all_ones
  else
    Qd[i] ← all_zeros
  end if
end for


Summary: Compares elements (<=). Alias for VCGE with swapped operands.

Vector Compare Less Than or Equal is an alias that performs signed element-wise comparison on 128-bit SIMD registers with operands swapped relative to VCGE. For each element in Qn, if it is less than or equal to the corresponding element in Qm, the result element in Qd is set to all 1s; otherwise, it is set to all 0s. No condition flags are affected. This is a NEON instruction available in both A32 and T32 states.

for i = 0 to (128 / element_size) - 1 do
  if Qn[i] <= Qm[i] then
    Qd[i] ← all_ones
  else
    Qd[i] ← all_zeros
  end if
end for


Summary: Compares elements (<). Alias for VCGT with swapped operands.

Vector Compare Less Than is an alias that performs signed element-wise comparison on 128-bit SIMD registers with operands swapped relative to VCGT. For each element in Qn, if it is strictly less than the corresponding element in Qm, the result element in Qd is set to all 1s; otherwise, it is set to all 0s. No condition flags are affected. This is a NEON instruction available in both A32 and T32 states.

for i = 0 to (128 / element_size) - 1 do
  if Qn[i] < Qm[i] then
    Qd[i] ← all_ones
  else
    Qd[i] ← all_zeros
  end if
end for


Summary: Counts number of consecutive sign bits.

Vector Count Leading Sign Bits counts the number of consecutive sign bits (bits matching the sign bit) in each element of the source register. For each integer element in Qm, the result in Qd is the count of leading sign bits. The data type determines element size (8, 16, or 32 bits). No condition flags are affected. This is a NEON instruction available in both A32 and T32 states.

for i = 0 to (128 / element_size) - 1 do
  sign_bit ← Qm[i] >> (element_size - 1)
  count ← 0
  for j = element_size - 2 downto 0 do
    if (Qm[i] >> j) & 1 == sign_bit then
      count ← count + 1
    else
      break
    end if
  end for
  Qd[i] ← count
end for


Summary: Counts number of consecutive zeros.

Vector Count Leading Zeros counts the number of consecutive zero bits from the most significant bit in each element of the source register. For each integer element in Qm, the result in Qd is the count of leading zeros. The data type determines element size (8, 16, or 32 bits). No condition flags are affected. This is a NEON instruction available in both A32 and T32 states.

for i = 0 to (128 / element_size) - 1 do
  count ← 0
  for j = element_size - 1 downto 0 do
    if (Qm[i] >> j) & 1 == 0 then
      count ← count + 1
    else
      break
    end if
  end for
  Qd[i] ← count
end for


Summary: Population count (number of 1s) per byte.

Vector Count Set Bits (population count) counts the number of set (1) bits in each 8-bit element of the source register. For each byte element in Qm, the result in Qd is the count of set bits within that byte. The data type is always .8 (8-bit elements). No condition flags are affected. This is a NEON instruction available in both A32 and T32 states.

for i = 0 to 15 do
  count ← 0
  for j = 0 to 7 do
    if (Qm[8*i + j] & (1 << j)) != 0 then
      count ← count + 1
    end if
  end for
  Qd[8*i..8*i+7] ← count
end for


Summary: Duplicates a scalar value to all lanes of a vector.

Duplicates a scalar value from a lane of a NEON register to all lanes of a destination vector. The scalar is extracted from the indexed lane of Dm based on the element size, then broadcast to fill all lanes of Qd. No condition flags are affected. This is an ARMv7 Advanced SIMD (NEON) instruction, executable in both A32 and T32 states.

lane_index ← imm4
element_size ← dt_in_bits
scalar_value ← Dm[lane_index]
for i = 0 to (128 / element_size - 1)
  Qd[i] ← scalar_value


Summary: Bitwise XOR of two vectors.

Performs a bitwise exclusive OR (XOR) of corresponding lanes in two 128-bit NEON vectors and stores the result in the destination. Each lane of Qn is XORed with the corresponding lane of Qm, producing Qd. No condition flags are affected. This is an ARMv7 Advanced SIMD instruction, executable in both A32 and T32 states.

for i = 0 to 127
  Qd[i] ← Qn[i] XOR Qm[i]


Summary: Extracts a new vector from a pair of vectors (Sliding window).

Extracts a contiguous sequence of bytes from the concatenation of two 128-bit NEON vectors and stores the result in the destination. The vectors Qn and Qm are logically concatenated, then bytes [imm:imm+15] are extracted to form Qd. All operations are on 8-bit granularity. No condition flags are affected. This is an ARMv7 Advanced SIMD instruction, executable in both A32 and T32 states.


Summary: Add elements and shift right by 1 (Average).

Adds corresponding elements of two 128-bit NEON vectors and right-shifts the result by 1 bit (rounded toward zero), effectively computing the average. The operation is performed element-wise according to the data type. No condition flags are affected. This is an ARMv7 Advanced SIMD instruction, executable in both A32 and T32 states.

for each lane i of size specified by dt
  sum ← Qn[i] + Qm[i]
  Qd[i] ← sum >> 1


Summary: Subtract elements and shift right by 1.

Subtracts corresponding elements of two 128-bit NEON vectors and right-shifts the result by 1 bit (rounded toward zero). The operation is performed element-wise according to the data type. No condition flags are affected. This is an ARMv7 Advanced SIMD instruction, executable in both A32 and T32 states.

for each lane i of size specified by dt
  diff ← Qn[i] - Qm[i]
  Qd[i] ← diff >> 1