Summary: Performs the first part of the AES-128/192/256 key schedule generation (RV64).

AES64KS1I performs the first step of the AES-128/192/256 key schedule, applying SubWord, RotWord, and XOR with a round constant (Rcon[imm]) to rs1.


Summary: Performs the second part of the AES-192/256 key schedule generation (RV64).

AES64KS2 performs the second step of the AES-256 key schedule, XORing rs1 with the appropriate bytes of rs2.


Summary: Performs the Inverse MixColumns transformation for AES decryption (RV64).

AES64IM applies the AES InvMixColumns transformation to the 64-bit value in rs1 and writes the result to rd. Used to convert round keys for equivalent inverse cipher.


Wait on Reservation Set (Normal Time-Out)

Summary: Stalls the hart until a reservation set is invalid or a short timeout expires. Used for efficient polling/spinlocks.

while (reservation_valid() && !timeout) { pause(); }

WRS.NTO (Wait on Reservation Set, No Timeout) causes the hart to pause until the reservation set established by an LR instruction is invalidated or an interrupt or trap is pending. Unlike WFI, it is expected to resume on any reservation invalidation.


Wait on Reservation Set (Short Time-Out)

Summary: Stalls the hart until a reservation set is invalid or a very short implementation-defined timeout expires.

while (reservation_valid() && !short_timeout) { pause(); }

WRS.STO (Wait on Reservation Set, Short Timeout) behaves like WRS.NTO but may optionally time out after an implementation-defined short period, allowing the hart to poll the reservation set.


Summary: Orders previous stores against subsequent local instruction fetches or translations (Memory Management).

SFENCE.W.INVAL, when used with SFENCE.INVAL.IR, provides fine-grained virtual memory management. It ensures that all stores preceding this instruction are ordered before any subsequent SFENCE.INVAL.IR.


Summary: Invalidates a range of address translations based on ASID and Virtual Address.

SFENCE.INVAL.IR invalidates all address-translation cache entries that match stores ordered before a preceding SFENCE.W.INVAL on the same hart.


Non-Temporal Locality Hint (Prefetch Level 1)

Summary: Hint that the target cache block will be needed, but is likely to be discarded after use (Stream data).

NTL.P1 hints that the following memory instruction has low temporal locality at the innermost cache level (L1). Implementations may bypass L1 on the memory access.


Summary: Hint that the target data should not be cached in any level of the cache hierarchy (Transient data).

NTL.PALL hints that the following memory instruction has low temporal locality at all private cache levels. Implementations may bypass all private caches.


Non-Temporal Locality Hint (Store Level 1)

Summary: Hint that the subsequent store is non-temporal (Streaming Store).

NTL.S1 hints that the following memory instruction has low temporal locality at the innermost shared cache level.


Summary: Hint that the subsequent store should bypass all cache levels.

NTL.ALL hints that the following memory instruction has low temporal locality at all cache levels. Implementations may bypass all caches.


Summary: Adds N-bit elements to produce 2*N-bit results (Widening).

foreach(i < vl): vd[i] = sext(vs1[i]) + sext(vs2[i]);

Performs a widening operation, producing results twice as wide as the source elements. Results are written to vd using 2× the element grouping (EEW). The number of elements and masking are governed by vl and vm.


Summary: Adds unsigned N-bit elements to produce unsigned 2*N-bit results.

foreach(i < vl): vd[i] = zext(vs1[i]) + zext(vs2[i]);


Summary: Subtracts N-bit elements to produce 2*N-bit results.

foreach(i < vl): vd[i] = sext(vs2[i]) - sext(vs1[i]);


Summary: Multiplies N-bit elements to produce 2*N-bit results.

foreach(i < vl): vd[i] = sext(vs2[i]) * sext(vs1[i]);


Summary: Shifts 2*N-bit elements right and narrows the result to N-bits.

foreach(i < vl): vd[i] = (vs2[i] >> rs1) & Mask(SEW);

Performs a narrowing operation, halving the result element width relative to the source. Optionally saturates the result. Active elements are determined by vl; masking by vm.


Summary: Arithmetically shifts 2*N-bit elements right and narrows to N-bits.

foreach(i < vl): vd[i] = (vs2[i] >>s rs1) & Mask(SEW);


Summary: Merges two vectors based on the mask (if mask=0, pick vs2; if mask=1, pick vs1).

foreach(i < vl): vd[i] = v0[i] ? vs1[i] : vs2[i];

Merges elements from vs1 and vs2 (or an immediate) according to the mask: masked-on elements come from vs1, masked-off from vs2.


Summary: Copies a vector register.

Copies vector vs1 to vd under mask vm.


Summary: Copies element 0 of a vector to an integer register.

Moves element 0 of vector vs2 to GPR rd.


Summary: Copies an integer register to element 0 of a vector.

Moves a scalar integer value from GPR rs1 into element 0 of vd.


Summary: Compares float vectors for equality, writing result to mask register.

Compares elements element-wise for equal and writes a mask result to vd.


Summary: Compares float vectors (vs2 <= vs1), writing result to mask register.

Compares elements element-wise for less than or equal and writes a mask result to vd.


Summary: Compares float vectors (vs2 < vs1), writing result to mask register.

Compares elements element-wise for less than and writes a mask result to vd.


Summary: Classifies elements of a float vector (NaN, Inf, etc.).

foreach(i < vl): vd[i] = classify(vs2[i]);

Classifies each floating-point element (NaN, infinity, zero, normal, subnormal, negative/positive), writing a bitmask classification to vd.


Summary: Moves element 0 of a float vector to a scalar float register.

Moves element 0 of vector vs2 to floating-point register fd.


Summary: Moves a scalar float register to element 0 of a vector.

Moves floating-point scalar fs1 into element 0 of vd.


Summary: Loads a common floating-point constant (e.g., 1.0, 0.5, PI) into a register from a small table.

Loads a single-precision (32-bit) floating-point constant from a predefined lookup table (indexed by rs1) into fd. Provides common constants such as -1, 0, 1, 2, ∞, and others without a memory access.


Summary: Loads a common double-precision constant into a register.

Loads a double-precision (64-bit) floating-point constant from a predefined lookup table (indexed by rs1) into fd. Provides common constants such as -1, 0, 1, 2, ∞, and others without a memory access.


Summary: Loads a common half-precision constant into a register.

Loads a half-precision (16-bit) floating-point constant from a predefined lookup table (indexed by rs1) into fd. Provides common constants such as -1, 0, 1, 2, ∞, and others without a memory access.


Summary: Minimum of two floats, treating -0.0 as smaller than +0.0 (canonicalize NaNs).

Returns the single-precision (32-bit) floating-point minimum of rs1 and rs2, following IEEE 754-2019 minNum/maxNum semantics. Quiet NaN inputs return the non-NaN operand; signalling NaN inputs raise invalid-operation.


Summary: Maximum of two floats, treating +0.0 as larger than -0.0.

Returns the single-precision (32-bit) floating-point maximum of rs1 and rs2, following IEEE 754-2019 minNum/maxNum semantics. Quiet NaN inputs return the non-NaN operand; signalling NaN inputs raise invalid-operation.


Summary: Rounds a float to the nearest integer value (returned as a float).

Rounds the single-precision (32-bit) floating-point value in rs1 to an integer value (still in FP format), using the rounding mode in the rm field. The result preserves the FP type.


Summary: Atomically compares memory at rs1 with rd; if equal, writes rs2 to memory. Returns original value in rd.

atomic { if(M[rs1]==R[rd]) M[rs1]=R[rs2]; R[rd]=M[rs1]; }

AMOCAS.W (Zacas) atomically compares the word at the address in rs1 with rs1 (the compare value), and if equal, writes rs2 to that address. The original value is returned in rd.


Summary: Atomically compares 64-bit memory at rs1 with rd; if equal, writes rs2 to memory.

AMOCAS.D atomically compares a doubleword in memory with a register pair and conditionally swaps it with another register pair (RV64 only).


Summary: Performs 32-bit multiplication (rd = rd * rs2) in 16-bit encoding.

Multiplies rd′ and rs2′, writing the lower XLEN bits of the product to rd′ (Zcb).


Summary: Zero extends the lowest byte of rd' to XLEN.

Zero-extends the least-significant byte of rd′ in place (Zcb).


Summary: Sign extends the lowest byte of rd' to XLEN.

Sign-extends the least-significant byte of rd′ in place (Zcb).


Summary: Computes bitwise logical negation.

Bitwise logical NOT of rd′; writes to rd′ (Zcb). Equivalent to XORI rd′, -1.


Summary: Accelerates the SM4 block cipher (encryption/decryption round).

SM4ED performs one round of the SM4 block cipher encryption/decryption by applying the S-box and linear transformation to four bytes from rs2, XORing with rs1, and accumulating into rd.


Summary: Accelerates the SM4 key schedule generation.

SM4KS performs one step of the SM4 key schedule by applying the S-box and key-schedule linear transformation to four bytes from rs2, XORing with rs1, and accumulating into rd.


Summary: Performs the P0 permutation for the SM3 hash algorithm.

SM3P0 applies the SM3 P0 permutation function to rs1 and writes to rd. Used in the key schedule and compression function of the Chinese SM3 hash algorithm.


Summary: Performs the P1 permutation for the SM3 hash algorithm.

SM3P1 applies the SM3 P1 permutation function to rs1 and writes to rd. Used in message expansion of the SM3 hash algorithm.


Summary: Pushes multiple registers (ra, s0-s11) to the stack and adjusts sp. Critical for small code size.

CM.PUSH (Zcmp) saves a set of registers to the stack and decrements sp by a stack-frame size. The register list and stack adjustment are encoded in the instruction. Used as a function prologue.


Summary: Pops multiple registers from the stack and restores sp.

CM.POP (Zcmp) restores a set of registers from the stack, increments sp by the matching stack-frame size, and returns. Used as a function epilogue.


Summary: Sets the vector length (VL) based on the application vector length (AVL) in rs1 and configuration in rs2.

Sets the vector length (vl) and vector type (vtype) registers based on the requested application vector length (AVL) and element width/grouping. The actual vector length set is written to rd. vtype encodes SEW (element width), LMUL (register grouping), and tail/mask policies.


Summary: Zeros a cache block corresponding to the address in rs1.

CBO.ZERO writes zeros to the cache block containing the effective address. Typically faster than a sequence of store instructions for zeroing memory.


Summary: Converts a single-precision floating-point number to a signed 32-bit integer.

Converts between floating-point types or between floating-point and integer. Result is rounded according to the dynamic rounding mode. Invalid conversions produce the IEEE default NaN or the appropriate integer saturation value.


Summary: Converts a signed 32-bit integer to a single-precision floating-point number.


Summary: Converts a single-precision float to a double-precision float.


Summary: Converts a double-precision float to a single-precision float.


Summary: Injects the sign of rs2 into rs1. Used to copy values or manipulate signs.

Produces a result with the magnitude of rs1 and the sign bit taken from the source rs2. Used to implement floating-point absolute value, negate, and copy-sign.


Summary: Injects the *negated* sign of rs2 into rs1. Used for negation and absolute value.


Summary: Injects the XOR of signs of rs1 and rs2. Used to copy sign.

Logic similar to Abs(f1) if f2 is properly set.


Summary: Sets integer rd to 1 if float rs1 equals float rs2, else 0.

Performs a single-precision (32-bit) floating-point equality comparison and writes 1 (true) or 0 (false) to integer rd. NaN inputs produce 0 (unordered), except FEQ which raises invalid-operation if either operand is a signalling NaN.


Summary: Sets integer rd to 1 if float rs1 is less than float rs2, else 0.

Performs a single-precision (32-bit) floating-point less-than comparison and writes 1 (true) or 0 (false) to integer rd. NaN inputs produce 0 (unordered), except FEQ which raises invalid-operation if either operand is a signalling NaN.


Summary: Sets integer rd to 1 if float rs1 is less than or equal to float rs2, else 0.

Performs a single-precision (32-bit) floating-point less-than-or-equal comparison and writes 1 (true) or 0 (false) to integer rd. NaN inputs produce 0 (unordered), except FEQ which raises invalid-operation if either operand is a signalling NaN.


Summary: Moves the bit pattern of a floating-point register to an integer register.

Moves bits from a floating-point register to an integer register (or vice versa) without conversion. The bit pattern is preserved exactly.


Summary: Moves the bit pattern of an integer register to a floating-point register.


Summary: Multiplies elements of two floating-point vectors.

foreach(i < vl): vd[i] = vs1[i] * vs2[i];

Performs element-wise floating-point multiplication on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Divides elements of two floating-point vectors.

foreach(i < vl): vd[i] = vs1[i] / vs2[i];

Performs element-wise floating-point division on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Computes the square root of elements in a floating-point vector.

Performs element-wise FP square root on operands, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Computes (vs1 * vs2) + vd (overwriting vd) with single rounding.

foreach(i < vl): vd[i] = (vs1[i] * vs2[i]) + vd[i];

Performs element-wise FP fused multiply-add on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Writes the smaller of two floating-point vector elements to vd.

foreach(i < vl): vd[i] = min(vs1[i], vs2[i]);

Performs element-wise FP min on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Writes the larger of two floating-point vector elements to vd.

foreach(i < vl): vd[i] = max(vs1[i], vs2[i]);

Performs element-wise FP max on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Injects the sign of vs2 into vs1 (Copy Sign).

foreach(i < vl): vd[i] = copy_sign(vs1[i], vs2[i]);

Injects the sign of one FP element into the magnitude of another, implementing sign copy, negate, or XOR operations.


Summary: Adds elements with signed saturation (clips to Max/Min instead of wrapping).

foreach(i < vl): vd[i] = saturate_s(vs1[i] + vs2[i]);

Performs element-wise signed saturating add on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Subtracts elements with signed saturation.

foreach(i < vl): vd[i] = saturate_s(vs1[i] - vs2[i]);

Performs element-wise signed saturating subtract on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Vector Averaging Add: Computes (vs1 + vs2) >> 1 with rounding. Operation: foreach(i < vl): vd[i] = (vs1[i] + vs2[i] + 1) >> 1;.


Summary: Compacts elements from source vector into contiguous elements in dest where the mask is 1.

idx = 0; foreach(i < vl): if vs1[i]: vd[idx++] = vs2[i];

Compresses active (masked) elements of vs2 into the low elements of vd, discarding masked-off elements.


Summary: Performs 16-bit floating-point subtraction.

Performs half-precision (16-bit) floating-point subtraction. The operation subtracts the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.


Summary: Performs 16-bit floating-point multiplication.

Performs half-precision (16-bit) floating-point multiplication. The operation multiplies the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.


Summary: Performs 16-bit floating-point division.

Performs half-precision (16-bit) floating-point division. The operation divides the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.


Summary: Computes the square root of a 16-bit floating-point number.

Stores a floating-point register to memory at address rs1+sext(offset).


Summary: Writes the smaller of two 16-bit floating-point values to rd.

Returns the half-precision (16-bit) floating-point minimum of rs1 and rs2, following IEEE 754-2019 minNum/maxNum semantics. Quiet NaN inputs return the non-NaN operand; signalling NaN inputs raise invalid-operation.


Summary: Writes the larger of two 16-bit floating-point values to rd.

Returns the half-precision (16-bit) floating-point maximum of rs1 and rs2, following IEEE 754-2019 minNum/maxNum semantics. Quiet NaN inputs return the non-NaN operand; signalling NaN inputs raise invalid-operation.


Summary: Computes (rs1 * rs2) + rs3 with single rounding (16-bit).

Performs half-precision (16-bit) floating-point fused multiply-add. The operation computes fused multiply-add on the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.


Summary: Computes (rs1 * rs2) - rs3 with single rounding (16-bit).

Performs half-precision (16-bit) floating-point fused multiply-subtract. The operation computes fused multiply-subtract on the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.


Summary: Computes -(rs1 * rs2) - rs3 with single rounding (16-bit).

Performs half-precision (16-bit) floating-point fused negate-multiply-add. The operation computes fused negate-multiply-add on the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.


Float Negated Fused Multiply-Subtract (Half)

Summary: Computes -(rs1 * rs2) + rs3 with single rounding (16-bit).

Performs half-precision (16-bit) floating-point fused negate-multiply-subtract. The operation computes fused negate-multiply-subtract on the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.


Summary: Sets integer rd to 1 if half-precision rs1 equals rs2, else 0.

Performs a half-precision (16-bit) floating-point equality comparison and writes 1 (true) or 0 (false) to integer rd. NaN inputs produce 0 (unordered), except FEQ which raises invalid-operation if either operand is a signalling NaN.


Summary: Sets integer rd to 1 if half-precision rs1 is less than rs2, else 0.

Performs a half-precision (16-bit) floating-point less-than comparison and writes 1 (true) or 0 (false) to integer rd. NaN inputs produce 0 (unordered), except FEQ which raises invalid-operation if either operand is a signalling NaN.


Summary: Sets integer rd to 1 if half-precision rs1 is less than or equal to rs2, else 0.

Performs a half-precision (16-bit) floating-point less-than-or-equal comparison and writes 1 (true) or 0 (false) to integer rd. NaN inputs produce 0 (unordered), except FEQ which raises invalid-operation if either operand is a signalling NaN.


Summary: Examines a 16-bit floating-point number and generates a classification bitmask.

Classifies the half-precision (16-bit) floating-point value in rs1, writing a 10-bit one-hot result to integer rd. Bits represent: negative infinity, negative normal, negative subnormal, negative zero, positive zero, positive subnormal, positive normal, positive infinity, signalling NaN, quiet NaN.


Summary: Injects the sign of rs2 into rs1 (16-bit).

Produces a result with the magnitude of rs1 and the sign bit taken from the source rs2. Used to implement floating-point absolute value, negate, and copy-sign.


Summary: Injects the negated sign of rs2 into rs1 (16-bit).


Summary: Injects the XOR of signs of rs1 and rs2 (16-bit).


Summary: Converts a 16-bit floating-point number to a 32-bit signed integer.

Converts between floating-point types or between floating-point and integer. Result is rounded according to the dynamic rounding mode. Invalid conversions produce the IEEE default NaN or the appropriate integer saturation value.


Summary: Converts a 16-bit floating-point number to a 32-bit unsigned integer.


Summary: Converts a 32-bit signed integer to a 16-bit floating-point number.


Summary: Converts a 32-bit unsigned integer to a 16-bit floating-point number.


Vector Narrowing Clip (Arithmetic Shift)

Summary: Shifts elements right, rounds, and clips (saturates) the result to the destination width. Critical for Quantization.

foreach(i < vl): vd[i] = clip(round(vs2[i] >> vs1[i]));

Performs a narrowing operation, halving the result element width relative to the source. Optionally saturates the result. Active elements are determined by vl; masking by vm.


Vector Narrowing Clip Unsigned (Immediate)

Summary: Shifts right (logical), rounds, and clips to unsigned destination. Used for pixel packing.

foreach(i < vl): vd[i] = clip_u(round(vs2[i] >>u imm));


Summary: Converts floating-point elements to signed integers.

foreach(i < vl): vd[i] = float_to_int(vs2[i]);

Converts vector elements between floating-point and integer types, or between floating-point precisions. Conversions respect the active rounding mode.


Summary: Converts signed integer elements to floating-point.

foreach(i < vl): vd[i] = int_to_float(vs2[i]);


Vector Widening Integer to Float Convert

Summary: Converts N-bit integers to 2*N-bit floats (e.g., Int16 -> FP32).

foreach(i < vl): vd[i] = int_to_wide_float(vs2[i]);

Performs a widening operation, producing results twice as wide as the source elements. Results are written to vd using 2× the element grouping (EEW). The number of elements and masking are governed by vl and vm.


Summary: Converts 2*N-bit floats to N-bit floats (e.g., FP32 -> FP16).

foreach(i < vl): vd[i] = narrow_float(vs2[i]);


Vector Float Reciprocal Estimate 7-bit: Computes an estimate of 1/x (7-bit precision). Used for fast division/normalization loops. Operation: foreach(i < vl): vd[i] = approx_reciprocal(vs2[i]);.


Vector Float Reciprocal Sqrt Estimate 7-bit: Computes an estimate of 1/sqrt(x). Critical for vector normalization. Operation: foreach(i < vl): vd[i] = approx_rsqrt(vs2[i]);.


Vector Add with Carry (Produce Mask): Adds two vectors and a carry-in, producing the carry-out to the destination mask. Operation: foreach(i < vl): vd[i] = carry_out(vs1[i] + vs2[i] + v0[i]);.


Vector Subtract with Borrow: Subtracts two vectors minus a borrow-in from the mask register. Operation: foreach(i < vl): vd[i] = vs1[i] - vs2[i] - v0[i];.


Vector Integer Multiply-Accumulate: Computes vd = vd + (vs1 * vs2). Essential for dot products. Operation: foreach(i < vl): vd[i] = vd[i] + (vs1[i] * vs2[i]);.


Vector Integer Negative Multiply-Subtract

Summary: Computes vd = -(vd - (vs1 * vs2)).


Summary: Performs signed saturating multiplication, keeping the high half of the product (Fixed-point support).

foreach(i < vl): vd[i] = (sext(vs1[i]) * sext(vs2[i])) >> (SEW-1);

Performs a vector mask register store of element-sized-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.


Summary: Reduces a vector to a scalar by finding the maximum signed element.

Performs a vector reduction: applies the operation across all active elements of vs2, using vs1[0] as the initial accumulator, and writes the scalar result to vd[0]. Active elements are determined by vl.


Summary: Reduces a vector to a scalar by finding the minimum signed element.


Summary: Reduces a vector to a scalar using bitwise AND.


Summary: Reduces a vector to a scalar using bitwise OR.


Summary: Adds N-bit floats to produce 2*N-bit float results (e.g., FP16 + FP16 -> FP32).

foreach(i < vl): vd[i] = extend(vs1[i]) + extend(vs2[i]);


Summary: Multiplies N-bit floats to produce 2*N-bit float results.

foreach(i < vl): vd[i] = extend(vs1[i]) * extend(vs2[i]);


Summary: Reduces a float vector to a scalar by summing elements (Order not preserved, faster).

vd[0] = vs1[0] + sum(vs2[*]); // Non-deterministic order


Summary: Reduces a float vector to a scalar by finding the maximum element.


Vector Mask Set Before First: Writes a mask where bits are 1 before the first element in vs2 that is 1. Operation: Sets mask bits to 1 up to (but not including) the first set bit in vs2..


Summary: Moves rs1 to rd if rs2 is non-zero, otherwise sets rd to zero.

CZERO.EQZ conditionally zeroes rd: it writes zero to rd if rs2 equals zero, otherwise writes the value of rs1 to rd. Useful for branch-free conditional selection.


Summary: Moves rs1 to rd if rs2 is zero, otherwise sets rd to zero.

CZERO.NEZ conditionally zeroes rd: it writes zero to rd if rs2 is non-zero, otherwise writes rs1 to rd. Useful for branch-free conditional selection.


Summary: Hints that the current hart is in a spin-wait loop, allowing the hardware to reduce power consumption or yield resources.

PAUSE is a hint instruction that may stall the pipeline for an implementation-defined short period. It is intended to reduce energy consumption in spin-wait loops.


Summary: Performs a clean operation on the cache block containing the effective address.

CBO.CLEAN performs a clean operation on a cache block containing the effective address computed from rs1. It writes back the contents of the cache block to memory if dirty, but retains the block in the cache.


Summary: Performs a flush (clean + invalidate) operation on the cache block.

CBO.FLUSH cleans and then invalidates the cache block containing the effective address. The block's contents are written back to memory if dirty, then the block is evicted from the cache.


Summary: Performs an invalidate operation on the cache block.

Discard cache line (data lost if dirty).

CBO.INVAL invalidates the cache block containing the effective address, removing it from the cache without writing back dirty data. This is a hint; the implementation may write back dirty data.


Summary: Reads the lower 32/64 bits of the cycle counter.

RDCYCLE reads the cycle CSR, which counts the number of clock cycles executed by the processor. It is an assembler pseudoinstruction for CSRRS rd, cycle, x0.


Summary: Reads the lower 32/64 bits of the real-time clock.

RDTIME reads the time CSR, which reflects the current value of the real-time counter. It is an assembler pseudoinstruction for CSRRS rd, time, x0.


Summary: Reads the count of instructions retired (completed).

RDINSTRET reads the instret CSR, which counts the number of instructions retired by the processor. It is an assembler pseudoinstruction for CSRRS rd, instret, x0.


Summary: Performs no operation. Used for alignment or timing delays.

NOP does not change any architecturally visible state except advancing the PC. It is canonically encoded as ADDI x0, x0, 0.


Summary: Copies the value of one register into another.

MV copies the value of rs1 into rd. It is an assembler pseudoinstruction for ADDI rd, rs1, 0.


Summary: Loads an arbitrary immediate value into a register.

Expands to: LUI x5, 0x12; ADDI x5, x5, 0x345

LI loads an arbitrary immediate value into rd using one or two instructions (LUI+ADDI for 32-bit, or longer for 64-bit). It is an assembler pseudoinstruction.


Summary: Returns from a subroutine call.

Jumps to the address in the Return Address register (ra/x1).

RET returns from a subroutine by jumping to the address in x1 (ra). It is a pseudoinstruction for JALR x0, 0(x1).


Summary: Unconditionally jumps to a target offset.

Unconditional jump (discarding return address).

J performs an unconditional jump to a PC-relative offset. It is a pseudoinstruction for JAL x0, offset.


Summary: Unconditionally jumps to an address held in a register.

JR performs an unconditional indirect jump to the address in rs1. It is a pseudoinstruction for JALR x0, 0(rs1).


Summary: Calls a function by jumping to an address and saving the return address.

CALL calls a far subroutine using a two-instruction AUIPC+JALR sequence, saving the return address in x1 (ra).


Summary: Computes the bitwise logical negation (one's complement).

NOT performs a bitwise logical NOT of rs1 and writes to rd. It is a pseudoinstruction for XORI rd, rs1, -1.


Summary: Computes the two's complement negation (arithmetic negative).

NEG negates rs1 and writes to rd. It is a pseudoinstruction for SUB rd, x0, rs1.


Summary: Branches if the register is zero.

BEQZ branches to the target if rs1 equals zero. It is a pseudoinstruction for BEQ rs1, x0, offset.


Summary: Branches if the register is not zero.

BNEZ branches to the target if rs1 is non-zero. It is a pseudoinstruction for BNE rs1, x0, offset.


Summary: Sets rd to 1 if rs is zero, otherwise 0.

SEQZ writes 1 to rd if rs1 equals zero, and 0 otherwise. It is a pseudoinstruction for SLTIU rd, rs1, 1.


Summary: Sets rd to 1 if rs is not zero, otherwise 0.

SNEZ writes 1 to rd if rs1 is non-zero, and 0 otherwise. It is a pseudoinstruction for SLTU rd, x0, rs1.


Summary: Performs one round of AES-128 encryption key schedule generation.

R[rd] = aes_encrypt_schedule(R[rs1], R[rs2]);

AES64ES performs two phases of the AES forward SubBytes and ShiftRows transformation. Used in AES encryption.


Summary: Performs one round of AES-128 decryption key schedule generation.

R[rd] = aes_decrypt_schedule(R[rs1], R[rs2]);

AES64DS performs two phases of the AES block cipher inverse SubBytes and ShiftRows transformation on 64-bit halves of the round state. Used in AES decryption.


Summary: Performs the Sigma0 transformation function for SHA-256.

SHA256SIG0 computes the sigma_0 mixing function for SHA-256, applying a combination of rotate-right and shift operations to rs1.


Summary: Performs the Sum0 transformation function for SHA-256.

SHA256SUM0 computes the sum-0 mixing function (Sigma-0 capital) for SHA-256 message scheduling.


Summary: Converts a single-precision float to a 32-bit unsigned integer.

Converts between floating-point types or between floating-point and integer. Result is rounded according to the dynamic rounding mode. Invalid conversions produce the IEEE default NaN or the appropriate integer saturation value.


Summary: Converts a 32-bit unsigned integer to a single-precision float.


Summary: Converts a double-precision float to a 32-bit signed integer.


Summary: Converts a 32-bit signed integer to a double-precision float.


Summary: Shifts rs1 left by 1 and adds rs2. Used for calculating addresses of 16-bit elements.

SH1ADD shifts rs1 left by 1 bit, then adds the result to rs2, writing to rd. Used for stride-1 array indexing (byte element + base).


Summary: Shifts rs1 left by 2 and adds rs2. Used for calculating addresses of 32-bit elements.

SH2ADD shifts rs1 left by 2 bits, then adds to rs2, writing to rd. Used for stride-4 array indexing (e.g., int32 arrays).


Summary: Shifts rs1 left by 3 and adds rs2. Used for calculating addresses of 64-bit elements.

SH3ADD shifts rs1 left by 3 bits, then adds to rs2, writing to rd. Used for stride-8 array indexing (e.g., int64 arrays).


Summary: Zero-extends the lower 32 bits of rs1 and adds it to rs2. Useful for 64-bit address calculations with 32-bit unsigned indices.

ADD.UW zero-extends the lower 32 bits of rs1 to XLEN bits, adds the result to rs2, and writes to rd. Used for pointer arithmetic with zero-extended 32-bit offsets.


Summary: Sets a single bit in rs1 at the index specified by rs2.

BSET sets the single bit of rs1 selected by the lower log2(XLEN) bits of rs2, writing the result to rd.


Summary: Sets a single bit in rs1 at the index specified by an immediate.

BSETI sets the single bit of rs1 selected by the immediate, writing the result to rd.


Summary: Clears a single bit in rs1 at the index specified by rs2.

BCLR clears the single bit of rs1 selected by the lower log2(XLEN) bits of rs2, writing the result to rd.


Summary: Clears a single bit in rs1 at the index specified by an immediate.

BCLRI clears the single bit of rs1 selected by the immediate, writing the result to rd.


Summary: Inverts (toggles) a single bit in rs1 at the index specified by rs2.

BINV inverts the single bit of rs1 selected by the lower log2(XLEN) bits of rs2, writing the result to rd.


Summary: Inverts (toggles) a single bit in rs1 at the index specified by an immediate.

BINVI inverts the single bit of rs1 selected by the immediate, writing the result to rd.


Summary: Extracts the value of a single bit (0 or 1) at the index specified by rs2. The result is placed in the LSB of rd.

BEXT extracts the single bit of rs1 selected by the lower log2(XLEN) bits of rs2, zero-extending to XLEN and writing to rd.


Summary: Extracts the value of a single bit (0 or 1) at the index specified by an immediate.

BEXTI extracts the single bit of rs1 selected by the immediate, zero-extending to XLEN and writing to rd.


Summary: Performs carry-less multiplication of the lower bits of rs1 and rs2. Used for CRC and GCM (crypto).

CLMUL performs carry-less multiplication of rs1 and rs2, writing the lower XLEN bits of the carry-less product to rd. Used in GF(2^n) arithmetic and CRC computation.


Summary: Adds unsigned integers with saturation (clips to max instead of wrapping).

foreach(i < vl): vd[i] = saturate_u(vs1[i] + vs2[i]);

Performs element-wise unsigned saturating add on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Vector Saturating Integer Subtract Unsigned

Summary: Subtracts unsigned integers with saturation (clips to 0 instead of wrapping).

foreach(i < vl): vd[i] = saturate_u(vs1[i] - vs2[i]);

Performs element-wise unsigned saturating subtract on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Vector Averaging Add Unsigned: Computes (a + b + 1) >> 1 for unsigned integers. Operation: foreach(i < vl): vd[i] = (vs1[i] + vs2[i] + 1) >> 1;.


Vector Averaging Subtract Signed: Computes (a - b) >> 1 for signed integers. Operation: foreach(i < vl): vd[i] = (vs1[i] - vs2[i]) >> 1;.


Vector Averaging Subtract Unsigned: Computes (a - b) >> 1 for unsigned integers. Operation: foreach(i < vl): vd[i] = (vs1[i] - vs2[i]) >> 1;.


Vector Saturating Shift Right Arithmetic: Shifts right with sign extension and rounding/saturation logic. Operation: foreach(i < vl): vd[i] = saturate(vs2[i] >>s vs1[i]);.


Vector Saturating Shift Right Logical: Shifts right with zero extension and rounding/saturation logic. Operation: foreach(i < vl): vd[i] = saturate(vs2[i] >>u vs1[i]);.


Summary: Sums N-bit elements into a 2*N-bit scalar accumulator (Signed).

Performs a widening operation, producing results twice as wide as the source elements. Results are written to vd using 2× the element grouping (EEW). The number of elements and masking are governed by vl and vm.


Summary: Sums N-bit elements into a 2*N-bit scalar accumulator (Unsigned).


Summary: Computes vd = vs1 & ~vs2 (mask operation).

Performs element-wise mask AND on the mask registers vm1 and vm2, writing to vd.


Summary: Computes vd = vs1 | ~vs2 (mask operation).

Performs element-wise mask OR on the mask registers vm1 and vm2, writing to vd.


Summary: Computes vd = ~(vs1 ^ vs2) (mask operation).

Performs element-wise mask XNOR on the mask registers vm1 and vm2, writing to vd.


Summary: Computes the maximum of two unsigned integers.

MAXU computes the unsigned maximum of rs1 and rs2, writing the result to rd.


Summary: Computes the minimum of two unsigned integers.

MINU computes the unsigned minimum of rs1 and rs2, writing the result to rd.


Pack two words into a register: Packs the lower halves of rs1 and rs2 into rd. Operation: R[rd] = (R[rs2] << XLEN/2) | (R[rs1] & ((1 << XLEN/2)-1));.


Pack Byte: Packs the lower bytes of rs1 and rs2 into a 16-bit value. Operation: R[rd] = (R[rs2] << 8) | (R[rs1] & 0xFF);.


Summary: Loads a word from guest physical memory (unsigned).

HLV.WU performs a virtual-machine load of an unsigned word using VS-mode translation, zero-extending to 64 bits (RV64 only).


Summary: Loads a doubleword from guest physical memory.

HLV.D performs a virtual-machine load of a doubleword using VS-mode translation (RV64 only).


Summary: Stores a doubleword to guest physical memory.

HSV.D stores the doubleword in rs2 to the VS-mode virtual address in rs1 (RV64 only).


Vector Load Ordered Indexed (32-bit indices)

Summary: Loads elements using indices, ensuring order (useful for I/O buffers).

Performs a vector indexed ordered load of 32-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.


Vector Store Ordered Indexed (32-bit indices)

Summary: Stores elements using indices, ensuring order.

Performs a vector indexed ordered store of 32-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.


Summary: Multiplies signed integers and keeps the high N bits.

foreach(i < vl): vd[i] = (sext(vs1[i]) * sext(vs2[i])) >> SEW;

Performs element-wise high-half multiply signed on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Multiplies unsigned integers and keeps the high N bits.

foreach(i < vl): vd[i] = (zext(vs1[i]) * zext(vs2[i])) >> SEW;

Performs element-wise high-half multiply unsigned on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Divides signed vector elements.

foreach(i < vl): vd[i] = vs1[i] / vs2[i];

Performs element-wise signed integer division on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Divides unsigned vector elements.

foreach(i < vl): vd[i] = vs1[i] /u vs2[i];

Performs element-wise unsigned integer division on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Computes signed remainder.

foreach(i < vl): vd[i] = vs1[i] % vs2[i];

Performs element-wise signed remainder on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Computes unsigned remainder.

foreach(i < vl): vd[i] = vs1[i] %u vs2[i];

Performs element-wise unsigned remainder on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Computes vd = vd + (vs1 * vs2) with widening (N*N -> 2N + 2N).

foreach(i < vl): vd[i] = vd[i] + (sext(vs1[i]) * sext(vs2[i]));

Performs a widening operation, producing results twice as wide as the source elements. Results are written to vd using 2× the element grouping (EEW). The number of elements and masking are governed by vl and vm.


Vector Widening Multiply-Accumulate Unsigned

Summary: Computes vd = vd + (vs1 * vs2) widening unsigned.

foreach(i < vl): vd[i] = vd[i] + (zext(vs1[i]) * zext(vs2[i]));


Summary: Writes the index of the active element to the destination. Useful for parallel prefix sums.

count = 0; foreach(i < vl): if vm[i]: vd[i] = count++;

Writes to each element of vd the sum of set mask bits in vs2 at positions less than the current element index.


Summary: Writes the element index (0, 1, 2...) to the destination.

Writes the element index (0, 1, 2, …, vl-1) to each active element of vd.


Summary: Converts N-bit floats to 2*N-bit floats (e.g., FP16 -> FP32).

foreach(i < vl): vd[i] = convert_w(vs2[i]);


Summary: Converts N-bit float to 2*N-bit signed integer.

foreach(i < vl): vd[i] = f_to_x_w(vs2[i]);


Summary: Converts 2*N-bit float to N-bit signed integer.

foreach(i < vl): vd[i] = f_to_x_n(vs2[i]);

Converts vector elements between floating-point and integer types, or between floating-point precisions. Conversions respect the active rounding mode.


Vector Narrowing Shift Right Logical Immediate

Summary: Shifts wide elements right by immediate and narrows.

foreach(i < vl): vd[i] = (vs2[i] >>u imm) & Mask;

Performs a narrowing operation, halving the result element width relative to the source. Optionally saturates the result. Active elements are determined by vl; masking by vm.


Vector Narrowing Shift Right Arithmetic Immediate

Summary: Shifts wide elements right (arithmetic) by immediate and narrows.

foreach(i < vl): vd[i] = (vs2[i] >>s imm) & Mask;


Summary: Examines the value in a float register and generates a 10-bit bitmask indicating its class (NaN, Inf, Zero, Normal, etc.).

Classifies the single-precision (32-bit) floating-point value in rs1, writing a 10-bit one-hot result to integer rd. Bits represent: negative infinity, negative normal, negative subnormal, negative zero, positive zero, positive subnormal, positive normal, positive infinity, signalling NaN, quiet NaN.


Summary: Examines a double-precision register and generates a classification bitmask.

Classifies the double-precision (64-bit) floating-point value in rs1, writing a 10-bit one-hot result to integer rd. Bits represent: negative infinity, negative normal, negative subnormal, negative zero, positive zero, positive subnormal, positive normal, positive infinity, signalling NaN, quiet NaN.


Summary: Converts a 64-bit signed integer (Long) to a single-precision float.

Converts between floating-point types or between floating-point and integer. Result is rounded according to the dynamic rounding mode. Invalid conversions produce the IEEE default NaN or the appropriate integer saturation value.


Summary: Converts a 64-bit unsigned integer to a single-precision float.


Summary: Converts a single-precision float to a 64-bit signed integer.


Summary: Converts a single-precision float to a 64-bit unsigned integer.


Summary: Converts a 64-bit signed integer to a double-precision float.


Summary: Converts a 64-bit unsigned integer to a double-precision float.


Summary: Converts a double-precision float to a 64-bit signed integer.


Summary: Injects the sign of rs2 into rs1 (Double Precision).

Produces a result with the magnitude of rs1 and the sign bit taken from the source rs2. Used to implement floating-point absolute value, negate, and copy-sign.


Summary: Injects the *negated* sign of rs2 into rs1 (Double Precision).


Summary: Sets integer rd to 1 if double rs1 equals double rs2, else 0.

Performs a double-precision (64-bit) floating-point equality comparison and writes 1 (true) or 0 (false) to integer rd. NaN inputs produce 0 (unordered), except FEQ which raises invalid-operation if either operand is a signalling NaN.


Summary: Sets integer rd to 1 if double rs1 is less than double rs2, else 0.

Performs a double-precision (64-bit) floating-point less-than comparison and writes 1 (true) or 0 (false) to integer rd. NaN inputs produce 0 (unordered), except FEQ which raises invalid-operation if either operand is a signalling NaN.


Summary: Sets integer rd to 1 if double rs1 is less than or equal to double rs2, else 0.

Performs a double-precision (64-bit) floating-point less-than-or-equal comparison and writes 1 (true) or 0 (false) to integer rd. NaN inputs produce 0 (unordered), except FEQ which raises invalid-operation if either operand is a signalling NaN.


Summary: Loads 3 fields (e.g., RGB) of 8-bit elements into 3 vector registers.

Load 3 interleaved 8-bit streams into 3 vector registers.

Performs a vector strided load of 3-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.


Summary: Stores 3 vector registers (e.g., RGB) into memory as interleaved 8-bit fields.

Store 3 vector registers as interleaved 8-bit fields.

Performs a vector strided store of 3-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.


Summary: Loads 4 fields (e.g., RGBA) of 8-bit elements into 4 vector registers.

Load 4 interleaved 8-bit streams into 4 vector registers.

Performs a vector strided load of 4-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.


Summary: Stores 4 vector registers (e.g., RGBA) into memory as interleaved 8-bit fields.

Store 4 vector registers as interleaved 8-bit fields.

Performs a vector strided store of 4-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.


Summary: Loads 2 fields (e.g., Complex Real/Imag) of 16-bit elements.

Performs a vector strided load of 2-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.


Summary: Stores 2 vector registers as interleaved 16-bit fields.

Performs a vector strided store of 2-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.


Summary: Loads 8-bit elements, suppressing faults on elements after the first. Sets VL to number of elements loaded. Critical for strings.

Performs a vector unit-stride load of 8-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.


Summary: Loads 16-bit elements with fault suppression.

Performs a vector unit-stride load of 16-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.


Summary: Loads 32-bit elements with fault suppression.

Performs a vector unit-stride load of 32-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.


Summary: Loads 64-bit elements with fault suppression.

Performs a vector unit-stride load of 64-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.


Vector Atomic Add Word: Atomically adds elements from vs2 to memory addresses in rs1 (indexed by vs2? No, rs1 is base, vs2 is index). Operation: AtomicAdd(rs1 + vs2[i], vd[i]);.


Vector Atomic Add Doubleword: Atomically adds elements from vs2 to memory addresses (64-bit). Operation: AtomicAdd(rs1 + vs2[i], vd[i]);.


Summary: Atomically ANDs elements.

Vector Atomic AND Word: Atomically ANDs elements. Operation: AtomicAnd(rs1 + vs2[i], vd[i]);.


Summary: Atomically ANDs elements (64-bit).

Vector Atomic AND Doubleword: Atomically ANDs elements (64-bit). Operation: AtomicAnd(rs1 + vs2[i], vd[i]);.


Summary: Atomically ORs elements.

Vector Atomic OR Word: Atomically ORs elements. Operation: AtomicOr(rs1 + vs2[i], vd[i]);.


Summary: Atomically ORs elements (64-bit).

Vector Atomic OR Doubleword: Atomically ORs elements (64-bit). Operation: AtomicOr(rs1 + vs2[i], vd[i]);.


Summary: Atomically XORs elements.

Vector Atomic XOR Word: Atomically XORs elements. Operation: AtomicXor(rs1 + vs2[i], vd[i]);.


Summary: Atomically XORs elements (64-bit).

Vector Atomic XOR Doubleword: Atomically XORs elements (64-bit). Operation: AtomicXor(rs1 + vs2[i], vd[i]);.


Summary: Atomic Max (Signed).

Vector Atomic Max Word: Atomic Max (Signed). Operation: AtomicMax(rs1 + vs2[i], vd[i]);.


Summary: Atomic Max (Signed, 64-bit).

Vector Atomic Max Doubleword: Atomic Max (Signed, 64-bit). Operation: AtomicMax(rs1 + vs2[i], vd[i]);.


Summary: Atomic Min (Signed).

Vector Atomic Min Word: Atomic Min (Signed). Operation: AtomicMin(rs1 + vs2[i], vd[i]);.


Summary: Atomic Min (Signed, 64-bit).

Vector Atomic Min Doubleword: Atomic Min (Signed, 64-bit). Operation: AtomicMin(rs1 + vs2[i], vd[i]);.


Summary: Atomic Max (Unsigned, Width implicit).

Vector Atomic Max Unsigned: Atomic Max (Unsigned, Width implicit). Operation: AtomicMaxU(rs1 + vs2[i], vd[i]);.


Summary: Atomic Min (Unsigned, Width implicit).

Vector Atomic Min Unsigned: Atomic Min (Unsigned, Width implicit). Operation: AtomicMinU(rs1 + vs2[i], vd[i]);.


Summary: Moves elements up by 1, injecting scalar into index 0.

Slides vector elements up by the specified offset, filling vacated positions with zero or the value from vs1[0].


Summary: Moves elements down by 1, injecting scalar into top index.

Slides vector elements down by the specified offset, filling vacated positions with zero or the value from vs1[0].


Summary: Sums float vector elements in exact order (0 to vl-1).

Performs a vector reduction: applies the operation across all active elements of vs2, using vs1[0] as the initial accumulator, and writes the scalar result to vd[0]. Active elements are determined by vl.


Vector Widening Unordered Float Reduction Sum

Summary: Sums N-bit floats into 2*N-bit scalar accumulator (Unordered).

Performs a widening operation, producing results twice as wide as the source elements. Results are written to vd using 2× the element grouping (EEW). The number of elements and masking are governed by vl and vm.


Vector Widening Ordered Float Reduction Sum

Summary: Sums N-bit floats into 2*N-bit scalar accumulator (Ordered).


Summary: Merges integer scalar vs vector based on mask.

Merges elements from vs1 and vs2 (or an immediate) according to the mask: masked-on elements come from vs1, masked-off from vs2.


Summary: Merges immediate vs vector based on mask.


Summary: Performs SHA-512 Sigma0 transformation (RV64).

SHA512SIG0 computes the lower 64-bit word of the sigma_0 function for SHA-512.


Summary: Performs SHA-512 Sigma1 transformation (RV64).

SHA512SIG1 computes the sigma_1 function for SHA-512.


Summary: Performs SHA-512 Sum0 transformation (RV64).

SHA512SUM0 computes the sum-0 (capital Sigma-0) function for SHA-512.


Summary: Performs SHA-512 Sum1 transformation (RV64).

SHA512SUM1 computes the sum-1 (capital Sigma-1) function for SHA-512.


Summary: Loads a double-precision float from memory (Compressed).

? | 001 | c_uimm8hi | rs1_p | c_uimm8lo | rd_p | 00

Loads a double-precision FP value from memory into fd′. Stack-pointer relative or register-based variants.


Summary: Stores a double-precision float to memory (Compressed).

? | 101 | c_uimm8hi | rs1_p | c_uimm8lo | rs2_p | 00

Stores a double-precision FP value from fd′ to memory.


Compressed Add Immediate to Stack Pointer (Non-zero)

Summary: Adds a zero-extended non-zero immediate to the stack pointer (x2) and stores the result in a register.

Adds a zero-extended non-zero immediate to sp (x2) and writes the result to rd′ (CIW format). Used to address stack-allocated data.


Summary: Loads a 32-bit word from memory using a compressed encoding.

? | 010 | c_uimm7hi | rs1_p | c_uimm7lo | rd_p | 00

Loads a 32-bit word from memory at a 6-bit unsigned offset from rs1′ into rd′.


Summary: Stores a 32-bit word to memory using a compressed encoding.

? | 110 | c_uimm7hi | rs1_p | c_uimm7lo | rs2_p | 00

Stores the low 32 bits of rs2′ to memory at a 6-bit unsigned offset from rs1′.


Summary: Adds a non-zero immediate to a register.

? | 000 | c_nzimm6hi | rd_rs1_n0 | c_nzimm6lo | 01

Adds a non-zero 6-bit sign-extended immediate to rd (≠ x0) and writes back. 16-bit encoding of ADDI.


Summary: Performs a PC-relative jump and stores return address in x1 (ra). RV32 only.

Performs a PC-relative jump and saves the return address in x1 (RV32 only).


Summary: Loads a 6-bit signed immediate into a register.

Loads a 6-bit sign-extended immediate into rd (≠ x0). Equivalent to ADDI rd, x0, imm.


Compressed Add Immediate to Stack Pointer

Summary: Adds a signed non-zero immediate to the stack pointer (x2).

Adds a non-zero 6-bit sign-extended immediate scaled by 16 to the stack pointer (x2).


Summary: Loads a non-zero 6-bit immediate into bits 17-12 of the destination register, clears lower 12 bits, sign-extends bit 17.

? | 011 | c_nzimm18hi | rd_n2 | c_nzimm18lo | 01

Loads a 18-bit sign-extended value (upper 6 bits of 20-bit immediate) into rd (≠ x0, x2).


Compressed Shift Right Logical Immediate

Summary: Logically shifts a register right by immediate.

? | 100 | c_nzuimm6hi | 00 | rd_rs1_p | c_nzuimm6lo | 01

Logical right shift of rd′ by a 5-bit immediate.


Compressed Shift Right Arithmetic Immediate

Summary: Arithmetically shifts a register right by immediate.

? | 100 | c_nzuimm6hi | 01 | rd_rs1_p | c_nzuimm6lo | 01

Arithmetic right shift of rd′ by a 5-bit immediate.


Summary: Computes bitwise AND with a signed immediate.

Computes the bitwise AND of rd′ and a 6-bit sign-extended immediate.


Summary: Subtracts two registers.

Subtracts rs2′ from rd′ and writes the result to rd′.


Summary: Bitwise XOR of two registers.

Computes the bitwise XOR of rd′ and rs2′, writing to rd′.


Summary: Bitwise OR of two registers.

Computes the bitwise OR of rd′ and rs2′, writing to rd′.


Summary: Bitwise AND of two registers.

Computes the bitwise AND of rd′ and rs2′, writing the result to rd′.


Summary: Unconditional PC-relative jump.

Performs an unconditional PC-relative jump within an 11-bit signed offset range.


Summary: Branches if the register is zero.

? | 110 | c_bimm9hi | rs1_p | c_bimm9lo | 01

Branches to an 8-bit PC-relative offset if rs1′ equals zero.


Summary: Branches if the register is not zero.

? | 111 | c_bimm9hi | rs1_p | c_bimm9lo | 01

Branches to an 8-bit PC-relative offset if rs1′ is non-zero.


Summary: Logically shifts a register left by immediate.

? | 000 | c_nzuimm6hi | rd_rs1_n0 | c_nzuimm6lo | 10

Logical left shift of rd (≠ x0) by a 5-bit (RV32) or 6-bit (RV64) immediate.


Summary: Loads a word from the stack pointer (x2).

? | 010 | c_uimm8sphi | rd_n0 | c_uimm8splo | 10

Loads a 32-bit word from a stack-pointer-relative address into rd.


Summary: Stores a word to the stack pointer (x2).

Stores the low 32 bits of rs2 to a stack-pointer-relative address.


Summary: Unconditionally jumps to address in register.

Jumps to the address in rs1 without linking.


Summary: Copies register rs2 to rd.

Copies the value of rs2 (≠ x0) to rd (≠ x0). Equivalent to C.ADD rd, x0, rs2.


Summary: Triggers a debugger breakpoint.

Causes a breakpoint exception. 16-bit encoding of EBREAK.


Summary: Jumps to register address and links (saves PC+2 to ra).

Jumps to address in rs1 and saves PC+2 in x1.


Summary: Adds two registers.

Adds the value of a register to rd/rs1 and writes the result back to rd. 16-bit encoding of ADD.


Summary: Take the branch if registers rs1 and rs2 are equal.

if (R[rs1] == R[rs2]) PC += sext(offset);

BEQ takes the branch if rs1 equals rs2. The branch target is the PC of the branch plus the sign-extended B-immediate, which encodes an offset in multiples of 2 bytes within a ±4 KiB range.


Summary: Take the branch if registers rs1 and rs2 are not equal.

if (R[rs1] != R[rs2]) PC += sext(offset);

BNE takes the branch if rs1 is not equal to rs2. The branch target is the PC of the branch plus the sign-extended B-immediate within a ±4 KiB range.


Summary: Take the branch if rs1 is less than rs2 (signed).

if (R[rs1] <s R[rs2]) PC += sext(offset);

Branch to 'exit' if x10 < x11 (signed comparison).

BLT takes the branch if rs1 is less than rs2, using a signed comparison. The branch target is the PC plus the sign-extended B-immediate.


Summary: Take the branch if rs1 is greater than or equal to rs2 (signed).

if (R[rs1] >=s R[rs2]) PC += sext(offset);

BGE takes the branch if rs1 is greater than or equal to rs2, using a signed comparison. The branch target is the PC plus the sign-extended B-immediate.


Summary: Atomically swaps values in the CSRs. Reads the old value of the CSR into rd, then writes rs1 to the CSR.

t = CSRs[csr]; CSRs[csr] = R[rs1]; R[rd] = t;

Writes x11 to 'scause' CSR and reads old 'scause' into x10.

CSRRW atomically reads the value of CSR csr into rd, then writes the value from rs1 into the CSR. If rd is x0, the read is skipped and no side-effects from reading occur.


Summary: Reads the value of the CSR into rd, then bitwise ORs the value in rs1 into the CSR (setting bits).

t = CSRs[csr]; CSRs[csr] = t | R[rs1]; R[rd] = t;

Sets bits in 'sstatus' using mask in x5 (Result discarded).

CSRRS atomically reads CSR csr into rd, then sets the bits in the CSR that correspond to bits set in rs1. If rs1 is x0, no bits are modified.


Summary: Performs signed integer division.

DIV divides rs1 by rs2 using signed division and writes the quotient to rd, truncated toward zero. Division by zero yields -1; overflow (INT_MIN ÷ -1) yields INT_MIN.


Summary: Performs unsigned integer division.

DIVU divides rs1 by rs2 using unsigned division and writes the quotient to rd, truncated toward zero. Division by zero yields 2^XLEN - 1.


Summary: Used by debuggers to cause control to be transferred back to a debugging environment.

EBREAK causes a breakpoint exception to be raised, intended for use by debuggers. Execution is transferred to the appropriate trap handler.


Summary: Orders device I/O and memory accesses.

Ensures all previous reads/writes complete before subsequent reads/writes.

FENCE orders device I/O and memory accesses as viewed by other RISC-V harts and external devices. The predecessor and successor sets of operations are specified by the pred and succ fields. FENCE with all fields zero is a full memory fence.


Summary: Loads a single-precision floating-point value from memory.

Loads a 32-bit word from memory at address rs1+sext(offset) into floating-point register rd.


Summary: Stores a single-precision floating-point value to memory.

Stores a floating-point register to memory at address rs1+sext(offset).


Summary: Performs single-precision floating-point addition.

Performs single-precision (32-bit) floating-point addition. The operation adds the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.


Summary: Performs a 32-bit (or 64-bit) multiplication of rs1 and rs2 and stores the lower bits in rd.

MUL performs an XLEN-bit × XLEN-bit multiplication of rs1 and rs2 and writes the lower XLEN bits of the product to rd. Both operands are treated as signed or unsigned (the result is the same for the low bits).


Summary: Performs a signed multiplication and stores the upper bits of the result.

R[rd] = (sext(R[rs1]) * sext(R[rs2])) >> XLEN;

Get upper bits of signed multiplication.

MULH multiplies rs1 and rs2 as signed values and writes the upper XLEN bits of the 2×XLEN-bit product to rd.


Summary: Returns from a machine-mode trap handler.

Return to previous privilege level defined in mstatus.

MRET returns from a machine-level trap. It restores the PC from mepc, restores privilege from the MPP field of mstatus, and updates interrupt-enable and privilege fields in mstatus.


Summary: Performs a bitwise logical OR operation.

OR performs a bitwise logical OR of the values in rs1 and rs2, writing the result to rd.


Summary: Performs a bitwise logical OR with a sign-extended immediate.

ORI performs a bitwise OR of register rs1 with the sign-extended 12-bit immediate, writing the result to rd.


Summary: Computes the signed remainder of division.

REM computes the signed remainder of rs1 ÷ rs2, writing the result to rd. The sign of the result equals the sign of the dividend (rs1). Remainder by zero yields the dividend; overflow (INT_MIN % -1) yields zero.


Summary: Stores the lowest 8 bits of a register to memory.

SB stores the least-significant byte of rs2 to memory at address rs1+sext(offset).


Summary: Stores the lowest 16 bits of a register to memory.

SH stores the least-significant halfword (16 bits) of rs2 to memory at address rs1+sext(offset).


Summary: Stores a 32-bit word to memory.

SW stores the least-significant 32-bit word of rs2 to memory at address rs1+sext(offset).


Summary: Stores a 64-bit doubleword to memory.

SD stores the 64-bit doubleword in rs2 to memory at address rs1+sext(offset).


Summary: Shifts a register left by the number of bits specified in another register.

SLL performs a logical left shift of the value in rs1 by the shift amount held in the lower 5 bits of rs2 (or 6 bits in RV64I), writing the result to rd. Zeros are shifted into the low-order bits.


Summary: Shifts a register left by a constant amount.

SLLI is a logical left shift by the constant encoded in the immediate field. The shift amount is the lower 5 bits (RV32I) or 6 bits (RV64I) of the immediate. Zeros are shifted into low-order bits.


Summary: Shifts a register right, shifting in zeros.

SRL performs a logical right shift of the value in rs1 by the shift amount held in the lower 5 bits of rs2 (or 6 bits in RV64I), writing the result to rd. Zeros are shifted into the high-order bits.


Summary: Shifts a register right, preserving the sign bit.

Arithmetic right shift (sign preserved).

SRA performs an arithmetic right shift of the value in rs1 by the shift amount held in the lower 5 bits of rs2 (or 6 bits in RV64I), writing the result to rd. The original sign bit is copied into the vacated upper bits.


Summary: Sets rd to 1 if rs1 < rs2 (signed), otherwise 0.

SLT performs a signed comparison of rs1 and rs2, writing 1 to rd if rs1 < rs2 (signed), and 0 otherwise.


Summary: Sets rd to 1 if rs1 < immediate (signed), otherwise 0.

SLTI places 1 in rd if rs1 is less than the sign-extended 12-bit immediate when both are treated as signed numbers, else 0.


Summary: Conditionally stores a word to memory if the reservation (from LR) is still valid.

if (ReservationValid) { M[R[rs1]] = R[rs2]; R[rd] = 0; } else { R[rd] = 1; }

Try to store x11 to x12. x10=0 on success.

SC.W conditionally stores the word in rs2 to the address in rs1, only if the reservation set by LR.W is still valid. It writes 0 to rd on success and a non-zero value on failure.


Summary: Synchronizes updates to in-memory address translation data structures (TLB flush).

SFENCE.VMA is a fence for virtual memory management. It guarantees that preceding stores to the page table are visible to subsequent page-table walks. The rs1 and rs2 operands optionally restrict the fence to a specific virtual address and ASID.


Summary: Returns from a supervisor-mode trap handler.

Return from exception/interrupt in supervisor mode.

SRET returns from a supervisor-level trap. It restores the PC from sepc, restores privilege from the SPP field of sstatus, and updates interrupt-enable fields.


Summary: Provides a hint to the implementation that the current hart can be stalled until an interrupt occurs.

while(!Interrupt) { /* low power state */ }

WFI (Wait For Interrupt) provides a hint to the implementation that the current hart can be stalled until an interrupt might need servicing. Implementations may simply implement WFI as NOP.


Summary: Performs a bitwise logical Exclusive-OR operation.

XOR performs a bitwise logical exclusive-OR of the values in rs1 and rs2, writing the result to rd.


Summary: Performs a bitwise logical Exclusive-OR with a sign-extended immediate.

XORI performs a bitwise XOR of register rs1 with the sign-extended 12-bit immediate, writing the result to rd. XORI rd, rs1, -1 performs a bitwise logical inversion of rs1 (assembler pseudoinstruction NOT rd, rs).


Hypervisor Fence Guest Virtual Memory Address

Summary: Synchronizes updates to guest physical address translation data structures.

HFENCE.GVMA orders implicit reads and writes to G-stage page tables, ensuring preceding stores to the second-stage page table are visible to subsequent VS-mode address translations. rs1 optionally restricts the fence to a guest physical address; rs2 optionally restricts it to a VMID.


Hypervisor Fence Virtual Virtual Memory Address

Summary: Synchronizes updates to VS-stage address translation data structures.

HFENCE.VVMA orders implicit reads and writes to VS-stage page tables for the current VMID. rs1 optionally restricts to a virtual address; rs2 to an ASID.


Summary: Jumps to an offset relative to PC and saves the return address (PC+4) to rd.

Jump to 'loop_target' and save return address in x1 (ra).

JAL (Jump and Link) adds the sign-extended J-immediate (encoded in multiples of 2 bytes) to the PC of the JAL instruction to form the jump target, stores PC+4 into rd as a return address, then jumps. Plain unconditional jumps use rd=x0.


Summary: Jumps to address in rs1 + offset, saving return address to rd.

t = PC + 4; PC = (R[rs1] + sext(offset)) & ~1; R[rd] = t;

Return from function (jumps to address in x1/ra).

JALR (Jump and Link Register) computes a target address by adding the sign-extended 12-bit immediate to rs1, then clears the least-significant bit of the result. It writes the address of the following instruction (PC+4) to rd, then jumps to the target.


Summary: Loads an 8-bit byte from memory and sign-extends it to the register width.

R[rd] = sext(M[R[rs1] + sext(offset)][7:0]);

Load byte from stack pointer (x2) into x10.

LB loads a byte from memory at address rs1+sext(offset), sign-extends it to XLEN bits, and writes it to rd.


Summary: Loads a 16-bit halfword from memory and sign-extends it.

R[rd] = sext(M[R[rs1] + sext(offset)][15:0]);

LH loads a halfword (16 bits) from memory at address rs1+sext(offset), sign-extends it to XLEN bits, and writes it to rd.


Summary: Loads a 32-bit word from memory and sign-extends it to 64 bits.

R[rd] = sext(M[R[rs1] + sext(offset)][31:0]);

LW loads a 32-bit word from memory at address rs1+sext(offset). In RV32I the result is written directly to rd; in RV64I it is sign-extended to 64 bits before being written.


Summary: Loads an 8-bit byte from memory and zero-extends it.

R[rd] = zext(M[R[rs1] + sext(offset)][7:0]);

LBU loads a byte from memory at address rs1+sext(offset), zero-extends it to XLEN bits, and writes it to rd.


Summary: Loads a 16-bit halfword from memory and zero-extends it.

R[rd] = zext(M[R[rs1] + sext(offset)][15:0]);

LHU loads a halfword (16 bits) from memory at address rs1+sext(offset), zero-extends it to XLEN bits, and writes it to rd.


Summary: Loads a 64-bit doubleword from memory.

LD loads a 64-bit doubleword from memory at address rs1+sext(offset) and writes it to rd.


Summary: Loads a 32-bit word from memory and zero-extends it to 64 bits.

R[rd] = zext(M[R[rs1] + sext(offset)][31:0]);

Load 32-bit word and zero-extend to 64-bit.

LWU loads a 32-bit word from memory at address rs1+sext(offset), zero-extends it to 64 bits, and writes it to rd. Unlike LW, it does not sign-extend.


Summary: Loads the 20-bit immediate into the upper 20 bits of the register (lower 12 bits are zero).

LUI (Load Upper Immediate) places the 20-bit U-immediate into bits 31:12 of rd, filling bits 11:0 with zeros and sign-extending to XLEN bits. It is used together with ADDI to build arbitrary 32-bit constants.


Summary: Loads a word from memory and registers a reservation set for the address.

Start atomic read-modify-write sequence.

LR.W loads a word from the memory address in rs1 into rd and registers a reservation on that address. The reservation is used by SC.W to implement load-reserved/store-conditional atomics.


Summary: Loads a doubleword from memory and registers a reservation set.

LR.D loads a doubleword from the memory address in rs1 into rd and registers a reservation on that address (RV64 only).


Summary: Sets mask if vs2 > vs1.

Compares elements element-wise for greater than and writes a mask result to vd.


Summary: Sets mask if vs2 > vs1 (Unsigned).


Summary: Sets mask if vs2 <= vs1.

Compares elements element-wise for less than or equal and writes a mask result to vd.


Vector Mask Set Less or Equal (Unsigned)

Summary: Sets mask if vs2 <= vs1 (Unsigned).


Vector Mask Set Greater or Equal (Signed)

Summary: Sets mask if vs2 >= vs1.

Compares elements element-wise for greater than or equal and writes a mask result to vd.


Vector Mask Set Greater or Equal (Unsigned)

Summary: Sets mask if vs2 >= vs1 (Unsigned).


Summary: Add Immediate with Carry.

Vector Mask Add with Carry Immediate: Add Immediate with Carry. Operation: vd = carry(vs2 + imm + v0);.


Summary: vd = vd + (signed(vs1) * unsigned(vs2)).

Performs a widening operation, producing results twice as wide as the source elements. Results are written to vd using 2× the element grouping (EEW). The number of elements and masking are governed by vl and vm.


Summary: vd = vd + (unsigned(vs1) * signed(vs2)).


Summary: Computes vd = vs1 + vs2 + carry (v0).

Vector Add with Carry: Computes vd = vs1 + vs2 + carry (v0). Operation: vd = vs1 + vs2 + v0;.


Summary: Adds immediate to vector.

Performs element-wise integer addition on a vector and an immediate, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Computes vd = imm - vs2.

Performs element-wise reverse integer subtraction on a vector and an immediate, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Bitwise AND with immediate.

Performs element-wise bitwise AND on a vector and an immediate, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Bitwise OR with immediate.

Performs element-wise bitwise OR on a vector and an immediate, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Bitwise XOR with immediate.

Performs element-wise bitwise XOR on a vector and an immediate, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Gathers element at index 'imm' from vs2 (splat).

Gathers elements from vs2 using indices in vs1 (or an immediate), writing to vd. Out-of-range indices produce zero.


Summary: Moves elements up by immediate amount.

Slides vector elements up by the specified offset, filling vacated positions with zero or the value from vs1[0].


Summary: Moves elements down by immediate amount.

Slides vector elements down by the specified offset, filling vacated positions with zero or the value from vs1[0].


Summary: Sets mask if element == imm.

Compares elements element-wise for equal and writes a mask result to vd.


Summary: Sets mask if element != imm.

Compares elements element-wise for not equal and writes a mask result to vd.


Summary: Sets mask if element <= imm (Signed).


Vector Mask Set Less or Equal Unsigned Immediate

Summary: Sets mask if element <= imm (Unsigned).


Summary: Sets mask if element < imm (Signed).

Compares elements element-wise for less than and writes a mask result to vd.


Vector Mask Set Less Than Unsigned Immediate

Summary: Sets mask if element < imm (Unsigned).


Summary: Shifts elements left by immediate.

Performs element-wise left logical shift on a vector and an immediate, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Shifts elements right (logical) by immediate.

Performs element-wise right logical shift on a vector and an immediate, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Shifts elements right (arithmetic) by immediate.

Performs element-wise right arithmetic shift on a vector and an immediate, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Adds the contents of two registers.

Computes x11 + x12 and stores the result in x10.

ADD performs an XLEN-bit addition of the values in registers rs1 and rs2, writing the result to rd. Arithmetic overflow is ignored; the result is simply the low XLEN bits of the mathematical sum.


Summary: Adds a register and a sign-extended 12-bit immediate value.

Adds 10 to the value in x6 and stores it in x5.

ADDI adds the sign-extended 12-bit immediate to register rs1 and writes the low XLEN bits to rd. Arithmetic overflow is ignored. ADDI rd, rs1, 0 implements the MV assembler pseudoinstruction.


Summary: Adds two 32-bit registers and sign-extends the result to 64 bits.

Performs 32-bit addition of x11 and x12, result is sign-extended to 64 bits.

ADDW adds rs1 and rs2, truncates the result to 32 bits, sign-extends to 64 bits, and writes to rd. Arithmetic overflow is ignored.


Summary: Adds a 12-bit immediate to a register (32-bit arithmetic) and sign-extends to 64 bits.

Adds 5 to lower 32 bits of x6, sign-extends result to x5.

ADDIW adds the sign-extended 12-bit immediate to rs1, truncates to 32 bits, sign-extends to 64 bits, and writes to rd. Arithmetic overflow is ignored.


Summary: Performs a bitwise logical AND operation between two registers.

AND performs a bitwise logical AND of the values in rs1 and rs2, writing the result to rd.


Summary: Performs a bitwise logical AND between a register and a sign-extended 12-bit immediate.

Keeps only the lowest 4 bits of x11 (mask 0xF).

ANDI performs a bitwise AND of register rs1 with the sign-extended 12-bit immediate, writing the result to rd.


Summary: Adds a 20-bit upper immediate to the Program Counter, used for PC-relative addressing.

Adds 0x1000000 to the current PC and stores in x10.

AUIPC (Add Upper Immediate to PC) forms a 32-bit offset from the 20-bit U-immediate (filling the low 12 bits with zeros), adds it to the PC of the AUIPC instruction, and places the result in rd. It is used for PC-relative addressing.


Summary: Atomically adds a value to a word in memory.

temp = M[R[rs1]]; M[R[rs1]] = temp + R[rs2]; R[rd] = temp;

Atomically adds x11 to memory at x12. Old value stored in x10.

AMOADD.W atomically loads a word from the address in rs1 into rd, then adds rs2 to it, and stores the result back to that address.


Summary: Atomically swaps a value in memory with a register.

temp = M[R[rs1]]; M[R[rs1]] = R[rs2]; R[rd] = temp;

Writes x11 to memory at x12, loads old memory value into x10.

AMOSWAP.W atomically loads a word from the address in rs1 into rd and stores the value of rs2 to that address.


Summary: Atomically performs bitwise AND on a word in memory.

temp = M[R[rs1]]; M[R[rs1]] = temp & R[rs2]; R[rd] = temp;

AMOAND.W atomically loads a word from the address in rs1 into rd, ANDs it with rs2, and stores the result back.


Summary: Compute the absolute value of a signed or floating-point operand.

Absolute value.

abs.s32  r0,a;

abs.ftz.f32  x,f0;

abs.ftz.f16  x,f0;
abs.bf16     x,b0;
abs.bf16x2   x1,b1;

Take absolute value of a and store the result in d.
For.f16x2 and.bf16x2 instruction type, forms input vector by extracting half word values
from the source operand. Absolute values of half-word operands are then computed in parallel to
produce.f16x2 or.bf16x2 result in destination.
For.f16 instruction type, operands d and a have.f16 or.b16 type. For.f16x2 instruction type, operands d and a have.f16x2 or.b32 type. For.bf16 instruction type, operands d and a have.b16 type. For.bf16x2 instruction
type, operands d and a have.b32 type.


Parallel Synchronization and Communication Instructions

Summary: Query the bitmask of currently active (converged) lanes in the executing warp.

Reads the current active-lane mask with no side effects and no synchronization.

d

Destination register receiving the active-lane bitmask

d = bitmask of lanes currently active/converged at this point in the warp.

activemask queries predicated-on active threads from the executing warp and sets the destination d with 32-bit integer mask where bit position in the mask corresponds to the thread’s laneid.
Destination d is a 32-bit destination register.
An active thread will contribute 1 for its entry in the result and exited or inactive or
predicated-off thread will contribute 0 for its entry in the result.


Summary: Add two operands of the same type, with optional saturation for signed 32-bit integers.

Generic add across integer and floating-point types.

Signed 32-bit add with saturation on overflow instead of wraparound.

d = a + b, evaluated at the selected type's width.

@p  add.u32     x,y,z;
    add.sat.s32 c,c,1;
    add.u16x2   u,v,w;
    add.s8x4.sat p, q, r;

@p  add.rz.ftz.f32  f1,f2,f3;
add.rp.ftz.f32x2    d, a, b;

// scalar f16 additions
add.f16        d0, a0, b0;
add.rn.f16     d1, a1, b1;
add.bf16       bd0, ba0, bb0;
add.rn.bf16    bd1, ba1, bb1;
// (truncated - see the official PTX ISA docs for the full example)

.reg .f32 fc, fd;
.reg .b16 ba;
add.rz.f32.bf16.sat   fd, fa, fc;

Performs addition and writes the resulting value into a destination register.
For.u16x2,.s16x2 instruction types, forms input vectors by half word values from source
operands. Half-word operands are then added in parallel to produce.u16x2,.s16x2 result in
destination.
For.u8x4,.s8x4 instruction types, forms input vectors by quarter word values from source
operands. Quarter-word operands are then added in parallel to produce.u8x4,.s8x4 result
in destination.
Operands d, a and b have the same type as the instruction type. For instruction types.u16x2,.s16x2,.u8x4,.s8x4, operands d, a and b have type.b32.


Extended-Precision Integer Arithmetic Instructions

Summary: Performs integer addition and writes the carry-out value into the condition code register.

@p  add.cc.u32   x1,y1,z1;   // extended-precision addition of
@p  addc.cc.u32  x2,y2,z2;   // two 128-bit values
@p  addc.cc.u32  x3,y3,z3;
@p  addc.u32     x4,y4,z4;


Summary:
Performs integer addition with carry-in and optionally writes the carry-out value into the condition
code register.


The alloca instruction dynamically allocates memory on the stack frame of the current function
and updates the stack pointer accordingly. (see the official PTX ISA docs for the full description)

alloca.type ptr, size, immAlign:

a = max(immAlign, frame_align); // frame_align is the minimum guaranteed alignment

// Allocate size bytes of stack memory with alignment a and update the stack pointer.
// Since the stack grows down, the updated stack pointer contains a lower address.
stackptr = alloc_stack_mem(size, a);

// Return the new value of stack pointer as ptr. Since ptr is the lowest address of the memory
// allocated by alloca, the memory can be accessed using ptr up to (ptr + size of allocated memory).
stacksave ptr;

.reg .u32 ra, stackptr, ptr, size;

stacksave.u32 stackptr;     // Save the current stack pointer
alloca ptr, size, 8;        // Allocate stack memory
st.local.u32 [ptr], ra;     // Use the allocated stack memory
stackrestore.u32 stackptr;  // Deallocate memory by restoring the stack pointer

The alloca instruction dynamically allocates memory on the stack frame of the current function
and updates the stack pointer accordingly. The returned pointer ptr points to local memory and
can be used in the address operand of ld.local and st.local instructions.
If sufficient memory is unavailable for allocation on the stack, then execution of alloca may
result in stack overflow. In such cases, attempting to access the allocated memory with ptr will
result in undefined program behavior.
The memory allocated by alloca is deallocated in the following ways:
It is automatically deallocated when the function exits. (see the official PTX ISA docs for the full description)


Summary: Bitwise AND of two operands.

Bitwise AND, including a predicate form.

and.b32  x,q,r;
and.b32  sign,fpvalue,0x80000000;

Compute the bit-wise and operation for the bits in a and b.


Data Movement and Conversion Instructions

applypriority{.global}.level::eviction_priority  [a], size;

The applypriority instruction applies the cache eviction priority specified by the.level::eviction_priority qualifier to the address range [a..a+size) in the specified cache
level. (see the official PTX ISA docs for the full description)

The applypriority instruction applies the cache eviction priority specified by the.level::eviction_priority qualifier to the address range [a..a+size) in the specified cache
level.
If no state space is specified then Generic Addressing is
used. If the specified address does not fall within the address window of.global state space
then the behavior is undefined.
The operand size is an integer constant that specifies the amount of data, in bytes, in the
specified cache level on which the priority is to be applied. The only supported value for the size operand is 128.
Supported addressing modes for operand a are described in Addresses as Operands. a must be aligned to 128 bytes.


Summary: Atomically read-modify-write a memory location and return the prior value.

Atomic operation; op selects the read-modify-write function.

Destination register (receives the pre-operation value)

d = *a; *a = op(*a, b); indivisible with respect to other threads targeting the same address.

atom.global.add.s32  d,[a],1;
atom.shared::cta.max.u32  d,[x+4],0;
@p  atom.global.cas.b32  d,[p],my_val,my_new_val;
atom.global.sys.add.u32 d, [a], 1;
atom.global.acquire.sys.inc.u32 ans, [gbl], %r0;
atom.add.noftz.f16x2 d, [a], b;
// (truncated - see the official PTX ISA docs for the full example)

Atomically loads the original value at location a into destination register d, performs a
reduction operation with operand b and the value in location a, and stores the result of the
specified operation at location a, overwriting the original value. For the.cas (compare-and-swap)
operation, operand b is the compare value and operand c is the swap value. The operation
compares the value at location a with operand b; if they are equal, it stores operand c at location a, otherwise it leaves the value at location a unchanged. Operand a specifies a
location in the specified state space. If no state space is given, perform the memory accesses using Generic Addressing. (see the official PTX ISA docs for the full description)


Performs barrier synchronization and communication within a CTA. Each CTA instance has sixteen
barriers numbered 0..15.
barrier{. (see the official PTX ISA docs for the full description)

// Use bar.sync to arrive at a pre-computed barrier number and
// wait for all threads in CTA to also arrive:
    st.shared [r0],r1;  // write my result to shared memory
    bar.cta.sync  1;    // arrive, wait for others to arrive
    ld.shared r2,[r3];  // use shared results from other threads
// (truncated - see the official PTX ISA docs for the full example)

Performs barrier synchronization and communication within a CTA. Each CTA instance has sixteen
barriers numbered 0..15.
barrier{.cta} instructions can be used by the threads within the CTA for synchronization and
communication.
Operands a, b, and d have type.u32; operands p and c are predicates. Source
operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15. Operand b specifies the number of threads participating in the barrier. If
no thread count is specified, all threads in the CTA participate in the barrier. When specifying a
thread count, the value must be a multiple of the warp size. (see the official PTX ISA docs for the full description)


bar.warp.sync will cause executing thread to wait until all threads corresponding to membermask have executed a bar.warp.sync with the same membermask value before resuming
execution. (see the official PTX ISA docs for the full description)

st.shared.u32 [r0],r1;         // write my result to shared memory
bar.warp.sync  0xffffffff;     // arrive, wait for others to arrive
ld.shared.u32 r2,[r3];         // read results written by other threads

bar.warp.sync will cause executing thread to wait until all threads corresponding to membermask have executed a bar.warp.sync with the same membermask value before resuming
execution.
Operand membermask specifies a 32-bit integer which is a mask indicating threads participating
in barrier where the bit position corresponds to thread’s laneid.
The behavior of bar.warp.sync is undefined if the executing thread is not in the membermask.
bar.warp.sync also guarantee memory ordering among threads participating in barrier. (see the official PTX ISA docs for the full description)


Summary: Block threads in a CTA at a named barrier until the expected number of threads has arrived.

barrier{.cta}.sync{.aligned}      a{, b};

Wait at barrier resource a for all (or b) threads of the CTA.

Legacy short-form alias of barrier.sync with the same semantics.

b

Optional thread count participating in the barrier

Every participating thread blocks until all have executed the barrier; also orders shared-memory visibility across the participating threads.


Performs barrier synchronization and communication within a cluster.
barrier.cluster instructions can be used by the threads within the cluster for synchronization
and communication.
barrier.cluster. (see the official PTX ISA docs for the full description)

// use of arrive followed by wait
ld.shared::cluster.u32 r0, [addr];
barrier.cluster.arrive.aligned;
...
barrier.cluster.wait.aligned;
st.shared::cluster.u32 [addr], r1;
// (truncated - see the official PTX ISA docs for the full example)

Performs barrier synchronization and communication within a cluster.
barrier.cluster instructions can be used by the threads within the cluster for synchronization
and communication.
barrier.cluster.arrive instruction marks warps’ arrival at barrier without causing executing
thread to wait for threads of other participating warps.
barrier.cluster.wait instruction causes the executing thread to wait for all non-exited threads
of the cluster to perform barrier.cluster.arrive.
In addition, barrier.cluster instructions cause the executing thread to wait for all non-exited
threads from its warp.
When all non-exited threads in the cluster have executed barrier.cluster. (see the official PTX ISA docs for the full description)


Extract bit field from a and place the zero or sign-extended result in d. Source b gives
the bit field starting bit position, and source c gives the bit field length in bits. (see the official PTX ISA docs for the full description)

msb = (.type==.u32 || .type==.s32) ? 31 : 63;
pos = b & 0xff;  // pos restricted to 0..255 range
len = c & 0xff;  // len restricted to 0..255 range

if (.type==.u32 || .type==.u64 || len==0)
    sbit = 0;
else
    sbit = a[min(pos+len-1,msb)];

d = 0;
for (i=0; i<=msb; i++) {
    d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit;
}

Extract bit field from a and place the zero or sign-extended result in d. Source b gives
the bit field starting bit position, and source c gives the bit field length in bits.
Operands a and d have the same type as the instruction type. Operands b and c are
type.u32, but are restricted to the 8-bit value range 0..255.
The sign bit of the extracted field is defined as:.u32,.u64: zero.s32,.s64: msb of input a if the extracted field extends beyond the msb of a msb of extracted
field, otherwise
If the bit field length is zero, the result is zero.
The destination d is padded with the sign bit of the extracted field. (see the official PTX ISA docs for the full description)


Align and insert a bit field from a into b, and place the result in f. Source c gives the starting bit position for the insertion, and source d gives the bit field length in
bits. (see the official PTX ISA docs for the full description)

msb = (.type==.b32) ? 31 : 63;
pos = c & 0xff;  // pos restricted to 0..255 range
len = d & 0xff;  // len restricted to 0..255 range

f = b;
for (i=0; i<len && pos+i<=msb; i++) {
    f[pos+i] = a[i];
}

Align and insert a bit field from a into b, and place the result in f. Source c gives the starting bit position for the insertion, and source d gives the bit field length in
bits.
Operands a, b, and f have the same type as the instruction type. Operands c and d are type.u32, but are restricted to the 8-bit value range 0..255.
If the bit field length is zero, the result is b.
If the start position is beyond the msb of the input, the result is b.


Find the bit position of the most significant non-sign bit in a and place the result in d. Operand a has the instruction type, and destination d has type.u32. (see the official PTX ISA docs for the full description)

msb = (.type==.u32 || .type==.s32) ? 31 : 63;
// negate negative signed inputs
if ( (.type==.s32 || .type==.s64) && (a & (1<<msb)) ) {
    a = ~a;
}
.u32  d = 0xffffffff;
for (.s32 i=msb; i>=0; i--) {
    if (a & (1<<i))  { d = i; break; }
}
if (.shiftamt && d != 0xffffffff)  { d = msb - d; }

bfind.u32  d, a;
bfind.shiftamt.s64  cnt, X;  // cnt is .u32

Find the bit position of the most significant non-sign bit in a and place the result in d. Operand a has the instruction type, and destination d has type.u32. For unsigned
integers, bfind returns the bit position of the most significant 1. For signed integers, bfind returns the bit position of the most significant 0 for negative inputs and the most
significant 1 for non-negative inputs.
If.shiftamt is specified, bfind returns the shift amount needed to left-shift the found bit
into the most-significant bit position.
bfind returns 0xffffffff if no non-sign bit is found.


Generates a 32-bit mask starting from the bit position specified in operand a, and of the width
specified in operand b. (see the official PTX ISA docs for the full description)

a1    = a & 0x1f;
mask0 = (~0) << a1;
b1    = b & 0x1f;
sum   = a1 + b1;
mask1 = (~0) << sum;

sum-overflow          = sum >= 32 ? true : false;
bit-position-overflow = false;
bit-width-overflow    = false;

if (.mode == .clamp) {
    if (a >= 32) {
        bit-position-overflow = true;
        mask0 = 0;
    }
    if (b >= 32) {
        bit-width-overflow = true;
    }
}

if (sum-overflow || bit-position-overflow || bit-width-overflow) {
    mask1 = 0;
} else if (b1 == 0) {
    mask1 = ~0;
}
d = mask0 & ~mask1;

bmsk.clamp.b32  rd, ra, rb;
bmsk.wrap.b32   rd, 1, 2; // Creates a bitmask of 0x00000006.

Generates a 32-bit mask starting from the bit position specified in operand a, and of the width
specified in operand b. The generated bitmask is stored in the destination operand d.
The resulting bitmask is 0 in the following cases:
When the value of a is 32 or higher and.mode is.clamp. When either the specified value of b or the wrapped value of b (when.mode is
specified as.wrap ) is 0.


Summary: Continue execution at the target.

@p   bra{.uni}  tgt;           // tgt is a label

Continue execution at the target. Conditional branches are specified by using a guard predicate. The
branch target must be a label.
bra.uni is guaranteed to be non-divergent, i.e. (see the official PTX ISA docs for the full description)

bra.uni  L_exit;    // uniform unconditional jump
@q  bra      L23;   // conditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The
branch target must be a label.
bra.uni is guaranteed to be non-divergent, i.e. all active threads in a warp that are currently
executing this instruction have identical values for the guard predicate and branch target.


Summary: Perform bitwise reversal of input.

Perform bitwise reversal of input.

Perform bitwise reversal of input.


Summary: Suspends execution.

Suspends execution.

Suspends execution.


Index into a list of possible destination labels, and continue execution from the chosen
label. Conditional branches are specified by using a guard predicate.
brx.idx. (see the official PTX ISA docs for the full description)

if (p) {
    if (index < length(tlist)) {
      pc = tlist[index];
    } else {
      pc = undefined;
    }
}

.function foo () {
    .reg .u32 %r0;
    ...
    L1:
    ...
    L2:
// (truncated - see the official PTX ISA docs for the full example)

Index into a list of possible destination labels, and continue execution from the chosen
label. Conditional branches are specified by using a guard predicate.
brx.idx.uni guarantees that the branch is non-divergent, i.e. all active threads in a warp that
are currently executing this instruction have identical values for the guard predicate and the index argument.
The index operand is a.u32 register. The tlist operand must be the label of a.branchtargets directive. It is accessed as a zero-based sequence using index. (see the official PTX ISA docs for the full description)


// direct call to named function, func is a symbol
call{.uni} (ret-param), func, (param-list);

The call instruction stores the address of the next instruction, so execution can resume at that
point after executing a ret instruction. (see the official PTX ISA docs for the full description)

// examples of direct call
    call     init;    // call function 'init'
    call.uni g, (a);  // call function 'g' with parameter 'a'
@p  call     (d), h, (a, b);  // return value into register d

// call-via-pointer using jump table
// (truncated - see the official PTX ISA docs for the full example)

The call instruction stores the address of the next instruction, so execution can resume at that
point after executing a ret instruction. A call is assumed to be divergent unless the.uni suffix is present. The.uni suffix indicates that the call is guaranteed to be
non-divergent, i.e. all active threads in a warp that are currently executing this instruction have
identical values for the guard predicate and call target.
For direct calls, the called location func must be a symbolic function name; for indirect calls,
the called location fptr must be an address of a function held in a register. Input arguments
and return values are optional. (see the official PTX ISA docs for the full description)


Performs a carryless multiplication of a and b, followed by a carryless
addition of c, and writes the result into destination register d.
All operands of clmad are unsigned 64-bit values. (see the official PTX ISA docs for the full description)

tmp[127:0] = 0;  // 128-bit result of carryless multiplication.

for (i = 0; i < 64; i++) {
    if ((a & (1 << i)) != 0) {
        tmp ^= b << i;
    }
}

// Select upper or lower 64 bits depending on the value of .mode.
if (.mode == .lo) {
    d = tmp[63..0];
} else {
    d = tmp[127..64];
}

d ^= c;  // carryless accumulation.

.reg .u64 Rd, Ra, Rb, Rc;

// Carryless multiply-add producing lower 64 bits of result.
clmad.lo.u64 Rd, Ra, Rb, Rc;

// Carryless multiply-add producing higher 64 bits of result.
// (truncated - see the official PTX ISA docs for the full example)

Performs a carryless multiplication of a and b, followed by a carryless
addition of c, and writes the result into destination register d.
All operands of clmad are unsigned 64-bit values.
The modifier.mode specifies which part of the carryless product is stored in
the destination register:.lo Produces lower 64 bits of the product, with addition of c..hi Produces higher 64 bits of the product, with addition of c.


Instruction clusterlaunchcontrol.query_cancel can be used to decode opaque response
written by instruction clusterlaunchcontrol.try_cancel.
After loading response from clusterlaunchcontrol. (see the official PTX ISA docs for the full description)

clusterlaunchcontrol.query_cancel.is_canceled pred.b128 p, handle;

@p clusterlaunchcontrol.query_cancel.get_first_ctaid.v4.b32.b128 {xdim, ydim, zdim, ignr}  handle;

clusterlaunchcontrol.query_cancel.get_first_ctaid::x.b32.b128 reg0, handle;
// (truncated - see the official PTX ISA docs for the full example)

Instruction clusterlaunchcontrol.query_cancel can be used to decode opaque response
written by instruction clusterlaunchcontrol.try_cancel.
After loading response from clusterlaunchcontrol.try_cancel instruction into 16-byte
register it can be further queried using clusterlaunchcontrol.query_cancel instruction
as follows:
clusterlaunchcontrol.query_cancel.is_canceled.pred.b128: If the cluster is canceled
successfully, predicate p is set to true; otherwise, it is set to false.
If the request succeeded, the instruction clusterlaunchcontrol.query_cancel.get_first_ctaid extracts the CTA id of the first CTA in the canceled cluster. (see the official PTX ISA docs for the full description)


The clusterlaunchcontrol.try_cancel instruction requests atomically cancelling the launch of
a cluster that has not started running yet. (see the official PTX ISA docs for the full description)

// Assumption: 1D cluster (cluster_ctaid.y/.z == 1) with 1 thread per CTA.

// Current Cluster to be processed: initially the launched cluster:
mov.b32 xctaid, %ctaid.x;

// Establish full synchronization across all CTAs of the cluster for the first iteration.
// (truncated - see the official PTX ISA docs for the full example)

The clusterlaunchcontrol.try_cancel instruction requests atomically cancelling the launch of
a cluster that has not started running yet. It asynchronously writes an opaque response to shared
memory indicating whether the operation succeeded or failed. The completion of the asynchronous
operation is tracked using the mbarrier completion mechanism at.cluster scope.
This instruction accesses its mbarrier operand using generic-proxy.
On success, the opaque response contains the ctaid of the first CTA of the canceled cluster; no
other successful response from other clusterlaunchcontrol.try_cancel operations from the same
grid will contain that id.
The mandatory. (see the official PTX ISA docs for the full description)


Summary: Count the number of leading zero bits in an integer operand.

Count leading zeros.

d = number of leading 0-bits in a, counted from the most-significant bit.

clz.b32  d, a;
clz.b64  cnt, X;  // cnt is .u32

Count the number of leading zeros in a starting with the most-significant bit and place the
result in 32-bit destination register d. Operand a has the instruction type, and destination d has type.u32. For.b32 type, the number of leading zeros is between 0 and 32,
inclusively. For.b64 type, the number of leading zeros is between 0 and 64, inclusively.


Summary: Compute the logical negation using C/C++ semantics.


Summary: Copy sign bit of a into value of b, and return the result as d.

copysign.f32  x, y, z;
copysign.f64  A, B, C;


Summary: Find the cosine of the angle a (in radians).