Summary: Multiply the 32x32 matrix in the first input by the 32x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply…

Multiply the 32x32 matrix in the first input by the 32x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.


Summary: Multiply the 32x4 matrix in the first input by the 4x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply…

Multiply the 32x4 matrix in the first input by the 4x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.

D = A (32x4) * B (4x32) + C (32x32)
This instruction performs 2 matrix multiplies. Each operand contains 2 matrices back to back, and each matrix
has elements distributed across all lanes of the wave. Each matrix multiple is computed and the row-column
dot products are distributed across the vector ALU for higher performance. The result matrices are stored
back-to-back in the destination vector registers.
Matrices A and B are signed 8-bit integer format. Matrices C and D are signed 32-bit integer format.


Multiply the 4x4 matrix in the first input by the 4x4 matrix in the second input and add the 4x4 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.

D = A (4x4) * B (4x4) + C (4x4)
This instruction performs 16 matrix multiplies. Each operand contains 16 matrices back to back, and each
matrix has elements distributed across all lanes of the wave. Each matrix multiple is computed and the row-column dot products are distributed across the vector ALU for higher performance. The result matrices are
stored back-to-back in the destination vector registers.
Matrices A and B are signed 8-bit integer format. Matrices C and D are signed 32-bit integer format.


Summary: AMDGPU VOP3P matrix instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Select the minimum of three half-precision float inputs and store the selected value into a vector register.


Summary: Select the minimum of three single-precision float inputs and store the selected value into a vector register.


Summary: Select the minimum of three signed 16-bit integer inputs and store the selected value into a vector register.


Summary: Select the minimum of three signed 32-bit integer inputs and store the selected value into a vector register.


Summary: Select the IEEE minimumNumber() of three half-precision float inputs and store the selected value into a vector register.


Summary: Select the IEEE minimumNumber() of three single-precision float inputs and store the selected value into a vector register.


Summary: Select the minimum of three unsigned 16-bit integer inputs and store the selected value into a vector register.


Summary: Select the minimum of three unsigned 32-bit integer inputs and store the selected value into a vector register.


Summary: Select the minimum of two half-precision float inputs and store the result into a vector register.

if (WAVE_MODE.IEEE && isSignalNAN(64'F(S0.f16))) then
D0.f16 = 16'F(cvtToQuietNAN(64'F(S0.f16)))
elsif (WAVE_MODE.IEEE && isSignalNAN(64'F(S1.f16))) then
D0.f16 = 16'F(cvtToQuietNAN(64'F(S1.f16)))
elsif isNAN(64'F(S0.f16)) then
D0.f16 = S1.f16
elsif isNAN(64'F(S1.f16)) then
D0.f16 = S0.f16
elsif ((64'F(S0.f16) == +0.0) && (64'F(S1.f16) == -0.0)) then
D0.f16 = S1.f16
elsif ((64'F(S0.f16) == -0.0) && (64'F(S1.f16) == +0.0)) then
D0.f16 = S0.f16
else
// Note: there's no IEEE case here like there is for V_MAX_F16.
D0.f16 = S0.f16 < S1.f16 ? S0.f16 : S1.f16
endif

IEEE compliant. Supports denormals, round mode, exception flags, saturation.


Summary: Select the minimum of two single-precision float inputs and store the result into a vector register.

if (WAVE_MODE.IEEE && isSignalNAN(64'F(S0.f32))) then
D0.f32 = 32'F(cvtToQuietNAN(64'F(S0.f32)))
elsif (WAVE_MODE.IEEE && isSignalNAN(64'F(S1.f32))) then
D0.f32 = 32'F(cvtToQuietNAN(64'F(S1.f32)))
elsif isNAN(64'F(S0.f32)) then
D0.f32 = S1.f32
elsif isNAN(64'F(S1.f32)) then
D0.f32 = S0.f32
elsif ((64'F(S0.f32) == +0.0) && (64'F(S1.f32) == -0.0)) then
D0.f32 = S1.f32
elsif ((64'F(S0.f32) == -0.0) && (64'F(S1.f32) == +0.0)) then
D0.f32 = S0.f32
else
// Note: there's no IEEE case here like there is for V_MAX_F32.
D0.f32 = S0.f32 < S1.f32 ? S0.f32 : S1.f32
endif


Summary: Select the minimum of two double-precision float inputs and store the selected value into a vector register.


Summary: Select the minimum of two signed 16-bit integer inputs and store the selected value into a vector register.


Summary: Select the minimum of two signed 32-bit integer inputs and store the selected value into a vector register.


Summary: AMDGPU VOP3 vector instruction operating on i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU VOP2 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Select the IEEE minimumNumber() of two half-precision float inputs and store the selected value into a vector register.


Summary: Select the IEEE minimumNumber() of two single-precision float inputs and store the selected value into a vector register.


Summary: Select the IEEE minimumNumber() of two double-precision float inputs and store the selected value into a vector register.


Summary: Select the minimum of two unsigned 16-bit integer inputs and store the selected value into a vector register.


Summary: Select the minimum of two unsigned 32-bit integer inputs and store the selected value into a vector register.


Summary: AMDGPU VOP3 vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Select the IEEE minimum() of three half-precision float inputs and store the selected value into a vector register.


Summary: Select the IEEE minimum() of three single-precision float inputs and store the result into a vector register.


Summary: Select the IEEE minimum() of two half-precision float inputs and store the selected value into a vector register.


Summary: Select the IEEE minimum() of two single-precision float inputs and store the selected value into a vector register.


Summary: Select the IEEE minimum() of two double-precision float inputs and store the selected value into a vector register.


Summary: Select the IEEE minimum() of the first two half-precision float inputs and then select the IEEE maximum() of that result and third half-precision…

Select the IEEE minimum() of the first two half-precision float inputs and then select the IEEE maximum() of that result and third half-precision float input. Store the final result into a vector register.


Summary: Select the IEEE minimum() of the first two single-precision float inputs and then select the IEEE maximum() of that result and third single-precision…

Select the IEEE minimum() of the first two single-precision float inputs and then select the IEEE maximum() of that result and third single-precision float input. Store the final result into a vector register.


Select the minimum of the first two half-precision float inputs and then select the maximum of that result and third half-precision float input. Store the final result into a vector register.


Select the minimum of the first two single-precision float inputs and then select the maximum of that result and third single-precision float input. Store the final result into a vector register.


Select the minimum of the first two signed 32-bit integer inputs and then select the maximum of that result and third signed 32-bit integer input. Store the final result into a vector register.


Summary: Select the IEEE minimumNumber() of the first two half-precision float inputs and then select the IEEE maximumNumber() of that result and third…

Select the IEEE minimumNumber() of the first two half-precision float inputs and then select the IEEE maximumNumber() of that result and third half-precision float input. Store the final result into a vector register.


Summary: Select the IEEE minimumNumber() of the first two single-precision float inputs and then select the IEEE maximumNumber() of that result and third…

Select the IEEE minimumNumber() of the first two single-precision float inputs and then select the IEEE maximumNumber() of that result and third single-precision float input. Store the final result into a vector register.


Select the minimum of the first two unsigned 32-bit integer inputs and then select the maximum of that result and third unsigned 32-bit integer input. Store the final result into a vector register.


Summary: Move 16-bit data from a vector input into a vector register.


Summary: Move 32-bit data from a vector input into a vector register.

v_mov_b32 v0, v1    // Move into v0 from v1
v_mov_b32 v0, -v1   // Set v0 to the negation of v1
v_mov_b32 v0, abs(v1)   // Set v0 to the absolute value of v1

Floating-point modifiers are valid for this instruction if S0 is a 32-bit floating point value. This instruction is suitable for negating or taking the absolute value of a floating-point value.


Summary: Move data from a 64-bit vector input into a vector register.

Floating-point modifiers are valid for this instruction if S0.u64 is a 64-bit floating point value. This instruction is suitable for negating or taking the absolute value of a floating-point value.


Summary: Move data from a vector input into a relatively-indexed vector register.


Summary: Move data from a relatively-indexed vector register into another vector register.


Summary: Move data from a relatively-indexed vector register into another relatively-indexed vector register.


Summary: Perform the V_MSAD_U8 operation four times using different slices of the first array, all entries of the second array and each entry of the third…

Perform the V_MSAD_U8 operation four times using different slices of the first array, all entries of the second array and each entry of the third array. Truncate each result to 16 bits, pack the values into a 4-entry array and store the array into a vector register. The first input is an 8-entry array of unsigned 8-bit integers, the second input is a 4-entry array of unsigned 8-bit integers and the third input is a 4-entry array of unsigned 16-bit integers.


Perform the V_MSAD_U8 operation four times using different slices of the first array, all entries of the second array and each entry of the third array. Pack each 32-bit value into a 4-entry array and store the array into a vector register. The first input is an 8-entry array of unsigned 8-bit integers, the second input is a 4-entry array of unsigned 8-bit integers and the third input is a 4-entry array of unsigned 32-bit integers.


Summary: Calculate the sum of absolute differences of elements in two packed 4-component unsigned 8-bit integer inputs, except that elements where the second…

Calculate the sum of absolute differences of elements in two packed 4-component unsigned 8-bit integer inputs, except that elements where the second input (known as the reference input) is zero are not included in the sum. Add an unsigned 32-bit integer value from the third input and store the result into a vector register.

Overflow into the upper bits is allowed.


Summary: Multiply two floating point inputs and store the result into a vector register.

0.5ULP precision. Supports denormals, round mode, exception flags and saturation.


Summary: Per-lane single-precision floating-point multiply.

VDST[lane] = S0[lane].f32 * S1[lane].f32 for each active lane.

v_mul_f32  v2, v0, v1   // per-lane v2 = v0 * v1


Summary: AMDGPU VOP2 vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Multiply two signed 32-bit integer inputs and store the high 32 bits of the result into a vector register.

To multiply integers with small magnitudes consider V_MUL_HI_I32_I24, which is intended to be a more efficient implementation.


Summary: Multiply two signed 24-bit integer inputs and store the high 32 bits of the result as a signed 32-bit integer into a vector register.


Summary: Multiply two unsigned 32-bit integer inputs and store the high 32 bits of the result into a vector register.

To multiply integers with small magnitudes consider V_MUL_HI_U32_U24, which is intended to be a more efficient implementation.


Summary: Multiply two unsigned 24-bit integer inputs and store the high 32 bits of the result as an unsigned 32-bit integer into a vector register.


Summary: Multiply two signed 24-bit integer inputs and store the result as a signed 32-bit integer into a vector register.

This opcode is expected to be as efficient as basic single-precision opcodes since it utilizes the single-precision floating point multiplier. See also V_MUL_HI_I32_I24.


Multiply two floating point inputs and store the result into a vector register. Follows DX9 rules where 0.0 times anything produces 0.0 (this differs from other APIs when the other input is infinity or NaN).


Summary: AMDGPU VOP3 vector instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Multiply two unsigned 16-bit integer inputs and store the low bits of the result into a vector register.

Supports saturation (unsigned 16-bit integer domain).


Summary: Per-lane 32-bit unsigned multiply, low half of the product.

Multiply two unsigned 32-bit integer inputs and store the result into a vector register.

VDST[lane] = lo32(S0[lane].u32 * S1[lane].u32) for each active lane.

v_mul_lo_u32  v2, v0, v1   // per-lane low 32 bits of v0 * v1


Summary: Multiply two unsigned 24-bit integer inputs and store the result as an unsigned 32-bit integer into a vector register.

This opcode is expected to be as efficient as basic single-precision opcodes since it utilizes the single-precision floating point multiplier. See also V_MUL_HI_U32_U24.


Summary: AMDGPU VOP2 vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Multiply two floating point inputs and store the result into a vector register. Specific rules apply to accommodate lighting calculations: 0.0 * x = 0.0 and alternate INF, NAN, overflow rules apply.


Summary: Do nothing.

Do nothing.

This instruction can be used to insert a single-cycle bubble in the vector ALU pipeline. For multiple cycles repeat this opcode.


Summary: Calculate bitwise negation on a vector input and store the result into a vector register.


Input and output modifiers not supported.


Summary: Calculate the bitwise OR of three vector inputs and store the result into a vector register.


Summary: Calculate bitwise OR on two vector inputs and store the result into a vector register.


Summary: AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Pack two half-precision float values into a single 32-bit value and store the result into a vector register.


Summary: Permute a 64-bit value constructed from two vector inputs (most significant bits come from the first input) using a per-lane selector from the third…

Permute a 64-bit value constructed from two vector inputs (most significant bits come from the first input) using a per-lane selector from the third input. The lane selector allows each byte of the result to choose from any of the 8 input bytes, perform sign extension or pad with 0/1 bits. Store the result into a vector register.

BYTE_PERMUTE = lambda(data, sel) (
declare in : 8'B[8];
for i in 0 : 7 do
in[i] = data[i * 8 + 7 : i * 8].b8
endfor;
if sel.u32 >= 13U then
return 8'0xff
elsif sel.u32 == 12U then
return 8'0x0
elsif sel.u32 == 11U then
return in[7][7].b8 * 8'0xff
elsif sel.u32 == 10U then
return in[5][7].b8 * 8'0xff
elsif sel.u32 == 9U then
return in[3][7].b8 * 8'0xff
elsif sel.u32 == 8U then
return in[1][7].b8 * 8'0xff
else
return in[sel]
endif);
D0[31 : 24] = BYTE_PERMUTE({ S0.u32, S1.u32 }, S2.u32[31 : 24]);
D0[23 : 16] = BYTE_PERMUTE({ S0.u32, S1.u32 }, S2.u32[23 : 16]);
D0[15 : 8] = BYTE_PERMUTE({ S0.u32, S1.u32 }, S2.u32[15 : 8]);
D0[7 : 0] = BYTE_PERMUTE({ S0.u32, S1.u32 }, S2.u32[7 : 0])

Selects 0 through 7 select the corresponding byte of the 64-bit input value. Selects 8 through 11 are useful in modeling sign extension of a smaller-precision signed integer to a larger- precision result by replicating the leading bit of a selected byte. Selects 12 and 13 return padding values of 0 and 1 bits respectively. Note the MSBs of the 64-bit value being selected are stored in S0. This is counterintuitive for a little-endian architecture.


Summary: AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU VOP3 vector instruction operating on b8 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Perform arbitrary gather-style operation within a row (16 contiguous lanes).


Summary: Swap data between two vector registers. Odd rows of the first operand are swapped with even rows of the second operand (one row is 16 lanes).


Summary: Swap data between two vector registers. Rows 2 and 3 of the first operand are swapped with rows 0 and 1 of the second operand (one row is 16 lanes).


Summary: Perform a specific permutation across lanes where the high half and low half of a wave64 are swapped. Performs no operation in wave32 mode.


Summary: AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Perform arbitrary gather-style operation across two rows (each row is 16 contiguous lanes).


Summary: Flush the vector ALU pipeline through the destination cache.


Summary: AMDGPU VOP3P vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Add two packed half-precision float inputs component-wise and store the result into a vector register. No carry- in or carry-out support.


Summary: Add two packed single-precision float inputs component-wise and store the result into a vector register. No carry-in or carry-out support.


Summary: AMDGPU VOP3P vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Add two packed signed 16-bit integer inputs component-wise and store the result into a vector register. No carry-in or carry-out support.


Summary: AMDGPU VOP3P vector instruction operating on i16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU VOP3P vector instruction operating on u16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU VOP3P vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Add two packed unsigned 16-bit integer inputs component-wise and store the result into a vector register. No carry-in or carry-out support.


Summary: Given a packed shift count in the first vector input, calculate the component-wise arithmetic shift right (preserving sign bit) of the second packed…

Given a packed shift count in the first vector input, calculate the component-wise arithmetic shift right (preserving sign bit) of the second packed vector input and store the result into a vector register.


Summary: Multiply two packed half-precision float inputs component-wise and add a third input component-wise using fused multiply add, and store the result…

Multiply two packed half-precision float inputs component-wise and add a third input component-wise using fused multiply add, and store the result into a vector register.


Summary: Multiply two packed single-precision float inputs component-wise and add a third input component-wise using fused multiply add, and store the result…

Multiply two packed single-precision float inputs component-wise and add a third input component-wise using fused multiply add, and store the result into a vector register.


Summary: Multiply two packed half-precision float inputs component-wise and accumulate the result into the destination register using fused multiply add.


Summary: Given a packed shift count in the first vector input, calculate the component-wise logical shift left of the second packed vector input and store the…

Given a packed shift count in the first vector input, calculate the component-wise logical shift left of the second packed vector input and store the result into a vector register.


Summary: Given a packed shift count in the first vector input, calculate the component-wise logical shift right of the second packed vector input and store…

Given a packed shift count in the first vector input, calculate the component-wise logical shift right of the second packed vector input and store the result into a vector register.


Summary: Multiply two packed signed 16-bit integer inputs component-wise, add a packed signed 16-bit integer value from a third input component-wise, and…

Multiply two packed signed 16-bit integer inputs component-wise, add a packed signed 16-bit integer value from a third input component-wise, and store the result into a vector register.


Summary: Multiply two packed unsigned 16-bit integer inputs component-wise, add a packed unsigned 16-bit integer value from a third input component-wise, and…

Multiply two packed unsigned 16-bit integer inputs component-wise, add a packed unsigned 16-bit integer value from a third input component-wise, and store the result into a vector register.


Summary: AMDGPU VOP3P vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Select the component-wise maximum of two packed half-precision float inputs and store the result into a vector register.


Summary: Select the component-wise maximum of two packed signed 16-bit integer inputs and store the selected values into a vector register.


Summary: AMDGPU VOP3P vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Select the component-wise IEEE maximumNumber() of two packed half-precision float inputs and store the selected values into a vector register.


Summary: AMDGPU VOP3P vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Select the component-wise maximum of two packed unsigned 16-bit integer inputs and store the selected values into a vector register.


Summary: Select the component-wise IEEE maximum() of three half-precision float inputs and store the result into a vector register.


Summary: Select the component-wise IEEE maximum() of two packed half-precision float inputs and store the selected values into a vector register.


Summary: AMDGPU VOP3P vector instruction operating on i16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU VOP3P vector instruction operating on u16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Select the component-wise minimum of two packed half-precision float inputs and store the result into a vector register.


Summary: Select the component-wise minimum of two packed signed 16-bit integer inputs and store the selected values into a vector register.


Summary: Select the component-wise IEEE minimumNumber() of two packed half-precision float inputs and store the selected values into a vector register.


Summary: Select the component-wise minimum of two packed unsigned 16-bit integer inputs and store the selected values into a vector register.


Summary: Select the component-wise IEEE minimum() of three half-precision float inputs and store the result into a vector register.


Summary: Select the component-wise IEEE minimum() of two packed half-precision float inputs and store the selected values into a vector register.


Summary: Move data from two vector inputs into two vector registers.

The source operands are treated as 64 bit and are subject to alignment restrictions for both SGPR and VGPR. For two VGPR inputs this opcode can be used as an arbitrary gather by using OP_SEL to select either the even VGPR specified or the next odd VGPR. v_pk_mov_b32 v0, v2, v4 op_sel:[0,1] // evaluates v0 <- v2 and v1 <- v5. Due to scalar broadcast restrictions if two SGPRs are specified as operands, they must be the same SGPR. v_pk_mov_b32 v0, s6, s6 op_sel:[0,1] // 64-bit move from scalar s[6:7].


Summary: Multiply two packed half-precision float inputs component-wise and store the result into a vector register.


Summary: Multiply two packed single-precision float inputs component-wise and store the result into a vector register.


Summary: Multiply two packed unsigned 16-bit integer inputs component-wise and store the low bits of each resulting component into a vector register.


Subtract the second packed signed 16-bit integer input from the first input component-wise and store the result into a vector register. No carry-in or carry-out support.


Summary: AMDGPU VOP3P vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Subtract the second packed unsigned 16-bit integer input from the first input component-wise and store the result into a vector register. No carry-in or carry-out support.


Summary: Generate a pseudorandom number using an LFSR (linear feedback shift register) seeded with the vector input, then store the result into a vector…

Generate a pseudorandom number using an LFSR (linear feedback shift register) seeded with the vector input, then store the result into a vector register.


Summary: Perform the V_SAD_U8 operation four times using different slices of the first array, all entries of the second array and each entry of the third…

Perform the V_SAD_U8 operation four times using different slices of the first array, all entries of the second array and each entry of the third array. Truncate each result to 16 bits, pack the values into a 4-entry array and store the array into a vector register. The first input is an 8-entry array of unsigned 8-bit integers, the second input is a 4-entry array of unsigned 8-bit integers and the third input is a 4-entry array of unsigned 16-bit integers.


Summary: AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Calculate the reciprocal of the half-precision float input using IEEE rules and store the result into a vector register.


Summary: Calculate the reciprocal of the single-precision float input using IEEE rules and store the result into a vector register.

1ULP accuracy. Accuracy converges to < 0.5ULP when using the Newton-Raphson method and 2 FMA operations. Denormals are flushed.


Summary: Calculate the reciprocal of the double-precision float input using IEEE rules and store the result into a vector register.

This opcode has (2**29)ULP accuracy and supports denormals.


Calculate the reciprocal of the vector float input in a manner suitable for integer division and store the result into a vector register. This opcode is intended for use as part of an integer division macro.

D0.f32 = 1.0F / S0.f32;
// Can only raise integer DIV_BY_ZERO exception

Can raise integer DIV_BY_ZERO exception but cannot raise floating-point exceptions. To be used in an integer reciprocal macro by the compiler with one of the sequences listed below (depending on signed or unsigned operation). Unsigned usage: CVT_F32_U32 RCP_IFLAG_F32 MUL_F32 (2**32 - 1) CVT_U32_F32 Signed usage: CVT_F32_I32 RCP_IFLAG_F32 MUL_F32 (2**31 - 1) CVT_I32_F32


Summary: Read the value of a VGPR from the first active lane into a scalar register.

Read the scalar value in the lowest active lane of the input vector register and store it into a scalar register.

SDST = S0[first active lane in EXEC]; used to move a per-lane value into scalar (wavefront-uniform) state when all active lanes are known to agree.

v_readfirstlane_b32  s0, v0   // s0 = v0 from the first active lane


Summary: Read the scalar value in the specified lane of the first input where the lane select is in the second input. Store the result into a scalar register.


Summary: Round the half-precision float input to the nearest even integer and store the result in floating point format into a vector register.


Summary: Round the single-precision float input to the nearest even integer and store the result in floating point format into a vector register.


Summary: Round the double-precision float input to the nearest even integer and store the result in floating point format into a vector register.


Summary: Calculate the reciprocal of the square root of the half-precision float input using IEEE rules and store the result into a vector register.


Summary: Per-lane fast approximate reciprocal square root.

Calculate the reciprocal of the square root of the single-precision float input using IEEE rules and store the result into a vector register.

VDST[lane] ≈ 1 / sqrt(S0[lane].f32) for each active lane, with a hardware-specific ULP error bound.

v_rsq_f32  v1, v0   // v1 = approx(1 / sqrt(v0))


Summary: Calculate the reciprocal of the square root of the double-precision float input using IEEE rules and store the result into a vector register.


Summary: Calculate 2 raised to the power of the half-precision float input and store the result into a scalar register.


Summary: Calculate 2 raised to the power of the single-precision float input and store the result into a scalar register.


Summary: Calculate the base 2 logarithm of the half-precision float input and store the result into a scalar register.


Summary: Calculate the base 2 logarithm of the single-precision float input and store the result into a scalar register.


Summary: Calculate the reciprocal of the half-precision float input using IEEE rules and store the result into a scalar register.


Summary: Calculate the reciprocal of the single-precision float input using IEEE rules and store the result into a scalar register.


Summary: Calculate the reciprocal of the square root of the half-precision float input using IEEE rules and store the result into a scalar register.


Summary: Calculate the reciprocal of the square root of the single-precision float input using IEEE rules and store the result into a scalar register.


Summary: Calculate the square root of the half-precision float input using IEEE rules and store the result into a scalar register.


Summary: Calculate the square root of the single-precision float input using IEEE rules and store the result into a scalar register.


Summary: Calculate the sum of absolute differences of elements in two packed 4-component unsigned 8-bit integer inputs, shift the sum left by 16 bits, add an…

Calculate the sum of absolute differences of elements in two packed 4-component unsigned 8-bit integer inputs, shift the sum left by 16 bits, add an unsigned 32-bit integer value from the third input and store the result into a vector register.


Summary: Calculate the sum of absolute differences of elements in two packed 2-component unsigned 16-bit integer inputs, add an unsigned 32-bit integer value…

Calculate the sum of absolute differences of elements in two packed 2-component unsigned 16-bit integer inputs, add an unsigned 32-bit integer value from the third input and store the result into a vector register.


Summary: Calculate the absolute difference of two unsigned 32-bit integer inputs, add an unsigned 32-bit integer value from the third input and store the…

Calculate the absolute difference of two unsigned 32-bit integer inputs, add an unsigned 32-bit integer value from the third input and store the result into a vector register.

ABSDIFF = lambda(x, y) (
x > y ? x - y : y - x);
// UNSIGNED comparison
D0.u32 = ABSDIFF(S0.u32, S1.u32) + S2.u32


Summary: Calculate the sum of absolute differences of elements in two packed 4-component unsigned 8-bit integer inputs, add an unsigned 32-bit integer value…

Calculate the sum of absolute differences of elements in two packed 4-component unsigned 8-bit integer inputs, add an unsigned 32-bit integer value from the third input and store the result into a vector register.


Summary: AMDGPU VOP1 vector instruction operating on i8 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU VOP1 vector instruction operating on u8 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Given 2 signed 16-bit integer inputs, saturate each input over an unsigned 8-bit integer range, pack the resulting values into a packed 16-bit value…

Given 2 signed 16-bit integer inputs, saturate each input over an unsigned 8-bit integer range, pack the resulting values into a packed 16-bit value and store the result into a vector register.

Used for 4x16bit data packed as 4x8bit data.


4SE version of LUT instruction for screen partitioning/filtering. This opcode is intended to help accelerate screen partitioning in the 4SE case only. 2SE and 1SE cases use normal ALU instructions.


Summary: AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Calculate the trigonometric sine of a half-precision float value using IEEE rules and store the result into a vector register. The operand is calculated by scaling the vector input by 2 PI.

Denormals are supported. Full range input is supported.


Summary: Per-lane fast approximate sine.

Calculate the trigonometric sine of a single-precision float value using IEEE rules and store the result into a vector register. The operand is calculated by scaling the vector input by 2 PI.

Source operand (radians, pre-scaled per hardware convention)

VDST[lane] ≈ sin(S0[lane].f32) for each active lane, valid over a hardware-defined input range.

v_sin_f32  v1, v0   // v1 = approx(sin(v0))


Summary: Multiply the 16x128 sparse matrix in the first input by the 128x16 matrix in the second input and accumulate the result into the 16x16 matrix stored…

Multiply the 16x128 sparse matrix in the first input by the 128x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.


Summary: AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Multiply the 16x32 sparse matrix in the first input by the 32x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in…

Multiply the 16x32 sparse matrix in the first input by the 32x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.

D = A (sparse 16x32) * B (32x16) + D (16x16)
Each operand contains a single matrix whose elements are distributed across all lanes of the wave. A single
matrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher
performance.
Matrix A is a sparse matrix in BF16 float format, consuming half the physical storage of a dense matrix with
same dimensions. Matrix B is a dense matrix in BF16 float format. Matrix D is single-precision float format and
is both the output and the accumulate input.
2 out of every 4 elements on the K axis of matrix A are zero. The sparse indexes are used to determine which 2
elements are zero.


D = A (sparse 16x32) * B (32x16) + D (16x16)
Each operand contains a single matrix whose elements are distributed across all lanes of the wave. A single
matrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher
performance.
Matrix A is a sparse matrix in half-precision float format, consuming half the physical storage of a dense
matrix with same dimensions. Matrix B is a dense matrix in half-precision float format. Matrix D is single-precision float format and is both the output and the accumulate input.
2 out of every 4 elements on the K axis of matrix A are zero. The sparse indexes are used to determine which 2
elements are zero.


Summary: Multiply the 16x64 sparse matrix in the first input by the 64x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in…

Multiply the 16x64 sparse matrix in the first input by the 64x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.


D = A (sparse 16x64) * B (64x16) + D (16x16)
Each operand contains a single matrix whose elements are distributed across all lanes of the wave. A single
matrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher
performance.
Matrix A is a sparse matrix in BF8 float format, consuming half the physical storage of a dense matrix with
same dimensions. Matrix B is a dense matrix in BF8 float format. Matrix D is single-precision float format and
is both the output and the accumulate input.
2 out of every 4 elements on the K axis of matrix A are zero. The sparse indexes are used to determine which 2
elements are zero.


D = A (sparse 16x64) * B (64x16) + D (16x16)
Each operand contains a single matrix whose elements are distributed across all lanes of the wave. A single
matrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher
performance.
Matrix A is a sparse matrix in BF8 float format, consuming half the physical storage of a dense matrix with
same dimensions. Matrix B is a dense matrix in FP8 float format. Matrix D is single-precision float format and
is both the output and the accumulate input.
2 out of every 4 elements on the K axis of matrix A are zero. The sparse indexes are used to determine which 2
elements are zero.


D = A (sparse 16x64) * B (64x16) + D (16x16)
Each operand contains a single matrix whose elements are distributed across all lanes of the wave. A single
matrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher
performance.
Matrix A is a sparse matrix in FP8 float format, consuming half the physical storage of a dense matrix with
same dimensions. Matrix B is a dense matrix in BF8 float format. Matrix D is single-precision float format and
is both the output and the accumulate input.
2 out of every 4 elements on the K axis of matrix A are zero. The sparse indexes are used to determine which 2
elements are zero.


D = A (sparse 16x64) * B (64x16) + D (16x16)
Each operand contains a single matrix whose elements are distributed across all lanes of the wave. A single
matrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher
performance.
Matrix A is a sparse matrix in FP8 float format, consuming half the physical storage of a dense matrix with
same dimensions. Matrix B is a dense matrix in FP8 float format. Matrix D is single-precision float format and
is both the output and the accumulate input.
2 out of every 4 elements on the K axis of matrix A are zero. The sparse indexes are used to determine which 2
elements are zero.


Summary: Multiply the 32x16 sparse matrix in the first input by the 16x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in…

Multiply the 32x16 sparse matrix in the first input by the 16x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.

D = A (sparse 32x16) * B (16x32) + D (32x32)
Each operand contains a single matrix whose elements are distributed across all lanes of the wave. A single
matrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher
performance.
Matrix A is a sparse matrix in BF16 float format, consuming half the physical storage of a dense matrix with
same dimensions. Matrix B is a dense matrix in BF16 float format. Matrix D is single-precision float format and
is both the output and the accumulate input.
2 out of every 4 elements on the K axis of matrix A are zero. The sparse indexes are used to determine which 2
elements are zero.


D = A (sparse 32x16) * B (16x32) + D (32x32)
Each operand contains a single matrix whose elements are distributed across all lanes of the wave. A single
matrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher
performance.
Matrix A is a sparse matrix in half-precision float format, consuming half the physical storage of a dense
matrix with same dimensions. Matrix B is a dense matrix in half-precision float format. Matrix D is single-precision float format and is both the output and the accumulate input.
2 out of every 4 elements on the K axis of matrix A are zero. The sparse indexes are used to determine which 2
elements are zero.


Summary: Multiply the 32x32 sparse matrix in the first input by the 32x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in…

Multiply the 32x32 sparse matrix in the first input by the 32x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.


D = A (sparse 32x32) * B (32x32) + D (32x32)
Each operand contains a single matrix whose elements are distributed across all lanes of the wave. A single
matrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher
performance.
Matrix A is a sparse matrix in BF8 float format, consuming half the physical storage of a dense matrix with
same dimensions. Matrix B is a dense matrix in BF8 float format. Matrix D is single-precision float format and
is both the output and the accumulate input.
2 out of every 4 elements on the K axis of matrix A are zero. The sparse indexes are used to determine which 2
elements are zero.


D = A (sparse 32x32) * B (32x32) + D (32x32)
Each operand contains a single matrix whose elements are distributed across all lanes of the wave. A single
matrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher
performance.
Matrix A is a sparse matrix in BF8 float format, consuming half the physical storage of a dense matrix with
same dimensions. Matrix B is a dense matrix in FP8 float format. Matrix D is single-precision float format and
is both the output and the accumulate input.
2 out of every 4 elements on the K axis of matrix A are zero. The sparse indexes are used to determine which 2
elements are zero.


D = A (sparse 32x32) * B (32x32) + D (32x32)
Each operand contains a single matrix whose elements are distributed across all lanes of the wave. A single
matrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher
performance.
Matrix A is a sparse matrix in FP8 float format, consuming half the physical storage of a dense matrix with
same dimensions. Matrix B is a dense matrix in BF8 float format. Matrix D is single-precision float format and
is both the output and the accumulate input.
2 out of every 4 elements on the K axis of matrix A are zero. The sparse indexes are used to determine which 2
elements are zero.


D = A (sparse 32x32) * B (32x32) + D (32x32)
Each operand contains a single matrix whose elements are distributed across all lanes of the wave. A single
matrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher
performance.
Matrix A is a sparse matrix in FP8 float format, consuming half the physical storage of a dense matrix with
same dimensions. Matrix B is a dense matrix in FP8 float format. Matrix D is single-precision float format and
is both the output and the accumulate input.
2 out of every 4 elements on the K axis of matrix A are zero. The sparse indexes are used to determine which 2
elements are zero.


Summary: Multiply the 32x64 sparse matrix in the first input by the 64x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in…

Multiply the 32x64 sparse matrix in the first input by the 64x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.


Summary: AMDGPU VOP3P matrix instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


D = A (sparse 16x64) * B (64x16) + D (16x16)
Each operand contains a single matrix whose elements are distributed across all lanes of the wave. A single
matrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher
performance.
Matrix A is a sparse matrix in signed 8-bit integer format, consuming half the physical storage of a dense
matrix with same dimensions. Matrix B is a dense matrix in signed 8-bit integer format. Matrix D is signed 32-
bit integer format and is both the output and the accumulate input.
2 out of every 4 elements on the K axis of matrix A are zero. The sparse indexes are used to determine which 2
elements are zero.


D = A (sparse 32x32) * B (32x32) + D (32x32)
Each operand contains a single matrix whose elements are distributed across all lanes of the wave. A single
matrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher
performance.
Matrix A is a sparse matrix in signed 8-bit integer format, consuming half the physical storage of a dense
matrix with same dimensions. Matrix B is a dense matrix in signed 8-bit integer format. Matrix D is signed 32-
bit integer format and is both the output and the accumulate input.
2 out of every 4 elements on the K axis of matrix A are zero. The sparse indexes are used to determine which 2
elements are zero.


Summary: Calculate the square root of the half-precision float input using IEEE rules and store the result into a vector register.


Summary: Calculate the square root of the single-precision float input using IEEE rules and store the result into a vector register.


Summary: Calculate the square root of the double-precision float input using IEEE rules and store the result into a vector register.


Summary: Subtract the second unsigned 32-bit integer input from the first input, store the result into a vector register and store the carry-out mask into a…

Subtract the second unsigned 32-bit integer input from the first input, store the result into a vector register and store the carry-out mask into a scalar register.

tmp = S0.u32 - S1.u32;
VCC.u64[laneId] = S1.u32 > S0.u32 ? 1'1U : 1'0U;
// VCC is an UNSIGNED overflow/carry-out for V_SUBB_CO_U32.
D0.u32 = tmp.u32

In VOP3 the VCC destination may be an arbitrary SGPR-pair. Supports saturation (unsigned 32-bit integer domain).


Summary: Subtract the second floating point input from the first input and store the result into a vector register.


Summary: Per-lane single-precision floating-point subtract.

VDST[lane] = S0[lane].f32 - S1[lane].f32 for each active lane.

v_sub_f32  v2, v0, v1   // per-lane v2 = v0 - v1


Summary: Subtract the second signed 16-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support.

Supports saturation (signed 16-bit integer domain).


Summary: Subtract the second signed 32-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support.


Summary: Subtract the second unsigned 16-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support.


Summary: AMDGPU VOP2 vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Subtract the second unsigned 32-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support.

Supports saturation (unsigned 32-bit integer domain).


Summary: Subtract the second unsigned 32-bit integer input from the first input, subtract a bit from the carry-in mask, store the result into a vector…

Subtract the second unsigned 32-bit integer input from the first input, subtract a bit from the carry-in mask, store the result into a vector register and store the carry-out mask into a scalar register.

tmp = S0.u32 - S1.u32 - VCC.u64[laneId].u32;
VCC.u64[laneId] = 64'U(S1.u32) + VCC.u64[laneId].u64 > 64'U(S0.u32) ? 1'1U : 1'0U;
// VCC is an UNSIGNED overflow/carry-out for V_SUBB_CO_U32.
D0.u32 = tmp.u32

In VOP3 the VCC destination may be an arbitrary SGPR-pair, and the VCC source comes from the SGPR-pair at S2.u. Supports saturation (unsigned 32-bit integer domain).


Summary: AMDGPU VOP2 vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Subtract the first unsigned 32-bit integer input from the second input, subtract a bit from the carry-in mask, store the result into a vector…

Subtract the first unsigned 32-bit integer input from the second input, subtract a bit from the carry-in mask, store the result into a vector register and store the carry-out mask into a scalar register.

tmp = S1.u32 - S0.u32 - VCC.u64[laneId].u32;
VCC.u64[laneId] = 64'U(S0.u32) + VCC.u64[laneId].u64 > 64'U(S1.u32) ? 1'1U : 1'0U;
// VCC is an UNSIGNED overflow/carry-out for V_SUBB_CO_U32.
D0.u32 = tmp.u32


Summary: Subtract the first unsigned 32-bit integer input from the second input, store the result into a vector register and store the carry-out mask into a…

Subtract the first unsigned 32-bit integer input from the second input, store the result into a vector register and store the carry-out mask into a scalar register.

tmp = S1.u32 - S0.u32;
VCC.u64[laneId] = S0.u32 > S1.u32 ? 1'1U : 1'0U;
// VCC is an UNSIGNED overflow/carry-out for V_SUBB_CO_U32.
D0.u32 = tmp.u32


Summary: Subtract the first floating point input from the second input and store the result into a vector register.

0.5ULP precision. Supports denormals, round mode, exception flags and saturation.


0.5ULP precision, denormals are supported.


Summary: AMDGPU VOP2 vector instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Subtract the first unsigned 16-bit integer input from the second input and store the result into a vector register. No carry-in or carry-out support.

Supports saturation (unsigned 16-bit integer domain).


Summary: Subtract the first unsigned 32-bit integer input from the second input and store the result into a vector register. No carry-in or carry-out support.


Summary: Swap the values in two vector registers.


Input and output modifiers not supported; this is an untyped operation.


Summary: Swap the values in two relatively-indexed vector registers.


Summary: AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU VOP1 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Look up a 53-bit segment of 2/PI using an integer segment select in the second input. Scale the intermediate result by the exponent from the first double-precision float input and store the double-precision float result into a vector register. This operation returns an aligned, double precision segment of 2/PI needed to do trigonometric argument reduction on the floating point input. Multiple segments can be accessed using the first input. Rounding is toward zero. Large floating point inputs (with an exponent > 1968) are scaled to avoid loss of precision through denormalization.

shift = 32'I(S1[4 : 0].u32) * 53;
if exponent(S0.f64) > 1077 then
shift += exponent(S0.f64) - 1077
endif;
// (2.0/PI) == 0.{b_1200, b_1199, b_1198, ..., b_1, b_0}
// b_1200 is the MSB of the fractional part of 2.0/PI
// Left shift operation indicates which bits are brought
// into the whole part of the number.
// Only whole part of result is kept.
result = 64'F((1201'B(2.0 / PI)[1200 : 0] << shift.u32) & 1201'0x1fffffffffffff);
scale = -53 - shift;
if exponent(S0.f64) >= 1968 then
scale += 128
endif;
D0.f64 = ldexp(result, scale)

For a more complete treatment of trigonometric argument reduction refer to Argument Reduction for Huge Arguments: Good to the Last Bit, K. C. Ng et.al., March 1992, available online.


Summary: Compute the integer part of a half-precision float input using round toward zero semantics and store the result in floating point format into a…

Compute the integer part of a half-precision float input using round toward zero semantics and store the result in floating point format into a vector register.


Summary: Compute the integer part of a single-precision float input using round toward zero semantics and store the result in floating point format into a…

Compute the integer part of a single-precision float input using round toward zero semantics and store the result in floating point format into a vector register.


Summary: Compute the integer part of a double-precision float input using round toward zero semantics and store the result in floating point format into a…

Compute the integer part of a double-precision float input using round toward zero semantics and store the result in floating point format into a vector register.


Summary: AMDGPU VOP3P matrix instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU VOP3P matrix instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Write the scalar value in the first input into the specified lane of a vector register where the lane select is in the second input.


Summary: Calculate bitwise XOR of the first two vector inputs, then add the third vector input to the intermediate result, then store the final result into a…

Calculate bitwise XOR of the first two vector inputs, then add the third vector input to the intermediate result, then store the final result into a vector register.

No carryin/carryout and no saturation. This opcode is designed to help accelerate the SHA256 hash algorithm.


Summary: Calculate bitwise XNOR on two vector inputs and store the result into a vector register.

Input and output modifiers not supported.


Summary: Calculate the bitwise XOR of three vector inputs and store the result into a vector register.


Summary: Calculate bitwise XOR on two vector inputs and store the result into a vector register.


Summary: AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)