Summary: Loads vector data from memory (interleaved or sequential).

Loads one or more NEON vectors from memory at an address specified by a general-purpose register, with optional post-index update. The instruction supports contiguous or strided loading patterns depending on the type field. No condition flags are affected. This is an ARMv7 Advanced SIMD memory instruction, executable in both A32 and T32 states.

address ← Rn
for each register in list
  load vector from address
  address ← address + stride
if writeback
  Rn ← Rn + total_bytes_loaded


Vector Load Multiple (2-Element Structure)

Summary: De-interleaves 2 streams of data while loading.

Rn

First source / base general-purpose register

Loads two streams of interleaved data from memory and de-interleaves them into separate 128-bit NEON vectors. The instruction handles 2-element structures, reading from memory and distributing elements to the destination registers in a de-interleaved pattern. No condition flags are affected. This is an ARMv7 Advanced SIMD memory instruction, executable in both A32 and T32 states.

address ← Rn
for each 2-element structure at address
  element0 ← memory[address]
  element1 ← memory[address + size_bytes]
  store element0 in first destination register
  store element1 in second destination register
  address ← address + 2 * size_bytes
if writeback
  Rn ← Rn + total_bytes_loaded


Summary: Selects maximum value from elements.

Compares corresponding lanes of two 128-bit NEON vectors and stores the maximum value in each lane of the destination. The comparison is performed element-wise according to the data type (signed or unsigned integer). No condition flags are affected. This is an ARMv7 Advanced SIMD instruction, executable in both A32 and T32 states.

for each lane i of size specified by dt
  if Qn[i] > Qm[i]
    Qd[i] ← Qn[i]
  else
    Qd[i] ← Qm[i]


Summary: Selects minimum value from elements.

Performs element-wise minimum operation on two 128-bit SIMD registers, selecting the smaller value from each corresponding pair of elements. The data type (sz field) determines whether elements are 32-bit or 16-bit integers. Condition flags N, Z, C, V are unaffected. This is an A32/T32 NEON instruction with no privilege restrictions.

for i = 0 to (128 / element_width) - 1:
  Qd[i] ← min(Qn[i], Qm[i])


Summary: Multiplies and adds to accumulator.

Multiplies corresponding elements from two source registers and accumulates (adds) the products into the destination register. Performs Qd ← Qd + (Qn × Qm) for each element. The sz field specifies 16-bit or 32-bit element width. Condition flags are unaffected. This is an A32/T32 NEON instruction with no privilege restrictions.

for i = 0 to (128 / element_width) - 1:
  product ← Qn[i] × Qm[i]
  Qd[i] ← Qd[i] + product


Summary: Multiplies and subtracts from accumulator.

Multiplies corresponding elements from two source registers and subtracts the products from the accumulator. Performs Qd ← Qd - (Qn × Qm) for each element. The sz field specifies 16-bit or 32-bit element width. Condition flags are unaffected. This is an A32/T32 NEON instruction with no privilege restrictions.

for i = 0 to (128 / element_width) - 1:
  product ← Qn[i] × Qm[i]
  Qd[i] ← Qd[i] - product


Summary: Moves immediate value into vector.

Vector Move (Immediate) moves an immediate value into all elements of a 128-bit NEON register. The immediate is replicated across elements according to the data type (8, 16, 32, or 64 bits) and element expansion mode (cmode). No flags are affected. This is a NEON instruction available in both A32 and T32 states when NEON is supported.

imm_expanded ← ExpandImmediate(imm, cmode)
for each element i in Qd:
  Qd[i] ← imm_expanded


Summary: Copies N-bit elements to 2N-bit elements (Widening).

Widens N-bit elements from a 64-bit source register to 2N-bit elements in a 128-bit destination register, with zero or sign extension based on the data type. The Q field and element size encoding determine which half of the source to use and the widening operation. Condition flags are unaffected. This is an A32/T32 NEON instruction with no privilege restrictions.

for i = 0 to (64 / source_element_width) - 1:
  Qd[i] ← ZeroExtend(Dm[i]) or SignExtend(Dm[i])


Summary: Copies 2N-bit elements to N-bit elements (Narrowing).

Narrows 2N-bit elements from a 128-bit source register to N-bit elements in a 64-bit destination register, discarding the upper bits. The sz field determines the source element size (16, 32, or 64 bits) and corresponding destination size. Condition flags are unaffected. This is an A32/T32 NEON instruction with no privilege restrictions.

for i = 0 to (128 / source_element_width) - 1:
  Dd[i] ← Qm[i][destination_element_width-1:0]


Summary: Multiplies elements.

Performs element-wise multiplication of two 128-bit SIMD registers, storing results in the destination. The sz field determines 16-bit or 32-bit element width. Condition flags N, Z, C, V are unaffected. This is an A32/T32 NEON instruction with no privilege restrictions.

for i = 0 to (128 / element_width) - 1:
  Qd[i] ← Qn[i] × Qm[i]


Summary: Multiplies N-bit elements producing 2N-bit results.

Multiplies N-bit elements from two 64-bit source registers to produce 2N-bit results in a 128-bit destination register. The sz field specifies 8, 16, or 32-bit source element width. Condition flags are unaffected. This is an A32/T32 NEON instruction with no privilege restrictions.

for i = 0 to (64 / source_element_width) - 1:
  Qd[i] ← Dn[i] × Dm[i]


Summary: Moves bitwise inverse of immediate/register.

Performs bitwise NOT (inversion) of all bits in a 128-bit SIMD register, storing the result in the destination. This is a data-type-independent operation that works on all bit patterns equally. Condition flags are unaffected. This is an A32/T32 NEON instruction with no privilege restrictions.


Summary: Negates integer/float elements.

Negates each element in the source vector and places the result in the destination register. For integer elements, the result is two's complement negation; for floating-point elements, only the sign bit is inverted. No condition flags are affected. Execution is available in both A32 and T32 instruction sets via NEON.

for i = 0 to elements-1
  Qd[i] ← -Qm[i]


Summary: Bitwise OR with NOT (Vd = Vn | ~Vm).

Performs bitwise OR of the first operand with the bitwise NOT of the second operand (Qd = Qn | ~Qm), element-wise. No condition flags are affected. Execution is available in both A32 and T32 instruction sets via NEON.

for i = 0 to 127
  Qd[i] ← Qn[i] | ~Qm[i]


Summary: Bitwise OR of two vectors.

Performs bitwise OR of two vectors element-wise (Qd = Qn | Qm). No condition flags are affected. Execution is available in both A32 and T32 instruction sets via NEON.

for i = 0 to 127
  Qd[i] ← Qn[i] | Qm[i]


Summary: Adds adjacent pairs of elements.

Adds adjacent pairs of elements from the source operands and places the results in the destination register, reducing dimensionality by half. For example, in 32-bit mode, pairs of adjacent 32-bit elements are summed to produce 4 results in the 64-bit destination. No condition flags are affected. Execution is available in both A32 and T32 instruction sets via NEON.


Summary: Minimum of adjacent pairs.

Computes the minimum of adjacent pairs of elements from the source operands and places the results in the destination register, reducing dimensionality by half. For each pair, the smaller element is selected. No condition flags are affected. Execution is available in both A32 and T32 instruction sets via NEON.


Summary: Maximum of adjacent pairs.

Computes the maximum of adjacent pairs of elements from the source operands and places the results in the destination register, reducing dimensionality by half. For each pair, the larger element is selected. No condition flags are affected. Execution is available in both A32 and T32 instruction sets via NEON.


Summary: Adds elements with saturation.

Adds corresponding elements from two vectors with saturation. If the result overflows or underflows, it is saturated to the data type's maximum or minimum representable value. No condition flags are affected; saturation status is not reflected in APSR. Execution is available in both A32 and T32 instruction sets via NEON.

for i = 0 to elements-1
  Qd[i] ← SatQ(Qn[i] + Qm[i], dt)


Summary: Subtracts elements with saturation.

Subtracts the second operand from the first with saturation. If the result overflows or underflows, it is saturated to the data type's maximum or minimum representable value. No condition flags are affected; saturation status is not reflected in APSR. Execution is available in both A32 and T32 instruction sets via NEON.

for i = 0 to elements-1
  Qd[i] ← SatQ(Qn[i] - Qm[i], dt)


Summary: Estimates reciprocal (1/x).

Computes a vector reciprocal estimate (1/x) for each element in the source register and stores the result in the destination register. This is a Newton-Raphson reciprocal estimate; the result is not fully accurate and is intended as a starting point for iterative refinement. Condition flags (N, Z, C, V) are not affected. Executes in A32/T32 with NEON extension; requires FPEXC.EN = 1 for floating-point operation.

for i = 0 to 127 by element_size:
  element ← Vm[i+element_size-1:i]
  Qd[i+element_size-1:i] ← RecipEstimate(element)


Summary: Estimates reciprocal square root (1/sqrt(x)).

Computes a vector reciprocal square root estimate (1/√x) for each element in the source register and stores the result in the destination register. This is a Newton-Raphson reciprocal square root estimate; the result serves as a starting point for iterative refinement. Condition flags (N, Z, C, V) are not affected. Executes in A32/T32 with NEON extension; requires FPEXC.EN = 1 for floating-point operation.

for i = 0 to 127 by element_size:
  element ← Qm[i+element_size-1:i]
  Qd[i+element_size-1:i] ← RecipSqrtEstimate(element)


Summary: Reverses bytes within 16-bit halfwords.

Reverses the byte order within each 16-bit halfword element in the source register. For example, bytes [1,0] become [0,1] within each 16-bit element. Condition flags (N, Z, C, V) are not affected. Executes in A32/T32 with NEON extension; operates on integer data types.


Summary: Reverses elements within 32-bit words.

Reverses the byte or halfword order within each 32-bit word element in the source register, depending on element size. For 8-bit elements, reverses bytes within words; for 16-bit elements, reverses halfwords within words. Condition flags (N, Z, C, V) are not affected. Executes in A32/T32 with NEON extension; operates on integer data types.

if element_size == 8:
  for i = 0 to 127 by 32:
    for j = 0 to 31 by 8:
      Qd[i+j+7:i+j] ← Qm[i+31-j:i+24-j]
else if element_size == 16:
  for i = 0 to 127 by 32:
    Qd[i+31:i+16] ← Qm[i+15:i+0]
    Qd[i+15:i+0] ← Qm[i+31:i+16]


Summary: Reverses elements within 64-bit doublewords.

Reverses the order of elements within each 64-bit doubleword in the source register. The granularity of reversal depends on element size: 8-bit elements are reversed within 64-bit units, 16-bit elements are reversed within 64-bit units, and 32-bit elements are reversed within 64-bit units. Condition flags (N, Z, C, V) are not affected. Executes in A32/T32 with NEON extension; operates on integer data types.

if element_size == 8:
  for i = 0 to 127 by 64:
    for j = 0 to 63 by 8:
      Qd[i+j+7:i+j] ← Qm[i+63-j:i+56-j]
else if element_size == 16:
  for i = 0 to 127 by 64:
    for j = 0 to 48 by 16:
      Qd[i+j+15:i+j] ← Qm[i+63-j:i+48-j]
else if element_size == 32:
  for i = 0 to 127 by 64:
    Qd[i+63:i+32] ← Qm[i+31:i+0]
    Qd[i+31:i+0] ← Qm[i+63:i+32]


Summary: Shifts elements left.

Shifts each element in the source register left by an immediate number of bits and stores the result in the destination register. Bits shifted out of the left end are lost, and zeros are shifted in from the right. The shift amount is applied uniformly to all elements and is encoded in the imm6 field, with the interpretation dependent on element size (sz). Condition flags (N, Z, C, V) are not affected. Executes in A32/T32 with NEON extension.

shift_amount ← DecodeImmShift(imm6, sz)  // Decodes imm6 based on element size
for i = 0 to 127 by element_size:
  element ← Qm[i+element_size-1:i]
  Qd[i+element_size-1:i] ← element << shift_amount


Summary: Shifts elements right.

Shifts each element in the source register right by an immediate number of bits, performing a logical (unsigned) or arithmetic (signed) shift depending on the data type, and stores the result in the destination register. For unsigned types, zeros are shifted in from the left; for signed types, the sign bit is extended. Condition flags (N, Z, C, V) are not affected. Executes in A32/T32 with NEON extension.

shift_amount ← DecodeImmShift(imm6, sz)  // Decodes imm6 based on element size
for i = 0 to 127 by element_size:
  element ← Qm[i+element_size-1:i]
  if is_signed_type:
    Qd[i+element_size-1:i] ← arithmetic_shift_right(element, shift_amount)
  else:
    Qd[i+element_size-1:i] ← element >> shift_amount


Summary: Shifts right and narrows result.

Shifts each element in the 128-bit source register right by an immediate number of bits, narrows the result to half-width, and stores the narrowed values in the 64-bit destination register. For example, 16-bit results from 32-bit elements are stored in a 64-bit destination. Condition flags (N, Z, C, V) are not affected. Executes in A32/T32 with NEON extension.

shift_amount ← DecodeImmShift(imm6, input_element_size)
output_element_size ← input_element_size / 2
for i = 0 to 63 by output_element_size:
  element ← Qm[i*2+input_element_size*2-1:i*2]
  shifted ← element >> shift_amount
  Dd[i+output_element_size-1:i] ← shifted[output_element_size-1:0]


Summary: Stores vector data to memory.

Stores one or more NEON vectors to memory at the address held in Rn. The <list> specifies the vector registers to store (1-4 registers), and <size> determines the element width (8, 16, 32, or 64 bits). If ! is present, Rn is post-indexed by the number of bytes stored. No flags are affected. Execution is restricted to A32/T32 with NEON support; privilege level is determined by the memory access.

address ← Rn
for each register in list:
  [address] ← register value (element size as specified)
  address ← address + (register_width_in_bytes)
if postindex:
  Rn ← Rn + (total_bytes_stored)


Summary: Subtracts integer elements.

Vector Subtract (Integer) performs element-wise subtraction of two NEON 128-bit registers, subtracting corresponding integer elements of size 8, 16, 32, or 64 bits. The instruction executes in Q-register (128-bit) mode and wraps on underflow without setting flags. This is a NEON SIMD instruction available in both A32 and T32 states when NEON is supported.

for each element i in Qd:
  Qd[i] ← Qn[i] - Qm[i]


Summary: Look up elements in a vector table.

Performs a table lookup where each element of Dm is used as an index into the table formed by one or more consecutive NEON registers in <list>, and the corresponding table element is written to Dd. Out-of-range indices produce a zero result. No flags are affected. Execution is restricted to A32/T32 with NEON support; the table may span 1-4 consecutive registers, controlled by the <len> encoding field.

for i ← 0 to (size_of_Dd / 8) - 1:
  index ← Dm[i*8 +: 8]
  if index < (len + 1) * 16:
    Dd[i*8 +: 8] ← table[index]
  else:
    Dd[i*8 +: 8] ← 0


Summary: Transposes elements of two vectors.

Transposes elements of two 128-bit NEON vectors Qd and Qm, swapping odd and even elements. The element size is determined by <dt> (8, 16, or 32 bits). After execution, Qd and Qm contain interleaved even/odd elements from the original vectors. No flags are affected. Execution is restricted to A32/T32 with NEON support.

temp_d ← Qd
temp_m ← Qm
for i ← 0 to (128 / element_width) - 1:
  if i is even:
    Qd[i * element_width +: element_width] ← temp_d[i * element_width +: element_width]
    Qm[i * element_width +: element_width] ← temp_m[i * element_width +: element_width]
  else:
    Qd[i * element_width +: element_width] ← temp_m[(i - 1) * element_width +: element_width]
    Qm[i * element_width +: element_width] ← temp_d[(i - 1) * element_width +: element_width]


Summary: Tests if any bits match (Vd = (Vn & Vm) != 0).

Tests if any bits match by computing (Qn AND Qm) per element and writing all 1s (matching element size) to Qd if the result is nonzero, else all 0s. Element size is determined by <dt>. No arithmetic flags are modified. Execution is restricted to A32/T32 with NEON support.

for i ← 0 to (128 / element_width) - 1:
  result ← Qn[i * element_width +: element_width] AND Qm[i * element_width +: element_width]
  if result != 0:
    Qd[i * element_width +: element_width] ← (element_width bits of 1s)
  else:
    Qd[i * element_width +: element_width] ← 0


Summary: De-interleaves vectors.

De-interleaves elements from two 128-bit NEON vectors by extracting all even-indexed or all odd-indexed elements and placing them into Qd and Qm respectively. Element size is determined by <dt>. No flags are affected. Execution is restricted to A32/T32 with NEON support.

temp_d ← Qd
temp_m ← Qm
for i ← 0 to (128 / (2 * element_width)) - 1:
  Qd[i * element_width +: element_width] ← temp_d[(2 * i) * element_width +: element_width]
  Qd[(64 + i) * element_width +: element_width] ← temp_m[(2 * i) * element_width +: element_width]
  Qm[i * element_width +: element_width] ← temp_d[(2 * i + 1) * element_width +: element_width]
  Qm[(64 + i) * element_width +: element_width] ← temp_m[(2 * i + 1) * element_width +: element_width]


Summary: Interleaves vectors.

Interleaves elements from two 128-bit NEON vectors by mixing even-indexed elements from Qd with odd-indexed elements from Qm and vice versa. Element size is determined by <dt>. No flags are affected. Execution is restricted to A32/T32 with NEON support.

temp_d ← Qd
temp_m ← Qm
for i ← 0 to (128 / (2 * element_width)) - 1:
  Qd[2 * i * element_width +: element_width] ← temp_d[i * element_width +: element_width]
  Qd[(2 * i + 1) * element_width +: element_width] ← temp_m[i * element_width +: element_width]
  Qm[2 * i * element_width +: element_width] ← temp_d[(64 + i) * element_width +: element_width]
  Qm[(2 * i + 1) * element_width +: element_width] ← temp_m[(64 + i) * element_width +: element_width]


Summary: Adds two register values and the Carry flag.

Wn

First source / base 32-bit integer register

Wm

Second source / offset 32-bit integer register

Adds Wn and Wm plus the Carry flag (C), placing the 32-bit result in Wd. The C flag is read but not modified by this instruction; use ADCS to update flags. Execution is available in AArch64 only.


Summary: Adds two 64-bit register values and the Carry flag.

Xn

First source / base 64-bit integer register

Xm

Second source / offset 64-bit integer register

Add with Carry adds two 64-bit register values and the Carry flag, storing the result in a 64-bit register. The N, Z, C, and V flags are not modified; use ADCS to update flags. This instruction is AArch64-only and executes at any privilege level.


Summary: Adds two register values and Carry, updating NZCV flags.

Adds Wn and Wm plus the Carry flag (C), placing the 32-bit result in Wd and updating the NZCV condition flags. The N, Z, C, and V flags are set based on the result: N if bit 31 is set, Z if the result is zero, C if an unsigned overflow occurs, V if a signed overflow occurs. Execution is available in AArch64 only.

result ← Wn + Wm + C
Wd ← result[0:31]
N ← result[31]
Z ← (result[0:31] == 0)
C ← result[32] (unsigned overflow)
V ← (overflow from signed addition)


Summary: Adds two 64-bit register values and Carry, updating NZCV flags.

Add with Carry and Set Flags adds two 64-bit register values and the Carry flag, updating the NZCV condition flags based on the result. The N flag reflects the sign of the result, Z is set if the result is zero, C is set on unsigned carry, and V is set on signed overflow. This instruction is AArch64-only and executes at any privilege level.

result ← Xn + Xm + C
Xd ← result
N ← result[63]
Z ← (result == 0)
C ← UnsignedOverflow(Xn, Xm, C)
V ← SignedOverflow(Xn, Xm, C)


Summary: Adds a register value and a sign/zero-extended register value.

ADD <Wd|Wsp>, <Wn|Wsp>, <Wm> {, <extend> {#<amount>}}

Adds a sign/zero-extended 32-bit register value to another 32-bit register and stores the result in the destination register. The extension type and optional shift amount are specified via the extend operand. Condition flags (N, Z, C, V) are not affected by this instruction.

Wd ← Wn + ExtendValue(Wm, extend, amount)


Summary: Adds a 64-bit register and an extended register value.

ADD <Xd|SP>, <Xn|SP>, <R><m> {, <extend> {#<amount>}}

Rm

Second source / offset general-purpose register

Adds a sign/zero-extended 64-bit register value to another 64-bit register and stores the result in the destination register. The extension type and optional shift amount determine how Rm is extended. Condition flags (N, Z, C, V) are not affected by this instruction.

Xd ← Xn + ExtendValue(Rm, extend, amount)


Summary: Adds a register value and an immediate value.

ADD <Wd|Wsp>, <Wn|Wsp>, #<imm> {, lsl #<shift>}

Adds a 12-bit immediate value (optionally shifted left by 0 or 12 bits) to a 32-bit register and stores the result in the destination register. Condition flags (N, Z, C, V) are not affected by this instruction. SP may be used as source or destination.


Summary: Adds a 64-bit register value and an immediate value.

ADD <Xd|SP>, <Xn|SP>, #<imm> {, lsl #<shift>}

Adds a 12-bit immediate value (optionally shifted left by 0 or 12 bits) to a 64-bit register and stores the result in the destination register. Condition flags (N, Z, C, V) are not affected by this instruction. SP may be used as source or destination.


Summary: Adds a register value and a shifted register value.

ADD <Wd>, <Wn>, <Wm> {, <shift> #<amount>}

Adds a shifted 32-bit register value to another 32-bit register and stores the result in the destination register. The shift type and amount are encoded in the imm6 field. Condition flags (N, Z, C, V) are not affected by this instruction.

Wd ← Wn + ShiftReg(Wm, shift_type, shift_amount)


Summary: Adds a 64-bit register value and a shifted register value.

ADD <Xd>, <Xn>, <Xm> {, <shift> #<amount>}

Adds a shifted 64-bit register value to another 64-bit register and stores the result in the destination register. The shift type and amount are encoded in the imm6 field. Condition flags (N, Z, C, V) are not affected by this instruction.

Xd ← Xn + ShiftReg(Xm, shift_type, shift_amount)


Summary: Adds and updates flags (Extended Register).

ADDS <Wd>, <Wn|Wsp>, <Wm> {, <extend> {#<amount>}}

Add and Set Flags adds a 32-bit register value (optionally extended or shifted) to a 32-bit register or stack pointer, updating the NZCV condition flags. The N flag reflects the sign of the result, Z is set if result is zero, C is set on unsigned carry, and V is set on signed overflow. This instruction is AArch64-only and executes at any privilege level.

shifted ← ExtendAndShift(Wm, option, imm3)
result ← Wn + shifted
Wd ← result
N ← result[31]
Z ← (result == 0)
C ← UnsignedOverflow(Wn, shifted)
V ← SignedOverflow(Wn, shifted)


Add and Set Flags (Extended Register 64-bit)

Summary: Adds and updates flags (Extended Register 64-bit).

ADDS <Xd>, <Xn|SP>, <R><m> {, <extend> {#<amount>}}

Add with extended register operand and set condition flags. Adds the sign-extended or zero-extended value of Rm to Xn, stores the result in Xd, and updates the N, Z, C, and V flags based on the result. AArch64-only instruction executing at any privilege level.

result ← Xn + ExtendValue(Rm, extend, amount)
Xd ← result
N ← result[63]
Z ← (result == 0)
C ← CarryOut(Xn, ExtendValue(Rm, extend, amount))
V ← OverflowFrom(Xn, ExtendValue(Rm, extend, amount))


Summary: Adds immediate and updates flags.

ADDS <Wd>, <Wn|Wsp>, #<imm> {, lsl #<shift>}

Add immediate value to 32-bit register and set condition flags. Adds a 12-bit immediate (optionally left-shifted by 0 or 12 bits) to Wn, stores the result in Wd, and updates the N, Z, C, and V flags based on the result. AArch64-only instruction executing at any privilege level.

imm_val ← imm12 << (sh * 12)
result ← Wn + imm_val
Wd ← result
N ← result[31]
Z ← (result == 0)
C ← CarryOut(Wn, imm_val)
V ← OverflowFrom(Wn, imm_val)


Summary: Adds immediate and updates flags (64-bit).

ADDS <Xd>, <Xn|SP>, #<imm> {, lsl #<shift>}

Add immediate value to 64-bit register and set condition flags. Adds a 12-bit immediate (optionally left-shifted by 0 or 12 bits) to Xn, stores the result in Xd, and updates the N, Z, C, and V flags based on the result. AArch64-only instruction executing at any privilege level.

imm_val ← imm12 << (sh * 12)
result ← Xn + imm_val
Xd ← result
N ← result[63]
Z ← (result == 0)
C ← CarryOut(Xn, imm_val)
V ← OverflowFrom(Xn, imm_val)


Summary: Adds shifted register and updates flags.

ADDS <Wd>, <Wn>, <Wm> {, <shift> #<amount>}

Add shifted 32-bit register to another and set condition flags. Adds the optionally shifted value of Wm to Wn, stores the result in Wd, and updates the N, Z, C, and V flags based on the result. AArch64-only instruction executing at any privilege level.

shifted_val ← Wm << amount
result ← Wn + shifted_val
Wd ← result
N ← result[31]
Z ← (result == 0)
C ← CarryOut(Wn, shifted_val)
V ← OverflowFrom(Wn, shifted_val)


Add and Set Flags (Shifted Register 64-bit)

Summary: Adds shifted register and updates flags (64-bit).

ADDS <Xd>, <Xn>, <Xm> {, <shift> #<amount>}

Add shifted 64-bit register to another and set condition flags. Adds the optionally shifted value of Xm to Xn, stores the result in Xd, and updates the N, Z, C, and V flags based on the result. AArch64-only instruction executing at any privilege level.

shifted_val ← Xm << amount
result ← Xn + shifted_val
Xd ← result
N ← result[63]
Z ← (result == 0)
C ← CarryOut(Xn, shifted_val)
V ← OverflowFrom(Xn, shifted_val)


Summary: Calculates the address of a label (PC +/- 1MB range).

Forms a PC-relative address by adding a signed 21-bit offset to the current PC and stores the result in the destination register. The immediate is composed of immhi (19 bits) and immlo (2 bits) and supports label references within ±1 MB. This is an AArch64-only instruction that does not affect condition flags.


Summary: Calculates page address of a label (PC +/- 4GB range).

Forms a PC-relative page address by shifting a signed 21-bit offset left by 12 bits and adding to the current PC (with lower 12 bits zeroed), storing the result in the destination register. Supports label references within ±4 GB and is typically used with subsequent ldr or add instructions for full address formation. This is an AArch64-only instruction that does not affect condition flags.

Xd ← (PC & ~0xFFF) + (SignExtend(immhi:immlo, 21) << 12)


Summary: Bitwise AND with logical immediate.

Bitwise AND 32-bit register with a logical immediate. Performs a bitwise AND of Wn with a 32-bit logical immediate, stores the result in Wd. Does not modify condition flags. AArch64-only instruction executing at any privilege level.

imm_val ← DecodeBitMasks(N, immr, imms, 32)
Wd ← Wn AND imm_val


Summary: Bitwise AND with logical immediate (64-bit).

Bitwise AND 64-bit register with a logical immediate. Performs a bitwise AND of Xn with a 64-bit logical immediate, stores the result in Xd. Does not modify condition flags. AArch64-only instruction executing at any privilege level.

imm_val ← DecodeBitMasks(N, immr, imms, 64)
Xd ← Xn AND imm_val


Summary: Bitwise AND with shifted register.

AND <Wd>, <Wn>, <Wm> {, <shift> #<amount>}

Bitwise AND two 32-bit registers with optional shift. Performs a bitwise AND of Wn with the optionally shifted value of Wm, stores the result in Wd. Does not modify condition flags. AArch64-only instruction executing at any privilege level.

shifted_val ← Wm << amount
Wd ← Wn AND shifted_val


Summary: Bitwise AND with shifted register (64-bit).

AND <Xd>, <Xn>, <Xm> {, <shift> #<amount>}

Performs a bitwise AND between Xn and a shifted Xm, storing the result in Xd. The shift amount and type are specified by the shift operand. No condition flags are affected by this instruction.

Xd ← Xn AND (Xm shifted by shift_amount)


Summary: Bitwise AND immediate, updates flags.

Performs a bitwise AND between Wn and a 32-bit immediate value, storing the result in Wd and updating the condition flags. Sets the Z flag if the result is zero, the N flag based on bit 31 of the result, and clears the C and V flags.

result ← Wn AND imm
Wd ← result
N ← result[31]
Z ← (result == 0)
C ← 0
V ← 0


Bitwise AND and Set Flags (Immediate 64-bit)

Summary: Bitwise AND immediate, updates flags (64-bit).

Performs a bitwise AND between Xn and a 64-bit immediate value, storing the result in Xd and updating the condition flags. Sets the Z flag if the result is zero, the N flag based on bit 63 of the result, and clears the C and V flags.

result ← Xn AND imm
Xd ← result
N ← result[63]
Z ← (result == 0)
C ← 0
V ← 0


Bitwise AND and Set Flags (Shifted Register)

Summary: Bitwise AND shifted register, updates flags.

ANDS <Wd>, <Wn>, <Wm> {, <shift> #<amount>}

Performs a bitwise AND between Wn and a shifted Wm, storing the result in Wd and updating the condition flags. Sets the Z flag if the result is zero, the N flag based on bit 31 of the result, and clears the C and V flags.

result ← Wn AND (Wm shifted by shift_amount)
Wd ← result
N ← result[31]
Z ← (result == 0)
C ← 0
V ← 0


Bitwise AND and Set Flags (Shifted Register 64-bit)

Summary: Bitwise AND shifted register, updates flags (64-bit).

ANDS <Xd>, <Xn>, <Xm> {, <shift> #<amount>}

Performs a bitwise AND between Xn and a shifted Xm, storing the result in Xd and updating the condition flags. Sets the Z flag if the result is zero, the N flag based on bit 63 of the result, and clears the C and V flags.

result ← Xn AND (Xm shifted by shift_amount)
Xd ← result
N ← result[63]
Z ← (result == 0)
C ← 0
V ← 0


Summary: Arithmetic shift right by immediate.

Performs an arithmetic right shift of Wn by an immediate amount, storing the result in Wd. The sign bit (bit 31) is replicated into vacated bit positions. No condition flags are affected.

Wd ← Wn >> shift (arithmetic, sign-extended)


Arithmetic Shift Right (Immediate 64-bit)

Summary: Arithmetic shift right by immediate (64-bit).

Performs an arithmetic right shift of Xn by an immediate amount, storing the result in Xd. The sign bit (bit 63) is replicated into vacated bit positions. No condition flags are affected.

Xd ← Xn >> shift (arithmetic, sign-extended)


Summary: Arithmetic shift right by register value.

Performs an arithmetic right shift of Wn by the value in Wm (modulo 32), storing the result in Wd. The sign bit (bit 31) is replicated into vacated bit positions. No condition flags are affected.

Wd ← Wn >> (Wm AND 0x1F) (arithmetic, sign-extended)


Arithmetic Shift Right (Register 64-bit)

Summary: Arithmetic shift right by register value (64-bit).

Arithmetic shift right of Xn by the number of bits specified in the least significant byte of Xm, writing the result to Xd. The sign bit is replicated into vacated bit positions. NZCV flags are not affected by this instruction in AArch64.

shift_amount ← Xm[7:0]
if shift_amount >= 64 then
  if Xn[63] == 1 then Xd ← 0xFFFFFFFFFFFFFFFF else Xd ← 0
else
  Xd ← Xn >> shift_amount (arithmetic)


Summary: Unconditional branch to label.

Unconditional branch to a PC-relative label in AArch64. The 26-bit signed immediate is shifted left by 2 and added to the current PC. No condition flags are affected. This is an AArch64-only instruction.


Summary: Branch if condition is met (e.g., B.EQ, B.NE).

Conditional branch to a PC-relative label in AArch64, executed only if the specified condition is true. The 19-bit signed immediate is shifted left by 2 and added to the current PC. No condition flags are modified by this instruction. This is an AArch64-only instruction.

if ConditionHolds(cond) then
  PC ← PC + (SignExtend(imm19, 64) << 2)


Summary: Moves a bitfield from source to destination.

Bitfield move that extracts a bitfield from the source register and inserts it into the destination register at a specified position. The bitfield is rotated right by immr bits, then the imms field specifies the field width. No condition flags are affected. This is an AArch64-only instruction.

width ← imms - immr + 1
if width < 0 then width ← width + 64
lsb ← imms - width + 1
src_bits ← (Wn >> immr) & ((1 << width) - 1)
dst_mask ← ((1 << width) - 1) << lsb
Wd ← (Wd & ~dst_mask) | (src_bits << lsb)


Summary: Moves a bitfield from source to destination (64-bit).

Bitfield move that extracts a bitfield from Xn and inserts it into Xd at a rotated position. The bitfield width is determined by imms, and rotation by immr controls where bits are placed. NZCV flags are not affected. This is an AArch64-only instruction.

width ← 64
bfwidth ← (imms - immr) mod width + 1
if immr <= imms then
  wmask ← ((1 << bfwidth) - 1) << immr
  tmask ← ((1 << bfwidth) - 1)
  Xd ← (Xd AND NOT wmask) OR ((Xn << immr) AND wmask)
else
  wmask ← ((1 << bfwidth) - 1) >> (width - immr)
  tmask ← ((1 << bfwidth) - 1) << (width - immr)
  Xd ← (Xd AND NOT wmask) OR (((Xn >> (imms + 1)) OR (Xn << (width - imms - 1))) AND wmask)


Summary: ANDs register with NOT of shifted register (AND NOT).

BIC <Wd>, <Wn>, <Wm> {, <shift> #<amount>}

32-bit bitwise AND NOT: Xd ← Wn AND NOT (Wm, optionally shifted). The second operand is shifted before the NOT operation is applied. NZCV flags are not affected. Execution in AArch64 or A32 mode.

operand2 ← DecodeShift(Wm, shift, amount)
Wd ← Wn AND NOT operand2
if Wd[31] == 1 then N ← 1 else N ← 0
if Wd == 0 then Z ← 1 else Z ← 0


Bitwise Bit Clear (Shifted Register 64-bit)

Summary: ANDs register with NOT of shifted register (64-bit).

BIC <Xd>, <Xn>, <Xm> {, <shift> #<amount>}

64-bit bitwise AND NOT: Xd ← Xn AND NOT (Xm, optionally shifted). The second operand is shifted before the NOT operation is applied. NZCV flags are not affected. This is an AArch64-only instruction.

operand2 ← DecodeShift(Xm, shift, amount)
Xd ← Xn AND NOT operand2
if Xd[63] == 1 then N ← 1 else N ← 0
if Xd == 0 then Z ← 1 else Z ← 0


Summary: Performs BIC and updates flags.

BICS <Wd>, <Wn>, <Wm> {, <shift> #<amount>}

Bitwise AND with bitwise NOT (BIC) of the second source operand (optionally shifted) with the first source operand, storing the result in the destination and updating the condition flags. Sets N and Z flags according to the result; clears C and V. This is an AArch64-only instruction available in A32 and T32 variants.

operand2 ← Wm
if shift != NONE then
  operand2 ← operand2 shift_op amount
result ← Wn & ~operand2
Wd ← result
N ← result[31]
Z ← (result == 0)
C ← 0
V ← 0


Bitwise Bit Clear and Set Flags (64-bit)

Summary: Performs BIC and updates flags (64-bit).

BICS <Xd>, <Xn>, <Xm> {, <shift> #<amount>}

64-bit bitwise AND NOT with flag update: Xd ← Xn AND NOT (Xm, optionally shifted), then updates NZCV condition flags based on the result. The C and V flags are cleared. This is an AArch64-only instruction.

operand2 ← DecodeShift(Xm, shift, amount)
Xd ← Xn AND NOT operand2
N ← Xd[63]
Z ← (Xd == 0)
C ← 0
V ← 0


Summary: Function call. Branches to label and stores return address in LR (X30).

Branch with link: unconditional branch to a PC-relative label and stores the return address (current PC + 4) in the link register X30 (LR). The 26-bit signed immediate is shifted left by 2 and added to the current PC. No condition flags are affected. This is an AArch64-only instruction.

LR ← PC + 4
PC ← PC + (SignExtend(imm26, 64) << 2)


Summary: Indirect function call. Branches to address in Xn and stores return in LR.

Branch with link to register: indirect branch to the address held in Xn and stores the return address (current PC + 4) in the link register X30 (LR). No condition flags are affected. This is an AArch64-only instruction.


Summary: Indirect branch to address in Xn.

Branch to register: indirect unconditional branch to the address held in Xn. No condition flags are affected. This is an AArch64-only instruction.


Summary: Generates a Breakpoint instruction exception.

Generate a breakpoint exception (ESR_ELx.EC = 0x3C). The 16-bit immediate is encoded in the instruction and passed to the exception handler but does not affect architectural state. Execution does not proceed to the next instruction unless the exception handler explicitly resumes. This is an AArch64-only instruction.

AArch64.SystemSideEffect()
ESR_ELx.EC ← 0x3C
ESR_ELx.ISS ← imm16
TakeSynchronousException(Breakpoint)


Summary: Branches if register is not zero.

Compare and Branch if Not Zero. Compares the contents of the 32-bit register Wt with zero, and branches to the target address if the result is not equal to zero. This is a non-conditional branch that does not affect the condition flags. AArch64-only instruction.


Summary: Branches if 64-bit register is not zero.

Compare and Branch if Not Zero: if Xt is not zero, branch to the label by adding the sign-extended 19-bit immediate (×4) to the PC. No condition flags are affected. This is an AArch64-only instruction.

if Xt != 0 then
  PC ← PC + SignExtend(imm19 << 2, 64)


Summary: Branches if register is zero.

Compare and Branch if Zero. Compares the contents of the 32-bit register Wt with zero, and branches to the target address if the result equals zero. This is a non-conditional branch that does not affect the condition flags. AArch64-only instruction.


Summary: Branches if 64-bit register is zero.

Compare and Branch if Zero: if Xt is zero, branch to the label by adding the sign-extended 19-bit immediate (×4) to the PC. No condition flags are affected. This is an AArch64-only instruction.

if Xt == 0 then
  PC ← PC + SignExtend(imm19 << 2, 64)


Summary: Compares register with negative immediate if condition is true.

Conditional Compare Negative (Immediate), 32-bit. If the condition is true, performs an arithmetic compare of Wn + imm5, otherwise loads the NZCV flags with the immediate value nzcv. The comparison sets or clears N, Z, C, V flags accordingly. AArch64-only instruction.

if ConditionHolds(cond) then temp ← Wn + imm5; N ← temp[31]; Z ← (temp == 0); C ← UnsignedOverflow(Wn, imm5); V ← SignedOverflow(Wn, imm5) else N ← nzcv[3]; Z ← nzcv[2]; C ← nzcv[1]; V ← nzcv[0]


Conditional Compare Negative (Immediate 64-bit)

Summary: Compares 64-bit register with negative immediate if condition is true.

Conditional Compare Negative (Immediate), 64-bit. If the condition is true, performs an arithmetic compare of Xn + imm5, otherwise loads the NZCV flags with the immediate value nzcv. The comparison sets or clears N, Z, C, V flags accordingly. AArch64-only instruction.

if ConditionHolds(cond) then temp ← Xn + imm5; N ← temp[63]; Z ← (temp == 0); C ← UnsignedOverflow(Xn, imm5); V ← SignedOverflow(Xn, imm5) else N ← nzcv[3]; Z ← nzcv[2]; C ← nzcv[1]; V ← nzcv[0]


Summary: Compares two registers (negated) if condition is true.

Conditional Compare Negative (Register), 32-bit. If the condition is true, performs an arithmetic compare of Wn + Wm, otherwise loads the NZCV flags with the immediate value nzcv. The comparison sets or clears N, Z, C, V flags accordingly. AArch64-only instruction.

if ConditionHolds(cond) then temp ← Wn + Wm; N ← temp[31]; Z ← (temp == 0); C ← UnsignedOverflow(Wn, Wm); V ← SignedOverflow(Wn, Wm) else N ← nzcv[3]; Z ← nzcv[2]; C ← nzcv[1]; V ← nzcv[0]


Summary: Compares register with immediate if condition is true.

Conditional Compare (Immediate), 32-bit. If the condition is true, performs an arithmetic compare of Wn - imm5, otherwise loads the NZCV flags with the immediate value nzcv. The comparison sets or clears N, Z, C, V flags accordingly. AArch64-only instruction.

if ConditionHolds(cond) then temp ← Wn - imm5; N ← temp[31]; Z ← (temp == 0); C ← NOT(BorrowFrom(Wn, imm5)); V ← SignedOverflow(Wn, -imm5) else N ← nzcv[3]; Z ← nzcv[2]; C ← nzcv[1]; V ← nzcv[0]


Summary: Compares two registers if condition is true.

Conditional Compare (Register), 32-bit. If the condition is true, performs an arithmetic compare of Wn - Wm, otherwise loads the NZCV flags with the immediate value nzcv. The comparison sets or clears N, Z, C, V flags accordingly. AArch64-only instruction.

if ConditionHolds(cond) then temp ← Wn - Wm; N ← temp[31]; Z ← (temp == 0); C ← NOT(BorrowFrom(Wn, Wm)); V ← SignedOverflow(Wn, -Wm) else N ← nzcv[3]; Z ← nzcv[2]; C ← nzcv[1]; V ← nzcv[0]


Summary: Increment register if condition is true, else copy. (Alias for CSINC)

Conditional Increment, 32-bit. An alias for CSINC that conditionally increments Wn by 1 and writes the result to Wd if the condition is true, otherwise copies Wn to Wd. This instruction does not affect the condition flags. AArch64-only instruction.

if ConditionHolds(cond) then Wd ← Wn + 1 else Wd ← Wn


Summary: Invert register bits if condition is true, else copy. (Alias for CSINV)

Conditionally inverts all bits in the source register and writes the result to the destination, or copies the source unchanged based on the condition code. This is an alias for CSINV (Conditional Select Invert). Condition flags are not affected by this instruction. Executes in AArch64 state only.

if ConditionHolds(cond) then
  Wd ← ~Wn
else
  Wd ← Wn


Summary: Counts number of consecutive sign bits.

Counts the number of consecutive sign bits starting from bit 31 (for 32-bit operands) and writes the count to the destination register. Sign bits are those that match the most significant bit. Condition flags (N, Z, C, V) are not affected. Executes in AArch64 state only.

count ← 0
msb ← Wn[31]
for i = 30 downto 0
  if Wn[i] == msb then
    count ← count + 1
  else
    break
Wd ← count


Summary: Counts number of consecutive zeros.

Counts the number of consecutive zero bits starting from the most significant bit (bit 31 for 32-bit operands) and writes the count to the destination register. Condition flags (N, Z, C, V) are not affected. Executes in AArch64 state only.

count ← 0
for i = 31 downto 0
  if Wn[i] == 0 then
    count ← count + 1
  else
    break
Wd ← count


Summary: Adds register and immediate, updates flags (discard result). (Alias for ADDS)

Adds a 12-bit immediate value to a register and updates the condition flags based on the result; the result itself is discarded. This is an alias for ADDS with destination WZR. Sets N, Z, C, V flags according to the addition result. Executes in AArch64 state only.

result ← Wn + imm
N ← result[31]
Z ← (result == 0)
C ← CarryOut(Wn + imm)
V ← OverflowFrom(Wn + imm)


Summary: Subtracts immediate from register, updates flags (discard result). (Alias for SUBS)

Subtracts a 12-bit immediate value from a register and updates the condition flags based on the result; the result itself is discarded. This is an alias for SUBS with destination WZR. Sets N, Z, C, V flags according to the subtraction result. Executes in AArch64 state only.

result ← Wn - imm
N ← result[31]
Z ← (result == 0)
C ← NOT(BorrowFrom(Wn - imm))
V ← OverflowFrom(Wn - imm)


Summary: Negate register if condition is true, else copy. (Alias for CSNEG)

Conditionally negates the source register and writes the result to the destination, or copies the source unchanged based on the condition code. This is an alias for CSNEG (Conditional Select Negate). Condition flags are not affected by this instruction. Executes in AArch64 state only.

if ConditionHolds(cond) then
  Wd ← -Wn
else
  Wd ← Wn


Summary: Selects between two registers based on condition.

Selects one of two source registers and writes it to the destination based on the evaluated condition code. If the condition is true, Wn is selected; otherwise Wm is selected. Condition flags (N, Z, C, V) are not affected. Executes in AArch64 state only.

if ConditionHolds(cond) then
  Wd ← Wn
else
  Wd ← Wm


Summary: Sets register to 1 if condition true, else 0. (Alias for CSINC)

Sets the destination register to 1 if the condition code is true, otherwise sets it to 0. This is an alias for CSINC (Conditional Select Increment) with both source registers set to WZR. Condition flags (N, Z, C, V) are not affected. Executes in AArch64 state only.

if ConditionHolds(cond) then
  Wd ← 1
else
  Wd ← 0


Summary: Selects Wn if cond true, else (Wm + 1).

Conditionally selects between two values: if the condition is true, writes Wn to Wd; otherwise writes (Wm + 1) to Wd. The upper 32 bits of Xd are zeroed. No flags are affected by this instruction. Available in AArch64 only.

if ConditionHolds(cond) then
  Wd ← Wn
else
  Wd ← Wm + 1


Summary: Selects Wn if cond true, else NOT Wm.

Conditionally selects between two values: if the condition is true, writes Wn to Wd; otherwise writes the bitwise inversion of Wm to Wd. The upper 32 bits of Xd are zeroed. No flags are affected by this instruction. Available in AArch64 only.

if ConditionHolds(cond) then
  Wd ← Wn
else
  Wd ← ~Wm


Summary: Selects Wn if cond true, else -Wm.

Conditionally selects between two values: if the condition is true, writes Wn to Wd; otherwise writes the arithmetic negation of Wm to Wd. The upper 32 bits of Xd are zeroed. No flags are affected by this instruction. Available in AArch64 only.

if ConditionHolds(cond) then
  Wd ← Wn
else
  Wd ← -Wm


Summary: Switch to Exception Level 1 (Debug).

Debug instruction that changes the PE to Exception Level 1. This is a privileged instruction typically used in debug state to transition exception levels. The optional immediate provides a 16-bit debug context identifier. Requires debug permissions and is AArch64-only.

SPSR_EL1 ← PSTATE
PSTATE.EL ← '01'
PC ← DLR_EL0


Summary: Switch to Exception Level 2 (Debug).

Debug instruction that changes the PE to Exception Level 2. This is a privileged instruction typically used in debug state to transition exception levels. The optional immediate provides a 16-bit debug context identifier. Requires debug permissions and is AArch64-only.

SPSR_EL2 ← PSTATE
PSTATE.EL ← '10'
PC ← DLR_EL0


Summary: Switch to Exception Level 3 (Debug).

Debug instruction that changes the PE to Exception Level 3. This is a privileged instruction typically used in debug state to transition exception levels. The optional immediate provides a 16-bit debug context identifier. Requires debug permissions and is AArch64-only.

SPSR_EL3 ← PSTATE
PSTATE.EL ← '11'
PC ← DLR_EL0


Summary: Ensures memory access ordering.

Data Memory Barrier instruction that ensures all memory accesses before this instruction are observed before any memory accesses after it. The option field specifies the scope (SY for full system, ISH for inner shareable, NSH for non-shareable, etc.). No register changes or flags are affected. Available in AArch64, A32, and T32.


Summary: Restores state from SPSR_ELx and DLR_EL0.

Debug Restore PE State instruction that restores the PE state from the debug link register (DLR_EL0) and the saved program state register (SPSR_ELx), effectively returning from debug state. This is a privileged instruction requiring debug permissions and is AArch64-only.


Summary: Ensures completion of memory accesses.

Data Synchronization Barrier ensures that all memory accesses prior to the barrier are observed before any subsequent memory accesses. It acts as a full system memory barrier, blocking speculative memory accesses. Condition flags (N, Z, C, V) are unaffected. This is an AArch64 instruction requiring any privilege level; it serializes the instruction stream and all load/store operations.


Summary: XORs register with NOT of shifted register (XNOR).

EON <Wd>, <Wn>, <Wm> {, <shift> #<amount>}

Bitwise Exclusive OR NOT performs XNOR operation: destination = source1 XOR (NOT source2_shifted). The second source register can be shifted by immediate or register amount (LSL, LSR, ASR, ROR). The N and Z condition flags are set based on the result; C and V flags are unaffected. This 32-bit operation zero-extends the result in AArch64.

result ← Wn XOR (NOT (Wm << shift_amount))
Wd ← result[31:0]
N ← result[31]
Z ← (result == 0)


Summary: XORs 64-bit register with NOT of shifted register.

EON <Xd>, <Xn>, <Xm> {, <shift> #<amount>}

64-bit exclusive OR NOT: Xd ← Xn XOR NOT (Xm, optionally shifted). The second operand is shifted before the NOT operation is applied. NZCV flags are not affected. This is an AArch64-only instruction.

operand2 ← DecodeShift(Xm, shift, amount)
Xd ← Xn XOR NOT operand2


Summary: XORs register with immediate.

Bitwise Exclusive OR (Immediate) performs a logical XOR between a 32-bit register and a bitmask immediate, writing the result to the destination register. This instruction does not affect the condition flags. It executes in AArch64 state and is available at all privilege levels.


Summary: XORs two registers.

EOR <Wd>, <Wn>, <Wm> {, <shift> #<amount>}

Bitwise Exclusive OR (Register) performs a logical XOR between two 32-bit registers with optional shift, writing the result to the destination register. This instruction does not affect the condition flags. It executes in AArch64 state and is available at all privilege levels.


Summary: Returns from an exception.

Exception Return returns control from an exception handler to the point of exception. It restores the program counter from ELR_ELx and the CPU state (mode, condition flags) from SPSR_ELx. The behavior depends on the current exception level; it is privileged and available only at EL1 or higher. No condition flags are modified by the instruction itself.


Summary: Extracts a register from a pair of registers.

Extract concatenates two 32-bit registers (high Wn concatenated with low Wm) and extracts a contiguous 32-bit slice starting at bit position lsb. The extracted bits are placed in destination Wd. Condition flags (N, Z, C, V) are unaffected. This instruction has no implicit side effects beyond the register write.


Summary: Extracts a 64-bit register from a pair.

Extract concatenates two 64-bit registers (high Xn concatenated with low Xm) and extracts a contiguous 64-bit slice starting at bit position lsb. The extracted bits are placed in destination Xd. Condition flags (N, Z, C, V) are unaffected. This is the 64-bit variant with lsb range 0-63.


Summary: Provides a hint to the processor (e.g., NOP, YIELD).

Hint provides a processor hint via an immediate value; the processor may optimize behavior based on the hint type but is not required to act on it. Common hints include NOP (0x0), YIELD (0x1), WFE (0x2), and WFI (0x3). Condition flags (N, Z, C, V) are unaffected. The instruction executes in all exception levels without privilege requirements.

case imm of
  0: NOP
  1: Yield()
  2: WaitForEvent()
  3: WaitForInterrupt()
  otherwise: NOP


Summary: Enters Halting debug mode.

Halting Debug-mode halts the processor and requests entry into halting debug mode with the given exception number. It generates an exception and is typically used only in debug scenarios. No condition flags are modified. This instruction is privileged and requires AArch64 execution; it transitions to debug state and may not return to normal execution.


Summary: Generates a Hypervisor Call exception to EL2.

Hypervisor Call generates an exception to the hypervisor (EL2) and passes a 16-bit immediate value to it. The exception is synchronous and the current state is saved so the hypervisor can interpret the request. Condition flags (N, Z, C, V) are unaffected by the instruction itself. This requires AArch64 execution and can be called from EL0, EL1, or EL2.

exception ← HypervisorCall
ESR_ELx.ISS ← imm16
Branch to EL2 exception handler


Summary: Flushes the pipeline and prefetches.

Instruction Synchronization Barrier flushes the instruction pipeline and discards prefetched instructions, ensuring all prior instructions complete before subsequent instructions begin execution. This is a memory ordering operation that does not affect the condition flags. It executes in AArch64 state at EL0 and above.

Instruction pipeline ← flushed; Prefetched instructions ← discarded


Summary: Loads a word with Acquire semantics.

Wt

Transfer 32-bit integer register (load/store)

Load-Acquire Register loads a 32-bit word from memory with Acquire semantics, establishing a one-way barrier that prevents subsequent memory operations from being observed before the load completes. The instruction is AArch64-only, does not modify condition flags, and provides explicit synchronization without atomic read-modify-write. The loaded value is zero-extended to 64 bits in the destination register.

Wt ← ZeroExtend(Mem32[Xn], 32)
# Acquire semantics: subsequent memory operations appear after this load


Summary: Loads a byte with Acquire semantics.

Load-Acquire Register Byte loads an 8-bit byte from memory with Acquire semantics, establishing a one-way barrier that prevents subsequent memory operations from being observed before the load completes. The instruction is AArch64-only, does not modify condition flags, and the loaded byte is zero-extended to 32 bits in the destination register.

Wt ← ZeroExtend(Mem8[Xn], 8)
# Acquire semantics: subsequent memory operations appear after this load


Summary: Loads a halfword with Acquire semantics.

Load-Acquire Register Halfword loads a 16-bit halfword from memory with Acquire semantics, establishing a one-way barrier that prevents subsequent memory operations from being observed before the load completes. The instruction is AArch64-only, does not modify condition flags, and the loaded halfword is zero-extended to 32 bits in the destination register.

Wt ← ZeroExtend(Mem16[Xn], 16)
# Acquire semantics: subsequent memory operations appear after this load


Summary: Loads a word with Acquire Exclusive semantics.

Load-Acquire Exclusive Register loads a 32-bit word from memory with both Acquire and Exclusive semantics, establishing a one-way memory barrier and reserving the addressed location for exclusive write tracking. The instruction is AArch64-only, does not modify condition flags, and the loaded value is zero-extended to 64 bits. This instruction must be paired with a store exclusive to complete atomic transactions.

Wt ← ZeroExtend(Mem32[Xn], 32)
ExclusiveMonitor[Xn] ← LOCKED
# Acquire semantics: subsequent memory operations appear after this load


Summary: Loads a byte with Acquire Exclusive semantics.

Load-Acquire Exclusive Register Byte loads an 8-bit byte from memory with both Acquire and Exclusive semantics, establishing a one-way memory barrier and reserving the addressed location for exclusive write tracking. The instruction is AArch64-only, does not modify condition flags, and the loaded byte is zero-extended to 32 bits. This instruction must be paired with a store exclusive to complete atomic byte transactions.

Wt ← ZeroExtend(Mem8[Xn], 8)
ExclusiveMonitor[Xn] ← LOCKED
# Acquire semantics: subsequent memory operations appear after this load


Summary: Loads a halfword with Acquire Exclusive semantics.

Load-Acquire Exclusive Register Halfword loads a 16-bit halfword from memory with both Acquire and Exclusive semantics, establishing a one-way memory barrier and reserving the addressed location for exclusive write tracking. The instruction is AArch64-only, does not modify condition flags, and the loaded halfword is zero-extended to 32 bits. This instruction must be paired with a store exclusive to complete atomic halfword transactions.

Wt ← ZeroExtend(Mem16[Xn], 16)
ExclusiveMonitor[Xn] ← LOCKED
# Acquire semantics: subsequent memory operations appear after this load


Summary: Loads two words, hinting non-temporal data (no caching).

Load Pair of Registers (Non-temporal) loads two 32-bit words from memory into two registers with a non-temporal hint indicating the data is unlikely to be reused soon, allowing the processor to avoid cache pollution. The instruction does not affect the condition flags. It executes in AArch64 state and is available at all privilege levels.

address ← Xn + (sign_extend(imm7) << 2); Wt1 ← [address]; Wt2 ← [address + 4]


Summary: Loads two words from memory.

Load Pair of Registers loads two 32-bit words from consecutive memory locations into two registers, with optional post-index addressing. The instruction is AArch64-only, does not modify condition flags, and the two loaded values are zero-extended to 64 bits if using Wt1/Wt2 operands. The base register is updated after the load if post-index addressing is specified.

offset ← SignExtend(imm7 << 2, 64)
Wt1 ← ZeroExtend(Mem32[Xn], 32)
Wt2 ← ZeroExtend(Mem32[Xn + 4], 32)
Xn ← Xn + offset


Summary: Loads two 64-bit doublewords from memory.

Load Pair of Registers (64-bit) loads two 64-bit doublewords from memory into two 64-bit registers and then post-increments the base register. The instruction does not affect the condition flags. It executes in AArch64 state and is available at all privilege levels.

address ← Xn; Xt1 ← [address]; Xt2 ← [address + 8]; Xn ← Xn + (sign_extend(imm7) << 3)


Summary: Loads two words and sign-extends them to 64-bit.

Loads two consecutive signed 32-bit words from memory and sign-extends each to 64 bits, storing them in Xt1 and Xt2. The memory address is computed from the base register Xn (or SP) plus a scaled 7-bit signed immediate offset (scaled by 4). No condition flags are affected. This is an AArch64-only instruction.

offset ← imm << 2;
address ← (if Xn == 31 then SP else Xn) + offset;
Xt1 ← SignExtend(Mem[address, 4], 32);
Xt2 ← SignExtend(Mem[address + 4, 4], 32);


Summary: Loads a word from memory (Immediate offset).

Load Register (Immediate) loads a 32-bit word from memory at an offset address into a 32-bit register. The instruction does not affect the condition flags. It executes in AArch64 state and is available at all privilege levels.

address ← Xn + (zero_extend(imm12) << 2); Wt ← [address]


Summary: Loads a word from a PC-relative address.

Load Register (Literal) loads a 32-bit word from a PC-relative address into a 32-bit register. The instruction does not affect the condition flags. It executes in AArch64 state and is available at all privilege levels.

address ← PC + (sign_extend(imm19) << 2); Wt ← [address]


Summary: Loads a word from memory (Register offset).

LDR <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}]

Load Register (Register) loads a 32-bit word from memory using a register offset with optional sign/zero extension or shift into a 32-bit register. The instruction does not affect the condition flags. It executes in AArch64 state and is available at all privilege levels.

offset ← extended_value(Rm, extend_type, shift_amount); address ← Xn + offset; Wt ← [address]


Summary: Adds corresponding elements in two vectors.

Adds corresponding integer elements in two NEON vectors and writes the results to the destination vector. Operates element-wise on 8-bit, 16-bit, 32-bit, or 64-bit elements as determined by the size and Q fields. Condition flags (N, Z, C, V) are not affected; wrapping addition is performed on overflow.

for i = 0 to elements_in_vector - 1
  Vd[i] ← Vn[i] + Vm[i]


Summary: Subtracts elements of Vm from Vn.

Subtracts corresponding integer elements of Vm from Vn and writes the results to the destination vector. Operates element-wise on 8-bit, 16-bit, 32-bit, or 64-bit elements as determined by the size and Q fields. Condition flags (N, Z, C, V) are not affected; wrapping subtraction is performed on underflow.

for i = 0 to elements_in_vector - 1
  Vd[i] ← Vn[i] - Vm[i]


Summary: Multiplies corresponding elements in two vectors.

Multiplies corresponding integer elements in two NEON vectors and writes the results to the destination vector. Operates element-wise on 8-bit, 16-bit, or 32-bit elements; the result is the lower bits of the product (wrapping multiplication). Condition flags (N, Z, C, V) are not affected.

for i = 0 to elements_in_vector - 1
  Vd[i] ← (Vn[i] × Vm[i]) mod 2^element_width


Summary: Multiplies elements and adds to destination (Vd = Vd + Vn * Vm).

Multiplies corresponding elements of Vn and Vm, then adds the products to the corresponding elements of Vd, storing results back in Vd. Operates on integer elements of size determined by the size field (8, 16, or 32 bits). The Q bit determines operation width (64-bit for Q=0, 128-bit for Q=1). No condition flags are affected. AArch64 NEON extension.

for i = 0 to (128 >> (if Q then 0 else 1)) - 1 step esize:
  Vd[i +: esize] ← Vd[i +: esize] + (Vn[i +: esize] * Vm[i +: esize]);


Summary: Multiplies elements and subtracts from destination (Vd = Vd - Vn * Vm).

Multiplies corresponding elements of Vn and Vm, then subtracts the products from the corresponding elements of Vd, storing results back in Vd. Operates on integer elements of size determined by the size field (8, 16, or 32 bits). The Q bit determines operation width (64-bit for Q=0, 128-bit for Q=1). No condition flags are affected. AArch64 NEON extension.

for i = 0 to (128 >> (if Q then 0 else 1)) - 1 step esize:
  Vd[i +: esize] ← Vd[i +: esize] - (Vn[i +: esize] * Vm[i +: esize]);


Summary: Performs polynomial multiplication over {0,1}.

Performs polynomial multiplication over GF(2^m) on corresponding 8-bit elements of Vn and Vm, storing results in Vd. Each element is treated as a polynomial with coefficients in {0,1}, and multiplication is performed modulo an irreducible polynomial. The Q bit determines operation width (64-bit for Q=0, 128-bit for Q=1). No condition flags are affected. AArch64 NEON extension.

for i = 0 to (128 >> (if Q then 0 else 1)) - 1 step 8:
  Vd[i +: 8] ← PolynomialMultiply(Vn[i +: 8], Vm[i +: 8]);


Summary: Bitwise AND of two vectors.

Performs bitwise AND between corresponding elements of Vn and Vm, storing results in Vd. Operates on the full vector width without regard to element size. The Q bit determines operation width (64-bit for Q=0, 128-bit for Q=1). No condition flags are affected. AArch64 NEON extension.

for i = 0 to (128 >> (if Q then 0 else 1)) - 1:
  Vd[i] ← Vn[i] AND Vm[i];


Summary: Bitwise OR of two vectors.

Performs bitwise OR between corresponding elements of Vn and Vm, storing results in Vd. Operates on the full vector width without regard to element size. The Q bit determines operation width (64-bit for Q=0, 128-bit for Q=1). No condition flags are affected. AArch64 NEON extension.

for i = 0 to (128 >> (if Q then 0 else 1)) - 1:
  Vd[i] ← Vn[i] OR Vm[i];


Summary: Bitwise XOR of two vectors.

Performs bitwise exclusive OR between corresponding elements of Vn and Vm, storing results in Vd. Operates on the full vector width without regard to element size. The Q bit determines operation width (64-bit for Q=0, 128-bit for Q=1). No condition flags are affected. AArch64 NEON extension.

for i = 0 to (128 >> (if Q then 0 else 1)) - 1:
  Vd[i] ← Vn[i] XOR Vm[i];


Summary: ANDs Vd with NOT of Vm.

Performs bitwise AND between Vn and the bitwise NOT of Vm, storing results in Vd. This clears bits in Vn where corresponding bits in Vm are set. Operates on the full vector width without regard to element size. The Q bit determines operation width (64-bit for Q=0, 128-bit for Q=1). No condition flags are affected. AArch64 NEON extension.

for i = 0 to (128 >> (if Q then 0 else 1)) - 1:
  Vd[i] ← Vn[i] AND NOT(Vm[i]);


Summary: ORs Vd with NOT of Vm.

Performs a bitwise OR NOT operation on SIMD vector elements: each bit in Vd is set to (Vn | ~Vm). This is a bitwise logical operation that operates independently on each bit across all lanes. No condition flags are affected. Executes in AArch64 state with NEON extension; operates on both 64-bit (Q=0) and 128-bit (Q=1) vector registers.


Summary: Copies a vector register (Alias for ORR Vd, Vn, Vn).

Copies a SIMD vector register to another. This is an alias for ORR Vd, Vn, Vn that performs a bitwise OR of Vn with itself, resulting in an identical copy. No condition flags are affected; the instruction operates on all elements simultaneously.


Summary: Selects bits from Vn or Vm based on Vd (mask). (Vd = (Vd & Vn) | (~Vd & Vm)).

Performs a bitwise select operation using Vd as a mask: Vd ← (Vd & Vn) | (~Vd & Vm). Bits are selected from Vn where the corresponding bit in Vd is 1, and from Vm where the corresponding bit in Vd is 0. No condition flags are affected. Executes in AArch64 state with NEON extension on both 64-bit (Q=0) and 128-bit (Q=1) vectors.


Summary: Inserts bits from Vn into Vd where Vm (mask) is 1.

Performs a bitwise insert-if-true operation: Vd ← (Vd & ~Vm) | (Vn & Vm). Bits from Vn are inserted into Vd where the corresponding bit in Vm is 1; Vd bits are retained where Vm is 0. No condition flags are affected. Executes in AArch64 state with NEON extension on both 64-bit (Q=0) and 128-bit (Q=1) vectors.


Summary: Inserts bits from Vn into Vd where Vm (mask) is 0.

Performs a bitwise insert-if-false operation: Vd ← (Vd & Vm) | (Vn & ~Vm). Bits from Vn are inserted into Vd where the corresponding bit in Vm is 0; Vd bits are retained where Vm is 1. No condition flags are affected. Executes in AArch64 state with NEON extension on both 64-bit (Q=0) and 128-bit (Q=1) vectors.


Summary: Adds elements of two floating-point vectors.

Adds corresponding floating-point elements in Vn and Vm, storing results in Vd. Supports both 32-bit (sz=0) and 64-bit (sz=1) floating-point lanes across 64-bit (Q=0) or 128-bit (Q=1) vectors. Floating-point exception behavior follows IEEE 754 semantics; no integer condition flags are affected. Executes in AArch64 state with NEON extension.


Summary: Subtracts elements of floating-point vectors.

Subtracts floating-point elements in Vm from corresponding elements in Vn, storing results in Vd. Supports both 32-bit (sz=0) and 64-bit (sz=1) floating-point lanes across 64-bit (Q=0) or 128-bit (Q=1) vectors. Floating-point exception behavior follows IEEE 754 semantics; no integer condition flags are affected. Executes in AArch64 state with NEON extension.


Summary: Multiplies elements of floating-point vectors.

Multiplies corresponding floating-point elements in Vn and Vm, storing results in Vd. Supports both 32-bit (sz=0) and 64-bit (sz=1) floating-point lanes across 64-bit (Q=0) or 128-bit (Q=1) vectors. Floating-point exception behavior follows IEEE 754 semantics; no integer condition flags are affected. Executes in AArch64 state with NEON extension.


Summary: Divides elements of floating-point vectors.

Divides corresponding floating-point elements in Vn by elements in Vm, storing results in Vd. Supports both 32-bit (sz=0) and 64-bit (sz=1) floating-point lanes across 64-bit (Q=0) or 128-bit (Q=1) vectors. Floating-point exception behavior follows IEEE 754 semantics including division-by-zero handling; no integer condition flags are affected. Executes in AArch64 state with NEON extension.


Summary: Compares and returns the larger value per element.

Compares corresponding floating-point elements in two NEON vectors and places the larger value in the destination vector for each element. No NEON flag bits are affected; this is a per-element maximum operation available in 32-bit and 64-bit floating-point forms (controlled by sz). Executes on AArch64 with NEON/ASIMD extension; the Q bit selects between 64-bit (Q=0) and 128-bit (Q=1) vector width.

for i = 0 to elements_in_vector-1:
  element_size = 32 if sz==0 else 64
  Vd[element][element_size-1:0] = max_fp(Vn[element][element_size-1:0], Vm[element][element_size-1:0])


Summary: Compares and returns the smaller value per element.

Compares corresponding floating-point elements in two NEON vectors and places the smaller value in the destination vector for each element. No NEON flag bits are affected; this is a per-element minimum operation available in 32-bit and 64-bit floating-point forms (controlled by sz). Executes on AArch64 with NEON/ASIMD extension; the Q bit selects between 64-bit (Q=0) and 128-bit (Q=1) vector width.

for i = 0 to elements_in_vector-1:
  element_size = 32 if sz==0 else 64
  Vd[element][element_size-1:0] = min_fp(Vn[element][element_size-1:0], Vm[element][element_size-1:0])


Summary: Multiplies and adds to destination (Vd = Vd + Vn * Vm).

Multiplies corresponding floating-point elements from two source vectors and accumulates the product into the destination vector: Vd[i] = Vd[i] + Vn[i] × Vm[i] per element. Floating-point exceptions (invalid operation, overflow, underflow, inexact) may be signaled per IEEE 754 semantics; no integer flags are affected. Available in 32-bit and 64-bit floating-point forms (sz controls element width) on AArch64 with NEON/ASIMD extension.

for i = 0 to elements_in_vector-1:
  element_size = 32 if sz==0 else 64
  product = Vn[element][element_size-1:0] * Vm[element][element_size-1:0]
  Vd[element][element_size-1:0] = Vd[element][element_size-1:0] + product


Summary: Multiplies and subtracts from destination (Vd = Vd - Vn * Vm).

Multiplies corresponding floating-point elements from two source vectors and subtracts the product from the destination vector: Vd[i] = Vd[i] - Vn[i] × Vm[i] per element. Floating-point exceptions (invalid operation, overflow, underflow, inexact) may be signaled per IEEE 754 semantics; no integer flags are affected. Available in 32-bit and 64-bit floating-point forms (sz controls element width) on AArch64 with NEON/ASIMD extension.

for i = 0 to elements_in_vector-1:
  element_size = 32 if sz==0 else 64
  product = Vn[element][element_size-1:0] * Vm[element][element_size-1:0]
  Vd[element][element_size-1:0] = Vd[element][element_size-1:0] - product


Summary: Calculates square root for each element.

Calculates the floating-point square root of each element in the source vector and places the result in the destination vector. Floating-point exceptions (invalid operation, inexact) may be signaled per IEEE 754 semantics; no integer flags are affected. Available in 32-bit and 64-bit floating-point forms (sz controls element width) on AArch64 with NEON/ASIMD extension.

for i = 0 to elements_in_vector-1:
  element_size = 32 if sz==0 else 64
  Vd[element][element_size-1:0] = sqrt_fp(Vn[element][element_size-1:0])


Summary: Calculates absolute value for each element.

Clears the sign bit of each floating-point element in the source vector, placing the absolute value in the destination vector. This is a bit-level operation that does not signal floating-point exceptions. Available in 32-bit and 64-bit floating-point forms (sz controls element width) on AArch64 with NEON/ASIMD extension.

for i = 0 to elements_in_vector-1:
  element_size = 32 if sz==0 else 64
  Vd[element][element_size-1:0] = Vn[element][element_size-2:0] || 0


Summary: Negates each element.

Inverts the sign bit of each floating-point element in the source vector, placing the negated value in the destination vector. This is a bit-level operation that does not signal floating-point exceptions. Available in 32-bit and 64-bit floating-point forms (sz controls element width) on AArch64 with NEON/ASIMD extension.

for i = 0 to elements_in_vector-1:
  element_size = 32 if sz==0 else 64
  sign_bit = NOT(Vn[element][element_size-1])
  Vd[element][element_size-1:0] = sign_bit || Vn[element][element_size-2:0]


Summary: Duplicates a general-purpose register to all vector elements.

Broadcasts the value from a general-purpose register (either X or W form) to every element of the destination NEON vector. The imm5 field encodes the element size: bit 0 distinguishes 8/16-bit, bits 1-2 distinguish 8/16/32/64-bit granularity. No flags are affected. Available on AArch64 with NEON/ASIMD extension; the Q bit selects 64-bit (Q=0) or 128-bit (Q=1) vector width.

element_size = decode_imm5(imm5)
for i = 0 to elements_in_vector-1:
  Vd[element][element_size-1:0] = Rn[element_size-1:0]


Summary: Duplicates a vector element to all elements in destination.

Duplicates a single element from a vector and replicates it to fill all elements in the destination vector. The element index is encoded in the imm5 field, which also determines the element size based on the position of the most significant set bit. This is a NEON SIMD instruction available in AArch64 only, with Q determining 64-bit (Q=0) or 128-bit (Q=1) operation. No condition flags are affected.

element_size ← decode_element_size(imm5);
element ← Vn.<element_size>[index_from_imm5];
for i = 0 to (vector_length / element_size - 1)
  Vd.<element_size>[i] ← element;


Summary: Moves data from a GPR to a specific vector element.

Moves a single 64-bit value from a general-purpose register to a specified element position within a vector register, leaving other elements unchanged. The destination element index is encoded in the imm5 field, with the element size implicitly 64-bit. This is a NEON SIMD instruction available in AArch64 only. No condition flags are affected.

element_index ← decode_index_from_imm5(imm5);
Vd.D[element_index] ← Rn;


Summary: Moves a vector element to another vector element (Alias for INS).

Moves a single vector element from a source vector to a specified element position in a destination vector (this is an alias for INS when source and destination are both vector registers). The element indices are encoded in the imm5 field, which must support dual index encoding. This is a NEON SIMD instruction available in AArch64 only. No condition flags are affected.

src_index ← decode_src_index_from_imm5(imm5);
dst_index ← decode_dst_index_from_imm5(imm5);
element_size ← decode_element_size(imm5);
Vd.<element_size>[dst_index] ← Vn.<element_size>[src_index];


Summary: Calculates absolute value of integer elements.

Computes the absolute value of each signed integer element in the source vector and stores the result in the destination vector. The operation processes all elements in parallel; Q determines 64-bit (Q=0) or 128-bit (Q=1) operation, and size determines element width (8, 16, 32, or 64 bits). This is a NEON SIMD instruction available in AArch64 only. No condition flags are affected; saturation behavior depends on implementation.

element_size ← 8 << size;
for i = 0 to (vector_length / element_size - 1)
  if Vn.<element_size>[i] == minimum_signed_value(element_size)
    Vd.<element_size>[i] ← minimum_signed_value(element_size);
  else
    Vd.<element_size>[i] ← |Vn.<element_size>[i]|;


Summary: Negates integer elements.

Negates each signed or unsigned integer element in the source vector and stores the result in the destination vector. The operation processes all elements in parallel; Q determines 64-bit (Q=0) or 128-bit (Q=1) operation, and size determines element width (8, 16, 32, or 64 bits). This is a NEON SIMD instruction available in AArch64 only. No condition flags are affected.

element_size ← 8 << size;
for i = 0 to (vector_length / element_size - 1)
  Vd.<element_size>[i] ← -Vn.<element_size>[i];


Summary: Bitwise NOT of a vector.

Performs a bitwise NOT (complement) on each bit of the source vector and stores the result in the destination vector. The operation processes all elements in parallel with the same bitwise inversion applied across all bits; Q determines 64-bit (Q=0) or 128-bit (Q=1) operation. This is a NEON SIMD instruction available in AArch64 only. No condition flags are affected.

for i = 0 to (vector_length - 1)
  Vd.bit[i] ← NOT Vn.bit[i];


Summary: Returns larger signed integer per element.

Computes the signed maximum of corresponding elements from two source vectors and stores the result in the destination vector. The operation processes all elements in parallel; Q determines 64-bit (Q=0) or 128-bit (Q=1) operation, and size determines element width (8, 16, 32, or 64 bits). This is a NEON SIMD instruction available in AArch64 only. No condition flags are affected.

element_size ← 8 << size;
for i = 0 to (vector_length / element_size - 1)
  Vd.<element_size>[i] ← max_signed(Vn.<element_size>[i], Vm.<element_size>[i]);


Summary: Returns smaller signed integer per element.

Computes the signed minimum of corresponding elements from two source vectors and stores the result in the destination vector. The operation processes all elements in parallel; Q determines 64-bit (Q=0) or 128-bit (Q=1) operation, and size determines element width (8, 16, 32, or 64 bits). This is a NEON SIMD instruction available in AArch64 only. No condition flags are affected.

element_size ← 8 << size;
for i = 0 to (vector_length / element_size - 1)
  Vd.<element_size>[i] ← min_signed(Vn.<element_size>[i], Vm.<element_size>[i]);


Summary: Returns larger unsigned integer per element.

Vector Unsigned Maximum compares corresponding unsigned integer elements in two NEON registers and places the larger value into the destination register, operating element-wise according to the element type T. This instruction operates on all elements within the vector (128-bit if Q=1, 64-bit if Q=0) and does not modify the condition flags. AArch64-only NEON instruction with no privilege restrictions.

for i = 0 to elements_in_vector(Q, size) - 1 do
  Vd[i] ← max_unsigned(Vn[i], Vm[i])
end for


Summary: Returns smaller unsigned integer per element.

Vector Unsigned Minimum compares corresponding unsigned integer elements in two NEON registers and places the smaller value into the destination register, operating element-wise according to the element type T. This instruction operates on all elements within the vector (128-bit if Q=1, 64-bit if Q=0) and does not modify the condition flags. AArch64-only NEON instruction with no privilege restrictions.

for i = 0 to elements_in_vector(Q, size) - 1 do
  Vd[i] ← min_unsigned(Vn[i], Vm[i])
end for


Summary: Adds signed integers with saturation.

Vector Signed Saturating Add adds corresponding signed integer elements from two NEON registers with saturation, placing the sum into the destination register. If overflow occurs, the result is clamped to the maximum or minimum value representable in the element type. This instruction operates element-wise on all vector elements and does not modify the condition flags. AArch64-only NEON instruction with no privilege restrictions.

for i = 0 to elements_in_vector(Q, size) - 1 do
  sum ← signed_add(Vn[i], Vm[i])
  if overflow then
    Vd[i] ← (Vn[i] < 0) ? INT_MIN(size) : INT_MAX(size)
  else
    Vd[i] ← sum
  end if
end for


Summary: Adds unsigned integers with saturation.

Vector Unsigned Saturating Add adds corresponding unsigned integer elements from two NEON registers with saturation, placing the sum into the destination register. If the sum exceeds the maximum value representable in the element type, the result is saturated to that maximum. This instruction operates element-wise on all vector elements and does not modify the condition flags. AArch64-only NEON instruction with no privilege restrictions.

for i = 0 to elements_in_vector(Q, size) - 1 do
  sum ← Vn[i] + Vm[i]
  if sum > UINT_MAX(size) then
    Vd[i] ← UINT_MAX(size)
  else
    Vd[i] ← sum
  end if
end for


Summary: Subtracts signed integers with saturation.

Vector Signed Saturating Subtract subtracts corresponding signed integer elements from two NEON registers with saturation, placing the difference into the destination register. If overflow occurs, the result is clamped to the maximum or minimum value representable in the element type. This instruction operates element-wise on all vector elements and does not modify the condition flags. AArch64-only NEON instruction with no privilege restrictions.

for i = 0 to elements_in_vector(Q, size) - 1 do
  diff ← signed_subtract(Vn[i], Vm[i])
  if overflow then
    Vd[i] ← (Vn[i] < 0) ? INT_MIN(size) : INT_MAX(size)
  else
    Vd[i] ← diff
  end if
end for


Summary: Subtracts unsigned integers with saturation.

Vector Unsigned Saturating Subtract subtracts corresponding unsigned integer elements from two NEON registers with saturation, placing the difference into the destination register. If the subtraction would produce a negative result, the result is saturated to zero. This instruction operates element-wise on all vector elements and does not modify the condition flags. AArch64-only NEON instruction with no privilege restrictions.

for i = 0 to elements_in_vector(Q, size) - 1 do
  if Vn[i] < Vm[i] then
    Vd[i] ← 0
  else
    Vd[i] ← Vn[i] - Vm[i]
  end if
end for


Summary: Shifts elements left by immediate value.

Vector Shift Left shifts each element of a NEON register left by an immediate value, filling vacated bit positions with zeros. The immediate shift amount is encoded in the imm field and must be within the range [0, element_width-1]; shifting by the element width or more produces a zero result. This instruction does not modify the condition flags. AArch64-only NEON instruction with no privilege restrictions.

for i = 0 to elements_in_vector(Q, size) - 1 do
  if shift_amount < element_width(size) then
    Vd[i] ← Vn[i] << shift_amount
  else
    Vd[i] ← 0
  end if
end for


Summary: Shifts elements right (logical).

Vector Unsigned Shift Right performs a logical right shift on each element of a NEON register by an immediate value, filling vacated bit positions with zeros. The immediate shift amount is encoded in the imm field and must be within the range [1, element_width]; shifting by the element width or more produces a zero result. This instruction does not modify the condition flags. AArch64-only NEON instruction with no privilege restrictions.

for i = 0 to elements_in_vector(Q, size) - 1 do
  if shift_amount <= element_width(size) then
    Vd[i] ← Vn[i] >> shift_amount
  else
    Vd[i] ← 0
  end if
end for


Summary: Shifts elements right (arithmetic/sign-extending).

Shifts each signed element in the vector right by an immediate shift count, filling the vacated bits with the sign bit (arithmetic right shift). The shift amount is encoded in the imm field; the element size is determined by the type specifier (.8B, .4H, .2S, .1D, etc.). Condition flags are not affected. This is a NEON instruction available in AArch64 execution state.

shift_amount ← imm
for i = 0 to elements_in_vector - 1
  Vd[i] ← SignExtend(Vn[i] >> shift_amount, element_width)


Summary: Compares elements (Vn > Vm) and sets bits to all 1s or 0s.

Compares each signed element of Vn with the corresponding element of Vm; if Vn[i] > Vm[i], sets all bits in Vd[i] to 1; otherwise sets them to 0. The comparison is signed. Condition flags are not affected. This is a NEON instruction available in AArch64 execution state.

for i = 0 to elements_in_vector - 1
  if (Vn[i] > Vm[i]) then
    Vd[i] ← all_ones
  else
    Vd[i] ← all_zeros


Summary: Compares elements (Vn == Vm) and sets bits to all 1s or 0s.

Compares each element of Vn with the corresponding element of Vm for equality; if Vn[i] == Vm[i], sets all bits in Vd[i] to 1; otherwise sets them to 0. The comparison is bitwise exact, regardless of signedness. Condition flags are not affected. This is a NEON instruction available in AArch64 execution state.

for i = 0 to elements_in_vector - 1
  if (Vn[i] == Vm[i]) then
    Vd[i] ← all_ones
  else
    Vd[i] ← all_zeros


Summary: Compares elements (Vn >= Vm).

Compares each signed element of Vn with the corresponding element of Vm; if Vn[i] >= Vm[i], sets all bits in Vd[i] to 1; otherwise sets them to 0. The comparison is signed. Condition flags are not affected. This is a NEON instruction available in AArch64 execution state.

for i = 0 to elements_in_vector - 1
  if (Vn[i] >= Vm[i]) then
    Vd[i] ← all_ones
  else
    Vd[i] ← all_zeros


Summary: Tests if any bits match ((Vn & Vm) != 0).

Tests whether any bits match between Vn and Vm by computing the bitwise AND; if (Vn[i] & Vm[i]) != 0, sets all bits in Vd[i] to 1; otherwise sets them to 0. Condition flags are not affected. This is a NEON instruction available in AArch64 execution state.

for i = 0 to elements_in_vector - 1
  if ((Vn[i] & Vm[i]) != 0) then
    Vd[i] ← all_ones
  else
    Vd[i] ← all_zeros


Summary: Adds all elements of the vector into a scalar result.

Adds all elements in the vector and places the scalar result in the destination register. The result element width matches the input element width, and only the corresponding element in Vd is updated (upper bits of the 128-bit register are zeroed for the scalar result). Condition flags are not affected. This is a NEON across-lane instruction available in AArch64 execution state.

result ← 0
for i = 0 to elements_in_vector - 1
  result ← result + Vn[i]
Vd[result_element_index] ← result
Vd[upper_bits] ← 0


Summary: Finds the maximum signed value across the vector.

Finds the maximum signed value among all elements in the vector and places the scalar result in the destination register. The result element width matches the input element width, and only the corresponding scalar element in Vd is updated (upper bits are zeroed). Condition flags are not affected. This is a NEON across-lane instruction available in AArch64 execution state.

result ← Vn[0]
for i = 1 to elements_in_vector - 1
  result ← max_signed(result, Vn[i])
Vd[result_element_index] ← result
Vd[upper_bits] ← 0


Summary: Finds the minimum unsigned value across the vector.

Finds the minimum unsigned value among all elements in the vector and places the scalar result in the destination register. The result element width matches the input element width, and only the corresponding scalar element in Vd is updated (upper bits are zeroed). Condition flags are not affected. This is a NEON across-lane instruction available in AArch64 execution state.

result ← Vn[0]
for i = 1 to elements_in_vector - 1
  result ← min_unsigned(result, Vn[i])
Vd[result_element_index] ← result
Vd[upper_bits] ← 0


Summary: Interleaves the lower halves of two vectors.

Interleaves the lower halves of two vectors by taking alternate elements from Vn and Vm and writing them to Vd. This is a pure data movement operation with no flag updates. Execution is restricted to AArch64 with NEON support (ARMv8.0+) and does not require elevated privilege.

bits(128) result;
for e = 0 to (esize/8)-1
  result[e*16 +: 8] ← Vn[e*16 +: 8];
  result[e*16 + 8 +: 8] ← Vm[e*16 +: 8];
if Q == 0 then
  Vd ← result[0 +: 64];
else
  Vd ← result;


Summary: Interleaves the upper halves of two vectors.

Interleaves the upper halves of two vectors by taking alternate elements from the upper halves of Vn and Vm. Like ZIP1, this is a permutation-only operation with no flag updates. Execution is restricted to AArch64 with NEON support (ARMv8.0+).

bits(128) result;
for e = 0 to (esize/8)-1
  result[e*16 +: 8] ← Vn[(e+half)*16 +: 8];
  result[e*16 + 8 +: 8] ← Vm[(e+half)*16 +: 8];
if Q == 0 then
  Vd ← result[0 +: 64];
else
  Vd ← result;


Summary: De-interleaves lower halves (Selects odd elements).

De-interleaves the lower halves of two vectors by selecting odd-indexed elements (every other element starting from index 1) from the concatenation of Vn and Vm. This is a pure permutation with no flag updates. Execution is restricted to AArch64 with NEON support (ARMv8.0+).

bits(128) concatenated = Vn[0 +: 64] concatenate Vm[0 +: 64];
bits(128) result;
for e = 0 to (esize/8)-1
  result[e*8 +: 8] ← concatenated[(e*2 + 1)*8 +: 8];
if Q == 0 then
  Vd ← result[0 +: 64];
else
  Vd ← result;


Summary: De-interleaves upper halves (Selects even elements).

De-interleaves the upper halves of two vectors by selecting even-indexed elements (every other element starting from index 0) from the concatenation of Vn and Vm. This is a pure permutation with no flag updates. Execution is restricted to AArch64 with NEON support (ARMv8.0+).

bits(128) concatenated = Vn[0 +: 64] concatenate Vm[0 +: 64];
bits(128) result;
for e = 0 to (esize/8)-1
  result[e*8 +: 8] ← concatenated[(e*2)*8 +: 8];
if Q == 0 then
  Vd ← result[0 +: 64];
else
  Vd ← result;


Summary: Transposes elements (Lower).

Transposes elements by interleaving lower halves of Vn and Vm in a transposition pattern, selecting alternate elements from Vn first. This is a pure permutation with no flag updates. Execution is restricted to AArch64 with NEON support (ARMv8.0+).

bits(128) result;
for e = 0 to (esize/16)-1
  result[e*16 +: 8] ← Vn[e*16 +: 8];
  result[e*16 + 8 +: 8] ← Vm[e*16 +: 8];
if Q == 0 then
  Vd ← result[0 +: 64];
else
  Vd ← result;


Summary: Transposes elements (Upper).

Transposes elements by interleaving upper halves of Vn and Vm in a transposition pattern, selecting alternate elements from Vn first. This is a pure permutation with no flag updates. Execution is restricted to AArch64 with NEON support (ARMv8.0+).

bits(128) result;
for e = 0 to (esize/16)-1
  result[e*16 +: 8] ← Vn[(e + half)*16 +: 8];
  result[e*16 + 8 +: 8] ← Vm[(e + half)*16 +: 8];
if Q == 0 then
  Vd ← result[0 +: 64];
else
  Vd ← result;


Summary: Look up elements in a table of vectors using indices.

Uses byte-index elements in Vm to look up corresponding bytes in a table formed by one or more consecutive SIMD registers starting at Vn, writing the results to Vd. Out-of-range indices return zero; this is a pure permutation with no flag updates. Execution is restricted to AArch64 with NEON support (ARMv8.0+).

bits(128) table[(len+1)*128-1:0];
for i = 0 to len
  table[i*128 +: 128] ← V[(Rn + i) mod 32];
for e = 0 to elements-1
  index ← Vm[e*8 +: 8];
  if index < (len+1)*16 then
    result[e*8 +: 8] ← table[index*8 +: 8];
  else
    result[e*8 +: 8] ← 0;
Vd ← result;


Summary: Reads elements, narrows them, and writes to lower half of destination.

Extracts elements from Vn, narrows them by taking the least significant bits according to the narrower type, and writes them to the lower half of Vd. The upper half of Vd is zeroed. This is a type conversion with no flag updates. Execution is restricted to AArch64 with NEON support (ARMv8.0+).

esize_src ← 8 << size;
esize_dst ← esize_src / 2;
for e = 0 to esize_dst-1
  element ← Vn[e * esize_src +: esize_src];
  result[e * esize_dst +: esize_dst] ← element[0 +: esize_dst];
Vd[0 +: 64] ← result[0 +: 64];
Vd[64 +: 64] ← 0;


Summary: Loads one element structure from memory into 1-4 registers.

Loads one element structure from memory into 1-4 NEON vector registers. The Q bit determines vector size (64-bit for Q=0, 128-bit for Q=1). No condition flags are affected. AArch64-only instruction; requires NEON extension support.

address ← Xn
for i = 0 to num_registers - 1 do
  Vt[i] ← memory[address + offset]
if postindex then Xn ← Xn + transfer_size


Summary: Stores one element structure from 1-4 registers to memory.

Stores one element structure from 1-4 NEON vector registers to memory. The Q bit determines vector size (64-bit for Q=0, 128-bit for Q=1). No condition flags are affected. AArch64-only instruction; requires NEON extension support.

address ← Xn
for i = 0 to num_registers - 1 do
  memory[address + offset] ← Vt[i]
if postindex then Xn ← Xn + transfer_size


Pointer Authentication Code Generic Address

Summary: Computes a pointer authentication code for an address and modifier.

Computes a pointer authentication code (PAC) for a generic address using the provided address and modifier. The result is placed in Xd with only the PAC bits set; other bits are cleared. No condition flags are affected. AArch64-only; requires PAC extension; may trap if PAC key is not initialized.

pac ← ComputePAC(Xn, Xm, PAC_key_generic)
Xd ← SignExtend(pac, 64)


Pointer Authentication Code for Instruction Address (Key A)

Summary: Signs an instruction address using Key A.

Computes a pointer authentication code for an instruction address using Key A and the modifier in Xn, storing the signed value in Xd. This is an AArch64-only instruction used for control-flow integrity. No general-purpose condition flags are set; authentication failure (during later verification) generates an exception.

Xd ← AddPAC(Xd, Xn, Key_A, InstructionAddressType)


Pointer Authentication Code for Instruction Address (Key B)

Summary: Signs an instruction address using Key B.

Computes a pointer authentication code for an instruction address using Key B and the modifier in Xn, storing the signed value in Xd. This is an AArch64-only instruction used for control-flow integrity. No general-purpose condition flags are set; authentication failure (during later verification) generates an exception.

Xd ← AddPAC(Xd, Xn, Key_B, InstructionAddressType)


Pointer Authentication Code for Data Address (Key A)

Summary: Signs a data address using Key A.

Computes a pointer authentication code for a data address using Key A and the modifier in Xn, storing the signed value in Xd. This is an AArch64-only instruction used for data-pointer integrity. No general-purpose condition flags are set; authentication failure (during later verification) generates an exception.

Xd ← AddPAC(Xd, Xn, Key_A, DataAddressType)


Pointer Authentication Code for Data Address (Key B)

Summary: Signs a data address using Key B.

Computes a pointer authentication code for a data address using Key B and the modifier in Xn, storing the signed value in Xd. This is an AArch64-only instruction used for data-pointer integrity. No general-purpose condition flags are set; authentication failure (during later verification) generates an exception.

Xd ← AddPAC(Xd, Xn, Key_B, DataAddressType)


Authenticate Instruction Address (Key A)

Summary: Authenticates an instruction address signed with Key A.

Authenticates a 64-bit instruction address in Xd using Key A and a modifier in Xn. The instruction performs cryptographic verification of the pointer authentication code (PAC) embedded in Xd. If authentication fails, the result is corrupted (set to an invalid address). This instruction is AArch64-only and requires ARMv8.3-A or later with PAC extension enabled; it does not affect condition flags.


Authenticate Instruction Address (Key B)

Summary: Authenticates an instruction address signed with Key B.

Authenticates a 64-bit instruction address in Xd using Key B and a modifier in Xn. Similar to AUTIA, this instruction cryptographically verifies the pointer authentication code embedded in Xd using the alternate (Key B) authentication key. If authentication fails, the result is corrupted. This instruction is AArch64-only and requires ARMv8.3-A or later with PAC extension enabled; it does not affect condition flags.


Summary: Authenticates a data address signed with Key A.

Authenticates a 64-bit data address in Xd using Key A and a modifier in Xn. The instruction performs cryptographic verification of the pointer authentication code (PAC) embedded in Xd for data pointers. If authentication fails, the result is corrupted (set to an invalid address). This instruction is AArch64-only and requires ARMv8.3-A or later with PAC extension enabled; it does not affect condition flags.


Summary: Authenticates a data address signed with Key B.

Authenticates a 64-bit data address in Xd using Key B and a modifier in Xn. Similar to AUTDA, this instruction cryptographically verifies the pointer authentication code embedded in Xd for data pointers using the alternate (Key B) authentication key. If authentication fails, the result is corrupted. This instruction is AArch64-only and requires ARMv8.3-A or later with PAC extension enabled; it does not affect condition flags.


Summary: Removes the pointer authentication code from an instruction address.

Strips the pointer authentication code from the instruction address held in LR, clearing the PAC bits but retaining the address bits. Used after an indirect branch to remove authentication metadata. No condition flags are affected. AArch64-only; requires PAC extension; no operands.


Summary: Mark a valid target for an indirect branch (Control Flow Integrity).

Marks a valid branch target for indirect branches as part of Control Flow Integrity (CFI). Encodes the expected branch target type (c=call, j=jump, jc=both) in the immediate field. Causes a PACM fault if the branch was not of the expected type. No condition flags are affected. AArch64-only; requires BTI extension.

if current_branch_type is not compatible with target then
  raise PACM_exception
else
  NOP


Summary: Stores the Allocation Tag to memory.

Stores the Allocation Tag from Xt to a single 16-byte memory granule at [Xn + offset]. The offset is scaled by 16 (imm9 is left-shifted by 4). No condition flags are affected. AArch64-only; requires MTE extension; generates an exception if MTE is not enabled or tag check fails.

address ← Xn + (SignExtend(imm9, 9) << 4)
tag ← GetAllocationTag(Xt)
memory[address] ← memory[address] with tag set to tag


Store Allocation Tag and Zero (Two Granules)

Summary: Stores Tag and zeros memory for two granules.

Stores the Allocation Tag from Xt to two consecutive 16-byte memory granules and zeros both granules. The offset is scaled by 16. Useful for initializing memory with a specific tag. No condition flags are affected. AArch64-only; requires MTE extension.

address ← Xn + (SignExtend(imm9, 9) << 4)
tag ← GetAllocationTag(Xt)
memory[address : address + 15] ← 0 with tag set to tag
memory[address + 16 : address + 31] ← 0 with tag set to tag


Summary: Subtracts pointers (ignoring tags) and sets condition flags.

Subtracts the second source pointer from the first, ignoring memory tag bits in both operands, and updates the N, Z, C, and V condition flags based on the 64-bit result. The tagged address bits are excluded from the arithmetic so the comparison reflects only the pointer value. Available when the Memory Tagging Extension (MTE) is implemented.

Xd ← Xn - Xm
// Flags affected: N, Z, C, V


Summary: Atomic Compare and Swap (32-bit).

Atomic compare and swap of a 32-bit word. Compares the value in Ws with the memory location at address Xn; if equal, stores Wt to that location and loads the old memory value into Ws; otherwise loads the memory value into Ws. This is an AArch64-only instruction requiring LSE extension support. The instruction does not modify condition flags; it provides full sequential consistency without explicit acquire/release semantics.

address ← Xn; old_value ← [address]; if Ws == old_value then [address] ← Wt; Ws ← old_value; else Ws ← old_value;


Summary: Atomic Compare and Swap (64-bit).

Atomic compare and swap of a 64-bit doubleword. Compares the value in Xs with the memory location at address Xn; if equal, stores Xt to that location and loads the old memory value into Xs; otherwise loads the memory value into Xs. This is an AArch64-only instruction requiring LSE extension support. The instruction does not modify condition flags; it provides full sequential consistency without explicit acquire/release semantics.

address ← Xn; old_value ← [address]; if Xs == old_value then [address] ← Xt; Xs ← old_value; else Xs ← old_value;


Summary: Atomic CAS with Acquire semantics.

Atomic compare and swap of a 32-bit word with acquire semantics. Compares Ws with memory at address Xn; if equal, stores Wt and loads old value into Ws; otherwise loads the memory value into Ws. This AArch64-only LSE instruction provides an acquire barrier for load operations, preventing subsequent memory operations from being observed before this load completes. Condition flags are not affected.

address ← Xn; AcquireSemantics(); old_value ← [address]; if Ws == old_value then [address] ← Wt; Ws ← old_value; else Ws ← old_value;