{"mnemonic": "inc", "architecture": "x86", "full_name": "Increment", "summary": "Increments the operand by 1.", "syntax": "INC r/m", "encoding": {"format": "Legacy", "hex_opcode": "FF /0", "visual_parts": [], "binary_pattern": "FF | ModRM", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m", "desc": "Register or memory operand"}], "description": "Increments operand by 1 and stores result in operand. Sets OF, SF, ZF, AF, PF; does not affect CF. Supports 8/16/32/64-bit operand sizes in all modes. Useful for loop counters and pointer arithmetic.", "pseudocode": "result ← dest + 1; dest ← result; OF ← overflow; ZF ← (result == 0); SF ← (result < 0); AF ← (result & 0xF); PF ← parity(result)", "example": "INC rbx"} {"mnemonic": "dec", "architecture": "x86", "full_name": "Decrement", "summary": "Decrements the operand by 1.", "syntax": "DEC r/m", "encoding": {"format": "Legacy", "hex_opcode": "FF /1", "visual_parts": [], "binary_pattern": "FF | ModRM", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m", "desc": "Register or memory operand"}], "description": "Decrements operand by 1 and stores result in operand. Sets OF, SF, ZF, AF, PF; does not affect CF. Supports 8/16/32/64-bit operand sizes in all modes. Commonly used in loop control.", "pseudocode": "result ← dest - 1; dest ← result; OF ← overflow; ZF ← (result == 0); SF ← (result < 0); AF ← (result & 0xF); PF ← parity(result)", "example": "DEC rbx"} {"mnemonic": "mul", "architecture": "x86", "full_name": "Unsigned Multiply", "summary": "Unsigned multiply (AX = AL * src).", "syntax": "MUL r/m", "encoding": {"format": "Legacy", "hex_opcode": "F7 /4", "visual_parts": [], "binary_pattern": "F7 | ModRM", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m", "desc": "Register or memory operand"}], "description": "Performs unsigned multiplication of accumulator (AL/AX/EAX/RAX) by operand, storing result in AX/DX:AX/EDX:EAX/RDX:RAX respectively. Sets CF and OF if product overflows accumulator width; other flags undefined. High byte/word/dword/qword of result goes into AH/DX/EDX/RDX.", "pseudocode": "if (operand_width == 8) { product ← AL * src; AX ← product; CF ← OF ← (AH != 0); } else if (operand_width == 16) { product ← AX * src; DX:AX ← product; CF ← OF ← (DX != 0); } else if (operand_width == 32) { product ← EAX * src; EDX:EAX ← product; CF ← OF ← (EDX != 0); } else { product ← RAX * src; RDX:RAX ← product; CF ← OF ← (RDX != 0); }", "example": "MUL rbx"} {"mnemonic": "imul", "architecture": "x86", "full_name": "Signed Multiply", "summary": "Signed multiply.", "syntax": "IMUL r, r/m", "encoding": {"format": "Legacy", "hex_opcode": "0F AF", "visual_parts": [], "binary_pattern": "0F | AF", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r", "desc": "General-purpose register"}, {"name": "src", "type": "r/m", "desc": "Register or memory operand"}], "description": "Performs signed multiplication of destination register by source operand, storing result in destination. Sets OF and CF if result overflows destination width; SF, ZF, AF, PF undefined. Two-operand form (dest ← dest * src) is commonly used for scalar multiplies; one-operand form multiplies into EDX:EAX.", "pseudocode": "result ← dest * src; dest ← result; if (result overflows dest width) { CF ← 1; OF ← 1; } else { CF ← 0; OF ← 0; }", "example": "IMUL rax, rbx"} {"mnemonic": "div", "architecture": "x86", "full_name": "Unsigned Divide", "summary": "Unsigned divide (AX / src).", "syntax": "DIV r/m", "encoding": {"format": "Legacy", "hex_opcode": "F7 /6", "visual_parts": [], "binary_pattern": "F7 | ModRM", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m", "desc": "Register or memory operand"}], "description": "Performs unsigned division of accumulator (AX/DX:AX/EDX:EAX/RDX:RAX) by operand, storing quotient in AL/AX/EAX/RAX and remainder in AH/DX/EDX/RDX respectively. All flags undefined after division. Raises #DE exception if divisor is zero or quotient overflows.", "pseudocode": "if (operand_width == 8) { quotient ← AX / src; remainder ← AX mod src; AL ← quotient; AH ← remainder; } else if (operand_width == 16) { quotient ← DX:AX / src; remainder ← DX:AX mod src; AX ← quotient; DX ← remainder; } else if (operand_width == 32) { quotient ← EDX:EAX / src; remainder ← EDX:EAX mod src; EAX ← quotient; EDX ← remainder; } else { quotient ← RDX:RAX / src; remainder ← RDX:RAX mod src; RAX ← quotient; RDX ← remainder; }", "example": "DIV rbx"} {"mnemonic": "idiv", "architecture": "x86", "full_name": "Signed Divide", "summary": "Signed divide (AX / src).", "syntax": "IDIV r/m", "encoding": {"format": "Legacy", "hex_opcode": "F7 /7", "visual_parts": [], "binary_pattern": "F7 | ModRM", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m", "desc": "Register or memory operand"}], "description": "Performs signed division of the implicit accumulator (EDX:EAX for 32-bit or RDX:RAX for 64-bit) by the specified operand; quotient is stored in EAX/RAX and remainder in EDX/RDX. Sets OF, SF, ZF, AF, CF, and PF to undefined values; raises #DE exception if divisor is zero or quotient overflows. Available in 8-bit (AX/AL:AH), 16-bit (DX:AX), 32-bit, and 64-bit variants.", "pseudocode": "if (src == 0) raise #DE;\ntemp_dividend = (src_size == 8) ? AX : ((src_size == 16) ? (DX:AX) : ((src_size == 32) ? (EDX:EAX) : (RDX:RAX)));\nif ((temp_dividend / src) > max_signed || (temp_dividend / src) < min_signed) raise #DE;\nquotient = temp_dividend / src;\nremainder = temp_dividend % src;\nif (src_size == 8) { AL ← quotient; AH ← remainder; }\nelse if (src_size == 16) { AX ← quotient; DX ← remainder; }\nelse if (src_size == 32) { EAX ← quotient; EDX ← remainder; }\nelse { RAX ← quotient; RDX ← remainder; }\nOF ← undefined; SF ← undefined; ZF ← undefined; AF ← undefined; CF ← undefined; PF ← undefined;", "example": "IDIV rbx"} {"mnemonic": "not", "architecture": "x86", "full_name": "One's Complement Negation", "summary": "Reverses bits of operand.", "syntax": "NOT r/m", "encoding": {"format": "Legacy", "hex_opcode": "F7 /2", "visual_parts": [], "binary_pattern": "F7 | ModRM", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m", "desc": "Register or memory operand"}], "description": "Performs one's complement (bitwise negation) on the operand, inverting all bits and storing the result back. Does not affect any flags. Available in 8/16/32/64-bit variants.", "pseudocode": "dest ← ~dest;", "example": "NOT rbx"} {"mnemonic": "neg", "architecture": "x86", "full_name": "Two's Complement Negation", "summary": "Negates value (0 - operand).", "syntax": "NEG r/m", "encoding": {"format": "Legacy", "hex_opcode": "F7 /3", "visual_parts": [], "binary_pattern": "F7 | ModRM", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m", "desc": "Register or memory operand"}], "description": "Performs two's complement negation (0 - operand), storing the result back in the operand. Sets/clears CF, OF, ZF, SF, AF, PF based on result; CF is set unless operand was zero. Available in 8/16/32/64-bit variants.", "pseudocode": "old_operand ← dest;\nresult ← 0 - dest;\ndest ← result;\nCF ← (old_operand != 0);\nOF ← (old_operand == (1 << (operand_size * 8 - 1)));\nZF ← (result == 0);\nSF ← (result & sign_bit) != 0;\nPF ← popcount(result & 0xFF) % 2 == 0;\nAF ← ((0 - old_operand) & 0x10) != (old_operand & 0x10);", "example": "NEG rbx"} {"mnemonic": "shl", "architecture": "x86", "full_name": "Shift Logical Left", "summary": "Shifts bits left (same as SAL).", "syntax": "SHL r/m, imm8", "encoding": {"format": "Legacy", "hex_opcode": "C1 /4", "visual_parts": [], "binary_pattern": "C1 | ModRM", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m", "desc": "Register or memory operand"}, {"name": "src", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Shifts the bits of the destination operand left by the count specified in the immediate operand, filling vacated bits with zeros; leftmost bit is shifted into CF. Sets CF and OF based on shift; ZF, SF, PF reflect the result. Available in 8/16/32/64-bit variants; count is typically 1 or specified by imm8.", "pseudocode": "if (count == 0) return;\ntemp ← dest;\nCF ← (dest >> (operand_size * 8 - count)) & 1;\nresult ← dest << count;\nOF ← (result & sign_bit) != (temp & sign_bit);\nZF ← (result == 0);\nSF ← (result & sign_bit) != 0;\nPF ← popcount(result & 0xFF) % 2 == 0;\ndest ← result;", "example": "SHL rbx, 3"} {"mnemonic": "shr", "architecture": "x86", "full_name": "Shift Logical Right", "summary": "Shifts bits right, filling with zeros.", "syntax": "SHR r/m, imm8", "encoding": {"format": "Legacy", "hex_opcode": "C1 /5", "visual_parts": [], "binary_pattern": "C1 | ModRM", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m", "desc": "Register or memory operand"}, {"name": "src", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Shifts the bits of the destination operand right by the count specified in the immediate operand, filling vacated bits with zeros; rightmost bit is shifted into CF. Sets CF and OF based on shift; ZF, SF, PF reflect the result. Available in 8/16/32/64-bit variants; count is typically 1 or specified by imm8.", "pseudocode": "if (count == 0) return;\ntemp ← dest;\nCF ← (dest >> (count - 1)) & 1;\nresult ← dest >> count;\nOF ← (temp & sign_bit);\nZF ← (result == 0);\nSF ← 0;\nPF ← popcount(result & 0xFF) % 2 == 0;\ndest ← result;", "example": "SHR rbx, 3"} {"mnemonic": "sar", "architecture": "x86", "full_name": "Shift Arithmetic Right", "summary": "Shifts bits right, preserving sign bit.", "syntax": "SAR r/m, imm8", "encoding": {"format": "Legacy", "hex_opcode": "C1 /7", "visual_parts": [], "binary_pattern": "C1 | ModRM", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m", "desc": "Register or memory operand"}, {"name": "src", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Shifts the bits of the destination operand right by the number of bits specified in the source operand, with the sign bit (MSB) replicated into vacated positions, preserving the sign of the value. The Carry Flag is set to the last bit shifted out. Available in 8/16/32/64-bit variants; OF is undefined when count > 1.", "pseudocode": "shift_count ← src\ntemp ← dest\nfor i ← 0 to shift_count - 1 do\n CF ← temp[0]\n temp ← (sign_extend(temp[width-1]) << (width-1)) | (temp >> 1)\ndest ← temp\nif shift_count == 1 then\n OF ← 0\nelse if shift_count > 1 then\n OF ← undefined\nZF ← (dest == 0)\nSF ← dest[width-1]\nPF ← parity(dest)", "example": "SAR rbx, 3"} {"mnemonic": "jmp", "architecture": "x86", "full_name": "Jump", "summary": "Unconditional jump to target.", "syntax": "JMP rel", "encoding": {"format": "Legacy", "hex_opcode": "EB CB", "visual_parts": [], "binary_pattern": "EB | E9", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "rel", "desc": "Relative branch offset"}], "description": "Performs an unconditional jump by adding the sign-extended relative offset to the instruction pointer (EIP/RIP). Available in 8-bit relative (EB opcode, -128 to +127) and 32-bit relative (E9 opcode) variants. No flags are affected.", "pseudocode": "if operand_size == 8 then\n RIP ← RIP + sign_extend_8(rel8)\nelse if operand_size == 32 then\n RIP ← RIP + sign_extend_32(rel32)\n// In 64-bit mode, RIP is the canonical form of EIP", "example": "JMP 0x401000 ; Jump to address\nJMP label ; Jump to label"} {"mnemonic": "je", "architecture": "x86", "full_name": "Jump if Equal", "summary": "Jump if ZF=1 (Same as JZ).", "syntax": "JE rel", "encoding": {"format": "Legacy", "hex_opcode": "74", "visual_parts": [], "binary_pattern": "74", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "rel", "desc": "Relative branch offset"}], "description": "Jumps to the target if the Zero Flag is set (ZF=1), indicating the result of a prior comparison or arithmetic operation was zero. Available in 8-bit relative form (opcode 74). No flags are affected by the jump itself; the jump condition is determined by previously set flags.", "pseudocode": "if ZF == 1 then\n RIP ← RIP + sign_extend_8(rel8)\nelse\n RIP ← RIP + 1 // no jump, continue to next instruction", "example": "JE rel"} {"mnemonic": "jne", "architecture": "x86", "full_name": "Jump if Not Equal", "summary": "Jump if ZF=0 (Same as JNZ).", "syntax": "JNE rel", "encoding": {"format": "Legacy", "hex_opcode": "75", "visual_parts": [], "binary_pattern": "75", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "rel", "desc": "Relative branch offset"}], "description": "Jumps to the target if the Zero Flag is clear (ZF=0), indicating the result of a prior comparison or arithmetic operation was non-zero. Available in 8-bit relative form (opcode 75). No flags are affected by the jump itself; the jump condition is determined by previously set flags.", "pseudocode": "if ZF == 0 then\n RIP ← RIP + sign_extend_8(rel8)\nelse\n RIP ← RIP + 1 // no jump, continue to next instruction", "example": "JNE rel"} {"mnemonic": "jg", "architecture": "x86", "full_name": "Jump if Greater", "summary": "Jump if ZF=0 and SF=OF (Signed >).", "syntax": "JG rel", "encoding": {"format": "Legacy", "hex_opcode": "7F", "visual_parts": [], "binary_pattern": "7F", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "rel", "desc": "Relative branch offset"}], "description": "Jumps to the target if the Zero Flag is clear and Sign Flag equals Overflow Flag (ZF=0 AND SF=OF), indicating a signed arithmetic result is greater than zero. Available in 8-bit relative form (opcode 7F). No flags are affected by the jump itself; the jump condition depends on previously set flags.", "pseudocode": "if (ZF == 0) AND (SF == OF) then\n RIP ← RIP + sign_extend_8(rel8)\nelse\n RIP ← RIP + 1 // no jump, continue to next instruction", "example": "JG rel"} {"mnemonic": "jl", "architecture": "x86", "full_name": "Jump if Less", "summary": "Jump if SF!=OF (Signed <).", "syntax": "JL rel", "encoding": {"format": "Legacy", "hex_opcode": "7C", "visual_parts": [], "binary_pattern": "7C", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "rel", "desc": "Relative branch offset"}], "description": "Jumps to the target if Sign Flag does not equal Overflow Flag (SF≠OF), indicating a signed arithmetic result is less than zero. Available in 8-bit relative form (opcode 7C). No flags are affected by the jump itself; the jump condition depends on previously set flags.", "pseudocode": "if SF != OF then\n RIP ← RIP + sign_extend_8(rel8)\nelse\n RIP ← RIP + 1 // no jump, continue to next instruction", "example": "JL rel"} {"mnemonic": "ja", "architecture": "x86", "full_name": "Jump if Above", "summary": "Jump if CF=0 and ZF=0 (Unsigned >).", "syntax": "JA rel", "encoding": {"format": "Legacy", "hex_opcode": "77", "visual_parts": [], "binary_pattern": "77", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "rel", "desc": "Relative branch offset"}], "description": "Performs a conditional jump to the target address if the previous comparison or arithmetic operation resulted in an unsigned greater-than condition (CF=0 AND ZF=0). This instruction is commonly used after unsigned comparisons (CMP) to branch based on the above condition. No flags are modified by this instruction; it only reads CF and ZF to determine the jump condition.", "pseudocode": "if (CF == 0 && ZF == 0) { RIP ← RIP + sign_extend(rel); }", "example": "JA rel"} {"mnemonic": "jb", "architecture": "x86", "full_name": "Jump if Below", "summary": "Jump if CF=1 (Unsigned <).", "syntax": "JB rel", "encoding": {"format": "Legacy", "hex_opcode": "72", "visual_parts": [], "binary_pattern": "72", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "rel", "desc": "Relative branch offset"}], "description": "Performs a conditional jump to the target address if the carry flag is set (CF=1), indicating an unsigned less-than condition from the previous operation. Commonly used after unsigned CMP or arithmetic operations to branch on the below condition. No flags are modified; the instruction only reads CF.", "pseudocode": "if (CF == 1) { RIP ← RIP + sign_extend(rel); }", "example": "JB rel"} {"mnemonic": "call", "architecture": "x86", "full_name": "Call Procedure", "summary": "Push EIP/RIP and jump to target.", "syntax": "CALL rel", "encoding": {"format": "Legacy", "hex_opcode": "E8", "visual_parts": [], "binary_pattern": "E8", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "rel", "desc": "Relative branch offset"}], "description": "Pushes the return address (next instruction pointer) onto the stack and jumps to the target procedure. In 32-bit mode, EIP is pushed; in 64-bit mode, RIP is pushed. This instruction does not modify any arithmetic flags but causes implicit stack manipulation and memory writes. Control flow changes to the called procedure.", "pseudocode": "if (64-bit mode) { RSP ← RSP - 8; [RSP] ← RIP + instruction_length; RIP ← RIP + sign_extend(rel); } else { ESP ← ESP - 4; [ESP] ← EIP + instruction_length; EIP ← EIP + sign_extend(rel); }", "example": "CALL rel"} {"mnemonic": "ret", "architecture": "x86", "full_name": "Return from Procedure", "summary": "Pop EIP/RIP and resume execution.", "syntax": "RET", "encoding": {"format": "Legacy", "hex_opcode": "C3", "visual_parts": [], "binary_pattern": "C3", "bit_positions": "+0"}, "extension": "Base", "operands": [], "description": "Pops the return address from the stack and resumes execution at that address, effectively returning from a procedure called with CALL. In 32-bit mode, EIP is popped; in 64-bit mode, RIP is popped. No flags are modified. This instruction performs implicit stack manipulation and a memory read.", "pseudocode": "if (64-bit mode) { RIP ← [RSP]; RSP ← RSP + 8; } else { EIP ← [ESP]; ESP ← ESP + 4; }", "example": "RET"} {"mnemonic": "push", "architecture": "x86", "full_name": "Push Word/Doubleword/Quadword Onto Stack", "summary": "Decrements SP and stores operand on stack.", "syntax": "PUSH r/m", "encoding": {"format": "Legacy", "hex_opcode": "FF /6", "length": "2+", "visual_parts": [], "binary_pattern": "FF | ModRM", "bit_positions": "+0 | +1"}, "operands": [{"name": "src", "desc": "Reg/Mem"}], "extension": "Base", "description": "Decrements the stack pointer (ESP in 32-bit mode, RSP in 64-bit mode) by the operand size and stores the operand value at the new stack pointer. The operand can be a register or memory location. No flags are modified; this instruction performs implicit stack pointer decrement and a memory write.", "pseudocode": "if (64-bit mode) { RSP ← RSP - 8; [RSP] ← src_value; } else { ESP ← ESP - 4; [ESP] ← src_value; }", "example": "PUSH rbx"} {"mnemonic": "pop", "architecture": "x86", "full_name": "Pop Value from Stack", "summary": "Loads operand from stack and increments SP.", "syntax": "POP r/m", "encoding": {"format": "Legacy", "hex_opcode": "8F /0", "visual_parts": [], "binary_pattern": "8F | ModRM", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m", "desc": "Register or memory operand"}], "description": "Loads a value from the top of the stack into the destination operand and increments the stack pointer (ESP in 32-bit mode, RSP in 64-bit mode) by the operand size. The destination can be a register or memory location. No flags are modified; this instruction performs implicit stack pointer increment and a memory read.", "pseudocode": "if (64-bit mode) { dest_value ← [RSP]; RSP ← RSP + 8; } else { dest_value ← [ESP]; ESP ← ESP + 4; }", "example": "POP rbx"} {"mnemonic": "lea", "architecture": "x86", "full_name": "Load Effective Address", "summary": "Computes effective address and stores in register.", "syntax": "LEA r, m", "encoding": {"format": "Legacy", "hex_opcode": "8D", "visual_parts": [], "binary_pattern": "8D", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "r", "desc": "General-purpose register"}, {"name": "src", "type": "m", "desc": "Memory operand"}], "description": "Computes the effective address of the memory operand and stores it in the destination register without performing a memory access. This instruction is useful for address arithmetic and pointer calculations. No flags are modified by this instruction.", "pseudocode": "dest ← address_of(src)", "example": "LEA rax, [rbp-8]"} {"mnemonic": "nop", "architecture": "x86", "full_name": "No Operation", "summary": "Does nothing (alias for XCHG EAX, EAX).", "syntax": "NOP", "encoding": {"format": "Legacy", "hex_opcode": "NP 90", "visual_parts": [], "binary_pattern": "90", "bit_positions": "+0"}, "extension": "Base", "operands": [], "description": "Performs no operation and consumes one clock cycle. The one-byte NOP (0x90) is functionally equivalent to XCHG EAX, EAX. Longer NOP sequences (multi-byte) are available on newer processors for code padding without pipeline stalls. No flags are modified.", "pseudocode": "// No operation (pipeline advance only)", "example": "NOP"} {"mnemonic": "xchg", "architecture": "x86", "full_name": "Exchange Register/Memory with Register", "summary": "Exchanges content of two operands.", "syntax": "XCHG r/m, r", "encoding": {"format": "Legacy", "hex_opcode": "87", "visual_parts": [], "binary_pattern": "87", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m", "desc": "Register or memory operand"}, {"name": "src", "type": "r", "desc": "General-purpose register"}], "description": "Atomically exchanges the contents of two operands (register and register/memory or vice versa). The operation is performed with implicit locking semantics when one operand is memory, ensuring atomic behavior on multiprocessor systems. No flags are affected by this instruction.", "pseudocode": "temp ← dest; dest ← src; src ← temp;", "example": "XCHG rbx, rax"} {"mnemonic": "cpuid", "architecture": "x86", "full_name": "CPU Identification", "summary": "Returns processor information based on EAX value.", "syntax": "CPUID", "encoding": {"format": "Legacy", "hex_opcode": "0F A2", "visual_parts": [], "binary_pattern": "0F | A2", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [], "description": "Executes CPU identification, returning processor feature information and capabilities into EAX, EBX, ECX, and EDX based on the input value in EAX (and sometimes ECX). This is a privileged instruction in some contexts and causes a serializing event; it clears the pipeline and blocks out-of-order execution until completion. The exact output depends on the EAX input leaf and subleaf (ECX) values.", "pseudocode": "EAX, EBX, ECX, EDX ← cpuid_data[EAX, ECX];", "example": "CPUID"} {"mnemonic": "rdtsc", "architecture": "x86", "full_name": "Read Time-Stamp Counter", "summary": "Reads the time-stamp counter into EDX:EAX.", "syntax": "RDTSC", "encoding": {"format": "Legacy", "hex_opcode": "0F 31", "visual_parts": [], "binary_pattern": "0F | 31", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [], "description": "Reads the 64-bit time-stamp counter (TSC) and places the result in EDX:EAX, with EDX holding bits 63-32 and EAX holding bits 31-0. No flags are modified. This instruction is a serializing operation in some CPU implementations and may have variable latency; it is commonly used for performance measurement and requires appropriate privilege level or user-space access controls (managed by CR4.TSD).", "pseudocode": "EDX:EAX ← TimeStampCounter;", "example": "RDTSC"} {"mnemonic": "movsx", "architecture": "x86", "full_name": "Move with Sign-Extension", "summary": "Copies and sign-extends a smaller value to a larger register.", "syntax": "MOVSX r, r/m", "encoding": {"format": "Legacy", "hex_opcode": "0F BE", "visual_parts": [], "binary_pattern": "0F | BE", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r", "desc": "General-purpose register"}, {"name": "src", "type": "r/m", "desc": "Register or memory operand"}], "description": "Moves a value from a smaller source operand (8, 16, or 32 bits) to a larger destination register, sign-extending the value to fill the destination width. The sign bit of the source is copied to all high-order bits of the destination. No flags are affected by this instruction. Supported size combinations: r16 ← r/m8, r32 ← r/m8, r32 ← r/m16, r64 ← r/m8, r64 ← r/m16, r64 ← r/m32.", "pseudocode": "sign_bit ← src[source_width - 1]; dest ← (source_width < dest_width) ? (sign_extend(src, sign_bit, dest_width)) : src;", "example": "MOVSX rax, rbx"} {"mnemonic": "movzx", "architecture": "x86", "full_name": "Move with Zero-Extension", "summary": "Copies and zero-extends a smaller value to a larger register.", "syntax": "MOVZX r, r/m", "encoding": {"format": "Legacy", "hex_opcode": "0F B6", "visual_parts": [], "binary_pattern": "0F | B6", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r", "desc": "General-purpose register"}, {"name": "src", "type": "r/m", "desc": "Register or memory operand"}], "description": "Moves a value from a smaller source operand (8 or 16 bits) to a larger destination register, zero-extending the value to fill the destination width. All high-order bits of the destination beyond the source width are cleared to zero. No flags are affected by this instruction. Supported size combinations: r16 ← r/m8, r32 ← r/m8, r32 ← r/m16, r64 ← r/m8, r64 ← r/m16.", "pseudocode": "dest ← (source_width < dest_width) ? (zero_extend(src, dest_width)) : src;", "example": "MOVZX rax, rbx"} {"mnemonic": "cwtl", "architecture": "x86", "full_name": "Convert Word to Long", "summary": "Sign-extends AX into EAX (also CWDE).", "syntax": "CWTL", "encoding": {"format": "Legacy", "hex_opcode": "98", "visual_parts": [], "binary_pattern": "98", "bit_positions": "+0"}, "extension": "Base", "operands": [], "description": "Sign-extends the 16-bit value in AX into the 32-bit register EAX; the sign bit of AX (bit 15) is copied to all high-order bits (31-16) of EAX, and EAX's low 16 bits (AX) remain unchanged. This is a zero-operand instruction with no flags modified. In 64-bit mode, CWDE is the canonical mnemonic and has the same behavior.", "pseudocode": "EAX[31:16] ← (AX[15]) ? 0xFFFF : 0x0000;", "example": "CWTL"} {"mnemonic": "cltd", "architecture": "x86", "full_name": "Convert Long to Double Long", "summary": "Sign-extends EAX into EDX:EAX (also CDQ).", "syntax": "CLTD", "encoding": {"format": "Legacy", "hex_opcode": "99", "visual_parts": [], "binary_pattern": "99", "bit_positions": "+0"}, "extension": "Base", "operands": [], "description": "Sign-extends the 32-bit value in EAX into the 64-bit pair EDX:EAX; the sign bit of EAX (bit 31) is copied to all bits of EDX (bits 63-32), and EAX remains unchanged. This is a zero-operand instruction with no flags modified. In 64-bit mode, CDQ is the canonical mnemonic and has the same behavior. Commonly used before IDIV to prepare the dividend.", "pseudocode": "EDX ← (EAX[31]) ? 0xFFFFFFFF : 0x00000000;", "example": "CLTD"} {"mnemonic": "cqto", "architecture": "x86", "full_name": "Convert Quadword to Octoword", "summary": "Sign-extends RAX into RDX:RAX (also CQO).", "syntax": "CQTO", "encoding": {"format": "Legacy", "hex_opcode": "REX.W + 99", "visual_parts": [], "binary_pattern": "48 | 99", "bit_positions": "+0 | +1"}, "extension": "Base (64-bit)", "operands": [], "description": "Sign-extends the 64-bit value in RAX into the 128-bit pair RDX:RAX (64-bit mode only); the sign bit of RAX (bit 63) is copied to all bits of RDX, and RAX remains unchanged. This is a zero-operand instruction with no flags modified. CQO is the canonical mnemonic for this operation. Commonly used before IDIV (64-bit) to prepare the dividend.", "pseudocode": "RDX ← (RAX[63]) ? 0xFFFFFFFFFFFFFFFF : 0x0000000000000000;", "example": "CQTO"} {"mnemonic": "bswap", "architecture": "x86", "full_name": "Byte Swap", "summary": "Reverses the byte order of a register (Endian swap).", "syntax": "BSWAP r32", "encoding": {"format": "Legacy", "hex_opcode": "0F C8+rd", "visual_parts": [], "binary_pattern": "0F | C8+reg", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}], "description": "Reverses the byte order of a 32-bit register, converting between little-endian and big-endian representations. No flags are affected. This instruction requires 386+ and operates on 32-bit operands in protected and 64-bit modes; in 64-bit mode, a REX.W prefix extends it to 64-bit operands.", "pseudocode": "temp ← dest[0:7] || dest[8:15] || dest[16:23] || dest[24:31]\ndest ← dest[24:31] || dest[16:23] || dest[8:15] || temp", "example": "BSWAP eax"} {"mnemonic": "xadd", "architecture": "x86", "full_name": "Exchange and Add", "summary": "Exchanges dest and src, then loads sum into dest.", "syntax": "XADD r/m, r", "encoding": {"format": "Legacy", "hex_opcode": "0F C1", "visual_parts": [], "binary_pattern": "0F | C1", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m", "desc": "Register or memory operand"}, {"name": "src", "type": "r", "desc": "General-purpose register"}], "description": "Exchanges the values of dest and src, then stores their sum into dest. Sets OF, SF, ZF, AF, CF, PF based on the addition result. Implicitly uses the accumulator (EAX/RAX) for implicit operand size determination. Available in 386+ with size variants 8/16/32/64-bit; used in multi-threaded code for atomic operations.", "pseudocode": "temp ← src\nsrc ← dest\ndest ← dest + temp\nflags ← set based on (dest + temp) result\nZF ← (dest == 0); CF ← carry_out; OF ← overflow; SF ← (dest & sign_bit) != 0; PF ← parity(dest); AF ← (((dest ^ temp) ^ result) & 0x10) != 0", "example": "XADD rbx, rax"} {"mnemonic": "cmpxchg", "architecture": "x86", "full_name": "Compare and Exchange", "summary": "Compares accumulator with dest; if equal, dest = src; else accumulator = dest.", "syntax": "CMPXCHG r/m, r", "encoding": {"format": "Legacy", "hex_opcode": "0F B1", "visual_parts": [], "binary_pattern": "0F | B1", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m", "desc": "Register or memory operand"}, {"name": "src", "type": "r", "desc": "General-purpose register"}], "description": "Compares an implicit accumulator (AL/AX/EAX/RAX) with dest; if equal, src is written to dest and ZF is set; otherwise dest is written to the accumulator and ZF is cleared. Sets OF, SF, ZF, AF, CF, PF based on the comparison. Available in 386+ with size variants 8/16/32/64-bit; used for atomic compare-and-swap operations in lock-free code.", "pseudocode": "if (size == 8) {\n if (AL == dest) { dest ← src; ZF ← 1; } else { AL ← dest; ZF ← 0; }\n} else if (size == 16) {\n if (AX == dest) { dest ← src; ZF ← 1; } else { AX ← dest; ZF ← 0; }\n} else if (size == 32) {\n if (EAX == dest) { dest ← src; ZF ← 1; } else { EAX ← dest; ZF ← 0; }\n} else { /* size == 64 */\n if (RAX == dest) { dest ← src; ZF ← 1; } else { RAX ← dest; ZF ← 0; }\n}\nOF, SF, AF, CF, PF ← undefined (or set by comparison result)", "example": "CMPXCHG rbx, rax"} {"mnemonic": "cmovcc", "architecture": "x86", "full_name": "Conditional Move", "summary": "Moves data if condition code is met (e.g., CMOVE, CMOVNE).", "syntax": "CMOVcc r, r/m", "encoding": {"format": "Legacy", "hex_opcode": "0F 40 /r", "visual_parts": [], "binary_pattern": "0F", "bit_positions": "+0"}, "extension": "CMOV", "operands": [{"name": "dest", "type": "r", "desc": "General-purpose register"}, {"name": "src", "type": "r/m", "desc": "Register or memory operand"}], "description": "Conditionally moves src to dest if the specified condition code (based on EFLAGS) is true; otherwise dest is unchanged. No flags are modified. Available in P6+ processors (CMOV extension) with size variants 16/32/64-bit; eliminates branch mispredictions in conditional data flow.", "pseudocode": "if (condition_code) {\n dest ← src\n}\n/* EFLAGS unchanged */", "example": "CMOVcc rax, rbx"} {"mnemonic": "setcc", "architecture": "x86", "full_name": "Set Byte on Condition", "summary": "Sets byte to 1 if condition met, else 0 (e.g., SETE, SETZ).", "syntax": "SETcc r/m8", "encoding": {"format": "Legacy", "hex_opcode": "0F 90", "visual_parts": [], "binary_pattern": "0F", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m8", "desc": "8-bit register or memory"}], "description": "Sets the byte at dest to 1 if the specified condition code (based on EFLAGS) is true, otherwise sets it to 0. No other flags are affected. Available in 386+ with 8-bit size only; condition codes include SETE, SETNE, SETL, SETG, SETA, SETB, etc.", "pseudocode": "if (condition_code) {\n dest[0:7] ← 0xFF\n} else {\n dest[0:7] ← 0x00\n}\n/* EFLAGS unchanged */", "example": "SETcc bl"} {"mnemonic": "hlt", "architecture": "x86", "full_name": "Halt", "summary": "Stops instruction execution and places processor in HALT state.", "syntax": "HLT", "encoding": {"format": "Legacy", "hex_opcode": "F4", "visual_parts": [], "binary_pattern": "F4", "bit_positions": "+0"}, "extension": "Base", "operands": [], "description": "Stops instruction execution and places the processor in a HALT state, waiting for an external interrupt or reset. Requires privilege level 0 (kernel mode); attempting HLT in user mode raises a #GP exception. No flags are affected. Used in idle loops and system shutdown sequences.", "pseudocode": "halt_cpu()\n/* Wait for external interrupt or reset */", "example": "HLT"} {"mnemonic": "int", "architecture": "x86", "full_name": "Interrupt", "summary": "Calls to interrupt procedure.", "syntax": "INT imm8", "encoding": {"format": "Legacy", "hex_opcode": "CD ib", "visual_parts": [], "binary_pattern": "CD", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Invokes an interrupt handler identified by the 8-bit vector. Pushes EFLAGS (or RFLAGS), CS, and EIP (or RIP) onto the stack, then transfers control to the interrupt handler. Privilege level checked; IF flag is cleared upon entry. Available in all modes with different stack/address behaviors in real vs. protected vs. 64-bit mode.", "pseudocode": "if (mode == 64) {\n RSP ← RSP - 8; [RSP] ← RFLAGS\n RSP ← RSP - 8; [RSP] ← CS\n RSP ← RSP - 8; [RSP] ← RIP\n} else {\n ESP ← ESP - 4; [ESP] ← EFLAGS\n ESP ← ESP - 4; [ESP] ← CS\n ESP ← ESP - 4; [ESP] ← EIP\n}\nCS:RIP ← IDT[imm8]\nIF ← 0\nTF ← 0", "example": "INT 3"} {"mnemonic": "int3", "architecture": "x86", "full_name": "Breakpoint", "summary": "Calls to interrupt vector 3 (Debugger breakpoint).", "syntax": "INT3", "encoding": {"format": "Legacy", "hex_opcode": "CC", "visual_parts": [], "binary_pattern": "CC", "bit_positions": "+0"}, "extension": "Base", "operands": [], "description": "Invokes interrupt vector 3, which typically triggers a debugger breakpoint. Equivalent to INT 3 but encoded as a single byte (0xCC) for efficient inline breakpoint insertion. Pushes EFLAGS, CS, and EIP (or RFLAGS, CS, RIP in 64-bit mode) onto the stack. Available in all modes and privilege levels.", "pseudocode": "if (mode == 64) {\n RSP ← RSP - 8; [RSP] ← RFLAGS\n RSP ← RSP - 8; [RSP] ← CS\n RSP ← RSP - 8; [RSP] ← RIP\n} else {\n ESP ← ESP - 4; [ESP] ← EFLAGS\n ESP ← ESP - 4; [ESP] ← CS\n ESP ← ESP - 4; [ESP] ← EIP\n}\nCS:RIP ← IDT[3]\nIF ← 0\nTF ← 0", "example": "INT3"} {"mnemonic": "ud2", "architecture": "x86", "full_name": "Undefined Instruction", "summary": "Generates an invalid opcode exception.", "syntax": "UD2", "encoding": {"format": "Legacy", "hex_opcode": "0F 0B", "visual_parts": [], "binary_pattern": "0F | 0B", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [], "description": "Generates an invalid opcode exception (#UD) unconditionally, causing the processor to raise a fault. This instruction has no operands and performs no other operation. It is commonly used for intentional traps, unreachable code markers, and testing exception handling.", "pseudocode": "raise InvalidOpcodeException()", "example": "UD2"} {"mnemonic": "pause", "architecture": "x86", "full_name": "Spin Loop Hint", "summary": "Improves performance of spin-wait loops (alias for REP NOP).", "syntax": "PAUSE", "encoding": {"format": "Legacy", "hex_opcode": "F3 90", "visual_parts": [], "binary_pattern": "F3 | 90", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [], "description": "Provides a hint to the processor that the code is executing a spin-wait loop, improving power efficiency and reducing contention on shared memory buses without altering program logic. The instruction is semantically equivalent to REP NOP (F3 90 encoding) and executes as a very short delay; no flags are affected.", "pseudocode": "// Improves performance of spin-wait loops (alias for REP NOP)", "example": "PAUSE"} {"mnemonic": "clc", "architecture": "x86", "full_name": "Clear Carry Flag", "summary": "Sets the CF flag to 0.", "syntax": "CLC", "encoding": {"format": "Legacy", "hex_opcode": "F8", "visual_parts": [], "binary_pattern": "F8", "bit_positions": "+0"}, "extension": "Base", "operands": [], "description": "Unconditionally clears the Carry Flag (CF) to 0. Only the CF flag is modified; all other flags and CPU state remain unchanged. Available in all modes (real, protected, and 64-bit).", "pseudocode": "CF ← 0", "example": "CLC"} {"mnemonic": "stc", "architecture": "x86", "full_name": "Set Carry Flag", "summary": "Sets the CF flag to 1.", "syntax": "STC", "encoding": {"format": "Legacy", "hex_opcode": "F9", "visual_parts": [], "binary_pattern": "F9", "bit_positions": "+0"}, "extension": "Base", "operands": [], "description": "Unconditionally sets the Carry Flag (CF) to 1. Only the CF flag is modified; all other flags and CPU state remain unchanged. Available in all modes (real, protected, and 64-bit).", "pseudocode": "CF ← 1", "example": "STC"} {"mnemonic": "cmc", "architecture": "x86", "full_name": "Complement Carry Flag", "summary": "Toggles the CF flag.", "syntax": "CMC", "encoding": {"format": "Legacy", "hex_opcode": "F5", "visual_parts": [], "binary_pattern": "F5", "bit_positions": "+0"}, "extension": "Base", "operands": [], "description": "Complements (toggles) the Carry Flag (CF): if CF=0 it becomes 1, and if CF=1 it becomes 0. Only the CF flag is modified; all other flags remain unchanged. Available in all modes (real, protected, and 64-bit).", "pseudocode": "CF ← NOT CF", "example": "CMC"} {"mnemonic": "cld", "architecture": "x86", "full_name": "Clear Direction Flag", "summary": "Sets DF to 0 (String operations increment).", "syntax": "CLD", "encoding": {"format": "Legacy", "hex_opcode": "FC", "visual_parts": [], "binary_pattern": "FC", "bit_positions": "+0"}, "extension": "Base", "operands": [], "description": "Clears the Direction Flag (DF) to 0, causing string instructions (MOVS, SCAS, LODS, STOS, CMPS) to auto-increment the index registers (ESI/EDI or RSI/RDI) rather than decrement them. Only DF is modified; all other flags remain unchanged. Available in all modes.", "pseudocode": "DF ← 0", "example": "CLD"} {"mnemonic": "std", "architecture": "x86", "full_name": "Set Direction Flag", "summary": "Sets DF to 1 (String operations decrement).", "syntax": "STD", "encoding": {"format": "Legacy", "hex_opcode": "FD", "visual_parts": [], "binary_pattern": "FD", "bit_positions": "+0"}, "extension": "Base", "operands": [], "description": "Sets the Direction Flag (DF) to 1, causing string instructions (MOVS, SCAS, LODS, STOS, CMPS) to auto-decrement the index registers (ESI/EDI or RSI/RDI) rather than increment them. Only DF is modified; all other flags remain unchanged. Available in all modes.", "pseudocode": "DF ← 1", "example": "STD"} {"mnemonic": "cli", "architecture": "x86", "full_name": "Clear Interrupt Flag", "summary": "Disables maskable hardware interrupts.", "syntax": "CLI", "encoding": {"format": "Legacy", "hex_opcode": "FA", "visual_parts": [], "binary_pattern": "FA", "bit_positions": "+0"}, "extension": "Base", "operands": [], "description": "Clears the Interrupt Flag (IF) to 0, disabling maskable hardware interrupts (IRQ0-IRQ15) but not non-maskable interrupts (NMI) or exceptions. This instruction is privileged and requires CPL=0; execution in user mode raises a #GP exception. Available in protected and 64-bit modes.", "pseudocode": "IF ← 0 // Requires CPL = 0 (kernel mode)", "example": "CLI"} {"mnemonic": "sti", "architecture": "x86", "full_name": "Set Interrupt Flag", "summary": "Enables maskable hardware interrupts.", "syntax": "STI", "encoding": {"format": "Legacy", "hex_opcode": "FB", "visual_parts": [], "binary_pattern": "FB", "bit_positions": "+0"}, "extension": "Base", "operands": [], "description": "Sets the Interrupt Flag (IF) in EFLAGS, enabling maskable hardware interrupts at the next instruction boundary. This is a privileged instruction that requires CPL=0 (kernel mode). The instruction takes effect after the next instruction executes, allowing one more instruction to complete before interrupts are actually serviced.", "pseudocode": "IF (CPL == 0) THEN IF ← 1; ELSE #GP(0); FI;", "example": "STI"} {"mnemonic": "sahf", "architecture": "x86", "full_name": "Store AH into Flags", "summary": "Loads SF, ZF, AF, PF, and CF from AH.", "syntax": "SAHF", "encoding": {"format": "Legacy", "hex_opcode": "9E", "visual_parts": [], "binary_pattern": "9E", "bit_positions": "+0"}, "extension": "Base", "operands": [], "description": "Loads the lower byte of EFLAGS from the AH register, restoring flags CF, PF, AF, ZF, and SF. The upper bits of EFLAGS (IF, TF, DF, OF, NT, RF, VM, AC, VIF, VIP, ID) are unaffected. This is commonly used to restore previously saved flag state.", "pseudocode": "CF ← AH[0]; PF ← AH[2]; AF ← AH[4]; ZF ← AH[6]; SF ← AH[7];", "example": "SAHF"} {"mnemonic": "lahf", "architecture": "x86", "full_name": "Load Flags into AH", "summary": "Loads bits 0, 2, 4, 6, and 7 of EFLAGS into AH.", "syntax": "LAHF", "encoding": {"format": "Legacy", "hex_opcode": "9F", "visual_parts": [], "binary_pattern": "9F", "bit_positions": "+0"}, "extension": "Base", "operands": [], "description": "Loads the lower byte of EFLAGS into the AH register, extracting flags CF, PF, AF, ZF, and SF. Bits 1, 3, and 5 are set to 0, bit 7 contains SF, and bits 0, 2, 4, 6 contain CF, PF, AF, ZF respectively. This is commonly used to save flag state for later restoration with SAHF.", "pseudocode": "AH ← 0; AH[0] ← CF; AH[2] ← PF; AH[4] ← AF; AH[6] ← ZF; AH[7] ← SF;", "example": "LAHF"} {"mnemonic": "loop", "architecture": "x86", "full_name": "Loop", "summary": "Decrements ECX/RCX and jumps if not zero.", "syntax": "LOOP rel", "encoding": {"format": "Legacy", "hex_opcode": "E2", "visual_parts": [], "binary_pattern": "E2", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "rel", "desc": "Relative branch offset"}], "description": "Decrements the count register (ECX in 32-bit mode, RCX in 64-bit mode) and jumps to the destination if the count is non-zero. Does not set any flags; it only reads the decremented value to determine branch condition. In 64-bit mode, LOOP with a 32-bit operand-size prefix uses ECX (with implicit ZX of RCX).", "pseudocode": "count ← (MODE64 ? RCX : ECX); count ← count - 1; IF (MODE64) RCX ← count; ELSE ECX ← count; IF (count != 0) THEN IP ← IP + sign_extend(rel8); FI;", "example": "LOOP rel"} {"mnemonic": "loope", "architecture": "x86", "full_name": "Loop if Equal", "summary": "Decrements count; jumps if count!=0 and ZF=1.", "syntax": "LOOPE rel", "encoding": {"format": "Legacy", "hex_opcode": "E1", "visual_parts": [], "binary_pattern": "E1", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "rel", "desc": "Relative branch offset"}], "description": "Decrements the count register (ECX/RCX) and jumps to destination if count is non-zero AND the Zero Flag is set. Combines loop counting with a zero-flag condition, useful for scanning arrays until an element matches or count exhausted. No flags are modified by this instruction.", "pseudocode": "count ← (MODE64 ? RCX : ECX); count ← count - 1; IF (MODE64) RCX ← count; ELSE ECX ← count; IF ((count != 0) ∧ (ZF == 1)) THEN IP ← IP + sign_extend(rel8); FI;", "example": "LOOPE rel"} {"mnemonic": "loopne", "architecture": "x86", "full_name": "Loop if Not Equal", "summary": "Decrements count; jumps if count!=0 and ZF=0.", "syntax": "LOOPNE rel", "encoding": {"format": "Legacy", "hex_opcode": "E0", "visual_parts": [], "binary_pattern": "E0", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "rel", "desc": "Relative branch offset"}], "description": "Decrements the count register (ECX/RCX) and jumps to destination if count is non-zero AND the Zero Flag is clear. Combines loop counting with a non-zero-flag condition, useful for scanning arrays until an element matches or count exhausted. No flags are modified by this instruction.", "pseudocode": "count ← (MODE64 ? RCX : ECX); count ← count - 1; IF (MODE64) RCX ← count; ELSE ECX ← count; IF ((count != 0) ∧ (ZF == 0)) THEN IP ← IP + sign_extend(rel8); FI;", "example": "LOOPNE rel"} {"mnemonic": "jecxz", "architecture": "x86", "full_name": "Jump if ECX is Zero", "summary": "Jumps if ECX register is 0.", "syntax": "JECXZ rel", "encoding": {"format": "Legacy", "hex_opcode": "E3", "visual_parts": [], "binary_pattern": "E3", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "rel", "desc": "Relative branch offset"}], "description": "Jumps to the destination if ECX register is zero (or RCX in 64-bit mode when used with REX.W). Unlike LOOP variants, this instruction does not modify any register or flag; it only tests the count value. In 64-bit mode, the non-REX.W form still checks ECX (32-bit).", "pseudocode": "IF (MODE64 ∧ REX.W) THEN IF (RCX == 0) THEN IP ← IP + sign_extend(rel8); FI; ELSE IF (ECX == 0) THEN IP ← IP + sign_extend(rel8); FI; FI;", "example": "JECXZ rel"} {"mnemonic": "enter", "architecture": "x86", "full_name": "Make Stack Frame", "summary": "Creates a stack frame for procedure parameters.", "syntax": "ENTER imm16, imm8", "encoding": {"format": "Legacy", "hex_opcode": "C8", "visual_parts": [], "binary_pattern": "C8", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "imm16", "desc": "16-bit immediate"}, {"name": "src", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Creates a stack frame for a procedure call by pushing RBP/EBP and allocating local variable space, supporting nested frames via the nesting level (imm8). The size (imm16) specifies bytes to allocate; nesting level controls how many prior frame pointers are copied. No flags are affected. High nesting levels serialize execution due to repeated memory operations.", "pseudocode": "push_size ← (OPSIZE == 16 ? 2 : 8); level ← imm8 & 0x1F; size ← imm16; SP ← SP - push_size; [SP] ← BP; frame_ptr ← SP; IF (level > 0) THEN FOR i ← 1 TO level-1 DO BP ← BP - push_size; SP ← SP - push_size; [SP] ← [BP]; OD; SP ← SP - push_size; [SP] ← frame_ptr; FI; BP ← frame_ptr; SP ← SP - size;", "example": "ENTER 0x100, 3"} {"mnemonic": "leave", "architecture": "x86", "full_name": "High Level Procedure Exit", "summary": "Releases stack frame (MOV ESP, EBP; POP EBP).", "syntax": "LEAVE", "encoding": {"format": "Legacy", "hex_opcode": "C9", "visual_parts": [], "binary_pattern": "C9", "bit_positions": "+0"}, "extension": "Base", "operands": [], "description": "Releases the current stack frame by copying the base pointer (EBP/RBP) to the stack pointer (ESP/RSP), then pops the saved base pointer from the stack. This is the inverse of ENTER and restores the caller's frame pointer. No flags are affected. Valid in 16/32/64-bit modes; in 64-bit mode it operates on RBP/RSP.", "pseudocode": "if (OperandSize == 64) {\n RSP ← RBP;\n RBP ← [RSP];\n RSP ← RSP + 8;\n} else if (OperandSize == 32) {\n ESP ← EBP;\n EBP ← [ESP];\n ESP ← ESP + 4;\n} else {\n SP ← BP;\n BP ← [SP];\n SP ← SP + 2;\n}", "example": "LEAVE"} {"mnemonic": "rep movs", "architecture": "x86", "full_name": "Repeat Move String", "summary": "Moves ECX bytes/words from [ESI] to [EDI].", "syntax": "REP MOVS m, m", "encoding": {"format": "Legacy", "hex_opcode": "F3 A4", "visual_parts": [], "binary_pattern": "F3", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "MOVS m", "desc": "Implicit memory for MOVS: ES:[DI] destination, DS:[SI] source"}, {"name": "src", "type": "m", "desc": "Memory operand"}], "description": "Copies ECX/RCX bytes or words from the memory location at DS:[ESI/RSI] to ES:[EDI/RDI], decrementing or incrementing the pointers based on the Direction Flag (DF), and decrementing the counter. Repeats until RCX=0 or an interrupt occurs. No flags are modified by the instruction itself, though DF controls direction. The REP prefix causes automatic looping at the microarchitectural level.", "pseudocode": "while (RCX != 0) {\n if (OperandSize == 8) {\n [RDI] ← [RSI];\n if (DF == 0) { RSI ← RSI + 1; RDI ← RDI + 1; } else { RSI ← RSI - 1; RDI ← RDI - 1; }\n } else if (OperandSize == 16) {\n [RDI] ← [RSI];\n if (DF == 0) { RSI ← RSI + 2; RDI ← RDI + 2; } else { RSI ← RSI - 2; RDI ← RDI - 2; }\n } else {\n [RDI] ← [RSI];\n if (DF == 0) { RSI ← RSI + 4; RDI ← RDI + 4; } else { RSI ← RSI - 4; RDI ← RDI - 4; }\n }\n RCX ← RCX - 1;\n}", "example": "REP MOVS m, [rbp-8]"} {"mnemonic": "rep stos", "architecture": "x86", "full_name": "Repeat Store String", "summary": "Fills [EDI] with AL/AX/EAX for ECX repeats.", "syntax": "REP STOS m", "encoding": {"format": "Legacy", "hex_opcode": "F3 AA", "visual_parts": [], "binary_pattern": "F3", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "STOS m", "desc": "Implicit memory destination for STOS (ES:[DI])"}], "description": "Stores the value in AL/AX/EAX/RAX into memory at ES:[RDI] repeatedly, incrementing or decrementing RDI based on the Direction Flag, and decrementing RCX until the counter reaches zero. No flags are modified. The REP prefix enables automatic looping in hardware.", "pseudocode": "while (RCX != 0) {\n if (OperandSize == 8) {\n [RDI] ← AL;\n if (DF == 0) { RDI ← RDI + 1; } else { RDI ← RDI - 1; }\n } else if (OperandSize == 16) {\n [RDI] ← AX;\n if (DF == 0) { RDI ← RDI + 2; } else { RDI ← RDI - 2; }\n } else if (OperandSize == 32) {\n [RDI] ← EAX;\n if (DF == 0) { RDI ← RDI + 4; } else { RDI ← RDI - 4; }\n } else {\n [RDI] ← RAX;\n if (DF == 0) { RDI ← RDI + 8; } else { RDI ← RDI - 8; }\n }\n RCX ← RCX - 1;\n}", "example": "REP STOS m"} {"mnemonic": "repe cmps", "architecture": "x86", "full_name": "Repeat Compare String Equal", "summary": "Compares [ESI] and [EDI] until mismatch or ECX=0.", "syntax": "REPE CMPS m, m", "encoding": {"format": "Legacy", "hex_opcode": "F3 A6", "visual_parts": [], "binary_pattern": "F3", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "CMPS m", "desc": "Implicit memory for CMPS string compare (DS:[SI] vs ES:[DI])"}, {"name": "src", "type": "m", "desc": "Memory operand"}], "description": "Compares bytes or words at DS:[RSI] with ES:[RDI], setting flags as if by a SUB instruction, and repeats while the Zero Flag is set (operands equal) and RCX > 0. Stops on mismatch, RCX=0, or interrupt. Flags OF, SF, ZF, AF, CF, PF are set based on the comparison result.", "pseudocode": "while (RCX != 0) {\n if (OperandSize == 8) {\n result ← [RSI] - [RDI];\n if (DF == 0) { RSI ← RSI + 1; RDI ← RDI + 1; } else { RSI ← RSI - 1; RDI ← RDI - 1; }\n } else if (OperandSize == 16) {\n result ← [RSI] - [RDI];\n if (DF == 0) { RSI ← RSI + 2; RDI ← RDI + 2; } else { RSI ← RSI - 2; RDI ← RDI - 2; }\n } else {\n result ← [RSI] - [RDI];\n if (DF == 0) { RSI ← RSI + 4; RDI ← RDI + 4; } else { RSI ← RSI - 4; RDI ← RDI - 4; }\n }\n RCX ← RCX - 1;\n OF ← OverflowFlag(result); SF ← SignBit(result); ZF ← (result == 0); AF ← AuxiliaryFlag(result); CF ← CarryFlag(result); PF ← ParityFlag(result);\n if (ZF == 0) break;\n}", "example": "REPE CMPS m, [rbp-8]"} {"mnemonic": "repne scas", "architecture": "x86", "full_name": "Repeat Scan String Not Equal", "summary": "Scans [EDI] for AL/AX/EAX until match or ECX=0.", "syntax": "REPNE SCAS m", "encoding": {"format": "Legacy", "hex_opcode": "F2 AE", "visual_parts": [], "binary_pattern": "F2", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "SCAS m", "desc": "Implicit memory for SCAS (compare accumulator with ES:[DI])"}], "description": "Scans memory at ES:[RDI] for a match with AL/AX/EAX/RAX, setting flags by subtraction, and repeats while the Zero Flag is clear (no match) and RCX > 0. Stops on a match, RCX=0, or interrupt. Flags OF, SF, ZF, AF, CF, PF are set based on the comparison.", "pseudocode": "while (RCX != 0) {\n if (OperandSize == 8) {\n result ← AL - [RDI];\n if (DF == 0) { RDI ← RDI + 1; } else { RDI ← RDI - 1; }\n } else if (OperandSize == 16) {\n result ← AX - [RDI];\n if (DF == 0) { RDI ← RDI + 2; } else { RDI ← RDI - 2; }\n } else if (OperandSize == 32) {\n result ← EAX - [RDI];\n if (DF == 0) { RDI ← RDI + 4; } else { RDI ← RDI - 4; }\n } else {\n result ← RAX - [RDI];\n if (DF == 0) { RDI ← RDI + 8; } else { RDI ← RDI - 8; }\n }\n RCX ← RCX - 1;\n OF ← OverflowFlag(result); SF ← SignBit(result); ZF ← (result == 0); AF ← AuxiliaryFlag(result); CF ← CarryFlag(result); PF ← ParityFlag(result);\n if (ZF == 1) break;\n}", "example": "REPNE SCAS m"} {"mnemonic": "rol", "architecture": "x86", "full_name": "Rotate Left", "summary": "Rotates bits left.", "syntax": "ROL r/m, imm8", "encoding": {"format": "Legacy", "hex_opcode": "C1 /0", "visual_parts": [], "binary_pattern": "C1 | ModRM", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m", "desc": "Register or memory operand"}, {"name": "src", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Rotates the bits in the destination operand left by the number of bit positions specified in the source (immediate or CL register), with the leftmost bit wrapping to the rightmost position. The Carry Flag is set to the bit shifted out; Overflow Flag is set only if the operation rotates by 1 and the sign bit changed. No other flags are affected for rotations > 1.", "pseudocode": "shift_count ← src & ((OperandSize * 8) - 1);\nif (shift_count == 0) { CF ← undefined; OF ← undefined; }\nelse {\n for (i = 0; i < shift_count; i++) {\n CF ← MSB(dest);\n dest ← (dest << 1) | CF;\n }\n if (shift_count == 1) {\n OF ← MSB_before_rotation XOR MSB_after_rotation;\n } else {\n OF ← undefined;\n }\n}", "example": "ROL rbx, 3"} {"mnemonic": "ror", "architecture": "x86", "full_name": "Rotate Right", "summary": "Rotates bits right.", "syntax": "ROR r/m, imm8", "encoding": {"format": "Legacy", "hex_opcode": "C1 /1", "visual_parts": [], "binary_pattern": "C1 | ModRM", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m", "desc": "Register or memory operand"}, {"name": "src", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Rotates the bits in the destination operand right by the number of bit positions specified in the source, with the rightmost bit wrapping to the leftmost position. The Carry Flag is set to the bit shifted out; Overflow Flag is set only if rotating by 1 and the sign bit changed. No other flags are affected for rotations > 1.", "pseudocode": "shift_count ← src & ((OperandSize * 8) - 1);\nif (shift_count == 0) { CF ← undefined; OF ← undefined; }\nelse {\n for (i = 0; i < shift_count; i++) {\n CF ← LSB(dest);\n dest ← (dest >> 1) | (CF << (OperandSize * 8 - 1));\n }\n if (shift_count == 1) {\n OF ← MSB_before_rotation XOR (MSB_before_rotation >> 1);\n } else {\n OF ← undefined;\n }\n}", "example": "ROR rbx, 3"} {"mnemonic": "rcl", "architecture": "x86", "full_name": "Rotate Carry Left", "summary": "Rotates bits left through Carry Flag.", "syntax": "RCL r/m, imm8", "encoding": {"format": "Legacy", "hex_opcode": "C1 /2", "visual_parts": [], "binary_pattern": "C1 | ModRM", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m", "desc": "Register or memory operand"}, {"name": "src", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Rotates the bits in the destination operand left through the Carry Flag by the number of bit positions specified in the source, treating CF as an additional bit position between the MSB and LSB. The CF is set to the bit shifted out. Overflow Flag is set if rotating by 1 and the MSB changed sign. For shifts > 1, OF is undefined. Other flags unchanged.", "pseudocode": "shift_count ← src & ((OperandSize * 8) - 1);\nif (shift_count == 0) { CF ← undefined; OF ← undefined; }\nelse if (shift_count == 1) {\n temp_CF ← MSB(dest);\n dest ← (dest << 1) | CF;\n CF ← temp_CF;\n OF ← MSB_before XOR MSB_after;\n}\nelse {\n for (i = 0; i < shift_count; i++) {\n temp_CF ← MSB(dest);\n dest ← (dest << 1) | CF;\n CF ← temp_CF;\n }\n OF ← undefined;\n}", "example": "RCL rbx, 3"} {"mnemonic": "rcr", "architecture": "x86", "full_name": "Rotate Carry Right", "summary": "Rotates bits right through Carry Flag.", "syntax": "RCR r/m, imm8", "encoding": {"format": "Legacy", "hex_opcode": "C1 /3", "visual_parts": [], "binary_pattern": "C1 | ModRM", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m", "desc": "Register or memory operand"}, {"name": "src", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Rotates the bits of the destination operand right by the number of positions specified in the count operand, with the carry flag inserted at the high end and the low bit shifted into the carry flag. The rotation is through the carry flag, making it part of the rotating chain. All bits including CF participate in a circular rotate. The OF flag is set/cleared based on the most significant bit change on a single-bit rotate; CF is updated to the last bit shifted out.", "pseudocode": "count ← (src == 0) ? 1 : src & 0x1F;\ntemp_cf ← CF;\nfor i ← 0 to count - 1:\n new_cf ← dest & 1;\n dest ← (dest >> 1) | (temp_cf << (width - 1));\n temp_cf ← new_cf;\nCF ← temp_cf;\nif count == 1:\n OF ← MSB_before_rotate XOR CF;", "example": "RCR rbx, 3"} {"mnemonic": "bt", "architecture": "x86", "full_name": "Bit Test", "summary": "Selects a bit and stores it in CF.", "syntax": "BT r/m, r", "encoding": {"format": "Legacy", "hex_opcode": "0F A3", "visual_parts": [], "binary_pattern": "0F | A3", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m", "desc": "Register or memory operand"}, {"name": "src", "type": "r", "desc": "General-purpose register"}], "description": "Tests a bit in the destination operand at the position specified by the source operand and stores the selected bit value in the carry flag. The destination is not modified. The source operand specifies which bit to test (bit position is source value modulo operand size). OF, SF, ZF, AF, PF flags are undefined; only CF is set to the tested bit value.", "pseudocode": "bit_position ← src MOD (width of dest);\nCF ← (dest >> bit_position) & 1;\nOF ← undefined;\nSF ← undefined;\nZF ← undefined;\nAF ← undefined;\nPF ← undefined;", "example": "BT rbx, rax"} {"mnemonic": "bts", "architecture": "x86", "full_name": "Bit Test and Set", "summary": "Stores bit in CF and sets bit to 1.", "syntax": "BTS r/m, r", "encoding": {"format": "Legacy", "hex_opcode": "0F AB", "visual_parts": [], "binary_pattern": "0F | AB", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m", "desc": "Register or memory operand"}, {"name": "src", "type": "r", "desc": "General-purpose register"}], "description": "Tests a bit in the destination operand at the position specified by the source operand, stores the selected bit value in the carry flag, and then sets that bit to 1. The destination is modified atomically with respect to memory accesses. CF receives the original bit value before it is set. OF, SF, ZF, AF, PF flags are undefined.", "pseudocode": "bit_position ← src MOD (width of dest);\nCF ← (dest >> bit_position) & 1;\ndest ← dest | (1 << bit_position);\nOF ← undefined;\nSF ← undefined;\nZF ← undefined;\nAF ← undefined;\nPF ← undefined;", "example": "BTS rbx, rax"} {"mnemonic": "btr", "architecture": "x86", "full_name": "Bit Test and Reset", "summary": "Stores bit in CF and clears bit to 0.", "syntax": "BTR r/m, r", "encoding": {"format": "Legacy", "hex_opcode": "0F B3", "visual_parts": [], "binary_pattern": "0F | B3", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m", "desc": "Register or memory operand"}, {"name": "src", "type": "r", "desc": "General-purpose register"}], "description": "Tests a bit in the destination operand at the position specified by the source operand, stores the selected bit value in the carry flag, and then clears that bit to 0. The destination is modified atomically with respect to memory accesses. CF receives the original bit value before it is cleared. OF, SF, ZF, AF, PF flags are undefined.", "pseudocode": "bit_position ← src MOD (width of dest);\nCF ← (dest >> bit_position) & 1;\ndest ← dest & ~(1 << bit_position);\nOF ← undefined;\nSF ← undefined;\nZF ← undefined;\nAF ← undefined;\nPF ← undefined;", "example": "BTR rbx, rax"} {"mnemonic": "btc", "architecture": "x86", "full_name": "Bit Test and Complement", "summary": "Stores bit in CF and complements the bit.", "syntax": "BTC r/m, r", "encoding": {"format": "Legacy", "hex_opcode": "0F BB", "visual_parts": [], "binary_pattern": "0F | BB", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m", "desc": "Register or memory operand"}, {"name": "src", "type": "r", "desc": "General-purpose register"}], "description": "Tests a bit in the destination operand at the position specified by the source operand, stores the selected bit value in the carry flag, and then complements (inverts) that bit. The destination is modified atomically with respect to memory accesses. CF receives the original bit value before it is complemented. OF, SF, ZF, AF, PF flags are undefined.", "pseudocode": "bit_position ← src MOD (width of dest);\nCF ← (dest >> bit_position) & 1;\ndest ← dest XOR (1 << bit_position);\nOF ← undefined;\nSF ← undefined;\nZF ← undefined;\nAF ← undefined;\nPF ← undefined;", "example": "BTC rbx, rax"} {"mnemonic": "bsf", "architecture": "x86", "full_name": "Bit Scan Forward", "summary": "Scans for LSB set to 1.", "syntax": "BSF r, r/m", "encoding": {"format": "Legacy", "hex_opcode": "0F BC", "visual_parts": [], "binary_pattern": "0F | BC", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r", "desc": "General-purpose register"}, {"name": "src", "type": "r/m", "desc": "Register or memory operand"}], "description": "Scans the source operand from the least significant bit (LSB) forward to locate the first set bit, and stores the bit position in the destination register. If no set bit is found, the zero flag is set and the destination register is undefined. This instruction is commonly used to find the index of the lowest set bit in a value.", "pseudocode": "for i ← 0 to (width - 1):\n if (src >> i) & 1 == 1:\n dest ← i;\n ZF ← 0;\n return;\nZF ← 1;\ndest ← undefined;", "example": "BSF rax, rbx"} {"mnemonic": "bsr", "architecture": "x86", "full_name": "Bit Scan Reverse", "summary": "Scans for MSB set to 1.", "syntax": "BSR r, r/m", "encoding": {"format": "Legacy", "hex_opcode": "0F BD", "visual_parts": [], "binary_pattern": "0F | BD", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r", "desc": "General-purpose register"}, {"name": "src", "type": "r/m", "desc": "Register or memory operand"}], "description": "Scans the source operand from the most significant bit (MSB) backward to locate the first set bit, and stores the bit position in the destination register. If no set bit is found, the zero flag is set and the destination register is undefined. This instruction is commonly used to find the index of the highest set bit in a value.", "pseudocode": "for i ← (width - 1) down to 0:\n if (src >> i) & 1 == 1:\n dest ← i;\n ZF ← 0;\n return;\nZF ← 1;\ndest ← undefined;", "example": "BSR rax, rbx"} {"mnemonic": "lzcnt", "architecture": "x86", "full_name": "Count Leading Zeros", "summary": "Counts number of leading zeros.", "syntax": "LZCNT r, r/m", "encoding": {"format": "VEX", "hex_opcode": "F3 0F BD", "visual_parts": [], "binary_pattern": "F3 | 0F | BD", "bit_positions": "+0 | +1 | +2"}, "extension": "ABM/BMI", "operands": [{"name": "dest", "type": "r", "desc": "General-purpose register"}, {"name": "src", "type": "r/m", "desc": "Register or memory operand"}], "description": "Counts the number of leading zero bits in the source operand and stores the result in the destination register. This is an ABM (Advanced Bit Manipulation) instruction that sets the zero flag if the source is zero (result is operand width) and clears it otherwise. Unlike BSR, this always produces a result without undefined behavior, making it safer for leading zero counting.", "pseudocode": "count ← 0;\nfor i ← (width - 1) down to 0:\n if (src >> i) & 1 == 1:\n break;\n count ← count + 1;\nif src == 0:\n dest ← width;\n ZF ← 1;\nelse:\n dest ← count;\n ZF ← 0;", "example": "LZCNT rax, rbx"} {"mnemonic": "popcnt", "architecture": "x86", "full_name": "Population Count", "summary": "Counts number of bits set to 1.", "syntax": "POPCNT r, r/m", "encoding": {"format": "VEX", "hex_opcode": "F3 0F B8", "visual_parts": [], "binary_pattern": "F3 | 0F | B8", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE4.2", "operands": [{"name": "dest", "type": "r", "desc": "General-purpose register"}, {"name": "src", "type": "r/m", "desc": "Register or memory operand"}], "description": "Counts the number of set bits (1s) in the source operand and stores the result in the destination register. This instruction requires the SSE4.2 extension and is available in 16/32/64-bit variants. No flags are affected by this instruction, making it useful for bit-counting operations in high-performance code.", "pseudocode": "dest ← count_set_bits(src)", "example": "POPCNT rax, rbx"} {"mnemonic": "xlat", "architecture": "x86", "full_name": "Table Look-up Translation", "summary": "Replaces AL with byte from table at [EBX+AL].", "syntax": "XLAT m8", "encoding": {"format": "Legacy", "hex_opcode": "D7", "visual_parts": [], "binary_pattern": "D7", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "m8", "desc": "8-bit memory operand"}], "description": "Translates the byte in AL using a table in memory located at address EBX + AL (or RBX + AL in 64-bit mode), replacing AL with the byte from the table. The base address is determined by EBX/RBX, and the offset is the current value of AL. No flags are affected. This instruction is useful for character translation and lookup tables.", "pseudocode": "AL ← [EBX + zero_extend(AL)]", "example": "XLAT [rbp-1]"} {"mnemonic": "pushf", "architecture": "x86", "full_name": "Push Flags", "summary": "Pushes EFLAGS onto stack.", "syntax": "PUSHF", "encoding": {"format": "Legacy", "hex_opcode": "9C", "visual_parts": [], "binary_pattern": "9C", "bit_positions": "+0"}, "extension": "Base", "operands": [], "description": "Pushes the EFLAGS register (or FLAGS register in 16-bit mode) onto the stack, decrementing the stack pointer. In 64-bit mode, PUSHF pushes the lower 32 bits of RFLAGS. All flag states are preserved on the stack. This instruction is commonly used to save the current processor state before modifying flags.", "pseudocode": "ESP ← ESP - 4; [ESP] ← EFLAGS", "example": "PUSHF"} {"mnemonic": "popf", "architecture": "x86", "full_name": "Pop Flags", "summary": "Pops stack into EFLAGS.", "syntax": "POPF", "encoding": {"format": "Legacy", "hex_opcode": "9D", "visual_parts": [], "binary_pattern": "9D", "bit_positions": "+0"}, "extension": "Base", "operands": [], "description": "Pops a value from the stack into the EFLAGS register (or FLAGS in 16-bit mode), restoring previously saved flag states. This instruction restores OF, SF, ZF, AF, PF, and CF flags from the popped value. POPF also increments the stack pointer. Certain flags may be restricted based on the current privilege level.", "pseudocode": "EFLAGS ← [ESP]; ESP ← ESP + 4", "example": "POPF"} {"mnemonic": "pusha", "architecture": "x86", "full_name": "Push All General-Purpose Registers", "summary": "Pushes AX, CX, DX, BX, SP, BP, SI, DI (Invalid in 64-bit).", "syntax": "PUSHA", "encoding": {"format": "Legacy", "hex_opcode": "60", "visual_parts": [], "binary_pattern": "60", "bit_positions": "+0"}, "extension": "Base (32-bit only)", "operands": [], "description": "Pushes all eight general-purpose 16-bit or 32-bit registers (AX/EAX, CX/ECX, DX/EDX, BX/EBX, SP/ESP, BP/EBP, SI/ESI, DI/EDI) onto the stack in that order. The SP/ESP value pushed is the value before the first push. This instruction is invalid in 64-bit mode and is primarily a legacy instruction. No flags are affected.", "pseudocode": "temp ← SP; SP ← SP - 16; [SP+0] ← AX; [SP+2] ← CX; [SP+4] ← DX; [SP+6] ← BX; [SP+8] ← temp; [SP+10] ← BP; [SP+12] ← SI; [SP+14] ← DI", "example": "PUSHA"} {"mnemonic": "popa", "architecture": "x86", "full_name": "Pop All General-Purpose Registers", "summary": "Pops into DI, SI, BP, SP, BX, DX, CX, AX (Invalid in 64-bit).", "syntax": "POPA", "encoding": {"format": "Legacy", "hex_opcode": "61", "visual_parts": [], "binary_pattern": "61", "bit_positions": "+0"}, "extension": "Base (32-bit only)", "operands": [], "description": "Pops eight values from the stack into the general-purpose registers in reverse order of PUSHA (DI, SI, BP, SP, BX, DX, CX, AX), restoring a previously saved register state. The SP/ESP value is automatically popped and discarded. This instruction is invalid in 64-bit mode. No flags are affected.", "pseudocode": "DI ← [SP+0]; SI ← [SP+2]; BP ← [SP+4]; SP ← SP + 6; BX ← [SP+0]; DX ← [SP+2]; CX ← [SP+4]; AX ← [SP+6]; SP ← SP + 8", "example": "POPA"} {"mnemonic": "bound", "architecture": "x86", "full_name": "Check Array Index Against Bounds", "summary": "Checks if operand is within bounds defined in memory.", "syntax": "BOUND r, m", "encoding": {"format": "Legacy", "hex_opcode": "62", "visual_parts": [], "binary_pattern": "62", "bit_positions": "+0"}, "extension": "Base (32-bit only)", "operands": [{"name": "dest", "type": "r", "desc": "General-purpose register"}, {"name": "src", "type": "m", "desc": "Memory operand"}], "description": "Checks whether the signed value in the register operand is within the bounds specified by two signed integers in memory (lower bound at m, upper bound at m+size). If the value is outside the bounds, a #BR (BOUND Range Exceeded) exception is generated. This instruction is invalid in 64-bit mode. No flags are affected if no exception occurs.", "pseudocode": "lower ← [mem]; upper ← [mem + operand_size]; if (register < lower || register > upper) { raise BR_exception }", "example": "BOUND rax, [rbp-8]"} {"mnemonic": "aaa", "architecture": "x86", "full_name": "ASCII Adjust After Addition", "summary": "Adjusts AL after addition for unpacked BCD.", "syntax": "AAA", "encoding": {"format": "Legacy", "hex_opcode": "37", "visual_parts": [], "binary_pattern": "37", "bit_positions": "+0"}, "extension": "Base (Legacy)", "operands": [], "description": "Adjusts AL after addition of two unpacked BCD (Binary Coded Decimal) digits, correcting the result to ensure valid BCD. If the lower nibble of AL is greater than 9 or the AF flag is set, AL is adjusted by adding 6 to the lower nibble and 1 is added to AH. The AF and CF flags are set or cleared accordingly. This instruction is invalid in 64-bit mode and is primarily legacy.", "pseudocode": "if ((AL & 0x0F) > 9 || AF == 1) { AL ← (AL + 6) & 0xFF; AH ← AH + 1; AF ← 1; CF ← 1 } else { AF ← 0; CF ← 0 }; AL ← AL & 0x0F", "example": "AAA"} {"mnemonic": "aas", "architecture": "x86", "full_name": "ASCII Adjust After Subtraction", "summary": "Adjusts AL after subtraction for unpacked BCD.", "syntax": "AAS", "encoding": {"format": "Legacy", "hex_opcode": "3F", "visual_parts": [], "binary_pattern": "3F", "bit_positions": "+0"}, "extension": "Base (Legacy)", "operands": [], "description": "Adjusts the value in AL after a subtraction operation to make it a valid unpacked BCD digit (0-9 in the lower nibble). If the lower nibble of AL is greater than 9 or the auxiliary carry flag is set, AL is decremented by 6 and AH is decremented by 1; otherwise no adjustment occurs. Sets or clears AF and CF based on whether an adjustment was made; other flags are undefined.", "pseudocode": "if ((AL & 0x0F) > 9) || (AF == 1) {\n AL ← AL - 6;\n AH ← AH - 1;\n AF ← 1;\n CF ← 1;\n} else {\n AF ← 0;\n CF ← 0;\n}\nAL ← AL & 0x0F;", "example": "AAS"} {"mnemonic": "daa", "architecture": "x86", "full_name": "Decimal Adjust After Addition", "summary": "Adjusts AL after addition for packed BCD.", "syntax": "DAA", "encoding": {"format": "Legacy", "hex_opcode": "27", "visual_parts": [], "binary_pattern": "27", "bit_positions": "+0"}, "extension": "Base (Legacy)", "operands": [], "description": "Adjusts AL after addition of two packed BCD values. If the lower nibble exceeds 9 or AF is set, adds 6 to AL; if the upper nibble then exceeds 9 or CF is set, adds 0x60 to AL. Sets CF and AF as needed; OF is undefined; SF, ZF, PF are computed on the result.", "pseudocode": "old_AL ← AL;\nif ((AL & 0x0F) > 9) || (AF == 1) {\n AL ← AL + 6;\n AF ← 1;\n} else {\n AF ← 0;\n}\nif (old_AL > 0x99) || (CF == 1) {\n AL ← AL + 0x60;\n CF ← 1;\n} else {\n CF ← 0;\n}\nZF ← (AL == 0);\nSF ← (AL[7] == 1);\nPF ← parity(AL);", "example": "DAA"} {"mnemonic": "das", "architecture": "x86", "full_name": "Decimal Adjust After Subtraction", "summary": "Adjusts AL after subtraction for packed BCD.", "syntax": "DAS", "encoding": {"format": "Legacy", "hex_opcode": "2F", "visual_parts": [], "binary_pattern": "2F", "bit_positions": "+0"}, "extension": "Base (Legacy)", "operands": [], "description": "Adjusts AL after subtraction of two packed BCD values. If the lower nibble exceeds 9 or AF is set, subtracts 6 from AL; if the upper nibble then exceeds 9 or CF is set, subtracts 0x60 from AL. Sets CF and AF as needed; OF is undefined; SF, ZF, PF are computed on the result.", "pseudocode": "old_AL ← AL;\nif ((AL & 0x0F) > 9) || (AF == 1) {\n AL ← AL - 6;\n AF ← 1;\n} else {\n AF ← 0;\n}\nif (old_AL > 0x99) || (CF == 1) {\n AL ← AL - 0x60;\n CF ← 1;\n} else {\n CF ← 0;\n}\nZF ← (AL == 0);\nSF ← (AL[7] == 1);\nPF ← parity(AL);", "example": "DAS"} {"mnemonic": "aam", "architecture": "x86", "full_name": "ASCII Adjust After Multiply", "summary": "Adjusts AX after multiply for unpacked BCD.", "syntax": "AAM imm8", "encoding": {"format": "Legacy", "hex_opcode": "D4", "visual_parts": [], "binary_pattern": "D4", "bit_positions": "+0"}, "extension": "Base (Legacy)", "operands": [{"name": "dest", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Adjusts AX after a multiply operation on unpacked BCD operands (imm8 specifies the radix, typically 10). Divides AL by the immediate operand, placing the quotient in AH and remainder in AL. Sets SF, ZF, PF based on the result in AL; CF and OF are undefined; AF is undefined.", "pseudocode": "AH ← AL / imm8;\nAL ← AL % imm8;\nZF ← (AL == 0);\nSF ← (AL[7] == 1);\nPF ← parity(AL);", "example": "AAM 3"} {"mnemonic": "aad", "architecture": "x86", "full_name": "ASCII Adjust Before Division", "summary": "Adjusts AX before division for unpacked BCD.", "syntax": "AAD imm8", "encoding": {"format": "Legacy", "hex_opcode": "D5", "visual_parts": [], "binary_pattern": "D5", "bit_positions": "+0"}, "extension": "Base (Legacy)", "operands": [{"name": "dest", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Adjusts AX before a division operation on unpacked BCD operands (imm8 specifies the radix, typically 10). Multiplies AH by the immediate operand and adds to AL, placing the result in AL with AH cleared to 0. Sets SF, ZF, PF based on the result; CF and OF are undefined; AF is undefined.", "pseudocode": "AL ← (AH * imm8) + AL;\nAH ← 0;\nZF ← (AL == 0);\nSF ← (AL[7] == 1);\nPF ← parity(AL);", "example": "AAD 3"} {"mnemonic": "cbw", "architecture": "x86", "full_name": "Convert Byte to Word", "summary": "Sign-extends AL into AX.", "syntax": "CBW", "encoding": {"format": "Legacy", "hex_opcode": "98", "visual_parts": [], "binary_pattern": "98", "bit_positions": "+0"}, "extension": "Base", "operands": [], "description": "Sign-extends the byte value in AL to a word in AX by copying bit 7 of AL to all bits 8-15 of AX. No flags are affected. In 64-bit mode, only the lower word of RAX is modified.", "pseudocode": "AX ← sign_extend_byte_to_word(AL);", "example": "CBW"} {"mnemonic": "cwd", "architecture": "x86", "full_name": "Convert Word to Doubleword", "summary": "Sign-extends AX into DX:AX.", "syntax": "CWD", "encoding": {"format": "Legacy", "hex_opcode": "99", "visual_parts": [], "binary_pattern": "99", "bit_positions": "+0"}, "extension": "Base", "operands": [], "description": "Sign-extends the word value in AX to a doubleword across DX:AX by copying bit 15 of AX to all bits of DX. No flags are affected. In 64-bit mode, this is typically replaced by CDQE or CQO for larger sign extensions.", "pseudocode": "DX ← (AX[15] == 1) ? 0xFFFF : 0x0000;", "example": "CWD"} {"mnemonic": "wait", "architecture": "x86", "full_name": "Wait", "summary": "Wait for FPU (same as FWAIT).", "syntax": "WAIT", "encoding": {"format": "Legacy", "hex_opcode": "9B", "visual_parts": [], "binary_pattern": "9B", "bit_positions": "+0"}, "extension": "Base", "operands": [], "description": "Waits for pending FPU operations to complete by checking the FPU busy flag; execution stalls until the FPU signals completion. Commonly used to synchronize between x87 floating-point and integer units. No flags are modified.", "pseudocode": "while (FPU_busy_flag == 1) {\n stall();\n}", "example": "WAIT"} {"mnemonic": "ldtilecfg", "architecture": "x86", "full_name": "Load Tile Configuration", "summary": "Loads AMX tile configuration from memory.", "syntax": "LDTILECFG m512", "encoding": {"format": "VEX", "hex_opcode": "VEX.128.NP.0F38.W0 49 !(11):000:bbb", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AMX-TILE", "operands": [{"name": "dest", "type": "m512", "desc": "512-bit memory operand"}], "description": "Loads a 512-bit tile configuration structure from memory into the AMX tile configuration state, enabling subsequent AMX tile operations. The memory operand must be 64-byte aligned. This instruction is a serializing operation that flushes pending tile operations and updates the internal tile geometry metadata (rows and columns for each tile). Requires AMX-TILE extension support; raises #UD if AMX is not enabled or memory is misaligned.", "pseudocode": "tilecfg_state ← load_512bits_from_memory(m512); tile_config_valid ← 1;", "example": "LDTILECFG [rbp-64]"} {"mnemonic": "sttilecfg", "architecture": "x86", "full_name": "Store Tile Configuration", "summary": "Stores AMX tile configuration to memory.", "syntax": "STTILECFG m512", "encoding": {"format": "VEX", "hex_opcode": "VEX.128.66.0F38.W0 49 !(11):000:bbb", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AMX-TILE", "operands": [{"name": "dest", "type": "m512", "desc": "512-bit memory operand"}], "description": "Stores the current AMX tile configuration state to a 512-bit memory location. Writes the internal tile dimensions and configuration metadata that was previously loaded via LDTILECFG. The memory operand must be 64-byte aligned. This is a serializing operation that ensures all pending tile operations complete before the store. Requires AMX-TILE extension support.", "pseudocode": "m512 ← store_512bits_to_memory(tilecfg_state);", "example": "STTILECFG [rbp-64]"} {"mnemonic": "tileloadd", "architecture": "x86", "full_name": "Load Tile Data", "summary": "Loads data into an AMX tile register.", "syntax": "TILELOADD tmm1, m", "encoding": {"format": "VEX", "hex_opcode": "VEX.128.F2.0F38.W0 4B !(11):rrr:100", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AMX-TILE", "operands": [{"name": "dest", "type": "tmm1", "desc": "AMX tile register"}, {"name": "src", "type": "m", "desc": "Memory operand"}], "description": "Loads a rectangular block of 32-bit doubleword elements from memory into an AMX tile register according to the current tile configuration. The memory layout is row-major; the memory address is typically formed from a base register and a stride register. This is a non-faulting instruction that respects the tile row/column dimensions set by LDTILECFG. Requires AMX-TILE extension and valid tile configuration.", "pseudocode": "stride ← (addressing mode determines memory stride); rows ← tilecfg_state.rows[tmm1]; cols ← tilecfg_state.cols[tmm1]; for (i = 0; i < rows; i++) { for (j = 0; j < cols; j++) { tmm1[i, j] ← m[base + i*stride + j*4]; } }", "example": "TILELOADD tmm1, [rbp-8]"} {"mnemonic": "tilestored", "architecture": "x86", "full_name": "Store Tile Data", "summary": "Stores data from an AMX tile register to memory.", "syntax": "TILESTORED m, tmm1", "encoding": {"format": "VEX", "hex_opcode": "VEX.128.F3.0F38.W0 4B !(11):rrr:100", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AMX-TILE", "operands": [{"name": "dest", "type": "m", "desc": "Memory operand"}, {"name": "src", "type": "tmm1", "desc": "AMX tile register"}], "description": "Stores a rectangular block of 32-bit doubleword elements from an AMX tile register to memory in row-major order, respecting the tile configuration dimensions. The destination memory address is typically formed from a base register and a stride register. This is a non-faulting instruction that outputs only the configured rows and columns. Requires AMX-TILE extension and valid tile configuration.", "pseudocode": "stride ← (addressing mode determines memory stride); rows ← tilecfg_state.rows[tmm_src]; cols ← tilecfg_state.cols[tmm_src]; for (i = 0; i < rows; i++) { for (j = 0; j < cols; j++) { m[base + i*stride + j*4] ← tmm_src[i, j]; } }", "example": "TILESTORED [rbp-8], tmm1"} {"mnemonic": "tilezero", "architecture": "x86", "full_name": "Zero Tile", "summary": "Clears an AMX tile register.", "syntax": "TILEZERO tmm1", "encoding": {"format": "VEX", "hex_opcode": "VEX.128.F2.0F38.W0 49 11:rrr:000", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AMX-TILE", "operands": [{"name": "dest", "type": "tmm1", "desc": "AMX tile register"}], "description": "Clears all elements of an AMX tile register to zero. The tile retains its configured dimensions; only the data elements are zeroed. This instruction is a common initialization step for accumulator tiles before performing matrix operations. Requires AMX-TILE extension and valid tile configuration. No flags are affected.", "pseudocode": "rows ← tilecfg_state.rows[tmm1]; cols ← tilecfg_state.cols[tmm1]; for (i = 0; i < rows; i++) { for (j = 0; j < cols; j++) { tmm1[i, j] ← 0; } }", "example": "TILEZERO tmm1"} {"mnemonic": "tdpbssd", "architecture": "x86", "full_name": "Tile Dot Product Byte Signed Signed Doubleword", "summary": "Matrix multiply (Signed Int8 * Signed Int8) accumulating to Int32.", "syntax": "TDPBSSD tmm1, tmm2, tmm3", "encoding": {"format": "VEX", "hex_opcode": "VEX.128.F2.0F38.W0 5E 11:rrr:bbb", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AMX-INT8", "operands": [{"name": "dest", "type": "tmm1", "desc": "AMX tile register"}, {"name": "src1", "type": "tmm2", "desc": "AMX tile register"}, {"name": "src2", "type": "tmm3", "desc": "AMX tile register"}], "description": "Performs a tile matrix multiply-accumulate operation: multiplies signed 8-bit elements from two source tiles and accumulates the 32-bit signed products into a 32-bit destination tile. Computes dest[i,k] += sum(src1[i,j] * src2[j,k]) for all j over the configured row/column ranges. The operation respects the tile configuration for all three operands. Requires AMX-INT8 extension. No EFLAGS are modified.", "pseudocode": "rows_dest ← tilecfg_state.rows[tmm1]; cols_dest ← tilecfg_state.cols[tmm1]; cols_src1 ← tilecfg_state.cols[tmm2]; for (i = 0; i < rows_dest; i++) { for (k = 0; k < cols_dest; k++) { for (j = 0; j < cols_src1; j++) { product ← (int32_t)(int8_t)src1[i,j] * (int32_t)(int8_t)src2[j,k]; tmm1[i,k] ← (int32_t)tmm1[i,k] + product; } } }", "example": "TDPBSSD tmm1, tmm2, tmm3"} {"mnemonic": "tdpbsud", "architecture": "x86", "full_name": "Tile Dot Product Byte Signed Unsigned Doubleword", "summary": "Matrix multiply (Signed * Unsigned) accumulating to Int32.", "syntax": "TDPBSUD tmm1, tmm2, tmm3", "encoding": {"format": "VEX", "hex_opcode": "VEX.128.F3.0F38.W0 5E 11:rrr:bbb", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AMX-INT8", "operands": [{"name": "dest", "type": "tmm1", "desc": "AMX tile register"}, {"name": "src1", "type": "tmm2", "desc": "AMX tile register"}, {"name": "src2", "type": "tmm3", "desc": "AMX tile register"}], "description": "Performs a tile matrix multiply-accumulate operation: multiplies signed 8-bit elements from the first source by unsigned 8-bit elements from the second source, accumulating 32-bit signed results into the destination tile. Computes dest[i,k] += sum(src1[i,j] * src2[j,k]) for all j, with src1 treated as signed and src2 as unsigned. Respects tile configuration dimensions. Requires AMX-INT8 extension. No EFLAGS are modified.", "pseudocode": "rows_dest ← tilecfg_state.rows[tmm1]; cols_dest ← tilecfg_state.cols[tmm1]; cols_src1 ← tilecfg_state.cols[tmm2]; for (i = 0; i < rows_dest; i++) { for (k = 0; k < cols_dest; k++) { for (j = 0; j < cols_src1; j++) { product ← (int32_t)(int8_t)src1[i,j] * (int32_t)(uint8_t)src2[j,k]; tmm1[i,k] ← (int32_t)tmm1[i,k] + product; } } }", "example": "TDPBSUD tmm1, tmm2, tmm3"} {"mnemonic": "tdpbf16ps", "architecture": "x86", "full_name": "Tile Dot Product BFloat16 Packed Single", "summary": "Matrix multiply (BFloat16) accumulating to Float32.", "syntax": "TDPBF16PS tmm1, tmm2, tmm3", "encoding": {"format": "VEX", "hex_opcode": "VEX.128.F3.0F38.W0 5C 11:rrr:bbb", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AMX-BF16", "operands": [{"name": "dest", "type": "tmm1", "desc": "AMX tile register"}, {"name": "src1", "type": "tmm2", "desc": "AMX tile register"}, {"name": "src2", "type": "tmm3", "desc": "AMX tile register"}], "description": "Performs a tile matrix multiply-accumulate operation on BFloat16 (16-bit brain float) elements, accumulating 32-bit floating-point results into the destination tile. Computes dest[i,k] += sum(src1[i,j] * src2[j,k]) for all j using BFloat16 multiplication and single-precision floating-point accumulation. Respects tile configuration for row/column dimensions. Requires AMX-BF16 extension. No EFLAGS are modified.", "pseudocode": "rows_dest ← tilecfg_state.rows[tmm1]; cols_dest ← tilecfg_state.cols[tmm1]; cols_src1 ← tilecfg_state.cols[tmm2]; for (i = 0; i < rows_dest; i++) { for (k = 0; k < cols_dest; k++) { for (j = 0; j < cols_src1; j++) { product ← convert_bf16_to_fp32(src1[i,j]) * convert_bf16_to_fp32(src2[j,k]); tmm1[i,k] ← (float32)tmm1[i,k] + product; } } }", "example": "TDPBF16PS tmm1, tmm2, tmm3"} {"mnemonic": "endbr64", "architecture": "x86", "full_name": "End Branch 64-bit", "summary": "Marker instruction for Indirect Branch Tracking (IBT).", "syntax": "ENDBR64", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F 1E FA", "visual_parts": [], "binary_pattern": "F3 | 0F | 1E | FA", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "CET-IBT", "operands": [], "description": "End Branch 64-bit marker for Control Flow Enforcement Technology (CET) Indirect Branch Tracking. This is a NOP-like instruction that marks valid target points for indirect branches in 64-bit mode; it is consumed by hardware when CET-IBT is enabled and causes a control-flow exception (#CP) if an indirect branch lands on a non-ENDBR64/ENDBR32 location. No flags are affected. Requires CET-IBT capability.", "pseudocode": "// Marker instruction for Indirect Branch Tracking (IBT)", "example": "ENDBR64"} {"mnemonic": "endbr32", "architecture": "x86", "full_name": "End Branch 32-bit", "summary": "Marker instruction for Indirect Branch Tracking (IBT).", "syntax": "ENDBR32", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F 1E FB", "visual_parts": [], "binary_pattern": "F3 | 0F | 1E | FB", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "CET-IBT", "operands": [], "description": "End Branch 32-bit marker for Control Flow Enforcement Technology (CET) Indirect Branch Tracking. Similar to ENDBR64, this marks valid indirect branch targets in 32-bit or compat mode; enforces CET-IBT policy when enabled. No flags are affected. Requires CET-IBT capability.", "pseudocode": "// Marker instruction for Indirect Branch Tracking (IBT)", "example": "ENDBR32"} {"mnemonic": "rdsspq", "architecture": "x86", "full_name": "Read Shadow Stack Pointer (Quadword)", "summary": "Reads the current shadow stack pointer into a register.", "syntax": "RDSSPQ r64", "encoding": {"format": "Legacy", "hex_opcode": "F3 REX.W 0F 1E /1", "visual_parts": [], "binary_pattern": "F3 | 0F | 1E | ModRM", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "CET-SS", "operands": [{"name": "dest", "type": "r64", "desc": "64-bit general-purpose register (e.g. RAX)"}], "description": "Read Shadow Stack Pointer into a 64-bit register. Reads the current shadow stack pointer (SSP) maintained by CET-SS hardware and stores it in the destination register. No flags are affected. Requires CET-SS (Control Flow Enforcement Technology-Shadow Stack) capability; 64-bit mode only.", "pseudocode": "dest ← SSP", "example": "RDSSPQ rax"} {"mnemonic": "incsspq", "architecture": "x86", "full_name": "Increment Shadow Stack Pointer (Quadword)", "summary": "Adjusts the shadow stack pointer.", "syntax": "INCSSPQ r64", "encoding": {"format": "Legacy", "hex_opcode": "F3 REX.W 0F AE /5", "visual_parts": [], "binary_pattern": "F3 | 0F | AE | ModRM", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "CET-SS", "operands": [{"name": "dest", "type": "r64", "desc": "64-bit general-purpose register (e.g. RAX)"}], "description": "Increment Shadow Stack Pointer by the value in a 64-bit register. Adjusts the shadow stack pointer (SSP) forward by the count specified in the source register, typically used to skip multiple shadow stack entries or adjust SSP during context switching. No flags are affected. Requires CET-SS capability; 64-bit mode only.", "pseudocode": "SSP ← SSP + src", "example": "INCSSPQ rax"} {"mnemonic": "rstorssp", "architecture": "x86", "full_name": "Restore Shadow Stack Pointer", "summary": "Restores SSP from memory token.", "syntax": "RSTORSSP m64", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F 01 /5", "visual_parts": [], "binary_pattern": "F3 | 0F | 01 | ModRM", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "CET-SS", "operands": [{"name": "dest", "type": "m64", "desc": "64-bit memory operand (quadword)"}], "description": "Restore Shadow Stack Pointer from a 64-bit memory token. Reads a restoration token from memory and updates the shadow stack pointer (SSP); validates the token format and raises #CP if invalid. Used during context restoration or privilege transitions with CET-SS. No flags are affected. Requires CET-SS capability; 64-bit mode only.", "pseudocode": "token ← [src]\n// Validate token format; if invalid raise #CP\nSSP ← token", "example": "RSTORSSP [rbp-8]"} {"mnemonic": "saveprevssp", "architecture": "x86", "full_name": "Save Previous Shadow Stack Pointer", "summary": "Saves the previous SSP to the shadow stack token.", "syntax": "SAVEPREVSSP", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F 01 EA", "visual_parts": [], "binary_pattern": "F3 | 0F | 01 | EA", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "CET-SS", "operands": [], "description": "Save the previous Shadow Stack Pointer to the top of the shadow stack. Writes the previous SSP value (stored in a CET control register) as a token to the current shadow stack location and typically increments SSP. Used to preserve SSP across context switches or privilege transitions. No flags are affected. Requires CET-SS capability; 64-bit mode only.", "pseudocode": "[SSP] ← previous_SSP\nSSP ← SSP + 8", "example": "SAVEPREVSSP"} {"mnemonic": "clwb", "architecture": "x86", "full_name": "Cache Line Write Back", "summary": "Writes back modified cache line without flushing (Persistent Memory).", "syntax": "CLWB m8", "encoding": {"format": "Legacy", "hex_opcode": "66 0F AE !(11):110:bbb", "visual_parts": [], "binary_pattern": "66 | 0F | AE | ModRM", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "CLWB", "operands": [{"name": "dest", "type": "m8", "desc": "8-bit memory operand"}], "description": "Cache Line Write Back to memory without invalidation. Writes back a modified cache line to memory (coherent with other agents) but does not invalidate it from the cache hierarchy; optimized for persistent memory workloads. No flags are affected. Serialization and memory ordering depend on surrounding instructions. Requires CLWB capability.", "pseudocode": "// Write back cache line containing [m8] to memory\n// Cache line remains in cache after writeback\nwrite_back_cache_line(address(m8))", "example": "CLWB [rbp-1]"} {"mnemonic": "clflushopt", "architecture": "x86", "full_name": "Optimized Cache Line Flush", "summary": "Optimized version of CLFLUSH (Higher throughput).", "syntax": "CLFLUSHOPT m8", "encoding": {"format": "Legacy", "hex_opcode": "NFx 66 0F AE /7", "visual_parts": [], "binary_pattern": "66 | 0F | AE | ModRM", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "CLFLUSHOPT", "operands": [{"name": "dest", "type": "m8", "desc": "8-bit memory operand"}], "description": "Optimized Cache Line Flush with higher throughput than CLFLUSH. Invalidates a cache line from all levels of the cache hierarchy and writes it back to memory if modified. No flags are affected. Provides better pipelining and throughput characteristics than legacy CLFLUSH. Requires CLFLUSHOPT capability.", "pseudocode": "// Invalidate and writeback cache line containing [m8]\ninvalidate_writeback_cache_line(address(m8))", "example": "CLFLUSHOPT [rbp-1]"} {"mnemonic": "cldemote", "architecture": "x86", "full_name": "Cache Line Demote", "summary": "Hints to move cache line to lower cache level.", "syntax": "CLDEMOTE m8", "encoding": {"format": "Legacy", "hex_opcode": "NP 0F 1C /0", "visual_parts": [], "binary_pattern": "0F | 1C | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "CLDEMOTE", "operands": [{"name": "dest", "type": "m8", "desc": "8-bit memory operand"}], "description": "Provides a hint to demote a cache line to a lower cache level (L2 or L3) without invalidating it. The instruction has no architectural effect on cache state and does not modify flags; it is a performance hint that may improve system throughput by reducing cache coherency traffic. Requires CLDEMOTE instruction extension; available in 64-bit mode.", "pseudocode": "// Hint to demote cache line at m8\n// No architectural registers or flags are modified\nDemoteHint([m8])", "example": "CLDEMOTE [rbp-1]"} {"mnemonic": "movdiri", "architecture": "x86", "full_name": "Move Direct Store Integer", "summary": "Moves 32/64-bit data avoiding cache pollution (Direct IO).", "syntax": "MOVDIRI m, r", "encoding": {"format": "Legacy", "hex_opcode": "NP 0F 38 F9 /r", "visual_parts": [], "binary_pattern": "0F | 38 | F9", "bit_positions": "+0 | +1 | +2"}, "extension": "MOVDIRI", "operands": [{"name": "dest", "type": "m", "desc": "Memory operand"}, {"name": "src", "type": "r", "desc": "General-purpose register"}], "description": "Moves 32-bit or 64-bit data from a general-purpose register directly to memory, bypassing the cache hierarchy to avoid cache pollution (Direct I/O store). The instruction writes directly to memory without allocating or updating cache lines. No flags are affected; requires MOVDIRI instruction extension and is intended for low-latency memory-mapped I/O operations.", "pseudocode": "if (src is r32) {\n [dest] ← src[31:0];\n} else if (src is r64) {\n [dest] ← src[63:0];\n}\n// No cache line allocated; bypasses cache hierarchy\n// No flags modified", "example": "MOVDIRI [rbp-8], rax"} {"mnemonic": "movdir64b", "architecture": "x86", "full_name": "Move Direct Store 64-Bytes", "summary": "Atomically moves 64-byte block avoiding cache pollution.", "syntax": "MOVDIR64B m512, m512", "encoding": {"format": "Legacy", "hex_opcode": "66 0F 38 F8", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | F8", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "MOVDIR64B", "operands": [{"name": "dest", "type": "m512", "desc": "512-bit memory operand"}, {"name": "src", "type": "m512", "desc": "512-bit memory operand"}], "description": "Atomically moves a 64-byte block from memory to memory using a Direct I/O store, bypassing the cache hierarchy without allocating cache lines. The operation is atomic with respect to other MOVDIR64B operations and ensures the destination cache line is not allocated. No flags are affected; requires MOVDIR64B extension and 64-byte alignment of both operands.", "pseudocode": "// Atomically copy 64 bytes from src to dest, bypassing cache\nfor (i = 0; i < 64; i++) {\n [dest + i] ← [src + i];\n}\n// Destination cache line not allocated\n// Operation is atomic and serializing\n// No flags modified", "example": "MOVDIR64B [rbp-64], [rbp-64]"} {"mnemonic": "xbegin", "architecture": "x86", "full_name": "Transaction Begin", "summary": "Specifies start of Restricted Transactional Memory region.", "syntax": "XBEGIN rel", "encoding": {"format": "Legacy", "hex_opcode": "C7 F8", "visual_parts": [], "binary_pattern": "C7 | F8", "bit_positions": "+0 | +1"}, "extension": "RTM (TSX)", "operands": [{"name": "dest", "type": "rel", "desc": "Relative branch offset"}], "description": "Specifies the entry point into a Restricted Transactional Memory (RTM) region; execution begins optimistically buffering memory updates. If the transaction aborts, execution branches to the fallback address (rel32); if successful, the transaction commits on XEND. The ZF flag is cleared on successful entry and set on abort; EAX contains a non-zero abort code if a transaction fails.", "pseudocode": "if (RTM_EntryAllowed) {\n RTM_TransactionActive ← 1;\n ZF ← 0;\n // Speculatively execute instructions; buffer memory modifications\n} else {\n // Transaction abort\n ZF ← 1;\n EAX ← abort_code;\n RIP ← RIP + rel32; // Branch to fallback address\n}", "example": "XBEGIN rel"} {"mnemonic": "xend", "architecture": "x86", "full_name": "Transaction End", "summary": "Specifies end of RTM region.", "syntax": "XEND", "encoding": {"format": "Legacy", "hex_opcode": "NP 0F 01 D5", "visual_parts": [], "binary_pattern": "0F | 01 | D5", "bit_positions": "+0 | +1 | +2"}, "extension": "RTM (TSX)", "operands": [], "description": "Marks the end of a Restricted Transactional Memory (RTM) region and commits all buffered memory writes if the transaction succeeds. If the transaction has been aborted prior, XEND is a no-op; no flags are modified. Requires RTM extension and must be paired with XBEGIN.", "pseudocode": "if (RTM_TransactionActive) {\n if (RTMAborted) {\n // No-op; abort already occurred\n } else {\n // Commit buffered writes atomically\n CommitBufferedWrites();\n RTM_TransactionActive ← 0;\n }\n // No flags modified\n}", "example": "XEND"} {"mnemonic": "xabort", "architecture": "x86", "full_name": "Transaction Abort", "summary": "Forces an RTM abort.", "syntax": "XABORT imm8", "encoding": {"format": "Legacy", "hex_opcode": "C6 F8", "visual_parts": [], "binary_pattern": "C6 | F8", "bit_positions": "+0 | +1"}, "extension": "RTM (TSX)", "operands": [{"name": "dest", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Forces an explicit abort of the current Restricted Transactional Memory (RTM) transaction, causing execution to branch to the XBEGIN fallback address. The 8-bit immediate value is encoded in the low byte of EAX to indicate the abort reason. No flags are modified by XABORT itself; control flow branches via the RTM abort mechanism.", "pseudocode": "if (RTM_TransactionActive) {\n // Abort transaction\n EAX[7:0] ← imm8;\n RTM_TransactionActive ← 0;\n RIP ← XBEGINFallbackAddress; // Branch to XBEGIN offset\n} else {\n // Outside transaction; XABORT is a no-op\n}", "example": "XABORT 3"} {"mnemonic": "xtest", "architecture": "x86", "full_name": "Test If In Transaction", "summary": "Sets ZF if processor is in transactional region.", "syntax": "XTEST", "encoding": {"format": "Legacy", "hex_opcode": "NP 0F 01 D6", "visual_parts": [], "binary_pattern": "0F | 01 | D6", "bit_positions": "+0 | +1 | +2"}, "extension": "TSX", "operands": [], "description": "Tests whether the processor is currently executing within a Restricted Transactional Memory (RTM) region by setting the Zero Flag (ZF) to 1 if inside a transaction, or clearing it (ZF = 0) if outside. No other flags or registers are modified; useful for conditional logic in fallback code paths.", "pseudocode": "if (RTM_TransactionActive) {\n ZF ← 1; // Inside transaction\n} else {\n ZF ← 0; // Outside transaction\n}\n// All other flags unchanged", "example": "XTEST"} {"mnemonic": "umonitor", "architecture": "x86", "full_name": "User Level Monitor", "summary": "Sets up a monitor address for User Wait instructions.", "syntax": "UMONITOR r64", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F AE 11:110:bbb", "visual_parts": [], "binary_pattern": "F3 | 0F | AE | ModRM", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "WAITPKG", "operands": [{"name": "dest", "type": "r64", "desc": "64-bit general-purpose register (e.g. RAX)"}], "description": "Sets up a monitor address for User Wait instructions (UMWAIT, TPAUSE) by storing the linear address from the source register in the hardware monitor. The monitor watches for writes to the address range to arm the wait condition. No flags are modified; requires WAITPKG extension and 64-bit mode.", "pseudocode": "// Load monitor address from r64\nMonitorAddress ← src;\nMonitorState ← ARMED;\n// Monitor watches for writes to this address\n// No flags modified", "example": "UMONITOR rax"} {"mnemonic": "umwait", "architecture": "x86", "full_name": "User Level Monitor Wait", "summary": "Waits for store to monitored address (Low power state).", "syntax": "UMWAIT r32", "encoding": {"format": "Legacy", "hex_opcode": "F2 0F AE /6", "visual_parts": [], "binary_pattern": "F2 | 0F | AE | ModRM", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "WAITPKG", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}], "description": "Enters a low-power wait state and monitors the address specified in EDX:EAX until a store occurs to that monitored address or a timeout expires. The timeout value in ECX specifies the deadline. This instruction requires WAITPKG support and operates only in protected/64-bit mode at privilege level 0 (CPL=0). No flags are modified by this instruction.", "pseudocode": "if (WAITPKG not supported) raise #UD;\nif (CPL != 0) raise #GP(0);\nmonitor_address ← EDX:EAX;\ntimeout_value ← ECX;\nenter_low_power_state();\nwhile (monitored_address not written && current_time < timeout_value) {\n // CPU stays in low-power state\n}\nexit_low_power_state();\nEAX ← status_code;", "example": "UMWAIT eax"} {"mnemonic": "tpause", "architecture": "x86", "full_name": "Timed Pause", "summary": "Pauses execution for a specified time or until trigger.", "syntax": "TPAUSE r32", "encoding": {"format": "Legacy", "hex_opcode": "66 0F AE 11:110:bbb", "visual_parts": [], "binary_pattern": "66 | 0F | AE | ModRM", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "WAITPKG", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}], "description": "Pauses execution for a specified time interval (in TSC cycles) or until an external interrupt/event occurs, whichever comes first. The pause duration is specified in EDX:EAX and source operand controls pause type. This instruction requires WAITPKG support and operates only in protected/64-bit modes. No flags are modified; EAX contains a status code on completion.", "pseudocode": "if (WAITPKG not supported) raise #UD;\npause_type ← r32 & 0xF;\nduration ← EDX:EAX;\nif (pause_type == 0) {\n // Absolute TSC deadline\n while (current_tsc < duration && no_interrupt) pause_cycle();\n} else if (pause_type == 1) {\n // Relative delay\n end_time ← current_tsc + duration;\n while (current_tsc < end_time && no_interrupt) pause_cycle();\n}\nEAX ← status_code;", "example": "TPAUSE eax"} {"mnemonic": "vaddph", "architecture": "x86", "full_name": "Add Packed FP16 Values", "summary": "Adds half-precision floating-point values.", "syntax": "VADDPH zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.NP.MAP5.W0 58 /r", "visual_parts": [], "binary_pattern": "EVEX | 58", "bit_positions": "+0 | +4"}, "extension": "AVX-512-FP16", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Adds 32 pairs of half-precision (FP16) floating-point values from zmm2 and zmm3/m512, storing the result in zmm1 with optional write masking via k1. The operation follows IEEE 754 semantics for FP16 arithmetic, supporting rounding modes from MXCSR. Requires AVX-512-FP16 extension. Denormal operands may trigger exceptions per MXCSR exception mask settings.", "pseudocode": "for i ← 0 to 31 do\n if (k1[i] or no_mask) then\n zmm1[16*i+15:16*i] ← FP16_ADD(zmm2[16*i+15:16*i], zmm3[16*i+15:16*i]);\n else if (zeroing_mask)\n zmm1[16*i+15:16*i] ← 0;\nendfor;\n// MXCSR exception flags updated per result", "example": "VADDPH zmm1, zmm2, zmm3/m512"} {"mnemonic": "vsubph", "architecture": "x86", "full_name": "Subtract Packed FP16 Values", "summary": "Subtracts half-precision floating-point values.", "syntax": "VSUBPH zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.NP.MAP5.W0 5C /r", "visual_parts": [], "binary_pattern": "EVEX | 5C", "bit_positions": "+0 | +4"}, "extension": "AVX-512-FP16", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Subtracts 32 pairs of half-precision (FP16) floating-point values (zmm3/m512 from zmm2), storing the result in zmm1 with optional write masking via k1. The operation follows IEEE 754 semantics for FP16 arithmetic with configurable rounding modes from MXCSR. Requires AVX-512-FP16 extension. Exception behavior depends on MXCSR exception mask and denormal handling.", "pseudocode": "for i ← 0 to 31 do\n if (k1[i] or no_mask) then\n zmm1[16*i+15:16*i] ← FP16_SUB(zmm2[16*i+15:16*i], zmm3[16*i+15:16*i]);\n else if (zeroing_mask)\n zmm1[16*i+15:16*i] ← 0;\nendfor;\n// MXCSR exception flags updated per result", "example": "VSUBPH zmm1, zmm2, zmm3/m512"} {"mnemonic": "vmulph", "architecture": "x86", "full_name": "Multiply Packed FP16 Values", "summary": "Multiplies half-precision floating-point values.", "syntax": "VMULPH zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.NP.MAP5.W0 59 /r", "visual_parts": [], "binary_pattern": "EVEX | 59", "bit_positions": "+0 | +4"}, "extension": "AVX-512-FP16", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Multiplies 32 pairs of half-precision (FP16) floating-point values from zmm2 and zmm3/m512, storing the result in zmm1 with optional write masking via k1. Follows IEEE 754 semantics with rounding controlled by MXCSR. Requires AVX-512-FP16 extension. Exception flags in MXCSR are set per IEEE 754 rules (underflow, overflow, precision, invalid operation).", "pseudocode": "for i ← 0 to 31 do\n if (k1[i] or no_mask) then\n zmm1[16*i+15:16*i] ← FP16_MUL(zmm2[16*i+15:16*i], zmm3[16*i+15:16*i]);\n else if (zeroing_mask)\n zmm1[16*i+15:16*i] ← 0;\nendfor;\n// MXCSR exception flags updated per result", "example": "VMULPH zmm1, zmm2, zmm3/m512"} {"mnemonic": "vdivph", "architecture": "x86", "full_name": "Divide Packed FP16 Values", "summary": "Divides half-precision floating-point values.", "syntax": "VDIVPH zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.NP.MAP5.W0 5E /r", "visual_parts": [], "binary_pattern": "EVEX | 5E", "bit_positions": "+0 | +4"}, "extension": "AVX-512-FP16", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Divides 32 half-precision (FP16) floating-point values in zmm2 by corresponding values in zmm3/m512, storing the result in zmm1 with optional write masking via k1. Division follows IEEE 754 semantics with configurable rounding from MXCSR. Requires AVX-512-FP16 extension. Division-by-zero, invalid operations, and underflow/overflow exceptions are reported via MXCSR.", "pseudocode": "for i ← 0 to 31 do\n if (k1[i] or no_mask) then\n zmm1[16*i+15:16*i] ← FP16_DIV(zmm2[16*i+15:16*i], zmm3[16*i+15:16*i]);\n else if (zeroing_mask)\n zmm1[16*i+15:16*i] ← 0;\nendfor;\n// MXCSR exception flags updated per result (division-by-zero, etc.)", "example": "VDIVPH zmm1, zmm2, zmm3/m512"} {"mnemonic": "vsqrtph", "architecture": "x86", "full_name": "Square Root Packed FP16 Values", "summary": "Square root of half-precision values.", "syntax": "VSQRTPH zmm1 {k1}, zmm2/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.NP.MAP5.W0 51 /r", "visual_parts": [], "binary_pattern": "EVEX | 51", "bit_positions": "+0 | +4"}, "extension": "AVX-512-FP16", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src", "type": "zmm2/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Computes the square root of 32 half-precision (FP16) floating-point values from zmm2/m512, storing the result in zmm1 with optional write masking via k1. Square root follows IEEE 754 semantics with rounding controlled by MXCSR. Requires AVX-512-FP16 extension. Invalid operation (negative non-zero operand) and underflow/precision exceptions are reported via MXCSR.", "pseudocode": "for i ← 0 to 31 do\n if (k1[i] or no_mask) then\n zmm1[16*i+15:16*i] ← FP16_SQRT(zmm2[16*i+15:16*i]);\n else if (zeroing_mask)\n zmm1[16*i+15:16*i] ← 0;\nendfor;\n// MXCSR exception flags updated per result (invalid operation, underflow, etc.)", "example": "VSQRTPH zmm1, zmm2/m512"} {"mnemonic": "vminph", "architecture": "x86", "full_name": "Minimum Packed FP16 Values", "summary": "Minimum of half-precision values.", "syntax": "VMINPH zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.NP.MAP5.W0 5D /r", "visual_parts": [], "binary_pattern": "EVEX | 5D", "bit_positions": "+0 | +4"}, "extension": "AVX-512-FP16", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Computes element-wise minimum of 32 half-precision (FP16) floating-point values from zmm2 and zmm3/m512, storing the result in zmm1 with optional write masking via k1. Comparison follows IEEE 754 minimum semantics: NaN handling returns non-NaN operand when possible; equal values return zmm2. Requires AVX-512-FP16 extension. No exception flags are modified by comparison.", "pseudocode": "for i ← 0 to 31 do\n if (k1[i] or no_mask) then\n a ← zmm2[16*i+15:16*i];\n b ← zmm3[16*i+15:16*i];\n if (is_nan(a) && not is_nan(b)) zmm1[16*i+15:16*i] ← b;\n else if (is_nan(b) && not is_nan(a)) zmm1[16*i+15:16*i] ← a;\n else zmm1[16*i+15:16*i] ← (a < b) ? a : b;\n else if (zeroing_mask)\n zmm1[16*i+15:16*i] ← 0;\nendfor;", "example": "VMINPH zmm1, zmm2, zmm3/m512"} {"mnemonic": "vmaxph", "architecture": "x86", "full_name": "Maximum Packed FP16 Values", "summary": "Maximum of half-precision values.", "syntax": "VMAXPH zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.NP.MAP5.W0 5F /r", "visual_parts": [], "binary_pattern": "EVEX | 5F", "bit_positions": "+0 | +4"}, "extension": "AVX-512-FP16", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Computes the maximum of packed half-precision (FP16) values from two 512-bit sources, writing results to a 512-bit ZMM register under EVEX mask control. The instruction performs element-wise comparison following IEEE 754 semantics, with special handling for NaN and signed zero. No arithmetic flags are modified; this is a masked operation requiring AVX-512-FP16 support.", "pseudocode": "for i = 0 to 31:\n if (k1[i] == 1):\n zmm1[16*i:16*i+15] ← max_fp16(zmm2[16*i:16*i+15], zmm3/m512[16*i:16*i+15])\n else if (EVEX.z == 1):\n zmm1[16*i:16*i+15] ← 0\n // else zmm1[16*i:16*i+15] unchanged", "example": "VMAXPH zmm1, zmm2, zmm3/m512"} {"mnemonic": "vfmadd132ph", "architecture": "x86", "full_name": "Fused Multiply-Add (132) Packed FP16", "summary": "Computes (Dest * Src2) + Src1 in half-precision.", "syntax": "VFMADD132PH zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.MAP6.W0 98 /r", "visual_parts": [], "binary_pattern": "EVEX | 98", "bit_positions": "+0 | +4"}, "extension": "AVX-512-FP16", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Fused multiply-add instruction computing (zmm1 × zmm3/m512) + zmm2 in FP16 precision with a single rounding operation, improving accuracy and performance. The operand order (132) indicates zmm1 is the first multiplier, zmm3/m512 is the second, and zmm2 is the addend. Requires AVX-512-FP16; no arithmetic flags are modified; results are written to zmm1 under EVEX mask control.", "pseudocode": "for i = 0 to 31:\n if (k1[i] == 1):\n zmm1[16*i:16*i+15] ← fma_fp16(zmm1[16*i:16*i+15], zmm3/m512[16*i:16*i+15], zmm2[16*i:16*i+15])\n else if (EVEX.z == 1):\n zmm1[16*i:16*i+15] ← 0\n // else zmm1[16*i:16*i+15] unchanged", "example": "VFMADD132PH zmm1, zmm2, zmm3/m512"} {"mnemonic": "vfmadd213ph", "architecture": "x86", "full_name": "Fused Multiply-Add (213) Packed FP16", "summary": "Computes (Src1 * Dest) + Src2 in half-precision.", "syntax": "VFMADD213PH zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.MAP6.W0 A8 /r", "visual_parts": [], "binary_pattern": "EVEX | A8", "bit_positions": "+0 | +4"}, "extension": "AVX-512-FP16", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Fused multiply-add instruction computing (zmm2 × zmm1) + zmm3/m512 in FP16 precision with a single rounding operation. The operand order (213) indicates zmm2 is the first multiplier, zmm1 is the second, and zmm3/m512 is the addend. Requires AVX-512-FP16; no arithmetic flags are modified; results are written to zmm1 under EVEX mask control.", "pseudocode": "for i = 0 to 31:\n if (k1[i] == 1):\n zmm1[16*i:16*i+15] ← fma_fp16(zmm2[16*i:16*i+15], zmm1[16*i:16*i+15], zmm3/m512[16*i:16*i+15])\n else if (EVEX.z == 1):\n zmm1[16*i:16*i+15] ← 0\n // else zmm1[16*i:16*i+15] unchanged", "example": "VFMADD213PH zmm1, zmm2, zmm3/m512"} {"mnemonic": "vfmadd231ph", "architecture": "x86", "full_name": "Fused Multiply-Add (231) Packed FP16", "summary": "Computes (Src1 * Src2) + Dest in half-precision.", "syntax": "VFMADD231PH zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.MAP6.W0 B8 /r", "visual_parts": [], "binary_pattern": "EVEX | B8", "bit_positions": "+0 | +4"}, "extension": "AVX-512-FP16", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Fused multiply-add instruction computing (zmm2 × zmm3/m512) + zmm1 in FP16 precision with a single rounding operation. The operand order (231) indicates zmm2 is the first multiplier, zmm3/m512 is the second, and zmm1 is the addend. Requires AVX-512-FP16; no arithmetic flags are modified; results are written to zmm1 under EVEX mask control.", "pseudocode": "for i = 0 to 31:\n if (k1[i] == 1):\n zmm1[16*i:16*i+15] ← fma_fp16(zmm2[16*i:16*i+15], zmm3/m512[16*i:16*i+15], zmm1[16*i:16*i+15])\n else if (EVEX.z == 1):\n zmm1[16*i:16*i+15] ← 0\n // else zmm1[16*i:16*i+15] unchanged", "example": "VFMADD231PH zmm1, zmm2, zmm3/m512"} {"mnemonic": "vcvtne2ps2bf16", "architecture": "x86", "full_name": "Convert Two Packed Single to Packed BFloat16", "summary": "Converts two float vectors to one BFloat16 vector.", "syntax": "VCVTNE2PS2BF16 zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.F2.0F38.W0 72 /r", "visual_parts": [], "binary_pattern": "EVEX | 72", "bit_positions": "+0 | +4"}, "extension": "AVX-512-BF16", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Converts two packed single-precision (FP32) vectors into one packed bfloat16 vector by interleaving and rounding, producing 32 bfloat16 values in the destination ZMM register. The 'ne2' notation indicates two inputs are consumed to produce one output with truncation-based rounding (not MXCSR-controlled). Requires AVX-512-BF16; results are written under EVEX mask control; no arithmetic flags are modified.", "pseudocode": "for i = 0 to 15:\n if (k1[2*i] == 1 or k1[2*i+1] == 1):\n fp32_val1 ← zmm2[32*i:32*i+31]\n fp32_val2 ← zmm3/m512[32*i:32*i+31]\n zmm1[16*(2*i):16*(2*i)+15] ← convert_to_bf16_truncate(fp32_val1)\n zmm1[16*(2*i+1):16*(2*i+1)+15] ← convert_to_bf16_truncate(fp32_val2)\n else if (EVEX.z == 1):\n zmm1[16*(2*i):16*(2*i)+31] ← 0\n // else zmm1 unchanged", "example": "VCVTNE2PS2BF16 zmm1, zmm2, zmm3/m512"} {"mnemonic": "vdpbf16ps", "architecture": "x86", "full_name": "Dot Product BFloat16 to Packed Single", "summary": "BFloat16 dot product accumulating to Float32.", "syntax": "VDPBF16PS zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.F3.0F38.W0 52 /r", "visual_parts": [], "binary_pattern": "EVEX | 52", "bit_positions": "+0 | +4"}, "extension": "AVX-512-BF16", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Dot product instruction that multiplies pairs of bfloat16 elements from two sources and accumulates the products into FP32 results, with 32-bit precision accumulation improving accuracy for neural network operations. Each 512-bit register holds 8 groups of 4 bfloat16 values (32 elements total) producing 8 FP32 sums. Requires AVX-512-BF16; no arithmetic flags are modified; results are written to zmm1 under EVEX mask control.", "pseudocode": "for i = 0 to 7:\n if (k1[i] == 1):\n sum_fp32 ← zmm1[32*i:32*i+31] // accumulation value\n for j = 0 to 3:\n bf16_a ← zmm2[16*(4*i+j):16*(4*i+j)+15]\n bf16_b ← zmm3/m512[16*(4*i+j):16*(4*i+j)+15]\n fp32_a ← convert_bf16_to_fp32(bf16_a)\n fp32_b ← convert_bf16_to_fp32(bf16_b)\n sum_fp32 ← sum_fp32 + (fp32_a * fp32_b)\n zmm1[32*i:32*i+31] ← sum_fp32\n else if (EVEX.z == 1):\n zmm1[32*i:32*i+31] ← 0\n // else zmm1[32*i:32*i+31] unchanged", "example": "VDPBF16PS zmm1, zmm2, zmm3/m512"} {"mnemonic": "vaesenc", "architecture": "x86", "full_name": "Vector AES Encrypt (AVX512)", "summary": "AES Encrypt on 512-bit vector.", "syntax": "VAESENC zmm1, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.WIG DC /r", "visual_parts": [], "binary_pattern": "EVEX | DC", "bit_positions": "+0 | +4"}, "extension": "AVX-512-VAES", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Performs AES single-round encryption on 512-bit data, applying SubBytes, ShiftRows, MixColumns, and AddRoundKey operations to four independent 128-bit AES blocks in parallel. The instruction treats the 512-bit register as four consecutive 128-bit AES state blocks and applies the round key (zmm3/m512) element-wise. Requires AVX-512-VAES; no arithmetic flags are modified; results are written to zmm1.", "pseudocode": "for block = 0 to 3:\n state_128 ← zmm2[128*block:128*block+127]\n round_key_128 ← zmm3/m512[128*block:128*block+127]\n state_128 ← AES_SubBytes(state_128)\n state_128 ← AES_ShiftRows(state_128)\n state_128 ← AES_MixColumns(state_128)\n state_128 ← state_128 XOR round_key_128\n zmm1[128*block:128*block+127] ← state_128", "example": "VAESENC zmm1, zmm2, zmm3/m512"} {"mnemonic": "vaesdec", "architecture": "x86", "full_name": "Vector AES Decrypt (AVX512)", "summary": "AES Decrypt on 512-bit vector.", "syntax": "VAESDEC zmm1, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.WIG DE /r", "visual_parts": [], "binary_pattern": "EVEX | DE", "bit_positions": "+0 | +4"}, "extension": "AVX-512-VAES", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Performs AES single-round decryption on 512-bit data, applying InvSubBytes, InvShiftRows, InvMixColumns, and AddRoundKey operations to four independent 128-bit AES blocks in parallel. The instruction treats the 512-bit register as four consecutive 128-bit AES state blocks and applies the round key (zmm3/m512) element-wise. Requires AVX-512-VAES; no arithmetic flags are modified; results are written to zmm1.", "pseudocode": "for block = 0 to 3:\n state_128 ← zmm2[128*block:128*block+127]\n round_key_128 ← zmm3/m512[128*block:128*block+127]\n state_128 ← AES_InvSubBytes(state_128)\n state_128 ← AES_InvShiftRows(state_128)\n state_128 ← AES_InvMixColumns(state_128)\n state_128 ← state_128 XOR round_key_128\n zmm1[128*block:128*block+127] ← state_128", "example": "VAESDEC zmm1, zmm2, zmm3/m512"} {"mnemonic": "vpclmulqdq", "architecture": "x86", "full_name": "Vector Carry-Less Multiplication (AVX512)", "summary": "Carry-less multiply on 512-bit vector.", "syntax": "VPCLMULQDQ zmm1, zmm2, zmm3/m512, imm8", "encoding": {"format": "EVEX", "hex_opcode": "VEX.128.66.0F3A.WIG 44 /r ib", "visual_parts": [], "binary_pattern": "EVEX | 44", "bit_positions": "+0 | +4"}, "extension": "AVX-512-VPCLMULQDQ", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}, {"name": "src3", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Performs carry-less multiplication of 64-bit elements from two 512-bit vectors, producing 128-bit results that are stored in the destination ZMM register. The imm8 field selects which 64-bit quadwords from the source operands participate in the multiplication. No flags are affected; this is a cryptographic primitive used in GCM and other authenticated encryption modes.", "pseudocode": "for i in 0 to 3:\n qw1 = (imm8[0] == 0) ? zmm2[i*64..i*64+63] : zmm2[i*64+64..i*64+127]\n qw2 = (imm8[4] == 0) ? zmm3[i*64..i*64+63] : zmm3[i*64+64..i*64+127]\n zmm1[i*128..i*128+127] ← carryless_multiply(qw1, qw2)", "example": "VPCLMULQDQ zmm1, zmm2, zmm3/m512, 3"} {"mnemonic": "vsha512msg1", "architecture": "x86", "full_name": "SHA512 Message Schedule 1", "summary": "SHA512 intermediate calculation (AVX512).", "syntax": "VSHA512MSG1 ymm1, xmm2", "encoding": {"format": "EVEX", "hex_opcode": "VEX.256.F2.0F38.W0 CC 11:rrr:bbb", "visual_parts": [], "binary_pattern": "CC", "bit_positions": "+0"}, "extension": "SHA512", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src", "type": "xmm2", "desc": "128-bit XMM SIMD register"}], "description": "Computes SHA-512 message schedule expansion for the first message schedule instruction, operating on a 128-bit XMM source and producing a 256-bit YMM result. This instruction is part of the SHA-512 cryptographic hash computation pipeline and requires AVX-512 or SHA512 extension support. No EFLAGS are modified.", "pseudocode": "W[0..3] ← xmm2[64*i..64*i+63] for i in 0 to 1\nW[4..7] ← expand_sha512_msg_schedule(W[0..3])\nymm1[256 bits] ← W[4..7]", "example": "VSHA512MSG1 ymm1, xmm2"} {"mnemonic": "vsha512msg2", "architecture": "x86", "full_name": "SHA512 Message Schedule 2", "summary": "SHA512 final calculation (AVX512).", "syntax": "VSHA512MSG2 ymm1, ymm2", "encoding": {"format": "EVEX", "hex_opcode": "VEX.256.F2.0F38.W0 CD 11:rrr:bbb", "visual_parts": [], "binary_pattern": "CD", "bit_positions": "+0"}, "extension": "SHA512", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src", "type": "ymm2", "desc": "256-bit YMM AVX register"}], "description": "Computes the second stage of SHA-512 message schedule expansion, combining two 256-bit YMM inputs to produce a 256-bit result. This instruction is used after VSHA512MSG1 to complete the message schedule preparation for SHA-512 block processing. No EFLAGS are modified.", "pseudocode": "W[0..3] ← ymm1[64*i..64*i+63] for i in 0 to 3\nW[4..7] ← ymm2[64*i..64*i+63] for i in 0 to 3\nresult ← sha512_msg2_schedule(W[0..3], W[4..7])\nymm1[256 bits] ← result", "example": "VSHA512MSG2 ymm1, ymm2"} {"mnemonic": "vsha512rnds2", "architecture": "x86", "full_name": "SHA512 Rounds 2", "summary": "SHA512 2 rounds calculation (AVX512).", "syntax": "VSHA512RNDS2 ymm1, ymm2, xmm3", "encoding": {"format": "EVEX", "hex_opcode": "VEX.256.F2.0F38.W0 CB 11:rrr:bbb", "visual_parts": [], "binary_pattern": "CB", "bit_positions": "+0"}, "extension": "SHA512", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src1", "type": "ymm2", "desc": "256-bit YMM AVX register"}, {"name": "src2", "type": "xmm3", "desc": "128-bit XMM SIMD register"}], "description": "Executes two rounds of SHA-512 compression function, processing a 256-bit working variable vector (ymm1) using a 256-bit state operand (ymm2) and round constants from a 128-bit XMM register. This instruction performs the core iterative hash compression and does not modify EFLAGS.", "pseudocode": "A_B[0..1] ← ymm1[128*i..128*i+127] for i in 0 to 1\nC_D_E_F_G_H[0..3] ← ymm2[64*i..64*i+63] for i in 0 to 3\nRK[0..1] ← xmm3[64*i..64*i+63] for i in 0 to 1\nfor round in 0 to 1:\n temp ← sha512_compress_round(A_B, C_D_E_F_G_H, RK[round])\n A_B, C_D_E_F_G_H ← temp\nymm1[256 bits] ← A_B[0..1]", "example": "VSHA512RNDS2 ymm1, ymm2, xmm3"} {"mnemonic": "vsm3msg1", "architecture": "x86", "full_name": "SM3 Message Schedule 1", "summary": "SM3 crypto message schedule part 1.", "syntax": "VSM3MSG1 xmm1, xmm2, xmm3", "encoding": {"format": "VEX", "hex_opcode": "VEX.128.NP.0F38.W0 DA /r", "visual_parts": [], "binary_pattern": "DA", "bit_positions": "+0"}, "extension": "SM3", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2", "desc": "128-bit XMM SIMD register"}, {"name": "src2", "type": "xmm3", "desc": "128-bit XMM SIMD register"}], "description": "Performs the first stage of SM3 (Chinese cryptographic hash standard) message schedule computation on 128-bit inputs, producing a 128-bit expanded message word. This instruction combines three XMM operands using SM3-specific expansion logic and does not modify EFLAGS.", "pseudocode": "W ← xmm2[32*i..32*i+31] for i in 0 to 3\nW_prime ← xmm3[32*i..32*i+31] for i in 0 to 3\nW_new ← sm3_msg1_expand(W, W_prime)\nxmm1[128 bits] ← W_new", "example": "VSM3MSG1 xmm1, xmm2, xmm3"} {"mnemonic": "vsm3rnds2", "architecture": "x86", "full_name": "SM3 Rounds 2", "summary": "SM3 crypto 2 rounds.", "syntax": "VSM3RNDS2 xmm1, xmm2, imm8", "encoding": {"format": "VEX", "hex_opcode": "VEX.128.66.0F3A.W0 DE /r /ib", "visual_parts": [], "binary_pattern": "DE", "bit_positions": "+0"}, "extension": "SM3", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2", "desc": "128-bit XMM SIMD register"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Executes two rounds of SM3 compression function using a 128-bit working variable XMM register and an immediate value specifying round constants and control flow. The instruction applies SM3-specific round transformations and does not modify EFLAGS.", "pseudocode": "A_B_C_D ← xmm1[32*i..32*i+31] for i in 0 to 3\nE_F_G_H ← xmm2[32*i..32*i+31] for i in 0 to 3\nround_sel ← imm8[7..0]\nfor round in 0 to 1:\n RK ← sm3_round_constant(round_sel + round)\n temp ← sm3_compress_round(A_B_C_D, E_F_G_H, RK)\n A_B_C_D, E_F_G_H ← temp\nxmm1[128 bits] ← A_B_C_D", "example": "VSM3RNDS2 xmm1, xmm2, 3"} {"mnemonic": "vsm4rnds4", "architecture": "x86", "full_name": "SM4 Four Rounds Encryption", "summary": "Performs four rounds of SM4 encryption.", "syntax": "VSM4RNDS4 xmm1, xmm2, xmm3/m128", "encoding": {"format": "VEX", "hex_opcode": "VEX.128.F2.0F38.W0 DA /r", "visual_parts": [], "binary_pattern": "DA", "bit_positions": "+0"}, "extension": "SM4", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2", "desc": "128-bit XMM SIMD register"}, {"name": "src2", "type": "xmm3/m128", "desc": "128-bit XMM SIMD register or 128-bit memory operand"}], "description": "Performs one round of SM4 block cipher encryption on 128-bit data, applying the SM4 S-box substitution and linear transformation using round key material from the source XMM register. This instruction is used iteratively to encrypt 32 rounds of the SM4 algorithm and does not modify EFLAGS.", "pseudocode": "plaintext ← xmm1[32*i..32*i+31] for i in 0 to 3\nRK ← xmm2[32*i..32*i+31] for i in 0 to 3\nfor i in 0 to 3:\n X ← plaintext[0..3]\n X ← SM4_F(X, RK[i])\n plaintext ← rotate_left(X, 1)\nxmm1[128 bits] ← plaintext", "example": "VSM4RNDS4 xmm1, xmm2, xmm3"} {"mnemonic": "vsm4key4", "architecture": "x86", "full_name": "SM4 Key Generation", "summary": "SM4 key generation.", "syntax": "VSM4KEY4 xmm1, xmm2, xmm3/m128", "encoding": {"format": "VEX", "hex_opcode": "VEX.128.F3.0F38.W0 DA /r", "visual_parts": [], "binary_pattern": "DA", "bit_positions": "+0"}, "extension": "SM4", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2", "desc": "128-bit XMM SIMD register"}, {"name": "src2", "type": "xmm3/m128", "desc": "128-bit XMM SIMD register or 128-bit memory operand"}], "description": "Performs key schedule expansion for SM4 block cipher, deriving round keys from a 128-bit key material input and producing expanded key words in the destination XMM register. This instruction is used during SM4 key setup to generate all required round keys and does not modify EFLAGS.", "pseudocode": "key ← xmm2[32*i..32*i+31] for i in 0 to 3\nexpanded_key ← SM4_KEY_SCHEDULE(key)\nxmm1[128 bits] ← expanded_key[0..3]", "example": "VSM4KEY4 xmm1, xmm2, xmm3"} {"mnemonic": "loadiwkey", "architecture": "x86", "full_name": "Load Internal Wrapping Key", "summary": "Loads the Key Locker internal wrapping key.", "syntax": "LOADIWKEY xmm1, xmm2", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F 38 DC", "visual_parts": [], "binary_pattern": "F3 | 0F | 38 | DC", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "KEYLOCKER", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2", "desc": "128-bit XMM SIMD register"}], "description": "Loads the Key Locker internal wrapping key from xmm2 into the processor's internal state, using xmm1 as a control operand. This instruction requires the KEYLOCKER CPU feature and is a privileged operation. No flags are modified; the instruction serializes execution and may cause a general-protection exception (#GP) if the key material is invalid or the CPL is not 0.", "pseudocode": "IF CPL != 0 THEN #GP(0) FI;\nif CPUID.KEYLOCKER = 0 THEN #UD FI;\nINTERNAL_WRAPPING_KEY ← xmm2[127:0];\nCONTROL ← xmm1[127:0];", "example": "LOADIWKEY xmm1, xmm2"} {"mnemonic": "encodekey128", "architecture": "x86", "full_name": "Encode 128-bit Key", "summary": "Wraps a 128-bit AES key into a handle.", "syntax": "ENCODEKEY128 r32, r32", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F 38 FA", "visual_parts": [], "binary_pattern": "F3 | 0F | 38 | FA", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "KEYLOCKER", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}], "description": "Wraps a 128-bit AES key into an encoded Key Locker handle, where the second r32 operand contains the key and the first r32 receives status/handle information. The ZF flag is set to indicate success (ZF=0) or failure (ZF=1). This instruction requires KEYLOCKER support and uses the internal wrapping key loaded by LOADIWKEY.", "pseudocode": "IF CPUID.KEYLOCKER = 0 THEN #UD FI;\nkey_material ← src[31:0];\nhandle_out ← AES_WRAP_128(key_material, INTERNAL_WRAPPING_KEY);\ndest[31:0] ← handle_out;\nZF ← 0;", "example": "ENCODEKEY128 eax, eax"} {"mnemonic": "aesenc128kl", "architecture": "x86", "full_name": "AES Encrypt 128-bit Key Locker", "summary": "Encrypts data using Key Locker handle.", "syntax": "AESENC128KL m128, xmm", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F 38 DC !(11):rrr:bbb", "visual_parts": [], "binary_pattern": "F3 | 0F | 38 | DD", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "KEYLOCKER", "operands": [{"name": "dest", "type": "m128", "desc": "128-bit memory operand"}, {"name": "src", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}], "description": "Performs AES encryption on 128-bit data in the XMM register using a Key Locker handle stored in memory. The encrypted result is written back to the XMM register, and ZF is set to indicate success or failure of the operation. This instruction requires KEYLOCKER support and performs the operation using the internal wrapping key.", "pseudocode": "IF CPUID.KEYLOCKER = 0 THEN #UD FI;\nhandle ← [dest][127:0];\nplaintext ← src[127:0];\nciphertext ← AES_ENCRYPT_128(plaintext, UNWRAP_KEY_128(handle, INTERNAL_WRAPPING_KEY));\nsrc[127:0] ← ciphertext;\nZF ← 0;", "example": "AESENC128KL [rbp-16], xmm0"} {"mnemonic": "aesdec128kl", "architecture": "x86", "full_name": "AES Decrypt 128-bit Key Locker", "summary": "Decrypts data using Key Locker handle.", "syntax": "AESDEC128KL m128, xmm", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F 38 DD !(11):rrr:bbb", "visual_parts": [], "binary_pattern": "F3 | 0F | 38 | DE", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "KEYLOCKER", "operands": [{"name": "dest", "type": "m128", "desc": "128-bit memory operand"}, {"name": "src", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}], "description": "Performs AES decryption on 128-bit data in the XMM register using a Key Locker handle stored in memory. The decrypted result is written back to the XMM register, and ZF is set to indicate success or failure. This instruction requires KEYLOCKER support and unwraps the key using the internal wrapping key.", "pseudocode": "IF CPUID.KEYLOCKER = 0 THEN #UD FI;\nhandle ← [dest][127:0];\nciphertext ← src[127:0];\nplaintext ← AES_DECRYPT_128(ciphertext, UNWRAP_KEY_128(handle, INTERNAL_WRAPPING_KEY));\nsrc[127:0] ← plaintext;\nZF ← 0;", "example": "AESDEC128KL [rbp-16], xmm0"} {"mnemonic": "hreset", "architecture": "x86", "full_name": "History Reset", "summary": "Resets processor history (prediction) structures.", "syntax": "HRESET imm8", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F 3A F0 C0 ib", "visual_parts": [], "binary_pattern": "F3 | 0F | 3A | F0", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "HRESET", "operands": [{"name": "dest", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Resets selected processor prediction/history structures (BTB, TLB, or other micro-architectural caches) as specified by the 8-bit immediate operand. The instruction may serialize the execution pipeline and is typically used to mitigate side-channel attacks. No EFLAGS are modified; the instruction requires HRESET CPU feature support.", "pseudocode": "IF CPUID.HRESET = 0 THEN #UD FI;\nselect_bits ← imm8[7:0];\nIF select_bits & 0x01 THEN RESET_BTB() FI;\nIF select_bits & 0x02 THEN RESET_TLB() FI;\nIF select_bits & 0x04 THEN RESET_RSB() FI;", "example": "HRESET 3"} {"mnemonic": "serialize", "architecture": "x86", "full_name": "Serialize Instruction Execution", "summary": "Forces serialization of instruction fetch/execution.", "syntax": "SERIALIZE", "encoding": {"format": "Legacy", "hex_opcode": "NP 0F 01 E8", "visual_parts": [], "binary_pattern": "0F | 01 | E8", "bit_positions": "+0 | +1 | +2"}, "extension": "SERIALIZE", "operands": [], "description": "Serializes instruction execution by ensuring all prior instructions have completed and all memory operations are ordered before subsequent instructions execute. This instruction blocks out-of-order execution, flushes the pipeline, and may have significant performance impact. No flags are modified; the instruction requires SERIALIZE CPU feature and may incur substantial latency.", "pseudocode": "IF CPUID.SERIALIZE = 0 THEN #UD FI;\nWAIT_FOR_ALL_PRIOR_INSTRUCTIONS();\nFLUSH_EXECUTION_PIPELINE();\nCLEAR_OUT_OF_ORDER_BUFFERS();", "example": "SERIALIZE"} {"mnemonic": "rdpid", "architecture": "x86", "full_name": "Read Processor ID", "summary": "Reads the processor ID (TSC_AUX) into register.", "syntax": "RDPID r32", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F C7 /7", "visual_parts": [], "binary_pattern": "F3 | 0F | C7 | ModRM", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "RDPID", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}], "description": "Reads the processor ID (IA32_TSC_AUX MSR value) into the destination 32-bit register, providing thread/core identification information. This is a fast operation compared to RDMSR and requires the RDPID CPU feature. No flags are modified; the instruction can execute in user mode if IA32_TSC_AUX is readable.", "pseudocode": "IF CPUID.RDPID = 0 THEN #UD FI;\ndest[31:0] ← IA32_TSC_AUX[31:0];\ndest[63:32] ← 0;", "example": "RDPID eax"} {"mnemonic": "xsaves", "architecture": "x86", "full_name": "Save Supervisor States", "summary": "Saves supervisor state components to memory (Compact).", "syntax": "XSAVES m", "encoding": {"format": "Legacy", "hex_opcode": "NP 0F C7 /5", "visual_parts": [], "binary_pattern": "0F | C7 | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "XSAVES", "operands": [{"name": "dest", "type": "m", "desc": "Memory operand"}], "description": "Saves processor extended state components (both user and supervisor states) to memory in compact form, controlled by the XCR0 and IA32_XSS MSRs and a mask in EDX:EAX. This instruction is a supervisor-mode only operation requiring CPL=0 and XSAVES feature support. No EFLAGS are modified; memory layout is compact and may trigger #GP if state is invalid.", "pseudocode": "IF CPL != 0 THEN #GP(0) FI;\nIF CPUID.XSAVES = 0 THEN #UD FI;\nmask ← (EDX << 32) | EAX;\nsave_regions ← GET_SAVE_REGIONS_MASKED(XCR0, IA32_XSS, mask);\nCOMPACT_SAVE_STATE(dest, save_regions);", "example": "XSAVES [rbp-8]"} {"mnemonic": "xrstors", "architecture": "x86", "full_name": "Restore Supervisor States", "summary": "Restores supervisor state components from memory (Compact).", "syntax": "XRSTORS m", "encoding": {"format": "Legacy", "hex_opcode": "NP 0F C7 /3", "visual_parts": [], "binary_pattern": "0F | C7 | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "XSAVES", "operands": [{"name": "dest", "type": "m", "desc": "Memory operand"}], "description": "Restores processor extended state components (XMM, YMM, ZMM, and other state) from memory in compact form, using the state bitmap in EDX:EAX to determine which components to restore. This instruction is privileged (ring 0 only) and requires the XSAVES extension. Requires XSAVE feature enabled and XSAVES support; no flags are affected.", "pseudocode": "IF (CR4.OSXSAVE == 0 || CPL != 0) THEN #UD;\nIF (m is not 64-byte aligned) THEN #GP(0);\nstate_bitmap ← EDX:EAX;\nrestore_xsave_state_from_memory(m, state_bitmap, supervisor=true);", "example": "XRSTORS [rbp-8]"} {"mnemonic": "ptwrite", "architecture": "x86", "full_name": "Write Data to Processor Trace", "summary": "Writes data to the Intel Processor Trace stream.", "syntax": "PTWRITE r32/r64", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F AE /4", "visual_parts": [], "binary_pattern": "F3 | 0F | AE | ModRM", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "PTWRITE", "operands": [{"name": "dest", "type": "r32/r64", "desc": "General-purpose register or General-purpose register"}], "description": "Writes a 32-bit or 64-bit value from a general-purpose register into the Intel Processor Trace output stream, if PT is enabled and PT.PTW is set. The write is non-blocking and does not modify CPU flags. Requires PTWRITE extension support; operation has no effect if Processor Trace is disabled.", "pseudocode": "IF (CPL > 0 && IA32_RTIT_CTL.CR3Filter == 1) THEN #GP(0);\nIF (PT_enabled && PT.PTW) THEN {\n trace_output ← operand;\n generate_ptw_packet(operand);\n}\nELSE {\n // No effect if PT disabled or PTW not set\n}", "example": "PTWRITE r32/r64"} {"mnemonic": "uiret", "architecture": "x86", "full_name": "User Interrupt Return", "summary": "Returns from a User Interrupt handler.", "syntax": "UIRET", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F 01 EC", "visual_parts": [], "binary_pattern": "F3 | 0F | 01 | EC", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "UINTR", "operands": [], "description": "Returns from a User Interrupt handler to user code, restoring the previously saved user context (RIP, RFLAGS) from the User Interrupt Stack Table (UIST). This is a privileged operation (executed only in the UIRET target code path) and requires UINTR extension support. No flags are affected by the instruction itself; user flags are restored from the saved context.", "pseudocode": "IF (!UINTR_enabled) THEN #UD;\ntemp_rip ← read_from_UIST();\ntemp_rflags ← read_from_UIST();\nRIP ← temp_rip;\nRFLAGS ← temp_rflags;\nRETURN_TO_USER_MODE();", "example": "UIRET"} {"mnemonic": "senduipi", "architecture": "x86", "full_name": "Send User Inter-Processor Interrupt", "summary": "Sends a User IPI to another processor.", "syntax": "SENDUIPI r64", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F C7 11:110:bbb", "visual_parts": [], "binary_pattern": "F3 | 0F | C7 | ModRM", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "UINTR", "operands": [{"name": "dest", "type": "r64", "desc": "64-bit general-purpose register (e.g. RAX)"}], "description": "Sends a User Inter-Processor Interrupt (User IPI) to another processor identified by the UIPI index stored in the source 64-bit register. The source register contains an UPID (User IPI Posting Descriptor) index that identifies the target thread. Requires UINTR extension support; operation may be serializing and updates the target processor's interrupt state.", "pseudocode": "IF (!UINTR_enabled) THEN #UD;\nuipi_index ← src_reg[63:0];\nupid ← retrieve_UPID_from_index(uipi_index);\npost_user_interrupt_to_target(upid);\nSEND_IPI_TO_TARGET_CPU();", "example": "SENDUIPI rax"} {"mnemonic": "in", "architecture": "x86", "full_name": "Input from Port", "summary": "Reads data from an I/O port into AL/AX/EAX.", "syntax": "IN AL, imm8", "encoding": {"format": "Legacy", "hex_opcode": "E4", "visual_parts": [], "binary_pattern": "E4", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "AL", "desc": "Implicit AL register (8-bit accumulator)"}, {"name": "src", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Reads a byte from an I/O port (specified by the immediate 8-bit operand) and stores the result in AL. If IOPL permits, this instruction can be used in user mode; otherwise it requires ring 0. No flags are affected. The port number is zero-extended to 16 bits for I/O address calculation.", "pseudocode": "IF (CPL > IOPL && !V86_mode) THEN #GP(0);\nAL ← I/O_port[imm8];", "example": "IN AL, 3"} {"mnemonic": "out", "architecture": "x86", "full_name": "Output to Port", "summary": "Writes data from AL/AX/EAX to an I/O port.", "syntax": "OUT imm8, AL", "encoding": {"format": "Legacy", "hex_opcode": "E6", "visual_parts": [], "binary_pattern": "E6", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "imm8", "desc": "8-bit signed immediate"}, {"name": "src", "type": "AL", "desc": "Implicit AL register (8-bit accumulator)"}], "description": "Writes a byte from AL to an I/O port (specified by the immediate 8-bit operand). If IOPL permits, this instruction can be used in user mode; otherwise it requires ring 0. No flags are affected. The port number is zero-extended to 16 bits for I/O address calculation.", "pseudocode": "IF (CPL > IOPL && !V86_mode) THEN #GP(0);\nI/O_port[imm8] ← AL;", "example": "OUT 3, AL"} {"mnemonic": "ins", "architecture": "x86", "full_name": "Input String from Port", "summary": "Reads string from I/O port to memory at [EDI].", "syntax": "INSB", "encoding": {"format": "Legacy", "hex_opcode": "6C", "visual_parts": [], "binary_pattern": "6C", "bit_positions": "+0"}, "extension": "Base", "operands": [], "description": "Reads a byte from the I/O port specified in DX and writes it to memory at the address [RDI/EDI/DI] (selected by address-size override). The destination address pointer is incremented or decremented by 1 based on the direction flag (DF). This is a string instruction often used with REP prefix; no flags are affected directly by INS itself.", "pseudocode": "IF (CPL > IOPL && !V86_mode) THEN #GP(0);\ntempByte ← I/O_port[DX];\n[RDI] ← tempByte;\nIF (DF == 0) THEN RDI ← RDI + 1;\nELSE RDI ← RDI - 1;", "example": "INSB"} {"mnemonic": "outs", "architecture": "x86", "full_name": "Output String to Port", "summary": "Writes string from memory at [ESI] to I/O port.", "syntax": "OUTSB", "encoding": {"format": "Legacy", "hex_opcode": "6E", "visual_parts": [], "binary_pattern": "6E", "bit_positions": "+0"}, "extension": "Base", "operands": [], "description": "Reads a byte from memory at the address [RSI/ESI/SI] (selected by address-size override) and writes it to the I/O port specified in DX. The source address pointer is incremented or decremented by 1 based on the direction flag (DF). This is a string instruction often used with REP prefix; no flags are affected directly by OUTS itself.", "pseudocode": "IF (CPL > IOPL && !V86_mode) THEN #GP(0);\ntempByte ← [RSI];\nI/O_port[DX] ← tempByte;\nIF (DF == 0) THEN RSI ← RSI + 1;\nELSE RSI ← RSI - 1;", "example": "OUTSB"} {"mnemonic": "lods", "architecture": "x86", "full_name": "Load String", "summary": "Loads byte/word/dword from [ESI] into AL/AX/EAX.", "syntax": "LODSB", "encoding": {"format": "Legacy", "hex_opcode": "AC", "visual_parts": [], "binary_pattern": "AC", "bit_positions": "+0"}, "extension": "Base", "operands": [], "description": "Loads a byte, word, or doubleword from memory at address DS:[ESI] (or RSI in 64-bit mode) into the accumulator (AL, AX, or EAX respectively), then increments or decrements ESI/RSI by the operand size based on the direction flag (DF). No flags are affected by this instruction.", "pseudocode": "if (DF == 0) {\n ESI ← ESI + operand_size;\n} else {\n ESI ← ESI - operand_size;\n}\nAL/AX/EAX ← [DS:ESI];", "example": "LODSB"} {"mnemonic": "stos", "architecture": "x86", "full_name": "Store String", "summary": "Stores AL/AX/EAX to memory at [EDI].", "syntax": "STOSB", "encoding": {"format": "Legacy", "hex_opcode": "AA", "visual_parts": [], "binary_pattern": "AA", "bit_positions": "+0"}, "extension": "Base", "operands": [], "description": "Stores the contents of the accumulator (AL, AX, or EAX) into memory at address ES:[EDI] (or RDI in 64-bit mode), then increments or decrements EDI/RDI by the operand size based on the direction flag (DF). No flags are affected. This instruction is commonly used with REP prefix for bulk memory fills.", "pseudocode": "[ES:EDI] ← AL/AX/EAX;\nif (DF == 0) {\n EDI ← EDI + operand_size;\n} else {\n EDI ← EDI - operand_size;\n}", "example": "STOSB"} {"mnemonic": "scas", "architecture": "x86", "full_name": "Scan String", "summary": "Compares AL/AX/EAX with memory at [EDI].", "syntax": "SCASB", "encoding": {"format": "Legacy", "hex_opcode": "AE", "visual_parts": [], "binary_pattern": "AE", "bit_positions": "+0"}, "extension": "Base", "operands": [], "description": "Compares the accumulator (AL, AX, or EAX) with a byte, word, or doubleword in memory at address ES:[EDI], setting EFLAGS as if by subtraction, then increments or decrements EDI/RDI by the operand size based on DF. ZF, CF, OF, SF, AF, and PF are set according to the comparison result.", "pseudocode": "temp ← AL/AX/EAX - [ES:EDI];\nZF ← (temp == 0);\nCF ← (AL/AX/EAX < [ES:EDI]);\nOF ← overflow_from_subtraction;\nSF ← sign_bit_of(temp);\nAF ← auxiliary_carry_from_subtraction;\nPF ← parity_of(temp);\nif (DF == 0) {\n EDI ← EDI + operand_size;\n} else {\n EDI ← EDI - operand_size;\n}", "example": "SCASB"} {"mnemonic": "cmps", "architecture": "x86", "full_name": "Compare String", "summary": "Compares byte/word at [ESI] with [EDI].", "syntax": "CMPSB", "encoding": {"format": "Legacy", "hex_opcode": "A6", "visual_parts": [], "binary_pattern": "A6", "bit_positions": "+0"}, "extension": "Base", "operands": [], "description": "Compares a byte, word, or doubleword at memory address DS:[ESI] with the value at ES:[EDI], setting EFLAGS as if by subtraction, then increments or decrements both ESI/RSI and EDI/RDI by the operand size based on DF. ZF, CF, OF, SF, AF, and PF reflect the comparison result.", "pseudocode": "temp ← [DS:ESI] - [ES:EDI];\nZF ← (temp == 0);\nCF ← ([DS:ESI] < [ES:EDI]);\nOF ← overflow_from_subtraction;\nSF ← sign_bit_of(temp);\nAF ← auxiliary_carry_from_subtraction;\nPF ← parity_of(temp);\nif (DF == 0) {\n ESI ← ESI + operand_size;\n EDI ← EDI + operand_size;\n} else {\n ESI ← ESI - operand_size;\n EDI ← EDI - operand_size;\n}", "example": "CMPSB"} {"mnemonic": "lds", "architecture": "x86", "full_name": "Load Far Pointer using DS", "summary": "Loads pointer into DS and register.", "syntax": "LDS r, m", "encoding": {"format": "Legacy", "hex_opcode": "C5", "visual_parts": [], "binary_pattern": "C5", "bit_positions": "+0"}, "extension": "Base (Legacy)", "operands": [{"name": "dest", "type": "r", "desc": "General-purpose register"}, {"name": "src", "type": "m", "desc": "Memory operand"}], "description": "Loads a far pointer from memory into a general-purpose register and the DS segment register. The memory operand contains a 32-bit pointer (16-bit offset and 16-bit segment) in 16/32-bit modes. Not available in 64-bit mode. No flags are affected.", "pseudocode": "dest ← [src];\nDS ← [src + operand_size];", "example": "LDS rax, [rbp-8]"} {"mnemonic": "les", "architecture": "x86", "full_name": "Load Far Pointer using ES", "summary": "Loads pointer into ES and register.", "syntax": "LES r, m", "encoding": {"format": "Legacy", "hex_opcode": "C4", "visual_parts": [], "binary_pattern": "C4", "bit_positions": "+0"}, "extension": "Base (Legacy)", "operands": [{"name": "dest", "type": "r", "desc": "General-purpose register"}, {"name": "src", "type": "m", "desc": "Memory operand"}], "description": "Loads a far pointer from memory into a general-purpose register and the ES segment register. The memory operand contains a 32-bit pointer (16-bit offset and 16-bit segment) in 16/32-bit modes. Not available in 64-bit mode. No flags are affected.", "pseudocode": "dest ← [src];\nES ← [src + operand_size];", "example": "LES rax, [rbp-8]"} {"mnemonic": "lfs", "architecture": "x86", "full_name": "Load Far Pointer using FS", "summary": "Loads pointer into FS and register.", "syntax": "LFS r, m", "encoding": {"format": "Legacy", "hex_opcode": "0F B4", "visual_parts": [], "binary_pattern": "0F | B4", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r", "desc": "General-purpose register"}, {"name": "src", "type": "m", "desc": "Memory operand"}], "description": "Loads a far pointer from memory into a general-purpose register and the FS segment register. The memory operand contains a 32-bit or 48-bit pointer (16/32-bit offset and 16-bit segment). Available in 32-bit and 64-bit modes. No flags are affected.", "pseudocode": "dest ← [src];\nFS ← [src + operand_size];", "example": "LFS rax, [rbp-8]"} {"mnemonic": "lgs", "architecture": "x86", "full_name": "Load Far Pointer using GS", "summary": "Loads pointer into GS and register.", "syntax": "LGS r, m", "encoding": {"format": "Legacy", "hex_opcode": "0F B5", "visual_parts": [], "binary_pattern": "0F | B5", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r", "desc": "General-purpose register"}, {"name": "src", "type": "m", "desc": "Memory operand"}], "description": "Loads a far pointer from memory into a general-purpose register and the GS segment register. The memory operand contains a 32-bit or 48-bit pointer (16/32-bit offset and 16-bit segment). Available in 32-bit and 64-bit modes. No flags are affected.", "pseudocode": "dest ← [src];\nGS ← [src + operand_size];", "example": "LGS rax, [rbp-8]"} {"mnemonic": "lss", "architecture": "x86", "full_name": "Load Far Pointer using SS", "summary": "Loads pointer into SS and register.", "syntax": "LSS r, m", "encoding": {"format": "Legacy", "hex_opcode": "0F B2", "visual_parts": [], "binary_pattern": "0F | B2", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r", "desc": "General-purpose register"}, {"name": "src", "type": "m", "desc": "Memory operand"}], "description": "Loads a 48-bit or 80-bit far pointer from memory into SS and a general-purpose register, updating the stack segment base address and register value simultaneously. The memory operand contains the offset and segment selector; the segment is loaded into SS and the offset into the destination register. This instruction does not modify any flags and is available in real, protected, and 64-bit modes.", "pseudocode": "if (operand_size == 32) {\n offset ← [src];\n SS ← [src + 4];\n dest ← offset;\n} else if (operand_size == 64) {\n offset ← [src];\n SS ← [src + 8];\n dest ← offset;\n}", "example": "LSS rax, [rbp-8]"} {"mnemonic": "swapgs", "architecture": "x86", "full_name": "Swap GS Base Register", "summary": "Swaps user/kernel GS base address (System).", "syntax": "SWAPGS", "encoding": {"format": "Legacy", "hex_opcode": "0F 01 F8", "visual_parts": [], "binary_pattern": "0F | 01 | F8", "bit_positions": "+0 | +1 | +2"}, "extension": "Base (64-bit System)", "operands": [], "description": "Atomically exchanges the user-mode and kernel-mode FS base register values by swapping the contents of the MSR_FS_BASE and MSR_KERNEL_FS_BASE model-specific registers. This is a 64-bit only instruction used for efficient user/kernel context switching in system software. No flags are modified, and the operation serializes the instruction pipeline.", "pseudocode": "if (CODESIZE == 64 && CPL == 0) {\n temp ← MSR_FS_BASE;\n MSR_FS_BASE ← MSR_KERNEL_FS_BASE;\n MSR_KERNEL_FS_BASE ← temp;\n}", "example": "SWAPGS"} {"mnemonic": "rdfsbase", "architecture": "x86", "full_name": "Read FS Base", "summary": "Reads the FS base address into a register.", "syntax": "RDFSBASE r64", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F AE /0", "visual_parts": [], "binary_pattern": "F3 | 0F | AE | ModRM", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "FSGSBASE", "operands": [{"name": "dest", "type": "r64", "desc": "64-bit general-purpose register (e.g. RAX)"}], "description": "Reads the current FS segment base address (from MSR_FS_BASE) into a 64-bit general-purpose register. Available only in 64-bit mode and requires the FSGSBASE CPU feature to be enabled. No flags are modified; the instruction executes with serialization semantics to ensure consistency of segment-base state.", "pseudocode": "if (FSGSBASE_enabled) {\n dest ← MSR_FS_BASE;\n} else {\n raise(UD_EXCEPTION);\n}", "example": "RDFSBASE rax"} {"mnemonic": "rdgsbase", "architecture": "x86", "full_name": "Read GS Base", "summary": "Reads the GS base address into a register.", "syntax": "RDGSBASE r64", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F AE /1", "visual_parts": [], "binary_pattern": "F3 | 0F | AE | ModRM", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "FSGSBASE", "operands": [{"name": "dest", "type": "r64", "desc": "64-bit general-purpose register (e.g. RAX)"}], "description": "Reads the current GS segment base address (from MSR_GS_BASE) into a 64-bit general-purpose register. Available only in 64-bit mode and requires the FSGSBASE CPU feature to be enabled. No flags are modified; the instruction executes with serialization semantics to ensure consistency of segment-base state.", "pseudocode": "if (FSGSBASE_enabled) {\n dest ← MSR_GS_BASE;\n} else {\n raise(UD_EXCEPTION);\n}", "example": "RDGSBASE rax"} {"mnemonic": "wrfsbase", "architecture": "x86", "full_name": "Write FS Base", "summary": "Writes a register to the FS base address.", "syntax": "WRFSBASE r64", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F AE /2", "visual_parts": [], "binary_pattern": "F3 | 0F | AE | ModRM", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "FSGSBASE", "operands": [{"name": "dest", "type": "r64", "desc": "64-bit general-purpose register (e.g. RAX)"}], "description": "Writes the value from a 64-bit general-purpose register into the FS segment base address (MSR_FS_BASE). Available only in 64-bit mode and requires the FSGSBASE CPU feature to be enabled. No flags are modified; the instruction executes with serialization semantics to ensure consistency of segment-base state.", "pseudocode": "if (FSGSBASE_enabled) {\n MSR_FS_BASE ← dest;\n} else {\n raise(UD_EXCEPTION);\n}", "example": "WRFSBASE rax"} {"mnemonic": "wrgsbase", "architecture": "x86", "full_name": "Write GS Base", "summary": "Writes a register to the GS base address.", "syntax": "WRGSBASE r64", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F AE /3", "visual_parts": [], "binary_pattern": "F3 | 0F | AE | ModRM", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "FSGSBASE", "operands": [{"name": "dest", "type": "r64", "desc": "64-bit general-purpose register (e.g. RAX)"}], "description": "Writes the value from a 64-bit general-purpose register into the GS segment base address (MSR_GS_BASE). Available only in 64-bit mode and requires the FSGSBASE CPU feature to be enabled. No flags are modified; the instruction executes with serialization semantics to ensure consistency of segment-base state.", "pseudocode": "if (FSGSBASE_enabled) {\n MSR_GS_BASE ← src;\n} else {\n raise(UD_EXCEPTION);\n}", "example": "WRGSBASE rax"} {"mnemonic": "monitor", "architecture": "x86", "full_name": "Monitor", "summary": "Sets up a linear address range to be monitored.", "syntax": "MONITOR", "encoding": {"format": "Legacy", "hex_opcode": "0F 01 C8", "visual_parts": [], "binary_pattern": "0F | 01 | C8", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE3", "operands": [], "description": "Establishes a linear address range starting at [RAX] with a size specified by ECX (in bytes) to be monitored for writes by the CPU. The EAX and ECX registers supply the monitor address and size; EDX supplies optional extensions. No flags are modified. This instruction typically requires CPL ≤ 1 (ring 0/1) and is used with MWAIT for efficient polling.", "pseudocode": "if (CPL <= 1 || (CR4.MONITOR_BIT && CPL == 3)) {\n MONITOR_ADDR ← RAX;\n MONITOR_SIZE ← ECX;\n MONITOR_EXT ← EDX;\n set_up_address_range_monitoring();\n} else {\n raise(GP_EXCEPTION);\n}", "example": "MONITOR"} {"mnemonic": "mwait", "architecture": "x86", "full_name": "Monitor Wait", "summary": "Waits for a write to a monitored address.", "syntax": "MWAIT", "encoding": {"format": "Legacy", "hex_opcode": "0F 01 C9", "visual_parts": [], "binary_pattern": "0F | 01 | C9", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE3", "operands": [], "description": "Suspends CPU execution and waits for a write to an address range that was previously set up by MONITOR, or waits for an interrupt or other wake event. The EAX register specifies the monitor sub-C-state (low byte) and optional extensions (high bytes); EBX may specify additional parameters depending on CPU model. No flags are modified. This instruction serializes the processor and is typically restricted to CPL ≤ 1.", "pseudocode": "if (CPL <= 1 || (CR4.MONITOR_BIT && CPL == 3)) {\n substate ← EAX[7:0];\n extensions ← EAX[31:8];\n enter_monitor_wait(substate, extensions);\n wait_for_wakeup_or_interrupt();\n} else {\n raise(GP_EXCEPTION);\n}", "example": "MWAIT"} {"mnemonic": "getsec", "architecture": "x86", "full_name": "Get Security Extensions", "summary": "Entry point for Safer Mode Extensions (Trusted Execution).", "syntax": "GETSEC", "encoding": {"format": "Legacy", "hex_opcode": "NP 0F 37", "visual_parts": [], "binary_pattern": "0F | 37", "bit_positions": "+0 | +1"}, "extension": "SMX", "operands": [], "description": "Entry point for Safer Mode Extensions (SMX), allowing software to invoke security functions in trusted execution mode. The specific function is determined by the EAX register at execution time. This instruction serializes the pipeline, disables interrupts during execution, and requires either SMX mode to be enabled or execution from authenticated code. On success, control returns to the instruction following GETSEC; on failure or security violation, a #UD or system reset may occur.", "pseudocode": "// EAX contains function code (e.g., GETSEC.CAPABILITIES=0, GETSEC.ENTERACCS=2, etc.)\n// Execution is serialized; interrupts disabled during SMX operation\nIF (SMX_mode_enabled OR authenticated_code_execution_mode) THEN\n Invoke_SMX_function(EAX);\n // Control returns here on success\nELSE\n #UD; // Undefined Opcode fault\nEND;", "example": "GETSEC"} {"mnemonic": "bndmk", "architecture": "x86", "full_name": "Make Bounds", "summary": "Creates bounds data for MPX.", "syntax": "BNDMK b, m", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F 1B", "visual_parts": [], "binary_pattern": "F3 | 0F | 1B", "bit_positions": "+0 | +1 | +2"}, "extension": "MPX", "operands": [{"name": "dest", "type": "b", "desc": "MPX bounds register (bnd0-bnd3)"}, {"name": "src", "type": "m", "desc": "Memory operand"}], "description": "Creates a bounds pair from a memory address range, storing the lower bound and upper bound in the destination bounds register (bnd0-bnd3). The source memory operand specifies an address; the instruction computes bounds from memory operand addressing. No flags are set. This instruction is part of Memory Protection Extensions (MPX) and is deprecated on modern processors.", "pseudocode": "// Compute bounds from memory operand m\n// The bounds are derived from the addressing operation itself\nlower_bound ← compute_lower_bound(m);\nupper_bound ← compute_upper_bound(m);\n// Store in 128-bit bounds register (2×64-bit values)\nbndN.lower ← lower_bound;\nbndN.upper ← upper_bound;", "example": "BNDMK b, [rbp-8]"} {"mnemonic": "bndcl", "architecture": "x86", "full_name": "Check Lower Bound", "summary": "Checks if address is within lower bound.", "syntax": "BNDCL b, r/m", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F 1A", "visual_parts": [], "binary_pattern": "F3 | 0F | 1A", "bit_positions": "+0 | +1 | +2"}, "extension": "MPX", "operands": [{"name": "dest", "type": "b", "desc": "MPX bounds register (bnd0-bnd3)"}, {"name": "src", "type": "r/m", "desc": "Register or memory operand"}], "description": "Checks if an address or value is greater than or equal to the lower bound stored in the bounds register; if not, a bounds exception (#BR) is signaled. The source operand (register or memory) contains the address to be checked against bndN.lower. No flags are modified; an out-of-bounds condition triggers exception delivery. This instruction is part of deprecated Memory Protection Extensions (MPX).", "pseudocode": "address ← (src is memory) ? load_from_memory(src) : src;\nIF (address < bndN.lower) THEN\n #BR; // Bounds Range Exceeded exception\nEND;\n// No flags modified; execution continues on success", "example": "BNDCL b, rbx"} {"mnemonic": "bndcu", "architecture": "x86", "full_name": "Check Upper Bound", "summary": "Checks if address is within upper bound.", "syntax": "BNDCU b, r/m", "encoding": {"format": "Legacy", "hex_opcode": "F2 0F 1A", "visual_parts": [], "binary_pattern": "F2 | 0F | 1A", "bit_positions": "+0 | +1 | +2"}, "extension": "MPX", "operands": [{"name": "dest", "type": "b", "desc": "MPX bounds register (bnd0-bnd3)"}, {"name": "src", "type": "r/m", "desc": "Register or memory operand"}], "description": "Checks if an address or value is less than or equal to the upper bound stored in the bounds register; if not, a bounds exception (#BR) is signaled. The source operand (register or memory) contains the address to be checked against bndN.upper. No flags are modified; an out-of-bounds condition triggers exception delivery. This instruction is part of deprecated Memory Protection Extensions (MPX).", "pseudocode": "address ← (src is memory) ? load_from_memory(src) : src;\nIF (address > bndN.upper) THEN\n #BR; // Bounds Range Exceeded exception\nEND;\n// No flags modified; execution continues on success", "example": "BNDCU b, rbx"} {"mnemonic": "bndmov", "architecture": "x86", "full_name": "Move Bounds", "summary": "Moves MPX bounds data.", "syntax": "BNDMOV b, b/m", "encoding": {"format": "Legacy", "hex_opcode": "66 0F 1A", "visual_parts": [], "binary_pattern": "66 | 0F | 1A", "bit_positions": "+0 | +1 | +2"}, "extension": "MPX", "operands": [{"name": "dest", "type": "b", "desc": "MPX bounds register (bnd0-bnd3)"}, {"name": "src", "type": "b/m", "desc": "Memory operand"}], "description": "Moves a 128-bit bounds pair from source (bounds register or memory) to destination (bounds register). The bounds pair consists of two 64-bit values (lower and upper bounds). No flags are set or modified. This instruction is part of deprecated Memory Protection Extensions (MPX) and is one of the few instructions that operate directly on bounds data.", "pseudocode": "// Source can be bounds register or 16 bytes of memory\nIF (src is bounds register) THEN\n bndN.lower ← src.lower;\n bndN.upper ← src.upper;\nELSE\n bndN.lower ← [src];\n bndN.upper ← [src + 8];\nEND;\n// No flags modified", "example": "BNDMOV b, b/m"} {"mnemonic": "rdpkru", "architecture": "x86", "full_name": "Read Protection Key Rights", "summary": "Reads PKRU register into EAX (User-mode pages).", "syntax": "RDPKRU", "encoding": {"format": "Legacy", "hex_opcode": "NP 0F 01 EE", "visual_parts": [], "binary_pattern": "0F | 01 | EE", "bit_positions": "+0 | +1 | +2"}, "extension": "PKU", "operands": [], "description": "Reads the Protection Key Rights User register (PKRU) into EAX; EDX is zeroed. PKRU controls read and write access permissions for pages marked with a protection key (0-15). This instruction is a serializing operation at the architectural level and is only available in 64-bit mode and user mode (CPL=3). No flags are modified by this instruction.", "pseudocode": "// Read PKRU into EAX, zero EDX\nEAX ← PKRU;\nEDX ← 0;\n// No flags modified; instruction is serializing", "example": "RDPKRU"} {"mnemonic": "wrpkru", "architecture": "x86", "full_name": "Write Protection Key Rights", "summary": "Writes EAX/EDX to PKRU register.", "syntax": "WRPKRU", "encoding": {"format": "Legacy", "hex_opcode": "NP 0F 01 EF", "visual_parts": [], "binary_pattern": "0F | 01 | EF", "bit_positions": "+0 | +1 | +2"}, "extension": "PKU", "operands": [], "description": "Writes the value in EAX to the Protection Key Rights User register (PKRU); EDX must be zero. PKRU controls read/write access permissions for pages with protection keys (0-15). This instruction is a serializing operation and is available only in 64-bit mode at user mode (CPL=3). No flags are set; if EDX is nonzero, #GP(0) is raised.", "pseudocode": "// Write EAX to PKRU, EDX must be zero\nIF (EDX ≠ 0) THEN\n #GP(0); // General Protection Fault\nELSE\n PKRU ← EAX;\nEND;\n// No flags modified; instruction is serializing", "example": "WRPKRU"} {"mnemonic": "vpdpbusd", "architecture": "x86", "full_name": "Multiply and Add Unsigned and Signed Bytes", "summary": "Dot product of unsigned/signed bytes, accum to dword.", "syntax": "VPDPBUSD zmm1, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W0 50 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 50", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512-VNNI", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Performs a dot product of unsigned 8-bit and signed 8-bit integers across multiple pairs, accumulating the results into 32-bit dwords. Processes 512 bits (64 bytes) with 16 sets of 4-byte dot products (zmm2[31:0] × zmm3[31:0] + zmm1[31:0]), with masking and rounding support via EVEX encoding. ZF, PF, CF, OF, SF, AF are undefined after execution; no integer flags are modified.", "pseudocode": "// VPDPBUSD zmm1{k1}{z}, zmm2, zmm3/m512\n// Signed 8×4 dot products with 32-bit accumulation\nFOR i ← 0 TO 15 DO // 16 dwords in 512-bit vector\n prod0 ← (unsigned int8) zmm2[i*32 + 7:0] × (signed int8) zmm3[i*32 + 7:0];\n prod1 ← (unsigned int8) zmm2[i*32 + 15:8] × (signed int8) zmm3[i*32 + 15:8];\n prod2 ← (unsigned int8) zmm2[i*32 + 23:16] × (signed int8) zmm3[i*32 + 23:16];\n prod3 ← (unsigned int8) zmm2[i*32 + 31:24] × (signed int8) zmm3[i*32 + 31:24];\n sum ← prod0 + prod1 + prod2 + prod3;\n zmm1[i*32 + 31:0] ← zmm1[i*32 + 31:0] + sum; // Accumulate\nEND;\n// Masking and zeroing applied per EVEX encoding; no flags modified", "example": "VPDPBUSD zmm1, zmm2, zmm3/m512"} {"mnemonic": "vpdpbusds", "architecture": "x86", "full_name": "Multiply and Add Unsigned and Signed Bytes with Saturation", "summary": "Dot product of unsigned/signed bytes, accum to dword (Saturate).", "syntax": "VPDPBUSDS zmm1, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W0 51 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 51", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512-VNNI", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Computes dot product of unsigned and signed bytes, accumulating results into 32-bit signed integers with saturation. Processes 16 pairs of (unsigned byte × signed byte) products per 512-bit vector, summing each group of 4 products and saturating the result to the signed 32-bit range. No flags are affected; operates only on vector registers and memory.", "pseudocode": "for i in 0 to 15 {\n prod0 = ZeroExtend(src1[i*32+0:7]) * SignExtend(src2[i*32+0:7]);\n prod1 = ZeroExtend(src1[i*32+8:15]) * SignExtend(src2[i*32+8:15]);\n prod2 = ZeroExtend(src1[i*32+16:23]) * SignExtend(src2[i*32+16:23]);\n prod3 = ZeroExtend(src1[i*32+24:31]) * SignExtend(src2[i*32+24:31]);\n sum = prod0 + prod1 + prod2 + prod3;\n dest[i*32:31] ← SaturateSignedToS32(sum);\n}", "example": "VPDPBUSDS zmm1, zmm2, zmm3/m512"} {"mnemonic": "vpdpwssd", "architecture": "x86", "full_name": "Multiply and Add Signed Words", "summary": "Dot product of signed words, accum to dword.", "syntax": "VPDPWSSD zmm1, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W0 52 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 52", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512-VNNI", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Computes dot product of signed 16-bit words, accumulating results into 32-bit signed integers without saturation. Processes 8 pairs of signed word products per 512-bit vector, summing each group of 2 products and storing the result to the destination. No flags are affected; operates only on vector registers and memory.", "pseudocode": "for i in 0 to 7 {\n prod0 = SignExtend(src1[i*32+0:15]) * SignExtend(src2[i*32+0:15]);\n prod1 = SignExtend(src1[i*32+16:31]) * SignExtend(src2[i*32+16:31]);\n sum = prod0 + prod1;\n dest[i*32:31] ← sum;\n}", "example": "VPDPWSSD zmm1, zmm2, zmm3/m512"} {"mnemonic": "vpdpwssds", "architecture": "x86", "full_name": "Multiply and Add Signed Words with Saturation", "summary": "Dot product of signed words, accum to dword (Saturate).", "syntax": "VPDPWSSDS zmm1, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W0 53 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 53", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512-VNNI", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Computes dot product of signed 16-bit words, accumulating results into 32-bit signed integers with saturation. Processes 8 pairs of signed word products per 512-bit vector, summing each group of 2 products and saturating the result to the signed 32-bit range. No flags are affected; operates only on vector registers and memory.", "pseudocode": "for i in 0 to 7 {\n prod0 = SignExtend(src1[i*32+0:15]) * SignExtend(src2[i*32+0:15]);\n prod1 = SignExtend(src1[i*32+16:31]) * SignExtend(src2[i*32+16:31]);\n sum = prod0 + prod1;\n dest[i*32:31] ← SaturateSignedToS32(sum);\n}", "example": "VPDPWSSDS zmm1, zmm2, zmm3/m512"} {"mnemonic": "gf2p8affineinvqb", "architecture": "x86", "full_name": "Galois Field Affine Transformation Inverse", "summary": "Computes inverse affine transformation in GF(2^8).", "syntax": "GF2P8AFFINEINVQB xmm1, xmm2/m128, imm8", "encoding": {"format": "VEX", "hex_opcode": "66 0F 3A CF /r ib", "visual_parts": [], "binary_pattern": "66 | 0F | 3A | CF", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "GFNI", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Performs inverse affine transformation in the Galois Field GF(2^8) on 128-bit packed bytes. Each byte is transformed by computing b × src1 ⊕ imm8 where operations are in GF(2^8), with b from the first operand. The immediate byte controls the constant term of the affine transformation. No flags are affected; operates only on vector registers and memory.", "pseudocode": "for i in 0 to 15 {\n byte_val = dest[i*8:7];\n gf_prod = GF2P8_MultiplyInverse(byte_val, src1[i*8:7]);\n dest[i*8:7] ← gf_prod ⊕ imm8;\n}", "example": "GF2P8AFFINEINVQB xmm1, xmm2/m128, 3"} {"mnemonic": "prefetchw", "architecture": "x86", "full_name": "Prefetch Data into Caches in Anticipation of a Write", "summary": "Prefetches data with intent to write (RFO).", "syntax": "PREFETCHW m8", "encoding": {"format": "Legacy", "hex_opcode": "0F 0D /1", "visual_parts": [], "binary_pattern": "0F | 0D | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "PREFETCHW", "operands": [{"name": "dest", "type": "m8", "desc": "8-bit memory operand"}], "description": "Prefetches a cache line from memory with intent to write, requesting read-for-ownership (RFO) semantics. Brings the data into the lowest-level private cache (typically L1D) in exclusive or modified state to optimize subsequent write operations. This instruction is a hint and has no architectural effect on registers, flags, or memory contents.", "pseudocode": "// Prefetch memory address for writing (RFO semantics)\nCachePrefetchForWrite([mem_address]);", "example": "PREFETCHW [rbp-1]"} {"mnemonic": "prefetchwt1", "architecture": "x86", "full_name": "Prefetch Hint T1 with Intent to Write", "summary": "Prefetches data to L2 (T1 hint) with intent to write.", "syntax": "PREFETCHWT1 m8", "encoding": {"format": "Legacy", "hex_opcode": "0F 0D /2", "visual_parts": [], "binary_pattern": "0F | 0D | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "PREFETCHWT1", "operands": [{"name": "dest", "type": "m8", "desc": "8-bit memory operand"}], "description": "Prefetches a cache line from memory with intent to write into the L2 cache (T1 hint). Optimizes for temporal locality by loading data into the mid-level cache hierarchy rather than L1, reducing contention when multiple cores are writing to different addresses. This instruction is a hint and has no architectural effect on registers, flags, or memory contents.", "pseudocode": "// Prefetch memory address to L2 (T1 hint) with write intent\nCachePrefetchToL2ForWrite([mem_address]);", "example": "PREFETCHWT1 [rbp-1]"} {"mnemonic": "vscatterdps", "architecture": "x86", "full_name": "Scatter Packed Single Precision", "summary": "Stores floats to non-contiguous memory locations.", "syntax": "VSCATTERDPS [base+zmm_idx*scale] {k1}, zmm1", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W0 A2 /vsib", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | A2", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "[base+zmm_idx*scale]", "desc": "AVX-512 scatter: base register + scaled ZMM vector index"}, {"name": "src", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}], "description": "Stores 16 packed single-precision floats (32-bit each) to non-contiguous memory locations determined by a base register and 32-bit ZMM index vector with optional scaling. Each element is stored to memory[base + index[i] × scale] where the index is zero-extended from the low 32 bits of each 64-bit ZMM element. The operation is masked via the k1 writemask; no flags are affected.", "pseudocode": "for i in 0 to 15 {\n if k1[i] {\n addr = base_reg + ZeroExtend(src2_idx[i*32:31]) * scale;\n [addr] ← src1[i*32:31];\n }\n}", "example": "VSCATTERDPS [base+zmm_idx*scale], zmm1"} {"mnemonic": "vscatterdpd", "architecture": "x86", "full_name": "Scatter Packed Double Precision", "summary": "Stores doubles to non-contiguous memory locations.", "syntax": "VSCATTERDPD [base+zmm_idx*scale] {k1}, zmm1", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W1 A2 /vsib", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | A2", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "[base+zmm_idx*scale]", "desc": "AVX-512 scatter: base register + scaled ZMM vector index"}, {"name": "src", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}], "description": "Stores 8 packed double-precision floats (64-bit each) to non-contiguous memory locations determined by a base register and 64-bit ZMM index vector with optional scaling. Each element is stored to memory[base + index[i] × scale] where the index comes from the corresponding 64-bit ZMM element. The operation is masked via the k1 writemask; no flags are affected.", "pseudocode": "for i in 0 to 7 {\n if k1[i] {\n addr = base_reg + src2_idx[i*64:63] * scale;\n [addr] ← src1[i*64:63];\n }\n}", "example": "VSCATTERDPD [base+zmm_idx*scale], zmm1"} {"mnemonic": "vscatterqps", "architecture": "x86", "full_name": "Scatter Packed Single Precision (Quadword Indices)", "summary": "Stores floats using 64-bit indices.", "syntax": "VSCATTERQPS [base+zmm_idx*scale] {k1}, zmm1", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W0 A3 /vsib", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | A3", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "[base+zmm_idx*scale]", "desc": "AVX-512 scatter: base register + scaled ZMM vector index"}, {"name": "src", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}], "description": "Scatters packed single-precision (32-bit) floating-point values from a ZMM register to memory using 64-bit quadword indices with optional scaling. Each element in the source ZMM is written to a memory location computed as [base + index[i]*scale], with write masking controlled by the opmask register k1. This is a non-temporal scatter operation that does not update CPU flags.", "pseudocode": "for i in 0 to 7:\n if k1[i] == 1:\n addr ← base + sign_extend(zmm_idx[i]) * scale\n [addr] ← src.f32[i]", "example": "VSCATTERQPS [base+zmm_idx*scale], zmm1"} {"mnemonic": "vscatterqpd", "architecture": "x86", "full_name": "Scatter Packed Double Precision (Quadword Indices)", "summary": "Stores doubles using 64-bit indices.", "syntax": "VSCATTERQPD [base+zmm_idx*scale] {k1}, zmm1", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W1 A3 /vsib", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | A3", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "[base+zmm_idx*scale]", "desc": "AVX-512 scatter: base register + scaled ZMM vector index"}, {"name": "src", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}], "description": "Scatters packed double-precision (64-bit) floating-point values from a ZMM register to memory using 64-bit quadword indices with optional scaling. Each element in the source ZMM is written to a memory location computed as [base + index[i]*scale], with write masking controlled by the opmask register k1. This is a non-temporal scatter operation that does not update CPU flags.", "pseudocode": "for i in 0 to 3:\n if k1[i] == 1:\n addr ← base + sign_extend(zmm_idx[i]) * scale\n [addr] ← src.f64[i]", "example": "VSCATTERQPD [base+zmm_idx*scale], zmm1"} {"mnemonic": "vfpclassps", "architecture": "x86", "full_name": "Floating-Point Class Single", "summary": "Tests for category (NaN, Inf, Denormal) for floats.", "syntax": "VFPCLASSPS k1 {k2}, zmm2/m512, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F3A.W0 66 /r ib", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 3A | 66", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512DQ", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "zmm2/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Tests each single-precision float in the source operand against a class mask (imm8) and sets the corresponding bit in the destination opmask register. The mask specifies FP classes: positive/negative zero, denormal, normal, infinity, and quiet/signaling NaN. The operation is merged or zeroed based on the opmask k2; no arithmetic flags are affected.", "pseudocode": "for i in 0 to 15:\n if k2[i] == 1 or k2_merge_mode == 0:\n class_bits ← classify_fp32(src[i])\n k1[i] ← (imm8 & (1 << class_bits)) != 0\n else:\n k1[i] ← 0", "example": "VFPCLASSPS k1, zmm2/m512, 3"} {"mnemonic": "vfpclasspd", "architecture": "x86", "full_name": "Floating-Point Class Double", "summary": "Tests for category (NaN, Inf, Denormal) for doubles.", "syntax": "VFPCLASSPD k1 {k2}, zmm2/m512, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F3A.W1 66 /r ib", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 3A | 67", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512DQ", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "zmm2/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Tests each double-precision float in the source operand against a class mask (imm8) and sets the corresponding bit in the destination opmask register. The mask specifies FP classes: positive/negative zero, denormal, normal, infinity, and quiet/signaling NaN. The operation is merged or zeroed based on the opmask k2; no arithmetic flags are affected.", "pseudocode": "for i in 0 to 7:\n if k2[i] == 1 or k2_merge_mode == 0:\n class_bits ← classify_fp64(src[i])\n k1[i] ← (imm8 & (1 << class_bits)) != 0\n else:\n k1[i] ← 0", "example": "VFPCLASSPD k1, zmm2/m512, 3"} {"mnemonic": "vrangeps", "architecture": "x86", "full_name": "Range Restriction Calculation Packed Single", "summary": "Calculates range (min/max/abs) of float values.", "syntax": "VRANGEPS zmm1 {k1}, zmm2, zmm3/m512, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F3A.W0 50 /r ib", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 3A | 50", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512DQ", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}, {"name": "src3", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Computes range restrictions on packed single-precision floats by selecting minimum, maximum, or absolute value operations controlled by an immediate operand. The result is the restricted range of two input operands after applying the imm8-controlled transformation. Results are merged or zeroed to the destination based on the opmask k1; no arithmetic flags are set.", "pseudocode": "for i in 0 to 15:\n if k1[i] == 1 or k1_merge_mode == 0:\n val1 ← src1.f32[i]\n val2 ← src2.f32[i]\n transformed ← apply_range_transform(val1, val2, imm8[2:0])\n dest.f32[i] ← transformed\n else:\n dest.f32[i] ← 0", "example": "VRANGEPS zmm1, zmm2, zmm3/m512, 3"} {"mnemonic": "vreduceps", "architecture": "x86", "full_name": "Perform Reduction Transformation Packed Single", "summary": "Performs reduction on floats (e.g. range reduction for trig).", "syntax": "VREDUCEPS zmm1 {k1}, zmm2/m512, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F3A.W0 56 /r ib", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 3A | 56", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512DQ", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Performs reduction transformations (e.g., range reduction for trigonometric functions) on packed single-precision floats. The imm8 operand selects the reduction mode and rounding behavior. The transformed values are written to the destination with masking controlled by opmask k1; no arithmetic flags are affected.", "pseudocode": "for i in 0 to 15:\n if k1[i] == 1 or k1_merge_mode == 0:\n result ← apply_reduction(src.f32[i], imm8[2:0])\n dest.f32[i] ← result_with_rounding(result, imm8[7:4])\n else:\n dest.f32[i] ← 0", "example": "VREDUCEPS zmm1, zmm2/m512, 3"} {"mnemonic": "vfixupimmps", "architecture": "x86", "full_name": "Fix Up Special Packed Float32 Values", "summary": "Fixes special cases (NaN, Inf) using a table (Float32).", "syntax": "VFIXUPIMMPS zmm1 {k1}, zmm2, zmm3/m512, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F3A.W0 54 /r ib", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 3A | 54", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}, {"name": "src3", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Fixes special floating-point cases (NaN, infinity, denormal) in packed single-precision data using a lookup table indexed by the immediate operand. The first source operand provides the primary value, the second provides a backup value for special cases, and the imm8 configures the fixup behavior. Results are masked by k1; no arithmetic flags are affected.", "pseudocode": "for i in 0 to 15:\n if k1[i] == 1 or k1_merge_mode == 0:\n primary ← src1.f32[i]\n backup ← src2.f32[i]\n fixup_class ← classify_special_fp32(primary)\n if is_special(fixup_class):\n dest.f32[i] ← lookup_fixup_table(backup, fixup_class, imm8)\n else:\n dest.f32[i] ← primary\n else:\n dest.f32[i] ← 0", "example": "VFIXUPIMMPS zmm1, zmm2, zmm3/m512, 3"} {"mnemonic": "vrsqrt14ps", "architecture": "x86", "full_name": "Compute Approximate Reciprocal Square Root (14-bit)", "summary": "Approximate 1/sqrt(x) with 2^-14 error.", "syntax": "VRSQRT14PS zmm1 {k1}, zmm2/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W0 4E /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 4E", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src", "type": "zmm2/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Computes approximate reciprocal square root (1/√x) with 2^-14 relative error for packed single-precision floats. This fast approximation is suitable for iterative refinement or low-precision applications. Results are merged or zeroed to the destination based on opmask k1; no arithmetic flags are affected.", "pseudocode": "for i in 0 to 15:\n if k1[i] == 1 or k1_merge_mode == 0:\n dest.f32[i] ← approx_rsqrt14(src.f32[i])\n else:\n dest.f32[i] ← 0", "example": "VRSQRT14PS zmm1, zmm2/m512"} {"mnemonic": "vrcp14ps", "architecture": "x86", "full_name": "Compute Approximate Reciprocal (14-bit)", "summary": "Approximate 1/x with 2^-14 error.", "syntax": "VRCP14PS zmm1 {k1}, zmm2/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W0 4C /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 4C", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src", "type": "zmm2/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Computes a 14-bit reciprocal approximation (1/x) for each single-precision float in the source operand, writing results to the destination with a maximum relative error of 2^-14. The instruction operates on 512-bit vectors (16 × 32-bit floats) in AVX-512, supports writemask control via k1, and sets no CPU flags. Denormalized inputs produce denormalized outputs; NaN, zero, and infinity operands behave according to IEEE 754 semantics.", "pseudocode": "for i = 0 to 15:\n if k1[i] or no mask:\n zmm1[32*i+31:32*i] ← approximate_reciprocal_14bit(zmm2/m512[32*i+31:32*i])\n else if zeroing:\n zmm1[32*i+31:32*i] ← 0", "example": "VRCP14PS zmm1, zmm2/m512"} {"mnemonic": "clui", "architecture": "x86", "full_name": "Clear User Interrupt Flag", "summary": "Clears the User Interrupt Flag (UIF).", "syntax": "CLUI", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F 01 EE", "visual_parts": [], "binary_pattern": "F3 | 0F | 01 | EE", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "UINTR", "operands": [], "description": "Clears the User Interrupt Flag (UIF) in the UINTR register, preventing delivery of user-level interrupts to the current process. This is a privileged-equivalent instruction that requires the UINTR CPU feature and operates only in user mode; it has no effect on standard CPU flags or other processor state. Execution in a context where UINTR is unavailable causes a #UD exception.", "pseudocode": "UINTR.UIF ← 0", "example": "CLUI"} {"mnemonic": "stui", "architecture": "x86", "full_name": "Set User Interrupt Flag", "summary": "Sets the User Interrupt Flag (UIF).", "syntax": "STUI", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F 01 EF", "visual_parts": [], "binary_pattern": "F3 | 0F | 01 | EF", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "UINTR", "operands": [], "description": "Sets the User Interrupt Flag (UIF) in the UINTR register, enabling delivery of user-level interrupts to the current process. This is a privileged-equivalent instruction that requires the UINTR CPU feature and operates only in user mode; it modifies no standard CPU flags. Execution in a context where UINTR is unavailable causes a #UD exception.", "pseudocode": "UINTR.UIF ← 1", "example": "STUI"} {"mnemonic": "testui", "architecture": "x86", "full_name": "Test User Interrupt", "summary": "Sets CF if UIF is 1, ZF if User Interrupt Pending.", "syntax": "TESTUI", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F 01 ED", "visual_parts": [], "binary_pattern": "F3 | 0F | 01 | ED", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "UINTR", "operands": [], "description": "Tests the User Interrupt Flag (UIF) and User Interrupt Pending (UIP) status, setting CF if UIF is 1 and ZF if a user interrupt is pending. This instruction requires the UINTR CPU feature and operates only in user mode; it does not modify other flags. Execution without UINTR support causes a #UD exception.", "pseudocode": "CF ← UINTR.UIF\nZF ← UINTR.UIP\nOF ← 0\nSF ← 0\nAF ← 0\nPF ← 0", "example": "TESTUI"} {"mnemonic": "fld", "architecture": "x86", "full_name": "Load Floating Point Value", "summary": "Pushes a floating-point value onto the FPU register stack (ST0).", "syntax": "FLD m32fp/m64fp/m80fp", "encoding": {"format": "Legacy", "hex_opcode": "D9 /0", "length": "2+", "visual_parts": [], "binary_pattern": "D9 | ModRM", "bit_positions": "+0 | +1"}, "operands": [{"name": "src", "desc": "Memory"}], "extension": "x87 FPU", "description": "Loads a floating-point value (32-bit single, 64-bit double, or 80-bit extended precision) from memory, converts if necessary to 80-bit extended precision, and pushes it onto the x87 FPU register stack (ST(0)). Stack pointer (TOP) is decremented by one; overflow to an invalid slot raises #IS (stack fault). No CPU flags are modified; the instruction may set x87 exception flags (PE, UE, OE, IE) in the x87 status word.", "pseudocode": "ST(0) ← load_and_convert(memory)\nTOP ← TOP - 1\nif TOP underflow: raise x87_stack_fault", "example": "FLD m32fp/m64fp/m80fp"} {"mnemonic": "fst", "architecture": "x86", "full_name": "Store Floating Point Value", "summary": "Copies the value in ST(0) to memory or another register.", "syntax": "FST m32fp/m64fp", "encoding": {"format": "Legacy", "hex_opcode": "D9 /2", "length": "2+", "visual_parts": [], "binary_pattern": "D9 | ModRM", "bit_positions": "+0 | +1"}, "operands": [{"name": "dest", "desc": "Memory"}], "extension": "x87 FPU", "description": "Stores the value in ST(0) to memory as either 32-bit single or 64-bit double precision (converting from 80-bit extended if necessary), without popping the stack. The source remains in ST(0); floating-point exceptions (PE, UE, OE) may be raised in the x87 status word if conversion underflows, overflows, or loses precision. No CPU flags are modified.", "pseudocode": "memory ← convert_to_32or64bit(ST(0))\nif conversion_error: raise x87_exception", "example": "FST m32fp/m64fp"} {"mnemonic": "fstp", "architecture": "x86", "full_name": "Store Floating Point Value and Pop", "summary": "Copies ST(0) to destination and pops the register stack.", "syntax": "FSTP m32fp/m64fp/m80fp", "encoding": {"format": "Legacy", "hex_opcode": "D9 /3", "length": "2+", "visual_parts": [], "binary_pattern": "D9 | ModRM", "bit_positions": "+0 | +1"}, "operands": [{"name": "dest", "desc": "Memory"}], "extension": "x87 FPU", "description": "Stores the value in ST(0) to memory (as 32-bit single, 64-bit double, or 80-bit extended precision, converting if necessary), then pops the register stack by incrementing TOP. The source register is invalidated after the pop; floating-point exceptions may be raised in the x87 status word during conversion. No CPU flags are modified.", "pseudocode": "memory ← convert_and_store(ST(0))\nTOP ← TOP + 1\nif conversion_error: raise x87_exception", "example": "FSTP m32fp/m64fp/m80fp"} {"mnemonic": "fild", "architecture": "x86", "full_name": "Load Integer", "summary": "Converts integer in memory to double-extended-precision float and pushes to ST(0).", "syntax": "FILD m16int/m32int/m64int", "encoding": {"format": "Legacy", "hex_opcode": "DF /0", "length": "2+", "visual_parts": [], "binary_pattern": "DF | ModRM", "bit_positions": "+0 | +1"}, "operands": [{"name": "src", "desc": "Integer Memory"}], "extension": "x87 FPU", "description": "Loads a signed integer (16-bit, 32-bit, or 64-bit) from memory, converts it to 80-bit extended precision floating-point, and pushes onto the x87 register stack (ST(0)). Stack pointer is decremented; conversion is exact and raises no precision or rounding exceptions unless stack overflow occurs. No CPU flags are modified.", "pseudocode": "ST(0) ← convert_integer_to_fp80(memory)\nTOP ← TOP - 1\nif TOP underflow: raise x87_stack_fault", "example": "FILD m16int/m32int/m64int"} {"mnemonic": "fist", "architecture": "x86", "full_name": "Store Integer", "summary": "Converts ST(0) to integer and stores in memory.", "syntax": "FIST m16int/m32int", "encoding": {"format": "Legacy", "hex_opcode": "DF /2", "length": "2+", "visual_parts": [], "binary_pattern": "DF | ModRM", "bit_positions": "+0 | +1"}, "operands": [{"name": "dest", "desc": "Integer Memory"}], "extension": "x87 FPU", "description": "Converts the floating-point value in ST(0) to a signed integer using the current rounding mode and stores the result in the specified 16-bit or 32-bit memory location. The x87 FPU status flags (C0, C1, C2, C3) may be set depending on rounding or overflow conditions. The stack top (ST(0)) remains unchanged after the operation.", "pseudocode": "dest ← convert_to_integer(ST(0), rounding_mode);\nupdate_x87_status_flags();", "example": "FIST m16int/m32int"} {"mnemonic": "fistp", "architecture": "x86", "full_name": "Store Integer and Pop", "summary": "Converts ST(0) to integer, stores in memory, and pops stack.", "syntax": "FISTP m16int/m32int/m64int", "encoding": {"format": "Legacy", "hex_opcode": "DF /3", "length": "2+", "visual_parts": [], "binary_pattern": "DF | ModRM", "bit_positions": "+0 | +1"}, "operands": [{"name": "dest", "desc": "Integer Memory"}], "extension": "x87 FPU", "description": "Converts the floating-point value in ST(0) to a signed integer using the current rounding mode, stores the result in the specified 16-bit, 32-bit, or 64-bit memory location, and then pops the FPU stack. The x87 status flags may be updated based on rounding or overflow conditions. The stack top pointer is decremented after the operation.", "pseudocode": "dest ← convert_to_integer(ST(0), rounding_mode);\nupdate_x87_status_flags();\nST(0) is popped; stack_top ← stack_top - 1;", "example": "FISTP m16int/m32int/m64int"} {"mnemonic": "fadd", "architecture": "x86", "full_name": "Add Floating Point", "summary": "Adds src to dest (ST(0) += src).", "syntax": "FADD m32fp/m64fp", "encoding": {"format": "Legacy", "hex_opcode": "D8 /0", "length": "2+", "visual_parts": [], "binary_pattern": "D8 | ModRM", "bit_positions": "+0 | +1"}, "operands": [{"name": "src", "desc": "Memory/Reg"}], "extension": "x87 FPU", "description": "Adds the floating-point operand in memory (m32fp or m64fp) to ST(0) and stores the result in ST(0). The operation follows IEEE 754 semantics with the current rounding mode. The x87 FPU status flags (C0, C1, C2, C3) are updated based on the result; invalid operation, underflow, overflow, or precision exceptions may be raised.", "pseudocode": "src_value ← load_from_memory(src);\nST(0) ← ST(0) + src_value;\nupdate_x87_status_flags();", "example": "FADD m32fp/m64fp"} {"mnemonic": "fsub", "architecture": "x86", "full_name": "Subtract Floating Point", "summary": "Subtracts src from dest.", "syntax": "FSUB m32fp/m64fp", "encoding": {"format": "Legacy", "hex_opcode": "D8 /4", "length": "2+", "visual_parts": [], "binary_pattern": "D8 | ModRM", "bit_positions": "+0 | +1"}, "operands": [{"name": "src", "desc": "Memory/Reg"}], "extension": "x87 FPU", "description": "Subtracts the floating-point operand in memory (m32fp or m64fp) from ST(0) and stores the result in ST(0). The operation follows IEEE 754 semantics with the current rounding mode. The x87 FPU status flags (C0, C1, C2, C3) are updated; invalid operation, underflow, overflow, or precision exceptions may be raised.", "pseudocode": "src_value ← load_from_memory(src);\nST(0) ← ST(0) - src_value;\nupdate_x87_status_flags();", "example": "FSUB m32fp/m64fp"} {"mnemonic": "fmul", "architecture": "x86", "full_name": "Multiply Floating Point", "summary": "Multiplies dest by src.", "syntax": "FMUL m32fp/m64fp", "encoding": {"format": "Legacy", "hex_opcode": "D8 /1", "length": "2+", "visual_parts": [], "binary_pattern": "D8 | ModRM", "bit_positions": "+0 | +1"}, "operands": [{"name": "src", "desc": "Memory/Reg"}], "extension": "x87 FPU", "description": "Multiplies ST(0) by the floating-point operand in memory (m32fp or m64fp) and stores the result in ST(0). The operation follows IEEE 754 semantics with the current rounding mode. The x87 FPU status flags (C0, C1, C2, C3) are updated; invalid operation, underflow, overflow, or precision exceptions may be raised.", "pseudocode": "src_value ← load_from_memory(src);\nST(0) ← ST(0) × src_value;\nupdate_x87_status_flags();", "example": "FMUL m32fp/m64fp"} {"mnemonic": "fdiv", "architecture": "x86", "full_name": "Divide Floating Point", "summary": "Divides dest by src.", "syntax": "FDIV m32fp/m64fp", "encoding": {"format": "Legacy", "hex_opcode": "D8 /6", "length": "2+", "visual_parts": [], "binary_pattern": "D8 | ModRM", "bit_positions": "+0 | +1"}, "operands": [{"name": "src", "desc": "Memory/Reg"}], "extension": "x87 FPU", "description": "Divides ST(0) by the floating-point operand in memory (m32fp or m64fp) and stores the result in ST(0). The operation follows IEEE 754 semantics with the current rounding mode. The x87 FPU status flags (C0, C1, C2, C3) are updated; division-by-zero, invalid operation, underflow, overflow, or precision exceptions may be raised.", "pseudocode": "src_value ← load_from_memory(src);\nST(0) ← ST(0) ÷ src_value;\nupdate_x87_status_flags();", "example": "FDIV m32fp/m64fp"} {"mnemonic": "fprem", "architecture": "x86", "full_name": "Partial Remainder", "summary": "Computes remainder of ST(0) / ST(1).", "syntax": "FPREM", "encoding": {"format": "Legacy", "hex_opcode": "D9 F8", "visual_parts": [], "binary_pattern": "D9 | F8", "bit_positions": "+0 | +1"}, "extension": "x87 FPU", "operands": [], "description": "Computes the IEEE partial remainder of ST(0) divided by ST(1), storing the result in ST(0). This instruction performs an iterative reduction and may require multiple iterations to complete; the C2 flag indicates whether the result is incomplete (more iterations needed). The x87 status flags (C0, C1, C2, C3) encode the sign and partial quotient information.", "pseudocode": "quotient ← ST(0) ÷ ST(1);\nremainder ← ST(0) - (rounded_quotient × ST(1));\nST(0) ← remainder;\nC0, C1, C2, C3 ← encode_quotient_and_status(quotient, remainder);", "example": "FPREM"} {"mnemonic": "fabs", "architecture": "x86", "full_name": "Absolute Value", "summary": "Replaces ST(0) with its absolute value.", "syntax": "FABS", "encoding": {"format": "Legacy", "hex_opcode": "D9 E1", "visual_parts": [], "binary_pattern": "D9 | E1", "bit_positions": "+0 | +1"}, "extension": "x87 FPU", "operands": [], "description": "Replaces the value in ST(0) with its absolute value by clearing the sign bit. The operation does not modify the x87 status flags and does not raise exceptions. This is a fast unary operation that operates solely on the register stack.", "pseudocode": "ST(0) ← |ST(0)|;", "example": "FABS"} {"mnemonic": "fchs", "architecture": "x86", "full_name": "Change Sign", "summary": "Reverses the sign of ST(0).", "syntax": "FCHS", "encoding": {"format": "Legacy", "hex_opcode": "D9 E0", "visual_parts": [], "binary_pattern": "D9 | E0", "bit_positions": "+0 | +1"}, "extension": "x87 FPU", "operands": [], "description": "Reverses the sign bit of the value in ST(0), converting positive to negative and vice versa. This is a single-bit operation on the sign bit of the extended-precision floating-point format. No flags are affected; the instruction operates entirely within the x87 FPU stack.", "pseudocode": "ST(0) ← -ST(0)", "example": "FCHS"} {"mnemonic": "fsqrt", "architecture": "x86", "full_name": "Square Root", "summary": "Computes square root of ST(0).", "syntax": "FSQRT", "encoding": {"format": "Legacy", "hex_opcode": "D9 FA", "visual_parts": [], "binary_pattern": "D9 | FA", "bit_positions": "+0 | +1"}, "extension": "x87 FPU", "operands": [], "description": "Computes the square root of ST(0) and replaces ST(0) with the result using extended-precision floating-point arithmetic. The x87 FPU C1 flag may be set based on stack conditions; other x87 status flags (C0, C2, C3) are updated according to the result. This is a transcendental operation with typical latency of 70-100 cycles.", "pseudocode": "ST(0) ← sqrt(ST(0))", "example": "FSQRT"} {"mnemonic": "fsin", "architecture": "x86", "full_name": "Sine", "summary": "Computes sine of ST(0) (in radians).", "syntax": "FSIN", "encoding": {"format": "Legacy", "hex_opcode": "D9 FE", "visual_parts": [], "binary_pattern": "D9 | FE", "bit_positions": "+0 | +1"}, "extension": "x87 FPU", "operands": [], "description": "Computes the sine of ST(0), where the argument is interpreted as an angle in radians. The result replaces ST(0); the x87 FPU status flags are updated. This transcendental instruction has high latency and may trigger a C2 flag if the argument is outside the acceptable range (roughly ±2^63).", "pseudocode": "ST(0) ← sin(ST(0))", "example": "FSIN"} {"mnemonic": "fcos", "architecture": "x86", "full_name": "Cosine", "summary": "Computes cosine of ST(0) (in radians).", "syntax": "FCOS", "encoding": {"format": "Legacy", "hex_opcode": "D9 FF", "visual_parts": [], "binary_pattern": "D9 | FF", "bit_positions": "+0 | +1"}, "extension": "x87 FPU", "operands": [], "description": "Computes the cosine of ST(0), where the argument is interpreted as an angle in radians. The result replaces ST(0); the x87 FPU status flags are updated. This transcendental instruction may set the C2 flag if the argument exceeds the acceptable range.", "pseudocode": "ST(0) ← cos(ST(0))", "example": "FCOS"} {"mnemonic": "fsincos", "architecture": "x86", "full_name": "Sine and Cosine", "summary": "Computes sine and cosine of ST(0), pushing both to stack.", "syntax": "FSINCOS", "encoding": {"format": "Legacy", "hex_opcode": "D9 FB", "visual_parts": [], "binary_pattern": "D9 | FB", "bit_positions": "+0 | +1"}, "extension": "x87 FPU", "operands": [], "description": "Computes both sine and cosine of ST(0) in a single operation, pushing the cosine result onto the stack and leaving the sine in ST(0). The stack pointer is incremented after the push, so the sine ends up in ST(0) and cosine in ST(1). The x87 status flags are updated; C2 may be set if the argument is out of range.", "pseudocode": "temp ← ST(0); ST(0) ← sin(temp); push(cos(temp)); TOS ← TOS + 1", "example": "FSINCOS"} {"mnemonic": "fptan", "architecture": "x86", "full_name": "Partial Tangent", "summary": "Computes tangent of ST(0) and pushes 1.0.", "syntax": "FPTAN", "encoding": {"format": "Legacy", "hex_opcode": "D9 F2", "visual_parts": [], "binary_pattern": "D9 | F2", "bit_positions": "+0 | +1"}, "extension": "x87 FPU", "operands": [], "description": "Computes the tangent of ST(0) and then pushes 1.0 onto the stack, so ST(0) becomes tan(original ST(0)) and the constant 1.0 moves to ST(1). The x87 status flags are updated; C2 may be set if the argument is out of the acceptable range. This is used in conjuction with FPATAN to compute arctangent.", "pseudocode": "temp ← ST(0); ST(0) ← tan(temp); push(1.0); TOS ← TOS + 1", "example": "FPTAN"} {"mnemonic": "fpatan", "architecture": "x86", "full_name": "Partial Arctangent", "summary": "Computes arctan(ST(1)/ST(0)).", "syntax": "FPATAN", "encoding": {"format": "Legacy", "hex_opcode": "D9 F3", "visual_parts": [], "binary_pattern": "D9 | F3", "bit_positions": "+0 | +1"}, "extension": "x87 FPU", "operands": [], "description": "Computes the two-argument arctangent of ST(1)/ST(0) and replaces both stack entries with the result in ST(0); the stack pointer is decremented. The result is in the range [-π/2, π/2] or [-π, π] depending on the signs of ST(1) and ST(0). The x87 status flags are updated accordingly.", "pseudocode": "ST(0) ← atan2(ST(1), ST(0)); pop(); TOS ← TOS - 1", "example": "FPATAN"} {"mnemonic": "fyl2x", "architecture": "x86", "full_name": "Y * log2(X)", "summary": "Computes ST(1) * log2(ST(0)).", "syntax": "FYL2X", "encoding": {"format": "Legacy", "hex_opcode": "D9 F1", "visual_parts": [], "binary_pattern": "D9 | F1", "bit_positions": "+0 | +1"}, "extension": "x87 FPU", "operands": [], "description": "Computes ST(1) * log₂(ST(0)) and replaces both stack entries with the result in ST(0); the stack pointer is decremented. ST(0) must be strictly positive; the result is typically used for computing logarithmic and exponential functions. The x87 status flags are updated; C2 may be set for out-of-range arguments.", "pseudocode": "ST(0) ← ST(1) * log2(ST(0)); pop(); TOS ← TOS - 1", "example": "FYL2X"} {"mnemonic": "fxch", "architecture": "x86", "full_name": "Exchange Register", "summary": "Exchanges contents of ST(0) and ST(i).", "syntax": "FXCH ST(i)", "encoding": {"format": "Legacy", "hex_opcode": "D9 C8+i", "visual_parts": [], "binary_pattern": "D9", "bit_positions": "+0"}, "extension": "x87 FPU", "operands": [{"name": "dest", "type": "ST(i)", "desc": "x87 FPU stack register ST(i)"}], "description": "Exchanges the contents of ST(0) and ST(i), swapping the top of the x87 FPU stack with another stack register. This is a register-only operation with no impact on EFLAGS. The instruction is part of the x87 FPU instruction set and does not cause pipeline serialization.", "pseudocode": "temp ← ST(0);\nST(0) ← ST(i);\nST(i) ← temp;", "example": "FXCH st(1)"} {"mnemonic": "fcom", "architecture": "x86", "full_name": "Compare Real", "summary": "Compares ST(0) with source.", "syntax": "FCOM m32fp/m64fp", "encoding": {"format": "Legacy", "hex_opcode": "D8 /2", "length": "2+", "visual_parts": [], "binary_pattern": "D8 | ModRM", "bit_positions": "+0 | +1"}, "operands": [{"name": "src", "desc": "Memory/Reg"}], "extension": "x87 FPU", "description": "Compares ST(0) with a single-precision (m32fp) or double-precision (m64fp) floating-point memory operand and sets the FPU condition code flags (C0, C2, C3) in the status word. The comparison result is reflected only in FPU flags, not in CPU EFLAGS. This instruction does not modify the stack.", "pseudocode": "src_value ← [memory];\nif (ST(0) > src_value) { C0←0; C2←0; C3←0; }\nelse if (ST(0) < src_value) { C0←1; C2←0; C3←0; }\nelse if (ST(0) == src_value) { C0←0; C2←0; C3←1; }\nelse { C0←1; C2←1; C3←1; }", "example": "FCOM m32fp/m64fp"} {"mnemonic": "fcomi", "architecture": "x86", "full_name": "Compare Real and Set EFLAGS", "summary": "Compares ST(0) with ST(i) and sets CPU EFLAGS directly.", "syntax": "FCOMI ST(0), ST(i)", "encoding": {"format": "Legacy", "hex_opcode": "DB F0+i", "visual_parts": [], "binary_pattern": "DB", "bit_positions": "+0"}, "extension": "x87 FPU (P6+)", "operands": [{"name": "dest", "type": "ST(0)", "desc": "x87 FPU top-of-stack register ST(0)"}, {"name": "src", "type": "ST(i)", "desc": "x87 FPU stack register ST(i)"}], "description": "Compares ST(0) with ST(i) and directly sets the CPU EFLAGS (ZF, PF, CF) to reflect the comparison result, enabling use of standard conditional jumps without FSTSW. Available on P6 and later processors. The comparison does not pop the stack and affects CPU flags rather than FPU condition codes.", "pseudocode": "if (ST(0) > ST(i)) { ZF←0; PF←0; CF←0; }\nelse if (ST(0) < ST(i)) { ZF←0; PF←0; CF←1; }\nelse if (ST(0) == ST(i)) { ZF←1; PF←0; CF←0; }\nelse { ZF←1; PF←1; CF←1; }", "example": "FCOMI st(0), st(1)"} {"mnemonic": "finit", "architecture": "x86", "full_name": "Initialize FPU", "summary": "Resets FPU to default state.", "syntax": "FINIT", "encoding": {"format": "Legacy", "hex_opcode": "9B DB E3", "visual_parts": [], "binary_pattern": "9B | DB | E3", "bit_positions": "+0 | +1 | +2"}, "extension": "x87 FPU", "operands": [], "description": "Initializes the x87 FPU to its default state, clearing the stack, setting control word to 0x037F (round to nearest, all exceptions masked), and clearing all status flags and exception flags. The instruction is preceded by FWAIT (0x9B) to ensure any pending FPU operations complete before reinitializing. This causes full FPU state reset with no impact on integer registers or EFLAGS.", "pseudocode": "FPU_Control_Word ← 0x037F;\nFPU_Status_Word ← 0x0000;\nFPU_Tag_Word ← 0xFFFF;\nfor (i = 0; i < 8; i++) ST(i) ← 0.0;\nFPU_Exception_Flags ← 0;", "example": "FINIT"} {"mnemonic": "fclex", "architecture": "x86", "full_name": "Clear Exceptions", "summary": "Clears floating-point exception flags.", "syntax": "FCLEX", "encoding": {"format": "Legacy", "hex_opcode": "9B DB E2", "visual_parts": [], "binary_pattern": "9B | DB | E2", "bit_positions": "+0 | +1 | +2"}, "extension": "x87 FPU", "operands": [], "description": "Clears all floating-point exception flags (IE, DE, ZE, OE, UE, PE) in the FPU status word without clearing the condition codes or the stack. The instruction is preceded by FWAIT (0x9B) to synchronize with any pending FPU operations. Does not affect CPU EFLAGS or FPU control/tag words.", "pseudocode": "FPU_Status_Word.IE ← 0;\nFPU_Status_Word.DE ← 0;\nFPU_Status_Word.ZE ← 0;\nFPU_Status_Word.OE ← 0;\nFPU_Status_Word.UE ← 0;\nFPU_Status_Word.PE ← 0;", "example": "FCLEX"} {"mnemonic": "fstsw", "architecture": "x86", "full_name": "Store Status Word", "summary": "Stores FPU status word to AX or memory.", "syntax": "FSTSW AX", "encoding": {"format": "Legacy", "hex_opcode": "9B DF E0", "length": "3", "visual_parts": [], "binary_pattern": "9B | DF | E0", "bit_positions": "+0 | +1 | +2"}, "operands": [{"name": "dest", "desc": "AX/Mem"}], "extension": "x87 FPU", "description": "Stores the FPU status word (16-bit value containing exception flags, condition codes, stack pointer, and busy bit) into AX or memory. When destination is AX, the instruction may be used to examine FPU state from integer code without memory operands. The encoding shown (9B DF E0) uses FWAIT prefix and stores to AX; memory forms use D9 /7.", "pseudocode": "if (destination == AX) {\n AX ← FPU_Status_Word;\n} else {\n [memory] ← FPU_Status_Word;\n}", "example": "FSTSW AX"} {"mnemonic": "fldcw", "architecture": "x86", "full_name": "Load Control Word", "summary": "Loads FPU control word from memory.", "syntax": "FLDCW m2byte", "encoding": {"format": "Legacy", "hex_opcode": "D9 /5", "length": "2+", "visual_parts": [], "binary_pattern": "D9 | ModRM", "bit_positions": "+0 | +1"}, "operands": [{"name": "src", "desc": "Memory"}], "extension": "x87 FPU", "description": "Loads a 16-bit control word from memory into the FPU control word register, affecting rounding mode, exception masks, precision control, and other FPU operating parameters. This instruction does not require FWAIT and takes effect immediately on subsequent FPU instructions. Changes to rounding mode and exception masks apply only to future floating-point operations.", "pseudocode": "FPU_Control_Word ← [memory];", "example": "FLDCW m2byte"} {"mnemonic": "fstcw", "architecture": "x86", "full_name": "Store Control Word", "summary": "Stores FPU control word to memory.", "syntax": "FSTCW m2byte", "encoding": {"format": "Legacy", "hex_opcode": "9B D9 /7", "length": "3+", "visual_parts": [], "binary_pattern": "9B | D9 | ModRM", "bit_positions": "+0 | +1 | +2"}, "operands": [{"name": "dest", "desc": "Memory"}], "extension": "x87 FPU", "description": "Stores the current FPU control word (16-bit value) to memory, preserving rounding mode, exception mask bits, precision control, and infinity control settings. The instruction is preceded by FWAIT (0x9B) to ensure any pending FPU operations complete before the store. Does not affect CPU EFLAGS or FPU stack contents.", "pseudocode": "[memory] ← FPU_Control_Word;", "example": "FSTCW m2byte"} {"mnemonic": "frstor", "architecture": "x86", "full_name": "Restore FPU State", "summary": "Loads FPU state from memory.", "syntax": "FRSTOR m108byte", "encoding": {"format": "Legacy", "hex_opcode": "DD /4", "length": "2+", "visual_parts": [], "binary_pattern": "DD | ModRM", "bit_positions": "+0 | +1"}, "operands": [{"name": "src", "desc": "Memory"}], "extension": "x87 FPU", "description": "Loads the complete x87 FPU state (108 bytes) from memory, including all eight floating-point registers, control word, status word, tag word, instruction pointer, and data pointer. This instruction does not set any CPU flags and is not serializing. It is available in all CPU modes (real, protected, 64-bit) and requires memory operand addressing.", "pseudocode": "FPU_state ← [m108byte]\n// Restores: FPR0-FPR7, CW, SW, TW, IP, DP, DS, opcode", "example": "FRSTOR m108byte"} {"mnemonic": "fsave", "architecture": "x86", "full_name": "Save FPU State", "summary": "Stores FPU state to memory and re-initializes FPU.", "syntax": "FSAVE m108byte", "encoding": {"format": "Legacy", "hex_opcode": "9B DD /6", "length": "3+", "visual_parts": [], "binary_pattern": "9B | DD | ModRM", "bit_positions": "+0 | +1 | +2"}, "operands": [{"name": "dest", "desc": "Memory"}], "extension": "x87 FPU", "description": "Saves the entire x87 FPU state (108 bytes) to memory and reinitializes the FPU to its default state. The instruction issues an implicit FWAIT (0x9B prefix) to ensure prior floating-point operations complete before saving. No CPU flags are set; the instruction is serializing with respect to x87 operations. Available in all modes.", "pseudocode": "[m108byte] ← FPU_state\n// Saves: FPR0-FPR7, CW, SW, TW, IP, DP, DS, opcode\nFPU_state ← initial_state", "example": "FSAVE m108byte"} {"mnemonic": "lgdt", "architecture": "x86", "full_name": "Load Global Descriptor Table Register", "summary": "Loads the GDT register (Privileged).", "syntax": "LGDT m16&32", "encoding": {"format": "System", "hex_opcode": "0F 01 /2", "length": "3+", "visual_parts": [], "binary_pattern": "0F | 01 | ModRM", "bit_positions": "+0 | +1 | +2"}, "operands": [{"name": "src", "desc": "Memory"}], "extension": "System", "description": "Loads the Global Descriptor Table (GDT) register with a limit (16 bits) and base address (32 bits in 32-bit mode, 64 bits in 64-bit mode) from a 6-byte or 10-byte memory operand. This is a privileged instruction (requires CPL=0) and causes a pipeline flush. No flags are affected. In 64-bit mode, the operand is 10 bytes (16-bit limit + 64-bit base).", "pseudocode": "GDTR.limit ← [m16&32 + 0:1]\nGDTR.base ← [m16&32 + 2:5] // 32-bit or 64-bit depending on mode", "example": "LGDT m16&32"} {"mnemonic": "lidt", "architecture": "x86", "full_name": "Load Interrupt Descriptor Table Register", "summary": "Loads the IDT register (Privileged).", "syntax": "LIDT m16&32", "encoding": {"format": "System", "hex_opcode": "0F 01 /3", "length": "3+", "visual_parts": [], "binary_pattern": "0F | 01 | ModRM", "bit_positions": "+0 | +1 | +2"}, "operands": [{"name": "src", "desc": "Memory"}], "extension": "System", "description": "Loads the Interrupt Descriptor Table (IDT) register with a limit (16 bits) and base address (32 bits in 32-bit mode, 64 bits in 64-bit mode) from a 6-byte or 10-byte memory operand. This is a privileged instruction (requires CPL=0) and causes a pipeline flush. No flags are affected. In 64-bit mode, the operand is 10 bytes (16-bit limit + 64-bit base).", "pseudocode": "IDTR.limit ← [m16&32 + 0:1]\nIDTR.base ← [m16&32 + 2:5] // 32-bit or 64-bit depending on mode", "example": "LIDT m16&32"} {"mnemonic": "sgdt", "architecture": "x86", "full_name": "Store Global Descriptor Table Register", "summary": "Stores GDT limit and base address to memory.", "syntax": "SGDT m", "encoding": {"format": "System", "hex_opcode": "0F 01 /0", "visual_parts": [], "binary_pattern": "0F | 01 | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "System", "operands": [{"name": "dest", "type": "m", "desc": "Memory operand"}], "description": "Stores the current Global Descriptor Table (GDT) register contents (limit and base address) to memory. The format is 2-byte limit followed by 4-byte base in 32-bit mode, or 2-byte limit followed by 8-byte base in 64-bit mode. No flags are affected. This instruction is not privileged and can be executed at any CPL.", "pseudocode": "[m + 0:1] ← GDTR.limit\n[m + 2:5] ← GDTR.base // 4 or 8 bytes depending on mode", "example": "SGDT [rbp-8]"} {"mnemonic": "sidt", "architecture": "x86", "full_name": "Store Interrupt Descriptor Table Register", "summary": "Stores IDT limit and base address to memory.", "syntax": "SIDT m", "encoding": {"format": "System", "hex_opcode": "0F 01 /1", "visual_parts": [], "binary_pattern": "0F | 01 | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "System", "operands": [{"name": "dest", "type": "m", "desc": "Memory operand"}], "description": "Stores the current Interrupt Descriptor Table (IDT) register contents (limit and base address) to memory. The format is 2-byte limit followed by 4-byte base in 32-bit mode, or 2-byte limit followed by 8-byte base in 64-bit mode. No flags are affected. This instruction is not privileged and can be executed at any CPL.", "pseudocode": "[m + 0:1] ← IDTR.limit\n[m + 2:5] ← IDTR.base // 4 or 8 bytes depending on mode", "example": "SIDT [rbp-8]"} {"mnemonic": "lldt", "architecture": "x86", "full_name": "Load Local Descriptor Table Register", "summary": "Loads LDT segment selector (Privileged).", "syntax": "LLDT r/m16", "encoding": {"format": "System", "hex_opcode": "0F 00 /2", "visual_parts": [], "binary_pattern": "0F | 00 | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "System", "operands": [{"name": "dest", "type": "r/m16", "desc": "16-bit register or memory"}], "description": "Loads the Local Descriptor Table (LDT) register with a 16-bit segment selector from a register or memory. This is a privileged instruction (requires CPL=0) and causes a pipeline flush. The selector must reference a valid LDT descriptor in the GDT; an invalid selector clears the LDT register. No flags are affected.", "pseudocode": "LDTR ← r/m16\n// Selector is validated; if invalid, LDTR is cleared", "example": "LLDT bx"} {"mnemonic": "sldt", "architecture": "x86", "full_name": "Store Local Descriptor Table Register", "summary": "Stores LDT segment selector.", "syntax": "SLDT r/m16", "encoding": {"format": "System", "hex_opcode": "0F 00 /0", "visual_parts": [], "binary_pattern": "0F | 00 | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "System", "operands": [{"name": "dest", "type": "r/m16", "desc": "16-bit register or memory"}], "description": "Stores the current Local Descriptor Table (LDT) register contents (16-bit segment selector) into a register or memory. If the destination is a 32-bit or 64-bit register, the selector is zero-extended. No flags are affected. This instruction is not privileged and can be executed at any CPL.", "pseudocode": "r/m16 ← LDTR // For 32/64-bit dest: zero-extended", "example": "SLDT bx"} {"mnemonic": "ltr", "architecture": "x86", "full_name": "Load Task Register", "summary": "Loads Task Register (Privileged).", "syntax": "LTR r/m16", "encoding": {"format": "System", "hex_opcode": "0F 00 /3", "visual_parts": [], "binary_pattern": "0F | 00 | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "System", "operands": [{"name": "dest", "type": "r/m16", "desc": "16-bit register or memory"}], "description": "Loads a 16-bit Task Register selector from a register or memory operand. This privileged instruction (CPL=0 only) loads the TR register with a task gate descriptor selector, initiating task switching if the selector points to a valid TSS descriptor. No flags are affected.", "pseudocode": "TR ← source[15:0]; (task switch occurs if source is valid TSS selector)", "example": "LTR bx"} {"mnemonic": "str", "architecture": "x86", "full_name": "Store Task Register", "summary": "Stores Task Register.", "syntax": "STR r/m16", "encoding": {"format": "System", "hex_opcode": "0F 00 /1", "visual_parts": [], "binary_pattern": "0F | 00 | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "System", "operands": [{"name": "dest", "type": "r/m16", "desc": "16-bit register or memory"}], "description": "Stores the current Task Register selector into a 16-bit register or memory operand. This non-privileged instruction reads the TR register and writes its selector value; it operates in all modes and does not affect any flags.", "pseudocode": "dest ← TR[15:0]", "example": "STR bx"} {"mnemonic": "mov cr", "architecture": "x86", "full_name": "Move Control Register", "summary": "Moves data to/from Control Registers (CR0, CR3, etc.) (Privileged).", "syntax": "MOV CRn, r", "encoding": {"format": "System", "hex_opcode": "0F 22 /r", "length": "3", "visual_parts": [], "binary_pattern": "0F | 22 | ModRM", "bit_positions": "+0 | +1 | +2"}, "operands": [{"name": "dest", "desc": "CRn"}, {"name": "src", "desc": "Reg"}], "extension": "System", "description": "Moves a 32-bit or 64-bit value from a general-purpose register to a control register (CR0, CR2, CR3, CR4, CR8 in 64-bit mode). This privileged instruction (CPL=0 only) performs hardware state modification with potential serialization effects; certain CR writes invalidate TLBs or flush caches. No arithmetic flags are affected.", "pseudocode": "CRn ← r (where n ∈ {0,2,3,4,8}); TLB and cache invalidation may occur", "example": "MOV CRn, rax"} {"mnemonic": "mov dr", "architecture": "x86", "full_name": "Move Debug Register", "summary": "Moves data to/from Debug Registers (DR0-DR7) (Privileged).", "syntax": "MOV DRn, r", "encoding": {"format": "System", "hex_opcode": "0F 23 /r", "length": "3", "visual_parts": [], "binary_pattern": "0F | 23 | ModRM", "bit_positions": "+0 | +1 | +2"}, "operands": [{"name": "dest", "desc": "DRn"}, {"name": "src", "desc": "Reg"}], "extension": "System", "description": "Moves a 32-bit or 64-bit value from a general-purpose register to a debug register (DR0-DR7). This privileged instruction (CPL=0 only) performs hardware debug state modification; writes to DR6 and DR7 may clear breakpoint conditions and alter breakpoint control. No arithmetic flags are affected.", "pseudocode": "DRn ← r (where n ∈ {0,1,2,3,6,7}); breakpoint state may change", "example": "MOV DRn, rax"} {"mnemonic": "lmsw", "architecture": "x86", "full_name": "Load Machine Status Word", "summary": "Loads Machine Status Word (Legacy CR0 modification).", "syntax": "LMSW r/m16", "encoding": {"format": "System", "hex_opcode": "0F 01 /6", "visual_parts": [], "binary_pattern": "0F | 01 | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "System", "operands": [{"name": "dest", "type": "r/m16", "desc": "16-bit register or memory"}], "description": "Loads the lower 4 bits of a 16-bit operand into the lower 4 bits of CR0 (the machine status word: PE, MP, EM, TS). This privileged instruction (CPL=0 only) affects processor mode and FPU handling; it can enable protected mode but cannot disable it or modify higher CR0 bits. No flags are affected.", "pseudocode": "CR0[3:0] ← source[3:0]; (legacy CR0 access, cannot clear PE or modify bits 31:4)", "example": "LMSW bx"} {"mnemonic": "smsw", "architecture": "x86", "full_name": "Store Machine Status Word", "summary": "Stores Machine Status Word.", "syntax": "SMSW r/m16", "encoding": {"format": "System", "hex_opcode": "0F 01 /4", "visual_parts": [], "binary_pattern": "0F | 01 | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "System", "operands": [{"name": "dest", "type": "r/m16", "desc": "16-bit register or memory"}], "description": "Stores the lower 16 bits of CR0 (the machine status word: PE, MP, EM, TS, and reserved bits) into a 16-bit register or memory operand. This non-privileged instruction reads CR0[15:0]; in 64-bit mode, a 32-bit destination is zero-extended to 64 bits. No flags are affected.", "pseudocode": "dest ← CR0[15:0]; (in 64-bit with r64 operand: dest ← CR0[15:0] zero-extended to 64 bits)", "example": "SMSW bx"} {"mnemonic": "clts", "architecture": "x86", "full_name": "Clear Task-Switched Flag", "summary": "Clears the TS flag in CR0 (Privileged).", "syntax": "CLTS", "encoding": {"format": "System", "hex_opcode": "0F 06", "visual_parts": [], "binary_pattern": "0F | 06", "bit_positions": "+0 | +1"}, "extension": "System", "operands": [], "description": "Clears the Task-Switched flag (TS, bit 3) in CR0. This privileged instruction (CPL=0 only) allows the processor to use the FPU without raising a #NM exception; it is typically executed after an FPU context save. No flags are affected.", "pseudocode": "CR0[3] ← 0", "example": "CLTS"} {"mnemonic": "invd", "architecture": "x86", "full_name": "Invalidate Internal Caches", "summary": "Flushes internal caches without writing back data (Privileged).", "syntax": "INVD", "encoding": {"format": "System", "hex_opcode": "0F 08", "visual_parts": [], "binary_pattern": "0F | 08", "bit_positions": "+0 | +1"}, "extension": "System", "operands": [], "description": "Invalidates all internal cache lines without writing back modified data to memory. This privileged instruction (CPL=0 only) causes a complete pipeline flush and memory ordering barrier; dirty cache lines are discarded, potentially losing uncommitted writes, making it dangerous for general use. No flags are affected.", "pseudocode": "invalidate_all_cache_lines(); flush_pipeline(); memory_barrier()", "example": "INVD"} {"mnemonic": "wbinvd", "architecture": "x86", "full_name": "Write Back and Invalidate Cache", "summary": "Writes back modified data and invalidates caches (Privileged).", "syntax": "WBINVD", "encoding": {"format": "System", "hex_opcode": "0F 09", "visual_parts": [], "binary_pattern": "0F | 09", "bit_positions": "+0 | +1"}, "extension": "System", "operands": [], "description": "Writes back all modified cache lines to memory and invalidates all internal caches, ensuring cache coherency across the system. This is a privileged instruction (CPL 0 only) that serializes the pipeline and may take hundreds of cycles. No flags are affected.", "pseudocode": "for each cache line in all caches:\n if (cache_line.modified) write_to_memory(cache_line);\n invalidate(cache_line);\nPipeline_Serialization();", "example": "WBINVD"} {"mnemonic": "invlpg", "architecture": "x86", "full_name": "Invalidate TLB Entry", "summary": "Invalidates a specific TLB entry (Privileged).", "syntax": "INVLPG m", "encoding": {"format": "System", "hex_opcode": "0F 01/7", "visual_parts": [], "binary_pattern": "0F | 01 | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "System", "operands": [{"name": "dest", "type": "m", "desc": "Memory operand"}], "description": "Invalidates the TLB entry for the linear address specified by the memory operand, forcing a TLB reload on next access. This is a privileged instruction (CPL 0 only) used after page table modifications. No flags are affected; pipeline serialization may occur depending on implementation.", "pseudocode": "linear_address ← address_of(m);\nTLB[linear_address].valid ← 0;", "example": "INVLPG [rbp-8]"} {"mnemonic": "rdmsr", "architecture": "x86", "full_name": "Read Model Specific Register", "summary": "Reads MSR specified by ECX into EDX:EAX (Privileged).", "syntax": "RDMSR", "encoding": {"format": "System", "hex_opcode": "0F 32", "visual_parts": [], "binary_pattern": "0F | 32", "bit_positions": "+0 | +1"}, "extension": "System", "operands": [], "description": "Reads a 64-bit Model Specific Register (MSR) whose index is in ECX and stores the result in EDX:EAX (EDX holds bits 63-32, EAX holds bits 31-0). This is a privileged instruction (CPL 0 only) that may cause a general protection fault if ECX selects an invalid or inaccessible MSR. No EFLAGS are modified.", "pseudocode": "msr_index ← ECX;\nmsr_value ← MSR[msr_index];\nEAX ← msr_value[31:0];\nEDX ← msr_value[63:32];", "example": "RDMSR"} {"mnemonic": "wrmsr", "architecture": "x86", "full_name": "Write Model Specific Register", "summary": "Writes EDX:EAX to MSR specified by ECX (Privileged).", "syntax": "WRMSR", "encoding": {"format": "System", "hex_opcode": "0F 30", "visual_parts": [], "binary_pattern": "0F | 30", "bit_positions": "+0 | +1"}, "extension": "System", "operands": [], "description": "Writes a 64-bit value from EDX:EAX to the Model Specific Register (MSR) whose index is in ECX (EDX holds bits 63-32, EAX holds bits 31-0). This is a privileged instruction (CPL 0 only) that serializes execution and may cause a general protection fault if ECX selects an invalid or write-protected MSR. No EFLAGS are modified.", "pseudocode": "msr_index ← ECX;\nmsr_value ← (EDX << 32) | EAX;\nMSR[msr_index] ← msr_value;\nPipeline_Serialization();", "example": "WRMSR"} {"mnemonic": "rdpmc", "architecture": "x86", "full_name": "Read Performance-Monitoring Counters", "summary": "Reads performance counter specified by ECX into EDX:EAX.", "syntax": "RDPMC", "encoding": {"format": "System", "hex_opcode": "0F 33", "visual_parts": [], "binary_pattern": "0F | 33", "bit_positions": "+0 | +1"}, "extension": "System", "operands": [], "description": "Reads a 40-bit performance monitoring counter whose index is in ECX and stores the result in EDX:EAX (EDX holds bits 39-32, EAX holds bits 31-0). User-mode execution may be permitted depending on RDPMC flag in CR4; a general protection fault occurs if not allowed. No EFLAGS are modified.", "pseudocode": "counter_index ← ECX;\ncounter_value ← PMC[counter_index];\nEAX ← counter_value[31:0];\nEDX ← counter_value[39:32] & 0xFF;", "example": "RDPMC"} {"mnemonic": "sysenter", "architecture": "x86", "full_name": "Fast System Call", "summary": "Fast call to level 0 system procedures.", "syntax": "SYSENTER", "encoding": {"format": "System", "hex_opcode": "0F 34", "visual_parts": [], "binary_pattern": "0F | 34", "bit_positions": "+0 | +1"}, "extension": "System", "operands": [], "description": "Fast transition from user mode (CPL 3) to kernel mode (CPL 0) by loading CS, SS, EIP, and ESP from IA32_SYSENTER_* MSRs. This instruction serializes the pipeline, disables interrupts, and clears EFLAGS.IF. It is the fast-path alternative to INT for system calls.", "pseudocode": "if (CPL != 3) raise_exception(INVALID_OPCODE);\nCS ← IA32_SYSENTER_CS & ~3; // load kernel code segment\nSS ← (IA32_SYSENTER_CS + 8) | 0; // load kernel stack segment\nEIP ← IA32_SYSENTER_EIP;\nESP ← IA32_SYSENTER_ESP;\nEFLAGS.IF ← 0;\nPipeline_Serialization();", "example": "SYSENTER"} {"mnemonic": "sysexit", "architecture": "x86", "full_name": "Fast Return from System Call", "summary": "Fast return to level 3 user code.", "syntax": "SYSEXIT", "encoding": {"format": "System", "hex_opcode": "0F 35", "visual_parts": [], "binary_pattern": "0F | 35", "bit_positions": "+0 | +1"}, "extension": "System", "operands": [], "description": "Fast return from kernel mode (CPL 0) to user mode (CPL 3) by restoring CS, SS, EIP, and ESP from implicit registers or operands. This instruction serializes the pipeline and re-enables interrupts. It complements SYSENTER for rapid system call returns.", "pseudocode": "if (CPL != 0) raise_exception(INVALID_OPCODE);\nCS ← (IA32_SYSENTER_CS + 16) | 3; // load user code segment\nSS ← (IA32_SYSENTER_CS + 24) | 3; // load user stack segment\nEIP ← ECX;\nESP ← EDX;\nEFLAGS.IF ← 1;\nPipeline_Serialization();", "example": "SYSEXIT"} {"mnemonic": "lar", "architecture": "x86", "full_name": "Load Access Rights Byte", "summary": "Reads access rights from segment descriptor.", "syntax": "LAR r, r/m16", "encoding": {"format": "System", "hex_opcode": "0F 02", "visual_parts": [], "binary_pattern": "0F | 02", "bit_positions": "+0 | +1"}, "extension": "System", "operands": [{"name": "dest", "type": "r", "desc": "General-purpose register"}, {"name": "src", "type": "r/m16", "desc": "16-bit register or memory"}], "description": "Loads the access rights byte from the segment descriptor referenced by the 16-bit selector in r/m16 into the destination general-purpose register (zero-extended to 32 or 64 bits). The ZF flag is cleared if the selector is invalid or references a data segment; ZF is set if successful. No other flags are modified.", "pseudocode": "selector ← r/m16;\nif (selector is invalid || descriptor_type(selector) != code_segment) {\n ZF ← 0;\n} else {\n dest ← zero_extend(descriptor_access_rights_byte(selector));\n ZF ← 1;\n}", "example": "LAR rax, bx"} {"mnemonic": "lsl", "architecture": "x86", "full_name": "Load Segment Limit", "summary": "Reads segment limit from descriptor.", "syntax": "LSL r, r/m16", "encoding": {"format": "System", "hex_opcode": "0F 03", "visual_parts": [], "binary_pattern": "0F | 03", "bit_positions": "+0 | +1"}, "extension": "System", "operands": [{"name": "dest", "type": "r", "desc": "General-purpose register"}, {"name": "src", "type": "r/m16", "desc": "16-bit register or memory"}], "description": "Loads the segment limit from the descriptor table entry referenced by the source selector into the destination register. The instruction reads the descriptor from the GDT or LDT, extracts the limit field, and writes it to the destination. The ZF flag is cleared if the selector is valid and the descriptor is accessible; ZF is set if the selector is invalid or the descriptor type is unsuitable. This instruction is privileged and operates only in protected mode or 64-bit mode.", "pseudocode": "selector ← src[15:0];\ndescriptor ← load_descriptor(selector);\nif (descriptor is valid AND descriptor.type in {code, data, tss, gate}) {\n dest ← descriptor.limit;\n ZF ← 0;\n} else {\n ZF ← 1;\n}", "example": "LSL rax, bx"} {"mnemonic": "verr", "architecture": "x86", "full_name": "Verify Segment for Reading", "summary": "Checks if segment can be read; sets ZF.", "syntax": "VERR r/m16", "encoding": {"format": "System", "hex_opcode": "0F 00 /4", "visual_parts": [], "binary_pattern": "0F | 00 | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "System", "operands": [{"name": "dest", "type": "r/m16", "desc": "16-bit register or memory"}], "description": "Verifies that the segment referenced by the selector can be read by the current code. The instruction loads the descriptor table entry and checks the segment type and privilege level. ZF is set to 1 if the selector is valid and readable at the current privilege level; ZF is cleared if the selector is invalid, the descriptor type is unsuitable, or privilege checks fail. This instruction is privileged and operates only in protected or 64-bit mode.", "pseudocode": "selector ← src[15:0];\ndescriptor ← load_descriptor(selector);\nif (descriptor is valid AND descriptor.type in {data, code-readable} AND cpl_check_passes) {\n ZF ← 1;\n} else {\n ZF ← 0;\n}", "example": "VERR bx"} {"mnemonic": "verw", "architecture": "x86", "full_name": "Verify Segment for Writing", "summary": "Checks if segment can be written; sets ZF.", "syntax": "VERW r/m16", "encoding": {"format": "System", "hex_opcode": "0F 00 /5", "visual_parts": [], "binary_pattern": "0F | 00 | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "System", "operands": [{"name": "dest", "type": "r/m16", "desc": "16-bit register or memory"}], "description": "Verifies that the segment referenced by the selector can be written by the current code. The instruction loads the descriptor table entry and checks the segment type and privilege level. ZF is set to 1 if the selector is valid and writable at the current privilege level; ZF is cleared if the selector is invalid, the descriptor type is unsuitable (e.g., code segment or read-only data), or privilege checks fail. This instruction is privileged and operates only in protected or 64-bit mode.", "pseudocode": "selector ← src[15:0];\ndescriptor ← load_descriptor(selector);\nif (descriptor is valid AND descriptor.type in {data-writable} AND cpl_check_passes) {\n ZF ← 1;\n} else {\n ZF ← 0;\n}", "example": "VERW bx"} {"mnemonic": "arpl", "architecture": "x86", "full_name": "Adjust Requested Privilege Level", "summary": "Adjusts RPL of selector to match current CPL (Legacy).", "syntax": "ARPL r/m16, r16", "encoding": {"format": "System", "hex_opcode": "63", "visual_parts": [], "binary_pattern": "63", "bit_positions": "+0"}, "extension": "System (32-bit)", "operands": [{"name": "dest", "type": "r/m16", "desc": "16-bit register or memory"}, {"name": "src", "type": "r16", "desc": "16-bit general-purpose register"}], "description": "Adjusts the Requested Privilege Level (RPL) field of a selector to match the current Code Privilege Level (CPL) if the selector's current RPL is less privileged than CPL. If the adjustment occurs, ZF is set; otherwise ZF is cleared. This is a legacy instruction used in 32-bit protected mode to enforce privilege level consistency; it is not supported in 64-bit mode. All flags except ZF are unchanged.", "pseudocode": "selector ← dest[15:0];\nrpl ← selector[1:0];\ncpl ← current_cpl;\nif (rpl < cpl) {\n selector[1:0] ← cpl;\n dest ← selector;\n ZF ← 1;\n} else {\n ZF ← 0;\n}", "example": "ARPL bx, ax"} {"mnemonic": "rsm", "architecture": "x86", "full_name": "Resume from System Management Mode", "summary": "Exits SMM and returns to previous state (Privileged).", "syntax": "RSM", "encoding": {"format": "System", "hex_opcode": "0F AA", "visual_parts": [], "binary_pattern": "0F | AA", "bit_positions": "+0 | +1"}, "extension": "System (SMM)", "operands": [], "description": "Resumes normal CPU operation from System Management Mode (SMM), restoring processor state from the SMM state save area and resuming execution at the return instruction pointer saved at SMM entry. This instruction is privileged and can only be executed inside SMM. The CPU context (all registers, segment descriptors, and memory-type ranges) is restored atomically, and control flow returns to the interrupted code or handler.", "pseudocode": "restore_cpu_state_from_smm_save_area();\nreturn_eip ← SMM_SAVE_AREA[return_address_offset];\njump(return_eip);", "example": "RSM"} {"mnemonic": "bswap", "architecture": "x86", "full_name": "Byte Swap", "summary": "Reverses the byte order of a 32/64-bit register.", "syntax": "BSWAP r", "encoding": {"format": "Legacy", "hex_opcode": "0F C8", "visual_parts": [], "binary_pattern": "0F | C8", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r", "desc": "General-purpose register"}], "description": "Reverses the byte order within a 32-bit or 64-bit general-purpose register. In 32-bit mode, bits [7:0] swap with [31:24] and bits [15:8] swap with [23:16]. In 64-bit mode, all 8 bytes are reversed. No flags are modified. For 16-bit operands, the instruction is undefined on modern processors.", "pseudocode": "if (operand_size == 32) {\n dest ← {dest[7:0], dest[15:8], dest[23:16], dest[31:24]};\n} else if (operand_size == 64) {\n dest ← {dest[7:0], dest[15:8], dest[23:16], dest[31:24], dest[39:32], dest[47:40], dest[55:48], dest[63:56]};\n}", "example": "BSWAP rax"} {"mnemonic": "cmpxchg8b", "architecture": "x86", "full_name": "Compare and Exchange 8 Bytes", "summary": "Atomically compares EDX:EAX with memory; swaps if equal.", "syntax": "CMPXCHG8B m64", "encoding": {"format": "Legacy", "hex_opcode": "0F C7 /1", "visual_parts": [], "binary_pattern": "0F | C7 | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "Base", "operands": [{"name": "dest", "type": "m64", "desc": "64-bit memory operand (quadword)"}], "description": "Atomically compares the 64-bit value in EDX:EAX with the 64-bit memory operand; if equal, the instruction exchanges the value in ECX:EBX with memory and clears ZF, otherwise it loads memory into EDX:EAX and sets ZF. The operation is atomic at the memory bus level on single-processor systems and uses locked semantics on multiprocessor systems. All arithmetic flags (OF, SF, ZF, AF, CF, PF) are updated based on the compare result; other flags are undefined.", "pseudocode": "value_memory ← [dest];\nif (EDX:EAX == value_memory) {\n [dest] ← ECX:EBX;\n ZF ← 1;\n} else {\n EDX:EAX ← value_memory;\n ZF ← 0;\n}\nOF, SF, AF, CF, PF undefined;", "example": "CMPXCHG8B [rbp-8]"} {"mnemonic": "addsubps", "architecture": "x86", "full_name": "Packed Single-FP Add/Subtract", "summary": "Adds odd elements, subtracts even elements (Complex Math).", "syntax": "ADDSUBPS xmm1, xmm2/m128", "encoding": {"format": "SSE3", "hex_opcode": "F2 0F D0", "visual_parts": [], "binary_pattern": "F2 | 0F | D0", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE3", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Performs packed single-precision floating-point addition on odd-indexed elements (1, 3) and subtraction on even-indexed elements (0, 2) within 128-bit XMM operands. The first operand is destination and implicitly source; the second operand is source from register or memory. Exceptions are not masked and follow standard SIMD exception handling. No flags are modified; denormalized inputs may generate exceptions depending on MXCSR settings.", "pseudocode": "dest[31:0] ← dest[31:0] - src[31:0];\ndest[63:32] ← dest[63:32] + src[63:32];\ndest[95:64] ← dest[95:64] - src[95:64];\ndest[127:96] ← dest[127:96] + src[127:96];", "example": "ADDSUBPS xmm1, xmm2/m128"} {"mnemonic": "haddps", "architecture": "x86", "full_name": "Horizontal Add Packed Single-Precision", "summary": "Adds adjacent float elements horizontally.", "syntax": "HADDPS xmm1, xmm2/m128", "encoding": {"format": "SSE3", "hex_opcode": "F2 0F 7C", "visual_parts": [], "binary_pattern": "F2 | 0F | 7C", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE3", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Adds adjacent pairs of single-precision floating-point values horizontally within 128-bit XMM registers. The instruction pairs elements from the destination and source operands, computing the sum of adjacent elements and storing results in the destination. No CPU flags are affected by this instruction.", "pseudocode": "dest[0:31] ← dest[0:31] + dest[32:63]\ndest[32:63] ← src[0:31] + src[32:63]\ndest[64:95] ← dest[64:95] + dest[96:127]\ndest[96:127] ← src[64:65] + src[96:127]", "example": "HADDPS xmm1, xmm2/m128"} {"mnemonic": "movddup", "architecture": "x86", "full_name": "Move One Double-FP and Duplicate", "summary": "Loads 64-bit double and duplicates it to fill 128-bit register.", "syntax": "MOVDDUP xmm1, xmm2/m64", "encoding": {"format": "SSE3", "hex_opcode": "F2 0F 12", "visual_parts": [], "binary_pattern": "F2 | 0F | 12", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE3", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m64", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Loads a 64-bit double-precision floating-point value from the source operand and duplicates it to fill the entire 128-bit XMM register destination. The lower 64 bits of the source are replicated to both the lower and upper 64 bits of the destination. No CPU flags are affected by this instruction.", "pseudocode": "temp64 ← src[0:63]\ndest[0:63] ← temp64\ndest[64:127] ← temp64", "example": "MOVDDUP xmm1, xmm2/m64"} {"mnemonic": "lddqu", "architecture": "x86", "full_name": "Load Unaligned Integer 128-bit", "summary": "Loads unaligned data avoiding split-line penalties.", "syntax": "LDDQU xmm1, m128", "encoding": {"format": "SSE3", "hex_opcode": "F2 0F F0", "visual_parts": [], "binary_pattern": "F2 | 0F | F0", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE3", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "m128", "desc": "128-bit memory operand"}], "description": "Loads 128 bits of unaligned integer data from memory into an XMM register without causing split-cache-line penalties on processors that support this instruction. This instruction provides better performance than MOVDQU for certain memory alignments. No CPU flags are affected by this instruction.", "pseudocode": "dest[0:127] ← mem[addr:addr+15]", "example": "LDDQU xmm1, [rbp-16]"} {"mnemonic": "pshufb", "architecture": "x86", "full_name": "Packed Shuffle Bytes", "summary": "Shuffles bytes according to indices in source operand.", "syntax": "PSHUFB xmm1, xmm2/m128", "encoding": {"format": "SSSE3", "hex_opcode": "66 0F 38 00", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 00", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSSE3", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Shuffles bytes within 128-bit operands using a shuffle control mask in the source operand. For each byte in the destination, the corresponding control byte in the source specifies which byte from the destination is placed in that position; if bit 7 of the control byte is set, the result byte is zeroed. No CPU flags are affected by this instruction.", "pseudocode": "for i ← 0 to 15 do\n if src[i*8+7] == 1 then\n dest[i*8:i*8+7] ← 0\n else\n j ← src[i*8:i*8+3]\n dest[i*8:i*8+7] ← dest[j*8:j*8+7]\n end if\nend for", "example": "PSHUFB xmm1, xmm2/m128"} {"mnemonic": "phaddw", "architecture": "x86", "full_name": "Packed Horizontal Add Word", "summary": "Adds adjacent 16-bit integers horizontally.", "syntax": "PHADDW xmm1, xmm2/m128", "encoding": {"format": "SSSE3", "hex_opcode": "66 0F 38 01", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 01", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSSE3", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Adds adjacent pairs of signed 16-bit integer values horizontally within 128-bit XMM registers. Two pairs are summed from the destination operand and two pairs from the source operand, with results placed in the lower and upper halves of the destination. No CPU flags are affected by this instruction.", "pseudocode": "dest[0:15] ← dest[0:15] + dest[16:31]\ndest[16:31] ← dest[32:47] + dest[48:63]\ndest[32:47] ← src[0:15] + src[16:31]\ndest[48:63] ← src[32:47] + src[48:63]\ndest[64:79] ← dest[64:79] + dest[80:95]\ndest[80:95] ← dest[96:111] + dest[112:127]\ndest[96:111] ← src[64:79] + src[80:95]\ndest[112:127] ← src[96:111] + src[112:127]", "example": "PHADDW xmm1, xmm2/m128"} {"mnemonic": "palignr", "architecture": "x86", "full_name": "Packed Align Right", "summary": "Concatenates dest and src, extracts 128 bits byte-aligned.", "syntax": "PALIGNR xmm1, xmm2/m128, imm8", "encoding": {"format": "SSSE3", "hex_opcode": "66 0F 3A 0F", "visual_parts": [], "binary_pattern": "66 | 0F | 3A | 0F", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSSE3", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Concatenates the 128-bit destination and 128-bit source operands into a 256-bit intermediate value, then extracts a 128-bit aligned region starting at a byte offset specified by an 8-bit immediate value. The result is stored in the destination operand. No CPU flags are affected by this instruction.", "pseudocode": "concat[0:255] ← (src[0:127] << 128) | dest[0:127]\nshift_amount ← imm8 * 8\nif shift_amount >= 128 then\n result ← 0\nelse\n result ← concat[shift_amount:shift_amount+127]\nend if\ndest[0:127] ← result", "example": "PALIGNR xmm1, xmm2/m128, 3"} {"mnemonic": "pmulhrsw", "architecture": "x86", "full_name": "Packed Multiply High with Round and Scale", "summary": "Multiplies signed 16-bit words, rounds, and scales.", "syntax": "PMULHRSW xmm1, xmm2/m128", "encoding": {"format": "SSSE3", "hex_opcode": "66 0F 38 0B", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 0B", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSSE3", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Multiplies signed 16-bit integers from destination and source operands, returning the scaled and rounded high 16 bits of the 32-bit product (result = (product + 0x4000) >> 15). Saturation occurs if the result exceeds the signed 16-bit range. No CPU flags are affected by this instruction.", "pseudocode": "for i ← 0 to 7 do\n product[i] ← dest[i*16:i*16+15] * src[i*16:i*16+15]\n intermediate[i] ← product[i] + 0x4000\n result[i] ← intermediate[i] >> 15\n if result[i] > 32767 then\n dest[i*16:i*16+15] ← 32767\n else if result[i] < -32768 then\n dest[i*16:i*16+15] ← -32768\n else\n dest[i*16:i*16+15] ← result[i]\n end if\nend for", "example": "PMULHRSW xmm1, xmm2/m128"} {"mnemonic": "psignb", "architecture": "x86", "full_name": "Packed Sign Byte", "summary": "Negates/Zeroes bytes in dest based on sign of src.", "syntax": "PSIGNB xmm1, xmm2/m128", "encoding": {"format": "SSSE3", "hex_opcode": "66 0F 38 08", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 08", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSSE3", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Negates or zeros bytes in the destination operand based on the sign of corresponding bytes in the source operand. If the source byte is negative, the destination byte is negated; if zero, the destination byte is zeroed; if positive, the destination byte is unchanged. No CPU flags are affected by this instruction.", "pseudocode": "for i ← 0 to 15 do\n if src[i*8:i*8+7] < 0 then\n dest[i*8:i*8+7] ← -dest[i*8:i*8+7]\n else if src[i*8:i*8+7] == 0 then\n dest[i*8:i*8+7] ← 0\n else\n dest[i*8:i*8+7] ← dest[i*8:i*8+7]\n end if\nend for", "example": "PSIGNB xmm1, xmm2/m128"} {"mnemonic": "pabsb", "architecture": "x86", "full_name": "Packed Absolute Value Byte", "summary": "Computes absolute value of bytes.", "syntax": "PABSB xmm1, xmm2/m128", "encoding": {"format": "SSSE3", "hex_opcode": "66 0F 38 1C", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 1C", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSSE3", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Computes the absolute value of each signed byte in the source operand and stores the result in the destination XMM register. All 16 bytes are processed in parallel; the value 0x80 (-128) is handled specially and remains 0x80. No flags are affected by this instruction.", "pseudocode": "for i = 0 to 15:\n byte = src[i]\n if byte == 0x80:\n dest[i] ← 0x80\n else if byte < 0:\n dest[i] ← -byte\n else:\n dest[i] ← byte", "example": "PABSB xmm1, xmm2/m128"} {"mnemonic": "blendps", "architecture": "x86", "full_name": "Blend Packed Single-Precision", "summary": "Selects floats from two sources based on immediate mask.", "syntax": "BLENDPS xmm1, xmm2/m128, imm8", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 3A 0C", "visual_parts": [], "binary_pattern": "66 | 0F | 3A | 0C", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Selects single-precision floating-point values from two sources based on bit positions in an 8-bit immediate; bits 0-3 each control selection of one 32-bit element (0 selects dest, 1 selects src). Requires SSE4.1. No flags are affected.", "pseudocode": "for i = 0 to 3:\n bit_pos = i\n if (imm8 >> bit_pos) & 1:\n dest[i*32 : i*32+31] ← src[i*32 : i*32+31]\n else:\n dest[i*32 : i*32+31] ← dest[i*32 : i*32+31]", "example": "BLENDPS xmm1, xmm2/m128, 3"} {"mnemonic": "pblendw", "architecture": "x86", "full_name": "Packed Blend Words", "summary": "Selects words from two sources based on immediate mask.", "syntax": "PBLENDW xmm1, xmm2/m128, imm8", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 3A 0E", "visual_parts": [], "binary_pattern": "66 | 0F | 3A | 0E", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Selects 16-bit word values from two sources based on bit positions in an 8-bit immediate; bits 0-7 each control selection of one 16-bit word element (0 selects dest, 1 selects src). Requires SSE4.1. No flags are affected.", "pseudocode": "for i = 0 to 7:\n bit_pos = i\n if (imm8 >> bit_pos) & 1:\n dest[i*16 : i*16+15] ← src[i*16 : i*16+15]\n else:\n dest[i*16 : i*16+15] ← dest[i*16 : i*16+15]", "example": "PBLENDW xmm1, xmm2/m128, 3"} {"mnemonic": "adc", "architecture": "x86", "full_name": "Add with Carry", "summary": "Adds operands and the Carry Flag (CF).", "syntax": "ADC r/m, r", "encoding": {"format": "Legacy", "hex_opcode": "11", "length": "2+", "visual_parts": [], "binary_pattern": "11", "bit_positions": "+0"}, "operands": [{"name": "dest", "desc": "Reg/Mem"}, {"name": "src", "desc": "Reg"}], "extension": "Base", "description": "Adds the source operand and the Carry Flag (CF) to the destination operand, storing the result in the destination. Supports 8/16/32/64-bit sizes (64-bit in long mode only). Sets CF on unsigned overflow, SF/ZF/AF/OF/PF based on result; CF is critical for multi-precision arithmetic chains.", "pseudocode": "result ← dest + src + CF\ndest ← result\nCF ← unsigned_overflow(dest_old, src, CF)\nOF ← signed_overflow(dest_old, src, result)\nZF ← (result == 0)\nSF ← (result_sign_bit == 1)\nAF ← ((dest_old & 0xF) + (src & 0xF) + CF) > 0xF\nPF ← popcount(result & 0xFF) is even", "example": "ADC rbx, rax"} {"mnemonic": "sbb", "architecture": "x86", "full_name": "Subtract with Borrow", "summary": "Subtracts operands and the Carry Flag (CF).", "syntax": "SBB r/m, r", "encoding": {"format": "Legacy", "hex_opcode": "19", "length": "2+", "visual_parts": [], "binary_pattern": "19", "bit_positions": "+0"}, "operands": [{"name": "dest", "desc": "Reg/Mem"}, {"name": "src", "desc": "Reg"}], "extension": "Base", "description": "Subtracts the source operand and the Carry Flag (CF) from the destination operand, storing the result in the destination. Supports 8/16/32/64-bit sizes (64-bit in long mode only). Sets CF on unsigned borrow, SF/ZF/AF/OF/PF based on result; CF enables multi-precision subtraction chains.", "pseudocode": "result ← dest - src - CF\ndest ← result\nCF ← unsigned_borrow(dest_old, src, CF)\nOF ← signed_overflow(dest_old, src, result)\nZF ← (result == 0)\nSF ← (result_sign_bit == 1)\nAF ← ((dest_old & 0xF) - (src & 0xF) - CF) has unsigned borrow\nPF ← popcount(result & 0xFF) is even", "example": "SBB rbx, rax"} {"mnemonic": "shld", "architecture": "x86", "full_name": "Double Precision Shift Left", "summary": "Shifts dest left, filling with bits from src.", "syntax": "SHLD r/m, r, imm8", "encoding": {"format": "Legacy", "hex_opcode": "0F A4", "length": "4+", "visual_parts": [], "binary_pattern": "0F | A4", "bit_positions": "+0 | +1"}, "operands": [{"name": "dest", "desc": "Reg/Mem"}, {"name": "fill", "desc": "Reg"}, {"name": "count", "desc": "Imm"}], "extension": "Base", "description": "Shifts the destination operand left by a count, filling the vacated bits from the most-significant bits of the source operand. Supports 16/32/64-bit operands; count comes from the immediate or implicitly from CL. Sets CF to the last bit shifted out, OF if count=1, SF/ZF/PF based on the result.", "pseudocode": "if count > operand_width:\n count ← count mod (operand_width + 1)\nif count == 0:\n skip\nelse:\n CF ← bit_shifted_out_from_left\n dest ← (dest << count) | (src >> (operand_width - count))\n if count == 1:\n OF ← (dest_sign_bit_after != CF)\n else:\n OF ← undefined\n ZF ← (dest == 0)\n SF ← (dest_sign_bit == 1)\n PF ← popcount(dest & 0xFF) is even", "example": "SHLD rbx, rax, 3"} {"mnemonic": "shrd", "architecture": "x86", "full_name": "Double Precision Shift Right", "summary": "Shifts dest right, filling with bits from src.", "syntax": "SHRD r/m, r, imm8", "encoding": {"format": "Legacy", "hex_opcode": "0F AC", "length": "4+", "visual_parts": [], "binary_pattern": "0F | AC", "bit_positions": "+0 | +1"}, "operands": [{"name": "dest", "desc": "Reg/Mem"}, {"name": "fill", "desc": "Reg"}, {"name": "count", "desc": "Imm"}], "extension": "Base", "description": "Shifts the destination operand right by a count, filling the vacated bits from the least-significant bits of the source operand. Supports 16/32/64-bit operands; count comes from the immediate or implicitly from CL. Sets CF to the last bit shifted out, OF if count=1, SF/ZF/PF based on the result.", "pseudocode": "if count > operand_width:\n count ← count mod (operand_width + 1)\nif count == 0:\n skip\nelse:\n CF ← bit_shifted_out_from_right\n dest ← (dest >> count) | (src << (operand_width - count))\n if count == 1:\n OF ← (dest_sign_bit_after != bit_was_at_position_width_1)\n else:\n OF ← undefined\n ZF ← (dest == 0)\n SF ← (dest_sign_bit == 1)\n PF ← popcount(dest & 0xFF) is even", "example": "SHRD rbx, rax, 3"} {"mnemonic": "vpermb", "architecture": "x86", "full_name": "Permute Packed Bytes", "summary": "Permutes bytes in ZMM based on index vector.", "syntax": "VPERMB zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W0 8D /r", "length": "6+", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 8D", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "operands": [{"name": "dest", "desc": "ZMM"}, {"name": "idx", "desc": "ZMM"}, {"name": "src", "desc": "ZMM/Mem"}], "extension": "AVX-512-VBMI", "description": "Permutes bytes within 64-byte blocks of a ZMM register using a 512-bit index vector; each byte in the index selects a source byte (bits 3-0 select lane, bits 6-4 select byte within 64-byte lane). Requires AVX-512-VBMI. Supports write-masking via {k1}. No flags are affected.", "pseudocode": "for lane = 0 to 7:\n for byte_in_lane = 0 to 63:\n idx_byte = zmm2[lane*64 + byte_in_lane]\n src_lane = idx_byte & 0x7\n src_byte_offset = idx_byte >> 3\n if src_byte_offset < 64:\n selected = zmm3[src_lane*64 + src_byte_offset]\n else:\n selected = 0\n if k1[byte_in_lane] or k1 is not used:\n zmm1[lane*64 + byte_in_lane] ← selected", "example": "VPERMB zmm1, zmm2, zmm3/m512"} {"mnemonic": "vpermi2b", "architecture": "x86", "full_name": "Permute Two-Source Bytes", "summary": "Shuffles bytes from two ZMM registers into destination.", "syntax": "VPERMI2B zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W0 75 /r", "length": "6+", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 75", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "operands": [{"name": "dest", "desc": "ZMM"}, {"name": "idx", "desc": "ZMM"}, {"name": "src", "desc": "ZMM/Mem"}], "extension": "AVX-512-VBMI", "description": "Permutes bytes from two ZMM registers (destination and source) using byte indices in the second source, storing results in the destination. The instruction performs a gather-like operation where each byte index selects from either the destination or source register based on the high bit. No flags are modified; the operation is masked by the opmask register k1, with zeroing or merging semantics.", "pseudocode": "for i = 0 to 63:\n idx = zmm2[8*i:8*i+7]\n if idx[7] == 0:\n zmm1[8*i:8*i+7] ← zmm1[8*(idx[6:0]):8*(idx[6:0])+7]\n else:\n zmm1[8*i:8*i+7] ← zmm3[8*(idx[6:0]):8*(idx[6:0])+7]\n zmm1[8*i:8*i+7] ← zmm1[8*i:8*i+7] & k1_mask[i]", "example": "VPERMI2B zmm1, zmm2, zmm3/m512"} {"mnemonic": "vpermt2b", "architecture": "x86", "full_name": "Permute Two-Source Bytes (Overwrite)", "summary": "Shuffles bytes from two sources, overwriting index.", "syntax": "VPERMT2B zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W0 7D /r", "length": "6+", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 7D", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "operands": [{"name": "dest", "desc": "ZMM"}, {"name": "idx", "desc": "ZMM"}, {"name": "src", "desc": "ZMM/Mem"}], "extension": "AVX-512-VBMI", "description": "Permutes bytes from two sources using indices in the destination register (which is overwritten), selecting from either the index register or the second source based on the index's high bit. This is the two-operand form where indices reside in what becomes the output. No flags are modified; masking via k1 applies to the result with optional zeroing.", "pseudocode": "for i = 0 to 63:\n idx = zmm1[8*i:8*i+7]\n if idx[7] == 0:\n result[8*i:8*i+7] ← zmm2[8*(idx[6:0]):8*(idx[6:0])+7]\n else:\n result[8*i:8*i+7] ← zmm3[8*(idx[6:0]):8*(idx[6:0])+7]\n zmm1[8*i:8*i+7] ← result[8*i:8*i+7] & k1_mask[i]", "example": "VPERMT2B zmm1, zmm2, zmm3/m512"} {"mnemonic": "vpmultishiftqb", "architecture": "x86", "full_name": "Select Packed Unaligned Bytes from Quadword Sources", "summary": "Selects bytes from each 64-bit element based on shift control.", "syntax": "VPMULTISHIFTQB zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W1 83 /r", "length": "6+", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 83", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "operands": [{"name": "dest", "desc": "ZMM"}, {"name": "ctrl", "desc": "ZMM"}, {"name": "src", "desc": "ZMM/Mem"}], "extension": "AVX-512-VBMI", "description": "Selects bytes from each 64-bit element by using 4-bit shift control values extracted from the control ZMM register. Each 8-bit control field specifies which of 8 bytes within its 64-bit source element to extract into each output byte. No flags are modified; the operation respects the opmask k1 for selective writing.", "pseudocode": "for i = 0 to 7: // 8 quadwords (64-bit elements)\n for j = 0 to 7: // 8 bytes within each quadword\n shift_val = zmm2[64*i+4*j+3:64*i+4*j]\n zmm1[64*i+8*j+7:64*i+8*j] ← zmm3[64*i + 8*shift_val + 7 : 64*i + 8*shift_val]\n zmm1[64*i+8*j+7:64*i+8*j] ← zmm1[64*i+8*j+7:64*i+8*j] & k1_mask[64*i+8*j:64*i+8*j+7]", "example": "VPMULTISHIFTQB zmm1, zmm2, zmm3/m512"} {"mnemonic": "vpshldd", "architecture": "x86", "full_name": "Packed Shift Left Double Concatenate", "summary": "Funnel shift left of doublewords.", "syntax": "VPSHLDD zmm1 {k1}, zmm2, zmm3/m512, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F3A.W0 71 /r /ib", "length": "6+", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 3A | 71", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "operands": [{"name": "dest", "desc": "ZMM"}, {"name": "src1", "desc": "ZMM"}, {"name": "src2", "desc": "ZMM/Mem"}, {"name": "cnt", "desc": "Imm"}], "extension": "AVX-512-VBMI2", "description": "Performs a funnel left-shift (double concatenate) on 32-bit doublewords: each output doubleword is the logical left-shift result of concatenating src2 into src1, shifted left by the immediate count. Bits shifted out on the left are discarded; bits from src2 fill in on the right. No arithmetic flags are modified; the operation is EVEX-encoded with masking support via k1.", "pseudocode": "for i = 0 to 15: // 16 doublewords\n concatenated = (zmm2[32*i+31:32*i] << 32) | zmm3[32*i+31:32*i]\n shift_amount = cnt & 0x1F\n zmm1[32*i+31:32*i] ← (concatenated >> (32 - shift_amount)) & 0xFFFFFFFF\n zmm1[32*i+31:32*i] ← zmm1[32*i+31:32*i] & k1_mask[i]", "example": "VPSHLDD zmm1, zmm2, zmm3/m512, 3"} {"mnemonic": "vpshrdd", "architecture": "x86", "full_name": "Packed Shift Right Double Concatenate", "summary": "Funnel shift right of doublewords.", "syntax": "VPSHRDD zmm1 {k1}, zmm2, zmm3/m512, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F3A.W0 73 /r /ib", "length": "6+", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 3A | 73", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "operands": [{"name": "dest", "desc": "ZMM"}, {"name": "src1", "desc": "ZMM"}, {"name": "src2", "desc": "ZMM/Mem"}, {"name": "cnt", "desc": "Imm"}], "extension": "AVX-512-VBMI2", "description": "Performs a funnel right-shift (double concatenate) on 32-bit doublewords: each output doubleword is the logical right-shift result of concatenating src1 and src2, shifted right by the immediate count. Bits shifted out on the right are discarded; bits from src1 fill in on the left. No arithmetic flags are modified; masking via k1 applies to the result.", "pseudocode": "for i = 0 to 15: // 16 doublewords\n concatenated = (zmm2[32*i+31:32*i] << 32) | zmm3[32*i+31:32*i]\n shift_amount = cnt & 0x1F\n zmm1[32*i+31:32*i] ← (concatenated >> shift_amount) & 0xFFFFFFFF\n zmm1[32*i+31:32*i] ← zmm1[32*i+31:32*i] & k1_mask[i]", "example": "VPSHRDD zmm1, zmm2, zmm3/m512, 3"} {"mnemonic": "vpcompressb", "architecture": "x86", "full_name": "Store Sparse Packed Byte Integer Values", "summary": "Compresses active bytes from ZMM to memory.", "syntax": "VPCOMPRESSB m512 {k1}, zmm1", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W0 63 /r", "length": "6+", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 63", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "operands": [{"name": "dest", "desc": "Mem"}, {"name": "src", "desc": "ZMM"}], "extension": "AVX-512-VBMI2", "description": "Stores bytes from ZMM into memory at sparse, mask-selected positions: only bytes where the corresponding opmask bit k1 is set are written to consecutive memory locations. The instruction performs a contiguous write of active bytes while maintaining their relative order. No flags are modified; this is a memory write operation with variable length determined by the popcount of the mask.", "pseudocode": "byte_count = 0\nfor i = 0 to 63:\n if k1_mask[i] == 1:\n mem[byte_count] ← zmm1[8*i+7:8*i]\n byte_count += 1", "example": "VPCOMPRESSB [rbp-64], zmm1"} {"mnemonic": "vpexpandb", "architecture": "x86", "full_name": "Load Sparse Packed Byte Integer Values", "summary": "Expands bytes from memory into sparse locations in ZMM.", "syntax": "VPEXPANDB zmm1 {k1}, m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W0 62 /r", "length": "6+", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 62", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "operands": [{"name": "dest", "desc": "ZMM"}, {"name": "src", "desc": "Mem"}], "extension": "AVX-512-VBMI2", "description": "Loads bytes from memory into sparse, mask-selected positions in ZMM: bytes at consecutive memory locations are placed into ZMM positions where the opmask k1 is set, with unmasked positions remaining zero or unchanged. This is the inverse of compress. No flags are modified; the operation fills a sparse vector from compact memory data.", "pseudocode": "byte_count = 0\nfor i = 0 to 63:\n if k1_mask[i] == 1:\n zmm1[8*i+7:8*i] ← mem[byte_count]\n byte_count += 1\n else:\n zmm1[8*i+7:8*i] ← 0 // or unchanged if merging mode", "example": "VPEXPANDB zmm1, [rbp-64]"} {"mnemonic": "vpopcntb", "architecture": "x86", "full_name": "Packed Population Count Byte", "summary": "Counts set bits in each byte.", "syntax": "VPOPCNTB zmm1 {k1}, zmm2/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W0 54 /r", "length": "6+", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 54", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "operands": [{"name": "dest", "desc": "ZMM"}, {"name": "src", "desc": "ZMM/Mem"}], "extension": "AVX-512-BITALG", "description": "Counts the number of set bits (population count) in each byte of the source, writing the count (0-8) into the corresponding byte of the destination. This operates independently on each of 64 bytes in the ZMM register. No arithmetic flags are modified; the instruction is part of AVX-512-BITALG and supports masking via k1.", "pseudocode": "for i = 0 to 63:\n count = 0\n byte_val = zmm2[8*i+7:8*i]\n for bit = 0 to 7:\n if byte_val[bit] == 1:\n count += 1\n zmm1[8*i+7:8*i] ← count & k1_mask[i]", "example": "VPOPCNTB zmm1, zmm2/m512"} {"mnemonic": "vpshufbitqmb", "architecture": "x86", "full_name": "Shuffle Bits from Quadword Elements to Mask", "summary": "Extracts bits from bytes and packs into a mask register.", "syntax": "VPSHUFBITQMB k1 {k2}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W0 8F /r", "length": "6+", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 8F", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "operands": [{"name": "dest", "desc": "k-reg"}, {"name": "src1", "desc": "ZMM"}, {"name": "src2", "desc": "ZMM/Mem"}], "extension": "AVX-512-BITALG", "description": "Extracts bits from quadword elements using a shuffle pattern and packs them into a mask register. The operation uses zmm3/m512 as a bit-select control for each bit position in zmm2, extracting one bit per control byte and combining results into an 8-bit or 16-bit mask. This is a non-SIMD operation that produces only a mask output; no arithmetic flags are modified.", "pseudocode": "for (i = 0; i < 64; i++) {\n byte_idx = zmm3[8*i : 8*i+7];\n if (byte_idx < 64) {\n bit = zmm2[byte_idx];\n } else {\n bit = 0;\n }\n k1[i] = bit;\n}\nk1 = k1 & k2;", "example": "VPSHUFBITQMB k1, zmm2, zmm3/m512"} {"mnemonic": "vp2intersectd", "architecture": "x86", "full_name": "Compute Intersection Pair Doublewords", "summary": "Computes intersection of two ZMM registers into mask pair.", "syntax": "VP2INTERSECTD k1+1, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.NDS.512.F2.0F38.W0 68 /r", "length": "6+", "visual_parts": [], "binary_pattern": "EVEX | F2 | 0F | 38 | 68", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "operands": [{"name": "kdest", "desc": "k-pair"}, {"name": "src1", "desc": "ZMM"}, {"name": "src2", "desc": "ZMM/Mem"}], "extension": "AVX-512-VP2INTERSECT", "description": "Computes the intersection of two sets of doublewords and produces a pair of mask registers (k1 and k1+1). Each 32-bit element in zmm2 is compared against all elements in zmm3/m512; k1 contains matches at each position, and k1+1 contains match counts or indices. No arithmetic flags are modified; results are written only to the mask pair.", "pseudocode": "match_mask = 0;\nmatch_count = 0;\nfor (i = 0; i < 16; i++) {\n matches = 0;\n for (j = 0; j < 16; j++) {\n if (zmm2[32*i : 32*i+31] == zmm3[32*j : 32*j+31]) {\n matches = 1;\n break;\n }\n }\n match_mask = match_mask | (matches << i);\n if (matches) match_count++;\n}\nk1 = match_mask;\nk2 = match_count;", "example": "VP2INTERSECTD k1+1, zmm2, zmm3/m512"} {"mnemonic": "vpmadd52luq", "architecture": "x86", "full_name": "Packed Multiply-Add Unsigned 52-bit Integers (Low)", "summary": "Fused multiply-add for 52-bit integers (Low 52 bits).", "syntax": "VPMADD52LUQ zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W1 B4 /r", "length": "6+", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | B4", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "operands": [{"name": "dest", "desc": "ZMM"}, {"name": "src1", "desc": "ZMM"}, {"name": "src2", "desc": "ZMM/Mem"}], "extension": "AVX-512-IFMA", "description": "Performs a fused multiply-add operation on 52-bit unsigned integers, extracting the lower 52 bits of the 104-bit product and accumulating into the destination. For each 64-bit lane: compute (zmm2[63:0] * zmm3[63:0]) + (zmm1[63:0]), extract bits [51:0], and write back to zmm1. Supports masking via k1; no arithmetic flags are modified.", "pseudocode": "for (i = 0; i < 8; i++) {\n idx = 64*i;\n product = zmm2[idx+63 : idx] * zmm3[idx+63 : idx];\n sum = (product + zmm1[idx+63 : idx]);\n result = sum & 0xFFFFFFFFFFFFF; // 52 bits\n zmm1[idx+63 : idx] = result;\n if (k1[i]) zmm1[idx+63 : idx] = result;\n}", "example": "VPMADD52LUQ zmm1, zmm2, zmm3/m512"} {"mnemonic": "vpmadd52huq", "architecture": "x86", "full_name": "Packed Multiply-Add Unsigned 52-bit Integers (High)", "summary": "Fused multiply-add for 52-bit integers (High 52 bits).", "syntax": "VPMADD52HUQ zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W1 B5 /r", "length": "6+", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | B5", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "operands": [{"name": "dest", "desc": "ZMM"}, {"name": "src1", "desc": "ZMM"}, {"name": "src2", "desc": "ZMM/Mem"}], "extension": "AVX-512-IFMA", "description": "Performs a fused multiply-add operation on 52-bit unsigned integers, extracting the upper 52 bits of the 104-bit product and accumulating into the destination. For each 64-bit lane: compute (zmm2[63:0] * zmm3[63:0]) + (zmm1[63:0]), extract bits [103:52], and write back to zmm1. Supports masking via k1; no arithmetic flags are modified.", "pseudocode": "for (i = 0; i < 8; i++) {\n idx = 64*i;\n product = zmm2[idx+63 : idx] * zmm3[idx+63 : idx];\n sum = (product + zmm1[idx+63 : idx]);\n result = (sum >> 52) & 0xFFFFFFFFFFFFF; // upper 52 bits\n if (k1[i]) zmm1[idx+63 : idx] = result;\n}", "example": "VPMADD52HUQ zmm1, zmm2, zmm3/m512"} {"mnemonic": "aadd", "architecture": "x86", "full_name": "Atomically Add", "summary": "Atomically adds a value to a remote memory location.", "syntax": "AADD m32, r32", "encoding": {"format": "VEX", "hex_opcode": "NP 0F 38 FC !(11):rrr:bbb", "length": "5+", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | FC", "bit_positions": "+0 | +1 | +2 | +3"}, "operands": [{"name": "dest", "desc": "Mem"}, {"name": "src", "desc": "Reg"}], "extension": "RAO-INT", "description": "Atomically adds a 32-bit register value to a memory location without acquiring a lock and without returning the old value. This is a remote atomic operation that guarantees atomicity at the hardware level via cache coherency; the instruction does not serialize the entire pipeline but may have store ordering implications. No flags are modified; this is a write-only operation to memory.", "pseudocode": "atomic_add([dest], src);\n// Semantically: [dest] ← [dest] + src", "example": "AADD [rbp-4], eax"} {"mnemonic": "aand", "architecture": "x86", "full_name": "Atomically AND", "summary": "Atomically ANDs a value to a remote memory location.", "syntax": "AAND m32, r32", "encoding": {"format": "VEX", "hex_opcode": "66 0F 38 FC !(11):rrr:bbb", "length": "5+", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | FC | ModRM", "bit_positions": "+0 | +1 | +2 | +3 | +4"}, "operands": [{"name": "dest", "desc": "Mem"}, {"name": "src", "desc": "Reg"}], "extension": "RAO-INT", "description": "Atomically ANDs a 32-bit register value with a memory location without acquiring a lock and without returning the old value. This remote atomic operation guarantees atomicity via cache coherency mechanisms; it does not serialize the entire pipeline but provides store-ordering guarantees. No flags are modified.", "pseudocode": "atomic_and([dest], src);\n// Semantically: [dest] ← [dest] & src", "example": "AAND [rbp-4], eax"} {"mnemonic": "aor", "architecture": "x86", "full_name": "Atomically OR", "summary": "Atomically ORs a value to a remote memory location.", "syntax": "AOR m32, r32", "encoding": {"format": "VEX", "hex_opcode": "F2 0F 38 FC !(11):rrr:bbb", "length": "5+", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | FC | ModRM", "bit_positions": "+0 | +1 | +2 | +3 | +4"}, "operands": [{"name": "dest", "desc": "Mem"}, {"name": "src", "desc": "Reg"}], "extension": "RAO-INT", "description": "Atomically ORs a 32-bit register value with a memory location without acquiring a lock and without returning the old value. This remote atomic operation uses cache coherency to guarantee atomicity; it does not serialize the full pipeline but enforces store ordering. No flags are modified.", "pseudocode": "atomic_or([dest], src);\n// Semantically: [dest] ← [dest] | src", "example": "AOR [rbp-4], eax"} {"mnemonic": "axor", "architecture": "x86", "full_name": "Atomically XOR", "summary": "Atomically XORs a value to a remote memory location.", "syntax": "AXOR m32, r32", "encoding": {"format": "VEX", "hex_opcode": "F3 0F 38 FC !(11):rrr:bbb", "length": "5+", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | FC | ModRM", "bit_positions": "+0 | +1 | +2 | +3 | +4"}, "operands": [{"name": "dest", "desc": "Mem"}, {"name": "src", "desc": "Reg"}], "extension": "RAO-INT", "description": "Atomically XORs a 32-bit register value with a memory location without acquiring a lock and without returning the old value. This remote atomic operation guarantees atomicity through cache coherency; it does not serialize the entire pipeline but maintains store-ordering properties. No flags are modified.", "pseudocode": "atomic_xor([dest], src);\n// Semantically: [dest] ← [dest] ^ src", "example": "AXOR [rbp-4], eax"} {"mnemonic": "cmpccxadd", "architecture": "x86", "full_name": "Compare and Add if Condition is Met", "summary": "Atomically adds if condition is met.", "syntax": "CMPccXADD m32, r32, r32", "encoding": {"format": "EVEX", "hex_opcode": "VEX.128.66.0F38.W0 E0 /r", "length": "6+", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | E0", "bit_positions": "+0 | +1 | +2 | +3"}, "operands": [{"name": "dest", "desc": "Mem"}, {"name": "src1", "desc": "Reg"}, {"name": "src2", "desc": "Reg"}], "extension": "CMPccXADD", "description": "Atomically compares a value in memory with an operand and adds a second operand to memory if the condition is met. This instruction is part of the APX (Advanced Performance eXtensions) and operates under EVEX encoding with implicit condition code selection via the embedded immediate. The instruction performs a compare-and-add loop at the CPU microarchitecture level, setting ZF based on the comparison result and CF/OF/SF based on the add operation if executed.", "pseudocode": "temp ← [dest]; ZF ← (temp == src1); if (condition_met) { [dest] ← [dest] + src2; CF ← carry_from_add; OF ← overflow_from_add; SF ← sign_of_result; } src1 ← temp;", "example": "CMPccXADD [rbp-4], eax, eax"} {"mnemonic": "erets", "architecture": "x86", "full_name": "Event Return Supervisor", "summary": "Returns from an event handler to supervisor mode (FRED).", "syntax": "ERETS", "encoding": {"format": "Legacy", "hex_opcode": "F2 0F 01 CA", "length": "4", "visual_parts": [], "binary_pattern": "F2 | 0F | 01 | CA", "bit_positions": "+0 | +1 | +2 | +3"}, "operands": [], "extension": "FRED", "description": "Returns from a FRED (Flexible Return and Event Delivery) event handler in supervisor mode, restoring the interrupted execution context from the event stack. This instruction is part of the FRED extension and performs implicit stack unwinding and privilege level restoration. No flags are modified; this is a serializing instruction that also flushes the instruction cache.", "pseudocode": "// Returns from an event handler to supervisor mode (FRED)", "example": "ERETS"} {"mnemonic": "eretu", "architecture": "x86", "full_name": "Event Return User", "summary": "Returns from an event handler to user mode (FRED).", "syntax": "ERETU", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F 01 CA", "length": "4", "visual_parts": [], "binary_pattern": "F3 | 0F | 01 | CA", "bit_positions": "+0 | +1 | +2 | +3"}, "operands": [], "extension": "FRED", "description": "Returns from a FRED (Flexible Return and Event Delivery) event handler to user mode, restoring the interrupted user-level execution context from the event stack. This instruction is part of the FRED extension and performs implicit stack unwinding with privilege level transition. No flags are modified; this is a serializing instruction that flushes the instruction cache and clears sensitive state.", "pseudocode": "// Returns from an event handler to user mode (FRED)", "example": "ERETU"} {"mnemonic": "lkgs", "architecture": "x86", "full_name": "Load Kernel GS Base", "summary": "Loads the kernel GS base address (FRED support).", "syntax": "LKGS r16", "encoding": {"format": "Legacy", "hex_opcode": "F2 0F 00 /6", "length": "4+", "visual_parts": [], "binary_pattern": "F2 | 0F | 00 | ModRM", "bit_positions": "+0 | +1 | +2 | +3"}, "operands": [{"name": "src", "desc": "Reg"}], "extension": "LKGS", "description": "Loads a 16-bit selector or handle into the kernel GS base register, supporting FRED event delivery. The instruction reads from the specified register and updates the MSR-backed kernel GS base, used for exception handler context. This is a privileged instruction (CPL = 0) and does not modify any flags.", "pseudocode": "IA32_KERNEL_GS_BASE ← src;", "example": "LKGS ax"} {"mnemonic": "enqcmd", "architecture": "x86", "full_name": "Enqueue Command", "summary": "Writes a command to a device (DSA/IAA accelerator).", "syntax": "ENQCMD r32, m512", "encoding": {"format": "Legacy", "hex_opcode": "F2 0F 38 F8", "length": "5+", "visual_parts": [], "binary_pattern": "F2 | 0F | 38 | F8", "bit_positions": "+0 | +1 | +2 | +3"}, "operands": [{"name": "dest", "desc": "Reg"}, {"name": "src", "desc": "Mem"}], "extension": "ENQCMD", "description": "Atomically enqueues a 512-bit command descriptor from memory to a device queue (DSA/IAA accelerator), writing a doorbell or status register via the destination register. The instruction performs an atomic write to the device, and ZF is set to indicate success or failure of the enqueue operation. This is a non-temporal memory operation and does not cache the 512-bit data.", "pseudocode": "// Writes a command to a device (DSA/IAA accelerator)", "example": "ENQCMD eax, [rbp-64]"} {"mnemonic": "pconfig", "architecture": "x86", "full_name": "Platform Configuration", "summary": "Configures platform features like MKTME (Memory Encryption).", "syntax": "PCONFIG", "encoding": {"format": "Legacy", "hex_opcode": "NP 0F 01 C5", "length": "3", "visual_parts": [], "binary_pattern": "0F | 01 | C5", "bit_positions": "+0 | +1 | +2"}, "operands": [], "extension": "PCONFIG", "description": "Performs platform configuration operations such as MKTME (Memory Key Total Memory Encryption) setup, with the operation type specified implicitly via EAX. This is a privileged instruction (CPL = 0) that modifies platform encryption keys and memory encryption metadata. The instruction may serialize the pipeline and has implementation-dependent effects on cache coherency.", "pseudocode": "// Configures platform features like MKTME (Memory Encryption)", "example": "PCONFIG"} {"mnemonic": "wbnoinvd", "architecture": "x86", "full_name": "Write Back and Do Not Invalidate Cache", "summary": "Writes back modified lines but keeps them valid in cache.", "syntax": "WBNOINVD", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F 09", "length": "3", "visual_parts": [], "binary_pattern": "F3 | 0F | 09", "bit_positions": "+0 | +1 | +2"}, "operands": [], "extension": "WBNOINVD", "description": "Writes back all modified cache lines to memory but keeps them valid in the L3 cache, improving performance compared to WBINVD which invalidates. This instruction is non-privileged and does not modify any flags. It provides write-back semantics without the full cache flush, useful for cache coherency operations while maintaining data locality.", "pseudocode": "// Writes back modified lines but keeps them valid in cache", "example": "WBNOINVD"} {"mnemonic": "aesencwide128kl", "architecture": "x86", "full_name": "AES Encrypt Wide 128-bit Key Locker", "summary": "Encrypts 8 blocks using 128-bit Key Locker handle.", "syntax": "AESENCWIDE128KL m128", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F 38 D8 !(11):000:bbb", "length": "5+", "visual_parts": [], "binary_pattern": "F3 | 0F | 38 | D8", "bit_positions": "+0 | +1 | +2 | +3"}, "operands": [{"name": "handle", "desc": "Mem"}], "extension": "KEYLOCKER_WIDE", "description": "Encrypts eight 128-bit blocks in parallel using a 128-bit Key Locker handle, performing wide-block AES encryption for high-throughput scenarios. The handle is loaded from memory and used to derive keys without exposing them, setting ZF to indicate success. This instruction operates on XMM0-XMM7 implicitly as input and output blocks, and clears sensitive key material after use.", "pseudocode": "handle ← [handle_mem]; if (valid_handle) { XMM0-XMM7 ← AES_ENC_WIDE_128(XMM0-XMM7, handle); ZF ← 0; } else { ZF ← 1; }", "example": "AESENCWIDE128KL [rbp-16]"} {"mnemonic": "aesencwide256kl", "architecture": "x86", "full_name": "AES Encrypt Wide 256-bit Key Locker", "summary": "Encrypts 8 blocks using 256-bit Key Locker handle.", "syntax": "AESENCWIDE256KL m128", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F 38 D8 !(11):010:bbb", "length": "5+", "visual_parts": [], "binary_pattern": "F3 | 0F | 38 | D8 | ModRM", "bit_positions": "+0 | +1 | +2 | +3 | +4"}, "operands": [{"name": "handle", "desc": "Mem"}], "extension": "KEYLOCKER_WIDE", "description": "Encrypts 8 consecutive 128-bit blocks using AES in ECB mode with a 256-bit key loaded from a Key Locker handle. This instruction is part of the Key Locker extension and requires the handle at the memory operand to be a valid, initialized 512-bit Key Locker structure. The instruction reads plaintext from XMM0-XMM7, encrypts all blocks in parallel, and writes ciphertext back to XMM0-XMM7; ZF is set to 0 on success or 1 if the handle is invalid or key usage limit exceeded.", "pseudocode": "handle ← [mem128]\nif (handle is invalid or usage_limit_exceeded) {\n ZF ← 1\n} else {\n for i = 0 to 7:\n XMM[i] ← AES_Encrypt_256(XMM[i], key_from_handle)\n ZF ← 0\n}", "example": "AESENCWIDE256KL [rbp-16]"} {"mnemonic": "fucom", "architecture": "x86", "full_name": "Unordered Compare Real", "summary": "Compares ST(0) with source (supports NaNs).", "syntax": "FUCOM ST(i)", "encoding": {"format": "Legacy", "hex_opcode": "DD E0+i", "length": "2", "visual_parts": [], "binary_pattern": "DD", "bit_positions": "+0"}, "operands": [{"name": "src", "desc": "Reg"}], "extension": "x87 FPU", "description": "Compares the top of the x87 FPU stack (ST(0)) with an operand (ST(i) by default) and sets condition code bits in the FPU status word. Unlike FCOM, FUCOM treats QNaN operands as comparable rather than signaling. The C3, C2, and C0 bits are set based on the comparison result (unordered, greater than, less than, or equal), and C1 is cleared.", "pseudocode": "if (is_unordered(ST(0), ST(i))) {\n C3 ← 1; C2 ← 1; C0 ← 1\n} else if (ST(0) > ST(i)) {\n C3 ← 0; C2 ← 0; C0 ← 0\n} else if (ST(0) < ST(i)) {\n C3 ← 0; C2 ← 0; C0 ← 1\n} else {\n C3 ← 1; C2 ← 0; C0 ← 0\n}\nC1 ← 0", "example": "FUCOM st(1)"} {"mnemonic": "frndint", "architecture": "x86", "full_name": "Round to Integer", "summary": "Rounds ST(0) to integer according to RC field.", "syntax": "FRNDINT", "encoding": {"format": "Legacy", "hex_opcode": "D9 FC", "length": "2", "visual_parts": [], "binary_pattern": "D9 | FC", "bit_positions": "+0 | +1"}, "operands": [], "extension": "x87 FPU", "description": "Rounds the value in ST(0) to an integer according to the rounding control (RC) field in the FPU control word (bits 10-11). The result remains in ST(0) as a floating-point number with zero fractional part. This instruction does not pop the stack and does not set exception flags.", "pseudocode": "ST(0) ← round_to_integer(ST(0), RC_field)", "example": "FRNDINT"} {"mnemonic": "fscale", "architecture": "x86", "full_name": "Scale", "summary": "Scales ST(0) by ST(1) (ST(0) * 2^ST(1)).", "syntax": "FSCALE", "encoding": {"format": "Legacy", "hex_opcode": "D9 FD", "length": "2", "visual_parts": [], "binary_pattern": "D9 | FD", "bit_positions": "+0 | +1"}, "operands": [], "extension": "x87 FPU", "description": "Scales ST(0) by raising 2 to the power of ST(1): ST(0) ← ST(0) × 2^ST(1). ST(1) must be an integer within the range [-2^31, 2^31-1]; if out of range or NaN, an invalid-operation exception is generated. The stack is not popped; ST(0) is replaced with the scaled result.", "pseudocode": "if (ST(1) is not integer or out_of_range) {\n raise_exception(invalid_operation)\n} else {\n ST(0) ← ST(0) * (2 ^ trunc(ST(1)))\n}", "example": "FSCALE"} {"mnemonic": "fxtract", "architecture": "x86", "full_name": "Extract Exponent and Significand", "summary": "Separates exponent and significand of ST(0).", "syntax": "FXTRACT", "encoding": {"format": "Legacy", "hex_opcode": "D9 F4", "length": "2", "visual_parts": [], "binary_pattern": "D9 | F4", "bit_positions": "+0 | +1"}, "operands": [], "extension": "x87 FPU", "description": "Separates ST(0) into its exponent (as an integer) and significand (as a number in [1, 2) or [0, ∞) for special values). The exponent is pushed onto the stack, and ST(0) is replaced with the significand, so the original value can be recovered as significand × 2^exponent. This operation logically duplicates and replaces ST(0), increasing stack depth.", "pseudocode": "exponent ← extract_exponent(ST(0))\nsignificand ← extract_significand(ST(0))\nFPU_stack_push(exponent)\nST(0) ← significand", "example": "FXTRACT"} {"mnemonic": "f2xm1", "architecture": "x86", "full_name": "Compute 2^x - 1", "summary": "Computes (2^ST(0)) - 1.", "syntax": "F2XM1", "encoding": {"format": "Legacy", "hex_opcode": "D9 F0", "length": "2", "visual_parts": [], "binary_pattern": "D9 | F0", "bit_positions": "+0 | +1"}, "operands": [], "extension": "x87 FPU", "description": "Computes 2^ST(0) - 1 and stores the result back in ST(0). ST(0) must be in the range [-1, 1] for accurate results; values outside this range produce undefined behavior or reduced accuracy. This instruction is used as part of logarithm and exponential function approximations in transcendental math libraries.", "pseudocode": "if (ST(0) < -1 or ST(0) > 1) {\n undefined_behavior()\n} else {\n ST(0) ← (2 ^ ST(0)) - 1\n}", "example": "F2XM1"} {"mnemonic": "fyl2xp1", "architecture": "x86", "full_name": "Compute y * log2(x + 1)", "summary": "Computes ST(1) * log2(ST(0) + 1).", "syntax": "FYL2XP1", "encoding": {"format": "Legacy", "hex_opcode": "D9 F9", "length": "2", "visual_parts": [], "binary_pattern": "D9 | F9", "bit_positions": "+0 | +1"}, "operands": [], "extension": "x87 FPU", "description": "Computes ST(1) × log₂(ST(0) + 1) and stores the result in ST(1), then pops ST(0). ST(0) must be in the range (-1, 1) for full accuracy. This instruction is optimized for computing logarithms of numbers close to 1 and is used in transcendental function implementations to reduce rounding error.", "pseudocode": "if (ST(0) <= -1 or ST(0) >= 1) {\n undefined_behavior()\n} else {\n result ← ST(1) * log2(ST(0) + 1)\n FPU_stack_pop()\n ST(0) ← result\n}", "example": "FYL2XP1"} {"mnemonic": "clrssbsy", "architecture": "x86", "full_name": "Clear Shadow Stack Busy Flag", "summary": "Clears the busy flag in the shadow stack token.", "syntax": "CLRSSBSY m64", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F AE !(11):110:bbb", "length": "4+", "visual_parts": [], "binary_pattern": "F3 | 0F | AE | ModRM", "bit_positions": "+0 | +1 | +2 | +3"}, "operands": [{"name": "token", "desc": "Mem"}], "extension": "CET-SS", "description": "Clears the busy flag (bit 0) of a shadow stack token located at the memory address specified by the operand. This instruction is part of Control-flow Enforcement Technology (CET) Shadow Stack and is used to mark a shadow stack token as no longer busy (e.g., after an exception handler has completed). ZF is set to 0 on success or 1 if the token address is misaligned or the token is invalid.", "pseudocode": "token_addr ← m64\nif (token_addr is misaligned or not_valid_token) {\n ZF ← 1\n} else {\n [token_addr] ← [token_addr] & ~(1) // Clear bit 0\n ZF ← 0\n}", "example": "CLRSSBSY [rbp-8]"} {"mnemonic": "tdpfp16ps", "architecture": "x86", "full_name": "Tile Dot Product FP16 Packed Single", "summary": "Matrix multiply (FP16 * FP16) accumulating to Float32.", "syntax": "TDPFP16PS tmm1, tmm2, tmm3", "encoding": {"format": "VEX", "hex_opcode": "VEX.128.F2.0F38.W0 5C 11:rrr:bbb", "length": "6+", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "operands": [{"name": "dest", "desc": "TMM"}, {"name": "src1", "desc": "TMM"}, {"name": "src2", "desc": "TMM"}], "extension": "AMX-FP16", "description": "Performs a tile matrix multiply-accumulate operation where two FP16 matrices (tmm2 and tmm3) are multiplied element-wise and accumulated into tmm1 as FP32 results. This is a specialized AMX instruction that leverages tile registers for high-throughput matrix operations. No standard CPU flags are affected; results that overflow to infinity or underflow to zero follow IEEE 754 semantics.", "pseudocode": "tmm1 ← tmm1 + (tmm2 * tmm3) // FP16 × FP16 → FP32 accumulation, per tile dimensions", "example": "TDPFP16PS tmm1, tmm2, tmm3"} {"mnemonic": "movss", "architecture": "x86", "full_name": "Move Scalar Single-Precision", "summary": "Moves a single float (low 32 bits) between XMM/Memory.", "syntax": "MOVSS xmm1, xmm2/m32", "encoding": {"format": "SSE", "hex_opcode": "F3 0F 10", "visual_parts": [], "binary_pattern": "F3 | 0F | 10", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m32", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Moves a scalar single-precision (32-bit) floating-point value from the source to the low 32 bits of the destination XMM register. The upper 96 bits of the destination XMM register are preserved. No CPU flags are modified. This instruction operates in 32-bit mode or higher.", "pseudocode": "dest[31:0] ← src[31:0]\n// dest[127:32] unchanged", "example": "MOVSS xmm1, xmm2/m32"} {"mnemonic": "movsd", "architecture": "x86", "full_name": "Move Scalar Double-Precision", "summary": "Moves a single double (low 64 bits) between XMM/Memory.", "syntax": "MOVSD xmm1, xmm2/m64", "encoding": {"format": "SSE2", "hex_opcode": "F2 0F 10", "visual_parts": [], "binary_pattern": "F2 | 0F | 10", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m64", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Moves a scalar double-precision (64-bit) floating-point value from the source to the low 64 bits of the destination XMM register. The upper 64 bits of the destination XMM register are preserved. No CPU flags are modified. This instruction operates in 32-bit mode or higher.", "pseudocode": "dest[63:0] ← src[63:0]\n// dest[127:64] unchanged", "example": "MOVSD xmm1, xmm2/m64"} {"mnemonic": "cvtdq2pd", "architecture": "x86", "full_name": "Convert Packed Doubleword to Packed Double-Precision", "summary": "Converts two 32-bit integers to two 64-bit doubles.", "syntax": "CVTDQ2PD xmm1, xmm2/m64", "encoding": {"format": "SSE2", "hex_opcode": "F3 0F E6", "visual_parts": [], "binary_pattern": "F3 | 0F | E6", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m64", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Converts the lower two 32-bit signed doublewords from the source to two 64-bit IEEE 754 double-precision floating-point values in the destination XMM register. The conversion is exact (no rounding error for representable integers). No CPU flags are modified. Operates in 32-bit mode or higher with SSE2 support.", "pseudocode": "dest[63:0] ← CVTF64(src[31:0]) // lower 32-bit int to double\ndest[127:64] ← CVTF64(src[63:32]) // upper 32-bit int to double", "example": "CVTDQ2PD xmm1, xmm2/m64"} {"mnemonic": "cvtpd2dq", "architecture": "x86", "full_name": "Convert Packed Double-Precision to Packed Doubleword", "summary": "Converts two doubles to two 32-bit integers (Rounded).", "syntax": "CVTPD2DQ xmm1, xmm2/m128", "encoding": {"format": "SSE2", "hex_opcode": "F2 0F E6", "visual_parts": [], "binary_pattern": "F2 | 0F | E6", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Converts two 64-bit double-precision floating-point values from the source to two 32-bit signed doublewords in the destination XMM register, using the rounding mode specified by MXCSR. Overflow results are saturated to 0x80000000 (INT32_MIN) or 0x7FFFFFFF (INT32_MAX); invalid/NaN inputs produce 0x80000000. The upper 64 bits of the destination are zeroed. No CPU flags are modified.", "pseudocode": "rounding_mode ← MXCSR[13:11]\ndest[31:0] ← CVTI32(src[63:0], rounding_mode) // lower double to 32-bit int\ndest[63:32] ← CVTI32(src[127:64], rounding_mode) // upper double to 32-bit int\ndest[127:64] ← 0", "example": "CVTPD2DQ xmm1, xmm2/m128"} {"mnemonic": "cvttpd2dq", "architecture": "x86", "full_name": "Convert with Truncation Packed Double to Packed Doubleword", "summary": "Converts two doubles to two 32-bit integers (Truncated).", "syntax": "CVTTPD2DQ xmm1, xmm2/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F E6", "visual_parts": [], "binary_pattern": "66 | 0F | E6", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Converts two 64-bit double-precision floating-point values from the source to two 32-bit signed doublewords in the destination XMM register, always using truncation (rounding towards zero), ignoring MXCSR. Overflow results are saturated to 0x80000000 (INT32_MIN) or 0x7FFFFFFF (INT32_MAX); invalid/NaN inputs produce 0x80000000. The upper 64 bits of the destination are zeroed. No CPU flags are modified.", "pseudocode": "dest[31:0] ← CVTI32_TRUNC(src[63:0]) // lower double to 32-bit int (truncate)\ndest[63:32] ← CVTI32_TRUNC(src[127:64]) // upper double to 32-bit int (truncate)\ndest[127:64] ← 0", "example": "CVTTPD2DQ xmm1, xmm2/m128"} {"mnemonic": "cvtss2si", "architecture": "x86", "full_name": "Convert Scalar Single to Integer", "summary": "Converts low float to integer (Rounded according to MXCSR).", "syntax": "CVTSS2SI r32, xmm/m32", "encoding": {"format": "SSE", "hex_opcode": "F3 0F 2D", "visual_parts": [], "binary_pattern": "F3 | 0F | 2D", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src", "type": "xmm/m32", "desc": "128-bit XMM register or 32-bit memory"}], "description": "Converts the low 32-bit single-precision floating-point value from the source to a 32-bit signed integer in the destination general-purpose register, using the rounding mode specified by MXCSR. Overflow and invalid/NaN inputs produce 0x80000000 (INT32_MIN). In 64-bit mode, the destination register is zero-extended to 64 bits. No CPU flags are modified.", "pseudocode": "rounding_mode ← MXCSR[13:11]\ndest[31:0] ← CVTI32(src[31:0], rounding_mode)\n// In 64-bit mode: dest[63:32] ← 0", "example": "CVTSS2SI eax, xmm1"} {"mnemonic": "cvtsd2si", "architecture": "x86", "full_name": "Convert Scalar Double to Integer", "summary": "Converts low double to integer (Rounded according to MXCSR).", "syntax": "CVTSD2SI r32, xmm/m64", "encoding": {"format": "SSE2", "hex_opcode": "F2 0F 2D", "visual_parts": [], "binary_pattern": "F2 | 0F | 2D", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src", "type": "xmm/m64", "desc": "128-bit XMM register or 64-bit memory"}], "description": "Converts the low 64-bit double-precision floating-point value from the source to a 32-bit signed integer in the destination general-purpose register, using the rounding mode specified by MXCSR. Overflow and invalid/NaN inputs produce 0x80000000 (INT32_MIN). In 64-bit mode, the destination register is zero-extended to 64 bits. No CPU flags are modified.", "pseudocode": "rounding_mode ← MXCSR[13:11]\ndest[31:0] ← CVTI32(src[63:0], rounding_mode)\n// In 64-bit mode: dest[63:32] ← 0", "example": "CVTSD2SI eax, xmm1"} {"mnemonic": "vcvtph2ps", "architecture": "x86", "full_name": "Convert 16-bit FP to 32-bit FP", "summary": "Converts half-precision floats to single-precision.", "syntax": "VCVTPH2PS xmm1, xmm2/m64", "encoding": {"format": "VEX", "hex_opcode": "VEX.128.66.0F38.W0 13 /r", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 13", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "F16C", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m64", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Converts four 16-bit half-precision floating-point values to four 32-bit single-precision floating-point values. The source contains up to four FP16 values packed in the lower 64 bits; the destination receives four FP32 results in a 128-bit XMM register. No flags are modified; this is a data conversion instruction.", "pseudocode": "dest[127:0] ← CONVERT_FP16_TO_FP32(src[63:0]); // upper 64 bits of dest are zeroed", "example": "VCVTPH2PS xmm1, xmm2/m64"} {"mnemonic": "vcvtps2ph", "architecture": "x86", "full_name": "Convert 32-bit FP to 16-bit FP", "summary": "Converts single-precision floats to half-precision.", "syntax": "VCVTPS2PH xmm1/m64, xmm2, imm8", "encoding": {"format": "VEX", "hex_opcode": "VEX.128.66.0F3A.W0 1D /r ib", "visual_parts": [], "binary_pattern": "66 | 0F | 3A | 1D", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "F16C", "operands": [{"name": "dest", "type": "xmm1/m64", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src1", "type": "xmm2", "desc": "128-bit XMM SIMD register"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Converts four 32-bit single-precision floating-point values to four 16-bit half-precision floating-point values using a rounding mode specified by imm8[2:0]. Results are packed into the lower 64 bits of the destination (register or memory); the upper 64 bits are cleared if destination is XMM. No flags are modified.", "pseudocode": "rounding_mode ← imm8[2:0]; dest[63:0] ← CONVERT_FP32_TO_FP16(src1[127:0], rounding_mode); dest[127:64] ← 0;", "example": "VCVTPS2PH xmm1/m64, xmm2, 3"} {"mnemonic": "vtestps", "architecture": "x86", "full_name": "Packed Bit Test Single-Precision", "summary": "Sets ZF/CF based on sign bit comparisons of floats.", "syntax": "VTESTPS xmm1, xmm2/m128", "encoding": {"format": "AVX", "hex_opcode": "VEX.128.66.0F38.W0 0E /r", "visual_parts": [], "binary_pattern": "VEX | 66 | 0F | 38 | 0E", "bit_positions": "+0 | +3 | +4 | +5 | +6"}, "extension": "AVX", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Performs a bitwise AND of two packed single-precision float vectors and sets ZF based on whether all result bits are zero, and CF based on whether all sign bits are set. No other flags are modified; OF, SF, AF, PF are undefined after execution.", "pseudocode": "temp ← dest[127:0] AND src[127:0]; ZF ← (temp == 0); CF ← ((dest[127] AND src[127]) AND (dest[95] AND src[95]) AND (dest[63] AND src[63]) AND (dest[31] AND src[31]));", "example": "VTESTPS xmm1, xmm2/m128"} {"mnemonic": "vtestpd", "architecture": "x86", "full_name": "Packed Bit Test Double-Precision", "summary": "Sets ZF/CF based on sign bit comparisons of doubles.", "syntax": "VTESTPD xmm1, xmm2/m128", "encoding": {"format": "AVX", "hex_opcode": "VEX.128.66.0F38.W0 0F /r", "visual_parts": [], "binary_pattern": "VEX | 66 | 0F | 38 | 0F", "bit_positions": "+0 | +3 | +4 | +5 | +6"}, "extension": "AVX", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Performs a bitwise AND of two packed double-precision float vectors and sets ZF based on whether all result bits are zero, and CF based on whether both sign bits are set. No other flags are modified; OF, SF, AF, PF are undefined after execution.", "pseudocode": "temp ← dest[127:0] AND src[127:0]; ZF ← (temp == 0); CF ← ((dest[127] AND src[127]) AND (dest[63] AND src[63]));", "example": "VTESTPD xmm1, xmm2/m128"} {"mnemonic": "vperm2f128", "architecture": "x86", "full_name": "Permute Floating-Point 128-bit Blocks", "summary": "Shuffles 128-bit float lanes between YMM registers.", "syntax": "VPERM2F128 ymm1, ymm2, ymm3/m256, imm8", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F3A.W0 06 /r ib", "visual_parts": [], "binary_pattern": "VEX | 66 | 0F | 3A | 06", "bit_positions": "+0 | +3 | +4 | +5 | +6"}, "extension": "AVX", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src1", "type": "ymm2", "desc": "256-bit YMM AVX register"}, {"name": "src2", "type": "ymm3/m256", "desc": "256-bit YMM AVX register or Memory operand"}, {"name": "src3", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Rearranges two 128-bit blocks from two 256-bit YMM operands into the destination 256-bit YMM register according to an 8-bit immediate selector. Bits [3:0] select which 128-bit half goes to the low 128 bits, bits [7:4] select the high 128 bits; bit 3 can zero-out the selected half. No flags are modified.", "pseudocode": "imm8 ← src3; x ← imm8[3:0]; y ← imm8[7:4]; if (imm8[3]) { dest[127:0] ← 0; } else { dest[127:0] ← (x[2:0]==0) ? src1[127:0] : (x[2:0]==1) ? src1[255:128] : (x[2:0]==2) ? src2[127:0] : src2[255:128]; } if (imm8[7]) { dest[255:128] ← 0; } else { dest[255:128] ← (y[2:0]==0) ? src1[127:0] : (y[2:0]==1) ? src1[255:128] : (y[2:0]==2) ? src2[127:0] : src2[255:128]; }", "example": "VPERM2F128 ymm1, ymm2, ymm3/m256, 3"} {"mnemonic": "prefetcht1", "architecture": "x86", "full_name": "Prefetch Data to L2 Cache", "summary": "Hints to fetch data to L2 and L3 caches.", "syntax": "PREFETCHT1 m8", "encoding": {"format": "SSE", "hex_opcode": "0F 18 /2", "visual_parts": [], "binary_pattern": "0F | 18 | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE", "operands": [{"name": "dest", "type": "m8", "desc": "8-bit memory operand"}], "description": "Non-binding hint to the memory system to fetch the byte at the given address into the L2 and L3 caches. The instruction is a no-op to program semantics; it has no effect on registers, flags, or memory, and serves only as a performance hint to reduce cache misses.", "pseudocode": "// Hints to fetch data to L2 and L3 caches", "example": "PREFETCHT1 [rbp-1]"} {"mnemonic": "prefetcht2", "architecture": "x86", "full_name": "Prefetch Data to L3 Cache", "summary": "Hints to fetch data to L3 cache only.", "syntax": "PREFETCHT2 m8", "encoding": {"format": "SSE", "hex_opcode": "0F 18 /3", "visual_parts": [], "binary_pattern": "0F | 18 | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE", "operands": [{"name": "dest", "type": "m8", "desc": "8-bit memory operand"}], "description": "Non-binding hint to the memory system to fetch the byte at the given address into the L3 cache. The instruction is a no-op to program semantics; it has no effect on registers, flags, or memory, and serves only as a performance hint.", "pseudocode": "// Hints to fetch data to L3 cache only", "example": "PREFETCHT2 [rbp-1]"} {"mnemonic": "movsxd", "architecture": "x86", "full_name": "Move with Sign-Extension Doubleword", "summary": "Sign-extends 32-bit register to 64-bit.", "syntax": "MOVSXD r64, r/m32", "encoding": {"format": "Base (64-bit)", "hex_opcode": "63", "visual_parts": [], "binary_pattern": "63", "bit_positions": "+0"}, "extension": "Base (64-bit)", "operands": [{"name": "dest", "type": "r64", "desc": "64-bit general-purpose register (e.g. RAX)"}, {"name": "src", "type": "r/m32", "desc": "32-bit register or memory"}], "description": "Sign-extends a 32-bit value from a register or memory location to a 64-bit value and stores it in a 64-bit destination register. Only valid in 64-bit mode; the upper 32 bits of the destination are filled with sign-extended copies of bit 31 of the source. No flags are modified.", "pseudocode": "dest[63:0] ← SIGN_EXTEND_32_TO_64(src[31:0]);", "example": "MOVSXD rax, ebx"} {"mnemonic": "int1", "architecture": "x86", "full_name": "ICE Breakpoint", "summary": "Single byte opcode (0xF1) used for In-Circuit Emulation.", "syntax": "INT1", "encoding": {"format": "Legacy", "hex_opcode": "F1", "visual_parts": [], "binary_pattern": "F1", "bit_positions": "+0"}, "extension": "Base", "operands": [], "description": "Raises a single-byte breakpoint exception (SIMD debugger breakpoint) with opcode 0xF1, used primarily for In-Circuit Emulation (ICE) debugging. This instruction generates an INT 1 exception (vector 1) immediately without privilege level change. The instruction does not set or clear EFLAGS; it is a synchronous trap that suspends execution and invokes the debugger.", "pseudocode": "push_to_stack(EIP + 1);\npush_to_stack(EFLAGS);\njump_to_IDT_entry(1);", "example": "INT1"} {"mnemonic": "vpcmov", "architecture": "x86", "full_name": "Vector Packed Conditional Move", "summary": "Bitwise conditional move based on selector.", "syntax": "VPCMOV xmm1, xmm2, xmm3, xmm4", "encoding": {"format": "XOP", "hex_opcode": "XOP.128.08.W0 A2 /r ib", "visual_parts": [], "binary_pattern": "08 | A2", "bit_positions": "+0 | +1"}, "extension": "XOP", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2", "desc": "128-bit XMM SIMD register"}, {"name": "src2", "type": "xmm3", "desc": "128-bit XMM SIMD register"}, {"name": "src3", "type": "xmm4", "desc": "128-bit XMM SIMD register"}], "description": "Performs bitwise conditional move on packed 128-bit XMM data using a selector register. For each bit in the selector (xmm4), if the bit is set (1), the corresponding bit from xmm3 is selected; otherwise, the bit from xmm2 is selected. Result is stored in xmm1. No flags are modified.", "pseudocode": "for i in 0 to 127:\n if (xmm4[i] == 1):\n xmm1[i] ← xmm3[i]\n else:\n xmm1[i] ← xmm2[i]", "example": "VPCMOV xmm1, xmm2, xmm3, xmm4"} {"mnemonic": "vpcomb", "architecture": "x86", "full_name": "Vector Packed Compare Byte", "summary": "Compares bytes using immediate condition.", "syntax": "VPCOMB xmm1, xmm2, xmm3/m128, imm8", "encoding": {"format": "XOP", "hex_opcode": "XOP.128.08.W0 CC /r ib", "visual_parts": [], "binary_pattern": "08 | CC", "bit_positions": "+0 | +1"}, "extension": "XOP", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2", "desc": "128-bit XMM SIMD register"}, {"name": "src2", "type": "xmm3/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src3", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Compares 16 packed bytes in xmm2 and xmm3/m128 using the condition specified in imm8, storing comparison results (all-1s or all-0s per byte) in xmm1. Supports eight comparison predicates (EQ, LT, LE, etc.). No EFLAGS are modified; results are encoded as packed byte masks.", "pseudocode": "for i in 0 to 15:\n byte_a ← xmm2[i*8 : i*8+7]\n byte_b ← xmm3[i*8 : i*8+7]\n result ← evaluate_condition(byte_a, byte_b, imm8)\n xmm1[i*8 : i*8+7] ← result ? 0xFF : 0x00", "example": "VPCOMB xmm1, xmm2, xmm3/m128, 3"} {"mnemonic": "blcfill", "architecture": "x86", "full_name": "Fill From Lowest Clear Bit", "summary": "Sets all bits below the lowest clear bit (x & (x+1)).", "syntax": "BLCFILL r32, r/m32", "encoding": {"format": "TBM", "hex_opcode": "XOP.L0.09.W0 01 /1", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "TBM", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src", "type": "r/m32", "desc": "32-bit register or memory"}], "description": "Fills all bits from the lowest clear bit position downward; computes (src & (src+1)) and stores the result in dest. This sets all bits below and including the position of the lowest 0-bit in the source. No flags are modified by this TBM instruction.", "pseudocode": "result ← src & (src + 1)\ndest ← result", "example": "BLCFILL eax, ebx"} {"mnemonic": "vgetexpss", "architecture": "x86", "full_name": "Get Exponent Scalar Single", "summary": "Extracts exponent from low float.", "syntax": "VGETEXPSS xmm1 {k1}, xmm2, xmm3/m32", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.LLIG.66.0F38.W0 43 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 43", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2", "desc": "128-bit XMM SIMD register"}, {"name": "src2", "type": "xmm3/m32", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Extracts the biased exponent from the low 32-bit single-precision floating-point element of xmm3/m32 and stores the result as a float in xmm1. The exponent is converted to a normalized floating-point representation. Supports EVEX masking and rounding modes; other three 32-bit elements in xmm1 are preserved from xmm2.", "pseudocode": "float32 src_val ← xmm3[0:31]\nint32 exponent ← extract_biased_exponent(src_val)\nxmm1[0:31] ← convert_exponent_to_float(exponent)\nxmm1[32:127] ← xmm2[32:127]", "example": "VGETEXPSS xmm1, xmm2, xmm3/m32"} {"mnemonic": "vgetmantsd", "architecture": "x86", "full_name": "Get Mantissa Scalar Double", "summary": "Extracts mantissa from low double.", "syntax": "VGETMANTSD xmm1 {k1}, xmm2, xmm3/m64, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.LLIG.66.0F3A.W1 27 /r ib", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 3A | 27", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2", "desc": "128-bit XMM SIMD register"}, {"name": "src2", "type": "xmm3/m64", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src3", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Extracts the mantissa (significand) from the low 64-bit double-precision floating-point element of xmm3/m64 using the normalization mode in imm8, storing the result as a double in xmm1. Supports EVEX masking and rounding modes; the high 64 bits of xmm1 are preserved from xmm2.", "pseudocode": "float64 src_val ← xmm3[0:63]\nint8 mode ← imm8\nfloat64 mantissa ← extract_mantissa(src_val, mode)\nxmm1[0:63] ← mantissa\nxmm1[64:127] ← xmm2[64:127]", "example": "VGETMANTSD xmm1, xmm2, xmm3/m64, 3"} {"mnemonic": "movq", "architecture": "x86", "full_name": "Move Quadword (MMX)", "summary": "Moves 64-bit data between MMX registers/memory.", "syntax": "MOVQ mm, mm/m64", "encoding": {"format": "MMX", "hex_opcode": "NP 0F 6F /r", "visual_parts": [], "binary_pattern": "0F | 6F", "bit_positions": "+0 | +1"}, "extension": "MMX", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "mm/m64", "desc": "64-bit MMX register or Memory operand"}], "description": "Moves a 64-bit quadword from an MMX register or memory location to an MMX register. This instruction clears the upper 64 bits of the 128-bit XMM register if used with XMM operands (SSE variant). No flags are modified.", "pseudocode": "dest ← src", "example": "MOVQ mm, mm/m64"} {"mnemonic": "paddusb", "architecture": "x86", "full_name": "Packed Add Unsigned Saturate Byte (MMX)", "summary": "Adds 8 unsigned bytes with saturation (MMX).", "syntax": "PADDUSB mm, mm/m64", "encoding": {"format": "MMX", "hex_opcode": "NP 0F DC /r1", "visual_parts": [], "binary_pattern": "0F | DC", "bit_positions": "+0 | +1"}, "extension": "MMX", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "mm/m64", "desc": "64-bit MMX register or Memory operand"}], "description": "Adds 8 pairs of packed unsigned 8-bit integers from the MMX register and memory/register source with saturation. If the sum exceeds 255, the result is saturated to 255. No flags are modified; the 64-bit result is stored in the destination MMX register.", "pseudocode": "for i in 0 to 7:\n byte_a ← dest[i*8 : i*8+7]\n byte_b ← src[i*8 : i*8+7]\n sum ← byte_a + byte_b\n dest[i*8 : i*8+7] ← min(sum, 255)", "example": "PADDUSB mm, mm/m64"} {"mnemonic": "paddsb", "architecture": "x86", "full_name": "Packed Add Signed Saturate Byte (MMX)", "summary": "Adds 8 signed bytes with saturation (MMX).", "syntax": "PADDSB mm, mm/m64", "encoding": {"format": "MMX", "hex_opcode": "NP 0F EC /r1", "visual_parts": [], "binary_pattern": "0F | EC", "bit_positions": "+0 | +1"}, "extension": "MMX", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "mm/m64", "desc": "64-bit MMX register or Memory operand"}], "description": "Adds 8 signed byte pairs in parallel with saturation; if the result overflows (exceeds 127) or underflows (below -128), the result saturates to 127 or -128 respectively. This MMX instruction does not modify any EFLAGS; it operates entirely within the 64-bit MMX register or memory operand.", "pseudocode": "for i = 0 to 7:\n temp ← (signed8)dest[i*8+7:i*8] + (signed8)src[i*8+7:i*8]\n if temp > 127:\n dest[i*8+7:i*8] ← 127\n else if temp < -128:\n dest[i*8+7:i*8] ← -128\n else:\n dest[i*8+7:i*8] ← temp", "example": "PADDSB mm, mm/m64"} {"mnemonic": "paddusw", "architecture": "x86", "full_name": "Packed Add Unsigned Saturate Word (MMX)", "summary": "Adds 4 unsigned words with saturation (MMX).", "syntax": "PADDUSW mm, mm/m64", "encoding": {"format": "MMX", "hex_opcode": "NP 0F DD /r1", "visual_parts": [], "binary_pattern": "0F | DD", "bit_positions": "+0 | +1"}, "extension": "MMX", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "mm/m64", "desc": "64-bit MMX register or Memory operand"}], "description": "Adds 4 unsigned word pairs in parallel with saturation; overflow is clamped to 65535 (0xFFFF). This MMX instruction does not modify any EFLAGS and operates entirely within the 64-bit MMX register or memory operand.", "pseudocode": "for i = 0 to 3:\n temp ← (unsigned16)dest[i*16+15:i*16] + (unsigned16)src[i*16+15:i*16]\n if temp > 65535:\n dest[i*16+15:i*16] ← 65535\n else:\n dest[i*16+15:i*16] ← temp", "example": "PADDUSW mm, mm/m64"} {"mnemonic": "paddsw", "architecture": "x86", "full_name": "Packed Add Signed Saturate Word (MMX)", "summary": "Adds 4 signed words with saturation (MMX).", "syntax": "PADDSW mm, mm/m64", "encoding": {"format": "MMX", "hex_opcode": "NP 0F ED /r1", "visual_parts": [], "binary_pattern": "0F | ED", "bit_positions": "+0 | +1"}, "extension": "MMX", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "mm/m64", "desc": "64-bit MMX register or Memory operand"}], "description": "Adds 4 signed word pairs in parallel with saturation; overflow saturates to 32767 and underflow to -32768. This MMX instruction does not modify any EFLAGS and operates entirely within the 64-bit MMX register or memory operand.", "pseudocode": "for i = 0 to 3:\n temp ← (signed16)dest[i*16+15:i*16] + (signed16)src[i*16+15:i*16]\n if temp > 32767:\n dest[i*16+15:i*16] ← 32767\n else if temp < -32768:\n dest[i*16+15:i*16] ← -32768\n else:\n dest[i*16+15:i*16] ← temp", "example": "PADDSW mm, mm/m64"} {"mnemonic": "psubusb", "architecture": "x86", "full_name": "Packed Subtract Unsigned Saturate Byte (MMX)", "summary": "Subtracts 8 unsigned bytes with saturation (MMX).", "syntax": "PSUBUSB mm, mm/m64", "encoding": {"format": "MMX", "hex_opcode": "NP 0F D8 /r1", "visual_parts": [], "binary_pattern": "0F | D8", "bit_positions": "+0 | +1"}, "extension": "MMX", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "mm/m64", "desc": "64-bit MMX register or Memory operand"}], "description": "Subtracts 8 unsigned byte pairs in parallel with saturation; underflow is clamped to 0. This MMX instruction does not modify any EFLAGS and operates entirely within the 64-bit MMX register or memory operand.", "pseudocode": "for i = 0 to 7:\n if (unsigned8)dest[i*8+7:i*8] < (unsigned8)src[i*8+7:i*8]:\n dest[i*8+7:i*8] ← 0\n else:\n dest[i*8+7:i*8] ← (unsigned8)dest[i*8+7:i*8] - (unsigned8)src[i*8+7:i*8]", "example": "PSUBUSB mm, mm/m64"} {"mnemonic": "psubsb", "architecture": "x86", "full_name": "Packed Subtract Signed Saturate Byte (MMX)", "summary": "Subtracts 8 signed bytes with saturation (MMX).", "syntax": "PSUBSB mm, mm/m64", "encoding": {"format": "MMX", "hex_opcode": "NP 0F E8 /r1", "visual_parts": [], "binary_pattern": "0F | E8", "bit_positions": "+0 | +1"}, "extension": "MMX", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "mm/m64", "desc": "64-bit MMX register or Memory operand"}], "description": "Subtracts 8 signed byte pairs in parallel with saturation; underflow saturates to -128 and overflow to 127. This MMX instruction does not modify any EFLAGS and operates entirely within the 64-bit MMX register or memory operand.", "pseudocode": "for i = 0 to 7:\n temp ← (signed8)dest[i*8+7:i*8] - (signed8)src[i*8+7:i*8]\n if temp > 127:\n dest[i*8+7:i*8] ← 127\n else if temp < -128:\n dest[i*8+7:i*8] ← -128\n else:\n dest[i*8+7:i*8] ← temp", "example": "PSUBSB mm, mm/m64"} {"mnemonic": "psubusw", "architecture": "x86", "full_name": "Packed Subtract Unsigned Saturate Word (MMX)", "summary": "Subtracts 4 unsigned words with saturation (MMX).", "syntax": "PSUBUSW mm, mm/m64", "encoding": {"format": "MMX", "hex_opcode": "NP 0F D9 /r1", "visual_parts": [], "binary_pattern": "0F | D9", "bit_positions": "+0 | +1"}, "extension": "MMX", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "mm/m64", "desc": "64-bit MMX register or Memory operand"}], "description": "Subtracts 4 unsigned word pairs in parallel with saturation; underflow is clamped to 0. This MMX instruction does not modify any EFLAGS and operates entirely within the 64-bit MMX register or memory operand.", "pseudocode": "for i = 0 to 3:\n if (unsigned16)dest[i*16+15:i*16] < (unsigned16)src[i*16+15:i*16]:\n dest[i*16+15:i*16] ← 0\n else:\n dest[i*16+15:i*16] ← (unsigned16)dest[i*16+15:i*16] - (unsigned16)src[i*16+15:i*16]", "example": "PSUBUSW mm, mm/m64"} {"mnemonic": "psubsw", "architecture": "x86", "full_name": "Packed Subtract Signed Saturate Word (MMX)", "summary": "Subtracts 4 signed words with saturation (MMX).", "syntax": "PSUBSW mm, mm/m64", "encoding": {"format": "MMX", "hex_opcode": "NP 0F E9 /r1", "visual_parts": [], "binary_pattern": "0F | E9", "bit_positions": "+0 | +1"}, "extension": "MMX", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "mm/m64", "desc": "64-bit MMX register or Memory operand"}], "description": "Subtracts 4 signed word pairs in parallel with saturation; underflow saturates to -32768 and overflow to 32767. This MMX instruction does not modify any EFLAGS and operates entirely within the 64-bit MMX register or memory operand.", "pseudocode": "for i = 0 to 3:\n temp ← (signed16)dest[i*16+15:i*16] - (signed16)src[i*16+15:i*16]\n if temp > 32767:\n dest[i*16+15:i*16] ← 32767\n else if temp < -32768:\n dest[i*16+15:i*16] ← -32768\n else:\n dest[i*16+15:i*16] ← temp", "example": "PSUBSW mm, mm/m64"} {"mnemonic": "pmullw", "architecture": "x86", "full_name": "Packed Multiply Low Word (MMX)", "summary": "Multiplies 4 words and stores low 16 bits (MMX).", "syntax": "PMULLW mm, mm/m64", "encoding": {"format": "MMX", "hex_opcode": "NP 0F D5 /r1", "visual_parts": [], "binary_pattern": "0F | D5", "bit_positions": "+0 | +1"}, "extension": "MMX", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "mm/m64", "desc": "64-bit MMX register or Memory operand"}], "description": "Multiplies 4 word pairs in parallel and stores the low 16 bits of each product; the high 16 bits are discarded. This MMX instruction does not modify any EFLAGS and operates entirely within the 64-bit MMX register or memory operand.", "pseudocode": "for i = 0 to 3:\n product ← (signed16)dest[i*16+15:i*16] × (signed16)src[i*16+15:i*16]\n dest[i*16+15:i*16] ← product[15:0]", "example": "PMULLW mm, mm/m64"} {"mnemonic": "pmulhw", "architecture": "x86", "full_name": "Packed Multiply High Word (MMX)", "summary": "Multiplies 4 signed words and stores high 16 bits (MMX).", "syntax": "PMULHW mm, mm/m64", "encoding": {"format": "MMX", "hex_opcode": "NP 0F E5 /r1", "visual_parts": [], "binary_pattern": "0F | E5", "bit_positions": "+0 | +1"}, "extension": "MMX", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "mm/m64", "desc": "64-bit MMX register or Memory operand"}], "description": "Multiplies four signed 16-bit words in the destination MMX register by four signed 16-bit words in the source operand, and stores the high 16 bits of each 32-bit product in the destination register. This instruction operates on packed 16-bit signed integers and does not affect any flags. It requires MMX support and is commonly used in multimedia and DSP applications.", "pseudocode": "dest[0:15] ← ((INT32(dest[0:15]) * INT32(src[0:15])) >> 16)[0:15];\ndest[16:31] ← ((INT32(dest[16:31]) * INT32(src[16:31])) >> 16)[0:15];\ndest[32:47] ← ((INT32(dest[32:47]) * INT32(src[32:47])) >> 16)[0:15];\ndest[48:63] ← ((INT32(dest[48:63]) * INT32(src[48:63])) >> 16)[0:15];", "example": "PMULHW mm, mm/m64"} {"mnemonic": "pmaddwd", "architecture": "x86", "full_name": "Packed Multiply Add Word to Doubleword (MMX)", "summary": "Multiplies words and adds adjacent pairs (MMX).", "syntax": "PMADDWD mm, mm/m64", "encoding": {"format": "MMX", "hex_opcode": "NP 0F F5 /r1", "visual_parts": [], "binary_pattern": "0F | F5", "bit_positions": "+0 | +1"}, "extension": "MMX", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "mm/m64", "desc": "64-bit MMX register or Memory operand"}], "description": "Multiplies four pairs of signed 16-bit words, then adds the high and low results of adjacent pairs to produce two signed 32-bit doublewords. The destination MMX register receives the two packed 32-bit sums. This instruction does not affect any flags and is frequently used in audio/video processing and convolution operations.", "pseudocode": "prod[0] ← INT32(dest[0:15]) * INT32(src[0:15]);\nprod[1] ← INT32(dest[16:31]) * INT32(src[16:31]);\nprod[2] ← INT32(dest[32:47]) * INT32(src[32:47]);\nprod[3] ← INT32(dest[48:63]) * INT32(src[48:63]);\ndest[0:31] ← prod[0] + prod[1];\ndest[32:63] ← prod[2] + prod[3];", "example": "PMADDWD mm, mm/m64"} {"mnemonic": "pand", "architecture": "x86", "full_name": "Packed Logical AND (MMX)", "summary": "Bitwise AND of 64-bit MMX registers.", "syntax": "PAND mm, mm/m64", "encoding": {"format": "MMX", "hex_opcode": "NP 0F DB /r1", "visual_parts": [], "binary_pattern": "0F | DB", "bit_positions": "+0 | +1"}, "extension": "MMX", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "mm/m64", "desc": "64-bit MMX register or Memory operand"}], "description": "Performs a bitwise AND of the 64-bit destination MMX register and a 64-bit source operand, storing the result in the destination. All 64 bits are treated as a single operand; no flag bits are affected. This instruction has no size variants and is available in all processors with MMX support.", "pseudocode": "dest[0:63] ← dest[0:63] & src[0:63];", "example": "PAND mm, mm/m64"} {"mnemonic": "por", "architecture": "x86", "full_name": "Packed Logical OR (MMX)", "summary": "Bitwise OR of 64-bit MMX registers.", "syntax": "POR mm, mm/m64", "encoding": {"format": "MMX", "hex_opcode": "NP 0F EB /r1", "visual_parts": [], "binary_pattern": "0F | EB", "bit_positions": "+0 | +1"}, "extension": "MMX", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "mm/m64", "desc": "64-bit MMX register or Memory operand"}], "description": "Performs a bitwise OR of the 64-bit destination MMX register and a 64-bit source operand, storing the result in the destination. All 64 bits participate in the operation as a single unit; no flags are affected. This instruction is available on all MMX-capable processors and has no size variants.", "pseudocode": "dest[0:63] ← dest[0:63] | src[0:63];", "example": "POR mm, mm/m64"} {"mnemonic": "pxor", "architecture": "x86", "full_name": "Packed Logical XOR (MMX)", "summary": "Bitwise XOR of 64-bit MMX registers.", "syntax": "PXOR mm, mm/m64", "encoding": {"format": "MMX", "hex_opcode": "NP 0F EF /r1", "visual_parts": [], "binary_pattern": "0F | EF", "bit_positions": "+0 | +1"}, "extension": "MMX", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "mm/m64", "desc": "64-bit MMX register or Memory operand"}], "description": "Performs a bitwise XOR of the 64-bit destination MMX register and a 64-bit source operand, storing the result in the destination. The operation treats all 64 bits as a single logical unit and does not affect any flags. Notably, PXOR with the same register as both operands can be used to zero a register in one cycle.", "pseudocode": "dest[0:63] ← dest[0:63] ^ src[0:63];", "example": "PXOR mm, mm/m64"} {"mnemonic": "pandn", "architecture": "x86", "full_name": "Packed Logical AND NOT (MMX)", "summary": "Bitwise AND NOT of 64-bit MMX registers.", "syntax": "PANDN mm, mm/m64", "encoding": {"format": "MMX", "hex_opcode": "NP 0F DF /r1", "visual_parts": [], "binary_pattern": "0F | DF", "bit_positions": "+0 | +1"}, "extension": "MMX", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "mm/m64", "desc": "64-bit MMX register or Memory operand"}], "description": "Performs a bitwise AND NOT operation: the destination is AND'ed with the bitwise complement of the source, storing the result in the destination. Equivalent to (dest & ~src). No flags are modified and the operation processes all 64 bits in a single cycle on MMX-capable processors.", "pseudocode": "dest[0:63] ← dest[0:63] & (~src[0:63]);", "example": "PANDN mm, mm/m64"} {"mnemonic": "pcmpgtb", "architecture": "x86", "full_name": "Packed Compare Greater Than Byte (MMX)", "summary": "Compares bytes for greater than (MMX).", "syntax": "PCMPGTB mm, mm/m64", "encoding": {"format": "MMX", "hex_opcode": "NP 0F 64 /r1", "visual_parts": [], "binary_pattern": "0F | 64", "bit_positions": "+0 | +1"}, "extension": "MMX", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "mm/m64", "desc": "64-bit MMX register or Memory operand"}], "description": "Compares four signed 8-bit bytes in the destination MMX register with four signed 8-bit bytes in the source operand. Each byte position in the destination is set to 0xFF if the destination byte is greater than the source byte, or 0x00 otherwise. No EFLAGS are affected by this comparison; results are returned as a packed mask in the MMX register.", "pseudocode": "FOR i = 0 TO 7 STEP 8:\n IF INT8(dest[i:i+7]) > INT8(src[i:i+7]) THEN\n dest[i:i+7] ← 0xFF;\n ELSE\n dest[i:i+7] ← 0x00;\n ENDIF;\nENDFOR;", "example": "PCMPGTB mm, mm/m64"} {"mnemonic": "pcmpgtw", "architecture": "x86", "full_name": "Packed Compare Greater Than Word (MMX)", "summary": "Compares words for greater than (MMX).", "syntax": "PCMPGTW mm, mm/m64", "encoding": {"format": "MMX", "hex_opcode": "NP 0F 65 /r1", "visual_parts": [], "binary_pattern": "0F | 65", "bit_positions": "+0 | +1"}, "extension": "MMX", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "mm/m64", "desc": "64-bit MMX register or Memory operand"}], "description": "Compares two signed 16-bit words in the destination MMX register with two signed 16-bit words in the source operand. Each word position in the destination is set to 0xFFFF if the destination word is greater than the source word, or 0x0000 otherwise. No EFLAGS are modified; comparison results are returned as a packed mask directly in the destination MMX register.", "pseudocode": "FOR i = 0 TO 2 STEP 16:\n IF INT16(dest[i:i+15]) > INT16(src[i:i+15]) THEN\n dest[i:i+15] ← 0xFFFF;\n ELSE\n dest[i:i+15] ← 0x0000;\n ENDIF;\nENDFOR;", "example": "PCMPGTW mm, mm/m64"} {"mnemonic": "pcmpgtd", "architecture": "x86", "full_name": "Packed Compare Greater Than Doubleword (MMX)", "summary": "Compares doublewords for greater than (MMX).", "syntax": "PCMPGTD mm, mm/m64", "encoding": {"format": "MMX", "hex_opcode": "NP 0F 66 /r1", "visual_parts": [], "binary_pattern": "0F | 66", "bit_positions": "+0 | +1"}, "extension": "MMX", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "mm/m64", "desc": "64-bit MMX register or Memory operand"}], "description": "Performs a signed greater-than comparison on four packed 32-bit doublewords in the destination MMX register and source operand, setting each corresponding doubleword in the destination to all 1s if the comparison is true, or all 0s if false. No EFLAGS are affected; this is a data-parallel operation that operates entirely within the MMX register file.", "pseudocode": "for i = 0 to 1 {\n if (signed(dest.dword[i]) > signed(src.dword[i])) {\n dest.dword[i] ← 0xFFFFFFFF\n } else {\n dest.dword[i] ← 0x00000000\n }\n}", "example": "PCMPGTD mm, mm/m64"} {"mnemonic": "pcmpeqb", "architecture": "x86", "full_name": "Packed Compare Equal Byte (MMX)", "summary": "Compares bytes for equality (MMX).", "syntax": "PCMPEQB mm, mm/m64", "encoding": {"format": "MMX", "hex_opcode": "NP 0F 74 /r1", "visual_parts": [], "binary_pattern": "0F | 74", "bit_positions": "+0 | +1"}, "extension": "MMX", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "mm/m64", "desc": "64-bit MMX register or Memory operand"}], "description": "Performs an equality comparison on eight packed 8-bit bytes in the destination MMX register and source operand, setting each corresponding byte in the destination to all 1s if equal, or all 0s if not equal. No EFLAGS are affected; the result is a byte-wise mask suitable for conditional data selection.", "pseudocode": "for i = 0 to 7 {\n if (dest.byte[i] == src.byte[i]) {\n dest.byte[i] ← 0xFF\n } else {\n dest.byte[i] ← 0x00\n }\n}", "example": "PCMPEQB mm, mm/m64"} {"mnemonic": "pcmpeqw", "architecture": "x86", "full_name": "Packed Compare Equal Word (MMX)", "summary": "Compares words for equality (MMX).", "syntax": "PCMPEQW mm, mm/m64", "encoding": {"format": "MMX", "hex_opcode": "NP 0F 75 /r1", "visual_parts": [], "binary_pattern": "0F | 75", "bit_positions": "+0 | +1"}, "extension": "MMX", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "mm/m64", "desc": "64-bit MMX register or Memory operand"}], "description": "Performs an equality comparison on four packed 16-bit words in the destination MMX register and source operand, setting each corresponding word in the destination to all 1s if equal, or all 0s if not equal. No EFLAGS are affected; this is used for creating word-level masks in SIMD operations.", "pseudocode": "for i = 0 to 3 {\n if (dest.word[i] == src.word[i]) {\n dest.word[i] ← 0xFFFF\n } else {\n dest.word[i] ← 0x0000\n }\n}", "example": "PCMPEQW mm, mm/m64"} {"mnemonic": "pcmpeqd", "architecture": "x86", "full_name": "Packed Compare Equal Doubleword (MMX)", "summary": "Compares doublewords for equality (MMX).", "syntax": "PCMPEQD mm, mm/m64", "encoding": {"format": "MMX", "hex_opcode": "NP 0F 76 /r1", "visual_parts": [], "binary_pattern": "0F | 76", "bit_positions": "+0 | +1"}, "extension": "MMX", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "mm/m64", "desc": "64-bit MMX register or Memory operand"}], "description": "Performs an equality comparison on two packed 32-bit doublewords in the destination MMX register and source operand, setting each corresponding doubleword in the destination to all 1s if equal, or all 0s if not equal. No EFLAGS are affected; the result is a doubleword-wise mask suitable for conditional operations.", "pseudocode": "for i = 0 to 1 {\n if (dest.dword[i] == src.dword[i]) {\n dest.dword[i] ← 0xFFFFFFFF\n } else {\n dest.dword[i] ← 0x00000000\n }\n}", "example": "PCMPEQD mm, mm/m64"} {"mnemonic": "psllw", "architecture": "x86", "full_name": "Packed Shift Left Logical Word (MMX)", "summary": "Shifts words left (MMX).", "syntax": "PSLLW mm, imm8", "encoding": {"format": "MMX", "hex_opcode": "NP 0F 71 /6 ib", "visual_parts": [], "binary_pattern": "0F | 71 | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "MMX", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Performs a logical left shift on four packed 16-bit words in the destination MMX register by the count specified in the 8-bit immediate operand, shifting bits out to the left and filling vacated positions with zeros. No EFLAGS are affected; shift counts greater than or equal to 16 result in all zeros for the affected words.", "pseudocode": "count ← src & 0xFF\nfor i = 0 to 3 {\n if (count >= 16) {\n dest.word[i] ← 0x0000\n } else {\n dest.word[i] ← dest.word[i] << count\n }\n}", "example": "PSLLW mm, 3"} {"mnemonic": "pslld", "architecture": "x86", "full_name": "Packed Shift Left Logical Doubleword (MMX)", "summary": "Shifts doublewords left (MMX).", "syntax": "PSLLD mm, imm8", "encoding": {"format": "MMX", "hex_opcode": "66 0F 72 /6 ib", "visual_parts": [], "binary_pattern": "0F | 72 | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "MMX", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Performs a logical left shift on two packed 32-bit doublewords in the destination MMX register by the count specified in the 8-bit immediate operand, shifting bits out to the left and filling vacated positions with zeros. No EFLAGS are affected; shift counts greater than or equal to 32 result in all zeros for the affected doublewords.", "pseudocode": "count ← src & 0xFF\nfor i = 0 to 1 {\n if (count >= 32) {\n dest.dword[i] ← 0x00000000\n } else {\n dest.dword[i] ← dest.dword[i] << count\n }\n}", "example": "PSLLD mm, 3"} {"mnemonic": "psllq", "architecture": "x86", "full_name": "Packed Shift Left Logical Quadword (MMX)", "summary": "Shifts quadword left (MMX).", "syntax": "PSLLQ mm, imm8", "encoding": {"format": "MMX", "hex_opcode": "66 0F 73 /6 ib", "visual_parts": [], "binary_pattern": "0F | 73 | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "MMX", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Performs a logical left shift on one packed 64-bit quadword in the destination MMX register by the count specified in the 8-bit immediate operand, shifting bits out to the left and filling vacated positions with zeros. No EFLAGS are affected; shift counts greater than or equal to 64 result in zero.", "pseudocode": "count ← src & 0xFF\nif (count >= 64) {\n dest.qword[0] ← 0x0000000000000000\n} else {\n dest.qword[0] ← dest.qword[0] << count\n}", "example": "PSLLQ mm, 3"} {"mnemonic": "psrlw", "architecture": "x86", "full_name": "Packed Shift Right Logical Word (MMX)", "summary": "Shifts words right logical (MMX).", "syntax": "PSRLW mm, imm8", "encoding": {"format": "MMX", "hex_opcode": "66 0F 71 /2 ib", "visual_parts": [], "binary_pattern": "0F | 71 | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "MMX", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Performs a logical right shift on four packed 16-bit words in the destination MMX register by the count specified in the 8-bit immediate operand, shifting bits out to the right and filling vacated positions with zeros. No EFLAGS are affected; shift counts greater than or equal to 16 result in all zeros for the affected words.", "pseudocode": "count ← src & 0xFF\nfor i = 0 to 3 {\n if (count >= 16) {\n dest.word[i] ← 0x0000\n } else {\n dest.word[i] ← dest.word[i] >> count\n }\n}", "example": "PSRLW mm, 3"} {"mnemonic": "psrld", "architecture": "x86", "full_name": "Packed Shift Right Logical Doubleword (MMX)", "summary": "Shifts doublewords right logical (MMX).", "syntax": "PSRLD mm, imm8", "encoding": {"format": "MMX", "hex_opcode": "66 0F 72 /2 ib", "visual_parts": [], "binary_pattern": "0F | 72 | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "MMX", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Shifts each 32-bit doubleword element in an MMX register right by an immediate count, filling vacated high-order bits with zeros. This is a logical right shift (sign-insensitive) operating on packed doubleword elements. No flags are affected; the shift amount is masked to 5 bits (0-31).", "pseudocode": "count ← src AND 31;\nfor i ← 0 to 1 do\n dest.dw[i] ← dest.dw[i] >> count;\nend;", "example": "PSRLD mm, 3"} {"mnemonic": "psrlq", "architecture": "x86", "full_name": "Packed Shift Right Logical Quadword (MMX)", "summary": "Shifts quadword right logical (MMX).", "syntax": "PSRLQ mm, imm8", "encoding": {"format": "MMX", "hex_opcode": "66 0F 73 /2 ib", "visual_parts": [], "binary_pattern": "0F | 73 | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "MMX", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Shifts the 64-bit quadword in an MMX register right by an immediate count, filling vacated high-order bits with zeros. This is a logical right shift operating on a single 64-bit element. No flags are affected; the shift amount is masked to 6 bits (0-63).", "pseudocode": "count ← src AND 63;\ndest.qw ← dest.qw >> count;", "example": "PSRLQ mm, 3"} {"mnemonic": "psraw", "architecture": "x86", "full_name": "Packed Shift Right Arithmetic Word (MMX)", "summary": "Shifts words right arithmetic (MMX).", "syntax": "PSRAW mm, imm8", "encoding": {"format": "MMX", "hex_opcode": "66 0F 71 /4 ib", "visual_parts": [], "binary_pattern": "0F | 71 | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "MMX", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Shifts each 16-bit word element in an MMX register right by an immediate count, filling vacated high-order bits with the sign bit (arithmetic shift). This preserves the sign of signed 16-bit integers. No flags are affected; the shift amount is masked to 4 bits (0-15).", "pseudocode": "count ← src AND 15;\nfor i ← 0 to 3 do\n dest.w[i] ← ARITHMETIC_SHIFT_RIGHT(dest.w[i], count);\nend;", "example": "PSRAW mm, 3"} {"mnemonic": "psrad", "architecture": "x86", "full_name": "Packed Shift Right Arithmetic Doubleword (MMX)", "summary": "Shifts doublewords right arithmetic (MMX).", "syntax": "PSRAD mm, imm8", "encoding": {"format": "MMX", "hex_opcode": "66 0F 72 /4 ib", "visual_parts": [], "binary_pattern": "0F | 72 | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "MMX", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Shifts each 32-bit doubleword element in an MMX register right by an immediate count, filling vacated high-order bits with the sign bit (arithmetic shift). This preserves the sign of signed 32-bit integers. No flags are affected; the shift amount is masked to 5 bits (0-31).", "pseudocode": "count ← src AND 31;\nfor i ← 0 to 1 do\n dest.dw[i] ← ARITHMETIC_SHIFT_RIGHT(dest.dw[i], count);\nend;", "example": "PSRAD mm, 3"} {"mnemonic": "mov", "architecture": "x86", "full_name": "Move", "summary": "Copies data from source to destination.", "syntax": "MOV r/m, r", "pseudocode": "dest ← src;", "example": "MOV EAX, 5 ; Load 5 into EAX\nMOV [EBX], EAX ; Store EAX to memory at EBX", "encoding": {"format": "Legacy", "hex_opcode": "89", "length": "2+", "visual_parts": [], "binary_pattern": "89", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m", "desc": "Register or memory operand"}, {"name": "src", "type": "r", "desc": "General-purpose register"}], "description": "Copies data from the source register to the destination register or memory location. Operates on 16-bit, 32-bit, or 64-bit operands (size determined by operand-size prefix and REX.W in 64-bit mode). No flags are affected; memory ordering is not guaranteed with respect to other threads without explicit synchronization."} {"mnemonic": "add", "architecture": "x86", "full_name": "Add", "summary": "Adds src to dest and stores result in dest.", "syntax": "ADD r/m, r", "pseudocode": "result ← dest + src;\nOF ← overflow_occurred(dest, src, result);\nSF ← (result < 0);\nZF ← (result == 0);\nAF ← carry_from_bit(3);\nPF ← parity(result);\nCF ← carry_out;\ndest ← result;", "example": "ADD EAX, EBX ; Add EBX to EAX\nADD [EAX], 5 ; Add 5 to the 32-bit integer at address EAX", "encoding": {"format": "Legacy", "hex_opcode": "01", "length": "2+", "visual_parts": [], "binary_pattern": "01", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m", "desc": "Register or memory operand"}, {"name": "src", "type": "r", "desc": "General-purpose register"}], "description": "Adds the source operand to the destination operand and stores the result in the destination; the sum is computed modulo 2^(operand size). Sets OF, SF, ZF, AF, CF, and PF based on the result. Available in 16-bit, 32-bit, and 64-bit forms; operand size is determined by the prefix and REX.W in 64-bit mode."} {"mnemonic": "sub", "architecture": "x86", "full_name": "Subtract", "summary": "Subtracts src from dest.", "syntax": "SUB r/m, r", "pseudocode": "result ← dest - src;\nOF ← overflow_occurred(dest, src, result);\nSF ← (result < 0);\nZF ← (result == 0);\nAF ← borrow_from_bit(3);\nPF ← parity(result);\nCF ← borrow_out;\ndest ← result;", "example": "SUB EAX, 10 ; Subtract 10 from EAX\nSUB ECX, EDX ; Subtract EDX from ECX", "encoding": {"format": "Legacy", "hex_opcode": "29", "length": "2+", "visual_parts": [], "binary_pattern": "29", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m", "desc": "Register or memory operand"}, {"name": "src", "type": "r", "desc": "General-purpose register"}], "description": "Subtracts the source operand from the destination operand and stores the result in the destination; the difference is computed modulo 2^(operand size). Sets OF, SF, ZF, AF, CF, and PF based on the result. Available in 16-bit, 32-bit, and 64-bit forms; operand size is determined by the prefix and REX.W in 64-bit mode."} {"mnemonic": "and", "architecture": "x86", "full_name": "Logical AND", "summary": "Performs bitwise AND.", "syntax": "AND r/m, r", "encoding": {"format": "Legacy", "hex_opcode": "21", "length": "2+", "visual_parts": [], "binary_pattern": "21", "bit_positions": "+0"}, "operands": [{"name": "dest", "desc": "Register/Memory", "type": "r/m"}, {"name": "src", "desc": "Register", "type": "r"}], "extension": "Base", "description": "Performs a bitwise logical AND of the destination and source operands, storing the result in the destination. Sets SF, ZF, and PF based on the result; clears OF and CF; AF is undefined. Available in 16-bit, 32-bit, and 64-bit forms; operand size is determined by the prefix and REX.W in 64-bit mode.", "pseudocode": "result ← dest AND src;\nSF ← (result < 0);\nZF ← (result == 0);\nPF ← parity(result);\nOF ← 0;\nCF ← 0;\nAF ← undefined;\ndest ← result;", "example": "AND EAX, 0xFF ; Keep lowest 8 bits\nAND ECX, EDX ; Bitwise AND of ECX and EDX"} {"mnemonic": "or", "architecture": "x86", "full_name": "Logical OR", "summary": "Performs bitwise OR.", "syntax": "OR r/m, r", "encoding": {"format": "Legacy", "hex_opcode": "09", "length": "2+", "visual_parts": [], "binary_pattern": "09", "bit_positions": "+0"}, "operands": [{"name": "dest", "desc": "Register/Memory", "type": "r/m"}, {"name": "src", "desc": "Register", "type": "r"}], "extension": "Base", "description": "Performs a bitwise logical OR between the destination and source operands, storing the result in the destination. Sets ZF, SF, and PF based on the result; clears OF and CF; AF is undefined. Available in 8, 16, 32, and 64-bit variants across all modes.", "pseudocode": "dest ← dest | src; ZF ← (result == 0); SF ← (result < 0); PF ← parity(result); CF ← 0; OF ← 0; AF ← undefined;", "example": "OR EAX, 1 ; Set lowest bit\nOR EAX, EAX ; Check if EAX is zero (sets ZF)"} {"mnemonic": "xor", "architecture": "x86", "full_name": "Logical Exclusive OR", "summary": "Performs bitwise XOR.", "syntax": "XOR r/m, r", "encoding": {"format": "Legacy", "hex_opcode": "31", "length": "2+", "visual_parts": [], "binary_pattern": "31", "bit_positions": "+0"}, "operands": [{"name": "dest", "desc": "Register/Memory", "type": "r/m"}, {"name": "src", "desc": "Register", "type": "r"}], "extension": "Base", "description": "Performs a bitwise logical exclusive OR (XOR) between the destination and source operands, storing the result in the destination. Sets ZF, SF, and PF based on the result; clears OF and CF; AF is undefined. Available in 8, 16, 32, and 64-bit variants across all modes.", "pseudocode": "dest ← dest ^ src; ZF ← (result == 0); SF ← (result < 0); PF ← parity(result); CF ← 0; OF ← 0; AF ← undefined;", "example": "XOR EAX, EAX ; Clear EAX (set to 0)\nXOR EAX, 5 ; Toggle bits 0 and 2"} {"mnemonic": "cmp", "architecture": "x86", "full_name": "Compare Two Operands", "summary": "Subtracts src from dest and updates flags (dest not modified).", "syntax": "CMP r/m, r", "encoding": {"format": "Legacy", "hex_opcode": "39", "length": "2+", "visual_parts": [], "binary_pattern": "39", "bit_positions": "+0"}, "operands": [{"name": "dest", "desc": "Register/Memory", "type": "r/m"}, {"name": "src", "desc": "Register", "type": "r"}], "extension": "Base", "description": "Subtracts the source operand from the destination operand and updates the EFLAGS register without modifying the destination. Sets or clears CF, PF, AF, ZF, SF, and OF based on the subtraction result. Available in 8, 16, 32, and 64-bit variants across all modes.", "pseudocode": "temp ← dest - src; CF ← (dest < src); ZF ← (temp == 0); SF ← (temp < 0); OF ← overflow(dest, src); PF ← parity(temp); AF ← half_borrow(dest, src);", "example": "CMP EAX, 10 ; Compare EAX with 10\nJE label ; Jump if Equal"} {"mnemonic": "test", "architecture": "x86", "full_name": "Logical Compare", "summary": "ANDs operands and updates flags (result discarded).", "syntax": "TEST r/m, r", "pseudocode": "temp ← dest & src; ZF ← (temp == 0); SF ← (temp < 0); PF ← parity(temp); CF ← 0; OF ← 0; AF ← undefined;", "example": "TEST EAX, EAX ; Check if EAX is 0\nTEST AL, 1 ; Check if lowest bit is set", "encoding": {"format": "Legacy", "hex_opcode": "85", "length": "2+", "visual_parts": [], "binary_pattern": "85", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m", "desc": "Register or memory operand"}, {"name": "src", "type": "r", "desc": "General-purpose register"}], "description": "Performs a bitwise logical AND between the destination and source operands, updating EFLAGS without modifying either operand. Sets ZF, SF, and PF based on the AND result; clears OF and CF; AF is undefined. Available in 8, 16, 32, and 64-bit variants across all modes."} {"mnemonic": "lfence", "architecture": "x86", "full_name": "Load Fence", "summary": "Serializes load operations (Wait for prior loads to complete).", "syntax": "LFENCE", "encoding": {"format": "SSE2", "hex_opcode": "NP 0F AE E8", "visual_parts": [], "binary_pattern": "0F | AE | E8", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [], "description": "Serializes all load instructions that precede it in program order; subsequent loads wait until prior loads complete and their data is globally visible. Provides acquire-like semantics for loads on TSO (Total Store Order) architectures. No flags are affected. SSE2 extension; acts as a no-op on non-TSO systems without explicit serialization requirements.", "pseudocode": "wait_for_all_prior_loads_to_complete();", "example": "LFENCE"} {"mnemonic": "sfence", "architecture": "x86", "full_name": "Store Fence", "summary": "Serializes store operations (Wait for prior stores to complete).", "syntax": "SFENCE", "encoding": {"format": "SSE", "hex_opcode": "NP 0F AE F8", "visual_parts": [], "binary_pattern": "0F | AE | F8", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE", "operands": [], "description": "Serializes all store instructions that precede it in program order; subsequent stores wait until prior stores complete and are globally visible. Provides release-like semantics for stores. No flags are affected. SSE extension; acts as a no-op on processors where stores are already globally ordered.", "pseudocode": "wait_for_all_prior_stores_to_complete();", "example": "SFENCE"} {"mnemonic": "mfence", "architecture": "x86", "full_name": "Memory Fence", "summary": "Serializes all load and store operations.", "syntax": "MFENCE", "encoding": {"format": "SSE2", "hex_opcode": "NP 0F AE F0", "visual_parts": [], "binary_pattern": "0F | AE | F0", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [], "description": "Serializes all load and store instructions (both prior and subsequent) with respect to one another; acts as a full memory barrier. Ensures all prior memory operations complete and are globally visible before any subsequent memory operations begin. No flags are affected. SSE2 extension; commonly used for cross-CPU synchronization.", "pseudocode": "wait_for_all_prior_loads_and_stores_to_complete(); wait_for_global_visibility();", "example": "MFENCE"} {"mnemonic": "clflush", "architecture": "x86", "full_name": "Cache Line Flush", "summary": "Flushes the cache line containing the operand from all caches.", "syntax": "CLFLUSH m8", "encoding": {"format": "SSE2", "hex_opcode": "NP 0F AE /7", "visual_parts": [], "binary_pattern": "0F | AE | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "m8", "desc": "8-bit memory operand"}], "description": "Flushes the cache line containing the specified memory address from all cache levels (L1, L2, L3) without writing dirty data back to memory. Serializes the instruction stream and ensures all prior memory operations complete before execution. No flags are modified. Supported in protected and 64-bit modes; requires SSE2 or equivalent.", "pseudocode": "cache_line ← address_of(memory_address)\nfor each cache_level in (L1, L2, L3):\n invalidate(cache_line in cache_level)", "example": "CLFLUSH [rbp-1]"} {"mnemonic": "rdtscp", "architecture": "x86", "full_name": "Read Time-Stamp Counter and Processor ID", "summary": "Reads TSC into EDX:EAX and Processor ID into ECX.", "syntax": "RDTSCP", "encoding": {"format": "Legacy", "hex_opcode": "0F 01 F9", "visual_parts": [], "binary_pattern": "0F | 01 | F9", "bit_positions": "+0 | +1 | +2"}, "extension": "Base", "operands": [], "description": "Reads the 64-bit Time-Stamp Counter (TSC) into EDX:EAX and writes the low byte of the IA32_TSC_AUX MSR into ECX. Acts as a serializing instruction, ensuring all prior instructions have completed before TSC is captured. No arithmetic flags are modified. Requires RDTSCP capability; available in both 32-bit and 64-bit modes.", "pseudocode": "EDX:EAX ← TSC\nECX ← (IA32_TSC_AUX MSR)[0:31]", "example": "RDTSCP"} {"mnemonic": "xsave", "architecture": "x86", "full_name": "Save Processor Extended States", "summary": "Saves specified state components (AVX, SSE, etc.) to memory.", "syntax": "XSAVE m", "encoding": {"format": "Legacy", "hex_opcode": "NP 0F AE /4", "visual_parts": [], "binary_pattern": "0F | AE | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "XSAVE", "operands": [{"name": "dest", "type": "m", "desc": "Memory operand"}], "description": "Saves processor extended state components (selected by EDX:EAX, typically FPU, SSE, AVX, and AVX-512 state) to a memory region starting at the address specified in the operand. Serializes the instruction stream and performs a context save without modifying any flags. Requires XSAVE capability; privilege level may be restricted depending on state component being saved.", "pseudocode": "state_mask ← EDX:EAX\nfor each enabled_state in state_components:\n if state_mask & enabled_state:\n memory_region ← save(enabled_state)", "example": "XSAVE [rbp-8]"} {"mnemonic": "xrstor", "architecture": "x86", "full_name": "Restore Processor Extended States", "summary": "Restores specified state components from memory.", "syntax": "XRSTOR m", "encoding": {"format": "Legacy", "hex_opcode": "NP 0F AE /5", "visual_parts": [], "binary_pattern": "0F | AE | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "XSAVE", "operands": [{"name": "dest", "type": "m", "desc": "Memory operand"}], "description": "Restores processor extended state components (selected by EDX:EAX) from a memory region at the specified address. Loads FPU, SSE, AVX, and AVX-512 state as indicated by the state mask. Serializes the instruction stream and does not modify arithmetic flags. Requires XRSTOR capability; memory layout must match that produced by XSAVE.", "pseudocode": "state_mask ← EDX:EAX\nfor each enabled_state in state_components:\n if state_mask & enabled_state:\n enabled_state ← memory_region[offset]", "example": "XRSTOR [rbp-8]"} {"mnemonic": "xgetbv", "architecture": "x86", "full_name": "Get Value of Extended Control Register", "summary": "Reads the state of XCR0 (feature mask) into EDX:EAX.", "syntax": "XGETBV", "encoding": {"format": "Legacy", "hex_opcode": "NP 0F 01 D0", "visual_parts": [], "binary_pattern": "0F | 01 | D0", "bit_positions": "+0 | +1 | +2"}, "extension": "XSAVE", "operands": [], "description": "Reads the 64-bit value of extended control register XCR0 (feature mask indicating which extended processor states are enabled) into EDX:EAX. Does not modify any arithmetic flags. Requires XSAVE capability and typically requires execution at privilege level 0, though user-mode access may be permitted with UMWAIT or in certain OS configurations.", "pseudocode": "EDX:EAX ← XCR0", "example": "XGETBV"} {"mnemonic": "xsetbv", "architecture": "x86", "full_name": "Set Value of Extended Control Register", "summary": "Writes EDX:EAX to XCR0 (Enables/disables AVX/SSE states).", "syntax": "XSETBV", "encoding": {"format": "Legacy", "hex_opcode": "NP 0F 01 D1", "visual_parts": [], "binary_pattern": "0F | 01 | D1", "bit_positions": "+0 | +1 | +2"}, "extension": "XSAVE", "operands": [], "description": "Writes the 64-bit value from EDX:EAX into extended control register XCR0, enabling or disabling processor extended states (AVX, SSE, AVX-512, etc.). Serializes the instruction stream and forces all prior instructions to complete. No arithmetic flags are modified. Requires privilege level 0 and XSAVE capability.", "pseudocode": "XCR0 ← EDX:EAX", "example": "XSETBV"} {"mnemonic": "shufps", "architecture": "x86", "full_name": "Shuffle Packed Single-Precision", "summary": "Shuffles 32-bit floats between two XMM registers.", "syntax": "SHUFPS xmm1, xmm2/m128, imm8", "encoding": {"format": "SSE", "hex_opcode": "NP 0F C6 /r ib", "visual_parts": [], "binary_pattern": "0F | C6", "bit_positions": "+0 | +1"}, "extension": "SSE", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Shuffles four 32-bit single-precision floating-point values from the destination XMM register and source XMM/memory operand according to a 2-bit control value in the immediate byte, placing the result in the destination. The immediate selects which of the four source elements populate each destination element. No arithmetic flags are affected. Supported in SSE and later.", "pseudocode": "dest[31:0] ← select_from_2bits(imm8[1:0], dest[31:0], dest[63:32], src[31:0], src[63:32])\ndest[63:32] ← select_from_2bits(imm8[3:2], dest[31:0], dest[63:32], src[31:0], src[63:32])\ndest[95:64] ← select_from_2bits(imm8[5:4], src[127:96], src[95:64], src[31:0], src[63:32])\ndest[127:96] ← select_from_2bits(imm8[7:6], src[127:96], src[95:64], src[31:0], src[63:32])", "example": "SHUFPS xmm1, xmm2/m128, 3"} {"mnemonic": "shufpd", "architecture": "x86", "full_name": "Shuffle Packed Double-Precision", "summary": "Shuffles 64-bit doubles between two XMM registers.", "syntax": "SHUFPD xmm1, xmm2/m128, imm8", "encoding": {"format": "SSE2", "hex_opcode": "66 0F C6", "visual_parts": [], "binary_pattern": "66 | 0F | C6", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Shuffles two 64-bit double-precision floating-point values from the destination XMM register and source XMM/memory operand according to a 2-bit control value in the immediate byte, placing the result in the destination. The low bit selects element 0 of the result (from dest or src), the high bit selects element 1. No arithmetic flags are affected. Requires SSE2 or later.", "pseudocode": "dest[63:0] ← imm8[0] ? src[63:0] : dest[63:0]\ndest[127:64] ← imm8[1] ? src[127:64] : dest[127:64]", "example": "SHUFPD xmm1, xmm2/m128, 3"} {"mnemonic": "unpcklps", "architecture": "x86", "full_name": "Unpack Low Packed Single-Precision", "summary": "Interleaves low floats from two registers.", "syntax": "UNPCKLPS xmm1, xmm2/m128", "encoding": {"format": "SSE", "hex_opcode": "NP 0F 14 /r", "visual_parts": [], "binary_pattern": "0F | 14", "bit_positions": "+0 | +1"}, "extension": "SSE", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Interleaves the low 64 bits (two 32-bit floats) from the destination XMM register with the low 64 bits from the source, producing [src[31:0], dest[31:0], src[63:32], dest[63:32]] in the destination. This SIMD instruction has no effect on CPU flags and operates only on the XMM register file. It is part of the SSE extension and works identically across all modern 64-bit modes.", "pseudocode": "xmm1[31:0] ← xmm1[31:0];\nxmm1[63:32] ← src[31:0];\nxmm1[95:64] ← xmm1[63:32];\nxmm1[127:96] ← src[63:32];", "example": "UNPCKLPS xmm1, xmm2/m128"} {"mnemonic": "unpckhps", "architecture": "x86", "full_name": "Unpack High Packed Single-Precision", "summary": "Interleaves high floats from two registers.", "syntax": "UNPCKHPS xmm1, xmm2/m128", "encoding": {"format": "SSE", "hex_opcode": "NP 0F 15 /r", "visual_parts": [], "binary_pattern": "0F | 15", "bit_positions": "+0 | +1"}, "extension": "SSE", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Interleaves the high 64 bits (two 32-bit floats) from the destination XMM register with the high 64 bits from the source, producing [src[95:64], dest[95:64], src[127:96], dest[127:96]] in the destination. This SIMD instruction has no effect on CPU flags and operates only on the XMM register file. It is part of the SSE extension and works identically across all modern 64-bit modes.", "pseudocode": "xmm1[31:0] ← xmm1[95:64];\nxmm1[63:32] ← src[95:64];\nxmm1[95:64] ← xmm1[127:96];\nxmm1[127:96] ← src[127:96];", "example": "UNPCKHPS xmm1, xmm2/m128"} {"mnemonic": "movntps", "architecture": "x86", "full_name": "Move Non-Temporal Packed Single", "summary": "Stores float vectors directly to RAM, bypassing cache.", "syntax": "MOVNTPS m128, xmm", "encoding": {"format": "SSE", "hex_opcode": "NP 0F 2B /r", "visual_parts": [], "binary_pattern": "0F | 2B", "bit_positions": "+0 | +1"}, "extension": "SSE", "operands": [{"name": "dest", "type": "m128", "desc": "128-bit memory operand"}, {"name": "src", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}], "description": "Writes 128 bits from an XMM register directly to memory without bringing the cache line into the L1 data cache, using a write-combining memory type. This non-temporal store is optimal for streaming data that will not be reused soon. The instruction has no effect on CPU flags and executes as a store-to-memory operation without fence semantics.", "pseudocode": "[m128] ← xmm;", "example": "MOVNTPS [rbp-16], xmm0"} {"mnemonic": "movntpd", "architecture": "x86", "full_name": "Move Non-Temporal Packed Double", "summary": "Stores double vectors directly to RAM, bypassing cache.", "syntax": "MOVNTPD m128, xmm", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 2B", "visual_parts": [], "binary_pattern": "66 | 0F | 2B", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "m128", "desc": "128-bit memory operand"}, {"name": "src", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}], "description": "Writes 128 bits from an XMM register directly to memory without bringing the cache line into the L1 data cache, using a write-combining memory type, operating on two 64-bit double-precision floats. This non-temporal store is optimal for streaming data that will not be reused soon. The instruction has no effect on CPU flags and executes as a store-to-memory operation without fence semantics.", "pseudocode": "[m128] ← xmm;", "example": "MOVNTPD [rbp-16], xmm0"} {"mnemonic": "blendpd", "architecture": "x86", "full_name": "Blend Packed Double-Precision", "summary": "Selects doubles from two sources based on immediate mask.", "syntax": "BLENDPD xmm1, xmm2/m128, imm8", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 3A 0D", "visual_parts": [], "binary_pattern": "66 | 0F | 3A | 0D", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Selects each 64-bit double-precision element from the destination or source register based on the corresponding bit in an 8-bit immediate mask (bit 0 for element 0, bit 1 for element 1). If the bit is 0, the element from xmm1 is retained; if 1, the element from the source is used. No CPU flags are affected by this SIMD operation, which is part of the SSE4.1 extension.", "pseudocode": "imm ← imm8;\nxmm1[63:0] ← (imm[0] == 1) ? src[63:0] : xmm1[63:0];\nxmm1[127:64] ← (imm[1] == 1) ? src[127:64] : xmm1[127:64];", "example": "BLENDPD xmm1, xmm2/m128, 3"} {"mnemonic": "insertps", "architecture": "x86", "full_name": "Insert Packed Single-Precision", "summary": "Inserts a single float into a specific index of XMM.", "syntax": "INSERTPS xmm1, xmm2/m32, imm8", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 3A 21", "visual_parts": [], "binary_pattern": "66 | 0F | 3A | 21", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m32", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Inserts a single 32-bit float from a source (register or memory) into a specific lane of the destination XMM register as specified by bits [5:4] of the immediate operand, and optionally zeros lanes specified by bits [3:0]. No CPU flags are affected by this SIMD operation, which is part of the SSE4.1 extension.", "pseudocode": "imm ← imm8;\ncount_d ← (imm >> 4) & 0x3;\nzero_mask ← imm & 0xF;\nsrc_dword ← src[31:0];\nxmm1[count_d*32 + 31 : count_d*32] ← src_dword;\nfor i in 0 to 3:\n if (zero_mask & (1 << i)) then xmm1[i*32 + 31 : i*32] ← 0;", "example": "INSERTPS xmm1, xmm2/m32, 3"} {"mnemonic": "extractps", "architecture": "x86", "full_name": "Extract Packed Single-Precision", "summary": "Extracts a single float from XMM to an integer register.", "syntax": "EXTRACTPS r32/m32, xmm1, imm8", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 3A 17", "visual_parts": [], "binary_pattern": "66 | 0F | 3A | 17", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "r32/m32", "desc": "General-purpose register or Memory operand"}, {"name": "src1", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Extracts a single 32-bit float from a source XMM register at a lane specified by bits [1:0] of the immediate operand and writes it to a 32-bit destination (GP register or memory). The extracted value is zero-extended if written to a 32-bit register. No CPU flags are affected by this SIMD operation, which is part of the SSE4.1 extension.", "pseudocode": "imm ← imm8;\nindex ← imm & 0x3;\nsrc_dword ← xmm1[index*32 + 31 : index*32];\ndest[31:0] ← src_dword;", "example": "EXTRACTPS r32/m32, xmm1, 3"} {"mnemonic": "dpps", "architecture": "x86", "full_name": "Dot Product Packed Single-Precision", "summary": "Computes the dot product of two float vectors.", "syntax": "DPPS xmm1, xmm2/m128, imm8", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 3A 40", "visual_parts": [], "binary_pattern": "66 | 0F | 3A | 40", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Computes the dot product of the four 32-bit float elements in the destination and source registers, then selectively masks the result and zeros based on an 8-bit immediate. The result (or zero) is replicated into each 32-bit element of the destination according to the mask. No CPU flags are affected by this SIMD operation, which is part of the SSE4.1 extension.", "pseudocode": "imm ← imm8;\nproduct ← 0.0;\nfor i in 0 to 3:\n if (imm & (1 << (i+4))) then\n product ← product + (dest[i*32+31:i*32] * src[i*32+31:i*32]);\nfor i in 0 to 3:\n if (imm & (1 << i)) then\n dest[i*32+31:i*32] ← product;\n else\n dest[i*32+31:i*32] ← 0.0;", "example": "DPPS xmm1, xmm2/m128, 3"} {"mnemonic": "dppd", "architecture": "x86", "full_name": "Dot Product Packed Double-Precision", "summary": "Computes the dot product of two double vectors.", "syntax": "DPPD xmm1, xmm2/m128, imm8", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 3A 41", "visual_parts": [], "binary_pattern": "66 | 0F | 3A | 41", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Computes the dot product of two packed double-precision floating-point vectors (2 doubles per 128-bit operand) and stores the result in the destination. The imm8 byte controls which elements participate in the dot product and which output elements are zeroed. No flags are affected; this is a SSE4.1 instruction that operates only in 64-bit and protected modes.", "pseudocode": "select_mask ← imm8[7:4]\nproduct_mask ← imm8[3:0]\ntemp ← 0.0\nfor i in 0..1:\n if (product_mask[i] == 1):\n temp ← temp + (xmm1[i*64+63:i*64] * src1[i*64+63:i*64])\nfor i in 0..1:\n if (select_mask[i] == 1):\n dest[i*64+63:i*64] ← temp\n else:\n dest[i*64+63:i*64] ← 0.0", "example": "DPPD xmm1, xmm2/m128, 3"} {"mnemonic": "roundps", "architecture": "x86", "full_name": "Round Packed Single-Precision", "summary": "Rounds all packed floats according to immediate mode.", "syntax": "ROUNDPS xmm1, xmm2/m128, imm8", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 3A 08", "visual_parts": [], "binary_pattern": "66 | 0F | 3A | 08", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Rounds each packed single-precision floating-point element in the source operand according to the rounding mode specified in imm8 and stores the result in the destination. The rounding mode imm8[2:0] selects between round-to-nearest, round-down, round-up, or truncate; bit 3 selects whether to suppress inexact exceptions. No CPU flags are modified; this is a SSE4.1 instruction available in 64-bit and protected modes.", "pseudocode": "rounding_mode ← imm8[2:0]\nsuppress_inexact ← imm8[3]\nfor i in 0..3:\n f32 ← src[i*32+31:i*32]\n if (rounding_mode == 0): /* round to nearest */\n result ← round_nearest(f32)\n elif (rounding_mode == 1): /* round down */\n result ← round_down(f32)\n elif (rounding_mode == 2): /* round up */\n result ← round_up(f32)\n elif (rounding_mode == 3): /* truncate */\n result ← truncate(f32)\n dest[i*32+31:i*32] ← result", "example": "ROUNDPS xmm1, xmm2/m128, 3"} {"mnemonic": "roundpd", "architecture": "x86", "full_name": "Round Packed Double-Precision", "summary": "Rounds all packed doubles according to immediate mode.", "syntax": "ROUNDPD xmm1, xmm2/m128, imm8", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 3A 09", "visual_parts": [], "binary_pattern": "66 | 0F | 3A | 09", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Rounds each packed double-precision floating-point element in the source operand according to the rounding mode specified in imm8 and stores the result in the destination. The rounding mode imm8[2:0] selects between round-to-nearest, round-down, round-up, or truncate; bit 3 controls inexact exception suppression. No CPU flags are modified; this is a SSE4.1 instruction available in 64-bit and protected modes.", "pseudocode": "rounding_mode ← imm8[2:0]\nsuppress_inexact ← imm8[3]\nfor i in 0..1:\n f64 ← src[i*64+63:i*64]\n if (rounding_mode == 0): /* round to nearest */\n result ← round_nearest(f64)\n elif (rounding_mode == 1): /* round down */\n result ← round_down(f64)\n elif (rounding_mode == 2): /* round up */\n result ← round_up(f64)\n elif (rounding_mode == 3): /* truncate */\n result ← truncate(f64)\n dest[i*64+63:i*64] ← result", "example": "ROUNDPD xmm1, xmm2/m128, 3"} {"mnemonic": "pcmpeqq", "architecture": "x86", "full_name": "Packed Compare Equal Quadword", "summary": "Checks if 64-bit integer elements are equal.", "syntax": "PCMPEQQ xmm1, xmm2/m128", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 38 29", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 29", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Compares packed 64-bit signed integer elements in the destination and source operands for equality, setting all bits to 1 in the corresponding 64-bit result element if equal, or 0 if not equal. No CPU flags are affected; this is a SSE4.1 instruction available in 64-bit and protected modes.", "pseudocode": "for i in 0..1:\n if (dest[i*64+63:i*64] == src[i*64+63:i*64]):\n dest[i*64+63:i*64] ← 0xFFFFFFFFFFFFFFFF\n else:\n dest[i*64+63:i*64] ← 0x0000000000000000", "example": "PCMPEQQ xmm1, xmm2/m128"} {"mnemonic": "pcmpestri", "architecture": "x86", "full_name": "Packed Compare Explicit Length Strings, Return Index", "summary": "Complex string search/compare; returns index in ECX.", "syntax": "PCMPESTRI xmm1, xmm2/m128, imm8", "encoding": {"format": "SSE4.2", "hex_opcode": "66 0F 3A 61", "visual_parts": [], "binary_pattern": "66 | 0F | 3A | 61", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.2", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Performs explicit-length packed string comparison between two 128-bit operands using element size and comparison operation encoded in imm8, returning the index of the first match (or mismatch, depending on control bits) in ECX and setting CF and ZF flags. The lengths of the strings are provided implicitly in EAX and EDX; this is a SSE4.2 instruction that can serialize the pipeline and is available in 64-bit and protected modes.", "pseudocode": "pcmp_control ← imm8[2:0]\nstring_type ← imm8[5:4]\npolarity ← imm8[7:6]\nlen1 ← EAX & 0xFFFF\nlen2 ← EDX & 0xFFFF\nintres ← perform_string_compare(dest, src, string_type, pcmp_control, len1, len2)\nECX ← intres\nCF ← (intres < string_length)\nZF ← (intres == string_length)\nSF ← OF ← undefined", "example": "PCMPESTRI xmm1, xmm2/m128, 3"} {"mnemonic": "pcmpestrm", "architecture": "x86", "full_name": "Packed Compare Explicit Length Strings, Return Mask", "summary": "Complex string search/compare; returns mask in XMM0.", "syntax": "PCMPESTRM xmm1, xmm2/m128, imm8", "encoding": {"format": "SSE4.2", "hex_opcode": "66 0F 3A 60", "visual_parts": [], "binary_pattern": "66 | 0F | 3A | 60", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.2", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Performs explicit-length packed string comparison between two 128-bit operands using element size and comparison operation encoded in imm8, returning a 128-bit mask of comparison results in XMM0 and setting CF and ZF flags. The string lengths are provided implicitly in EAX and EDX; this is a SSE4.2 instruction that can serialize the pipeline and is available in 64-bit and protected modes.", "pseudocode": "pcmp_control ← imm8[2:0]\nstring_type ← imm8[5:4]\npolarity ← imm8[7:6]\nlen1 ← EAX & 0xFFFF\nlen2 ← EDX & 0xFFFF\nmask ← perform_string_compare_mask(dest, src, string_type, pcmp_control, len1, len2)\nXMM0 ← mask\nCF ← (any_match_found)\nZF ← (all_matches_found)\nSF ← OF ← undefined", "example": "PCMPESTRM xmm1, xmm2/m128, 3"} {"mnemonic": "pcmpistri", "architecture": "x86", "full_name": "Packed Compare Implicit Length Strings, Return Index", "summary": "String search (null-terminated); returns index in ECX.", "syntax": "PCMPISTRI xmm1, xmm2/m128, imm8", "encoding": {"format": "SSE4.2", "hex_opcode": "66 0F 3A 63", "visual_parts": [], "binary_pattern": "66 | 0F | 3A | 63", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.2", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Performs implicit-length (null-terminated) packed string comparison between two 128-bit operands using element size and comparison operation encoded in imm8, returning the index of the first match in ECX and setting CF and ZF flags. String lengths are determined by scanning for zero terminators; this is a SSE4.2 instruction that can serialize the pipeline and is available in 64-bit and protected modes.", "pseudocode": "pcmp_control ← imm8[2:0]\nstring_type ← imm8[5:4]\npolarity ← imm8[7:6]\nlen1 ← scan_for_null(dest, string_type)\nlen2 ← scan_for_null(src, string_type)\nintres ← perform_string_compare(dest, src, string_type, pcmp_control, len1, len2)\nECX ← intres\nCF ← (intres < max_length)\nZF ← (intres == max_length)\nSF ← OF ← undefined", "example": "PCMPISTRI xmm1, xmm2/m128, 3"} {"mnemonic": "vfmadd132ss", "architecture": "x86", "full_name": "Fused Multiply-Add Scalar Single (132)", "summary": "Scalar FMA: Dest = (Dest * Src2) + Src1.", "syntax": "VFMADD132SS xmm1, xmm2, xmm3/m32", "encoding": {"format": "FMA3", "hex_opcode": "VEX.LIG.66.0F38.W0 99 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "FMA3", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2", "desc": "128-bit XMM SIMD register"}, {"name": "src2", "type": "xmm3/m32", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Performs a scalar fused multiply-add of three operands using VEX encoding: computes (Dest * Src2) + Src1 and stores the result in Dest with only the lower 32-bit scalar single-precision element affected while preserving upper 96 bits. The operand order '132' indicates destination is the first operand, first source is the second register operand, and second source is the third operand. No CPU flags are modified; this is a FMA3 instruction available in 64-bit mode on processors supporting the FMA3 extension.", "pseudocode": "temp_f32 ← (dest[31:0] * src2[31:0]) + src1[31:0]\ndest[31:0] ← temp_f32\n/* dest[127:32] unchanged */", "example": "VFMADD132SS xmm1, xmm2, xmm3/m32"} {"mnemonic": "vfmadd213ss", "architecture": "x86", "full_name": "Fused Multiply-Add Scalar Single (213)", "summary": "Scalar FMA: Dest = (Src1 * Dest) + Src2.", "syntax": "VFMADD213SS xmm1, xmm2, xmm3/m32", "encoding": {"format": "FMA3", "hex_opcode": "VEX.LIG.66.0F38.W0 A9 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "FMA3", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2", "desc": "128-bit XMM SIMD register"}, {"name": "src2", "type": "xmm3/m32", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Fused multiply-add scalar single: performs (Src1 * Dest) + Src2, storing the result in Dest with a single rounding step. Only the lowest 32-bit float element is operated on; upper 96 bits of Dest are preserved. No EFLAGS are modified; rounding is controlled by MXCSR.", "pseudocode": "Dest[0..31] ← FMA(Src1[0..31] * Dest[0..31] + Src2[0..31])\nDest[32..127] ← unchanged", "example": "VFMADD213SS xmm1, xmm2, xmm3/m32"} {"mnemonic": "vfmadd231ss", "architecture": "x86", "full_name": "Fused Multiply-Add Scalar Single (231)", "summary": "Scalar FMA: Dest = (Src1 * Src2) + Dest.", "syntax": "VFMADD231SS xmm1, xmm2, xmm3/m32", "encoding": {"format": "FMA3", "hex_opcode": "VEX.LIG.66.0F38.W0 B9 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "FMA3", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2", "desc": "128-bit XMM SIMD register"}, {"name": "src2", "type": "xmm3/m32", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Fused multiply-add scalar single: performs (Src1 * Src2) + Dest, storing the result in Dest with a single rounding step. Only the lowest 32-bit float element is operated on; upper 96 bits of Dest are preserved. No EFLAGS are modified; rounding is controlled by MXCSR.", "pseudocode": "Dest[0..31] ← FMA(Src1[0..31] * Src2[0..31] + Dest[0..31])\nDest[32..127] ← unchanged", "example": "VFMADD231SS xmm1, xmm2, xmm3/m32"} {"mnemonic": "vpermilps", "architecture": "x86", "full_name": "Permute In-Lane Packed Single", "summary": "Shuffles floats within 128-bit lanes (AVX).", "syntax": "VPERMILPS ymm1, ymm2/m256, imm8", "encoding": {"format": "AVX", "hex_opcode": "VEX.256.66.0F3A.W0 04 /r ib", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AVX", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src1", "type": "ymm2/m256", "desc": "256-bit YMM AVX register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Permutes 32-bit float elements within 128-bit lanes independently using an 8-bit immediate, allowing shuffles within the lower and upper halves of a 256-bit register. No EFLAGS are affected. The immediate encoding selects 2-bit indices per float element.", "pseudocode": "for each 128-bit lane L in 0..1:\n for each 32-bit element i in 0..3:\n idx ← (Src1[L*128 + i*2 + 1 : L*128 + i*2]) & 0x3\n Dest[L*128 + i*32 : L*128 + i*32 + 31] ← Src1[L*128 + idx*32 : L*128 + idx*32 + 31]", "example": "VPERMILPS ymm1, ymm2/m256, 3"} {"mnemonic": "vpermilpd", "architecture": "x86", "full_name": "Permute In-Lane Packed Double", "summary": "Shuffles doubles within 128-bit lanes (AVX).", "syntax": "VPERMILPD ymm1, ymm2/m256, imm8", "encoding": {"format": "AVX", "hex_opcode": "VEX.256.66.0F3A.W0 05 /r ib", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AVX", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src1", "type": "ymm2/m256", "desc": "256-bit YMM AVX register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Permutes 64-bit double elements within 128-bit lanes independently using an 8-bit immediate, allowing shuffles within the lower and upper halves of a 256-bit register. No EFLAGS are affected. The immediate encoding selects 1-bit indices per double element.", "pseudocode": "for each 128-bit lane L in 0..1:\n for each 64-bit element i in 0..1:\n idx ← (Src1[L*128 + i]) & 0x1\n Dest[L*128 + i*64 : L*128 + i*64 + 63] ← Src1[L*128 + idx*64 : L*128 + idx*64 + 63]", "example": "VPERMILPD ymm1, ymm2/m256, 3"} {"mnemonic": "vbroadcastss", "architecture": "x86", "full_name": "Broadcast Scalar Single", "summary": "Loads one float and replicates it to all YMM elements.", "syntax": "VBROADCASTSS ymm1, m32", "encoding": {"format": "AVX", "hex_opcode": "VEX.256.66.0F38.W0 18 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AVX", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src", "type": "m32", "desc": "32-bit memory operand"}], "description": "Loads a single 32-bit float from memory and replicates it to all eight 32-bit elements in a 256-bit YMM register. No EFLAGS are modified. Requires AVX support.", "pseudocode": "value ← [Src]\nfor i ← 0 to 7:\n Dest[i*32 : i*32 + 31] ← value", "example": "VBROADCASTSS ymm1, [rbp-4]"} {"mnemonic": "vpbroadcastd", "architecture": "x86", "full_name": "Broadcast Doubleword", "summary": "Loads one integer and replicates it to all YMM elements.", "syntax": "VPBROADCASTD ymm1, xmm2/m32", "encoding": {"format": "AVX2", "hex_opcode": "VEX.256.66.0F38.W0 58 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AVX2", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src", "type": "xmm2/m32", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Loads a single 32-bit integer from a register or memory and replicates it to all eight 32-bit elements in a 256-bit YMM register. No EFLAGS are modified. Requires AVX2 support.", "pseudocode": "if Src is xmm register:\n value ← Src[0..31]\nelse (Src is m32):\n value ← [Src]\nfor i ← 0 to 7:\n Dest[i*32 : i*32 + 31] ← value", "example": "VPBROADCASTD ymm1, xmm2/m32"} {"mnemonic": "pclmulqdq", "architecture": "x86", "full_name": "Carry-Less Multiplication", "summary": "Performs carry-less multiplication (Galois Field math for AES-GCM).", "syntax": "PCLMULQDQ xmm1, xmm2/m128, imm8", "encoding": {"format": "PCLMUL", "hex_opcode": "66 0F 3A 44", "visual_parts": [], "binary_pattern": "66 | 0F | 3A | 44", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "PCLMULQDQ", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Performs carry-less multiplication of two 64-bit operands extracted from 128-bit XMM operands, producing a 128-bit result. Used in Galois/Counter Mode (GCM) for AES authentication. No EFLAGS are modified. The immediate selects which 64-bit halves of the operands participate.", "pseudocode": "if Imm[0] == 0:\n a ← Src1[0..63]\nelse:\n a ← Src1[64..127]\nif Imm[4] == 0:\n b ← Src2[0..63]\nelse:\n b ← Src2[64..127]\nDest ← GF_multiply(a, b) // Carry-less multiplication in GF(2^64), result fits in 128 bits", "example": "PCLMULQDQ xmm1, xmm2/m128, 3"} {"mnemonic": "crc32", "architecture": "x86", "full_name": "Accumulate CRC32 Value", "summary": "Accumulates CRC32C value using polynomial 0x11EDC6F41.", "syntax": "CRC32 r32, r/m", "encoding": {"format": "SSE4.2", "hex_opcode": "F2 0F 38 F1", "visual_parts": [], "binary_pattern": "F2 | 0F | 38 | F1", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.2", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src", "type": "r/m", "desc": "Register or memory operand"}], "description": "Accumulates a CRC32C checksum using the Castagnoli polynomial (0x11EDC6F41) into the destination register. The source operand size (8/16/32/64-bit) determines the operation width; destination is zero-extended to full register width. No EFLAGS are modified. Requires SSE4.2.", "pseudocode": "if Src is 8-bit:\n Dest[0..31] ← CRC32C(Dest[0..31], [Src])\n Dest[32..63] ← 0 (if 64-bit destination)\nelse if Src is 16-bit:\n Dest[0..31] ← CRC32C(Dest[0..31], [Src])\n Dest[32..63] ← 0 (if 64-bit destination)\nelse if Src is 32-bit:\n Dest[0..31] ← CRC32C(Dest[0..31], [Src])\n Dest[32..63] ← 0 (if 64-bit destination)\nelse if Src is 64-bit:\n Dest ← CRC32C(Dest, [Src])", "example": "CRC32 eax, rbx"} {"mnemonic": "cvtsq2ss", "architecture": "x86", "full_name": "Convert Signed Quadword Integer to Scalar Single-Precision", "summary": "Converts 64-bit integer to float.", "syntax": "CVTSQ2SS xmm1, r/m64", "encoding": {"format": "SSE", "hex_opcode": "F3 REX.W 0F 2A /r", "visual_parts": [], "binary_pattern": "F3 | 0F | 2A", "bit_positions": "+0 | +1 | +2"}, "extension": "Base (64-bit)", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "r/m64", "desc": "64-bit register or memory"}], "description": "Converts a signed 64-bit integer to a single-precision floating-point value and stores it in the low 32 bits of the destination XMM register; the upper 96 bits are zeroed. The conversion uses the current rounding mode from MXCSR. This instruction is only available in 64-bit mode and sets no flags.", "pseudocode": "dest[31:0] ← ConvertInt64ToSinglePrecision(src);\ndest[127:32] ← 0;", "example": "CVTSQ2SS xmm1, rbx"} {"mnemonic": "cvtsq2sd", "architecture": "x86", "full_name": "Convert Signed Quadword Integer to Scalar Double-Precision", "summary": "Converts 64-bit integer to double.", "syntax": "CVTSQ2SD xmm1, r/m64", "encoding": {"format": "SSE2", "hex_opcode": "F2 REX.W 0F 2A /r", "visual_parts": [], "binary_pattern": "F2 | 0F | 2A", "bit_positions": "+0 | +1 | +2"}, "extension": "Base (64-bit)", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "r/m64", "desc": "64-bit register or memory"}], "description": "Converts a signed 64-bit integer to a double-precision floating-point value and stores it in the low 64 bits of the destination XMM register; the upper 64 bits are zeroed. The conversion uses the current rounding mode from MXCSR. This instruction is only available in 64-bit mode and sets no flags.", "pseudocode": "dest[63:0] ← ConvertInt64ToDoublePrecision(src);\ndest[127:64] ← 0;", "example": "CVTSQ2SD xmm1, rbx"} {"mnemonic": "cvtss2sq", "architecture": "x86", "full_name": "Convert Scalar Single-Precision to Signed Quadword Integer", "summary": "Converts float to 64-bit integer (Rounded).", "syntax": "CVTSS2SQ r64, xmm/m32", "encoding": {"format": "SSE", "hex_opcode": "F3 REX.W 0F 2D /r", "visual_parts": [], "binary_pattern": "F3 | 0F | 2D", "bit_positions": "+0 | +1 | +2"}, "extension": "Base (64-bit)", "operands": [{"name": "dest", "type": "r64", "desc": "64-bit general-purpose register (e.g. RAX)"}, {"name": "src", "type": "xmm/m32", "desc": "128-bit XMM register or 32-bit memory"}], "description": "Converts the low 32-bit single-precision floating-point value from the source XMM register or memory to a signed 64-bit integer, using the current rounding mode from MXCSR. The result is stored in the destination 64-bit general-purpose register. This instruction is only available in 64-bit mode and sets no flags.", "pseudocode": "dest ← ConvertSinglePrecisionToInt64(src[31:0]);", "example": "CVTSS2SQ rax, xmm1"} {"mnemonic": "cvtsd2sq", "architecture": "x86", "full_name": "Convert Scalar Double-Precision to Signed Quadword Integer", "summary": "Converts double to 64-bit integer (Rounded).", "syntax": "CVTSD2SQ r64, xmm/m64", "encoding": {"format": "SSE2", "hex_opcode": "F2 REX.W 0F 2D /r", "visual_parts": [], "binary_pattern": "F2 | 0F | 2D", "bit_positions": "+0 | +1 | +2"}, "extension": "Base (64-bit)", "operands": [{"name": "dest", "type": "r64", "desc": "64-bit general-purpose register (e.g. RAX)"}, {"name": "src", "type": "xmm/m64", "desc": "128-bit XMM register or 64-bit memory"}], "description": "Converts the low 64-bit double-precision floating-point value from the source XMM register or memory to a signed 64-bit integer, using the current rounding mode from MXCSR. The result is stored in the destination 64-bit general-purpose register. This instruction is only available in 64-bit mode and sets no flags.", "pseudocode": "dest ← ConvertDoublePrecisionToInt64(src[63:0]);", "example": "CVTSD2SQ rax, xmm1"} {"mnemonic": "cvttss2sq", "architecture": "x86", "full_name": "Convert with Truncation Scalar Single-Precision to Signed Quadword Integer", "summary": "Converts float to 64-bit integer (Truncated).", "syntax": "CVTTSS2SQ r64, xmm/m32", "encoding": {"format": "SSE", "hex_opcode": "F3 REX.W 0F 2C /r", "visual_parts": [], "binary_pattern": "F3 | 0F | 2C", "bit_positions": "+0 | +1 | +2"}, "extension": "Base (64-bit)", "operands": [{"name": "dest", "type": "r64", "desc": "64-bit general-purpose register (e.g. RAX)"}, {"name": "src", "type": "xmm/m32", "desc": "128-bit XMM register or 32-bit memory"}], "description": "Converts the low 32-bit single-precision floating-point value from the source XMM register or memory to a signed 64-bit integer by truncating toward zero (ignoring MXCSR rounding mode). The result is stored in the destination 64-bit general-purpose register. This instruction is only available in 64-bit mode and sets no flags.", "pseudocode": "dest ← TruncateSinglePrecisionToInt64(src[31:0]);", "example": "CVTTSS2SQ rax, xmm1"} {"mnemonic": "cvttsd2sq", "architecture": "x86", "full_name": "Convert with Truncation Scalar Double-Precision to Signed Quadword Integer", "summary": "Converts double to 64-bit integer (Truncated).", "syntax": "CVTTSD2SQ r64, xmm/m64", "encoding": {"format": "SSE2", "hex_opcode": "F2 REX.W 0F 2C /r", "visual_parts": [], "binary_pattern": "F2 | 0F | 2C", "bit_positions": "+0 | +1 | +2"}, "extension": "Base (64-bit)", "operands": [{"name": "dest", "type": "r64", "desc": "64-bit general-purpose register (e.g. RAX)"}, {"name": "src", "type": "xmm/m64", "desc": "128-bit XMM register or 64-bit memory"}], "description": "Converts the low 64-bit double-precision floating-point value from the source XMM register or memory to a signed 64-bit integer by truncating toward zero (ignoring MXCSR rounding mode). The result is stored in the destination 64-bit general-purpose register. This instruction is only available in 64-bit mode and sets no flags.", "pseudocode": "dest ← TruncateDoublePrecisionToInt64(src[63:0]);", "example": "CVTTSD2SQ rax, xmm1"} {"mnemonic": "haddpd", "architecture": "x86", "full_name": "Horizontal Add Packed Double-Precision", "summary": "Adds adjacent double-precision elements horizontally.", "syntax": "HADDPD xmm1, xmm2/m128", "encoding": {"format": "SSE3", "hex_opcode": "66 0F 7C", "visual_parts": [], "binary_pattern": "66 | 0F | 7C", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE3", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Horizontally adds adjacent pairs of double-precision floating-point elements: the first destination element is the sum of the two low double elements, and the second destination element is the sum of the two high double elements. The source operand may be an XMM register or 128-bit memory. No flags are modified.", "pseudocode": "dest[63:0] ← dest[63:0] + dest[127:64];\ndest[127:64] ← src[63:0] + src[127:64];", "example": "HADDPD xmm1, xmm2/m128"} {"mnemonic": "hsubps", "architecture": "x86", "full_name": "Horizontal Subtract Packed Single-Precision", "summary": "Subtracts adjacent single-precision elements horizontally.", "syntax": "HSUBPS xmm1, xmm2/m128", "encoding": {"format": "SSE3", "hex_opcode": "F2 0F 7D", "visual_parts": [], "binary_pattern": "F2 | 0F | 7D", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE3", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Horizontally subtracts adjacent pairs of single-precision floating-point elements: the first destination element is the difference of the two low single elements, and the second destination element is the difference of the two high single elements. The source operand may be an XMM register or 128-bit memory. No flags are modified.", "pseudocode": "dest[31:0] ← dest[31:0] - dest[63:32];\ndest[63:32] ← dest[95:64] - dest[127:96];\ndest[95:64] ← src[31:0] - src[63:32];\ndest[127:96] ← src[95:64] - src[127:96];", "example": "HSUBPS xmm1, xmm2/m128"} {"mnemonic": "hsubpd", "architecture": "x86", "full_name": "Horizontal Subtract Packed Double-Precision", "summary": "Subtracts adjacent double-precision elements horizontally.", "syntax": "HSUBPD xmm1, xmm2/m128", "encoding": {"format": "SSE3", "hex_opcode": "66 0F 7D", "visual_parts": [], "binary_pattern": "66 | 0F | 7D", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE3", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Performs horizontal subtraction of adjacent pairs of double-precision floating-point values in the source and destination XMM registers, storing results in the destination. Specifically, it subtracts the upper element from the lower element of each 128-bit lane (result[63:0] = dest[63:0] - dest[127:64]; result[127:64] = src[63:0] - src[127:64]). All floating-point exception flags may be set based on the operation; no integer flags are affected. This is an SSE3 instruction operating exclusively on 128-bit XMM registers.", "pseudocode": "dest[63:0] ← dest[63:0] - dest[127:64];\ndest[127:64] ← src[63:0] - src[127:64];", "example": "HSUBPD xmm1, xmm2/m128"} {"mnemonic": "addsubpd", "architecture": "x86", "full_name": "Packed Double-FP Add/Subtract", "summary": "Adds odd elements, subtracts even elements (Double).", "syntax": "ADDSUBPD xmm1, xmm2/m128", "encoding": {"format": "SSE3", "hex_opcode": "66 0F D0", "visual_parts": [], "binary_pattern": "66 | 0F | D0", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE3", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Performs lane-wise alternating addition and subtraction on packed double-precision floating-point values: even-indexed elements (0, 2, ...) are subtracted, odd-indexed elements (1, 3, ...) are added. The operation is (dest[63:0] - src[63:0]) in the low qword and (dest[127:64] + src[127:64]) in the high qword. All floating-point exception flags may be set; no integer flags are affected. This is an SSE3 instruction operating on 128-bit XMM registers.", "pseudocode": "dest[63:0] ← dest[63:0] - src[63:0];\ndest[127:64] ← dest[127:64] + src[127:64];", "example": "ADDSUBPD xmm1, xmm2/m128"} {"mnemonic": "vpermi2q", "architecture": "x86", "full_name": "Permute Two-Source Quadwords", "summary": "Shuffles quadwords from two ZMM registers into destination.", "syntax": "VPERMI2Q zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W1 76 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 76", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Performs a two-source permutation of 64-bit quadwords using indices from the destination register (zmm1), which acts as the index/control vector. Each 6-bit index in zmm1 selects a quadword from either zmm2 (index 0-7) or zmm3 (index 8-15), with the selected element placed into the corresponding position in the destination. The instruction supports AVX-512F masking via the k1 opmask register and operates on 512-bit ZMM registers. Memory operands are supported for zmm3/m512.", "pseudocode": "for i = 0 to 7 {\n idx ← zmm1[i*64+5:i*64];\n if idx[3] == 0:\n zmm1[i*64+63:i*64] ← zmm2[idx[2:0]*64+63:idx[2:0]*64];\n else:\n zmm1[i*64+63:i*64] ← zmm3[(idx[2:0])*64+63:(idx[2:0])*64];\n}", "example": "VPERMI2Q zmm1, zmm2, zmm3/m512"} {"mnemonic": "vpermt2q", "architecture": "x86", "full_name": "Permute Two-Source Quadwords (Overwrite)", "summary": "Shuffles 2 sources, overwriting the index register (Quadword).", "syntax": "VPERMT2Q zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W1 7E /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 7F", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Performs a two-source permutation of 64-bit quadwords using indices from the second source register (zmm2), which acts as the control vector. Each 6-bit index in zmm2 selects a quadword from either zmm1 (index 0-7) or zmm3 (index 8-15), and the result is stored in the destination (zmm1), overwriting the original source data. The instruction supports AVX-512F masking via the k1 opmask register and operates on 512-bit ZMM registers. Memory operands are supported for zmm3/m512.", "pseudocode": "temp ← zmm1;\nfor i = 0 to 7 {\n idx ← zmm2[i*64+5:i*64];\n if idx[3] == 0:\n zmm1[i*64+63:i*64] ← temp[idx[2:0]*64+63:idx[2:0]*64];\n else:\n zmm1[i*64+63:i*64] ← zmm3[(idx[2:0])*64+63:(idx[2:0])*64];\n}", "example": "VPERMT2Q zmm1, zmm2, zmm3/m512"} {"mnemonic": "vpsllvd", "architecture": "x86", "full_name": "Variable Bit Shift Left Logical Doubleword", "summary": "Shifts doublewords left by individual counts.", "syntax": "VPSLLVD ymm1, ymm2, ymm3/m256", "encoding": {"format": "AVX2", "hex_opcode": "VEX.256.66.0F38.W0 47 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AVX2", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src1", "type": "ymm2", "desc": "256-bit YMM AVX register"}, {"name": "src2", "type": "ymm3/m256", "desc": "256-bit YMM AVX register or Memory operand"}], "description": "Performs variable left logical bit shift on packed 32-bit doublewords, where each element is shifted by the corresponding count value from the third operand (bits 4:0 of each 32-bit element determine the shift amount, max 31 bits). Bits shifted out are lost; positions vacated are filled with zeros. The instruction operates on 256-bit YMM registers with AVX2 encoding and does not affect any integer flags.", "pseudocode": "for i = 0 to 7 {\n shift_amt ← ymm3[i*32+4:i*32];\n if shift_amt > 31:\n ymm1[i*32+31:i*32] ← 0;\n else:\n ymm1[i*32+31:i*32] ← ymm2[i*32+31:i*32] << shift_amt;\n}", "example": "VPSLLVD ymm1, ymm2, ymm3/m256"} {"mnemonic": "vpsllvq", "architecture": "x86", "full_name": "Variable Bit Shift Left Logical Quadword", "summary": "Shifts quadwords left by individual counts.", "syntax": "VPSLLVQ ymm1, ymm2, ymm3/m256", "encoding": {"format": "AVX2", "hex_opcode": "VEX.256.66.0F38.W1 47 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AVX2", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src1", "type": "ymm2", "desc": "256-bit YMM AVX register"}, {"name": "src2", "type": "ymm3/m256", "desc": "256-bit YMM AVX register or Memory operand"}], "description": "Performs variable left logical bit shift on packed 64-bit quadwords, where each element is shifted by the corresponding count value from the third operand (bits 5:0 of each 64-bit element determine the shift amount, max 63 bits). Bits shifted out are lost; positions vacated are filled with zeros. The instruction operates on 256-bit YMM registers with AVX2 encoding and does not affect any integer flags.", "pseudocode": "for i = 0 to 3 {\n shift_amt ← ymm3[i*64+5:i*64];\n if shift_amt > 63:\n ymm1[i*64+63:i*64] ← 0;\n else:\n ymm1[i*64+63:i*64] ← ymm2[i*64+63:i*64] << shift_amt;\n}", "example": "VPSLLVQ ymm1, ymm2, ymm3/m256"} {"mnemonic": "vpsravd", "architecture": "x86", "full_name": "Variable Bit Shift Right Arithmetic Doubleword", "summary": "Shifts doublewords right arithmetic by individual counts.", "syntax": "VPSRAVD ymm1, ymm2, ymm3/m256", "encoding": {"format": "AVX2", "hex_opcode": "VEX.256.66.0F38.W0 46 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AVX2", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src1", "type": "ymm2", "desc": "256-bit YMM AVX register"}, {"name": "src2", "type": "ymm3/m256", "desc": "256-bit YMM AVX register or Memory operand"}], "description": "Performs variable arithmetic right shift on packed 32-bit signed doublewords, where each element is shifted by the corresponding count value from the third operand (bits 4:0 of each 32-bit element determine the shift amount, max 31 bits). The sign bit is replicated into vacated positions. The instruction operates on 256-bit YMM registers with AVX2 encoding and does not affect any integer flags.", "pseudocode": "for i = 0 to 7 {\n shift_amt ← ymm3[i*32+4:i*32];\n if shift_amt > 31:\n if ymm2[i*32+31] == 1:\n ymm1[i*32+31:i*32] ← -1;\n else:\n ymm1[i*32+31:i*32] ← 0;\n else:\n ymm1[i*32+31:i*32] ← (signed) ymm2[i*32+31:i*32] >> shift_amt;\n}", "example": "VPSRAVD ymm1, ymm2, ymm3/m256"} {"mnemonic": "vpsravq", "architecture": "x86", "full_name": "Variable Bit Shift Right Arithmetic Quadword", "summary": "Shifts quadwords right arithmetic by individual counts.", "syntax": "VPSRAVQ zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W1 46 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 46", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Performs variable arithmetic right shift on packed 64-bit signed quadwords, where each element is shifted by the corresponding count value from the third operand (bits 5:0 of each 64-bit element determine the shift amount, max 63 bits). The sign bit is replicated into vacated positions. The instruction supports AVX-512F masking via the k1 opmask register and operates on 512-bit ZMM registers. Memory operands are supported for zmm3/m512; no integer flags are affected.", "pseudocode": "for i = 0 to 7 {\n shift_amt ← zmm2[i*64+5:i*64];\n if shift_amt > 63:\n if zmm2[i*64+63] == 1:\n zmm1[i*64+63:i*64] ← -1;\n else:\n zmm1[i*64+63:i*64] ← 0;\n else:\n zmm1[i*64+63:i*64] ← (signed) zmm2[i*64+63:i*64] >> shift_amt;\n}", "example": "VPSRAVQ zmm1, zmm2, zmm3/m512"} {"mnemonic": "vpsrlvd", "architecture": "x86", "full_name": "Variable Bit Shift Right Logical Doubleword", "summary": "Shifts doublewords right logical by individual counts.", "syntax": "VPSRLVD ymm1, ymm2, ymm3/m256", "encoding": {"format": "AVX2", "hex_opcode": "VEX.256.66.0F38.W0 45 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AVX2", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src1", "type": "ymm2", "desc": "256-bit YMM AVX register"}, {"name": "src2", "type": "ymm3/m256", "desc": "256-bit YMM AVX register or Memory operand"}], "description": "Performs variable logical right shifts on packed 32-bit doublewords in the first source operand (ymm2) by the amounts specified in the corresponding doubleword elements of the second source operand (ymm3/m256), storing results in the destination (ymm1). Each doubleword is shifted independently; shift amounts > 31 produce zero. No flags are affected; this is an AVX2 instruction available in 256-bit form.", "pseudocode": "for i in 0 to 7:\n shift_amount = src2[i*32 : i*32+31]\n if shift_amount > 31:\n dest[i*32 : i*32+31] = 0\n else:\n dest[i*32 : i*32+31] = src1[i*32 : i*32+31] >> shift_amount", "example": "VPSRLVD ymm1, ymm2, ymm3/m256"} {"mnemonic": "vpsrlvq", "architecture": "x86", "full_name": "Variable Bit Shift Right Logical Quadword", "summary": "Shifts quadwords right logical by individual counts.", "syntax": "VPSRLVQ ymm1, ymm2, ymm3/m256", "encoding": {"format": "AVX2", "hex_opcode": "VEX.256.66.0F38.W1 45 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AVX2", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src1", "type": "ymm2", "desc": "256-bit YMM AVX register"}, {"name": "src2", "type": "ymm3/m256", "desc": "256-bit YMM AVX register or Memory operand"}], "description": "Performs variable logical right shifts on packed 64-bit quadwords in the first source operand (ymm2) by the amounts specified in the corresponding quadword elements of the second source operand (ymm3/m256), storing results in the destination (ymm1). Each quadword is shifted independently; shift amounts > 63 produce zero. No flags are affected; this is an AVX2 instruction available in 256-bit form.", "pseudocode": "for i in 0 to 3:\n shift_amount = src2[i*64 : i*64+63]\n if shift_amount > 63:\n dest[i*64 : i*64+63] = 0\n else:\n dest[i*64 : i*64+63] = src1[i*64 : i*64+63] >> shift_amount", "example": "VPSRLVQ ymm1, ymm2, ymm3/m256"} {"mnemonic": "pminsb", "architecture": "x86", "full_name": "Minimum of Packed Signed Byte Integers", "summary": "Returns minimum of signed bytes.", "syntax": "PMINSB xmm1, xmm2/m128", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 38 38", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 38", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Compares packed signed byte integers in the destination operand (xmm1) with those in the source operand (xmm2/m128) and stores the minimum of each pair in the destination. Each of the 16 bytes is compared independently as a signed 8-bit value. No flags are affected; this is an SSE4.1 instruction that operates on 128-bit XMM registers.", "pseudocode": "for i in 0 to 15:\n byte_a = sign_extend(dest[i*8 : i*8+7])\n byte_b = sign_extend(src[i*8 : i*8+7])\n dest[i*8 : i*8+7] = (byte_a < byte_b) ? byte_a : byte_b", "example": "PMINSB xmm1, xmm2/m128"} {"mnemonic": "pmaxsb", "architecture": "x86", "full_name": "Maximum of Packed Signed Byte Integers", "summary": "Returns maximum of signed bytes.", "syntax": "PMAXSB xmm1, xmm2/m128", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 38 3C", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 3C", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Compares packed signed byte integers in the destination operand (xmm1) with those in the source operand (xmm2/m128) and stores the maximum of each pair in the destination. Each of the 16 bytes is compared independently as a signed 8-bit value. No flags are affected; this is an SSE4.1 instruction that operates on 128-bit XMM registers.", "pseudocode": "for i in 0 to 15:\n byte_a = sign_extend(dest[i*8 : i*8+7])\n byte_b = sign_extend(src[i*8 : i*8+7])\n dest[i*8 : i*8+7] = (byte_a > byte_b) ? byte_a : byte_b", "example": "PMAXSB xmm1, xmm2/m128"} {"mnemonic": "pminuw", "architecture": "x86", "full_name": "Minimum of Packed Unsigned Word Integers", "summary": "Returns minimum of unsigned words.", "syntax": "PMINUW xmm1, xmm2/m128", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 38 3A", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 3A", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Compares packed unsigned word integers in the destination operand (xmm1) with those in the source operand (xmm2/m128) and stores the minimum of each pair in the destination. Each of the 8 words is compared independently as an unsigned 16-bit value. No flags are affected; this is an SSE4.1 instruction that operates on 128-bit XMM registers.", "pseudocode": "for i in 0 to 7:\n word_a = dest[i*16 : i*16+15]\n word_b = src[i*16 : i*16+15]\n dest[i*16 : i*16+15] = (word_a < word_b) ? word_a : word_b", "example": "PMINUW xmm1, xmm2/m128"} {"mnemonic": "pmaxuw", "architecture": "x86", "full_name": "Maximum of Packed Unsigned Word Integers", "summary": "Returns maximum of unsigned words.", "syntax": "PMAXUW xmm1, xmm2/m128", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 38 3E", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 3E", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Compares packed unsigned word integers in the destination operand (xmm1) with those in the source operand (xmm2/m128) and stores the maximum of each pair in the destination. Each of the 8 words is compared independently as an unsigned 16-bit value. No flags are affected; this is an SSE4.1 instruction that operates on 128-bit XMM registers.", "pseudocode": "for i in 0 to 7:\n word_a = dest[i*16 : i*16+15]\n word_b = src[i*16 : i*16+15]\n dest[i*16 : i*16+15] = (word_a > word_b) ? word_a : word_b", "example": "PMAXUW xmm1, xmm2/m128"} {"mnemonic": "pminud", "architecture": "x86", "full_name": "Minimum of Packed Unsigned Doubleword Integers", "summary": "Returns minimum of unsigned doublewords.", "syntax": "PMINUD xmm1, xmm2/m128", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 38 3B", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 3B", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Compares packed unsigned doubleword integers in the destination operand (xmm1) with those in the source operand (xmm2/m128) and stores the minimum of each pair in the destination. Each of the 4 doublewords is compared independently as an unsigned 32-bit value. No flags are affected; this is an SSE4.1 instruction that operates on 128-bit XMM registers.", "pseudocode": "for i in 0 to 3:\n dword_a = dest[i*32 : i*32+31]\n dword_b = src[i*32 : i*32+31]\n dest[i*32 : i*32+31] = (dword_a < dword_b) ? dword_a : dword_b", "example": "PMINUD xmm1, xmm2/m128"} {"mnemonic": "pmaxud", "architecture": "x86", "full_name": "Maximum of Packed Unsigned Doubleword Integers", "summary": "Returns maximum of unsigned doublewords.", "syntax": "PMAXUD xmm1, xmm2/m128", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 38 3F", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 3F", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Compares packed unsigned doubleword integers in the destination operand (xmm1) with those in the source operand (xmm2/m128) and stores the maximum of each pair in the destination. Each of the 4 doublewords is compared independently as an unsigned 32-bit value. No flags are affected; this is an SSE4.1 instruction that operates on 128-bit XMM registers.", "pseudocode": "for i in 0 to 3:\n dword_a = dest[i*32 : i*32+31]\n dword_b = src[i*32 : i*32+31]\n dest[i*32 : i*32+31] = (dword_a > dword_b) ? dword_a : dword_b", "example": "PMAXUD xmm1, xmm2/m128"} {"mnemonic": "pminsd", "architecture": "x86", "full_name": "Minimum of Packed Signed Doubleword Integers", "summary": "Returns minimum of signed doublewords.", "syntax": "PMINSD xmm1, xmm2/m128", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 38 39", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 39", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Compares packed signed 32-bit integers in xmm1 with xmm2/m128 and writes the minimum of each pair to xmm1. This is a SIMD operation with no effect on the CPU flags. Available in SSE4.1 and later; operates on 128-bit XMM registers containing four 32-bit signed doublewords.", "pseudocode": "xmm1[127:96] ← (xmm1[127:96] < xmm2[127:96]) ? xmm1[127:96] : xmm2[127:96];\nxmm1[95:64] ← (xmm1[95:64] < xmm2[95:64]) ? xmm1[95:64] : xmm2[95:64];\nxmm1[63:32] ← (xmm1[63:32] < xmm2[63:32]) ? xmm1[63:32] : xmm2[63:32];\nxmm1[31:0] ← (xmm1[31:0] < xmm2[31:0]) ? xmm1[31:0] : xmm2[31:0];", "example": "PMINSD xmm1, xmm2/m128"} {"mnemonic": "pmaxsd", "architecture": "x86", "full_name": "Maximum of Packed Signed Doubleword Integers", "summary": "Returns maximum of signed doublewords.", "syntax": "PMAXSD xmm1, xmm2/m128", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 38 3D", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 3D", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Compares packed signed 32-bit integers in xmm1 with xmm2/m128 and writes the maximum of each pair to xmm1. This is a SIMD operation with no effect on the CPU flags. Available in SSE4.1 and later; operates on 128-bit XMM registers containing four 32-bit signed doublewords.", "pseudocode": "xmm1[127:96] ← (xmm1[127:96] > xmm2[127:96]) ? xmm1[127:96] : xmm2[127:96];\nxmm1[95:64] ← (xmm1[95:64] > xmm2[95:64]) ? xmm1[95:64] : xmm2[95:64];\nxmm1[63:32] ← (xmm1[63:32] > xmm2[63:32]) ? xmm1[63:32] : xmm2[63:32];\nxmm1[31:0] ← (xmm1[31:0] > xmm2[31:0]) ? xmm1[31:0] : xmm2[31:0];", "example": "PMAXSD xmm1, xmm2/m128"} {"mnemonic": "pinsrd", "architecture": "x86", "full_name": "Packed Insert Doubleword", "summary": "Inserts a doubleword from register to XMM.", "syntax": "PINSRD xmm1, r32/m32, imm8", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 3A 22", "visual_parts": [], "binary_pattern": "66 | 0F | 3A | 22", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "r32/m32", "desc": "General-purpose register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Inserts a 32-bit doubleword from a general-purpose register or memory into an XMM register at the position specified by an 8-bit immediate index. The remaining XMM lanes are unchanged. Available in SSE4.1 and later; no flags are affected by this instruction.", "pseudocode": "index ← imm8[1:0];\ncase index of\n 0: xmm1[31:0] ← (r32/m32 is register) ? r32 : [r32/m32];\n 1: xmm1[63:32] ← (r32/m32 is register) ? r32 : [r32/m32];\n 2: xmm1[95:64] ← (r32/m32 is register) ? r32 : [r32/m32];\n 3: xmm1[127:96] ← (r32/m32 is register) ? r32 : [r32/m32];\nendcase;", "example": "PINSRD xmm1, r32/m32, 3"} {"mnemonic": "pinsrq", "architecture": "x86", "full_name": "Packed Insert Quadword", "summary": "Inserts a quadword from register to XMM.", "syntax": "PINSRQ xmm1, r64/m64, imm8", "encoding": {"format": "SSE4.1", "hex_opcode": "66 REX.W 0F 3A 22 /r ib", "visual_parts": [], "binary_pattern": "66 | 0F | 3A | 22", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "r64/m64", "desc": "General-purpose register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Inserts a 64-bit quadword from a general-purpose register or memory into an XMM register at the position specified by an 8-bit immediate index. The other 64-bit lane remains unchanged. Available in SSE4.1 and later (64-bit mode only); no flags are affected by this instruction.", "pseudocode": "index ← imm8[0];\ncase index of\n 0: xmm1[63:0] ← (r64/m64 is register) ? r64 : [r64/m64];\n 1: xmm1[127:64] ← (r64/m64 is register) ? r64 : [r64/m64];\nendcase;", "example": "PINSRQ xmm1, r64/m64, 3"} {"mnemonic": "pextrd", "architecture": "x86", "full_name": "Packed Extract Doubleword", "summary": "Extracts a doubleword from XMM to register.", "syntax": "PEXTRD r32/m32, xmm1, imm8", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 3A 16", "visual_parts": [], "binary_pattern": "66 | 0F | 3A | 16", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "r32/m32", "desc": "General-purpose register or Memory operand"}, {"name": "src1", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Extracts a 32-bit doubleword from an XMM register at the position specified by an 8-bit immediate and writes it to a general-purpose register or memory. Zero-extends the extracted value when writing to a 32-bit register. Available in SSE4.1 and later; no flags are affected by this instruction.", "pseudocode": "index ← imm8[1:0];\ncase index of\n 0: value ← xmm1[31:0];\n 1: value ← xmm1[63:32];\n 2: value ← xmm1[95:64];\n 3: value ← xmm1[127:96];\nendcase;\nif (r32/m32 is register) then\n r32 ← value;\nelse\n [r32/m32] ← value;\nendif;", "example": "PEXTRD r32/m32, xmm1, 3"} {"mnemonic": "pextrq", "architecture": "x86", "full_name": "Packed Extract Quadword", "summary": "Extracts a quadword from XMM to register.", "syntax": "PEXTRQ r64/m64, xmm1, imm8", "encoding": {"format": "SSE4.1", "hex_opcode": "66 REX.W 0F 3A 16 /r ib", "visual_parts": [], "binary_pattern": "66 | 0F | 3A | 16", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "r64/m64", "desc": "General-purpose register or Memory operand"}, {"name": "src1", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Extracts a 64-bit quadword from an XMM register at the position specified by an 8-bit immediate and writes it to a general-purpose register or memory. Available in SSE4.1 and later (64-bit mode only); no flags are affected by this instruction.", "pseudocode": "index ← imm8[0];\ncase index of\n 0: value ← xmm1[63:0];\n 1: value ← xmm1[127:64];\nendcase;\nif (r64/m64 is register) then\n r64 ← value;\nelse\n [r64/m64] ← value;\nendif;", "example": "PEXTRQ r64/m64, xmm1, 3"} {"mnemonic": "movntdqa", "architecture": "x86", "full_name": "Load Double Quadword Non-Temporal Aligned", "summary": "Efficiently loads 128-bits from WC memory (Streaming Load).", "syntax": "MOVNTDQA xmm1, m128", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 38 2A", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 2A", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "m128", "desc": "128-bit memory operand"}], "description": "Loads 128 bits from write-combining (WC) memory into an XMM register using a non-temporal hint to minimize cache pollution. This instruction bypasses the normal cache coherency protocol and is optimized for streaming data loads. Available in SSE4.1 and later; no flags are affected. The memory address should be 16-byte aligned for best performance.", "pseudocode": "xmm1 ← [m128];", "example": "MOVNTDQA xmm1, [rbp-16]"} {"mnemonic": "pcmpgtq", "architecture": "x86", "full_name": "Packed Compare Greater Than Quadword", "summary": "Compares quadwords for greater than (signed).", "syntax": "PCMPGTQ xmm1, xmm2/m128", "encoding": {"format": "SSE4.2", "hex_opcode": "66 0F 38 37", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 37", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.2", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Compares packed signed 64-bit integers in xmm1 with xmm2/m128 for greater-than, writing a mask (all-1s for true, all-0s for false) of each comparison to xmm1. This is a SIMD comparison with no effect on the CPU flags. Available in SSE4.2 and later; operates on 128-bit XMM registers containing two 64-bit signed quadwords.", "pseudocode": "xmm1[127:64] ← (xmm1[127:64] > xmm2[127:64]) ? 0xFFFFFFFFFFFFFFFF : 0x0000000000000000;\nxmm1[63:0] ← (xmm1[63:0] > xmm2[63:0]) ? 0xFFFFFFFFFFFFFFFF : 0x0000000000000000;", "example": "PCMPGTQ xmm1, xmm2/m128"} {"mnemonic": "packusdw", "architecture": "x86", "full_name": "Pack with Unsigned Saturation Doubleword to Word", "summary": "Converts signed dwords to unsigned words with saturation.", "syntax": "PACKUSDW xmm1, xmm2/m128", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 38 2B", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 2B", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Packs four signed doublewords (32-bit) from each 128-bit operand into eight unsigned words (16-bit) with unsigned saturation, storing the result in the destination XMM register. Values outside the range [0, 65535] are saturated to the nearest boundary. No flags are affected.", "pseudocode": "dest[0:15] ← saturate_unsigned(src1[0:31], 0, 65535)\ndest[16:31] ← saturate_unsigned(src1[32:63], 0, 65535)\ndest[32:47] ← saturate_unsigned(src1[64:95], 0, 65535)\ndest[48:63] ← saturate_unsigned(src1[96:127], 0, 65535)\ndest[64:79] ← saturate_unsigned(src2[0:31], 0, 65535)\ndest[80:95] ← saturate_unsigned(src2[32:63], 0, 65535)\ndest[96:111] ← saturate_unsigned(src2[64:95], 0, 65535)\ndest[112:127] ← saturate_unsigned(src2[96:127], 0, 65535)", "example": "PACKUSDW xmm1, xmm2/m128"} {"mnemonic": "sets", "architecture": "x86", "full_name": "Set Byte on Sign", "summary": "Sets byte to 1 if SF=1 (Negative).", "syntax": "SETS r/m8", "encoding": {"format": "Legacy", "hex_opcode": "0F 98", "visual_parts": [], "binary_pattern": "0F | 98", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m8", "desc": "8-bit register or memory"}], "description": "Sets the destination byte to 1 if the Sign Flag (SF) is set (indicating a negative result from the previous operation), otherwise sets it to 0. No flags are affected by this instruction. Available in all x86/x64 modes.", "pseudocode": "if (SF == 1) {\n dest ← 0xFF\n} else {\n dest ← 0x00\n}", "example": "SETS bl"} {"mnemonic": "setns", "architecture": "x86", "full_name": "Set Byte on Not Sign", "summary": "Sets byte to 1 if SF=0 (Positive).", "syntax": "SETNS r/m8", "encoding": {"format": "Legacy", "hex_opcode": "0F 99", "visual_parts": [], "binary_pattern": "0F | 99", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m8", "desc": "8-bit register or memory"}], "description": "Sets the destination byte to 1 if the Sign Flag (SF) is clear (indicating a positive or zero result from the previous operation), otherwise sets it to 0. No flags are affected by this instruction. Available in all x86/x64 modes.", "pseudocode": "if (SF == 0) {\n dest ← 0xFF\n} else {\n dest ← 0x00\n}", "example": "SETNS bl"} {"mnemonic": "setp", "architecture": "x86", "full_name": "Set Byte on Parity", "summary": "Sets byte to 1 if PF=1 (Even Parity).", "syntax": "SETP r/m8", "encoding": {"format": "Legacy", "hex_opcode": "0F 9A", "visual_parts": [], "binary_pattern": "0F | 9A", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m8", "desc": "8-bit register or memory"}], "description": "Sets the destination byte to 1 if the Parity Flag (PF) is set (indicating an even number of 1-bits in the low byte of the result), otherwise sets it to 0. No flags are affected by this instruction. Available in all x86/x64 modes.", "pseudocode": "if (PF == 1) {\n dest ← 0xFF\n} else {\n dest ← 0x00\n}", "example": "SETP bl"} {"mnemonic": "setnp", "architecture": "x86", "full_name": "Set Byte on Not Parity", "summary": "Sets byte to 1 if PF=0 (Odd Parity).", "syntax": "SETNP r/m8", "encoding": {"format": "Legacy", "hex_opcode": "0F 9B", "visual_parts": [], "binary_pattern": "0F | 9B", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m8", "desc": "8-bit register or memory"}], "description": "Sets the destination byte to 1 if the Parity Flag (PF) is clear (indicating an odd number of 1-bits in the low byte of the result), otherwise sets it to 0. No flags are affected by this instruction. Available in all x86/x64 modes.", "pseudocode": "if (PF == 0) {\n dest ← 0xFF\n} else {\n dest ← 0x00\n}", "example": "SETNP bl"} {"mnemonic": "setl", "architecture": "x86", "full_name": "Set Byte on Less", "summary": "Sets byte to 1 if SF!=OF.", "syntax": "SETL r/m8", "encoding": {"format": "Legacy", "hex_opcode": "0F 9C", "visual_parts": [], "binary_pattern": "0F | 9C", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m8", "desc": "8-bit register or memory"}], "description": "Sets the destination byte to 1 if the previous signed comparison or arithmetic result indicates a less-than condition (SF ≠ OF), otherwise sets it to 0. No flags are affected by this instruction. Used after signed compare or arithmetic operations.", "pseudocode": "if (SF != OF) {\n dest ← 0xFF\n} else {\n dest ← 0x00\n}", "example": "SETL bl"} {"mnemonic": "setle", "architecture": "x86", "full_name": "Set Byte on Less or Equal", "summary": "Sets byte to 1 if ZF=1 or SF!=OF.", "syntax": "SETLE r/m8", "encoding": {"format": "Legacy", "hex_opcode": "0F 9E", "visual_parts": [], "binary_pattern": "0F | 9E", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m8", "desc": "8-bit register or memory"}], "description": "Sets the destination byte to 1 if the previous signed comparison or arithmetic result indicates a less-than-or-equal condition (ZF = 1 or SF ≠ OF), otherwise sets it to 0. No flags are affected by this instruction. Used after signed compare or arithmetic operations.", "pseudocode": "if ((ZF == 1) || (SF != OF)) {\n dest ← 0xFF\n} else {\n dest ← 0x00\n}", "example": "SETLE bl"} {"mnemonic": "setg", "architecture": "x86", "full_name": "Set Byte on Greater", "summary": "Sets byte to 1 if ZF=0 and SF=OF.", "syntax": "SETG r/m8", "encoding": {"format": "Legacy", "hex_opcode": "0F 9F", "visual_parts": [], "binary_pattern": "0F | 9F", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m8", "desc": "8-bit register or memory"}], "description": "Sets the destination byte to 1 if the previous signed comparison or arithmetic result indicates a greater-than condition (ZF = 0 and SF = OF), otherwise sets it to 0. No flags are affected by this instruction. Used after signed compare or arithmetic operations.", "pseudocode": "if ((ZF == 0) && (SF == OF)) {\n dest ← 0xFF\n} else {\n dest ← 0x00\n}", "example": "SETG bl"} {"mnemonic": "setge", "architecture": "x86", "full_name": "Set Byte on Greater or Equal", "summary": "Sets byte to 1 if SF=OF.", "syntax": "SETGE r/m8", "encoding": {"format": "Legacy", "hex_opcode": "0F 9D", "visual_parts": [], "binary_pattern": "0F | 9D", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m8", "desc": "8-bit register or memory"}], "description": "Sets the destination byte to 1 if the signed comparison condition is true (SF = OF, indicating greater-than-or-equal for signed integers), or to 0 otherwise. This instruction reads the SF and OF flags from EFLAGS and does not modify any flags. It operates only on 8-bit destinations in all modes.", "pseudocode": "dest ← (SF == OF) ? 1 : 0;", "example": "SETGE bl"} {"mnemonic": "setb", "architecture": "x86", "full_name": "Set Byte on Below", "summary": "Sets byte to 1 if CF=1.", "syntax": "SETB r/m8", "encoding": {"format": "Legacy", "hex_opcode": "0F 92", "visual_parts": [], "binary_pattern": "0F | 92", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m8", "desc": "8-bit register or memory"}], "description": "Sets the destination byte to 1 if the carry flag (CF) is set, indicating an unsigned borrow or carry condition, or to 0 otherwise. This instruction reads CF from EFLAGS and does not modify any flags. It operates only on 8-bit destinations in all modes.", "pseudocode": "dest ← CF ? 1 : 0;", "example": "SETB bl"} {"mnemonic": "setbe", "architecture": "x86", "full_name": "Set Byte on Below or Equal", "summary": "Sets byte to 1 if CF=1 or ZF=1.", "syntax": "SETBE r/m8", "encoding": {"format": "Legacy", "hex_opcode": "0F 96", "visual_parts": [], "binary_pattern": "0F | 96", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m8", "desc": "8-bit register or memory"}], "description": "Sets the destination byte to 1 if the unsigned comparison condition is true (CF = 1 or ZF = 1, indicating below-or-equal for unsigned integers), or to 0 otherwise. This instruction reads the CF and ZF flags from EFLAGS and does not modify any flags. It operates only on 8-bit destinations in all modes.", "pseudocode": "dest ← (CF || ZF) ? 1 : 0;", "example": "SETBE bl"} {"mnemonic": "seta", "architecture": "x86", "full_name": "Set Byte on Above", "summary": "Sets byte to 1 if CF=0 and ZF=0.", "syntax": "SETA r/m8", "encoding": {"format": "Legacy", "hex_opcode": "0F 97", "visual_parts": [], "binary_pattern": "0F | 97", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m8", "desc": "8-bit register or memory"}], "description": "Sets the destination byte to 1 if the unsigned comparison condition is true (CF = 0 and ZF = 0, indicating above for unsigned integers), or to 0 otherwise. This instruction reads the CF and ZF flags from EFLAGS and does not modify any flags. It operates only on 8-bit destinations in all modes.", "pseudocode": "dest ← (!CF && !ZF) ? 1 : 0;", "example": "SETA bl"} {"mnemonic": "setae", "architecture": "x86", "full_name": "Set Byte on Above or Equal", "summary": "Sets byte to 1 if CF=0.", "syntax": "SETAE r/m8", "encoding": {"format": "Legacy", "hex_opcode": "0F 93", "visual_parts": [], "binary_pattern": "0F | 93", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m8", "desc": "8-bit register or memory"}], "description": "Sets the destination byte to 1 if the carry flag (CF) is clear, indicating no unsigned borrow (above-or-equal for unsigned integers), or to 0 otherwise. This instruction reads CF from EFLAGS and does not modify any flags. It operates only on 8-bit destinations in all modes.", "pseudocode": "dest ← (!CF) ? 1 : 0;", "example": "SETAE bl"} {"mnemonic": "kunpckwd", "architecture": "x86", "full_name": "Unpack and Interleave Masks Word to Doubleword", "summary": "Interleaves 16-bit masks into 32-bit mask.", "syntax": "KUNPCKWD k1, k2, k3", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L1.0F.W0 4B /r", "visual_parts": [], "binary_pattern": "EVEX | 0F | 4B", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512BW", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "k2", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src2", "type": "k3", "desc": "AVX-512 opmask register (k0-k7)"}], "description": "Unpacks and interleaves two 16-bit mask registers into a 32-bit mask register, with src2 supplying the high 16 bits and src1 supplying the low 16 bits of the result. This instruction is part of AVX-512BW and operates only on opmask registers (k0-k7); it does not modify any EFLAGS flags. The opmask register k0 cannot be used as a write mask.", "pseudocode": "dest[15:0] ← src1[15:0]; dest[31:16] ← src2[15:0]; dest[63:32] ← 0;", "example": "KUNPCKWD k1, k2, k3"} {"mnemonic": "kunpckdq", "architecture": "x86", "full_name": "Unpack and Interleave Masks Doubleword to Quadword", "summary": "Interleaves 32-bit masks into 64-bit mask.", "syntax": "KUNPCKDQ k1, k2, k3", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L1.0F.W1 4B /r", "visual_parts": [], "binary_pattern": "EVEX | 0F | 4B", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512BW", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "k2", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src2", "type": "k3", "desc": "AVX-512 opmask register (k0-k7)"}], "description": "Unpacks and interleaves two 32-bit mask registers into a 64-bit mask register, with src2 supplying the high 32 bits and src1 supplying the low 32 bits of the result. This instruction is part of AVX-512BW and operates only on opmask registers (k0-k7); it does not modify any EFLAGS flags. The opmask register k0 cannot be used as a write mask.", "pseudocode": "dest[31:0] ← src1[31:0]; dest[63:32] ← src2[31:0];", "example": "KUNPCKDQ k1, k2, k3"} {"mnemonic": "vpconflictq", "architecture": "x86", "full_name": "Detect Conflicts Within a Vector of Packed Quadword Values", "summary": "Detects duplicate values in a quadword vector.", "syntax": "VPCONFLICTQ zmm1 {k1}, zmm2/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W1 C4 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | C4", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512CD", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src", "type": "zmm2/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Detects conflicts (duplicate values) within a vector of 64-bit quadword values and writes a conflict mask to the destination; each element in the result contains a bitmask indicating which earlier elements in the source vector have the same value. This instruction is part of AVX-512CD, supports embedded masking via k1, and does not modify EFLAGS. Zeroing masking clears masked elements in the destination.", "pseudocode": "for i ← 0 to 7 do { dest[i*64+63:i*64] ← 0; for j ← 0 to i-1 do if src[i*64+63:i*64] == src[j*64+63:j*64] then dest[i*64+j] ← 1; } if k1_mask[i] == 0 and zeroing then dest[i*64+63:i*64] ← 0;", "example": "VPCONFLICTQ zmm1, zmm2/m512"} {"mnemonic": "vplzcntq", "architecture": "x86", "full_name": "Count Leading Zero Bits Quadword", "summary": "Counts leading zeros for each quadword element.", "syntax": "VPLZCNTQ zmm1 {k1}, zmm2/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W1 44 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 44", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512CD", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src", "type": "zmm2/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Counts the number of leading zero bits in each 64-bit quadword element of the source operand and stores the results in the destination register. Operates element-wise on 8 quadwords (512-bit / 64-bit per element). The instruction does not modify CPU flags; it is a pure SIMD data-parallel operation with AVX-512 opmask support for conditional write-masking.", "pseudocode": "for i = 0 to 7:\n src_qw = src2[64*i : 64*i+63]\n dest[64*i : 64*i+63] ← count_leading_zeros_64(src_qw)", "example": "VPLZCNTQ zmm1, zmm2/m512"} {"mnemonic": "vpermw", "architecture": "x86", "full_name": "Permute Word Integers", "summary": "Full permutation of 32 words using indices.", "syntax": "VPERMW zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W1 8D /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 8D", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512BW", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Performs a full permutation of 32 word (16-bit) elements across the entire 512-bit register using indices from a second vector operand. The index operand specifies which source element to copy to each destination position. Supports AVX-512 opmask write-masking; does not affect CPU flags.", "pseudocode": "for i = 0 to 31:\n index = src2[16*i : 16*i+15] & 0x1F\n dest[16*i : 16*i+15] ← src1[16*index : 16*index+15]", "example": "VPERMW zmm1, zmm2, zmm3/m512"} {"mnemonic": "vpermq", "architecture": "x86", "full_name": "Permute Quadword Integers", "summary": "Shuffles quadwords within 256-bit lanes using immediate.", "syntax": "VPERMQ ymm1, ymm2/m256, imm8", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F3A.W1 00 /r ib", "visual_parts": [], "binary_pattern": "VEX | 66 | 0F | 3A | 00", "bit_positions": "+0 | +3 | +4 | +5 | +6"}, "extension": "AVX2", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src1", "type": "ymm2/m256", "desc": "256-bit YMM AVX register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Shuffles four 64-bit quadword elements within each 256-bit lane using a 2-bit immediate index for each element. The immediate controls the permutation pattern within the two halves of the 256-bit operand independently. Does not affect CPU flags; operates on 256-bit YMM registers under AVX2.", "pseudocode": "for i = 0 to 3:\n index = (imm8 >> (2*i)) & 0x3\n dest[64*i : 64*i+63] ← src[64*index : 64*index+63]", "example": "VPERMQ ymm1, ymm2/m256, 3"} {"mnemonic": "vprolvq", "architecture": "x86", "full_name": "Rotate Left Quadword Variable", "summary": "Rotates quadwords left by amounts in second vector.", "syntax": "VPROLVQ zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W1 15 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 15", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Rotates each 64-bit quadword element in the first source left by the number of bits specified in the corresponding element of the second source operand. Operates on 8 quadwords in parallel; supports AVX-512 opmask write-masking. Does not modify CPU flags.", "pseudocode": "for i = 0 to 7:\n value = src1[64*i : 64*i+63]\n shift_count = src2[64*i : 64*i+63] & 0x3F\n dest[64*i : 64*i+63] ← rotate_left_64(value, shift_count)", "example": "VPROLVQ zmm1, zmm2, zmm3/m512"} {"mnemonic": "vprorvd", "architecture": "x86", "full_name": "Rotate Right Doubleword Variable", "summary": "Rotates doublewords right by amounts in second vector.", "syntax": "VPRORVD zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W0 14 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 14", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Rotates each 32-bit doubleword element in the first source right by the number of bits specified in the corresponding element of the second source operand. Operates on 16 doublewords in parallel; supports AVX-512 opmask write-masking. Does not modify CPU flags.", "pseudocode": "for i = 0 to 15:\n value = src1[32*i : 32*i+31]\n shift_count = src2[32*i : 32*i+31] & 0x1F\n dest[32*i : 32*i+31] ← rotate_right_32(value, shift_count)", "example": "VPRORVD zmm1, zmm2, zmm3/m512"} {"mnemonic": "vprorvq", "architecture": "x86", "full_name": "Rotate Right Quadword Variable", "summary": "Rotates quadwords right by amounts in second vector.", "syntax": "VPRORVQ zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W1 14 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 14", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Rotates each 64-bit quadword element in the first source right by the number of bits specified in the corresponding element of the second source operand. Operates on 8 quadwords in parallel; supports AVX-512 opmask write-masking. Does not modify CPU flags.", "pseudocode": "for i = 0 to 7:\n value = src1[64*i : 64*i+63]\n shift_count = src2[64*i : 64*i+63] & 0x3F\n dest[64*i : 64*i+63] ← rotate_right_64(value, shift_count)", "example": "VPRORVQ zmm1, zmm2, zmm3/m512"} {"mnemonic": "vpmovb2m", "architecture": "x86", "full_name": "Move Byte Mask to Mask Register", "summary": "Moves byte integer mask from ZMM to k-register.", "syntax": "VPMOVB2M k1, zmm1", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.F3.0F38.W0 29 /r", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512BW", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}], "description": "Extracts the most significant bit (MSB) from each byte element in a 512-bit ZMM register and compacts them into a 64-bit opmask register. The resulting mask register has one bit per original byte, forming a 64-bit result. Does not modify CPU flags; operates in 64-bit mode only with AVX-512BW.", "pseudocode": "mask_result = 0\nfor i = 0 to 63:\n if (src[8*i+7] != 0):\n mask_result |= (1 << i)\ndest ← mask_result", "example": "VPMOVB2M k1, zmm1"} {"mnemonic": "vpmovw2m", "architecture": "x86", "full_name": "Move Word Mask to Mask Register", "summary": "Moves word integer mask from ZMM to k-register.", "syntax": "VPMOVW2M k1, zmm1", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.F3.0F38.W1 29 /r", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512BW", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}], "description": "Extracts the most significant bit (MSB) from each word (16-bit) element in a 512-bit ZMM register and compacts them into a 32-bit opmask register. The resulting mask register has one bit per original word, forming a 32-bit result. Does not modify CPU flags; operates in 64-bit mode only with AVX-512BW.", "pseudocode": "mask_result = 0\nfor i = 0 to 31:\n if (src[16*i+15] != 0):\n mask_result |= (1 << i)\ndest ← mask_result", "example": "VPMOVW2M k1, zmm1"} {"mnemonic": "vpmovd2m", "architecture": "x86", "full_name": "Move Doubleword Mask to Mask Register", "summary": "Moves doubleword integer mask from ZMM to k-register.", "syntax": "VPMOVD2M k1, zmm1", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.F3.0F38.W0 39 /r", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512DQ", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}], "description": "Extracts the sign bit (MSB) from each 32-bit doubleword element in a 512-bit ZMM register and compacts these bits into an 8-bit mask register (k1). This instruction performs a vectorized comparison-to-mask operation, setting each bit in the destination k-register based on the corresponding doubleword's sign bit. No flags are affected by this instruction.", "pseudocode": "for i in 0 to 15:\n k1[i] ← zmm1[i*32 + 31]\nk1[16:63] ← 0", "example": "VPMOVD2M k1, zmm1"} {"mnemonic": "vpmovq2m", "architecture": "x86", "full_name": "Move Quadword Mask to Mask Register", "summary": "Moves quadword integer mask from ZMM to k-register.", "syntax": "VPMOVQ2M k1, zmm1", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.F3.0F38.W1 39 /r", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512DQ", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}], "description": "Extracts the sign bit (MSB) from each 64-bit quadword element in a 512-bit ZMM register and compacts these bits into an 8-bit mask register (k1). This instruction performs a vectorized comparison-to-mask operation on 64-bit elements, setting each bit in the destination k-register based on the corresponding quadword's sign bit. No flags are affected by this instruction.", "pseudocode": "for i in 0 to 7:\n k1[i] ← zmm1[i*64 + 63]\nk1[8:63] ← 0", "example": "VPMOVQ2M k1, zmm1"} {"mnemonic": "vpmovm2b", "architecture": "x86", "full_name": "Move Mask Register to Byte Mask", "summary": "Expands k-register bits to byte elements in ZMM.", "syntax": "VPMOVM2B zmm1, k1", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.F3.0F38.W0 28 /r", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512BW", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}], "description": "Expands each bit from an 8-bit mask register into a full byte (0x00 or 0xFF) in a 512-bit ZMM register, producing 64 byte elements. Each set bit in the source k-register generates a byte of all 1s (0xFF) in the destination; each clear bit generates a byte of all 0s (0x00). No flags are affected; this is a mask-expansion operation with no conditional behavior.", "pseudocode": "for i in 0 to 63:\n zmm1[i*8:i*8+7] ← (k1[i] ? 0xFF : 0x00)", "example": "VPMOVM2B zmm1, k1"} {"mnemonic": "vpmovm2w", "architecture": "x86", "full_name": "Move Mask Register to Word Mask", "summary": "Expands k-register bits to word elements in ZMM.", "syntax": "VPMOVM2W zmm1, k1", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.F3.0F38.W1 28 /r", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512BW", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}], "description": "Expands each bit from an 8-bit mask register into a full word (0x0000 or 0xFFFF) in a 512-bit ZMM register, producing 32 word elements. Each set bit in the source k-register generates a word of all 1s (0xFFFF) in the destination; each clear bit generates a word of all 0s (0x0000). No flags are affected; this is a mask-expansion operation with no conditional behavior.", "pseudocode": "for i in 0 to 31:\n zmm1[i*16:i*16+15] ← (k1[i] ? 0xFFFF : 0x0000)", "example": "VPMOVM2W zmm1, k1"} {"mnemonic": "vpmovm2d", "architecture": "x86", "full_name": "Move Mask Register to Doubleword Mask", "summary": "Expands k-register bits to doubleword elements in ZMM.", "syntax": "VPMOVM2D zmm1, k1", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.F3.0F38.W0 38 /r", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512DQ", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}], "description": "Expands each bit from an 8-bit mask register into a full doubleword (0x00000000 or 0xFFFFFFFF) in a 512-bit ZMM register, producing 16 doubleword elements. Each set bit in the source k-register generates a doubleword of all 1s (0xFFFFFFFF) in the destination; each clear bit generates a doubleword of all 0s (0x00000000). No flags are affected; this is a mask-expansion operation with no conditional behavior.", "pseudocode": "for i in 0 to 15:\n zmm1[i*32:i*32+31] ← (k1[i] ? 0xFFFFFFFF : 0x00000000)", "example": "VPMOVM2D zmm1, k1"} {"mnemonic": "vpmovm2q", "architecture": "x86", "full_name": "Move Mask Register to Quadword Mask", "summary": "Expands k-register bits to quadword elements in ZMM.", "syntax": "VPMOVM2Q zmm1, k1", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.F3.0F38.W1 38 /r", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512DQ", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}], "description": "Expands each bit from an 8-bit mask register into a full quadword (0x0000000000000000 or 0xFFFFFFFFFFFFFFFF) in a 512-bit ZMM register, producing 8 quadword elements. Each set bit in the source k-register generates a quadword of all 1s (0xFFFFFFFFFFFFFFFF) in the destination; each clear bit generates a quadword of all 0s (0x0000000000000000). No flags are affected; this is a mask-expansion operation with no conditional behavior.", "pseudocode": "for i in 0 to 7:\n zmm1[i*64:i*64+63] ← (k1[i] ? 0xFFFFFFFFFFFFFFFF : 0x0000000000000000)", "example": "VPMOVM2Q zmm1, k1"} {"mnemonic": "kshiftrb", "architecture": "x86", "full_name": "Shift Right Mask Byte", "summary": "Logically shifts 8-bit mask right.", "syntax": "KSHIFTRB k1, k2, imm8", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L0.66.0F3A.W0 30 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 3A | 30", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512DQ", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "k2", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Logically shifts the 8-bit contents of the source k-register right by the count specified in an 8-bit immediate, storing the result in the destination k-register. Vacated bit positions are filled with zeros; bits shifted out are discarded. No flags are affected by this mask shift operation.", "pseudocode": "shift_count ← imm8 & 0x07\nk1 ← k2 >> shift_count\nk1[8:63] ← 0", "example": "KSHIFTRB k1, k2, 3"} {"mnemonic": "kshiftrw", "architecture": "x86", "full_name": "Shift Right Mask Word", "summary": "Logically shifts 16-bit mask right.", "syntax": "KSHIFTRW k1, k2, imm8", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L0.66.0F3A.W1 30 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 3A | 32", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "k2", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Logically shifts the 16-bit contents of the source k-register right by the count specified in an 8-bit immediate, storing the result in the destination k-register. Vacated bit positions are filled with zeros; bits shifted out are discarded. No flags are affected by this mask shift operation.", "pseudocode": "shift_count ← imm8 & 0x0F\nk1 ← k2 >> shift_count\nk1[16:63] ← 0", "example": "KSHIFTRW k1, k2, 3"} {"mnemonic": "kshiftrd", "architecture": "x86", "full_name": "Shift Right Mask Doubleword", "summary": "Logically shifts 32-bit mask right.", "syntax": "KSHIFTRD k1, k2, imm8", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L0.66.0F3A.W0 31 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 3A | 34", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512BW", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "k2", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Logically shifts the 32-bit content of the source mask register right by the amount specified in the immediate operand, storing the result in the destination mask register. Bits shifted out are discarded; vacant bit positions are filled with zeros. No flags are affected; this is an AVX-512BW instruction that operates only on opmask registers (k0-k7).", "pseudocode": "dest ← (src1 >> imm8) & 0xFFFFFFFF;", "example": "KSHIFTRD k1, k2, 3"} {"mnemonic": "kshiftrq", "architecture": "x86", "full_name": "Shift Right Mask Quadword", "summary": "Logically shifts 64-bit mask right.", "syntax": "KSHIFTRQ k1, k2, imm8", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L0.66.0F3A.W1 31 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 3A | 36", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512BW", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "k2", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Logically shifts the 64-bit content of the source mask register right by the amount specified in the immediate operand, storing the result in the destination mask register. Bits shifted out are discarded; vacant bit positions are filled with zeros. No flags are affected; this is an AVX-512BW instruction that operates only on opmask registers (k0-k7).", "pseudocode": "dest ← (src1 >> imm8) & 0xFFFFFFFFFFFFFFFF;", "example": "KSHIFTRQ k1, k2, 3"} {"mnemonic": "kshiftlb", "architecture": "x86", "full_name": "Shift Left Mask Byte", "summary": "Logically shifts 8-bit mask left.", "syntax": "KSHIFTLB k1, k2, imm8", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L0.66.0F3A.W0 32 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 3A | 31", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512DQ", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "k2", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Logically shifts the 8-bit content of the source mask register left by the amount specified in the immediate operand, storing the result in the destination mask register. Bits shifted out are discarded; vacant bit positions are filled with zeros. No flags are affected; this is an AVX-512DQ instruction that operates only on opmask registers (k0-k7).", "pseudocode": "dest ← (src1 << imm8) & 0xFF;", "example": "KSHIFTLB k1, k2, 3"} {"mnemonic": "kshiftlw", "architecture": "x86", "full_name": "Shift Left Mask Word", "summary": "Logically shifts 16-bit mask left.", "syntax": "KSHIFTLW k1, k2, imm8", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L0.66.0F3A.W1 32 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 3A | 33", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "k2", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Logically shifts the 16-bit content of the source mask register left by the amount specified in the immediate operand, storing the result in the destination mask register. Bits shifted out are discarded; vacant bit positions are filled with zeros. No flags are affected; this is an AVX-512F instruction that operates only on opmask registers (k0-k7).", "pseudocode": "dest ← (src1 << imm8) & 0xFFFF;", "example": "KSHIFTLW k1, k2, 3"} {"mnemonic": "kshiftld", "architecture": "x86", "full_name": "Shift Left Mask Doubleword", "summary": "Logically shifts 32-bit mask left.", "syntax": "KSHIFTLD k1, k2, imm8", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L0.66.0F3A.W0 33 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 3A | 35", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512BW", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "k2", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Logically shifts the 32-bit content of the source mask register left by the amount specified in the immediate operand, storing the result in the destination mask register. Bits shifted out are discarded; vacant bit positions are filled with zeros. No flags are affected; this is an AVX-512BW instruction that operates only on opmask registers (k0-k7).", "pseudocode": "dest ← (src1 << imm8) & 0xFFFFFFFF;", "example": "KSHIFTLD k1, k2, 3"} {"mnemonic": "kshiftlq", "architecture": "x86", "full_name": "Shift Left Mask Quadword", "summary": "Logically shifts 64-bit mask left.", "syntax": "KSHIFTLQ k1, k2, imm8", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L0.66.0F3A.W1 33 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 3A | 37", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512BW", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "k2", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Logically shifts the 64-bit content of the source mask register left by the amount specified in the immediate operand, storing the result in the destination mask register. Bits shifted out are discarded; vacant bit positions are filled with zeros. No flags are affected; this is an AVX-512BW instruction that operates only on opmask registers (k0-k7).", "pseudocode": "dest ← (src1 << imm8) & 0xFFFFFFFFFFFFFFFF;", "example": "KSHIFTLQ k1, k2, 3"} {"mnemonic": "knotb", "architecture": "x86", "full_name": "NOT Mask Byte", "summary": "Bitwise NOT of 8-bit mask.", "syntax": "KNOTB k1, k2", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L0.66.0F.W0 44 /r", "visual_parts": [], "binary_pattern": "EVEX | 0F | 44", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512DQ", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src", "type": "k2", "desc": "AVX-512 opmask register (k0-k7)"}], "description": "Performs a bitwise NOT of the 8-bit content of the source mask register, storing the result in the destination mask register. Only the lower 8 bits are affected; other bits are zeroed. No flags are affected; this is an AVX-512DQ instruction that operates only on opmask registers (k0-k7).", "pseudocode": "dest ← (~src) & 0xFF;", "example": "KNOTB k1, k2"} {"mnemonic": "knotd", "architecture": "x86", "full_name": "NOT Mask Doubleword", "summary": "Bitwise NOT of 32-bit mask.", "syntax": "KNOTD k1, k2", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L0.66.0F.W1 44 /r", "visual_parts": [], "binary_pattern": "EVEX | 0F | 44", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512BW", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src", "type": "k2", "desc": "AVX-512 opmask register (k0-k7)"}], "description": "Performs a bitwise NOT of the 32-bit content of the source mask register, storing the result in the destination mask register. Only the lower 32 bits are affected; other bits are zeroed. No flags are affected; this is an AVX-512BW instruction that operates only on opmask registers (k0-k7).", "pseudocode": "dest ← (~src) & 0xFFFFFFFF;", "example": "KNOTD k1, k2"} {"mnemonic": "korb", "architecture": "x86", "full_name": "OR Mask Byte", "summary": "Bitwise OR of 8-bit masks.", "syntax": "KORB k1, k2, k3", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L1.66.0F.W0 45 /r", "visual_parts": [], "binary_pattern": "EVEX | 0F | 45", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512DQ", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "k2", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src2", "type": "k3", "desc": "AVX-512 opmask register (k0-k7)"}], "description": "Performs a bitwise OR of two 8-bit AVX-512 opmask registers and stores the result in the destination opmask. This instruction operates on the mask registers (k0-k7) and does not affect EFLAGS. It is part of the AVX-512DQ extension and executes with minimal latency on modern AVX-512 capable processors.", "pseudocode": "k1 ← k2 | k3;", "example": "KORB k1, k2, k3"} {"mnemonic": "kord", "architecture": "x86", "full_name": "OR Mask Doubleword", "summary": "Bitwise OR of 32-bit masks.", "syntax": "KORD k1, k2, k3", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L1.66.0F.W1 45 /r", "visual_parts": [], "binary_pattern": "EVEX | 0F | 45", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512BW", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "k2", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src2", "type": "k3", "desc": "AVX-512 opmask register (k0-k7)"}], "description": "Performs a bitwise OR of two 32-bit AVX-512 opmask registers and stores the result in the destination opmask. This instruction operates on mask registers (k0-k7) treating them as 32-bit values and does not affect EFLAGS. It is part of the AVX-512BW extension and executes with minimal latency.", "pseudocode": "k1 ← k2 | k3;", "example": "KORD k1, k2, k3"} {"mnemonic": "kxorq", "architecture": "x86", "full_name": "XOR Mask Quadword", "summary": "Bitwise XOR of 64-bit masks.", "syntax": "KXORQ k1, k2, k3", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L1.0F.W1 47 /r", "visual_parts": [], "binary_pattern": "EVEX | 0F | 47", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512BW", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "k2", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src2", "type": "k3", "desc": "AVX-512 opmask register (k0-k7)"}], "description": "Performs a bitwise XOR of two 64-bit AVX-512 opmask registers and stores the result in the destination opmask. This instruction operates on mask registers (k0-k7) treating them as 64-bit values and does not affect EFLAGS. It is part of the AVX-512BW extension and executes with minimal latency.", "pseudocode": "k1 ← k2 ^ k3;", "example": "KXORQ k1, k2, k3"} {"mnemonic": "kxord", "architecture": "x86", "full_name": "XOR Mask Doubleword", "summary": "Bitwise XOR of 32-bit masks.", "syntax": "KXORD k1, k2, k3", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L1.66.0F.W1 47 /r", "visual_parts": [], "binary_pattern": "EVEX | 0F | 47", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512BW", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "k2", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src2", "type": "k3", "desc": "AVX-512 opmask register (k0-k7)"}], "description": "Performs a bitwise XOR of two 32-bit AVX-512 opmask registers and stores the result in the destination opmask. This instruction operates on mask registers (k0-k7) treating them as 32-bit values and does not affect EFLAGS. It is part of the AVX-512BW extension and executes with minimal latency.", "pseudocode": "k1 ← k2 ^ k3;", "example": "KXORD k1, k2, k3"} {"mnemonic": "kxorb", "architecture": "x86", "full_name": "XOR Mask Byte", "summary": "Bitwise XOR of 8-bit masks.", "syntax": "KXORB k1, k2, k3", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L1.66.0F.W0 47 /r", "visual_parts": [], "binary_pattern": "EVEX | 0F | 47", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512DQ", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "k2", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src2", "type": "k3", "desc": "AVX-512 opmask register (k0-k7)"}], "description": "Performs a bitwise XOR of two 8-bit AVX-512 opmask registers and stores the result in the destination opmask. This instruction operates on mask registers (k0-k7) and does not affect EFLAGS. It is part of the AVX-512DQ extension and executes with minimal latency.", "pseudocode": "k1 ← k2 ^ k3;", "example": "KXORB k1, k2, k3"} {"mnemonic": "kortestb", "architecture": "x86", "full_name": "OR Masks and Set Flags Byte", "summary": "ORs 8-bit masks and sets EFLAGS (ZF/CF).", "syntax": "KORTESTB k1, k2", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L0.66.0F.W0 98 /r", "visual_parts": [], "binary_pattern": "EVEX | 0F | 98", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512DQ", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src", "type": "k2", "desc": "AVX-512 opmask register (k0-k7)"}], "description": "ORs two 8-bit AVX-512 opmask registers and sets EFLAGS based on the result without storing the OR result. Sets ZF if the OR result is all zeros, and CF if the first source opmask is all zeros. Part of the AVX-512DQ extension, this instruction is useful for testing mask conditions.", "pseudocode": "temp ← k1 | k2; ZF ← (temp == 0); CF ← (k1 == 0);", "example": "KORTESTB k1, k2"} {"mnemonic": "kortestq", "architecture": "x86", "full_name": "OR Masks and Set Flags Quadword", "summary": "ORs 64-bit masks and sets EFLAGS (ZF/CF).", "syntax": "KORTESTQ k1, k2", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L0.0F.W1 98 /r", "visual_parts": [], "binary_pattern": "EVEX | 0F | 98", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512BW", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src", "type": "k2", "desc": "AVX-512 opmask register (k0-k7)"}], "description": "ORs two 64-bit AVX-512 opmask registers and sets EFLAGS based on the result without storing the OR result. Sets ZF if the OR result is all zeros, and CF if the first source opmask is all zeros. Part of the AVX-512BW extension, this instruction is useful for testing mask conditions.", "pseudocode": "temp ← k1 | k2; ZF ← (temp == 0); CF ← (k1 == 0);", "example": "KORTESTQ k1, k2"} {"mnemonic": "ktestb", "architecture": "x86", "full_name": "Test Masks Byte", "summary": "ANDs 8-bit masks and sets EFLAGS (ZF/CF).", "syntax": "KTESTB k1, k2", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L0.66.0F.W0 99 /r", "visual_parts": [], "binary_pattern": "EVEX | 0F | 99", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512DQ", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src", "type": "k2", "desc": "AVX-512 opmask register (k0-k7)"}], "description": "ANDs two 8-bit AVX-512 opmask registers and sets EFLAGS based on the result without storing the AND result. Sets ZF if the AND result is all zeros, and CF if the first source opmask is all zeros. Part of the AVX-512DQ extension, this instruction is useful for testing mask bit intersections.", "pseudocode": "temp ← k1 & k2; ZF ← (temp == 0); CF ← (k1 == 0);", "example": "KTESTB k1, k2"} {"mnemonic": "ktestw", "architecture": "x86", "full_name": "Test Masks Word", "summary": "ANDs 16-bit masks and sets EFLAGS (ZF/CF).", "syntax": "KTESTW k1, k2", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L0.0F.W0 99 /r", "visual_parts": [], "binary_pattern": "EVEX | 0F | 99", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src", "type": "k2", "desc": "AVX-512 opmask register (k0-k7)"}], "description": "Performs a bitwise AND of two 16-bit AVX-512 opmask registers and updates EFLAGS based on the result without storing the AND product. Sets ZF if the result is zero, clears ZF otherwise; sets CF if all bits of the first operand are zero, clears CF otherwise. This instruction executes in 64-bit mode only and is part of AVX-512F.", "pseudocode": "temp ← k1 AND k2\nZF ← (temp == 0)\nCF ← (k1 == 0)\nOF ← 0\nSF ← 0\nAF ← undefined\nPF ← undefined", "example": "KTESTW k1, k2"} {"mnemonic": "ktestd", "architecture": "x86", "full_name": "Test Masks Doubleword", "summary": "ANDs 32-bit masks and sets EFLAGS (ZF/CF).", "syntax": "KTESTD k1, k2", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L0.66.0F.W1 99 /r", "visual_parts": [], "binary_pattern": "EVEX | 0F | 99", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512BW", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src", "type": "k2", "desc": "AVX-512 opmask register (k0-k7)"}], "description": "Performs a bitwise AND of two 32-bit AVX-512 opmask registers and updates EFLAGS based on the result without storing the AND product. Sets ZF if the result is zero, clears ZF otherwise; sets CF if all bits of the first operand are zero, clears CF otherwise. This instruction executes in 64-bit mode only and requires AVX-512BW.", "pseudocode": "temp ← k1 AND k2\nZF ← (temp == 0)\nCF ← (k1 == 0)\nOF ← 0\nSF ← 0\nAF ← undefined\nPF ← undefined", "example": "KTESTD k1, k2"} {"mnemonic": "ktestq", "architecture": "x86", "full_name": "Test Masks Quadword", "summary": "ANDs 64-bit masks and sets EFLAGS (ZF/CF).", "syntax": "KTESTQ k1, k2", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L0.0F.W1 99 /r", "visual_parts": [], "binary_pattern": "EVEX | 0F | 99", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512BW", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src", "type": "k2", "desc": "AVX-512 opmask register (k0-k7)"}], "description": "Performs a bitwise AND of two 64-bit AVX-512 opmask registers and updates EFLAGS based on the result without storing the AND product. Sets ZF if the result is zero, clears ZF otherwise; sets CF if all bits of the first operand are zero, clears CF otherwise. This instruction executes in 64-bit mode only and requires AVX-512BW.", "pseudocode": "temp ← k1 AND k2\nZF ← (temp == 0)\nCF ← (k1 == 0)\nOF ← 0\nSF ← 0\nAF ← undefined\nPF ← undefined", "example": "KTESTQ k1, k2"} {"mnemonic": "vcvtudq2pd", "architecture": "x86", "full_name": "Convert Packed Unsigned Doubleword to Double", "summary": "Converts unsigned 32-bit integers to 64-bit doubles.", "syntax": "VCVTUDQ2PD zmm1 {k1}, ymm2/m256", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.F3.0F.W0 7A /r", "visual_parts": [], "binary_pattern": "EVEX | F3 | 0F | 7A", "bit_positions": "+0 | +4 | +5 | +6"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src", "type": "ymm2/m256", "desc": "256-bit YMM AVX register or Memory operand"}], "description": "Converts four unsigned 32-bit doublewords (from a 256-bit YMM or memory operand) to four 64-bit double-precision floating-point values, storing the result in a 512-bit ZMM register with optional opmask write control. The conversion uses the current rounding mode from MXCSR. Executes in 64-bit mode only and requires AVX-512F; precision may be lost for large unsigned integers that exceed 2^53.", "pseudocode": "for i ← 0 to 3\n if k1[i] or no mask:\n zmm1[64*i:64*i+63] ← convert_udq_to_pd(ymm2_or_mem[32*i:32*i+31])\n else if zeroing:\n zmm1[64*i:64*i+63] ← 0", "example": "VCVTUDQ2PD zmm1, ymm2/m256"} {"mnemonic": "vcvtpd2udq", "architecture": "x86", "full_name": "Convert Packed Double to Unsigned Doubleword", "summary": "Converts 64-bit doubles to unsigned 32-bit integers.", "syntax": "VCVTPD2UDQ ymm1 {k1}, zmm2/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.0F.W1 79 /r", "visual_parts": [], "binary_pattern": "EVEX | 0F | 79", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src", "type": "zmm2/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Converts eight 64-bit double-precision floating-point values (from a 512-bit ZMM or memory operand) to eight unsigned 32-bit doublewords, storing the result in a 256-bit YMM register with optional opmask write control. The conversion uses the current rounding mode from MXCSR; out-of-range values saturate to the maximum unsigned 32-bit integer (2^32-1). Executes in 64-bit mode only and requires AVX-512F.", "pseudocode": "for i ← 0 to 7\n if k1[i] or no mask:\n ymm1[32*i:32*i+31] ← convert_pd_to_udq_saturate(zmm2_or_mem[64*i:64*i+63])\n else if zeroing:\n ymm1[32*i:32*i+31] ← 0", "example": "VCVTPD2UDQ ymm1, zmm2/m512"} {"mnemonic": "vcvtps2udq", "architecture": "x86", "full_name": "Convert Packed Single to Unsigned Doubleword", "summary": "Converts 32-bit floats to unsigned 32-bit integers.", "syntax": "VCVTPS2UDQ zmm1 {k1}, zmm2/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.0F.W0 79 /r", "visual_parts": [], "binary_pattern": "EVEX | 0F | 79", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src", "type": "zmm2/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Converts sixteen 32-bit single-precision floating-point values (from a 512-bit ZMM or memory operand) to sixteen unsigned 32-bit doublewords, storing the result in a 512-bit ZMM register with optional opmask write control. The conversion uses the current rounding mode from MXCSR; out-of-range values saturate to the maximum unsigned 32-bit integer (2^32-1). Executes in 64-bit mode only and requires AVX-512F.", "pseudocode": "for i ← 0 to 15\n if k1[i] or no mask:\n zmm1[32*i:32*i+31] ← convert_ps_to_udq_saturate(zmm2_or_mem[32*i:32*i+31])\n else if zeroing:\n zmm1[32*i:32*i+31] ← 0", "example": "VCVTPS2UDQ zmm1, zmm2/m512"} {"mnemonic": "vcvtuqq2ps", "architecture": "x86", "full_name": "Convert Packed Unsigned Quadword to Single", "summary": "Converts unsigned 64-bit integers to 32-bit floats.", "syntax": "VCVTUQQ2PS ymm1 {k1}, zmm2/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.F2.0F.W1 7A /r", "visual_parts": [], "binary_pattern": "EVEX | F2 | 0F | 7A", "bit_positions": "+0 | +4 | +5 | +6"}, "extension": "AVX-512DQ", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src", "type": "zmm2/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Converts eight unsigned 64-bit quadwords (from a 512-bit ZMM or memory operand) to eight 32-bit single-precision floating-point values, storing the result in a 256-bit YMM register with optional opmask write control. The conversion uses the current rounding mode from MXCSR. Executes in 64-bit mode only and requires AVX-512F; precision may be lost for large unsigned integers that exceed 2^24.", "pseudocode": "for i ← 0 to 7\n if k1[i] or no mask:\n ymm1[32*i:32*i+31] ← convert_uq_to_ps(zmm2_or_mem[64*i:64*i+63])\n else if zeroing:\n ymm1[32*i:32*i+31] ← 0", "example": "VCVTUQQ2PS ymm1, zmm2/m512"} {"mnemonic": "vcvtuqq2pd", "architecture": "x86", "full_name": "Convert Packed Unsigned Quadword to Double", "summary": "Converts unsigned 64-bit integers to 64-bit doubles.", "syntax": "VCVTUQQ2PD zmm1 {k1}, zmm2/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.F3.0F.W1 7A /r", "visual_parts": [], "binary_pattern": "EVEX | F3 | 0F | 7A", "bit_positions": "+0 | +4 | +5 | +6"}, "extension": "AVX-512DQ", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src", "type": "zmm2/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Converts eight unsigned 64-bit quadwords (from a 512-bit ZMM or memory operand) to eight 64-bit double-precision floating-point values, storing the result in a 512-bit ZMM register with optional opmask write control. The conversion uses the current rounding mode from MXCSR. Executes in 64-bit mode only and requires AVX-512F; full precision is maintained since IEEE 754 double can exactly represent all 64-bit unsigned integers.", "pseudocode": "for i ← 0 to 7\n if k1[i] or no mask:\n zmm1[64*i:64*i+63] ← convert_uq_to_pd(zmm2_or_mem[64*i:64*i+63])\n else if zeroing:\n zmm1[64*i:64*i+63] ← 0", "example": "VCVTUQQ2PD zmm1, zmm2/m512"} {"mnemonic": "vcvtps2uqq", "architecture": "x86", "full_name": "Convert Packed Single to Unsigned Quadword", "summary": "Converts 32-bit floats to unsigned 64-bit integers.", "syntax": "VCVTPS2UQ zmm1 {k1}, ymm2/m256", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F.W0 79 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 79", "bit_positions": "+0 | +4 | +5 | +6"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src", "type": "ymm2/m256", "desc": "256-bit YMM AVX register or Memory operand"}], "description": "Converts packed 32-bit single-precision floating-point values to unsigned 64-bit integers. The instruction reads 256 bits (4 × 32-bit floats from ymm2/m256) and produces 512 bits (4 × 64-bit unsigned integers in zmm1). EVEX encoding enables masking via k1 and rounding mode control; results are undefined if any value overflows the unsigned 64-bit range, and invalid floating-point exceptions are raised on NaN inputs. The instruction operates in 64-bit, protected, and real modes with AVX-512F support.", "pseudocode": "zmm1[63:0] ← (src[31:0] is valid && src[31:0] ≤ 2^64-1) ? convert_float_to_uint64(src[31:0]) : undefined; zmm1[127:64] ← convert_float_to_uint64(src[63:32]); zmm1[191:128] ← convert_float_to_uint64(src[95:64]); zmm1[255:192] ← convert_float_to_uint64(src[127:96]);", "example": "VCVTPS2UQ zmm1, ymm2/m256"} {"mnemonic": "vcvtpd2uqq", "architecture": "x86", "full_name": "Convert Packed Double to Unsigned Quadword", "summary": "Converts 64-bit doubles to unsigned 64-bit integers.", "syntax": "VCVTPD2UQ zmm1 {k1}, zmm2/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F.W1 79 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 79", "bit_positions": "+0 | +4 | +5 | +6"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src", "type": "zmm2/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Converts packed 64-bit double-precision floating-point values to unsigned 64-bit integers. The instruction reads 512 bits (4 × 64-bit doubles from zmm2/m512) and produces 512 bits (4 × 64-bit unsigned integers in zmm1). EVEX masking via k1 and rounding control are supported; overflow conditions and NaN inputs trigger invalid floating-point exceptions. Operates in 64-bit, protected, and real modes with AVX-512F support.", "pseudocode": "zmm1[63:0] ← convert_double_to_uint64(src[63:0]); zmm1[127:64] ← convert_double_to_uint64(src[127:64]); zmm1[191:128] ← convert_double_to_uint64(src[191:128]); zmm1[255:192] ← convert_double_to_uint64(src[255:192]);", "example": "VCVTPD2UQ zmm1, zmm2/m512"} {"mnemonic": "vfmaddcph", "architecture": "x86", "full_name": "Complex Multiply-Add FP16", "summary": "Complex multiply-add for half-precision.", "syntax": "VFMADDCPH zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.F3.MAP6.W0 56 /r", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512-FP16", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Performs complex multiply-add on packed half-precision (FP16) complex numbers. Each ZMM register holds 16 FP16 values (8 complex pairs); the instruction computes (src1 × src2) + dest for each complex pair and stores the result in dest. EVEX masking (k1) and embedded rounding are supported. Intermediate calculations use extended precision to minimize rounding errors. Requires AVX-512-FP16 support.", "pseudocode": "for i = 0 to 7 do: real_i ← src1[32*i+15:32*i] * src2[32*i+15:32*i] - src1[32*i+31:32*i+16] * src2[32*i+31:32*i+16]; imag_i ← src1[32*i+15:32*i] * src2[32*i+31:32*i+16] + src1[32*i+31:32*i+16] * src2[32*i+15:32*i]; dest[32*i+15:32*i] ← real_i + dest[32*i+15:32*i]; dest[32*i+31:32*i+16] ← imag_i + dest[32*i+31:32*i+16];", "example": "VFMADDCPH zmm1, zmm2, zmm3/m512"} {"mnemonic": "vfcmaddcph", "architecture": "x86", "full_name": "Complex Conjugate Multiply-Add FP16", "summary": "Complex conjugate multiply-add for half-precision.", "syntax": "VFCMADDCPH zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.F2.MAP6.W0 56 /r", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512-FP16", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Performs complex conjugate multiply-add on packed half-precision (FP16) complex numbers. Each ZMM holds 16 FP16 values (8 complex pairs); the instruction computes (src1 × conj(src2)) + dest for each pair, where conj() negates the imaginary component. EVEX masking (k1) and embedded rounding control are supported. Intermediate precision extension minimizes rounding artifacts. Requires AVX-512-FP16 support.", "pseudocode": "for i = 0 to 7 do: real_i ← src1[32*i+15:32*i] * src2[32*i+15:32*i] + src1[32*i+31:32*i+16] * src2[32*i+31:32*i+16]; imag_i ← src1[32*i+31:32*i+16] * src2[32*i+15:32*i] - src1[32*i+15:32*i] * src2[32*i+31:32*i+16]; dest[32*i+15:32*i] ← real_i + dest[32*i+15:32*i]; dest[32*i+31:32*i+16] ← imag_i + dest[32*i+31:32*i+16];", "example": "VFCMADDCPH zmm1, zmm2, zmm3/m512"} {"mnemonic": "vfmaddcsh", "architecture": "x86", "full_name": "Complex Multiply-Add Scalar FP16", "summary": "Complex multiply-add for scalar half-precision.", "syntax": "VFMADDCSH xmm1 {k1}, xmm2, xmm3/m32", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.LLIG.F3.MAP6.W0 57 /r", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512-FP16", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2", "desc": "128-bit XMM SIMD register"}, {"name": "src2", "type": "xmm3/m32", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Performs scalar complex multiply-add on half-precision (FP16) complex numbers. The lower 32 bits of xmm1 and xmm2 represent a single complex number (two FP16 values: real and imaginary); the instruction computes (src1 × src2) + dest for that pair and updates only the lower 32 bits of xmm1. EVEX masking (k1) and embedded rounding are supported. Requires AVX-512-FP16 support.", "pseudocode": "real ← src1[15:0] * src2[15:0] - src1[31:16] * src2[31:16]; imag ← src1[15:0] * src2[31:16] + src1[31:16] * src2[15:0]; xmm1[15:0] ← real + dest[15:0]; xmm1[31:16] ← imag + dest[31:16]; xmm1[127:32] ← dest[127:32];", "example": "VFMADDCSH xmm1, xmm2, xmm3/m32"} {"mnemonic": "vcmpps", "architecture": "x86", "full_name": "Compare Packed Single-Precision (AVX)", "summary": "Compares packed floats (AVX version with immediate).", "syntax": "VCMPPS ymm1, ymm2, ymm3/m256, imm8", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.0F.WIG C2 /r ib", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AVX", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src1", "type": "ymm2", "desc": "256-bit YMM AVX register"}, {"name": "src2", "type": "ymm3/m256", "desc": "256-bit YMM AVX register or Memory operand"}, {"name": "src3", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Compares packed 32-bit single-precision floats and stores the boolean result (all-ones or all-zeros per element) in the destination YMM register. The comparison operator is encoded in the imm8 field (0=EQ, 1=LT, 2=LE, 4=NEQ, 5=NLT, 6=NLE, etc.). Quiet NaNs produce false results; signaling NaNs trigger invalid floating-point exceptions (unless masked). VEX encoding supports 256-bit operations; three-operand form allows non-destructive destination. Operates in 64-bit, protected, and real modes with AVX support.", "pseudocode": "for i = 0 to 7 do: cmp_result ← compare_float(src1[32*i+31:32*i], src2[32*i+31:32*i], imm8); dest[32*i+31:32*i] ← cmp_result ? 0xFFFFFFFF : 0x00000000;", "example": "VCMPPS ymm1, ymm2, ymm3/m256, 3"} {"mnemonic": "vcmppd", "architecture": "x86", "full_name": "Compare Packed Double-Precision (AVX)", "summary": "Compares packed doubles (AVX version with immediate).", "syntax": "VCMPPD ymm1, ymm2, ymm3/m256, imm8", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F.WIG C2 /r ib", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AVX", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src1", "type": "ymm2", "desc": "256-bit YMM AVX register"}, {"name": "src2", "type": "ymm3/m256", "desc": "256-bit YMM AVX register or Memory operand"}, {"name": "src3", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Compares packed 64-bit double-precision floats and stores the boolean result (all-ones or all-zeros per element) in the destination YMM register. The comparison predicate is encoded in imm8 (0=EQ, 1=LT, 2=LE, 4=NEQ, 5=NLT, 6=NLE, etc.). Quiet NaNs return false; signaling NaNs trigger invalid floating-point exceptions (unless masked). VEX encoding supports 256-bit operations; three-operand form enables non-destructive destination. Operates in 64-bit, protected, and real modes with AVX support.", "pseudocode": "for i = 0 to 3 do: cmp_result ← compare_double(src1[64*i+63:64*i], src2[64*i+63:64*i], imm8); dest[64*i+63:64*i] ← cmp_result ? 0xFFFFFFFFFFFFFFFF : 0x0000000000000000;", "example": "VCMPPD ymm1, ymm2, ymm3/m256, 3"} {"mnemonic": "vpcmpb", "architecture": "x86", "full_name": "Compare Packed Byte Integers", "summary": "Compares bytes and stores result in k-register mask.", "syntax": "VPCMPB k1 {k2}, zmm2, zmm3/m512, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F3A.W0 3F /r ib", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512BW", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}, {"name": "src3", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Compares packed 8-bit signed integers and stores the boolean result in an AVX-512 opmask register (k1). The comparison operator is encoded in imm8 (0=EQ, 1=LT, 2=LE, 4=NEQ, 5=NLT, 6=NLE, etc.). EVEX encoding enables masking via k2 (merge-with-zero or keep-unchanged per bit). The destination k1 register holds 64 single-bit results corresponding to 64 bytes. Operates in 64-bit mode with AVX-512BW support.", "pseudocode": "for i = 0 to 63 do: if k2[i] == 1 or k2 is unused then: cmp_result ← compare_signed_byte(src1[8*i+7:8*i], src2[8*i+7:8*i], imm8); k1[i] ← cmp_result ? 1 : 0; else: k1[i] ← 0;", "example": "VPCMPB k1, zmm2, zmm3/m512, 3"} {"mnemonic": "vpcmpw", "architecture": "x86", "full_name": "Compare Packed Word Integers", "summary": "Compares words and stores result in k-register mask.", "syntax": "VPCMPW k1 {k2}, zmm2, zmm3/m512, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F3A.W1 3F /r ib", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512BW", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}, {"name": "src3", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Compares packed signed 16-bit integers in zmm2 against zmm3/m512 using the comparison predicate specified in imm8, storing the boolean results in the opmask k1 (optionally merged with k2). The instruction operates on 32 word elements in 512-bit vectors and does not modify EFLAGS; the predicate selector in imm8 determines the comparison type (equal, less, less-equal, unordered, etc.). Available only in 64-bit mode with AVX-512BW extension.", "pseudocode": "for i in 0..31:\n elem1 ← zmm2[16*i : 16*i+15] as signed 16-bit\n elem2 ← zmm3/m512[16*i : 16*i+15] as signed 16-bit\n k1[i] ← (mask_merge) ? k2[i] : 0\n if pred(elem1, elem2, imm8) then k1[i] ← 1", "example": "VPCMPW k1, zmm2, zmm3/m512, 3"} {"mnemonic": "vpcmpd", "architecture": "x86", "full_name": "Compare Packed Doubleword Integers", "summary": "Compares doublewords and stores result in k-register mask.", "syntax": "VPCMPD k1 {k2}, zmm2, zmm3/m512, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F3A.W0 1F /r ib", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}, {"name": "src3", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Compares packed signed 32-bit integers in zmm2 against zmm3/m512 using the comparison predicate in imm8, storing boolean results in opmask k1 (optionally merged with k2). Operates on 16 doubleword elements in 512-bit vectors without affecting EFLAGS; the imm8 predicate determines comparison semantics (EQ, LT, LE, NEQ, NLT, NLE, etc.). Available in 64-bit mode with AVX-512F extension.", "pseudocode": "for i in 0..15:\n elem1 ← zmm2[32*i : 32*i+31] as signed 32-bit\n elem2 ← zmm3/m512[32*i : 32*i+31] as signed 32-bit\n k1[i] ← (mask_merge) ? k2[i] : 0\n if pred(elem1, elem2, imm8) then k1[i] ← 1", "example": "VPCMPD k1, zmm2, zmm3/m512, 3"} {"mnemonic": "vpcmpq", "architecture": "x86", "full_name": "Compare Packed Quadword Integers", "summary": "Compares quadwords and stores result in k-register mask.", "syntax": "VPCMPQ k1 {k2}, zmm2, zmm3/m512, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F3A.W1 1F /r ib", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}, {"name": "src3", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Compares packed signed 64-bit integers in zmm2 against zmm3/m512 using the comparison predicate in imm8, storing boolean results in opmask k1 (optionally merged with k2). Operates on 8 quadword elements in 512-bit vectors without modifying EFLAGS; the imm8 predicate encodes the comparison condition (equal, less-than, less-than-or-equal, etc.). Available in 64-bit mode with AVX-512F extension.", "pseudocode": "for i in 0..7:\n elem1 ← zmm2[64*i : 64*i+63] as signed 64-bit\n elem2 ← zmm3/m512[64*i : 64*i+63] as signed 64-bit\n k1[i] ← (mask_merge) ? k2[i] : 0\n if pred(elem1, elem2, imm8) then k1[i] ← 1", "example": "VPCMPQ k1, zmm2, zmm3/m512, 3"} {"mnemonic": "vpcmpub", "architecture": "x86", "full_name": "Compare Packed Unsigned Byte Integers", "summary": "Compares unsigned bytes and stores result in k-register.", "syntax": "VPCMPUB k1 {k2}, zmm2, zmm3/m512, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F3A.W0 3E /r ib", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512BW", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}, {"name": "src3", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Compares packed unsigned 8-bit integers in zmm2 against zmm3/m512 using the comparison predicate in imm8, storing boolean results in opmask k1 (optionally merged with k2). Operates on 64 byte elements in 512-bit vectors; comparison is performed as unsigned and imm8 specifies the predicate (equal, less, less-equal, etc.). Available in 64-bit mode with AVX-512BW extension; EFLAGS are not modified.", "pseudocode": "for i in 0..63:\n elem1 ← zmm2[8*i : 8*i+7] as unsigned 8-bit\n elem2 ← zmm3/m512[8*i : 8*i+7] as unsigned 8-bit\n k1[i] ← (mask_merge) ? k2[i] : 0\n if pred(elem1, elem2, imm8) then k1[i] ← 1", "example": "VPCMPUB k1, zmm2, zmm3/m512, 3"} {"mnemonic": "vpcmpuw", "architecture": "x86", "full_name": "Compare Packed Unsigned Word Integers", "summary": "Compares unsigned words and stores result in k-register.", "syntax": "VPCMPUW k1 {k2}, zmm2, zmm3/m512, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F3A.W1 3E /r ib", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512BW", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}, {"name": "src3", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Compares packed unsigned 16-bit integers in zmm2 against zmm3/m512 using the comparison predicate in imm8, storing boolean results in opmask k1 (optionally merged with k2). Operates on 32 word elements in 512-bit vectors; comparison is performed as unsigned and imm8 encodes the predicate type (equal, less, less-equal, not-equal, etc.). Available in 64-bit mode with AVX-512BW extension; EFLAGS remain unaffected.", "pseudocode": "for i in 0..31:\n elem1 ← zmm2[16*i : 16*i+15] as unsigned 16-bit\n elem2 ← zmm3/m512[16*i : 16*i+15] as unsigned 16-bit\n k1[i] ← (mask_merge) ? k2[i] : 0\n if pred(elem1, elem2, imm8) then k1[i] ← 1", "example": "VPCMPUW k1, zmm2, zmm3/m512, 3"} {"mnemonic": "vpcmpud", "architecture": "x86", "full_name": "Compare Packed Unsigned Doubleword Integers", "summary": "Compares unsigned doublewords and stores result in k-register.", "syntax": "VPCMPUD k1 {k2}, zmm2, zmm3/m512, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F3A.W0 1E /r ib", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}, {"name": "src3", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Compares packed unsigned 32-bit integers in zmm2 against zmm3/m512 using the comparison predicate in imm8, storing boolean results in opmask k1 (optionally merged with k2). Operates on 16 doubleword elements in 512-bit vectors; all comparisons are unsigned and imm8 specifies the predicate (equal, less, less-equal, not-equal, etc.). Available in 64-bit mode with AVX-512F extension; EFLAGS are not modified.", "pseudocode": "for i in 0..15:\n elem1 ← zmm2[32*i : 32*i+31] as unsigned 32-bit\n elem2 ← zmm3/m512[32*i : 32*i+31] as unsigned 32-bit\n k1[i] ← (mask_merge) ? k2[i] : 0\n if pred(elem1, elem2, imm8) then k1[i] ← 1", "example": "VPCMPUD k1, zmm2, zmm3/m512, 3"} {"mnemonic": "vpcmpuq", "architecture": "x86", "full_name": "Compare Packed Unsigned Quadword Integers", "summary": "Compares unsigned quadwords and stores result in k-register.", "syntax": "VPCMPUQ k1 {k2}, zmm2, zmm3/m512, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F3A.W1 1E /r ib", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}, {"name": "src3", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Compares packed unsigned 64-bit integers in zmm2 against zmm3/m512 using the comparison predicate in imm8, storing boolean results in opmask k1 (optionally merged with k2). Operates on 8 quadword elements in 512-bit vectors; all comparisons are unsigned and imm8 encodes the predicate (equal, less-than, less-equal, not-equal, etc.). Available in 64-bit mode with AVX-512F extension; EFLAGS remain unchanged.", "pseudocode": "for i in 0..7:\n elem1 ← zmm2[64*i : 64*i+63] as unsigned 64-bit\n elem2 ← zmm3/m512[64*i : 64*i+63] as unsigned 64-bit\n k1[i] ← (mask_merge) ? k2[i] : 0\n if pred(elem1, elem2, imm8) then k1[i] ← 1", "example": "VPCMPUQ k1, zmm2, zmm3/m512, 3"} {"mnemonic": "vptestmb", "architecture": "x86", "full_name": "Packed Test Mask Byte", "summary": "Tests byte integers and sets k-register mask.", "syntax": "VPTESTMB k1 {k2}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W0 26 /r", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512BW", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Tests packed 8-bit integers by performing a bitwise AND of zmm2 and zmm3/m512, setting each bit in opmask k1 if the result is nonzero (optionally merged with k2). Operates on 64 byte elements in 512-bit vectors and does not modify EFLAGS; this is a destructive AND-test operation that sets mask bits based on non-zero results. Available in 64-bit mode with AVX-512BW extension.", "pseudocode": "for i in 0..63:\n elem1 ← zmm2[8*i : 8*i+7]\n elem2 ← zmm3/m512[8*i : 8*i+7]\n k1[i] ← (mask_merge) ? k2[i] : 0\n if (elem1 & elem2) != 0 then k1[i] ← 1", "example": "VPTESTMB k1, zmm2, zmm3/m512"} {"mnemonic": "vptestmw", "architecture": "x86", "full_name": "Packed Test Mask Word", "summary": "Tests word integers and sets k-register mask.", "syntax": "VPTESTMW k1 {k2}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W1 26 /r", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512BW", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Tests packed word integers by performing a bitwise AND between two 512-bit ZMM sources and sets the result bits in the destination k-register mask. Each bit in the k-register corresponds to whether the AND result for that word element is nonzero. No arithmetic flags (OF, SF, ZF, AF, CF, PF) are modified; only the k-register mask is updated. This is an AVX-512BW instruction that operates on 16-bit elements.", "pseudocode": "for i = 0 to 31:\n element_result = zmm2[i*16+15:i*16] & zmm3[i*16+15:i*16]\n k1[i] = (element_result != 0) ? 1 : 0", "example": "VPTESTMW k1, zmm2, zmm3/m512"} {"mnemonic": "vptestmd", "architecture": "x86", "full_name": "Packed Test Mask Doubleword", "summary": "Tests doubleword integers and sets k-register mask.", "syntax": "VPTESTMD k1 {k2}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W0 27 /r", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Tests packed doubleword integers by performing a bitwise AND between two 512-bit ZMM sources and sets the result bits in the destination k-register mask. Each bit in the k-register corresponds to whether the AND result for that doubleword element is nonzero. No arithmetic flags (OF, SF, ZF, AF, CF, PF) are modified; only the k-register mask is updated. This is an AVX-512F instruction that operates on 32-bit elements.", "pseudocode": "for i = 0 to 15:\n element_result = zmm2[i*32+31:i*32] & zmm3[i*32+31:i*32]\n k1[i] = (element_result != 0) ? 1 : 0", "example": "VPTESTMD k1, zmm2, zmm3/m512"} {"mnemonic": "vptestmq", "architecture": "x86", "full_name": "Packed Test Mask Quadword", "summary": "Tests quadword integers and sets k-register mask.", "syntax": "VPTESTMQ k1 {k2}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W1 27 /r", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Tests packed quadword integers by performing a bitwise AND between two 512-bit ZMM sources and sets the result bits in the destination k-register mask. Each bit in the k-register corresponds to whether the AND result for that quadword element is nonzero. No arithmetic flags (OF, SF, ZF, AF, CF, PF) are modified; only the k-register mask is updated. This is an AVX-512F instruction that operates on 64-bit elements.", "pseudocode": "for i = 0 to 7:\n element_result = zmm2[i*64+63:i*64] & zmm3[i*64+63:i*64]\n k1[i] = (element_result != 0) ? 1 : 0", "example": "VPTESTMQ k1, zmm2, zmm3/m512"} {"mnemonic": "monitorx", "architecture": "x86", "full_name": "Monitor Extended", "summary": "Sets up a monitor address (AMD extension).", "syntax": "MONITORX", "encoding": {"format": "AMD", "hex_opcode": "0F 01 FA", "visual_parts": [], "binary_pattern": "0F | 01 | FA", "bit_positions": "+0 | +1 | +2"}, "extension": "AMD", "operands": [], "description": "Sets up a monitor address and optional extensions for memory monitoring (AMD-specific extension). The instruction uses the address in EAX (or RAX in 64-bit mode) as the monitor target, with optional parameters in ECX (monitor extensions/timeout) and EDX (optional threshold). This instruction primes the CPU's monitoring hardware for use with MWAITX and does not modify any arithmetic flags. MONITORX is a privileged instruction available on AMD Zen and later processors.", "pseudocode": "monitor_address ← EAX\nmonitor_extensions ← ECX\nmonitor_threshold ← EDX", "example": "MONITORX"} {"mnemonic": "mwaitx", "architecture": "x86", "full_name": "Monitor Wait Extended", "summary": "Waits for a write to monitored address (AMD extension).", "syntax": "MWAITX", "encoding": {"format": "AMD", "hex_opcode": "0F 01 FB", "visual_parts": [], "binary_pattern": "0F | 01 | FB", "bit_positions": "+0 | +1 | +2"}, "extension": "AMD", "operands": [], "description": "Waits for a write to the address set by MONITORX, with optional timeout support (AMD-specific extension). The instruction operates with implicit operands: EAX contains the monitor address, ECX contains extensions/flags, and EDX contains a timeout value in clock cycles (if ECX[1] is set for timeout mode). The instruction is interruptible and will exit on an interrupt, cache line write to the monitored address, or timeout expiration. No arithmetic flags are modified; this is a privileged instruction available on AMD Zen and later processors.", "pseudocode": "while (memory[monitor_address] has not been written) {\n if (ECX[1] == 1 && timeout_expired(EDX)) break\n if (interrupt_pending()) break\n wait()\n}", "example": "MWAITX"} {"mnemonic": "subss", "architecture": "x86", "full_name": "Subtract Scalar Single-Precision", "summary": "Subtracts the low single-precision floating-point value.", "syntax": "SUBSS xmm1, xmm2/m32", "encoding": {"format": "SSE", "hex_opcode": "F3 0F 5C", "visual_parts": [], "binary_pattern": "F3 | 0F | 5C", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m32", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Subtracts the low 32-bit single-precision floating-point value in the source from the destination XMM register, following IEEE 754 semantics. The high 96 bits of the destination XMM register are left unchanged. The result may raise floating-point exceptions (invalid operation, overflow, underflow, inexact) but does not modify the general-purpose arithmetic flags (OF, SF, ZF, AF, CF, PF). This is an SSE instruction available in 32-bit and 64-bit modes.", "pseudocode": "xmm1[31:0] ← xmm1[31:0] - src[31:0] (IEEE 754 single-precision)\nxmm1[127:32] ← unchanged\nFP_exceptions may be raised", "example": "SUBSS xmm1, xmm2/m32"} {"mnemonic": "subsd", "architecture": "x86", "full_name": "Subtract Scalar Double-Precision", "summary": "Subtracts the low double-precision floating-point value.", "syntax": "SUBSD xmm1, xmm2/m64", "encoding": {"format": "SSE2", "hex_opcode": "F2 0F 5C", "visual_parts": [], "binary_pattern": "F2 | 0F | 5C", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m64", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Subtracts the low 64-bit double-precision floating-point value in the source from the destination XMM register, following IEEE 754 semantics. The high 64 bits of the destination XMM register are left unchanged. The result may raise floating-point exceptions (invalid operation, overflow, underflow, inexact) but does not modify the general-purpose arithmetic flags (OF, SF, ZF, AF, CF, PF). This is an SSE2 instruction available in 32-bit and 64-bit modes.", "pseudocode": "xmm1[63:0] ← xmm1[63:0] - src[63:0] (IEEE 754 double-precision)\nxmm1[127:64] ← unchanged\nFP_exceptions may be raised", "example": "SUBSD xmm1, xmm2/m64"} {"mnemonic": "mulss", "architecture": "x86", "full_name": "Multiply Scalar Single-Precision", "summary": "Multiplies the low single-precision floating-point value.", "syntax": "MULSS xmm1, xmm2/m32", "encoding": {"format": "SSE", "hex_opcode": "F3 0F 59", "visual_parts": [], "binary_pattern": "F3 | 0F | 59", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m32", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Multiplies the low 32-bit single-precision floating-point value in the source by the destination XMM register, following IEEE 754 semantics. The high 96 bits of the destination XMM register are left unchanged. The result may raise floating-point exceptions (invalid operation, overflow, underflow, inexact) but does not modify the general-purpose arithmetic flags (OF, SF, ZF, AF, CF, PF). This is an SSE instruction available in 32-bit and 64-bit modes.", "pseudocode": "xmm1[31:0] ← xmm1[31:0] * src[31:0] (IEEE 754 single-precision)\nxmm1[127:32] ← unchanged\nFP_exceptions may be raised", "example": "MULSS xmm1, xmm2/m32"} {"mnemonic": "mulsd", "architecture": "x86", "full_name": "Multiply Scalar Double-Precision", "summary": "Multiplies the low double-precision floating-point value.", "syntax": "MULSD xmm1, xmm2/m64", "encoding": {"format": "SSE2", "hex_opcode": "F2 0F 59", "visual_parts": [], "binary_pattern": "F2 | 0F | 59", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m64", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Multiplies the low 64-bit double-precision floating-point value in xmm1 by the low 64-bit value from xmm2/m64, storing the result in xmm1; the high 64-bit value in xmm1 is preserved. This operation follows IEEE 754 semantics for floating-point multiplication and does not modify EFLAGS.", "pseudocode": "xmm1[0:63] ← FP64_multiply(xmm1[0:63], xmm2/m64[0:63])\nxmm1[64:127] ← unchanged", "example": "MULSD xmm1, xmm2/m64"} {"mnemonic": "divss", "architecture": "x86", "full_name": "Divide Scalar Single-Precision", "summary": "Divides the low single-precision floating-point value.", "syntax": "DIVSS xmm1, xmm2/m32", "encoding": {"format": "SSE", "hex_opcode": "F3 0F 5E", "visual_parts": [], "binary_pattern": "F3 | 0F | 5E", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m32", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Divides the low 32-bit single-precision floating-point value in xmm1 by the low 32-bit value from xmm2/m32, storing the result in xmm1; the upper 96 bits of xmm1 are preserved. This operation follows IEEE 754 semantics and does not modify EFLAGS; division by zero produces infinity or NaN per IEEE rules.", "pseudocode": "xmm1[0:31] ← FP32_divide(xmm1[0:31], xmm2/m32[0:31])\nxmm1[32:127] ← unchanged", "example": "DIVSS xmm1, xmm2/m32"} {"mnemonic": "divsd", "architecture": "x86", "full_name": "Divide Scalar Double-Precision", "summary": "Divides the low double-precision floating-point value.", "syntax": "DIVSD xmm1, xmm2/m64", "encoding": {"format": "SSE2", "hex_opcode": "F2 0F 5E", "visual_parts": [], "binary_pattern": "F2 | 0F | 5E", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m64", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Divides the low 64-bit double-precision floating-point value in xmm1 by the low 64-bit value from xmm2/m64, storing the result in xmm1; the high 64-bit value in xmm1 is preserved. This operation follows IEEE 754 semantics and does not modify EFLAGS; division by zero produces infinity or NaN per IEEE rules.", "pseudocode": "xmm1[0:63] ← FP64_divide(xmm1[0:63], xmm2/m64[0:63])\nxmm1[64:127] ← unchanged", "example": "DIVSD xmm1, xmm2/m64"} {"mnemonic": "sqrtss", "architecture": "x86", "full_name": "Square Root Scalar Single-Precision", "summary": "Computes square root of the low float.", "syntax": "SQRTSS xmm1, xmm2/m32", "encoding": {"format": "SSE", "hex_opcode": "F3 0F 51", "visual_parts": [], "binary_pattern": "F3 | 0F | 51", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m32", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Computes the square root of the low 32-bit single-precision floating-point value in xmm2/m32 and stores the result in the low 32 bits of xmm1; the upper 96 bits of xmm1 are set to zero. This operation follows IEEE 754 semantics and does not modify EFLAGS; negative operands produce NaN.", "pseudocode": "xmm1[0:31] ← FP32_sqrt(xmm2/m32[0:31])\nxmm1[32:127] ← 0", "example": "SQRTSS xmm1, xmm2/m32"} {"mnemonic": "sqrtsd", "architecture": "x86", "full_name": "Square Root Scalar Double-Precision", "summary": "Computes square root of the low double.", "syntax": "SQRTSD xmm1, xmm2/m64", "encoding": {"format": "SSE2", "hex_opcode": "F2 0F 51", "visual_parts": [], "binary_pattern": "F2 | 0F | 51", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m64", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Computes the square root of the low 64-bit double-precision floating-point value in xmm2/m64 and stores the result in the low 64 bits of xmm1; the high 64 bits of xmm1 are set to zero. This operation follows IEEE 754 semantics and does not modify EFLAGS; negative operands produce NaN.", "pseudocode": "xmm1[0:63] ← FP64_sqrt(xmm2/m64[0:63])\nxmm1[64:127] ← 0", "example": "SQRTSD xmm1, xmm2/m64"} {"mnemonic": "minss", "architecture": "x86", "full_name": "Minimum Scalar Single-Precision", "summary": "Returns the minimum of two low single-precision values.", "syntax": "MINSS xmm1, xmm2/m32", "encoding": {"format": "SSE", "hex_opcode": "F3 0F 5D", "visual_parts": [], "binary_pattern": "F3 | 0F | 5D", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m32", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Returns the minimum of the low 32-bit single-precision floating-point values from xmm1 and xmm2/m32, storing the result in xmm1; the upper 96 bits of xmm1 are preserved. Comparison follows IEEE 754 rules where NaN comparisons return NaN and negative zero is less than positive zero; EFLAGS are not modified.", "pseudocode": "xmm1[0:31] ← FP32_min(xmm1[0:31], xmm2/m32[0:31])\nxmm1[32:127] ← unchanged", "example": "MINSS xmm1, xmm2/m32"} {"mnemonic": "minsd", "architecture": "x86", "full_name": "Minimum Scalar Double-Precision", "summary": "Returns the minimum of two low double-precision values.", "syntax": "MINSD xmm1, xmm2/m64", "encoding": {"format": "SSE2", "hex_opcode": "F2 0F 5D", "visual_parts": [], "binary_pattern": "F2 | 0F | 5D", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m64", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Returns the minimum of the low 64-bit double-precision floating-point values from xmm1 and xmm2/m64, storing the result in xmm1; the high 64 bits of xmm1 are preserved. Comparison follows IEEE 754 rules where NaN comparisons return NaN and negative zero is less than positive zero; EFLAGS are not modified.", "pseudocode": "xmm1[0:63] ← FP64_min(xmm1[0:63], xmm2/m64[0:63])\nxmm1[64:127] ← unchanged", "example": "MINSD xmm1, xmm2/m64"} {"mnemonic": "maxss", "architecture": "x86", "full_name": "Maximum Scalar Single-Precision", "summary": "Returns the maximum of two low single-precision values.", "syntax": "MAXSS xmm1, xmm2/m32", "encoding": {"format": "SSE", "hex_opcode": "F3 0F 5F", "visual_parts": [], "binary_pattern": "F3 | 0F | 5F", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m32", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Returns the maximum of the low 32-bit single-precision floating-point values from xmm1 and xmm2/m32, storing the result in xmm1; the upper 96 bits of xmm1 are preserved. Comparison follows IEEE 754 rules where NaN comparisons return NaN and positive zero is greater than negative zero; EFLAGS are not modified.", "pseudocode": "xmm1[0:31] ← FP32_max(xmm1[0:31], xmm2/m32[0:31])\nxmm1[32:127] ← unchanged", "example": "MAXSS xmm1, xmm2/m32"} {"mnemonic": "maxsd", "architecture": "x86", "full_name": "Maximum Scalar Double-Precision", "summary": "Returns the maximum of two low double-precision values.", "syntax": "MAXSD xmm1, xmm2/m64", "encoding": {"format": "SSE2", "hex_opcode": "F2 0F 5F", "visual_parts": [], "binary_pattern": "F2 | 0F | 5F", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m64", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Compares the low 64-bit double-precision floating-point values in the destination and source operands, returns the maximum value, and stores it in the low 64 bits of the destination XMM register while leaving the high 64 bits unchanged. No CPU flags are affected. This instruction operates only on the scalar (low) element; the upper 64 bits of xmm1 are preserved.", "pseudocode": "xmm1[0:63] ← max(xmm1[0:63], src[0:63]); xmm1[64:127] ← xmm1[64:127];", "example": "MAXSD xmm1, xmm2/m64"} {"mnemonic": "cmpss", "architecture": "x86", "full_name": "Compare Scalar Single-Precision", "summary": "Compares low single-precision values and returns mask.", "syntax": "CMPSS xmm1, xmm2/m32, imm8", "encoding": {"format": "SSE", "hex_opcode": "F3 0F C2", "visual_parts": [], "binary_pattern": "F3 | 0F | C2", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m32", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Performs a scalar single-precision floating-point comparison between the low 32-bit elements of xmm1 and xmm2/m32 according to the condition specified by the immediate byte, storing a mask (all 1s or all 0s) in the low 32 bits of xmm1 while the upper 96 bits are preserved. No CPU flags are modified. The comparison predicate is encoded in imm8[2:0].", "pseudocode": "condition ← imm8[2:0]; result ← compare(xmm1[0:31], src[0:31], condition); xmm1[0:31] ← result ? 0xFFFFFFFF : 0; xmm1[32:127] ← xmm1[32:127];", "example": "CMPSS xmm1, xmm2/m32, 3"} {"mnemonic": "cmpsd", "architecture": "x86", "full_name": "Compare Scalar Double-Precision", "summary": "Compares low double-precision values and returns mask.", "syntax": "CMPSD xmm1, xmm2/m64, imm8", "encoding": {"format": "SSE2", "hex_opcode": "F2 0F C2", "visual_parts": [], "binary_pattern": "F2 | 0F | C2", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m64", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Performs a scalar double-precision floating-point comparison between the low 64-bit elements of xmm1 and xmm2/m64 according to the condition specified by the immediate byte, storing a mask (all 1s or all 0s) in the low 64 bits of xmm1 while the upper 64 bits are preserved. No CPU flags are modified. The comparison predicate is encoded in imm8[2:0].", "pseudocode": "condition ← imm8[2:0]; result ← compare(xmm1[0:63], src[0:63], condition); xmm1[0:63] ← result ? 0xFFFFFFFFFFFFFFFF : 0; xmm1[64:127] ← xmm1[64:127];", "example": "CMPSD xmm1, xmm2/m64, 3"} {"mnemonic": "rcpss", "architecture": "x86", "full_name": "Reciprocal Scalar Single-Precision", "summary": "Computes approximate reciprocal (1/x) of low float.", "syntax": "RCPSS xmm1, xmm2/m32", "encoding": {"format": "SSE", "hex_opcode": "F3 0F 53", "visual_parts": [], "binary_pattern": "F3 | 0F | 53", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m32", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Computes an approximate reciprocal (1/x) of the low 32-bit single-precision floating-point value in the source operand and stores the result in the low 32 bits of the destination XMM register, while preserving the upper 96 bits of xmm1. No CPU flags are affected. The result has a maximum relative error of approximately 1.5×2^-12.", "pseudocode": "xmm1[0:31] ← 1.0 / src[0:31]; xmm1[32:127] ← xmm1[32:127];", "example": "RCPSS xmm1, xmm2/m32"} {"mnemonic": "rsqrtss", "architecture": "x86", "full_name": "Reciprocal Square Root Scalar Single-Precision", "summary": "Computes approximate reciprocal sqrt (1/sqrt(x)) of low float.", "syntax": "RSQRTSS xmm1, xmm2/m32", "encoding": {"format": "SSE", "hex_opcode": "F3 0F 52", "visual_parts": [], "binary_pattern": "F3 | 0F | 52", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m32", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Computes an approximate reciprocal square root (1/√x) of the low 32-bit single-precision floating-point value in the source operand and stores the result in the low 32 bits of the destination XMM register, while preserving the upper 96 bits of xmm1. No CPU flags are affected. The result has a maximum relative error of approximately 1.5×2^-12.", "pseudocode": "xmm1[0:31] ← 1.0 / sqrt(src[0:31]); xmm1[32:127] ← xmm1[32:127];", "example": "RSQRTSS xmm1, xmm2/m32"} {"mnemonic": "roundss", "architecture": "x86", "full_name": "Round Scalar Single-Precision", "summary": "Rounds low float according to immediate mode.", "syntax": "ROUNDSS xmm1, xmm2/m32, imm8", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 3A 0A", "visual_parts": [], "binary_pattern": "66 | 0F | 3A | 0A", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m32", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Rounds the low 32-bit single-precision floating-point value in xmm2/m32 according to the rounding mode specified in imm8 and stores the rounded result in the low 32 bits of xmm1, while preserving the upper 96 bits of xmm1. No CPU flags are affected. Rounding mode is selected via imm8[1:0]; bit 2 can suppress inexact exceptions.", "pseudocode": "mode ← imm8[1:0]; precision_exception_suppress ← imm8[2]; xmm1[0:31] ← round(src[0:31], mode, precision_exception_suppress); xmm1[32:127] ← xmm1[32:127];", "example": "ROUNDSS xmm1, xmm2/m32, 3"} {"mnemonic": "roundsd", "architecture": "x86", "full_name": "Round Scalar Double-Precision", "summary": "Rounds low double according to immediate mode.", "syntax": "ROUNDSD xmm1, xmm2/m64, imm8", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 3A 0B", "visual_parts": [], "binary_pattern": "66 | 0F | 3A | 0B", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m64", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Rounds the low 64-bit double-precision floating-point value in xmm2/m64 according to the rounding mode specified in imm8 and stores the rounded result in the low 64 bits of xmm1, while preserving the upper 64 bits of xmm1. No CPU flags are affected. Rounding mode is selected via imm8[1:0]; bit 2 can suppress inexact exceptions.", "pseudocode": "mode ← imm8[1:0]; precision_exception_suppress ← imm8[2]; xmm1[0:63] ← round(src[0:63], mode, precision_exception_suppress); xmm1[64:127] ← xmm1[64:127];", "example": "ROUNDSD xmm1, xmm2/m64, 3"} {"mnemonic": "cvttps2pi", "architecture": "x86", "full_name": "Convert with Truncation Packed Single to Packed Integer (MMX)", "summary": "Converts packed floats to packed MMX integers (Truncate).", "syntax": "CVTTPS2PI mm, xmm/m64", "encoding": {"format": "SSE", "hex_opcode": "NP 0F 2C /r", "visual_parts": [], "binary_pattern": "0F | 2C", "bit_positions": "+0 | +1"}, "extension": "SSE", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "xmm/m64", "desc": "128-bit XMM register or 64-bit memory"}], "description": "Converts the two low single-precision floating-point values (32 bits each) from an XMM register or 64-bit memory location to two packed 32-bit signed integers via truncation, storing the result in an MMX register. The upper two single-precision values in the XMM operand are ignored. No CPU flags are affected; the instruction operates on the MMX register state.", "pseudocode": "mm[0:31] ← truncate_to_int32(src[0:31]); mm[32:63] ← truncate_to_int32(src[32:63]);", "example": "CVTTPS2PI mm, xmm1"} {"mnemonic": "cvtps2pd", "architecture": "x86", "full_name": "Convert Packed Single to Packed Double", "summary": "Converts lower two floats to doubles.", "syntax": "CVTPS2PD xmm1, xmm2/m64", "encoding": {"format": "SSE2", "hex_opcode": "NP 0F 5A /r", "visual_parts": [], "binary_pattern": "0F | 5A", "bit_positions": "+0 | +1"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m64", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Converts the lower two packed single-precision floats (32-bit) to two packed double-precision floats (64-bit), storing the result in the destination XMM register. The conversion rounds according to the MXCSR rounding mode; #IA (invalid operation) and #D (denormal) exceptions may be signaled. No flags are affected.", "pseudocode": "dest[0:63] ← convert_sp_to_dp(src[0:31]);\ndest[64:127] ← convert_sp_to_dp(src[32:63]);", "example": "CVTPS2PD xmm1, xmm2/m64"} {"mnemonic": "cvtpd2ps", "architecture": "x86", "full_name": "Convert Packed Double to Packed Single", "summary": "Converts two doubles to two floats.", "syntax": "CVTPD2PS xmm1, xmm2/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 5A", "visual_parts": [], "binary_pattern": "66 | 0F | 5A", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Converts two packed double-precision floats (64-bit each) to two packed single-precision floats (32-bit each), storing the result in the lower 64 bits of the destination XMM register and zeroing the upper 64 bits. The conversion rounds according to the MXCSR rounding mode; #IA and #O (overflow) exceptions may be signaled. No flags are affected.", "pseudocode": "dest[0:31] ← convert_dp_to_sp(src[0:63]);\ndest[32:63] ← convert_dp_to_sp(src[64:127]);\ndest[64:127] ← 0;", "example": "CVTPD2PS xmm1, xmm2/m128"} {"mnemonic": "jo", "architecture": "x86", "full_name": "Jump if Overflow", "summary": "Jump near if overflow flag is 1.", "syntax": "JO rel", "encoding": {"format": "Legacy", "hex_opcode": "70", "visual_parts": [], "binary_pattern": "70", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "rel", "desc": "Relative branch offset"}], "description": "Performs a near jump to the target address if the overflow flag (OF) is set (1). The jump is relative to the instruction pointer; this is a conditional branch with no effect on CPU flags. Available in all modes (real, protected, 64-bit).", "pseudocode": "if (OF == 1) {\n RIP ← RIP + sign_extend(rel8_or_rel32);\n}", "example": "JO rel"} {"mnemonic": "jno", "architecture": "x86", "full_name": "Jump if Not Overflow", "summary": "Jump near if overflow flag is 0.", "syntax": "JNO rel", "encoding": {"format": "Legacy", "hex_opcode": "71", "visual_parts": [], "binary_pattern": "71", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "rel", "desc": "Relative branch offset"}], "description": "Performs a near jump to the target address if the overflow flag (OF) is clear (0). The jump is relative to the instruction pointer; this is a conditional branch with no effect on CPU flags. Available in all modes (real, protected, 64-bit).", "pseudocode": "if (OF == 0) {\n RIP ← RIP + sign_extend(rel8_or_rel32);\n}", "example": "JNO rel"} {"mnemonic": "js", "architecture": "x86", "full_name": "Jump if Sign", "summary": "Jump near if sign flag is 1 (Negative).", "syntax": "JS rel", "encoding": {"format": "Legacy", "hex_opcode": "78", "visual_parts": [], "binary_pattern": "78", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "rel", "desc": "Relative branch offset"}], "description": "Performs a near jump to the target address if the sign flag (SF) is set (1), indicating a negative result from a prior arithmetic operation. The jump is relative to the instruction pointer; this is a conditional branch with no effect on CPU flags. Available in all modes (real, protected, 64-bit).", "pseudocode": "if (SF == 1) {\n RIP ← RIP + sign_extend(rel8_or_rel32);\n}", "example": "JS rel"} {"mnemonic": "jns", "architecture": "x86", "full_name": "Jump if Not Sign", "summary": "Jump near if sign flag is 0 (Positive).", "syntax": "JNS rel", "encoding": {"format": "Legacy", "hex_opcode": "79", "visual_parts": [], "binary_pattern": "79", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "rel", "desc": "Relative branch offset"}], "description": "Performs a near jump to the target address if the sign flag (SF) is clear (0), indicating a non-negative result from a prior arithmetic operation. The jump is relative to the instruction pointer; this is a conditional branch with no effect on CPU flags. Available in all modes (real, protected, 64-bit).", "pseudocode": "if (SF == 0) {\n RIP ← RIP + sign_extend(rel8_or_rel32);\n}", "example": "JNS rel"} {"mnemonic": "jp", "architecture": "x86", "full_name": "Jump if Parity", "summary": "Jump near if parity flag is 1 (Even parity).", "syntax": "JP rel", "encoding": {"format": "Legacy", "hex_opcode": "7A", "visual_parts": [], "binary_pattern": "7A", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "rel", "desc": "Relative branch offset"}], "description": "Performs a near jump to the target address if the parity flag (PF) is set (1), indicating even parity in the low-order byte of a prior operation result. The jump is relative to the instruction pointer; this is a conditional branch with no effect on CPU flags. Available in all modes (real, protected, 64-bit).", "pseudocode": "if (PF == 1) {\n RIP ← RIP + sign_extend(rel8_or_rel32);\n}", "example": "JP rel"} {"mnemonic": "jnp", "architecture": "x86", "full_name": "Jump if Not Parity", "summary": "Jump near if parity flag is 0 (Odd parity).", "syntax": "JNP rel", "encoding": {"format": "Legacy", "hex_opcode": "7B", "visual_parts": [], "binary_pattern": "7B", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "rel", "desc": "Relative branch offset"}], "description": "Performs a near jump to the target address if the parity flag (PF) is clear (0), indicating odd parity in the low-order byte of a prior operation result. The jump is relative to the instruction pointer; this is a conditional branch with no effect on CPU flags. Available in all modes (real, protected, 64-bit).", "pseudocode": "if (PF == 0) {\n RIP ← RIP + sign_extend(rel8_or_rel32);\n}", "example": "JNP rel"} {"mnemonic": "seto", "architecture": "x86", "full_name": "Set Byte on Overflow", "summary": "Sets byte to 1 if OF=1.", "syntax": "SETO r/m8", "encoding": {"format": "Legacy", "hex_opcode": "0F 90", "visual_parts": [], "binary_pattern": "0F | 90", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m8", "desc": "8-bit register or memory"}], "description": "Sets the destination byte to 1 if the Overflow Flag (OF) is set, otherwise sets it to 0. This instruction does not modify any flags. Available in 32-bit and 64-bit modes; commonly used after arithmetic operations to test for signed overflow.", "pseudocode": "dest ← (OF == 1) ? 1 : 0;", "example": "SETO bl"} {"mnemonic": "setno", "architecture": "x86", "full_name": "Set Byte on Not Overflow", "summary": "Sets byte to 1 if OF=0.", "syntax": "SETNO r/m8", "encoding": {"format": "Legacy", "hex_opcode": "0F 91", "visual_parts": [], "binary_pattern": "0F | 91", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m8", "desc": "8-bit register or memory"}], "description": "Sets the destination byte to 1 if the Overflow Flag (OF) is clear, otherwise sets it to 0. This instruction does not modify any flags. Available in 32-bit and 64-bit modes; used to test when no signed overflow has occurred.", "pseudocode": "dest ← (OF == 0) ? 1 : 0;", "example": "SETNO bl"} {"mnemonic": "setz", "architecture": "x86", "full_name": "Set Byte on Zero", "summary": "Sets byte to 1 if ZF=1.", "syntax": "SETZ r/m8", "encoding": {"format": "Legacy", "hex_opcode": "0F 94", "visual_parts": [], "binary_pattern": "0F | 94", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m8", "desc": "8-bit register or memory"}], "description": "Sets the destination byte to 1 if the Zero Flag (ZF) is set, otherwise sets it to 0. This instruction does not modify any flags. Available in 32-bit and 64-bit modes; commonly used after comparisons or arithmetic to test if the result was zero.", "pseudocode": "dest ← (ZF == 1) ? 1 : 0;", "example": "SETZ bl"} {"mnemonic": "setnz", "architecture": "x86", "full_name": "Set Byte on Not Zero", "summary": "Sets byte to 1 if ZF=0.", "syntax": "SETNZ r/m8", "encoding": {"format": "Legacy", "hex_opcode": "0F 95", "visual_parts": [], "binary_pattern": "0F | 95", "bit_positions": "+0 | +1"}, "extension": "Base", "operands": [{"name": "dest", "type": "r/m8", "desc": "8-bit register or memory"}], "description": "Sets the destination byte to 1 if the Zero Flag (ZF) is clear, otherwise sets it to 0. This instruction does not modify any flags. Available in 32-bit and 64-bit modes; commonly used after comparisons or arithmetic to test if the result was non-zero.", "pseudocode": "dest ← (ZF == 0) ? 1 : 0;", "example": "SETNZ bl"} {"mnemonic": "cmovg", "architecture": "x86", "full_name": "Conditional Move Greater", "summary": "Move if ZF=0 and SF=OF.", "syntax": "CMOVG r, r/m", "encoding": {"format": "Legacy", "hex_opcode": "0F 4F", "visual_parts": [], "binary_pattern": "0F | 4F", "bit_positions": "+0 | +1"}, "extension": "CMOV", "operands": [{"name": "dest", "type": "r", "desc": "General-purpose register"}, {"name": "src", "type": "r/m", "desc": "Register or memory operand"}], "description": "Conditionally moves the source operand to the destination register if the signed greater-than condition is true (ZF=0 and SF=OF). No flags are modified by this instruction. The operand size can be 16, 32, or 64 bits (determined by REX.W and operand-size prefix). Requires the CMOV extension; available in 32-bit and 64-bit modes.", "pseudocode": "if (ZF == 0 && SF == OF) dest ← src;", "example": "CMOVG rax, rbx"} {"mnemonic": "cmovge", "architecture": "x86", "full_name": "Conditional Move Greater or Equal", "summary": "Move if SF=OF.", "syntax": "CMOVGE r, r/m", "encoding": {"format": "Legacy", "hex_opcode": "0F 4D", "visual_parts": [], "binary_pattern": "0F | 4D", "bit_positions": "+0 | +1"}, "extension": "CMOV", "operands": [{"name": "dest", "type": "r", "desc": "General-purpose register"}, {"name": "src", "type": "r/m", "desc": "Register or memory operand"}], "description": "Conditionally moves the source operand to the destination register if the signed greater-than-or-equal condition is true (SF=OF). No flags are modified by this instruction. The operand size can be 16, 32, or 64 bits (determined by REX.W and operand-size prefix). Requires the CMOV extension; available in 32-bit and 64-bit modes.", "pseudocode": "if (SF == OF) dest ← src;", "example": "CMOVGE rax, rbx"} {"mnemonic": "cmovl", "architecture": "x86", "full_name": "Conditional Move Less", "summary": "Move if SF!=OF.", "syntax": "CMOVL r, r/m", "encoding": {"format": "Legacy", "hex_opcode": "0F 4C", "visual_parts": [], "binary_pattern": "0F | 4C", "bit_positions": "+0 | +1"}, "extension": "CMOV", "operands": [{"name": "dest", "type": "r", "desc": "General-purpose register"}, {"name": "src", "type": "r/m", "desc": "Register or memory operand"}], "description": "Conditionally moves the source operand to the destination register if the signed less-than condition is true (SF≠OF). No flags are modified by this instruction. The operand size can be 16, 32, or 64 bits (determined by REX.W and operand-size prefix). Requires the CMOV extension; available in 32-bit and 64-bit modes.", "pseudocode": "if (SF != OF) dest ← src;", "example": "CMOVL rax, rbx"} {"mnemonic": "cmovle", "architecture": "x86", "full_name": "Conditional Move Less or Equal", "summary": "Move if ZF=1 or SF!=OF.", "syntax": "CMOVLE r, r/m", "encoding": {"format": "Legacy", "hex_opcode": "0F 4E", "visual_parts": [], "binary_pattern": "0F | 4E", "bit_positions": "+0 | +1"}, "extension": "CMOV", "operands": [{"name": "dest", "type": "r", "desc": "General-purpose register"}, {"name": "src", "type": "r/m", "desc": "Register or memory operand"}], "description": "Conditionally moves the source operand to the destination register if the signed less-than-or-equal condition is true (ZF=1 or SF≠OF). No flags are modified by this instruction. The operand size can be 16, 32, or 64 bits (determined by REX.W and operand-size prefix). Requires the CMOV extension; available in 32-bit and 64-bit modes.", "pseudocode": "if (ZF == 1 || SF != OF) dest ← src;", "example": "CMOVLE rax, rbx"} {"mnemonic": "cmovz", "architecture": "x86", "full_name": "Conditional Move Zero", "summary": "Move if ZF=1.", "syntax": "CMOVZ r, r/m", "encoding": {"format": "Legacy", "hex_opcode": "0F 44", "visual_parts": [], "binary_pattern": "0F | 44", "bit_positions": "+0 | +1"}, "extension": "CMOV", "operands": [{"name": "dest", "type": "r", "desc": "General-purpose register"}, {"name": "src", "type": "r/m", "desc": "Register or memory operand"}], "description": "Conditionally moves the source operand to the destination register if the Zero Flag (ZF) is set to 1, otherwise the destination register remains unchanged. This instruction operates on 16/32/64-bit operands and does not modify any CPU flags. It is available in protected mode and 64-bit mode on processors supporting the CMOV extension.", "pseudocode": "if (ZF == 1) { dest ← src; }", "example": "CMOVZ rax, rbx"} {"mnemonic": "cmovnz", "architecture": "x86", "full_name": "Conditional Move Not Zero", "summary": "Move if ZF=0.", "syntax": "CMOVNZ r, r/m", "encoding": {"format": "Legacy", "hex_opcode": "0F 45", "visual_parts": [], "binary_pattern": "0F | 45", "bit_positions": "+0 | +1"}, "extension": "CMOV", "operands": [{"name": "dest", "type": "r", "desc": "General-purpose register"}, {"name": "src", "type": "r/m", "desc": "Register or memory operand"}], "description": "Conditionally moves the source operand to the destination register if the Zero Flag (ZF) is cleared to 0 (i.e., result was non-zero), otherwise the destination register remains unchanged. This instruction operates on 16/32/64-bit operands and does not modify any CPU flags. It is available in protected mode and 64-bit mode on processors supporting the CMOV extension.", "pseudocode": "if (ZF == 0) { dest ← src; }", "example": "CMOVNZ rax, rbx"} {"mnemonic": "paddusw", "architecture": "x86", "full_name": "Packed Add Unsigned Saturation Word", "summary": "Adds 16-bit words with unsigned saturation.", "syntax": "PADDUSW xmm1, xmm2/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F DD", "visual_parts": [], "binary_pattern": "66 | 0F | DD", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Adds eight pairs of 16-bit unsigned integers in parallel from the destination and source operands, with unsigned saturation applied to each pair independently. The result is stored in the destination XMM register; overflow is clamped to 0xFFFF and does not set CPU flags. Available in SSE2 and later extensions.", "pseudocode": "for (i = 0; i < 8; i++) { result[i] = UNSIGNED_SAT_16(dest[i] + src[i]); } dest ← result;", "example": "PADDUSW xmm1, xmm2/m128"} {"mnemonic": "paddsw", "architecture": "x86", "full_name": "Packed Add Signed Saturation Word", "summary": "Adds 16-bit words with signed saturation.", "syntax": "PADDSW xmm1, xmm2/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F ED", "visual_parts": [], "binary_pattern": "66 | 0F | ED", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Adds eight pairs of 16-bit signed integers in parallel from the destination and source operands, with signed saturation applied to each pair independently. The result is stored in the destination XMM register; overflow is clamped to 0x7FFF and underflow to 0x8000, and no CPU flags are modified. Available in SSE2 and later extensions.", "pseudocode": "for (i = 0; i < 8; i++) { result[i] = SIGNED_SAT_16(dest[i] + src[i]); } dest ← result;", "example": "PADDSW xmm1, xmm2/m128"} {"mnemonic": "psubusw", "architecture": "x86", "full_name": "Packed Subtract Unsigned Saturation Word", "summary": "Subtracts 16-bit words with unsigned saturation.", "syntax": "PSUBUSW xmm1, xmm2/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F D9", "visual_parts": [], "binary_pattern": "66 | 0F | D9", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Subtracts eight pairs of 16-bit unsigned integers in parallel; the source is subtracted from the destination with unsigned saturation applied to each pair independently. The result is stored in the destination XMM register; underflow is clamped to 0x0000 and does not set CPU flags. Available in SSE2 and later extensions.", "pseudocode": "for (i = 0; i < 8; i++) { result[i] = UNSIGNED_SAT_16(dest[i] - src[i]); } dest ← result;", "example": "PSUBUSW xmm1, xmm2/m128"} {"mnemonic": "psubsw", "architecture": "x86", "full_name": "Packed Subtract Signed Saturation Word", "summary": "Subtracts 16-bit words with signed saturation.", "syntax": "PSUBSW xmm1, xmm2/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F E9", "visual_parts": [], "binary_pattern": "66 | 0F | E9", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Subtracts eight pairs of 16-bit signed integers in parallel; the source is subtracted from the destination with signed saturation applied to each pair independently. The result is stored in the destination XMM register; overflow is clamped to 0x7FFF and underflow to 0x8000, and no CPU flags are modified. Available in SSE2 and later extensions.", "pseudocode": "for (i = 0; i < 8; i++) { result[i] = SIGNED_SAT_16(dest[i] - src[i]); } dest ← result;", "example": "PSUBSW xmm1, xmm2/m128"} {"mnemonic": "pmullw", "architecture": "x86", "full_name": "Packed Multiply Low Word", "summary": "Multiplies 16-bit words and stores low 16-bit result.", "syntax": "PMULLW xmm1, xmm2/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F D5", "visual_parts": [], "binary_pattern": "66 | 0F | D5", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Multiplies eight pairs of 16-bit signed integers from the destination and source operands in parallel; the low 16 bits of each 32-bit product are stored in the destination XMM register while the high 16 bits are discarded. No CPU flags are modified, and this instruction does not generate saturation. Available in SSE2 and later extensions.", "pseudocode": "for (i = 0; i < 8; i++) { product = (int32_t)dest[i] * (int32_t)src[i]; result[i] = (int16_t)(product & 0xFFFF); } dest ← result;", "example": "PMULLW xmm1, xmm2/m128"} {"mnemonic": "pmaddwd", "architecture": "x86", "full_name": "Packed Multiply and Add Word to Doubleword", "summary": "Multiplies words, adds adjacent pairs to doublewords.", "syntax": "PMADDWD xmm1, xmm2/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F F5", "visual_parts": [], "binary_pattern": "66 | 0F | F5", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Multiplies four pairs of 16-bit signed integers from the destination and source operands in parallel; adjacent pairs of 32-bit products are then summed with signed saturation, and the four 32-bit saturated results are stored in the destination XMM register. No CPU flags are modified. Available in SSE2 and later extensions.", "pseudocode": "for (i = 0; i < 4; i++) { prod0 = (int32_t)dest[2*i] * (int32_t)src[2*i]; prod1 = (int32_t)dest[2*i+1] * (int32_t)src[2*i+1]; result[i] = SIGNED_SAT_32(prod0 + prod1); } dest ← result;", "example": "PMADDWD xmm1, xmm2/m128"} {"mnemonic": "pcmpgtb", "architecture": "x86", "full_name": "Packed Compare Greater Than Byte", "summary": "Compares bytes for greater than (signed).", "syntax": "PCMPGTB xmm1, xmm2/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 64", "visual_parts": [], "binary_pattern": "66 | 0F | 64", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Compares packed signed bytes in xmm1 against xmm2/m128, setting each byte in xmm1 to 0xFF if the comparison is true or 0x00 if false. This is a SIMD integer comparison with no CPU flags affected; the result mask is stored directly in the destination XMM register.", "pseudocode": "for i = 0 to 15:\n if xmm1[byte_i] > xmm2/m128[byte_i] (signed):\n xmm1[byte_i] ← 0xFF\n else:\n xmm1[byte_i] ← 0x00", "example": "PCMPGTB xmm1, xmm2/m128"} {"mnemonic": "pcmpgtw", "architecture": "x86", "full_name": "Packed Compare Greater Than Word", "summary": "Compares words for greater than (signed).", "syntax": "PCMPGTW xmm1, xmm2/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 65", "visual_parts": [], "binary_pattern": "66 | 0F | 65", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Compares packed signed words in xmm1 against xmm2/m128, setting each word in xmm1 to 0xFFFF if the comparison is true or 0x0000 if false. This is a SIMD integer comparison with no CPU flags affected; the result mask is stored directly in the destination XMM register.", "pseudocode": "for i = 0 to 7:\n if xmm1[word_i] > xmm2/m128[word_i] (signed):\n xmm1[word_i] ← 0xFFFF\n else:\n xmm1[word_i] ← 0x0000", "example": "PCMPGTW xmm1, xmm2/m128"} {"mnemonic": "pcmpgtd", "architecture": "x86", "full_name": "Packed Compare Greater Than Doubleword", "summary": "Compares doublewords for greater than (signed).", "syntax": "PCMPGTD xmm1, xmm2/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 66", "visual_parts": [], "binary_pattern": "66 | 0F | 66", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Compares packed signed doublewords in xmm1 against xmm2/m128, setting each doubleword in xmm1 to 0xFFFFFFFF if the comparison is true or 0x00000000 if false. This is a SIMD integer comparison with no CPU flags affected; the result mask is stored directly in the destination XMM register.", "pseudocode": "for i = 0 to 3:\n if xmm1[dword_i] > xmm2/m128[dword_i] (signed):\n xmm1[dword_i] ← 0xFFFFFFFF\n else:\n xmm1[dword_i] ← 0x00000000", "example": "PCMPGTD xmm1, xmm2/m128"} {"mnemonic": "pinsrw", "architecture": "x86", "full_name": "Packed Insert Word", "summary": "Inserts a word from integer register into XMM.", "syntax": "PINSRW xmm1, r32/m16, imm8", "encoding": {"format": "SSE", "hex_opcode": "66 0F C4", "visual_parts": [], "binary_pattern": "66 | 0F | C4", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "r32/m16", "desc": "General-purpose register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Inserts a 16-bit word from a general-purpose register or memory into an XMM register at the position specified by an 8-bit index. The low 16 bits of the source are extracted; other bits in the destination XMM register remain unchanged. No CPU flags are affected.", "pseudocode": "index ← imm8 & 0x7\nword_value ← (r32/m16) & 0xFFFF\nxmm1[word_index * 16 : word_index * 16 + 15] ← word_value", "example": "PINSRW xmm1, r32/m16, 3"} {"mnemonic": "pextrw", "architecture": "x86", "full_name": "Packed Extract Word", "summary": "Extracts a word from XMM to integer register.", "syntax": "PEXTRW r32, xmm1, imm8", "encoding": {"format": "SSE", "hex_opcode": "66 0F C5", "visual_parts": [], "binary_pattern": "66 | 0F | C5", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src1", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Extracts a 16-bit word from an XMM register at the position specified by an 8-bit index and zero-extends it into a 32-bit general-purpose register. The upper 16 bits of the destination register are zeroed. No CPU flags are affected.", "pseudocode": "index ← imm8 & 0x7\nword_value ← xmm1[word_index * 16 : word_index * 16 + 15]\nr32 ← zero_extend(word_value, 32)", "example": "PEXTRW eax, xmm1, 3"} {"mnemonic": "pshuflw", "architecture": "x86", "full_name": "Packed Shuffle Low Words", "summary": "Shuffles the low 4 words of XMM.", "syntax": "PSHUFLW xmm1, xmm2/m128, imm8", "encoding": {"format": "SSE2", "hex_opcode": "F2 0F 70", "visual_parts": [], "binary_pattern": "F2 | 0F | 70", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Shuffles the low 4 words of an XMM register using an 8-bit immediate that specifies the source indices for each destination word; the high 4 words are unchanged. This is a data permutation with no CPU flags affected.", "pseudocode": "order ← imm8\nfor i = 0 to 3:\n src_index ← (order >> (i * 2)) & 0x3\n xmm1[word_i] ← (xmm2/m128)[word_src_index]\nfor i = 4 to 7:\n xmm1[word_i] ← (xmm2/m128)[word_i]", "example": "PSHUFLW xmm1, xmm2/m128, 3"} {"mnemonic": "pshufhw", "architecture": "x86", "full_name": "Packed Shuffle High Words", "summary": "Shuffles the high 4 words of XMM.", "syntax": "PSHUFHW xmm1, xmm2/m128, imm8", "encoding": {"format": "SSE2", "hex_opcode": "F3 0F 70", "visual_parts": [], "binary_pattern": "F3 | 0F | 70", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Shuffles the high 4 words of an XMM register using an 8-bit immediate that specifies the source indices for each destination word; the low 4 words are unchanged. This is a data permutation with no CPU flags affected.", "pseudocode": "order ← imm8\nfor i = 0 to 3:\n xmm1[word_i] ← (xmm2/m128)[word_i]\nfor i = 4 to 7:\n src_index ← (order >> ((i - 4) * 2)) & 0x3\n xmm1[word_i] ← (xmm2/m128)[word_(4 + src_index)]", "example": "PSHUFHW xmm1, xmm2/m128, 3"} {"mnemonic": "movntq", "architecture": "x86", "full_name": "Move Non-Temporal Quadword", "summary": "Stores 64-bit MMX data bypassing cache.", "syntax": "MOVNTQ m64, mm", "encoding": {"format": "SSE", "hex_opcode": "NP 0F E7 /r", "visual_parts": [], "binary_pattern": "0F | E7", "bit_positions": "+0 | +1"}, "extension": "SSE", "operands": [{"name": "dest", "type": "m64", "desc": "64-bit memory operand (quadword)"}, {"name": "src", "type": "mm", "desc": "64-bit MMX register"}], "description": "Stores a 64-bit quadword from an MMX register directly to memory, bypassing the L1 and L2 caches (non-temporal hint). This instruction provides a memory-ordering serialization point and can improve performance for streaming writes that do not benefit from caching. No CPU flags are affected.", "pseudocode": "[m64] ← mm (non-temporal write)", "example": "MOVNTQ [rbp-8], mm"} {"mnemonic": "movnti", "architecture": "x86", "full_name": "Move Non-Temporal Integer", "summary": "Stores integer register to memory bypassing cache.", "syntax": "MOVNTI m32, r32", "encoding": {"format": "SSE2", "hex_opcode": "NP 0F C3 /r", "visual_parts": [], "binary_pattern": "0F | C3", "bit_positions": "+0 | +1"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "m32", "desc": "32-bit memory operand"}, {"name": "src", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}], "description": "Stores a 32-bit or 64-bit general-purpose register to memory while bypassing the L1 and L2 caches, using a non-temporal hint to the memory subsystem. This instruction is useful for streaming writes that are unlikely to be reused soon. No flags are affected; the instruction may serialize the store buffer but does not guarantee memory ordering with respect to other instructions.", "pseudocode": "[dest] ← src", "example": "MOVNTI [rbp-4], eax"} {"mnemonic": "cmpxchg16b", "architecture": "x86", "full_name": "Compare and Exchange 16 Bytes", "summary": "Atomically compares 128-bit memory with RDX:RAX.", "syntax": "CMPXCHG16B m128", "encoding": {"format": "Base (64-bit)", "hex_opcode": "REX.W + 0F C7 /1", "visual_parts": [], "binary_pattern": "0F | C7 | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "Base (64-bit)", "operands": [{"name": "dest", "type": "m128", "desc": "128-bit memory operand"}], "description": "Atomically compares a 128-bit memory operand with the implicit 128-bit value in RDX:RAX; if they match, writes RCX:RBX to memory and sets ZF to 1; otherwise, loads the memory value into RDX:RAX and clears ZF. This instruction requires 16-byte alignment and is only available in 64-bit mode; it serializes the memory bus and guarantees atomic execution.", "pseudocode": "if ([dest] == (RDX:RAX)) {\n [dest] ← (RCX:RBX);\n ZF ← 1;\n} else {\n (RDX:RAX) ← [dest];\n ZF ← 0;\n}", "example": "CMPXCHG16B [rbp-16]"} {"mnemonic": "movbe", "architecture": "x86", "full_name": "Move Big-Endian", "summary": "Moves data swapping bytes (Big Endian load/store).", "syntax": "MOVBE r, m", "encoding": {"format": "Legacy", "hex_opcode": "0F 38 F0", "visual_parts": [], "binary_pattern": "0F | 38 | F0", "bit_positions": "+0 | +1 | +2"}, "extension": "MOVBE", "operands": [{"name": "dest", "type": "r", "desc": "General-purpose register"}, {"name": "src", "type": "m", "desc": "Memory operand"}], "description": "Loads data from memory or register and reverses the byte order (big-endian conversion) while storing to the destination register or memory. Supports 16-bit, 32-bit, and 64-bit operands; no flags are affected. Available on processors with the MOVBE extension; useful for endianness conversion in multi-byte data transfers.", "pseudocode": "if (dest is register) {\n dest ← byte_reverse(src);\n} else {\n [dest] ← byte_reverse(src);\n}", "example": "MOVBE rax, [rbp-8]"} {"mnemonic": "blendvpd", "architecture": "x86", "full_name": "Variable Blend Packed Double", "summary": "Blends doubles based on variable mask in XMM0.", "syntax": "BLENDVPD xmm1, xmm2/m128, ", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 38 15", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 15", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "", "desc": "Implicit XMM0 register (blend control mask)"}], "description": "Blends two packed double-precision floating-point values in XMM registers or memory based on per-lane sign bits of an implicit mask in XMM0; for each 64-bit lane, if the sign bit is 1, the value from the second source is selected, otherwise from the first source. Part of SSE4.1; no flags are affected. The result is stored in the first source operand (xmm1).", "pseudocode": "for i = 0 to 1 {\n if (XMM0.qword[i] < 0) {\n xmm1.double[i] ← src1.double[i];\n } else {\n xmm1.double[i] ← xmm1.double[i];\n }\n}", "example": "BLENDVPD xmm1, xmm2/m128, "} {"mnemonic": "blendvps", "architecture": "x86", "full_name": "Variable Blend Packed Single", "summary": "Blends floats based on variable mask in XMM0.", "syntax": "BLENDVPS xmm1, xmm2/m128, ", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 38 14", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 14", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "", "desc": "Implicit XMM0 register (blend control mask)"}], "description": "Blends two packed single-precision floating-point values in XMM registers or memory based on per-lane sign bits of an implicit mask in XMM0; for each 32-bit lane, if the sign bit is 1, the value from the second source is selected, otherwise from the first source. Part of SSE4.1; no flags are affected. The result is stored in the first source operand (xmm1).", "pseudocode": "for i = 0 to 3 {\n if (XMM0.dword[i] < 0) {\n xmm1.float[i] ← src1.float[i];\n } else {\n xmm1.float[i] ← xmm1.float[i];\n }\n}", "example": "BLENDVPS xmm1, xmm2/m128, "} {"mnemonic": "pblendvb", "architecture": "x86", "full_name": "Variable Blend Packed Bytes", "summary": "Blends bytes based on variable mask in XMM0.", "syntax": "PBLENDVB xmm1, xmm2/m128, ", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 38 10", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 10", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "", "desc": "Implicit XMM0 register (blend control mask)"}], "description": "Blends two packed byte values in XMM registers or memory based on per-byte sign bits of an implicit mask in XMM0; for each byte, if the sign bit is 1, the value from the second source is selected, otherwise from the first source. Part of SSE4.1; no flags are affected. The result is stored in the first source operand (xmm1).", "pseudocode": "for i = 0 to 15 {\n if (XMM0.byte[i] < 0) {\n xmm1.byte[i] ← src1.byte[i];\n } else {\n xmm1.byte[i] ← xmm1.byte[i];\n }\n}", "example": "PBLENDVB xmm1, xmm2/m128, "} {"mnemonic": "vmrun", "architecture": "x86", "full_name": "Run Virtual Machine", "summary": "Switch to guest VM (AMD SVM).", "syntax": "VMRUN", "encoding": {"format": "SVM", "hex_opcode": "0F 01 D8", "visual_parts": [], "binary_pattern": "0F | 01 | D8", "bit_positions": "+0 | +1 | +2"}, "extension": "SVM", "operands": [], "description": "Switches execution from host to guest virtual machine context by loading guest state from the VMCB (Virtual Machine Control Block) addressed by RAX; serializes the processor and triggers a full context switch including segment registers, control registers, and TLB state. Available only in 64-bit mode with AMD SVM (Secure Virtual Machine) enabled and appropriate privilege level; no flags are affected from the host perspective as execution transfers to guest.", "pseudocode": "VMCB_addr ← RAX;\nload_guest_state(VMCB_addr);\nexecute_guest();", "example": "VMRUN"} {"mnemonic": "vmload", "architecture": "x86", "full_name": "Load State from VMCB", "summary": "Loads processor state from VMCB (AMD SVM).", "syntax": "VMLOAD", "encoding": {"format": "SVM", "hex_opcode": "0F 01 DA", "visual_parts": [], "binary_pattern": "0F | 01 | DA", "bit_positions": "+0 | +1 | +2"}, "extension": "SVM", "operands": [], "description": "Loads processor state (segments, control registers, debug registers, and other hidden state) from the VMCB (Virtual Machine Control Block) referenced by RAX without switching to guest mode execution. Part of AMD SVM; requires 64-bit mode and appropriate privilege level; no flags are affected. This instruction is typically used in host or nested virtualization contexts to synchronize host state.", "pseudocode": "VMCB_addr ← RAX;\nload_state_from_VMCB(VMCB_addr);", "example": "VMLOAD"} {"mnemonic": "vmsave", "architecture": "x86", "full_name": "Save State to VMCB", "summary": "Saves processor state to VMCB (AMD SVM).", "syntax": "VMSAVE", "encoding": {"format": "SVM", "hex_opcode": "0F 01 DB", "visual_parts": [], "binary_pattern": "0F | 01 | DB", "bit_positions": "+0 | +1 | +2"}, "extension": "SVM", "operands": [], "description": "Saves the current processor state to the VMCB (Virtual Machine Control Block) at the address specified in RAX. This is a privileged SVM instruction that serializes the processor and must execute at privilege level 0. The instruction writes guest state registers and internal processor state to memory; it does not modify flags.", "pseudocode": "[RAX + offset] ← processor_state; // VMCB state save", "example": "VMSAVE"} {"mnemonic": "clgi", "architecture": "x86", "full_name": "Clear Global Interrupt Flag", "summary": "Disables global interrupts (AMD SVM).", "syntax": "CLGI", "encoding": {"format": "SVM", "hex_opcode": "0F 01 DD", "visual_parts": [], "binary_pattern": "0F | 01 | DD", "bit_positions": "+0 | +1 | +2"}, "extension": "SVM", "operands": [], "description": "Clears the Global Interrupt Flag (GIF) in the VMCB, which disables interrupts and exceptions at the SVM guest level. This is a privileged instruction that requires CPL=0 and SVM capability. It does not modify EFLAGS but affects the processor's ability to accept external interrupts.", "pseudocode": "GIF ← 0; // Global interrupt flag disabled", "example": "CLGI"} {"mnemonic": "stgi", "architecture": "x86", "full_name": "Set Global Interrupt Flag", "summary": "Enables global interrupts (AMD SVM).", "syntax": "STGI", "encoding": {"format": "SVM", "hex_opcode": "0F 01 DC", "visual_parts": [], "binary_pattern": "0F | 01 | DC", "bit_positions": "+0 | +1 | +2"}, "extension": "SVM", "operands": [], "description": "Sets the Global Interrupt Flag (GIF) in the VMCB, enabling interrupts and exceptions at the SVM guest level. This is a privileged instruction requiring CPL=0 and SVM capability. After execution, the processor will accept maskable interrupts; no EFLAGS are modified.", "pseudocode": "GIF ← 1; // Global interrupt flag enabled", "example": "STGI"} {"mnemonic": "invlpga", "architecture": "x86", "full_name": "Invalidate TLB Entry in ASID", "summary": "Invalidates TLB entry for specific ASID (AMD SVM).", "syntax": "INVLPGA", "encoding": {"format": "SVM", "hex_opcode": "0F 01 DF", "visual_parts": [], "binary_pattern": "0F | 01 | DF", "bit_positions": "+0 | +1 | +2"}, "extension": "SVM", "operands": [], "description": "Invalidates TLB entries for a linear address using the ASID (Address Space Identifier) specified in ECX, applicable only within the current VMCB context. This is a privileged SVM instruction that selectively flushes TLB entries without serializing the entire pipeline. The linear address is implicitly taken from RAX.", "pseudocode": "TLB_entry ← invalidate(RAX, ECX); // Invalidate TLB with ASID", "example": "INVLPGA"} {"mnemonic": "pfadd", "architecture": "x86", "full_name": "Packed Floating-Point Add", "summary": "Adds two packed floats (3DNow!).", "syntax": "PFADD mm, mm/m64", "encoding": {"format": "3DNow!", "hex_opcode": "0F 0F /r 9E", "visual_parts": [], "binary_pattern": "0F | 0F | ModRM | 9E", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "3DNow!", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "mm/m64", "desc": "64-bit MMX register or Memory operand"}], "description": "Adds two packed single-precision floating-point values (two 32-bit floats per 64-bit operand) using 3DNow! arithmetic. The result is written to the destination MMX register with round-to-nearest mode. This instruction does not modify EFLAGS; floating-point exceptions may be masked or pending.", "pseudocode": "dest[31:0] ← float_add(dest[31:0], src[31:0]); dest[63:32] ← float_add(dest[63:32], src[63:32]);", "example": "PFADD mm, mm/m64"} {"mnemonic": "pfsub", "architecture": "x86", "full_name": "Packed Floating-Point Subtract", "summary": "Subtracts packed floats (3DNow!).", "syntax": "PFSUB mm, mm/m64", "encoding": {"format": "3DNow!", "hex_opcode": "0F 0F /r 9A", "visual_parts": [], "binary_pattern": "0F | 0F | ModRM | 9A", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "3DNow!", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "mm/m64", "desc": "64-bit MMX register or Memory operand"}], "description": "Subtracts two packed single-precision floating-point values (two 32-bit floats per 64-bit operand) using 3DNow! arithmetic. The result is written to the destination MMX register. This instruction does not modify EFLAGS; floating-point exceptions may be masked or pending.", "pseudocode": "dest[31:0] ← float_sub(dest[31:0], src[31:0]); dest[63:32] ← float_sub(dest[63:32], src[63:32]);", "example": "PFSUB mm, mm/m64"} {"mnemonic": "pfmul", "architecture": "x86", "full_name": "Packed Floating-Point Multiply", "summary": "Multiplies packed floats (3DNow!).", "syntax": "PFMUL mm, mm/m64", "encoding": {"format": "3DNow!", "hex_opcode": "0F 0F /r B4", "visual_parts": [], "binary_pattern": "0F | 0F | ModRM | B4", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "3DNow!", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "mm/m64", "desc": "64-bit MMX register or Memory operand"}], "description": "Multiplies two packed single-precision floating-point values (two 32-bit floats per 64-bit operand) using 3DNow! arithmetic. The result is written to the destination MMX register. This instruction does not modify EFLAGS; floating-point exceptions may be masked or pending.", "pseudocode": "dest[31:0] ← float_mul(dest[31:0], src[31:0]); dest[63:32] ← float_mul(dest[63:32], src[63:32]);", "example": "PFMUL mm, mm/m64"} {"mnemonic": "pfrcp", "architecture": "x86", "full_name": "Packed Floating-Point Reciprocal", "summary": "Approximates reciprocal (3DNow!).", "syntax": "PFRCP mm, mm/m64", "encoding": {"format": "3DNow!", "hex_opcode": "0F 0F /r 96", "visual_parts": [], "binary_pattern": "0F | 0F | ModRM | 96", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "3DNow!", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "mm/m64", "desc": "64-bit MMX register or Memory operand"}], "description": "Computes a fast approximation of the reciprocal (1/x) for each packed single-precision floating-point value using 3DNow!. The result is written to the destination MMX register with reduced precision (typically 14-15 bits of accuracy). This instruction does not modify EFLAGS; it may generate floating-point exceptions.", "pseudocode": "dest[31:0] ← float_reciprocal_approx(src[31:0]); dest[63:32] ← float_reciprocal_approx(src[63:32]);", "example": "PFRCP mm, mm/m64"} {"mnemonic": "pfrsqrt", "architecture": "x86", "full_name": "Packed Floating-Point Reciprocal Square Root", "summary": "Approximates reciprocal sqrt (3DNow!).", "syntax": "PFRSQRT mm, mm/m64", "encoding": {"format": "3DNow!", "hex_opcode": "0F 0F /r 97", "visual_parts": [], "binary_pattern": "0F | 0F | ModRM | 97", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "3DNow!", "operands": [{"name": "dest", "type": "mm", "desc": "64-bit MMX register"}, {"name": "src", "type": "mm/m64", "desc": "64-bit MMX register or Memory operand"}], "description": "Computes a fast approximation of the reciprocal square root (1/√x) for two packed single-precision floating-point values in parallel. This is a 3DNow! extension instruction that performs low-precision approximation suitable for iterative refinement; the approximation has limited accuracy (typically ~11-12 bits). No EFLAGS are modified.", "pseudocode": "dest[0:31] ← approx_rsqrt(src[0:31]);\ndest[32:63] ← approx_rsqrt(src[32:63]);", "example": "PFRSQRT mm, mm/m64"} {"mnemonic": "vaddsh", "architecture": "x86", "full_name": "Add Scalar Half-Precision", "summary": "Adds low FP16 value.", "syntax": "VADDSH xmm1 {k1}, xmm2, xmm3/m16", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.LLIG.F3.MAP5.W0 58 /r", "visual_parts": [], "binary_pattern": "EVEX | 58", "bit_positions": "+0 | +4"}, "extension": "AVX-512-FP16", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2", "desc": "128-bit XMM SIMD register"}, {"name": "src2", "type": "xmm3/m16", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Adds the low-order half-precision (FP16) element from two XMM registers and stores the scalar result in the low 16 bits of the destination, with upper 112 bits cleared or preserved based on write-mask. Uses EVEX encoding with optional masking and suppression of exceptions. Rounding mode is determined by MXCSR[15:13].", "pseudocode": "if (k1[0] || !masking_enabled) {\n dest[0:15] ← src1[0:15] +FP16 src2[0:15];\n} else {\n dest[0:15] ← preserve_or_zero(dest[0:15]);\n}\ndest[16:127] ← 0;", "example": "VADDSH xmm1, xmm2, xmm3/m16"} {"mnemonic": "vsubsh", "architecture": "x86", "full_name": "Subtract Scalar Half-Precision", "summary": "Subtracts low FP16 value.", "syntax": "VSUBSH xmm1 {k1}, xmm2, xmm3/m16", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.LLIG.F3.MAP5.W0 5C /r", "visual_parts": [], "binary_pattern": "EVEX | 5C", "bit_positions": "+0 | +4"}, "extension": "AVX-512-FP16", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2", "desc": "128-bit XMM SIMD register"}, {"name": "src2", "type": "xmm3/m16", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Subtracts the low-order half-precision (FP16) element of the second operand from the first and stores the scalar result in the low 16 bits of the destination, with upper 112 bits cleared or preserved based on write-mask. Uses EVEX encoding with optional masking and exception suppression. Rounding controlled by MXCSR[15:13].", "pseudocode": "if (k1[0] || !masking_enabled) {\n dest[0:15] ← src1[0:15] -FP16 src2[0:15];\n} else {\n dest[0:15] ← preserve_or_zero(dest[0:15]);\n}\ndest[16:127] ← 0;", "example": "VSUBSH xmm1, xmm2, xmm3/m16"} {"mnemonic": "vmulsh", "architecture": "x86", "full_name": "Multiply Scalar Half-Precision", "summary": "Multiplies low FP16 value.", "syntax": "VMULSH xmm1 {k1}, xmm2, xmm3/m16", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.LLIG.F3.MAP5.W0 59 /r", "visual_parts": [], "binary_pattern": "EVEX | 59", "bit_positions": "+0 | +4"}, "extension": "AVX-512-FP16", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2", "desc": "128-bit XMM SIMD register"}, {"name": "src2", "type": "xmm3/m16", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Multiplies the low-order half-precision (FP16) element from two operands and stores the scalar result in the low 16 bits of the destination, with upper 112 bits cleared or preserved based on write-mask. Uses EVEX encoding with optional masking and exception control. Rounding mode determined by MXCSR[15:13].", "pseudocode": "if (k1[0] || !masking_enabled) {\n dest[0:15] ← src1[0:15] ×FP16 src2[0:15];\n} else {\n dest[0:15] ← preserve_or_zero(dest[0:15]);\n}\ndest[16:127] ← 0;", "example": "VMULSH xmm1, xmm2, xmm3/m16"} {"mnemonic": "vdivsh", "architecture": "x86", "full_name": "Divide Scalar Half-Precision", "summary": "Divides low FP16 value.", "syntax": "VDIVSH xmm1 {k1}, xmm2, xmm3/m16", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.LLIG.F3.MAP5.W0 5E /r", "visual_parts": [], "binary_pattern": "EVEX | 5E", "bit_positions": "+0 | +4"}, "extension": "AVX-512-FP16", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2", "desc": "128-bit XMM SIMD register"}, {"name": "src2", "type": "xmm3/m16", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Divides the low-order half-precision (FP16) element of the first operand by the second and stores the scalar result in the low 16 bits of the destination, with upper 112 bits cleared or preserved based on write-mask. Uses EVEX encoding with optional masking and exception suppression. Rounding controlled by MXCSR[15:13]; may generate precision/underflow/overflow exceptions.", "pseudocode": "if (k1[0] || !masking_enabled) {\n dest[0:15] ← src1[0:15] ÷FP16 src2[0:15];\n} else {\n dest[0:15] ← preserve_or_zero(dest[0:15]);\n}\ndest[16:127] ← 0;", "example": "VDIVSH xmm1, xmm2, xmm3/m16"} {"mnemonic": "vsqrtsh", "architecture": "x86", "full_name": "Square Root Scalar Half-Precision", "summary": "Square root of low FP16 value.", "syntax": "VSQRTSH xmm1 {k1}, xmm2/m16", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.LLIG.F3.MAP5.W0 51 /r", "visual_parts": [], "binary_pattern": "EVEX | 51", "bit_positions": "+0 | +4"}, "extension": "AVX-512-FP16", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m16", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Computes the square root of the low-order half-precision (FP16) element and stores the scalar result in the low 16 bits of the destination, with upper 112 bits cleared or preserved based on write-mask. Uses EVEX encoding with optional masking and exception suppression. Rounding mode determined by MXCSR[15:13].", "pseudocode": "if (k1[0] || !masking_enabled) {\n dest[0:15] ← sqrt_FP16(src[0:15]);\n} else {\n dest[0:15] ← preserve_or_zero(dest[0:15]);\n}\ndest[16:127] ← 0;", "example": "VSQRTSH xmm1, xmm2/m16"} {"mnemonic": "vfmadd132sh", "architecture": "x86", "full_name": "Fused Multiply-Add Scalar Half-Precision (132)", "summary": "Scalar FMA (Dest * Src2 + Src1) for FP16.", "syntax": "VFMADD132SH xmm1 {k1}, xmm2, xmm3/m16", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.LLIG.66.MAP6.W0 99 /r", "visual_parts": [], "binary_pattern": "EVEX | 99", "bit_positions": "+0 | +4"}, "extension": "AVX-512-FP16", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2", "desc": "128-bit XMM SIMD register"}, {"name": "src2", "type": "xmm3/m16", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Performs fused multiply-add on scalar half-precision (FP16) values: multiplies the destination by src2, adds src1, and stores result in destination. The '132' form computes (dest × src2) + src1. Uses EVEX encoding with optional masking and exception suppression. Single rounding applied to the final result per MXCSR[15:13].", "pseudocode": "if (k1[0] || !masking_enabled) {\n dest[0:15] ← (dest[0:15] ×FP16 src2[0:15]) +FP16 src1[0:15];\n} else {\n dest[0:15] ← preserve_or_zero(dest[0:15]);\n}\ndest[16:127] ← 0;", "example": "VFMADD132SH xmm1, xmm2, xmm3/m16"} {"mnemonic": "vpmullq", "architecture": "x86", "full_name": "Packed Multiply Low Quadword", "summary": "Multiplies 64-bit integers and keeps low 64-bit result.", "syntax": "VPMULLQ zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W1 40 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 40", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512DQ", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Multiplies eight packed 64-bit signed integers and stores the low 64-bit results of each multiplication in eight 64-bit elements of the destination ZMM register. Uses EVEX encoding with optional per-element masking via write-mask register. No overflow flags are set; overflow is silently truncated to 64 bits.", "pseudocode": "for (i = 0; i < 8; i++) {\n if (k1[i] || !masking_enabled) {\n dest[64*i:64*i+63] ← (src1[64*i:64*i+63] ×64-bit src2[64*i:64*i+63]) & 0xFFFFFFFFFFFFFFFF;\n } else {\n dest[64*i:64*i+63] ← preserve_or_zero(dest[64*i:64*i+63]);\n }\n}", "example": "VPMULLQ zmm1, zmm2, zmm3/m512"} {"mnemonic": "vpabsd", "architecture": "x86", "full_name": "Packed Absolute Value Doubleword", "summary": "Computes absolute value of 32-bit integers.", "syntax": "VPABSD zmm1 {k1}, zmm2/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W0 1E /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 1E", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src", "type": "zmm2/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Computes the absolute value of packed 32-bit signed integers in the source operand and stores the results in the destination register. Each 32-bit element is independently processed; if the input is 0x80000000 (minimum signed 32-bit), the result remains 0x80000000 due to two's complement representation. Operates on 512-bit data with EVEX prefix, supporting write-masking via k1.", "pseudocode": "for i = 0 to 15 {\n src_val = src[32*i+31:32*i]\n if (src_val == 0x80000000) {\n dest[32*i+31:32*i] = 0x80000000\n } else if (src_val & 0x80000000 == 1) {\n dest[32*i+31:32*i] = -src_val\n } else {\n dest[32*i+31:32*i] = src_val\n }\n}", "example": "VPABSD zmm1, zmm2/m512"} {"mnemonic": "valignq", "architecture": "x86", "full_name": "Align Quadword Vectors", "summary": "Extracts 512-bits from two concatenated ZMMs shifted by count.", "syntax": "VALIGNQ zmm1 {k1}, zmm2, zmm3/m512, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F3A.W1 03 /r ib", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 3A | 03", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}, {"name": "src3", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Extracts 512 bits from two concatenated 512-bit quadword vectors, with the extraction window shifted by an immediate count (in quadword units). The operation concatenates src1 and src2, then shifts right by count*64 bits. The lowest 512 bits of the result are stored in dest. Operates under EVEX with write-masking support.", "pseudocode": "shift_bits = (imm8 & 0x7) * 64\nconcatenated = (src2 << 512) | src1\nshifted = concatenated >> shift_bits\ndest = shifted[511:0]", "example": "VALIGNQ zmm1, zmm2, zmm3/m512, 3"} {"mnemonic": "vdbpsadbw", "architecture": "x86", "full_name": "Double Block Packed Sum-Absolute-Differences", "summary": "Computes SAD on 16-bit blocks.", "syntax": "VDBPSADBW zmm1 {k1}, zmm2, zmm3/m512, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F3A.W0 42 /r ib", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 3A | 42", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512BW", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}, {"name": "src3", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Computes double-block packed sum-of-absolute-differences on 16-bit blocks between src1 and src2, producing 16-bit results. The operation partitions each 128-bit lane into blocks of 16 bits, computes SAD across specified block boundaries controlled by imm8, and accumulates results into 16-bit fields. Requires AVX-512BW; operates on 512-bit vectors with EVEX masking.", "pseudocode": "for lane = 0 to 3 {\n for block = 0 to 3 {\n result = 0\n block_offset = (imm8 >> (block*2)) & 0x3\n for j = 0 to 1 {\n idx1 = lane*128 + block*32 + j*16\n idx2 = lane*128 + block_offset*32 + j*16\n result += abs(src1[idx1+15:idx1] - src2[idx2+15:idx2])\n }\n dest[lane*128 + block*16 + 15 : lane*128 + block*16] = result[15:0]\n }\n}", "example": "VDBPSADBW zmm1, zmm2, zmm3/m512, 3"} {"mnemonic": "vrangess", "architecture": "x86", "full_name": "Range Restriction Calculation Scalar Single", "summary": "Calculates range (min/max/abs) of low float.", "syntax": "VRANGESS xmm1 {k1}, xmm2, xmm3/m32, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.LLIG.66.0F3A.W0 51 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 3A | 51", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512DQ", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2", "desc": "128-bit XMM SIMD register"}, {"name": "src2", "type": "xmm3/m32", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src3", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Restricts the range of the low single-precision float in xmm2 and the corresponding float from xmm3/m32 according to the range specification in imm8, storing the result in xmm1. The imm8 encodes operations such as minimum, maximum, and absolute value selection. Upper three floats of xmm1 are copied from xmm2 unchanged. Operates in 32-bit scalar mode with EVEX write-masking via k1; requires AVX-512DQ.", "pseudocode": "range_op = imm8[3:0]\nop1_float = xmm2[31:0]\nop2_float = xmm3/m32[31:0]\nxmm1[31:0] = perform_range_restriction(op1_float, op2_float, range_op)\nxmm1[127:32] = xmm2[127:32]", "example": "VRANGESS xmm1, xmm2, xmm3/m32, 3"} {"mnemonic": "vfixupimmss", "architecture": "x86", "full_name": "Fix Up Special Scalar Float32 Value", "summary": "Fixes special cases (NaN, Inf) in low float using table.", "syntax": "VFIXUPIMMSS xmm1 {k1}, xmm2, xmm3/m32, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.LLIG.66.0F3A.W0 55 /r ib", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 3A | 55", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2", "desc": "128-bit XMM SIMD register"}, {"name": "src2", "type": "xmm3/m32", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src3", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Fixes up special floating-point values (NaN, infinity, denormal, sign) in the low single-precision float using a table lookup controlled by imm8. The lookup uses xmm2[31:0] as one input and xmm3/m32[31:0] as reference, producing a corrected value in xmm1[31:0]. Upper three floats in xmm1 are copied from xmm2. Operates under EVEX with write-masking; AVX-512F compliant.", "pseudocode": "op1 = xmm2[31:0]\nop2 = xmm3/m32[31:0]\nlookup_index = (sign_of(op1)<<4) | (class_of(op1)<<1) | (class_of(op2))\nfixed_value = fixup_table[lookup_index][imm8[7:0]]\nxmm1[31:0] = fixed_value\nxmm1[127:32] = xmm2[127:32]", "example": "VFIXUPIMMSS xmm1, xmm2, xmm3/m32, 3"} {"mnemonic": "vreducess", "architecture": "x86", "full_name": "Perform Reduction Transformation Scalar Single", "summary": "Performs reduction on low float.", "syntax": "VREDUCESS xmm1 {k1}, xmm2, xmm3/m32, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.LLIG.66.0F3A.W0 57 /r /ib", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 3A | 57", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512DQ", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2", "desc": "128-bit XMM SIMD register"}, {"name": "src2", "type": "xmm3/m32", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src3", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Performs a reduction transformation (rounding, exponent manipulation) on the low single-precision float from xmm2 and xmm3/m32 according to the control specified in imm8, storing the scalar result in xmm1[31:0]. Upper three floats in xmm1 are copied from xmm2. Reduction includes operations like round-to-integral, exponent bias removal, or truncation. Requires AVX-512DQ with EVEX masking.", "pseudocode": "reduction_op = (imm8[3:0])\nsignaling_bit = imm8[4]\nop1_float = xmm2[31:0]\nop2_float = xmm3/m32[31:0]\nxmm1[31:0] = perform_reduction(op1_float, op2_float, reduction_op, signaling_bit)\nxmm1[127:32] = xmm2[127:32]", "example": "VREDUCESS xmm1, xmm2, xmm3/m32, 3"} {"mnemonic": "kandq", "architecture": "x86", "full_name": "Bitwise Logical AND Masks Quadword", "summary": "Bitwise AND of 64-bit mask registers.", "syntax": "KANDQ k1, k2, k3", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L1.0F.W1 41 /r", "visual_parts": [], "binary_pattern": "EVEX | 0F | 41", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512BW", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "k2", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src2", "type": "k3", "desc": "AVX-512 opmask register (k0-k7)"}], "description": "Performs a bitwise logical AND on two 64-bit mask registers (k2 and k3) and stores the result in the destination mask register (k1). All 64 bits of the mask registers are operated on. This is a low-latency operation with no flag modifications. Requires AVX-512BW for 64-bit mask register support.", "pseudocode": "k1 = k2 & k3", "example": "KANDQ k1, k2, k3"} {"mnemonic": "korq", "architecture": "x86", "full_name": "Bitwise Logical OR Masks Quadword", "summary": "Bitwise OR of 64-bit mask registers.", "syntax": "KORQ k1, k2, k3", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L1.0F.W1 45 /r", "visual_parts": [], "binary_pattern": "EVEX | 0F | 45", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512BW", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "k2", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src2", "type": "k3", "desc": "AVX-512 opmask register (k0-k7)"}], "description": "Performs a bitwise logical OR on two 64-bit mask registers (k2 and k3) and stores the result in the destination mask register (k1). All 64 bits of the mask registers participate in the operation. This is a low-latency mask manipulation instruction with no EFLAGS modification. Requires AVX-512BW for 64-bit mask operations.", "pseudocode": "k1 = k2 | k3", "example": "KORQ k1, k2, k3"} {"mnemonic": "knotq", "architecture": "x86", "full_name": "Bitwise Logical NOT Masks Quadword", "summary": "Bitwise NOT of 64-bit mask register.", "syntax": "KNOTQ k1, k2", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L0.0F.W1 44 /r", "visual_parts": [], "binary_pattern": "EVEX | 0F | 44", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512BW", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src", "type": "k2", "desc": "AVX-512 opmask register (k0-k7)"}], "description": "Performs a bitwise logical NOT operation on a 64-bit AVX-512 opmask register, inverting all bits. The instruction operates only on opmask registers (k0-k7) and does not affect general EFLAGS. This is an AVX-512BW extension instruction with no flag side effects.", "pseudocode": "dest ← ~src", "example": "KNOTQ k1, k2"} {"mnemonic": "aesimc", "architecture": "x86", "full_name": "AES Inverse Mix Columns", "summary": "Performs AES InvMixColumns transformation (decryption helper).", "syntax": "AESIMC xmm1, xmm2/m128", "encoding": {"format": "AES-NI", "hex_opcode": "66 0F 38 DB", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | DB", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "AES-NI", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Performs the AES InvMixColumns transformation on a 128-bit XMM register, applying the inverse MixColumns step used in AES block cipher decryption. This is a cryptographic acceleration instruction from the AES-NI extension that operates on 128-bit values and produces no flag modifications.", "pseudocode": "dest ← InvMixColumns(src)", "example": "AESIMC xmm1, xmm2/m128"} {"mnemonic": "maskmovq", "architecture": "x86", "full_name": "Store Selected Bytes of Quadword", "summary": "Non-temporal store of selected MMX bytes.", "syntax": "MASKMOVQ mm1, mm2", "encoding": {"format": "MMX", "hex_opcode": "NP 0F F7 /r", "visual_parts": [], "binary_pattern": "0F | F7", "bit_positions": "+0 | +1"}, "extension": "MMX", "operands": [{"name": "dest", "type": "mm1", "desc": "64-bit MMX register"}, {"name": "src", "type": "mm2", "desc": "64-bit MMX register"}], "description": "Conditionally stores selected bytes from a 64-bit MMX register to memory based on byte-granularity mask bits from another MMX register, using the implicit address in EDI (32-bit) or RDI (64-bit). The instruction writes non-temporally where supported and does not affect EFLAGS; it requires real or protected mode for address generation.", "pseudocode": "for (i = 0; i < 8; i++) {\n if (src[i*8 + 7] == 1) {\n [EDI/RDI + i] ← dest[i*8 : i*8+7]\n }\n}", "example": "MASKMOVQ mm1, mm2"} {"mnemonic": "pmulld", "architecture": "x86", "full_name": "Packed Multiply Low Doubleword", "summary": "Multiplies 32-bit integers, stores low 32-bit result.", "syntax": "PMULLD xmm1, xmm2/m128", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 38 40", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 40", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Multiplies four pairs of 32-bit signed integers in parallel, storing the low 32 bits of each product in the destination XMM register. This SSE4.1 instruction operates on 128-bit vectors and does not modify EFLAGS; overflow is silently discarded.", "pseudocode": "for (i = 0; i < 4; i++) {\n dest[i*32 : i*32+31] ← (src1[i*32 : i*32+31] * src2[i*32 : i*32+31]) & 0xFFFFFFFF\n}", "example": "PMULLD xmm1, xmm2/m128"} {"mnemonic": "pmovsxbw", "architecture": "x86", "full_name": "Packed Move with Sign Extend Byte to Word", "summary": "Sign extends 8-bit integers to 16-bit.", "syntax": "PMOVSXBW xmm1, xmm2/m64", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 38 20", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 20", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m64", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Sign-extends four 8-bit signed integers from the lower 32 bits of the source to four 16-bit signed integers in the destination XMM register. This SSE4.1 instruction performs element-wise sign extension with no flag side effects; the upper 64 bits of the source are ignored.", "pseudocode": "for (i = 0; i < 4; i++) {\n dest[i*16 : i*16+15] ← sign_extend_8to16(src[i*8 : i*8+7])\n}\ndest[64:127] ← 0", "example": "PMOVSXBW xmm1, xmm2/m64"} {"mnemonic": "pmovzxbw", "architecture": "x86", "full_name": "Packed Move with Zero Extend Byte to Word", "summary": "Zero extends 8-bit integers to 16-bit.", "syntax": "PMOVZXBW xmm1, xmm2/m64", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 38 30", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 30", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m64", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Zero-extends four 8-bit unsigned integers from the lower 32 bits of the source to four 16-bit unsigned integers in the destination XMM register. This SSE4.1 instruction performs element-wise zero extension with no flag modifications; the upper 64 bits of the source are ignored.", "pseudocode": "for (i = 0; i < 4; i++) {\n dest[i*16 : i*16+15] ← zero_extend_8to16(src[i*8 : i*8+7])\n}\ndest[64:127] ← 0", "example": "PMOVZXBW xmm1, xmm2/m64"} {"mnemonic": "pinsrb", "architecture": "x86", "full_name": "Packed Insert Byte", "summary": "Inserts a byte from integer register into XMM.", "syntax": "PINSRB xmm1, r32/m8, imm8", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 3A 20", "visual_parts": [], "binary_pattern": "66 | 0F | 3A | 20", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "r32/m8", "desc": "General-purpose register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Inserts an 8-bit integer value from a general-purpose register or memory into a byte position within the destination XMM register, as specified by an immediate index. This SSE4.1 instruction does not affect EFLAGS; the immediate selects one of 16 byte lanes (0-15) in the 128-bit register.", "pseudocode": "index ← src2 & 0xF\ndest[index*8 : index*8+7] ← src1[0:7]", "example": "PINSRB xmm1, r32/m8, 3"} {"mnemonic": "pextrb", "architecture": "x86", "full_name": "Packed Extract Byte", "summary": "Extracts a byte from XMM to integer register.", "syntax": "PEXTRB r32/m8, xmm1, imm8", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 3A 14", "visual_parts": [], "binary_pattern": "66 | 0F | 3A | 14", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "r32/m8", "desc": "General-purpose register or Memory operand"}, {"name": "src1", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Extracts an 8-bit byte from a specified position within the source XMM register and stores it into a general-purpose register or memory location. This SSE4.1 instruction does not modify EFLAGS; the immediate selects one of 16 byte lanes (0-15), and destination registers are zero-extended to 32 bits when writing to r32.", "pseudocode": "index ← src2 & 0xF\ndest ← src1[index*8 : index*8+7]", "example": "PEXTRB r32/m8, xmm1, 3"} {"mnemonic": "ptest", "architecture": "x86", "full_name": "Packed Logical Comparison", "summary": "Bitwise compare of 128-bit value (AND) setting flags.", "syntax": "PTEST xmm1, xmm2/m128", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 38 17", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 17", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4.1", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Performs a bitwise AND of the 128-bit source operand with the 128-bit destination operand and sets EFLAGS based on the result, without modifying the destination. Sets ZF if the AND result is all zeros, sets CF if the AND of the source with the bitwise NOT of the destination is all zeros. Does not update OF, SF, AF, or PF. Available only in SSE4.1 and later; operates on 128-bit XMM registers.", "pseudocode": "temp ← dest[127:0] AND src[127:0];\nZF ← (temp == 0);\nCF ← ((src[127:0] AND (NOT dest[127:0])) == 0);\nOF ← 0; SF ← 0; AF ← 0; PF ← 0;", "example": "PTEST xmm1, xmm2/m128"} {"mnemonic": "aesenc", "architecture": "x86", "full_name": "AES Encrypt", "summary": "Performs one round of AES encryption flow.", "syntax": "AESENC xmm1, xmm2/m128", "encoding": {"format": "AES-NI", "hex_opcode": "66 0F 38 DC", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | DC", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "AES-NI", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Performs a single round of AES encryption on the 128-bit state in the destination XMM register using the round key in the source operand. The operation includes SubBytes, ShiftRows, MixColumns, and AddRoundKey transformations. Does not modify EFLAGS. Requires the AES-NI instruction set extension; operates on 128-bit XMM registers or memory.", "pseudocode": "dest[127:0] ← AES_EncryptionRound(dest[127:0], src[127:0]);\nOF ← 0; CF ← 0; ZF ← 0; SF ← 0; AF ← 0; PF ← 0;", "example": "AESENC xmm1, xmm2/m128"} {"mnemonic": "aesenclast", "architecture": "x86", "full_name": "AES Encrypt Last Round", "summary": "Performs the last round of AES encryption.", "syntax": "AESENCLAST xmm1, xmm2/m128", "encoding": {"format": "AES-NI", "hex_opcode": "66 0F 38 DD", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | DD", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "AES-NI", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Performs the final round of AES encryption on the 128-bit state in the destination XMM register using the round key in the source operand. The final round excludes the MixColumns transformation compared to aesenc. Does not modify EFLAGS. Requires the AES-NI instruction set extension; operates on 128-bit XMM registers or memory.", "pseudocode": "dest[127:0] ← AES_EncryptionLastRound(dest[127:0], src[127:0]);\nOF ← 0; CF ← 0; ZF ← 0; SF ← 0; AF ← 0; PF ← 0;", "example": "AESENCLAST xmm1, xmm2/m128"} {"mnemonic": "aesdec", "architecture": "x86", "full_name": "AES Decrypt", "summary": "Performs one round of AES decryption flow.", "syntax": "AESDEC xmm1, xmm2/m128", "encoding": {"format": "AES-NI", "hex_opcode": "66 0F 38 DE", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | DE", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "AES-NI", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Performs a single round of AES decryption on the 128-bit state in the destination XMM register using the round key in the source operand. The operation includes InvSubBytes, InvShiftRows, InvMixColumns, and AddRoundKey transformations. Does not modify EFLAGS. Requires the AES-NI instruction set extension; operates on 128-bit XMM registers or memory.", "pseudocode": "dest[127:0] ← AES_DecryptionRound(dest[127:0], src[127:0]);\nOF ← 0; CF ← 0; ZF ← 0; SF ← 0; AF ← 0; PF ← 0;", "example": "AESDEC xmm1, xmm2/m128"} {"mnemonic": "aeskeygenassist", "architecture": "x86", "full_name": "AES Key Generation Assist", "summary": "Generates round key for AES encryption.", "syntax": "AESKEYGENASSIST xmm1, xmm2/m128, imm8", "encoding": {"format": "AES-NI", "hex_opcode": "66 0F 3A DF", "visual_parts": [], "binary_pattern": "66 | 0F | 3A | DF", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "AES-NI", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Generates a round key for AES encryption by performing key schedule computation on the 128-bit source operand and an immediate byte, storing the result in the destination XMM register. Used to facilitate AES key expansion during encryption key setup. Does not modify EFLAGS. Requires the AES-NI instruction set extension; operates on 128-bit XMM registers or memory with an 8-bit immediate.", "pseudocode": "dest[127:0] ← AES_KeyGenAssist(src[127:0], imm8);\nOF ← 0; CF ← 0; ZF ← 0; SF ← 0; AF ← 0; PF ← 0;", "example": "AESKEYGENASSIST xmm1, xmm2/m128, 3"} {"mnemonic": "vaddps", "architecture": "x86", "full_name": "Add Packed Single-Precision (AVX)", "summary": "Adds packed floats (256-bit YMM support).", "syntax": "VADDPS ymm1, ymm2, ymm3/m256", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.0F.WIG 58 /r", "visual_parts": [], "binary_pattern": "VEX | C5 | ModRM | 58", "bit_positions": "+0 | +3 | +4 | +5"}, "extension": "AVX", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src1", "type": "ymm2", "desc": "256-bit YMM AVX register"}, {"name": "src2", "type": "ymm3/m256", "desc": "256-bit YMM AVX register or Memory operand"}], "description": "Adds four packed single-precision floating-point values from the source operand to the corresponding values in the first source operand and stores the result in the destination YMM register. Floating-point exceptions and rounding mode are controlled by MXCSR. Does not modify EFLAGS. Requires AVX and is available in 64-bit mode; operates on 256-bit YMM registers or memory with three-operand form.", "pseudocode": "dest[255:0] ← src1[255:0] + src2[255:0];\nfor i ← 0 to 7 do\n dest[32*i+31:32*i] ← FP32_Add(src1[32*i+31:32*i], src2[32*i+31:32*i]);\nendfor;", "example": "VADDPS ymm1, ymm2, ymm3/m256"} {"mnemonic": "vmulps", "architecture": "x86", "full_name": "Multiply Packed Single-Precision (AVX)", "summary": "Multiplies packed floats (256-bit).", "syntax": "VMULPS ymm1, ymm2, ymm3/m256", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.0F.WIG 59 /r", "visual_parts": [], "binary_pattern": "VEX | C5 | ModRM | 59", "bit_positions": "+0 | +3 | +4 | +5"}, "extension": "AVX", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src1", "type": "ymm2", "desc": "256-bit YMM AVX register"}, {"name": "src2", "type": "ymm3/m256", "desc": "256-bit YMM AVX register or Memory operand"}], "description": "Multiplies four packed single-precision floating-point values from the source operand by the corresponding values in the first source operand and stores the result in the destination YMM register. Floating-point exceptions and rounding mode are controlled by MXCSR. Does not modify EFLAGS. Requires AVX and is available in 64-bit mode; operates on 256-bit YMM registers or memory with three-operand form.", "pseudocode": "dest[255:0] ← src1[255:0] * src2[255:0];\nfor i ← 0 to 7 do\n dest[32*i+31:32*i] ← FP32_Multiply(src1[32*i+31:32*i], src2[32*i+31:32*i]);\nendfor;", "example": "VMULPS ymm1, ymm2, ymm3/m256"} {"mnemonic": "vfmadd231ps", "architecture": "x86", "full_name": "Fused Multiply-Add (132)", "summary": "Computes (Dest * Src2) + Src1.", "syntax": "VFMADD231PS ymm1, ymm2, ymm3/m256", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F38.0 B8 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "FMA3", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src1", "type": "ymm2", "desc": "256-bit YMM AVX register"}, {"name": "src2", "type": "ymm3/m256", "desc": "256-bit YMM AVX register or Memory operand"}], "description": "Performs a fused multiply-add operation: multiplies the destination operand by the third operand and adds the result to the second operand, storing the result in the destination YMM register. The 231 variant computes (dest * src2) + src1 in a single operation with one rounding step, improving precision over separate multiply and add. Does not modify EFLAGS. Requires FMA3 and is available in 64-bit mode; operates on 256-bit YMM registers or memory.", "pseudocode": "dest[255:0] ← FMA(dest[255:0], src2[255:0], src1[255:0]);\nfor i ← 0 to 7 do\n dest[32*i+31:32*i] ← FP32_FMA(dest[32*i+31:32*i], src2[32*i+31:32*i], src1[32*i+31:32*i]);\nendfor;", "example": "VFMADD231PS ymm1, ymm2, ymm3/m256"} {"mnemonic": "vinsertf128", "architecture": "x86", "full_name": "Insert Float 128-bit", "summary": "Inserts 128-bits into a YMM register.", "syntax": "VINSERTF128 ymm1, ymm2, xmm3/m128, imm8", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F3A.W0 18 /r ib", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AVX", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src1", "type": "ymm2", "desc": "256-bit YMM AVX register"}, {"name": "src2", "type": "xmm3/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src3", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Inserts a 128-bit float vector into a 256-bit YMM register at either the lower or upper 128-bit lane, with the remaining lane copied from the first source operand. This is a non-destructive three-operand instruction where the immediate byte (bits 0-7) selects the destination lane (0=lower, 1=upper). No flags are affected; this is purely a data movement and lane selection operation.", "pseudocode": "imm_index ← imm8[0];\nif (imm_index == 0) {\n ymm1[0:127] ← xmm3/m128[0:127];\n ymm1[128:255] ← ymm2[128:255];\n} else {\n ymm1[0:127] ← ymm2[0:127];\n ymm1[128:255] ← xmm3/m128[0:127];\n}", "example": "VINSERTF128 ymm1, ymm2, xmm3/m128, 3"} {"mnemonic": "vextractf128", "architecture": "x86", "full_name": "Extract Float 128-bit", "summary": "Extracts 128-bits from YMM register.", "syntax": "VEXTRACTF128 xmm1/m128, ymm2, imm8", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F3A.W0 19 /r ib", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AVX", "operands": [{"name": "dest", "type": "xmm1/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src1", "type": "ymm2", "desc": "256-bit YMM AVX register"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Extracts a 128-bit float vector from a 256-bit YMM register based on an immediate selector and stores it to an XMM register or 128-bit memory location. The immediate byte (bit 0) selects which 128-bit lane to extract (0=lower, 1=upper). No flags are affected; this is a data extraction and movement operation only.", "pseudocode": "imm_index ← imm8[0];\nif (imm_index == 0) {\n xmm1/m128[0:127] ← ymm2[0:127];\n} else {\n xmm1/m128[0:127] ← ymm2[128:255];\n}", "example": "VEXTRACTF128 xmm1/m128, ymm2, 3"} {"mnemonic": "vzeroupper", "architecture": "x86", "full_name": "Zero Upper Bits of YMM Registers", "summary": "Clears bits 128-255 of all YMM registers (Avoids AVX-SSE transition penalty).", "syntax": "VZEROUPPER", "encoding": {"format": "VEX", "hex_opcode": "VEX.128.0F.WIG 77", "visual_parts": [], "binary_pattern": "VEX | C5 | F8 | 77", "bit_positions": "+0 | +3 | +4 | +5"}, "extension": "AVX", "operands": [], "description": "Clears bits 128-255 of all 16 YMM registers (YMM0-YMM15 in 64-bit mode, YMM0-YMM7 in 32-bit mode), leaving bits 0-127 unchanged. This eliminates the AVX-to-SSE transition penalty by ensuring the upper 128-bit portions are zero before executing SSE instructions. No flags are affected. This instruction must be executed in protected or 64-bit mode.", "pseudocode": "for i from 0 to (is_64bit_mode ? 15 : 7) {\n YMM[i][128:255] ← 0;\n}", "example": "VZEROUPPER"} {"mnemonic": "vzeroall", "architecture": "x86", "full_name": "Zero All YMM Registers", "summary": "Clears all YMM registers.", "syntax": "VZEROALL", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.0F.WIG 77", "visual_parts": [], "binary_pattern": "VEX | C5 | FC | 77", "bit_positions": "+0 | +3 | +4 | +5"}, "extension": "AVX", "operands": [], "description": "Clears all bits of all 16 YMM registers (YMM0-YMM15 in 64-bit mode, YMM0-YMM7 in 32-bit mode) to zero. This is a faster alternative to clearing individual YMM registers via multiple VXORPS or similar instructions. No flags are affected. Execution is restricted to protected or 64-bit mode.", "pseudocode": "for i from 0 to (is_64bit_mode ? 15 : 7) {\n YMM[i][0:255] ← 0;\n}", "example": "VZEROALL"} {"mnemonic": "emms", "architecture": "x86", "full_name": "Empty MMX Technology State", "summary": "Clears the FPU tag word to allow FP instructions after MMX.", "syntax": "EMMS", "encoding": {"format": "MMX", "hex_opcode": "NP 0F 77", "visual_parts": [], "binary_pattern": "0F | 77", "bit_positions": "+0 | +1"}, "extension": "MMX", "operands": [], "description": "Sets all tag bits in the x87 FPU tag word to 1 (all entries marked empty), allowing the x87 FPU to be used immediately after MMX instructions without a transition penalty. This instruction clears the MMX state and must be executed before mixing MMX and x87 floating-point operations. No general-purpose flags are affected, but internal x87 state is modified.", "pseudocode": "FPU_TAG_WORD[0:15] ← 0xFFFF;", "example": "EMMS"} {"mnemonic": "movd", "architecture": "x86", "full_name": "Move Doubleword", "summary": "Moves 32 bits between GPR and XMM/MMX register.", "syntax": "MOVD mm/xmm, r32/m32", "encoding": {"format": "SSE", "hex_opcode": "66 0F 6E /r", "visual_parts": [], "binary_pattern": "0F | 6E", "bit_positions": "+0 | +1"}, "extension": "MMX/SSE2", "operands": [{"name": "dest", "type": "mm/xmm", "desc": "64-bit MMX register or 128-bit XMM SIMD register"}, {"name": "src", "type": "r32/m32", "desc": "General-purpose register or Memory operand"}], "description": "Moves a 32-bit value from a general-purpose register or memory location into the lower 32 bits of an MMX or XMM register, zero-extending or copying the upper bits depending on context. When destination is MMX, the upper 32 bits become undefined; when destination is XMM, the upper 96 bits are zeroed (for SSE2 and later). No flags are affected. Supported in MMX and SSE2 extensions.", "pseudocode": "if (dest_is_xmm) {\n xmm[0:31] ← r32/m32[0:31];\n xmm[32:127] ← 0;\n} else {\n mm[0:31] ← r32/m32[0:31];\n}", "example": "MOVD mm/xmm, r32/m32"} {"mnemonic": "movq", "architecture": "x86", "full_name": "Move Quadword", "summary": "Moves 64 bits between XMM registers or memory.", "syntax": "MOVQ xmm, xmm/m64", "encoding": {"format": "SSE2", "hex_opcode": "F3 0F 7E", "visual_parts": [], "binary_pattern": "F3 | 0F | 7E", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m64", "desc": "128-bit XMM register or 64-bit memory"}], "description": "Moves a 64-bit quadword between XMM registers or from/to 64-bit memory. When the source is memory, only the lower 64 bits of the destination XMM register are updated and the upper 64 bits are zeroed. When both operands are XMM registers, all 128 bits of the destination are affected (lower 64 from source, upper 64 zeroed). No flags are affected. This instruction is part of SSE2 and later.", "pseudocode": "xmm_dest[0:63] ← xmm/m64[0:63];\nxmm_dest[64:127] ← 0;", "example": "MOVQ xmm0, xmm1"} {"mnemonic": "movaps", "architecture": "x86", "full_name": "Move Aligned Packed Single-Precision", "summary": "Moves 128-bit packed float data (Must be 16-byte aligned).", "syntax": "MOVAPS xmm, xmm/m128", "encoding": {"format": "SSE", "hex_opcode": "NP 0F 28 /r", "visual_parts": [], "binary_pattern": "0F | 28", "bit_positions": "+0 | +1"}, "extension": "SSE", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Moves 128 bits of packed single-precision floating-point data between XMM registers or between an XMM register and 16-byte aligned memory. The memory operand must be 16-byte aligned; unaligned memory access results in a general-protection exception (#GP). This is a cache-efficient operation for aligned data. No flags are affected. Supported in SSE and later extensions.", "pseudocode": "xmm_dest[0:127] ← xmm/m128[0:127];", "example": "MOVAPS xmm0, xmm1"} {"mnemonic": "movups", "architecture": "x86", "full_name": "Move Unaligned Packed Single-Precision", "summary": "Moves 128-bit packed float data (Unaligned).", "syntax": "MOVUPS xmm, xmm/m128", "encoding": {"format": "SSE", "hex_opcode": "NP 0F 10 /r", "visual_parts": [], "binary_pattern": "0F | 10", "bit_positions": "+0 | +1"}, "extension": "SSE", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Moves 128 bits of unaligned packed single-precision floating-point data from source to destination XMM register. No alignment requirement on memory operand. Does not affect any flags; operates only on XMM state.", "pseudocode": "dest[127:0] ← src[127:0]", "example": "MOVUPS xmm0, xmm1"} {"mnemonic": "movapd", "architecture": "x86", "full_name": "Move Aligned Packed Double-Precision", "summary": "Moves 128-bit packed double data (Must be 16-byte aligned).", "syntax": "MOVAPD xmm, xmm/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 28", "visual_parts": [], "binary_pattern": "66 | 0F | 28", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Moves 128 bits of aligned packed double-precision floating-point data from source to destination XMM register. Memory operand must be 16-byte aligned; unaligned access generates #GP(0). Does not affect any flags; operates only on XMM state.", "pseudocode": "dest[127:0] ← src[127:0]", "example": "MOVAPD xmm0, xmm1"} {"mnemonic": "movupd", "architecture": "x86", "full_name": "Move Unaligned Packed Double-Precision", "summary": "Moves 128-bit packed double data (Unaligned).", "syntax": "MOVUPD xmm, xmm/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 10", "visual_parts": [], "binary_pattern": "66 | 0F | 10", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Moves 128 bits of unaligned packed double-precision floating-point data from source to destination XMM register. No alignment requirement on memory operand. Does not affect any flags; operates only on XMM state.", "pseudocode": "dest[127:0] ← src[127:0]", "example": "MOVUPD xmm0, xmm1"} {"mnemonic": "movdqa", "architecture": "x86", "full_name": "Move Aligned Packed Integer", "summary": "Moves 128-bit integer data (Aligned).", "syntax": "MOVDQA xmm, xmm/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 6F", "visual_parts": [], "binary_pattern": "66 | 0F | 6F", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Moves 128 bits of aligned packed integer data from source to destination XMM register. Memory operand must be 16-byte aligned; unaligned access generates #GP(0). Does not affect any flags; operates only on XMM state.", "pseudocode": "dest[127:0] ← src[127:0]", "example": "MOVDQA xmm0, xmm1"} {"mnemonic": "movdqu", "architecture": "x86", "full_name": "Move Unaligned Packed Integer", "summary": "Moves 128-bit integer data (Unaligned).", "syntax": "MOVDQU xmm, xmm/m128", "encoding": {"format": "SSE2", "hex_opcode": "F3 0F 6F", "visual_parts": [], "binary_pattern": "F3 | 0F | 6F", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Moves 128 bits of unaligned packed integer data from source to destination XMM register. No alignment requirement on memory operand. Does not affect any flags; operates only on XMM state.", "pseudocode": "dest[127:0] ← src[127:0]", "example": "MOVDQU xmm0, xmm1"} {"mnemonic": "addps", "architecture": "x86", "full_name": "Add Packed Single-Precision", "summary": "Adds four 32-bit floats.", "syntax": "ADDPS xmm, xmm/m128", "encoding": {"format": "SSE", "hex_opcode": "NP 0F 58 /r", "visual_parts": [], "binary_pattern": "0F | 58", "bit_positions": "+0 | +1"}, "extension": "SSE", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Adds four 32-bit single-precision floating-point values element-wise from source to destination XMM register, storing results in destination. Each element addition produces IEEE 754 floating-point result; does not affect integer flags. Available in 128-bit (XMM) form.", "pseudocode": "dest[31:0] ← dest[31:0] + src[31:0]\ndest[63:32] ← dest[63:32] + src[63:32]\ndest[95:64] ← dest[95:64] + src[95:64]\ndest[127:96] ← dest[127:96] + src[127:96]", "example": "ADDPS xmm0, xmm1"} {"mnemonic": "addpd", "architecture": "x86", "full_name": "Add Packed Double-Precision", "summary": "Adds two 64-bit doubles.", "syntax": "ADDPD xmm, xmm/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 58", "visual_parts": [], "binary_pattern": "66 | 0F | 58", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Adds two 64-bit double-precision floating-point values element-wise from source to destination XMM register, storing results in destination. Each element addition produces IEEE 754 floating-point result; does not affect integer flags. Available in 128-bit (XMM) form.", "pseudocode": "dest[63:0] ← dest[63:0] + src[63:0]\ndest[127:64] ← dest[127:64] + src[127:64]", "example": "ADDPD xmm0, xmm1"} {"mnemonic": "addss", "architecture": "x86", "full_name": "Add Scalar Single-Precision", "summary": "Adds the low 32-bit float.", "syntax": "ADDSS xmm, xmm/m32", "encoding": {"format": "SSE", "hex_opcode": "F3 0F 58", "visual_parts": [], "binary_pattern": "F3 | 0F | 58", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m32", "desc": "128-bit XMM register or 32-bit memory"}], "description": "Adds the low 32-bit single-precision floating-point values from source to destination XMM register; upper three 32-bit elements of destination are unchanged. Scalar operation on lowest element; does not affect integer flags. Result follows IEEE 754 floating-point semantics.", "pseudocode": "dest[31:0] ← dest[31:0] + src[31:0]\ndest[127:32] ← dest[127:32]", "example": "ADDSS xmm0, xmm1"} {"mnemonic": "addsd", "architecture": "x86", "full_name": "Add Scalar Double-Precision", "summary": "Adds the low 64-bit double.", "syntax": "ADDSD xmm, xmm/m64", "encoding": {"format": "SSE2", "hex_opcode": "F2 0F 58", "visual_parts": [], "binary_pattern": "F2 | 0F | 58", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m64", "desc": "128-bit XMM register or 64-bit memory"}], "description": "Adds the low 64-bit double-precision floating-point value in the source operand to the low 64-bit double-precision value in the destination XMM register, storing the result in the destination. The high 64 bits of the destination remain unchanged. This instruction operates on scalar (single) values and respects IEEE 754 rounding modes controlled by MXCSR.", "pseudocode": "dest[63:0] ← dest[63:0] + src[63:0];\ndest[127:64] ← unchanged;", "example": "ADDSD xmm0, xmm1"} {"mnemonic": "subps", "architecture": "x86", "full_name": "Subtract Packed Single-Precision", "summary": "Subtracts four 32-bit floats.", "syntax": "SUBPS xmm, xmm/m128", "encoding": {"format": "SSE", "hex_opcode": "NP 0F 5C /r", "visual_parts": [], "binary_pattern": "0F | 5C", "bit_positions": "+0 | +1"}, "extension": "SSE", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Subtracts four 32-bit single-precision floating-point values in the source operand from the four 32-bit single-precision values in the destination XMM register, storing all four results in the destination. Operates on packed values in parallel and respects IEEE 754 rounding modes controlled by MXCSR.", "pseudocode": "dest[31:0] ← dest[31:0] - src[31:0];\ndest[63:32] ← dest[63:32] - src[63:32];\ndest[95:64] ← dest[95:64] - src[95:64];\ndest[127:96] ← dest[127:96] - src[127:96];", "example": "SUBPS xmm0, xmm1"} {"mnemonic": "subpd", "architecture": "x86", "full_name": "Subtract Packed Double-Precision", "summary": "Subtracts two 64-bit doubles.", "syntax": "SUBPD xmm, xmm/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 5C", "visual_parts": [], "binary_pattern": "66 | 0F | 5C", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Subtracts two 64-bit double-precision floating-point values in the source operand from the two 64-bit double-precision values in the destination XMM register, storing both results in the destination. Operates on packed values in parallel and respects IEEE 754 rounding modes controlled by MXCSR.", "pseudocode": "dest[63:0] ← dest[63:0] - src[63:0];\ndest[127:64] ← dest[127:64] - src[127:64];", "example": "SUBPD xmm0, xmm1"} {"mnemonic": "mulps", "architecture": "x86", "full_name": "Multiply Packed Single-Precision", "summary": "Multiplies four 32-bit floats.", "syntax": "MULPS xmm, xmm/m128", "encoding": {"format": "SSE", "hex_opcode": "NP 0F 59 /r", "visual_parts": [], "binary_pattern": "0F | 59", "bit_positions": "+0 | +1"}, "extension": "SSE", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Multiplies four 32-bit single-precision floating-point values in the source operand by the four 32-bit single-precision values in the destination XMM register, storing all four products in the destination. Operates on packed values in parallel and respects IEEE 754 rounding modes controlled by MXCSR.", "pseudocode": "dest[31:0] ← dest[31:0] * src[31:0];\ndest[63:32] ← dest[63:32] * src[63:32];\ndest[95:64] ← dest[95:64] * src[95:64];\ndest[127:96] ← dest[127:96] * src[127:96];", "example": "MULPS xmm0, xmm1"} {"mnemonic": "mulpd", "architecture": "x86", "full_name": "Multiply Packed Double-Precision", "summary": "Multiplies two 64-bit doubles.", "syntax": "MULPD xmm, xmm/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 59", "visual_parts": [], "binary_pattern": "66 | 0F | 59", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Multiplies two 64-bit double-precision floating-point values in the source operand by the two 64-bit double-precision values in the destination XMM register, storing both products in the destination. Operates on packed values in parallel and respects IEEE 754 rounding modes controlled by MXCSR.", "pseudocode": "dest[63:0] ← dest[63:0] * src[63:0];\ndest[127:64] ← dest[127:64] * src[127:64];", "example": "MULPD xmm0, xmm1"} {"mnemonic": "divps", "architecture": "x86", "full_name": "Divide Packed Single-Precision", "summary": "Divides four 32-bit floats.", "syntax": "DIVPS xmm, xmm/m128", "encoding": {"format": "SSE", "hex_opcode": "NP 0F 5E /r", "visual_parts": [], "binary_pattern": "0F | 5E", "bit_positions": "+0 | +1"}, "extension": "SSE", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Divides four 32-bit single-precision floating-point values in the destination XMM register by the four 32-bit single-precision values in the source operand, storing all four quotients in the destination. Operates on packed values in parallel and respects IEEE 754 rounding modes controlled by MXCSR; division by zero produces infinity or NaN according to IEEE 754 rules.", "pseudocode": "dest[31:0] ← dest[31:0] / src[31:0];\ndest[63:32] ← dest[63:32] / src[63:32];\ndest[95:64] ← dest[95:64] / src[95:64];\ndest[127:96] ← dest[127:96] / src[127:96];", "example": "DIVPS xmm0, xmm1"} {"mnemonic": "divpd", "architecture": "x86", "full_name": "Divide Packed Double-Precision", "summary": "Divides two 64-bit doubles.", "syntax": "DIVPD xmm, xmm/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 5E", "visual_parts": [], "binary_pattern": "66 | 0F | 5E", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Divides two 64-bit double-precision floating-point values in the destination XMM register by the two 64-bit double-precision values in the source operand, storing both quotients in the destination. Operates on packed values in parallel and respects IEEE 754 rounding modes controlled by MXCSR; division by zero produces infinity or NaN according to IEEE 754 rules.", "pseudocode": "dest[63:0] ← dest[63:0] / src[63:0];\ndest[127:64] ← dest[127:64] / src[127:64];", "example": "DIVPD xmm0, xmm1"} {"mnemonic": "sqrtps", "architecture": "x86", "full_name": "Square Root Packed Single-Precision", "summary": "Computes square root of four 32-bit floats.", "syntax": "SQRTPS xmm, xmm/m128", "encoding": {"format": "SSE", "hex_opcode": "NP 0F 51 /r", "visual_parts": [], "binary_pattern": "0F | 51", "bit_positions": "+0 | +1"}, "extension": "SSE", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Computes the square root of four 32-bit single-precision floating-point values in the source operand and stores all four results in the destination XMM register. Operates on packed values in parallel and respects IEEE 754 rounding modes controlled by MXCSR; negative values produce NaN according to IEEE 754 rules.", "pseudocode": "dest[31:0] ← sqrt(src[31:0]);\ndest[63:32] ← sqrt(src[63:32]);\ndest[95:64] ← sqrt(src[95:64]);\ndest[127:96] ← sqrt(src[127:96]);", "example": "SQRTPS xmm0, xmm1"} {"mnemonic": "sqrtpd", "architecture": "x86", "full_name": "Square Root Packed Double-Precision", "summary": "Computes square root of two 64-bit doubles.", "syntax": "SQRTPD xmm, xmm/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 51", "visual_parts": [], "binary_pattern": "66 | 0F | 51", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Computes the square root of two packed 64-bit double-precision floating-point values and stores the results in the destination XMM register. This instruction operates at the FPU execution unit and sets MXCSR exception flags according to IEEE 754 rounding mode and precision; no general-purpose flags are affected. Requires SSE2 support.", "pseudocode": "dest[0:63] ← sqrt(src[0:63])\ndest[64:127] ← sqrt(src[64:127])\nMXCSR exception flags ← updated based on IEEE 754 result", "example": "SQRTPD xmm0, xmm1"} {"mnemonic": "rcpps", "architecture": "x86", "full_name": "Reciprocal Packed Single-Precision", "summary": "Approximate reciprocal (1/x) of four 32-bit floats.", "syntax": "RCPPS xmm, xmm/m128", "encoding": {"format": "SSE", "hex_opcode": "NP 0F 53 /r", "visual_parts": [], "binary_pattern": "0F | 53", "bit_positions": "+0 | +1"}, "extension": "SSE", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Computes the approximate reciprocal (1/x) of four packed 32-bit single-precision floating-point values with a relative error of at most 1.5×2⁻¹² and stores results in the destination XMM register. This is a fast approximation instruction suitable for iterative refinement; no general-purpose flags are affected. Requires SSE support.", "pseudocode": "dest[0:31] ← approx_reciprocal(src[0:31])\ndest[32:63] ← approx_reciprocal(src[32:63])\ndest[64:95] ← approx_reciprocal(src[64:95])\ndest[96:127] ← approx_reciprocal(src[96:127])", "example": "RCPPS xmm0, xmm1"} {"mnemonic": "rsqrtps", "architecture": "x86", "full_name": "Reciprocal Square Root Packed Single-Precision", "summary": "Approximate reciprocal sqrt (1/sqrt(x)) of four 32-bit floats.", "syntax": "RSQRTPS xmm, xmm/m128", "encoding": {"format": "SSE", "hex_opcode": "NP 0F 52 /r", "visual_parts": [], "binary_pattern": "0F | 52", "bit_positions": "+0 | +1"}, "extension": "SSE", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Computes the approximate reciprocal square root (1/√x) of four packed 32-bit single-precision floating-point values with a relative error of at most 1.5×2⁻¹² and stores results in the destination XMM register. This is a fast approximation instruction useful for physics simulations and graphics; no general-purpose flags are affected. Requires SSE support.", "pseudocode": "dest[0:31] ← approx_reciprocal_sqrt(src[0:31])\ndest[32:63] ← approx_reciprocal_sqrt(src[32:63])\ndest[64:95] ← approx_reciprocal_sqrt(src[64:95])\ndest[96:127] ← approx_reciprocal_sqrt(src[96:127])", "example": "RSQRTPS xmm0, xmm1"} {"mnemonic": "maxps", "architecture": "x86", "full_name": "Maximum Packed Single-Precision", "summary": "Returns maximum of packed floats.", "syntax": "MAXPS xmm, xmm/m128", "encoding": {"format": "SSE", "hex_opcode": "NP 0F 5F /r", "visual_parts": [], "binary_pattern": "0F | 5F", "bit_positions": "+0 | +1"}, "extension": "SSE", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Compares four packed 32-bit single-precision floating-point values element-wise and stores the maximum of each pair in the destination XMM register. Special values (NaN, signed zeros) follow IEEE 754 comparison semantics; no general-purpose flags are affected. Requires SSE support.", "pseudocode": "dest[0:31] ← max(dest[0:31], src[0:31])\ndest[32:63] ← max(dest[32:63], src[32:63])\ndest[64:95] ← max(dest[64:95], src[64:95])\ndest[96:127] ← max(dest[96:127], src[96:127])", "example": "MAXPS xmm0, xmm1"} {"mnemonic": "minps", "architecture": "x86", "full_name": "Minimum Packed Single-Precision", "summary": "Returns minimum of packed floats.", "syntax": "MINPS xmm, xmm/m128", "encoding": {"format": "SSE", "hex_opcode": "NP 0F 5D /r", "visual_parts": [], "binary_pattern": "0F | 5D", "bit_positions": "+0 | +1"}, "extension": "SSE", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Compares four packed 32-bit single-precision floating-point values element-wise and stores the minimum of each pair in the destination XMM register. Special values (NaN, signed zeros) follow IEEE 754 comparison semantics; no general-purpose flags are affected. Requires SSE support.", "pseudocode": "dest[0:31] ← min(dest[0:31], src[0:31])\ndest[32:63] ← min(dest[32:63], src[32:63])\ndest[64:95] ← min(dest[64:95], src[64:95])\ndest[96:127] ← min(dest[96:127], src[96:127])", "example": "MINPS xmm0, xmm1"} {"mnemonic": "andps", "architecture": "x86", "full_name": "Bitwise Logical AND Packed Single-Precision", "summary": "Bitwise AND of 128 bits.", "syntax": "ANDPS xmm, xmm/m128", "encoding": {"format": "SSE", "hex_opcode": "NP 0F 54 /r", "visual_parts": [], "binary_pattern": "0F | 54", "bit_positions": "+0 | +1"}, "extension": "SSE", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Performs a bitwise logical AND of all 128 bits in the destination and source XMM registers and stores the result in the destination. This is a pure logical operation treating the packed single-precision floats as integer bit patterns; no general-purpose flags are affected. Requires SSE support.", "pseudocode": "dest[0:127] ← dest[0:127] AND src[0:127]", "example": "ANDPS xmm0, xmm1"} {"mnemonic": "andpd", "architecture": "x86", "full_name": "Bitwise Logical AND Packed Double-Precision", "summary": "Bitwise AND of 128 bits.", "syntax": "ANDPD xmm, xmm/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 54", "visual_parts": [], "binary_pattern": "66 | 0F | 54", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Performs a bitwise logical AND of all 128 bits in the destination and source XMM registers and stores the result in the destination. This is a pure logical operation treating the packed double-precision floats as integer bit patterns; no general-purpose flags are affected. Requires SSE2 support.", "pseudocode": "dest[0:127] ← dest[0:127] AND src[0:127]", "example": "ANDPD xmm0, xmm1"} {"mnemonic": "orps", "architecture": "x86", "full_name": "Bitwise Logical OR Packed Single-Precision", "summary": "Bitwise OR of 128 bits.", "syntax": "ORPS xmm, xmm/m128", "encoding": {"format": "SSE", "hex_opcode": "NP 0F 56 /r", "visual_parts": [], "binary_pattern": "0F | 56", "bit_positions": "+0 | +1"}, "extension": "SSE", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Performs a bitwise logical OR of all 128 bits in the destination and source XMM registers and stores the result in the destination. This is a pure logical operation treating the packed single-precision floats as integer bit patterns; no general-purpose flags are affected. Requires SSE support.", "pseudocode": "dest[0:127] ← dest[0:127] OR src[0:127]", "example": "ORPS xmm0, xmm1"} {"mnemonic": "xorps", "architecture": "x86", "full_name": "Bitwise Logical XOR Packed Single-Precision", "summary": "Bitwise XOR of 128 bits (Used to clear registers).", "syntax": "XORPS xmm, xmm/m128", "encoding": {"format": "SSE", "hex_opcode": "NP 0F 57 /r", "visual_parts": [], "binary_pattern": "0F | 57", "bit_positions": "+0 | +1"}, "extension": "SSE", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Performs a bitwise XOR of two 128-bit packed single-precision floating-point values, storing the result in the destination XMM register. No flags are affected by this operation. This instruction is commonly used to zero XMM registers efficiently (xorps xmm0, xmm0) as a dependency-breaking micro-optimization.", "pseudocode": "dest ← dest XOR src", "example": "XORPS xmm0, xmm1"} {"mnemonic": "paddb", "architecture": "x86", "full_name": "Packed Add Bytes", "summary": "Adds 16 bytes (Wraparound).", "syntax": "PADDB xmm, xmm/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F FC", "visual_parts": [], "binary_pattern": "66 | 0F | FC", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Performs 16 independent 8-bit unsigned or signed integer additions in parallel on packed byte data, wrapping on overflow without affecting flags. Results are stored in the destination XMM register with no saturation; overflow is silent and wraps modulo 256.", "pseudocode": "for i = 0 to 15:\n dest[i*8 + 7 : i*8] ← (dest[i*8 + 7 : i*8] + src[i*8 + 7 : i*8]) AND 0xFF", "example": "PADDB xmm0, xmm1"} {"mnemonic": "paddw", "architecture": "x86", "full_name": "Packed Add Words", "summary": "Adds 8 words (Wraparound).", "syntax": "PADDW xmm, xmm/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F FD", "visual_parts": [], "binary_pattern": "66 | 0F | FD", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Performs 8 independent 16-bit unsigned or signed integer additions in parallel on packed word data, wrapping on overflow without affecting flags. Results are stored in the destination XMM register with no saturation; overflow wraps modulo 65536.", "pseudocode": "for i = 0 to 7:\n dest[i*16 + 15 : i*16] ← (dest[i*16 + 15 : i*16] + src[i*16 + 15 : i*16]) AND 0xFFFF", "example": "PADDW xmm0, xmm1"} {"mnemonic": "paddd", "architecture": "x86", "full_name": "Packed Add Doublewords", "summary": "Adds 4 doublewords (Wraparound).", "syntax": "PADDD xmm, xmm/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F FE", "visual_parts": [], "binary_pattern": "66 | 0F | FE", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Performs 4 independent 32-bit unsigned or signed integer additions in parallel on packed doubleword data, wrapping on overflow without affecting flags. Results are stored in the destination XMM register with no saturation; overflow wraps modulo 2^32.", "pseudocode": "for i = 0 to 3:\n dest[i*32 + 31 : i*32] ← (dest[i*32 + 31 : i*32] + src[i*32 + 31 : i*32]) AND 0xFFFFFFFF", "example": "PADDD xmm0, xmm1"} {"mnemonic": "paddq", "architecture": "x86", "full_name": "Packed Add Quadwords", "summary": "Adds 2 quadwords (Wraparound).", "syntax": "PADDQ xmm, xmm/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F D4", "visual_parts": [], "binary_pattern": "66 | 0F | D4", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Performs 2 independent 64-bit unsigned or signed integer additions in parallel on packed quadword data, wrapping on overflow without affecting flags. Results are stored in the destination XMM register with no saturation; overflow wraps modulo 2^64.", "pseudocode": "for i = 0 to 1:\n dest[i*64 + 63 : i*64] ← (dest[i*64 + 63 : i*64] + src[i*64 + 63 : i*64]) AND 0xFFFFFFFFFFFFFFFF", "example": "PADDQ xmm0, xmm1"} {"mnemonic": "paddsb", "architecture": "x86", "full_name": "Packed Add Bytes Signed Saturate", "summary": "Adds 16 signed bytes with saturation.", "syntax": "PADDSB xmm, xmm/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F EC", "visual_parts": [], "binary_pattern": "66 | 0F | EC", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Performs 16 independent 8-bit signed integer additions in parallel with signed saturation on packed byte data. If the result overflows or underflows the signed 8-bit range [-128, 127], the value is clamped to the nearest boundary; no flags are affected.", "pseudocode": "for i = 0 to 15:\n temp ← (int32)(int8)dest[i*8 + 7 : i*8] + (int32)(int8)src[i*8 + 7 : i*8]\n if temp > 127: dest[i*8 + 7 : i*8] ← 127\n else if temp < -128: dest[i*8 + 7 : i*8] ← -128\n else: dest[i*8 + 7 : i*8] ← temp AND 0xFF", "example": "PADDSB xmm0, xmm1"} {"mnemonic": "paddusb", "architecture": "x86", "full_name": "Packed Add Bytes Unsigned Saturate", "summary": "Adds 16 unsigned bytes with saturation.", "syntax": "PADDUSB xmm, xmm/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F DC", "visual_parts": [], "binary_pattern": "66 | 0F | DC", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Performs 16 independent 8-bit unsigned integer additions in parallel with unsigned saturation on packed byte data. If the result exceeds 255, the value is clamped to 255; no flags are affected.", "pseudocode": "for i = 0 to 15:\n temp ← (uint16)dest[i*8 + 7 : i*8] + (uint16)src[i*8 + 7 : i*8]\n if temp > 255: dest[i*8 + 7 : i*8] ← 255\n else: dest[i*8 + 7 : i*8] ← temp AND 0xFF", "example": "PADDUSB xmm0, xmm1"} {"mnemonic": "psubb", "architecture": "x86", "full_name": "Packed Subtract Bytes", "summary": "Subtracts 16 bytes.", "syntax": "PSUBB xmm, xmm/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F F8", "visual_parts": [], "binary_pattern": "66 | 0F | F8", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Performs 16 independent 8-bit unsigned or signed integer subtractions in parallel on packed byte data, wrapping on underflow without affecting flags. Results are stored in the destination XMM register with no saturation; underflow wraps modulo 256.", "pseudocode": "for i = 0 to 15:\n dest[i*8 + 7 : i*8] ← (dest[i*8 + 7 : i*8] - src[i*8 + 7 : i*8]) AND 0xFF", "example": "PSUBB xmm0, xmm1"} {"mnemonic": "psubw", "architecture": "x86", "full_name": "Packed Subtract Words", "summary": "Subtracts 8 words.", "syntax": "PSUBW xmm, xmm/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F F9", "visual_parts": [], "binary_pattern": "66 | 0F | F9", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Subtracts packed 16-bit words element-wise: each of the 8 words in the destination XMM register is decremented by the corresponding word in the source XMM register or 128-bit memory operand, with wrapping on underflow. No flags are affected; the operation is performed modulo 2^16 for each element.", "pseudocode": "for i = 0 to 7 do\n dest.word[i] ← (dest.word[i] - src.word[i]) mod 2^16\nend for", "example": "PSUBW xmm0, xmm1"} {"mnemonic": "psubd", "architecture": "x86", "full_name": "Packed Subtract Doublewords", "summary": "Subtracts 4 doublewords.", "syntax": "PSUBD xmm, xmm/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F FA", "visual_parts": [], "binary_pattern": "66 | 0F | FA", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Subtracts packed 32-bit doublewords element-wise: each of the 4 doublewords in the destination XMM register is decremented by the corresponding doubleword in the source XMM register or 128-bit memory operand, with wrapping on underflow. No flags are affected; the operation is performed modulo 2^32 for each element.", "pseudocode": "for i = 0 to 3 do\n dest.dword[i] ← (dest.dword[i] - src.dword[i]) mod 2^32\nend for", "example": "PSUBD xmm0, xmm1"} {"mnemonic": "pand", "architecture": "x86", "full_name": "Packed Logical AND", "summary": "Bitwise AND of 128-bit integers.", "syntax": "PAND xmm, xmm/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F DB", "visual_parts": [], "binary_pattern": "66 | 0F | DB", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Performs a bitwise logical AND operation on the entire 128-bit content of the destination XMM register with the source XMM register or 128-bit memory operand, storing the result back in the destination. No flags are affected; the operation is a pure bitwise AND with no carry or borrow semantics.", "pseudocode": "dest ← dest AND src", "example": "PAND xmm0, xmm1"} {"mnemonic": "por", "architecture": "x86", "full_name": "Packed Logical OR", "summary": "Bitwise OR of 128-bit integers.", "syntax": "POR xmm, xmm/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F EB", "visual_parts": [], "binary_pattern": "66 | 0F | EB", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Performs a bitwise logical OR operation on the entire 128-bit content of the destination XMM register with the source XMM register or 128-bit memory operand, storing the result back in the destination. No flags are affected; the operation is a pure bitwise OR with no carry or borrow semantics.", "pseudocode": "dest ← dest OR src", "example": "POR xmm0, xmm1"} {"mnemonic": "pxor", "architecture": "x86", "full_name": "Packed Logical Exclusive OR", "summary": "Bitwise XOR of 128-bit integers.", "syntax": "PXOR xmm, xmm/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F EF", "visual_parts": [], "binary_pattern": "66 | 0F | EF", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Performs a bitwise logical exclusive OR operation on the entire 128-bit content of the destination XMM register with the source XMM register or 128-bit memory operand, storing the result back in the destination. No flags are affected; the operation is a pure bitwise XOR with no carry or borrow semantics.", "pseudocode": "dest ← dest XOR src", "example": "PXOR xmm0, xmm1"} {"mnemonic": "psllw", "architecture": "x86", "full_name": "Packed Shift Left Logical Word", "summary": "Shifts words left.", "syntax": "PSLLW xmm, imm8", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 71 /6", "visual_parts": [], "binary_pattern": "66 | 0F | 71 | ModRM", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Shifts each of the 8 packed 16-bit words in the destination XMM register left logically by the number of bits specified in the 8-bit immediate operand, with zero fill on the right. Shift amounts greater than or equal to 16 zero out the corresponding word. No flags are affected.", "pseudocode": "count ← imm8 AND 0xFF\nfor i = 0 to 7 do\n if count >= 16 then\n dest.word[i] ← 0\n else\n dest.word[i] ← (dest.word[i] << count) AND 0xFFFF\n end if\nend for", "example": "PSLLW xmm0, 3"} {"mnemonic": "pslld", "architecture": "x86", "full_name": "Packed Shift Left Logical Doubleword", "summary": "Shifts doublewords left.", "syntax": "PSLLD xmm, imm8", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 72 /6", "visual_parts": [], "binary_pattern": "66 | 0F | 72 | ModRM", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Shifts each of the 4 packed 32-bit doublewords in the destination XMM register left logically by the number of bits specified in the 8-bit immediate operand, with zero fill on the right. Shift amounts greater than or equal to 32 zero out the corresponding doubleword. No flags are affected.", "pseudocode": "count ← imm8 AND 0xFF\nfor i = 0 to 3 do\n if count >= 32 then\n dest.dword[i] ← 0\n else\n dest.dword[i] ← (dest.dword[i] << count) AND 0xFFFFFFFF\n end if\nend for", "example": "PSLLD xmm0, 3"} {"mnemonic": "psrlw", "architecture": "x86", "full_name": "Packed Shift Right Logical Word", "summary": "Shifts words right logical.", "syntax": "PSRLW xmm, imm8", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 71 /2", "visual_parts": [], "binary_pattern": "66 | 0F | 71 | ModRM", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Shifts each of the 8 packed 16-bit words in the destination XMM register right logically (unsigned) by the number of bits specified in the 8-bit immediate operand, with zero fill on the left. Shift amounts greater than or equal to 16 zero out the corresponding word. No flags are affected.", "pseudocode": "count ← imm8 AND 0xFF\nfor i = 0 to 7 do\n if count >= 16 then\n dest.word[i] ← 0\n else\n dest.word[i] ← (dest.word[i] >> count) AND 0xFFFF\n end if\nend for", "example": "PSRLW xmm0, 3"} {"mnemonic": "psrld", "architecture": "x86", "full_name": "Packed Shift Right Logical Doubleword", "summary": "Shifts doublewords right logical.", "syntax": "PSRLD xmm, imm8", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 72 /2", "visual_parts": [], "binary_pattern": "66 | 0F | 72 | ModRM", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Shifts each 32-bit doubleword element in the XMM register right logically by the count specified in the immediate value. Bits shifted out are discarded, and vacated positions are filled with zeros. No flags are affected. Available in SSE2 and later; operates on 128-bit packed data (four 32-bit elements).", "pseudocode": "for i ← 0 to 3 do\n xmm.dword[i] ← xmm.dword[i] >> imm8\nend for", "example": "PSRLD xmm0, 3"} {"mnemonic": "psraw", "architecture": "x86", "full_name": "Packed Shift Right Arithmetic Word", "summary": "Shifts words right arithmetic (sign bit).", "syntax": "PSRAW xmm, imm8", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 71 /4", "visual_parts": [], "binary_pattern": "66 | 0F | 71 | ModRM", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Shifts each 16-bit word element in the XMM register right arithmetically by the count specified in the immediate value. The sign bit is replicated into vacated positions. No flags are affected. Available in SSE2 and later; operates on 128-bit packed data (eight 16-bit elements).", "pseudocode": "for i ← 0 to 7 do\n sign_bit ← xmm.word[i][15]\n xmm.word[i] ← arithmetic_shift_right(xmm.word[i], imm8)\n if imm8 >= 16 then xmm.word[i] ← sign_bit ? 0xFFFF : 0x0000 end if\nend for", "example": "PSRAW xmm0, 3"} {"mnemonic": "psrad", "architecture": "x86", "full_name": "Packed Shift Right Arithmetic Doubleword", "summary": "Shifts doublewords right arithmetic.", "syntax": "PSRAD xmm, imm8", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 72 /4", "visual_parts": [], "binary_pattern": "66 | 0F | 72 | ModRM", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Shifts each 32-bit doubleword element in the XMM register right arithmetically by the count specified in the immediate value. The sign bit is replicated into vacated positions. No flags are affected. Available in SSE2 and later; operates on 128-bit packed data (four 32-bit elements).", "pseudocode": "for i ← 0 to 3 do\n sign_bit ← xmm.dword[i][31]\n xmm.dword[i] ← arithmetic_shift_right(xmm.dword[i], imm8)\n if imm8 >= 32 then xmm.dword[i] ← sign_bit ? 0xFFFFFFFF : 0x00000000 end if\nend for", "example": "PSRAD xmm0, 3"} {"mnemonic": "pcmpeqb", "architecture": "x86", "full_name": "Packed Compare Equal Byte", "summary": "Compares bytes for equality (Result mask 0xFF or 0x00).", "syntax": "PCMPEQB xmm, xmm/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 74", "visual_parts": [], "binary_pattern": "66 | 0F | 74", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Performs a packed comparison for equality on 8-bit byte elements. For each byte position, the result is 0xFF if the elements are equal, or 0x00 if they are not equal. No traditional flags (OF, SF, ZF, etc.) are affected; results are stored in the destination register. Available in SSE2 and later; operates on 128-bit vectors (sixteen 8-bit elements).", "pseudocode": "for i ← 0 to 15 do\n if dest.byte[i] == src.byte[i] then\n dest.byte[i] ← 0xFF\n else\n dest.byte[i] ← 0x00\n end if\nend for", "example": "PCMPEQB xmm0, xmm1"} {"mnemonic": "pcmpeqw", "architecture": "x86", "full_name": "Packed Compare Equal Word", "summary": "Compares words for equality.", "syntax": "PCMPEQW xmm, xmm/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 75", "visual_parts": [], "binary_pattern": "66 | 0F | 75", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Performs a packed comparison for equality on 16-bit word elements. For each word position, the result is 0xFFFF if the elements are equal, or 0x0000 if they are not equal. No traditional flags are affected; results are stored in the destination register. Available in SSE2 and later; operates on 128-bit vectors (eight 16-bit elements).", "pseudocode": "for i ← 0 to 7 do\n if dest.word[i] == src.word[i] then\n dest.word[i] ← 0xFFFF\n else\n dest.word[i] ← 0x0000\n end if\nend for", "example": "PCMPEQW xmm0, xmm1"} {"mnemonic": "pcmpeqd", "architecture": "x86", "full_name": "Packed Compare Equal Doubleword", "summary": "Compares doublewords for equality.", "syntax": "PCMPEQD xmm, xmm/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 76", "visual_parts": [], "binary_pattern": "66 | 0F | 76", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Performs a packed comparison for equality on 32-bit doubleword elements. For each doubleword position, the result is 0xFFFFFFFF if the elements are equal, or 0x00000000 if they are not equal. No traditional flags are affected; results are stored in the destination register. Available in SSE2 and later; operates on 128-bit vectors (four 32-bit elements).", "pseudocode": "for i ← 0 to 3 do\n if dest.dword[i] == src.dword[i] then\n dest.dword[i] ← 0xFFFFFFFF\n else\n dest.dword[i] ← 0x00000000\n end if\nend for", "example": "PCMPEQD xmm0, xmm1"} {"mnemonic": "pshufd", "architecture": "x86", "full_name": "Packed Shuffle Doubleword", "summary": "Shuffles 32-bit integers.", "syntax": "PSHUFD xmm, xmm/m128, imm8", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 70", "visual_parts": [], "binary_pattern": "66 | 0F | 70", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src1", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Rearranges the four 32-bit doubleword elements in an XMM register according to the shuffle pattern encoded in the 8-bit immediate operand. Each pair of bits in the immediate selects which source doubleword populates each destination position. No flags are affected. Available in SSE2 and later; operates on 128-bit vectors.", "pseudocode": "temp ← src\nfor i ← 0 to 3 do\n selector ← (imm8 >> (i * 2)) & 0x3\n dest.dword[i] ← temp.dword[selector]\nend for", "example": "PSHUFD xmm0, xmm1, 3"} {"mnemonic": "cvtsi2ss", "architecture": "x86", "full_name": "Convert Doubleword Integer to Scalar Single-Precision", "summary": "Converts 32-bit int to float.", "syntax": "CVTSI2SS xmm, r/m32", "encoding": {"format": "SSE", "hex_opcode": "F3 0F 2A", "visual_parts": [], "binary_pattern": "F3 | 0F | 2A", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "r/m32", "desc": "32-bit register or memory"}], "description": "Converts a 32-bit signed integer operand to a scalar single-precision floating-point value and stores the result in the low 32-bit lane of the destination XMM register, leaving the upper 96 bits unchanged. No traditional flags are affected. Available in SSE and later; the conversion follows IEEE 754 rounding rules.", "pseudocode": "src_int ← [src] (sign-extended if r/m32)\nfp_value ← convert_int32_to_float(src_int)\ndest.float32[0] ← fp_value\n// dest.float32[1..3] unchanged", "example": "CVTSI2SS xmm0, ebx"} {"mnemonic": "cvtsi2sd", "architecture": "x86", "full_name": "Convert Doubleword Integer to Scalar Double-Precision", "summary": "Converts 32-bit int to double.", "syntax": "CVTSI2SD xmm, r/m32", "encoding": {"format": "SSE2", "hex_opcode": "F2 0F 2A", "visual_parts": [], "binary_pattern": "F2 | 0F | 2A", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "r/m32", "desc": "32-bit register or memory"}], "description": "Converts a 32-bit signed integer to a 64-bit double-precision floating-point value and stores the result in the low 64 bits of the destination XMM register, leaving the upper 64 bits unchanged. The conversion uses the current rounding mode from MXCSR. No EFLAGS are affected by this instruction.", "pseudocode": "dest.low64 ← (double)src32;", "example": "CVTSI2SD xmm0, ebx"} {"mnemonic": "cvttss2si", "architecture": "x86", "full_name": "Convert with Truncation Scalar Single to Integer", "summary": "Converts float to 32-bit int (Truncate).", "syntax": "CVTTSS2SI r32, xmm/m32", "encoding": {"format": "SSE", "hex_opcode": "F3 0F 2C", "visual_parts": [], "binary_pattern": "F3 | 0F | 2C", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src", "type": "xmm/m32", "desc": "128-bit XMM register or 32-bit memory"}], "description": "Converts a 32-bit single-precision floating-point value to a 32-bit signed integer using truncation towards zero, regardless of the rounding mode in MXCSR. If a NaN or overflow occurs, the result is INT32_MIN (0x80000000) and no exception is raised by default.", "pseudocode": "dest32 ← (int32)truncate(src32_float); CF ← 0; OF ← 0; SF ← 0; ZF ← 0; AF ← 0; PF ← 0;", "example": "CVTTSS2SI eax, xmm1"} {"mnemonic": "cvttsd2si", "architecture": "x86", "full_name": "Convert with Truncation Scalar Double to Integer", "summary": "Converts double to 32-bit int (Truncate).", "syntax": "CVTTSD2SI r32, xmm/m64", "encoding": {"format": "SSE2", "hex_opcode": "F2 0F 2C", "visual_parts": [], "binary_pattern": "F2 | 0F | 2C", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src", "type": "xmm/m64", "desc": "128-bit XMM register or 64-bit memory"}], "description": "Converts a 64-bit double-precision floating-point value to a 32-bit signed integer using truncation towards zero, independent of the MXCSR rounding mode. If a NaN or overflow occurs, the result is INT32_MIN (0x80000000) with no exception raised by default.", "pseudocode": "dest32 ← (int32)truncate(src64_double); CF ← 0; OF ← 0; SF ← 0; ZF ← 0; AF ← 0; PF ← 0;", "example": "CVTTSD2SI eax, xmm1"} {"mnemonic": "cvtss2sd", "architecture": "x86", "full_name": "Convert Scalar Single to Scalar Double", "summary": "Converts float to double.", "syntax": "CVTSS2SD xmm, xmm/m32", "encoding": {"format": "SSE2", "hex_opcode": "F3 0F 5A", "visual_parts": [], "binary_pattern": "F3 | 0F | 5A", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m32", "desc": "128-bit XMM register or 32-bit memory"}], "description": "Converts a 32-bit single-precision floating-point value to a 64-bit double-precision floating-point value and stores the result in the low 64 bits of the destination XMM register, preserving the upper 64 bits. The conversion uses the current rounding mode from MXCSR, though single-to-double conversion is typically lossless.", "pseudocode": "dest.low64 ← (double)src32_float;", "example": "CVTSS2SD xmm0, xmm1"} {"mnemonic": "cvtsd2ss", "architecture": "x86", "full_name": "Convert Scalar Double to Scalar Single", "summary": "Converts double to float.", "syntax": "CVTSD2SS xmm, xmm/m64", "encoding": {"format": "SSE2", "hex_opcode": "F2 0F 5A", "visual_parts": [], "binary_pattern": "F2 | 0F | 5A", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m64", "desc": "128-bit XMM register or 64-bit memory"}], "description": "Converts a 64-bit double-precision floating-point value to a 32-bit single-precision floating-point value and stores the result in the low 32 bits of the destination XMM register, leaving bits 32-127 unchanged. The conversion uses the current rounding mode from MXCSR and may result in precision loss or denormalized results.", "pseudocode": "dest.low32 ← (float)src64_double;", "example": "CVTSD2SS xmm0, xmm1"} {"mnemonic": "ucomiss", "architecture": "x86", "full_name": "Unordered Compare Scalar Single-Precision", "summary": "Compares low float and sets EFLAGS.", "syntax": "UCOMISS xmm1, xmm2/m32", "encoding": {"format": "SSE", "hex_opcode": "NP 0F 2E /r", "visual_parts": [], "binary_pattern": "0F | 2E", "bit_positions": "+0 | +1"}, "extension": "SSE", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m32", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Performs an unordered comparison of two single-precision floating-point values and sets EFLAGS (ZF, PF, CF) based on the result. If either operand is a signaling NaN, the comparison is treated as unordered; quiet NaNs also produce an unordered result. EFLAGS are set such that ZF=1, PF=1, CF=1 for unordered, ZF=0 for less, ZF=0 CF=1 for greater, and ZF=1 for equal.", "pseudocode": "cmp_result ← unordered_compare(dest.low32_float, src.low32_float); ZF ← (cmp_result == equal); PF ← (cmp_result == unordered); CF ← (cmp_result == less || cmp_result == unordered); AF ← 0; OF ← 0; SF ← 0;", "example": "UCOMISS xmm1, xmm2/m32"} {"mnemonic": "ucomisd", "architecture": "x86", "full_name": "Unordered Compare Scalar Double-Precision", "summary": "Compares low double and sets EFLAGS.", "syntax": "UCOMISD xmm1, xmm2/m64", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 2E", "visual_parts": [], "binary_pattern": "66 | 0F | 2E", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m64", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Performs an unordered comparison of two double-precision floating-point values and sets EFLAGS (ZF, PF, CF) based on the result. If either operand is a signaling NaN, the comparison is unordered; quiet NaNs also produce an unordered result. EFLAGS reflect unordered (ZF=PF=CF=1), less, greater, or equal conditions.", "pseudocode": "cmp_result ← unordered_compare(dest.low64_double, src.low64_double); ZF ← (cmp_result == equal); PF ← (cmp_result == unordered); CF ← (cmp_result == less || cmp_result == unordered); AF ← 0; OF ← 0; SF ← 0;", "example": "UCOMISD xmm1, xmm2/m64"} {"mnemonic": "punpcklbw", "architecture": "x86", "full_name": "Unpack Low Data Bytes", "summary": "Interleaves low bytes from two sources.", "syntax": "PUNPCKLBW xmm, xmm/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 60", "visual_parts": [], "binary_pattern": "66 | 0F | 60", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Interleaves the low 64 bits (8 bytes) of the destination and source XMM registers, expanding them to 128 bits with alternating bytes from each source: byte 0 from dest, byte 0 from src, byte 1 from dest, byte 1 from src, and so on. No EFLAGS are affected.", "pseudocode": "for i ← 0 to 7 do dest.byte[2*i] ← dest.byte[i]; dest.byte[2*i+1] ← src.byte[i];", "example": "PUNPCKLBW xmm0, xmm1"} {"mnemonic": "punpcklwd", "architecture": "x86", "full_name": "Unpack Low Data Words", "summary": "Interleaves low words.", "syntax": "PUNPCKLWD xmm, xmm/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 61", "visual_parts": [], "binary_pattern": "66 | 0F | 61", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Interleaves the low 64 bits (4 words) of the destination XMM register with the low 64 bits (4 words) of the source XMM/memory operand, placing results back in the destination. No flags are affected. This SSE2 instruction operates on 128-bit packed word data and is available in 64-bit and protected modes.", "pseudocode": "dest[127:0] = [dest[47:32], src[47:32], dest[31:16], src[31:16], dest[15:0], src[15:0], dest[63:48], src[63:48]]", "example": "PUNPCKLWD xmm0, xmm1"} {"mnemonic": "punpckldq", "architecture": "x86", "full_name": "Unpack Low Data Doublewords", "summary": "Interleaves low doublewords.", "syntax": "PUNPCKLDQ xmm, xmm/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 62", "visual_parts": [], "binary_pattern": "66 | 0F | 62", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Interleaves the low 64 bits (2 doublewords) of the destination XMM register with the low 64 bits (2 doublewords) of the source XMM/memory operand, placing results back in the destination. No flags are affected. This SSE2 instruction operates on 128-bit packed doubleword data and is available in 64-bit and protected modes.", "pseudocode": "dest[127:0] = [dest[31:0], src[31:0], dest[63:32], src[63:32]]", "example": "PUNPCKLDQ xmm0, xmm1"} {"mnemonic": "punpcklqdq", "architecture": "x86", "full_name": "Unpack Low Data Quadwords", "summary": "Interleaves low quadwords.", "syntax": "PUNPCKLQDQ xmm, xmm/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 6C", "visual_parts": [], "binary_pattern": "66 | 0F | 6C", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Interleaves the low 64 bits (1 quadword) of the destination XMM register with the low 64 bits (1 quadword) of the source XMM/memory operand, placing results back in the destination. No flags are affected. This SSE2 instruction operates on 128-bit packed quadword data and is available in 64-bit and protected modes.", "pseudocode": "dest[127:0] = [dest[63:0], src[63:0]]", "example": "PUNPCKLQDQ xmm0, xmm1"} {"mnemonic": "packsswb", "architecture": "x86", "full_name": "Pack with Signed Saturation Word to Byte", "summary": "Converts words to bytes with saturation.", "syntax": "PACKSSWB xmm, xmm/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 63", "visual_parts": [], "binary_pattern": "66 | 0F | 63", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Packs 8 signed word values from the destination and source XMM registers into 16 signed byte values using signed saturation, storing the result in the destination. Values outside the range [-128, 127] are clamped to the boundaries. No flags are affected. This SSE2 instruction is available in 64-bit and protected modes.", "pseudocode": "for i in 0..7:\n dest[8*i+7:8*i] = SaturateSignedWordToByte(dest[16*i+15:16*i])\nfor i in 0..7:\n dest[8*(i+8)+7:8*(i+8)] = SaturateSignedWordToByte(src[16*i+15:16*i])", "example": "PACKSSWB xmm0, xmm1"} {"mnemonic": "packssdw", "architecture": "x86", "full_name": "Pack with Signed Saturation Doubleword to Word", "summary": "Converts doublewords to words with saturation.", "syntax": "PACKSSDW xmm, xmm/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 6B", "visual_parts": [], "binary_pattern": "66 | 0F | 6B", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm/m128", "desc": "128-bit XMM register or 128-bit memory"}], "description": "Packs 4 signed doubleword values from the destination and source XMM registers into 8 signed word values using signed saturation, storing the result in the destination. Values outside the range [-32768, 32767] are clamped to the boundaries. No flags are affected. This SSE2 instruction is available in 64-bit and protected modes.", "pseudocode": "for i in 0..3:\n dest[16*i+15:16*i] = SaturateSignedDwordToWord(dest[32*i+31:32*i])\nfor i in 0..3:\n dest[16*(i+4)+15:16*(i+4)] = SaturateSignedDwordToWord(src[32*i+31:32*i])", "example": "PACKSSDW xmm0, xmm1"} {"mnemonic": "pmovmskb", "architecture": "x86", "full_name": "Move Byte Mask", "summary": "Creates a mask from the MSB of each byte in XMM.", "syntax": "PMOVMSKB r32, xmm", "encoding": {"format": "SSE2", "hex_opcode": "66 0F D7", "visual_parts": [], "binary_pattern": "66 | 0F | D7", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}], "description": "Extracts the most significant bit from each of the 16 bytes in the source XMM register and packs them into the low 16 bits of the destination 32-bit register; the upper 16 bits of the destination are zeroed. No flags are affected. This SSE2 instruction is useful for creating byte masks and is available in 64-bit and protected modes.", "pseudocode": "mask = 0\nfor i in 0..15:\n if src[8*i+7] == 1:\n mask |= (1 << i)\ndest[31:0] = mask", "example": "PMOVMSKB eax, xmm0"} {"mnemonic": "maskmovdqu", "architecture": "x86", "full_name": "Store Selected Bytes of Double Quadword", "summary": "Non-temporal store of selected bytes (masked).", "syntax": "MASKMOVDQU xmm, xmm", "encoding": {"format": "SSE2", "hex_opcode": "66 0F F7", "visual_parts": [], "binary_pattern": "66 | 0F | F7", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE2", "operands": [{"name": "dest", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}, {"name": "src", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}], "description": "Conditionally stores bytes from the first XMM register to memory at the address in EDI/RDI, using the second XMM register as a write mask (only bytes with MSB set are written). This is a weakly-ordered operation; memory ordering is not guaranteed without explicit serialization. The first operand is the source of data, the second is the mask. No flags are affected. This SSE2 instruction is available in 64-bit and protected modes.", "pseudocode": "address = EDI (32-bit mode) or RDI (64-bit mode)\nfor i in 0..15:\n if src[8*i+7] == 1:\n [address + i] = dest[8*i+7:8*i]", "example": "MASKMOVDQU xmm0, xmm0"} {"mnemonic": "ldmxcsr", "architecture": "x86", "full_name": "Load MXCSR Register", "summary": "Loads the MXCSR control/status register from memory.", "syntax": "LDMXCSR m32", "encoding": {"format": "SSE", "hex_opcode": "NP 0F AE /2", "visual_parts": [], "binary_pattern": "0F | AE | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE", "operands": [{"name": "dest", "type": "m32", "desc": "32-bit memory operand"}], "description": "Loads the MXCSR control and status register from a 32-bit memory operand, updating all SSE floating-point rounding modes, exception masks, exception flags, and DAZ/FTZ controls. This instruction serializes the CPU pipeline on many implementations. The instruction is available in 64-bit and protected modes with SSE support.", "pseudocode": "MXCSR ← [m32]", "example": "LDMXCSR [rbp-4]"} {"mnemonic": "stmxcsr", "architecture": "x86", "full_name": "Store MXCSR Register", "summary": "Stores the MXCSR register to memory.", "syntax": "STMXCSR m32", "encoding": {"format": "SSE", "hex_opcode": "NP 0F AE /3", "visual_parts": [], "binary_pattern": "0F | AE | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE", "operands": [{"name": "dest", "type": "m32", "desc": "32-bit memory operand"}], "description": "Stores the 32-bit MXCSR control and status register to a 32-bit memory location. This instruction serializes execution and is typically used to save the SSE/SSE2/SSE3 floating-point state. No flags are modified by this instruction.", "pseudocode": "[dest] ← MXCSR;", "example": "STMXCSR [rbp-4]"} {"mnemonic": "prefetcht0", "architecture": "x86", "full_name": "Prefetch Data into all Cache Levels", "summary": "Prefetches data to L1 cache.", "syntax": "PREFETCHT0 m8", "encoding": {"format": "SSE", "hex_opcode": "0F 18 /1", "visual_parts": [], "binary_pattern": "0F | 18 | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE", "operands": [{"name": "dest", "type": "m8", "desc": "8-bit memory operand"}], "description": "Issues a prefetch hint to load data from the specified memory address into all levels of the cache hierarchy (L1, L2, L3). This is a non-binding hint; the CPU may optimize or ignore it. No flags are modified and no exception is raised for invalid addresses.", "pseudocode": "prefetch_hint(dest, TEMPORAL_ALL_LEVELS);", "example": "PREFETCHT0 [rbp-1]"} {"mnemonic": "prefetchnta", "architecture": "x86", "full_name": "Prefetch Data using Non-Temporal Access", "summary": "Prefetches data to non-temporal cache structure (minimize pollution).", "syntax": "PREFETCHNTA m8", "encoding": {"format": "SSE", "hex_opcode": "0F 18 /0", "visual_parts": [], "binary_pattern": "0F | 18 | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE", "operands": [{"name": "dest", "type": "m8", "desc": "8-bit memory operand"}], "description": "Issues a prefetch hint to load data from the specified memory address into the L1 cache using non-temporal access semantics, minimizing cache pollution for data that will not be reused. This is a non-binding hint; execution continues without waiting. No flags are modified.", "pseudocode": "prefetch_hint(dest, NON_TEMPORAL);", "example": "PREFETCHNTA [rbp-1]"} {"mnemonic": "vfmadd132ps", "architecture": "x86", "full_name": "Fused Multiply-Add (132) Packed Single", "summary": "Computes (Dest * Src2) + Src1.", "syntax": "VFMADD132PS ymm1, ymm2, ymm3/m256", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F38.W0 98 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "FMA3", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src1", "type": "ymm2", "desc": "256-bit YMM AVX register"}, {"name": "src2", "type": "ymm3/m256", "desc": "256-bit YMM AVX register or Memory operand"}], "description": "Fused multiply-add on four packed single-precision floats: computes (dest × src2) + src1 with a single rounding operation, reducing latency and improving accuracy compared to separate multiply and add. Requires FMA3 extension (Intel Haswell+, AMD Piledriver+). Floating-point exceptions may be raised per IEEE 754; no integer flags are modified.", "pseudocode": "dest ← (dest * src2) + src1; // single rounding, 256-bit YMM", "example": "VFMADD132PS ymm1, ymm2, ymm3/m256"} {"mnemonic": "vfmadd213ps", "architecture": "x86", "full_name": "Fused Multiply-Add (213) Packed Single", "summary": "Computes (Src1 * Dest) + Src2.", "syntax": "VFMADD213PS ymm1, ymm2, ymm3/m256", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F38.W0 A8 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "FMA3", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src1", "type": "ymm2", "desc": "256-bit YMM AVX register"}, {"name": "src2", "type": "ymm3/m256", "desc": "256-bit YMM AVX register or Memory operand"}], "description": "Fused multiply-add on four packed single-precision floats: computes (src1 × dest) + src2 with a single rounding operation. The operand order differs from vfmadd132ps. Requires FMA3 extension. Floating-point exceptions may be raised per IEEE 754; no integer flags are modified.", "pseudocode": "dest ← (src1 * dest) + src2; // single rounding, 256-bit YMM", "example": "VFMADD213PS ymm1, ymm2, ymm3/m256"} {"mnemonic": "vfmsub132ps", "architecture": "x86", "full_name": "Fused Multiply-Subtract (132) Packed Single", "summary": "Computes (Dest * Src2) - Src1.", "syntax": "VFMSUB132PS ymm1, ymm2, ymm3/m256", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F38.W0 9A /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "FMA3", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src1", "type": "ymm2", "desc": "256-bit YMM AVX register"}, {"name": "src2", "type": "ymm3/m256", "desc": "256-bit YMM AVX register or Memory operand"}], "description": "Fused multiply-subtract on four packed single-precision floats: computes (dest × src2) - src1 with a single rounding operation. Requires FMA3 extension. Floating-point exceptions may be raised per IEEE 754; no integer flags are modified.", "pseudocode": "dest ← (dest * src2) - src1; // single rounding, 256-bit YMM", "example": "VFMSUB132PS ymm1, ymm2, ymm3/m256"} {"mnemonic": "vfnmadd132ps", "architecture": "x86", "full_name": "Fused Negative Multiply-Add (132) Packed Single", "summary": "Computes -(Dest * Src2) + Src1.", "syntax": "VFNMADD132PS ymm1, ymm2, ymm3/m256", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F38.W0 9C /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "FMA3", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src1", "type": "ymm2", "desc": "256-bit YMM AVX register"}, {"name": "src2", "type": "ymm3/m256", "desc": "256-bit YMM AVX register or Memory operand"}], "description": "Fused negative multiply-add on four packed single-precision floats: computes -(dest × src2) + src1 with a single rounding operation, negating the product before the addition. Requires FMA3 extension. Floating-point exceptions may be raised per IEEE 754; no integer flags are modified.", "pseudocode": "dest ← -(dest * src2) + src1; // single rounding, 256-bit YMM", "example": "VFNMADD132PS ymm1, ymm2, ymm3/m256"} {"mnemonic": "vpaddd", "architecture": "x86", "full_name": "Packed Add Doubleword (AVX2)", "summary": "Adds 8 integers (256-bit).", "syntax": "VPADDD ymm1, ymm2, ymm3/m256", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F.WIG FE /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AVX2", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src1", "type": "ymm2", "desc": "256-bit YMM AVX register"}, {"name": "src2", "type": "ymm3/m256", "desc": "256-bit YMM AVX register or Memory operand"}], "description": "Adds eight packed 32-bit signed/unsigned integers from two 256-bit YMM registers or memory, storing the result in the destination. Integer overflow wraps around; no overflow flag is set. Requires AVX2 extension (Intel Haswell+, AMD Excavator+). No flags are modified.", "pseudocode": "for i = 0 to 7:\n dest[32*i+31:32*i] ← dest[32*i+31:32*i] + src2[32*i+31:32*i];", "example": "VPADDD ymm1, ymm2, ymm3/m256"} {"mnemonic": "vpaddb", "architecture": "x86", "full_name": "Packed Add Byte (AVX2)", "summary": "Adds 32 bytes (256-bit).", "syntax": "VPADDB ymm1, ymm2, ymm3/m256", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F.WIG FC /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AVX2", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src1", "type": "ymm2", "desc": "256-bit YMM AVX register"}, {"name": "src2", "type": "ymm3/m256", "desc": "256-bit YMM AVX register or Memory operand"}], "description": "Adds packed byte integers element-wise across two 256-bit YMM registers (or one YMM and one memory operand), producing 32 sums in the destination. No arithmetic flags are affected; wrapping occurs on overflow. This is a non-destructive three-operand instruction (VEX encoding allows the first source to remain unchanged).", "pseudocode": "for i = 0 to 31:\n dest[i*8 + 7 : i*8] ← src1[i*8 + 7 : i*8] + src2[i*8 + 7 : i*8]", "example": "VPADDB ymm1, ymm2, ymm3/m256"} {"mnemonic": "vpsubd", "architecture": "x86", "full_name": "Packed Subtract Doubleword (AVX2)", "summary": "Subtracts 8 integers (256-bit).", "syntax": "VPSUBD ymm1, ymm2, ymm3/m256", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F.WIG FA /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AVX2", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src1", "type": "ymm2", "desc": "256-bit YMM AVX register"}, {"name": "src2", "type": "ymm3/m256", "desc": "256-bit YMM AVX register or Memory operand"}], "description": "Subtracts packed doubleword (32-bit) integers element-wise from two 256-bit YMM registers (or one YMM and one memory operand), producing 8 differences in the destination. No arithmetic flags are affected; wrapping occurs on underflow. This is a non-destructive three-operand instruction (VEX encoding).", "pseudocode": "for i = 0 to 7:\n dest[i*32 + 31 : i*32] ← src1[i*32 + 31 : i*32] - src2[i*32 + 31 : i*32]", "example": "VPSUBD ymm1, ymm2, ymm3/m256"} {"mnemonic": "vpmulld", "architecture": "x86", "full_name": "Packed Multiply Low Doubleword (AVX2)", "summary": "Multiplies 8 integers (256-bit).", "syntax": "VPMULLD ymm1, ymm2, ymm3/m256", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F38.WIG 40 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AVX2", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src1", "type": "ymm2", "desc": "256-bit YMM AVX register"}, {"name": "src2", "type": "ymm3/m256", "desc": "256-bit YMM AVX register or Memory operand"}], "description": "Multiplies packed doubleword (32-bit) integers element-wise across two 256-bit YMM registers (or one YMM and one memory operand), producing 8 low 32-bit products in the destination. No arithmetic flags are affected; the high 32 bits of each product are discarded. This is a non-destructive three-operand instruction (VEX encoding requires AVX2).", "pseudocode": "for i = 0 to 7:\n temp_product ← src1[i*32 + 31 : i*32] * src2[i*32 + 31 : i*32]\n dest[i*32 + 31 : i*32] ← temp_product[31 : 0]", "example": "VPMULLD ymm1, ymm2, ymm3/m256"} {"mnemonic": "vpshufb", "architecture": "x86", "full_name": "Packed Shuffle Bytes (AVX2)", "summary": "Shuffles 32 bytes based on indices.", "syntax": "VPSHUFB ymm1, ymm2, ymm3/m256", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F38.WIG 00 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AVX2", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src1", "type": "ymm2", "desc": "256-bit YMM AVX register"}, {"name": "src2", "type": "ymm3/m256", "desc": "256-bit YMM AVX register or Memory operand"}], "description": "Shuffles 32 bytes within 256-bit YMM register using per-byte indices from another YMM register or memory; the operation works within 128-bit lanes (bytes 0-15 and 16-31 are shuffled independently). If the index's high bit (bit 7) is set, the result byte is zeroed; otherwise the low 4 bits select which source byte to copy within the lane. No arithmetic flags are affected.", "pseudocode": "for i = 0 to 1:\n for j = 0 to 15:\n idx_byte = src2[(i*16 + j)*8 + 7 : (i*16 + j)*8]\n if idx_byte[7] == 1:\n dest[(i*16 + j)*8 + 7 : (i*16 + j)*8] ← 0\n else:\n byte_offset = (i*16) + (idx_byte[3:0])\n dest[(i*16 + j)*8 + 7 : (i*16 + j)*8] ← src1[byte_offset*8 + 7 : byte_offset*8]", "example": "VPSHUFB ymm1, ymm2, ymm3/m256"} {"mnemonic": "vperm2i128", "architecture": "x86", "full_name": "Permute 128-bit Integer Blocks", "summary": "Shuffles two 128-bit lanes between registers.", "syntax": "VPERM2I128 ymm1, ymm2, ymm3/m256, imm8", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F3A.W0 46 /r ib", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AVX2", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src1", "type": "ymm2", "desc": "256-bit YMM AVX register"}, {"name": "src2", "type": "ymm3/m256", "desc": "256-bit YMM AVX register or Memory operand"}, {"name": "src3", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Permutes two 128-bit lanes from two 256-bit YMM registers based on an 8-bit immediate control value. The low nibble selects which 128-bit lane to take from src1, and the high nibble selects from src2; a lane can be zeroed by setting its selector to 0x8. The result fills the destination's two 128-bit halves independently. No arithmetic flags are affected.", "pseudocode": "ctrl_low = src3[3:0]\nctrl_high = src3[7:4]\nif ctrl_low == 0x8:\n dest[127:0] ← 0\nelse:\n dest[127:0] ← src1[127:0] if (ctrl_low & 0x4) == 0 else src1[255:128]\nif ctrl_high == 0x8:\n dest[255:128] ← 0\nelse:\n dest[255:128] ← src2[127:0] if (ctrl_high & 0x4) == 0 else src2[255:128]", "example": "VPERM2I128 ymm1, ymm2, ymm3/m256, 3"} {"mnemonic": "vpermd", "architecture": "x86", "full_name": "Permute Doublewords", "summary": "Full permutation of 8 integers using indices from a register.", "syntax": "VPERMD ymm1, ymm2, ymm3/m256", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F38.W0 36 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AVX2", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src1", "type": "ymm2", "desc": "256-bit YMM AVX register"}, {"name": "src2", "type": "ymm3/m256", "desc": "256-bit YMM AVX register or Memory operand"}], "description": "Performs a full permutation of 8 doublewords (32-bit integers) within a 256-bit YMM register using per-element indices from another YMM register or memory. The low 3 bits of each index select which of the 8 source doublewords to place at that position; if bit 31 is set in the index, the result element is zeroed. No arithmetic flags are affected.", "pseudocode": "for i = 0 to 7:\n idx = src1[i*32 + 31 : i*32]\n if idx[31] == 1:\n dest[i*32 + 31 : i*32] ← 0\n else:\n src_idx = idx[2:0]\n dest[i*32 + 31 : i*32] ← src2[src_idx*32 + 31 : src_idx*32]", "example": "VPERMD ymm1, ymm2, ymm3/m256"} {"mnemonic": "vpermps", "architecture": "x86", "full_name": "Permute Single-Precision Floating-Point", "summary": "Full permutation of 8 floats using indices.", "syntax": "VPERMPS ymm1, ymm2, ymm3/m256", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F38.W0 16 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AVX2", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src1", "type": "ymm2", "desc": "256-bit YMM AVX register"}, {"name": "src2", "type": "ymm3/m256", "desc": "256-bit YMM AVX register or Memory operand"}], "description": "Performs a full permutation of 8 single-precision floating-point values within a 256-bit YMM register using per-element indices from another YMM register or memory. The low 3 bits of each index select which of the 8 source floats to place at that position; if bit 31 is set in the index, the result element is zeroed. No arithmetic flags are affected.", "pseudocode": "for i = 0 to 7:\n idx = src1[i*32 + 31 : i*32]\n if idx[31] == 1:\n dest[i*32 + 31 : i*32] ← 0\n else:\n src_idx = idx[2:0]\n dest[i*32 + 31 : i*32] ← src2[src_idx*32 + 31 : src_idx*32]", "example": "VPERMPS ymm1, ymm2, ymm3/m256"} {"mnemonic": "vpbroadcastb", "architecture": "x86", "full_name": "Broadcast Byte", "summary": "Broadcasts a byte from memory/register to all elements of YMM.", "syntax": "VPBROADCASTB ymm1, xmm2/m8", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F38.W0 78 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AVX2", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src", "type": "xmm2/m8", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Broadcasts a single byte from an XMM register or memory location to all 32 byte positions in a 256-bit YMM destination register. The source byte is replicated 32 times, filling the entire YMM with the same byte value. No arithmetic flags are affected.", "pseudocode": "src_byte = src[7:0]\nfor i = 0 to 31:\n dest[i*8 + 7 : i*8] ← src_byte", "example": "VPBROADCASTB ymm1, xmm2/m8"} {"mnemonic": "vgatherdps", "architecture": "x86", "full_name": "Gather Packed Single Precision", "summary": "Loads floats from non-contiguous memory using indices.", "syntax": "VGATHERDPS ymm1, [base+ymm_idx*scale], ymm_mask", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F38.W0 92 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AVX2", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src1", "type": "[base+ymm_idx*scale]", "desc": "AVX scatter: base register + scaled YMM vector index"}, {"name": "src2", "type": "ymm_mask", "desc": "YMM register acting as gather/scatter mask and result destination"}], "description": "Gathers four single-precision floating-point values from non-contiguous memory locations using a base address and a YMM vector of 32-bit indices with optional scaling, storing results in the destination YMM register. The mask register controls which elements are loaded (set bits indicate active gather); masked-out elements are zeroed. Sets ZF if all mask bits are zero, clears CF and OF; other flags undefined.", "pseudocode": "for i = 0 to 3:\n if mask[i*32 : i*32+31] != 0:\n addr = base + (index_ymm[i*32 : i*32+31] * scale)\n dest_ymm[i*32 : i*32+31] = [addr]\n mask[i*32 : i*32+31] = 0\n else:\n dest_ymm[i*32 : i*32+31] = 0\nZF = (mask == 0)\nCF = 0\nOF = 0", "example": "VGATHERDPS ymm1, [base+ymm_idx*scale], ymm_mask"} {"mnemonic": "vgatherdpd", "architecture": "x86", "full_name": "Gather Packed Double Precision", "summary": "Loads doubles from non-contiguous memory using indices.", "syntax": "VGATHERDPD ymm1, [base+xmm_idx*scale], ymm_mask", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F38.W1 92 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AVX2", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src1", "type": "[base+xmm_idx*scale]", "desc": "AVX gather: base register + scaled XMM vector index"}, {"name": "src2", "type": "ymm_mask", "desc": "YMM register acting as gather/scatter mask and result destination"}], "description": "Gathers two double-precision floating-point values from non-contiguous memory locations using a base address and an XMM vector of 32-bit indices with optional scaling, storing results in the destination YMM register. The mask register (YMM) controls which of the two elements are loaded; masked-out elements are zeroed. Sets ZF if all mask bits are zero, clears CF and OF; other flags undefined.", "pseudocode": "for i = 0 to 1:\n if mask[i*64 : i*64+63] != 0:\n addr = base + (index_xmm[i*32 : i*32+31] * scale)\n dest_ymm[i*64 : i*64+63] = [addr]\n mask[i*64 : i*64+63] = 0\n else:\n dest_ymm[i*64 : i*64+63] = 0\nZF = (mask == 0)\nCF = 0\nOF = 0", "example": "VGATHERDPD ymm1, [base+xmm_idx*scale], ymm_mask"} {"mnemonic": "andn", "architecture": "x86", "full_name": "Logical AND NOT", "summary": "Calculates (NOT src1) AND src2. Non-destructive.", "syntax": "ANDN r32, r32, r/m32", "encoding": {"format": "VEX", "hex_opcode": "VEX.LZ.0F38.W0 F2 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "BMI1", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src1", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src2", "type": "r/m32", "desc": "32-bit register or memory"}], "description": "Performs bitwise AND of the logical NOT of src1 with src2, storing the result in dest without modifying src1. ZF is set if result is zero; CF and OF are cleared; AF and PF are undefined. Available in 32-bit and 64-bit operand sizes; requires BMI1 extension.", "pseudocode": "dest ← (~src1) & src2\nZF ← (dest == 0)\nCF ← 0\nOF ← 0\nAF ← undefined\nPF ← undefined", "example": "ANDN eax, eax, ebx"} {"mnemonic": "bextr", "architecture": "x86", "full_name": "Bit Field Extract", "summary": "Extracts sequence of bits from source using index/length.", "syntax": "BEXTR r32, r/m32, r32", "encoding": {"format": "VEX", "hex_opcode": "VEX.LZ.0F38.W0 F7 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "BMI1", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src1", "type": "r/m32", "desc": "32-bit register or memory"}, {"name": "src2", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}], "description": "Extracts a contiguous sequence of bits from src1 specified by the start position and length encoded in src2 (bits 7:0 = start, bits 15:8 = length), storing the extracted bits in dest. ZF is set if the result is zero; CF and OF are cleared; AF and PF are undefined. Available in 32-bit and 64-bit sizes; requires BMI1 extension.", "pseudocode": "start ← src2[0:7]\nlength ← src2[8:15]\nif length == 0:\n dest ← 0\nelse if (start + length) > 32:\n dest ← 0\nelse:\n dest ← (src1 >> start) & ((1 << length) - 1)\nZF ← (dest == 0)\nCF ← 0\nOF ← 0\nAF ← undefined\nPF ← undefined", "example": "BEXTR eax, ebx, eax"} {"mnemonic": "blsi", "architecture": "x86", "full_name": "Extract Lowest Set Isolated Bit", "summary": "Extracts the lowest set bit (x & -x).", "syntax": "BLSI r32, r/m32", "encoding": {"format": "VEX", "hex_opcode": "VEX.LZ.0F38.W0 F3 /3", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "BMI1", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src", "type": "r/m32", "desc": "32-bit register or memory"}], "description": "Extracts the lowest set bit from src by computing (src & -src), storing the result in dest. ZF is set if src is zero; CF is set if src is zero; OF is cleared; AF and PF are undefined. Available in 32-bit and 64-bit sizes; requires BMI1 extension.", "pseudocode": "dest ← src & (-src)\nZF ← (src == 0)\nCF ← (src == 0)\nOF ← 0\nAF ← undefined\nPF ← undefined", "example": "BLSI eax, ebx"} {"mnemonic": "blsmsk", "architecture": "x86", "full_name": "Get Mask Up to Lowest Set Bit", "summary": "Creates mask up to lowest set bit (x ^ (x-1)).", "syntax": "BLSMSK r32, r/m32", "encoding": {"format": "VEX", "hex_opcode": "VEX.LZ.0F38.W0 F3 /2", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "BMI1", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src", "type": "r/m32", "desc": "32-bit register or memory"}], "description": "Creates a mask of all bits set from bit 0 up to and including the lowest set bit in src by computing (src ^ (src - 1)), storing the result in dest. ZF is set if src is zero; CF is set if src is zero; OF is cleared; AF and PF are undefined. Available in 32-bit and 64-bit sizes; requires BMI1 extension.", "pseudocode": "dest ← src ^ (src - 1)\nZF ← (src == 0)\nCF ← (src == 0)\nOF ← 0\nAF ← undefined\nPF ← undefined", "example": "BLSMSK eax, ebx"} {"mnemonic": "blsr", "architecture": "x86", "full_name": "Reset Lowest Set Bit", "summary": "Clears the lowest set bit (x & (x-1)).", "syntax": "BLSR r32, r/m32", "encoding": {"format": "VEX", "hex_opcode": "VEX.LZ.0F38.W0 F3 /1", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "BMI1", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src", "type": "r/m32", "desc": "32-bit register or memory"}], "description": "Clears the lowest set bit in src by computing (src & (src - 1)), storing the result in dest. ZF is set if the result is zero; CF is set if src is zero; OF is cleared; AF and PF are undefined. Available in 32-bit and 64-bit sizes; requires BMI1 extension.", "pseudocode": "dest ← src & (src - 1)\nZF ← (dest == 0)\nCF ← (src == 0)\nOF ← 0\nAF ← undefined\nPF ← undefined", "example": "BLSR eax, ebx"} {"mnemonic": "tzcnt", "architecture": "x86", "full_name": "Count Trailing Zeros", "summary": "Counts the number of trailing zeros.", "syntax": "TZCNT r32, r/m32", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F BC", "visual_parts": [], "binary_pattern": "F3 | 0F | BC", "bit_positions": "+0 | +1 | +2"}, "extension": "BMI1", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src", "type": "r/m32", "desc": "32-bit register or memory"}], "description": "Counts the number of trailing zero bits in src, storing the count in dest. If src is zero, dest is set to the operand size (32 for r/m32); ZF is set if src is zero; CF is cleared; other flags undefined. Available in 32-bit and 64-bit operand sizes; BMI1 extension provides faster behavior than BSF.", "pseudocode": "if src == 0:\n dest ← 32\n ZF ← 1\nelse:\n count ← 0\n while (src & 1) == 0:\n count ← count + 1\n src ← src >> 1\n dest ← count\n ZF ← 0\nCF ← 0", "example": "TZCNT eax, ebx"} {"mnemonic": "bzhi", "architecture": "x86", "full_name": "Zero High Bits Starting with Specified Bit Position", "summary": "Clears high bits starting at index.", "syntax": "BZHI r32, r/m32, r32", "encoding": {"format": "VEX", "hex_opcode": "VEX.LZ.0F38.W0 F5 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "BMI2", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src1", "type": "r/m32", "desc": "32-bit register or memory"}, {"name": "src2", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}], "description": "Zero High Bits Starting with Specified Bit Position clears all bits in the source operand at positions greater than or equal to the bit index specified in the third operand, storing the result in the destination. No flags are modified. Supported in 32-bit and 64-bit modes with BMI2 extension; the operand size can be 32 or 64 bits.", "pseudocode": "count ← src2[7:0] & 0x3F; mask ← (1 << count) - 1; dest ← src1 & mask;", "example": "BZHI eax, ebx, eax"} {"mnemonic": "pext", "architecture": "x86", "full_name": "Parallel Bits Extract", "summary": "Extracts bits from source using mask and packs them to LSB.", "syntax": "PEXT r32, r32, r/m32", "encoding": {"format": "VEX", "hex_opcode": "VEX.LZ.F3.0F38.W0 F5 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "BMI2", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src1", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src2", "type": "r/m32", "desc": "32-bit register or memory"}], "description": "Parallel Bits Extract copies bits from the first source operand to the destination at positions where the mask operand has set bits, compacting them toward the LSB. No flags are modified. Supported in 32-bit and 64-bit modes with BMI2 extension; operand size can be 32 or 64 bits.", "pseudocode": "result ← 0; dest_bit ← 0; for (i = 0; i < operand_size; i++) { if (src2[i]) { result[dest_bit] ← src1[i]; dest_bit += 1; } } dest ← result;", "example": "PEXT eax, eax, ebx"} {"mnemonic": "pdep", "architecture": "x86", "full_name": "Parallel Bits Deposit", "summary": "Scatters bits from LSB of source to positions marked in mask.", "syntax": "PDEP r32, r32, r/m32", "encoding": {"format": "VEX", "hex_opcode": "VEX.LZ.F2.0F38.W0 F5 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "BMI2", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src1", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src2", "type": "r/m32", "desc": "32-bit register or memory"}], "description": "Parallel Bits Deposit scatters bits from the LSB of the first source operand to positions marked by set bits in the mask operand, storing the result in the destination. No flags are modified. Supported in 32-bit and 64-bit modes with BMI2 extension; operand size can be 32 or 64 bits.", "pseudocode": "result ← 0; src_bit ← 0; for (i = 0; i < operand_size; i++) { if (src2[i]) { result[i] ← src1[src_bit]; src_bit += 1; } } dest ← result;", "example": "PDEP eax, eax, ebx"} {"mnemonic": "mulx", "architecture": "x86", "full_name": "Unsigned Multiply Without Affecting Flags", "summary": "Unsigned multiply of RDX * Src. Result in Hi:Lo. No flags.", "syntax": "MULX r32, r32, r/m32", "encoding": {"format": "VEX", "hex_opcode": "VEX.LZ.F2.0F38.W0 F6 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "BMI2", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src1", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src2", "type": "r/m32", "desc": "32-bit register or memory"}], "description": "Unsigned Multiply Without Affecting Flags multiplies the implicit RDX register by the source operand and stores the 128-bit product in two destination registers (high part in the first operand, low part in the second), without modifying any arithmetic flags. Supported in 32-bit and 64-bit modes with BMI2 extension; the operand size can be 32 or 64 bits.", "pseudocode": "product ← RDX * src; dest_hi ← product[127:64]; dest_lo ← product[63:0];", "example": "MULX eax, eax, ebx"} {"mnemonic": "shlx", "architecture": "x86", "full_name": "Shift Logical Left Without Affecting Flags", "summary": "Logical left shift, count in register. No flags update.", "syntax": "SHLX r32, r/m32, r32", "encoding": {"format": "VEX", "hex_opcode": "VEX.LZ.66.0F38.W0 F7 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "BMI2", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src1", "type": "r/m32", "desc": "32-bit register or memory"}, {"name": "src2", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}], "description": "Shift Logical Left Without Affecting Flags performs a left shift of the source operand by a count held in a register, storing the result in the destination, without modifying any arithmetic flags. Supported in 32-bit and 64-bit modes with BMI2 extension; operand size can be 32 or 64 bits.", "pseudocode": "count ← src2 & ((operand_size == 64) ? 0x3F : 0x1F); dest ← src1 << count;", "example": "SHLX eax, ebx, eax"} {"mnemonic": "shrx", "architecture": "x86", "full_name": "Shift Logical Right Without Affecting Flags", "summary": "Logical right shift, count in register. No flags update.", "syntax": "SHRX r32, r/m32, r32", "encoding": {"format": "VEX", "hex_opcode": "VEX.LZ.F2.0F38.W0 F7 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "BMI2", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src1", "type": "r/m32", "desc": "32-bit register or memory"}, {"name": "src2", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}], "description": "Shift Logical Right Without Affecting Flags performs a logical right shift of the source operand by a count held in a register, storing the result in the destination, without modifying any arithmetic flags. Supported in 32-bit and 64-bit modes with BMI2 extension; operand size can be 32 or 64 bits.", "pseudocode": "count ← src2 & ((operand_size == 64) ? 0x3F : 0x1F); dest ← src1 >> count;", "example": "SHRX eax, ebx, eax"} {"mnemonic": "sarx", "architecture": "x86", "full_name": "Shift Arithmetic Right Without Affecting Flags", "summary": "Arithmetic right shift, count in register. No flags update.", "syntax": "SARX r32, r/m32, r32", "encoding": {"format": "VEX", "hex_opcode": "VEX.LZ.F3.0F38.W0 F7 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "BMI2", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src1", "type": "r/m32", "desc": "32-bit register or memory"}, {"name": "src2", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}], "description": "Shift Arithmetic Right Without Affecting Flags performs an arithmetic right shift of the source operand by a count held in a register, storing the result in the destination, without modifying any arithmetic flags. Supported in 32-bit and 64-bit modes with BMI2 extension; operand size can be 32 or 64 bits; the sign bit is extended into vacated positions.", "pseudocode": "count ← src2 & ((operand_size == 64) ? 0x3F : 0x1F); dest ← (signed)src1 >> count;", "example": "SARX eax, ebx, eax"} {"mnemonic": "rorx", "architecture": "x86", "full_name": "Rotate Right Logical Without Affecting Flags", "summary": "Rotate right with immediate. No flags update.", "syntax": "RORX r32, r/m32, imm8", "encoding": {"format": "VEX", "hex_opcode": "VEX.LZ.F2.0F3A.W0 F0 /r ib", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "BMI2", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src1", "type": "r/m32", "desc": "32-bit register or memory"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Rotate Right Logical Without Affecting Flags rotates the source operand right by an immediate count, storing the result in the destination, without modifying any arithmetic flags. Supported in 32-bit and 64-bit modes with BMI2 extension; operand size can be 32 or 64 bits.", "pseudocode": "count ← src2 & ((operand_size == 64) ? 0x3F : 0x1F); dest ← (src1 >> count) | (src1 << (operand_size - count));", "example": "RORX eax, ebx, 3"} {"mnemonic": "rdrand", "architecture": "x86", "full_name": "Read Random Number", "summary": "Retrieves a hardware-generated random number.", "syntax": "RDRAND r32", "encoding": {"format": "Legacy", "hex_opcode": "NFx 0F C7 /6", "visual_parts": [], "binary_pattern": "0F | C7 | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "RDRAND", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}], "description": "Retrieves a cryptographically secure random number from the CPU's hardware random number generator and stores it in the destination register. The CF flag is set to 1 if a random number was successfully generated within the timeout period, or cleared to 0 if the generator failed to produce a value. No other flags are affected. This instruction is available only on processors with the RDRAND extension and cannot be used in real mode.", "pseudocode": "temp ← hardware_RNG();\nif (RNG_success) {\n dest ← temp;\n CF ← 1;\n} else {\n CF ← 0;\n}", "example": "RDRAND eax"} {"mnemonic": "rdseed", "architecture": "x86", "full_name": "Read Random Seed", "summary": "Retrieves a random seed from hardware entropy source.", "syntax": "RDSEED r32", "encoding": {"format": "Legacy", "hex_opcode": "NFx 0F C7 /7", "visual_parts": [], "binary_pattern": "0F | C7 | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "RDSEED", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}], "description": "Retrieves an entropy seed value from the CPU's hardware entropy source and stores it in the destination register. The CF flag is set to 1 if the seed was successfully obtained within the timeout period, or cleared to 0 on failure. No other flags are affected. This instruction requires the RDSEED extension and operates in protected and 64-bit modes only.", "pseudocode": "temp ← hardware_entropy_source();\nif (entropy_success) {\n dest ← temp;\n CF ← 1;\n} else {\n CF ← 0;\n}", "example": "RDSEED eax"} {"mnemonic": "invpcid", "architecture": "x86", "full_name": "Invalidate Process-Context Identifier", "summary": "Invalidates TLB entries based on PCID.", "syntax": "INVPCID r32, m128", "encoding": {"format": "Legacy", "hex_opcode": "66 0F 38 82", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 82", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "INVPCID", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src", "type": "m128", "desc": "128-bit memory operand"}], "description": "Invalidates TLB entries based on the PCID (Process-Context Identifier) specified in the 128-bit memory operand, with the invalidation type determined by the descriptor type field. The source register provides an address (typically a general register holding PCID context information), and the memory operand contains the full 128-bit invalidation descriptor. This is a privileged instruction (CPL 0 only) that serializes the pipeline and requires the INVPCID extension. No flags are affected.", "pseudocode": "descriptor ← [src + 0:127];\ninvalidation_type ← descriptor.type;\npcid ← descriptor.pcid;\nswitch(invalidation_type) {\n case 0: invalidate_tlb_entry_by_pcid(pcid); break;\n case 1: invalidate_all_tlb_entries_by_pcid(pcid); break;\n case 2: invalidate_all_tlb_entries(); break;\n case 3: invalidate_all_tlb_entries_except_global(); break;\n}\npipeline_serialization();", "example": "INVPCID eax, [rbp-16]"} {"mnemonic": "adcx", "architecture": "x86", "full_name": "Unsigned Integer Addition of Two Operands with Carry Flag", "summary": "Adds with Carry Flag (distinct from ADC, affects CF only).", "syntax": "ADCX r32, r/m32", "encoding": {"format": "Legacy", "hex_opcode": "66 0F 38 F6", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | F6", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "ADX", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src", "type": "r/m32", "desc": "32-bit register or memory"}], "description": "Adds the source operand and the Carry Flag (CF) to the destination operand, storing the result in the destination. Only the CF flag is modified (set to 1 if unsigned overflow occurs, cleared to 0 otherwise); OF, SF, ZF, AF, and PF are left unchanged. This instruction is distinct from ADC in that it does not affect other flags, making it useful for parallel carry-chain operations with ADOX. Available in 32-bit and 64-bit operand sizes with the ADX extension.", "pseudocode": "temp ← dest + src + CF;\nCF ← (temp > 0xFFFFFFFF) ? 1 : 0;\ndest ← temp & 0xFFFFFFFF;", "example": "ADCX eax, ebx"} {"mnemonic": "adox", "architecture": "x86", "full_name": "Unsigned Integer Addition of Two Operands with Overflow Flag", "summary": "Adds with Overflow Flag (Parallel addition with ADCX).", "syntax": "ADOX r32, r/m32", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F 38 F6", "visual_parts": [], "binary_pattern": "F3 | 0F | 38 | F6", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "ADX", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src", "type": "r/m32", "desc": "32-bit register or memory"}], "description": "Adds the source operand and the Overflow Flag (OF) to the destination operand, storing the result in the destination. Only the OF flag is modified (set to 1 if signed overflow occurs, cleared to 0 otherwise); CF, SF, ZF, AF, and PF are left unchanged. This instruction is designed to execute in parallel with ADCX for independent carry and overflow chains in multi-precision arithmetic. Available in 32-bit and 64-bit operand sizes with the ADX extension.", "pseudocode": "temp ← dest + src + OF;\nOF ← (signed_overflow(dest, src, temp)) ? 1 : 0;\ndest ← temp & 0xFFFFFFFF;", "example": "ADOX eax, ebx"} {"mnemonic": "vinserti128", "architecture": "x86", "full_name": "Insert Integer 128-bit", "summary": "Inserts 128-bits of integer data into a YMM register.", "syntax": "VINSERTI128 ymm1, ymm2, xmm3/m128, imm8", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F3A.W0 38 /r ib", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AVX2", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src1", "type": "ymm2", "desc": "256-bit YMM AVX register"}, {"name": "src2", "type": "xmm3/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src3", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Inserts a 128-bit integer value from the source operand into the destination YMM register at the position specified by the immediate operand. The lower 128 bits of the source YMM register (src1) are preserved or replaced depending on the immediate; typically imm8[0]=0 replaces the lower 128 bits, and imm8[0]=1 replaces the upper 128 bits. No flags are affected. This is a VEX-encoded AVX2 instruction that supports 32-bit or 64-bit vector elements.", "pseudocode": "if (imm8[0] == 0) {\n dest[127:0] ← src2[127:0];\n dest[255:128] ← src1[255:128];\n} else {\n dest[127:0] ← src1[127:0];\n dest[255:128] ← src2[127:0];\n}", "example": "VINSERTI128 ymm1, ymm2, xmm3/m128, 3"} {"mnemonic": "vextracti128", "architecture": "x86", "full_name": "Extract Integer 128-bit", "summary": "Extracts 128-bits of integer data from YMM.", "syntax": "VEXTRACTI128 xmm1/m128, ymm2, imm8", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F3A.W0 39 /r ib", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AVX2", "operands": [{"name": "dest", "type": "xmm1/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src1", "type": "ymm2", "desc": "256-bit YMM AVX register"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Extracts a 128-bit integer value from the source YMM register and stores it in the destination XMM register or memory location. The specific 128-bit lane extracted is determined by the immediate operand (imm8[0]=0 for lower 128 bits, imm8[0]=1 for upper 128 bits). No flags are affected. This is a VEX-encoded AVX2 instruction that complements VINSERTI128 for manipulating 256-bit vectors.", "pseudocode": "if (imm8[0] == 0) {\n dest ← src1[127:0];\n} else {\n dest ← src1[255:128];\n}", "example": "VEXTRACTI128 xmm1/m128, ymm2, 3"} {"mnemonic": "clac", "architecture": "x86", "full_name": "Clear AC Flag in EFLAGS", "summary": "Clears Alignment Check flag (SMAP prevention).", "syntax": "CLAC", "encoding": {"format": "Legacy", "hex_opcode": "NP 0F 01 CA", "visual_parts": [], "binary_pattern": "0F | 01 | CA", "bit_positions": "+0 | +1 | +2"}, "extension": "SMAP", "operands": [], "description": "Clears the Alignment Check (AC) flag in EFLAGS, disabling alignment checking for user-mode code. When combined with SMAP (Supervisor Mode Access Prevention), this instruction allows the kernel to temporarily disable SMAP protections. This is a privileged instruction (CPL 0 only) available with the SMAP extension. No other flags are affected.", "pseudocode": "EFLAGS.AC ← 0;", "example": "CLAC"} {"mnemonic": "stac", "architecture": "x86", "full_name": "Set AC Flag in EFLAGS", "summary": "Sets Alignment Check flag (Allow user memory access).", "syntax": "STAC", "encoding": {"format": "Legacy", "hex_opcode": "NP 0F 01 CB", "visual_parts": [], "binary_pattern": "0F | 01 | CB", "bit_positions": "+0 | +1 | +2"}, "extension": "SMAP", "operands": [], "description": "Sets the Alignment Check (AC) flag in EFLAGS, enabling alignment checking and allowing user-mode access to supervisor-mode data structures when SMAP protection is present. This instruction requires SMAP support and ring 0 privilege. Only the AC flag is modified; all other flags remain unchanged.", "pseudocode": "EFLAGS.AC ← 1;", "example": "STAC"} {"mnemonic": "gf2p8affineqb", "architecture": "x86", "full_name": "Galois Field Affine Transformation", "summary": "Computes affine transformation in GF(2^8).", "syntax": "GF2P8AFFINEQB xmm1, xmm2/m128, imm8", "encoding": {"format": "VEX", "hex_opcode": "66 0F 3A CE /r ib", "visual_parts": [], "binary_pattern": "66 | 0F | 3A | CE", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "GFNI", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Performs byte-wise affine transformation in Galois Field GF(2^8) on 128-bit XMM operands using a constant 8-bit immediate as the affine constant. Each byte in the destination is transformed using the corresponding byte from the source operand. No flags are affected; this is a pure data-parallel cryptographic operation.", "pseudocode": "for i in 0..15:\n dest[i] ← GF2P8_AFFINE_TRANSFORM(dest[i], src[i], imm8);", "example": "GF2P8AFFINEQB xmm1, xmm2/m128, 3"} {"mnemonic": "gf2p8mulb", "architecture": "x86", "full_name": "Galois Field Multiply Bytes", "summary": "Multiplies bytes in GF(2^8).", "syntax": "GF2P8MULB xmm1, xmm2/m128", "encoding": {"format": "VEX", "hex_opcode": "66 0F 38 CF /r", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | CF", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "GFNI", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Multiplies each byte in the destination XMM register by the corresponding byte in the source operand within Galois Field GF(2^8). The result replaces the destination operand byte-wise. No flags are affected; this is a pure cryptographic SIMD operation with full latency parallelism.", "pseudocode": "for i in 0..15:\n dest[i] ← GF2P8_MULTIPLY(dest[i], src[i]);", "example": "GF2P8MULB xmm1, xmm2/m128"} {"mnemonic": "sha1msg1", "architecture": "x86", "full_name": "SHA1 Message Schedule 1", "summary": "Performs intermediate calculation for SHA1 message schedule.", "syntax": "SHA1MSG1 xmm1, xmm2/m128", "encoding": {"format": "Legacy", "hex_opcode": "NP 0F 38 C9 /r", "visual_parts": [], "binary_pattern": "0F | 38 | C9", "bit_positions": "+0 | +1 | +2"}, "extension": "SHA", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Performs the first intermediate step of SHA-1 message schedule expansion on 128-bit XMM operands, computing partial W values (message words) for rounds 16-19. The destination is updated with results of the schedule computation; no flags are affected.", "pseudocode": "W[0..3] ← dest[0..3];\nW[4..7] ← src[0..3];\nfor i in 0..3:\n dest[i] ← W[i] ⊕ W[i+2] ⊕ W[i+8] ⊕ W[i+13];", "example": "SHA1MSG1 xmm1, xmm2/m128"} {"mnemonic": "sha1msg2", "architecture": "x86", "full_name": "SHA1 Message Schedule 2", "summary": "Performs final calculation for SHA1 message schedule.", "syntax": "SHA1MSG2 xmm1, xmm2/m128", "encoding": {"format": "Legacy", "hex_opcode": "NP 0F 38 CA /r", "visual_parts": [], "binary_pattern": "0F | 38 | CA", "bit_positions": "+0 | +1 | +2"}, "extension": "SHA", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Performs the second final step of SHA-1 message schedule expansion on 128-bit XMM operands, completing W value computation and applying left rotation. The destination is updated with final message schedule results; no flags are affected.", "pseudocode": "W[0..3] ← dest[0..3];\nW[4..7] ← src[0..3];\nfor i in 0..3:\n W[i] ← W[i] ⊕ W[i+4] ⊕ W[i+5] ⊕ W[i+6];\n dest[i] ← ROTL32(W[i], 1);", "example": "SHA1MSG2 xmm1, xmm2/m128"} {"mnemonic": "sha1nexte", "architecture": "x86", "full_name": "SHA1 State Variable E", "summary": "Calculates SHA1 state variable E.", "syntax": "SHA1NEXTE xmm1, xmm2/m128", "encoding": {"format": "Legacy", "hex_opcode": "NP 0F 38 C8 /r", "visual_parts": [], "binary_pattern": "0F | 38 | C8", "bit_positions": "+0 | +1 | +2"}, "extension": "SHA", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Calculates intermediate SHA-1 state variable E for one round, adding the source operand (containing message schedule and round constants) to the destination operand and applying left rotation. The result updates the destination with the next E value; no flags are affected.", "pseudocode": "E ← dest[0];\nW ← src[0];\ndest[0] ← ROTL32(E, 5) + W;\ndest[1..3] ← dest[1..3] rotated left by 30 bits from the previous round state;", "example": "SHA1NEXTE xmm1, xmm2/m128"} {"mnemonic": "sha1rnds4", "architecture": "x86", "full_name": "SHA1 Rounds 4", "summary": "Performs 4 rounds of SHA1 operation.", "syntax": "SHA1RNDS4 xmm1, xmm2/m128, imm8", "encoding": {"format": "Legacy", "hex_opcode": "NP 0F 3A CC /r ib", "visual_parts": [], "binary_pattern": "0F | 3A | CC", "bit_positions": "+0 | +1 | +2"}, "extension": "SHA", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Executes 4 rounds of the SHA-1 compression function, performing circular left shift, addition, and XOR operations on the five 32-bit state variables (A, B, C, D, E). The immediate byte selects the round function constant (K value 0-3); no flags are affected.", "pseudocode": "for round in 0..3:\n f ← SHA1_FUNCTION(round + imm8*4, B, C, D);\n K ← SHA1_CONSTANT(round + imm8*4);\n T ← ROTL32(A, 5) + f + E + K + W[round + imm8*4];\n E ← D; D ← C; C ← ROTL32(B, 30); B ← A; A ← T;", "example": "SHA1RNDS4 xmm1, xmm2/m128, 3"} {"mnemonic": "sha256msg1", "architecture": "x86", "full_name": "SHA256 Message Schedule 1", "summary": "Performs intermediate calculation for SHA256 message schedule.", "syntax": "SHA256MSG1 xmm1, xmm2/m128", "encoding": {"format": "Legacy", "hex_opcode": "NP 0F 38 CC /r", "visual_parts": [], "binary_pattern": "0F | 38 | CC", "bit_positions": "+0 | +1 | +2"}, "extension": "SHA", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Performs the first intermediate step of SHA-256 message schedule expansion on 128-bit XMM operands, computing partial W values for the message schedule. The destination is updated with results of the partial expansion; no flags are affected.", "pseudocode": "W[0..3] ← dest[0..3];\nW[4..7] ← src[0..3];\nfor i in 0..3:\n dest[i] ← W[i] + SHA256_GAMMA0(W[i+1]);", "example": "SHA256MSG1 xmm1, xmm2/m128"} {"mnemonic": "sha256msg2", "architecture": "x86", "full_name": "SHA256 Message Schedule 2", "summary": "Performs final calculation for SHA256 message schedule.", "syntax": "SHA256MSG2 xmm1, xmm2/m128", "encoding": {"format": "Legacy", "hex_opcode": "NP 0F 38 CD /r", "visual_parts": [], "binary_pattern": "0F | 38 | CD", "bit_positions": "+0 | +1 | +2"}, "extension": "SHA", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Performs the final calculation of the SHA256 message schedule for the next 4 message words. The instruction operates on 128-bit XMM registers containing 32-bit message schedule values and combines them with the previous message schedule state. All flags (CF, PF, AF, ZF, SF, OF) remain unchanged; this is a pure data-transformation instruction with no flag effects.", "pseudocode": "xmm1[127:0] ← SHA256_MSG_SCHEDULE_ROUND(xmm1[127:0], xmm2/m128[127:0])", "example": "SHA256MSG2 xmm1, xmm2/m128"} {"mnemonic": "sha256rnds2", "architecture": "x86", "full_name": "SHA256 Rounds 2", "summary": "Performs 2 rounds of SHA256 operation.", "syntax": "SHA256RNDS2 xmm1, xmm2/m128, xmm0", "encoding": {"format": "Legacy", "hex_opcode": "NP 0F 38 CB /r", "visual_parts": [], "binary_pattern": "0F | 38 | CB", "bit_positions": "+0 | +1 | +2"}, "extension": "SHA", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "xmm0", "desc": "128-bit XMM SIMD register"}], "description": "Executes two rounds of the SHA256 compression function on the working variables. The instruction reads round constants from XMM0 and processes the destination register in-place using the source operand as input to the SHA256 rounds. All flags remain unchanged; this instruction has no flag side effects and requires the SHA CPU extension.", "pseudocode": "xmm1[127:0] ← SHA256_ROUNDS(xmm1[127:0], xmm2/m128[127:0], xmm0[127:0], round_constants)", "example": "SHA256RNDS2 xmm1, xmm2/m128, xmm0"} {"mnemonic": "vmxon", "architecture": "x86", "full_name": "Enter VMX Operation", "summary": "Enters VMX root operation (Host Mode).", "syntax": "VMXON m64", "encoding": {"format": "VMX", "hex_opcode": "F3 0F C7 !(11):110:bbb", "visual_parts": [], "binary_pattern": "F3 | 0F | C7 | ModRM", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "VMX", "operands": [{"name": "dest", "type": "m64", "desc": "64-bit memory operand (quadword)"}], "description": "Enters VMX root operation (host/hypervisor mode) using a 64-bit VMXON region pointer loaded from memory. The instruction validates the VMXON region, sets the VMXON flag in CR4, and transitions the processor to VMX root mode; failure causes #UD or sets RFLAGS.CF/ZF. This is a privileged instruction (requires CPL=0) and available only on processors with VMX support.", "pseudocode": "if (CPL != 0 || VMX_ENABLED == 0) raise #UD\nVMXON_PTR ← [m64]\nif (!validate_vmxon_region(VMXON_PTR)) { RFLAGS.CF ← 1; RFLAGS.ZF ← 0; } else { VMX_ROOT ← 1; RFLAGS.CF ← 0; RFLAGS.ZF ← 0; }", "example": "VMXON [rbp-8]"} {"mnemonic": "vmcall", "architecture": "x86", "full_name": "Call to VM Monitor", "summary": "Guest VM calls the Hypervisor (VM Exit).", "syntax": "VMCALL", "encoding": {"format": "VMX", "hex_opcode": "0F 01 C1", "visual_parts": [], "binary_pattern": "0F | 01 | C1", "bit_positions": "+0 | +1 | +2"}, "extension": "VMX", "operands": [], "description": "Initiates a VM exit from guest mode to invoke the VM monitor (hypervisor). The instruction immediately transitions control to the hypervisor and is available only when running in VMX non-root mode; execution in root mode raises #UD. RFLAGS.CF and ZF may be set on VM exit depending on the exit reason; other flags are preserved across the transition.", "pseudocode": "if (CPL != 0 || VMX_ROOT == 1) raise #UD\nVMEXIT(VMCALL_EXIT_REASON)\nif (exit_error) { RFLAGS.CF ← 1; RFLAGS.ZF ← 1; }", "example": "VMCALL"} {"mnemonic": "vmclear", "architecture": "x86", "full_name": "Clear Virtual-Machine Control Structure", "summary": "Initializes a VMCS region in memory.", "syntax": "VMCLEAR m64", "encoding": {"format": "VMX", "hex_opcode": "66 0F C7 /6", "visual_parts": [], "binary_pattern": "66 | 0F | C7 | ModRM", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "VMX", "operands": [{"name": "dest", "type": "m64", "desc": "64-bit memory operand (quadword)"}], "description": "Initializes a Virtual Machine Control Structure (VMCS) region in memory by clearing its launch state and marking it as inactive. The instruction loads a 64-bit VMCS pointer from memory, validates the region, and sets CF/ZF on validation failure. This is a privileged instruction (CPL=0) requiring VMX support and must be executed in VMX root mode.", "pseudocode": "if (CPL != 0 || VMX_ROOT == 0) raise #UD\nVMCS_PTR ← [m64]\nif (!validate_vmcs_region(VMCS_PTR)) { RFLAGS.CF ← 1; RFLAGS.ZF ← 0; } else { clear_vmcs(VMCS_PTR); RFLAGS.CF ← 0; RFLAGS.ZF ← 0; }", "example": "VMCLEAR [rbp-8]"} {"mnemonic": "vmlaunch", "architecture": "x86", "full_name": "Launch Virtual Machine", "summary": "Launches a VM managed by the current VMCS.", "syntax": "VMLAUNCH", "encoding": {"format": "VMX", "hex_opcode": "0F 01 C2", "visual_parts": [], "binary_pattern": "0F | 01 | C2", "bit_positions": "+0 | +1 | +2"}, "extension": "VMX", "operands": [], "description": "Launches a virtual machine using the current VMCS. The instruction reads guest state from the current VMCS, validates it, and transitions to VMX non-root mode; on success, control transfers to the guest; on failure, returns to the instruction with CF/ZF set. This is a privileged instruction (CPL=0) available only in VMX root mode on processors with VMX support.", "pseudocode": "if (CPL != 0 || VMX_ROOT == 0) raise #UD\nif (!validate_vmcs_state()) { RFLAGS.CF ← 1; RFLAGS.ZF ← 0; } else { load_guest_state_from_vmcs(); VMX_ROOT ← 0; transfer_control_to_guest(); }", "example": "VMLAUNCH"} {"mnemonic": "vmresume", "architecture": "x86", "full_name": "Resume Virtual Machine", "summary": "Resumes a VM from the current VMCS.", "syntax": "VMRESUME", "encoding": {"format": "VMX", "hex_opcode": "0F 01 C3", "visual_parts": [], "binary_pattern": "0F | 01 | C3", "bit_positions": "+0 | +1 | +2"}, "extension": "VMX", "operands": [], "description": "Resumes a suspended virtual machine from the current VMCS. The instruction restores guest CPU state from the VMCS and returns control to the guest; on validation failure, CF/ZF are set and control returns to the hypervisor. This is a privileged instruction (CPL=0) available only in VMX root mode and following a prior VMLAUNCH or VM exit.", "pseudocode": "if (CPL != 0 || VMX_ROOT == 0) raise #UD\nif (!validate_vmcs_state()) { RFLAGS.CF ← 1; RFLAGS.ZF ← 0; } else { restore_guest_state_from_vmcs(); VMX_ROOT ← 0; transfer_control_to_guest(); }", "example": "VMRESUME"} {"mnemonic": "vmptrld", "architecture": "x86", "full_name": "Load Pointer to VMCS", "summary": "Loads the current VMCS pointer from memory.", "syntax": "VMPTRLD m64", "encoding": {"format": "VMX", "hex_opcode": "NP 0F C7 /6", "visual_parts": [], "binary_pattern": "0F | C7 | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "VMX", "operands": [{"name": "dest", "type": "m64", "desc": "64-bit memory operand (quadword)"}], "description": "Loads a pointer to the Virtual Machine Control Structure (VMCS) from memory and sets it as the current VMCS. The instruction reads a 64-bit VMCS physical address from memory, validates the region, and sets CF/ZF on failure. This is a privileged instruction (CPL=0) requiring VMX support and execution in VMX root mode; the VMCS region must be 4KB-aligned.", "pseudocode": "if (CPL != 0 || VMX_ROOT == 0) raise #UD\nVMCS_PTR ← [m64]\nif (!validate_vmcs_region(VMCS_PTR)) { RFLAGS.CF ← 1; RFLAGS.ZF ← 0; } else { CURRENT_VMCS ← VMCS_PTR; RFLAGS.CF ← 0; RFLAGS.ZF ← 0; }", "example": "VMPTRLD [rbp-8]"} {"mnemonic": "vmptrst", "architecture": "x86", "full_name": "Store Pointer to VMCS", "summary": "Stores the current VMCS pointer to memory.", "syntax": "VMPTRST m64", "encoding": {"format": "VMX", "hex_opcode": "NP 0F C7 /7", "visual_parts": [], "binary_pattern": "0F | C7 | ModRM", "bit_positions": "+0 | +1 | +2"}, "extension": "VMX", "operands": [{"name": "dest", "type": "m64", "desc": "64-bit memory operand (quadword)"}], "description": "Stores the current VMCS pointer (from the VMCS pointer register) to a 64-bit memory location. This instruction is privileged and requires VMX root operation; it clears the memory destination with the active VMCS pointer value. The CF flag is set if an error occurs (invalid VMCS pointer state); ZF is set to indicate success or failure.", "pseudocode": "if (VMX_mode == ROOT && VMCS_pointer != INVALID) {\n [dest] ← VMCS_pointer_register;\n CF ← 0;\n ZF ← 0;\n} else {\n CF ← 1;\n ZF ← 1;\n}", "example": "VMPTRST [rbp-8]"} {"mnemonic": "vmread", "architecture": "x86", "full_name": "Read Field from VMCS", "summary": "Reads a field from the Virtual Machine Control Structure.", "syntax": "VMREAD r/m64, r64", "encoding": {"format": "VMX", "hex_opcode": "NP 0F 78", "visual_parts": [], "binary_pattern": "0F | 78", "bit_positions": "+0 | +1"}, "extension": "VMX", "operands": [{"name": "dest", "type": "r/m64", "desc": "64-bit register or memory"}, {"name": "src", "type": "r64", "desc": "64-bit general-purpose register (e.g. RAX)"}], "description": "Reads a 64-bit field from the current VMCS (specified by the index in the source operand) and writes the value to the destination register or memory. Requires active VMCS and VMX root or non-root operation; CF is set on error, ZF indicates field validity.", "pseudocode": "if (VMCS_pointer_valid && VMX_mode_active) {\n field_index ← src;\n value ← VMCS[field_index];\n dest ← value;\n CF ← 0;\n ZF ← 0;\n} else {\n CF ← 1;\n ZF ← 1;\n}", "example": "VMREAD rbx, rax"} {"mnemonic": "vmwrite", "architecture": "x86", "full_name": "Write Field to VMCS", "summary": "Writes a field to the Virtual Machine Control Structure.", "syntax": "VMWRITE r64, r/m64", "encoding": {"format": "VMX", "hex_opcode": "NP 0F 79", "visual_parts": [], "binary_pattern": "0F | 79", "bit_positions": "+0 | +1"}, "extension": "VMX", "operands": [{"name": "dest", "type": "r64", "desc": "64-bit general-purpose register (e.g. RAX)"}, {"name": "src", "type": "r/m64", "desc": "64-bit register or memory"}], "description": "Writes a 64-bit value to a field in the current VMCS (specified by the index in the destination operand). Requires active VMCS and VMX root or non-root operation; CF is set on error, ZF indicates write success.", "pseudocode": "if (VMCS_pointer_valid && VMX_mode_active) {\n field_index ← dest;\n value ← src;\n VMCS[field_index] ← value;\n CF ← 0;\n ZF ← 0;\n} else {\n CF ← 1;\n ZF ← 1;\n}", "example": "VMWRITE rax, rbx"} {"mnemonic": "vmxoff", "architecture": "x86", "full_name": "Leave VMX Operation", "summary": "Leaves VMX root operation.", "syntax": "VMXOFF", "encoding": {"format": "VMX", "hex_opcode": "0F 01 C4", "visual_parts": [], "binary_pattern": "0F | 01 | C4", "bit_positions": "+0 | +1 | +2"}, "extension": "VMX", "operands": [], "description": "Exits VMX root operation and returns the processor to non-VMX mode. This instruction requires VMX root operation and clears the VMXE bit in CR4. CF and ZF flags are set to indicate error conditions if the operation fails; execution may be serialized.", "pseudocode": "if (VMX_root_operation) {\n VMX_mode ← OFF;\n CR4.VMXE ← 0;\n CF ← 0;\n ZF ← 0;\n} else {\n CF ← 1;\n ZF ← 1;\n}", "example": "VMXOFF"} {"mnemonic": "invept", "architecture": "x86", "full_name": "Invalidate Translations Derived from EPT", "summary": "Invalidates Extended Page Table entries.", "syntax": "INVEPT r64, m128", "encoding": {"format": "VMX", "hex_opcode": "66 0F 38 80", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 80", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "VMX (EPT)", "operands": [{"name": "dest", "type": "r64", "desc": "64-bit general-purpose register (e.g. RAX)"}, {"name": "src", "type": "m128", "desc": "128-bit memory operand"}], "description": "Invalidates Extended Page Table (EPT) translation cache entries based on the invalidation type and operand descriptor. The destination register specifies the invalidation type (1=single context, 2=all contexts), and the source memory operand contains EPTP and VPID information. CF/ZF flags indicate success or error; this instruction may serialize execution.", "pseudocode": "if (EPT_enabled && VMX_mode_active) {\n invalidation_type ← dest;\n descriptor ← [src];\n if (invalidation_type == 1) {\n invalidate_EPT_context(descriptor);\n } else if (invalidation_type == 2) {\n invalidate_all_EPT();\n }\n CF ← 0;\n ZF ← 0;\n} else {\n CF ← 1;\n ZF ← 1;\n}", "example": "INVEPT rax, [rbp-16]"} {"mnemonic": "invvpid", "architecture": "x86", "full_name": "Invalidate Translations Based on VPID", "summary": "Invalidates TLB entries based on Virtual Processor ID.", "syntax": "INVVPID r64, m128", "encoding": {"format": "VMX", "hex_opcode": "66 0F 38 81", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 81", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "VMX (VPID)", "operands": [{"name": "dest", "type": "r64", "desc": "64-bit general-purpose register (e.g. RAX)"}, {"name": "src", "type": "m128", "desc": "128-bit memory operand"}], "description": "Invalidates TLB entries based on Virtual Processor ID (VPID). The destination register specifies the invalidation type (1=individual address, 2=single VPID context, 3=all VPID contexts, 4=individual address keeping globals), and the source memory operand contains VPID and address information. CF/ZF flags indicate success or error; this instruction serializes execution.", "pseudocode": "if (VPID_enabled && VMX_mode_active) {\n invalidation_type ← dest;\n descriptor ← [src];\n if (invalidation_type == 1) {\n invalidate_TLB_address(descriptor);\n } else if (invalidation_type == 2) {\n invalidate_TLB_VPID(descriptor);\n } else if (invalidation_type == 3) {\n invalidate_all_TLB();\n } else if (invalidation_type == 4) {\n invalidate_TLB_address_keep_global(descriptor);\n }\n CF ← 0;\n ZF ← 0;\n} else {\n CF ← 1;\n ZF ← 1;\n}", "example": "INVVPID rax, [rbp-16]"} {"mnemonic": "kmovw", "architecture": "x86", "full_name": "Move Word Mask Register", "summary": "Moves 16-bit mask to/from k-register.", "syntax": "KMOVW k1, k2/m16", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L0.0F.W0 90 /r", "visual_parts": [], "binary_pattern": "EVEX | 0F | 90", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src", "type": "k2/m16", "desc": "AVX-512 opmask register (k0-k7) or Memory operand"}], "description": "Moves a 16-bit value between AVX-512 opmask registers (k0-k7) or from/to a 16-bit memory location. When moving from register/memory to k-register, the upper bits beyond 16 are zeroed. ZF is set based on source value; CF is typically cleared unless an error occurs.", "pseudocode": "if (source_is_register) {\n dest_k ← src_k & 0xFFFF;\n} else {\n dest_k ← [src] & 0xFFFF;\n}\nZF ← (dest_k == 0);\nCF ← 0;", "example": "KMOVW k1, k2/m16"} {"mnemonic": "kmovq", "architecture": "x86", "full_name": "Move Quadword Mask Register", "summary": "Moves 64-bit mask to/from k-register.", "syntax": "KMOVQ k1, k2/m64", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L0.0F.W1 90 /r", "visual_parts": [], "binary_pattern": "EVEX | 0F | 90", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512BW", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src", "type": "k2/m64", "desc": "AVX-512 opmask register (k0-k7) or Memory operand"}], "description": "Moves a 64-bit value between AVX-512 opmask registers (k0-k7) or from/to a 64-bit memory location. Requires AVX-512BW support; destination k-register receives the full 64-bit mask. ZF is set based on source value; CF is typically cleared unless an error occurs.", "pseudocode": "if (source_is_register) {\n dest_k ← src_k;\n} else {\n dest_k ← [src];\n}\nZF ← (dest_k == 0);\nCF ← 0;", "example": "KMOVQ k1, k2/m64"} {"mnemonic": "kandw", "architecture": "x86", "full_name": "Bitwise Logical AND Masks Word", "summary": "Bitwise AND of 16-bit masks.", "syntax": "KANDW k1, k2, k3", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L1.0F.W0 41 /r", "visual_parts": [], "binary_pattern": "EVEX | 0F | 41", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "k2", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src2", "type": "k3", "desc": "AVX-512 opmask register (k0-k7)"}], "description": "Performs a bitwise AND operation on two 16-bit AVX-512 opmask registers and stores the result in a third opmask register. This is a mask-only operation that does not affect EFLAGS. The instruction operates on the lower 16 bits of the k registers; bits above 16 are zeroed in the destination.", "pseudocode": "k1[15:0] ← k2[15:0] & k3[15:0]; k1[63:16] ← 0;", "example": "KANDW k1, k2, k3"} {"mnemonic": "kandnw", "architecture": "x86", "full_name": "Bitwise Logical AND NOT Masks Word", "summary": "Bitwise AND NOT of 16-bit masks.", "syntax": "KANDNW k1, k2, k3", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L1.0F.W0 42 /r", "visual_parts": [], "binary_pattern": "EVEX | 0F | 42", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "k2", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src2", "type": "k3", "desc": "AVX-512 opmask register (k0-k7)"}], "description": "Performs a bitwise AND NOT operation (NOT src1 AND src2) on two 16-bit AVX-512 opmask registers and stores the result in a third opmask register. This is a mask-only operation that does not affect EFLAGS. Bits above 16 in the destination are zeroed.", "pseudocode": "k1[15:0] ← (~k2[15:0]) & k3[15:0]; k1[63:16] ← 0;", "example": "KANDNW k1, k2, k3"} {"mnemonic": "korw", "architecture": "x86", "full_name": "Bitwise Logical OR Masks Word", "summary": "Bitwise OR of 16-bit masks.", "syntax": "KORW k1, k2, k3", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L1.0F.W0 45 /r", "visual_parts": [], "binary_pattern": "EVEX | 0F | 45", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "k2", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src2", "type": "k3", "desc": "AVX-512 opmask register (k0-k7)"}], "description": "Performs a bitwise OR operation on two 16-bit AVX-512 opmask registers and stores the result in a third opmask register. This is a mask-only operation that does not affect EFLAGS. Bits above 16 in the destination are zeroed.", "pseudocode": "k1[15:0] ← k2[15:0] | k3[15:0]; k1[63:16] ← 0;", "example": "KORW k1, k2, k3"} {"mnemonic": "kxorw", "architecture": "x86", "full_name": "Bitwise Logical XOR Masks Word", "summary": "Bitwise XOR of 16-bit masks.", "syntax": "KXORW k1, k2, k3", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L1.0F.W0 47 /r", "visual_parts": [], "binary_pattern": "EVEX | 0F | 47", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src1", "type": "k2", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src2", "type": "k3", "desc": "AVX-512 opmask register (k0-k7)"}], "description": "Performs a bitwise XOR operation on two 16-bit AVX-512 opmask registers and stores the result in a third opmask register. This is a mask-only operation that does not affect EFLAGS. Bits above 16 in the destination are zeroed.", "pseudocode": "k1[15:0] ← k2[15:0] ^ k3[15:0]; k1[63:16] ← 0;", "example": "KXORW k1, k2, k3"} {"mnemonic": "knotw", "architecture": "x86", "full_name": "Bitwise Logical NOT Masks Word", "summary": "Bitwise NOT of 16-bit mask.", "syntax": "KNOTW k1, k2", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L0.0F.W0 44 /r", "visual_parts": [], "binary_pattern": "EVEX | 0F | 44", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src", "type": "k2", "desc": "AVX-512 opmask register (k0-k7)"}], "description": "Performs a bitwise NOT operation on a 16-bit AVX-512 opmask register and stores the result in another opmask register. This is a mask-only operation that does not affect EFLAGS. Bits above 16 in the destination are zeroed.", "pseudocode": "k1[15:0] ← ~k2[15:0]; k1[63:16] ← 0;", "example": "KNOTW k1, k2"} {"mnemonic": "kortestw", "architecture": "x86", "full_name": "OR Masks And Set Flags Word", "summary": "ORs two masks and sets EFLAGS (ZF, CF) based on result.", "syntax": "KORTESTW k1, k2", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L0.0F.W0 98 /r", "visual_parts": [], "binary_pattern": "EVEX | 0F | 98", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512", "operands": [{"name": "dest", "type": "k1", "desc": "AVX-512 opmask register (k0-k7)"}, {"name": "src", "type": "k2", "desc": "AVX-512 opmask register (k0-k7)"}], "description": "Performs a bitwise OR of two 16-bit AVX-512 opmask registers and sets EFLAGS based on the result. Sets ZF if the result is zero, CF if the result is 0xFFFF (all ones in the 16-bit field), and clears OF and SF. This instruction is typically used for predication and loop control in AVX-512 code.", "pseudocode": "temp ← k1[15:0] | k2[15:0]; ZF ← (temp == 0); CF ← (temp == 0xFFFF); OF ← 0; SF ← 0;", "example": "KORTESTW k1, k2"} {"mnemonic": "vpternlogd", "architecture": "x86", "full_name": "Packed Doubleword Ternary Logic", "summary": "Performs one of 256 logical operations on 3 inputs.", "syntax": "VPTERNLOGD zmm1 {k1}, zmm2, zmm3/m512, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F3A.W0 25 /r ib", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 3A | 25", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}, {"name": "src3", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Performs one of 256 possible three-input Boolean logical operations on 512-bit packed doublewords. The immediate operand selects which Boolean function to apply; supports opmask-controlled execution and writes to ZMM registers. No EFLAGS are affected; the instruction is fully predicated by {k1} if specified.", "pseudocode": "for i ← 0 to 15 do if k1[i] or k1 is not specified then zmm1[32*i+31:32*i] ← LUT256[imm8][zmm2[32*i+31:32*i], zmm3[32*i+31:32*i], zmm1[32*i+31:32*i]];", "example": "VPTERNLOGD zmm1, zmm2, zmm3/m512, 3"} {"mnemonic": "vpternlogq", "architecture": "x86", "full_name": "Packed Quadword Ternary Logic", "summary": "Performs one of 256 logical operations on 3 quadwords.", "syntax": "VPTERNLOGQ zmm1 {k1}, zmm2, zmm3/m512, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F3A.W1 25 /r ib", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 3A | 25", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}, {"name": "src3", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Performs one of 256 possible three-input Boolean logical operations on 512-bit packed quadwords. The immediate operand selects which Boolean function to apply; supports opmask-controlled execution and writes to ZMM registers. No EFLAGS are affected; the instruction is fully predicated by {k1} if specified.", "pseudocode": "for i ← 0 to 7 do if k1[i] or k1 is not specified then zmm1[64*i+63:64*i] ← LUT256[imm8][zmm2[64*i+63:64*i], zmm3[64*i+63:64*i], zmm1[64*i+63:64*i]];", "example": "VPTERNLOGQ zmm1, zmm2, zmm3/m512, 3"} {"mnemonic": "vcompresspd", "architecture": "x86", "full_name": "Store Sparse Packed Double-Precision Floating-Point Values", "summary": "Compresses active elements from ZMM to memory.", "syntax": "VCOMPRESSPD m512 {k1}, zmm1", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W1 8A /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 8A", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "m512", "desc": "512-bit memory operand"}, {"name": "src", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}], "description": "Stores active (mask-enabled) 64-bit double-precision floating-point elements from a ZMM register to memory in compressed form, where only the elements selected by the opmask k1 are written consecutively to the destination address. No flags are modified. Requires AVX-512F; operates on 512-bit ZMM registers and writes up to 512 bits of memory depending on mask population.", "pseudocode": "count ← 0\nfor i in 0 to 7:\n if k1[i] == 1:\n [dest + count * 8] ← ZMM2[i*64 : (i+1)*64]\n count ← count + 1", "example": "VCOMPRESSPD [rbp-64], zmm1"} {"mnemonic": "vcompressps", "architecture": "x86", "full_name": "Store Sparse Packed Single-Precision Floating-Point Values", "summary": "Compresses active elements from ZMM to memory.", "syntax": "VCOMPRESSPS m512 {k1}, zmm1", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W0 8A /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 8A", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "m512", "desc": "512-bit memory operand"}, {"name": "src", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}], "description": "Stores active (mask-enabled) 32-bit single-precision floating-point elements from a ZMM register to memory in compressed form, where only the elements selected by the opmask k1 are written consecutively to the destination address. No flags are modified. Requires AVX-512F; operates on 512-bit ZMM registers and writes up to 512 bits of memory depending on mask population.", "pseudocode": "count ← 0\nfor i in 0 to 15:\n if k1[i] == 1:\n [dest + count * 4] ← ZMM2[i*32 : (i+1)*32]\n count ← count + 1", "example": "VCOMPRESSPS [rbp-64], zmm1"} {"mnemonic": "vexpandpd", "architecture": "x86", "full_name": "Load Sparse Packed Double-Precision Floating-Point Values", "summary": "Expands data from memory into sparse locations in ZMM.", "syntax": "VEXPANDPD zmm1 {k1}, m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W1 88 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 88", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src", "type": "m512", "desc": "512-bit memory operand"}], "description": "Loads 64-bit double-precision floating-point elements from memory into a ZMM register at positions selected by the opmask k1, leaving masked-out positions unchanged if zeroing is not enabled. No flags are modified. Requires AVX-512F; reads from memory and expands sparse data into the 512-bit destination register.", "pseudocode": "count ← 0\nfor i in 0 to 7:\n if k1[i] == 1:\n ZMM1[i*64 : (i+1)*64] ← [src + count * 8]\n count ← count + 1\n else if k1[i] == 0 and zeroing == false:\n ZMM1[i*64 : (i+1)*64] ← ZMM1[i*64 : (i+1)*64]", "example": "VEXPANDPD zmm1, [rbp-64]"} {"mnemonic": "vexpandps", "architecture": "x86", "full_name": "Load Sparse Packed Single-Precision Floating-Point Values", "summary": "Expands data from memory into sparse locations in ZMM.", "syntax": "VEXPANDPS zmm1 {k1}, m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W0 88 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 88", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src", "type": "m512", "desc": "512-bit memory operand"}], "description": "Loads 32-bit single-precision floating-point elements from memory into a ZMM register at positions selected by the opmask k1, leaving masked-out positions unchanged if zeroing is not enabled. No flags are modified. Requires AVX-512F; reads from memory and expands sparse data into the 512-bit destination register.", "pseudocode": "count ← 0\nfor i in 0 to 15:\n if k1[i] == 1:\n ZMM1[i*32 : (i+1)*32] ← [src + count * 4]\n count ← count + 1\n else if k1[i] == 0 and zeroing == false:\n ZMM1[i*32 : (i+1)*32] ← ZMM1[i*32 : (i+1)*32]", "example": "VEXPANDPS zmm1, [rbp-64]"} {"mnemonic": "vpermi2d", "architecture": "x86", "full_name": "Permute Two-Source Doublewords", "summary": "Shuffles doublewords from two ZMM registers into destination.", "syntax": "VPERMI2D zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W0 76 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 76", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Permutes 32-bit doublewords from two source operands (zmm2 and zmm3/m512) using indices in zmm1 to produce a shuffled result in zmm1, where each 5-bit index selects one of 16 elements from each source. No flags are modified. Requires AVX-512F; results follow opmask k1 zeroing behavior. The index operand zmm1 is overwritten with the permuted result.", "pseudocode": "temp ← 0\nfor i in 0 to 15:\n if k1[i] == 1:\n idx ← ZMM1[i*32+4:i*32] & 0x1F\n if idx < 16:\n temp[i*32 : (i+1)*32] ← ZMM2[idx*32 : (idx+1)*32]\n else:\n temp[i*32 : (i+1)*32] ← ZMM3/M512[(idx-16)*32 : (idx-15)*32]\n else if zeroing == true:\n temp[i*32 : (i+1)*32] ← 0\n else:\n temp[i*32 : (i+1)*32] ← ZMM1[i*32 : (i+1)*32]\nZMM1 ← temp", "example": "VPERMI2D zmm1, zmm2, zmm3/m512"} {"mnemonic": "vpermt2d", "architecture": "x86", "full_name": "Permute Two-Source Doublewords (Overwrite)", "summary": "Shuffles 2 sources, overwriting the index register.", "syntax": "VPERMT2D zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W0 7E /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 7F", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Permutes 32-bit doublewords from two source operands (zmm2 and zmm3/m512) using indices in zmm1 to produce a shuffled result in zmm1, where each 5-bit index selects one of 16 elements from each source. No flags are modified. Requires AVX-512F; the index register zmm1 is overwritten with the permutation result and follows opmask k1 zeroing behavior.", "pseudocode": "temp ← 0\nfor i in 0 to 15:\n if k1[i] == 1:\n idx ← ZMM1[i*32+4:i*32] & 0x1F\n if idx < 16:\n temp[i*32 : (i+1)*32] ← ZMM2[idx*32 : (idx+1)*32]\n else:\n temp[i*32 : (i+1)*32] ← ZMM3/M512[(idx-16)*32 : (idx-15)*32]\n else if zeroing == true:\n temp[i*32 : (i+1)*32] ← 0\n else:\n temp[i*32 : (i+1)*32] ← ZMM1[i*32 : (i+1)*32]\nZMM1 ← temp", "example": "VPERMT2D zmm1, zmm2, zmm3/m512"} {"mnemonic": "vshuff32x4", "architecture": "x86", "full_name": "Shuffle Packed Float32x4", "summary": "Shuffles 128-bit blocks of single-precision floats.", "syntax": "VSHUFF32X4 zmm1 {k1}, zmm2, zmm3/m512, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.256.66.0F3A.W0 23 /r ib", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 3A | 23", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}, {"name": "src3", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Shuffles 128-bit blocks (each containing four 32-bit floats) from two ZMM sources according to an 8-bit immediate control, writing the result to the destination ZMM register. No flags are modified. Requires AVX-512F; the immediate selects which 128-bit quadwords are interleaved from the two sources. Opmask k1 controls which result elements are written.", "pseudocode": "temp ← 0\nfor i in 0 to 3:\n sel1 ← (imm8 >> (i*2)) & 0x3\n sel2 ← (imm8 >> (4 + i*2)) & 0x3\n temp[i*128 : (i+1)*128] ← ZMM2[sel1*128 : (sel1+1)*128]\n temp[(i+4)*128 : (i+5)*128] ← ZMM3/M512[sel2*128 : (sel2+1)*128]\nfor i in 0 to 15:\n if k1[i] == 1:\n ZMM1[i*32 : (i+1)*32] ← temp[i*32 : (i+1)*32]\n else if zeroing == true:\n ZMM1[i*32 : (i+1)*32] ← 0", "example": "VSHUFF32X4 zmm1, zmm2, zmm3/m512, 3"} {"mnemonic": "vpmovdb", "architecture": "x86", "full_name": "Truncate Doubleword to Byte", "summary": "Down-converts 32-bit integers to 8-bit.", "syntax": "VPMOVDB xmm1/m128 {k1}, zmm2", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.F3.0F38.W0 31 /r", "visual_parts": [], "binary_pattern": "EVEX | F3 | 0F | 38 | 31", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "xmm1/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}], "description": "Truncates 16 32-bit doubleword integers from a ZMM register down to 8-bit bytes, writing the 16 resulting bytes to an XMM register or 128-bit memory location. No flags are modified. Requires AVX-512F; the conversion is a simple truncation (low 8 bits extracted). Opmask k1 controls which byte results are written.", "pseudocode": "temp ← 0\nfor i in 0 to 15:\n if k1[i] == 1:\n temp[i*8 : (i+1)*8] ← ZMM2[i*32 : i*32+8]\n else if zeroing == true:\n temp[i*8 : (i+1)*8] ← 0\n else:\n temp[i*8 : (i+1)*8] ← temp[i*8 : (i+1)*8]\ndest[0 : 128] ← temp[0 : 128]", "example": "VPMOVDB xmm1/m128, zmm2"} {"mnemonic": "vpmovusdb", "architecture": "x86", "full_name": "Saturate Unsigned Doubleword to Byte", "summary": "Down-converts 32-bit to 8-bit with unsigned saturation.", "syntax": "VPMOVUSDB xmm1/m128 {k1}, zmm2", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.F3.0F38.W0 11 /r", "visual_parts": [], "binary_pattern": "EVEX | F3 | 0F | 38 | 11", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "xmm1/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}], "description": "Converts 16 packed 32-bit unsigned integers from a ZMM register to 16 packed 8-bit unsigned integers in an XMM register or memory, saturating values that exceed 255 to 255. The operation is element-wise; each 32-bit source value is independently clamped to the range [0, 255] and stored as an 8-bit result. Operates in 64-bit mode only and respects EVEX writemask {k1} for conditional element updates.", "pseudocode": "for i = 0 to 15:\n src_val = zmm2[i*32 + 31 : i*32]\n if src_val > 255:\n result[i*8 + 7 : i*8] = 255\n else:\n result[i*8 + 7 : i*8] = src_val[7:0]\nif k1_mask[i] == 1:\n dest[i*8 + 7 : i*8] = result[i*8 + 7 : i*8]\nelse if {z} == 1:\n dest[i*8 + 7 : i*8] = 0", "example": "VPMOVUSDB xmm1/m128, zmm2"} {"mnemonic": "vrndscalepd", "architecture": "x86", "full_name": "Round Packed Double-Precision Floating-Point with Scale", "summary": "Rounds doubles to integer values using imm8 control.", "syntax": "VRNDSCALEPD zmm1 {k1}, zmm2/m512, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F3A.W1 09 /r ib", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 3A | 09", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Rounds 8 packed 64-bit floating-point values to integer values using rounding control specified in imm8 (bits 3:0 select round-to-nearest-even, round-down, round-up, or round-toward-zero; bits 5:4 control sign, bits 7:6 control exception behavior). Destination is written with the scaled and rounded results. The instruction may set or clear floating-point exception flags (ZF, CF, OF, SF, PF) depending on the rounding results and imm8 exception control.", "pseudocode": "for i = 0 to 7:\n src_val = zmm2/m512[i*64 + 63 : i*64]\n round_mode = imm8[3:0]\n scaled_val = 2^(-(imm8[5:4])) * src_val\n rounded = RoundToIntegerFP(scaled_val, round_mode)\n result[i*64 + 63 : i*64] = rounded\n if (imm8[6] == 0 and FP_exception_raised):\n set_FP_exception_flags()\nif k1_mask[i] == 1:\n zmm1[i*64 + 63 : i*64] = result[i*64 + 63 : i*64]\nelse if {z} == 1:\n zmm1[i*64 + 63 : i*64] = 0", "example": "VRNDSCALEPD zmm1, zmm2/m512, 3"} {"mnemonic": "vfixupimmpd", "architecture": "x86", "full_name": "Fix Up Special Packed Float64 Values", "summary": "Fixes special cases (NaN, Inf) using a table.", "syntax": "VFIXUPIMMPD zmm1 {k1}, zmm2, zmm3/m512, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F3A.W1 54 /r ib", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 3A | 54", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}, {"name": "src3", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Fixes up special floating-point cases (NaN, Infinity, denormalized) in 8 packed 64-bit values using a lookup table indexed by imm8 and the class/sign of each element. For each source element, the instruction examines the exceptional condition bits and uses imm8 to select a fixup value or pass-through behavior. The result is placed in the destination; may set floating-point exception flags (ZF, CF, OF, SF, PF) if exceptions are not suppressed.", "pseudocode": "for i = 0 to 7:\n src1_val = zmm2[i*64 + 63 : i*64]\n src2_val = zmm3/m512[i*64 + 63 : i*64]\n class_bits = ClassifyFP64(src1_val)\n index = (imm8[1:0] << 2) | class_bits[1:0]\n lookup_result = FIXUP_TABLE[index]\n if lookup_result == PASS_THROUGH:\n result[i*64 + 63 : i*64] = src1_val\n else if lookup_result == USE_SRC2:\n result[i*64 + 63 : i*64] = src2_val\n else:\n result[i*64 + 63 : i*64] = lookup_result\n if (imm8[3:2] != 11 and exception_condition):\n set_FP_exception_flags()\nif k1_mask[i] == 1:\n zmm1[i*64 + 63 : i*64] = result[i*64 + 63 : i*64]\nelse if {z} == 1:\n zmm1[i*64 + 63 : i*64] = 0", "example": "VFIXUPIMMPD zmm1, zmm2, zmm3/m512, 3"} {"mnemonic": "vgetmantpd", "architecture": "x86", "full_name": "Get Mantissa Packed Double-Precision", "summary": "Extracts mantissas from doubles.", "syntax": "VGETMANTPD zmm1 {k1}, zmm2/m512, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F3A.W1 26 /r ib", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 3A | 26", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Extracts the mantissa (significand) from 8 packed 64-bit floating-point values and returns them as normalized floating-point results. The imm8 parameter controls which portion of the mantissa is returned (e.g., ±[1.0, 2.0), ±[0.5, 1.0), etc.) and the rounding mode for the mantissa extraction. Denormalized inputs and exceptional cases may be handled according to imm8 bits; floating-point exception flags may be set depending on exception handling mode.", "pseudocode": "for i = 0 to 7:\n src_val = zmm2/m512[i*64 + 63 : i*64]\n mantissa_mode = imm8[1:0]\n round_mode = imm8[3:2]\n suppress_exceptions = imm8[4]\n mantissa = ExtractMantissa(src_val, mantissa_mode)\n rounded_mantissa = RoundMantissa(mantissa, round_mode)\n result[i*64 + 63 : i*64] = rounded_mantissa\n if (suppress_exceptions == 0 and exception_condition):\n set_FP_exception_flags()\nif k1_mask[i] == 1:\n zmm1[i*64 + 63 : i*64] = result[i*64 + 63 : i*64]\nelse if {z} == 1:\n zmm1[i*64 + 63 : i*64] = 0", "example": "VGETMANTPD zmm1, zmm2/m512, 3"} {"mnemonic": "vgetexppd", "architecture": "x86", "full_name": "Get Exponent Packed Double-Precision", "summary": "Extracts exponents from doubles as float values.", "syntax": "VGETEXPPD zmm1 {k1}, zmm2/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W1 42 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 42", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src", "type": "zmm2/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Extracts the exponent from 8 packed 64-bit floating-point values and returns each exponent as a 64-bit floating-point value (i.e., the unbiased exponent is converted to a double-precision floating-point number). Special cases such as zero, denormalized, infinite, and NaN inputs follow IEEE 754 semantics; floating-point exception flags (ZF, CF, OF, SF, PF) may be set depending on the nature of the inputs and masking.", "pseudocode": "for i = 0 to 7:\n src_val = zmm2/m512[i*64 + 63 : i*64]\n if is_zero(src_val):\n result[i*64 + 63 : i*64] = -INF\n else if is_denormal(src_val):\n exp_val = MIN_EXPONENT\n result[i*64 + 63 : i*64] = ConvertToFP64(exp_val)\n else if is_infinity(src_val):\n result[i*64 + 63 : i*64] = +INF\n else if is_nan(src_val):\n result[i*64 + 63 : i*64] = NaN\n else:\n unbiased_exp = ExtractExponent(src_val) - BIAS\n result[i*64 + 63 : i*64] = ConvertToFP64(unbiased_exp)\nif k1_mask[i] == 1:\n zmm1[i*64 + 63 : i*64] = result[i*64 + 63 : i*64]\nelse if {z} == 1:\n zmm1[i*64 + 63 : i*64] = 0", "example": "VGETEXPPD zmm1, zmm2/m512"} {"mnemonic": "vscalefpd", "architecture": "x86", "full_name": "Scale Packed Float64 Values with Float64 Exponents", "summary": "Scales doubles by exponents (x * 2^n).", "syntax": "VSCALEFPD zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W1 2C /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 2C", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Scales 8 packed 64-bit floating-point values by raising 2 to the power of the corresponding exponent value (dst = src1 * 2^src2) using floating-point exponentiation. Each element of src2 is treated as an integer exponent; the result is computed with full floating-point precision. The instruction may set or clear floating-point exception flags (ZF, CF, OF, SF, PF) based on overflow, underflow, or other exceptional conditions.", "pseudocode": "for i = 0 to 7:\n mantissa = zmm2[i*64 + 63 : i*64]\n exponent = zmm3/m512[i*64 + 63 : i*64]\n exp_int = ConvertToInt(exponent)\n if exp_int > MAX_EXP:\n result[i*64 + 63 : i*64] = INF (sign from mantissa)\n set_FP_exception_flag(OVERFLOW)\n else if exp_int < MIN_EXP:\n result[i*64 + 63 : i*64] = 0.0 (sign from mantissa)\n set_FP_exception_flag(UNDERFLOW)\n else:\n scaled = mantissa * (2.0 ^ exp_int)\n result[i*64 + 63 : i*64] = scaled\nif k1_mask[i] == 1:\n zmm1[i*64 + 63 : i*64] = result[i*64 + 63 : i*64]\nelse if {z} == 1:\n zmm1[i*64 + 63 : i*64] = 0", "example": "VSCALEFPD zmm1, zmm2, zmm3/m512"} {"mnemonic": "valignd", "architecture": "x86", "full_name": "Align Doubleword Vectors", "summary": "Extracts 512-bits from two concatenated ZMMs shifted by count.", "syntax": "VALIGND zmm1 {k1}, zmm2, zmm3/m512, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F3A.W0 03 /r ib", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 3A | 03", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}, {"name": "src3", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Extracts 512 bits from the concatenation of two ZMM registers (src2 || src1), where src2 is the high part, shifted right by imm8 * 32 bits, and writes the result to dest. This acts as a multi-element rotate-right or barrel-shift operation on the combined 1024-bit value. All 16 packed 32-bit doubleword elements shift by the same amount; elements that shift out are discarded, and zero-fill enters from the left. Operates only in 64-bit mode.", "pseudocode": "shift_amount = imm8 * 32\ntemp_concat = (zmm2[511:0] << 512) | zmm1[511:0]\nresult = temp_concat >> shift_amount\nfor i = 0 to 15:\n result_dword[i] = result[(i+1)*32 - 1 : i*32]\nif k1_mask[i] == 1:\n zmm1[i*32 + 31 : i*32] = result_dword[i]\nelse if {z} == 1:\n zmm1[i*32 + 31 : i*32] = 0", "example": "VALIGND zmm1, zmm2, zmm3/m512, 3"} {"mnemonic": "vpconflictd", "architecture": "x86", "full_name": "Detect Conflicts Within a Vector of Packed Dword Values", "summary": "Detects duplicate values in a vector (Conflict Detection).", "syntax": "VPCONFLICTD zmm1 {k1}, zmm2/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W0 C4 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | C4", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512CD", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src", "type": "zmm2/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Detects conflicting (duplicate) values within a vector of 16 packed 32-bit unsigned integers and writes a conflict mask to the destination. For each element, the instruction generates a 32-bit mask where bit j is set to 1 if the element at position i equals the element at position j (where j > i). This enables efficient identification of duplicate elements within a single vector. Operates only in 64-bit mode; no arithmetic flags are modified.", "pseudocode": "for i = 0 to 15:\n conflict_mask = 0\n for j = i + 1 to 15:\n if zmm2/m512[i*32 + 31 : i*32] == zmm2/m512[j*32 + 31 : j*32]:\n conflict_mask |= (1 << j)\n result[i*32 + 31 : i*32] = conflict_mask\nif k1_mask[i] == 1:\n zmm1[i*32 + 31 : i*32] = result[i*32 + 31 : i*32]\nelse if {z} == 1:\n zmm1[i*32 + 31 : i*32] = 0", "example": "VPCONFLICTD zmm1, zmm2/m512"} {"mnemonic": "vplzcntd", "architecture": "x86", "full_name": "Count Leading Zero Bits", "summary": "Counts leading zeros for each doubleword element.", "syntax": "VPLZCNTD zmm1 {k1}, zmm2/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W0 44 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 44", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512CD", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src", "type": "zmm2/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Counts the number of leading zero bits in each 32-bit doubleword element of the source operand and writes the count to the corresponding doubleword in the destination. Operates on 512-bit vectors under EVEX encoding with optional write-mask (k1) and zeroing. No EFLAGS are affected by this instruction.", "pseudocode": "for i = 0 to 15 do\n src_val = zmm2[i*32 : (i+1)*32-1]\n count = 0\n for j = 31 downto 0 do\n if src_val[j] == 1 then break\n count++\n zmm1[i*32 : (i+1)*32-1] = count\nend for", "example": "VPLZCNTD zmm1, zmm2/m512"} {"mnemonic": "vcvtudq2ps", "architecture": "x86", "full_name": "Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point", "summary": "Converts unsigned int32 to float.", "syntax": "VCVTUDQ2PS zmm1 {k1}, zmm2/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.F2.0F.W0 7A /r", "visual_parts": [], "binary_pattern": "EVEX | F2 | 0F | 5B", "bit_positions": "+0 | +4 | +5 | +6"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src", "type": "zmm2/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Converts each 32-bit unsigned integer in the source to a single-precision floating-point value and stores the result in the destination. Operates on 512-bit vectors under EVEX encoding with optional write-mask (k1) and rounding control. No EFLAGS are affected; rounding follows MXCSR or embedded rounding mode.", "pseudocode": "for i = 0 to 15 do\n src_val = zmm2[i*32 : (i+1)*32-1]\n zmm1[i*32 : (i+1)*32-1] = convert_uint32_to_float32(src_val, rounding_mode)\nend for", "example": "VCVTUDQ2PS zmm1, zmm2/m512"} {"mnemonic": "vprolvd", "architecture": "x86", "full_name": "Rotate Left Doubleword Variable", "summary": "Rotates doublewords left by amounts in second vector.", "syntax": "VPROLVD zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W0 15 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 15", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512F", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Rotates each 32-bit element in the first source left by the amount specified in the corresponding 32-bit element of the second source, storing results in the destination. Operates on 512-bit vectors under EVEX encoding with optional write-mask (k1). The rotation amount is taken modulo 32. No EFLAGS are affected.", "pseudocode": "for i = 0 to 15 do\n value = zmm2[i*32 : (i+1)*32-1]\n shift = zmm3[i*32 : (i+1)*32-1] & 0x1F\n zmm1[i*32 : (i+1)*32-1] = (value << shift) | (value >> (32 - shift))\nend for", "example": "VPROLVD zmm1, zmm2, zmm3/m512"} {"mnemonic": "vpopcntd", "architecture": "x86", "full_name": "Packed Population Count Doubleword", "summary": "Counts set bits in each doubleword element.", "syntax": "VPOPCNTD zmm1 {k1}, zmm2/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W0 55 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 55", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512-VPOPCNTDQ", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src", "type": "zmm2/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Counts the number of set bits (1s) in each 32-bit doubleword element of the source operand and writes the population count to the corresponding doubleword in the destination. Operates on 512-bit vectors under EVEX encoding with optional write-mask (k1) and zeroing. No EFLAGS are affected.", "pseudocode": "for i = 0 to 15 do\n src_val = zmm2[i*32 : (i+1)*32-1]\n count = 0\n for j = 0 to 31 do\n if src_val[j] == 1 then count++\n zmm1[i*32 : (i+1)*32-1] = count\nend for", "example": "VPOPCNTD zmm1, zmm2/m512"} {"mnemonic": "encls", "architecture": "x86", "full_name": "Execute Enclave Supervisor Leaf", "summary": "Executes an SGX supervisor function specified by EAX.", "syntax": "ENCLS", "encoding": {"format": "Legacy", "hex_opcode": "NP 0F 01 CF", "visual_parts": [], "binary_pattern": "0F | 01 | CF", "bit_positions": "+0 | +1 | +2"}, "extension": "SGX", "operands": [], "description": "Executes an SGX supervisor enclave leaf function specified by a leaf number in EAX. The instruction serializes the CPU pipeline and transitions from non-root mode to root mode for executing privileged enclave operations. The actual operation depends on the leaf function code; CF flag may be set on error conditions, and various other registers may be modified based on the leaf function.", "pseudocode": "leaf_function = EAX\nif (leaf_function == EBLOCK) then\n // Block enclave\nelseif (leaf_function == ETRACK) then\n // Flush TLB\nelseif (leaf_function == EWBLOCK) then\n // Write block enclave\nelse\n // Execute other supervisor leaf functions\nend if", "example": "ENCLS"} {"mnemonic": "enclu", "architecture": "x86", "full_name": "Execute Enclave User Leaf", "summary": "Executes an SGX user function specified by EAX.", "syntax": "ENCLU", "encoding": {"format": "Legacy", "hex_opcode": "NP 0F 01 D7", "visual_parts": [], "binary_pattern": "0F | 01 | D7", "bit_positions": "+0 | +1 | +2"}, "extension": "SGX", "operands": [], "description": "Executes an SGX user enclave leaf function specified by a leaf number in EAX. The instruction serializes the CPU pipeline and may transition between user and enclave execution modes depending on the leaf function. The actual operation depends on the leaf function code; various registers and flags may be modified based on the requested operation.", "pseudocode": "leaf_function = EAX\nif (leaf_function == EREPORT) then\n // Generate enclave report\nelseif (leaf_function == EGETKEY) then\n // Get sealing/reporting key\nelseif (leaf_function == EEXIT) then\n // Exit enclave\nelseif (leaf_function == EENTER) then\n // Enter enclave\nelse\n // Execute other user leaf functions\nend if", "example": "ENCLU"} {"mnemonic": "extrq", "architecture": "x86", "full_name": "Extract Field from Register", "summary": "Extracts bit field from register (AMD SSE4a).", "syntax": "EXTRQ xmm1, xmm2", "encoding": {"format": "SSE4a", "hex_opcode": "66 0F 79 /r", "visual_parts": [], "binary_pattern": "66 | 0F | 79 | ModRM", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4a", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2", "desc": "128-bit XMM SIMD register"}], "description": "Extracts a bit field from the 128-bit xmm1 register using the field length and field position specified in xmm2 bits [13:8] and [5:0] respectively. The extracted field is zero-extended and placed in xmm1; bits not part of the extracted field are zeroed. No EFLAGS are affected; this is an AMD SSE4a extension instruction.", "pseudocode": "field_length = xmm2[13:8]\nfield_pos = xmm2[5:0]\nif (field_length == 0) then\n field_length = 64\nend if\nmask = ((1 << field_length) - 1)\nextracted = (xmm1 >> field_pos) & mask\nxmm1 = extracted", "example": "EXTRQ xmm1, xmm2"} {"mnemonic": "insertq", "architecture": "x86", "full_name": "Insert Field to Register", "summary": "Inserts bit field into register (AMD SSE4a).", "syntax": "INSERTQ xmm1, xmm2", "encoding": {"format": "SSE4a", "hex_opcode": "F2 0F 79 /r", "visual_parts": [], "binary_pattern": "66 | 0F | 79 | ModRM", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "SSE4a", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2", "desc": "128-bit XMM SIMD register"}], "description": "Inserts a bit field from xmm2 into xmm1 at the position and length specified in xmm2 bits [13:8] and [5:0] respectively. The field from xmm2 is placed into xmm1 starting at the specified bit position; the rest of xmm1 remains unchanged. No EFLAGS are affected; this is an AMD SSE4a extension instruction.", "pseudocode": "field_length = xmm2[13:8]\nfield_pos = xmm2[5:0]\nif (field_length == 0) then\n field_length = 64\nend if\nmask = ((1 << field_length) - 1)\ninsert_value = xmm2 & mask\nxmm1 = (xmm1 & ~(mask << field_pos)) | (insert_value << field_pos)", "example": "INSERTQ xmm1, xmm2"} {"mnemonic": "movntss", "architecture": "x86", "full_name": "Move Non-Temporal Scalar Single", "summary": "Stores scalar float bypassing cache (AMD SSE4a).", "syntax": "MOVNTSS m32, xmm1", "encoding": {"format": "SSE4a", "hex_opcode": "F3 0F 2B /r", "visual_parts": [], "binary_pattern": "F3 | 0F | 2B", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE4a", "operands": [{"name": "dest", "type": "m32", "desc": "32-bit memory operand"}, {"name": "src", "type": "xmm1", "desc": "128-bit XMM SIMD register"}], "description": "Stores the low 32-bit scalar single-precision floating-point value from an XMM register to a 32-bit memory location, bypassing the cache hierarchy using non-temporal semantics. The instruction issues a weakly-ordered write that avoids polluting the L1/L2 caches, useful for streaming writes. No arithmetic flags are affected; this is a memory store only.", "pseudocode": "[dest] ← src[31:0];", "example": "MOVNTSS [rbp-4], xmm1"} {"mnemonic": "movntsd", "architecture": "x86", "full_name": "Move Non-Temporal Scalar Double", "summary": "Stores scalar double bypassing cache (AMD SSE4a).", "syntax": "MOVNTSD m64, xmm1", "encoding": {"format": "SSE4a", "hex_opcode": "F2 0F 2B /r", "visual_parts": [], "binary_pattern": "F2 | 0F | 2B", "bit_positions": "+0 | +1 | +2"}, "extension": "SSE4a", "operands": [{"name": "dest", "type": "m64", "desc": "64-bit memory operand (quadword)"}, {"name": "src", "type": "xmm1", "desc": "128-bit XMM SIMD register"}], "description": "Stores the low 64-bit scalar double-precision floating-point value from an XMM register to a 64-bit memory location, bypassing the cache hierarchy using non-temporal semantics. Similar to MOVNTSS but for 64-bit double-precision values; useful for streaming writes of double-precision data. No arithmetic flags are affected; this is a memory store only.", "pseudocode": "[dest] ← src[63:0];", "example": "MOVNTSD [rbp-8], xmm1"} {"mnemonic": "clzero", "architecture": "x86", "full_name": "Zero Cache Line", "summary": "Clears the cache line at address RAX/EAX (AMD).", "syntax": "CLZERO", "encoding": {"format": "AMD", "hex_opcode": "0F 01 FC", "visual_parts": [], "binary_pattern": "0F | 01 | FC", "bit_positions": "+0 | +1 | +2"}, "extension": "CLZERO", "operands": [], "description": "Zeros (clears) a 64-byte cache line at the address held in RAX (in 64-bit mode) or EAX (in 32-bit mode), writing zeros to memory while bypassing caches. This instruction is a non-temporal operation useful for initializing large memory regions without cache pollution. No flags are affected; the memory is written directly and cache coherency is maintained.", "pseudocode": "lineaddr ← RAX & ~0x3F; memset([lineaddr], 0, 64);", "example": "CLZERO"} {"mnemonic": "blci", "architecture": "x86", "full_name": "Bit Line Create Isolated", "summary": "Sets all bits to 0 except the lowest set bit inverted (x | ~(x+1)).", "syntax": "BLCI r32, r/m32", "encoding": {"format": "TBM", "hex_opcode": "XOP.L0.09.W0 02 /6", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "TBM", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src", "type": "r/m32", "desc": "32-bit register or memory"}], "description": "Computes (src | ~(src+1)) and stores the result in dest, isolating all bits except the lowest set bit (which is inverted). Part of the TBM (Trailing Bit Manipulation) extension; sets flags based on the result: ZF if result is zero, SF based on sign bit, and CF/OF/PF are undefined. Available in 32-bit and 64-bit variants.", "pseudocode": "result ← src | ~(src + 1); dest ← result; ZF ← (result == 0); SF ← result[31]; CF ← undefined; OF ← undefined; PF ← undefined;", "example": "BLCI eax, ebx"} {"mnemonic": "blcic", "architecture": "x86", "full_name": "Bit Line Create Isolated and Complement", "summary": "Isolates lowest clear bit (~x & (x+1)).", "syntax": "BLCIC r32, r/m32", "encoding": {"format": "TBM", "hex_opcode": "XOP.L0.09.W0 01 /5", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "TBM", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src", "type": "r/m32", "desc": "32-bit register or memory"}], "description": "Computes (~src & (src+1)) and stores the result in dest, isolating the lowest clear (zero) bit. Part of the TBM extension; sets ZF if result is zero and SF based on the sign bit of the result; CF, OF, and PF are undefined. Available in 32-bit and 64-bit variants.", "pseudocode": "result ← ~src & (src + 1); dest ← result; ZF ← (result == 0); SF ← result[31]; CF ← undefined; OF ← undefined; PF ← undefined;", "example": "BLCIC eax, ebx"} {"mnemonic": "blcmsk", "architecture": "x86", "full_name": "Bit Line Create Mask", "summary": "Creates mask from lowest clear bit (x ^ (x+1)).", "syntax": "BLCMSK r32, r/m32", "encoding": {"format": "TBM", "hex_opcode": "XOP.L0.09.W0 02 /1", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "TBM", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src", "type": "r/m32", "desc": "32-bit register or memory"}], "description": "Computes (src ^ (src+1)) and stores the result in dest, creating a mask from the lowest clear bit to bit 0. Part of the TBM extension; sets ZF if result is zero and SF based on the sign bit of the result; CF, OF, and PF are undefined. Available in 32-bit and 64-bit variants.", "pseudocode": "result ← src ^ (src + 1); dest ← result; ZF ← (result == 0); SF ← result[31]; CF ← undefined; OF ← undefined; PF ← undefined;", "example": "BLCMSK eax, ebx"} {"mnemonic": "blcs", "architecture": "x86", "full_name": "Bit Line Create Set", "summary": "Sets lowest clear bit (x | (x+1)).", "syntax": "BLCS r32, r/m32", "encoding": {"format": "TBM", "hex_opcode": "XOP.L0.09.W0 01 /3", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "TBM", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src", "type": "r/m32", "desc": "32-bit register or memory"}], "description": "Computes (src | (src+1)) and stores the result in dest, setting the lowest clear bit. Part of the TBM extension; sets ZF if result is zero and SF based on the sign bit of the result; CF, OF, and PF are undefined. Available in 32-bit and 64-bit variants.", "pseudocode": "result ← src | (src + 1); dest ← result; ZF ← (result == 0); SF ← result[31]; CF ← undefined; OF ← undefined; PF ← undefined;", "example": "BLCS eax, ebx"} {"mnemonic": "blsfill", "architecture": "x86", "full_name": "Bit Line Set Fill", "summary": "Sets all bits below lowest set bit ((x-1) | x).", "syntax": "BLSFILL r32, r/m32", "encoding": {"format": "TBM", "hex_opcode": "XOP.L0.09.W0 01 /2", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "TBM", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src", "type": "r/m32", "desc": "32-bit register or memory"}], "description": "Computes ((src-1) | src) and stores the result in dest, filling all bits below and including the lowest set bit. Part of the TBM extension; sets ZF if result is zero and SF based on the sign bit of the result; CF, OF, and PF are undefined. Available in 32-bit and 64-bit variants.", "pseudocode": "result ← (src - 1) | src; dest ← result; ZF ← (result == 0); SF ← result[31]; CF ← undefined; OF ← undefined; PF ← undefined;", "example": "BLSFILL eax, ebx"} {"mnemonic": "blsic", "architecture": "x86", "full_name": "Bit Line Set Isolated and Complement", "summary": "Isolates lowest set bit and complements (~x | (x-1)).", "syntax": "BLSIC r32, r/m32", "encoding": {"format": "TBM", "hex_opcode": "XOP.L0.09.W0 01 /6", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "TBM", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src", "type": "r/m32", "desc": "32-bit register or memory"}], "description": "Isolates the lowest set bit and complements the result, computing ~src | (src - 1). This TBM instruction is useful for extracting bit masks and operates on 32-bit operands in protected/64-bit modes. No flags are modified by this instruction.", "pseudocode": "dest ← ~src | (src - 1)", "example": "BLSIC eax, ebx"} {"mnemonic": "t1mskc", "architecture": "x86", "full_name": "Inverse Mask From Trailing Ones", "summary": "Creates mask from trailing ones (~x | (x+1)).", "syntax": "T1MSKC r32, r/m32", "encoding": {"format": "TBM", "hex_opcode": "XOP.L0.09.W0 01 /7", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "TBM", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src", "type": "r/m32", "desc": "32-bit register or memory"}], "description": "Creates a mask from trailing ones by computing ~src | (src + 1), isolating all bits from the least significant one through trailing ones. This TBM instruction operates on 32-bit operands and does not modify CPU flags.", "pseudocode": "dest ← ~src | (src + 1)", "example": "T1MSKC eax, ebx"} {"mnemonic": "tzmsk", "architecture": "x86", "full_name": "Mask From Trailing Zeros", "summary": "Creates mask from trailing zeros (~x & (x-1)).", "syntax": "TZMSK r32, r/m32", "encoding": {"format": "TBM", "hex_opcode": "XOP.L0.09.W0 01 /4", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "TBM", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src", "type": "r/m32", "desc": "32-bit register or memory"}], "description": "Creates a mask from trailing zeros by computing ~src & (src - 1), isolating only the trailing zero bits. This TBM instruction operates on 32-bit operands in protected/64-bit modes and does not modify any CPU flags.", "pseudocode": "dest ← ~src & (src - 1)", "example": "TZMSK eax, ebx"} {"mnemonic": "vprotb", "architecture": "x86", "full_name": "Vector Packed Rotate Byte", "summary": "Rotates bytes in XMM register.", "syntax": "VPROTB xmm1, xmm2/m128, imm8", "encoding": {"format": "XOP", "hex_opcode": "XOP.128.08.W0 C0 /r ib", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "XOP", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Rotates each byte within a 128-bit XMM register by the amount specified in the 8-bit signed immediate, with rotation direction determined by the sign of the immediate (positive = left rotate, negative = right rotate). This XOP instruction is part of the AMD Bulldozer-era vector extensions and does not modify CPU flags.", "pseudocode": "for i in 0..15:\n if (imm8 >= 0):\n xmm1[i*8+7:i*8] ← ROL(src1[i*8+7:i*8], imm8 & 7)\n else:\n xmm1[i*8+7:i*8] ← ROR(src1[i*8+7:i*8], (-imm8) & 7)", "example": "VPROTB xmm1, xmm2/m128, 3"} {"mnemonic": "vprotw", "architecture": "x86", "full_name": "Vector Packed Rotate Word", "summary": "Rotates words in XMM register.", "syntax": "VPROTW xmm1, xmm2/m128, imm8", "encoding": {"format": "XOP", "hex_opcode": "XOP.128.08.W0 C1 /r ib", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "XOP", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Rotates each 16-bit word within a 128-bit XMM register by the amount specified in the 8-bit signed immediate, with rotation direction determined by sign (positive = left rotate, negative = right rotate). This XOP vector instruction does not modify CPU flags.", "pseudocode": "for i in 0..7:\n if (imm8 >= 0):\n xmm1[i*16+15:i*16] ← ROL(src1[i*16+15:i*16], imm8 & 15)\n else:\n xmm1[i*16+15:i*16] ← ROR(src1[i*16+15:i*16], (-imm8) & 15)", "example": "VPROTW xmm1, xmm2/m128, 3"} {"mnemonic": "vprotd", "architecture": "x86", "full_name": "Vector Packed Rotate Doubleword", "summary": "Rotates doublewords in XMM register.", "syntax": "VPROTD xmm1, xmm2/m128, imm8", "encoding": {"format": "XOP", "hex_opcode": "XOP.128.08.W0 C2 /r ib", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "XOP", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Rotates each 32-bit doubleword within a 128-bit XMM register by the amount specified in the 8-bit signed immediate, with rotation direction determined by sign (positive = left rotate, negative = right rotate). This XOP instruction does not affect CPU flags.", "pseudocode": "for i in 0..3:\n if (imm8 >= 0):\n xmm1[i*32+31:i*32] ← ROL(src1[i*32+31:i*32], imm8 & 31)\n else:\n xmm1[i*32+31:i*32] ← ROR(src1[i*32+31:i*32], (-imm8) & 31)", "example": "VPROTD xmm1, xmm2/m128, 3"} {"mnemonic": "vprotq", "architecture": "x86", "full_name": "Vector Packed Rotate Quadword", "summary": "Rotates quadwords in XMM register.", "syntax": "VPROTQ xmm1, xmm2/m128, imm8", "encoding": {"format": "XOP", "hex_opcode": "XOP.128.08.W0 C3 /r ib", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "XOP", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Rotates each 64-bit quadword within a 128-bit XMM register by the amount specified in the 8-bit signed immediate, with rotation direction determined by sign (positive = left rotate, negative = right rotate). This XOP vector instruction does not modify CPU flags.", "pseudocode": "for i in 0..1:\n if (imm8 >= 0):\n xmm1[i*64+63:i*64] ← ROL(src1[i*64+63:i*64], imm8 & 63)\n else:\n xmm1[i*64+63:i*64] ← ROR(src1[i*64+63:i*64], (-imm8) & 63)", "example": "VPROTQ xmm1, xmm2/m128, 3"} {"mnemonic": "vpshab", "architecture": "x86", "full_name": "Vector Packed Shift Arithmetic Byte", "summary": "Shifts bytes arithmetically.", "syntax": "VPSHAB xmm1, xmm2/m128, xmm3", "encoding": {"format": "XOP", "hex_opcode": "XOP.128.09.W0 98 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "XOP", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Performs arithmetic left or right shift on each byte element within a 128-bit XMM register based on the 8-bit signed immediate, with positive values for left shift and negative for right shift (sign-extending). This XOP instruction does not modify CPU flags.", "pseudocode": "for i in 0..15:\n if (imm8 >= 0):\n xmm1[i*8+7:i*8] ← src1[i*8+7:i*8] << (imm8 & 7)\n else:\n xmm1[i*8+7:i*8] ← arithmetic_shift_right(src1[i*8+7:i*8], (-imm8) & 7)", "example": "VPSHAB xmm1, xmm2/m128, 3"} {"mnemonic": "vpshaw", "architecture": "x86", "full_name": "Vector Packed Shift Arithmetic Word", "summary": "Shifts words arithmetically.", "syntax": "VPSHAW xmm1, xmm2/m128, xmm3", "encoding": {"format": "XOP", "hex_opcode": "XOP.128.09.W0 99 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "XOP", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Shifts each 16-bit word in xmm2/m128 arithmetically by the signed immediate count, storing results in xmm1. Arithmetic right shifts replicate the sign bit; left shifts fill with zeros. This XOP extension instruction operates on 128-bit packed word data and does not affect EFLAGS.", "pseudocode": "for i = 0 to 7 {\n if (imm8 >= 0) {\n xmm1[16*i:16*i+15] ← (xmm2/m128[16*i:16*i+15]) << imm8\n } else {\n xmm1[16*i:16*i+15] ← (xmm2/m128[16*i:16*i+15]) >> (-imm8) // arithmetic shift\n }\n}", "example": "VPSHAW xmm1, xmm2/m128, 3"} {"mnemonic": "vpshad", "architecture": "x86", "full_name": "Vector Packed Shift Arithmetic Doubleword", "summary": "Shifts doublewords arithmetically.", "syntax": "VPSHAD xmm1, xmm2/m128, xmm3", "encoding": {"format": "XOP", "hex_opcode": "XOP.128.09.W0 9A /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "XOP", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Shifts each 32-bit doubleword in xmm2/m128 arithmetically by the signed immediate count, storing results in xmm1. Arithmetic right shifts preserve the sign bit; left shifts fill with zeros. This XOP extension instruction operates on 128-bit packed doubleword data and does not affect EFLAGS.", "pseudocode": "for i = 0 to 3 {\n if (imm8 >= 0) {\n xmm1[32*i:32*i+31] ← (xmm2/m128[32*i:32*i+31]) << imm8\n } else {\n xmm1[32*i:32*i+31] ← (xmm2/m128[32*i:32*i+31]) >> (-imm8) // arithmetic shift\n }\n}", "example": "VPSHAD xmm1, xmm2/m128, 3"} {"mnemonic": "vpshaq", "architecture": "x86", "full_name": "Vector Packed Shift Arithmetic Quadword", "summary": "Shifts quadwords arithmetically.", "syntax": "VPSHAQ xmm1, xmm2/m128, xmm3", "encoding": {"format": "XOP", "hex_opcode": "XOP.128.09.W0 9B /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "XOP", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}, {"name": "src2", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Shifts each 64-bit quadword in xmm2/m128 arithmetically by the signed immediate count, storing results in xmm1. Arithmetic right shifts maintain the sign bit; left shifts fill with zeros. This XOP extension instruction operates on 128-bit packed quadword data and does not affect EFLAGS.", "pseudocode": "for i = 0 to 1 {\n if (imm8 >= 0) {\n xmm1[64*i:64*i+63] ← (xmm2/m128[64*i:64*i+63]) << imm8\n } else {\n xmm1[64*i:64*i+63] ← (xmm2/m128[64*i:64*i+63]) >> (-imm8) // arithmetic shift\n }\n}", "example": "VPSHAQ xmm1, xmm2/m128, 3"} {"mnemonic": "vphaddbw", "architecture": "x86", "full_name": "Vector Packed Horizontal Add Byte to Word", "summary": "Adds adjacent bytes to words.", "syntax": "VPHADDBW xmm1, xmm2/m128", "encoding": {"format": "XOP", "hex_opcode": "XOP.128.09.W0 C1 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "XOP", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Horizontally adds adjacent pairs of signed 8-bit bytes from xmm2/m128, accumulating results as 16-bit words in xmm1. Each pair of bytes produces one 16-bit word result; the operation doubles the data width. This XOP extension instruction does not affect EFLAGS and handles signed arithmetic with saturation or wrapping semantics dependent on implementation.", "pseudocode": "for i = 0 to 7 {\n xmm1[16*i:16*i+15] ← sign_extend(xmm2/m128[8*(2*i):8*(2*i)+7]) + sign_extend(xmm2/m128[8*(2*i+1):8*(2*i+1)+7])\n}", "example": "VPHADDBW xmm1, xmm2/m128"} {"mnemonic": "vphaddbd", "architecture": "x86", "full_name": "Vector Packed Horizontal Add Byte to Doubleword", "summary": "Adds adjacent bytes to doublewords.", "syntax": "VPHADDBD xmm1, xmm2/m128", "encoding": {"format": "XOP", "hex_opcode": "XOP.128.09.W0 C2 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "XOP", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Horizontally adds adjacent groups of four signed 8-bit bytes from xmm2/m128, accumulating results as 32-bit doublewords in xmm1. Four consecutive bytes are summed to produce one 32-bit result. This XOP extension instruction does not affect EFLAGS and performs signed arithmetic.", "pseudocode": "for i = 0 to 3 {\n xmm1[32*i:32*i+31] ← sign_extend(xmm2/m128[8*(4*i):8*(4*i)+7]) + sign_extend(xmm2/m128[8*(4*i+1):8*(4*i+1)+7]) + sign_extend(xmm2/m128[8*(4*i+2):8*(4*i+2)+7]) + sign_extend(xmm2/m128[8*(4*i+3):8*(4*i+3)+7])\n}", "example": "VPHADDBD xmm1, xmm2/m128"} {"mnemonic": "vphaddbq", "architecture": "x86", "full_name": "Vector Packed Horizontal Add Byte to Quadword", "summary": "Adds adjacent bytes to quadwords.", "syntax": "VPHADDBQ xmm1, xmm2/m128", "encoding": {"format": "XOP", "hex_opcode": "XOP.128.09.W0 C3 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "XOP", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Horizontally adds all eight signed 8-bit bytes from xmm2/m128 (lower half) and (upper half separately), accumulating results as 64-bit quadwords in xmm1. All bytes from each half are summed to produce two 64-bit results. This XOP extension instruction does not affect EFLAGS and performs signed arithmetic.", "pseudocode": "xmm1[63:0] ← sign_extend(xmm2/m128[7:0]) + sign_extend(xmm2/m128[15:8]) + sign_extend(xmm2/m128[23:16]) + sign_extend(xmm2/m128[31:24]) + sign_extend(xmm2/m128[39:32]) + sign_extend(xmm2/m128[47:40]) + sign_extend(xmm2/m128[55:48]) + sign_extend(xmm2/m128[63:56])\nxmm1[127:64] ← sign_extend(xmm2/m128[71:64]) + sign_extend(xmm2/m128[79:72]) + sign_extend(xmm2/m128[87:80]) + sign_extend(xmm2/m128[95:88]) + sign_extend(xmm2/m128[103:96]) + sign_extend(xmm2/m128[111:104]) + sign_extend(xmm2/m128[119:112]) + sign_extend(xmm2/m128[127:120])", "example": "VPHADDBQ xmm1, xmm2/m128"} {"mnemonic": "vphaddwd", "architecture": "x86", "full_name": "Vector Packed Horizontal Add Word to Doubleword", "summary": "Adds adjacent words to doublewords.", "syntax": "VPHADDWD xmm1, xmm2/m128", "encoding": {"format": "XOP", "hex_opcode": "XOP.128.09.W0 C6 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "XOP", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Horizontally adds adjacent pairs of signed 16-bit words from xmm2/m128, accumulating results as 32-bit doublewords in xmm1. Each pair of words produces one 32-bit doubleword result; the operation doubles the data width. This XOP extension instruction does not affect EFLAGS and performs signed arithmetic.", "pseudocode": "for i = 0 to 3 {\n xmm1[32*i:32*i+31] ← sign_extend(xmm2/m128[16*(2*i):16*(2*i)+15]) + sign_extend(xmm2/m128[16*(2*i+1):16*(2*i+1)+15])\n}", "example": "VPHADDWD xmm1, xmm2/m128"} {"mnemonic": "vphaddwq", "architecture": "x86", "full_name": "Vector Packed Horizontal Add Word to Quadword", "summary": "Adds adjacent words to quadwords.", "syntax": "VPHADDWQ xmm1, xmm2/m128", "encoding": {"format": "XOP", "hex_opcode": "XOP.128.09.W0 C7 /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "XOP", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Horizontally adds adjacent groups of four signed 16-bit words from xmm2/m128, accumulating results as 64-bit quadwords in xmm1. Four consecutive words are summed to produce one 64-bit result. This XOP extension instruction does not affect EFLAGS and performs signed arithmetic.", "pseudocode": "for i = 0 to 1 {\n xmm1[64*i:64*i+63] ← sign_extend(xmm2/m128[16*(4*i):16*(4*i)+15]) + sign_extend(xmm2/m128[16*(4*i+1):16*(4*i+1)+15]) + sign_extend(xmm2/m128[16*(4*i+2):16*(4*i+2)+15]) + sign_extend(xmm2/m128[16*(4*i+3):16*(4*i+3)+15])\n}", "example": "VPHADDWQ xmm1, xmm2/m128"} {"mnemonic": "vphadddq", "architecture": "x86", "full_name": "Vector Packed Horizontal Add Doubleword to Quadword", "summary": "Adds adjacent doublewords to quadwords.", "syntax": "VPHADDDQ xmm1, xmm2/m128", "encoding": {"format": "XOP", "hex_opcode": "XOP.128.09.W0 CB /r", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "XOP", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src", "type": "xmm2/m128", "desc": "128-bit XMM SIMD register or Memory operand"}], "description": "Adds pairs of adjacent 32-bit signed integers and stores the 64-bit sums in the destination XMM register. This is a horizontal operation that processes two 32-bit elements from each 64-bit lane, producing one 64-bit result per lane. No flags are affected.", "pseudocode": "for i = 0 to 1:\n result[i*64:(i*64)+63] ← sign_extend_64(src[(i*2)*32:(i*2)*32+31]) +\n sign_extend_64(src[(i*2+1)*32:(i*2+1)*32+31])\ndest ← result", "example": "VPHADDDQ xmm1, xmm2/m128"} {"mnemonic": "vpmacsww", "architecture": "x86", "full_name": "Vector Packed Multiply Accumulate Signed Word", "summary": "Multiply-accumulate signed words.", "syntax": "VPMACSWW xmm1, xmm2, xmm3, xmm4", "encoding": {"format": "XOP", "hex_opcode": "XOP.128.08.W0 95 /r ib", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "XOP", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2", "desc": "128-bit XMM SIMD register"}, {"name": "src2", "type": "xmm3", "desc": "128-bit XMM SIMD register"}, {"name": "src3", "type": "xmm4", "desc": "128-bit XMM SIMD register"}], "description": "Multiplies pairs of signed 16-bit integers, accumulates the 32-bit products, and stores results in the destination XMM register without saturation. This is a 4-operand instruction encoding multiply-accumulate semantics: dest = src1 * src2 + src3. No flags are affected.", "pseudocode": "for i = 0 to 7:\n product ← sign_extend_32(src1[i*16:(i*16)+15]) *\n sign_extend_32(src2[i*16:(i*16)+15])\n result[i*32:(i*32)+31] ← product + sign_extend_32(src3[i*16:(i*16)+15])\ndest ← result", "example": "VPMACSWW xmm1, xmm2, xmm3, xmm4"} {"mnemonic": "vpmacssww", "architecture": "x86", "full_name": "Vector Packed Multiply Accumulate Signed Saturate Word", "summary": "Multiply-accumulate signed words with saturation.", "syntax": "VPMACSSWW xmm1, xmm2, xmm3, xmm4", "encoding": {"format": "XOP", "hex_opcode": "XOP.128.08.W0 85 /r ib", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "XOP", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2", "desc": "128-bit XMM SIMD register"}, {"name": "src2", "type": "xmm3", "desc": "128-bit XMM SIMD register"}, {"name": "src3", "type": "xmm4", "desc": "128-bit XMM SIMD register"}], "description": "Multiplies pairs of signed 16-bit integers, accumulates the 32-bit products with saturation to signed 32-bit range, and stores results in the destination XMM register. This saturating variant clamps results to [-2³¹, 2³¹-1]. No flags are affected.", "pseudocode": "for i = 0 to 7:\n product ← sign_extend_32(src1[i*16:(i*16)+15]) *\n sign_extend_32(src2[i*16:(i*16)+15])\n sum ← product + sign_extend_32(src3[i*16:(i*16)+15])\n result[i*32:(i*32)+31] ← saturate_signed_32(sum)\ndest ← result", "example": "VPMACSSWW xmm1, xmm2, xmm3, xmm4"} {"mnemonic": "vgatherpf0dps", "architecture": "x86", "full_name": "Gather Prefetch Packed Single (L1)", "summary": "Prefetches floats to L1 cache using indices.", "syntax": "VGATHERPF0DPS {k1}, [base+zmm_idx]", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W0 C6 /1 /vsib", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512PF", "operands": [{"name": "dest", "type": "[base+zmm_idx]", "desc": "AVX-512 gather/scatter: base register + ZMM vector index"}], "description": "Prefetches cache lines to L1 for single-precision floats using 32-bit dword indices from a vector register. The instruction performs a gather-style prefetch where each ZMM element acts as an index offset from a base address, but does not load data into registers. The opmask register {k1} controls which prefetch operations execute. No flags are affected.", "pseudocode": "for i = 0 to 15:\n if k1[i] == 1:\n addr ← base + zmm_idx[i*32:(i*32)+31] * scale\n prefetch_L1(addr)\n endif", "example": "VGATHERPF0DPS {k1}, [base+zmm_idx]"} {"mnemonic": "vgatherpf0qps", "architecture": "x86", "full_name": "Gather Prefetch Packed Single (L1, Qword Indices)", "summary": "Prefetches floats to L1 using 64-bit indices.", "syntax": "VGATHERPF0QPS {k1}, [base+zmm_idx]", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W0 C7 /1 /vsib", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512PF", "operands": [{"name": "dest", "type": "[base+zmm_idx]", "desc": "AVX-512 gather/scatter: base register + ZMM vector index"}], "description": "Prefetches cache lines to L1 for single-precision floats using 64-bit qword indices from a vector register. Each element of the ZMM vector is treated as a 64-bit index offset from a base address for gather-prefetch semantics. The opmask {k1} selects which prefetch operations occur. No flags are affected.", "pseudocode": "for i = 0 to 7:\n if k1[i] == 1:\n addr ← base + zmm_idx[i*64:(i*64)+63] * scale\n prefetch_L1(addr)\n endif", "example": "VGATHERPF0QPS {k1}, [base+zmm_idx]"} {"mnemonic": "vgatherpf0dpd", "architecture": "x86", "full_name": "Gather Prefetch Packed Double (L1)", "summary": "Prefetches doubles to L1 cache using indices.", "syntax": "VGATHERPF0DPD {k1}, [base+ymm_idx]", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W1 C6 /1 /vsib", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512PF", "operands": [{"name": "dest", "type": "[base+ymm_idx]", "desc": "AVX gather/scatter: base register + YMM vector index"}], "description": "Prefetches cache lines to L1 for double-precision floats using 32-bit dword indices from a vector register. Each 32-bit index in the YMM register is scaled and added to a base address for gathering-style prefetch operations. The opmask {k1} gates which prefetch operations execute. No flags are affected.", "pseudocode": "for i = 0 to 7:\n if k1[i] == 1:\n addr ← base + ymm_idx[i*32:(i*32)+31] * scale\n prefetch_L1(addr)\n endif", "example": "VGATHERPF0DPD {k1}, [base+ymm_idx]"} {"mnemonic": "vgatherpf0qpd", "architecture": "x86", "full_name": "Gather Prefetch Packed Double (L1, Qword Indices)", "summary": "Prefetches doubles to L1 using 64-bit indices.", "syntax": "VGATHERPF0QPD {k1}, [base+zmm_idx]", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W1 C7 /1 /vsib", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512PF", "operands": [{"name": "dest", "type": "[base+zmm_idx]", "desc": "AVX-512 gather/scatter: base register + ZMM vector index"}], "description": "Prefetches cache lines to L1 for double-precision floats using 64-bit qword indices from a vector register. Each 64-bit element in the ZMM index register is scaled and added to a base address for gather-prefetch semantics. The opmask {k1} controls which prefetch operations are active. No flags are affected.", "pseudocode": "for i = 0 to 7:\n if k1[i] == 1:\n addr ← base + zmm_idx[i*64:(i*64)+63] * scale\n prefetch_L1(addr)\n endif", "example": "VGATHERPF0QPD {k1}, [base+zmm_idx]"} {"mnemonic": "vscatterpf0dps", "architecture": "x86", "full_name": "Scatter Prefetch Packed Single (L1)", "summary": "Prefetches cache lines for scatter write (L1).", "syntax": "VSCATTERPF0DPS {k1}, [base+zmm_idx]", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W0 C6 /5 /vsib", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512PF", "operands": [{"name": "dest", "type": "[base+zmm_idx]", "desc": "AVX-512 gather/scatter: base register + ZMM vector index"}], "description": "Prefetches cache lines to L1 in preparation for scatter write operations on single-precision floats using 32-bit dword indices. Unlike gather prefetch, this operation optimizes cache behavior for subsequent scatter stores. The opmask {k1} selects which prefetch operations occur. No flags are affected.", "pseudocode": "for i = 0 to 15:\n if k1[i] == 1:\n addr ← base + zmm_idx[i*32:(i*32)+31] * scale\n prefetch_L1_for_write(addr)\n endif", "example": "VSCATTERPF0DPS {k1}, [base+zmm_idx]"} {"mnemonic": "vscatterpf0qps", "architecture": "x86", "full_name": "Scatter Prefetch Packed Single (L1, Qword Indices)", "summary": "Prefetches lines for scatter write (L1, 64-bit idx).", "syntax": "VSCATTERPF0QPS {k1}, [base+zmm_idx]", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W0 C7 /5 /vsib", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512PF", "operands": [{"name": "dest", "type": "[base+zmm_idx]", "desc": "AVX-512 gather/scatter: base register + ZMM vector index"}], "description": "Prefetches cache lines for scatter write operations using 64-bit (qword) indices into a ZMM vector, with L1 cache as the target. This is a non-faulting prefetch hint that does not load data or raise exceptions; it only triggers hardware prefetch logic based on the indexed addresses. Execution is masked by the k1 opmask register, and no flags are affected.", "pseudocode": "for (i = 0; i < 8; i++) {\n if (k1[i]) {\n addr = base + ZMM_idx[i];\n prefetch_l1(addr);\n }\n}", "example": "VSCATTERPF0QPS {k1}, [base+zmm_idx]"} {"mnemonic": "vscatterpf0dpd", "architecture": "x86", "full_name": "Scatter Prefetch Packed Double (L1)", "summary": "Prefetches lines for scatter write (L1, Double).", "syntax": "VSCATTERPF0DPD {k1}, [base+ymm_idx]", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W1 C6 /5 /vsib", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512PF", "operands": [{"name": "dest", "type": "[base+ymm_idx]", "desc": "AVX gather/scatter: base register + YMM vector index"}], "description": "Prefetches cache lines for scatter write operations using 32-bit (dword) indices into a YMM vector containing doubles, with L1 cache as the target. This is a non-faulting prefetch hint that does not load data or raise exceptions; masked execution by k1 is supported. No flags are affected.", "pseudocode": "for (i = 0; i < 4; i++) {\n if (k1[i]) {\n addr = base + ZeroExtend64(YMM_idx[i*32:i*32+31]);\n prefetch_l1(addr);\n }\n}", "example": "VSCATTERPF0DPD {k1}, [base+ymm_idx]"} {"mnemonic": "vscatterpf0qpd", "architecture": "x86", "full_name": "Scatter Prefetch Packed Double (L1, Qword Indices)", "summary": "Prefetches lines for scatter write (L1, Double, 64-bit idx).", "syntax": "VSCATTERPF0QPD {k1}, [base+zmm_idx]", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W1 C7 /5 /vsib", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512PF", "operands": [{"name": "dest", "type": "[base+zmm_idx]", "desc": "AVX-512 gather/scatter: base register + ZMM vector index"}], "description": "Prefetches cache lines for scatter write operations using 64-bit (qword) indices into a ZMM vector containing doubles, with L1 cache as the target. This non-faulting prefetch hint is masked by the k1 opmask and does not load data or raise exceptions. No flags are affected.", "pseudocode": "for (i = 0; i < 8; i++) {\n if (k1[i]) {\n addr = base + ZMM_idx[i];\n prefetch_l1(addr);\n }\n}", "example": "VSCATTERPF0QPD {k1}, [base+zmm_idx]"} {"mnemonic": "vp4dpwssd", "architecture": "x86", "full_name": "Dot Product Signed Word to Signed Doubleword (4-iterations)", "summary": "Neural Net 4-way dot product.", "syntax": "VP4DPWSSD zmm1 {k1}, zmm2+3, m128", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.F2.0F38.W0 52 /r", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512-4VNNIW", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2+3", "desc": "ZMM register pair (consecutive even+odd registers, for 4-iteration FMA)"}, {"name": "src2", "type": "m128", "desc": "128-bit memory operand"}], "description": "Performs four iterations of fused multiply-add on signed word operands, accumulating into 32-bit signed doubleword results in zmm1. The instruction reads from a consecutive register pair (zmm2:zmm3) and a 128-bit memory operand, executing four parallel dot products per iteration. Masked by k1; no flags are affected; saturation does not occur (results wrap on overflow).", "pseudocode": "for (j = 0; j < 4; j++) {\n for (i = 0; i < 16; i++) {\n zmm1[i*32:(i*32)+31] += (int32_t)(zmm2[(j*4+i)*16:(j*4+i)*16+15]) * (int32_t)(m128[(j*16+i*2):(j*16+i*2)+15]);\n }\n}", "example": "VP4DPWSSD zmm1, zmm2+3, [rbp-16]"} {"mnemonic": "vp4dpwssds", "architecture": "x86", "full_name": "Dot Product Signed Word to Signed Doubleword Saturate (4-iter)", "summary": "Neural Net 4-way dot product with saturation.", "syntax": "VP4DPWSSDS zmm1 {k1}, zmm2+3, m128", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.F2.0F38.W0 53 /r", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512-4VNNIW", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2+3", "desc": "ZMM register pair (consecutive even+odd registers, for 4-iteration FMA)"}, {"name": "src2", "type": "m128", "desc": "128-bit memory operand"}], "description": "Performs four iterations of fused multiply-add on signed word operands, accumulating into 32-bit signed doubleword results in zmm1 with saturation. The instruction reads from a consecutive register pair (zmm2:zmm3) and a 128-bit memory operand, executing four parallel dot products per iteration. Results saturate to INT32_MIN/INT32_MAX on overflow; masked by k1; no flags are affected.", "pseudocode": "for (j = 0; j < 4; j++) {\n for (i = 0; i < 16; i++) {\n temp = (int64_t)(zmm2[(j*4+i)*16:(j*4+i)*16+15]) * (int64_t)(m128[(j*16+i*2):(j*16+i*2)+15]);\n zmm1[i*32:(i*32)+31] = SaturateSigned32(zmm1[i*32:(i*32)+31] + temp);\n }\n}", "example": "VP4DPWSSDS zmm1, zmm2+3, [rbp-16]"} {"mnemonic": "v4fmaddps", "architecture": "x86", "full_name": "Fused Multiply-Add Packed Single (4-iterations)", "summary": "4-way FMA for Neural Nets (Single).", "syntax": "V4FMADDPS zmm1 {k1}, zmm2+3, m128", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.F2.0F38.W0 9A /r", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512-4FMAPS", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2+3", "desc": "ZMM register pair (consecutive even+odd registers, for 4-iteration FMA)"}, {"name": "src2", "type": "m128", "desc": "128-bit memory operand"}], "description": "Performs four iterations of fused multiply-add on packed single-precision floating-point operands, accumulating results into zmm1. The instruction reads from a consecutive ZMM register pair (zmm2:zmm3) and a 128-bit memory operand, computing four parallel multiply-accumulate chains. Masked by k1; floating-point exceptions (precision, underflow, overflow, denormal) may be signaled; rounding is per MXCSR.", "pseudocode": "for (j = 0; j < 4; j++) {\n for (i = 0; i < 16; i++) {\n float mul = zmm2[(j*4+i)*32:(j*4+i)*32+31] * m128[(j*16+i*4):(j*16+i*4)+31];\n zmm1[i*32:(i*32)+31] = FP_ADD(zmm1[i*32:(i*32)+31], mul);\n }\n}", "example": "V4FMADDPS zmm1, zmm2+3, [rbp-16]"} {"mnemonic": "v4fmaddss", "architecture": "x86", "full_name": "Fused Multiply-Add Scalar Single (4-iterations)", "summary": "4-way FMA for Neural Nets (Scalar).", "syntax": "V4FMADDSS xmm1 {k1}, xmm2+3, m128", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.LLIG.F2.0F38.W0 9B /r", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512-4FMAPS", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2+3", "desc": "XMM register pair (consecutive even+odd registers)"}, {"name": "src2", "type": "m128", "desc": "128-bit memory operand"}], "description": "Performs four iterations of fused multiply-add on scalar single-precision floating-point operands, accumulating results into the low dword of xmm1. The instruction reads from a consecutive XMM register pair (xmm2:xmm3) and a 128-bit memory operand, computing four parallel multiply-accumulate operations into the scalar. Masked by k1; floating-point exceptions may be signaled; rounding is per MXCSR; high 96 bits of xmm1 are cleared.", "pseudocode": "temp = xmm1[0:31];\nfor (j = 0; j < 4; j++) {\n float mul = ((j == 0) ? xmm2[0:31] : xmm3[0:31]) * *(float*)&m128[(j*4):(j*4)+31];\n temp = FP_ADD(temp, mul);\n}\nxmm1[0:31] = temp;\nxmm1[32:127] = 0;", "example": "V4FMADDSS xmm1, xmm2+3, [rbp-16]"} {"mnemonic": "v4fnmaddps", "architecture": "x86", "full_name": "Fused Negative Multiply-Add Packed Single (4-iterations)", "summary": "4-way Negative FMA for Neural Nets (Single).", "syntax": "V4FNMADDPS zmm1 {k1}, zmm2+3, m128", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.F2.0F38.W0 AA /r", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512-4FMAPS", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2+3", "desc": "ZMM register pair (consecutive even+odd registers, for 4-iteration FMA)"}, {"name": "src2", "type": "m128", "desc": "128-bit memory operand"}], "description": "Performs four iterations of fused negative multiply-add on packed single-precision floating-point operands, computing -(zmm2×m128) + zmm1, accumulating results into zmm1. The instruction reads from a consecutive ZMM register pair (zmm2:zmm3) and a 128-bit memory operand, executing four parallel negated multiply-accumulate chains. Masked by k1; floating-point exceptions may be signaled; rounding is per MXCSR.", "pseudocode": "for (j = 0; j < 4; j++) {\n for (i = 0; i < 16; i++) {\n float mul = -(zmm2[(j*4+i)*32:(j*4+i)*32+31] * m128[(j*16+i*4):(j*16+i*4)+31]);\n zmm1[i*32:(i*32)+31] = FP_ADD(zmm1[i*32:(i*32)+31], mul);\n }\n}", "example": "V4FNMADDPS zmm1, zmm2+3, [rbp-16]"} {"mnemonic": "v4fnmaddss", "architecture": "x86", "full_name": "Fused Negative Multiply-Add Scalar Single (4-iterations)", "summary": "4-way Negative FMA for Neural Nets (Scalar).", "syntax": "V4FNMADDSS xmm1 {k1}, xmm2+3, m128", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.LLIG.F2.0F38.W0 AB /r", "visual_parts": [], "binary_pattern": "EVEX | opcode | ModRM", "bit_positions": "+0 | +4 | +5"}, "extension": "AVX-512-4FMAPS", "operands": [{"name": "dest", "type": "xmm1", "desc": "128-bit XMM SIMD register"}, {"name": "src1", "type": "xmm2+3", "desc": "XMM register pair (consecutive even+odd registers)"}, {"name": "src2", "type": "m128", "desc": "128-bit memory operand"}], "description": "Performs four iterations of fused negative multiply-add on scalar single-precision floating-point values, computing -(src1[i] * src2[i]) + dest for four pairs of operands. This instruction is specialized for neural network operations and executes within a single macro-op, improving throughput for repeated FMA patterns. All MXCSR exception flags may be set based on intermediate results; the result is written to dest with optional write-masking via k1.", "pseudocode": "for i in 0 to 3:\n temp ← -(xmm2[i] * m128[i])\n xmm1[i] ← temp + xmm1[i]\n update_MXCSR_flags(temp, xmm1[i])", "example": "V4FNMADDSS xmm1, xmm2+3, [rbp-16]"} {"mnemonic": "vcvtdq2ps", "architecture": "x86", "full_name": "Convert Packed Doubleword to Packed Single", "summary": "Converts four 32-bit integers to floats.", "syntax": "VCVTDQ2PS ymm1, ymm2/m256", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.0F.WIG 5B /r", "visual_parts": [], "binary_pattern": "VEX | 0F | 5B", "bit_positions": "+0 | +3 | +4"}, "extension": "AVX", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src", "type": "ymm2/m256", "desc": "256-bit YMM AVX register or Memory operand"}], "description": "Converts four packed 32-bit signed doubleword integers to four packed single-precision floating-point values. The conversion uses the current MXCSR rounding mode; inexact results may set the PE (precision exception) flag in MXCSR. Available in 128-bit (XMM) and 256-bit (YMM) variants; the 256-bit form converts eight integers. No legacy flags are modified.", "pseudocode": "if VEX.L = 0:\n for i in 0 to 1:\n xmm1[i] ← convert_dword_to_float(xmm2[i])\nelse:\n for i in 0 to 3:\n ymm1[i] ← convert_dword_to_float(ymm2[i])\nupdate_MXCSR_flags()", "example": "VCVTDQ2PS ymm1, ymm2/m256"} {"mnemonic": "vcvtps2dq", "architecture": "x86", "full_name": "Convert Packed Single to Packed Doubleword", "summary": "Converts four floats to 32-bit integers (Rounded).", "syntax": "VCVTPS2DQ ymm1, ymm2/m256", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F.WIG 5B /r", "visual_parts": [], "binary_pattern": "VEX | 66 | 0F | 5B", "bit_positions": "+0 | +3 | +4 | +5"}, "extension": "AVX", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src", "type": "ymm2/m256", "desc": "256-bit YMM AVX register or Memory operand"}], "description": "Converts four packed single-precision floating-point values to four packed 32-bit signed doubleword integers using the current MXCSR rounding mode. Overflowing results saturate to INT32_MIN or INT32_MAX; inexact results may set the PE flag in MXCSR. Available in 128-bit (XMM) and 256-bit (YMM) variants; the 256-bit form converts eight floats. No legacy x86 flags are modified.", "pseudocode": "if VEX.L = 0:\n for i in 0 to 1:\n xmm1[i] ← convert_float_to_dword_rounded(xmm2[i])\nelse:\n for i in 0 to 3:\n ymm1[i] ← convert_float_to_dword_rounded(ymm2[i])\nupdate_MXCSR_flags()", "example": "VCVTPS2DQ ymm1, ymm2/m256"} {"mnemonic": "vcvttps2dq", "architecture": "x86", "full_name": "Convert with Truncation Packed Single to Doubleword", "summary": "Converts four floats to 32-bit integers (Truncated).", "syntax": "VCVTTPS2DQ ymm1, ymm2/m256", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.F3.0F.WIG 5B /r", "visual_parts": [], "binary_pattern": "VEX | F3 | 0F | 5B", "bit_positions": "+0 | +3 | +4 | +5"}, "extension": "AVX", "operands": [{"name": "dest", "type": "ymm1", "desc": "256-bit YMM AVX register"}, {"name": "src", "type": "ymm2/m256", "desc": "256-bit YMM AVX register or Memory operand"}], "description": "Converts four packed single-precision floating-point values to four packed 32-bit signed doubleword integers by truncating toward zero (ignoring MXCSR rounding mode). Overflowing results saturate to INT32_MIN or INT32_MAX; inexact results may set the PE flag in MXCSR. Available in 128-bit (XMM) and 256-bit (YMM) variants; the 256-bit form converts eight floats. No legacy x86 flags are modified.", "pseudocode": "if VEX.L = 0:\n for i in 0 to 1:\n xmm1[i] ← convert_float_to_dword_truncate(xmm2[i])\nelse:\n for i in 0 to 3:\n ymm1[i] ← convert_float_to_dword_truncate(ymm2[i])\nupdate_MXCSR_flags()", "example": "VCVTTPS2DQ ymm1, ymm2/m256"} {"mnemonic": "iret", "architecture": "x86", "full_name": "Interrupt Return", "summary": "Returns from an interrupt, exception, or task handler.", "syntax": "IRET", "encoding": {"format": "Legacy", "hex_opcode": "CF", "visual_parts": [], "binary_pattern": "CF", "bit_positions": "+0"}, "extension": "Base", "operands": [], "description": "Returns from an interrupt handler, exception handler, or nested task by popping the return address and EFLAGS from the stack and resuming execution at the interrupted instruction. In protected mode, also restores CPL and task context; in 64-bit mode (IRETQ), pops a 64-bit return address. This instruction performs memory serialization and may reload segment registers, making it a heavy-weight operation that flushes pending stores.", "pseudocode": "if OperandSize = 16:\n temp_IP ← [SP]; SP ← SP + 2\n temp_CS ← [SP]; SP ← SP + 2\n EFLAGS ← [SP]; SP ← SP + 2\nelse if OperandSize = 32:\n temp_EIP ← [ESP]; ESP ← ESP + 4\n temp_CS ← [ESP]; ESP ← ESP + 4\n EFLAGS ← [ESP]; ESP ← ESP + 4\nelse if OperandSize = 64:\n temp_RIP ← [RSP]; RSP ← RSP + 8\n temp_CS ← [RSP]; RSP ← RSP + 8\n EFLAGS ← [RSP]; RSP ← RSP + 8\nCS ← temp_CS\nIP/EIP/RIP ← temp_IP/EIP/RIP", "example": "IRET"} {"mnemonic": "iretd", "architecture": "x86", "full_name": "Interrupt Return Doubleword", "summary": "Returns from interrupt (32-bit operand size).", "syntax": "IRETD", "encoding": {"format": "Legacy", "hex_opcode": "CF", "visual_parts": [], "binary_pattern": "CF", "bit_positions": "+0"}, "extension": "Base", "operands": [], "description": "Returns from an interrupt handler by explicitly using 32-bit operand size, popping the 32-bit return address (EIP) and EFLAGS from the stack. In protected mode, also restores the code segment (CS) and CPL; in real mode, only pops EIP and EFLAGS. This instruction serializes memory and may trigger privilege-level transitions or task switches, causing pipeline flushing.", "pseudocode": "temp_EIP ← [ESP]; ESP ← ESP + 4\ntemp_CS ← [ESP]; ESP ← ESP + 4\ntemp_EFLAGS ← [ESP]; ESP ← ESP + 4\nCS ← temp_CS\nEIP ← temp_EIP\nEFLAGS ← temp_EFLAGS", "example": "IRETD"} {"mnemonic": "iretq", "architecture": "x86", "full_name": "Interrupt Return Quadword", "summary": "Returns from interrupt (64-bit operand size).", "syntax": "IRETQ", "encoding": {"format": "Legacy", "hex_opcode": "REX.W + CF", "visual_parts": [], "binary_pattern": "CF", "bit_positions": "+0"}, "extension": "Base (64-bit)", "operands": [], "description": "Returns from an interrupt handler using 64-bit operand size, popping the 64-bit return address (RIP), code segment (CS), and RFLAGS from the stack. Exclusively available in 64-bit long mode; enables return to user-mode code and handles CPL transitions. This is a heavy-weight serializing instruction that flushes pending operations and may reload hidden segment state.", "pseudocode": "temp_RIP ← [RSP]; RSP ← RSP + 8\ntemp_CS ← [RSP]; RSP ← RSP + 8\ntemp_RFLAGS ← [RSP]; RSP ← RSP + 8\nCS ← temp_CS\nRIP ← temp_RIP\nRFLAGS ← temp_RFLAGS", "example": "IRETQ"} {"mnemonic": "in", "architecture": "x86", "full_name": "Input from Port (Variable)", "summary": "Reads data from I/O port specified in DX.", "syntax": "IN AL/AX/EAX, DX", "encoding": {"format": "Legacy", "hex_opcode": "ED", "visual_parts": [], "binary_pattern": "EC", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "AL/AX/EAX", "desc": "Implicit accumulator: AL, AX, or EAX (depends on operand size)"}, {"name": "src", "type": "DX", "desc": "Implicit DX register (I/O port address)"}], "description": "Reads 8, 16, or 32 bits from an I/O port whose address is specified in the DX register and stores the result in the AL, AX, or EAX accumulator respectively. The port number in DX is zero-extended to a full I/O address; I/O addressing and privilege checks are performed according to the IOPL field and TSS I/O bitmap. This instruction does not modify any flag bits and may have side effects on the I/O device.", "pseudocode": "port_address ← DX\nif operand_size = 8:\n AL ← I/O_Read(port_address, 1)\nelse if operand_size = 16:\n AX ← I/O_Read(port_address, 2)\nelse if operand_size = 32:\n EAX ← I/O_Read(port_address, 4)", "example": "IN AL/AX/EAX, DX"} {"mnemonic": "out", "architecture": "x86", "full_name": "Output to Port (Variable)", "summary": "Writes data to I/O port specified in DX.", "syntax": "OUT DX, AL/AX/EAX", "encoding": {"format": "Legacy", "hex_opcode": "EF", "visual_parts": [], "binary_pattern": "EE", "bit_positions": "+0"}, "extension": "Base", "operands": [{"name": "dest", "type": "DX", "desc": "Implicit DX register (I/O port address)"}, {"name": "src", "type": "AL/AX/EAX", "desc": "Implicit accumulator: AL, AX, or EAX (depends on operand size)"}], "description": "Writes data from the accumulator (AL, AX, or EAX depending on operand size) to an I/O port whose address is specified in the DX register. This instruction is used for legacy port-based I/O and requires I/O privilege level (IOPL) in protected/long modes. No CPU flags are affected.", "pseudocode": "port_address ← DX; if (operand_size == 8) { I/O[port_address] ← AL; } else if (operand_size == 16) { I/O[port_address] ← AX; } else if (operand_size == 32) { I/O[port_address] ← EAX; }", "example": "OUT DX, AL/AX/EAX"} {"mnemonic": "vpopcntq", "architecture": "x86", "full_name": "Packed Population Count Quadword", "summary": "Counts set bits in each quadword element.", "syntax": "VPOPCNTQ zmm1 {k1}, zmm2/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W1 55 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 55", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512-VPOPCNTDQ", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src", "type": "zmm2/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Counts the number of set bits (population count) in each 64-bit quadword element of the source operand and stores the result in the destination ZMM register. This is an AVX-512-VPOPCNTDQ instruction that operates on 512-bit vectors (8 quadwords). Masking via the opmask register k1 can selectively update or zero destination elements; no CPU arithmetic flags are modified.", "pseudocode": "for i ← 0 to 7 do { if (k1[i] or not_masked) { dst.qword[i] ← popcount(src.qword[i]); } else { dst.qword[i] ← 0; } }", "example": "VPOPCNTQ zmm1, zmm2/m512"} {"mnemonic": "vpopcntw", "architecture": "x86", "full_name": "Packed Population Count Word", "summary": "Counts set bits in each word element.", "syntax": "VPOPCNTW zmm1 {k1}, zmm2/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W1 54 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 54", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512-BITALG", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src", "type": "zmm2/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Counts the number of set bits (population count) in each 16-bit word element of the source operand and stores the result in the destination ZMM register. This is an AVX-512-BITALG instruction that operates on 512-bit vectors (32 words). Masking via opmask register k1 allows selective element updates; no CPU arithmetic flags are modified.", "pseudocode": "for i ← 0 to 31 do { if (k1[i] or not_masked) { dst.word[i] ← popcount(src.word[i]); } else { dst.word[i] ← 0; } }", "example": "VPOPCNTW zmm1, zmm2/m512"} {"mnemonic": "vpcompressw", "architecture": "x86", "full_name": "Store Sparse Packed Word Integer Values", "summary": "Compresses active words from ZMM to memory.", "syntax": "VPCOMPRESSW m512 {k1}, zmm1", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W1 63 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 63", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512-VBMI2", "operands": [{"name": "dest", "type": "m512", "desc": "512-bit memory operand"}, {"name": "src", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}], "description": "Compresses active 16-bit word elements from the source ZMM register into contiguous locations in memory, guided by the opmask register k1. Only elements where the corresponding mask bit is set are written to memory in order; unmasked elements are skipped. This is an AVX-512-VBMI2 instruction; no CPU flags are affected.", "pseudocode": "mem_offset ← 0; for i ← 0 to 31 do { if (k1[i]) { [dest + mem_offset] ← src.word[i]; mem_offset ← mem_offset + 2; } }", "example": "VPCOMPRESSW [rbp-64], zmm1"} {"mnemonic": "vpexpandw", "architecture": "x86", "full_name": "Load Sparse Packed Word Integer Values", "summary": "Expands words from memory into sparse locations in ZMM.", "syntax": "VPEXPANDW zmm1 {k1}, m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W1 62 /r", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 62", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512-VBMI2", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src", "type": "m512", "desc": "512-bit memory operand"}], "description": "Expands 16-bit word elements from memory into sparse positions within the destination ZMM register, guided by the opmask register k1. Words are read sequentially from memory and written to destination positions where the corresponding mask bit is set. This is an AVX-512-VBMI2 instruction; no CPU flags are affected.", "pseudocode": "mem_offset ← 0; for i ← 0 to 31 do { if (k1[i]) { dst.word[i] ← [src + mem_offset]; mem_offset ← mem_offset + 2; } else { dst.word[i] ← 0; } }", "example": "VPEXPANDW zmm1, [rbp-64]"} {"mnemonic": "vpshldw", "architecture": "x86", "full_name": "Packed Shift Left Word Concatenate", "summary": "Funnel shift left of words.", "syntax": "VPSHLDW zmm1 {k1}, zmm2, zmm3/m512, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F3A.W1 70 /r /ib", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 3A | 70", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512-VBMI2", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}, {"name": "src3", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Performs a funnel (concatenate and shift) left operation on pairs of 16-bit word elements: the result is (src1 || src2) shifted left by the count specified in imm8 modulo 16. This is an AVX-512-VBMI2 instruction operating on 32 word elements per 512-bit vector. Masking via k1 allows selective updates; no CPU arithmetic flags are modified.", "pseudocode": "for i ← 0 to 31 do { if (k1[i] or not_masked) { combined ← (src1.word[i] << 16) | src2.word[i]; shift_count ← imm8 & 0xF; dst.word[i] ← (combined >> (16 - shift_count)) & 0xFFFF; } }", "example": "VPSHLDW zmm1, zmm2, zmm3/m512, 3"} {"mnemonic": "vpshldq", "architecture": "x86", "full_name": "Packed Shift Left Quadword Concatenate", "summary": "Funnel shift left of quadwords.", "syntax": "VPSHLDQ zmm1 {k1}, zmm2, zmm3/m512, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F3A.W1 71 /r /ib", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 3A | 71", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512-VBMI2", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}, {"name": "src3", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Performs a funnel (concatenate and shift) left operation on pairs of 64-bit quadword elements: the result is (src1 || src2) shifted left by the count specified in imm8 modulo 64. This is an AVX-512-VBMI2 instruction operating on 8 quadword elements per 512-bit vector. Masking via k1 allows selective updates; no CPU arithmetic flags are modified.", "pseudocode": "for i ← 0 to 7 do { if (k1[i] or not_masked) { combined_hi ← src1.qword[i]; combined_lo ← src2.qword[i]; shift_count ← imm8 & 0x3F; if (shift_count == 0) { dst.qword[i] ← combined_lo; } else if (shift_count < 64) { dst.qword[i] ← (combined_lo >> (64 - shift_count)) | (combined_hi << shift_count); } else { dst.qword[i] ← combined_hi << (shift_count - 64); } } }", "example": "VPSHLDQ zmm1, zmm2, zmm3/m512, 3"} {"mnemonic": "vpshrdw", "architecture": "x86", "full_name": "Packed Shift Right Word Concatenate", "summary": "Funnel shift right of words.", "syntax": "VPSHRDW zmm1 {k1}, zmm2, zmm3/m512, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F3A.W1 72 /r /ib", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 3A | 72", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512-VBMI2", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}, {"name": "src3", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Performs a funnel (concatenate and shift) right operation on pairs of 16-bit word elements: the result is (src1 || src2) shifted right by the count specified in imm8 modulo 16. This is an AVX-512-VBMI2 instruction operating on 32 word elements per 512-bit vector. Masking via k1 allows selective updates; no CPU arithmetic flags are modified.", "pseudocode": "for i ← 0 to 31 do { if (k1[i] or not_masked) { combined ← (src1.word[i] << 16) | src2.word[i]; shift_count ← imm8 & 0xF; dst.word[i] ← (combined >> shift_count) & 0xFFFF; } }", "example": "VPSHRDW zmm1, zmm2, zmm3/m512, 3"} {"mnemonic": "vpshrdq", "architecture": "x86", "full_name": "Packed Shift Right Quadword Concatenate", "summary": "Funnel shift right of quadwords.", "syntax": "VPSHRDQ zmm1 {k1}, zmm2, zmm3/m512, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F3A.W1 73 /r /ib", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 3A | 73", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512-VBMI2", "operands": [{"name": "dest", "type": "zmm1", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}, {"name": "src3", "type": "imm8", "desc": "8-bit signed immediate"}], "description": "Performs a funnel shift right operation on packed 64-bit quadwords across two source operands. Each 64-bit element in zmm2 is concatenated with the corresponding element in zmm3/m512, and the result is shifted right by the amount specified in imm8 (modulo 64), with the lower bits written to zmm1. No flags are affected by this instruction.", "pseudocode": "for i = 0 to 7 {\n concatenated = (zmm3[i+1] << 64) | zmm2[i];\n zmm1[i] = (concatenated >> (imm8 % 64)) & 0xFFFFFFFFFFFFFFFF;\n}", "example": "VPSHRDQ zmm1, zmm2, zmm3/m512, 3"} {"mnemonic": "vp2intersectq", "architecture": "x86", "full_name": "Compute Intersection Pair Quadwords", "summary": "Computes intersection of two ZMM registers into mask pair.", "syntax": "VP2INTERSECTQ k1+1, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.NDS.512.F2.0F38.W1 68 /r", "visual_parts": [], "binary_pattern": "EVEX | F2 | 0F | 38 | 68", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "extension": "AVX-512-VP2INTERSECT", "operands": [{"name": "dest", "type": "k1+1", "desc": "Opmask register pair (k1 and the next adjacent register)"}, {"name": "src1", "type": "zmm2", "desc": "512-bit ZMM AVX-512 register"}, {"name": "src2", "type": "zmm3/m512", "desc": "512-bit ZMM AVX-512 register or Memory operand"}], "description": "Computes the intersection of two sets of 64-bit quadwords, producing a pair of opmask registers (k1 and k1+1) indicating which elements from the first operand have matches in the second operand. The instruction uses special hardware logic to compare quadwords and set mask bits accordingly. No arithmetic flags are affected.", "pseudocode": "for i = 0 to 7 {\n found_in_src2 = 0;\n for j = 0 to 7 {\n if (zmm2[i] == zmm3[j]) {\n found_in_src2 = 1;\n break;\n }\n }\n if (found_in_src2) k1[i] = 1; else k1[i] = 0;\n // k1+1 contains further comparison results or inverted results\n}", "example": "VP2INTERSECTQ k1+1, zmm2, zmm3/m512"} {"mnemonic": "tdpbuud", "architecture": "x86", "full_name": "Tile Dot Product Byte Unsigned Unsigned Doubleword", "summary": "Matrix multiply (Unsigned * Unsigned) accumulating to Int32.", "syntax": "TDPBUUD tmm1, tmm2, tmm3", "encoding": {"format": "VEX", "hex_opcode": "VEX.128.NP.0F38.W0 5E 11:rrr:bbb", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AMX-INT8", "operands": [{"name": "dest", "type": "tmm1", "desc": "AMX tile register"}, {"name": "src1", "type": "tmm2", "desc": "AMX tile register"}, {"name": "src2", "type": "tmm3", "desc": "AMX tile register"}], "description": "Performs a tile-based dot product operation on 8×32 unsigned byte matrix tmm2 and 32×8 unsigned byte matrix tmm3, accumulating the 32-bit unsigned results into 8×8 doubleword tile tmm1. The instruction uses specialized AMX hardware for fast matrix multiplication without affecting EFLAGS.", "pseudocode": "for i = 0 to 7 {\n for j = 0 to 7 {\n product = 0;\n for k = 0 to 31 {\n product += (unsigned)tmm2[i][k] * (unsigned)tmm3[k][j];\n }\n tmm1[i][j] += product;\n }\n}", "example": "TDPBUUD tmm1, tmm2, tmm3"} {"mnemonic": "tdpbusd", "architecture": "x86", "full_name": "Tile Dot Product Byte Unsigned Signed Doubleword", "summary": "Matrix multiply (Unsigned * Signed) accumulating to Int32.", "syntax": "TDPBUSD tmm1, tmm2, tmm3", "encoding": {"format": "VEX", "hex_opcode": "VEX.128.66.0F38.W0 5E 11:rrr:bbb", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AMX-INT8", "operands": [{"name": "dest", "type": "tmm1", "desc": "AMX tile register"}, {"name": "src1", "type": "tmm2", "desc": "AMX tile register"}, {"name": "src2", "type": "tmm3", "desc": "AMX tile register"}], "description": "Performs a tile-based dot product operation multiplying 8×32 unsigned byte matrix tmm2 by 32×8 signed byte matrix tmm3, accumulating the 32-bit signed results into 8×8 doubleword tile tmm1. This is the unsigned-by-signed variant of tile dot product, useful for mixed-precision neural network operations without affecting EFLAGS.", "pseudocode": "for i = 0 to 7 {\n for j = 0 to 7 {\n product = 0;\n for k = 0 to 31 {\n product += (unsigned)tmm2[i][k] * (signed)tmm3[k][j];\n }\n tmm1[i][j] += product;\n }\n}", "example": "TDPBUSD tmm1, tmm2, tmm3"} {"mnemonic": "tileloaddt1", "architecture": "x86", "full_name": "Load Tile Data (T1 Hint)", "summary": "Loads data into an AMX tile register with T1 hint.", "syntax": "TILELOADDT1 tmm1, m", "encoding": {"format": "VEX", "hex_opcode": "VEX.128.66.0F38.W0 4B !(11):rrr:100", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "extension": "AMX-TILE", "operands": [{"name": "dest", "type": "tmm1", "desc": "AMX tile register"}, {"name": "src", "type": "m", "desc": "Memory operand"}], "description": "Loads tile data from memory into an AMX tile register with a T1 (temporal) cache hint, indicating the data is likely to be used soon. The memory operand is typically addressed via a base register and optional displacement, and the tile dimensions are pre-configured via TILECONFIG. No flags are affected.", "pseudocode": "tmm1 = load_from_memory_with_t1_hint(m);\n// Tile shape determined by previously configured palette and TILECFG register", "example": "TILELOADDT1 tmm1, [rbp-8]"} {"mnemonic": "aesdecwide128kl", "architecture": "x86", "full_name": "AES Decrypt Wide 128-bit Key Locker", "summary": "Decrypts 8 blocks using 128-bit Key Locker handle.", "syntax": "AESDECWIDE128KL m128", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F 38 D8 !(11):001:bbb", "visual_parts": [], "binary_pattern": "F3 | 0F | 38 | D8", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "KEYLOCKER_WIDE", "operands": [{"name": "dest", "type": "m128", "desc": "128-bit memory operand"}], "description": "Decrypts 8 AES blocks (128 bits each) in parallel using a 128-bit Key Locker encrypted key handle stored at the memory operand. The ciphertext blocks are implicit in XMM0-XMM7 (input) and plaintext results are written back to XMM0-XMM7 (output). The ZF flag is set to 0 on success or 1 if the key handle is invalid.", "pseudocode": "key_handle = load_from_memory_128bit(m128);\nif (key_handle_invalid(key_handle)) {\n ZF = 1;\n} else {\n for i = 0 to 7 {\n XMM[i] = AES_decrypt_block(XMM[i], key_handle);\n }\n ZF = 0;\n}", "example": "AESDECWIDE128KL [rbp-16]"} {"mnemonic": "aesdecwide256kl", "architecture": "x86", "full_name": "AES Decrypt Wide 256-bit Key Locker", "summary": "Decrypts 8 blocks using 256-bit Key Locker handle.", "syntax": "AESDECWIDE256KL m128", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F 38 D8 !(11):011:bbb", "visual_parts": [], "binary_pattern": "F3 | 0F | 38 | D8", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "KEYLOCKER_WIDE", "operands": [{"name": "dest", "type": "m128", "desc": "128-bit memory operand"}], "description": "Decrypts 8 AES blocks (128 bits each) in parallel using a 256-bit Key Locker encrypted key handle stored at the memory operand. The ciphertext blocks are implicit in XMM0-XMM7 (input) and plaintext results are written back to XMM0-XMM7 (output). The ZF flag is set to 0 on success or 1 if the key handle is invalid.", "pseudocode": "key_handle = load_from_memory_128bit(m128);\nif (key_handle_invalid(key_handle)) {\n ZF = 1;\n} else {\n for i = 0 to 7 {\n XMM[i] = AES_decrypt_block_256bit_key(XMM[i], key_handle);\n }\n ZF = 0;\n}", "example": "AESDECWIDE256KL [rbp-16]"} {"mnemonic": "encodekey256", "architecture": "x86", "full_name": "Encode 256-bit Key", "summary": "Wraps a 256-bit AES key into a handle.", "syntax": "ENCODEKEY256 r32, r32", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F 38 FB", "visual_parts": [], "binary_pattern": "F3 | 0F | 38 | FB", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "KEYLOCKER", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}], "description": "Wraps a 256-bit AES key (provided in XMM registers via the second operand's implicit XMM context) into an encrypted handle stored in memory. This instruction is part of Intel Key Locker and requires the KEYLOCKER CPU feature. It performs cryptographic key material encoding that protects against certain side-channel attacks. No flags are modified.", "pseudocode": "handle ← AES_KW_Wrap_256bit(key_material)\ndest ← handle\n// XMM registers implicitly contain the 256-bit key to be encoded", "example": "ENCODEKEY256 eax, eax"} {"mnemonic": "aesenc256kl", "architecture": "x86", "full_name": "AES Encrypt 256-bit Key Locker", "summary": "Encrypts data using 256-bit Key Locker handle.", "syntax": "AESENC256KL m128, xmm", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F 38 DE !(11):rrr:bbb", "visual_parts": [], "binary_pattern": "F3 | 0F | 38 | DC", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "KEYLOCKER", "operands": [{"name": "dest", "type": "m128", "desc": "128-bit memory operand"}, {"name": "src", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}], "description": "Encrypts a 128-bit plaintext block (from XMM register) using a 256-bit Key Locker handle (from memory), storing the ciphertext back into the XMM register. This requires KEYLOCKER support and performs AES-256 encryption with hardware-protected key material. Sets ZF to indicate success/failure of the operation; other flags undefined.", "pseudocode": "handle ← [dest]\nciphertext ← AES_Encrypt_256(plaintext=src, key_handle=handle)\nsrc ← ciphertext\nZF ← (operation_successful ? 0 : 1)", "example": "AESENC256KL [rbp-16], xmm0"} {"mnemonic": "aesdec256kl", "architecture": "x86", "full_name": "AES Decrypt 256-bit Key Locker", "summary": "Decrypts data using 256-bit Key Locker handle.", "syntax": "AESDEC256KL m128, xmm", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F 38 DF !(11):rrr:bbb", "visual_parts": [], "binary_pattern": "F3 | 0F | 38 | DD", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "KEYLOCKER", "operands": [{"name": "dest", "type": "m128", "desc": "128-bit memory operand"}, {"name": "src", "type": "xmm", "desc": "128-bit SSE/AVX register (XMM)"}], "description": "Decrypts a 128-bit ciphertext block (from XMM register) using a 256-bit Key Locker handle (from memory), storing the plaintext back into the XMM register. This requires KEYLOCKER support and performs AES-256 decryption with hardware-protected key material. Sets ZF to indicate success/failure of the operation; other flags undefined.", "pseudocode": "handle ← [dest]\nplaintext ← AES_Decrypt_256(ciphertext=src, key_handle=handle)\nsrc ← plaintext\nZF ← (operation_successful ? 0 : 1)", "example": "AESDEC256KL [rbp-16], xmm0"} {"mnemonic": "enqcmds", "architecture": "x86", "full_name": "Enqueue Command Supervisor", "summary": "Writes a command to a device (Supervisor mode).", "syntax": "ENQCMDS r32, m512", "encoding": {"format": "Legacy", "hex_opcode": "F3 0F 38 F8", "visual_parts": [], "binary_pattern": "F3 | 0F | 38 | F8", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "ENQCMD", "operands": [{"name": "dest", "type": "r32", "desc": "32-bit general-purpose register (e.g. EAX)"}, {"name": "src", "type": "m512", "desc": "512-bit memory operand"}], "description": "Enqueues a 512-bit command descriptor to a device queue in supervisor mode only (requires CPL=0). The command is read from memory and written to a device via a memory-mapped queue; requires ENQCMD CPU feature. Sets ZF and CF flags: ZF=1 if queue is full, CF=1 if access denied or invalid descriptor format. Other flags undefined.", "pseudocode": "if (CPL != 0) { fault ← true; return; }\ndescriptor ← [src]\nstatus ← enqueue_device_command(descriptor)\ndest ← status\nZF ← (queue_full ? 1 : 0)\nCF ← (access_denied_or_invalid ? 1 : 0)", "example": "ENQCMDS eax, [rbp-64]"} {"mnemonic": "xsusldtrk", "architecture": "x86", "full_name": "Suspend Tracking Load Addresses", "summary": "Suspends tracking of load addresses in a TSX suspend-tracking region (resumed with XRESLDTRK).", "syntax": "XSUSLDTRK", "encoding": {"format": "Legacy", "hex_opcode": "F2 0F 01 E8", "visual_parts": [], "binary_pattern": "F2 | 0F | 01 | E8", "bit_positions": "+0 | +1 | +2 | +3"}, "extension": "TSXLDTRK", "operands": [], "description": "Suspends or resumes tracking of load operations within a TSX (Transactional Synchronization Extensions) transaction. Requires TSX support and TSX_LDTRK feature flag. Does not modify any flags. This instruction helps fine-tune transaction conflict detection by toggling whether loads are monitored for abort conditions.", "pseudocode": "if (in_transaction) {\n TSX_load_tracking_enabled ← !TSX_load_tracking_enabled\n}", "example": "XSUSLDTRK"} {"mnemonic": "syscall", "architecture": "x86", "full_name": "System Call", "summary": "Fast call to privilege level 0 system procedures.", "syntax": "SYSCALL", "encoding": {"format": "System", "hex_opcode": "0F 05", "length": "2", "visual_parts": [], "binary_pattern": "0F | 05", "bit_positions": "+0 | +1"}, "operands": [], "extension": "System (64-bit)", "description": "Fast low-latency call to a privilege level 0 system procedure (64-bit mode only). Loads the system call target address from IA32_LSTAR MSR, saves the return address (RIP+2) into RCX, and sets RFLAGS according to IA32_FMASK MSR. Does not set any condition flags; acts as a serializing operation. Requires 64-bit mode and supervisor software setup.", "pseudocode": "RCX ← RIP + 2\nRIP ← IA32_LSTAR\nRFLAGS ← RFLAGS & ~IA32_FMASK\n// Transition to CPL 0 with user code segment", "example": "SYSCALL"} {"mnemonic": "sysret", "architecture": "x86", "full_name": "Return from System Call", "summary": "Fast return to privilege level 3 user code.", "syntax": "SYSRET", "encoding": {"format": "System", "hex_opcode": "0F 07", "length": "2", "visual_parts": [], "binary_pattern": "0F | 07", "bit_positions": "+0 | +1"}, "operands": [], "extension": "System (64-bit)", "description": "Fast return from a system call invoked via SYSCALL, transitioning from CPL 0 back to CPL 3. Restores the user RIP from RCX and re-enables interrupts/flags as appropriate. Requires 64-bit mode and can only be executed at CPL 0. Does not modify condition flags; serializes instruction stream.", "pseudocode": "RIP ← RCX\n// Transition to CPL 3 with user code segment\n// Restore RFLAGS state (interrupts re-enabled per IA32_FMASK)", "example": "SYSRET"} {"mnemonic": "sal", "architecture": "x86", "full_name": "Shift Arithmetic Left", "summary": "Shifts bits left (Alias for SHL).", "syntax": "SAL r/m, imm8", "encoding": {"format": "Legacy", "hex_opcode": "C1 /4", "length": "3+", "visual_parts": [], "binary_pattern": "C1 | ModRM", "bit_positions": "+0 | +1"}, "operands": [{"name": "dest", "desc": "Reg/Mem"}, {"name": "count", "desc": "Immediate"}], "extension": "Base", "description": "Shifts the bits of the destination operand left by the count specified (immediate or ECX). Each shifted-out bit is moved into CF; vacated bits are filled with zeros. Sets OF if the sign bit changed after the shift, CF from the last shifted bit, ZF and SF based on the result, and PF is undefined. Available in 8/16/32/64-bit variants across all modes.", "pseudocode": "if (count > 0) {\n temp_cf ← dest >> (operand_width - count)\n dest ← (dest << count) & ((1 << operand_width) - 1)\n CF ← temp_cf\n ZF ← (dest == 0 ? 1 : 0)\n SF ← (dest >> (operand_width - 1)) & 1\n if (count == 1) { OF ← (SF != CF ? 1 : 0) }\n else { OF ← undefined }\n PF ← undefined\n}", "example": "SAL rbx, 3"} {"mnemonic": "cmpsw", "architecture": "x86", "full_name": "Compare String Word", "summary": "Compares word at [ESI] with [EDI].", "syntax": "CMPSW", "encoding": {"format": "Legacy", "hex_opcode": "A7", "length": "2", "visual_parts": [], "binary_pattern": "66 | A7", "bit_positions": "+0 | +1"}, "operands": [{"name": "DS:[ESI]", "type": "m16", "desc": "First memory operand at DS:ESI (source index register, typically data segment)."}, {"name": "ES:[EDI]", "type": "m16", "desc": "Second memory operand at ES:EDI (destination index register, typically extra segment)."}], "extension": "Base", "description": "Compares a word (16-bit) at memory address [ESI] with a word at [EDI] by performing an implicit subtraction ([ESI] - [EDI]), updates the EFLAGS register with the result, and increments or decrements both ESI and EDI by 2 depending on the direction flag (DF). The comparison affects OF, SF, ZF, AF, PF, and CF flags but does not modify either operand. Often used with repeat prefixes (REP, REPE, REPNE) for string comparison operations.", "pseudocode": "temp ← [ESI] - [EDI];\nOF ← overflow of subtraction;\nSF ← temp[15];\nZF ← (temp == 0);\nAF ← auxiliary carry of subtraction;\nPF ← parity of temp;\nCF ← borrow;\nif (DF == 0) {\n ESI ← ESI + 2;\n EDI ← EDI + 2;\n} else {\n ESI ← ESI - 2;\n EDI ← EDI - 2;\n}", "example": "CMPSW"} {"mnemonic": "cmpsd", "architecture": "x86", "full_name": "Compare String Doubleword", "summary": "Compares doubleword at [ESI] with [EDI].", "syntax": "CMPSD", "encoding": {"format": "Legacy", "hex_opcode": "A7", "length": "1", "visual_parts": [], "binary_pattern": "A7", "bit_positions": "+0"}, "operands": [{"name": "DS:[ESI]", "type": "m32", "desc": "First memory operand at DS:ESI (source index register)."}, {"name": "ES:[EDI]", "type": "m32", "desc": "Second memory operand at ES:EDI (destination index register)."}], "extension": "Base", "description": "Compares a doubleword (32-bit) at memory address [ESI] with a doubleword at [EDI] by performing an implicit subtraction ([ESI] - [EDI]), updates the EFLAGS register with the result, and increments or decrements both ESI and EDI by 4 depending on the direction flag (DF). The comparison affects OF, SF, ZF, AF, PF, and CF flags but does not modify either operand. Commonly used in 32-bit protected mode or with repeat prefixes for string operations.", "pseudocode": "temp ← [ESI] - [EDI];\nOF ← overflow of subtraction;\nSF ← temp[31];\nZF ← (temp == 0);\nAF ← auxiliary carry of subtraction;\nPF ← parity of temp;\nCF ← borrow;\nif (DF == 0) {\n ESI ← ESI + 4;\n EDI ← EDI + 4;\n} else {\n ESI ← ESI - 4;\n EDI ← EDI - 4;\n}", "example": "CMPSD"} {"mnemonic": "cmpsq", "architecture": "x86", "full_name": "Compare String Quadword", "summary": "Compares quadword at [RSI] with [RDI].", "syntax": "CMPSQ", "encoding": {"format": "Legacy", "hex_opcode": "REX.W + A7", "length": "2", "visual_parts": [], "binary_pattern": "48 | A7", "bit_positions": "+0 | +1"}, "operands": [{"name": "DS:[RSI]", "type": "m64", "desc": "First memory operand at DS:RSI (source index register in 64-bit mode)."}, {"name": "DS:[RDI]", "type": "m64", "desc": "Second memory operand at DS:RDI (destination index register in 64-bit mode)."}], "extension": "Base (64-bit)", "description": "Compares a quadword (64-bit) at memory address [RSI] with a quadword at [RDI] by performing an implicit subtraction ([RSI] - [RDI]), updates the EFLAGS register with the result, and increments or decrements both RSI and RDI by 8 depending on the direction flag (DF). The comparison affects OF, SF, ZF, AF, PF, and CF flags but does not modify either operand. Available only in 64-bit mode; operand size defaults to 64 bits.", "pseudocode": "temp ← [RSI] - [RDI];\nOF ← overflow of subtraction;\nSF ← temp[63];\nZF ← (temp == 0);\nAF ← auxiliary carry of subtraction;\nPF ← parity of temp;\nCF ← borrow;\nif (DF == 0) {\n RSI ← RSI + 8;\n RDI ← RDI + 8;\n} else {\n RSI ← RSI - 8;\n RDI ← RDI - 8;\n}", "example": "CMPSQ"} {"mnemonic": "scasw", "architecture": "x86", "full_name": "Scan String Word", "summary": "Compares AX with memory at [EDI].", "syntax": "SCASW", "encoding": {"format": "Legacy", "hex_opcode": "AF", "length": "2", "visual_parts": [], "binary_pattern": "66 | AF", "bit_positions": "+0 | +1"}, "operands": [{"name": "AX", "type": "r16", "desc": "Implicit source register (accumulator) containing the value to be compared."}, {"name": "ES:[EDI]", "type": "m16", "desc": "Memory operand at ES:EDI (destination index register) to be compared against AX."}], "extension": "Base", "description": "Compares the word in AX with a word at memory address [EDI] by performing an implicit subtraction (AX - [EDI]), updates the EFLAGS register with the result, and increments or decrements EDI by 2 depending on the direction flag (DF). The comparison affects OF, SF, ZF, AF, PF, and CF flags but does not modify either operand. Often used with repeat prefixes (REPE, REPNE) for scanning strings in memory.", "pseudocode": "temp ← AX - [EDI];\nOF ← overflow of subtraction;\nSF ← temp[15];\nZF ← (temp == 0);\nAF ← auxiliary carry of subtraction;\nPF ← parity of temp;\nCF ← borrow;\nif (DF == 0) {\n EDI ← EDI + 2;\n} else {\n EDI ← EDI - 2;\n}", "example": "SCASW"} {"mnemonic": "scasd", "architecture": "x86", "full_name": "Scan String Doubleword", "summary": "Compares EAX with memory at [EDI].", "syntax": "SCASD", "encoding": {"format": "Legacy", "hex_opcode": "AF", "length": "1", "visual_parts": [], "binary_pattern": "AF", "bit_positions": "+0"}, "operands": [{"name": "EAX", "type": "r32", "desc": "Implicit source register (accumulator) containing the value to be compared."}, {"name": "ES:[EDI]", "type": "m32", "desc": "Memory operand at ES:EDI (destination index register) to be compared against EAX."}], "extension": "Base", "description": "Compares the doubleword in EAX with a doubleword at memory address [EDI] by performing an implicit subtraction (EAX - [EDI]), updates the EFLAGS register with the result, and increments or decrements EDI by 4 depending on the direction flag (DF). The comparison affects OF, SF, ZF, AF, PF, and CF flags but does not modify either operand. Commonly used in 32-bit protected mode with repeat prefixes for memory scanning.", "pseudocode": "temp ← EAX - [EDI];\nOF ← overflow of subtraction;\nSF ← temp[31];\nZF ← (temp == 0);\nAF ← auxiliary carry of subtraction;\nPF ← parity of temp;\nCF ← borrow;\nif (DF == 0) {\n EDI ← EDI + 4;\n} else {\n EDI ← EDI - 4;\n}", "example": "SCASD"} {"mnemonic": "scasq", "architecture": "x86", "full_name": "Scan String Quadword", "summary": "Compares RAX with memory at [RDI].", "syntax": "SCASQ", "encoding": {"format": "Legacy", "hex_opcode": "REX.W + AF", "length": "2", "visual_parts": [], "binary_pattern": "48 | AF", "bit_positions": "+0 | +1"}, "operands": [{"name": "RAX", "type": "r64", "desc": "Implicit source register (accumulator in 64-bit mode) containing the value to be compared."}, {"name": "DS:[RDI]", "type": "m64", "desc": "Memory operand at DS:RDI (destination index register in 64-bit mode) to be compared against RAX."}], "extension": "Base (64-bit)", "description": "Compares the quadword in RAX with a quadword at memory address [RDI] by performing an implicit subtraction (RAX - [RDI]), updates the EFLAGS register with the result, and increments or decrements RDI by 8 depending on the direction flag (DF). The comparison affects OF, SF, ZF, AF, PF, and CF flags but does not modify either operand. Available only in 64-bit mode; commonly used with repeat prefixes for scanning 64-bit values in memory.", "pseudocode": "temp ← RAX - [RDI];\nOF ← overflow of subtraction;\nSF ← temp[63];\nZF ← (temp == 0);\nAF ← auxiliary carry of subtraction;\nPF ← parity of temp;\nCF ← borrow;\nif (DF == 0) {\n RDI ← RDI + 8;\n} else {\n RDI ← RDI - 8;\n}", "example": "SCASQ"} {"mnemonic": "lodsw", "architecture": "x86", "full_name": "Load String Word", "summary": "Loads word from [ESI] into AX.", "syntax": "LODSW", "encoding": {"format": "Legacy", "hex_opcode": "AD", "length": "2", "visual_parts": [], "binary_pattern": "66 | AC", "bit_positions": "+0 | +1"}, "operands": [{"name": "AX", "type": "r16", "desc": "Implicit destination register (accumulator) where the loaded word is stored."}, {"name": "DS:[ESI]", "type": "m16", "desc": "Memory operand at DS:ESI (source index register) from which the word is loaded."}], "extension": "Base", "description": "Loads a word (16-bit) from memory at address [ESI] into the AX register, then increments or decrements ESI by 2 depending on the direction flag (DF). No flags are affected by this instruction. Often used with repeat prefix (REP) to load successive words from memory into AX, though the repeat would only load the final value.", "pseudocode": "AX ← [ESI];\nif (DF == 0) {\n ESI ← ESI + 2;\n} else {\n ESI ← ESI - 2;\n}", "example": "LODSW"} {"mnemonic": "lodsd", "architecture": "x86", "full_name": "Load String Doubleword", "summary": "Loads doubleword from [ESI] into EAX.", "syntax": "LODSD", "encoding": {"format": "Legacy", "hex_opcode": "AD", "length": "1", "visual_parts": [], "binary_pattern": "AC", "bit_positions": "+0"}, "operands": [{"name": "EAX", "type": "r32", "desc": "Implicit destination register (accumulator) where the loaded doubleword is stored."}, {"name": "DS:[ESI]", "type": "m32", "desc": "Memory operand at DS:ESI (source index register) from which the doubleword is loaded."}], "extension": "Base", "description": "Loads a doubleword (32-bit) from memory at address [ESI] into the EAX register, then increments or decrements ESI by 4 depending on the direction flag (DF). No flags are affected by this instruction. Commonly used in 32-bit protected mode or with repeat prefix (REP) to load successive doublewords, though the repeat would only retain the final value in EAX.", "pseudocode": "EAX ← [ESI];\nif (DF == 0) {\n ESI ← ESI + 4;\n} else {\n ESI ← ESI - 4;\n}", "example": "LODSD"} {"mnemonic": "lodsq", "architecture": "x86", "full_name": "Load String Quadword", "summary": "Loads quadword from [RSI] into RAX.", "syntax": "LODSQ", "encoding": {"format": "Legacy", "hex_opcode": "REX.W + AD", "length": "2", "visual_parts": [], "binary_pattern": "48 | AC", "bit_positions": "+0 | +1"}, "operands": [], "extension": "Base (64-bit)", "description": "Loads a 64-bit value from memory at [RSI] into RAX, then adjusts RSI by ±8 based on the direction flag (DF). This is a string primitive operation commonly used in loops with REP prefix. No flags are affected by this instruction itself.", "pseudocode": "RAX ← [RSI];\nif (DF == 0) RSI ← RSI + 8;\nelse RSI ← RSI - 8;", "example": "LODSQ"} {"mnemonic": "stosw", "architecture": "x86", "full_name": "Store String Word", "summary": "Stores AX to memory at [EDI].", "syntax": "STOSW", "encoding": {"format": "Legacy", "hex_opcode": "AB", "length": "2", "visual_parts": [], "binary_pattern": "66 | AA", "bit_positions": "+0 | +1"}, "operands": [], "extension": "Base", "description": "Stores the 16-bit value in AX to memory at [EDI], then adjusts EDI by ±2 based on the direction flag (DF). This is a string primitive typically used with REP prefix for bulk memory fills. No flags are affected.", "pseudocode": "[EDI] ← AX;\nif (DF == 0) EDI ← EDI + 2;\nelse EDI ← EDI - 2;", "example": "STOSW"} {"mnemonic": "stosd", "architecture": "x86", "full_name": "Store String Doubleword", "summary": "Stores EAX to memory at [EDI].", "syntax": "STOSD", "encoding": {"format": "Legacy", "hex_opcode": "AB", "length": "1", "visual_parts": [], "binary_pattern": "AA", "bit_positions": "+0"}, "operands": [], "extension": "Base", "description": "Stores the 32-bit value in EAX to memory at [EDI], then adjusts EDI by ±4 based on the direction flag (DF). This is a string primitive commonly used with REP prefix for fast memory initialization. No flags are affected.", "pseudocode": "[EDI] ← EAX;\nif (DF == 0) EDI ← EDI + 4;\nelse EDI ← EDI - 4;", "example": "STOSD"} {"mnemonic": "stosq", "architecture": "x86", "full_name": "Store String Quadword", "summary": "Stores RAX to memory at [RDI].", "syntax": "STOSQ", "encoding": {"format": "Legacy", "hex_opcode": "REX.W + AB", "length": "2", "visual_parts": [], "binary_pattern": "48 | AA", "bit_positions": "+0 | +1"}, "operands": [], "extension": "Base (64-bit)", "description": "Stores the 64-bit value in RAX to memory at [RDI], then adjusts RDI by ±8 based on the direction flag (DF). Available only in 64-bit mode, this is a string primitive typically used with REP prefix for bulk memory operations. No flags are affected.", "pseudocode": "[RDI] ← RAX;\nif (DF == 0) RDI ← RDI + 8;\nelse RDI ← RDI - 8;", "example": "STOSQ"} {"mnemonic": "movsw", "architecture": "x86", "full_name": "Move String Word", "summary": "Moves word from [ESI] to [EDI].", "syntax": "MOVSW", "encoding": {"format": "Legacy", "hex_opcode": "A5", "length": "2", "visual_parts": [], "binary_pattern": "66 | A5", "bit_positions": "+0 | +1"}, "operands": [], "extension": "Base", "description": "Copies a 16-bit word from memory at [ESI] to memory at [EDI], then adjusts both ESI and EDI by ±2 based on the direction flag (DF). This is a string primitive commonly used with REP prefix for memory-to-memory block moves. No flags are affected.", "pseudocode": "[EDI] ← [ESI];\nif (DF == 0) { ESI ← ESI + 2; EDI ← EDI + 2; }\nelse { ESI ← ESI - 2; EDI ← EDI - 2; }", "example": "MOVSW"} {"mnemonic": "movsd", "architecture": "x86", "full_name": "Move String Doubleword", "summary": "Moves doubleword from [ESI] to [EDI].", "syntax": "MOVSD", "encoding": {"format": "Legacy", "hex_opcode": "A5", "length": "1", "visual_parts": [], "binary_pattern": "A5", "bit_positions": "+0"}, "operands": [], "extension": "Base", "description": "Copies a 32-bit doubleword from memory at [ESI] to memory at [EDI], then adjusts both ESI and EDI by ±4 based on the direction flag (DF). This is a string primitive frequently used with REP prefix for fast memory copy operations. No flags are affected.", "pseudocode": "[EDI] ← [ESI];\nif (DF == 0) { ESI ← ESI + 4; EDI ← EDI + 4; }\nelse { ESI ← ESI - 4; EDI ← EDI - 4; }", "example": "MOVSD"} {"mnemonic": "movsq", "architecture": "x86", "full_name": "Move String Quadword", "summary": "Moves quadword from [RSI] to [RDI].", "syntax": "MOVSQ", "encoding": {"format": "Legacy", "hex_opcode": "REX.W + A5", "length": "2", "visual_parts": [], "binary_pattern": "48 | A5", "bit_positions": "+0 | +1"}, "operands": [], "extension": "Base (64-bit)", "description": "Copies a 64-bit quadword from memory at [RSI] to memory at [RDI], then adjusts both RSI and RDI by ±8 based on the direction flag (DF). Available only in 64-bit mode, this string primitive is commonly used with REP prefix for optimized memory block copies. No flags are affected.", "pseudocode": "[RDI] ← [RSI];\nif (DF == 0) { RSI ← RSI + 8; RDI ← RDI + 8; }\nelse { RSI ← RSI - 8; RDI ← RDI - 8; }", "example": "MOVSQ"} {"mnemonic": "insw", "architecture": "x86", "full_name": "Input String Word from Port", "summary": "Reads word from I/O port to memory at [EDI].", "syntax": "INSW", "encoding": {"format": "Legacy", "hex_opcode": "6D", "length": "2", "visual_parts": [], "binary_pattern": "66 | 6D", "bit_positions": "+0 | +1"}, "operands": [], "extension": "Base", "description": "Reads a 16-bit word from the I/O port specified in DX into memory at [EDI], then adjusts EDI by ±2 based on the direction flag (DF). This instruction is privileged and typically used with REP prefix for bulk I/O input operations. No flags are affected.", "pseudocode": "[EDI] ← IO_PORT[DX];\nif (DF == 0) EDI ← EDI + 2;\nelse EDI ← EDI - 2;", "example": "INSW"} {"mnemonic": "insd", "architecture": "x86", "full_name": "Input String Doubleword from Port", "summary": "Reads doubleword from I/O port to memory at [EDI].", "syntax": "INSD", "encoding": {"format": "Legacy", "hex_opcode": "6D", "length": "1", "visual_parts": [], "binary_pattern": "6D", "bit_positions": "+0"}, "operands": [{"name": "DX", "type": "implicit", "desc": "The 16-bit port address register, implicitly selects the I/O port."}, {"name": "EDI", "type": "implicit", "desc": "The destination memory address register; auto-incremented or auto-decremented based on DF."}], "extension": "Base", "description": "Reads a 32-bit doubleword from the I/O port specified by the DX register and stores it in memory at the linear address [EDI]. The EDI register is then incremented or decremented based on the DF (Direction Flag); DF=0 increments EDI by 4, DF=1 decrements by 4. This instruction is typically used within a REP prefix loop for block I/O transfers and requires I/O privilege level in protected mode.", "pseudocode": "memory[EDI] ← IO_PORT[DX];\nif (DF == 0) {\n EDI ← EDI + 4;\n} else {\n EDI ← EDI - 4;\n}", "example": "INSD"} {"mnemonic": "outsw", "architecture": "x86", "full_name": "Output String Word to Port", "summary": "Writes word from memory at [ESI] to I/O port.", "syntax": "OUTSW", "encoding": {"format": "Legacy", "hex_opcode": "6F", "length": "2", "visual_parts": [], "binary_pattern": "66 | 6F", "bit_positions": "+0 | +1"}, "operands": [{"name": "DX", "type": "implicit", "desc": "The 16-bit port address register, implicitly selects the I/O port."}, {"name": "ESI", "type": "implicit", "desc": "The source memory address register; auto-incremented or auto-decremented based on DF."}], "extension": "Base", "description": "Reads a 16-bit word from memory at the linear address [ESI] and writes it to the I/O port specified by the DX register. The ESI register is then incremented or decremented based on the DF flag; DF=0 increments ESI by 2, DF=1 decrements by 2. This instruction is typically used within a REP prefix loop for block I/O transfers and requires I/O privilege level in protected mode.", "pseudocode": "IO_PORT[DX] ← memory[ESI];\nif (DF == 0) {\n ESI ← ESI + 2;\n} else {\n ESI ← ESI - 2;\n}", "example": "OUTSW"} {"mnemonic": "outsd", "architecture": "x86", "full_name": "Output String Doubleword to Port", "summary": "Writes doubleword from memory at [ESI] to I/O port.", "syntax": "OUTSD", "encoding": {"format": "Legacy", "hex_opcode": "6F", "length": "1", "visual_parts": [], "binary_pattern": "6F", "bit_positions": "+0"}, "operands": [{"name": "DX", "type": "implicit", "desc": "The 16-bit port address register, implicitly selects the I/O port."}, {"name": "ESI", "type": "implicit", "desc": "The source memory address register; auto-incremented or auto-decremented based on DF."}], "extension": "Base", "description": "Reads a 32-bit doubleword from memory at the linear address [ESI] and writes it to the I/O port specified by the DX register. The ESI register is then incremented or decremented based on the DF flag; DF=0 increments ESI by 4, DF=1 decrements by 4. This instruction is typically used within a REP prefix loop for block I/O transfers and requires I/O privilege level in protected mode.", "pseudocode": "IO_PORT[DX] ← memory[ESI];\nif (DF == 0) {\n ESI ← ESI + 4;\n} else {\n ESI ← ESI - 4;\n}", "example": "OUTSD"} {"mnemonic": "fld1", "architecture": "x86", "full_name": "Load Constant 1.0", "summary": "Pushes +1.0 onto the FPU register stack.", "syntax": "FLD1", "encoding": {"format": "Legacy", "hex_opcode": "D9 E8", "length": "2", "visual_parts": [], "binary_pattern": "D9 | E8", "bit_positions": "+0 | +1"}, "operands": [], "extension": "x87 FPU", "description": "Decrements the FPU stack pointer (ST(7)→ST(0)), then loads the constant +1.0 (extended precision double) into the top of the x87 FPU register stack (ST(0)). The instruction sets the C1 flag to 0 and leaves other status flags unchanged unless a stack overflow occurs (C0, C2, C3 may be set on exception). No CPU integer flags are affected.", "pseudocode": "FPU_TOP ← FPU_TOP - 1;\nif (FPU_TOP overflow) {\n raise FPU_EXCEPTION;\n}\nST(0) ← +1.0;", "example": "FLD1"} {"mnemonic": "fldz", "architecture": "x86", "full_name": "Load Constant +0.0", "summary": "Pushes +0.0 onto the FPU register stack.", "syntax": "FLDZ", "encoding": {"format": "Legacy", "hex_opcode": "D9 EE", "length": "2", "visual_parts": [], "binary_pattern": "D9 | EE", "bit_positions": "+0 | +1"}, "operands": [], "extension": "x87 FPU", "description": "Decrements the FPU stack pointer (ST(7)→ST(0)), then loads the constant +0.0 (extended precision double) into the top of the x87 FPU register stack (ST(0)). The instruction sets the C1 flag to 0 and leaves other status flags unchanged unless a stack overflow occurs. No CPU integer flags are affected.", "pseudocode": "FPU_TOP ← FPU_TOP - 1;\nif (FPU_TOP overflow) {\n raise FPU_EXCEPTION;\n}\nST(0) ← +0.0;", "example": "FLDZ"} {"mnemonic": "fldpi", "architecture": "x86", "full_name": "Load Constant Pi", "summary": "Pushes Pi onto the FPU register stack.", "syntax": "FLDPI", "encoding": {"format": "Legacy", "hex_opcode": "D9 EB", "length": "2", "visual_parts": [], "binary_pattern": "D9 | EB", "bit_positions": "+0 | +1"}, "operands": [], "extension": "x87 FPU", "description": "Decrements the FPU stack pointer (ST(7)→ST(0)), then loads the constant Pi (π ≈ 3.14159265..., extended precision) into the top of the x87 FPU register stack (ST(0)). The instruction sets the C1 flag to 0 and leaves other status flags unchanged unless a stack overflow occurs. No CPU integer flags are affected.", "pseudocode": "FPU_TOP ← FPU_TOP - 1;\nif (FPU_TOP overflow) {\n raise FPU_EXCEPTION;\n}\nST(0) ← π;", "example": "FLDPI"} {"mnemonic": "fldl2e", "architecture": "x86", "full_name": "Load Constant log2(e)", "summary": "Pushes log2(e) onto the FPU register stack.", "syntax": "FLDL2E", "encoding": {"format": "Legacy", "hex_opcode": "D9 EA", "length": "2", "visual_parts": [], "binary_pattern": "D9 | EA", "bit_positions": "+0 | +1"}, "operands": [], "extension": "x87 FPU", "description": "Decrements the FPU stack pointer (ST(7)→ST(0)), then loads the constant log₂(e) (≈ 1.44269504..., extended precision) into the top of the x87 FPU register stack (ST(0)). This constant is useful for logarithm and exponential calculations. The instruction sets the C1 flag to 0 and leaves other status flags unchanged unless a stack overflow occurs.", "pseudocode": "FPU_TOP ← FPU_TOP - 1;\nif (FPU_TOP overflow) {\n raise FPU_EXCEPTION;\n}\nST(0) ← log₂(e);", "example": "FLDL2E"} {"mnemonic": "fldl2t", "architecture": "x86", "full_name": "Load Constant log2(10)", "summary": "Pushes log2(10) onto the FPU register stack.", "syntax": "FLDL2T", "encoding": {"format": "Legacy", "hex_opcode": "D9 E9", "length": "2", "visual_parts": [], "binary_pattern": "D9 | E9", "bit_positions": "+0 | +1"}, "operands": [], "extension": "x87 FPU", "description": "Decrements the FPU stack pointer (ST(7)→ST(0)), then loads the constant log₂(10) (≈ 3.32192809..., extended precision) into the top of the x87 FPU register stack (ST(0)). This constant is useful for base-10 logarithm calculations. The instruction sets the C1 flag to 0 and leaves other status flags unchanged unless a stack overflow occurs.", "pseudocode": "FPU_TOP ← FPU_TOP - 1;\nif (FPU_TOP overflow) {\n raise FPU_EXCEPTION;\n}\nST(0) ← log₂(10);", "example": "FLDL2T"} {"mnemonic": "fldlg2", "architecture": "x86", "full_name": "Load Constant log10(2)", "summary": "Pushes log10(2) onto the FPU register stack.", "syntax": "FLDLG2", "encoding": {"format": "Legacy", "hex_opcode": "D9 EC", "length": "2", "visual_parts": [], "binary_pattern": "D9 | EC", "bit_positions": "+0 | +1"}, "operands": [], "extension": "x87 FPU", "description": "Pushes the constant log₁₀(2) ≈ 0.30103 onto the FPU register stack, incrementing the stack pointer (TOP). This is a zero-operand x87 FPU instruction that loads a precomputed constant into ST(0). No flags are modified by this instruction.", "pseudocode": "TOP ← (TOP - 1) mod 8; ST(0) ← log10(2);", "example": "FLDLG2"} {"mnemonic": "fldln2", "architecture": "x86", "full_name": "Load Constant ln(2)", "summary": "Pushes ln(2) onto the FPU register stack.", "syntax": "FLDLN2", "encoding": {"format": "Legacy", "hex_opcode": "D9 ED", "length": "2", "visual_parts": [], "binary_pattern": "D9 | ED", "bit_positions": "+0 | +1"}, "operands": [], "extension": "x87 FPU", "description": "Pushes the constant ln(2) ≈ 0.69315 onto the FPU register stack, incrementing the stack pointer (TOP). This is a zero-operand x87 FPU instruction that loads a precomputed constant into ST(0). No flags are modified by this instruction.", "pseudocode": "TOP ← (TOP - 1) mod 8; ST(0) ← ln(2);", "example": "FLDLN2"} {"mnemonic": "fincstp", "architecture": "x86", "full_name": "Increment Stack-Top Pointer", "summary": "Increments the TOP field in the FPU status word.", "syntax": "FINCSTP", "encoding": {"format": "Legacy", "hex_opcode": "D9 F7", "length": "2", "visual_parts": [], "binary_pattern": "D9 | F7", "bit_positions": "+0 | +1"}, "operands": [], "extension": "x87 FPU", "description": "Increments the TOP field (bits 13:11) of the x87 FPU status word, rotating the register stack pointer forward by one position. This is a zero-operand instruction that does not modify CPU EFLAGS. It is used to manually adjust the FPU stack pointer without popping data.", "pseudocode": "TOP ← (TOP + 1) mod 8;", "example": "FINCSTP"} {"mnemonic": "fdecstp", "architecture": "x86", "full_name": "Decrement Stack-Top Pointer", "summary": "Decrements the TOP field in the FPU status word.", "syntax": "FDECSTP", "encoding": {"format": "Legacy", "hex_opcode": "D9 F6", "length": "2", "visual_parts": [], "binary_pattern": "D9 | F6", "bit_positions": "+0 | +1"}, "operands": [], "extension": "x87 FPU", "description": "Decrements the TOP field (bits 13:11) of the x87 FPU status word, rotating the register stack pointer backward by one position. This is a zero-operand instruction that does not modify CPU EFLAGS. It is used to manually adjust the FPU stack pointer without pushing data.", "pseudocode": "TOP ← (TOP - 1) mod 8;", "example": "FDECSTP"} {"mnemonic": "ffree", "architecture": "x86", "full_name": "Free Floating-Point Register", "summary": "Sets the tag for ST(i) to empty.", "syntax": "FFREE ST(i)", "encoding": {"format": "Legacy", "hex_opcode": "DD C0+i", "length": "2", "visual_parts": [], "binary_pattern": "DD", "bit_positions": "+0"}, "operands": [{"name": "dest", "desc": "Register"}], "extension": "x87 FPU", "description": "Sets the tag bits for the specified FPU register to 11b (empty), marking it as unused without removing its value from the register. This instruction does not pop the stack or modify EFLAGS. It is commonly used to release floating-point registers for reuse.", "pseudocode": "Tag[ST(i)] ← 11b;", "example": "FFREE st(1)"} {"mnemonic": "fcmovb", "architecture": "x86", "full_name": "Floating-Point Conditional Move If Below", "summary": "Moves ST(i) to ST(0) if CF=1.", "syntax": "FCMOVB ST(0), ST(i)", "encoding": {"format": "Legacy", "hex_opcode": "DA C0+i", "length": "2", "visual_parts": [], "binary_pattern": "DA", "bit_positions": "+0"}, "operands": [{"name": "src", "desc": "Register"}], "extension": "x87 FPU (P6+)", "description": "Conditionally moves ST(i) to ST(0) if the carry flag (CF) is set, based on a prior integer comparison or EFLAGS state. This x87 instruction available on Pentium Pro and later does not modify EFLAGS; it only reads CF to determine whether to execute the move. If CF=0, no move occurs and ST(0) remains unchanged.", "pseudocode": "if (CF == 1) { ST(0) ← ST(i); }", "example": "FCMOVB st(0), st(1)"} {"mnemonic": "fcmove", "architecture": "x86", "full_name": "Floating-Point Conditional Move If Equal", "summary": "Moves ST(i) to ST(0) if ZF=1.", "syntax": "FCMOVE ST(0), ST(i)", "encoding": {"format": "Legacy", "hex_opcode": "DA C8+i", "length": "2", "visual_parts": [], "binary_pattern": "DA", "bit_positions": "+0"}, "operands": [{"name": "src", "desc": "Register"}], "extension": "x87 FPU (P6+)", "description": "Conditionally moves ST(i) to ST(0) if the zero flag (ZF) is set, based on a prior integer comparison or EFLAGS state. This x87 instruction available on Pentium Pro and later does not modify EFLAGS; it only reads ZF to determine whether to execute the move. If ZF=0, no move occurs and ST(0) remains unchanged.", "pseudocode": "if (ZF == 1) { ST(0) ← ST(i); }", "example": "FCMOVE st(0), st(1)"} {"mnemonic": "fcmovbe", "architecture": "x86", "full_name": "Floating-Point Conditional Move If Below or Equal", "summary": "Moves ST(i) to ST(0) if CF=1 or ZF=1.", "syntax": "FCMOVBE ST(0), ST(i)", "encoding": {"format": "Legacy", "hex_opcode": "DA D0+i", "length": "2", "visual_parts": [], "binary_pattern": "DA", "bit_positions": "+0"}, "operands": [{"name": "src", "desc": "Register"}], "extension": "x87 FPU (P6+)", "description": "Conditionally moves ST(i) to ST(0) if the carry flag (CF) is set or the zero flag (ZF) is set, based on a prior integer comparison or EFLAGS state. This x87 instruction available on Pentium Pro and later does not modify EFLAGS; it only reads CF and ZF to determine whether to execute the move. If neither CF nor ZF is set, no move occurs.", "pseudocode": "if ((CF == 1) || (ZF == 1)) { ST(0) ← ST(i); }", "example": "FCMOVBE st(0), st(1)"} {"mnemonic": "fcmovu", "architecture": "x86", "full_name": "Floating-Point Conditional Move If Unordered", "summary": "Moves ST(i) to ST(0) if PF=1.", "syntax": "FCMOVU ST(0), ST(i)", "encoding": {"format": "Legacy", "hex_opcode": "DA D8+i", "length": "2", "visual_parts": [], "binary_pattern": "DA", "bit_positions": "+0"}, "operands": [{"name": "src", "desc": "Register"}], "extension": "x87 FPU (P6+)", "description": "Conditionally moves the value in ST(i) to ST(0) if the parity flag (PF) is set, indicating an unordered comparison result (one or both operands are NaN). This instruction is part of the x87 FPU conditional move family introduced in P6 and later processors. No flags are modified by this instruction.", "pseudocode": "if (PF == 1) { ST(0) ← ST(i); }", "example": "FCMOVU st(0), st(1)"} {"mnemonic": "fcmovnb", "architecture": "x86", "full_name": "Floating-Point Conditional Move If Not Below", "summary": "Moves ST(i) to ST(0) if CF=0.", "syntax": "FCMOVNB ST(0), ST(i)", "encoding": {"format": "Legacy", "hex_opcode": "DB C0+i", "length": "2", "visual_parts": [], "binary_pattern": "DB", "bit_positions": "+0"}, "operands": [{"name": "src", "desc": "Register"}], "extension": "x87 FPU (P6+)", "description": "Conditionally moves the value in ST(i) to ST(0) if the carry flag (CF) is clear, indicating the first operand is not below the second in an x87 FPU comparison context. This is part of the x87 conditional move instruction set available on P6 and later processors. No flags are modified by this instruction.", "pseudocode": "if (CF == 0) { ST(0) ← ST(i); }", "example": "FCMOVNB st(0), st(1)"} {"mnemonic": "fcmovne", "architecture": "x86", "full_name": "Floating-Point Conditional Move If Not Equal", "summary": "Moves ST(i) to ST(0) if ZF=0.", "syntax": "FCMOVNE ST(0), ST(i)", "encoding": {"format": "Legacy", "hex_opcode": "DB C8+i", "length": "2", "visual_parts": [], "binary_pattern": "DB", "bit_positions": "+0"}, "operands": [{"name": "src", "desc": "Register"}], "extension": "x87 FPU (P6+)", "description": "Conditionally moves the value in ST(i) to ST(0) if the zero flag (ZF) is clear, indicating the operands are not equal in an x87 FPU comparison context. This instruction is part of the x87 conditional move family on P6 and later processors. No flags are modified by this instruction.", "pseudocode": "if (ZF == 0) { ST(0) ← ST(i); }", "example": "FCMOVNE st(0), st(1)"} {"mnemonic": "fcmovnbe", "architecture": "x86", "full_name": "Floating-Point Conditional Move If Not Below or Equal", "summary": "Moves ST(i) to ST(0) if CF=0 and ZF=0.", "syntax": "FCMOVNBE ST(0), ST(i)", "encoding": {"format": "Legacy", "hex_opcode": "DB D0+i", "length": "2", "visual_parts": [], "binary_pattern": "DB", "bit_positions": "+0"}, "operands": [{"name": "src", "desc": "Register"}], "extension": "x87 FPU (P6+)", "description": "Conditionally moves the value in ST(i) to ST(0) if both the carry flag (CF) and zero flag (ZF) are clear, indicating the first operand is greater than the second in an x87 FPU comparison context. This instruction is part of the x87 conditional move set on P6 and later processors. No flags are modified by this instruction.", "pseudocode": "if (CF == 0 && ZF == 0) { ST(0) ← ST(i); }", "example": "FCMOVNBE st(0), st(1)"} {"mnemonic": "fcmovnu", "architecture": "x86", "full_name": "Floating-Point Conditional Move If Not Unordered", "summary": "Moves ST(i) to ST(0) if PF=0.", "syntax": "FCMOVNU ST(0), ST(i)", "encoding": {"format": "Legacy", "hex_opcode": "DB D8+i", "length": "2", "visual_parts": [], "binary_pattern": "DB", "bit_positions": "+0"}, "operands": [{"name": "src", "desc": "Register"}], "extension": "x87 FPU (P6+)", "description": "Conditionally moves the value in ST(i) to ST(0) if the parity flag (PF) is clear, indicating an ordered comparison result (neither operand is NaN) in x87 FPU context. This instruction is part of the x87 conditional move family on P6 and later processors. No flags are modified by this instruction.", "pseudocode": "if (PF == 0) { ST(0) ← ST(i); }", "example": "FCMOVNU st(0), st(1)"} {"mnemonic": "packuswb", "architecture": "x86", "full_name": "Pack with Unsigned Saturation Word to Byte", "summary": "Converts signed words to unsigned bytes with saturation.", "syntax": "PACKUSWB xmm1, xmm2/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 67", "length": "4+", "visual_parts": [], "binary_pattern": "66 | 0F | 67", "bit_positions": "+0 | +1 | +2"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSE2", "description": "Converts four signed 16-bit words from each of two XMM registers or memory into eight unsigned 8-bit bytes with unsigned saturation, storing the result in the destination XMM register. Values greater than 255 saturate to 255, and negative values saturate to 0. No flags are affected by this instruction; it is an SSE2 SIMD operation.", "pseudocode": "for (i = 0; i < 4; i++) {\n temp1[i] = (dest[i*16:i*16+15] < 0) ? 0 : ((dest[i*16:i*16+15] > 255) ? 255 : dest[i*16:i*16+15]);\n temp2[i] = (src[i*16:i*16+15] < 0) ? 0 : ((src[i*16:i*16+15] > 255) ? 255 : src[i*16:i*16+15]);\n}\ndest[0:7] = temp1[0]; dest[8:15] = temp1[1]; dest[16:23] = temp1[2]; dest[24:31] = temp1[3];\ndest[32:39] = temp2[0]; dest[40:47] = temp2[1]; dest[48:55] = temp2[2]; dest[56:63] = temp2[3];", "example": "PACKUSWB xmm1, xmm2/m128"} {"mnemonic": "punpckhbw", "architecture": "x86", "full_name": "Unpack High Data Bytes", "summary": "Interleaves high bytes from two sources.", "syntax": "PUNPCKHBW xmm1, xmm2/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 68", "length": "4+", "visual_parts": [], "binary_pattern": "66 | 0F | 68", "bit_positions": "+0 | +1 | +2"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSE2", "description": "Interleaves the high-order bytes from corresponding positions in the destination and source XMM registers, storing bytes from the destination in even-indexed positions and source bytes in odd-indexed positions of the result. This SSE2 instruction performs no flag modifications and operates on 128-bit packed data.", "pseudocode": "for (i = 0; i < 8; i++) {\n result[i*2] = dest[i*8+64:i*8+71];\n result[i*2+1] = src[i*8+64:i*8+71];\n}\ndest ← result;", "example": "PUNPCKHBW xmm1, xmm2/m128"} {"mnemonic": "punpckhwd", "architecture": "x86", "full_name": "Unpack High Data Words", "summary": "Interleaves high words.", "syntax": "PUNPCKHWD xmm1, xmm2/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 69", "length": "4+", "visual_parts": [], "binary_pattern": "66 | 0F | 69", "bit_positions": "+0 | +1 | +2"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSE2", "description": "Interleaves the high-order words from corresponding positions in the destination and source XMM registers, storing words from the destination in even-indexed positions and source words in odd-indexed positions of the result. This SSE2 instruction performs no flag modifications and operates on 128-bit packed data.", "pseudocode": "for (i = 0; i < 4; i++) {\n result[i*2] = dest[i*16+64:i*16+79];\n result[i*2+1] = src[i*16+64:i*16+79];\n}\ndest ← result;", "example": "PUNPCKHWD xmm1, xmm2/m128"} {"mnemonic": "punpckhdq", "architecture": "x86", "full_name": "Unpack High Data Doublewords", "summary": "Interleaves high doublewords.", "syntax": "PUNPCKHDQ xmm1, xmm2/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 6A", "length": "4+", "visual_parts": [], "binary_pattern": "66 | 0F | 6A", "bit_positions": "+0 | +1 | +2"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSE2", "description": "Unpacks and interleaves the high-order 32-bit doublewords from the destination and source XMM registers into the destination. The instruction treats the 128-bit XMM register as four 32-bit elements, selects elements 1 and 3 (the high two), and interleaves them as [src[3], dest[3], src[1], dest[1]]. No flags are affected.", "pseudocode": "dest[0:31] ← dest[63:32]\ndest[32:63] ← src[63:32]\ndest[64:95] ← dest[127:96]\ndest[96:127] ← src[127:96]", "example": "PUNPCKHDQ xmm1, xmm2/m128"} {"mnemonic": "punpckhqdq", "architecture": "x86", "full_name": "Unpack High Data Quadwords", "summary": "Interleaves high quadwords.", "syntax": "PUNPCKHQDQ xmm1, xmm2/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 6D", "length": "4+", "visual_parts": [], "binary_pattern": "66 | 0F | 6D", "bit_positions": "+0 | +1 | +2"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSE2", "description": "Unpacks and interleaves the high-order 64-bit quadwords from the destination and source XMM registers into the destination. The instruction treats the 128-bit XMM register as two 64-bit elements, selects element 1 (the high half), and interleaves them as [src[1], dest[1]]. No flags are affected.", "pseudocode": "dest[0:63] ← dest[127:64]\ndest[64:127] ← src[127:64]", "example": "PUNPCKHQDQ xmm1, xmm2/m128"} {"mnemonic": "psadbw", "architecture": "x86", "full_name": "Compute Sum of Absolute Differences", "summary": "Computes absolute differences of bytes and sums them to words.", "syntax": "PSADBW xmm1, xmm2/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F F6", "length": "4+", "visual_parts": [], "binary_pattern": "66 | 0F | F6", "bit_positions": "+0 | +1 | +2"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSE2", "description": "Computes the absolute value of the difference for each of 16 packed unsigned bytes in the destination and source, then sums those differences within 64-bit groups and stores the results as two 64-bit values. Useful for motion estimation and SAD (Sum of Absolute Differences) operations. No flags are affected.", "pseudocode": "sum_low ← 0\nsum_high ← 0\nfor i in 0..7:\n sum_low ← sum_low + abs(dest[i*8 + 7:i*8] - src[i*8 + 7:i*8])\nfor i in 8..15:\n sum_high ← sum_high + abs(dest[i*8 + 7:i*8] - src[i*8 + 7:i*8])\ndest[0:63] ← sum_low\ndest[64:127] ← sum_high", "example": "PSADBW xmm1, xmm2/m128"} {"mnemonic": "pmaxub", "architecture": "x86", "full_name": "Maximum of Packed Unsigned Byte Integers", "summary": "Returns maximum of unsigned bytes.", "syntax": "PMAXUB xmm1, xmm2/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F DE", "length": "4+", "visual_parts": [], "binary_pattern": "66 | 0F | DE", "bit_positions": "+0 | +1 | +2"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSE2", "description": "Compares each of 16 packed unsigned bytes in the destination and source registers and stores the maximum value of each pair into the destination. This is an element-wise unsigned 8-bit maximum operation. No flags are affected.", "pseudocode": "for i in 0..15:\n dest[i*8 + 7:i*8] ← max(dest[i*8 + 7:i*8], src[i*8 + 7:i*8])", "example": "PMAXUB xmm1, xmm2/m128"} {"mnemonic": "pminub", "architecture": "x86", "full_name": "Minimum of Packed Unsigned Byte Integers", "summary": "Returns minimum of unsigned bytes.", "syntax": "PMINUB xmm1, xmm2/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F DA", "length": "4+", "visual_parts": [], "binary_pattern": "66 | 0F | DA", "bit_positions": "+0 | +1 | +2"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSE2", "description": "Compares each of 16 packed unsigned bytes in the destination and source registers and stores the minimum value of each pair into the destination. This is an element-wise unsigned 8-bit minimum operation. No flags are affected.", "pseudocode": "for i in 0..15:\n dest[i*8 + 7:i*8] ← min(dest[i*8 + 7:i*8], src[i*8 + 7:i*8])", "example": "PMINUB xmm1, xmm2/m128"} {"mnemonic": "pmaxsw", "architecture": "x86", "full_name": "Maximum of Packed Signed Word Integers", "summary": "Returns maximum of signed words.", "syntax": "PMAXSW xmm1, xmm2/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F EE", "length": "4+", "visual_parts": [], "binary_pattern": "66 | 0F | EE", "bit_positions": "+0 | +1 | +2"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSE2", "description": "Compares each of 8 packed signed words in the destination and source registers and stores the maximum value of each pair into the destination. This is an element-wise signed 16-bit maximum operation. No flags are affected.", "pseudocode": "for i in 0..7:\n dest[i*16 + 15:i*16] ← max_signed(dest[i*16 + 15:i*16], src[i*16 + 15:i*16])", "example": "PMAXSW xmm1, xmm2/m128"} {"mnemonic": "pminsw", "architecture": "x86", "full_name": "Minimum of Packed Signed Word Integers", "summary": "Returns minimum of signed words.", "syntax": "PMINSW xmm1, xmm2/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F EA", "length": "4+", "visual_parts": [], "binary_pattern": "66 | 0F | EA", "bit_positions": "+0 | +1 | +2"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSE2", "description": "Compares each of 8 packed signed words in the destination and source registers and stores the minimum value of each pair into the destination. This is an element-wise signed 16-bit minimum operation. No flags are affected.", "pseudocode": "for i in 0..7:\n dest[i*16 + 15:i*16] ← min_signed(dest[i*16 + 15:i*16], src[i*16 + 15:i*16])", "example": "PMINSW xmm1, xmm2/m128"} {"mnemonic": "pavgb", "architecture": "x86", "full_name": "Average Packed Integers (Byte)", "summary": "Averages packed unsigned bytes (rounded up).", "syntax": "PAVGB xmm1, xmm2/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F E0", "length": "4+", "visual_parts": [], "binary_pattern": "66 | 0F | E0", "bit_positions": "+0 | +1 | +2"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSE2", "description": "Computes the average of each pair of 16 packed unsigned bytes in the destination and source registers, rounding up (toward positive infinity), and stores the results into the destination. The formula is (a + b + 1) >> 1 for each byte pair. No flags are affected.", "pseudocode": "for i in 0..15:\n dest[i*8 + 7:i*8] ← (dest[i*8 + 7:i*8] + src[i*8 + 7:i*8] + 1) >> 1", "example": "PAVGB xmm1, xmm2/m128"} {"mnemonic": "pavgw", "architecture": "x86", "full_name": "Average Packed Integers (Word)", "summary": "Averages packed unsigned words (rounded up).", "syntax": "PAVGW xmm1, xmm2/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F E3", "length": "4+", "visual_parts": [], "binary_pattern": "66 | 0F | E3", "bit_positions": "+0 | +1 | +2"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSE2", "description": "Averages packed unsigned 16-bit integers element-wise, rounding up by adding 1 before shifting right. Each pair of corresponding 16-bit words from the destination and source are averaged independently and stored back in the destination. No flags are affected; this is a data-parallel operation with no special side effects.", "pseudocode": "for i = 0 to 7:\n dest.word[i] ← (dest.word[i] + src.word[i] + 1) >> 1", "example": "PAVGW xmm1, xmm2/m128"} {"mnemonic": "pmulhuw", "architecture": "x86", "full_name": "Packed Multiply High Unsigned", "summary": "Multiplies unsigned words, keeps high 16 bits.", "syntax": "PMULHUW xmm1, xmm2/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F E4", "length": "4+", "visual_parts": [], "binary_pattern": "66 | 0F | E4", "bit_positions": "+0 | +1 | +2"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSE2", "description": "Multiplies packed unsigned 16-bit integers and stores the high 16 bits of each 32-bit product. Each pair of corresponding 16-bit unsigned words from destination and source are multiplied (producing 32-bit results), and only the upper 16 bits are retained. No flags are affected.", "pseudocode": "for i = 0 to 7:\n product ← (uint32_t)dest.word[i] * (uint32_t)src.word[i]\n dest.word[i] ← (uint16_t)(product >> 16)", "example": "PMULHUW xmm1, xmm2/m128"} {"mnemonic": "pmulhw", "architecture": "x86", "full_name": "Packed Multiply High Signed", "summary": "Multiplies signed words, keeps high 16 bits.", "syntax": "PMULHW xmm1, xmm2/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F E5", "length": "4+", "visual_parts": [], "binary_pattern": "66 | 0F | E5", "bit_positions": "+0 | +1 | +2"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSE2", "description": "Multiplies packed signed 16-bit integers and stores the high 16 bits of each 32-bit product. Each pair of corresponding 16-bit signed words from destination and source are multiplied (producing 32-bit results), and only the upper 16 bits are retained. No flags are affected.", "pseudocode": "for i = 0 to 7:\n product ← (int32_t)dest.sword[i] * (int32_t)src.sword[i]\n dest.sword[i] ← (int16_t)(product >> 16)", "example": "PMULHW xmm1, xmm2/m128"} {"mnemonic": "psubq", "architecture": "x86", "full_name": "Packed Subtract Quadword", "summary": "Subtracts packed quadwords.", "syntax": "PSUBQ xmm1, xmm2/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F FB", "length": "4+", "visual_parts": [], "binary_pattern": "66 | 0F | FB", "bit_positions": "+0 | +1 | +2"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSE2", "description": "Subtracts packed 64-bit integers element-wise without saturation. The two 64-bit integers in the destination are each subtracted from by the corresponding 64-bit integers in the source, and results wrap on overflow. No flags are affected; wrapping behavior is identical to 64-bit integer subtraction.", "pseudocode": "for i = 0 to 1:\n dest.quad[i] ← dest.quad[i] - src.quad[i]", "example": "PSUBQ xmm1, xmm2/m128"} {"mnemonic": "pmuludq", "architecture": "x86", "full_name": "Multiply Packed Unsigned Doubleword Integers", "summary": "Multiplies low 32-bits of each 64-bit chunk to 64-bit result.", "syntax": "PMULUDQ xmm1, xmm2/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F F4", "length": "4+", "visual_parts": [], "binary_pattern": "66 | 0F | F4", "bit_positions": "+0 | +1 | +2"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSE2", "description": "Multiplies the low 32-bit doublewords of packed unsigned integers, producing 64-bit products. The even-indexed 32-bit elements (0, 2) from destination and source are multiplied, and the 64-bit results are written back to the even positions. No flags are affected.", "pseudocode": "dest.quad[0] ← (uint64_t)dest.dword[0] * (uint64_t)src.dword[0]\ndest.quad[1] ← (uint64_t)dest.dword[2] * (uint64_t)src.dword[2]", "example": "PMULUDQ xmm1, xmm2/m128"} {"mnemonic": "pslldq", "architecture": "x86", "full_name": "Shift Double Quadword Left Logical", "summary": "Shifts the entire 128-bit register left by bytes.", "syntax": "PSLLDQ xmm1, imm8", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 73 /7", "length": "5+", "visual_parts": [], "binary_pattern": "66 | 0F | 73 | ModRM", "bit_positions": "+0 | +1 | +2 | +3"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "count", "desc": "Imm"}], "extension": "SSE2", "description": "Shifts the entire 128-bit value in the destination XMM register left by a byte count, filling with zeros from the right. The shift count is specified as an 8-bit immediate and is applied to the whole register as a unit, not element-wise. No flags are affected.", "pseudocode": "shift_count ← imm8\nif shift_count >= 16:\n dest ← 0\nelse:\n dest ← dest << (shift_count * 8)", "example": "PSLLDQ xmm1, 3"} {"mnemonic": "psrldq", "architecture": "x86", "full_name": "Shift Double Quadword Right Logical", "summary": "Shifts the entire 128-bit register right by bytes.", "syntax": "PSRLDQ xmm1, imm8", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 73 /3", "length": "5+", "visual_parts": [], "binary_pattern": "66 | 0F | 73 | ModRM", "bit_positions": "+0 | +1 | +2 | +3"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "count", "desc": "Imm"}], "extension": "SSE2", "description": "Shifts the entire 128-bit value in the destination XMM register right by a byte count, filling with zeros from the left. The shift count is specified as an 8-bit immediate and is applied to the whole register as a unit, not element-wise. No flags are affected.", "pseudocode": "shift_count ← imm8\nif shift_count >= 16:\n dest ← 0\nelse:\n dest ← dest >> (shift_count * 8)", "example": "PSRLDQ xmm1, 3"} {"mnemonic": "cvtdq2ps", "architecture": "x86", "full_name": "Convert Packed Doubleword Integers to Packed Single-Precision", "summary": "Converts four 32-bit integers to floats.", "syntax": "CVTDQ2PS xmm1, xmm2/m128", "encoding": {"format": "SSE2", "hex_opcode": "NP 0F 5B /r", "length": "3+", "visual_parts": [], "binary_pattern": "0F | 5B", "bit_positions": "+0 | +1"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSE2", "description": "Converts four packed 32-bit signed doubleword integers to four packed single-precision floating-point values. Conversion uses the current rounding mode from MXCSR. Precision may be lost for very large integers; no flags are explicitly set, but the instruction may generate floating-point exceptions via MXCSR.", "pseudocode": "for i = 0 to 3:\n dest.float[i] ← (float)src.dword[i]", "example": "CVTDQ2PS xmm1, xmm2/m128"} {"mnemonic": "cvtps2dq", "architecture": "x86", "full_name": "Convert Packed Single-Precision to Packed Doubleword Integers", "summary": "Converts four floats to 32-bit integers (Rounded).", "syntax": "CVTPS2DQ xmm1, xmm2/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 5B", "length": "4+", "visual_parts": [], "binary_pattern": "66 | 0F | 5B", "bit_positions": "+0 | +1 | +2"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSE2", "description": "Converts four packed single-precision floating-point values to four packed signed 32-bit integers using the rounding mode specified in MXCSR. If any input is NaN, the result is the minimum signed 32-bit integer (0x80000000). Operates on 128-bit XMM registers and sets ZF, PF, CF based on rounding exceptions in MXCSR.", "pseudocode": "dest[0:31] ← RoundToNearest(src[0:31]); dest[32:63] ← RoundToNearest(src[32:63]); dest[64:95] ← RoundToNearest(src[64:95]); dest[96:127] ← RoundToNearest(src[96:127]);", "example": "CVTPS2DQ xmm1, xmm2/m128"} {"mnemonic": "cvttps2dq", "architecture": "x86", "full_name": "Convert with Truncation Packed Single-Precision to Packed Doubleword Integers", "summary": "Converts four floats to 32-bit integers (Truncated).", "syntax": "CVTTPS2DQ xmm1, xmm2/m128", "encoding": {"format": "SSE2", "hex_opcode": "F3 0F 5B", "length": "4+", "visual_parts": [], "binary_pattern": "F3 | 0F | 5B", "bit_positions": "+0 | +1 | +2"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSE2", "description": "Converts four packed single-precision floating-point values to four packed signed 32-bit integers by truncating toward zero (discarding fractional part). If any input is NaN or out of range, the result is 0x80000000. Operates on 128-bit XMM registers without using MXCSR rounding mode.", "pseudocode": "dest[0:31] ← Truncate(src[0:31]); dest[32:63] ← Truncate(src[32:63]); dest[64:95] ← Truncate(src[64:95]); dest[96:127] ← Truncate(src[96:127]);", "example": "CVTTPS2DQ xmm1, xmm2/m128"} {"mnemonic": "movmskps", "architecture": "x86", "full_name": "Extract Packed Single-Precision Mask", "summary": "Extracts sign bits from four floats into low 4 bits of register.", "syntax": "MOVMSKPS r32, xmm", "encoding": {"format": "SSE", "hex_opcode": "NP 0F 50 /r", "length": "3", "visual_parts": [], "binary_pattern": "0F | 50", "bit_positions": "+0 | +1"}, "operands": [{"name": "dest", "desc": "Reg"}, {"name": "src", "desc": "XMM"}], "extension": "SSE", "description": "Extracts the sign bit (bit 31) from each of four packed single-precision floating-point values in an XMM register and packs them into the low 4 bits of a general-purpose 32-bit register. The upper 28 bits of the destination are cleared. No flags are modified.", "pseudocode": "dest ← 0; dest[0] ← src[31]; dest[1] ← src[63]; dest[2] ← src[95]; dest[3] ← src[127];", "example": "MOVMSKPS eax, xmm0"} {"mnemonic": "movmskpd", "architecture": "x86", "full_name": "Extract Packed Double-Precision Mask", "summary": "Extracts sign bits from two doubles into low 2 bits of register.", "syntax": "MOVMSKPD r32, xmm", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 50", "length": "4", "visual_parts": [], "binary_pattern": "66 | 0F | 50", "bit_positions": "+0 | +1 | +2"}, "operands": [{"name": "dest", "desc": "Reg"}, {"name": "src", "desc": "XMM"}], "extension": "SSE2", "description": "Extracts the sign bit (bit 63) from each of two packed double-precision floating-point values in an XMM register and packs them into the low 2 bits of a general-purpose 32-bit register. The upper 30 bits of the destination are cleared. No flags are modified.", "pseudocode": "dest ← 0; dest[0] ← src[63]; dest[1] ← src[127];", "example": "MOVMSKPD eax, xmm0"} {"mnemonic": "comiss", "architecture": "x86", "full_name": "Compare Scalar Ordered Single-Precision", "summary": "Compares low float and sets EFLAGS (Signaling NaN raises exception).", "syntax": "COMISS xmm1, xmm2/m32", "encoding": {"format": "SSE", "hex_opcode": "NP 0F 2F /r", "length": "3+", "visual_parts": [], "binary_pattern": "0F | 2F", "bit_positions": "+0 | +1"}, "operands": [{"name": "src1", "desc": "XMM"}, {"name": "src2", "desc": "XMM/Mem"}], "extension": "SSE", "description": "Performs an ordered comparison of the low single-precision floating-point values in two XMM registers or memory, setting EFLAGS (ZF, PF, CF) accordingly. Signals invalid operation exception if either operand is a signaling NaN; quiet NaNs set ZF=1, PF=1, CF=1. Does not modify the XMM registers.", "pseudocode": "src1_val ← src1[0:31] (as float); src2_val ← src2[0:31] (as float); if (IsNaN(src1_val) || IsNaN(src2_val)) { ZF ← 1; PF ← 1; CF ← 1; OF ← 0; AF ← 0; SF ← 0; } else if (src1_val < src2_val) { CF ← 1; ZF ← 0; PF ← 0; OF ← 0; AF ← 0; SF ← 0; } else if (src1_val == src2_val) { ZF ← 1; CF ← 0; PF ← 0; OF ← 0; AF ← 0; SF ← 0; } else { ZF ← 0; CF ← 0; PF ← 0; OF ← 0; AF ← 0; SF ← 0; }", "example": "COMISS xmm1, xmm2/m32"} {"mnemonic": "comisd", "architecture": "x86", "full_name": "Compare Scalar Ordered Double-Precision", "summary": "Compares low double and sets EFLAGS (Signaling NaN raises exception).", "syntax": "COMISD xmm1, xmm2/m64", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 2F", "length": "4+", "visual_parts": [], "binary_pattern": "66 | 0F | 2F", "bit_positions": "+0 | +1 | +2"}, "operands": [{"name": "src1", "desc": "XMM"}, {"name": "src2", "desc": "XMM/Mem"}], "extension": "SSE2", "description": "Performs an ordered comparison of the low double-precision floating-point values in two XMM registers or memory, setting EFLAGS (ZF, PF, CF) accordingly. Signals invalid operation exception if either operand is a signaling NaN; quiet NaNs set ZF=1, PF=1, CF=1. Does not modify the XMM registers.", "pseudocode": "src1_val ← src1[0:63] (as double); src2_val ← src2[0:63] (as double); if (IsNaN(src1_val) || IsNaN(src2_val)) { ZF ← 1; PF ← 1; CF ← 1; OF ← 0; AF ← 0; SF ← 0; } else if (src1_val < src2_val) { CF ← 1; ZF ← 0; PF ← 0; OF ← 0; AF ← 0; SF ← 0; } else if (src1_val == src2_val) { ZF ← 1; CF ← 0; PF ← 0; OF ← 0; AF ← 0; SF ← 0; } else { ZF ← 0; CF ← 0; PF ← 0; OF ← 0; AF ← 0; SF ← 0; }", "example": "COMISD xmm1, xmm2/m64"} {"mnemonic": "unpcklpd", "architecture": "x86", "full_name": "Unpack Low Packed Double-Precision", "summary": "Interleaves low doubles from two sources.", "syntax": "UNPCKLPD xmm1, xmm2/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 14", "length": "4+", "visual_parts": [], "binary_pattern": "66 | 0F | 14", "bit_positions": "+0 | +1 | +2"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSE2", "description": "Unpacks and interleaves the low-order 64-bit double-precision values from the destination and source XMM registers, placing the result back in the destination. Destination element 0 receives the low double from dest, element 1 receives the low double from src. No flags are modified.", "pseudocode": "temp ← dest; dest[0:63] ← temp[0:63]; dest[64:127] ← src[0:63];", "example": "UNPCKLPD xmm1, xmm2/m128"} {"mnemonic": "unpckhpd", "architecture": "x86", "full_name": "Unpack High Packed Double-Precision", "summary": "Interleaves high doubles from two sources.", "syntax": "UNPCKHPD xmm1, xmm2/m128", "encoding": {"format": "SSE2", "hex_opcode": "66 0F 15", "length": "4+", "visual_parts": [], "binary_pattern": "66 | 0F | 15", "bit_positions": "+0 | +1 | +2"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSE2", "description": "Unpacks and interleaves the high-order 64-bit double-precision values from the destination and source XMM registers, placing the result back in the destination. Destination element 0 receives the high double from dest, element 1 receives the high double from src. No flags are modified.", "pseudocode": "temp ← dest; dest[0:63] ← temp[64:127]; dest[64:127] ← src[64:127];", "example": "UNPCKHPD xmm1, xmm2/m128"} {"mnemonic": "movshdup", "architecture": "x86", "full_name": "Move Packed Single-FP High and Duplicate", "summary": "Duplicates high element of each qword pair.", "syntax": "MOVSHDUP xmm1, xmm2/m128", "encoding": {"format": "SSE3", "hex_opcode": "F3 0F 16", "length": "4+", "visual_parts": [], "binary_pattern": "F3 | 0F | 16", "bit_positions": "+0 | +1 | +2"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSE3", "description": "Moves and duplicates the high 32-bit single-precision FP value from each 64-bit pair in the source to both elements of the corresponding pair in the destination. This SSE3 instruction operates on 128-bit XMM registers and does not modify flags. It is used for efficient duplication of high elements in packed FP data.", "pseudocode": "dest[127:96] ← src[127:96];\ndest[95:64] ← src[127:96];\ndest[63:32] ← src[63:32];\ndest[31:0] ← src[63:32];", "example": "MOVSHDUP xmm1, xmm2/m128"} {"mnemonic": "movsldup", "architecture": "x86", "full_name": "Move Packed Single-FP Low and Duplicate", "summary": "Duplicates low element of each qword pair.", "syntax": "MOVSLDUP xmm1, xmm2/m128", "encoding": {"format": "SSE3", "hex_opcode": "F3 0F 12", "length": "4+", "visual_parts": [], "binary_pattern": "F3 | 0F | 12", "bit_positions": "+0 | +1 | +2"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSE3", "description": "Moves and duplicates the low 32-bit single-precision FP value from each 64-bit pair in the source to both elements of the corresponding pair in the destination. This SSE3 instruction operates on 128-bit XMM registers and does not modify flags. It is the complement to MOVSHDUP, duplicating low rather than high elements.", "pseudocode": "dest[127:96] ← src[95:64];\ndest[95:64] ← src[95:64];\ndest[63:32] ← src[31:0];\ndest[31:0] ← src[31:0];", "example": "MOVSLDUP xmm1, xmm2/m128"} {"mnemonic": "phsubw", "architecture": "x86", "full_name": "Packed Horizontal Subtract Word", "summary": "Subtracts adjacent 16-bit integers horizontally.", "syntax": "PHSUBW xmm1, xmm2/m128", "encoding": {"format": "SSSE3", "hex_opcode": "66 0F 38 05", "length": "5+", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 05", "bit_positions": "+0 | +1 | +2 | +3"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSSE3", "description": "Subtracts horizontally adjacent 16-bit signed integers within each 128-bit operand, producing 16-bit results. This SSSE3 instruction performs eight parallel subtractions (higher element minus lower element in each pair) and does not modify EFLAGS. Results that overflow wrap with two's-complement semantics.", "pseudocode": "dest[15:0] ← (int16_t)src[31:16] - (int16_t)src[15:0];\ndest[31:16] ← (int16_t)src[63:48] - (int16_t)src[47:32];\ndest[47:32] ← (int16_t)src[95:80] - (int16_t)src[79:64];\ndest[63:48] ← (int16_t)src[127:112] - (int16_t)src[111:96];", "example": "PHSUBW xmm1, xmm2/m128"} {"mnemonic": "phsubd", "architecture": "x86", "full_name": "Packed Horizontal Subtract Doubleword", "summary": "Subtracts adjacent 32-bit integers horizontally.", "syntax": "PHSUBD xmm1, xmm2/m128", "encoding": {"format": "SSSE3", "hex_opcode": "66 0F 38 06", "length": "5+", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 06", "bit_positions": "+0 | +1 | +2 | +3"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSSE3", "description": "Subtracts horizontally adjacent 32-bit signed integers within each 128-bit operand, producing 32-bit results. This SSSE3 instruction performs four parallel subtractions (higher element minus lower element in each pair) and does not modify EFLAGS. Results wrap with two's-complement semantics on overflow.", "pseudocode": "dest[31:0] ← (int32_t)src[63:32] - (int32_t)src[31:0];\ndest[63:32] ← (int32_t)src[127:96] - (int32_t)src[95:64];", "example": "PHSUBD xmm1, xmm2/m128"} {"mnemonic": "pmaddubsw", "architecture": "x86", "full_name": "Multiply and Add Packed Signed and Unsigned Bytes", "summary": "Multiplies signed/unsigned bytes and adds pairs to words.", "syntax": "PMADDUBSW xmm1, xmm2/m128", "encoding": {"format": "SSSE3", "hex_opcode": "66 0F 38 04", "length": "5+", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 04", "bit_positions": "+0 | +1 | +2 | +3"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSSE3", "description": "Multiplies unsigned bytes from the destination by signed bytes from the source, then adds the products pairwise to produce signed 16-bit results with saturation. This SSSE3 instruction performs eight parallel multiply-add operations on byte pairs and does not modify EFLAGS. Results are clamped to the signed 16-bit range [-32768, 32767].", "pseudocode": "for i = 0 to 7:\n prod0 ← (uint8_t)dest[8*i+7:8*i] × (int8_t)src[8*i+7:8*i];\n prod1 ← (uint8_t)dest[8*i+15:8*i+8] × (int8_t)src[8*i+15:8*i+8];\n sum ← (int32_t)prod0 + (int32_t)prod1;\n dest[16*i+15:16*i] ← saturate_to_i16(sum);", "example": "PMADDUBSW xmm1, xmm2/m128"} {"mnemonic": "phminposuw", "architecture": "x86", "full_name": "Packed Horizontal Minimum", "summary": "Finds minimum word and its index.", "syntax": "PHMINPOSUW xmm1, xmm2/m128", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 38 41", "length": "5+", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 41", "bit_positions": "+0 | +1 | +2 | +3"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSE4.1", "description": "Finds the minimum unsigned 16-bit word among eight packed values and returns the minimum value in the low word of the destination with its index (0-7) in bits 16-18. This SSE4.1 instruction clears bits 19-127 of the destination and does not modify EFLAGS. It is useful for finding the position of minimum values in packed word arrays.", "pseudocode": "min_val ← src[15:0];\nmin_idx ← 0;\nfor i = 1 to 7:\n if (uint16_t)src[16*i+15:16*i] < min_val:\n min_val ← (uint16_t)src[16*i+15:16*i];\n min_idx ← i;\ndest[15:0] ← min_val;\ndest[18:16] ← min_idx;\ndest[127:19] ← 0;", "example": "PHMINPOSUW xmm1, xmm2/m128"} {"mnemonic": "mpsadbw", "architecture": "x86", "full_name": "Compute Multiple Sums of Absolute Differences", "summary": "Computes multiple SADs of byte blocks.", "syntax": "MPSADBW xmm1, xmm2/m128, imm8", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 3A 42", "length": "6+", "visual_parts": [], "binary_pattern": "66 | 0F | 3A | 42", "bit_positions": "+0 | +1 | +2 | +3"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}, {"name": "sel", "desc": "Imm"}], "extension": "SSE4.1", "description": "Computes multiple sums of absolute differences between corresponding bytes of two blocks selected by an immediate operand. This SSE4.1 instruction computes four parallel SADs, each summing the absolute differences across a byte block, and produces four 16-bit results. EFLAGS is not modified.", "pseudocode": "offset_dest ← (sel & 0x4) ? 4 : 0;\noffset_src ← (sel & 0x3) ? 4 * (sel & 0x3) : 0;\nfor k = 0 to 3:\n sum ← 0;\n for j = 0 to 3:\n idx_d ← offset_dest + 8*k + 8*j;\n idx_s ← offset_src + 8*j;\n sum ← sum + |dest[idx_d+7:idx_d] - src[idx_s+7:idx_s]|;\n dest[16*k+15:16*k] ← sum;", "example": "MPSADBW xmm1, xmm2/m128, 3"} {"mnemonic": "pmovsxbq", "architecture": "x86", "full_name": "Packed Move with Sign Extend Byte to Quadword", "summary": "Sign extends 8-bit integers to 64-bit.", "syntax": "PMOVSXBQ xmm1, xmm2/m16", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 38 22", "length": "5+", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 22", "bit_positions": "+0 | +1 | +2 | +3"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSE4.1", "description": "Sign-extends the low four bytes of the source to four 64-bit signed integers in the destination. This SSE4.1 instruction operates on 128-bit XMM registers and does not modify EFLAGS. The source may be a 16-bit memory operand or an XMM register; destination bits are filled with the sign bit of each source byte.", "pseudocode": "dest[63:0] ← sign_extend_64((int8_t)src[7:0]);\ndest[127:64] ← sign_extend_64((int8_t)src[15:8]);", "example": "PMOVSXBQ xmm1, xmm2/m16"} {"mnemonic": "pmovsxwd", "architecture": "x86", "full_name": "Packed Move with Sign Extend Word to Doubleword", "summary": "Sign extends 16-bit integers to 32-bit.", "syntax": "PMOVSXWD xmm1, xmm2/m64", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 38 23", "length": "5+", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 23", "bit_positions": "+0 | +1 | +2 | +3"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSE4.1", "description": "Sign-extends four packed 16-bit signed integers from the source operand to four packed 32-bit signed integers in the destination XMM register. The source is a 64-bit value (lower 64 bits of XMM or 64-bit memory location) containing four 16-bit elements; the destination is an 128-bit XMM register. No flags are affected.", "pseudocode": "xmm1[31:0] ← sign_extend_32(src[15:0]); xmm1[63:32] ← sign_extend_32(src[31:16]); xmm1[95:64] ← sign_extend_32(src[47:32]); xmm1[127:96] ← sign_extend_32(src[63:48]);", "example": "PMOVSXWD xmm1, xmm2/m64"} {"mnemonic": "pmovsxwq", "architecture": "x86", "full_name": "Packed Move with Sign Extend Word to Quadword", "summary": "Sign extends 16-bit integers to 64-bit.", "syntax": "PMOVSXWQ xmm1, xmm2/m32", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 38 24", "length": "5+", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 24", "bit_positions": "+0 | +1 | +2 | +3"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSE4.1", "description": "Sign-extends two packed 16-bit signed integers from the source operand to two packed 64-bit signed integers in the destination XMM register. The source is a 32-bit value (lower 32 bits of XMM or 32-bit memory location) containing two 16-bit elements; the destination is an 128-bit XMM register. No flags are affected.", "pseudocode": "xmm1[63:0] ← sign_extend_64(src[15:0]); xmm1[127:64] ← sign_extend_64(src[31:16]);", "example": "PMOVSXWQ xmm1, xmm2/m32"} {"mnemonic": "pmovsxdq", "architecture": "x86", "full_name": "Packed Move with Sign Extend Doubleword to Quadword", "summary": "Sign extends 32-bit integers to 64-bit.", "syntax": "PMOVSXDQ xmm1, xmm2/m64", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 38 25", "length": "5+", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 25", "bit_positions": "+0 | +1 | +2 | +3"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSE4.1", "description": "Sign-extends two packed 32-bit signed integers from the source operand to two packed 64-bit signed integers in the destination XMM register. The source is a 64-bit value (lower 64 bits of XMM or 64-bit memory location) containing two 32-bit elements; the destination is an 128-bit XMM register. No flags are affected.", "pseudocode": "xmm1[63:0] ← sign_extend_64(src[31:0]); xmm1[127:64] ← sign_extend_64(src[63:32]);", "example": "PMOVSXDQ xmm1, xmm2/m64"} {"mnemonic": "pmovzxbd", "architecture": "x86", "full_name": "Packed Move with Zero Extend Byte to Doubleword", "summary": "Zero extends 8-bit integers to 32-bit.", "syntax": "PMOVZXBD xmm1, xmm2/m32", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 38 31", "length": "5+", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 31", "bit_positions": "+0 | +1 | +2 | +3"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSE4.1", "description": "Zero-extends four packed 8-bit unsigned integers from the source operand to four packed 32-bit unsigned integers in the destination XMM register. The source is a 32-bit value (lower 32 bits of XMM or 32-bit memory location) containing four 8-bit elements; the destination is an 128-bit XMM register. No flags are affected.", "pseudocode": "xmm1[31:0] ← zero_extend_32(src[7:0]); xmm1[63:32] ← zero_extend_32(src[15:8]); xmm1[95:64] ← zero_extend_32(src[23:16]); xmm1[127:96] ← zero_extend_32(src[31:24]);", "example": "PMOVZXBD xmm1, xmm2/m32"} {"mnemonic": "pmovzxbq", "architecture": "x86", "full_name": "Packed Move with Zero Extend Byte to Quadword", "summary": "Zero extends 8-bit integers to 64-bit.", "syntax": "PMOVZXBQ xmm1, xmm2/m16", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 38 32", "length": "5+", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 32", "bit_positions": "+0 | +1 | +2 | +3"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSE4.1", "description": "Zero-extends two packed 8-bit unsigned integers from the source operand to two packed 64-bit unsigned integers in the destination XMM register. The source is a 16-bit value (lower 16 bits of XMM or 16-bit memory location) containing two 8-bit elements; the destination is an 128-bit XMM register. No flags are affected.", "pseudocode": "xmm1[63:0] ← zero_extend_64(src[7:0]); xmm1[127:64] ← zero_extend_64(src[15:8]);", "example": "PMOVZXBQ xmm1, xmm2/m16"} {"mnemonic": "pmovzxwd", "architecture": "x86", "full_name": "Packed Move with Zero Extend Word to Doubleword", "summary": "Zero extends 16-bit integers to 32-bit.", "syntax": "PMOVZXWD xmm1, xmm2/m64", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 38 33", "length": "5+", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 33", "bit_positions": "+0 | +1 | +2 | +3"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSE4.1", "description": "Zero-extends four packed 16-bit unsigned integers from the source operand to four packed 32-bit unsigned integers in the destination XMM register. The source is a 64-bit value (lower 64 bits of XMM or 64-bit memory location) containing four 16-bit elements; the destination is an 128-bit XMM register. No flags are affected.", "pseudocode": "xmm1[31:0] ← zero_extend_32(src[15:0]); xmm1[63:32] ← zero_extend_32(src[31:16]); xmm1[95:64] ← zero_extend_32(src[47:32]); xmm1[127:96] ← zero_extend_32(src[63:48]);", "example": "PMOVZXWD xmm1, xmm2/m64"} {"mnemonic": "pmovzxwq", "architecture": "x86", "full_name": "Packed Move with Zero Extend Word to Quadword", "summary": "Zero extends 16-bit integers to 64-bit.", "syntax": "PMOVZXWQ xmm1, xmm2/m32", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 38 34", "length": "5+", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 34", "bit_positions": "+0 | +1 | +2 | +3"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSE4.1", "description": "Zero-extends two packed 16-bit unsigned integers from the source operand to two packed 64-bit unsigned integers in the destination XMM register. The source is a 32-bit value (lower 32 bits of XMM or 32-bit memory location) containing two 16-bit elements; the destination is an 128-bit XMM register. No flags are affected.", "pseudocode": "xmm1[63:0] ← zero_extend_64(src[15:0]); xmm1[127:64] ← zero_extend_64(src[31:16]);", "example": "PMOVZXWQ xmm1, xmm2/m32"} {"mnemonic": "pmovzxdq", "architecture": "x86", "full_name": "Packed Move with Zero Extend Doubleword to Quadword", "summary": "Zero extends 32-bit integers to 64-bit.", "syntax": "PMOVZXDQ xmm1, xmm2/m64", "encoding": {"format": "SSE4.1", "hex_opcode": "66 0F 38 35", "length": "5+", "visual_parts": [], "binary_pattern": "66 | 0F | 38 | 35", "bit_positions": "+0 | +1 | +2 | +3"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "SSE4.1", "description": "Zero-extends two packed 32-bit unsigned integers from the source operand to two packed 64-bit unsigned integers in the destination XMM register. The source is a 64-bit value (lower 64 bits of XMM or 64-bit memory location) containing two 32-bit elements; the destination is an 128-bit XMM register. No flags are affected.", "pseudocode": "xmm1[63:0] ← zero_extend_64(src[31:0]); xmm1[127:64] ← zero_extend_64(src[63:32]);", "example": "PMOVZXDQ xmm1, xmm2/m64"} {"mnemonic": "vbroadcastsd", "architecture": "x86", "full_name": "Broadcast Scalar Double", "summary": "Broadcasts a double to all elements of YMM.", "syntax": "VBROADCASTSD ymm1, m64", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F38.W0 19 /r", "length": "5+", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "operands": [{"name": "dest", "desc": "Destination YMM register; all four 64-bit lanes receive the value"}, {"name": "src", "desc": "64-bit memory location holding the double-precision value to broadcast"}], "extension": "AVX2", "description": "Broadcasts a 64-bit double-precision floating-point value from memory to all four 64-bit elements of a 256-bit YMM register. This is a non-temporal data movement that replicates a single FP64 value across the entire YMM destination. No flags are affected.", "pseudocode": "ymm1[63:0] ← m64\nymm1[127:64] ← m64\nymm1[191:128] ← m64\nymm1[255:192] ← m64", "example": "VBROADCASTSD ymm1, [rbp-8]"} {"mnemonic": "vbroadcastf128", "architecture": "x86", "full_name": "Broadcast 128-bit Floating-Point", "summary": "Broadcasts 128-bit FP block to YMM.", "syntax": "VBROADCASTF128 ymm1, m128", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F38.W0 1A /r", "length": "5+", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "operands": [{"name": "dest", "desc": "YMM"}, {"name": "src", "desc": "Memory"}], "extension": "AVX", "description": "Broadcasts a 128-bit floating-point block from memory to both 128-bit halves of a 256-bit YMM register, replicating the 16-byte XMM-sized value twice. This instruction operates on floating-point data and does not affect any flags. Available in AVX mode and higher.", "pseudocode": "ymm1[127:0] ← m128\nymm1[255:128] ← m128", "example": "VBROADCASTF128 ymm1, [rbp-16]"} {"mnemonic": "vbroadcasti128", "architecture": "x86", "full_name": "Broadcast 128-bit Integer", "summary": "Broadcasts 128-bit integer block to YMM.", "syntax": "VBROADCASTI128 ymm1, m128", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F38.W0 5A /r", "length": "5+", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "operands": [{"name": "dest", "desc": "YMM"}, {"name": "src", "desc": "Memory"}], "extension": "AVX2", "description": "Broadcasts a 128-bit integer block from memory to both 128-bit halves of a 256-bit YMM register, replicating the 16-byte value as integer data. This is the integer-domain equivalent of VBROADCASTF128 and does not affect any CPU flags.", "pseudocode": "ymm1[127:0] ← m128\nymm1[255:128] ← m128", "example": "VBROADCASTI128 ymm1, [rbp-16]"} {"mnemonic": "vpbroadcastw", "architecture": "x86", "full_name": "Broadcast Word", "summary": "Broadcasts a word to all elements of YMM.", "syntax": "VPBROADCASTW ymm1, xmm2/m16", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F38.W0 79 /r", "length": "5+", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "operands": [{"name": "dest", "desc": "YMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "AVX2", "description": "Broadcasts a 16-bit word value from either an XMM register or memory to all 16-bit elements of a YMM register (16 copies total). The source operand can be a 16-bit memory location or the low word of an XMM register. No flags are modified.", "pseudocode": "val ← (src[15:0])\nfor i ← 0 to 15 do\n ymm1[i*16+15:i*16] ← val\nend for", "example": "VPBROADCASTW ymm1, xmm2/m16"} {"mnemonic": "vpbroadcastq", "architecture": "x86", "full_name": "Broadcast Quadword", "summary": "Broadcasts a quadword to all elements of YMM.", "syntax": "VPBROADCASTQ ymm1, xmm2/m64", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F38.W0 59 /r", "length": "5+", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "operands": [{"name": "dest", "desc": "YMM"}, {"name": "src", "desc": "XMM/Mem"}], "extension": "AVX2", "description": "Broadcasts a 64-bit quadword value from either an XMM register or memory to all 64-bit elements of a YMM register (four copies total). The source can be a 64-bit memory location or the low quadword of an XMM register. No flags are affected.", "pseudocode": "val ← (src[63:0])\nfor i ← 0 to 3 do\n ymm1[i*64+63:i*64] ← val\nend for", "example": "VPBROADCASTQ ymm1, xmm2/m64"} {"mnemonic": "vmaskmovps", "architecture": "x86", "full_name": "Conditional Move Packed Single-Precision", "summary": "Conditionally loads/stores floats based on mask.", "syntax": "VMASKMOVPS ymm1, ymm2, m256", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F38.W0 2C /r", "length": "5+", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "operands": [{"name": "dest", "desc": "YMM"}, {"name": "mask", "desc": "YMM"}, {"name": "src", "desc": "Mem"}], "extension": "AVX", "description": "Conditionally loads single-precision floating-point values from memory into a YMM register based on per-element mask bits; unset mask bits leave destination elements unchanged. This is a masked memory read operation where the high bit of each 32-bit mask element controls whether the corresponding FP32 is loaded. No flags are modified.", "pseudocode": "for i ← 0 to 7 do\n if ymm2[i*32+31] == 1 then\n ymm1[i*32+31:i*32] ← [memory_address + i*4]\n end if\nend for", "example": "VMASKMOVPS ymm1, ymm2, [rbp-32]"} {"mnemonic": "vmaskmovpd", "architecture": "x86", "full_name": "Conditional Move Packed Double-Precision", "summary": "Conditionally loads/stores doubles based on mask.", "syntax": "VMASKMOVPD ymm1, ymm2, m256", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F38.W0 2D /r", "length": "5+", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "operands": [{"name": "dest", "desc": "YMM"}, {"name": "mask", "desc": "YMM"}, {"name": "src", "desc": "Mem"}], "extension": "AVX", "description": "Conditionally loads double-precision floating-point values from memory into a YMM register based on per-element mask bits; unset mask bits leave destination elements unchanged. This is the FP64 variant of VMASKMOVPS where the high bit of each 64-bit mask element controls the corresponding load. No flags are affected.", "pseudocode": "for i ← 0 to 3 do\n if ymm2[i*64+63] == 1 then\n ymm1[i*64+63:i*64] ← [memory_address + i*8]\n end if\nend for", "example": "VMASKMOVPD ymm1, ymm2, [rbp-32]"} {"mnemonic": "vpgatherdd", "architecture": "x86", "full_name": "Gather Packed Doubleword with Signed Doubleword Indices", "summary": "Gathers 32-bit integers using 32-bit indices.", "syntax": "VPGATHERDD ymm1, [base+ymm_idx*scale], ymm_mask", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F38.W0 90 /r", "length": "5+", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "operands": [{"name": "dest", "desc": "YMM"}, {"name": "mem", "desc": "Base+Idx"}, {"name": "mask", "desc": "YMM"}], "extension": "AVX2", "description": "Gathers four doubleword (32-bit) integers from memory using 32-bit sign-extended indices in a YMM register, with per-element masking to conditionally perform each load. Each element of the destination YMM is loaded from [base + ymm_index[i] * scale] if the corresponding mask bit is set; mask elements are zeroed after a successful gather. This instruction serializes memory operations and sets mask elements to zero for loaded lanes.", "pseudocode": "for i ← 0 to 3 do\n if mask_ymm[i*32+31] == 1 then\n ymm1[i*32+31:i*32] ← [base + sign_extend(ymm_idx[i*32+31:i*32]) * scale]\n mask_ymm[i*32+31:i*32] ← 0\n end if\nend for", "example": "VPGATHERDD ymm1, [base+ymm_idx*scale], ymm_mask"} {"mnemonic": "vpgatherdq", "architecture": "x86", "full_name": "Gather Packed Quadword with Signed Doubleword Indices", "summary": "Gathers 64-bit integers using 32-bit indices.", "syntax": "VPGATHERDQ ymm1, [base+xmm_idx*scale], ymm_mask", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F38.W1 90 /r", "length": "5+", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "operands": [{"name": "dest", "desc": "YMM"}, {"name": "mem", "desc": "Base+Idx"}, {"name": "mask", "desc": "YMM"}], "extension": "AVX2", "description": "Gathers eight 64-bit integers from memory using four 32-bit signed indices packed in an XMM register, with scale and base address, into a YMM destination. The mask register (YMM) controls which elements are gathered; masked-out elements in the destination are zeroed. All memory access and mask updates occur in parallel, and the instruction serializes the CPU pipeline during execution.", "pseudocode": "for i in 0 to 3:\n if mask[2*i+1:2*i] == all_ones_64bit:\n addr ← base + sign_extend_32_to_64(index[i*32+31:i*32]) * scale\n dest[64*i+63:64*i] ← [addr]\n mask[64*i+63:64*i] ← all_ones_64bit\n else:\n dest[64*i+63:64*i] ← 0\n mask[64*i+63:64*i] ← 0", "example": "VPGATHERDQ ymm1, [base+xmm_idx*scale], ymm_mask"} {"mnemonic": "vpgatherqd", "architecture": "x86", "full_name": "Gather Packed Doubleword with Signed Quadword Indices", "summary": "Gathers 32-bit integers using 64-bit indices.", "syntax": "VPGATHERQD xmm1, [base+ymm_idx*scale], xmm_mask", "encoding": {"format": "VEX", "hex_opcode": "VEX.128.66.0F38.W0 91 /r", "length": "5+", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "mem", "desc": "Base+Idx"}, {"name": "mask", "desc": "XMM"}], "extension": "AVX2", "description": "Gathers four 32-bit integers from memory using four 64-bit signed indices packed in a YMM register, with scale and base address, into an XMM destination (lower half). The mask register (XMM) controls which elements are gathered; masked-out elements are zeroed and their corresponding mask bits are cleared. The instruction serializes execution and performs all memory accesses in parallel.", "pseudocode": "for i in 0 to 3:\n if mask[32*i+31:32*i] == all_ones_32bit:\n addr ← base + index[64*i+63:64*i] * scale\n dest[32*i+31:32*i] ← [addr]\n mask[32*i+31:32*i] ← all_ones_32bit\n else:\n dest[32*i+31:32*i] ← 0\n mask[32*i+31:32*i] ← 0", "example": "VPGATHERQD xmm1, [base+ymm_idx*scale], xmm_mask"} {"mnemonic": "vpgatherqq", "architecture": "x86", "full_name": "Gather Packed Quadword with Signed Quadword Indices", "summary": "Gathers 64-bit integers using 64-bit indices.", "syntax": "VPGATHERQQ ymm1, [base+ymm_idx*scale], ymm_mask", "encoding": {"format": "VEX", "hex_opcode": "VEX.256.66.0F38.W1 91 /r", "length": "5+", "visual_parts": [], "binary_pattern": "VEX | opcode | ModRM", "bit_positions": "+0 | +3 | +4"}, "operands": [{"name": "dest", "desc": "YMM"}, {"name": "mem", "desc": "Base+Idx"}, {"name": "mask", "desc": "YMM"}], "extension": "AVX2", "description": "Gathers four 64-bit integers from memory using four 64-bit signed indices packed in a YMM register, with scale and base address, into a YMM destination. The mask register (YMM) controls which elements are gathered; masked-out elements are zeroed and their corresponding mask bits are cleared. All memory accesses execute in parallel, and the instruction causes pipeline serialization.", "pseudocode": "for i in 0 to 3:\n if mask[64*i+63:64*i] == all_ones_64bit:\n addr ← base + index[64*i+63:64*i] * scale\n dest[64*i+63:64*i] ← [addr]\n mask[64*i+63:64*i] ← all_ones_64bit\n else:\n dest[64*i+63:64*i] ← 0\n mask[64*i+63:64*i] ← 0", "example": "VPGATHERQQ ymm1, [base+ymm_idx*scale], ymm_mask"} {"mnemonic": "vpabsq", "architecture": "x86", "full_name": "Packed Absolute Value Quadword", "summary": "Computes absolute value of 64-bit integers.", "syntax": "VPABSQ zmm1 {k1}, zmm2/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W1 1F /r", "length": "6+", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 1F", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "operands": [{"name": "dest", "desc": "ZMM"}, {"name": "src", "desc": "ZMM/Mem"}], "extension": "AVX-512F", "description": "Computes the absolute value of eight packed 64-bit signed integers from the source operand, storing the results in the destination ZMM register. Opmask register k1 selectively updates destination elements (merging or zeroing based on the mask mode). The operation handles the extreme case where abs(INT64_MIN) = INT64_MIN with wraparound; no overflow flags are set.", "pseudocode": "for i in 0 to 7:\n if k1[i] or not masked:\n src_val ← src[64*i+63:64*i]\n if src_val < 0:\n dest[64*i+63:64*i] ← -src_val\n else:\n dest[64*i+63:64*i] ← src_val\n else if zeroing:\n dest[64*i+63:64*i] ← 0", "example": "VPABSQ zmm1, zmm2/m512"} {"mnemonic": "vpmaxsq", "architecture": "x86", "full_name": "Maximum of Packed Signed Quadword Integers", "summary": "Returns maximum of signed 64-bit integers.", "syntax": "VPMAXSQ zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W1 3D /r", "length": "6+", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 3D", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "operands": [{"name": "dest", "desc": "ZMM"}, {"name": "src1", "desc": "ZMM"}, {"name": "src2", "desc": "ZMM/Mem"}], "extension": "AVX-512F", "description": "Computes the element-wise maximum of eight packed 64-bit signed integers from two source operands, storing results in the destination ZMM register. Opmask register k1 selectively updates destination elements. The operation compares signed values and has no effect on EFLAGS; results are computed in parallel.", "pseudocode": "for i in 0 to 7:\n if k1[i] or not masked:\n src1_val ← src1[64*i+63:64*i]\n src2_val ← src2[64*i+63:64*i]\n if src1_val >_signed src2_val:\n dest[64*i+63:64*i] ← src1_val\n else:\n dest[64*i+63:64*i] ← src2_val\n else if zeroing:\n dest[64*i+63:64*i] ← 0", "example": "VPMAXSQ zmm1, zmm2, zmm3/m512"} {"mnemonic": "vpmaxuq", "architecture": "x86", "full_name": "Maximum of Packed Unsigned Quadword Integers", "summary": "Returns maximum of unsigned 64-bit integers.", "syntax": "VPMAXUQ zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W1 3F /r", "length": "6+", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 3F", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "operands": [{"name": "dest", "desc": "ZMM"}, {"name": "src1", "desc": "ZMM"}, {"name": "src2", "desc": "ZMM/Mem"}], "extension": "AVX-512F", "description": "Computes the element-wise maximum of eight packed 64-bit unsigned integers from two source operands, storing results in the destination ZMM register. Opmask register k1 selectively updates destination elements. The operation compares unsigned values and does not affect EFLAGS; all comparisons execute in parallel.", "pseudocode": "for i in 0 to 7:\n if k1[i] or not masked:\n src1_val ← src1[64*i+63:64*i]\n src2_val ← src2[64*i+63:64*i]\n if src1_val >_unsigned src2_val:\n dest[64*i+63:64*i] ← src1_val\n else:\n dest[64*i+63:64*i] ← src2_val\n else if zeroing:\n dest[64*i+63:64*i] ← 0", "example": "VPMAXUQ zmm1, zmm2, zmm3/m512"} {"mnemonic": "vpminsq", "architecture": "x86", "full_name": "Minimum of Packed Signed Quadword Integers", "summary": "Returns minimum of signed 64-bit integers.", "syntax": "VPMINSQ zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W1 39 /r", "length": "6+", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 39", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "operands": [{"name": "dest", "desc": "ZMM"}, {"name": "src1", "desc": "ZMM"}, {"name": "src2", "desc": "ZMM/Mem"}], "extension": "AVX-512F", "description": "Computes the element-wise minimum of eight packed 64-bit signed integers from two source operands, storing results in the destination ZMM register. Opmask register k1 selectively updates destination elements. The operation compares signed values and does not modify EFLAGS; all comparisons are performed in parallel.", "pseudocode": "for i in 0 to 7:\n if k1[i] or not masked:\n src1_val ← src1[64*i+63:64*i]\n src2_val ← src2[64*i+63:64*i]\n if src1_val <_signed src2_val:\n dest[64*i+63:64*i] ← src1_val\n else:\n dest[64*i+63:64*i] ← src2_val\n else if zeroing:\n dest[64*i+63:64*i] ← 0", "example": "VPMINSQ zmm1, zmm2, zmm3/m512"} {"mnemonic": "vpminuq", "architecture": "x86", "full_name": "Minimum of Packed Unsigned Quadword Integers", "summary": "Returns minimum of unsigned 64-bit integers.", "syntax": "VPMINUQ zmm1 {k1}, zmm2, zmm3/m512", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F38.W1 3B /r", "length": "6+", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 38 | 3B", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "operands": [{"name": "dest", "desc": "ZMM"}, {"name": "src1", "desc": "ZMM"}, {"name": "src2", "desc": "ZMM/Mem"}], "extension": "AVX-512F", "description": "Computes the element-wise minimum of eight packed 64-bit unsigned integers from two source operands, storing results in the destination ZMM register. Opmask register k1 selectively updates destination elements. The operation compares unsigned values and leaves EFLAGS unchanged; all comparisons execute in parallel.", "pseudocode": "for i in 0 to 7:\n if k1[i] or not masked:\n src1_val ← src1[64*i+63:64*i]\n src2_val ← src2[64*i+63:64*i]\n if src1_val <_unsigned src2_val:\n dest[64*i+63:64*i] ← src1_val\n else:\n dest[64*i+63:64*i] ← src2_val\n else if zeroing:\n dest[64*i+63:64*i] ← 0", "example": "VPMINUQ zmm1, zmm2, zmm3/m512"} {"mnemonic": "vprolq", "architecture": "x86", "full_name": "Rotate Left Quadword", "summary": "Rotates 64-bit integers left.", "syntax": "VPROLQ zmm1 {k1}, zmm2, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F.W1 72 /1 ib", "length": "6+", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 72 | ModRM", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "operands": [{"name": "dest", "desc": "ZMM"}, {"name": "src", "desc": "ZMM"}, {"name": "count", "desc": "Imm"}], "extension": "AVX-512F", "description": "Rotates each 64-bit quadword in the source ZMM register left by an immediate count, writing the result to the destination ZMM register under write-mask control. This is a vectorized rotate-left operation with no effect on EFLAGS. Available only in 64-bit mode and requires AVX-512F support.", "pseudocode": "for i = 0 to 7:\n if k1[i]:\n zmm1[64*i : 64*i+63] ← (zmm2[64*i : 64*i+63] << count) | (zmm2[64*i : 64*i+63] >> (64 - count))\n else if zeroing:\n zmm1[64*i : 64*i+63] ← 0", "example": "VPROLQ zmm1, zmm2, 3"} {"mnemonic": "vprorq", "architecture": "x86", "full_name": "Rotate Right Quadword", "summary": "Rotates 64-bit integers right.", "syntax": "VPRORQ zmm1 {k1}, zmm2, imm8", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.66.0F.W1 72 /0 ib", "length": "6+", "visual_parts": [], "binary_pattern": "EVEX | 66 | 0F | 72 | ModRM", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "operands": [{"name": "dest", "desc": "ZMM"}, {"name": "src", "desc": "ZMM"}, {"name": "count", "desc": "Imm"}], "extension": "AVX-512F", "description": "Rotates each 64-bit quadword in the source ZMM register right by an immediate count, writing the result to the destination ZMM register under write-mask control. This is a vectorized rotate-right operation with no effect on EFLAGS. Available only in 64-bit mode and requires AVX-512F support.", "pseudocode": "for i = 0 to 7:\n if k1[i]:\n zmm1[64*i : 64*i+63] ← (zmm2[64*i : 64*i+63] >> count) | (zmm2[64*i : 64*i+63] << (64 - count))\n else if zeroing:\n zmm1[64*i : 64*i+63] ← 0", "example": "VPRORQ zmm1, zmm2, 3"} {"mnemonic": "vpmovswb", "architecture": "x86", "full_name": "Truncate Signed Word to Byte", "summary": "Down-converts 16-bit integers to 8-bit signed saturate.", "syntax": "VPMOVSWB xmm1/m128 {k1}, zmm2", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.256.F3.0F38.W0 20 /r", "length": "6+", "visual_parts": [], "binary_pattern": "EVEX | F3 | 0F | 38 | 20", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "ZMM"}], "extension": "AVX-512F", "description": "Truncates 16-bit signed words from a ZMM register to 8-bit signed bytes with saturation, storing the result in an XMM register or 128-bit memory location under write-mask control. Out-of-range values saturate to the signed byte limits (-128 to 127). No flags are affected. This instruction requires AVX-512F and operates only in 64-bit mode.", "pseudocode": "for i = 0 to 31:\n temp ← zmm2[16*i : 16*i+15]\n if temp > 127:\n xmm1[8*i : 8*i+7] ← 127 (under mask k1[i])\n else if temp < -128:\n xmm1[8*i : 8*i+7] ← -128 (under mask k1[i])\n else:\n xmm1[8*i : 8*i+7] ← temp[7:0] (under mask k1[i])\n if not k1[i] and zeroing:\n xmm1[8*i : 8*i+7] ← 0", "example": "VPMOVSWB xmm1/m128, zmm2"} {"mnemonic": "vpmovsqb", "architecture": "x86", "full_name": "Truncate Signed Quadword to Byte", "summary": "Down-converts 64-bit integers to 8-bit signed saturate.", "syntax": "VPMOVSQB xmm1/m128 {k1}, zmm2", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.512.F3.0F38.W0 22 /r", "length": "6+", "visual_parts": [], "binary_pattern": "EVEX | F3 | 0F | 38 | 22", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "ZMM"}], "extension": "AVX-512F", "description": "Truncates 64-bit signed quadwords from a ZMM register to 8-bit signed bytes with saturation, storing the result in an XMM register or 128-bit memory location under write-mask control. Out-of-range values saturate to signed byte limits (-128 to 127). No flags are affected. This instruction requires AVX-512F and operates only in 64-bit mode.", "pseudocode": "for i = 0 to 7:\n temp ← zmm2[64*i : 64*i+63]\n if temp > 127:\n xmm1[8*i : 8*i+7] ← 127 (under mask k1[i])\n else if temp < -128:\n xmm1[8*i : 8*i+7] ← -128 (under mask k1[i])\n else:\n xmm1[8*i : 8*i+7] ← temp[7:0] (under mask k1[i])\n if not k1[i] and zeroing:\n xmm1[8*i : 8*i+7] ← 0", "example": "VPMOVSQB xmm1/m128, zmm2"} {"mnemonic": "vpmovuswb", "architecture": "x86", "full_name": "Truncate Unsigned Word to Byte", "summary": "Down-converts 16-bit integers to 8-bit unsigned saturate.", "syntax": "VPMOVUSWB xmm1/m128 {k1}, zmm2", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.256.F3.0F38.W0 10 /r", "length": "6+", "visual_parts": [], "binary_pattern": "EVEX | F3 | 0F | 38 | 10", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "ZMM"}], "extension": "AVX-512F", "description": "Truncates 16-bit unsigned words from a ZMM register to 8-bit unsigned bytes with saturation, storing the result in an XMM register or 128-bit memory location under write-mask control. Out-of-range values saturate to the unsigned byte limit (0 to 255). No flags are affected. This instruction requires AVX-512F and operates only in 64-bit mode.", "pseudocode": "for i = 0 to 31:\n temp ← zmm2[16*i : 16*i+15]\n if temp > 255:\n xmm1[8*i : 8*i+7] ← 255 (under mask k1[i])\n else:\n xmm1[8*i : 8*i+7] ← temp[7:0] (under mask k1[i])\n if not k1[i] and zeroing:\n xmm1[8*i : 8*i+7] ← 0", "example": "VPMOVUSWB xmm1/m128, zmm2"} {"mnemonic": "vpmovusqb", "architecture": "x86", "full_name": "Truncate Unsigned Quadword to Byte", "summary": "Down-converts 64-bit integers to 8-bit unsigned saturate.", "syntax": "VPMOVUSQB xmm1/m128 {k1}, zmm2", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.128.F3.0F38.W0 12 /r", "length": "6+", "visual_parts": [], "binary_pattern": "EVEX | F3 | 0F | 38 | 12", "bit_positions": "+0 | +4 | +5 | +6 | +7"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src", "desc": "ZMM"}], "extension": "AVX-512F", "description": "Truncates 64-bit unsigned quadwords from a ZMM register to 8-bit unsigned bytes with saturation, storing the result in an XMM register or 128-bit memory location under write-mask control. Out-of-range values saturate to the unsigned byte limit (0 to 255). No flags are affected. This instruction requires AVX-512F and operates only in 64-bit mode.", "pseudocode": "for i = 0 to 7:\n temp ← zmm2[64*i : 64*i+63]\n if temp > 255:\n xmm1[8*i : 8*i+7] ← 255 (under mask k1[i])\n else:\n xmm1[8*i : 8*i+7] ← temp[7:0] (under mask k1[i])\n if not k1[i] and zeroing:\n xmm1[8*i : 8*i+7] ← 0", "example": "VPMOVUSQB xmm1/m128, zmm2"} {"mnemonic": "kaddw", "architecture": "x86", "full_name": "Add Masks Word", "summary": "Adds two 16-bit mask registers.", "syntax": "KADDW k1, k2, k3", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L1.0F.W0 4A /r", "length": "3+", "visual_parts": [], "binary_pattern": "EVEX | 0F | 4A", "bit_positions": "+0 | +4 | +5"}, "operands": [{"name": "dest", "desc": "k-reg"}, {"name": "src1", "desc": "k-reg"}, {"name": "src2", "desc": "k-reg"}], "extension": "AVX-512DQ", "description": "Adds two 16-bit mask registers and stores the result in a third 16-bit mask register, with write-mask control applied. The addition is performed on the full 16-bit width of each mask operand; no carry is defined beyond bit 15. No EFLAGS are modified. This instruction requires AVX-512DQ and operates only in 64-bit mode.", "pseudocode": "k1 ← (k2 + k3)[15:0]", "example": "KADDW k1, k2, k3"} {"mnemonic": "kaddb", "architecture": "x86", "full_name": "Add Masks Byte", "summary": "Adds two 8-bit mask registers.", "syntax": "KADDB k1, k2, k3", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L1.66.0F.W0 4A /r", "length": "3+", "visual_parts": [], "binary_pattern": "EVEX | 0F | 4A", "bit_positions": "+0 | +4 | +5"}, "operands": [{"name": "dest", "desc": "k-reg"}, {"name": "src1", "desc": "k-reg"}, {"name": "src2", "desc": "k-reg"}], "extension": "AVX-512DQ", "description": "Adds two 8-bit mask registers and stores the result in a third 8-bit mask register, with write-mask control applied. The addition is performed on the full 8-bit width of each mask operand; no carry is defined beyond bit 7. No EFLAGS are modified. This instruction requires AVX-512DQ and operates only in 64-bit mode.", "pseudocode": "k1 ← (k2 + k3)[7:0]", "example": "KADDB k1, k2, k3"} {"mnemonic": "kunpckbw", "architecture": "x86", "full_name": "Unpack and Interleave Masks Byte to Word", "summary": "Interleaves 8-bit masks into 16-bit mask.", "syntax": "KUNPCKBW k1, k2, k3", "encoding": {"format": "EVEX", "hex_opcode": "VEX.L1.66.0F.W0 4B /r", "length": "3+", "visual_parts": [], "binary_pattern": "EVEX | 0F | 4B", "bit_positions": "+0 | +4 | +5"}, "operands": [{"name": "dest", "desc": "k-reg"}, {"name": "src1", "desc": "k-reg"}, {"name": "src2", "desc": "k-reg"}], "extension": "AVX-512", "description": "Unpacks and interleaves two 8-bit mask register values into a 16-bit mask register. The operation treats the 8-bit sources as packed bit fields and expands them with interleaving to produce a 16-bit result. No flags are affected by this operation.", "pseudocode": "k1[15:8] ← k3[7:0]\nk1[7:0] ← k2[7:0]", "example": "KUNPCKBW k1, k2, k3"} {"mnemonic": "vaddss", "architecture": "x86", "full_name": "Add Scalar Single-Precision (EVEX)", "summary": "Adds scalar single precision (EVEX encoded with masking).", "syntax": "VADDSS xmm1 {k1}, xmm2, xmm3/m32", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.LLIG.F3.0F.W0 58 /r", "length": "6+", "visual_parts": [], "binary_pattern": "EVEX | 58", "bit_positions": "+0 | +4"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src1", "desc": "XMM"}, {"name": "src2", "desc": "XMM/Mem"}], "extension": "AVX-512F", "description": "Adds the low 32-bit single-precision floating-point operands of xmm2 and xmm3/m32, stores the result in xmm1, and leaves bits 127:32 of xmm1 unchanged. Supports EVEX encoding with optional write-mask (k1) and zeroing behavior. No integer flags are affected.", "pseudocode": "xmm1[31:0] ← xmm2[31:0] + xmm3/m32[31:0]\nxmm1[127:32] ← (k1 is used) ? (zeroing ? 0 : xmm1[127:32]) : xmm1[127:32]", "example": "VADDSS xmm1, xmm2, xmm3/m32"} {"mnemonic": "vmulss", "architecture": "x86", "full_name": "Multiply Scalar Single-Precision (EVEX)", "summary": "Multiplies scalar single precision (EVEX encoded with masking).", "syntax": "VMULSS xmm1 {k1}, xmm2, xmm3/m32", "encoding": {"format": "EVEX", "hex_opcode": "EVEX.LLIG.F3.0F.W0 59 /r", "length": "6+", "visual_parts": [], "binary_pattern": "EVEX | 59", "bit_positions": "+0 | +4"}, "operands": [{"name": "dest", "desc": "XMM"}, {"name": "src1", "desc": "XMM"}, {"name": "src2", "desc": "XMM/Mem"}], "extension": "AVX-512F", "description": "Multiplies the low 32-bit single-precision floating-point operands of xmm2 and xmm3/m32, stores the result in xmm1, and leaves bits 127:32 of xmm1 unchanged. Supports EVEX encoding with optional write-mask (k1) and zeroing behavior. No integer flags are affected.", "pseudocode": "xmm1[31:0] ← xmm2[31:0] * xmm3/m32[31:0]\nxmm1[127:32] ← (k1 is used) ? (zeroing ? 0 : xmm1[127:32]) : xmm1[127:32]", "example": "VMULSS xmm1, xmm2, xmm3/m32"} {"mnemonic": "xsaveopt", "architecture": "x86", "full_name": "Save Processor Extended States Optimized", "summary": "Saves state components (optimized for Modified state).", "syntax": "XSAVEOPT m", "encoding": {"format": "Legacy", "hex_opcode": "NP 0F AE /6", "length": "3+", "visual_parts": [], "binary_pattern": "0F | AE | ModRM", "bit_positions": "+0 | +1 | +2"}, "operands": [{"name": "dest", "desc": "Memory"}], "extension": "XSAVEOPT", "description": "Saves processor extended state components (FPU, SSE, AVX, etc.) to the memory location specified by EDX:EAX, using an optimized algorithm that tracks which state components have been modified. Requires XSAVEOPT feature support (CPUID EAX=0DH:EAX bit 0). No flags are modified; this instruction serializes execution and may cause VM exits in virtualized environments.", "pseudocode": "mem[EDX:EAX] ← XSTATE_COMPONENTS_PER_XCRF_BITMASK(ECX)\nXSTATE_HEADER[EDX:EAX + 512] ← MODIFIED_STATE_TRACKING", "example": "XSAVEOPT [rbp-8]"} {"mnemonic": "xsavec", "architecture": "x86", "full_name": "Save Processor Extended States with Compaction", "summary": "Saves state components using compaction.", "syntax": "XSAVEC m", "encoding": {"format": "Legacy", "hex_opcode": "NP 0F C7 /4", "length": "3+", "visual_parts": [], "binary_pattern": "0F | C7 | ModRM", "bit_positions": "+0 | +1 | +2"}, "operands": [{"name": "dest", "desc": "Memory"}], "extension": "XSAVEC", "description": "Saves processor extended state components to the memory location specified by EDX:EAX using compaction, removing unused state and reducing the saved data size. Requires XSAVEC feature support (CPUID EAX=0DH, ECX=1:EAX bit 1). No flags are modified; this instruction serializes execution and may trigger VM exits in virtualized environments.", "pseudocode": "mem[EDX:EAX] ← COMPACT_XSTATE_COMPONENTS()\nXSTATE_HEADER[EDX:EAX + 512] ← COMPACTED_SIZE_AND_LAYOUT", "example": "XSAVEC [rbp-8]"} {"mnemonic": "vmfunc", "architecture": "x86", "full_name": "Virtual Machine Function", "summary": "Invoke VM function specified in EAX.", "syntax": "VMFUNC", "encoding": {"format": "VMX", "hex_opcode": "NP 0F 01 D4", "length": "3", "visual_parts": [], "binary_pattern": "0F | 01 | D4", "bit_positions": "+0 | +1 | +2"}, "operands": [], "extension": "VMX", "description": "Invokes a VM function as specified by the function number in EAX and additional parameters in ECX. Only valid in VMX non-root operation (guest mode) and transitions control to the host via VM exit. Privilege level: VMX non-root; will raise #UD if not in VMX operation or if called in root mode.", "pseudocode": "FUNC_NUM ← EAX\nFUNC_PARAM ← ECX\nINVOKE_VMFUNCTION(FUNC_NUM, FUNC_PARAM)\nVMEXIT_TO_HOST", "example": "VMFUNC"} {"mnemonic": "ud0", "architecture": "x86", "full_name": "Undefined Instruction 0", "summary": "Generates invalid opcode exception.", "syntax": "UD0", "encoding": {"format": "Legacy", "hex_opcode": "0F FF /r", "length": "2", "visual_parts": [], "binary_pattern": "0F | FF", "bit_positions": "+0 | +1"}, "operands": [], "extension": "Base", "description": "Generates an invalid opcode exception (#UD). This instruction is reserved for generating intentional undefined instruction exceptions in all processor modes, useful for debugging and kernel routines. No flags are modified; execution terminates with a #UD fault.", "pseudocode": "RAISE_EXCEPTION(#UD)", "example": "UD0"} {"mnemonic": "at", "architecture": "ARMv8-A", "full_name": "Address Translate (Stage 1 Current)", "summary": "Performs stage 1 address translation for current EL.", "syntax": "AT S1E1R, ", "encoding": {"format": "System", "binary_pattern": "1101010100 | 0 | 01 | op1 | 0111 | CRm | op2 | Rt", "hex_opcode": "0xD5087800", "visual_parts": [{"raw": "1101010100", "clean": "1101010100"}, {"raw": "0", "clean": "0"}, {"raw": "01", "clean": "01"}, {"raw": "op1", "clean": "op1"}, {"raw": "0111", "clean": "0111"}, {"raw": "CRm", "clean": "CRm"}, {"raw": "op2", "clean": "op2"}, {"raw": "Rt", "clean": "Rt"}], "bit_positions": "31:22 | 21 | 20:19 | 18:16 | 15:12 | 11:8 | 7:5 | 4:0"}, "operands": [{"name": "Xt", "desc": "Virt Addr"}], "extension": "Base (System)", "description": "Performs stage 1 address translation for a virtual address in the current execution level, treating the access as a read. The translation result (physical address and attributes) is written to the PAR_EL1 register. No condition flags are affected. This is an AArch64-only instruction that requires appropriate privilege level to access the address translation system registers.", "example": "AT S1E1R, x3", "pseudocode": "address ← Xt\ntranslation_result ← TranslateAddress(address, S1E1R, current_EL)\nPAR_EL1 ← translation_result"} {"mnemonic": "at", "architecture": "ARMv8-A", "full_name": "Address Translate (Stage 1 Write)", "summary": "Performs stage 1 address translation for write permission.", "syntax": "AT S1E1W, ", "encoding": {"format": "System", "binary_pattern": "1101010100 | 0 | 01 | op1 | 0111 | CRm | op2 | Rt", "hex_opcode": "0xD5087800", "visual_parts": [{"raw": "1101010100", "clean": "1101010100"}, {"raw": "0", "clean": "0"}, {"raw": "01", "clean": "01"}, {"raw": "op1", "clean": "op1"}, {"raw": "0111", "clean": "0111"}, {"raw": "CRm", "clean": "CRm"}, {"raw": "op2", "clean": "op2"}, {"raw": "Rt", "clean": "Rt"}], "bit_positions": "31:22 | 21 | 20:19 | 18:16 | 15:12 | 11:8 | 7:5 | 4:0"}, "operands": [{"name": "Xt", "desc": "Virt Addr"}], "extension": "Base (System)", "description": "Performs stage 1 address translation for a virtual address in the current execution level, treating the access as a write. The translation result (physical address and attributes) is written to the PAR_EL1 register. No condition flags are affected. This is an AArch64-only instruction that requires appropriate privilege level to access the address translation system registers.", "example": "AT S1E1W, x3", "pseudocode": "address ← Xt\ntranslation_result ← TranslateAddress(address, S1E1W, current_EL)\nPAR_EL1 ← translation_result"} {"mnemonic": "tlbi", "architecture": "ARMv8-A", "full_name": "TLB Invalidate (All)", "summary": "Invalidates all TLB entries in the inner shareable domain.", "syntax": "TLBI VMALLE1IS", "encoding": {"format": "System", "binary_pattern": "1101010100 | 0 | 01 | op1 | CRn | CRm | op2 | Rt", "hex_opcode": "0xD5088000", "visual_parts": [{"raw": "1101010100", "clean": "1101010100"}, {"raw": "0", "clean": "0"}, {"raw": "01", "clean": "01"}, {"raw": "op1", "clean": "op1"}, {"raw": "CRn", "clean": "CRn"}, {"raw": "CRm", "clean": "CRm"}, {"raw": "op2", "clean": "op2"}, {"raw": "Rt", "clean": "Rt"}], "bit_positions": "31:22 | 21 | 20:19 | 18:16 | 15:12 | 11:8 | 7:5 | 4:0"}, "operands": [], "extension": "Base (System)", "description": "Invalidates all TLB entries in the inner shareable domain, affecting all PEs in the shareable domain. This is an AArch64-only instruction requiring EL1 or higher privilege. No condition flags are affected; the instruction generates an exception if executed at EL0.", "example": "TLBI VMALLE1IS", "pseudocode": "TLBInvalidateAll(InnerShareable); DSB(SY); ISB()"} {"mnemonic": "tlbi", "architecture": "ARMv8-A", "full_name": "TLB Invalidate (VA)", "summary": "Invalidates TLB entries by Virtual Address.", "syntax": "TLBI VAE1, ", "encoding": {"format": "System", "binary_pattern": "1101010100 | 0 | 01 | op1 | CRn | CRm | op2 | Rt", "hex_opcode": "0xD5088000", "visual_parts": [{"raw": "1101010100", "clean": "1101010100"}, {"raw": "0", "clean": "0"}, {"raw": "01", "clean": "01"}, {"raw": "op1", "clean": "op1"}, {"raw": "CRn", "clean": "CRn"}, {"raw": "CRm", "clean": "CRm"}, {"raw": "op2", "clean": "op2"}, {"raw": "Rt", "clean": "Rt"}], "bit_positions": "31:22 | 21 | 20:19 | 18:16 | 15:12 | 11:8 | 7:5 | 4:0"}, "operands": [{"name": "Xt", "desc": "VA"}], "extension": "Base (System)", "description": "Invalidates TLB entries matching the virtual address supplied in the register operand, at the current exception level. This is an AArch64-only instruction requiring EL1 or higher privilege. No condition flags are affected; the instruction generates an exception if executed at EL0.", "example": "TLBI VAE1, x3", "pseudocode": "TLBInvalidateByVA(Xt, EL1); DSB(SY); ISB()"} {"mnemonic": "mcr", "architecture": "ARMv8-A", "full_name": "Move to Coprocessor from Register (A32)", "summary": "Writes a general-purpose register to a coprocessor register (e.g., CP15).", "syntax": "MCR , , , , {, }", "encoding": {"format": "Coprocessor", "binary_pattern": "cond | 1110 | opc1 | 0 | CRn | Rt | 111 | coproc<0> | opc2 | 1 | CRm", "hex_opcode": "0x0E000E10", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "1110", "clean": "1110"}, {"raw": "opc1", "clean": "opc1"}, {"raw": "0", "clean": "0"}, {"raw": "CRn", "clean": "CRn"}, {"raw": "Rt", "clean": "Rt"}, {"raw": "111", "clean": "111"}, {"raw": "coproc<0>", "clean": "coproc<0>"}, {"raw": "opc2", "clean": "opc2"}, {"raw": "1", "clean": "1"}, {"raw": "CRm", "clean": "CRm"}], "bit_positions": "31:28 | 27:24 | 23:21 | 20 | 19:16 | 15:12 | 11:9 | 8 | 7:5 | 4 | 3:0"}, "operands": [{"name": "coproc", "desc": "CP Num"}, {"name": "Rt", "desc": "Transfer general-purpose register (load/store)"}, {"name": "CRn", "desc": "Dest CP Reg"}], "extension": "A32 (System)", "description": "Moves data from a general-purpose register into a coprocessor register (typically CP15 for system control). The instruction is conditional and executes only if the condition code is satisfied. No ARM condition flags (N, Z, C, V) are modified by this instruction. This is an A32-only instruction with implementation-specific side effects depending on the target coprocessor register.", "example": "MCR p15, 0, r3, c1, c2", "pseudocode": "if ConditionPassed(cond) then\n CP[coproc, opc1, CRn, CRm, opc2] ← Rt"} {"mnemonic": "mrc", "architecture": "ARMv8-A", "full_name": "Move to Register from Coprocessor (A32)", "summary": "Reads a coprocessor register into a general-purpose register.", "syntax": "MRC , , , , {, }", "encoding": {"format": "Coprocessor", "binary_pattern": "cond | 1110 | opc1 | 1 | CRn | Rt | 111 | coproc<0> | opc2 | 1 | CRm", "hex_opcode": "0x0E100E10", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "1110", "clean": "1110"}, {"raw": "opc1", "clean": "opc1"}, {"raw": "1", "clean": "1"}, {"raw": "CRn", "clean": "CRn"}, {"raw": "Rt", "clean": "Rt"}, {"raw": "111", "clean": "111"}, {"raw": "coproc<0>", "clean": "coproc<0>"}, {"raw": "opc2", "clean": "opc2"}, {"raw": "1", "clean": "1"}, {"raw": "CRm", "clean": "CRm"}], "bit_positions": "31:28 | 27:24 | 23:21 | 20 | 19:16 | 15:12 | 11:9 | 8 | 7:5 | 4 | 3:0"}, "operands": [{"name": "coproc", "desc": "CP Num"}, {"name": "Rt", "desc": "Transfer general-purpose register (load/store)"}, {"name": "CRn", "desc": "Src CP Reg"}], "extension": "A32 (System)", "description": "Moves data from a coprocessor register (typically CP15 for system control) into a general-purpose register. The instruction is conditional and executes only if the condition code is satisfied. The N, Z, C, V flags may be modified depending on the coprocessor register being read. This is an A32-only instruction with implementation-specific behavior depending on the source coprocessor register.", "example": "MRC p15, 0, r3, c1, c2", "pseudocode": "if ConditionPassed(cond) then\n Rt ← CP[coproc, opc1, CRn, CRm, opc2]\n condition_flags may be updated by coprocessor"} {"mnemonic": "mcrr", "architecture": "ARMv8-A", "full_name": "Move to Coprocessor from Two Registers (A32)", "summary": "Writes two general-purpose registers to a coprocessor (64-bit transfer).", "syntax": "MCRR , , , , ", "encoding": {"format": "Coprocessor", "binary_pattern": "cond | 11000 | 1 | 0 | 0 | Rt2 | Rt | 111 | coproc<0> | opc1 | CRm", "hex_opcode": "0x0C400E00", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "11000", "clean": "11000"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "Rt2", "clean": "Rt2"}, {"raw": "Rt", "clean": "Rt"}, {"raw": "111", "clean": "111"}, {"raw": "coproc<0>", "clean": "coproc<0>"}, {"raw": "opc1", "clean": "opc1"}, {"raw": "CRm", "clean": "CRm"}], "bit_positions": "31:28 | 27:23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "coproc", "desc": "CP Num"}, {"name": "Rt", "desc": "Transfer general-purpose register (load/store)"}, {"name": "Rt2", "desc": "Second transfer register (load/store pair)"}], "extension": "A32 (System)", "description": "Moves data from two consecutive general-purpose registers into a coprocessor (64-bit data transfer). The instruction is conditional and executes only if the condition code is satisfied. No ARM condition flags are modified. This is an A32-only instruction; the two source registers are treated as a 64-bit value with Rt containing the lower 32 bits.", "example": "MCRR p15, 0, r3, r4, c2", "pseudocode": "if ConditionPassed(cond) then\n CP64[coproc, opc1, CRm] ← (Rt2:Rt)\n // Rt holds bits [31:0], Rt2 holds bits [63:32]"} {"mnemonic": "mrrc", "architecture": "ARMv8-A", "full_name": "Move to Two Registers from Coprocessor (A32)", "summary": "Reads a coprocessor register into two general-purpose registers.", "syntax": "MRRC , , , , ", "encoding": {"format": "Coprocessor", "binary_pattern": "cond | 11000 | 1 | 0 | 1 | Rt2 | Rt | 111 | coproc<0> | opc1 | CRm", "hex_opcode": "0x0C500E00", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "11000", "clean": "11000"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "Rt2", "clean": "Rt2"}, {"raw": "Rt", "clean": "Rt"}, {"raw": "111", "clean": "111"}, {"raw": "coproc<0>", "clean": "coproc<0>"}, {"raw": "opc1", "clean": "opc1"}, {"raw": "CRm", "clean": "CRm"}], "bit_positions": "31:28 | 27:23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "coproc", "desc": "CP Num"}, {"name": "Rt", "desc": "Dest 1"}, {"name": "Rt2", "desc": "Dest 2"}], "extension": "A32 (System)", "description": "Moves data from a coprocessor into two consecutive general-purpose registers (64-bit data transfer). The instruction is conditional and executes only if the condition code is satisfied. No ARM condition flags are modified by this instruction itself, though the coprocessor may affect them. This is an A32-only instruction; the 64-bit result is split with Rt receiving the lower 32 bits and Rt2 the upper 32 bits.", "example": "MRRC p15, 0, r3, r4, c2", "pseudocode": "if ConditionPassed(cond) then\n data64 ← CP64[coproc, opc1, CRm]\n Rt ← data64[31:0]\n Rt2 ← data64[63:32]"} {"mnemonic": "ldc", "architecture": "ARMv8-A", "full_name": "Load Coprocessor (A32)", "summary": "Loads memory into a coprocessor.", "syntax": "LDC{L} , , [, #+/-]{!}", "encoding": {"format": "Coprocessor", "binary_pattern": "cond | 110 | 1 | U | 0 | 1 | 1 | Rn | 0101 | 111 | 0 | imm8", "hex_opcode": "0x0D305E00", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "110", "clean": "110"}, {"raw": "1", "clean": "1"}, {"raw": "U", "clean": "U"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "0101", "clean": "0101"}, {"raw": "111", "clean": "111"}, {"raw": "0", "clean": "0"}, {"raw": "imm8", "clean": "imm8"}], "bit_positions": "31:28 | 27:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:9 | 8 | 7:0"}, "operands": [{"name": "coproc", "desc": "CP Num"}, {"name": "CRd", "desc": "Destination coprocessor register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}], "extension": "A32 (System)", "description": "Loads data from memory into a coprocessor register, with pre/post-indexed addressing. This is an A32-only instruction that executes conditionally based on the condition field. The base register Rn is updated if the write-back bit W is set; no condition flags are affected by this instruction.", "example": "LDC p15, c0, [r1, #+/-#16]!", "pseudocode": "if ConditionPassed(cond) then\n address ← if P then (Rn + (imm8 << 2)) else Rn\n if U then address ← Rn + (imm8 << 2) else address ← Rn - (imm8 << 2)\n Coproc_load(address, CRd)\n if W then Rn ← address"} {"mnemonic": "stc", "architecture": "ARMv8-A", "full_name": "Store Coprocessor (A32)", "summary": "Stores coprocessor contents to memory.", "syntax": "STC{L} , , [, #+/-]{!}", "encoding": {"format": "Coprocessor", "binary_pattern": "cond | 110 | 1 | U | 0 | 1 | 0 | Rn | 0101 | 111 | 0 | imm8", "hex_opcode": "0x0D205E00", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "110", "clean": "110"}, {"raw": "1", "clean": "1"}, {"raw": "U", "clean": "U"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "0101", "clean": "0101"}, {"raw": "111", "clean": "111"}, {"raw": "0", "clean": "0"}, {"raw": "imm8", "clean": "imm8"}], "bit_positions": "31:28 | 27:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:9 | 8 | 7:0"}, "operands": [{"name": "coproc", "desc": "CP Num"}, {"name": "CRd", "desc": "Destination coprocessor register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}], "extension": "A32 (System)", "description": "Stores coprocessor register contents to memory, with pre/post-indexed addressing. This is an A32-only instruction that executes conditionally based on the condition field. The base register Rn is updated if the write-back bit W is set; no condition flags are affected by this instruction.", "example": "STC p15, c0, [r1, #+/-#16]!", "pseudocode": "if ConditionPassed(cond) then\n address ← if P then (Rn + (imm8 << 2)) else Rn\n if U then address ← Rn + (imm8 << 2) else address ← Rn - (imm8 << 2)\n [address] ← Coproc_store(CRd)\n if W then Rn ← address"} {"mnemonic": "vmrs", "architecture": "ARMv8-A", "full_name": "Move VFP System Register to Register", "summary": "Reads a VFP system register (like FPSCR).", "syntax": "VMRS , ", "encoding": {"format": "VFP System", "binary_pattern": "cond | 1110111 | 1 | reg | Rt | 1010 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0", "hex_opcode": "0x0EF00A10", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "1110111", "clean": "1110111"}, {"raw": "1", "clean": "1"}, {"raw": "reg", "clean": "reg"}, {"raw": "Rt", "clean": "Rt"}, {"raw": "1010", "clean": "1010"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}], "bit_positions": "31:28 | 27:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0"}, "operands": [{"name": "Rt", "desc": "Dest (or APSR_nzcv)"}, {"name": "spec_reg", "desc": "FPSCR"}], "extension": "VFP (System)", "description": "Reads a VFP system register (typically FPSCR) and transfers its value to a general-purpose register or the APSR condition flags. This is an A32/T32 instruction that executes conditionally. If Rt is R15, the N, Z, C, V flags are updated from FPSCR bits; otherwise no flags are modified.", "example": "VMRS r3, nzcv", "pseudocode": "if ConditionPassed(cond) then\n if Rt == 15 then\n APSR_nzcv ← FPSCR[31:28]\n else\n Rt ← FPSCR"} {"mnemonic": "vmsr", "architecture": "ARMv8-A", "full_name": "Move Register to VFP System Register", "summary": "Writes to a VFP system register.", "syntax": "VMSR , ", "encoding": {"format": "VFP System", "binary_pattern": "cond | 1110111 | 0 | reg | Rt | 1010 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0", "hex_opcode": "0x0EE00A10", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "1110111", "clean": "1110111"}, {"raw": "0", "clean": "0"}, {"raw": "reg", "clean": "reg"}, {"raw": "Rt", "clean": "Rt"}, {"raw": "1010", "clean": "1010"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}], "bit_positions": "31:28 | 27:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0"}, "operands": [{"name": "spec_reg", "desc": "FPSCR"}, {"name": "Rt", "desc": "Transfer general-purpose register (load/store)"}], "extension": "VFP (System)", "description": "Writes a general-purpose register value to a VFP system register (typically FPSCR). This is an A32/T32 instruction that executes conditionally. If Rt is R15, the APSR condition flags are written to FPSCR; the instruction may modify exception flags and rounding modes in FPSCR.", "example": "VMSR nzcv, r3", "pseudocode": "if ConditionPassed(cond) then\n if Rt == 15 then\n FPSCR[31:28] ← APSR_nzcv\n else\n FPSCR ← Rt"} {"mnemonic": "ldrexb", "architecture": "ARMv8-A", "full_name": "Load Register Exclusive Byte (A32)", "summary": "Loads a byte and marks address as exclusive.", "syntax": "LDREXB , []", "encoding": {"format": "Load/Store Excl", "binary_pattern": "cond | 00011 | 10 | 1 | Rn | Rt | 1 | 1 | 1 | 1 | 1001 | 1111", "hex_opcode": "0x01D00F9F", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00011", "clean": "00011"}, {"raw": "10", "clean": "10"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rt", "clean": "Rt"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1001", "clean": "1001"}, {"raw": "1111", "clean": "1111"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rt", "desc": "Transfer general-purpose register (load/store)"}, {"name": "Rn", "desc": "First source / base general-purpose register"}], "extension": "A32 (Atomic)", "description": "Loads a byte from memory into a register and marks the address as exclusive for synchronization. The byte is zero-extended to 32 bits in the destination register. No condition flags are modified. This is an A32-only instruction that atomically acquires an exclusive lock on the target byte address; the lock is released by a matching STREXB or other exclusive store.", "example": "LDREXB r3, [r1]", "pseudocode": "if ConditionPassed(cond) then\n address ← Rn\n Rt ← ZeroExtend([address], 8)\n SetExclusiveMonitor(address, 1)"} {"mnemonic": "strexb", "architecture": "ARMv8-A", "full_name": "Store Register Exclusive Byte (A32)", "summary": "Stores a byte if address is still exclusive.", "syntax": "STREXB , , []", "encoding": {"format": "Load/Store Excl", "binary_pattern": "cond | 00011 | 10 | 0 | Rn | Rd | 1 | 1 | 1 | 1 | 1001 | Rt", "hex_opcode": "0x01C00F90", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00011", "clean": "00011"}, {"raw": "10", "clean": "10"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1001", "clean": "1001"}, {"raw": "Rt", "clean": "Rt"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Status"}, {"name": "Rt", "desc": "Transfer general-purpose register (load/store)"}, {"name": "Rn", "desc": "First source / base general-purpose register"}], "extension": "A32 (Atomic)", "description": "Conditionally stores a byte to memory if the address is still marked as exclusive, returning a status in Rd (0=success, 1=failure). No condition flags are modified by the store result; success/failure is reported only in Rd. This is an A32-only instruction that atomically releases the exclusive lock and performs the write only if the lock is still held from a prior LDREXB.", "example": "STREXB r0, r3, [r1]", "pseudocode": "if ConditionPassed(cond) then\n address ← Rn\n byte_value ← Rt[7:0]\n if ExclusiveMonitorSet(address, 1) then\n [address] ← byte_value\n Rd ← 0\n ClearExclusiveMonitor(address, 1)\n else\n Rd ← 1"} {"mnemonic": "ldrexh", "architecture": "ARMv8-A", "full_name": "Load Register Exclusive Halfword (A32)", "summary": "Loads a halfword and marks address as exclusive.", "syntax": "LDREXH , []", "encoding": {"format": "Load/Store Excl", "binary_pattern": "cond | 00011 | 11 | 1 | Rn | Rt | 1 | 1 | 1 | 1 | 1001 | 1111", "hex_opcode": "0x01F00F9F", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00011", "clean": "00011"}, {"raw": "11", "clean": "11"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rt", "clean": "Rt"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1001", "clean": "1001"}, {"raw": "1111", "clean": "1111"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rt", "desc": "Transfer general-purpose register (load/store)"}, {"name": "Rn", "desc": "First source / base general-purpose register"}], "extension": "A32 (Atomic)", "description": "Loads a 16-bit value from memory at the address in Rn and marks that address as exclusive for the current processor. The loaded halfword is zero-extended and placed in Rt. No condition flags are affected. This A32 instruction requires a matching STREXH to conditionally store; if the exclusive monitor is cleared, a subsequent STREXH will fail.", "example": "LDREXH r3, [r1]", "pseudocode": "address ← Rn; Rt ← ZeroExtend(MemU[address, 2]); ExclusiveMonitorsMarkExclusive(address, ProcessorID(), 2);"} {"mnemonic": "strexh", "architecture": "ARMv8-A", "full_name": "Store Register Exclusive Halfword (A32)", "summary": "Stores a halfword if address is still exclusive.", "syntax": "STREXH , , []", "encoding": {"format": "Load/Store Excl", "binary_pattern": "cond | 00011 | 11 | 0 | Rn | Rd | 1 | 1 | 1 | 1 | 1001 | Rt", "hex_opcode": "0x01E00F90", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00011", "clean": "00011"}, {"raw": "11", "clean": "11"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1001", "clean": "1001"}, {"raw": "Rt", "clean": "Rt"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Status"}, {"name": "Rt", "desc": "Transfer general-purpose register (load/store)"}, {"name": "Rn", "desc": "First source / base general-purpose register"}], "extension": "A32 (Atomic)", "description": "Conditionally stores a 16-bit value from Rt to memory at the address in Rn if that address is still marked exclusive by the current processor. Writes 0 to Rd if the store succeeds, or 1 if it fails due to loss of exclusivity. No condition flags are affected by the instruction result itself; the exclusive monitor behavior determines success/failure.", "example": "STREXH r0, r3, [r1]", "pseudocode": "address ← Rn; if ExclusiveMonitorsCheckExclusive(address, ProcessorID(), 2) then MemU[address, 2] ← Rt[15:0]; Rd ← 0; ExclusiveMonitorsClearExclusive(ProcessorID()); else Rd ← 1;"} {"mnemonic": "ldrexd", "architecture": "ARMv8-A", "full_name": "Load Register Exclusive Double (A32)", "summary": "Loads a doubleword and marks address as exclusive.", "syntax": "LDREXD , , []", "encoding": {"format": "Load/Store Excl", "binary_pattern": "cond | 00011 | 01 | 1 | Rn | Rt | 1 | 1 | 1 | 1 | 1001 | 1111", "hex_opcode": "0x01B00F9F", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00011", "clean": "00011"}, {"raw": "01", "clean": "01"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rt", "clean": "Rt"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1001", "clean": "1001"}, {"raw": "1111", "clean": "1111"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rt", "desc": "Dest 1"}, {"name": "Rt2", "desc": "Dest 2"}, {"name": "Rn", "desc": "First source / base general-purpose register"}], "extension": "A32 (Atomic)", "description": "Loads a 64-bit doubleword from memory at the address in Rn and marks that address as exclusive for the current processor. The loaded value is split across Rt (lower 32 bits) and Rt2 (upper 32 bits). No condition flags are affected. This A32 instruction requires matching STREXD for conditional storage; Rt and Rt2 must be consecutive registers.", "example": "LDREXD r3, r4, [r1]", "pseudocode": "address ← Rn; value ← MemU[address, 8]; Rt ← value[31:0]; Rt2 ← value[63:32]; ExclusiveMonitorsMarkExclusive(address, ProcessorID(), 8);"} {"mnemonic": "strexd", "architecture": "ARMv8-A", "full_name": "Store Register Exclusive Double (A32)", "summary": "Stores a doubleword if address is still exclusive.", "syntax": "STREXD , , , []", "encoding": {"format": "Load/Store Excl", "binary_pattern": "cond | 00011 | 01 | 0 | Rn | Rd | 1 | 1 | 1 | 1 | 1001 | Rt", "hex_opcode": "0x01A00F90", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00011", "clean": "00011"}, {"raw": "01", "clean": "01"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1001", "clean": "1001"}, {"raw": "Rt", "clean": "Rt"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Status"}, {"name": "Rt", "desc": "Transfer general-purpose register (load/store)"}, {"name": "Rt2", "desc": "Second transfer register (load/store pair)"}, {"name": "Rn", "desc": "First source / base general-purpose register"}], "extension": "A32 (Atomic)", "description": "Conditionally stores a 64-bit doubleword from Rt and Rt2 to memory at the address in Rn if that address is still marked exclusive by the current processor. Writes 0 to Rd on success or 1 on failure. No condition flags are affected; exclusive monitor state determines the outcome.", "example": "STREXD r0, r3, r4, [r1]", "pseudocode": "address ← Rn; if ExclusiveMonitorsCheckExclusive(address, ProcessorID(), 8) then MemU[address, 8] ← Rt || Rt2; Rd ← 0; ExclusiveMonitorsClearExclusive(ProcessorID()); else Rd ← 1;"} {"mnemonic": "dcps1", "architecture": "ARMv8-A", "full_name": "Debug Change PE State to EL1 (A32)", "summary": "Switches execution to EL1 (Debug).", "syntax": "DCPS1", "encoding": {"format": "System", "binary_pattern": "111101111000 | 1111 | 1000 | 0000000000 | 01", "hex_opcode": "0xF78F8001", "visual_parts": [{"raw": "111101111000", "clean": "111101111000"}, {"raw": "1111", "clean": "1111"}, {"raw": "1000", "clean": "1000"}, {"raw": "0000000000", "clean": "0000000000"}, {"raw": "01", "clean": "01"}], "bit_positions": "31:20 | 19:16 | 15:12 | 11:2 | 1:0"}, "operands": [], "extension": "A32 (System)", "description": "Changes PE execution state to EL1 for debugging purposes. This is an A32-only instruction that immediately changes exception level and may update execution state; it does not return (implicit branch to debug handler). Condition flags are not affected by the instruction itself but are context-switched at the target exception level.", "example": "DCPS1", "pseudocode": "DebugChangeEL(EL1); // Changes exception level and branches to debug handler"} {"mnemonic": "dcps2", "architecture": "ARMv8-A", "full_name": "Debug Change PE State to EL2 (A32)", "summary": "Switches execution to EL2 (Debug).", "syntax": "DCPS2", "encoding": {"format": "System", "binary_pattern": "111101111000 | 1111 | 1000 | 0000000000 | 10", "hex_opcode": "0xF78F8002", "visual_parts": [{"raw": "111101111000", "clean": "111101111000"}, {"raw": "1111", "clean": "1111"}, {"raw": "1000", "clean": "1000"}, {"raw": "0000000000", "clean": "0000000000"}, {"raw": "10", "clean": "10"}], "bit_positions": "31:20 | 19:16 | 15:12 | 11:2 | 1:0"}, "operands": [], "extension": "A32 (System)", "description": "Changes PE execution state to EL2 for debugging purposes. This is an A32-only instruction that immediately changes exception level and may update execution state; it does not return (implicit branch to debug handler). Condition flags are not affected by the instruction itself but are context-switched at the target exception level.", "example": "DCPS2", "pseudocode": "DebugChangeEL(EL2); // Changes exception level and branches to debug handler"} {"mnemonic": "dcps3", "architecture": "ARMv8-A", "full_name": "Debug Change PE State to EL3 (A32)", "summary": "Switches execution to EL3 (Debug).", "syntax": "DCPS3", "encoding": {"format": "System", "binary_pattern": "111101111000 | 1111 | 1000 | 0000000000 | 11", "hex_opcode": "0xF78F8003", "visual_parts": [{"raw": "111101111000", "clean": "111101111000"}, {"raw": "1111", "clean": "1111"}, {"raw": "1000", "clean": "1000"}, {"raw": "0000000000", "clean": "0000000000"}, {"raw": "11", "clean": "11"}], "bit_positions": "31:20 | 19:16 | 15:12 | 11:2 | 1:0"}, "operands": [], "extension": "A32 (System)", "description": "Debug Change PE State to EL3 switches the processor to Exception Level 3 (EL3) in debug state without saving the current processor state. This instruction is used by debuggers to enter the highest privilege level. It is available only in A32 instruction set and requires debug authentication. No condition flags are modified.", "example": "DCPS3", "pseudocode": "CurrentEL ← EL3; PSTATE.EL ← '11'; PSTATE.SS ← '0';"} {"mnemonic": "setpan", "architecture": "ARMv8-A", "full_name": "Set Privileged Access Never (A32)", "summary": "Enables/Disables PAN (Prevents kernel accessing user memory).", "syntax": "SETPAN #", "encoding": {"format": "System", "binary_pattern": "111100010001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | imm1 | 0 | 0000 | 0 | 0 | 0 | 0", "hex_opcode": "0xF1100000", "visual_parts": [{"raw": "111100010001", "clean": "111100010001"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "imm1", "clean": "imm1"}, {"raw": "0", "clean": "0"}, {"raw": "0000", "clean": "0000"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}], "bit_positions": "31:20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7:4 | 3 | 2 | 1 | 0"}, "operands": [{"name": "imm", "desc": "0/1"}], "extension": "A32 (System)", "description": "Set Privileged Access Never enables or disables the PAN (Privileged Access Never) control bit, which prevents privileged software from accessing user-mode memory. When PAN is enabled (imm=1), privileged accesses to user memory are trapped; when disabled (imm=0), such accesses are permitted. This instruction is available in A32 and requires appropriate privilege level. No condition flags are modified.", "example": "SETPAN #16", "pseudocode": "PSTATE.PAN ← imm;"} {"mnemonic": "esb", "architecture": "ARMv8-A", "full_name": "Error Synchronization Barrier (A32)", "summary": "Synchronizes system errors (v8.2).", "syntax": "ESB", "encoding": {"format": "System Hint", "binary_pattern": "cond | 00110 | 0 | 10 | 0000 | 1 | 1 | 1 | 1 | 000000010000", "hex_opcode": "0x0320F010", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00110", "clean": "00110"}, {"raw": "0", "clean": "0"}, {"raw": "10", "clean": "10"}, {"raw": "0000", "clean": "0000"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "000000010000", "clean": "000000010000"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15 | 14 | 13 | 12 | 11:0"}, "operands": [], "extension": "A32 (RAS)", "description": "Error Synchronization Barrier (v8.2) for RAS (Reliability, Availability, and Serviceability) synchronizes system error handling, ensuring that error detection and processing operations complete in order. This instruction is essential in fault-tolerance and error recovery scenarios and does not modify general-purpose registers or condition flags. Available in A32 instruction set.", "example": "ESB", "pseudocode": "// Synchronize error handling\nErrorSynchronizationBarrier()\n// All pending error detection and processing operations complete"} {"mnemonic": "csdb", "architecture": "ARMv8-A", "full_name": "Consumption of Speculative Data Barrier (A32)", "summary": "Prevents speculative data consumption (v8.0).", "syntax": "CSDB", "encoding": {"format": "System Hint", "binary_pattern": "cond | 00110 | 0 | 10 | 0000 | 1 | 1 | 1 | 1 | 000000010100", "hex_opcode": "0x0320F014", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00110", "clean": "00110"}, {"raw": "0", "clean": "0"}, {"raw": "10", "clean": "10"}, {"raw": "0000", "clean": "0000"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "000000010100", "clean": "000000010100"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15 | 14 | 13 | 12 | 11:0"}, "operands": [], "extension": "A32 (v8.0)", "description": "Consumption of Speculative Data Barrier (v8.0) prevents the CPU from using speculatively-loaded data in subsequent operations, protecting against attacks that exploit speculative data consumption side channels. Instructions following CSDB cannot use data speculatively loaded before this barrier. Available in A32 instruction set; does not modify condition flags.", "example": "CSDB", "pseudocode": "// Prevent consumption of speculatively-loaded data\nConsumptionBarrier()\n// Subsequent instructions cannot use data obtained through speculative execution prior to this barrier"} {"mnemonic": "vldm", "architecture": "ARMv8-A", "full_name": "Vector Load Multiple (VFP)", "summary": "Loads multiple VFP registers from memory.", "syntax": "VLDM {!}, ", "encoding": {"format": "VFP Load Multiple", "binary_pattern": "cond | 110 | 0 | 1 | D | W | 1 | Rn | Vd | 10 | 10 | imm8", "hex_opcode": "0x0C900A00", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "110", "clean": "110"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "W", "clean": "W"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "imm8", "clean": "imm8"}], "bit_positions": "31:28 | 27:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:10 | 9:8 | 7:0"}, "operands": [{"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "list", "desc": "Registers"}], "extension": "VFP (Float)", "description": "Vector Load Multiple loads multiple consecutive double-precision or single-precision floating-point registers from memory using the address in a general-purpose base register. The base register can be optionally auto-incremented by the total bytes loaded. Condition flags (N, Z, C, V) are unaffected unless an exception occurs.", "example": "VLDMia r1!, {r0-r3", "pseudocode": "address ← Rn; for i = 0 to (list_count - 1) do; Driestlist[i] ← [address]; address ← address + (register_size / 8); end; if !(!) then Rn ← address;"} {"mnemonic": "vstm", "architecture": "ARMv8-A", "full_name": "Vector Store Multiple (VFP)", "summary": "Stores multiple VFP registers to memory.", "syntax": "VSTM {!}, ", "encoding": {"format": "VFP Store Multiple", "binary_pattern": "cond | 110 | 0 | 1 | D | W | 0 | Rn | Vd | 10 | 10 | imm8", "hex_opcode": "0x0C800A00", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "110", "clean": "110"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "W", "clean": "W"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "imm8", "clean": "imm8"}], "bit_positions": "31:28 | 27:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:10 | 9:8 | 7:0"}, "operands": [{"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "list", "desc": "Registers"}], "extension": "VFP (Float)", "description": "Vector Store Multiple stores multiple consecutive double-precision or single-precision floating-point registers to memory using the address in a general-purpose base register. The base register can be optionally auto-incremented by the total bytes stored. Condition flags (N, Z, C, V) are unaffected unless an exception occurs.", "example": "VSTMia r1!, {r0-r3", "pseudocode": "address ← Rn; for i = 0 to (list_count - 1) do; [address] ← Vriestlist[i]; address ← address + (register_size / 8); end; if !(!) then Rn ← address;"} {"mnemonic": "vcmp", "architecture": "ARMv8-A", "full_name": "Vector Compare Zero (VFP)", "summary": "Compares a floating-point value with #0.0.", "syntax": "VCMP.F32 , #0.0", "encoding": {"format": "VFP Compare", "binary_pattern": "cond | 11101 | D | 11 | 0 | 101 | Vd | 10 | 10 | 0 | 1 | 0 | 0 | 0000", "hex_opcode": "0x0EB50A40", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "11101", "clean": "11101"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "0", "clean": "0"}, {"raw": "101", "clean": "101"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0000", "clean": "0000"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}], "extension": "VFP (Float)", "description": "Vector Compare Zero compares a single-precision floating-point value against zero and updates the VFP condition flags (FPSCR bits 28-31) based on the result. The comparison sets flags for signed magnitude comparison: N, Z, C, V flags in FPSCR are updated; FPSCR.E bit may be set if an exception occurs. Available in A32 VFP extension.", "example": "VCMP.F32 s0, #0.0", "pseudocode": "result ← Sd - 0.0; UpdateFPSCRConditionFlags(result); if exception then SetFPSCRException();"} {"mnemonic": "vdiv", "architecture": "ARMv8-A", "full_name": "Vector Divide (Double)", "summary": "Divides two double-precision registers.", "syntax": "VDIV.F64
, , ", "encoding": {"format": "VFP Arith", "binary_pattern": "cond | 1110 | 1 | D | 00 | Vn | Vd | 10 | 11 | N | 0 | M | 0 | Vm", "hex_opcode": "0x0E800B00", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "1110", "clean": "1110"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "00", "clean": "00"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "11", "clean": "11"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:28 | 27:24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Dd", "desc": "Destination 64-bit SIMD/FP register"}, {"name": "Dn", "desc": "Dividend"}, {"name": "Dm", "desc": "Divisor"}], "extension": "VFP (Float)", "description": "Divides the 64-bit double-precision value in Dn by the value in Dm and places the floating-point result in Dd. The operation follows IEEE 754 semantics for rounding and exception handling. FPSCR condition flags (N, Z, C, V) may be set based on the result and any exceptions; this instruction is available only in A32 and T32 with VFP support.", "example": "VDIV.F64 d0, d1, d2", "pseudocode": "Dd ← FPDiv(Dn, Dm); FPSCR.N ← Dd[63]; FPSCR.Z ← (Dd == 0.0); FPSCR.C ← FPExceptionRaised(); FPSCR.V ← FPInvalidOp();"} {"mnemonic": "vabs", "architecture": "ARMv8-A", "full_name": "Vector Absolute Value (Double)", "summary": "Absolute value of double-precision register.", "syntax": "VABS.F64
, ", "encoding": {"format": "VFP Unary", "binary_pattern": "cond | 11101 | D | 11 | 0 | 000 | Vd | 10 | 11 | 1 | 1 | M | 0 | Vm", "hex_opcode": "0x0EB00BC0", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "11101", "clean": "11101"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "0", "clean": "0"}, {"raw": "000", "clean": "000"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "11", "clean": "11"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Dd", "desc": "Destination 64-bit SIMD/FP register"}, {"name": "Dm", "desc": "Second source 64-bit SIMD/FP register"}], "extension": "VFP (Float)", "description": "Vector Absolute Value computes the absolute value of a 64-bit double-precision floating-point register and stores the result in the destination register. The sign bit is cleared while the exponent and significand are preserved. Condition flags are unaffected unless an exception occurs. Available in A32 VFP extension.", "example": "VABS.F64 d0, d2", "pseudocode": "Dd.sign ← 0; Dd.exponent ← Dm.exponent; Dd.fraction ← Dm.fraction;"} {"mnemonic": "vneg", "architecture": "ARMv8-A", "full_name": "Vector Negate (Double)", "summary": "Negates double-precision register.", "syntax": "VNEG.F64
, ", "encoding": {"format": "VFP Unary", "binary_pattern": "cond | 11101 | D | 11 | 0 | 001 | Vd | 10 | 11 | 0 | 1 | M | 0 | Vm", "hex_opcode": "0x0EB10B40", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "11101", "clean": "11101"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "0", "clean": "0"}, {"raw": "001", "clean": "001"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "11", "clean": "11"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Dd", "desc": "Destination 64-bit SIMD/FP register"}, {"name": "Dm", "desc": "Second source 64-bit SIMD/FP register"}], "extension": "VFP (Float)", "description": "Negates a double-precision floating-point value in the source register and stores the result in the destination register. This is a unary VFP operation that inverts the sign bit of the IEEE 754 double-precision number. No condition flags are affected. Requires VFP extension and executes only in A32 instruction set.", "example": "VNEG.F64 d0, d2", "pseudocode": "Dd ← -Dm\nFPSCR.NZCV unchanged"} {"mnemonic": "vsqrt", "architecture": "ARMv8-A", "full_name": "Vector Square Root (Double)", "summary": "Square root of double-precision register.", "syntax": "VSQRT.F64
, ", "encoding": {"format": "VFP Unary", "binary_pattern": "cond | 11101 | D | 11 | 0 | 001 | Vd | 10 | 11 | 1 | 1 | M | 0 | Vm", "hex_opcode": "0x0EB10BC0", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "11101", "clean": "11101"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "0", "clean": "0"}, {"raw": "001", "clean": "001"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "11", "clean": "11"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Dd", "desc": "Destination 64-bit SIMD/FP register"}, {"name": "Dm", "desc": "Second source 64-bit SIMD/FP register"}], "extension": "VFP (Float)", "description": "Computes the square root of a double-precision floating-point value and stores the result in the destination register. This is a unary VFP operation that performs IEEE 754 compliant square-root computation; if the source is negative (excluding -0), the result is NaN. FPSCR exception flags may be set based on input and result. Requires VFP extension and executes only in A32 instruction set.", "example": "VSQRT.F64 d0, d2", "pseudocode": "Dd ← sqrt(Dm)\nFPSCR.IOC ← 1 if Dm < 0.0 and Dm ≠ -0.0 (invalid operation)\nFPSCR.UFC ← 1 if result is subnormal (underflow)\nFPSCR.OFC ← 1 if result overflows\nFPSCR.IXC ← 1 if result is inexact"} {"mnemonic": "vfma", "architecture": "ARMv8-A", "full_name": "Vector Fused Multiply Accumulate (Double)", "summary": "Fused multiply-add (Double).", "syntax": "VFMA.F64 , , ", "encoding": {"format": "VFP Arith", "binary_pattern": "cond | 1110 | 1 | D | 10 | Vn | Vd | 10 | 11 | N | 0 | M | 0 | Vm", "hex_opcode": "0x0EA00B00", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "1110", "clean": "1110"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "10", "clean": "10"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "11", "clean": "11"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:28 | 27:24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "VFPv4 (Float)", "description": "Performs a fused multiply-accumulate operation on two double-precision values with a third double-precision accumulator value: Qd ← Qd + (Qn × Qm). The operation is a single fused operation with one rounding step, providing higher precision than separate multiply and add instructions. FPSCR exception flags may be set. Requires VFPv4 extension and executes only in A32 instruction set.", "example": "VFMA.F64 q0, q1, q2", "pseudocode": "Qd ← Qd + (Qn × Qm)\nFPSCR.IOC ← 1 if invalid operand\nFPSCR.UFC ← 1 if result underflows\nFPSCR.OFC ← 1 if result overflows\nFPSCR.IXC ← 1 if result is inexact"} {"mnemonic": "vfms", "architecture": "ARMv8-A", "full_name": "Vector Fused Multiply Subtract (Double)", "summary": "Fused multiply-subtract (Double).", "syntax": "VFMS.F64 , , ", "encoding": {"format": "VFP Arith", "binary_pattern": "cond | 1110 | 1 | D | 10 | Vn | Vd | 10 | 11 | N | 1 | M | 0 | Vm", "hex_opcode": "0x0EA00B40", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "1110", "clean": "1110"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "10", "clean": "10"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "11", "clean": "11"}, {"raw": "N", "clean": "N"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:28 | 27:24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "VFPv4 (Float)", "description": "Performs a fused multiply-subtract on 128-bit NEON registers: computes Qd = Qd - (Qn × Qm) for double-precision (F64) elements with a single rounding step. This VFPv4 instruction is more accurate than separate multiply and subtract operations. Floating-point exception flags in FPSCR may be set; condition codes N, Z, C, V are not directly modified.", "example": "VFMS.F64 q0, q1, q2", "pseudocode": "Qd ← FPMulSubFused(Qd, Qn, Qm);"} {"mnemonic": "vcmp", "architecture": "ARMv8-A", "full_name": "Vector Compare (Double)", "summary": "Compares two double-precision values.", "syntax": "VCMP.F64
, ", "encoding": {"format": "VFP Compare", "binary_pattern": "cond | 11101 | D | 11 | 0 | 100 | Vd | 10 | 11 | 0 | 1 | M | 0 | Vm", "hex_opcode": "0x0EB40B40", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "11101", "clean": "11101"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "0", "clean": "0"}, {"raw": "100", "clean": "100"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "11", "clean": "11"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Dd", "desc": "Destination 64-bit SIMD/FP register"}, {"name": "Dm", "desc": "Second source 64-bit SIMD/FP register"}], "extension": "VFP (Float)", "description": "Compares two double-precision floating-point values and sets the FPSCR condition flags based on the comparison result (equal, less than, greater than, or unordered). The instruction does not produce a destination register value; it only updates FPSCR flags (N, Z, C, V). Requires VFP extension and executes only in A32 instruction set.", "example": "VCMP.F64 d0, d2", "pseudocode": "result ← Dd - Dm\nFPSCR.N ← sign bit of result\nFPSCR.Z ← 1 if values equal\nFPSCR.C ← 1 if Dd ≥ Dm\nFPSCR.V ← 1 if either operand is NaN (unordered)"} {"mnemonic": "vmov", "architecture": "ARMv8-A", "full_name": "Vector Move (Double)", "summary": "Moves data between Double registers.", "syntax": "VMOV.F64
, ", "encoding": {"format": "VFP Move", "binary_pattern": "cond | 11101 | D | 11 | 0 | 000 | Vd | 10 | size | 0 | 1 | M | 0 | Vm", "hex_opcode": "0x0EB00B40", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "11101", "clean": "11101"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "0", "clean": "0"}, {"raw": "000", "clean": "000"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "size", "clean": "size"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Dd", "desc": "Destination 64-bit SIMD/FP register"}, {"name": "Dm", "desc": "Second source 64-bit SIMD/FP register"}], "extension": "VFP (Float)", "description": "Copies a 64-bit double-precision floating-point value from Dm to Dd with no arithmetic or rounding. This is a register-to-register move within the VFP register file. No condition flags are affected, and this instruction executes unconditionally (though it respects the condition code in A32/T32).", "example": "VMOV.F64 d0, d2", "pseudocode": "Dd ← Dm;"} {"mnemonic": "vmov", "architecture": "ARMv8-A", "full_name": "Vector Move (Double <-> 2xGPR)", "summary": "Moves a Double register to/from two Core registers.", "syntax": "VMOV , , ", "encoding": {"format": "VFP Transfer", "binary_pattern": "cond | 11000 | 1 | 0 | 0 | Rt2 | Rt | 10 | 11 | 00 | M | 1 | Vm", "hex_opcode": "0x0C400B10", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "11000", "clean": "11000"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "Rt2", "clean": "Rt2"}, {"raw": "Rt", "clean": "Rt"}, {"raw": "10", "clean": "10"}, {"raw": "11", "clean": "11"}, {"raw": "00", "clean": "00"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:28 | 27:23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:10 | 9:8 | 7:6 | 5 | 4 | 3:0"}, "operands": [{"name": "Rt", "desc": "Low"}, {"name": "Rt2", "desc": "High"}, {"name": "Dm", "desc": "VFP"}], "extension": "VFP (Float)", "description": "Transfers a 64-bit value between a VFP double-precision register (Dm) and two consecutive ARM core registers (Rt for bits [31:0], Rt2 for bits [63:32]). Direction is determined by the opcode bit pattern: from core to VFP or VFP to core. No condition flags are affected.", "example": "VMOV r3, r4, d2", "pseudocode": "if direction == 'core_to_vfp' then Dm ← Rt2 || Rt; else Rt ← Dm[31:0]; Rt2 ← Dm[63:32];"} {"mnemonic": "vcvta", "architecture": "ARMv8-A", "full_name": "Vector Convert to Integer (Nearest, Double)", "summary": "Converts double to integer, rounding to nearest.", "syntax": "VCVTA.
.F64 , ", "encoding": {"format": "VFP Convert", "binary_pattern": "111111101 | D | 111 | 1 | 00 | Vd | 10 | 11 | op | 1 | M | 0 | Vm", "hex_opcode": "0xFEBC0B40", "visual_parts": [{"raw": "111111101", "clean": "111111101"}, {"raw": "D", "clean": "D"}, {"raw": "111", "clean": "111"}, {"raw": "1", "clean": "1"}, {"raw": "00", "clean": "00"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "11", "clean": "11"}, {"raw": "op", "clean": "op"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:19 | 18 | 17:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}, {"name": "Dm", "desc": "Second source 64-bit SIMD/FP register"}], "extension": "VFP (Float)", "description": "Converts a 64-bit double-precision floating-point value to a 32-bit integer, rounding to nearest (away from zero on tie). Executes conditionally in A32 and writes the integer result to a 32-bit floating-point register. No condition flags are affected by this instruction.", "example": "VCVTA.dt.F64 s0, d2", "pseudocode": "if ConditionPassed() then\n Sd = ConvertToInt(Dm, RoundingMode=RoundToNearest)"} {"mnemonic": "vcvtn", "architecture": "ARMv8-A", "full_name": "Vector Convert to Integer (Nearest Even, Double)", "summary": "Converts double to integer, rounding to nearest even.", "syntax": "VCVTN.
.F64 , ", "encoding": {"format": "VFP Convert", "binary_pattern": "111111101 | D | 111 | 1 | 01 | Vd | 10 | 11 | op | 1 | M | 0 | Vm", "hex_opcode": "0xFEBD0B40", "visual_parts": [{"raw": "111111101", "clean": "111111101"}, {"raw": "D", "clean": "D"}, {"raw": "111", "clean": "111"}, {"raw": "1", "clean": "1"}, {"raw": "01", "clean": "01"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "11", "clean": "11"}, {"raw": "op", "clean": "op"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:19 | 18 | 17:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}, {"name": "Dm", "desc": "Second source 64-bit SIMD/FP register"}], "extension": "VFP (Float)", "description": "Converts a 64-bit double-precision floating-point value to a 32-bit integer, rounding to nearest even (banker's rounding). Executes conditionally in A32 and writes the integer result to a 32-bit floating-point register. No condition flags are affected by this instruction.", "example": "VCVTN.dt.F64 s0, d2", "pseudocode": "if ConditionPassed() then\n Sd = ConvertToInt(Dm, RoundingMode=RoundToNearestEven)"} {"mnemonic": "vcvt", "architecture": "ARMv8-A", "full_name": "Vector Convert (Fixed Point)", "summary": "Converts between floating-point and fixed-point.", "syntax": "VCVT.. , , #", "encoding": {"format": "VFP Convert", "binary_pattern": "cond | 11101 | D | 11 | 1 | 1 | 1 | U | Vd | 10 | 10 | sx | 1 | i | 0 | imm4", "hex_opcode": "0x0EBE0A40", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "11101", "clean": "11101"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "U", "clean": "U"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "sx", "clean": "sx"}, {"raw": "1", "clean": "1"}, {"raw": "i", "clean": "i"}, {"raw": "0", "clean": "0"}, {"raw": "imm4", "clean": "imm4"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18 | 17 | 16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}, {"name": "fbits", "desc": "Number of fractional bits"}], "extension": "VFP (Float)", "description": "Converts between floating-point and fixed-point formats in 128-bit SIMD registers with a specified number of fractional bits. This is a NEON instruction that operates element-wise on the vector operands. No condition flags are affected.", "example": "VCVT.Td.Tm q0, q2, #8", "pseudocode": "if ConditionPassed() then\n for i = 0 to elements-1\n if Tm == F32 then\n Qd[i] = FixedPointConvert(Qm[i], fbits)\n else\n Qd[i] = FloatingPointConvert(Qm[i], fbits)"} {"mnemonic": "addg", "architecture": "ARMv8-A", "full_name": "Add with Tag", "summary": "Adds an immediate to an address, modifying the Allocation Tag (MTE).", "syntax": "ADDG , , #, #", "encoding": {"format": "Data Processing", "binary_pattern": "1 | 0 | 0 | 1000110 | uimm6 | 00 | uimm4 | Xn | Xd", "hex_opcode": "0x91800000", "visual_parts": [{"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "1000110", "clean": "1000110"}, {"raw": "uimm6", "clean": "uimm6"}, {"raw": "00", "clean": "00"}, {"raw": "uimm4", "clean": "uimm4"}, {"raw": "Xn", "clean": "Xn"}, {"raw": "Xd", "clean": "Xd"}], "bit_positions": "31 | 30 | 29 | 28:22 | 21:16 | 15:14 | 13:10 | 9:5 | 4:0"}, "operands": [{"name": "Xd", "desc": "Destination 64-bit integer register"}, {"name": "Xn", "desc": "First source / base 64-bit integer register"}, {"name": "uimm6", "desc": "Address Offset"}, {"name": "uimm4", "desc": "Tag Offset"}], "extension": "MTE (Memory Tagging)", "description": "Adds a scaled immediate offset (uimm6 × 16) to an address in the source register and simultaneously updates the Memory Tagging Extension (MTE) Allocation Tag in bits [59:56] by adding uimm4. The result is stored in the destination register. This is an AArch64-only instruction that modifies both address and tag atomically. No condition flags are affected.", "example": "ADDG x0, x1, #8, #3", "pseudocode": "address_offset ← uimm6 × 16\ntag_offset ← uimm4\nif Xn == SP then\n Xd ← (Xn + address_offset)[63:0]\n Xd[59:56] ← (Xn[59:56] + tag_offset) AND 0xF\nelse\n Xd ← (Xn + address_offset)[63:0]\n Xd[59:56] ← (Xn[59:56] + tag_offset) AND 0xF"} {"mnemonic": "subg", "architecture": "ARMv8-A", "full_name": "Subtract with Tag", "summary": "Subtracts an immediate from an address, modifying the Allocation Tag (MTE).", "syntax": "SUBG , , #, #", "encoding": {"format": "Data Processing", "binary_pattern": "1 | 1 | 0 | 1000110 | uimm6 | 00 | uimm4 | Xn | Xd", "hex_opcode": "0xD1800000", "visual_parts": [{"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "1000110", "clean": "1000110"}, {"raw": "uimm6", "clean": "uimm6"}, {"raw": "00", "clean": "00"}, {"raw": "uimm4", "clean": "uimm4"}, {"raw": "Xn", "clean": "Xn"}, {"raw": "Xd", "clean": "Xd"}], "bit_positions": "31 | 30 | 29 | 28:22 | 21:16 | 15:14 | 13:10 | 9:5 | 4:0"}, "operands": [{"name": "Xd", "desc": "Destination 64-bit integer register"}, {"name": "Xn", "desc": "First source / base 64-bit integer register"}, {"name": "uimm6", "desc": "Address Offset"}, {"name": "uimm4", "desc": "Tag Offset"}], "extension": "MTE (Memory Tagging)", "description": "Subtracts a scaled immediate offset (uimm6 × 16) from an address in the source register and simultaneously updates the Memory Tagging Extension (MTE) Allocation Tag in bits [59:56] by adding uimm4. The result is stored in the destination register. This is an AArch64-only instruction that modifies both address and tag atomically. No condition flags are affected.", "example": "SUBG x0, x1, #8, #3", "pseudocode": "address_offset ← uimm6 × 16\ntag_offset ← uimm4\nif Xn == SP then\n Xd ← (Xn - address_offset)[63:0]\n Xd[59:56] ← (Xn[59:56] + tag_offset) AND 0xF\nelse\n Xd ← (Xn - address_offset)[63:0]\n Xd[59:56] ← (Xn[59:56] + tag_offset) AND 0xF"} {"mnemonic": "cosp", "architecture": "ARMv8-A", "full_name": "Call Out Speculation", "summary": "Prevents speculation from determining that the instruction is executed.", "syntax": "COSP ", "encoding": {"format": "System", "binary_pattern": "1101010100 | 0 | 01 | 011 | 0111 | 0011 | 110 | Rt", "hex_opcode": "0xD50B73C0", "visual_parts": [{"raw": "1101010100", "clean": "1101010100"}, {"raw": "0", "clean": "0"}, {"raw": "01", "clean": "01"}, {"raw": "011", "clean": "011"}, {"raw": "0111", "clean": "0111"}, {"raw": "0011", "clean": "0011"}, {"raw": "110", "clean": "110"}, {"raw": "Rt", "clean": "Rt"}], "bit_positions": "31:22 | 21 | 20:19 | 18:16 | 15:12 | 11:8 | 7:5 | 4:0"}, "operands": [{"name": "Xt", "desc": "Reg"}], "extension": "FEAT_CSV3 (Speculation)", "description": "Call Out Speculation: prevents speculation from reaching instructions beyond this point until the operand register is committed. This instruction is part of the CSV3 speculation control feature and executes in AArch64 state only. It does not affect any condition flags and requires the source register value to be resolved before execution can proceed speculatively.", "example": "COSP x3", "pseudocode": "if FEAT_CSV3 == '0' then\n UNDEFINED\nelse\n CommitSpeculation(X[t])"} {"mnemonic": "cpp", "architecture": "ARMv8-A", "full_name": "Cache Prefetch Prediction Pruning", "summary": "Prevents cache prefetch prediction past this instruction.", "syntax": "CPPP ", "encoding": {"format": "System", "binary_pattern": "1101010100 | 0 | 01 | 011 | 0111 | 0011 | 111 | Rt", "hex_opcode": "0xD50B73E0", "visual_parts": [{"raw": "1101010100", "clean": "1101010100"}, {"raw": "0", "clean": "0"}, {"raw": "01", "clean": "01"}, {"raw": "011", "clean": "011"}, {"raw": "0111", "clean": "0111"}, {"raw": "0011", "clean": "0011"}, {"raw": "111", "clean": "111"}, {"raw": "Rt", "clean": "Rt"}], "bit_positions": "31:22 | 21 | 20:19 | 18:16 | 15:12 | 11:8 | 7:5 | 4:0"}, "operands": [{"name": "Xt", "desc": "Reg"}], "extension": "FEAT_CPP", "description": "Prevents cache prefetch prediction from reordering beyond this instruction, allowing precise control over cache prefetch behavior. This is an AArch64-only instruction requiring FEAT_CPP (Cache Prefetch Prediction). The source register Xt is ignored; the instruction acts as a prefetch prediction barrier. No condition flags are affected.", "example": "CPPP x3", "pseudocode": "Cache_Prefetch_Prediction_Barrier()"} {"mnemonic": "rcwswpp", "architecture": "ARMv8-A", "full_name": "Read Check Write Swap Pair", "summary": "Atomically swaps a 128-bit register pair with a checked descriptor in memory (Translation Hardening).", "syntax": "RCWSWPP , , []", "encoding": {"format": "Atomic", "binary_pattern": "0 | 0 | 011001 | 0 | 0 | 1 | Rt2 | 1 | 010 | 00 | Rn | Rt", "hex_opcode": "0x1920A000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "011001", "clean": "011001"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "Rt2", "clean": "Rt2"}, {"raw": "1", "clean": "1"}, {"raw": "010", "clean": "010"}, {"raw": "00", "clean": "00"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rt", "clean": "Rt"}], "bit_positions": "31 | 30 | 29:24 | 23 | 22 | 21 | 20:16 | 15 | 14:12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Xt", "desc": "Data/Status"}, {"name": "Xt+1", "desc": "Second register of the data pair"}, {"name": "Xn", "desc": "Address"}], "extension": "FEAT_THE (Hardening)", "description": "Atomically reads a 128-bit translation table descriptor from memory, checks its validity, and conditionally writes it back with hardening constraints (FEAT_THE). The instruction requires 128-bit alignment and is available only in AArch64. Acquire-Release semantics are not applied; results are returned in a pair of 64-bit registers with status flags.", "example": "RCWSWPP x2, x3, [x1]", "pseudocode": "address ← Xn; data ← Mem[address, 16]; ValidateAndProcess(data); if validated then Mem[address, 16] ← data; Xt ← data[63:0]; Xt+1 ← data[127:64];"} {"mnemonic": "ldff1b", "architecture": "ARMv8-A", "full_name": "SVE Load First-Fault Contiguous Bytes", "summary": "Loads bytes speculatively; suppresses faults after the first active element.", "syntax": "LDFF1B { .B }, /Z, []", "encoding": {"format": "SVE Load", "binary_pattern": "1010010 | 000 | 0 | Rm | 011 | Pg | Rn | Zt", "hex_opcode": "0xA4006000", "visual_parts": [{"raw": "1010010", "clean": "1010010"}, {"raw": "000", "clean": "000"}, {"raw": "0", "clean": "0"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "011", "clean": "011"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Zt", "clean": "Zt"}], "bit_positions": "31:25 | 24:22 | 21 | 20:16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Zt", "desc": "Transfer scalable vector register (SVE load/store)"}, {"name": "Pg", "desc": "Predicate"}, {"name": "Xn", "desc": "First source / base 64-bit integer register"}], "extension": "SVE", "description": "Loads bytes from memory into a scalable vector register with first-fault semantics; subsequent faults are suppressed if any active element has already been loaded. Only elements where the predicate is true are loaded. This instruction is AArch64-only and requires SVE. No condition flags are set.", "example": "LDFF1B p0/m/Z, [x1]", "pseudocode": "for i ← 0 to (VL/8 - 1) do if Pg[i] then Zt[i*8+7:i*8] ← [Xn + i]; faulted ← false; end if; if fault_occurs and faulted then suppress_fault; faulted ← true; end if; end for"} {"mnemonic": "ldff1h", "architecture": "ARMv8-A", "full_name": "SVE Load First-Fault Contiguous Halfwords", "summary": "Loads halfwords speculatively; suppresses faults after the first active element.", "syntax": "LDFF1H { .H }, /Z, []", "encoding": {"format": "SVE Load", "binary_pattern": "1010010 | 010 | 1 | Rm | 011 | Pg | Rn | Zt", "hex_opcode": "0xA4A06000", "visual_parts": [{"raw": "1010010", "clean": "1010010"}, {"raw": "010", "clean": "010"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "011", "clean": "011"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Zt", "clean": "Zt"}], "bit_positions": "31:25 | 24:22 | 21 | 20:16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Zt", "desc": "Transfer scalable vector register (SVE load/store)"}, {"name": "Pg", "desc": "Predicate"}, {"name": "Xn", "desc": "First source / base 64-bit integer register"}], "extension": "SVE", "description": "Loads halfwords from memory into a scalable vector register with first-fault semantics; subsequent faults are suppressed if any active element has already been loaded. Only elements where the predicate is true are loaded. This instruction is AArch64-only and requires SVE. No condition flags are set.", "example": "LDFF1H p0/m/Z, [x1]", "pseudocode": "for i ← 0 to (VL/16 - 1) do if Pg[i] then Zt[i*16+15:i*16] ← [Xn + i*2]; faulted ← false; end if; if fault_occurs and faulted then suppress_fault; faulted ← true; end if; end for"} {"mnemonic": "ldff1w", "architecture": "ARMv8-A", "full_name": "SVE Load First-Fault Contiguous Words", "summary": "Loads words speculatively; suppresses faults after the first active element.", "syntax": "LDFF1W { .S }, /Z, []", "encoding": {"format": "SVE Load", "binary_pattern": "1000010 | 1 | 0 | xs | 0 | Zm | 0 | 1 | 1 | Pg | Rn | Zt", "hex_opcode": "0x85006000", "visual_parts": [{"raw": "1000010", "clean": "1000010"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "xs", "clean": "xs"}, {"raw": "0", "clean": "0"}, {"raw": "Zm", "clean": "Zm"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Zt", "clean": "Zt"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21 | 20:16 | 15 | 14 | 13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Zt", "desc": "Transfer scalable vector register (SVE load/store)"}, {"name": "Pg", "desc": "Predicate"}, {"name": "Xn", "desc": "First source / base 64-bit integer register"}], "extension": "SVE", "description": "Loads words from memory into a scalable vector register with first-fault semantics; subsequent faults are suppressed if any active element has already been loaded. Only elements where the predicate is true are loaded. This instruction is AArch64-only and requires SVE. No condition flags are set.", "example": "LDFF1W p0/m/Z, [x1]", "pseudocode": "for i ← 0 to (VL/32 - 1) do if Pg[i] then Zt[i*32+31:i*32] ← [Xn + i*4]; faulted ← false; end if; if fault_occurs and faulted then suppress_fault; faulted ← true; end if; end for"} {"mnemonic": "ldff1d", "architecture": "ARMv8-A", "full_name": "SVE Load First-Fault Contiguous Doublewords", "summary": "Loads doublewords speculatively; suppresses faults after the first active element.", "syntax": "LDFF1D { .D }, /Z, []", "encoding": {"format": "SVE Load", "binary_pattern": "1100010 | 1 | 1 | 10 | Zm | 1 | 1 | 1 | Pg | Rn | Zt", "hex_opcode": "0xC5C0E000", "visual_parts": [{"raw": "1100010", "clean": "1100010"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "10", "clean": "10"}, {"raw": "Zm", "clean": "Zm"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Zt", "clean": "Zt"}], "bit_positions": "31:25 | 24 | 23 | 22:21 | 20:16 | 15 | 14 | 13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Zt", "desc": "Transfer scalable vector register (SVE load/store)"}, {"name": "Pg", "desc": "Predicate"}, {"name": "Xn", "desc": "First source / base 64-bit integer register"}], "extension": "SVE", "description": "Loads doublewords from memory into a scalable vector register with first-fault semantics; subsequent faults are suppressed if any active element has already been loaded. Only elements where the predicate is true are loaded. This instruction is AArch64-only and requires SVE. No condition flags are set.", "example": "LDFF1D p0/m/Z, [x1]", "pseudocode": "for i ← 0 to (VL/64 - 1) do if Pg[i] then Zt[i*64+63:i*64] ← [Xn + i*8]; faulted ← false; end if; if fault_occurs and faulted then suppress_fault; faulted ← true; end if; end for"} {"mnemonic": "ldnf1b", "architecture": "ARMv8-A", "full_name": "SVE Load Non-Fault Contiguous Bytes", "summary": "Loads bytes without faulting; returns 0 if fault occurs.", "syntax": "LDNF1B { .B }, /Z, []", "encoding": {"format": "SVE Load", "binary_pattern": "1010010 | 000 | 0 | 1 | imm4 | 101 | Pg | Rn | Zt", "hex_opcode": "0xA410A000", "visual_parts": [{"raw": "1010010", "clean": "1010010"}, {"raw": "000", "clean": "000"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "imm4", "clean": "imm4"}, {"raw": "101", "clean": "101"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Zt", "clean": "Zt"}], "bit_positions": "31:25 | 24:22 | 21 | 20 | 19:16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Zt", "desc": "Transfer scalable vector register (SVE load/store)"}, {"name": "Pg", "desc": "Predicate"}, {"name": "Xn", "desc": "First source / base 64-bit integer register"}], "extension": "SVE", "description": "Loads bytes from memory into a scalable vector register without raising faults; elements that would fault are loaded as zero. Only elements where the predicate is true are accessed. This instruction is AArch64-only and requires SVE. No condition flags are set.", "example": "LDNF1B p0/m/Z, [x1]", "pseudocode": "for i ← 0 to (VL/8 - 1) do if Pg[i] then if fault_would_occur then Zt[i*8+7:i*8] ← 0; else Zt[i*8+7:i*8] ← [Xn + i]; end if; end if; end for"} {"mnemonic": "ldnf1h", "architecture": "ARMv8-A", "full_name": "SVE Load Non-Fault Contiguous Halfwords", "summary": "Loads halfwords without faulting.", "syntax": "LDNF1H { .H }, /Z, []", "encoding": {"format": "SVE Load", "binary_pattern": "1010010 | 010 | 1 | 1 | imm4 | 101 | Pg | Rn | Zt", "hex_opcode": "0xA4B0A000", "visual_parts": [{"raw": "1010010", "clean": "1010010"}, {"raw": "010", "clean": "010"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "imm4", "clean": "imm4"}, {"raw": "101", "clean": "101"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Zt", "clean": "Zt"}], "bit_positions": "31:25 | 24:22 | 21 | 20 | 19:16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Zt", "desc": "Transfer scalable vector register (SVE load/store)"}, {"name": "Pg", "desc": "Predicate"}, {"name": "Xn", "desc": "First source / base 64-bit integer register"}], "extension": "SVE", "description": "Loads halfwords from memory into a scalable vector register without raising faults; elements that would fault are loaded as zero. Only elements where the predicate is true are accessed. This instruction is AArch64-only and requires SVE. No condition flags are set.", "example": "LDNF1H p0/m/Z, [x1]", "pseudocode": "for i ← 0 to (VL/16 - 1) do if Pg[i] then if fault_would_occur then Zt[i*16+15:i*16] ← 0; else Zt[i*16+15:i*16] ← [Xn + i*2]; end if; end if; end for"} {"mnemonic": "ldnf1w", "architecture": "ARMv8-A", "full_name": "SVE Load Non-Fault Contiguous Words", "summary": "Loads words without faulting.", "syntax": "LDNF1W { .S }, /Z, []", "encoding": {"format": "SVE Load", "binary_pattern": "1010010 | 101 | 0 | 1 | imm4 | 101 | Pg | Rn | Zt", "hex_opcode": "0xA550A000", "visual_parts": [{"raw": "1010010", "clean": "1010010"}, {"raw": "101", "clean": "101"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "imm4", "clean": "imm4"}, {"raw": "101", "clean": "101"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Zt", "clean": "Zt"}], "bit_positions": "31:25 | 24:22 | 21 | 20 | 19:16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Zt", "desc": "Transfer scalable vector register (SVE load/store)"}, {"name": "Pg", "desc": "Predicate"}, {"name": "Xn", "desc": "First source / base 64-bit integer register"}], "extension": "SVE", "description": "Loads words from memory into a scalable vector register without raising faults; elements that would fault are loaded as zero. Only elements where the predicate is true are accessed. This instruction is AArch64-only and requires SVE. No condition flags are set.", "example": "LDNF1W p0/m/Z, [x1]", "pseudocode": "for i ← 0 to (VL/32 - 1) do if Pg[i] then if fault_would_occur then Zt[i*32+31:i*32] ← 0; else Zt[i*32+31:i*32] ← [Xn + i*4]; end if; end if; end for"} {"mnemonic": "ldnf1d", "architecture": "ARMv8-A", "full_name": "SVE Load Non-Fault Contiguous Doublewords", "summary": "Loads doublewords without faulting.", "syntax": "LDNF1D { .D }, /Z, []", "encoding": {"format": "SVE Load", "binary_pattern": "1010010 | 111 | 1 | 1 | imm4 | 101 | Pg | Rn | Zt", "hex_opcode": "0xA5F0A000", "visual_parts": [{"raw": "1010010", "clean": "1010010"}, {"raw": "111", "clean": "111"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "imm4", "clean": "imm4"}, {"raw": "101", "clean": "101"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Zt", "clean": "Zt"}], "bit_positions": "31:25 | 24:22 | 21 | 20 | 19:16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Zt", "desc": "Transfer scalable vector register (SVE load/store)"}, {"name": "Pg", "desc": "Predicate"}, {"name": "Xn", "desc": "First source / base 64-bit integer register"}], "extension": "SVE", "description": "Loads contiguous doublewords (64-bit elements) from memory into a scalable vector register without generating a fault if a load would be out-of-bounds or inaccessible. Only elements where the corresponding predicate bit in Pg is true are loaded; others are zeroed in the destination Zt. This instruction is AArch64-only, requires SVE support, and does not affect condition flags.", "example": "LDNF1D p0/m/Z, [x1]", "pseudocode": "for i = 0 to VL/64-1\n if Pg[i] == 1 then\n Zt.D[i] ← [Xn + (i × 8)]\n else\n Zt.D[i] ← 0\n endif\nendfor"} {"mnemonic": "whilelo", "architecture": "ARMv8-A", "full_name": "SVE While Lower (Unsigned)", "summary": "Generates predicate for unsigned loop (while Xn < Xm).", "syntax": "WHILELO ., , ", "encoding": {"format": "SVE Compare", "binary_pattern": "00100101 | size | 1 | Rm | 000 | sf | 1 | 1 | Rn | 0 | Pd", "hex_opcode": "0x25200C00", "visual_parts": [{"raw": "00100101", "clean": "00100101"}, {"raw": "size", "clean": "size"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "000", "clean": "000"}, {"raw": "sf", "clean": "sf"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "0", "clean": "0"}, {"raw": "Pd", "clean": "Pd"}], "bit_positions": "31:24 | 23:22 | 21 | 20:16 | 15:13 | 12 | 11 | 10 | 9:5 | 4 | 3:0"}, "operands": [{"name": "Pd", "desc": "Destination predicate register (SVE)"}, {"name": "Xn", "desc": "Start"}, {"name": "Xm", "desc": "Limit"}], "extension": "SVE", "description": "Generates a predicate where each element is true if the corresponding loop counter (Xn + element_index) is less than Xm (unsigned comparison). The output predicate Pd has element width determined by (byte, halfword, word, or doubleword). This is an AArch64-only SVE instruction; all condition flags are unaffected.", "example": "WHILELO p0.T, x1, x2", "pseudocode": "element_size ← size_in_bytes()\nfor i = 0 to VL/element_size-1\n if (Xn + i) < Xm then\n Pd[i] ← 1\n else\n Pd[i] ← 0\n endif\nendfor"} {"mnemonic": "whilels", "architecture": "ARMv8-A", "full_name": "SVE While Lower or Same (Unsigned)", "summary": "Generates predicate for unsigned loop (while Xn <= Xm).", "syntax": "WHILELS ., , ", "encoding": {"format": "SVE Compare", "binary_pattern": "00100101 | size | 1 | Rm | 000 | sf | 1 | 1 | Rn | 1 | Pd", "hex_opcode": "0x25200C10", "visual_parts": [{"raw": "00100101", "clean": "00100101"}, {"raw": "size", "clean": "size"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "000", "clean": "000"}, {"raw": "sf", "clean": "sf"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "1", "clean": "1"}, {"raw": "Pd", "clean": "Pd"}], "bit_positions": "31:24 | 23:22 | 21 | 20:16 | 15:13 | 12 | 11 | 10 | 9:5 | 4 | 3:0"}, "operands": [{"name": "Pd", "desc": "Destination predicate register (SVE)"}, {"name": "Xn", "desc": "Start"}, {"name": "Xm", "desc": "Limit"}], "extension": "SVE", "description": "Generates a predicate where each element is true if the corresponding loop counter (Xn + element_index) is less than or equal to Xm (unsigned comparison). The output predicate Pd has element width determined by . This is an AArch64-only SVE instruction; all condition flags are unaffected.", "example": "WHILELS p0.T, x1, x2", "pseudocode": "element_size ← size_in_bytes()\nfor i = 0 to VL/element_size-1\n if (Xn + i) <= Xm then\n Pd[i] ← 1\n else\n Pd[i] ← 0\n endif\nendfor"} {"mnemonic": "whilehi", "architecture": "ARMv8-A", "full_name": "SVE While Higher (Unsigned)", "summary": "Generates predicate for unsigned loop (while Xn > Xm).", "syntax": "WHILEHI ., , ", "encoding": {"format": "SVE Compare", "binary_pattern": "00100101 | size | 1 | Rm | 000 | sf | 1 | 0 | Rn | 1 | Pd", "hex_opcode": "0x25200810", "visual_parts": [{"raw": "00100101", "clean": "00100101"}, {"raw": "size", "clean": "size"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "000", "clean": "000"}, {"raw": "sf", "clean": "sf"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "1", "clean": "1"}, {"raw": "Pd", "clean": "Pd"}], "bit_positions": "31:24 | 23:22 | 21 | 20:16 | 15:13 | 12 | 11 | 10 | 9:5 | 4 | 3:0"}, "operands": [{"name": "Pd", "desc": "Destination predicate register (SVE)"}, {"name": "Xn", "desc": "Start"}, {"name": "Xm", "desc": "Limit"}], "extension": "SVE", "description": "Generates a predicate where each element is true if the corresponding loop counter (Xn + element_index) is greater than Xm (unsigned comparison). The output predicate Pd has element width determined by . This is an AArch64-only SVE instruction; all condition flags are unaffected.", "example": "WHILEHI p0.T, x1, x2", "pseudocode": "element_size ← size_in_bytes()\nfor i = 0 to VL/element_size-1\n if (Xn + i) > Xm then\n Pd[i] ← 1\n else\n Pd[i] ← 0\n endif\nendfor"} {"mnemonic": "whilehs", "architecture": "ARMv8-A", "full_name": "SVE While Higher or Same (Unsigned)", "summary": "Generates predicate for unsigned loop (while Xn >= Xm).", "syntax": "WHILEHS ., , ", "encoding": {"format": "SVE Compare", "binary_pattern": "00100101 | size | 1 | Rm | 000 | sf | 1 | 0 | Rn | 0 | Pd", "hex_opcode": "0x25200800", "visual_parts": [{"raw": "00100101", "clean": "00100101"}, {"raw": "size", "clean": "size"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "000", "clean": "000"}, {"raw": "sf", "clean": "sf"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "0", "clean": "0"}, {"raw": "Pd", "clean": "Pd"}], "bit_positions": "31:24 | 23:22 | 21 | 20:16 | 15:13 | 12 | 11 | 10 | 9:5 | 4 | 3:0"}, "operands": [{"name": "Pd", "desc": "Destination predicate register (SVE)"}, {"name": "Xn", "desc": "Start"}, {"name": "Xm", "desc": "Limit"}], "extension": "SVE", "description": "Generates a predicate where each element is true if the corresponding loop counter (Xn + element_index) is greater than or equal to Xm (unsigned comparison). The output predicate Pd has element width determined by . This is an AArch64-only SVE instruction; all condition flags are unaffected.", "example": "WHILEHS p0.T, x1, x2", "pseudocode": "element_size ← size_in_bytes()\nfor i = 0 to VL/element_size-1\n if (Xn + i) >= Xm then\n Pd[i] ← 1\n else\n Pd[i] ← 0\n endif\nendfor"} {"mnemonic": "cntp", "architecture": "ARMv8-A", "full_name": "SVE Count Active Predicates", "summary": "Counts the number of true elements in a predicate.", "syntax": "CNTP , , .", "encoding": {"format": "SVE Count", "binary_pattern": "00100101 | size | 100 | 00 | 0 | 10 | Pg | 0 | Pn | Rd", "hex_opcode": "0x25208000", "visual_parts": [{"raw": "00100101", "clean": "00100101"}, {"raw": "size", "clean": "size"}, {"raw": "100", "clean": "100"}, {"raw": "00", "clean": "00"}, {"raw": "0", "clean": "0"}, {"raw": "10", "clean": "10"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "0", "clean": "0"}, {"raw": "Pn", "clean": "Pn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31:24 | 23:22 | 21:19 | 18:17 | 16 | 15:14 | 13:10 | 9 | 8:5 | 4:0"}, "operands": [{"name": "Xn", "desc": "Dest GPR"}, {"name": "Pg", "desc": "Mask"}, {"name": "Pn", "desc": "First source predicate register (SVE)"}], "extension": "SVE", "description": "Counts the number of true bits in Pn.T (where the element size determines the predicate width) that are also true in the governing predicate Pg, and writes the 64-bit count to the general-purpose register Xn. This is an AArch64-only SVE instruction; all condition flags are unaffected.", "example": "CNTP x1, p0/m, p1.T", "pseudocode": "count ← 0\nelement_size ← size_in_bytes()\nfor i = 0 to VL/element_size-1\n if Pg[i] == 1 and Pn[i] == 1 then\n count ← count + 1\n endif\nendfor\nXn ← count"} {"mnemonic": "ptest", "architecture": "ARMv8-A", "full_name": "SVE Predicate Test", "summary": "Updates processor flags (NZCV) based on predicate state.", "syntax": "PTEST , .B", "encoding": {"format": "SVE Predicate", "binary_pattern": "00 | 100101 | 0 | 1 | 01 | 000011 | Pg | 0 | Pn | 0 | 0 | 0 | 0 | 0", "hex_opcode": "0x2550C000", "visual_parts": [{"raw": "00", "clean": "00"}, {"raw": "100101", "clean": "100101"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "01", "clean": "01"}, {"raw": "000011", "clean": "000011"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "0", "clean": "0"}, {"raw": "Pn", "clean": "Pn"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}], "bit_positions": "31:30 | 29:24 | 23 | 22 | 21:20 | 19:14 | 13:10 | 9 | 8:5 | 4 | 3 | 2 | 1 | 0"}, "operands": [{"name": "Pg", "desc": "Mask"}, {"name": "Pn", "desc": "First source predicate register (SVE)"}], "extension": "SVE", "description": "Tests the predicate Pn.B (byte-wide elements) under the control of governing predicate Pg and updates the condition flags (N, Z, C, V) to indicate the result. Sets Z=1 if all tested elements are false, C=1 if any tested element is true, N and V are set according to the logical AND and OR of tested bits. This is an AArch64-only SVE instruction.", "example": "PTEST p0/m, p1.B", "pseudocode": "result_any ← 0\nresult_all ← 1\nfor i = 0 to VL/8-1\n if Pg[i] == 1 then\n if Pn[i] == 1 then\n result_any ← 1\n result_all ← result_all AND 1\n else\n result_all ← 0\n endif\n endif\nendfor\nZ ← (result_any == 0)\nC ← result_any\nN ← result_all\nV ← 0"} {"mnemonic": "pfirst", "architecture": "ARMv8-A", "full_name": "SVE Predicate First Active", "summary": "Sets destination predicate to true only at the first active element.", "syntax": "PFIRST .B, , .B", "encoding": {"format": "SVE Predicate", "binary_pattern": "00100101 | 0 | 1 | 011000110000 | 0 | Pg | 0 | Pdn", "hex_opcode": "0x2558C000", "visual_parts": [{"raw": "00100101", "clean": "00100101"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "011000110000", "clean": "011000110000"}, {"raw": "0", "clean": "0"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "0", "clean": "0"}, {"raw": "Pdn", "clean": "Pdn"}], "bit_positions": "31:24 | 23 | 22 | 21:10 | 9 | 8:5 | 4 | 3:0"}, "operands": [{"name": "Pd", "desc": "Dest Pred"}, {"name": "Pg", "desc": "Mask"}, {"name": "Pn", "desc": "First source predicate register (SVE)"}], "extension": "SVE", "description": "Sets the destination predicate Pd.B such that only the first element (in vector order) where both Pg and Pn are true is set to true; all other elements are set to false. This is useful for scalar tail-processing in loops. This is an AArch64-only SVE instruction; all condition flags are unaffected.", "example": "PFIRST p0.B, p0/m, p1.B", "pseudocode": "for i = 0 to VL/8-1\n if Pg[i] == 1 and Pn[i] == 1 then\n Pd[i] ← 1\n break\n else\n Pd[i] ← 0\n endif\nendfor\nfor j = i+1 to VL/8-1\n Pd[j] ← 0\nendfor"} {"mnemonic": "clasta", "architecture": "ARMv8-A", "full_name": "SVE Conditional Last Element After", "summary": "Extracts element after the last active element.", "syntax": "CLASTA , , , .", "encoding": {"format": "SVE Extract", "binary_pattern": "00000101 | size | 11000 | 0 | 101 | Pg | Zm | Rdn", "hex_opcode": "0x0530A000", "visual_parts": [{"raw": "00000101", "clean": "00000101"}, {"raw": "size", "clean": "size"}, {"raw": "11000", "clean": "11000"}, {"raw": "0", "clean": "0"}, {"raw": "101", "clean": "101"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zm", "clean": "Zm"}, {"raw": "Rdn", "clean": "Rdn"}], "bit_positions": "31:24 | 23:22 | 21:17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Rdn", "desc": "Dest/Fallback"}, {"name": "Pg", "desc": "Predicate"}, {"name": "Zm", "desc": "Vector"}], "extension": "SVE", "description": "Extracts the element immediately after the last active element (as determined by the predicate) from a SVE vector and writes it to a scalar register; if no active elements exist, the destination register is unchanged. This instruction operates only in AArch64 state and does not modify the condition flags.", "example": "CLASTA r0, p0/m, r0, z2.s.T", "pseudocode": "activecount ← CountActiveLanes(Pg, esize)\nif activecount == VL/esize then\n Rdn ← Zm[0]\nelse if activecount > 0 then\n Rdn ← Zm[activecount]\nelse\n Rdn ← Rdn"} {"mnemonic": "clastb", "architecture": "ARMv8-A", "full_name": "SVE Conditional Last Element Before", "summary": "Extracts the last active element.", "syntax": "CLASTB , , , .", "encoding": {"format": "SVE Extract", "binary_pattern": "00000101 | size | 11000 | 1 | 101 | Pg | Zm | Rdn", "hex_opcode": "0x0531A000", "visual_parts": [{"raw": "00000101", "clean": "00000101"}, {"raw": "size", "clean": "size"}, {"raw": "11000", "clean": "11000"}, {"raw": "1", "clean": "1"}, {"raw": "101", "clean": "101"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zm", "clean": "Zm"}, {"raw": "Rdn", "clean": "Rdn"}], "bit_positions": "31:24 | 23:22 | 21:17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Rdn", "desc": "Dest/Fallback"}, {"name": "Pg", "desc": "Predicate"}, {"name": "Zm", "desc": "Vector"}], "extension": "SVE", "description": "Extracts the last active element (as determined by the predicate) from a SVE vector and writes it to a scalar register; if no active elements exist, the destination register is unchanged. This instruction operates only in AArch64 state and does not modify the condition flags.", "example": "CLASTB r0, p0/m, r0, z2.s.T", "pseudocode": "activecount ← CountActiveLanes(Pg, esize)\nif activecount > 0 then\n Rdn ← Zm[activecount - 1]\nelse\n Rdn ← Rdn"} {"mnemonic": "lasta", "architecture": "ARMv8-A", "full_name": "SVE Extract Last Element After", "summary": "Extracts element after last active (SIMD scalar destination).", "syntax": "LASTA ., , .", "encoding": {"format": "SVE Extract", "binary_pattern": "00000101 | size | 10001 | 0 | 100 | Pg | Zn | Vd", "hex_opcode": "0x05228000", "visual_parts": [{"raw": "00000101", "clean": "00000101"}, {"raw": "size", "clean": "size"}, {"raw": "10001", "clean": "10001"}, {"raw": "0", "clean": "0"}, {"raw": "100", "clean": "100"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Vd", "clean": "Vd"}], "bit_positions": "31:24 | 23:22 | 21:17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Vd", "desc": "Dest Scalar"}, {"name": "Pg", "desc": "Predicate"}, {"name": "Zn", "desc": "Vector"}], "extension": "SVE", "description": "Extracts the element immediately after the last active element (as determined by the predicate) from a SVE vector and writes it to a SIMD scalar register; if no active elements exist, the destination register is unchanged. This instruction operates only in AArch64 state and does not modify the condition flags.", "example": "LASTA v0.4s.T, p0/m, z1.s.T", "pseudocode": "activecount ← CountActiveLanes(Pg, esize)\nif activecount == VL/esize then\n Vd ← Zn[0]\nelse if activecount > 0 then\n Vd ← Zn[activecount]\nelse\n Vd ← Vd"} {"mnemonic": "lastb", "architecture": "ARMv8-A", "full_name": "SVE Extract Last Element Before", "summary": "Extracts last active element (SIMD scalar destination).", "syntax": "LASTB ., , .", "encoding": {"format": "SVE Extract", "binary_pattern": "00000101 | size | 10001 | 1 | 100 | Pg | Zn | Vd", "hex_opcode": "0x05238000", "visual_parts": [{"raw": "00000101", "clean": "00000101"}, {"raw": "size", "clean": "size"}, {"raw": "10001", "clean": "10001"}, {"raw": "1", "clean": "1"}, {"raw": "100", "clean": "100"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Vd", "clean": "Vd"}], "bit_positions": "31:24 | 23:22 | 21:17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Vd", "desc": "Dest Scalar"}, {"name": "Pg", "desc": "Predicate"}, {"name": "Zn", "desc": "Vector"}], "extension": "SVE", "description": "Extracts the last active element (as determined by the predicate) from a SVE vector and writes it to a SIMD scalar register; if no active elements exist, the destination register is unchanged. This instruction operates only in AArch64 state and does not modify the condition flags.", "example": "LASTB v0.4s.T, p0/m, z1.s.T", "pseudocode": "activecount ← CountActiveLanes(Pg, esize)\nif activecount > 0 then\n Vd ← Zn[activecount - 1]\nelse\n Vd ← Vd"} {"mnemonic": "insr", "architecture": "ARMv8-A", "full_name": "SVE Insert Scalar", "summary": "Inserts scalar into bottom of vector, shifting other elements up.", "syntax": "INSR ., ", "encoding": {"format": "SVE Move", "binary_pattern": "00000101 | size | 100100001110 | Rm | Zdn", "hex_opcode": "0x05243800", "visual_parts": [{"raw": "00000101", "clean": "00000101"}, {"raw": "size", "clean": "size"}, {"raw": "100100001110", "clean": "100100001110"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "Zdn", "clean": "Zdn"}], "bit_positions": "31:24 | 23:22 | 21:10 | 9:5 | 4:0"}, "operands": [{"name": "Zdn", "desc": "Combined destination/source scalable vector register (SVE)"}, {"name": "Rm", "desc": "Scalar Src"}], "extension": "SVE", "description": "Inserts a scalar register value into the bottom element of a SVE vector, shifting all other elements upward (toward higher element indices), with the top element discarded. This instruction operates only in AArch64 state and does not modify the condition flags.", "example": "INSR z0.s.T, Rm", "pseudocode": "elements ← VL / esize\nfor i = elements - 1 downto 1\n Zdn[i] ← Zdn[i-1]\nZdn[0] ← Rm"} {"mnemonic": "ext", "architecture": "ARMv8-A", "full_name": "SVE Extract Vector", "summary": "Extracts a vector from a pair (sliding window) using immediate byte index.", "syntax": "EXT ., ., ., #", "encoding": {"format": "SVE Permute", "binary_pattern": "00000101001 | imm8h | 000 | imm8l | Zm | Zdn", "hex_opcode": "0x05200000", "visual_parts": [{"raw": "00000101001", "clean": "00000101001"}, {"raw": "imm8h", "clean": "imm8h"}, {"raw": "000", "clean": "000"}, {"raw": "imm8l", "clean": "imm8l"}, {"raw": "Zm", "clean": "Zm"}, {"raw": "Zdn", "clean": "Zdn"}], "bit_positions": "31:21 | 20:16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Zdn", "desc": "Dest/Low"}, {"name": "Zm", "desc": "High"}, {"name": "imm", "desc": "Index"}], "extension": "SVE", "description": "Extracts a contiguous sequence of bytes from the concatenation of two SVE vectors (the low vector followed by the high vector) starting at a byte offset, and places the result in the destination vector. This instruction operates only in AArch64 state and does not modify the condition flags.", "example": "EXT z0.s.T, z0.s.T, z2.s.T, #16", "pseudocode": "offset ← imm\nresult ← Concatenate(Zdn, Zm)[offset:offset + (VL/8) - 1]\nZdn ← result"} {"mnemonic": "rev", "architecture": "ARMv8-A", "full_name": "SVE Reverse Vector", "summary": "Reverses the order of elements in the vector.", "syntax": "REV ., .", "encoding": {"format": "SVE Permute", "binary_pattern": "00000101 | size | 111000001110 | Zn | Zd", "hex_opcode": "0x05383800", "visual_parts": [{"raw": "00000101", "clean": "00000101"}, {"raw": "size", "clean": "size"}, {"raw": "111000001110", "clean": "111000001110"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Zd", "clean": "Zd"}], "bit_positions": "31:24 | 23:22 | 21:10 | 9:5 | 4:0"}, "operands": [{"name": "Zd", "desc": "Destination scalable vector register (SVE)"}, {"name": "Zn", "desc": "First source scalable vector register (SVE)"}], "extension": "SVE", "description": "Reverses the order of elements within a SVE vector; the element at index 0 is moved to the last position, and the last element is moved to index 0. This instruction operates only in AArch64 state and does not modify the condition flags.", "example": "REV z0.s.T, z1.s.T", "pseudocode": "elements ← VL / esize\nfor i = 0 to elements - 1\n Zd[i] ← Zn[elements - 1 - i]"} {"mnemonic": "revb", "architecture": "ARMv8-A", "full_name": "SVE Reverse Bytes in Elements", "summary": "Reverses bytes within 16/32/64-bit elements.", "syntax": "REVB ., /M, .", "encoding": {"format": "SVE Permute", "binary_pattern": "00000101 | size | 1001 | 0 | 0 | 100 | Pg | Zn | Zd", "hex_opcode": "0x05248000", "visual_parts": [{"raw": "00000101", "clean": "00000101"}, {"raw": "size", "clean": "size"}, {"raw": "1001", "clean": "1001"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "100", "clean": "100"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Zd", "clean": "Zd"}], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Zd", "desc": "Destination scalable vector register (SVE)"}, {"name": "Pg", "desc": "Mask"}, {"name": "Zn", "desc": "First source scalable vector register (SVE)"}], "extension": "SVE", "description": "Reverses the byte order within each element of a SVE vector under predicate control; for 16-bit elements 2 bytes are reversed, for 32-bit elements 4 bytes, and for 64-bit elements 8 bytes. This instruction operates only in AArch64 state and does not modify the condition flags.", "example": "REVB z0.s.T, p0/m/M, z1.s.T", "pseudocode": "elements ← VL / esize\nfor i = 0 to elements - 1\n if Pg[i] then\n Zd[i] ← ReverseBytes(Zn[i], esize)\n else\n Zd[i] ← Zd[i]"} {"mnemonic": "revh", "architecture": "ARMv8-A", "full_name": "SVE Reverse Halfwords in Elements", "summary": "Reverses halfwords within 32/64-bit elements.", "syntax": "REVH ., /M, .", "encoding": {"format": "SVE Permute", "binary_pattern": "00000101 | size | 1001 | 0 | 1 | 100 | Pg | Zn | Zd", "hex_opcode": "0x05258000", "visual_parts": [{"raw": "00000101", "clean": "00000101"}, {"raw": "size", "clean": "size"}, {"raw": "1001", "clean": "1001"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "100", "clean": "100"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Zd", "clean": "Zd"}], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Zd", "desc": "Destination scalable vector register (SVE)"}, {"name": "Pg", "desc": "Mask"}, {"name": "Zn", "desc": "First source scalable vector register (SVE)"}], "extension": "SVE", "description": "Reverses the byte order of halfwords (16-bit elements) within 32-bit or 64-bit SVE vector elements, operating under predicate control. No condition flags are affected. This instruction is AArch64-only and available with the SVE extension; it performs element-wise reversals where each 32-bit or 64-bit element has its constituent halfwords byte-reversed in place.", "example": "REVH z0.s.T, p0/m/M, z1.s.T", "pseudocode": "for i = 0 to VL/esize-1\n if Pg[i] then\n case esize of\n 32: Zd[i+1:i] ← reverse_halfwords_in_32bit(Zn[i+1:i])\n 64: Zd[i+1:i] ← reverse_halfwords_in_64bit(Zn[i+1:i])\n else\n Zd[i+1:i] ← Zd[i+1:i]"} {"mnemonic": "revw", "architecture": "ARMv8-A", "full_name": "SVE Reverse Words in Elements", "summary": "Reverses words within 64-bit elements.", "syntax": "REVW .D, /M, .D", "encoding": {"format": "SVE Permute", "binary_pattern": "00000101 | size | 1001 | 1 | 0 | 100 | Pg | Zn | Zd", "hex_opcode": "0x05268000", "visual_parts": [{"raw": "00000101", "clean": "00000101"}, {"raw": "size", "clean": "size"}, {"raw": "1001", "clean": "1001"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "100", "clean": "100"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Zd", "clean": "Zd"}], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Zd", "desc": "Destination scalable vector register (SVE)"}, {"name": "Pg", "desc": "Mask"}, {"name": "Zn", "desc": "First source scalable vector register (SVE)"}], "extension": "SVE", "description": "Reverses the byte order of words (32-bit elements) within 64-bit SVE vector elements, operating under predicate control. No condition flags are affected. This instruction is AArch64-only and available with the SVE extension; it swaps the two 32-bit words in each 64-bit element.", "example": "REVW z0.s.D, p0/m/M, z1.s.D", "pseudocode": "for i = 0 to VL/64-1\n if Pg[i] then\n Zd[i+1:i] ← {Zn[i+31:i], Zn[i+63:i+32]}\n else\n Zd[i+1:i] ← Zd[i+1:i]"} {"mnemonic": "rbit", "architecture": "ARMv8-A", "full_name": "SVE Reverse Bits", "summary": "Reverses bits in each element.", "syntax": "RBIT ., /M, .", "encoding": {"format": "SVE Permute", "binary_pattern": "00000101 | size | 1001 | 1 | 1 | 100 | Pg | Zn | Zd", "hex_opcode": "0x05278000", "visual_parts": [{"raw": "00000101", "clean": "00000101"}, {"raw": "size", "clean": "size"}, {"raw": "1001", "clean": "1001"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "100", "clean": "100"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Zd", "clean": "Zd"}], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Zd", "desc": "Destination scalable vector register (SVE)"}, {"name": "Pg", "desc": "Mask"}, {"name": "Zn", "desc": "First source scalable vector register (SVE)"}], "extension": "SVE", "description": "Reverses the bit order within each SVE vector element, operating under predicate control. No condition flags are affected. This instruction is AArch64-only and available with the SVE extension; each element's bits are reversed such that bit 0 becomes the MSB and the MSB becomes bit 0.", "example": "RBIT z0.s.T, p0/m/M, z1.s.T", "pseudocode": "for i = 0 to VL/esize-1\n if Pg[i] then\n Zd[i+1:i] ← reverse_bits(Zn[i+1:i], esize)\n else\n Zd[i+1:i] ← Zd[i+1:i]"} {"mnemonic": "sunpklo", "architecture": "ARMv8-A", "full_name": "SVE Signed Unpack Low", "summary": "Unpacks and sign-extends lower half of vector elements.", "syntax": "SUNPKLO ., .", "encoding": {"format": "SVE Permute", "binary_pattern": "00000101 | size | 1100 | 0 | 0 | 001110 | Zn | Zd", "hex_opcode": "0x05303800", "visual_parts": [{"raw": "00000101", "clean": "00000101"}, {"raw": "size", "clean": "size"}, {"raw": "1100", "clean": "1100"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "001110", "clean": "001110"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Zd", "clean": "Zd"}], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Zd", "desc": "Destination scalable vector register (SVE)"}, {"name": "Zn", "desc": "First source scalable vector register (SVE)"}], "extension": "SVE", "description": "Unpacks the lower half of each source element and sign-extends it to the destination element size in SVE vectors. No condition flags are affected. This instruction is AArch64-only and available with the SVE extension; destination elements are twice the width of source elements, with sign extension applied to the lower elements.", "example": "SUNPKLO z0.s.T, z1.s.Tb", "pseudocode": "for i = 0 to VL/esize_dst-1\n Zd[i+1:i] ← sign_extend(Zn[i+esize_src/2-1:i], esize_dst)"} {"mnemonic": "sunpkhi", "architecture": "ARMv8-A", "full_name": "SVE Signed Unpack High", "summary": "Unpacks and sign-extends upper half of vector elements.", "syntax": "SUNPKHI ., .", "encoding": {"format": "SVE Permute", "binary_pattern": "00000101 | size | 1100 | 0 | 1 | 001110 | Zn | Zd", "hex_opcode": "0x05313800", "visual_parts": [{"raw": "00000101", "clean": "00000101"}, {"raw": "size", "clean": "size"}, {"raw": "1100", "clean": "1100"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "001110", "clean": "001110"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Zd", "clean": "Zd"}], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Zd", "desc": "Destination scalable vector register (SVE)"}, {"name": "Zn", "desc": "First source scalable vector register (SVE)"}], "extension": "SVE", "description": "Unpacks the upper half of each source element and sign-extends it to the destination element size in SVE vectors. No condition flags are affected. This instruction is AArch64-only and available with the SVE extension; destination elements are twice the width of source elements, with sign extension applied to the upper elements.", "example": "SUNPKHI z0.s.T, z1.s.Tb", "pseudocode": "for i = 0 to VL/esize_dst-1\n Zd[i+1:i] ← sign_extend(Zn[i+esize_src-1:i+esize_src/2], esize_dst)"} {"mnemonic": "uunpklo", "architecture": "ARMv8-A", "full_name": "SVE Unsigned Unpack Low", "summary": "Unpacks and zero-extends lower half of vector elements.", "syntax": "UUNPKLO ., .", "encoding": {"format": "SVE Permute", "binary_pattern": "00000101 | size | 1100 | 1 | 0 | 001110 | Zn | Zd", "hex_opcode": "0x05323800", "visual_parts": [{"raw": "00000101", "clean": "00000101"}, {"raw": "size", "clean": "size"}, {"raw": "1100", "clean": "1100"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "001110", "clean": "001110"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Zd", "clean": "Zd"}], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Zd", "desc": "Destination scalable vector register (SVE)"}, {"name": "Zn", "desc": "First source scalable vector register (SVE)"}], "extension": "SVE", "description": "Unpacks the lower half of each source element and zero-extends it to the destination element size in SVE vectors. No condition flags are affected. This instruction is AArch64-only and available with the SVE extension; destination elements are twice the width of source elements, with zero extension applied to the lower elements.", "example": "UUNPKLO z0.s.T, z1.s.Tb", "pseudocode": "for i = 0 to VL/esize_dst-1\n Zd[i+1:i] ← zero_extend(Zn[i+esize_src/2-1:i], esize_dst)"} {"mnemonic": "uunpkhi", "architecture": "ARMv8-A", "full_name": "SVE Unsigned Unpack High", "summary": "Unpacks and zero-extends upper half of vector elements.", "syntax": "UUNPKHI ., .", "encoding": {"format": "SVE Permute", "binary_pattern": "00000101 | size | 1100 | 1 | 1 | 001110 | Zn | Zd", "hex_opcode": "0x05333800", "visual_parts": [{"raw": "00000101", "clean": "00000101"}, {"raw": "size", "clean": "size"}, {"raw": "1100", "clean": "1100"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "001110", "clean": "001110"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Zd", "clean": "Zd"}], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Zd", "desc": "Destination scalable vector register (SVE)"}, {"name": "Zn", "desc": "First source scalable vector register (SVE)"}], "extension": "SVE", "description": "Unpacks the upper half of each source element and zero-extends it to the destination element size in SVE vectors. No condition flags are affected. This instruction is AArch64-only and available with the SVE extension; destination elements are twice the width of source elements, with zero extension applied to the upper elements.", "example": "UUNPKHI z0.s.T, z1.s.Tb", "pseudocode": "for i = 0 to VL/esize_dst-1\n Zd[i+1:i] ← zero_extend(Zn[i+esize_src-1:i+esize_src/2], esize_dst)"} {"mnemonic": "sdot", "architecture": "ARMv8-A", "full_name": "SVE Signed Dot Product", "summary": "Computes dot product of signed integers (AI Acceleration).", "syntax": "SDOT ., ., .", "encoding": {"format": "SVE Dot Product", "binary_pattern": "01000100 | size | 0 | Zm | 00000 | 0 | Zn | Zda", "hex_opcode": "0x44000000", "visual_parts": [{"raw": "01000100", "clean": "01000100"}, {"raw": "size", "clean": "size"}, {"raw": "0", "clean": "0"}, {"raw": "Zm", "clean": "Zm"}, {"raw": "00000", "clean": "00000"}, {"raw": "0", "clean": "0"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Zda", "clean": "Zda"}], "bit_positions": "31:24 | 23:22 | 21 | 20:16 | 15:11 | 10 | 9:5 | 4:0"}, "operands": [{"name": "Zda", "desc": "Accumulator"}, {"name": "Zn", "desc": "First source scalable vector register (SVE)"}, {"name": "Zm", "desc": "Second source scalable vector register (SVE)"}], "extension": "SVE", "description": "Computes the dot product of signed integer vectors and accumulates the result into the destination register, supporting AI acceleration. No condition flags are affected. This instruction is AArch64-only and available with the SVE extension; the destination is widened relative to the sources, and the accumulation is added to existing values in Zda.", "example": "SDOT z0.s.T, z1.s.Tb, z2.s.Tb", "pseudocode": "for i = 0 to VL/esize_dst-1\n product ← 0\n for j = 0 to (esize_dst / esize_src) - 1\n product ← product + sign_extend(Zn[i*esize_dst + (j+1)*esize_src - 1 : i*esize_dst + j*esize_src], esize_dst) * sign_extend(Zm[i*esize_dst + (j+1)*esize_src - 1 : i*esize_dst + j*esize_src], esize_dst)\n Zda[i+1:i] ← Zda[i+1:i] + product"} {"mnemonic": "udot", "architecture": "ARMv8-A", "full_name": "SVE Unsigned Dot Product", "summary": "Computes dot product of unsigned integers.", "syntax": "UDOT ., ., .", "encoding": {"format": "SVE Dot Product", "binary_pattern": "01000100 | size | 0 | Zm | 00000 | 1 | Zn | Zda", "hex_opcode": "0x44000400", "visual_parts": [{"raw": "01000100", "clean": "01000100"}, {"raw": "size", "clean": "size"}, {"raw": "0", "clean": "0"}, {"raw": "Zm", "clean": "Zm"}, {"raw": "00000", "clean": "00000"}, {"raw": "1", "clean": "1"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Zda", "clean": "Zda"}], "bit_positions": "31:24 | 23:22 | 21 | 20:16 | 15:11 | 10 | 9:5 | 4:0"}, "operands": [{"name": "Zda", "desc": "Accumulator"}, {"name": "Zn", "desc": "First source scalable vector register (SVE)"}, {"name": "Zm", "desc": "Second source scalable vector register (SVE)"}], "extension": "SVE", "description": "SVE unsigned dot product: accumulates the sum of element-wise products of unsigned integers from Zn and Zm into Zda. The element size of Zn and Zm (Tb) is half that of Zda (T), allowing 2, 4, or 8 products to be summed per destination element depending on the vector length. No condition flags are affected. This is an AArch64-only instruction requiring SVE support.", "example": "UDOT z0.s.T, z1.s.Tb, z2.s.Tb", "pseudocode": "for e = 0 to VL/getElementSize(T)-1\n element_pairs = getElements(Zn[e], Tb) × getElements(Zm[e], Tb)\n Zda[e] ← Zda[e] + sum(element_pairs)\nend for"} {"mnemonic": "smax", "architecture": "ARMv8-A", "full_name": "SVE Signed Maximum", "summary": "Determines maximum signed value per element.", "syntax": "SMAX ., /M, ., .", "encoding": {"format": "SVE Integer Binary", "binary_pattern": "00000100 | size | 001 | 0 | 0 | 0 | 000 | Pg | Zm | Zdn", "hex_opcode": "0x04080000", "visual_parts": [{"raw": "00000100", "clean": "00000100"}, {"raw": "size", "clean": "size"}, {"raw": "001", "clean": "001"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "000", "clean": "000"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zm", "clean": "Zm"}, {"raw": "Zdn", "clean": "Zdn"}], "bit_positions": "31:24 | 23:22 | 21:19 | 18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Zdn", "desc": "Combined destination/source scalable vector register (SVE)"}, {"name": "Pg", "desc": "Mask"}, {"name": "Zm", "desc": "Second source scalable vector register (SVE)"}], "extension": "SVE", "description": "SVE signed maximum: computes the element-wise maximum of two signed integer vectors (Zdn and Zm), writing results to Zdn under predicate mask control (Pg). Only elements where the predicate is active are updated; inactive elements retain their original values in Zdn. No condition flags are affected. This is an AArch64-only instruction requiring SVE support.", "example": "SMAX z0.s.T, p0/m/M, z0.s.T, z2.s.T", "pseudocode": "for e = 0 to VL/getElementSize(T)-1\n if Pg[e] == 1 then\n Zdn[e] ← max_signed(Zdn[e], Zm[e])\n end if\nend for"} {"mnemonic": "smin", "architecture": "ARMv8-A", "full_name": "SVE Signed Minimum", "summary": "Determines minimum signed value per element.", "syntax": "SMIN ., /M, ., .", "encoding": {"format": "SVE Integer Binary", "binary_pattern": "00000100 | size | 001 | 0 | 1 | 0 | 000 | Pg | Zm | Zdn", "hex_opcode": "0x040A0000", "visual_parts": [{"raw": "00000100", "clean": "00000100"}, {"raw": "size", "clean": "size"}, {"raw": "001", "clean": "001"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "000", "clean": "000"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zm", "clean": "Zm"}, {"raw": "Zdn", "clean": "Zdn"}], "bit_positions": "31:24 | 23:22 | 21:19 | 18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Zdn", "desc": "Combined destination/source scalable vector register (SVE)"}, {"name": "Pg", "desc": "Mask"}, {"name": "Zm", "desc": "Second source scalable vector register (SVE)"}], "extension": "SVE", "description": "SVE signed minimum: computes the element-wise minimum of two signed integer vectors (Zdn and Zm), writing results to Zdn under predicate mask control (Pg). Only elements where the predicate is active are updated; inactive elements retain their original values in Zdn. No condition flags are affected. This is an AArch64-only instruction requiring SVE support.", "example": "SMIN z0.s.T, p0/m/M, z0.s.T, z2.s.T", "pseudocode": "for e = 0 to VL/getElementSize(T)-1\n if Pg[e] == 1 then\n Zdn[e] ← min_signed(Zdn[e], Zm[e])\n end if\nend for"} {"mnemonic": "umax", "architecture": "ARMv8-A", "full_name": "SVE Unsigned Maximum", "summary": "Determines maximum unsigned value per element.", "syntax": "UMAX ., /M, ., .", "encoding": {"format": "SVE Integer Binary", "binary_pattern": "00000100 | size | 001 | 0 | 0 | 1 | 000 | Pg | Zm | Zdn", "hex_opcode": "0x04090000", "visual_parts": [{"raw": "00000100", "clean": "00000100"}, {"raw": "size", "clean": "size"}, {"raw": "001", "clean": "001"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "000", "clean": "000"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zm", "clean": "Zm"}, {"raw": "Zdn", "clean": "Zdn"}], "bit_positions": "31:24 | 23:22 | 21:19 | 18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Zdn", "desc": "Combined destination/source scalable vector register (SVE)"}, {"name": "Pg", "desc": "Mask"}, {"name": "Zm", "desc": "Second source scalable vector register (SVE)"}], "extension": "SVE", "description": "SVE unsigned maximum: computes the element-wise maximum of two unsigned integer vectors (Zdn and Zm), writing results to Zdn under predicate mask control (Pg). Only elements where the predicate is active are updated; inactive elements retain their original values in Zdn. No condition flags are affected. This is an AArch64-only instruction requiring SVE support.", "example": "UMAX z0.s.T, p0/m/M, z0.s.T, z2.s.T", "pseudocode": "for e = 0 to VL/getElementSize(T)-1\n if Pg[e] == 1 then\n Zdn[e] ← max_unsigned(Zdn[e], Zm[e])\n end if\nend for"} {"mnemonic": "umin", "architecture": "ARMv8-A", "full_name": "SVE Unsigned Minimum", "summary": "Determines minimum unsigned value per element.", "syntax": "UMIN ., /M, ., .", "encoding": {"format": "SVE Integer Binary", "binary_pattern": "00000100 | size | 001 | 0 | 1 | 1 | 000 | Pg | Zm | Zdn", "hex_opcode": "0x040B0000", "visual_parts": [{"raw": "00000100", "clean": "00000100"}, {"raw": "size", "clean": "size"}, {"raw": "001", "clean": "001"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "000", "clean": "000"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zm", "clean": "Zm"}, {"raw": "Zdn", "clean": "Zdn"}], "bit_positions": "31:24 | 23:22 | 21:19 | 18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Zdn", "desc": "Combined destination/source scalable vector register (SVE)"}, {"name": "Pg", "desc": "Mask"}, {"name": "Zm", "desc": "Second source scalable vector register (SVE)"}], "extension": "SVE", "description": "SVE unsigned minimum: computes the element-wise minimum of two unsigned integer vectors (Zdn and Zm), writing results to Zdn under predicate mask control (Pg). Only elements where the predicate is active are updated; inactive elements retain their original values in Zdn. No condition flags are affected. This is an AArch64-only instruction requiring SVE support.", "example": "UMIN z0.s.T, p0/m/M, z0.s.T, z2.s.T", "pseudocode": "for e = 0 to VL/getElementSize(T)-1\n if Pg[e] == 1 then\n Zdn[e] ← min_unsigned(Zdn[e], Zm[e])\n end if\nend for"} {"mnemonic": "abs", "architecture": "ARMv8-A", "full_name": "SVE Absolute Value", "summary": "Calculates absolute value of integers.", "syntax": "ABS ., /M, .", "encoding": {"format": "SVE Integer Unary", "binary_pattern": "00000100 | size | 010 | 11 | 0 | 101 | Pg | Zn | Zd", "hex_opcode": "0x0416A000", "visual_parts": [{"raw": "00000100", "clean": "00000100"}, {"raw": "size", "clean": "size"}, {"raw": "010", "clean": "010"}, {"raw": "11", "clean": "11"}, {"raw": "0", "clean": "0"}, {"raw": "101", "clean": "101"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Zd", "clean": "Zd"}], "bit_positions": "31:24 | 23:22 | 21:19 | 18:17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Zdn", "desc": "Dest/Src"}, {"name": "Pg", "desc": "Mask"}], "extension": "SVE", "description": "SVE absolute value: computes the element-wise absolute value of signed integers in Zdn, writing results back to Zdn under predicate mask control (Pg). Only elements where the predicate is active are updated; inactive elements retain their original values. No condition flags are affected. This is an AArch64-only instruction requiring SVE support.", "example": "ABS z0.s.T, p0/m/M, z0.s.T", "pseudocode": "for e = 0 to VL/getElementSize(T)-1\n if Pg[e] == 1 then\n Zdn[e] ← abs_signed(Zdn[e])\n end if\nend for"} {"mnemonic": "neg", "architecture": "ARMv8-A", "full_name": "SVE Negate", "summary": "Negates integers.", "syntax": "NEG ., /M, .", "encoding": {"format": "SVE Integer Unary", "binary_pattern": "00000100 | size | 010 | 11 | 1 | 101 | Pg | Zn | Zd", "hex_opcode": "0x0417A000", "visual_parts": [{"raw": "00000100", "clean": "00000100"}, {"raw": "size", "clean": "size"}, {"raw": "010", "clean": "010"}, {"raw": "11", "clean": "11"}, {"raw": "1", "clean": "1"}, {"raw": "101", "clean": "101"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Zd", "clean": "Zd"}], "bit_positions": "31:24 | 23:22 | 21:19 | 18:17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Zdn", "desc": "Dest/Src"}, {"name": "Pg", "desc": "Mask"}], "extension": "SVE", "description": "SVE negate: computes the element-wise negation (two's complement) of integers in Zdn, writing results back to Zdn under predicate mask control (Pg). Only elements where the predicate is active are updated; inactive elements retain their original values. No condition flags are affected. This is an AArch64-only instruction requiring SVE support.", "example": "NEG z0.s.T, p0/m/M, z0.s.T", "pseudocode": "for e = 0 to VL/getElementSize(T)-1\n if Pg[e] == 1 then\n Zdn[e] ← -Zdn[e]\n end if\nend for"} {"mnemonic": "not", "architecture": "ARMv8-A", "full_name": "SVE Bitwise NOT", "summary": "Inverts bits.", "syntax": "NOT ., /M, .", "encoding": {"format": "SVE Integer Unary", "binary_pattern": "00000100 | size | 011 | 11 | 0 | 101 | Pg | Zn | Zd", "hex_opcode": "0x041EA000", "visual_parts": [{"raw": "00000100", "clean": "00000100"}, {"raw": "size", "clean": "size"}, {"raw": "011", "clean": "011"}, {"raw": "11", "clean": "11"}, {"raw": "0", "clean": "0"}, {"raw": "101", "clean": "101"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Zd", "clean": "Zd"}], "bit_positions": "31:24 | 23:22 | 21:19 | 18:17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Zdn", "desc": "Dest/Src"}, {"name": "Pg", "desc": "Mask"}], "extension": "SVE", "description": "SVE bitwise NOT: inverts all bits in each element of Zdn under predicate mask control (Pg), writing the results back to Zdn. Only elements where the predicate is active are updated; inactive elements retain their original values. No condition flags are affected. This is an AArch64-only instruction requiring SVE support.", "example": "NOT z0.s.T, p0/m/M, z0.s.T", "pseudocode": "for e = 0 to VL/getElementSize(T)-1\n if Pg[e] == 1 then\n Zdn[e] ← ~Zdn[e]\n end if\nend for"} {"mnemonic": "sdiv", "architecture": "ARMv8-A", "full_name": "SVE Signed Divide", "summary": "Divides signed integers.", "syntax": "SDIV ., /M, ., .", "encoding": {"format": "SVE Integer Binary", "binary_pattern": "00000100 | size | 0101 | 0 | 0 | 000 | Pg | Zm | Zdn", "hex_opcode": "0x04140000", "visual_parts": [{"raw": "00000100", "clean": "00000100"}, {"raw": "size", "clean": "size"}, {"raw": "0101", "clean": "0101"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "000", "clean": "000"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zm", "clean": "Zm"}, {"raw": "Zdn", "clean": "Zdn"}], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Zdn", "desc": "Dest/Dividend"}, {"name": "Pg", "desc": "Mask"}, {"name": "Zm", "desc": "Divisor"}], "extension": "SVE", "description": "SVE signed integer divide: divides each active element of Zdn (dividend) by the corresponding element of Zm (divisor), storing the quotient back in Zdn. Elements where the predicate is false are left unchanged. No condition flags are affected. This is an SVE-only instruction and does not raise exceptions on division by zero; instead, undefined results are written to inactive elements.", "example": "SDIV z0.s.T, p0/m/M, z0.s.T, z2.s.T", "pseudocode": "for i = 0 to VL-1\n if Pg[i] == '1' then\n Zdn[i] ← Zdn[i] / Zm[i]\n // else Zdn[i] unchanged"} {"mnemonic": "udiv", "architecture": "ARMv8-A", "full_name": "SVE Unsigned Divide", "summary": "Divides unsigned integers.", "syntax": "UDIV ., /M, ., .", "encoding": {"format": "SVE Integer Binary", "binary_pattern": "00000100 | size | 0101 | 0 | 1 | 000 | Pg | Zm | Zdn", "hex_opcode": "0x04150000", "visual_parts": [{"raw": "00000100", "clean": "00000100"}, {"raw": "size", "clean": "size"}, {"raw": "0101", "clean": "0101"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "000", "clean": "000"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zm", "clean": "Zm"}, {"raw": "Zdn", "clean": "Zdn"}], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Zdn", "desc": "Dest/Dividend"}, {"name": "Pg", "desc": "Mask"}, {"name": "Zm", "desc": "Divisor"}], "extension": "SVE", "description": "SVE unsigned integer divide: divides each active element of Zdn (dividend) by the corresponding element of Zm (divisor) as unsigned values, storing the quotient back in Zdn. Elements where the predicate is false are left unchanged. No condition flags are affected. This is an SVE-only instruction and does not raise exceptions on division by zero.", "example": "UDIV z0.s.T, p0/m/M, z0.s.T, z2.s.T", "pseudocode": "for i = 0 to VL-1\n if Pg[i] == '1' then\n Zdn[i] ← UnsignedDivide(Zdn[i], Zm[i])\n // else Zdn[i] unchanged"} {"mnemonic": "fsqrt", "architecture": "ARMv8-A", "full_name": "SVE Floating-Point Square Root", "summary": "Calculates square root of floats.", "syntax": "FSQRT ., /M, .", "encoding": {"format": "SVE FP Unary", "binary_pattern": "01100101 | size | 0011 | 0 | 1 | 101 | Pg | Zn | Zd", "hex_opcode": "0x650DA000", "visual_parts": [{"raw": "01100101", "clean": "01100101"}, {"raw": "size", "clean": "size"}, {"raw": "0011", "clean": "0011"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "101", "clean": "101"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Zd", "clean": "Zd"}], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Zdn", "desc": "Combined destination/source scalable vector register (SVE)"}, {"name": "Pg", "desc": "Mask"}], "extension": "SVE", "description": "SVE floating-point square root: computes the square root of each active element in Zdn and stores the result back in Zdn. Elements where the predicate is false are left unchanged. Floating-point exception flags (IOC, DZC, OFC, UFC, IXC) are updated according to the IEEE 754 standard; no integer condition flags are affected. This is an SVE-only instruction.", "example": "FSQRT z0.s.T, p0/m/M, z0.s.T", "pseudocode": "for i = 0 to VL-1\n if Pg[i] == '1' then\n Zdn[i] ← FPSquareRoot(Zdn[i])\n // else Zdn[i] unchanged\n// FP exception flags updated per IEEE 754"} {"mnemonic": "fabs", "architecture": "ARMv8-A", "full_name": "SVE Floating-Point Absolute Value", "summary": "Calculates absolute value of floats.", "syntax": "FABS ., /M, .", "encoding": {"format": "SVE FP Unary", "binary_pattern": "00000100 | size | 011 | 10 | 0 | 101 | Pg | Zn | Zd", "hex_opcode": "0x041CA000", "visual_parts": [{"raw": "00000100", "clean": "00000100"}, {"raw": "size", "clean": "size"}, {"raw": "011", "clean": "011"}, {"raw": "10", "clean": "10"}, {"raw": "0", "clean": "0"}, {"raw": "101", "clean": "101"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Zd", "clean": "Zd"}], "bit_positions": "31:24 | 23:22 | 21:19 | 18:17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Zdn", "desc": "Combined destination/source scalable vector register (SVE)"}, {"name": "Pg", "desc": "Mask"}], "extension": "SVE", "description": "SVE floating-point absolute value: computes the absolute value of each active element in Zdn and stores the result back in Zdn, clearing the sign bit. Elements where the predicate is false are left unchanged. No condition flags or floating-point exceptions are affected. This is an SVE-only instruction.", "example": "FABS z0.s.T, p0/m/M, z0.s.T", "pseudocode": "for i = 0 to VL-1\n if Pg[i] == '1' then\n Zdn[i] ← FPAbs(Zdn[i])\n // else Zdn[i] unchanged"} {"mnemonic": "fneg", "architecture": "ARMv8-A", "full_name": "SVE Floating-Point Negate", "summary": "Negates floats.", "syntax": "FNEG ., /M, .", "encoding": {"format": "SVE FP Unary", "binary_pattern": "00000100 | size | 011 | 10 | 1 | 101 | Pg | Zn | Zd", "hex_opcode": "0x041DA000", "visual_parts": [{"raw": "00000100", "clean": "00000100"}, {"raw": "size", "clean": "size"}, {"raw": "011", "clean": "011"}, {"raw": "10", "clean": "10"}, {"raw": "1", "clean": "1"}, {"raw": "101", "clean": "101"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Zd", "clean": "Zd"}], "bit_positions": "31:24 | 23:22 | 21:19 | 18:17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Zdn", "desc": "Combined destination/source scalable vector register (SVE)"}, {"name": "Pg", "desc": "Mask"}], "extension": "SVE", "description": "SVE floating-point negate: flips the sign bit of each active element in Zdn and stores the result back in Zdn. Elements where the predicate is false are left unchanged. No condition flags or floating-point exceptions are affected. This is an SVE-only instruction.", "example": "FNEG z0.s.T, p0/m/M, z0.s.T", "pseudocode": "for i = 0 to VL-1\n if Pg[i] == '1' then\n Zdn[i] ← FPNegate(Zdn[i])\n // else Zdn[i] unchanged"} {"mnemonic": "fcadd", "architecture": "ARMv8-A", "full_name": "SVE Floating-Point Complex Add", "summary": "Performs complex addition with rotation.", "syntax": "FCADD ., /M, ., ., #", "encoding": {"format": "SVE FP Complex", "binary_pattern": "01100100 | size | 00000 | rot | 100 | Pg | Zm | Zdn", "hex_opcode": "0x64008000", "visual_parts": [{"raw": "01100100", "clean": "01100100"}, {"raw": "size", "clean": "size"}, {"raw": "00000", "clean": "00000"}, {"raw": "rot", "clean": "rot"}, {"raw": "100", "clean": "100"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zm", "clean": "Zm"}, {"raw": "Zdn", "clean": "Zdn"}], "bit_positions": "31:24 | 23:22 | 21:17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Zdn", "desc": "Combined destination/source scalable vector register (SVE)"}, {"name": "Pg", "desc": "Mask"}, {"name": "Zm", "desc": "Second source scalable vector register (SVE)"}, {"name": "rot", "desc": "Rotation (90, 270)"}], "extension": "SVE", "description": "SVE floating-point complex add: performs a predicate-masked complex addition of Zdn and Zm with a 90° or 270° rotation applied to Zm before addition. For rot=90, computes Zdn + i*Zm; for rot=270, computes Zdn - i*Zm. Elements where the predicate is false are left unchanged. Floating-point exceptions are signaled per IEEE 754. This is an SVE-only instruction.", "example": "FCADD z0.s.T, p0/m/M, z0.s.T, z2.s.T, #rot", "pseudocode": "for i = 0 to VL-1\n if Pg[i] == '1' then\n rotated ← RotateComplex(Zm[i], rot)\n Zdn[i] ← FPAdd(Zdn[i], rotated)\n // else Zdn[i] unchanged"} {"mnemonic": "fcmla", "architecture": "ARMv8-A", "full_name": "SVE Floating-Point Complex Multiply-Add", "summary": "Performs complex multiply-accumulate.", "syntax": "FCMLA ., /M, ., ., #", "encoding": {"format": "SVE FP Complex", "binary_pattern": "01100100 | size | 0 | Zm | 0 | rot | Pg | Zn | Zda", "hex_opcode": "0x64000000", "visual_parts": [{"raw": "01100100", "clean": "01100100"}, {"raw": "size", "clean": "size"}, {"raw": "0", "clean": "0"}, {"raw": "Zm", "clean": "Zm"}, {"raw": "0", "clean": "0"}, {"raw": "rot", "clean": "rot"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Zda", "clean": "Zda"}], "bit_positions": "31:24 | 23:22 | 21 | 20:16 | 15 | 14:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Zda", "desc": "Accumulator scalable vector register (SVE)"}, {"name": "Pg", "desc": "Mask"}, {"name": "Zn", "desc": "First source scalable vector register (SVE)"}, {"name": "Zm", "desc": "Second source scalable vector register (SVE)"}, {"name": "rot", "desc": "Rot"}], "extension": "SVE", "description": "SVE floating-point complex multiply-add: performs a predicate-masked complex multiply-accumulate operation where Zn and Zm are multiplied with rotation, and the result is added to Zda. For each rotation value (0°, 90°, 180°, 270°), a different complex multiplication result is accumulated. Elements where the predicate is false leave Zda unchanged. Floating-point exceptions are signaled per IEEE 754. This is an SVE-only instruction.", "example": "FCMLA z0.s.T, p0/m/M, z1.s.T, z2.s.T, #rot", "pseudocode": "for i = 0 to VL-1\n if Pg[i] == '1' then\n product ← FPComplexMultiply(Zn[i], Zm[i], rot)\n Zda[i] ← FPAdd(Zda[i], product)\n // else Zda[i] unchanged"} {"mnemonic": "saddv", "architecture": "ARMv8-A", "full_name": "SVE Signed Integer Add Reduction", "summary": "Sums all active signed elements into a scalar result.", "syntax": "SADDV , , .", "encoding": {"format": "SVE Reduction", "binary_pattern": "00000100 | size | 0000 | 0 | 0 | 001 | Pg | Zn | Vd", "hex_opcode": "0x04002000", "visual_parts": [{"raw": "00000100", "clean": "00000100"}, {"raw": "size", "clean": "size"}, {"raw": "0000", "clean": "0000"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "001", "clean": "001"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Vd", "clean": "Vd"}], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Vd", "desc": "Dest Scalar"}, {"name": "Pg", "desc": "Mask"}, {"name": "Zn", "desc": "Vector"}], "extension": "SVE", "description": "SVE signed integer add reduction: sums all active signed elements of the SVE vector Zn across the vector length and accumulates the result into the scalar destination Vd, sign-extending to the element width. Only elements where the corresponding predicate bit is set participate in the reduction. No condition flags are affected. This is an SVE-only instruction.", "example": "SADDV v0.4s, p0/m, z1.s.T", "pseudocode": "result ← 0\nfor i = 0 to VL-1\n if Pg[i] == '1' then\n result ← result + SignExtend(Zn[i])\nVd ← result"} {"mnemonic": "smaxv", "architecture": "ARMv8-A", "full_name": "SVE Signed Maximum Reduction", "summary": "Finds max signed element in vector.", "syntax": "SMAXV , , .", "encoding": {"format": "SVE Reduction", "binary_pattern": "00000100 | size | 0010 | 0 | 0 | 001 | Pg | Zn | Vd", "hex_opcode": "0x04082000", "visual_parts": [{"raw": "00000100", "clean": "00000100"}, {"raw": "size", "clean": "size"}, {"raw": "0010", "clean": "0010"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "001", "clean": "001"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Vd", "clean": "Vd"}], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Vd", "desc": "Dest Scalar"}, {"name": "Pg", "desc": "Mask"}, {"name": "Zn", "desc": "Vector"}], "extension": "SVE", "description": "SVE signed maximum reduction: finds the maximum signed element in vector Zn according to predicate mask Pg, and stores the result as a scalar in Vd. The operation reads all active elements from Zn, compares them as signed integers (element size determined by sz), and reduces to a single scalar value. No NZCV flags are affected by this instruction.", "example": "SMAXV v0.4s, p0/m, z1.s.T", "pseudocode": "bits(esize) result = MIN_INT(esize);\nfor i = 0 to VL/esize - 1\n if Pg[i] == '1' then\n element = Zn[i*esize +: esize];\n if element > result (signed) then result = element;\nVd[0 +: esize] ← result;"} {"mnemonic": "umaxv", "architecture": "ARMv8-A", "full_name": "SVE Unsigned Maximum Reduction", "summary": "Finds max unsigned element in vector.", "syntax": "UMAXV , , .", "encoding": {"format": "SVE Reduction", "binary_pattern": "00000100 | size | 0010 | 0 | 1 | 001 | Pg | Zn | Vd", "hex_opcode": "0x04092000", "visual_parts": [{"raw": "00000100", "clean": "00000100"}, {"raw": "size", "clean": "size"}, {"raw": "0010", "clean": "0010"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "001", "clean": "001"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Vd", "clean": "Vd"}], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Vd", "desc": "Dest Scalar"}, {"name": "Pg", "desc": "Mask"}, {"name": "Zn", "desc": "Vector"}], "extension": "SVE", "description": "SVE unsigned maximum reduction: finds the maximum unsigned element in vector Zn according to predicate mask Pg, and stores the result as a scalar in Vd. The operation compares all active elements as unsigned integers (element size determined by sz) and reduces to a single scalar. No NZCV flags are affected by this instruction.", "example": "UMAXV v0.4s, p0/m, z1.s.T", "pseudocode": "bits(esize) result = 0;\nfor i = 0 to VL/esize - 1\n if Pg[i] == '1' then\n element = Zn[i*esize +: esize];\n if element > result (unsigned) then result = element;\nVd[0 +: esize] ← result;"} {"mnemonic": "sminv", "architecture": "ARMv8-A", "full_name": "SVE Signed Minimum Reduction", "summary": "Finds min signed element in vector.", "syntax": "SMINV , , .", "encoding": {"format": "SVE Reduction", "binary_pattern": "00000100 | size | 0010 | 1 | 0 | 001 | Pg | Zn | Vd", "hex_opcode": "0x040A2000", "visual_parts": [{"raw": "00000100", "clean": "00000100"}, {"raw": "size", "clean": "size"}, {"raw": "0010", "clean": "0010"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "001", "clean": "001"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Vd", "clean": "Vd"}], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Vd", "desc": "Dest Scalar"}, {"name": "Pg", "desc": "Mask"}, {"name": "Zn", "desc": "Vector"}], "extension": "SVE", "description": "SVE signed minimum reduction: finds the minimum signed element in vector Zn according to predicate mask Pg, and stores the result as a scalar in Vd. The operation reads all active elements from Zn, compares them as signed integers (element size determined by sz), and reduces to a single scalar value. No NZCV flags are affected by this instruction.", "example": "SMINV v0.4s, p0/m, z1.s.T", "pseudocode": "bits(esize) result = MAX_INT(esize);\nfor i = 0 to VL/esize - 1\n if Pg[i] == '1' then\n element = Zn[i*esize +: esize];\n if element < result (signed) then result = element;\nVd[0 +: esize] ← result;"} {"mnemonic": "uminv", "architecture": "ARMv8-A", "full_name": "SVE Unsigned Minimum Reduction", "summary": "Finds min unsigned element in vector.", "syntax": "UMINV , , .", "encoding": {"format": "SVE Reduction", "binary_pattern": "00000100 | size | 0010 | 1 | 1 | 001 | Pg | Zn | Vd", "hex_opcode": "0x040B2000", "visual_parts": [{"raw": "00000100", "clean": "00000100"}, {"raw": "size", "clean": "size"}, {"raw": "0010", "clean": "0010"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "001", "clean": "001"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Vd", "clean": "Vd"}], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Vd", "desc": "Dest Scalar"}, {"name": "Pg", "desc": "Mask"}, {"name": "Zn", "desc": "Vector"}], "extension": "SVE", "description": "SVE unsigned minimum reduction: finds the minimum unsigned element in vector Zn according to predicate mask Pg, and stores the result as a scalar in Vd. The operation compares all active elements as unsigned integers (element size determined by sz) and reduces to a single scalar. No NZCV flags are affected by this instruction.", "example": "UMINV v0.4s, p0/m, z1.s.T", "pseudocode": "bits(esize) result = ALL_ONES(esize);\nfor i = 0 to VL/esize - 1\n if Pg[i] == '1' then\n element = Zn[i*esize +: esize];\n if element < result (unsigned) then result = element;\nVd[0 +: esize] ← result;"} {"mnemonic": "fmaxv", "architecture": "ARMv8-A", "full_name": "SVE Floating-Point Maximum Reduction", "summary": "Finds max float in vector.", "syntax": "FMAXV , , .", "encoding": {"format": "SVE Reduction", "binary_pattern": "01100101 | size | 000 | 11 | 0 | 001 | Pg | Zn | Vd", "hex_opcode": "0x65062000", "visual_parts": [{"raw": "01100101", "clean": "01100101"}, {"raw": "size", "clean": "size"}, {"raw": "000", "clean": "000"}, {"raw": "11", "clean": "11"}, {"raw": "0", "clean": "0"}, {"raw": "001", "clean": "001"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Vd", "clean": "Vd"}], "bit_positions": "31:24 | 23:22 | 21:19 | 18:17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Vd", "desc": "Dest Scalar"}, {"name": "Pg", "desc": "Mask"}, {"name": "Zn", "desc": "Vector"}], "extension": "SVE", "description": "SVE floating-point maximum reduction: finds the maximum floating-point element in vector Zn according to predicate mask Pg, and stores the result as a scalar in Vd. The operation compares all active elements as IEEE 754 floats (precision determined by sz: 0=half, 1=single or double) using quiet comparison semantics, and reduces to a single scalar. No NZCV flags are affected; SNaNs propagate as the maximum.", "example": "FMAXV v0.4s, p0/m, z1.s.T", "pseudocode": "bits(esize) result = NegInfinity(esize);\nfor i = 0 to VL/esize - 1\n if Pg[i] == '1' then\n element = Zn[i*esize +: esize];\n if element > result (FP) || IsNaN(result) then result = element;\nVd[0 +: esize] ← result;"} {"mnemonic": "fminv", "architecture": "ARMv8-A", "full_name": "SVE Floating-Point Minimum Reduction", "summary": "Finds min float in vector.", "syntax": "FMINV , , .", "encoding": {"format": "SVE Reduction", "binary_pattern": "01100101 | size | 000 | 11 | 1 | 001 | Pg | Zn | Vd", "hex_opcode": "0x65072000", "visual_parts": [{"raw": "01100101", "clean": "01100101"}, {"raw": "size", "clean": "size"}, {"raw": "000", "clean": "000"}, {"raw": "11", "clean": "11"}, {"raw": "1", "clean": "1"}, {"raw": "001", "clean": "001"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Vd", "clean": "Vd"}], "bit_positions": "31:24 | 23:22 | 21:19 | 18:17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Vd", "desc": "Dest Scalar"}, {"name": "Pg", "desc": "Mask"}, {"name": "Zn", "desc": "Vector"}], "extension": "SVE", "description": "SVE floating-point minimum reduction: finds the minimum floating-point element in vector Zn according to predicate mask Pg, and stores the result as a scalar in Vd. The operation compares all active elements as IEEE 754 floats (precision determined by sz: 0=half, 1=single or double) using quiet comparison semantics, and reduces to a single scalar. No NZCV flags are affected; SNaNs propagate as the minimum.", "example": "FMINV v0.4s, p0/m, z1.s.T", "pseudocode": "bits(esize) result = PosInfinity(esize);\nfor i = 0 to VL/esize - 1\n if Pg[i] == '1' then\n element = Zn[i*esize +: esize];\n if element < result (FP) || IsNaN(result) then result = element;\nVd[0 +: esize] ← result;"} {"mnemonic": "andv", "architecture": "ARMv8-A", "full_name": "SVE Bitwise AND Reduction", "summary": "ANDs all active elements into a scalar.", "syntax": "ANDV , , .", "encoding": {"format": "SVE Reduction", "binary_pattern": "00000100 | size | 0110 | 1 | 0 | 001 | Pg | Zn | Vd", "hex_opcode": "0x041A2000", "visual_parts": [{"raw": "00000100", "clean": "00000100"}, {"raw": "size", "clean": "size"}, {"raw": "0110", "clean": "0110"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "001", "clean": "001"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Vd", "clean": "Vd"}], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Vd", "desc": "Dest Scalar"}, {"name": "Pg", "desc": "Mask"}, {"name": "Zn", "desc": "Vector"}], "extension": "SVE", "description": "SVE bitwise AND reduction: performs a bitwise AND of all active elements in vector Zn according to predicate mask Pg, and stores the result as a scalar in Vd. The operation reduces a vector of integers to a single scalar by bitwise AND across all selected elements (element size determined by sz). No NZCV flags are affected by this instruction.", "example": "ANDV v0.4s, p0/m, z1.s.T", "pseudocode": "bits(esize) result = ALL_ONES(esize);\nfor i = 0 to VL/esize - 1\n if Pg[i] == '1' then\n element = Zn[i*esize +: esize];\n result = result AND element;\nVd[0 +: esize] ← result;"} {"mnemonic": "orv", "architecture": "ARMv8-A", "full_name": "SVE Bitwise OR Reduction", "summary": "ORs all active elements into a scalar.", "syntax": "ORV , , .", "encoding": {"format": "SVE Reduction", "binary_pattern": "00000100 | size | 0110 | 0 | 0 | 001 | Pg | Zn | Vd", "hex_opcode": "0x04182000", "visual_parts": [{"raw": "00000100", "clean": "00000100"}, {"raw": "size", "clean": "size"}, {"raw": "0110", "clean": "0110"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "001", "clean": "001"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Vd", "clean": "Vd"}], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Vd", "desc": "Dest Scalar"}, {"name": "Pg", "desc": "Mask"}, {"name": "Zn", "desc": "Vector"}], "extension": "SVE", "description": "SVE bitwise OR reduction: performs a bitwise OR of all active elements in vector Zn according to predicate mask Pg, and stores the result as a scalar in Vd. The operation reduces a vector of integers to a single scalar by bitwise OR across all selected elements (element size determined by sz). No NZCV flags are affected by this instruction.", "example": "ORV v0.4s, p0/m, z1.s.T", "pseudocode": "bits(esize) result = 0;\nfor i = 0 to VL/esize - 1\n if Pg[i] == '1' then\n element = Zn[i*esize +: esize];\n result = result OR element;\nVd[0 +: esize] ← result;"} {"mnemonic": "eorv", "architecture": "ARMv8-A", "full_name": "SVE Bitwise EOR Reduction", "summary": "XORs all active elements into a scalar.", "syntax": "EORV , , .", "encoding": {"format": "SVE Reduction", "binary_pattern": "00000100 | size | 0110 | 0 | 1 | 001 | Pg | Zn | Vd", "hex_opcode": "0x04192000", "visual_parts": [{"raw": "00000100", "clean": "00000100"}, {"raw": "size", "clean": "size"}, {"raw": "0110", "clean": "0110"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "001", "clean": "001"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Vd", "clean": "Vd"}], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Vd", "desc": "Dest Scalar"}, {"name": "Pg", "desc": "Mask"}, {"name": "Zn", "desc": "Vector"}], "extension": "SVE", "description": "SVE bitwise XOR reduction that combines all active predicated elements of a scalable vector into a scalar result. The operation iteratively XORs each active element into the destination scalar register. No condition flags are affected by this instruction. This is an AArch64-only SVE instruction.", "example": "EORV v0.4s, p0/m, z1.s.T", "pseudocode": "bits(smax(8*datasize,32)) result = Vd;\nfor i = 0 to (VL/esize)-1\n if Pg[i]\n result = result XOR Zn[i*esize+esize-1:i*esize]\nVd = result;"} {"mnemonic": "scvtf", "architecture": "ARMv8-A", "full_name": "SVE Signed Integer Convert to Floating-Point", "summary": "Converts signed integers to floats.", "syntax": "SCVTF ., /M, .", "encoding": {"format": "SVE Conversion", "binary_pattern": "01100101 | 0 | 1 | 010 | 0 | 1 | 0 | 101 | Pg | Zn | Zd", "hex_opcode": "0x6552A000", "visual_parts": [{"raw": "01100101", "clean": "01100101"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "010", "clean": "010"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "101", "clean": "101"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Zd", "clean": "Zd"}], "bit_positions": "31:24 | 23 | 22 | 21:19 | 18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Zdn", "desc": "Combined destination/source scalable vector register (SVE)"}, {"name": "Pg", "desc": "Mask"}], "extension": "SVE", "description": "SVE instruction that converts signed integer elements in a scalable vector to floating-point representation. Only active predicated elements are converted; inactive elements are zeroed. The instruction operates under predicate control with zeroing (/Z) semantics. This is an AArch64-only SVE instruction with no NZCV flag effects.", "example": "SCVTF z0.s.T, p0/m/M, z0.s.T", "pseudocode": "for i = 0 to (VL/esize)-1\n if Pg[i]\n Zdn[i*esize+esize-1:i*esize] = ConvertSignedIntegerToFP(Zdn[i*esize+esize-1:i*esize])\n else\n Zdn[i*esize+esize-1:i*esize] = 0"} {"mnemonic": "ucvtf", "architecture": "ARMv8-A", "full_name": "SVE Unsigned Integer Convert to Floating-Point", "summary": "Converts unsigned integers to floats.", "syntax": "UCVTF ., /M, .", "encoding": {"format": "SVE Conversion", "binary_pattern": "01100101 | 0 | 1 | 010 | 0 | 1 | 1 | 101 | Pg | Zn | Zd", "hex_opcode": "0x6553A000", "visual_parts": [{"raw": "01100101", "clean": "01100101"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "010", "clean": "010"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "101", "clean": "101"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Zd", "clean": "Zd"}], "bit_positions": "31:24 | 23 | 22 | 21:19 | 18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Zdn", "desc": "Combined destination/source scalable vector register (SVE)"}, {"name": "Pg", "desc": "Mask"}], "extension": "SVE", "description": "SVE instruction that converts unsigned integer elements in a scalable vector to floating-point representation. Only active predicated elements are converted; inactive elements are zeroed. The instruction operates under predicate control with zeroing (/Z) semantics. This is an AArch64-only SVE instruction with no NZCV flag effects.", "example": "UCVTF z0.s.T, p0/m/M, z0.s.T", "pseudocode": "for i = 0 to (VL/esize)-1\n if Pg[i]\n Zdn[i*esize+esize-1:i*esize] = ConvertUnsignedIntegerToFP(Zdn[i*esize+esize-1:i*esize])\n else\n Zdn[i*esize+esize-1:i*esize] = 0"} {"mnemonic": "fcvtzs", "architecture": "ARMv8-A", "full_name": "SVE Floating-Point Convert to Signed Integer", "summary": "Converts floats to signed integers (Truncate).", "syntax": "FCVTZS ., /M, .", "encoding": {"format": "SVE Conversion", "binary_pattern": "01100101 | 0 | 1 | 011 | 0 | 1 | 0 | 101 | Pg | Zn | Zd", "hex_opcode": "0x655AA000", "visual_parts": [{"raw": "01100101", "clean": "01100101"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "011", "clean": "011"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "101", "clean": "101"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Zd", "clean": "Zd"}], "bit_positions": "31:24 | 23 | 22 | 21:19 | 18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Zdn", "desc": "Combined destination/source scalable vector register (SVE)"}, {"name": "Pg", "desc": "Mask"}], "extension": "SVE", "description": "SVE instruction that converts floating-point elements in a scalable vector to signed integer representation by truncation toward zero. Only active predicated elements are converted; inactive elements are zeroed. The instruction operates under predicate control with zeroing (/Z) semantics. This is an AArch64-only SVE instruction with no NZCV flag effects.", "example": "FCVTZS z0.s.T, p0/m/M, z0.s.T", "pseudocode": "for i = 0 to (VL/esize)-1\n if Pg[i]\n Zdn[i*esize+esize-1:i*esize] = ConvertFPToSignedIntegerTruncate(Zdn[i*esize+esize-1:i*esize])\n else\n Zdn[i*esize+esize-1:i*esize] = 0"} {"mnemonic": "fcvtzu", "architecture": "ARMv8-A", "full_name": "SVE Floating-Point Convert to Unsigned Integer", "summary": "Converts floats to unsigned integers (Truncate).", "syntax": "FCVTZU ., /M, .", "encoding": {"format": "SVE Conversion", "binary_pattern": "01100101 | 0 | 1 | 011 | 0 | 1 | 1 | 101 | Pg | Zn | Zd", "hex_opcode": "0x655BA000", "visual_parts": [{"raw": "01100101", "clean": "01100101"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "011", "clean": "011"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "101", "clean": "101"}, {"raw": "Pg", "clean": "Pg"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Zd", "clean": "Zd"}], "bit_positions": "31:24 | 23 | 22 | 21:19 | 18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Zdn", "desc": "Combined destination/source scalable vector register (SVE)"}, {"name": "Pg", "desc": "Mask"}], "extension": "SVE", "description": "SVE instruction that converts floating-point elements in a scalable vector to unsigned integer representation by truncation toward zero. Only active predicated elements are converted; inactive elements are zeroed. The instruction operates under predicate control with zeroing (/Z) semantics. This is an AArch64-only SVE instruction with no NZCV flag effects.", "example": "FCVTZU z0.s.T, p0/m/M, z0.s.T", "pseudocode": "for i = 0 to (VL/esize)-1\n if Pg[i]\n Zdn[i*esize+esize-1:i*esize] = ConvertFPToUnsignedIntegerTruncate(Zdn[i*esize+esize-1:i*esize])\n else\n Zdn[i*esize+esize-1:i*esize] = 0"} {"mnemonic": "smulbb", "architecture": "ARMv8-A", "full_name": "Signed Multiply (Bottom x Bottom)", "summary": "Multiplies bottom 16 bits of Rn and Rm.", "syntax": "SMULBB , , ", "encoding": {"format": "Multiply", "binary_pattern": "cond | 00010 | 11 | 0 | Rd | 0000 | Rm | 1 | 0 | 0 | 0 | Rn", "hex_opcode": "0x01600080", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00010", "clean": "00010"}, {"raw": "11", "clean": "11"}, {"raw": "0", "clean": "0"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "0000", "clean": "0000"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "Src 1 (Bot)"}, {"name": "Rm", "desc": "Src 2 (Bot)"}], "extension": "A32 (DSP)", "description": "Multiplies the bottom 16 bits (bits [15:0]) of Rn by the bottom 16 bits of Rm as signed integers, producing a 32-bit signed result in Rd. This is an A32 DSP instruction that does not update condition flags.", "example": "SMULBB r0, r1, r2", "pseudocode": "if ConditionPassed() then\n operand1 = SignExtend(Rn[15:0], 32)\n operand2 = SignExtend(Rm[15:0], 32)\n Rd = operand1 * operand2"} {"mnemonic": "smulbt", "architecture": "ARMv8-A", "full_name": "Signed Multiply (Bottom x Top)", "summary": "Multiplies bottom 16 bits of Rn and top 16 bits of Rm.", "syntax": "SMULBT , , ", "encoding": {"format": "Multiply", "binary_pattern": "cond | 00010 | 11 | 0 | Rd | 0000 | Rm | 1 | 1 | 0 | 0 | Rn", "hex_opcode": "0x016000C0", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00010", "clean": "00010"}, {"raw": "11", "clean": "11"}, {"raw": "0", "clean": "0"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "0000", "clean": "0000"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "Src 1 (Bot)"}, {"name": "Rm", "desc": "Src 2 (Top)"}], "extension": "A32 (DSP)", "description": "A32 DSP multiply instruction that multiplies the bottom 16 bits (signed) of Rn by the top 16 bits (signed) of Rm and stores the 32-bit result in Rd. The instruction is conditional and does not affect the NZCV condition flags. Q flag behavior is not documented for this instruction in standard architectures.", "example": "SMULBT r0, r1, r2", "pseudocode": "operand1 = SignExtend(Rn<15:0>, 32)\noperand2 = SignExtend(Rm<31:16>, 32)\nRd = (operand1 * operand2)<31:0>"} {"mnemonic": "smultb", "architecture": "ARMv8-A", "full_name": "Signed Multiply (Top x Bottom)", "summary": "Multiplies top 16 bits of Rn and bottom 16 bits of Rm.", "syntax": "SMULTB , , ", "encoding": {"format": "Multiply", "binary_pattern": "cond | 00010 | 11 | 0 | Rd | 0000 | Rm | 1 | 0 | 1 | 0 | Rn", "hex_opcode": "0x016000A0", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00010", "clean": "00010"}, {"raw": "11", "clean": "11"}, {"raw": "0", "clean": "0"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "0000", "clean": "0000"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "Src 1 (Top)"}, {"name": "Rm", "desc": "Src 2 (Bot)"}], "extension": "A32 (DSP)", "description": "A32 DSP multiply instruction that multiplies the top 16 bits (signed) of Rn by the bottom 16 bits (signed) of Rm and stores the 32-bit result in Rd. The instruction is conditional and does not affect the NZCV condition flags. Q flag behavior is not documented for this instruction in standard architectures.", "example": "SMULTB r0, r1, r2", "pseudocode": "operand1 = SignExtend(Rn<31:16>, 32)\noperand2 = SignExtend(Rm<15:0>, 32)\nRd = (operand1 * operand2)<31:0>"} {"mnemonic": "smultt", "architecture": "ARMv8-A", "full_name": "Signed Multiply (Top x Top)", "summary": "Multiplies top 16 bits of Rn and top 16 bits of Rm.", "syntax": "SMULTT , , ", "encoding": {"format": "Multiply", "binary_pattern": "cond | 00010 | 11 | 0 | Rd | 0000 | Rm | 1 | 1 | 1 | 0 | Rn", "hex_opcode": "0x016000E0", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00010", "clean": "00010"}, {"raw": "11", "clean": "11"}, {"raw": "0", "clean": "0"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "0000", "clean": "0000"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "Src 1 (Top)"}, {"name": "Rm", "desc": "Src 2 (Top)"}], "extension": "A32 (DSP)", "description": "A32 DSP multiply instruction that multiplies the top 16 bits (signed) of Rn by the top 16 bits (signed) of Rm and stores the 32-bit result in Rd. The instruction is conditional and does not affect the NZCV condition flags. Q flag behavior is not documented for this instruction in standard architectures.", "example": "SMULTT r0, r1, r2", "pseudocode": "operand1 = SignExtend(Rn<31:16>, 32)\noperand2 = SignExtend(Rm<31:16>, 32)\nRd = (operand1 * operand2)<31:0>"} {"mnemonic": "smlabb", "architecture": "ARMv8-A", "full_name": "Signed Multiply Accumulate (Bottom x Bottom)", "summary": "Accumulates (Rn.B * Rm.B) into Ra.", "syntax": "SMLABB , , , ", "encoding": {"format": "Multiply", "binary_pattern": "cond | 00010 | 00 | 0 | Rd | Ra | Rm | 1 | 0 | 0 | 0 | Rn", "hex_opcode": "0x01000080", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00010", "clean": "00010"}, {"raw": "00", "clean": "00"}, {"raw": "0", "clean": "0"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "Ra", "clean": "Ra"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}, {"name": "Ra", "desc": "Acc"}], "extension": "A32 (DSP)", "description": "Signed multiply-accumulate of the bottom 16-bit halfwords of Rn and Rm, with the 32-bit product added to Ra and stored in Rd. This is an A32 DSP instruction that operates on 16-bit subregisters. The Q flag may be set if overflow occurs during accumulation, but N, Z, C, V flags are unchanged.", "example": "SMLABB r0, r1, r2, r5", "pseudocode": "temp ← SignExtend(Rn[15:0], 32) * SignExtend(Rm[15:0], 32);\nresult ← temp + Ra;\nif OverflowFrom_Addition(temp, Ra) then Q ← 1; end if;\nRd ← result;"} {"mnemonic": "smlabt", "architecture": "ARMv8-A", "full_name": "Signed Multiply Accumulate (Bottom x Top)", "summary": "Accumulates (Rn.B * Rm.T) into Ra.", "syntax": "SMLABT , , , ", "encoding": {"format": "Multiply", "binary_pattern": "cond | 00010 | 00 | 0 | Rd | Ra | Rm | 1 | 1 | 0 | 0 | Rn", "hex_opcode": "0x010000C0", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00010", "clean": "00010"}, {"raw": "00", "clean": "00"}, {"raw": "0", "clean": "0"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "Ra", "clean": "Ra"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}, {"name": "Ra", "desc": "Acc"}], "extension": "A32 (DSP)", "description": "Signed multiply-accumulate of the bottom 16-bit halfword of Rn and the top 16-bit halfword of Rm, with the 32-bit product added to Ra and stored in Rd. This is an A32 DSP instruction that operates on 16-bit subregisters. The Q flag may be set if overflow occurs during accumulation, but N, Z, C, V flags are unchanged.", "example": "SMLABT r0, r1, r2, r5", "pseudocode": "temp ← SignExtend(Rn[15:0], 32) * SignExtend(Rm[31:16], 32);\nresult ← temp + Ra;\nif OverflowFrom_Addition(temp, Ra) then Q ← 1; end if;\nRd ← result;"} {"mnemonic": "smlatb", "architecture": "ARMv8-A", "full_name": "Signed Multiply Accumulate (Top x Bottom)", "summary": "Accumulates (Rn.T * Rm.B) into Ra.", "syntax": "SMLATB , , , ", "encoding": {"format": "Multiply", "binary_pattern": "cond | 00010 | 00 | 0 | Rd | Ra | Rm | 1 | 0 | 1 | 0 | Rn", "hex_opcode": "0x010000A0", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00010", "clean": "00010"}, {"raw": "00", "clean": "00"}, {"raw": "0", "clean": "0"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "Ra", "clean": "Ra"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}, {"name": "Ra", "desc": "Acc"}], "extension": "A32 (DSP)", "description": "Signed multiply-accumulate of the top 16-bit halfword of Rn and the bottom 16-bit halfword of Rm, with the 32-bit product added to Ra and stored in Rd. This is an A32 DSP instruction that operates on 16-bit subregisters. The Q flag may be set if overflow occurs during accumulation, but N, Z, C, V flags are unchanged.", "example": "SMLATB r0, r1, r2, r5", "pseudocode": "temp ← SignExtend(Rn[31:16], 32) * SignExtend(Rm[15:0], 32);\nresult ← temp + Ra;\nif OverflowFrom_Addition(temp, Ra) then Q ← 1; end if;\nRd ← result;"} {"mnemonic": "smlatt", "architecture": "ARMv8-A", "full_name": "Signed Multiply Accumulate (Top x Top)", "summary": "Accumulates (Rn.T * Rm.T) into Ra.", "syntax": "SMLATT , , , ", "encoding": {"format": "Multiply", "binary_pattern": "cond | 00010 | 00 | 0 | Rd | Ra | Rm | 1 | 1 | 1 | 0 | Rn", "hex_opcode": "0x010000E0", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00010", "clean": "00010"}, {"raw": "00", "clean": "00"}, {"raw": "0", "clean": "0"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "Ra", "clean": "Ra"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}, {"name": "Ra", "desc": "Acc"}], "extension": "A32 (DSP)", "description": "Signed multiply-accumulate of the top 16-bit halfwords of Rn and Rm, with the 32-bit product added to Ra and stored in Rd. This is an A32 DSP instruction that operates on 16-bit subregisters. The Q flag may be set if overflow occurs during accumulation, but N, Z, C, V flags are unchanged.", "example": "SMLATT r0, r1, r2, r5", "pseudocode": "temp ← SignExtend(Rn[31:16], 32) * SignExtend(Rm[31:16], 32);\nresult ← temp + Ra;\nif OverflowFrom_Addition(temp, Ra) then Q ← 1; end if;\nRd ← result;"} {"mnemonic": "smulwb", "architecture": "ARMv8-A", "full_name": "Signed Multiply (Word x Bottom)", "summary": "Multiplies 32-bit Rn by bottom 16-bits of Rm, takes top 32-bits of result.", "syntax": "SMULWB , , ", "encoding": {"format": "Multiply", "binary_pattern": "cond | 00010 | 01 | 0 | Rd | 0000 | Rm | 1 | 0 | 1 | 0 | Rn", "hex_opcode": "0x012000A0", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00010", "clean": "00010"}, {"raw": "01", "clean": "01"}, {"raw": "0", "clean": "0"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "0000", "clean": "0000"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "Word Src"}, {"name": "Rm", "desc": "Half Src"}], "extension": "A32 (DSP)", "description": "Signed multiply of the 32-bit Rn by the bottom 16-bit halfword of Rm, extracting the top 32 bits of the 48-bit product into Rd. This is an A32 DSP instruction that produces no flag changes; overflow is not indicated.", "example": "SMULWB r0, r1, r2", "pseudocode": "product ← SignExtend(Rn[31:0], 48) * SignExtend(Rm[15:0], 48);\nRd ← product[47:16];"} {"mnemonic": "smulwt", "architecture": "ARMv8-A", "full_name": "Signed Multiply (Word x Top)", "summary": "Multiplies 32-bit Rn by top 16-bits of Rm, takes top 32-bits of result.", "syntax": "SMULWT , , ", "encoding": {"format": "Multiply", "binary_pattern": "cond | 00010 | 01 | 0 | Rd | 0000 | Rm | 1 | 1 | 1 | 0 | Rn", "hex_opcode": "0x012000E0", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00010", "clean": "00010"}, {"raw": "01", "clean": "01"}, {"raw": "0", "clean": "0"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "0000", "clean": "0000"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "Word Src"}, {"name": "Rm", "desc": "Half Src"}], "extension": "A32 (DSP)", "description": "Signed multiply of the 32-bit Rn by the top 16-bit halfword of Rm, extracting the top 32 bits of the 48-bit product into Rd. This is an A32 DSP instruction that produces no flag changes; overflow is not indicated.", "example": "SMULWT r0, r1, r2", "pseudocode": "product ← SignExtend(Rn[31:0], 48) * SignExtend(Rm[31:16], 48);\nRd ← product[47:16];"} {"mnemonic": "smlawb", "architecture": "ARMv8-A", "full_name": "Signed Multiply Accumulate (Word x Bottom)", "summary": "Performs SMULWB and adds to accumulator.", "syntax": "SMLAWB , , , ", "encoding": {"format": "Multiply", "binary_pattern": "cond | 00010 | 01 | 0 | Rd | Ra | Rm | 1 | 0 | 0 | 0 | Rn", "hex_opcode": "0x01200080", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00010", "clean": "00010"}, {"raw": "01", "clean": "01"}, {"raw": "0", "clean": "0"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "Ra", "clean": "Ra"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "Word"}, {"name": "Rm", "desc": "Half"}, {"name": "Ra", "desc": "Acc"}], "extension": "A32 (DSP)", "description": "Signed multiply-accumulate combining SMULWB with addition of Ra; multiplies 32-bit Rn by the bottom 16-bit halfword of Rm, takes the top 32 bits of the product, adds Ra, and stores in Rd. This is an A32 DSP instruction. The Q flag may be set if overflow occurs during accumulation, but N, Z, C, V flags are unchanged.", "example": "SMLAWB r0, r1, r2, r5", "pseudocode": "product ← SignExtend(Rn[31:0], 48) * SignExtend(Rm[15:0], 48);\ntemp ← product[47:16];\nresult ← temp + Ra;\nif OverflowFrom_Addition(temp, Ra) then Q ← 1; end if;\nRd ← result;"} {"mnemonic": "smlawt", "architecture": "ARMv8-A", "full_name": "Signed Multiply Accumulate (Word x Top)", "summary": "Performs SMULWT and adds to accumulator.", "syntax": "SMLAWT , , , ", "encoding": {"format": "Multiply", "binary_pattern": "cond | 00010 | 01 | 0 | Rd | Ra | Rm | 1 | 1 | 0 | 0 | Rn", "hex_opcode": "0x012000C0", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00010", "clean": "00010"}, {"raw": "01", "clean": "01"}, {"raw": "0", "clean": "0"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "Ra", "clean": "Ra"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "Word"}, {"name": "Rm", "desc": "Half"}, {"name": "Ra", "desc": "Acc"}], "extension": "A32 (DSP)", "description": "Signed multiply-accumulate combining SMULWT with addition of Ra; multiplies 32-bit Rn by the top 16-bit halfword of Rm, takes the top 32 bits of the product, adds Ra, and stores in Rd. This is an A32 DSP instruction. The Q flag may be set if overflow occurs during accumulation, but N, Z, C, V flags are unchanged.", "example": "SMLAWT r0, r1, r2, r5", "pseudocode": "product ← SignExtend(Rn[31:0], 48) * SignExtend(Rm[31:16], 48);\ntemp ← product[47:16];\nresult ← temp + Ra;\nif OverflowFrom_Addition(temp, Ra) then Q ← 1; end if;\nRd ← result;"} {"mnemonic": "smlalbb", "architecture": "ARMv8-A", "full_name": "Signed Multiply Accumulate Long (Bottom x Bottom)", "summary": "Accumulates (Rn.B * Rm.B) into 64-bit pair.", "syntax": "SMLALBB , , , ", "encoding": {"format": "Multiply", "binary_pattern": "cond | 00010 | 10 | 0 | RdHi | RdLo | Rm | 1 | 0 | 0 | 0 | Rn", "hex_opcode": "0x01400080", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00010", "clean": "00010"}, {"raw": "10", "clean": "10"}, {"raw": "0", "clean": "0"}, {"raw": "RdHi", "clean": "RdHi"}, {"raw": "RdLo", "clean": "RdLo"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "RdLo", "desc": "Lo"}, {"name": "RdHi", "desc": "Hi"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Signed Multiply Accumulate Long (Bottom × Bottom) multiplies the bottom 16 bits of Rn by the bottom 16 bits of Rm, treating both as signed, and accumulates the 32-bit result into the 64-bit value formed by RdHi:RdLo. This A32 DSP extension instruction does not update condition flags and is not available in AArch64.", "example": "SMLALBB r1, r0, r1, r2", "pseudocode": "operand1 ← SignExtend(Rn[15:0], 32);\noperand2 ← SignExtend(Rm[15:0], 32);\nresult ← operand1 * operand2;\nRdHi:RdLo ← RdHi:RdLo + result;"} {"mnemonic": "smlalbt", "architecture": "ARMv8-A", "full_name": "Signed Multiply Accumulate Long (Bottom x Top)", "summary": "Accumulates (Rn.B * Rm.T) into 64-bit pair.", "syntax": "SMLALBT , , , ", "encoding": {"format": "Multiply", "binary_pattern": "cond | 00010 | 10 | 0 | RdHi | RdLo | Rm | 1 | 1 | 0 | 0 | Rn", "hex_opcode": "0x014000C0", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00010", "clean": "00010"}, {"raw": "10", "clean": "10"}, {"raw": "0", "clean": "0"}, {"raw": "RdHi", "clean": "RdHi"}, {"raw": "RdLo", "clean": "RdLo"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "RdLo", "desc": "Lo"}, {"name": "RdHi", "desc": "Hi"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Signed Multiply Accumulate Long (Bottom × Top) multiplies the bottom 16 bits of Rn by the top 16 bits of Rm, treating both as signed, and accumulates the 32-bit result into the 64-bit value formed by RdHi:RdLo. This A32 DSP extension instruction does not update condition flags and is not available in AArch64.", "example": "SMLALBT r1, r0, r1, r2", "pseudocode": "operand1 ← SignExtend(Rn[15:0], 32);\noperand2 ← SignExtend(Rm[31:16], 32);\nresult ← operand1 * operand2;\nRdHi:RdLo ← RdHi:RdLo + result;"} {"mnemonic": "smlaltb", "architecture": "ARMv8-A", "full_name": "Signed Multiply Accumulate Long (Top x Bottom)", "summary": "Accumulates (Rn.T * Rm.B) into 64-bit pair.", "syntax": "SMLALTB , , , ", "encoding": {"format": "Multiply", "binary_pattern": "cond | 00010 | 10 | 0 | RdHi | RdLo | Rm | 1 | 0 | 1 | 0 | Rn", "hex_opcode": "0x014000A0", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00010", "clean": "00010"}, {"raw": "10", "clean": "10"}, {"raw": "0", "clean": "0"}, {"raw": "RdHi", "clean": "RdHi"}, {"raw": "RdLo", "clean": "RdLo"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "RdLo", "desc": "Lo"}, {"name": "RdHi", "desc": "Hi"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Signed Multiply Accumulate Long (Top × Bottom) multiplies the top 16 bits of Rn by the bottom 16 bits of Rm, treating both as signed, and accumulates the 32-bit result into the 64-bit value formed by RdHi:RdLo. This A32 DSP extension instruction does not update condition flags and is not available in AArch64.", "example": "SMLALTB r1, r0, r1, r2", "pseudocode": "operand1 ← SignExtend(Rn[31:16], 32);\noperand2 ← SignExtend(Rm[15:0], 32);\nresult ← operand1 * operand2;\nRdHi:RdLo ← RdHi:RdLo + result;"} {"mnemonic": "smlaltt", "architecture": "ARMv8-A", "full_name": "Signed Multiply Accumulate Long (Top x Top)", "summary": "Accumulates (Rn.T * Rm.T) into 64-bit pair.", "syntax": "SMLALTT , , , ", "encoding": {"format": "Multiply", "binary_pattern": "cond | 00010 | 10 | 0 | RdHi | RdLo | Rm | 1 | 1 | 1 | 0 | Rn", "hex_opcode": "0x014000E0", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00010", "clean": "00010"}, {"raw": "10", "clean": "10"}, {"raw": "0", "clean": "0"}, {"raw": "RdHi", "clean": "RdHi"}, {"raw": "RdLo", "clean": "RdLo"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "RdLo", "desc": "Lo"}, {"name": "RdHi", "desc": "Hi"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Signed Multiply Accumulate Long (Top × Top) multiplies the top 16 bits of Rn by the top 16 bits of Rm, treating both as signed, and accumulates the 32-bit result into the 64-bit value formed by RdHi:RdLo. This A32 DSP extension instruction does not update condition flags and is not available in AArch64.", "example": "SMLALTT r1, r0, r1, r2", "pseudocode": "operand1 ← SignExtend(Rn[31:16], 32);\noperand2 ← SignExtend(Rm[31:16], 32);\nresult ← operand1 * operand2;\nRdHi:RdLo ← RdHi:RdLo + result;"} {"mnemonic": "mia", "architecture": "ARMv8-A", "full_name": "Multiply with Internal Accumulate", "summary": "Multiplies two 32-bit values and adds to 40-bit internal acc (XScale Legacy).", "syntax": "MIA , , ", "encoding": {"format": "Coprocessor", "binary_pattern": "cond | 11100010 | 0000 | Rn | Acc | 0000 | 0001 | Rm", "hex_opcode": "0x0E200010", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "11100010", "clean": "11100010"}, {"raw": "0000", "clean": "0000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Acc", "clean": "Acc"}, {"raw": "0000", "clean": "0000"}, {"raw": "0001", "clean": "0001"}, {"raw": "Rm", "clean": "Rm"}]}, "operands": [{"name": "Acc", "desc": "Accumulator"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (XScale)", "description": "Multiply with Internal Accumulate multiplies two 32-bit values (Rn and Rm) and adds the 64-bit result to a 40-bit internal accumulator indexed by Acc. This XScale legacy A32 instruction is encoded as a coprocessor operation; condition flags are not updated, and this instruction is deprecated in modern ARM implementations.", "example": "MIA Acc, r1, r2", "pseudocode": "operand1 ← SignExtend(Rn, 64);\noperand2 ← SignExtend(Rm, 64);\nproduct ← operand1 * operand2;\ninternalAccumulator[Acc] ← internalAccumulator[Acc] + product;"} {"mnemonic": "miaph", "architecture": "ARMv8-A", "full_name": "Multiply with Internal Accumulate Packed Halfwords", "summary": "SIMD multiply of packed halfwords to internal acc (XScale Legacy).", "syntax": "MIAPH , , ", "encoding": {"format": "Coprocessor", "binary_pattern": "cond | 11100010 | 1000 | Rn | Acc | 0000 | 0001 | Rm", "hex_opcode": "0x0E280010", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "11100010", "clean": "11100010"}, {"raw": "1000", "clean": "1000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Acc", "clean": "Acc"}, {"raw": "0000", "clean": "0000"}, {"raw": "0001", "clean": "0001"}, {"raw": "Rm", "clean": "Rm"}]}, "operands": [{"name": "Acc", "desc": "Accumulator"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (XScale)", "description": "Multiply with Internal Accumulate Packed Halfwords performs SIMD multiplication of two packed 16-bit signed halfwords from Rn and Rm, accumulating each product into corresponding 40-bit internal accumulators. This XScale legacy A32 instruction is encoded as a coprocessor operation; condition flags are not updated, and this instruction is deprecated in modern ARM implementations.", "example": "MIAPH Acc, r1, r2", "pseudocode": "operand1_low ← SignExtend(Rn[15:0], 32);\noperand1_high ← SignExtend(Rn[31:16], 32);\noperand2_low ← SignExtend(Rm[15:0], 32);\noperand2_high ← SignExtend(Rm[31:16], 32);\nproduct_low ← operand1_low * operand2_low;\nproduct_high ← operand1_high * operand2_high;\ninternalAccumulator[Acc] ← internalAccumulator[Acc] + product_low;\ninternalAccumulator[Acc+1] ← internalAccumulator[Acc+1] + product_high;"} {"mnemonic": "sha256h", "architecture": "ARMv8-A", "full_name": "SHA256 Hash Part 1 (A32)", "summary": "SHA256 hash update (part 1).", "syntax": "SHA256H.32 , , ", "encoding": {"format": "Crypto 3-Reg", "binary_pattern": "11110011 | 0 | 0 | 0 | Vn | Vd | 1100 | N | Q | M | 0 | Vm", "hex_opcode": "0xF3000C00", "visual_parts": [{"raw": "11110011", "clean": "11110011"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1100", "clean": "1100"}, {"raw": "N", "clean": "N"}, {"raw": "Q", "clean": "Q"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}]}, "operands": [{"name": "Qd", "desc": "State"}, {"name": "Qn", "desc": "Hash"}, {"name": "Qm", "desc": "Data"}], "extension": "Crypto", "description": "SHA256 Hash Part 1 performs the first half of a SHA256 hash update operation on 128-bit NEON registers, processing the W array intermediate values. Qd receives updated hash state W[t] and W[t+1]; Qn provides the previous hash state; Qm provides the input data block words. This A32 Crypto extension instruction does not update condition flags and requires NEON support.", "example": "SHA256H.32 q0, q1, q2", "pseudocode": "hash_state ← Qd;\nw_data ← Qn;\ndata_words ← Qm;\ntemp ← SHA256_CH(hash_state.word[1], hash_state.word[2], hash_state.word[3]);\ntemp ← temp + SHA256_SUM1(hash_state.word[1]);\ntemp ← temp + data_words;\nQd.word[0] ← Qd.word[0] + temp;\nQd.word[1] ← hash_state.word[0];"} {"mnemonic": "sha256h2", "architecture": "ARMv8-A", "full_name": "SHA256 Hash Part 2 (A32)", "summary": "SHA256 hash update (part 2).", "syntax": "SHA256H2.32 , , ", "encoding": {"format": "Crypto 3-Reg", "binary_pattern": "11110011 | 0 | 0 | 0 | Vn | Vd | 1100 | N | Q | M | 1 | Vm", "hex_opcode": "0xF3100C00", "visual_parts": [{"raw": "11110011", "clean": "11110011"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1100", "clean": "1100"}, {"raw": "N", "clean": "N"}, {"raw": "Q", "clean": "Q"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}]}, "operands": [{"name": "Qd", "desc": "State"}, {"name": "Qn", "desc": "Hash"}, {"name": "Qm", "desc": "Data"}], "extension": "Crypto", "description": "SHA256 Hash Part 2 performs the second half of a SHA256 hash update operation on 128-bit NEON registers, processing the W array and final hash update. Qd receives the final hash state; Qn provides the hash value from the previous SHA256H instruction; Qm provides the input data block words. This A32 Crypto extension instruction does not update condition flags and requires NEON support.", "example": "SHA256H2.32 q0, q1, q2", "pseudocode": "hash_state ← Qd;\nw_data ← Qn;\ndata_words ← Qm;\ntemp ← SHA256_CH(hash_state.word[0], hash_state.word[1], hash_state.word[2]);\ntemp ← temp + SHA256_SUM1(hash_state.word[0]);\ntemp ← temp + data_words;\nQd.word[1] ← Qd.word[1] + temp;\nQd.word[0] ← hash_state.word[3];"} {"mnemonic": "sha256su0", "architecture": "ARMv8-A", "full_name": "SHA256 Schedule Update 0 (A32)", "summary": "SHA256 schedule update instruction 0.", "syntax": "SHA256SU0.32 , ", "encoding": {"format": "Crypto 2-Reg", "binary_pattern": "11110011 | 1 | D | 11 | 10 | 10 | Vd | 00100 | Q | M | 0 | Vm", "hex_opcode": "0xF3B203C0", "visual_parts": [{"raw": "11110011", "clean": "11110011"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "00100", "clean": "00100"}, {"raw": "Q", "clean": "Q"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:24 | 23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11:7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "Crypto", "description": "SHA256 Schedule Update 0 performs the first part of SHA256 message schedule expansion on four 32-bit words held in a 128-bit SIMD register. It processes the sigma_0 function as part of the SHA256 cryptographic algorithm. No condition flags are modified. This instruction requires the ARM Cryptography Extensions and executes only in A32 (ARM) state.", "example": "SHA256SU0.32 q0, q2", "pseudocode": "W[t] ← (W[t] >>> 7) XOR (W[t] >>> 18) XOR (W[t] >> 3); Qd ← result of applying this transformation to each 32-bit element of Qm"} {"mnemonic": "sha256su1", "architecture": "ARMv8-A", "full_name": "SHA256 Schedule Update 1 (A32)", "summary": "SHA256 schedule update instruction 1.", "syntax": "SHA256SU1.32 , , ", "encoding": {"format": "Crypto 3-Reg", "binary_pattern": "11110011 | 0 | 0 | 0 | Vn | Vd | 1101 | N | Q | M | 0 | Vm", "hex_opcode": "0xF3200C00", "visual_parts": [{"raw": "11110011", "clean": "11110011"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1101", "clean": "1101"}, {"raw": "N", "clean": "N"}, {"raw": "Q", "clean": "Q"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}]}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "Crypto", "description": "SHA256 Schedule Update 1 performs the second part of SHA256 message schedule expansion, combining three 128-bit registers to compute new message schedule words. It implements the full sigma_0(W[t-15]) + W[t-7] + sigma_1(W[t-2]) + W[t-16] operation. No condition flags are modified. This instruction requires the ARM Cryptography Extensions and executes only in A32 (ARM) state.", "example": "SHA256SU1.32 q0, q1, q2", "pseudocode": "Qd ← Qd + (Qn >>> 17) XOR (Qn >>> 19) XOR (Qn >> 10) + (Qm <<< 25) XOR (Qm <<< 14) XOR (Qm >> 6); (applied element-wise to 32-bit values)"} {"mnemonic": "sdot", "architecture": "ARMv8-A", "full_name": "Signed Dot Product (A32)", "summary": "Signed Dot Product (vector by vector).", "syntax": "SDOT.S8 , , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "01000100000 | Zm | 11001 | 0 | Zn | Zda", "hex_opcode": "0x4400C800", "visual_parts": [{"raw": "01000100000", "clean": "01000100000"}, {"raw": "Zm", "clean": "Zm"}, {"raw": "11001", "clean": "11001"}, {"raw": "0", "clean": "0"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Zda", "clean": "Zda"}], "bit_positions": "31:21 | 20:16 | 15:11 | 10 | 9:5 | 4:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (DotProd)", "description": "Signed Dot Product computes the dot product of four signed 8-bit integer elements from Qn and Qm, accumulating the result into the corresponding 32-bit element of Qd. Four separate dot products are computed in parallel across the 128-bit vectors. No condition flags are modified. This instruction requires the NEON Dot Product extension and executes in A32 (ARM) state.", "example": "SDOT.S8 q0, q1, q2", "pseudocode": "for i in [0, 1, 2, 3]:\n Qd[i*32+31:i*32] ← Qd[i*32+31:i*32] + SignedDotProduct(Qn[i*32+31:i*32], Qm[i*32+31:i*32])"} {"mnemonic": "udot", "architecture": "ARMv8-A", "full_name": "Unsigned Dot Product (A32)", "summary": "Unsigned Dot Product (vector by vector).", "syntax": "UDOT.U8 , , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "01000100000 | Zm | 11001 | 1 | Zn | Zda", "hex_opcode": "0x4400CC00", "visual_parts": [{"raw": "01000100000", "clean": "01000100000"}, {"raw": "Zm", "clean": "Zm"}, {"raw": "11001", "clean": "11001"}, {"raw": "1", "clean": "1"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Zda", "clean": "Zda"}], "bit_positions": "31:21 | 20:16 | 15:11 | 10 | 9:5 | 4:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (DotProd)", "description": "Unsigned Dot Product computes the dot product of four unsigned 8-bit integer elements from Qn and Qm, accumulating the result into the corresponding 32-bit element of Qd. Four separate dot products are computed in parallel across the 128-bit vectors. No condition flags are modified. This instruction requires the NEON Dot Product extension and executes in A32 (ARM) state.", "example": "UDOT.U8 q0, q1, q2", "pseudocode": "for i in [0, 1, 2, 3]:\n Qd[i*32+31:i*32] ← Qd[i*32+31:i*32] + UnsignedDotProduct(Qn[i*32+31:i*32], Qm[i*32+31:i*32])"} {"mnemonic": "vmmla", "architecture": "ARMv8-A", "full_name": "Matrix Multiply Accumulate (A32)", "summary": "Matrix multiply-accumulate (BFloat16/Int8).", "syntax": "VMMLA.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111110 | 00 | D | 0 | 0 | Vn | Vd | 1 | 1 | 0 | 0 | N | 1 | M | 0 | Vm", "hex_opcode": "0xFC000C40", "visual_parts": [{"raw": "1111110", "clean": "1111110"}, {"raw": "00", "clean": "00"}, {"raw": "D", "clean": "D"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "N", "clean": "N"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24:23 | 22 | 21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (MatMul)", "description": "Vector Matrix Multiply-Accumulate performs a 4×4 matrix multiply-accumulate operation on either 8-bit integers or BFloat16 values, with results accumulated into Qd. When sz=0, operates on signed/unsigned 8-bit elements; when sz=1, operates on BFloat16 elements. No condition flags are modified. This instruction requires the NEON Matrix Multiply extension and executes in A32 (ARM) state.", "example": "VMMLA.dt q0, q1, q2", "pseudocode": "if sz == 0:\n Qd ← Qd + MatMul_Int8(Qn, Qm) (4x4 matrix multiply of int8 elements)\nelse:\n Qd ← Qd + MatMul_BF16(Qn, Qm) (4x4 matrix multiply of bfloat16 elements)"} {"mnemonic": "usdot", "architecture": "ARMv8-A", "full_name": "Unsigned Signed Dot Product (A32)", "summary": "Dot product of unsigned and signed integers.", "syntax": "USDOT.S8 , , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "01000100 | 1 | 0 | 0 | Zm | 011110 | Zn | Zda", "hex_opcode": "0x44807800", "visual_parts": [{"raw": "01000100", "clean": "01000100"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "Zm", "clean": "Zm"}, {"raw": "011110", "clean": "011110"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Zda", "clean": "Zda"}], "bit_positions": "31:24 | 23 | 22 | 21 | 20:16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "Unsigned"}, {"name": "Qm", "desc": "Signed"}], "extension": "NEON (DotProd)", "description": "Unsigned-Signed Dot Product computes the dot product of unsigned 8-bit integers from Qn and signed 8-bit integers from Qm, accumulating into the corresponding 32-bit element of Qd. Four separate dot products are computed in parallel. No condition flags are modified. This instruction requires the NEON Dot Product extension and executes in A32 (ARM) state.", "example": "USDOT.S8 q0, q1, q2", "pseudocode": "for i in [0, 1, 2, 3]:\n Qd[i*32+31:i*32] ← Qd[i*32+31:i*32] + USSignedDotProduct(UnsignedQn[i*32+31:i*32], SignedQm[i*32+31:i*32])"} {"mnemonic": "sxtb", "architecture": "ARMv8-A", "full_name": "Signed Extend Byte (Thumb)", "summary": "Sign-extends byte to word (Thumb).", "syntax": "SXTB , ", "encoding": {"format": "Thumb Data Proc", "binary_pattern": "10110010 | 0 | 1 | Rm | Rd", "hex_opcode": "0xB240", "visual_parts": [{"raw": "10110010", "clean": "10110010"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "15:8 | 7 | 6 | 5:3 | 2:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "T32 (Thumb)", "description": "Sign-extends an 8-bit byte value to a 32-bit word in the T32 (Thumb) instruction set. The least-significant byte of Rm is sign-extended and written to Rd. No condition flags are affected.", "example": "SXTB r0, r2", "pseudocode": "Rd = SignExtend(Rm[7:0], 32)"} {"mnemonic": "sxth", "architecture": "ARMv8-A", "full_name": "Signed Extend Halfword (Thumb)", "summary": "Sign-extends halfword to word (Thumb).", "syntax": "SXTH , ", "encoding": {"format": "Thumb Data Proc", "binary_pattern": "10110010 | 0 | 0 | Rm | Rd", "hex_opcode": "0xB200", "visual_parts": [{"raw": "10110010", "clean": "10110010"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "15:8 | 7 | 6 | 5:3 | 2:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "T32 (Thumb)", "description": "Sign-extends a 16-bit halfword value to a 32-bit word in the T32 (Thumb) instruction set. The least-significant halfword of Rm is sign-extended and written to Rd. No condition flags are affected.", "example": "SXTH r0, r2", "pseudocode": "Rd = SignExtend(Rm[15:0], 32)"} {"mnemonic": "uxtb", "architecture": "ARMv8-A", "full_name": "Unsigned Extend Byte (Thumb)", "summary": "Zero-extends byte to word (Thumb).", "syntax": "UXTB , ", "encoding": {"format": "Thumb Data Proc", "binary_pattern": "10110010 | 1 | 1 | Rm | Rd", "hex_opcode": "0xB2C0", "visual_parts": [{"raw": "10110010", "clean": "10110010"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "15:8 | 7 | 6 | 5:3 | 2:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "T32 (Thumb)", "description": "Zero-extends an 8-bit byte value to a 32-bit word in the T32 (Thumb) instruction set. The least-significant byte of Rm is zero-extended and written to Rd. No condition flags are affected.", "example": "UXTB r0, r2", "pseudocode": "Rd = ZeroExtend(Rm[7:0], 32)"} {"mnemonic": "uxth", "architecture": "ARMv8-A", "full_name": "Unsigned Extend Halfword (Thumb)", "summary": "Zero-extends halfword to word (Thumb).", "syntax": "UXTH , ", "encoding": {"format": "Thumb Data Proc", "binary_pattern": "10110010 | 1 | 0 | Rm | Rd", "hex_opcode": "0xB280", "visual_parts": [{"raw": "10110010", "clean": "10110010"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "15:8 | 7 | 6 | 5:3 | 2:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "T32 (Thumb)", "description": "Zero-extends a 16-bit halfword value to a 32-bit word in the T32 (Thumb) instruction set. The least-significant halfword of Rm is zero-extended and written to Rd. No condition flags are affected.", "example": "UXTH r0, r2", "pseudocode": "Rd = ZeroExtend(Rm[15:0], 32)"} {"mnemonic": "rev", "architecture": "ARMv8-A", "full_name": "Reverse Bytes (Thumb)", "summary": "Endian swap (Thumb).", "syntax": "REV , ", "encoding": {"format": "Thumb Data Proc", "binary_pattern": "10111010 | 00 | Rm | Rd", "hex_opcode": "0xBA00", "visual_parts": [{"raw": "10111010", "clean": "10111010"}, {"raw": "00", "clean": "00"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "15:8 | 7:6 | 5:3 | 2:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "T32 (Thumb)", "description": "Reverses the byte order of a 32-bit value in a general-purpose register. The four bytes of the source register are swapped to convert between big-endian and little-endian representations. This instruction does not affect the condition flags. Execution is restricted to T32 (Thumb) instruction set.", "example": "REV r0, r2", "pseudocode": "Rd ← (Rm[7:0] << 24) | (Rm[15:8] << 16) | (Rm[23:16] << 8) | Rm[31:24]"} {"mnemonic": "rev16", "architecture": "ARMv8-A", "full_name": "Reverse Bytes Halfword (Thumb)", "summary": "Reverse bytes in halfwords (Thumb).", "syntax": "REV16 , ", "encoding": {"format": "Thumb Data Proc", "binary_pattern": "10111010 | 01 | Rm | Rd", "hex_opcode": "0xBA40", "visual_parts": [{"raw": "10111010", "clean": "10111010"}, {"raw": "01", "clean": "01"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "15:8 | 7:6 | 5:3 | 2:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "T32 (Thumb)", "description": "Reverses the byte order within each 16-bit halfword of a 32-bit register independently. Bytes [7:0] and [15:8] are swapped, and bytes [23:16] and [31:24] are swapped. This instruction does not affect the condition flags. Execution is restricted to T32 (Thumb) instruction set.", "example": "REV16 r0, r2", "pseudocode": "Rd ← (Rm[7:0] << 8) | Rm[15:8] | (Rm[23:16] << 8) | Rm[31:24]"} {"mnemonic": "revsh", "architecture": "ARMv8-A", "full_name": "Reverse Signed Halfword (Thumb)", "summary": "Reverse bytes in low halfword, sign extend (Thumb).", "syntax": "REVSH , ", "encoding": {"format": "Thumb Data Proc", "binary_pattern": "10111010 | 11 | Rm | Rd", "hex_opcode": "0xBAC0", "visual_parts": [{"raw": "10111010", "clean": "10111010"}, {"raw": "11", "clean": "11"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "15:8 | 7:6 | 5:3 | 2:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "T32 (Thumb)", "description": "Reverse Signed Halfword reverses the byte order of the low 16 bits of Rm, then sign-extends the result to 32 bits and writes it to Rd. This is commonly used to perform endian conversion on signed 16-bit values. No condition flags are modified. This instruction executes only in T32 (Thumb) state.", "example": "REVSH r0, r2", "pseudocode": "halfword ← Rm[15:0];\nreversed ← (halfword[7:0] << 8) | halfword[15:8];\nRd ← SignExtend(reversed, 16)"} {"mnemonic": "fabs", "architecture": "ARMv8-A", "full_name": "Floating-Point Absolute Value (Scalar)", "summary": "Calculates the absolute value of a float.", "syntax": "FABS , ", "encoding": {"format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 10000 | 01 | 10000 | Rn | Rd", "hex_opcode": "0x1E20C000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "10000", "clean": "10000"}, {"raw": "01", "clean": "01"}, {"raw": "10000", "clean": "10000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:17 | 16:15 | 14:10 | 9:5 | 4:0"}, "operands": [{"name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}], "extension": "Floating Point", "description": "Computes the absolute value of a scalar floating-point operand, clearing the sign bit while preserving all other bits. Floating-point exception conditions (invalid operation, etc.) are not generated. The instruction operates on Half-precision (16-bit), Single-precision (32-bit), or Double-precision (64-bit) formats, determined by the type field. This is an AArch64-only instruction.", "example": "FABS Dd, Dn", "pseudocode": "Rd ← abs(Rn)\nif (type == 00) then Rd is H-register (16-bit)\nelse if (type == 01) then Rd is S-register (32-bit)\nelse if (type == 10) then Rd is D-register (64-bit)"} {"mnemonic": "fadd", "architecture": "ARMv8-A", "full_name": "Floating-Point Add (Scalar)", "summary": "Adds two floating-point values.", "syntax": "FADD , , ", "encoding": {"format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | 001 | 0 | 10 | Rn | Rd", "hex_opcode": "0x1E202800", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "001", "clean": "001"}, {"raw": "0", "clean": "0"}, {"raw": "10", "clean": "10"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:13 | 12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}, {"name": "Hm|Sm|Dm", "desc": "Second source SIMD&FP register (half, single or double-precision)"}], "extension": "Floating Point", "description": "Adds two scalar floating-point operands and writes the result to the destination register. The operation respects IEEE 754 rounding modes and may generate floating-point exception conditions (invalid, overflow, underflow, inexact). The instruction operates on Half-precision (16-bit), Single-precision (32-bit), or Double-precision (64-bit) formats, determined by the type field. This is an AArch64-only instruction.", "example": "FADD Dd, Dn, Dm", "pseudocode": "Rd ← FP_Add(Rn, Rm)\nif (type == 00) then operands are H-registers (16-bit)\nelse if (type == 01) then operands are S-registers (32-bit)\nelse if (type == 10) then operands are D-registers (64-bit)"} {"mnemonic": "fsub", "architecture": "ARMv8-A", "full_name": "Floating-Point Subtract (Scalar)", "summary": "Subtracts two floating-point values.", "syntax": "FSUB , , ", "encoding": {"format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | 001 | 1 | 10 | Rn | Rd", "hex_opcode": "0x1E203800", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "001", "clean": "001"}, {"raw": "1", "clean": "1"}, {"raw": "10", "clean": "10"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:13 | 12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}, {"name": "Hm|Sm|Dm", "desc": "Second source SIMD&FP register (half, single or double-precision)"}], "extension": "Floating Point", "description": "Subtracts one scalar floating-point operand from another and writes the result to the destination register. The operation respects IEEE 754 rounding modes and may generate floating-point exception conditions (invalid, overflow, underflow, inexact). The instruction operates on Half-precision (16-bit), Single-precision (32-bit), or Double-precision (64-bit) formats, determined by the type field. This is an AArch64-only instruction.", "example": "FSUB Dd, Dn, Dm", "pseudocode": "Rd ← FP_Subtract(Rn, Rm)\nif (type == 00) then operands are H-registers (16-bit)\nelse if (type == 01) then operands are S-registers (32-bit)\nelse if (type == 10) then operands are D-registers (64-bit)"} {"mnemonic": "fmul", "architecture": "ARMv8-A", "full_name": "Floating-Point Multiply (Scalar)", "summary": "Multiplies two floating-point values.", "syntax": "FMUL , , ", "encoding": {"format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | 0 | 00010 | Rn | Rd", "hex_opcode": "0x1E200800", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "0", "clean": "0"}, {"raw": "00010", "clean": "00010"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15 | 14:10 | 9:5 | 4:0"}, "operands": [{"name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}, {"name": "Hm|Sm|Dm", "desc": "Second source SIMD&FP register (half, single or double-precision)"}], "extension": "Floating Point", "description": "Multiplies two scalar floating-point operands and writes the result to the destination register. The operation respects IEEE 754 rounding modes and may generate floating-point exception conditions (invalid, overflow, underflow, inexact). The instruction operates on Half-precision (16-bit), Single-precision (32-bit), or Double-precision (64-bit) formats, determined by the type field. This is an AArch64-only instruction.", "example": "FMUL Dd, Dn, Dm", "pseudocode": "Rd ← FP_Multiply(Rn, Rm)\nif (type == 00) then operands are H-registers (16-bit)\nelse if (type == 01) then operands are S-registers (32-bit)\nelse if (type == 10) then operands are D-registers (64-bit)"} {"mnemonic": "fdiv", "architecture": "ARMv8-A", "full_name": "Floating-Point Divide (Scalar)", "summary": "Divides two floating-point values.", "syntax": "FDIV , , ", "encoding": {"format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | 0001 | 10 | Rn | Rd", "hex_opcode": "0x1E201800", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "0001", "clean": "0001"}, {"raw": "10", "clean": "10"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}, {"name": "Hm|Sm|Dm", "desc": "Second source SIMD&FP register (half, single or double-precision)"}], "extension": "Floating Point", "description": "Divides one scalar floating-point operand by another and writes the result to the destination register. The operation respects IEEE 754 rounding modes and may generate floating-point exception conditions (invalid, overflow, underflow, inexact, divide-by-zero). The instruction operates on Half-precision (16-bit), Single-precision (32-bit), or Double-precision (64-bit) formats, determined by the type field. This is an AArch64-only instruction.", "example": "FDIV Dd, Dn, Dm", "pseudocode": "Rd ← FP_Divide(Rn, Rm)\nif (type == 00) then operands are H-registers (16-bit)\nelse if (type == 01) then operands are S-registers (32-bit)\nelse if (type == 10) then operands are D-registers (64-bit)"} {"mnemonic": "fmadd", "architecture": "ARMv8-A", "full_name": "Floating-Point Fused Multiply-Add (Scalar)", "summary": "Calculates (Vn * Vm) + Va without intermediate rounding.", "syntax": "FMADD , , , ", "encoding": {"format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11111 | 00 | 0 | Rm | 0 | Ra | Rn | Rd", "hex_opcode": "0x1F000000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11111", "clean": "11111"}, {"raw": "00", "clean": "00"}, {"raw": "0", "clean": "0"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "0", "clean": "0"}, {"raw": "Ra", "clean": "Ra"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15 | 14:10 | 9:5 | 4:0"}, "operands": [{"name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}, {"name": "Hm|Sm|Dm", "desc": "Second source SIMD&FP register (half, single or double-precision)"}, {"name": "Ha|Sa|Da", "desc": "Third source (accumulator) SIMD&FP register (half, single or double-precision)"}], "extension": "Floating Point", "description": "Computes a fused multiply-add operation: (Rn × Rm) + Ra, with a single rounding step applied to the final result. This guarantees higher precision than separate multiply and add instructions. Floating-point exception conditions (invalid, overflow, underflow, inexact) may be generated. The instruction operates on Half-precision (16-bit), Single-precision (32-bit), or Double-precision (64-bit) formats, determined by the type field. This is an AArch64-only instruction.", "example": "FMADD Dd, Dn, Dm, Da", "pseudocode": "Rd ← FP_FusedMultiplyAdd(Rn, Rm, Ra)\nif (type == 00) then operands are H-registers (16-bit)\nelse if (type == 01) then operands are S-registers (32-bit)\nelse if (type == 10) then operands are D-registers (64-bit)"} {"mnemonic": "fmsub", "architecture": "ARMv8-A", "full_name": "Floating-Point Fused Multiply-Subtract (Scalar)", "summary": "Calculates (Vn * Vm) - Va.", "syntax": "FMSUB , , , ", "encoding": {"format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11111 | 00 | 0 | Rm | 1 | Ra | Rn | Rd", "hex_opcode": "0x1F008000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11111", "clean": "11111"}, {"raw": "00", "clean": "00"}, {"raw": "0", "clean": "0"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "1", "clean": "1"}, {"raw": "Ra", "clean": "Ra"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15 | 14:10 | 9:5 | 4:0"}, "operands": [{"name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}, {"name": "Hm|Sm|Dm", "desc": "Second source SIMD&FP register (half, single or double-precision)"}, {"name": "Ha|Sa|Da", "desc": "Third source (accumulator) SIMD&FP register (half, single or double-precision)"}], "extension": "Floating Point", "description": "Floating-point fused multiply-subtract: computes (Vn × Vm) - Va and stores the result in Vd as a single fused operation with a single rounding step. Supports half-precision (H), single-precision (S), and double-precision (D) floating-point formats. No condition flags are affected; exceptions may be generated for invalid operations, overflow, underflow, inexact results, or input denormals depending on FPCR settings. AArch64 only.", "example": "FMSUB Dd, Dn, Dm, Da", "pseudocode": "if HaveFPExt() then\n Vd ← FPMulSub(Vn, Vm, Va)\nelse\n UNDEFINED"} {"mnemonic": "fnmadd", "architecture": "ARMv8-A", "full_name": "Floating-Point Fused Negated Multiply-Add (Scalar)", "summary": "Calculates -((Vn * Vm) + Va).", "syntax": "FNMADD , , , ", "encoding": {"format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11111 | 00 | 1 | Rm | 0 | Ra | Rn | Rd", "hex_opcode": "0x1F200000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11111", "clean": "11111"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "0", "clean": "0"}, {"raw": "Ra", "clean": "Ra"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15 | 14:10 | 9:5 | 4:0"}, "operands": [{"name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}, {"name": "Hm|Sm|Dm", "desc": "Second source SIMD&FP register (half, single or double-precision)"}, {"name": "Ha|Sa|Da", "desc": "Third source (accumulator) SIMD&FP register (half, single or double-precision)"}], "extension": "Floating Point", "description": "Floating-point fused negated multiply-add: computes -((Vn × Vm) + Va) and stores the result in Vd as a single fused operation with a single rounding step. Supports half-precision (H), single-precision (S), and double-precision (D) floating-point formats. No condition flags are affected; exceptions may be generated for invalid operations, overflow, underflow, inexact results, or input denormals depending on FPCR settings. AArch64 only.", "example": "FNMADD Dd, Dn, Dm, Da", "pseudocode": "if HaveFPExt() then\n Vd ← FPNegMulAdd(Vn, Vm, Va)\nelse\n UNDEFINED"} {"mnemonic": "fnmsub", "architecture": "ARMv8-A", "full_name": "Floating-Point Fused Negated Multiply-Subtract (Scalar)", "summary": "Calculates -((Vn * Vm) - Va).", "syntax": "FNMSUB , , , ", "encoding": {"format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11111 | 00 | 1 | Rm | 1 | Ra | Rn | Rd", "hex_opcode": "0x1F208000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11111", "clean": "11111"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "1", "clean": "1"}, {"raw": "Ra", "clean": "Ra"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15 | 14:10 | 9:5 | 4:0"}, "operands": [{"name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}, {"name": "Hm|Sm|Dm", "desc": "Second source SIMD&FP register (half, single or double-precision)"}, {"name": "Ha|Sa|Da", "desc": "Third source (accumulator) SIMD&FP register (half, single or double-precision)"}], "extension": "Floating Point", "description": "Floating-point fused negated multiply-subtract: computes -((Vn × Vm) - Va) and stores the result in Vd as a single fused operation with a single rounding step. Supports half-precision (H), single-precision (S), and double-precision (D) floating-point formats. No condition flags are affected; exceptions may be generated for invalid operations, overflow, underflow, inexact results, or input denormals depending on FPCR settings. AArch64 only.", "example": "FNMSUB Dd, Dn, Dm, Da", "pseudocode": "if HaveFPExt() then\n Vd ← FPNegMulSub(Vn, Vm, Va)\nelse\n UNDEFINED"} {"mnemonic": "fnmul", "architecture": "ARMv8-A", "full_name": "Floating-Point Negated Multiply (Scalar)", "summary": "Calculates -(Vn * Vm).", "syntax": "FNMUL , , ", "encoding": {"format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | 1 | 00010 | Rn | Rd", "hex_opcode": "0x1E208800", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "1", "clean": "1"}, {"raw": "00010", "clean": "00010"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15 | 14:10 | 9:5 | 4:0"}, "operands": [{"name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}, {"name": "Hm|Sm|Dm", "desc": "Second source SIMD&FP register (half, single or double-precision)"}], "extension": "Floating Point", "description": "Floating-Point Negated Multiply computes the negation of the product of two floating-point values: -(Vn × Vm), writing the result to Vd. Supports half-precision (type=0, 16-bit), single-precision (type=1, 32-bit), and double-precision (type=2, 64-bit) operands. FPSR exception flags may be set based on invalid, inexact, or overflow conditions. This instruction executes only in AArch64 state.", "example": "FNMUL Dd, Dn, Dm", "pseudocode": "if type == 0:\n Vd ← -(Vn_float16 × Vm_float16)\nelse if type == 1:\n Vd ← -(Vn_float32 × Vm_float32)\nelse if type == 2:\n Vd ← -(Vn_float64 × Vm_float64)"} {"mnemonic": "fsqrt", "architecture": "ARMv8-A", "full_name": "Floating-Point Square Root (Scalar)", "summary": "Calculates square root.", "syntax": "FSQRT , ", "encoding": {"format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 10000 | 11 | 10000 | Rn | Rd", "hex_opcode": "0x1E21C000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "10000", "clean": "10000"}, {"raw": "11", "clean": "11"}, {"raw": "10000", "clean": "10000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:17 | 16:15 | 14:10 | 9:5 | 4:0"}, "operands": [{"name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}], "extension": "Floating Point", "description": "Floating-point square root: computes the square root of Vn and stores the result in Vd. Supports half-precision (H), single-precision (S), and double-precision (D) floating-point formats. No condition flags are affected; exceptions may be generated for invalid operations (negative non-zero inputs), underflow, inexact results, or input denormals depending on FPCR settings. AArch64 only.", "example": "FSQRT Dd, Dn", "pseudocode": "if HaveFPExt() then\n Vd ← FPSqrt(Vn)\nelse\n UNDEFINED"} {"mnemonic": "fneg", "architecture": "ARMv8-A", "full_name": "Floating-Point Negate (Scalar)", "summary": "Negates the value (flips sign bit).", "syntax": "FNEG , ", "encoding": {"format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 11 | 10000 | 10 | 10000 | Rn | Rd", "hex_opcode": "0x1EE14000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "11", "clean": "11"}, {"raw": "10000", "clean": "10000"}, {"raw": "10", "clean": "10"}, {"raw": "10000", "clean": "10000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:17 | 16:15 | 14:10 | 9:5 | 4:0"}, "operands": [{"name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}], "extension": "Floating Point", "description": "Floating-point negate: flips the sign bit of Vn and stores the result in Vd, converting positive to negative and vice versa (including sign of zero). Supports half-precision (H), single-precision (S), and double-precision (D) floating-point formats. No condition flags are affected; no floating-point exceptions are generated. AArch64 only.", "example": "FNEG Dd, Dn", "pseudocode": "if HaveFPExt() then\n Vd ← FPNeg(Vn)\nelse\n UNDEFINED"} {"mnemonic": "fmax", "architecture": "ARMv8-A", "full_name": "Floating-Point Maximum (Scalar)", "summary": "Returns the larger of two values.", "syntax": "FMAX , , ", "encoding": {"format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | 01 | 00 | 10 | Rn | Rd", "hex_opcode": "0x1E204800", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "01", "clean": "01"}, {"raw": "00", "clean": "00"}, {"raw": "10", "clean": "10"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:14 | 13:12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}, {"name": "Hm|Sm|Dm", "desc": "Second source SIMD&FP register (half, single or double-precision)"}], "extension": "Floating Point", "description": "Floating-point maximum: returns the larger of Vn and Vm and stores it in Vd. Supports half-precision (H), single-precision (S), and double-precision (D) floating-point formats. Follows IEEE 754 rules where if either operand is NaN, NaN is returned; if one operand is zero and the other is -0, returns +0. No condition flags are affected; exceptions may be generated for invalid operations or input denormals depending on FPCR settings. AArch64 only.", "example": "FMAX Dd, Dn, Dm", "pseudocode": "if HaveFPExt() then\n Vd ← FPMax(Vn, Vm)\nelse\n UNDEFINED"} {"mnemonic": "fmin", "architecture": "ARMv8-A", "full_name": "Floating-Point Minimum (Scalar)", "summary": "Returns the smaller of two values.", "syntax": "FMIN , , ", "encoding": {"format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | 01 | 01 | 10 | Rn | Rd", "hex_opcode": "0x1E205800", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "01", "clean": "01"}, {"raw": "01", "clean": "01"}, {"raw": "10", "clean": "10"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:14 | 13:12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}, {"name": "Hm|Sm|Dm", "desc": "Second source SIMD&FP register (half, single or double-precision)"}], "extension": "Floating Point", "description": "Floating-point minimum: returns the smaller of Vn and Vm and stores it in Vd. Supports half-precision (H), single-precision (S), and double-precision (D) floating-point formats. Follows IEEE 754 rules where if either operand is NaN, NaN is returned; if one operand is zero and the other is -0, returns -0. No condition flags are affected; exceptions may be generated for invalid operations or input denormals depending on FPCR settings. AArch64 only.", "example": "FMIN Dd, Dn, Dm", "pseudocode": "if HaveFPExt() then\n Vd ← FPMin(Vn, Vm)\nelse\n UNDEFINED"} {"mnemonic": "fmaxnm", "architecture": "ARMv8-A", "full_name": "Floating-Point Max Number (Scalar)", "summary": "Returns larger value, handling NaNs according to IEEE 754-2008 'maxNum'.", "syntax": "FMAXNM , , ", "encoding": {"format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | 01 | 10 | 10 | Rn | Rd", "hex_opcode": "0x1E206800", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "01", "clean": "01"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:14 | 13:12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}, {"name": "Hm|Sm|Dm", "desc": "Second source SIMD&FP register (half, single or double-precision)"}], "extension": "Floating Point", "description": "Floating-point maximum number: returns the larger of two floating-point numbers Vn and Vm according to IEEE 754-2008 'maxNum' semantics, where if one operand is NaN and the other is a number, the number is returned. Supports half-precision (H), single-precision (S), and double-precision (D) floating-point formats. No condition flags are affected; exceptions may be generated for invalid operations or input denormals depending on FPCR settings. AArch64 only.", "example": "FMAXNM Dd, Dn, Dm", "pseudocode": "if HaveFPExt() then\n Vd ← FPMaxNum(Vn, Vm)\nelse\n UNDEFINED"} {"mnemonic": "fminnm", "architecture": "ARMv8-A", "full_name": "Floating-Point Min Number (Scalar)", "summary": "Returns smaller value, handling NaNs according to IEEE 754-2008 'minNum'.", "syntax": "FMINNM , , ", "encoding": {"format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | 01 | 11 | 10 | Rn | Rd", "hex_opcode": "0x1E207800", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "01", "clean": "01"}, {"raw": "11", "clean": "11"}, {"raw": "10", "clean": "10"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:14 | 13:12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}, {"name": "Hm|Sm|Dm", "desc": "Second source SIMD&FP register (half, single or double-precision)"}], "extension": "Floating Point", "description": "Floating-point minimum of two scalar values, returning the number (non-NaN) operand when one operand is NaN, per IEEE 754-2008 minNum semantics. Condition flags (N, Z, C, V) are not affected. AArch64-only instruction.", "example": "FMINNM Dd, Dn, Dm", "pseudocode": "if IsNaN(Vn) then\n result ← Vm\nelsif IsNaN(Vm) then\n result ← Vn\nelse\n result ← min(Vn, Vm)\nVd ← result"} {"mnemonic": "fcmp", "architecture": "ARMv8-A", "full_name": "Floating-Point Compare (Scalar)", "summary": "Compares two floating-point values and updates process flags (NZCV).", "syntax": "FCMP , ", "encoding": {"format": "FP Compare", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | 00 | 1000 | Rn | 00 | 000", "hex_opcode": "0x1E202000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "00", "clean": "00"}, {"raw": "1000", "clean": "1000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "00", "clean": "00"}, {"raw": "000", "clean": "000"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:14 | 13:10 | 9:5 | 4:3 | 2:0"}, "operands": [{"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}, {"name": "Hm|Sm|Dm|0.0", "desc": "Second source SIMD/FP vector register"}], "extension": "Floating Point", "description": "Compares two floating-point scalar values and updates the NZCV condition flags based on the result. The comparison is performed on the values in the two source registers, and flags are set to reflect whether the first operand is less than, equal to, greater than, or unordered with respect to the second. This is an AArch64-only instruction that does not modify any registers, only the NZCV flags.", "example": "FCMP Dn, Dm|#0.0", "pseudocode": "result ← FPCompare(Vn, Vm)\nN ← result.N\nZ ← result.Z\nC ← result.C\nV ← result.V"} {"mnemonic": "fccmp", "architecture": "ARMv8-A", "full_name": "Floating-Point Conditional Compare (Scalar)", "summary": "Compares floats only if condition is met, else sets flags to immediate.", "syntax": "FCCMP , , #, ", "encoding": {"format": "FP Compare", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | cond | 01 | Rn | 0 | nzcv", "hex_opcode": "0x1E200400", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "cond", "clean": "cond"}, {"raw": "01", "clean": "01"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "0", "clean": "0"}, {"raw": "nzcv", "clean": "nzcv"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:12 | 11:10 | 9:5 | 4 | 3:0"}, "operands": [{"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}, {"name": "Hm|Sm|Dm", "desc": "Second source SIMD&FP register (half, single or double-precision)"}, {"name": "nzcv", "desc": "Def Flags"}, {"name": "cond", "desc": "Condition"}], "extension": "Floating Point", "description": "Conditionally compares two floating-point scalar values if the specified condition is true, updating NZCV flags with the comparison result; if the condition is false, sets NZCV to the immediate value provided. This is an AArch64-only instruction that allows conditional flag updates without branching, useful for implementing conditional chains and complex control flow.", "example": "FCCMP Dn, Dm, #nzcv, cond", "pseudocode": "if ConditionHolds(cond) then\n result ← FPCompare(Vn, Vm)\n N ← result.N\n Z ← result.Z\n C ← result.C\n V ← result.V\nelse\n N ← nzcv[3]\n Z ← nzcv[2]\n C ← nzcv[1]\n V ← nzcv[0]"} {"mnemonic": "fcsel", "architecture": "ARMv8-A", "full_name": "Floating-Point Conditional Select (Scalar)", "summary": "Selects one of two floats based on condition flags.", "syntax": "FCSEL , , , ", "encoding": {"format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | cond | 11 | Rn | Rd", "hex_opcode": "0x1E200C00", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "cond", "clean": "cond"}, {"raw": "11", "clean": "11"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}, {"name": "Hm|Sm|Dm", "desc": "Second source SIMD&FP register (half, single or double-precision)"}, {"name": "cond", "desc": "Condition"}], "extension": "Floating Point", "description": "Selects between two floating-point scalar values based on the current condition flags, writing the selected value to the destination register. If the condition is true, Vn is selected; otherwise, Vm is selected. This is an AArch64-only instruction that does not modify condition flags or any register other than the destination.", "example": "FCSEL Dd, Dn, Dm, cond", "pseudocode": "if ConditionHolds(cond) then\n Vd ← Vn\nelse\n Vd ← Vm"} {"mnemonic": "fcvt", "architecture": "ARMv8-A", "full_name": "Floating-Point Convert (Scalar)", "summary": "Converts between float precisions (e.g., Half <-> Single <-> Double).", "syntax": "FCVT , ", "encoding": {"format": "FP Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 11 | 10001 | 00 | 10000 | Rn | Rd", "hex_opcode": "0x1EE24000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "11", "clean": "11"}, {"raw": "10001", "clean": "10001"}, {"raw": "00", "clean": "00"}, {"raw": "10000", "clean": "10000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:17 | 16:15 | 14:10 | 9:5 | 4:0"}, "operands": [{"name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}], "extension": "Floating Point", "description": "Converts a scalar floating-point value between precision formats (e.g., Half ↔ Single ↔ Double). The rounding mode is determined by FPCR.RMode. Condition flags are not affected. AArch64-only instruction.", "example": "FCVT Dd, Dn", "pseudocode": "operand ← Vn\nresult ← ConvertFP(operand, source_precision, destination_precision, FPCR.RMode)\nVd ← result"} {"mnemonic": "fcvtas", "architecture": "ARMv8-A", "full_name": "Floating-Point Convert to Signed Integer (Nearest)", "summary": "Converts float to signed integer, rounding to nearest.", "syntax": "FCVTAS , ", "encoding": {"format": "FP Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 11 | 1 | 00 | 100 | 000000 | Rn | Rd", "hex_opcode": "0x1EE40000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "11", "clean": "11"}, {"raw": "1", "clean": "1"}, {"raw": "00", "clean": "00"}, {"raw": "100", "clean": "100"}, {"raw": "000000", "clean": "000000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Wd|Xd", "desc": "Destination general-purpose register (32-bit/64-bit)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}], "extension": "Floating Point", "description": "Converts a scalar floating-point value to a signed integer, rounding to nearest with ties away from zero. Sets condition flags based on the integer result. Raises Invalid Operation exception on overflow or invalid input. AArch64-only instruction.", "example": "FCVTAS Wd, Dn", "pseudocode": "operand ← Vn\nintval ← RoundTowardNearestAwayFromZero(operand)\nif intval > MaxInt(destination_width) or intval < MinInt(destination_width) then\n GenerateException(InvalidOperation)\nelse\n Rd ← SignExtend(intval)\n UpdateFlags(intval)\nend"} {"mnemonic": "fcvtau", "architecture": "ARMv8-A", "full_name": "Floating-Point Convert to Unsigned Integer (Nearest)", "summary": "Converts float to unsigned integer, rounding to nearest.", "syntax": "FCVTAU , ", "encoding": {"format": "FP Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 11 | 1 | 00 | 101 | 000000 | Rn | Rd", "hex_opcode": "0x1EE50000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "11", "clean": "11"}, {"raw": "1", "clean": "1"}, {"raw": "00", "clean": "00"}, {"raw": "101", "clean": "101"}, {"raw": "000000", "clean": "000000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Wd|Xd", "desc": "Destination general-purpose register (32-bit/64-bit)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}], "extension": "Floating Point", "description": "Converts a scalar floating-point value to an unsigned integer, rounding to nearest with ties away from zero. Sets condition flags based on the integer result. Raises Invalid Operation exception on overflow or invalid input. AArch64-only instruction.", "example": "FCVTAU Wd, Dn", "pseudocode": "operand ← Vn\nintval ← RoundTowardNearestAwayFromZero(operand)\nif intval > MaxUInt(destination_width) or intval < 0 then\n GenerateException(InvalidOperation)\nelse\n Rd ← ZeroExtend(intval)\n UpdateFlags(intval)\nend"} {"mnemonic": "fcvtms", "architecture": "ARMv8-A", "full_name": "Floating-Point Convert to Signed Integer (Minus Infinity)", "summary": "Converts float to signed integer, rounding towards minus infinity (Floor).", "syntax": "FCVTMS , ", "encoding": {"format": "FP Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | 10 | 000 | 000000 | Rn | Rd", "hex_opcode": "0x1E300000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "10", "clean": "10"}, {"raw": "000", "clean": "000"}, {"raw": "000000", "clean": "000000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Wd|Xd", "desc": "Destination general-purpose register (32-bit/64-bit)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}], "extension": "Floating Point", "description": "Converts a scalar floating-point value to a signed integer, rounding towards negative infinity (floor). Sets condition flags based on the integer result. Raises Invalid Operation exception on overflow or invalid input. AArch64-only instruction.", "example": "FCVTMS Wd, Dn", "pseudocode": "operand ← Vn\nintval ← Floor(operand)\nif intval > MaxInt(destination_width) or intval < MinInt(destination_width) then\n GenerateException(InvalidOperation)\nelse\n Rd ← SignExtend(intval)\n UpdateFlags(intval)\nend"} {"mnemonic": "fcvtmu", "architecture": "ARMv8-A", "full_name": "Floating-Point Convert to Unsigned Integer (Minus Infinity)", "summary": "Converts float to unsigned integer, rounding towards minus infinity.", "syntax": "FCVTMU , ", "encoding": {"format": "FP Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | 10 | 001 | 000000 | Rn | Rd", "hex_opcode": "0x1E310000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "10", "clean": "10"}, {"raw": "001", "clean": "001"}, {"raw": "000000", "clean": "000000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Wd|Xd", "desc": "Destination general-purpose register (32-bit/64-bit)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}], "extension": "Floating Point", "description": "Converts a scalar floating-point value to an unsigned integer, rounding towards negative infinity (floor). Sets condition flags based on the integer result. Raises Invalid Operation exception on overflow or invalid input. AArch64-only instruction.", "example": "FCVTMU Wd, Dn", "pseudocode": "operand ← Vn\nintval ← Floor(operand)\nif intval > MaxUInt(destination_width) or intval < 0 then\n GenerateException(InvalidOperation)\nelse\n Rd ← ZeroExtend(intval)\n UpdateFlags(intval)\nend"} {"mnemonic": "fcvtns", "architecture": "ARMv8-A", "full_name": "Floating-Point Convert to Signed Integer (Nearest, ties to Even)", "summary": "Converts float to signed integer, rounding to nearest (bankers' round).", "syntax": "FCVTNS , ", "encoding": {"format": "FP Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | 00 | 000 | 000000 | Rn | Rd", "hex_opcode": "0x1E200000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "00", "clean": "00"}, {"raw": "000", "clean": "000"}, {"raw": "000000", "clean": "000000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Wd|Xd", "desc": "Destination general-purpose register (32-bit/64-bit)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}], "extension": "Floating Point", "description": "Converts a scalar floating-point value to a signed integer, rounding to nearest with ties to even (bankers' round). Sets condition flags based on the integer result. Raises Invalid Operation exception on overflow or invalid input. AArch64-only instruction.", "example": "FCVTNS Wd, Dn", "pseudocode": "operand ← Vn\nintval ← RoundTowardNearestEven(operand)\nif intval > MaxInt(destination_width) or intval < MinInt(destination_width) then\n GenerateException(InvalidOperation)\nelse\n Rd ← SignExtend(intval)\n UpdateFlags(intval)\nend"} {"mnemonic": "fcvtnu", "architecture": "ARMv8-A", "full_name": "Floating-Point Convert to Unsigned Integer (Nearest, ties to Even)", "summary": "Converts float to unsigned integer, rounding to nearest (bankers' round).", "syntax": "FCVTNU , ", "encoding": {"format": "FP Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | 00 | 001 | 000000 | Rn | Rd", "hex_opcode": "0x1E210000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "00", "clean": "00"}, {"raw": "001", "clean": "001"}, {"raw": "000000", "clean": "000000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Wd|Xd", "desc": "Destination general-purpose register (32-bit/64-bit)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}], "extension": "Floating Point", "description": "Converts a scalar floating-point value to an unsigned integer, rounding to nearest with ties to even (bankers' round). Sets condition flags based on the integer result. Raises Invalid Operation exception on overflow or invalid input. AArch64-only instruction.", "example": "FCVTNU Wd, Dn", "pseudocode": "operand ← Vn\nintval ← RoundTowardNearestEven(operand)\nif intval > MaxUInt(destination_width) or intval < 0 then\n GenerateException(InvalidOperation)\nelse\n Rd ← ZeroExtend(intval)\n UpdateFlags(intval)\nend"} {"mnemonic": "fcvtps", "architecture": "ARMv8-A", "full_name": "Floating-Point Convert to Signed Integer (Plus Infinity)", "summary": "Converts float to signed integer, rounding towards plus infinity (Ceil).", "syntax": "FCVTPS , ", "encoding": {"format": "FP Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | 01 | 000 | 000000 | Rn | Rd", "hex_opcode": "0x1E280000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "01", "clean": "01"}, {"raw": "000", "clean": "000"}, {"raw": "000000", "clean": "000000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Wd|Xd", "desc": "Destination general-purpose register (32-bit/64-bit)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}], "extension": "Floating Point", "description": "Converts a floating-point value to a signed integer, rounding towards plus infinity (ceiling). The source is read from a half-precision (H), single-precision (S), or double-precision (D) FP register, and the result is written to a 32-bit (W) or 64-bit (X) general-purpose register. NZCV flags are not affected by this instruction. This is an AArch64-only instruction that executes at any privilege level.", "example": "FCVTPS Wd, Dn", "pseudocode": "if source_is_nan then\n result ← 0\nelse\n result ← round_to_plus_infinity(FP_to_signed_integer(Vn))\nRd ← result"} {"mnemonic": "fcvtpu", "architecture": "ARMv8-A", "full_name": "Floating-Point Convert to Unsigned Integer (Plus Infinity)", "summary": "Converts float to unsigned integer, rounding towards plus infinity.", "syntax": "FCVTPU , ", "encoding": {"format": "FP Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | 01 | 001 | 000000 | Rn | Rd", "hex_opcode": "0x1E290000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "01", "clean": "01"}, {"raw": "001", "clean": "001"}, {"raw": "000000", "clean": "000000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Wd|Xd", "desc": "Destination general-purpose register (32-bit/64-bit)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}], "extension": "Floating Point", "description": "Converts a floating-point value to an unsigned integer, rounding towards plus infinity (ceiling). The source is read from a half-precision (H), single-precision (S), or double-precision (D) FP register, and the result is written to a 32-bit (W) or 64-bit (X) general-purpose register. NZCV flags are not affected by this instruction. This is an AArch64-only instruction that executes at any privilege level.", "example": "FCVTPU Wd, Dn", "pseudocode": "if source_is_nan then\n result ← 0\nelse\n result ← round_to_plus_infinity(FP_to_unsigned_integer(Vn))\nRd ← result"} {"mnemonic": "fcvtzs", "architecture": "ARMv8-A", "full_name": "Floating-Point Convert to Signed Integer (Zero)", "summary": "Converts float to signed integer, rounding towards zero (Truncate).", "syntax": "FCVTZS , {, #}", "encoding": {"format": "FP Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | 11 | 000 | 000000 | Rn | Rd", "hex_opcode": "0x1E380000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "11", "clean": "11"}, {"raw": "000", "clean": "000"}, {"raw": "000000", "clean": "000000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Wd|Xd", "desc": "Destination general-purpose register (32-bit/64-bit)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}, {"name": "fbits", "desc": "Number of fractional bits"}], "extension": "Floating Point", "description": "Converts a floating-point value to a signed integer, rounding towards zero (truncation). The source is read from a half-precision (H), single-precision (S), or double-precision (D) FP register, and the result is written to a 32-bit (W) or 64-bit (X) general-purpose register. An optional fixed-point shift parameter (fbits) can scale the result by 2^fbits. NZCV flags are not affected by this instruction. This is an AArch64-only instruction that executes at any privilege level.", "example": "FCVTZS Wd, Dn", "pseudocode": "if source_is_nan then\n result ← 0\nelse\n if fbits_present then\n result ← round_towards_zero(FP_to_signed_integer(Vn) × 2^fbits)\n else\n result ← round_towards_zero(FP_to_signed_integer(Vn))\nRd ← result"} {"mnemonic": "fcvtzu", "architecture": "ARMv8-A", "full_name": "Floating-Point Convert to Unsigned Integer (Zero)", "summary": "Converts float to unsigned integer, rounding towards zero (Truncate).", "syntax": "FCVTZU , {, #}", "encoding": {"format": "FP Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | 11 | 001 | 000000 | Rn | Rd", "hex_opcode": "0x1E390000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "11", "clean": "11"}, {"raw": "001", "clean": "001"}, {"raw": "000000", "clean": "000000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Wd|Xd", "desc": "Destination general-purpose register (32-bit/64-bit)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}, {"name": "fbits", "desc": "Number of fractional bits"}], "extension": "Floating Point", "description": "Converts a floating-point value to an unsigned integer, rounding towards zero (truncation). The source is read from a half-precision (H), single-precision (S), or double-precision (D) FP register, and the result is written to a 32-bit (W) or 64-bit (X) general-purpose register. An optional fixed-point shift parameter (fbits) can scale the result by 2^fbits. NZCV flags are not affected by this instruction. This is an AArch64-only instruction that executes at any privilege level.", "example": "FCVTZU Wd, Dn", "pseudocode": "if source_is_nan then\n result ← 0\nelse\n if fbits_present then\n result ← round_towards_zero(FP_to_unsigned_integer(Vn) × 2^fbits)\n else\n result ← round_towards_zero(FP_to_unsigned_integer(Vn))\nRd ← result"} {"mnemonic": "scvtf", "architecture": "ARMv8-A", "full_name": "Signed Integer Convert to Floating-Point", "summary": "Converts signed integer (GPR) to floating-point.", "syntax": "SCVTF , {, #}", "encoding": {"format": "FP Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | 00 | 010 | 000000 | Rn | Rd", "hex_opcode": "0x1E220000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "00", "clean": "00"}, {"raw": "010", "clean": "010"}, {"raw": "000000", "clean": "000000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)"}, {"name": "Wn|Xn", "desc": "First source general-purpose register (32-bit/64-bit)"}], "extension": "Floating Point", "description": "Converts a signed integer value from a GPR to floating-point format and writes the result to an FP scalar register. The conversion respects an optional fixed-point scaling factor (fbits) if provided, effectively dividing the result by 2^fbits. This is an AArch64-only instruction that does not modify condition flags.", "example": "SCVTF Dd, Wn", "pseudocode": "int_val ← SignExtend(Rn)\nif fbits != 0 then\n fp_val ← ConvertToFP(int_val / 2^fbits)\nelse\n fp_val ← ConvertToFP(int_val)\nVd ← fp_val"} {"mnemonic": "ucvtf", "architecture": "ARMv8-A", "full_name": "Unsigned Integer Convert to Floating-Point", "summary": "Converts unsigned integer (GPR) to floating-point.", "syntax": "UCVTF , {, #}", "encoding": {"format": "FP Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | 00 | 011 | 000000 | Rn | Rd", "hex_opcode": "0x1E230000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "00", "clean": "00"}, {"raw": "011", "clean": "011"}, {"raw": "000000", "clean": "000000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)"}, {"name": "Wn|Xn", "desc": "First source general-purpose register (32-bit/64-bit)"}], "extension": "Floating Point", "description": "Converts an unsigned integer value from a GPR to floating-point format and writes the result to an FP scalar register. The conversion respects an optional fixed-point scaling factor (fbits) if provided, effectively dividing the result by 2^fbits. This is an AArch64-only instruction that does not modify condition flags.", "example": "UCVTF Dd, Wn", "pseudocode": "uint_val ← ZeroExtend(Rn)\nif fbits != 0 then\n fp_val ← ConvertToFP(uint_val / 2^fbits)\nelse\n fp_val ← ConvertToFP(uint_val)\nVd ← fp_val"} {"mnemonic": "frinta", "architecture": "ARMv8-A", "full_name": "Floating-Point Round to Integral (Nearest)", "summary": "Rounds float to nearest integral value (ties away from zero).", "syntax": "FRINTA , ", "encoding": {"format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1001 | 100 | 10000 | Rn | Rd", "hex_opcode": "0x1E264000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1001", "clean": "1001"}, {"raw": "100", "clean": "100"}, {"raw": "10000", "clean": "10000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:18 | 17:15 | 14:10 | 9:5 | 4:0"}, "operands": [{"name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}], "extension": "Floating Point", "description": "Rounds a floating-point scalar value to the nearest integral value, with ties rounded away from zero. The rounding mode is always \"round to nearest, ties away from zero\" regardless of the FPCR rounding mode setting. This is an AArch64-only instruction that does not modify condition flags.", "example": "FRINTA Dd, Dn", "pseudocode": "rounded_val ← RoundToIntegral_TiesAwayFromZero(Vn)\nVd ← rounded_val"} {"mnemonic": "frinti", "architecture": "ARMv8-A", "full_name": "Floating-Point Round to Integral (Current)", "summary": "Rounds float to integral value using current FPCR rounding mode.", "syntax": "FRINTI , ", "encoding": {"format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1001 | 111 | 10000 | Rn | Rd", "hex_opcode": "0x1E27C000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1001", "clean": "1001"}, {"raw": "111", "clean": "111"}, {"raw": "10000", "clean": "10000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:18 | 17:15 | 14:10 | 9:5 | 4:0"}, "operands": [{"name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}], "extension": "Floating Point", "description": "Rounds a floating-point scalar value to an integral value using the current rounding mode specified in the FPCR (Floating-Point Control Register). The rounding behavior depends on the RMode field in FPCR. This is an AArch64-only instruction that does not modify condition flags.", "example": "FRINTI Dd, Dn", "pseudocode": "rounded_val ← RoundToIntegral_CurrentMode(Vn) \nVd ← rounded_val"} {"mnemonic": "frintm", "architecture": "ARMv8-A", "full_name": "Floating-Point Round to Integral (Minus Infinity)", "summary": "Rounds float to integral value towards minus infinity (Floor).", "syntax": "FRINTM , ", "encoding": {"format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1001 | 010 | 10000 | Rn | Rd", "hex_opcode": "0x1E254000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1001", "clean": "1001"}, {"raw": "010", "clean": "010"}, {"raw": "10000", "clean": "10000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:18 | 17:15 | 14:10 | 9:5 | 4:0"}, "operands": [{"name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}], "extension": "Floating Point", "description": "Rounds a floating-point scalar value towards negative infinity (floor). The rounding mode is always \"round towards minus infinity\" regardless of the FPCR rounding mode setting. This is an AArch64-only instruction that does not modify condition flags.", "example": "FRINTM Dd, Dn", "pseudocode": "rounded_val ← RoundToIntegral_MinusInfinity(Vn)\nVd ← rounded_val"} {"mnemonic": "frintn", "architecture": "ARMv8-A", "full_name": "Floating-Point Round to Integral (Nearest Even)", "summary": "Rounds float to integral value nearest, ties to even.", "syntax": "FRINTN , ", "encoding": {"format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1001 | 000 | 10000 | Rn | Rd", "hex_opcode": "0x1E244000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1001", "clean": "1001"}, {"raw": "000", "clean": "000"}, {"raw": "10000", "clean": "10000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:18 | 17:15 | 14:10 | 9:5 | 4:0"}, "operands": [{"name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}], "extension": "Floating Point", "description": "Rounds the floating-point value in the source register to the nearest integer using round-to-nearest-ties-to-even mode, and writes the result to the destination register. The instruction does not set any condition flags (N, Z, C, V remain unaffected). Execution is AArch64-only and may generate floating-point exceptions based on the source operand and enabled exception controls.", "example": "FRINTN Dd, Dn", "pseudocode": "Vd ← RoundToNearestEven(Vn)"} {"mnemonic": "frintp", "architecture": "ARMv8-A", "full_name": "Floating-Point Round to Integral (Plus Infinity)", "summary": "Rounds float to integral value towards plus infinity (Ceil).", "syntax": "FRINTP , ", "encoding": {"format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1001 | 001 | 10000 | Rn | Rd", "hex_opcode": "0x1E24C000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1001", "clean": "1001"}, {"raw": "001", "clean": "001"}, {"raw": "10000", "clean": "10000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:18 | 17:15 | 14:10 | 9:5 | 4:0"}, "operands": [{"name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}], "extension": "Floating Point", "description": "Rounds the floating-point value in the source register to the nearest integer towards positive infinity (ceiling), and writes the result to the destination register. The instruction does not set any condition flags (N, Z, C, V remain unaffected). Execution is AArch64-only and may generate floating-point exceptions based on the source operand and enabled exception controls.", "example": "FRINTP Dd, Dn", "pseudocode": "Vd ← RoundTowardsPlusInfinity(Vn)"} {"mnemonic": "frintx", "architecture": "ARMv8-A", "full_name": "Floating-Point Round to Integral (Exact)", "summary": "Rounds float to integral value using current mode, raising Inexact exception.", "syntax": "FRINTX , ", "encoding": {"format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1001 | 110 | 10000 | Rn | Rd", "hex_opcode": "0x1E274000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1001", "clean": "1001"}, {"raw": "110", "clean": "110"}, {"raw": "10000", "clean": "10000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:18 | 17:15 | 14:10 | 9:5 | 4:0"}, "operands": [{"name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}], "extension": "Floating Point", "description": "Rounds the floating-point value in the source register to the nearest integer using the current rounding mode and raises an Inexact floating-point exception if the result differs from the input. The instruction does not set condition flags (N, Z, C, V remain unaffected). Execution is AArch64-only and always signals the Inexact exception condition when rounding occurs.", "example": "FRINTX Dd, Dn", "pseudocode": "Vd ← RoundToIntegral(Vn); if Vd ≠ Vn then RaiseInexactException()"} {"mnemonic": "frintz", "architecture": "ARMv8-A", "full_name": "Floating-Point Round to Integral (Zero)", "summary": "Rounds float to integral value towards zero (Truncate).", "syntax": "FRINTZ , ", "encoding": {"format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1001 | 011 | 10000 | Rn | Rd", "hex_opcode": "0x1E25C000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1001", "clean": "1001"}, {"raw": "011", "clean": "011"}, {"raw": "10000", "clean": "10000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:18 | 17:15 | 14:10 | 9:5 | 4:0"}, "operands": [{"name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}], "extension": "Floating Point", "description": "Rounds the floating-point value in the source register to the nearest integer towards zero (truncation), and writes the result to the destination register. The instruction does not set any condition flags (N, Z, C, V remain unaffected). Execution is AArch64-only and may generate floating-point exceptions based on the source operand and enabled exception controls.", "example": "FRINTZ Dd, Dn", "pseudocode": "Vd ← RoundTowardsZero(Vn)"} {"mnemonic": "fmov", "architecture": "ARMv8-A", "full_name": "Floating-Point Move (Immediate)", "summary": "Moves a floating-point immediate into a scalar register.", "syntax": "FMOV , #", "encoding": {"format": "FP Immediate", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | imm8 | 100 | 00000 | Rd", "hex_opcode": "0x1E201000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "imm8", "clean": "imm8"}, {"raw": "100", "clean": "100"}, {"raw": "00000", "clean": "00000"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)"}, {"name": "fimm", "desc": "Floating-point immediate value"}], "extension": "Floating Point", "description": "Moves a floating-point immediate constant into a half-precision (H), single-precision (S), or double-precision (D) scalar FP register. The immediate is encoded as an 8-bit value and expanded to full precision according to the IEEE 754 floating-point format. NZCV flags are not affected. This is an AArch64-only instruction that executes at any privilege level.", "example": "FMOV Dd, #1.0", "pseudocode": "Vd ← decode_fp_immediate(imm8, type)"} {"mnemonic": "fmov", "architecture": "ARMv8-A", "full_name": "Floating-Point Move (Register)", "summary": "Copies a value from one scalar FP register to another.", "syntax": "FMOV , ", "encoding": {"format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 10000 | 00 | 10000 | Rn | Rd", "hex_opcode": "0x1E204000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "10000", "clean": "10000"}, {"raw": "00", "clean": "00"}, {"raw": "10000", "clean": "10000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:17 | 16:15 | 14:10 | 9:5 | 4:0"}, "operands": [{"name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)"}, {"name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)"}], "extension": "Floating Point", "description": "Copies a floating-point value from one scalar FP register to another, preserving the value and precision. Both source and destination must be the same type (half-precision, single-precision, or double-precision). NZCV flags are not affected. This is an AArch64-only instruction that executes at any privilege level.", "example": "FMOV Dd, Dn", "pseudocode": "Vd ← Vn"} {"mnemonic": "fmov", "architecture": "ARMv8-A", "full_name": "Floating-Point Move (General)", "summary": "Copies bits between a General-Purpose Register (W/X) and FP Register (S/D).", "syntax": "FMOV , ", "encoding": {"format": "FP Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | 00 | 110 | 000000 | Rn | Rd", "hex_opcode": "0x1E260000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "00", "clean": "00"}, {"raw": "110", "clean": "110"}, {"raw": "000000", "clean": "000000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Wd|Xd", "desc": "Destination general-purpose register (32-bit/64-bit)"}, {"name": "Sn|Dn", "desc": "First source SIMD&FP register (single or double-precision)"}], "extension": "Floating Point", "description": "Copies the bit pattern from a floating-point register (single-precision or double-precision) to a general-purpose register (32-bit or 64-bit), treating the value as an opaque bit sequence without any floating-point interpretation. NZCV flags are not affected. This is an AArch64-only instruction that executes at any privilege level.", "example": "FMOV Wd, Sn", "pseudocode": "Rd ← bits(Vn)"} {"mnemonic": "fmov", "architecture": "ARMv8-A", "full_name": "Floating-Point Move (General to FP)", "summary": "Copies bits from a General-Purpose Register (W/X) to FP Register (S/D).", "syntax": "FMOV , ", "encoding": {"format": "FP Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | 00 | 111 | 000000 | Rn | Rd", "hex_opcode": "0x1E270000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "00", "clean": "00"}, {"raw": "111", "clean": "111"}, {"raw": "000000", "clean": "000000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Sd|Dd", "desc": "Destination SIMD&FP register (single or double-precision)"}, {"name": "Wn|Xn", "desc": "First source general-purpose register (32-bit/64-bit)"}], "extension": "Floating Point", "description": "Copies the bit pattern from a general-purpose register (32-bit or 64-bit) to a floating-point register (single-precision or double-precision), treating the value as an opaque bit sequence without any floating-point interpretation. NZCV flags are not affected. This is an AArch64-only instruction that executes at any privilege level.", "example": "FMOV Sd, Wn", "pseudocode": "Vd ← bits(Rn)"} {"mnemonic": "ldr", "architecture": "ARMv8-A", "full_name": "Load SIMD&FP Register (Immediate)", "summary": "Loads a floating-point/SIMD register from memory.", "syntax": "LDR , [, #]", "encoding": {"format": "Load/Store", "binary_pattern": "10 | 111 | 1 | 01 | 01 | imm12 | Rn | Rt", "hex_opcode": "0xBD400000", "visual_parts": [{"raw": "10", "clean": "10"}, {"raw": "111", "clean": "111"}, {"raw": "1", "clean": "1"}, {"raw": "01", "clean": "01"}, {"raw": "01", "clean": "01"}, {"raw": "imm12", "clean": "imm12"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rt", "clean": "Rt"}], "bit_positions": "31:30 | 29:27 | 26 | 25:24 | 23:22 | 21:10 | 9:5 | 4:0"}, "operands": [{"name": "Bt|Ht|St|Dt|Qt", "desc": "Transfer SIMD&FP register (byte, half, single, double or quad-precision)"}, {"name": "Xn|SP", "desc": "First source / base 64-bit integer register"}, {"name": "pimm", "desc": "Positive immediate offset"}], "extension": "Floating Point", "description": "The Load SIMD&FP Register instruction loads a floating-point/SIMD register from memory.", "example": "LDR Qt, [x1, #16]", "pseudocode": "Vt ← Memory[address]"} {"mnemonic": "str", "architecture": "ARMv8-A", "full_name": "Store SIMD&FP Register (Immediate)", "summary": "Stores a floating-point/SIMD register to memory.", "syntax": "STR , [, #]", "encoding": {"format": "Load/Store", "binary_pattern": "10 | 111 | 1 | 01 | 00 | imm12 | Rn | Rt", "hex_opcode": "0xBD000000", "visual_parts": [{"raw": "10", "clean": "10"}, {"raw": "111", "clean": "111"}, {"raw": "1", "clean": "1"}, {"raw": "01", "clean": "01"}, {"raw": "00", "clean": "00"}, {"raw": "imm12", "clean": "imm12"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rt", "clean": "Rt"}], "bit_positions": "31:30 | 29:27 | 26 | 25:24 | 23:22 | 21:10 | 9:5 | 4:0"}, "operands": [{"name": "Bt|Ht|St|Dt|Qt", "desc": "Transfer SIMD&FP register (byte, half, single, double or quad-precision)"}, {"name": "Xn|SP", "desc": "First source / base 64-bit integer register"}, {"name": "pimm", "desc": "Positive immediate offset"}], "extension": "Floating Point", "description": "The Store SIMD&FP Register instruction stores a floating-point/SIMD register to memory.", "example": "STR Qt, [x1, #16]", "pseudocode": "Memory[address] ← Xn"} {"mnemonic": "ldp", "architecture": "ARMv8-A", "full_name": "Load Pair SIMD&FP Registers", "summary": "Loads two floating-point/SIMD registers.", "syntax": "LDP , , [, #]", "encoding": {"format": "Load/Store Pair", "binary_pattern": "00 | 101 | 1 | 010 | 1 | imm7 | Rt2 | Rn | Rt", "hex_opcode": "0x2D400000", "visual_parts": [{"raw": "00", "clean": "00"}, {"raw": "101", "clean": "101"}, {"raw": "1", "clean": "1"}, {"raw": "010", "clean": "010"}, {"raw": "1", "clean": "1"}, {"raw": "imm7", "clean": "imm7"}, {"raw": "Rt2", "clean": "Rt2"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rt", "clean": "Rt"}], "bit_positions": "31:30 | 29:27 | 26 | 25:23 | 22 | 21:15 | 14:10 | 9:5 | 4:0"}, "operands": [{"name": "St1|Dt1|Qt1", "desc": "First transfer SIMD&FP register (single, double or quad-precision)"}, {"name": "St2|Dt2|Qt2", "desc": "Second transfer SIMD&FP register (single, double or quad-precision)"}, {"name": "Xn|SP", "desc": "First source / base 64-bit integer register"}, {"name": "imm", "desc": "Signed immediate value"}], "extension": "Floating Point", "description": "Loads two consecutive floating-point or SIMD vector registers from memory at an address calculated from a base register and a scaled signed immediate offset. The two values are loaded atomically as a pair, and no condition flags are affected. Execution is AArch64-only; the immediate is scaled by the operand size (4 bytes for 32-bit, 8 bytes for 64-bit, 16 bytes for 128-bit).", "example": "LDP Qt1, Qt2, [x1, #16]", "pseudocode": "address ← (Xn | SP) + (imm7 << scale); Vt1 ← [address]; Vt2 ← [address + operand_size]"} {"mnemonic": "stp", "architecture": "ARMv8-A", "full_name": "Store Pair SIMD&FP Registers", "summary": "Stores two floating-point/SIMD registers.", "syntax": "STP , , [, #]", "encoding": {"format": "Load/Store Pair", "binary_pattern": "00 | 101 | 1 | 010 | 0 | imm7 | Rt2 | Rn | Rt", "hex_opcode": "0x2D000000", "visual_parts": [{"raw": "00", "clean": "00"}, {"raw": "101", "clean": "101"}, {"raw": "1", "clean": "1"}, {"raw": "010", "clean": "010"}, {"raw": "0", "clean": "0"}, {"raw": "imm7", "clean": "imm7"}, {"raw": "Rt2", "clean": "Rt2"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rt", "clean": "Rt"}], "bit_positions": "31:30 | 29:27 | 26 | 25:23 | 22 | 21:15 | 14:10 | 9:5 | 4:0"}, "operands": [{"name": "St1|Dt1|Qt1", "desc": "First transfer SIMD&FP register (single, double or quad-precision)"}, {"name": "St2|Dt2|Qt2", "desc": "Second transfer SIMD&FP register (single, double or quad-precision)"}, {"name": "Xn|SP", "desc": "First source / base 64-bit integer register"}, {"name": "imm", "desc": "Signed immediate value"}], "extension": "Floating Point", "description": "Stores two consecutive floating-point or SIMD vector registers to memory at an address calculated from a base register and a scaled signed immediate offset. The two values are stored atomically as a pair, and no condition flags are affected. Execution is AArch64-only; the immediate is scaled by the operand size (4 bytes for 32-bit, 8 bytes for 64-bit, 16 bytes for 128-bit).", "example": "STP Qt1, Qt2, [x1, #16]", "pseudocode": "address ← (Xn | SP) + (imm7 << scale); [address] ← Vt1; [address + operand_size] ← Vt2"} {"mnemonic": "ldrb", "architecture": "ARMv8-A", "full_name": "Load Register Byte (Immediate)", "summary": "Loads a byte from memory (zero-extended) using immediate offset.", "syntax": "LDRB , [, #]", "encoding": {"format": "Load/Store", "binary_pattern": "00 | 111 | 0 | 01 | 01 | imm12 | Rn | Rt", "hex_opcode": "0x39400000", "visual_parts": [{"raw": "00", "clean": "00"}, {"raw": "111", "clean": "111"}, {"raw": "0", "clean": "0"}, {"raw": "01", "clean": "01"}, {"raw": "01", "clean": "01"}, {"raw": "imm12", "clean": "imm12"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rt", "clean": "Rt"}], "bit_positions": "31:30 | 29:27 | 26 | 25:24 | 23:22 | 21:10 | 9:5 | 4:0"}, "operands": [{"name": "Wt", "desc": "Transfer 32-bit integer register (load/store)"}, {"name": "Xn", "desc": "First source / base 64-bit integer register"}, {"name": "pimm", "desc": "Positive immediate offset"}], "extension": "Base", "description": "Loads an unsigned byte from memory using immediate offset and zero-extends it to 32 bits, writing the result to a 32-bit register. No condition flags are affected. This is an AArch64 Base instruction that executes in all privilege levels.", "example": "LDRB w3, [x1, #16]", "pseudocode": "address ← Xn + (pimm << 0);\nWt ← ZeroExtend(Mem[address, 1], 32);"} {"mnemonic": "ldrb", "architecture": "ARMv8-A", "full_name": "Load Register Byte (Register)", "summary": "Loads a byte from memory (zero-extended) using register offset.", "syntax": "LDRB , [, {, }]", "encoding": {"format": "Load/Store", "binary_pattern": "00 | 111 | 0 | 00 | 01 | 1 | Rm | option | S | 10 | Rn | Rt", "hex_opcode": "0x38600800", "visual_parts": [{"raw": "00", "clean": "00"}, {"raw": "111", "clean": "111"}, {"raw": "0", "clean": "0"}, {"raw": "00", "clean": "00"}, {"raw": "01", "clean": "01"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "option", "clean": "option"}, {"raw": "S", "clean": "S"}, {"raw": "10", "clean": "10"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rt", "clean": "Rt"}], "bit_positions": "31:30 | 29:27 | 26 | 25:24 | 23:22 | 21 | 20:16 | 15:13 | 12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Wt", "desc": "Transfer 32-bit integer register (load/store)"}, {"name": "Xn", "desc": "First source / base 64-bit integer register"}, {"name": "Rm", "desc": "Offset Reg"}], "extension": "Base", "description": "Loads an unsigned byte from memory using register offset with optional shift/extension and zero-extends it to 32 bits. No condition flags are affected. This is an AArch64 Base instruction that executes in all privilege levels.", "example": "LDRB w3, [x1, Rm ]", "pseudocode": "offset ← ExtendReg(Rm, extend_type, shift_amount);\naddress ← Xn + offset;\nWt ← ZeroExtend(Mem[address, 1], 32);"} {"mnemonic": "ldrh", "architecture": "ARMv8-A", "full_name": "Load Register Halfword (Immediate)", "summary": "Loads a halfword from memory (zero-extended).", "syntax": "LDRH , [, #]", "encoding": {"format": "Load/Store", "binary_pattern": "01 | 111 | 0 | 01 | 01 | imm12 | Rn | Rt", "hex_opcode": "0x79400000", "visual_parts": [{"raw": "01", "clean": "01"}, {"raw": "111", "clean": "111"}, {"raw": "0", "clean": "0"}, {"raw": "01", "clean": "01"}, {"raw": "01", "clean": "01"}, {"raw": "imm12", "clean": "imm12"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rt", "clean": "Rt"}], "bit_positions": "31:30 | 29:27 | 26 | 25:24 | 23:22 | 21:10 | 9:5 | 4:0"}, "operands": [{"name": "Wt", "desc": "Transfer 32-bit integer register (load/store)"}, {"name": "Xn", "desc": "First source / base 64-bit integer register"}, {"name": "pimm", "desc": "Positive immediate offset"}], "extension": "Base", "description": "Loads an unsigned halfword from memory using immediate offset and zero-extends it to 32 bits. No condition flags are affected. This is an AArch64 Base instruction that executes in all privilege levels.", "example": "LDRH w3, [x1, #16]", "pseudocode": "address ← Xn + (pimm << 1);\nWt ← ZeroExtend(Mem[address, 2], 32);"} {"mnemonic": "ldrh", "architecture": "ARMv8-A", "full_name": "Load Register Halfword (Register)", "summary": "Loads a halfword from memory (zero-extended) using register offset.", "syntax": "LDRH , [, {, }]", "encoding": {"format": "Load/Store", "binary_pattern": "01 | 111 | 0 | 00 | 01 | 1 | Rm | option | S | 10 | Rn | Rt", "hex_opcode": "0x78600800", "visual_parts": [{"raw": "01", "clean": "01"}, {"raw": "111", "clean": "111"}, {"raw": "0", "clean": "0"}, {"raw": "00", "clean": "00"}, {"raw": "01", "clean": "01"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "option", "clean": "option"}, {"raw": "S", "clean": "S"}, {"raw": "10", "clean": "10"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rt", "clean": "Rt"}], "bit_positions": "31:30 | 29:27 | 26 | 25:24 | 23:22 | 21 | 20:16 | 15:13 | 12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Wt", "desc": "Transfer 32-bit integer register (load/store)"}, {"name": "Xn", "desc": "First source / base 64-bit integer register"}, {"name": "Rm", "desc": "Offset Reg"}], "extension": "Base", "description": "Loads an unsigned halfword from memory using register offset with optional extension and zero-extends it to 32 bits. No condition flags are affected. This is an AArch64 Base instruction that executes in all privilege levels.", "example": "LDRH w3, [x1, Rm ]", "pseudocode": "offset ← ExtendReg(Rm, extend_type, shift_amount);\naddress ← Xn + offset;\nWt ← ZeroExtend(Mem[address, 2], 32);"} {"mnemonic": "ldrsb", "architecture": "ARMv8-A", "full_name": "Load Register Signed Byte (Immediate)", "summary": "Loads a byte and sign-extends it to 32-bits.", "syntax": "LDRSB , [, #]", "encoding": {"format": "Load/Store", "binary_pattern": "00 | 111 | 0 | 01 | 11 | imm12 | Rn | Rt", "hex_opcode": "0x39C00000", "visual_parts": [{"raw": "00", "clean": "00"}, {"raw": "111", "clean": "111"}, {"raw": "0", "clean": "0"}, {"raw": "01", "clean": "01"}, {"raw": "11", "clean": "11"}, {"raw": "imm12", "clean": "imm12"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rt", "clean": "Rt"}], "bit_positions": "31:30 | 29:27 | 26 | 25:24 | 23:22 | 21:10 | 9:5 | 4:0"}, "operands": [{"name": "Wt", "desc": "Transfer 32-bit integer register (load/store)"}, {"name": "Xn", "desc": "First source / base 64-bit integer register"}, {"name": "pimm", "desc": "Positive immediate offset"}], "extension": "Base", "description": "Loads a signed byte from memory using immediate offset and sign-extends it to 32 bits. No condition flags are affected. This is an AArch64 Base instruction that executes in all privilege levels.", "example": "LDRSB w3, [x1, #16]", "pseudocode": "address ← Xn + (pimm << 0);\nWt ← SignExtend(Mem[address, 1], 32);"} {"mnemonic": "ldrsb", "architecture": "ARMv8-A", "full_name": "Load Register Signed Byte (64-bit Immediate)", "summary": "Loads a byte and sign-extends it to 64-bits.", "syntax": "LDRSB , [, #]", "encoding": {"format": "Load/Store", "binary_pattern": "00 | 111 | 0 | 01 | 10 | imm12 | Rn | Rt", "hex_opcode": "0x39800000", "visual_parts": [{"raw": "00", "clean": "00"}, {"raw": "111", "clean": "111"}, {"raw": "0", "clean": "0"}, {"raw": "01", "clean": "01"}, {"raw": "10", "clean": "10"}, {"raw": "imm12", "clean": "imm12"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rt", "clean": "Rt"}], "bit_positions": "31:30 | 29:27 | 26 | 25:24 | 23:22 | 21:10 | 9:5 | 4:0"}, "operands": [{"name": "Xt", "desc": "Transfer 64-bit integer register (load/store)"}, {"name": "Xn", "desc": "First source / base 64-bit integer register"}, {"name": "pimm", "desc": "Positive immediate offset"}], "extension": "Base", "description": "Loads a signed byte from memory using immediate offset and sign-extends it to 64 bits. No condition flags are affected. This is an AArch64 Base instruction that executes in all privilege levels.", "example": "LDRSB x3, [x1, #16]", "pseudocode": "address ← Xn + (pimm << 0);\nXt ← SignExtend(Mem[address, 1], 64);"} {"mnemonic": "ldrsw", "architecture": "ARMv8-A", "full_name": "Load Register Signed Word (Immediate)", "summary": "Loads a word and sign-extends it to 64-bits.", "syntax": "LDRSW , [, #]", "encoding": {"format": "Load/Store", "binary_pattern": "10 | 111 | 0 | 01 | 10 | imm12 | Rn | Rt", "hex_opcode": "0xB9800000", "visual_parts": [{"raw": "10", "clean": "10"}, {"raw": "111", "clean": "111"}, {"raw": "0", "clean": "0"}, {"raw": "01", "clean": "01"}, {"raw": "10", "clean": "10"}, {"raw": "imm12", "clean": "imm12"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rt", "clean": "Rt"}], "bit_positions": "31:30 | 29:27 | 26 | 25:24 | 23:22 | 21:10 | 9:5 | 4:0"}, "operands": [{"name": "Xt", "desc": "Transfer 64-bit integer register (load/store)"}, {"name": "Xn", "desc": "First source / base 64-bit integer register"}, {"name": "pimm", "desc": "Positive immediate offset"}], "extension": "Base", "description": "Loads a signed word from memory using immediate offset and sign-extends it to 64 bits. No condition flags are affected. This is an AArch64 Base instruction that executes in all privilege levels.", "example": "LDRSW x3, [x1, #16]", "pseudocode": "address ← Xn + (pimm << 2);\nXt ← SignExtend(Mem[address, 4], 64);"} {"mnemonic": "ldrsw", "architecture": "ARMv8-A", "full_name": "Load Register Signed Word (Literal)", "summary": "Loads a word from PC-relative address and sign-extends to 64-bits.", "syntax": "LDRSW ,
, , ", "encoding": {"format": "NEON Table", "binary_pattern": "111100111 | D | 11 | Vn | Vd | 10 | len | N | 1 | M | 0 | Vm", "hex_opcode": "0xF3B00840", "visual_parts": [{"raw": "111100111", "clean": "111100111"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "len", "clean": "len"}, {"raw": "N", "clean": "N"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Dd", "desc": "Dest/Base"}, {"name": "list", "desc": "Table"}, {"name": "Dm", "desc": "Indices"}], "extension": "NEON (SIMD)", "description": "Performs a table lookup and extension: for each byte index in Dm, looks up the corresponding byte in the table (1-4 registers starting at Vn) and inserts it into the corresponding position in Dd, leaving unmapped indices unchanged in Dd. Condition flags (N, Z, C, V) are unaffected. Execution is restricted to A32/T32 with NEON extension; out-of-range indices preserve the original element in Dd.", "example": "VTBX.8 d0, {r0-r3}, d2", "pseudocode": "for i = 0 to 15 do\n index ← Dm.byte[i]\n if (index < (len + 1) * 16) then\n table_reg ← Vn + (index / 16)\n element_offset ← index mod 16\n Dd.byte[i] ← [table_reg].byte[element_offset]\n else\n Dd.byte[i] ← Dd.byte[i]"} {"mnemonic": "vfma", "architecture": "ARMv8-A", "full_name": "Vector Fused Multiply Accumulate", "summary": "Computes Vd = Vd + (Vn * Vm) with single rounding.", "syntax": "VFMA.F32 , , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 0 | D | 0 | sz | Vn | Vd | 1100 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2000C10", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "0", "clean": "0"}, {"raw": "sz", "clean": "sz"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1100", "clean": "1100"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Dest/Acc"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "VFPv4 (SIMD)", "description": "Fused multiply-accumulate: computes Qd = Qd + (Qn × Qm) on 32-bit floating-point elements with a single rounding operation, improving precision over separate multiply and add. Condition flags (N, Z, C, V) are unaffected. Execution is restricted to A32/T32 with VFPv4 (NEON) extension; operates on 128-bit quad registers.", "example": "VFMA.F32 q0, q1, q2", "pseudocode": "for i = 0 to 3 do\n Qd[i] ← round_to_nearest(Qd[i] + (Qn[i] × Qm[i]))"} {"mnemonic": "vfms", "architecture": "ARMv8-A", "full_name": "Vector Fused Multiply Subtract", "summary": "Computes Vd = Vd - (Vn * Vm) with single rounding.", "syntax": "VFMS.F32 , , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 0 | D | 1 | sz | Vn | Vd | 1100 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2200C10", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "1", "clean": "1"}, {"raw": "sz", "clean": "sz"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1100", "clean": "1100"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Dest/Acc"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "VFPv4 (SIMD)", "description": "Fused multiply-subtract: computes Qd = Qd - (Qn × Qm) on 32-bit floating-point elements with a single rounding operation, improving precision over separate multiply and subtract. Condition flags (N, Z, C, V) are unaffected. Execution is restricted to A32/T32 with VFPv4 (NEON) extension; operates on 128-bit quad registers.", "example": "VFMS.F32 q0, q1, q2", "pseudocode": "for i = 0 to 3 do\n Qd[i] ← round_to_nearest(Qd[i] - (Qn[i] × Qm[i]))"} {"mnemonic": "vfnma", "architecture": "ARMv8-A", "full_name": "Vector Fused Negated Multiply Accumulate", "summary": "Computes Vd = Vd - (Vn * Vm).", "syntax": "VFNMA.F32 , , ", "encoding": {"format": "VFP Arith", "binary_pattern": "cond | 1110 | 1 | D | 01 | Vn | Vd | 10 | 10 | N | 1 | M | 0 | Vm", "hex_opcode": "0x0E900A40", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "1110", "clean": "1110"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "01", "clean": "01"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "N", "clean": "N"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:28 | 27:24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}, {"name": "Sn", "desc": "First source 32-bit floating-point register"}, {"name": "Sm", "desc": "Second source 32-bit floating-point register"}], "extension": "VFPv4 (Float)", "description": "Fused negated multiply-accumulate: computes Sd = Sd - (Sn × Sm) on 32-bit floating-point values with a single rounding operation. Condition flags (N, Z, C, V) are unaffected. Execution is restricted to A32/T32 with VFPv4 (scalar floating-point) extension; operates on 32-bit single-precision registers.", "example": "VFNMA.F32 s0, s1, s2", "pseudocode": "Sd ← round_to_nearest(Sd - (Sn × Sm))"} {"mnemonic": "vfnms", "architecture": "ARMv8-A", "full_name": "Vector Fused Negated Multiply Subtract", "summary": "Computes Vd = -Vd + (Vn * Vm).", "syntax": "VFNMS.F32 , , ", "encoding": {"format": "VFP Arith", "binary_pattern": "cond | 1110 | 1 | D | 01 | Vn | Vd | 10 | 10 | N | 0 | M | 0 | Vm", "hex_opcode": "0x0E900A00", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "1110", "clean": "1110"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "01", "clean": "01"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:28 | 27:24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}, {"name": "Sn", "desc": "First source 32-bit floating-point register"}, {"name": "Sm", "desc": "Second source 32-bit floating-point register"}], "extension": "VFPv4 (Float)", "description": "Vector Fused Negated Multiply Subtract computes the negation of the destination plus the product of two operands: Sd = -Sd + (Sn * Sm). This is a single fused operation that performs multiplication and subtraction with only one rounding step, improving precision over separate operations. The instruction is available in VFPv4 and operates on 32-bit single-precision floating-point values. Condition flags (N, Z, C, V) are not affected; floating-point exception flags may be set based on the result.", "example": "VFNMS.F32 s0, s1, s2", "pseudocode": "Sd ← -Sd + (Sn * Sm)"} {"mnemonic": "vrecps", "architecture": "ARMv8-A", "full_name": "Vector Reciprocal Step", "summary": "Newton-Raphson step for reciprocal refinement: (2 - Vn * Vm).", "syntax": "VRECPS.F32 , , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 0 | D | 0 | sz | Vn | Vd | 1111 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2000F10", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "0", "clean": "0"}, {"raw": "sz", "clean": "sz"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1111", "clean": "1111"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Vector Reciprocal Step performs a Newton-Raphson step for reciprocal refinement on 32-bit floating-point SIMD elements: Qd = 2.0 - (Qn * Qm). This operation is typically used iteratively to refine reciprocal approximations. The instruction operates on 128-bit SIMD registers, processing multiple 32-bit float elements in parallel. No integer flags are affected; floating-point exception flags may be set based on the results.", "example": "VRECPS.F32 q0, q1, q2", "pseudocode": "for i = 0 to 3\n Qd[i] ← 2.0 - (Qn[i] * Qm[i])"} {"mnemonic": "vrsqrts", "architecture": "ARMv8-A", "full_name": "Vector Reciprocal Square Root Step", "summary": "Newton-Raphson step for reciprocal sqrt refinement: (3 - Vn * Vm) / 2.", "syntax": "VRSQRTS.F32 , , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 0 | D | 1 | sz | Vn | Vd | 1111 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2200F10", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "1", "clean": "1"}, {"raw": "sz", "clean": "sz"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1111", "clean": "1111"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Vector Reciprocal Square Root Step performs a Newton-Raphson step for reciprocal square root refinement on 32-bit floating-point SIMD elements: Qd = (3.0 - (Qn * Qm)) / 2.0. This operation is typically used iteratively to refine reciprocal square root approximations. The instruction operates on 128-bit SIMD registers, processing multiple 32-bit float elements in parallel. No integer flags are affected; floating-point exception flags may be set based on the results.", "example": "VRSQRTS.F32 q0, q1, q2", "pseudocode": "for i = 0 to 3\n Qd[i] ← (3.0 - (Qn[i] * Qm[i])) / 2.0"} {"mnemonic": "vpadal", "architecture": "ARMv8-A", "full_name": "Vector Pairwise Add and Accumulate Long", "summary": "Adds adjacent pairs and accumulates into wide destination.", "syntax": "VPADAL.
, ", "encoding": {"format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 00 | Vd | 0 | 110 | op | 0 | M | 0 | Vm", "hex_opcode": "0xF3B00600", "visual_parts": [{"raw": "111100111", "clean": "111100111"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "size", "clean": "size"}, {"raw": "00", "clean": "00"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0", "clean": "0"}, {"raw": "110", "clean": "110"}, {"raw": "op", "clean": "op"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Vector Pairwise Add and Accumulate Long adds adjacent pairs of elements from the source register and accumulates the results into the destination register, which is widened. The data type and element size are specified by the size field; both signed and unsigned variants exist. No condition flags are affected. The destination elements are wider than the source elements to accommodate the accumulated sums.", "example": "VPADAL.dt q0, q2", "pseudocode": "for i = 0 to (pairs_in_Qm - 1)\n Qd[i] ← Qd[i] + (Qm[2*i] + Qm[2*i+1])"} {"mnemonic": "vpaddl", "architecture": "ARMv8-A", "full_name": "Vector Pairwise Add Long", "summary": "Adds adjacent pairs and produces wide result.", "syntax": "VPADDL.
, ", "encoding": {"format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 00 | Vd | 0 | 010 | op | 0 | M | 0 | Vm", "hex_opcode": "0xF3B00200", "visual_parts": [{"raw": "111100111", "clean": "111100111"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "size", "clean": "size"}, {"raw": "00", "clean": "00"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0", "clean": "0"}, {"raw": "010", "clean": "010"}, {"raw": "op", "clean": "op"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Vector Pairwise Add Long adds adjacent pairs of elements from the source register and produces a widened result in the destination register. The data type and element size are specified by the size field; both signed and unsigned variants exist. No condition flags are affected. The destination elements are wider than the source elements to accommodate the pair sums.", "example": "VPADDL.dt q0, q2", "pseudocode": "for i = 0 to (pairs_in_Qm - 1)\n Qd[i] ← Qm[2*i] + Qm[2*i+1]"} {"mnemonic": "vswp", "architecture": "ARMv8-A", "full_name": "Vector Swap", "summary": "Swaps the contents of two vectors.", "syntax": "VSWP , ", "encoding": {"format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | 00 | 10 | Vd | 0 | 0000 | 0 | M | 0 | Vm", "hex_opcode": "0xF3B20000", "visual_parts": [{"raw": "111100111", "clean": "111100111"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "00", "clean": "00"}, {"raw": "10", "clean": "10"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0", "clean": "0"}, {"raw": "0000", "clean": "0000"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Reg 1"}, {"name": "Qm", "desc": "Reg 2"}], "extension": "NEON (SIMD)", "description": "Vector Swap exchanges the entire contents of two SIMD registers. The register sizes (64-bit or 128-bit) are determined by the Q bit in the encoding. This is a data movement operation with no arithmetic or comparison; no condition flags are affected.", "example": "VSWP q0, q2", "pseudocode": "temp ← Qd\nQd ← Qm\nQm ← temp"} {"mnemonic": "vmaxnm", "architecture": "ARMv8-A", "full_name": "Vector Maximum Number", "summary": "Returns larger value, handling NaNs per IEEE 754-2008.", "syntax": "VMAXNM.F32 , , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "111111101 | D | 00 | Vn | Vd | 10 | 10 | N | 0 | M | 0 | Vm", "hex_opcode": "0xFE800A00", "visual_parts": [{"raw": "111111101", "clean": "111111101"}, {"raw": "D", "clean": "D"}, {"raw": "00", "clean": "00"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Vector Maximum Number returns the larger of two 32-bit floating-point values for each lane, handling NaN operands according to IEEE 754-2008 semantics (if one operand is NaN, the non-NaN value is returned). The instruction operates on 128-bit SIMD registers, processing multiple 32-bit float elements in parallel. No integer flags are affected; floating-point exception flags may be set based on the results.", "example": "VMAXNM.F32 q0, q1, q2", "pseudocode": "for i = 0 to 3\n if isNaN(Qn[i]) and not isNaN(Qm[i])\n Qd[i] ← Qm[i]\n else if isNaN(Qm[i]) and not isNaN(Qn[i])\n Qd[i] ← Qn[i]\n else\n Qd[i] ← max(Qn[i], Qm[i])"} {"mnemonic": "vminnm", "architecture": "ARMv8-A", "full_name": "Vector Minimum Number", "summary": "Returns smaller value, handling NaNs per IEEE 754-2008.", "syntax": "VMINNM.F32 , , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "111111101 | D | 00 | Vn | Vd | 10 | 10 | N | 1 | M | 0 | Vm", "hex_opcode": "0xFE800A40", "visual_parts": [{"raw": "111111101", "clean": "111111101"}, {"raw": "D", "clean": "D"}, {"raw": "00", "clean": "00"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "N", "clean": "N"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Vector Minimum Number returns the smaller of two 32-bit floating-point values for each lane, handling NaN operands according to IEEE 754-2008 semantics (if one operand is NaN, the non-NaN value is returned). The instruction operates on 128-bit SIMD registers, processing multiple 32-bit float elements in parallel. No integer flags are affected; floating-point exception flags may be set based on the results.", "example": "VMINNM.F32 q0, q1, q2", "pseudocode": "for i = 0 to 3\n if isNaN(Qn[i]) and not isNaN(Qm[i])\n Qd[i] ← Qm[i]\n else if isNaN(Qm[i]) and not isNaN(Qn[i])\n Qd[i] ← Qn[i]\n else\n Qd[i] ← min(Qn[i], Qm[i])"} {"mnemonic": "vcvta", "architecture": "ARMv8-A", "full_name": "Vector Convert to Integer (Nearest)", "summary": "Converts float to integer, rounding to nearest.", "syntax": "VCVTA.
.F32 , ", "encoding": {"format": "NEON 2-Reg", "binary_pattern": "111111101 | D | 111 | 1 | 00 | Vd | 10 | 10 | op | 1 | M | 0 | Vm", "hex_opcode": "0xFEBC0A40", "visual_parts": [{"raw": "111111101", "clean": "111111101"}, {"raw": "D", "clean": "D"}, {"raw": "111", "clean": "111"}, {"raw": "1", "clean": "1"}, {"raw": "00", "clean": "00"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "op", "clean": "op"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:19 | 18 | 17:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Converts each floating-point element in the source Q register to a signed or unsigned integer, rounding towards positive infinity (towards +∞), and writes the results to the destination Q register. This is a vector operation where each lane is independently converted. No NEON flags are modified; results follow IEEE 754 rounding semantics. This instruction requires NEON support and executes in AArch32 state (T32/A32).", "example": "VCVTA.dt.F32 q0, q2", "pseudocode": "for i ← 0 to (128 / element_width) - 1 do; element ← Qm[i]; integer_result ← ConvertToInteger(element, RoundTowardsPlusInfinity, unsigned); Qd[i] ← integer_result; end"} {"mnemonic": "vcvtn", "architecture": "ARMv8-A", "full_name": "Vector Convert to Integer (Nearest Even)", "summary": "Converts float to integer, rounding to nearest even.", "syntax": "VCVTN.
.F32 , ", "encoding": {"format": "NEON 2-Reg", "binary_pattern": "111111101 | D | 111 | 1 | 01 | Vd | 10 | 10 | op | 1 | M | 0 | Vm", "hex_opcode": "0xFEBD0A40", "visual_parts": [{"raw": "111111101", "clean": "111111101"}, {"raw": "D", "clean": "D"}, {"raw": "111", "clean": "111"}, {"raw": "1", "clean": "1"}, {"raw": "01", "clean": "01"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "op", "clean": "op"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:19 | 18 | 17:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Converts each floating-point element in the source Q register to a signed or unsigned integer, rounding to nearest even (banker's rounding), and writes the results to the destination Q register. This is a vector operation where each lane is independently converted. No NEON flags are modified; results follow IEEE 754 rounding semantics. This instruction requires NEON support and executes in AArch32 state (T32/A32).", "example": "VCVTN.dt.F32 q0, q2", "pseudocode": "for i ← 0 to (128 / element_width) - 1 do; element ← Qm[i]; integer_result ← ConvertToInteger(element, RoundToNearestEven, unsigned); Qd[i] ← integer_result; end"} {"mnemonic": "vcvtp", "architecture": "ARMv8-A", "full_name": "Vector Convert to Integer (Plus Infinity)", "summary": "Converts float to integer, rounding towards +Inf (Ceil).", "syntax": "VCVTP.
.F32 , ", "encoding": {"format": "NEON 2-Reg", "binary_pattern": "111111101 | D | 111 | 1 | 10 | Vd | 10 | 10 | op | 1 | M | 0 | Vm", "hex_opcode": "0xFEBE0A40", "visual_parts": [{"raw": "111111101", "clean": "111111101"}, {"raw": "D", "clean": "D"}, {"raw": "111", "clean": "111"}, {"raw": "1", "clean": "1"}, {"raw": "10", "clean": "10"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "op", "clean": "op"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:19 | 18 | 17:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Converts each floating-point element in the source Q register to a signed or unsigned integer, rounding towards positive infinity (ceiling), and writes the results to the destination Q register. This is a vector operation where each lane is independently converted. No NEON flags are modified; results follow IEEE 754 rounding semantics. This instruction requires NEON support and executes in AArch32 state (T32/A32).", "example": "VCVTP.dt.F32 q0, q2", "pseudocode": "for i ← 0 to (128 / element_width) - 1 do; element ← Qm[i]; integer_result ← ConvertToInteger(element, RoundTowardsPlusInfinity, unsigned); Qd[i] ← integer_result; end"} {"mnemonic": "vcvtm", "architecture": "ARMv8-A", "full_name": "Vector Convert to Integer (Minus Infinity)", "summary": "Converts float to integer, rounding towards -Inf (Floor).", "syntax": "VCVTM.
.F32 , ", "encoding": {"format": "NEON 2-Reg", "binary_pattern": "111111101 | D | 111 | 1 | 11 | Vd | 10 | 10 | op | 1 | M | 0 | Vm", "hex_opcode": "0xFEBF0A40", "visual_parts": [{"raw": "111111101", "clean": "111111101"}, {"raw": "D", "clean": "D"}, {"raw": "111", "clean": "111"}, {"raw": "1", "clean": "1"}, {"raw": "11", "clean": "11"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "op", "clean": "op"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:19 | 18 | 17:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Converts floating-point values in a NEON vector to signed integers, rounding towards negative infinity (floor). This is a NEON SIMD instruction that operates on 32-bit floating-point elements and produces integer results. No condition flags are affected by this instruction.", "example": "VCVTM.dt.F32 q0, q2", "pseudocode": "for i = 0 to elements-1\n Qd[i] ← RoundTowardsMinusInfinity(Qm[i])"} {"mnemonic": "vrinta", "architecture": "ARMv8-A", "full_name": "Vector Round Floating-Point (Nearest)", "summary": "Rounds float to integral float (Nearest).", "syntax": "VRINTA.F32 , ", "encoding": {"format": "NEON 2-Reg", "binary_pattern": "111111101 | D | 111 | 0 | 00 | Vd | 10 | 10 | 0 | 1 | M | 0 | Vm", "hex_opcode": "0xFEB80A40", "visual_parts": [{"raw": "111111101", "clean": "111111101"}, {"raw": "D", "clean": "D"}, {"raw": "111", "clean": "111"}, {"raw": "0", "clean": "0"}, {"raw": "00", "clean": "00"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:19 | 18 | 17:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Rounds each 32-bit floating-point element in the source vector to the nearest integer value, using round-to-nearest (ties away from zero) rounding mode, and writes the result as a floating-point value to the destination vector. This instruction does not modify the condition flags. Available in A32/T32 with NEON extension.", "example": "VRINTA.F32 q0, q2", "pseudocode": "for i = 0 to 3\n Qd[i] ← RoundToNearest(Qm[i])\nend for"} {"mnemonic": "vrintn", "architecture": "ARMv8-A", "full_name": "Vector Round Floating-Point (Nearest Even)", "summary": "Rounds float to integral float (Nearest Even).", "syntax": "VRINTN.F32 , ", "encoding": {"format": "NEON 2-Reg", "binary_pattern": "111111101 | D | 111 | 0 | 01 | Vd | 10 | 10 | 0 | 1 | M | 0 | Vm", "hex_opcode": "0xFEB90A40", "visual_parts": [{"raw": "111111101", "clean": "111111101"}, {"raw": "D", "clean": "D"}, {"raw": "111", "clean": "111"}, {"raw": "0", "clean": "0"}, {"raw": "01", "clean": "01"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:19 | 18 | 17:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Rounds each 32-bit floating-point element in the source vector to the nearest integer value, using round-to-nearest-even (banker's rounding) rounding mode, and writes the result as a floating-point value to the destination vector. This instruction does not modify the condition flags. Available in A32/T32 with NEON extension.", "example": "VRINTN.F32 q0, q2", "pseudocode": "for i = 0 to 3\n Qd[i] ← RoundToNearestEven(Qm[i])\nend for"} {"mnemonic": "vrintz", "architecture": "ARMv8-A", "full_name": "Vector Round Floating-Point (Zero)", "summary": "Rounds float to integral float (Towards Zero).", "syntax": "VRINTZ.F32 , ", "encoding": {"format": "NEON 2-Reg", "binary_pattern": "cond | 11101 | D | 11 | 0 | 110 | Vd | 10 | 10 | 1 | 1 | M | 0 | Vm", "hex_opcode": "0x0EB60AC0", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "11101", "clean": "11101"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "0", "clean": "0"}, {"raw": "110", "clean": "110"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Rounds each 32-bit floating-point element in the source vector towards zero to an integer value, and writes the result as a floating-point value to the destination vector. This instruction does not modify the condition flags. Available in A32/T32 with NEON extension.", "example": "VRINTZ.F32 q0, q2", "pseudocode": "for i = 0 to 3\n Qd[i] ← RoundTowardsZero(Qm[i])\nend for"} {"mnemonic": "vsel", "architecture": "ARMv8-A", "full_name": "Vector Select", "summary": "Selects elements from Dn or Dm based on condition flags (predicated VFP).", "syntax": "VSEL.F32 , , ", "encoding": {"format": "VFP Misc", "binary_pattern": "11111110 | 0 | D | cc | Vn | Vd | 1010 | N | 0 | M | Vm", "hex_opcode": "0xFE000A00", "visual_parts": [{"raw": "11111110", "clean": "11111110"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "cc", "clean": "cc"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1010", "clean": "1010"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "Vm", "clean": "Vm"}]}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}, {"name": "Sn", "desc": "First source 32-bit floating-point register"}, {"name": "Sm", "desc": "Second source 32-bit floating-point register"}], "extension": "VFP (Float)", "description": "Conditionally selects the 32-bit floating-point value from either Sn or Sm based on the current state of the condition flags and writes it to Sd. The condition code (cc) embedded in the instruction determines which flag combination is tested. This instruction does not modify condition flags. Available in A32/T32 with VFP extension.", "example": "VSELcond.F32 s0, s1, s2", "pseudocode": "if ConditionHolds(cc) then\n Sd ← Sn\nelse\n Sd ← Sm\nend if"} {"mnemonic": "aese", "architecture": "ARMv8-A", "full_name": "AES Encrypt (A32)", "summary": "Performs one round of AES encryption (AArch32).", "syntax": "AESE.8 , ", "encoding": {"format": "Crypto 2-Reg", "binary_pattern": "11110011 | 1 | D | 11 | 00 | 00 | Vd | 00110 | Q | M | 0 | Vm", "hex_opcode": "0xF3B00300", "visual_parts": [{"raw": "11110011", "clean": "11110011"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "00", "clean": "00"}, {"raw": "00", "clean": "00"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "00110", "clean": "00110"}, {"raw": "Q", "clean": "Q"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:24 | 23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11:7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Data"}, {"name": "Qm", "desc": "Key"}], "extension": "Crypto", "description": "Performs a single round of AES encryption (SubBytes, ShiftRows, MixColumns, and AddRoundKey stages) on the 128-bit data block in Qd using the 128-bit round key in Qm. The result is written back to Qd. This instruction does not modify the condition flags. Available in A32/T32 with Crypto extension and requires AES feature.", "example": "AESE.8 q0, q2", "pseudocode": "state ← Qd\nround_key ← Qm\nstate ← SubBytes(state)\nstate ← ShiftRows(state)\nstate ← MixColumns(state)\nstate ← AddRoundKey(state, round_key)\nQd ← state"} {"mnemonic": "aesd", "architecture": "ARMv8-A", "full_name": "AES Decrypt (A32)", "summary": "Performs one round of AES decryption (AArch32).", "syntax": "AESD.8 , ", "encoding": {"format": "Crypto 2-Reg", "binary_pattern": "11110011 | 1 | D | 11 | 00 | 00 | Vd | 00111 | Q | M | 0 | Vm", "hex_opcode": "0xF3B00340", "visual_parts": [{"raw": "11110011", "clean": "11110011"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "00", "clean": "00"}, {"raw": "00", "clean": "00"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "00111", "clean": "00111"}, {"raw": "Q", "clean": "Q"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:24 | 23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11:7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Data"}, {"name": "Qm", "desc": "Key"}], "extension": "Crypto", "description": "Performs a single round of AES decryption (InvShiftRows, InvSubBytes, AddRoundKey, and InvMixColumns stages) on the 128-bit data block in Qd using the 128-bit round key in Qm. The result is written back to Qd. This instruction does not modify the condition flags. Available in A32/T32 with Crypto extension and requires AES feature.", "example": "AESD.8 q0, q2", "pseudocode": "state ← Qd\nround_key ← Qm\nstate ← InvShiftRows(state)\nstate ← InvSubBytes(state)\nstate ← AddRoundKey(state, round_key)\nstate ← InvMixColumns(state)\nQd ← state"} {"mnemonic": "aesmc", "architecture": "ARMv8-A", "full_name": "AES Mix Columns (A32)", "summary": "AES Mix Columns transformation.", "syntax": "AESMC.8 , ", "encoding": {"format": "Crypto 2-Reg", "binary_pattern": "11110011 | 1 | D | 11 | 00 | 10 | Vd | 00110 | Q | M | 0 | Vm", "hex_opcode": "0xF3B00380", "visual_parts": [{"raw": "11110011", "clean": "11110011"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "00", "clean": "00"}, {"raw": "10", "clean": "10"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "00110", "clean": "00110"}, {"raw": "Q", "clean": "Q"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:24 | 23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11:7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "Crypto", "description": "Applies the AES MixColumns (forward) transformation to each column of the 128-bit state in Qm and writes the result to Qd. This transformation is equivalent to one round's MixColumns operation and is used in key expansion during AES encryption. This instruction does not modify the condition flags. Available in A32/T32 with Crypto extension and requires AES feature.", "example": "AESMC.8 q0, q2", "pseudocode": "Qd ← AESMixColumns(Qm)"} {"mnemonic": "aesimc", "architecture": "ARMv8-A", "full_name": "AES Inverse Mix Columns (A32)", "summary": "AES Inverse Mix Columns transformation.", "syntax": "AESIMC.8 , ", "encoding": {"format": "Crypto 2-Reg", "binary_pattern": "11110011 | 1 | D | 11 | 00 | 10 | Vd | 00111 | Q | M | 0 | Vm", "hex_opcode": "0xF3B003C0", "visual_parts": [{"raw": "11110011", "clean": "11110011"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "00", "clean": "00"}, {"raw": "10", "clean": "10"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "00111", "clean": "00111"}, {"raw": "Q", "clean": "Q"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:24 | 23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11:7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "Crypto", "description": "Applies the AES Inverse MixColumns (inverse) transformation to each column of the 128-bit state in Qm and writes the result to Qd. This transformation reverses the forward MixColumns operation and is used in equivalent inverse cipher key expansion during AES decryption. This instruction does not modify the condition flags. Available in A32/T32 with Crypto extension and requires AES feature.", "example": "AESIMC.8 q0, q2", "pseudocode": "Qd ← AESInverseMixColumns(Qm)"} {"mnemonic": "sha1c", "architecture": "ARMv8-A", "full_name": "SHA1 Choose (A32)", "summary": "SHA1 hash update (Choose).", "syntax": "SHA1C.32 , , ", "encoding": {"format": "Crypto 3-Reg", "binary_pattern": "11110010 | 0 | 0 | 0 | Vn | Vd | 0011 | N | Q | M | 0 | Vm", "hex_opcode": "0xF2000C00", "visual_parts": [{"raw": "11110010", "clean": "11110010"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0011", "clean": "0011"}, {"raw": "N", "clean": "N"}, {"raw": "Q", "clean": "Q"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}]}, "operands": [{"name": "Qd", "desc": "State"}, {"name": "Qn", "desc": "Hash"}, {"name": "Qm", "desc": "Data"}], "extension": "Crypto", "description": "SHA1 Choose function: updates SHA1 hash state by computing the Choose operation on 32-bit elements. This instruction performs a cryptographic hash round step specific to SHA1 and is part of the ARM Cryptographic Extension. No condition flags are affected. Available in A32 and T32 with Crypto extension support.", "example": "SHA1C.32 q0, q1, q2", "pseudocode": "Qd[127:96] ← SHA1_CHOOSE(Qd[127:96], Qn[127:96], Qm[127:96])\nQd[95:64] ← SHA1_CHOOSE(Qd[95:64], Qn[95:64], Qm[95:64])\nQd[63:32] ← SHA1_CHOOSE(Qd[63:32], Qn[63:32], Qm[63:32])\nQd[31:0] ← SHA1_CHOOSE(Qd[31:0], Qn[31:0], Qm[31:0])"} {"mnemonic": "sha1h", "architecture": "ARMv8-A", "full_name": "SHA1 Hash Update (A32)", "summary": "Updates SHA1 hash state.", "syntax": "SHA1H.32 , ", "encoding": {"format": "Crypto 2-Reg", "binary_pattern": "11110011 | 1 | D | 11 | 10 | 10 | Vd | 00000 | Q | M | 1 | Vm", "hex_opcode": "0xF3B102C0", "visual_parts": [{"raw": "11110011", "clean": "11110011"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "00000", "clean": "00000"}, {"raw": "Q", "clean": "Q"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:24 | 23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11:7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "Crypto", "description": "SHA1 Hash Update: performs the final hash update step in the SHA1 algorithm by processing the hash state. This instruction computes the SHA1 hash finalization on four 32-bit words in parallel. No condition flags are affected. Available in A32 and T32 with Crypto extension support.", "example": "SHA1H.32 q0, q2", "pseudocode": "Qd[127:96] ← ROTATE_LEFT(Qm[127:96], 30)\nQd[95:64] ← ROTATE_LEFT(Qm[95:64], 30)\nQd[63:32] ← ROTATE_LEFT(Qm[63:32], 30)\nQd[31:0] ← ROTATE_LEFT(Qm[31:0], 30)"} {"mnemonic": "sha1m", "architecture": "ARMv8-A", "full_name": "SHA1 Majority (A32)", "summary": "SHA1 hash update (Majority).", "syntax": "SHA1M.32 , , ", "encoding": {"format": "Crypto 3-Reg", "binary_pattern": "11110010 | 0 | 0 | 10 | Vn | Vd | 0011 | N | Q | M | 0 | Vm", "hex_opcode": "0xF2200C00", "visual_parts": [{"raw": "11110010", "clean": "11110010"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "10", "clean": "10"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0011", "clean": "0011"}, {"raw": "N", "clean": "N"}, {"raw": "Q", "clean": "Q"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "State"}, {"name": "Qn", "desc": "Hash"}, {"name": "Qm", "desc": "Data"}], "extension": "Crypto", "description": "SHA1 Majority function: updates SHA1 hash state by computing the Majority operation on 32-bit elements. This instruction performs a cryptographic hash round step specific to SHA1 and is part of the ARM Cryptographic Extension. No condition flags are affected. Available in A32 and T32 with Crypto extension support.", "example": "SHA1M.32 q0, q1, q2", "pseudocode": "Qd[127:96] ← SHA1_MAJORITY(Qd[127:96], Qn[127:96], Qm[127:96])\nQd[95:64] ← SHA1_MAJORITY(Qd[95:64], Qn[95:64], Qm[95:64])\nQd[63:32] ← SHA1_MAJORITY(Qd[63:32], Qn[63:32], Qm[63:32])\nQd[31:0] ← SHA1_MAJORITY(Qd[31:0], Qn[31:0], Qm[31:0])"} {"mnemonic": "sha1p", "architecture": "ARMv8-A", "full_name": "SHA1 Parity (A32)", "summary": "SHA1 hash update (Parity).", "syntax": "SHA1P.32 , , ", "encoding": {"format": "Crypto 3-Reg", "binary_pattern": "11110010 | 0 | 0 | 01 | Vn | Vd | 0011 | N | Q | M | 0 | Vm", "hex_opcode": "0xF2100C00", "visual_parts": [{"raw": "11110010", "clean": "11110010"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "01", "clean": "01"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0011", "clean": "0011"}, {"raw": "N", "clean": "N"}, {"raw": "Q", "clean": "Q"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "State"}, {"name": "Qn", "desc": "Hash"}, {"name": "Qm", "desc": "Data"}], "extension": "Crypto", "description": "SHA1 Parity function: updates SHA1 hash state by computing the Parity operation on 32-bit elements. This instruction performs a cryptographic hash round step specific to SHA1 and is part of the ARM Cryptographic Extension. No condition flags are affected. Available in A32 and T32 with Crypto extension support.", "example": "SHA1P.32 q0, q1, q2", "pseudocode": "Qd[127:96] ← SHA1_PARITY(Qd[127:96], Qn[127:96], Qm[127:96])\nQd[95:64] ← SHA1_PARITY(Qd[95:64], Qn[95:64], Qm[95:64])\nQd[63:32] ← SHA1_PARITY(Qd[63:32], Qn[63:32], Qm[63:32])\nQd[31:0] ← SHA1_PARITY(Qd[31:0], Qn[31:0], Qm[31:0])"} {"mnemonic": "crc32b", "architecture": "ARMv8-A", "full_name": "CRC32 Byte (A32)", "summary": "CRC32 checksum update (Byte).", "syntax": "CRC32B , , ", "encoding": {"format": "Data Proc", "binary_pattern": "cond | 00010 | 00 | 0 | Rn | Rd | 0 | 0 | 0 | 0 | 0100 | Rm", "hex_opcode": "0x01000040", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00010", "clean": "00010"}, {"raw": "00", "clean": "00"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0100", "clean": "0100"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "Acc"}, {"name": "Rm", "desc": "Data"}], "extension": "CRC", "description": "CRC32 Checksum Update (Byte): accumulates a 32-bit CRC checksum by processing a single byte from the input. Rd is updated with CRC32(Rn, Rm[7:0]) using the standard CRC32 polynomial. No condition flags are affected. Subject to condition code in A32; available in A32 only with CRC extension.", "example": "CRC32B r0, r1, r2", "pseudocode": "Rd ← CRC32_POLYNOMIAL(Rn, Rm[7:0])"} {"mnemonic": "crc32w", "architecture": "ARMv8-A", "full_name": "CRC32 Word (A32)", "summary": "CRC32 checksum update (Word).", "syntax": "CRC32W , , ", "encoding": {"format": "Data Proc", "binary_pattern": "cond | 00010 | 10 | 0 | Rn | Rd | 0 | 0 | 0 | 0 | 0100 | Rm", "hex_opcode": "0x01400040", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00010", "clean": "00010"}, {"raw": "10", "clean": "10"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0100", "clean": "0100"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "Acc"}, {"name": "Rm", "desc": "Data"}], "extension": "CRC", "description": "CRC32 Checksum Update (Word): accumulates a 32-bit CRC checksum by processing a full 32-bit word from the input. Rd is updated with CRC32(Rn, Rm[31:0]) using the standard CRC32 polynomial. No condition flags are affected. Subject to condition code in A32; available in A32 only with CRC extension.", "example": "CRC32W r0, r1, r2", "pseudocode": "Rd ← CRC32_POLYNOMIAL(Rn, Rm[31:0])"} {"mnemonic": "smc", "architecture": "ARMv8-A", "full_name": "Secure Monitor Call (A32)", "summary": "Calls the Secure Monitor (EL3).", "syntax": "SMC #", "encoding": {"format": "System", "binary_pattern": "cond | 00010 | 11 | 0 | 000000000000 | 0111 | imm4", "hex_opcode": "0x01600070", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00010", "clean": "00010"}, {"raw": "11", "clean": "11"}, {"raw": "0", "clean": "0"}, {"raw": "000000000000", "clean": "000000000000"}, {"raw": "0111", "clean": "0111"}, {"raw": "imm4", "clean": "imm4"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:8 | 7:4 | 3:0"}, "operands": [{"name": "imm", "desc": "ID"}], "extension": "A32 (System)", "description": "Secure Monitor Call: a synchronous exception that transitions execution to the Secure Monitor at EL3 to handle a secure service request. The immediate value encodes the SMC ID for the handler. This instruction requires Secure state; execution in Non-secure state is subject to the SMCNC trap. Subject to condition code in A32.", "example": "SMC #16", "pseudocode": "exception_taken ← 'SMC'\nELR_EL3 ← PC + 4\nSPSR_EL3 ← CPSR\nCPSR.M ← '10110' (Monitor mode)\nPC ← VECTOR_SMC"} {"mnemonic": "lda", "architecture": "ARMv8-A", "full_name": "Load Acquire (A32)", "summary": "Loads a word with Acquire semantics.", "syntax": "LDA , []", "encoding": {"format": "Load/Store", "binary_pattern": "cond | 00011 | 00 | 1 | Rn | Rt | 1 | 1 | 0 | 0 | 1001 | 1111", "hex_opcode": "0x01900C9F", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00011", "clean": "00011"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rt", "clean": "Rt"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "1001", "clean": "1001"}, {"raw": "1111", "clean": "1111"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rt", "desc": "Transfer general-purpose register (load/store)"}, {"name": "Rn", "desc": "First source / base general-purpose register"}], "extension": "A32 (Atomic)", "description": "Load Acquire: loads a 32-bit word from memory with Acquire semantics, ensuring memory synchronization and preventing subsequent memory operations from being reordered before this load. The address is computed from Rn (no offset). No condition flags are affected. Subject to condition code in A32; available in A32 with Atomic extension.", "example": "LDA r3, [r1]", "pseudocode": "Rt ← [Rn]\nAcquire_Semantics()"} {"mnemonic": "stl", "architecture": "ARMv8-A", "full_name": "Store Release (A32)", "summary": "Stores a word with Release semantics.", "syntax": "STL , []", "encoding": {"format": "Load/Store", "binary_pattern": "cond | 00011 | 00 | 0 | Rn | 1111 | 1 | 1 | 0 | 0 | 1001 | Rt", "hex_opcode": "0x0180FC90", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00011", "clean": "00011"}, {"raw": "00", "clean": "00"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "1111", "clean": "1111"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "1001", "clean": "1001"}, {"raw": "Rt", "clean": "Rt"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rt", "desc": "Transfer general-purpose register (load/store)"}, {"name": "Rn", "desc": "First source / base general-purpose register"}], "extension": "A32 (Atomic)", "description": "Stores a 32-bit word to memory with Release semantics, ensuring all prior memory operations are visible to other observers before the store completes. No condition flags are affected. This is an A32-only instruction that provides atomic release semantics for synchronization.", "example": "STL r3, [r1]", "pseudocode": "address ← Rn\nMemoryOrder ← Release\n[address] ← Rt[31:0]\nDRAIN_RELEASE_BARRIER()"} {"mnemonic": "ldaex", "architecture": "ARMv8-A", "full_name": "Load Acquire Exclusive (A32)", "summary": "Loads a word with Acquire Exclusive semantics.", "syntax": "LDAEX , []", "encoding": {"format": "Load/Store", "binary_pattern": "cond | 00011 | 00 | 1 | Rn | Rt | 1 | 1 | 1 | 0 | 1001 | 1111", "hex_opcode": "0x01900E9F", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00011", "clean": "00011"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rt", "clean": "Rt"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "1001", "clean": "1001"}, {"raw": "1111", "clean": "1111"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rt", "desc": "Transfer general-purpose register (load/store)"}, {"name": "Rn", "desc": "First source / base general-purpose register"}], "extension": "A32 (Atomic)", "description": "Loads a 32-bit word from memory with Acquire Exclusive semantics, allowing subsequent memory operations to observe earlier loads and stores. The processor acquires exclusive access to the address for potential paired store-exclusive. No condition flags are affected. This is an A32-only instruction.", "example": "LDAEX r3, [r1]", "pseudocode": "address ← Rn\nMemoryOrder ← Acquire\nRt ← [address]\nSET_EXCLUSIVE_MONITOR(address)\nDRAIN_ACQUIRE_BARRIER()"} {"mnemonic": "stlex", "architecture": "ARMv8-A", "full_name": "Store Release Exclusive (A32)", "summary": "Stores a word with Release Exclusive semantics.", "syntax": "STLEX , , []", "encoding": {"format": "Load/Store", "binary_pattern": "cond | 00011 | 00 | 0 | Rn | Rd | 1 | 1 | 1 | 0 | 1001 | Rt", "hex_opcode": "0x01800E90", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00011", "clean": "00011"}, {"raw": "00", "clean": "00"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "1001", "clean": "1001"}, {"raw": "Rt", "clean": "Rt"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Status"}, {"name": "Rt", "desc": "Transfer general-purpose register (load/store)"}, {"name": "Rn", "desc": "First source / base general-purpose register"}], "extension": "A32 (Atomic)", "description": "Atomically stores a 32-bit word to memory with Release semantics and exclusive access, writing status to Rd. This A32 instruction is used for inter-processor synchronization and memory ordering. The status register Rd is written with 0 on success or 1 on failure; no condition flags are affected.", "example": "STLEX r0, r3, [r1]", "pseudocode": "if ExclusiveAccess[Rn] then\n [Rn] ← Rt\n Rd ← 0\n ClearExclusiveAccess()\nelse\n Rd ← 1"} {"mnemonic": "bfdot", "architecture": "ARMv8-A", "full_name": "BFloat16 Dot Product (NEON)", "summary": "Computes dot product of BFloat16 elements, accumulating to Float32 (NEON).", "syntax": "BFDOT ., ., .", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "0 | Q | 1 | 01110 | 01 | 0 | Rm | 1 | 1111 | 1 | Rn | Rd", "hex_opcode": "0x2E40FC00", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "Q", "clean": "Q"}, {"raw": "1", "clean": "1"}, {"raw": "01110", "clean": "01110"}, {"raw": "01", "clean": "01"}, {"raw": "0", "clean": "0"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "1", "clean": "1"}, {"raw": "1111", "clean": "1111"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15 | 14:11 | 10 | 9:5 | 4:0"}, "operands": [{"name": "Vd", "desc": "Dest (F32)"}, {"name": "Vn", "desc": "Src1 (BF16)"}, {"name": "Vm", "desc": "Src2 (BF16)"}], "extension": "FEAT_BF16 (AI)", "description": "Computes the dot product of BFloat16 pairs from two NEON vectors and accumulates the Float32 result into the destination vector. Requires FEAT_BF16. No flags are affected. Operates on 128-bit NEON vectors with BFloat16 source elements.", "example": "BFDOT v0.4s.T, v1.4s.T, v2.4s.T", "pseudocode": "for i = 0 to elements-1 do\n product ← BF16_to_F32(Vn[2*i]) × BF16_to_F32(Vm[2*i]) +\n BF16_to_F32(Vn[2*i+1]) × BF16_to_F32(Vm[2*i+1])\n Vd[i] ← Vd[i] + product\nend for"} {"mnemonic": "bfmmla", "architecture": "ARMv8-A", "full_name": "BFloat16 Matrix Multiply-Accumulate (NEON)", "summary": "Performs 2x2 matrix multiplication on BFloat16 tiles (NEON).", "syntax": "BFMMLA ., ., .", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "0 | 1 | 1 | 01110 | 01 | 0 | Rm | 1 | 1101 | 1 | Rn | Rd", "hex_opcode": "0x6E40EC00", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "01110", "clean": "01110"}, {"raw": "01", "clean": "01"}, {"raw": "0", "clean": "0"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "1", "clean": "1"}, {"raw": "1101", "clean": "1101"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15 | 14:11 | 10 | 9:5 | 4:0"}, "operands": [{"name": "Vd", "desc": "Destination SIMD/FP vector register"}, {"name": "Vn", "desc": "First source SIMD/FP vector register"}, {"name": "Vm", "desc": "Second source SIMD/FP vector register"}], "extension": "FEAT_BF16 (AI)", "description": "Performs a 2×2 matrix multiply-accumulate operation on BFloat16 tiles, accumulating the result into Float32 elements of the destination vector. Requires FEAT_BF16. No flags are affected. Operates on 128-bit NEON vectors.", "example": "BFMMLA v0.4s.T, v1.4s.T, v2.4s.T", "pseudocode": "for i = 0 to 1 do\n for j = 0 to 1 do\n sum ← Vd[i*2+j]\n for k = 0 to 1 do\n sum ← sum + (BF16_to_F32(Vn[i*2+k]) × BF16_to_F32(Vm[k*2+j]))\n end for\n Vd[i*2+j] ← sum\n end for\nend for"} {"mnemonic": "bfcvtn", "architecture": "ARMv8-A", "full_name": "BFloat16 Convert Narrow (NEON)", "summary": "Converts Float32 to BFloat16 (Lower Half).", "syntax": "BFCVTN ., .", "encoding": {"format": "NEON 2-Reg", "binary_pattern": "0 | Q | 0 | 01110 | 10 | 10000 | 10110 | 10 | Rn | Rd", "hex_opcode": "0x0EA16800", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "Q", "clean": "Q"}, {"raw": "0", "clean": "0"}, {"raw": "01110", "clean": "01110"}, {"raw": "10", "clean": "10"}, {"raw": "10000", "clean": "10000"}, {"raw": "10110", "clean": "10110"}, {"raw": "10", "clean": "10"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:17 | 16:12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Vd", "desc": "Dest (BF16)"}, {"name": "Vn", "desc": "Src (F32)"}], "extension": "FEAT_BF16 (AI)", "description": "Converts Float32 values from the first half of the source vector to BFloat16 format and stores them in the lower half of the destination vector, leaving the upper half unchanged. Requires FEAT_BF16. No flags are affected. Operates on NEON vectors.", "example": "BFCVTN v0.4s.Tb, v1.4s.Ta", "pseudocode": "for i = 0 to 3 do\n Vd[i] ← F32_to_BF16(Vn[i])\nend for\nVd[8:4] ← Vd[8:4] // Upper half unchanged"} {"mnemonic": "bfcvtn2", "architecture": "ARMv8-A", "full_name": "BFloat16 Convert Narrow High (NEON)", "summary": "Converts Float32 to BFloat16 (Upper Half).", "syntax": "BFCVTN2 ., .", "encoding": {"format": "NEON 2-Reg", "binary_pattern": "0 | Q | 0 | 01110 | 10 | 10000 | 10110 | 10 | Rn | Rd", "hex_opcode": "0x0EA16800", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "Q", "clean": "Q"}, {"raw": "0", "clean": "0"}, {"raw": "01110", "clean": "01110"}, {"raw": "10", "clean": "10"}, {"raw": "10000", "clean": "10000"}, {"raw": "10110", "clean": "10110"}, {"raw": "10", "clean": "10"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:17 | 16:12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Vd", "desc": "Dest (BF16)"}, {"name": "Vn", "desc": "Src (F32)"}], "extension": "FEAT_BF16 (AI)", "description": "Converts Float32 values from the source vector to BFloat16 format and stores them in the upper half of the destination vector, leaving the lower half unchanged. Requires FEAT_BF16. No flags are affected. Operates on NEON vectors.", "example": "BFCVTN2 v0.4s.Tb, v1.4s.Ta", "pseudocode": "for i = 0 to 3 do\n Vd[i+4] ← F32_to_BF16(Vn[i])\nend for\nVd[3:0] ← Vd[3:0] // Lower half unchanged"} {"mnemonic": "smmla", "architecture": "ARMv8-A", "full_name": "Signed Integer Matrix Multiply-Accumulate (NEON)", "summary": "Performs 2x2 matrix multiplication on Signed Int8 tiles.", "syntax": "SMMLA ., ., .", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "0 | 1 | 0 | 01110 | 10 | 0 | Rm | 1010 | 0 | 1 | Rn | Rd", "hex_opcode": "0x4E80A400", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "01110", "clean": "01110"}, {"raw": "10", "clean": "10"}, {"raw": "0", "clean": "0"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "1010", "clean": "1010"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:12 | 11 | 10 | 9:5 | 4:0"}, "operands": [{"name": "Vd", "desc": "Destination SIMD/FP vector register"}, {"name": "Vn", "desc": "First source SIMD/FP vector register"}, {"name": "Vm", "desc": "Second source SIMD/FP vector register"}], "extension": "FEAT_I8MM (AI)", "description": "Performs a 2×2 signed integer matrix multiply-accumulate operation on Int8 tiles, accumulating the result into Int32 elements of the destination vector. Requires FEAT_I8MM. No flags are affected. Operates on 128-bit NEON vectors.", "example": "SMMLA v0.4s.T, v1.4s.T, v2.4s.T", "pseudocode": "for i = 0 to 1 do\n for j = 0 to 1 do\n sum ← Vd[i*4+j*4 : i*4+j*4+31]\n for k = 0 to 1 do\n sum ← sum + (SignExtend(Vn[i*4+k*4 : i*4+k*4+7]) × SignExtend(Vm[k*4+j*4 : k*4+j*4+7]))\n end for\n Vd[i*4+j*4 : i*4+j*4+31] ← sum\n end for\nend for"} {"mnemonic": "ummla", "architecture": "ARMv8-A", "full_name": "Unsigned Integer Matrix Multiply-Accumulate (NEON)", "summary": "Performs 2x2 matrix multiplication on Unsigned Int8 tiles.", "syntax": "UMMLA ., ., .", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "0 | 1 | 1 | 01110 | 10 | 0 | Rm | 1010 | 0 | 1 | Rn | Rd", "hex_opcode": "0x6E80A400", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "01110", "clean": "01110"}, {"raw": "10", "clean": "10"}, {"raw": "0", "clean": "0"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "1010", "clean": "1010"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:12 | 11 | 10 | 9:5 | 4:0"}, "operands": [{"name": "Vd", "desc": "Destination SIMD/FP vector register"}, {"name": "Vn", "desc": "First source SIMD/FP vector register"}, {"name": "Vm", "desc": "Second source SIMD/FP vector register"}], "extension": "FEAT_I8MM (AI)", "description": "Performs a 2×2 unsigned integer matrix multiply-accumulate operation on Int8 tiles, accumulating the result into Int32 elements of the destination vector. Requires FEAT_I8MM. No flags are affected. Operates on 128-bit NEON vectors.", "example": "UMMLA v0.4s.T, v1.4s.T, v2.4s.T", "pseudocode": "for i = 0 to 1 do\n for j = 0 to 1 do\n sum ← Vd[i*4+j*4 : i*4+j*4+31]\n for k = 0 to 1 do\n sum ← sum + (ZeroExtend(Vn[i*4+k*4 : i*4+k*4+7]) × ZeroExtend(Vm[k*4+j*4 : k*4+j*4+7]))\n end for\n Vd[i*4+j*4 : i*4+j*4+31] ← sum\n end for\nend for"} {"mnemonic": "usmmla", "architecture": "ARMv8-A", "full_name": "Unsigned-Signed Matrix Multiply-Accumulate (NEON)", "summary": "Matrix multiply Unsigned Int8 with Signed Int8.", "syntax": "USMMLA ., ., .", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "0 | 1 | 0 | 01110 | 10 | 0 | Rm | 1010 | 1 | 1 | Rn | Rd", "hex_opcode": "0x4E80AC00", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "01110", "clean": "01110"}, {"raw": "10", "clean": "10"}, {"raw": "0", "clean": "0"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "1010", "clean": "1010"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:12 | 11 | 10 | 9:5 | 4:0"}, "operands": [{"name": "Vd", "desc": "Destination SIMD/FP vector register"}, {"name": "Vn", "desc": "Unsigned"}, {"name": "Vm", "desc": "Signed"}], "extension": "FEAT_I8MM (AI)", "description": "Performs an unsigned-signed 8-bit integer matrix multiply-accumulate operation, multiplying unsigned Int8 elements from Vn with signed Int8 elements from Vm and accumulating the results into Vd. This instruction operates on 128-bit NEON vectors and requires the FEAT_I8MM (Advanced SIMD and Floating-point Extension 2) architectural feature. No condition flags are affected; this is an AArch64-only instruction.", "example": "USMMLA v0.4s.T, v1.4s.T, v2.4s.T", "pseudocode": "for e = 0 to (128 / 32) - 1\n Vd[e] ← Vd[e] + (Vn[4×e:4×e+3] × Vm[4×e:4×e+3])\n // Each element is 32-bit int32, products of 4×uint8 × 4×sint8"} {"mnemonic": "usdot", "architecture": "ARMv8-A", "full_name": "Unsigned-Signed Dot Product (NEON)", "summary": "Dot product of Unsigned Int8 and Signed Int8.", "syntax": "USDOT ., ., .", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "0 | Q | 0 | 01110 | 10 | 0 | Rm | 1 | 0011 | 1 | Rn | Rd", "hex_opcode": "0x0E809C00", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "Q", "clean": "Q"}, {"raw": "0", "clean": "0"}, {"raw": "01110", "clean": "01110"}, {"raw": "10", "clean": "10"}, {"raw": "0", "clean": "0"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "1", "clean": "1"}, {"raw": "0011", "clean": "0011"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15 | 14:11 | 10 | 9:5 | 4:0"}, "operands": [{"name": "Vd", "desc": "Destination SIMD/FP vector register"}, {"name": "Vn", "desc": "Unsigned"}, {"name": "Vm", "desc": "Signed"}], "extension": "FEAT_I8MM (AI)", "description": "Performs an unsigned-signed 8-bit integer dot product, multiplying unsigned Int8 elements from Vn with signed Int8 elements from Vm and accumulating into 32-bit integer lanes of Vd. This instruction operates on 128-bit NEON vectors and requires the FEAT_I8MM architectural feature. No condition flags are affected; this is an AArch64-only instruction.", "example": "USDOT v0.4s.T, v1.4s.T, v2.4s.T", "pseudocode": "for e = 0 to (128 / 32) - 1\n Vd[e] ← Vd[e] + (uint(Vn[4×e]) × sint(Vm[4×e]) +\n uint(Vn[4×e+1]) × sint(Vm[4×e+1]) +\n uint(Vn[4×e+2]) × sint(Vm[4×e+2]) +\n uint(Vn[4×e+3]) × sint(Vm[4×e+3]))\n // Each Vd[e] is a 32-bit signed result"} {"mnemonic": "sudot", "architecture": "ARMv8-A", "full_name": "Signed-Unsigned Dot Product (NEON)", "summary": "Dot product of Signed Int8 and Unsigned Int8 (Indexed).", "syntax": "SUDOT ., ., .[]", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "0 | Q | 0 | 01111 | 0 | 0 | L | M | Rm | 1111 | H | 0 | Rn | Rd", "hex_opcode": "0x0F00F000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "Q", "clean": "Q"}, {"raw": "0", "clean": "0"}, {"raw": "01111", "clean": "01111"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "L", "clean": "L"}, {"raw": "M", "clean": "M"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "1111", "clean": "1111"}, {"raw": "H", "clean": "H"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11 | 10 | 9:5 | 4:0"}, "operands": [{"name": "Vd", "desc": "Destination SIMD/FP vector register"}, {"name": "Vn", "desc": "Signed"}, {"name": "Vm", "desc": "Unsigned"}], "extension": "FEAT_I8MM (AI)", "description": "Performs a signed-unsigned 8-bit integer dot product with an indexed operand, multiplying signed Int8 elements from Vn with unsigned Int8 elements from a specific 32-bit lane of Vm and accumulating into 32-bit integer lanes of Vd. This instruction operates on 128-bit NEON vectors and requires the FEAT_I8MM architectural feature. No condition flags are affected; this is an AArch64-only instruction.", "example": "SUDOT v0.4s.T, v1.4s.T, v2.4s.T[index]", "pseudocode": "// Vm is indexed; extract the 32-bit lane containing 4 unsigned Int8 values\nfor e = 0 to (128 / 32) - 1\n lane_data ← Vm[32×index + 0 : 32×index + 31]\n Vd[e] ← Vd[e] + (sint(Vn[4×e]) × uint(lane_data[7:0]) +\n sint(Vn[4×e+1]) × uint(lane_data[15:8]) +\n sint(Vn[4×e+2]) × uint(lane_data[23:16]) +\n sint(Vn[4×e+3]) × uint(lane_data[31:24]))\n // Each Vd[e] is a 32-bit signed result"} {"mnemonic": "mrrs", "architecture": "ARMv8-A", "full_name": "Move to Two Registers from System Register (128-bit)", "summary": "Reads a 128-bit system register into two general-purpose registers.", "syntax": "MRRS , , ", "encoding": {"format": "System", "binary_pattern": "1101010101 | 1 | 1 | o0 | op1 | CRn | CRm | op2 | Rt", "hex_opcode": "0xD5700000", "visual_parts": [{"raw": "1101010101", "clean": "1101010101"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "o0", "clean": "o0"}, {"raw": "op1", "clean": "op1"}, {"raw": "CRn", "clean": "CRn"}, {"raw": "CRm", "clean": "CRm"}, {"raw": "op2", "clean": "op2"}, {"raw": "Rt", "clean": "Rt"}], "bit_positions": "31:22 | 21 | 20 | 19 | 18:16 | 15:12 | 11:8 | 7:5 | 4:0"}, "operands": [{"name": "Xt", "desc": "Lo"}, {"name": "Xt+1", "desc": "Hi"}, {"name": "sysreg", "desc": "Reg"}], "extension": "FEAT_SYSREG128", "description": "Reads a 128-bit system register into two consecutive 64-bit general-purpose registers (Xt and Xt+1). This is an AArch64-only instruction requiring FEAT_SYSREG128 and may require elevated privilege depending on the system register being accessed. No condition flags are affected.", "example": "MRRS x3, Xt+1, sysreg", "pseudocode": "Xt ← SYSREG[sysreg][63:0]\nXt+1 ← SYSREG[sysreg][127:64]"} {"mnemonic": "msrr", "architecture": "ARMv8-A", "full_name": "Move Two Registers to System Register (128-bit)", "summary": "Writes two general-purpose registers into a 128-bit system register.", "syntax": "MSRR , , ", "encoding": {"format": "System", "binary_pattern": "1101010101 | 0 | 1 | o0 | op1 | CRn | CRm | op2 | Rt", "hex_opcode": "0xD5500000", "visual_parts": [{"raw": "1101010101", "clean": "1101010101"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "o0", "clean": "o0"}, {"raw": "op1", "clean": "op1"}, {"raw": "CRn", "clean": "CRn"}, {"raw": "CRm", "clean": "CRm"}, {"raw": "op2", "clean": "op2"}, {"raw": "Rt", "clean": "Rt"}], "bit_positions": "31:22 | 21 | 20 | 19 | 18:16 | 15:12 | 11:8 | 7:5 | 4:0"}, "operands": [{"name": "sysreg", "desc": "Reg"}, {"name": "Xt", "desc": "Lo"}, {"name": "Xt+1", "desc": "Hi"}], "extension": "FEAT_SYSREG128", "description": "Writes two consecutive 64-bit general-purpose registers (Xt and Xt+1) into a 128-bit system register. This is an AArch64-only instruction requiring FEAT_SYSREG128 and may require elevated privilege depending on the system register being accessed. No condition flags are affected.", "example": "MSRR sysreg, x3, Xt+1", "pseudocode": "SYSREG[sysreg][63:0] ← Xt\nSYSREG[sysreg][127:64] ← Xt+1"} {"mnemonic": "irg", "architecture": "ARMv8-A", "full_name": "Insert Random Tag", "summary": "Inserts a random Allocation Tag into a pointer (MTE).", "syntax": "IRG , {, }", "encoding": {"format": "Data Processing", "binary_pattern": "1 | 0 | 0 | 11010110 | Xm | 000100 | Xn | Xd", "hex_opcode": "0x9AC01000", "visual_parts": [{"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11010110", "clean": "11010110"}, {"raw": "Xm", "clean": "Xm"}, {"raw": "000100", "clean": "000100"}, {"raw": "Xn", "clean": "Xn"}, {"raw": "Xd", "clean": "Xd"}], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Xd", "desc": "Dest Ptr"}, {"name": "Xn", "desc": "Src Ptr"}, {"name": "Xm", "desc": "Exclude Mask"}], "extension": "MTE (Memory Tagging)", "description": "Inserts a randomly selected Allocation Tag into a pointer held in Xn or SP, optionally excluding tags specified by a mask in Xm, and stores the result in Xd or SP. This instruction is only available in AArch64 and requires the MTE (Memory Tagging Extension) feature. The random tag selection is unpredictable from software perspective; no condition flags are affected.", "example": "IRG x0, x1", "pseudocode": "if Xm is not present then\n exclude_mask ← 0x0000000000000000\nelse\n exclude_mask ← Xm\ntag ← random_tag_not_in(exclude_mask)\nXd ← (Xn & ~0xF000000000000000) | (tag << 56)"} {"mnemonic": "gmi", "architecture": "ARMv8-A", "full_name": "Get Memory Tag Intersection", "summary": "Calculates a mask of excluded tags (MTE).", "syntax": "GMI , , ", "encoding": {"format": "Data Processing", "binary_pattern": "1 | 0 | 0 | 11010110 | Xm | 000101 | Xn | Xd", "hex_opcode": "0x9AC01400", "visual_parts": [{"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11010110", "clean": "11010110"}, {"raw": "Xm", "clean": "Xm"}, {"raw": "000101", "clean": "000101"}, {"raw": "Xn", "clean": "Xn"}, {"raw": "Xd", "clean": "Xd"}], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Xd", "desc": "Dest Mask"}, {"name": "Xn", "desc": "Ptr"}, {"name": "Xm", "desc": "Excluded"}], "extension": "MTE (Memory Tagging)", "description": "Calculates the intersection of an Allocation Tag mask (tags excluded from Xm) with tags that are NOT present in the pointer Xn, returning a 16-bit mask of valid alternative tags in Xd. This instruction is only available in AArch64 and requires the MTE feature. No condition flags are affected.", "example": "GMI x0, x1, x2", "pseudocode": "ptr_tag ← (Xn >> 56) & 0xF\nexclude_mask ← Xm & 0xFFFF\nvalid_tags ← ~exclude_mask & 0xFFFF\n// Return mask of tags that are both valid (not excluded) and different from current tag\nXd ← valid_tags & ~(1 << ptr_tag)"} {"mnemonic": "ldg", "architecture": "ARMv8-A", "full_name": "Load Allocation Tag", "summary": "Loads the Allocation Tag from memory.", "syntax": "LDG , [, #]", "encoding": {"format": "Load/Store", "binary_pattern": "11011001 | 01 | 1 | imm9 | 00 | Xn | Xt", "hex_opcode": "0xD9600000", "visual_parts": [{"raw": "11011001", "clean": "11011001"}, {"raw": "01", "clean": "01"}, {"raw": "1", "clean": "1"}, {"raw": "imm9", "clean": "imm9"}, {"raw": "00", "clean": "00"}, {"raw": "Xn", "clean": "Xn"}, {"raw": "Xt", "clean": "Xt"}], "bit_positions": "31:24 | 23:22 | 21 | 20:12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Xt", "desc": "Transfer 64-bit integer register (load/store)"}, {"name": "Xn", "desc": "First source / base 64-bit integer register"}, {"name": "simm", "desc": "Signed immediate offset"}], "extension": "MTE (Memory Tagging)", "description": "Loads the Allocation Tag from a 16-byte granule in memory at address [Xn + simm] and places it into the tag field (bits [59:56]) of Xt, with the lower 56 bits zeroed. This instruction is only available in AArch64 and requires the MTE feature. The simm9 immediate is scaled by 16 (granule size). No condition flags are affected.", "example": "LDG x3, [x1, #-8]", "pseudocode": "address ← Xn + (simm << 4) // simm is a signed 9-bit value, scaled by 16\nmemory_tag ← load_tag_from_memory(address)\nXt ← (memory_tag << 56) & 0xF000000000000000"} {"mnemonic": "stg", "architecture": "ARMv8-A", "full_name": "Store Allocation Tag", "summary": "Stores the Allocation Tag to memory.", "syntax": "STG , [, #]", "encoding": {"format": "Load/Store", "binary_pattern": "11011001 | 00 | 1 | imm9 | 01 | Xn | Xt", "hex_opcode": "0xD9200400", "visual_parts": [{"raw": "11011001", "clean": "11011001"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "imm9", "clean": "imm9"}, {"raw": "01", "clean": "01"}, {"raw": "Xn", "clean": "Xn"}, {"raw": "Xt", "clean": "Xt"}], "bit_positions": "31:24 | 23:22 | 21 | 20:12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Xt", "desc": "Tag Src"}, {"name": "Xn", "desc": "First source / base 64-bit integer register"}, {"name": "simm", "desc": "Signed immediate offset"}], "extension": "MTE (Memory Tagging)", "description": "Stores the Allocation Tag from Xt (bits [59:56]) into the tag storage of a 16-byte granule at address [Xn + simm]. This instruction is only available in AArch64 and requires the MTE feature. The simm9 immediate is scaled by 16. Data in the granule is not modified. No condition flags are affected.", "example": "STG Xt, [x1, #-8]", "pseudocode": "address ← Xn + (simm << 4) // simm is a signed 9-bit value, scaled by 16\ntag_to_store ← (Xt >> 56) & 0xF\nstore_tag_to_memory(address, tag_to_store)"} {"mnemonic": "stzg", "architecture": "ARMv8-A", "full_name": "Store Allocation Tag and Zero", "summary": "Stores the Allocation Tag and zeros the data granule.", "syntax": "STZG , [, #]", "encoding": {"format": "Load/Store", "binary_pattern": "11011001 | 01 | 1 | imm9 | 10 | Xn | Xt", "hex_opcode": "0xD9600800", "visual_parts": [{"raw": "11011001", "clean": "11011001"}, {"raw": "01", "clean": "01"}, {"raw": "1", "clean": "1"}, {"raw": "imm9", "clean": "imm9"}, {"raw": "10", "clean": "10"}, {"raw": "Xn", "clean": "Xn"}, {"raw": "Xt", "clean": "Xt"}], "bit_positions": "31:24 | 23:22 | 21 | 20:12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Xt", "desc": "Tag Src"}, {"name": "Xn", "desc": "First source / base 64-bit integer register"}, {"name": "simm", "desc": "Signed immediate offset"}], "extension": "MTE (Memory Tagging)", "description": "Stores the Allocation Tag from Xt (bits [59:56]) into tag storage at address [Xn + simm] and simultaneously zeros all 16 bytes of the data granule at that address. This instruction is only available in AArch64 and requires the MTE feature. The simm9 immediate is scaled by 16. No condition flags are affected; this is a combined tag-write and memory-zero operation.", "example": "STZG Xt, [x1, #-8]", "pseudocode": "address ← Xn + (simm << 4) // simm is a signed 9-bit value, scaled by 16\ntag_to_store ← (Xt >> 56) & 0xF\nstore_tag_to_memory(address, tag_to_store)\nfor i = 0 to 15\n memory[address + i] ← 0"} {"mnemonic": "st2g", "architecture": "ARMv8-A", "full_name": "Store Allocation Tag (Two Granules)", "summary": "Stores the Allocation Tag to two memory granules.", "syntax": "ST2G , [, #]", "encoding": {"format": "Load/Store", "binary_pattern": "11011001 | 10 | 1 | imm9 | 10 | Xn | Xt", "hex_opcode": "0xD9A00800", "visual_parts": [{"raw": "11011001", "clean": "11011001"}, {"raw": "10", "clean": "10"}, {"raw": "1", "clean": "1"}, {"raw": "imm9", "clean": "imm9"}, {"raw": "10", "clean": "10"}, {"raw": "Xn", "clean": "Xn"}, {"raw": "Xt", "clean": "Xt"}], "bit_positions": "31:24 | 23:22 | 21 | 20:12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Xt", "desc": "Source Tag"}, {"name": "Xn", "desc": "First source / base 64-bit integer register"}, {"name": "simm", "desc": "Signed immediate offset"}], "extension": "MTE (Memory Tagging)", "description": "Stores the Allocation Tag from Xt to two consecutive 16-byte memory granules at [Xn + offset]. The offset is scaled by 16. Both granules receive the same tag. No condition flags are affected. AArch64-only; requires MTE extension.", "example": "ST2G Xt, [x1, #-8]", "pseudocode": "address ← Xn + (SignExtend(imm9, 9) << 4)\ntag ← GetAllocationTag(Xt)\nmemory[address] ← memory[address] with tag set to tag\nmemory[address + 16] ← memory[address + 16] with tag set to tag"} {"mnemonic": "stgp", "architecture": "ARMv8-A", "full_name": "Store Allocation Tag and Pair", "summary": "Stores Tag and two 64-bit data values.", "syntax": "STGP , , [, #]", "encoding": {"format": "Load/Store", "binary_pattern": "01 | 101 | 0 | 010 | 0 | simm7 | Xt2 | Xn | Xt", "hex_opcode": "0x69000000", "visual_parts": [{"raw": "01", "clean": "01"}, {"raw": "101", "clean": "101"}, {"raw": "0", "clean": "0"}, {"raw": "010", "clean": "010"}, {"raw": "0", "clean": "0"}, {"raw": "simm7", "clean": "simm7"}, {"raw": "Xt2", "clean": "Xt2"}, {"raw": "Xn", "clean": "Xn"}, {"raw": "Xt", "clean": "Xt"}], "bit_positions": "31:30 | 29:27 | 26 | 25:23 | 22 | 21:15 | 14:10 | 9:5 | 4:0"}, "operands": [{"name": "Xt", "desc": "Data 1"}, {"name": "Xt2", "desc": "Data 2"}, {"name": "Xn", "desc": "First source / base 64-bit integer register"}], "extension": "MTE (Memory Tagging)", "description": "Stores the Allocation Tag to a 16-byte memory address and simultaneously stores two 64-bit values from Xt and Xt2 (the pair register following Xt). The tag is derived from Xt, and the offset is scaled by 16. This instruction requires MTE support, does not modify the condition flags, and operates only in AArch64 execution state.", "example": "STGP x3, x4, [x1, #-8]", "pseudocode": "address ← (Xn | SP) + (simm7 << 4)\ntag ← Xt[3:0]\nmemory[address:address+7] ← Xt[63:0]\nmemory[address+8:address+15] ← Xt2[63:0]\nmemory[address][3:0] ← tag"} {"mnemonic": "subp", "architecture": "ARMv8-A", "full_name": "Subtract Pointers", "summary": "Subtracts pointers ignoring Tags.", "syntax": "SUBP , , ", "encoding": {"format": "Data Processing", "binary_pattern": "1 | 0 | 0 | 11010110 | Xm | 000000 | Xn | Xd", "hex_opcode": "0x9AC00000", "visual_parts": [{"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11010110", "clean": "11010110"}, {"raw": "Xm", "clean": "Xm"}, {"raw": "000000", "clean": "000000"}, {"raw": "Xn", "clean": "Xn"}, {"raw": "Xd", "clean": "Xd"}], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Xd", "desc": "Destination 64-bit integer register"}, {"name": "Xn", "desc": "Ptr 1"}, {"name": "Xm", "desc": "Ptr 2"}], "extension": "MTE (Memory Tagging)", "description": "Subtracts the pointer in Xm from the pointer in Xn, removing any Allocation Tags from both operands before performing the subtraction. The result is stored in Xd. This instruction does not modify the condition flags and operates only in AArch64 execution state with MTE support.", "example": "SUBP x0, x1, x2", "pseudocode": "Xd ← (Xn | SP)[55:0] - (Xm | SP)[55:0]"} {"mnemonic": "pacia", "architecture": "ARMv8-A", "full_name": "Pointer Authentication Code (Inst A)", "summary": "Signs a pointer in Xd using Key A and modifier Xm (or SP).", "syntax": "PACIA , ", "encoding": {"format": "Data Processing", "binary_pattern": "1 | 1 | 0 | 11010110 | 00001 | 00 | 0 | 000 | Rn | Rd", "hex_opcode": "0xDAC10000", "visual_parts": [{"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "11010110", "clean": "11010110"}, {"raw": "00001", "clean": "00001"}, {"raw": "00", "clean": "00"}, {"raw": "0", "clean": "0"}, {"raw": "000", "clean": "000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:14 | 13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Xd", "desc": "Ptr"}, {"name": "Xn", "desc": "Modifier"}], "extension": "PAC (Security)", "description": "Signs the pointer in Xd using the Instruction key A and a modifier from Xn or SP, storing the Pointer Authentication Code (PAC) in the high bits of Xd. The instruction does not modify the condition flags and operates only in AArch64 execution state with PAC support. The operation is implementation-defined; a PACIA PACIASP variant uses SP as the modifier when Xn is omitted.", "example": "PACIA x0, x1", "pseudocode": "modifier ← Xn | SP\nXd ← AddPAC(Xd, modifier, key_a, instruction_key)"} {"mnemonic": "pacib", "architecture": "ARMv8-A", "full_name": "Pointer Authentication Code (Inst B)", "summary": "Signs a pointer in Xd using Key B.", "syntax": "PACIB , ", "encoding": {"format": "Data Processing", "binary_pattern": "1 | 1 | 0 | 11010110 | 00001 | 00 | 0 | 001 | Rn | Rd", "hex_opcode": "0xDAC10400", "visual_parts": [{"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "11010110", "clean": "11010110"}, {"raw": "00001", "clean": "00001"}, {"raw": "00", "clean": "00"}, {"raw": "0", "clean": "0"}, {"raw": "001", "clean": "001"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:14 | 13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Xd", "desc": "Ptr"}, {"name": "Xn", "desc": "Modifier"}], "extension": "PAC (Security)", "description": "Signs the pointer in Xd using the Instruction key B and a modifier from Xn or SP, storing the Pointer Authentication Code (PAC) in the high bits of Xd. The instruction does not modify the condition flags and operates only in AArch64 execution state with PAC support. The operation is implementation-defined; a PACIB PACIBSP variant uses SP as the modifier when Xn is omitted.", "example": "PACIB x0, x1", "pseudocode": "modifier ← Xn | SP\nXd ← AddPAC(Xd, modifier, key_b, instruction_key)"} {"mnemonic": "pacda", "architecture": "ARMv8-A", "full_name": "Pointer Authentication Code (Data A)", "summary": "Signs a data pointer using Key A.", "syntax": "PACDA , ", "encoding": {"format": "Data Processing", "binary_pattern": "1 | 1 | 0 | 11010110 | 00001 | 00 | 0 | 010 | Rn | Rd", "hex_opcode": "0xDAC10800", "visual_parts": [{"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "11010110", "clean": "11010110"}, {"raw": "00001", "clean": "00001"}, {"raw": "00", "clean": "00"}, {"raw": "0", "clean": "0"}, {"raw": "010", "clean": "010"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:14 | 13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Xd", "desc": "Ptr"}, {"name": "Xn", "desc": "Modifier"}], "extension": "PAC (Security)", "description": "Signs the data pointer in Xd using the Data key A and a modifier from Xn or SP, storing the Pointer Authentication Code (PAC) in the high bits of Xd. The instruction does not modify the condition flags and operates only in AArch64 execution state with PAC support. The operation is implementation-defined and typically used for signing data pointers rather than instruction pointers.", "example": "PACDA x0, x1", "pseudocode": "modifier ← Xn | SP\nXd ← AddPAC(Xd, modifier, key_a, data_key)"} {"mnemonic": "pacdb", "architecture": "ARMv8-A", "full_name": "Pointer Authentication Code (Data B)", "summary": "Signs a data pointer using Key B.", "syntax": "PACDB , ", "encoding": {"format": "Data Processing", "binary_pattern": "1 | 1 | 0 | 11010110 | 00001 | 00 | 0 | 011 | Rn | Rd", "hex_opcode": "0xDAC10C00", "visual_parts": [{"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "11010110", "clean": "11010110"}, {"raw": "00001", "clean": "00001"}, {"raw": "00", "clean": "00"}, {"raw": "0", "clean": "0"}, {"raw": "011", "clean": "011"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:14 | 13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Xd", "desc": "Ptr"}, {"name": "Xn", "desc": "Modifier"}], "extension": "PAC (Security)", "description": "Signs the data pointer in Xd using the Data key B and a modifier from Xn or SP, storing the Pointer Authentication Code (PAC) in the high bits of Xd. The instruction does not modify the condition flags and operates only in AArch64 execution state with PAC support. The operation is implementation-defined and typically used for signing data pointers rather than instruction pointers.", "example": "PACDB x0, x1", "pseudocode": "modifier ← Xn | SP\nXd ← AddPAC(Xd, modifier, key_b, data_key)"} {"mnemonic": "autia", "architecture": "ARMv8-A", "full_name": "Authenticate Code (Inst A)", "summary": "Authenticates a pointer signed with Key A. Corrupts pointer if failed.", "syntax": "AUTIA , ", "encoding": {"format": "Data Processing", "binary_pattern": "1 | 1 | 0 | 11010110 | 00001 | 00 | 0 | 100 | Rn | Rd", "hex_opcode": "0xDAC11000", "visual_parts": [{"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "11010110", "clean": "11010110"}, {"raw": "00001", "clean": "00001"}, {"raw": "00", "clean": "00"}, {"raw": "0", "clean": "0"}, {"raw": "100", "clean": "100"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:14 | 13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Xd", "desc": "Ptr"}, {"name": "Xn", "desc": "Modifier"}], "extension": "PAC (Security)", "description": "Authenticates a 64-bit pointer in Xd using Key A and a modifier from Xn or SP. If authentication fails, the pointer is corrupted with a known bit pattern. This instruction is AArch64-only and requires the PAC (Pointer Authentication Code) extension. It does not affect the condition flags (N, Z, C, V) but may generate an exception if executed in an inappropriate context.", "example": "AUTIA x0, x1", "pseudocode": "authenticated_pointer ← AuthenticatePointer(Xd, Xn, KeyA)\nif authentication_fails then\n Xd ← corrupted_value\nelse\n Xd ← authenticated_pointer\nend if"} {"mnemonic": "autib", "architecture": "ARMv8-A", "full_name": "Authenticate Code (Inst B)", "summary": "Authenticates a pointer signed with Key B.", "syntax": "AUTIB , ", "encoding": {"format": "Data Processing", "binary_pattern": "1 | 1 | 0 | 11010110 | 00001 | 00 | 0 | 101 | Rn | Rd", "hex_opcode": "0xDAC11400", "visual_parts": [{"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "11010110", "clean": "11010110"}, {"raw": "00001", "clean": "00001"}, {"raw": "00", "clean": "00"}, {"raw": "0", "clean": "0"}, {"raw": "101", "clean": "101"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:14 | 13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Xd", "desc": "Ptr"}, {"name": "Xn", "desc": "Modifier"}], "extension": "PAC (Security)", "description": "Authenticates a 64-bit pointer in Xd using Key B and a modifier from Xn or SP. If authentication fails, the pointer is corrupted with a known bit pattern. This instruction is AArch64-only and requires the PAC (Pointer Authentication Code) extension. It does not affect the condition flags (N, Z, C, V) but may generate an exception if executed in an inappropriate context.", "example": "AUTIB x0, x1", "pseudocode": "authenticated_pointer ← AuthenticatePointer(Xd, Xn, KeyB)\nif authentication_fails then\n Xd ← corrupted_value\nelse\n Xd ← authenticated_pointer\nend if"} {"mnemonic": "xpaci", "architecture": "ARMv8-A", "full_name": "Strip Pointer Authentication Code (Inst)", "summary": "Removes the PAC signature from an instruction pointer.", "syntax": "XPACI ", "encoding": {"format": "Data Processing", "binary_pattern": "1 | 1 | 0 | 11010110 | 00001 | 01000 | 0 | 11111 | Rd", "hex_opcode": "0xDAC143E0", "visual_parts": [{"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "11010110", "clean": "11010110"}, {"raw": "00001", "clean": "00001"}, {"raw": "01000", "clean": "01000"}, {"raw": "0", "clean": "0"}, {"raw": "11111", "clean": "11111"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:11 | 10 | 9:5 | 4:0"}, "operands": [{"name": "Xd", "desc": "Ptr"}], "extension": "PAC (Security)", "description": "Strips the Pointer Authentication Code from a 64-bit instruction pointer in Xd without verifying the signature. This instruction is AArch64-only and requires the PAC extension. The condition flags (N, Z, C, V) are not affected, and the operation is not privileged.", "example": "XPACI x0", "pseudocode": "Xd ← StripPAC(Xd, InstructionPointer)"} {"mnemonic": "xpacd", "architecture": "ARMv8-A", "full_name": "Strip Pointer Authentication Code (Data)", "summary": "Removes the PAC signature from a data pointer.", "syntax": "XPACD ", "encoding": {"format": "Data Processing", "binary_pattern": "1 | 1 | 0 | 11010110 | 00001 | 01000 | 1 | 11111 | Rd", "hex_opcode": "0xDAC147E0", "visual_parts": [{"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "11010110", "clean": "11010110"}, {"raw": "00001", "clean": "00001"}, {"raw": "01000", "clean": "01000"}, {"raw": "1", "clean": "1"}, {"raw": "11111", "clean": "11111"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:11 | 10 | 9:5 | 4:0"}, "operands": [{"name": "Xd", "desc": "Ptr"}], "extension": "PAC (Security)", "description": "Strips the Pointer Authentication Code from a 64-bit data pointer in Xd without verifying the signature. This instruction is AArch64-only and requires the PAC extension. The condition flags (N, Z, C, V) are not affected, and the operation is not privileged.", "example": "XPACD x0", "pseudocode": "Xd ← StripPAC(Xd, DataPointer)"} {"mnemonic": "ldraa", "architecture": "ARMv8-A", "full_name": "Load Register Authenticate (Key A)", "summary": "Loads a value, authenticating the address with Key A.", "syntax": "LDRAA , [, #]", "encoding": {"format": "Load/Store", "binary_pattern": "11 | 111 | 0 | 00 | 0 | S | 1 | imm9 | 0 | 1 | Rn | Rt", "hex_opcode": "0xF8200400", "visual_parts": [{"raw": "11", "clean": "11"}, {"raw": "111", "clean": "111"}, {"raw": "0", "clean": "0"}, {"raw": "00", "clean": "00"}, {"raw": "0", "clean": "0"}, {"raw": "S", "clean": "S"}, {"raw": "1", "clean": "1"}, {"raw": "imm9", "clean": "imm9"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rt", "clean": "Rt"}], "bit_positions": "31:30 | 29:27 | 26 | 25:24 | 23 | 22 | 21 | 20:12 | 11 | 10 | 9:5 | 4:0"}, "operands": [{"name": "Xt", "desc": "Transfer 64-bit integer register (load/store)"}, {"name": "Xn", "desc": "First source / base 64-bit integer register"}, {"name": "simm", "desc": "Signed immediate offset"}], "extension": "PAC (Security)", "description": "Loads a 64-bit value from memory using an address authenticated with Pointer Authentication Code (PAC) using Key A. The address is computed from a base register and a signed 9-bit immediate offset. This AArch64-only instruction requires PAC support and will generate an Authentication Failure exception if authentication fails; no condition flags are affected.", "example": "LDRAA x3, [x1, #-8]", "pseudocode": "address ← Xn|SP + (simm9 << 3)\nauthenticated_address ← AuthenticateAddressA(address)\nXt ← [authenticated_address]"} {"mnemonic": "ldrab", "architecture": "ARMv8-A", "full_name": "Load Register Authenticate (Key B)", "summary": "Loads a value, authenticating the address with Key B.", "syntax": "LDRAB , [, #]", "encoding": {"format": "Load/Store", "binary_pattern": "11 | 111 | 0 | 00 | 1 | S | 1 | imm9 | 0 | 1 | Rn | Rt", "hex_opcode": "0xF8A00400", "visual_parts": [{"raw": "11", "clean": "11"}, {"raw": "111", "clean": "111"}, {"raw": "0", "clean": "0"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "S", "clean": "S"}, {"raw": "1", "clean": "1"}, {"raw": "imm9", "clean": "imm9"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rt", "clean": "Rt"}], "bit_positions": "31:30 | 29:27 | 26 | 25:24 | 23 | 22 | 21 | 20:12 | 11 | 10 | 9:5 | 4:0"}, "operands": [{"name": "Xt", "desc": "Transfer 64-bit integer register (load/store)"}, {"name": "Xn", "desc": "First source / base 64-bit integer register"}, {"name": "simm", "desc": "Signed immediate offset"}], "extension": "PAC (Security)", "description": "Loads a 64-bit value from memory using an address authenticated with Pointer Authentication Code (PAC) using Key B. The address is computed from a base register and a signed 9-bit immediate offset. This AArch64-only instruction requires PAC support and will generate an Authentication Failure exception if authentication fails; no condition flags are affected.", "example": "LDRAB x3, [x1, #-8]", "pseudocode": "address ← Xn|SP + (simm9 << 3)\nauthenticated_address ← AuthenticateAddressB(address)\nXt ← [authenticated_address]"} {"mnemonic": "bti", "architecture": "ARMv8-A", "full_name": "Branch Target Identification", "summary": "Marks a valid target for indirect branches (Guard against JOP/ROP).", "syntax": "BTI ", "encoding": {"format": "System Hint", "binary_pattern": "11010101000000110010 | 0100 | op2 | 11111", "hex_opcode": "0xD503241F", "visual_parts": [{"raw": "11010101000000110010", "clean": "11010101000000110010"}, {"raw": "0100", "clean": "0100"}, {"raw": "op2", "clean": "op2"}, {"raw": "11111", "clean": "11111"}], "bit_positions": "31:12 | 11:8 | 7:5 | 4:0"}, "operands": [{"name": "target", "desc": "J/C/JC"}], "extension": "BTI (Security)", "description": "Marks a valid branch target for indirect branch instructions, providing defense against Jump-Oriented Programming (JOP) and Return-Oriented Programming (ROP) attacks. This instruction is AArch64-only and requires the BTI (Branch Target Identification) extension. It does not affect condition flags and acts as a hint; execution continues to the next instruction.", "example": "BTI target", "pseudocode": "if not_valid_branch_target and branch_target_enforcement_enabled then\n GenerateException(BTYPE_mismatch)\nelse\n NOP\nend if"} {"mnemonic": "rndr", "architecture": "ARMv8-A", "full_name": "Random Number", "summary": "Reads a random number from hardware entropy source.", "syntax": "RNDR ", "encoding": {"format": "System", "binary_pattern": "11010101001 | 00011 | 0011 | 0010 | 010 | Rt", "hex_opcode": "0xD53B2400", "visual_parts": [{"raw": "11010101001", "clean": "11010101001"}, {"raw": "00011", "clean": "00011"}, {"raw": "0011", "clean": "0011"}, {"raw": "0010", "clean": "0010"}, {"raw": "010", "clean": "010"}, {"raw": "Rt", "clean": "Rt"}]}, "operands": [{"name": "Xt", "desc": "Transfer 64-bit integer register (load/store)"}], "extension": "FEAT_RNG", "description": "Reads a 64-bit random number from the system's hardware entropy source and writes it to Xt. This instruction is AArch64-only and requires the FEAT_RNG extension. It does not modify condition flags and may set the C flag to indicate failure (entropy unavailable), depending on implementation.", "example": "RNDR x3", "pseudocode": "Xt ← HardwareRandomNumber()\nif entropy_available then\n C ← 0\nelse\n C ← 1\nend if"} {"mnemonic": "rndrrs", "architecture": "ARMv8-A", "full_name": "Random Number Reseed", "summary": "Reads a random number and requests reseed.", "syntax": "RNDRRS ", "encoding": {"format": "System", "binary_pattern": "11010101001 | 00011 | 0011 | 0010 | 011 | Rt", "hex_opcode": "0xD53B2600", "visual_parts": [{"raw": "11010101001", "clean": "11010101001"}, {"raw": "00011", "clean": "00011"}, {"raw": "0011", "clean": "0011"}, {"raw": "0010", "clean": "0010"}, {"raw": "011", "clean": "011"}, {"raw": "Rt", "clean": "Rt"}]}, "operands": [{"name": "Xt", "desc": "Transfer 64-bit integer register (load/store)"}], "extension": "FEAT_RNG", "description": "Reads a 64-bit random number from the hardware entropy source, writes it to Xt, and requests a reseed of the entropy generator. This instruction is AArch64-only and requires the FEAT_RNG extension. It may set the C flag to indicate entropy availability, similar to RNDR.", "example": "RNDRRS x3", "pseudocode": "Xt ← HardwareRandomNumber()\nRequestReseed(entropy_generator)\nif entropy_available then\n C ← 0\nelse\n C ← 1\nend if"} {"mnemonic": "cfinv", "architecture": "ARMv8-A", "full_name": "Condition Flag Invert", "summary": "Inverts the C (Carry) flag.", "syntax": "CFINV", "encoding": {"format": "System", "binary_pattern": "1101010100000 | 000 | 0100 | 0000 | 000 | 11111", "hex_opcode": "0xD500401F", "visual_parts": [{"raw": "1101010100000", "clean": "1101010100000"}, {"raw": "000", "clean": "000"}, {"raw": "0100", "clean": "0100"}, {"raw": "0000", "clean": "0000"}, {"raw": "000", "clean": "000"}, {"raw": "11111", "clean": "11111"}], "bit_positions": "31:19 | 18:16 | 15:12 | 11:8 | 7:5 | 4:0"}, "operands": [], "extension": "FEAT_FlagM", "description": "Inverts the Carry flag (C) in the condition flags register. This instruction is AArch64-only and requires the FEAT_FlagM extension. All other condition flags (N, Z, V) remain unchanged. The operation is not privileged.", "example": "CFINV", "pseudocode": "C ← NOT C"} {"mnemonic": "rmif", "architecture": "ARMv8-A", "full_name": "Rotate Mask Insert Flags", "summary": "Rotates a register and inserts bits into the Process State flags.", "syntax": "RMIF , #, #", "encoding": {"format": "Data Processing", "binary_pattern": "1 | 0 | 1 | 11010000 | imm6 | 00001 | Rn | 0 | mask", "hex_opcode": "0xBA000400", "visual_parts": [{"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "11010000", "clean": "11010000"}, {"raw": "imm6", "clean": "imm6"}, {"raw": "00001", "clean": "00001"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "0", "clean": "0"}, {"raw": "mask", "clean": "mask"}], "bit_positions": "31 | 30 | 29 | 28:21 | 20:15 | 14:10 | 9:5 | 4 | 3:0"}, "operands": [{"name": "Xn", "desc": "First source / base 64-bit integer register"}, {"name": "shift", "desc": "Rot"}, {"name": "mask", "desc": "Flags"}], "extension": "FEAT_FlagM", "description": "Rotates the 64-bit value in Xn right by shift bits, then uses the mask to selectively update PSTATE condition flags (N, Z, C, V). Each bit set in mask causes the corresponding rotated bit to update the corresponding flag. AArch64-only; requires FEAT_FlagM. Does not update any other registers.", "example": "RMIF x1, #LSL, #mask", "pseudocode": "rotated ← ROR(Xn, shift); if mask<3> then N ← rotated<63>; if mask<2> then Z ← (rotated == 0); if mask<1> then C ← rotated<0>; if mask<0> then V ← rotated<1>;"} {"mnemonic": "setf8", "architecture": "ARMv8-A", "full_name": "Set Flags 8-bit", "summary": "Sets PSTATE flags based on 8-bit operand.", "syntax": "SETF8 ", "encoding": {"format": "System", "binary_pattern": "0 | 0 | 1 | 11010000 | 000000 | 0 | 0010 | Rn | 0 | 1101", "hex_opcode": "0x3A00080D", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "11010000", "clean": "11010000"}, {"raw": "000000", "clean": "000000"}, {"raw": "0", "clean": "0"}, {"raw": "0010", "clean": "0010"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "0", "clean": "0"}, {"raw": "1101", "clean": "1101"}], "bit_positions": "31 | 30 | 29 | 28:21 | 20:15 | 14 | 13:10 | 9:5 | 4 | 3:0"}, "operands": [{"name": "Wn", "desc": "First source / base 32-bit integer register"}], "extension": "FEAT_FlagM", "description": "Sets PSTATE condition flags (N, Z, C, V) based on the lower 8 bits of the 32-bit source register Wn, interpreting them as a signed 8-bit value. AArch64-only; requires FEAT_FlagM. N is set if bit 7 of Wn is set; Z is set if the lower 8 bits are zero; C and V are cleared.", "example": "SETF8 w1", "pseudocode": "val8 ← Wn<7:0>; N ← val8<7>; Z ← (val8 == 0); C ← 0; V ← 0;"} {"mnemonic": "setf16", "architecture": "ARMv8-A", "full_name": "Set Flags 16-bit", "summary": "Sets PSTATE flags based on 16-bit operand.", "syntax": "SETF16 ", "encoding": {"format": "System", "binary_pattern": "0 | 0 | 1 | 11010000 | 000000 | 1 | 0010 | Rn | 0 | 1101", "hex_opcode": "0x3A00480D", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "11010000", "clean": "11010000"}, {"raw": "000000", "clean": "000000"}, {"raw": "1", "clean": "1"}, {"raw": "0010", "clean": "0010"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "0", "clean": "0"}, {"raw": "1101", "clean": "1101"}], "bit_positions": "31 | 30 | 29 | 28:21 | 20:15 | 14 | 13:10 | 9:5 | 4 | 3:0"}, "operands": [{"name": "Wn", "desc": "First source / base 32-bit integer register"}], "extension": "FEAT_FlagM", "description": "Sets PSTATE condition flags (N, Z, C, V) based on the lower 16 bits of the 32-bit source register Wn, interpreting them as a signed 16-bit value. AArch64-only; requires FEAT_FlagM. N is set if bit 15 of Wn is set; Z is set if the lower 16 bits are zero; C and V are cleared.", "example": "SETF16 w1", "pseudocode": "val16 ← Wn<15:0>; N ← val16<15>; Z ← (val16 == 0); C ← 0; V ← 0;"} {"mnemonic": "fjcvtzs", "architecture": "ARMv8-A", "full_name": "Floating-Point Javascript Convert", "summary": "Converts double to signed 32-bit integer with JS rounding semantics.", "syntax": "FJCVTZS , ", "encoding": {"format": "Float Convert", "binary_pattern": "0 | 0 | 0 | 11110 | 01 | 1 | 11 | 110 | 000000 | Rn | Rd", "hex_opcode": "0x1E7E0000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "01", "clean": "01"}, {"raw": "1", "clean": "1"}, {"raw": "11", "clean": "11"}, {"raw": "110", "clean": "110"}, {"raw": "000000", "clean": "000000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Wd", "desc": "Destination 32-bit integer register"}, {"name": "Dn", "desc": "First source 64-bit SIMD/FP register"}], "extension": "FEAT_JSCVT", "description": "Converts the 64-bit floating-point value in Dn to a signed 32-bit integer in Wd using JavaScript rounding semantics (round toward zero, with special handling for NaN and out-of-range values). AArch64-only; requires FEAT_JSCVT. Sets the C flag to 1 if the input is out of range or NaN, otherwise clears it. Other flags are not affected.", "example": "FJCVTZS w0, d1", "pseudocode": "if IsNaN(Dn) or (Dn > 2^31 - 1) or (Dn < -2^31) then Wd ← 0; C ← 1; else Wd ← SignedSaturate(RoundTowardZero(Dn), 32); C ← 0;"} {"mnemonic": "sbfx", "architecture": "ARMv8-A", "full_name": "Signed Bit Field Extract (A32)", "summary": "Extracts bits from a register and sign-extends them.", "syntax": "SBFX , , #, #", "encoding": {"format": "Data Proc", "binary_pattern": "cond | 01111 | 0 | 1 | widthm1 | Rd | lsb | 101 | Rn", "hex_opcode": "0x07A00050", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01111", "clean": "01111"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "widthm1", "clean": "widthm1"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "lsb", "clean": "lsb"}, {"raw": "101", "clean": "101"}, {"raw": "Rn", "clean": "Rn"}], "bit_positions": "31:28 | 27:23 | 22 | 21 | 20:16 | 15:12 | 11:7 | 6:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "lsb", "desc": "Start Bit"}, {"name": "width", "desc": "Width"}], "extension": "A32 (Base)", "description": "Extracts a bitfield of width bits starting at position lsb from Rn, sign-extends the extracted value, and writes it to Rd. A32 instruction; available in all A32 processor modes. Does not affect PSTATE flags. The condition code suffix controls execution.", "example": "SBFX r0, r1, #0, #width", "pseudocode": "extracted ← Rn<(lsb + width - 1):lsb>; if extracted<(width - 1)> == 1 then Rd ← SignExtend(extracted, width) else Rd ← ZeroExtend(extracted, width);"} {"mnemonic": "ubfx", "architecture": "ARMv8-A", "full_name": "Unsigned Bit Field Extract (A32)", "summary": "Extracts bits from a register and zero-extends them.", "syntax": "UBFX , , #, #", "encoding": {"format": "Data Proc", "binary_pattern": "cond | 01111 | 1 | 1 | widthm1 | Rd | lsb | 101 | Rn", "hex_opcode": "0x07E00050", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01111", "clean": "01111"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "widthm1", "clean": "widthm1"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "lsb", "clean": "lsb"}, {"raw": "101", "clean": "101"}, {"raw": "Rn", "clean": "Rn"}], "bit_positions": "31:28 | 27:23 | 22 | 21 | 20:16 | 15:12 | 11:7 | 6:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "lsb", "desc": "Start Bit"}, {"name": "width", "desc": "Width"}], "extension": "A32 (Base)", "description": "Extracts a bitfield of width bits starting at position lsb from Rn, zero-extends the extracted value, and writes it to Rd. A32 instruction; available in all A32 processor modes. Does not affect PSTATE flags. The condition code suffix controls execution.", "example": "UBFX r0, r1, #0, #width", "pseudocode": "extracted ← Rn<(lsb + width - 1):lsb>; Rd ← ZeroExtend(extracted, width);"} {"mnemonic": "sxtb", "architecture": "ARMv8-A", "full_name": "Signed Extend Byte (A32)", "summary": "Sign-extends the low byte (8-bits) to 32-bits.", "syntax": "SXTB , {, }", "encoding": {"format": "Data Proc", "binary_pattern": "cond | 01101 | 0 | 10 | 1111 | Rd | rotate | 0 | 0 | 0111 | Rm", "hex_opcode": "0x06AF0070", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01101", "clean": "01101"}, {"raw": "0", "clean": "0"}, {"raw": "10", "clean": "10"}, {"raw": "1111", "clean": "1111"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "rotate", "clean": "rotate"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0111", "clean": "0111"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (Base)", "description": "Sign-extends the low byte of Rm into the full 32-bit word in Rd, with optional pre-rotation of Rm by 0, 8, 16, or 24 bits. This is an A32 instruction that does not affect any condition flags. The rotation is applied before the sign extension.", "example": "SXTB r0, r2", "pseudocode": "rotated ← ROR(Rm, rotation)\nRd ← SignExtend(rotated[7:0], 32)"} {"mnemonic": "sxth", "architecture": "ARMv8-A", "full_name": "Signed Extend Halfword (A32)", "summary": "Sign-extends the low halfword (16-bits) to 32-bits.", "syntax": "SXTH , {, }", "encoding": {"format": "Data Proc", "binary_pattern": "cond | 01101 | 0 | 11 | 1111 | Rd | rotate | 0 | 0 | 0111 | Rm", "hex_opcode": "0x06BF0070", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01101", "clean": "01101"}, {"raw": "0", "clean": "0"}, {"raw": "11", "clean": "11"}, {"raw": "1111", "clean": "1111"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "rotate", "clean": "rotate"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0111", "clean": "0111"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (Base)", "description": "Sign-extends the low halfword of Rm into the full 32-bit word in Rd, with optional pre-rotation of Rm by 0, 8, 16, or 24 bits. This is an A32 instruction that does not affect any condition flags. The rotation is applied before the sign extension.", "example": "SXTH r0, r2", "pseudocode": "rotated ← ROR(Rm, rotation)\nRd ← SignExtend(rotated[15:0], 32)"} {"mnemonic": "sxtb16", "architecture": "ARMv8-A", "full_name": "Signed Extend Byte 16 (A32)", "summary": "Sign-extends two bytes to two halfwords.", "syntax": "SXTB16 , {, }", "encoding": {"format": "Data Proc", "binary_pattern": "cond | 01101 | 0 | 00 | 1111 | Rd | rotate | 0 | 0 | 0111 | Rm", "hex_opcode": "0x068F0070", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01101", "clean": "01101"}, {"raw": "0", "clean": "0"}, {"raw": "00", "clean": "00"}, {"raw": "1111", "clean": "1111"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "rotate", "clean": "rotate"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0111", "clean": "0111"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Sign-extends the two low bytes (bits 7:0 and 15:8) of Rm to two 16-bit halfwords in Rd, with an optional rotation applied to Rm before extraction. A32 instruction; requires DSP extension. Does not affect PSTATE flags. The condition code suffix controls execution.", "example": "SXTB16 r0, r2", "pseudocode": "rotated ← ROR(Rm, rotation); Rd<15:0> ← SignExtend(rotated<7:0>, 16); Rd<31:16> ← SignExtend(rotated<15:8>, 16);"} {"mnemonic": "uxtb", "architecture": "ARMv8-A", "full_name": "Unsigned Extend Byte (A32)", "summary": "Zero-extends the low byte to 32-bits.", "syntax": "UXTB , {, }", "encoding": {"format": "Data Proc", "binary_pattern": "cond | 01101 | 1 | 10 | 1111 | Rd | rotate | 0 | 0 | 0111 | Rm", "hex_opcode": "0x06EF0070", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01101", "clean": "01101"}, {"raw": "1", "clean": "1"}, {"raw": "10", "clean": "10"}, {"raw": "1111", "clean": "1111"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "rotate", "clean": "rotate"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0111", "clean": "0111"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (Base)", "description": "Zero-extends the low byte (bits [7:0]) of Rm to the full 32-bit width and stores the result in Rd. An optional rotation (0°, 90°, 180°, or 270°) can be applied to Rm before the extension. No condition flags are affected by this instruction. A32 only; executes in User and Privileged modes.", "example": "UXTB r0, r2", "pseudocode": "rotated ← ROR(Rm, rotation * 8)\nRd ← ZeroExtend(rotated[7:0], 32)"} {"mnemonic": "uxth", "architecture": "ARMv8-A", "full_name": "Unsigned Extend Halfword (A32)", "summary": "Zero-extends the low halfword to 32-bits.", "syntax": "UXTH , {, }", "encoding": {"format": "Data Proc", "binary_pattern": "cond | 01101 | 1 | 11 | 1111 | Rd | rotate | 0 | 0 | 0111 | Rm", "hex_opcode": "0x06FF0070", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01101", "clean": "01101"}, {"raw": "1", "clean": "1"}, {"raw": "11", "clean": "11"}, {"raw": "1111", "clean": "1111"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "rotate", "clean": "rotate"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0111", "clean": "0111"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (Base)", "description": "Zero-extends the low halfword (bits [15:0]) of Rm to the full 32-bit width and stores the result in Rd. An optional rotation (0°, 90°, 180°, or 270°) can be applied to Rm before the extension. No condition flags are affected by this instruction. A32 only; executes in User and Privileged modes.", "example": "UXTH r0, r2", "pseudocode": "rotated ← ROR(Rm, rotation * 8)\nRd ← ZeroExtend(rotated[15:0], 32)"} {"mnemonic": "uxtb16", "architecture": "ARMv8-A", "full_name": "Unsigned Extend Byte 16 (A32)", "summary": "Zero-extends two bytes to two halfwords.", "syntax": "UXTB16 , {, }", "encoding": {"format": "Data Proc", "binary_pattern": "cond | 01101 | 1 | 00 | 1111 | Rd | rotate | 0 | 0 | 0111 | Rm", "hex_opcode": "0x06CF0070", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01101", "clean": "01101"}, {"raw": "1", "clean": "1"}, {"raw": "00", "clean": "00"}, {"raw": "1111", "clean": "1111"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "rotate", "clean": "rotate"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0111", "clean": "0111"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Zero-extends the two low bytes (bits 7:0 and 15:8) of Rm to two 16-bit halfwords in Rd, with an optional rotation applied to Rm before extraction. A32 instruction; requires DSP extension. Does not affect PSTATE flags. The condition code suffix controls execution.", "example": "UXTB16 r0, r2", "pseudocode": "rotated ← ROR(Rm, rotation); Rd<15:0> ← ZeroExtend(rotated<7:0>, 16); Rd<31:16> ← ZeroExtend(rotated<15:8>, 16);"} {"mnemonic": "ssat", "architecture": "ARMv8-A", "full_name": "Signed Saturate (A32)", "summary": "Saturates a signed value to a specified bit width.", "syntax": "SSAT , #, {, }", "encoding": {"format": "Data Proc", "binary_pattern": "cond | 01101 | 0 | 1 | sat_imm | Rd | imm5 | 0 | 01 | Rn", "hex_opcode": "0x06A00010", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01101", "clean": "01101"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "sat_imm", "clean": "sat_imm"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "imm5", "clean": "imm5"}, {"raw": "0", "clean": "0"}, {"raw": "01", "clean": "01"}, {"raw": "Rn", "clean": "Rn"}], "bit_positions": "31:28 | 27:23 | 22 | 21 | 20:16 | 15:12 | 11:7 | 6 | 5:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "imm", "desc": "Bit Position"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Saturates a signed integer to a specified bit width. The instruction shifts the source value by an optional amount, then saturates the result to a signed range defined by the saturation position. Sets the Q flag if saturation occurs; N, Z, C, V flags are unaffected. A32-only instruction requiring DSP extension.", "example": "SSAT r0, #16, r2", "pseudocode": "shifted ← Rm << shift_amount\nsat_range ← 2^(imm-1) - 1\nif shifted > sat_range then\n Rd ← sat_range\n Q ← 1\nelse if shifted < -(2^(imm-1)) then\n Rd ← -(2^(imm-1))\n Q ← 1\nelse\n Rd ← shifted"} {"mnemonic": "usat", "architecture": "ARMv8-A", "full_name": "Unsigned Saturate (A32)", "summary": "Saturates an unsigned value to a specified bit width.", "syntax": "USAT , #, {, }", "encoding": {"format": "Data Proc", "binary_pattern": "cond | 01101 | 1 | 1 | sat_imm | Rd | imm5 | 0 | 01 | Rn", "hex_opcode": "0x06E00010", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01101", "clean": "01101"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "sat_imm", "clean": "sat_imm"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "imm5", "clean": "imm5"}, {"raw": "0", "clean": "0"}, {"raw": "01", "clean": "01"}, {"raw": "Rn", "clean": "Rn"}], "bit_positions": "31:28 | 27:23 | 22 | 21 | 20:16 | 15:12 | 11:7 | 6 | 5:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "imm", "desc": "Bit Position"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Saturates an unsigned integer to a specified bit width. The instruction shifts the source value by an optional amount, then saturates the result to an unsigned range [0, 2^imm-1]. Sets the Q flag if saturation occurs; N, Z, C, V flags are unaffected. A32-only instruction requiring DSP extension.", "example": "USAT r0, #16, r2", "pseudocode": "shifted ← Rm << shift_amount\nsat_max ← 2^imm - 1\nif shifted > sat_max then\n Rd ← sat_max\n Q ← 1\nelse if shifted < 0 then\n Rd ← 0\n Q ← 1\nelse\n Rd ← shifted"} {"mnemonic": "ssat16", "architecture": "ARMv8-A", "full_name": "Signed Saturate 16 (A32)", "summary": "Saturates two signed 16-bit values.", "syntax": "SSAT16 , #, ", "encoding": {"format": "Data Proc", "binary_pattern": "cond | 01101 | 0 | 10 | sat_imm | Rd | 1 | 1 | 1 | 1 | 0011 | Rn", "hex_opcode": "0x06A00F30", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01101", "clean": "01101"}, {"raw": "0", "clean": "0"}, {"raw": "10", "clean": "10"}, {"raw": "sat_imm", "clean": "sat_imm"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0011", "clean": "0011"}, {"raw": "Rn", "clean": "Rn"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "imm", "desc": "Bit Position"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Saturates two signed 16-bit halfword values packed in a register to a specified bit width. The upper and lower 16-bit values are independently saturated to the range [-(2^(imm-1)), 2^(imm-1)-1]. Sets the Q flag if either halfword saturates; N, Z, C, V flags are unaffected. A32-only instruction requiring DSP extension.", "example": "SSAT16 r0, #16, r2", "pseudocode": "lower_hw ← Rm[15:0] (signed)\nupper_hw ← Rm[31:16] (signed)\nsat_range ← 2^(imm-1) - 1\nsat_min ← -(2^(imm-1))\nif lower_hw > sat_range or lower_hw < sat_min then\n Rd[15:0] ← Clamp(lower_hw, sat_min, sat_range)\n Q ← 1\nelse\n Rd[15:0] ← lower_hw\nif upper_hw > sat_range or upper_hw < sat_min then\n Rd[31:16] ← Clamp(upper_hw, sat_min, sat_range)\n Q ← 1\nelse\n Rd[31:16] ← upper_hw"} {"mnemonic": "usat16", "architecture": "ARMv8-A", "full_name": "Unsigned Saturate 16 (A32)", "summary": "Saturates two unsigned 16-bit values.", "syntax": "USAT16 , #, ", "encoding": {"format": "Data Proc", "binary_pattern": "cond | 01101 | 1 | 10 | sat_imm | Rd | 1 | 1 | 1 | 1 | 0011 | Rn", "hex_opcode": "0x06E00F30", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01101", "clean": "01101"}, {"raw": "1", "clean": "1"}, {"raw": "10", "clean": "10"}, {"raw": "sat_imm", "clean": "sat_imm"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0011", "clean": "0011"}, {"raw": "Rn", "clean": "Rn"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "imm", "desc": "Bit Position"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Saturates two unsigned 16-bit halfword values packed in a register to a specified bit width. The upper and lower 16-bit values are independently saturated to the range [0, 2^imm-1]. Sets the Q flag if either halfword saturates; N, Z, C, V flags are unaffected. A32-only instruction requiring DSP extension.", "example": "USAT16 r0, #16, r2", "pseudocode": "lower_hw ← Rm[15:0] (unsigned)\nupper_hw ← Rm[31:16] (unsigned)\nsat_max ← 2^imm - 1\nif lower_hw > sat_max then\n Rd[15:0] ← sat_max\n Q ← 1\nelse\n Rd[15:0] ← lower_hw\nif upper_hw > sat_max then\n Rd[31:16] ← sat_max\n Q ← 1\nelse\n Rd[31:16] ← upper_hw"} {"mnemonic": "pkhbt", "architecture": "ARMv8-A", "full_name": "Pack Halfword Bottom Top", "summary": "Combines bottom half of Rn with top half of shifted Rm.", "syntax": "PKHBT , , {, LSL #}", "encoding": {"format": "Data Proc", "binary_pattern": "cond | 01101000 | Rn | Rd | imm5 | 0 | 01 | Rm", "hex_opcode": "0x06800010", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01101000", "clean": "01101000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "imm5", "clean": "imm5"}, {"raw": "0", "clean": "0"}, {"raw": "01", "clean": "01"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:20 | 19:16 | 15:12 | 11:7 | 6 | 5:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "Bottom Src"}, {"name": "Rm", "desc": "Top Src"}], "extension": "A32 (DSP)", "description": "Packs the bottom halfword of Rn with the top halfword of (Rm shifted left). Assembles a 32-bit result by taking bits [15:0] from Rn and bits [31:16] from the shifted Rm. Condition flags N, Z, C, V are unaffected. A32-only instruction requiring DSP extension.", "example": "PKHBT r0, r1, r2", "pseudocode": "Rd[15:0] ← Rn[15:0]\nshifted_rm ← Rm << shift_imm\nRd[31:16] ← shifted_rm[31:16]"} {"mnemonic": "pkhtb", "architecture": "ARMv8-A", "full_name": "Pack Halfword Top Bottom", "summary": "Combines top half of Rn with bottom half of shifted Rm.", "syntax": "PKHTB , , {, ASR #}", "encoding": {"format": "Data Proc", "binary_pattern": "cond | 01101000 | Rn | Rd | imm5 | 1 | 01 | Rm", "hex_opcode": "0x06800050", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01101000", "clean": "01101000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "imm5", "clean": "imm5"}, {"raw": "1", "clean": "1"}, {"raw": "01", "clean": "01"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:20 | 19:16 | 15:12 | 11:7 | 6 | 5:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "Top Src"}, {"name": "Rm", "desc": "Bottom Src"}], "extension": "A32 (DSP)", "description": "Packs the top halfword of Rn with the bottom halfword of (Rm shifted right). Assembles a 32-bit result by taking bits [31:16] from Rn and bits [15:0] from the shifted Rm. Condition flags N, Z, C, V are unaffected. A32-only instruction requiring DSP extension.", "example": "PKHTB r0, r1, r2", "pseudocode": "shifted_rm ← Rm >> shift_imm\nRd[15:0] ← shifted_rm[15:0]\nRd[31:16] ← Rn[31:16]"} {"mnemonic": "sadd16", "architecture": "ARMv8-A", "full_name": "Signed Add 16 (A32)", "summary": "Parallel add of two signed 16-bit halfwords.", "syntax": "SADD16 , , ", "encoding": {"format": "SIMD Integer", "binary_pattern": "cond | 01100 | 001 | Rn | Rd | 1 | 1 | 1 | 1 | 0 | 00 | 1 | Rm", "hex_opcode": "0x06100F10", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01100", "clean": "01100"}, {"raw": "001", "clean": "001"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Performs two independent parallel signed 16-bit additions: the high halfword of Rn is added to the high halfword of Rm, and the low halfword of Rn is added to the low halfword of Rm; results are stored in the corresponding halfwords of Rd. The CPSR GE[3:0] flags are updated to reflect signed overflow in each halfword; N, Z, C, V are unaffected. A32 only; requires DSP extension; executes in User and Privileged modes.", "example": "SADD16 r0, r1, r2", "pseudocode": "Rd[31:16] ← Rn[31:16] + Rm[31:16]\nRd[15:0] ← Rn[15:0] + Rm[15:0]\nGE[3] ← (Rd[31:16] >= 0) ? 1 : 0\nGE[2] ← (Rd[31:16] < 0) ? 0 : 1\nGE[1] ← (Rd[15:0] >= 0) ? 1 : 0\nGE[0] ← (Rd[15:0] < 0) ? 0 : 1"} {"mnemonic": "uadd16", "architecture": "ARMv8-A", "full_name": "Unsigned Add 16 (A32)", "summary": "Parallel add of two unsigned 16-bit halfwords.", "syntax": "UADD16 , , ", "encoding": {"format": "SIMD Integer", "binary_pattern": "cond | 01100 | 101 | Rn | Rd | 1 | 1 | 1 | 1 | 0 | 00 | 1 | Rm", "hex_opcode": "0x06500F10", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01100", "clean": "01100"}, {"raw": "101", "clean": "101"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Performs two independent parallel unsigned 16-bit additions: the high halfword of Rn is added to the high halfword of Rm, and the low halfword of Rn is added to the low halfword of Rm; results are stored in the corresponding halfwords of Rd. The CPSR GE[3:0] flags are updated to reflect unsigned overflow (carry-out) in each halfword; N, Z, C, V are unaffected. A32 only; requires DSP extension; executes in User and Privileged modes.", "example": "UADD16 r0, r1, r2", "pseudocode": "Rd[31:16] ← Rn[31:16] + Rm[31:16]\nRd[15:0] ← Rn[15:0] + Rm[15:0]\nGE[3] ← (Rn[31:16] + Rm[31:16] < 2^16) ? 0 : 1\nGE[2] ← (Rn[31:16] + Rm[31:16] < 2^16) ? 1 : 0\nGE[1] ← (Rn[15:0] + Rm[15:0] < 2^16) ? 0 : 1\nGE[0] ← (Rn[15:0] + Rm[15:0] < 2^16) ? 1 : 0"} {"mnemonic": "sadd8", "architecture": "ARMv8-A", "full_name": "Signed Add 8 (A32)", "summary": "Parallel add of four signed 8-bit bytes.", "syntax": "SADD8 , , ", "encoding": {"format": "SIMD Integer", "binary_pattern": "cond | 01100 | 001 | Rn | Rd | 1 | 1 | 1 | 1 | 1 | 00 | 1 | Rm", "hex_opcode": "0x06100F90", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01100", "clean": "01100"}, {"raw": "001", "clean": "001"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Performs four independent parallel signed 8-bit additions, one for each byte of Rn and Rm; results are stored in the corresponding bytes of Rd. The CPSR GE[3:0] flags are updated to reflect signed overflow in each byte; N, Z, C, V are unaffected. A32 only; requires DSP extension; executes in User and Privileged modes.", "example": "SADD8 r0, r1, r2", "pseudocode": "Rd[31:24] ← Rn[31:24] + Rm[31:24]\nRd[23:16] ← Rn[23:16] + Rm[23:16]\nRd[15:8] ← Rn[15:8] + Rm[15:8]\nRd[7:0] ← Rn[7:0] + Rm[7:0]\nfor i = 0 to 3:\n GE[i] ← (Rd[i*8+7:i*8] >= 0) ? 1 : 0"} {"mnemonic": "uadd8", "architecture": "ARMv8-A", "full_name": "Unsigned Add 8 (A32)", "summary": "Parallel add of four unsigned 8-bit bytes.", "syntax": "UADD8 , , ", "encoding": {"format": "SIMD Integer", "binary_pattern": "cond | 01100 | 101 | Rn | Rd | 1 | 1 | 1 | 1 | 1 | 00 | 1 | Rm", "hex_opcode": "0x06500F90", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01100", "clean": "01100"}, {"raw": "101", "clean": "101"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Performs four independent parallel unsigned 8-bit additions, one for each byte of Rn and Rm; results are stored in the corresponding bytes of Rd. The CPSR GE[3:0] flags are updated to reflect unsigned overflow (carry-out) in each byte; N, Z, C, V are unaffected. A32 only; requires DSP extension; executes in User and Privileged modes.", "example": "UADD8 r0, r1, r2", "pseudocode": "Rd[31:24] ← Rn[31:24] + Rm[31:24]\nRd[23:16] ← Rn[23:16] + Rm[23:16]\nRd[15:8] ← Rn[15:8] + Rm[15:8]\nRd[7:0] ← Rn[7:0] + Rm[7:0]\nfor i = 0 to 3:\n GE[i] ← (Rn[i*8+7:i*8] + Rm[i*8+7:i*8] < 2^8) ? 0 : 1"} {"mnemonic": "ssub16", "architecture": "ARMv8-A", "full_name": "Signed Subtract 16 (A32)", "summary": "Parallel sub of two signed 16-bit halfwords.", "syntax": "SSUB16 , , ", "encoding": {"format": "SIMD Integer", "binary_pattern": "cond | 01100 | 001 | Rn | Rd | 1 | 1 | 1 | 1 | 0 | 11 | 1 | Rm", "hex_opcode": "0x06100F70", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01100", "clean": "01100"}, {"raw": "001", "clean": "001"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "11", "clean": "11"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Performs two independent parallel signed 16-bit subtractions: the high halfword of Rm is subtracted from the high halfword of Rn, and the low halfword of Rm is subtracted from the low halfword of Rn; results are stored in the corresponding halfwords of Rd. The CPSR GE[3:0] flags are updated to reflect signed borrow in each halfword; N, Z, C, V are unaffected. A32 only; requires DSP extension; executes in User and Privileged modes.", "example": "SSUB16 r0, r1, r2", "pseudocode": "Rd[31:16] ← Rn[31:16] - Rm[31:16]\nRd[15:0] ← Rn[15:0] - Rm[15:0]\nGE[3] ← (Rd[31:16] >= 0) ? 1 : 0\nGE[2] ← (Rd[31:16] < 0) ? 0 : 1\nGE[1] ← (Rd[15:0] >= 0) ? 1 : 0\nGE[0] ← (Rd[15:0] < 0) ? 0 : 1"} {"mnemonic": "usub16", "architecture": "ARMv8-A", "full_name": "Unsigned Subtract 16 (A32)", "summary": "Parallel sub of two unsigned 16-bit halfwords.", "syntax": "USUB16 , , ", "encoding": {"format": "SIMD Integer", "binary_pattern": "cond | 01100 | 101 | Rn | Rd | 1 | 1 | 1 | 1 | 0 | 11 | 1 | Rm", "hex_opcode": "0x06500F70", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01100", "clean": "01100"}, {"raw": "101", "clean": "101"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "11", "clean": "11"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Performs two independent parallel unsigned 16-bit subtractions: the high halfword of Rm is subtracted from the high halfword of Rn, and the low halfword of Rm is subtracted from the low halfword of Rn; results are stored in the corresponding halfwords of Rd. The CPSR GE[3:0] flags are updated to reflect unsigned borrow (no carry-out) in each halfword; N, Z, C, V are unaffected. A32 only; requires DSP extension; executes in User and Privileged modes.", "example": "USUB16 r0, r1, r2", "pseudocode": "Rd[31:16] ← Rn[31:16] - Rm[31:16]\nRd[15:0] ← Rn[15:0] - Rm[15:0]\nGE[3] ← (Rn[31:16] >= Rm[31:16]) ? 1 : 0\nGE[2] ← (Rn[31:16] >= Rm[31:16]) ? 0 : 1\nGE[1] ← (Rn[15:0] >= Rm[15:0]) ? 1 : 0\nGE[0] ← (Rn[15:0] >= Rm[15:0]) ? 0 : 1"} {"mnemonic": "usad8", "architecture": "ARMv8-A", "full_name": "Unsigned Sum of Absolute Differences", "summary": "Computes sum of absolute differences of bytes (Video Codec).", "syntax": "USAD8 , , ", "encoding": {"format": "SIMD Integer", "binary_pattern": "cond | 01111000 | Rd | 1111 | Rm | 0001 | Rn", "hex_opcode": "0x0780F010", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01111000", "clean": "01111000"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1111", "clean": "1111"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "0001", "clean": "0001"}, {"raw": "Rn", "clean": "Rn"}], "bit_positions": "31:28 | 27:20 | 19:16 | 15:12 | 11:8 | 7:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Computes the unsigned sum of absolute differences of four byte-wide values. Treats Rn and Rm as four unsigned bytes each, computes the absolute difference for each byte pair, sums them, and stores the result in Rd. Condition flags N, Z, C, V are unaffected. A32-only instruction requiring DSP extension; commonly used in video codec applications.", "example": "USAD8 r0, r1, r2", "pseudocode": "diff0 ← |Rn[7:0] - Rm[7:0]|\ndiff1 ← |Rn[15:8] - Rm[15:8]|\ndiff2 ← |Rn[23:16] - Rm[23:16]|\ndiff3 ← |Rn[31:24] - Rm[31:24]|\nRd ← diff0 + diff1 + diff2 + diff3"} {"mnemonic": "usada8", "architecture": "ARMv8-A", "full_name": "Unsigned Sum of Absolute Differences Accumulate", "summary": "USAD8 plus accumulator.", "syntax": "USADA8 , , , ", "encoding": {"format": "SIMD Integer", "binary_pattern": "cond | 01111000 | Rd | Ra | Rm | 0001 | Rn", "hex_opcode": "0x07800010", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01111000", "clean": "01111000"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "Ra", "clean": "Ra"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "0001", "clean": "0001"}, {"raw": "Rn", "clean": "Rn"}], "bit_positions": "31:28 | 27:20 | 19:16 | 15:12 | 11:8 | 7:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}, {"name": "Ra", "desc": "Acc"}], "extension": "A32 (DSP)", "description": "Computes the unsigned sum of absolute differences of four byte-wide values and adds an accumulator. Treats Rn and Rm as four unsigned bytes each, computes absolute differences for each byte pair, sums them, and adds the value in Ra to produce the result stored in Rd. Condition flags N, Z, C, V are unaffected. A32-only instruction requiring DSP extension.", "example": "USADA8 r0, r1, r2, r5", "pseudocode": "diff0 ← |Rn[7:0] - Rm[7:0]|\ndiff1 ← |Rn[15:8] - Rm[15:8]|\ndiff2 ← |Rn[23:16] - Rm[23:16]|\ndiff3 ← |Rn[31:24] - Rm[31:24]|\nRd ← (diff0 + diff1 + diff2 + diff3) + Ra"} {"mnemonic": "smmul", "architecture": "ARMv8-A", "full_name": "Signed Most Significant Word Multiply", "summary": "Multiplies and returns the top 32-bits of the 64-bit result.", "syntax": "SMMUL{R} , , ", "encoding": {"format": "Multiply", "binary_pattern": "cond | 01110 | 101 | Rd | 1111 | Rm | 00 | 0 | 1 | Rn", "hex_opcode": "0x0750F010", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01110", "clean": "01110"}, {"raw": "101", "clean": "101"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1111", "clean": "1111"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "00", "clean": "00"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11:8 | 7:6 | 5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Signed Most Significant Word Multiply performs a signed 32×32-bit multiply and returns the upper 32 bits of the 64-bit result in Rd. This is commonly used for fixed-point arithmetic and fast DSP operations. No condition flags are affected. Available in A32 instruction set with DSP extension; the optional R suffix rounds the result by adding 0x80000000 before truncation.", "example": "SMMUL r0, r1, r2", "pseudocode": "product ← SignedMul(Rn, Rm)\nRd ← (product[63:32])"} {"mnemonic": "smmla", "architecture": "ARMv8-A", "full_name": "Signed Most Significant Word Multiply Accumulate", "summary": "SMMUL + Accumulate.", "syntax": "SMMLA{R} , , , ", "encoding": {"format": "Multiply", "binary_pattern": "cond | 01110 | 101 | Rd | Ra | Rm | 00 | 0 | 1 | Rn", "hex_opcode": "0x07500010", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01110", "clean": "01110"}, {"raw": "101", "clean": "101"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "Ra", "clean": "Ra"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "00", "clean": "00"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11:8 | 7:6 | 5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}, {"name": "Ra", "desc": "Acc"}], "extension": "A32 (DSP)", "description": "Signed Most Significant Word Multiply Accumulate computes the signed product of Rn and Rm, extracts the upper 32 bits, and adds the accumulator register Ra to produce the final result stored in Rd. This combines multiplication and accumulation in a single instruction, useful for DSP and filtering operations. No condition flags are affected. Available in A32 instruction set with DSP extension; the optional R suffix applies rounding.", "example": "SMMLA r0, r1, r2, r5", "pseudocode": "product ← SignedMul(Rn, Rm)\nRd ← Ra + (product[63:32])"} {"mnemonic": "vadd", "architecture": "ARMv8-A", "full_name": "Vector Add (VFP)", "summary": "Adds two floating-point values.", "syntax": "VADD.F32 , , ", "encoding": {"format": "VFP Arith", "binary_pattern": "cond | 1110 | 0 | D | 11 | Vn | Vd | 10 | 10 | N | 0 | M | 0 | Vm", "hex_opcode": "0x0E300A00", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "1110", "clean": "1110"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:28 | 27:24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}, {"name": "Sn", "desc": "First source 32-bit floating-point register"}, {"name": "Sm", "desc": "Second source 32-bit floating-point register"}], "extension": "VFP (Float)", "description": "Adds two single-precision floating-point values (Sn + Sm) and stores the result in Sd. This VFP instruction operates on 32-bit IEEE 754 single-precision operands. The condition flags (N, Z, C, V) are updated based on the floating-point result according to the FPSCR. Execution is conditional based on the condition code and requires VFP extension support in A32/T32 modes.", "example": "VADD.F32 s0, s1, s2", "pseudocode": "Sd ← Sn + Sm\nFPSCR.NZCV ← FP_CC(result)"} {"mnemonic": "vadd", "architecture": "ARMv8-A", "full_name": "Vector Add Double (VFP)", "summary": "Adds two double-precision floating-point values.", "syntax": "VADD.F64
, , ", "encoding": {"format": "VFP Arith", "binary_pattern": "cond | 1110 | 0 | D | 11 | Vn | Vd | 10 | 11 | N | 0 | M | 0 | Vm", "hex_opcode": "0x0E300B00", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "1110", "clean": "1110"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "11", "clean": "11"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:28 | 27:24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Dd", "desc": "Destination 64-bit SIMD/FP register"}, {"name": "Dn", "desc": "First source 64-bit SIMD/FP register"}, {"name": "Dm", "desc": "Second source 64-bit SIMD/FP register"}], "extension": "VFP (Float)", "description": "Adds two double-precision floating-point values (Dn + Dm) and stores the result in Dd. This VFP instruction operates on 64-bit IEEE 754 double-precision operands. The condition flags (N, Z, C, V) are updated based on the floating-point result according to the FPSCR. Execution is conditional based on the condition code and requires VFP extension support in A32/T32 modes.", "example": "VADD.F64 d0, d1, d2", "pseudocode": "Dd ← Dn + Dm\nFPSCR.NZCV ← FP_CC(result)"} {"mnemonic": "vsub", "architecture": "ARMv8-A", "full_name": "Vector Subtract (VFP)", "summary": "Subtracts two floating-point values.", "syntax": "VSUB.F32 , , ", "encoding": {"format": "VFP Arith", "binary_pattern": "cond | 1110 | 0 | D | 11 | Vn | Vd | 10 | 10 | N | 1 | M | 0 | Vm", "hex_opcode": "0x0E300A40", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "1110", "clean": "1110"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "N", "clean": "N"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:28 | 27:24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}, {"name": "Sn", "desc": "First source 32-bit floating-point register"}, {"name": "Sm", "desc": "Second source 32-bit floating-point register"}], "extension": "VFP (Float)", "description": "Subtracts two single-precision floating-point values (Sn - Sm) and stores the result in Sd. This VFP instruction operates on 32-bit IEEE 754 single-precision operands. The condition flags (N, Z, C, V) are updated based on the floating-point result according to the FPSCR. Execution is conditional based on the condition code and requires VFP extension support in A32/T32 modes.", "example": "VSUB.F32 s0, s1, s2", "pseudocode": "Sd ← Sn - Sm\nFPSCR.NZCV ← FP_CC(result)"} {"mnemonic": "vmul", "architecture": "ARMv8-A", "full_name": "Vector Multiply (VFP)", "summary": "Multiplies two floating-point values.", "syntax": "VMUL.F32 , , ", "encoding": {"format": "VFP Arith", "binary_pattern": "cond | 1110 | 0 | D | 10 | Vn | Vd | 10 | 10 | N | 0 | M | 0 | Vm", "hex_opcode": "0x0E200A00", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "1110", "clean": "1110"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "10", "clean": "10"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:28 | 27:24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}, {"name": "Sn", "desc": "First source 32-bit floating-point register"}, {"name": "Sm", "desc": "Second source 32-bit floating-point register"}], "extension": "VFP (Float)", "description": "Vector Multiply (VFP) performs single-precision floating-point multiplication of Sn and Sm, storing the result in Sd. The operation follows IEEE 754 semantics, updating the FPSCR exception flags (IXC, OFC, UFC, IOC, DZC) based on the result but not affecting the ARM condition flags N, Z, C, V. Available in A32/T32 with VFP extension; execution is conditional based on the condition code suffix.", "example": "VMUL.F32 s0, s1, s2", "pseudocode": "Sd ← FP_Multiply(Sn, Sm)\nFPSCR ← updated with floating-point exception flags"} {"mnemonic": "vdiv", "architecture": "ARMv8-A", "full_name": "Vector Divide (VFP)", "summary": "Divides two floating-point values.", "syntax": "VDIV.F32 , , ", "encoding": {"format": "VFP Arith", "binary_pattern": "cond | 1110 | 1 | D | 00 | Vn | Vd | 10 | 10 | N | 0 | M | 0 | Vm", "hex_opcode": "0x0E800A00", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "1110", "clean": "1110"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "00", "clean": "00"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:28 | 27:24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}, {"name": "Sn", "desc": "Dividend"}, {"name": "Sm", "desc": "Divisor"}], "extension": "VFP (Float)", "description": "Divides two single-precision floating-point values (Sn / Sm) and stores the result in Sd. This VFP instruction performs floating-point division on 32-bit IEEE 754 single-precision operands. The condition flags (N, Z, C, V) are updated based on the floating-point result according to the FPSCR; division by zero generates a floating-point exception or returns infinity depending on exception settings. Execution is conditional based on the condition code and requires VFP extension support in A32/T32 modes.", "example": "VDIV.F32 s0, s1, s2", "pseudocode": "Sd ← Sn / Sm\nFPSCR.NZCV ← FP_CC(result)\nif (Sm == 0.0) then FP_Exception(DivideByZero)"} {"mnemonic": "vmla", "architecture": "ARMv8-A", "full_name": "Vector Multiply Accumulate (VFP)", "summary": "Sd = Sd + (Sn * Sm).", "syntax": "VMLA.F32 , , ", "encoding": {"format": "VFP Arith", "binary_pattern": "cond | 1110 | 0 | D | 00 | Vn | Vd | 10 | 10 | N | 0 | M | 0 | Vm", "hex_opcode": "0x0E000A00", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "1110", "clean": "1110"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "00", "clean": "00"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:28 | 27:24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Sd", "desc": "Dest/Acc"}, {"name": "Sn", "desc": "First source 32-bit floating-point register"}, {"name": "Sm", "desc": "Second source 32-bit floating-point register"}], "extension": "VFP (Float)", "description": "Vector Multiply Accumulate (VFP) computes Sn × Sm and adds the result to Sd, storing the final value back in Sd. The operation follows IEEE 754 semantics with rounding and exception handling controlled by FPSCR, updating floating-point exception flags but not ARM condition flags. Available in A32/T32 with VFP extension; execution is conditional based on the condition code suffix.", "example": "VMLA.F32 s0, s1, s2", "pseudocode": "product ← FP_Multiply(Sn, Sm)\nSd ← FP_Add(Sd, product)\nFPSCR ← updated with floating-point exception flags"} {"mnemonic": "vmls", "architecture": "ARMv8-A", "full_name": "Vector Multiply Subtract (VFP)", "summary": "Sd = Sd - (Sn * Sm).", "syntax": "VMLS.F32 , , ", "encoding": {"format": "VFP Arith", "binary_pattern": "cond | 1110 | 0 | D | 00 | Vn | Vd | 10 | 10 | N | 1 | M | 0 | Vm", "hex_opcode": "0x0E000A40", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "1110", "clean": "1110"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "00", "clean": "00"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "N", "clean": "N"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:28 | 27:24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Sd", "desc": "Dest/Acc"}, {"name": "Sn", "desc": "First source 32-bit floating-point register"}, {"name": "Sm", "desc": "Second source 32-bit floating-point register"}], "extension": "VFP (Float)", "description": "Multiplies two single-precision floating-point values and subtracts the result from the destination (Sd ← Sd - (Sn × Sm)). This VFP instruction performs a fused multiply-subtract operation on 32-bit IEEE 754 single-precision operands, with Sd serving as both accumulator and destination. The condition flags (N, Z, C, V) are updated based on the final floating-point result according to the FPSCR. Execution is conditional based on the condition code and requires VFP extension support in A32/T32 modes.", "example": "VMLS.F32 s0, s1, s2", "pseudocode": "Sd ← Sd - (Sn × Sm)\nFPSCR.NZCV ← FP_CC(result)"} {"mnemonic": "vnmul", "architecture": "ARMv8-A", "full_name": "Vector Negated Multiply (VFP)", "summary": "Sd = -(Sn * Sm).", "syntax": "VNMUL.F32 , , ", "encoding": {"format": "VFP Arith", "binary_pattern": "cond | 1110 | 0 | D | 10 | Vn | Vd | 10 | 10 | N | 1 | M | 0 | Vm", "hex_opcode": "0x0E200A40", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "1110", "clean": "1110"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "10", "clean": "10"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "N", "clean": "N"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:28 | 27:24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}, {"name": "Sn", "desc": "First source 32-bit floating-point register"}, {"name": "Sm", "desc": "Second source 32-bit floating-point register"}], "extension": "VFP (Float)", "description": "Vector Negated Multiply (VFP) computes the negation of Sn × Sm and stores the result in Sd. This is equivalent to multiplying then negating, and follows IEEE 754 semantics for the intermediate product, with sign negation applied afterward. FPSCR exception flags are updated but ARM condition flags N, Z, C, V are not affected. Available in A32/T32 with VFP extension; execution is conditional based on the condition code suffix.", "example": "VNMUL.F32 s0, s1, s2", "pseudocode": "product ← FP_Multiply(Sn, Sm)\nSd ← FP_Negate(product)\nFPSCR ← updated with floating-point exception flags"} {"mnemonic": "vabs", "architecture": "ARMv8-A", "full_name": "Vector Absolute Value (VFP)", "summary": "Calculates absolute value.", "syntax": "VABS.F32 , ", "encoding": {"format": "VFP Unary", "binary_pattern": "cond | 11101 | D | 11 | 0 | 000 | Vd | 10 | 10 | 1 | 1 | M | 0 | Vm", "hex_opcode": "0x0EB00AC0", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "11101", "clean": "11101"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "0", "clean": "0"}, {"raw": "000", "clean": "000"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}, {"name": "Sm", "desc": "Second source 32-bit floating-point register"}], "extension": "VFP (Float)", "description": "Vector Absolute Value (VFP) computes the absolute value of Sm by clearing the sign bit and storing the result in Sd. This is a unary floating-point operation that follows IEEE 754 semantics, updating FPSCR exception flags but not affecting ARM condition flags. Available in A32/T32 with VFP extension; execution is conditional based on the condition code suffix.", "example": "VABS.F32 s0, s2", "pseudocode": "Sd ← FP_AbsoluteValue(Sm)\nFPSCR ← updated with floating-point exception flags"} {"mnemonic": "vneg", "architecture": "ARMv8-A", "full_name": "Vector Negate (VFP)", "summary": "Negates the value.", "syntax": "VNEG.F32 , ", "encoding": {"format": "VFP Unary", "binary_pattern": "cond | 11101 | D | 11 | 0 | 001 | Vd | 10 | 10 | 0 | 1 | M | 0 | Vm", "hex_opcode": "0x0EB10A40", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "11101", "clean": "11101"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "0", "clean": "0"}, {"raw": "001", "clean": "001"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}, {"name": "Sm", "desc": "Second source 32-bit floating-point register"}], "extension": "VFP (Float)", "description": "Vector Negate (VFP) negates the value in Sm by inverting the sign bit and stores the result in Sd. This is a unary floating-point operation that follows IEEE 754 semantics, affecting only the sign bit and updating FPSCR exception flags but not ARM condition flags. Available in A32/T32 with VFP extension; execution is conditional based on the condition code suffix.", "example": "VNEG.F32 s0, s2", "pseudocode": "Sd ← FP_Negate(Sm)\nFPSCR ← updated with floating-point exception flags"} {"mnemonic": "vsqrt", "architecture": "ARMv8-A", "full_name": "Vector Square Root (VFP)", "summary": "Calculates square root.", "syntax": "VSQRT.F32 , ", "encoding": {"format": "VFP Unary", "binary_pattern": "cond | 11101 | D | 11 | 0 | 001 | Vd | 10 | 10 | 1 | 1 | M | 0 | Vm", "hex_opcode": "0x0EB10AC0", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "11101", "clean": "11101"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "0", "clean": "0"}, {"raw": "001", "clean": "001"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}, {"name": "Sm", "desc": "Second source 32-bit floating-point register"}], "extension": "VFP (Float)", "description": "Vector Square Root (VFP) computes the square root of Sm using IEEE 754 semantics and stores the result in Sd. This unary floating-point operation may raise exceptions for invalid operands (negative inputs) or precision issues, updating FPSCR exception flags but not affecting ARM condition flags. Available in A32/T32 with VFP extension; execution is conditional based on the condition code suffix.", "example": "VSQRT.F32 s0, s2", "pseudocode": "Sd ← FP_SquareRoot(Sm)\nFPSCR ← updated with floating-point exception flags"} {"mnemonic": "vcmp", "architecture": "ARMv8-A", "full_name": "Vector Compare (VFP)", "summary": "Compares two floating-point values.", "syntax": "VCMP.F32 , ", "encoding": {"format": "VFP Compare", "binary_pattern": "cond | 11101 | D | 11 | 0 | 100 | Vd | 10 | 10 | 0 | 1 | M | 0 | Vm", "hex_opcode": "0x0EB40A40", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "11101", "clean": "11101"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "0", "clean": "0"}, {"raw": "100", "clean": "100"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}, {"name": "Sm", "desc": "Second source 32-bit floating-point register"}], "extension": "VFP (Float)", "description": "Compares two single-precision floating-point values in VFP registers and sets the FPSCR condition flags (N, Z, C, V) based on the comparison result. The comparison is quiet (does not raise exceptions for NaN operands). Executed in A32/T32 with VFP extension; condition flags are updated in the floating-point status and control register (FPSCR), not the general-purpose condition flags.", "example": "VCMP.F32 s0, s2", "pseudocode": "result ← compare(Sd, Sm)\nFPSCR.N ← result.N\nFPSCR.Z ← result.Z\nFPSCR.C ← result.C\nFPSCR.V ← result.V"} {"mnemonic": "vcmpe", "architecture": "ARMv8-A", "full_name": "Vector Compare Exception (VFP)", "summary": "Compares values and raises exception on NaN.", "syntax": "VCMPE.F32 , ", "encoding": {"format": "VFP Compare", "binary_pattern": "cond | 11101 | D | 11 | 0 | 100 | Vd | 10 | 10 | 1 | 1 | M | 0 | Vm", "hex_opcode": "0x0EB40AC0", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "11101", "clean": "11101"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "0", "clean": "0"}, {"raw": "100", "clean": "100"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}, {"name": "Sm", "desc": "Second source 32-bit floating-point register"}], "extension": "VFP (Float)", "description": "Compares two single-precision floating-point values in VFP registers and sets the FPSCR condition flags (N, Z, C, V) based on the comparison result. Unlike VCMP, this variant raises an Invalid Operation exception if either operand is NaN (signaling comparison). Executed in A32/T32 with VFP extension; exception behavior depends on FPSCR exception-enable bits.", "example": "VCMPE.F32 s0, s2", "pseudocode": "if Sd is NaN or Sm is NaN then\n if FPSCR.IXE then raise InvalidOperationException\nresult ← compare(Sd, Sm)\nFPSCR.N ← result.N\nFPSCR.Z ← result.Z\nFPSCR.C ← result.C\nFPSCR.V ← result.V"} {"mnemonic": "vcvt", "architecture": "ARMv8-A", "full_name": "Vector Convert (Float to Integer)", "summary": "Converts float to signed/unsigned integer.", "syntax": "VCVT.. , ", "encoding": {"format": "VFP Convert", "binary_pattern": "cond | 11101 | D | 11 | 1 | 000 | Vd | 10 | 01 | op | 1 | M | 0 | Vm", "hex_opcode": "0x0EB80940", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "11101", "clean": "11101"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "1", "clean": "1"}, {"raw": "000", "clean": "000"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "01", "clean": "01"}, {"raw": "op", "clean": "op"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}, {"name": "Sm", "desc": "Second source 32-bit floating-point register"}], "extension": "VFP (Float)", "description": "Converts a single-precision floating-point value to a signed or unsigned 32-bit integer and stores the result in Sd. This VFP instruction performs floating-point-to-integer conversion with rounding behavior controlled by the FPSCR rounding mode. The condition flags are not updated; conversion errors (overflow, invalid operand) may set exception bits in the FPSCR depending on exception configuration. Execution is conditional based on the condition code and requires VFP extension support in A32/T32 modes.", "example": "VCVT.Td.Tm s0, s2", "pseudocode": "result ← Convert_F32_to_Int32(Sm, signed/unsigned, rounding_mode)\nSd ← result\nif (overflow or invalid) then FP_Exception_or_Saturate()"} {"mnemonic": "vmov", "architecture": "ARMv8-A", "full_name": "Vector Move (Register)", "summary": "Moves data between VFP registers.", "syntax": "VMOV.F32 , ", "encoding": {"format": "VFP Move", "binary_pattern": "cond | 11101 | D | 11 | 0 | 000 | Vd | 10 | size | 0 | 1 | M | 0 | Vm", "hex_opcode": "0x0EB00A40", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "11101", "clean": "11101"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "0", "clean": "0"}, {"raw": "000", "clean": "000"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "size", "clean": "size"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}, {"name": "Sm", "desc": "Second source 32-bit floating-point register"}], "extension": "VFP (Float)", "description": "Moves (copies) a single-precision floating-point value from one VFP register to another (Sd ← Sm). This is a pure register-to-register transfer with no arithmetic; it preserves the bit pattern including NaN payloads and sign. Condition flags are not affected. Execution is conditional based on the condition code and requires VFP extension support in A32/T32 modes.", "example": "VMOV.F32 s0, s2", "pseudocode": "Sd ← Sm"} {"mnemonic": "vmov", "architecture": "ARMv8-A", "full_name": "Vector Move (Core <-> VFP)", "summary": "Moves data between Core registers (R) and VFP registers (S).", "syntax": "VMOV , ", "encoding": {"format": "VFP Transfer", "binary_pattern": "cond | 1110000 | 0 | Vn | Rt | 1010 | N | 0 | 0 | 1 | 0 | 0 | 0 | 0", "hex_opcode": "0x0E000A10", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "1110000", "clean": "1110000"}, {"raw": "0", "clean": "0"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Rt", "clean": "Rt"}, {"raw": "1010", "clean": "1010"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}], "bit_positions": "31:28 | 27:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0"}, "operands": [{"name": "Sn", "desc": "VFP Reg"}, {"name": "Rt", "desc": "Core Reg"}], "extension": "VFP (Float)", "description": "Moves a 32-bit value between a core integer register (Rt) and a VFP single-precision register (Sn). The instruction transfers the bit pattern without interpretation; a floating-point value moved to a core register is treated as raw bits. Condition flags are not affected. Execution is conditional based on the condition code and requires VFP extension support in A32/T32 modes.", "example": "VMOV s1, r3", "pseudocode": "Sn ← Rt (bit-exact transfer)"} {"mnemonic": "vldr", "architecture": "ARMv8-A", "full_name": "Vector Load Register (VFP)", "summary": "Loads a floating-point register from memory.", "syntax": "VLDR , [, #+/-]", "encoding": {"format": "VFP Load", "binary_pattern": "cond | 110 | 1 | U | D | 0 | 1 | Rn | Vd | 10 | 10 | imm8", "hex_opcode": "0x0D100A00", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "110", "clean": "110"}, {"raw": "1", "clean": "1"}, {"raw": "U", "clean": "U"}, {"raw": "D", "clean": "D"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "imm8", "clean": "imm8"}], "bit_positions": "31:28 | 27:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:10 | 9:8 | 7:0"}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "imm", "desc": "Signed immediate value"}], "extension": "VFP (Float)", "description": "Loads a single-precision floating-point value from memory into a VFP register using a PC-relative or register-relative address with an optional offset. The memory access uses the address [Rn ± (imm8 << 2)]. Executed in A32/T32 with VFP extension; no condition flags are affected.", "example": "VLDR s0, [r1, #+/-#16]", "pseudocode": "offset ← ZeroExtend(imm8) << 2\nif U == 1 then\n address ← Rn + offset\nelse\n address ← Rn - offset\nSd ← [address]"} {"mnemonic": "vstr", "architecture": "ARMv8-A", "full_name": "Vector Store Register (VFP)", "summary": "Stores a floating-point register to memory.", "syntax": "VSTR , [, #+/-]", "encoding": {"format": "VFP Store", "binary_pattern": "cond | 110 | 1 | U | D | 0 | 0 | Rn | Vd | 10 | 10 | imm8", "hex_opcode": "0x0D000A00", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "110", "clean": "110"}, {"raw": "1", "clean": "1"}, {"raw": "U", "clean": "U"}, {"raw": "D", "clean": "D"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "imm8", "clean": "imm8"}], "bit_positions": "31:28 | 27:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:10 | 9:8 | 7:0"}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "imm", "desc": "Signed immediate value"}], "extension": "VFP (Float)", "description": "Stores a single-precision floating-point value from a VFP register to memory using a register-relative address with an optional offset. The memory access uses the address [Rn ± (imm8 << 2)]. Executed in A32/T32 with VFP extension; no condition flags are affected.", "example": "VSTR s0, [r1, #+/-#16]", "pseudocode": "offset ← ZeroExtend(imm8) << 2\nif U == 1 then\n address ← Rn + offset\nelse\n address ← Rn - offset\n[address] ← Sd"} {"mnemonic": "vpop", "architecture": "ARMv8-A", "full_name": "Vector Pop (VFP)", "summary": "Pops VFP registers from the stack (Alias for VLDMIA SP!).", "syntax": "VPOP ", "encoding": {"format": "VFP Load Multiple", "binary_pattern": "cond | 110 | 0 | 1 | D | 1 | 1 | 1101 | Vd | 10 | 10 | imm8", "hex_opcode": "0x0CBD0A00", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "110", "clean": "110"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1101", "clean": "1101"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "imm8", "clean": "imm8"}], "bit_positions": "31:28 | 27:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:10 | 9:8 | 7:0"}, "operands": [{"name": "list", "desc": "Register List"}], "extension": "VFP (Float)", "description": "Pops VFP floating-point registers from the stack by loading them from memory at the address in SP, then post-incrementing SP. This is an alias for VLDMIA SP! (VFP Load Multiple with post-index). The condition flags (N, Z, C, V) are unaffected by this instruction. Execution is restricted to A32 and T32 instruction sets with VFP extension enabled.", "example": "VPOP {r0-r3", "pseudocode": "address ← SP; for each register in list (in ascending order): register ← [address]; address ← address + 4 or 8 (depending on register width); SP ← address;"} {"mnemonic": "vpush", "architecture": "ARMv8-A", "full_name": "Vector Push (VFP)", "summary": "Pushes VFP registers to the stack (Alias for VSTMDB SP!).", "syntax": "VPUSH ", "encoding": {"format": "VFP Store Multiple", "binary_pattern": "cond | 110 | 1 | 0 | D | 1 | 0 | 1101 | Vd | 10 | 10 | imm8", "hex_opcode": "0x0D2D0A00", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "110", "clean": "110"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "1101", "clean": "1101"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "imm8", "clean": "imm8"}], "bit_positions": "31:28 | 27:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:10 | 9:8 | 7:0"}, "operands": [{"name": "list", "desc": "Register List"}], "extension": "VFP (Float)", "description": "Pushes VFP floating-point registers onto the stack by decrementing SP and storing them to memory. This is an alias for VSTMDB SP! (VFP Store Multiple with pre-decrement). The condition flags (N, Z, C, V) are unaffected by this instruction. Execution is restricted to A32 and T32 instruction sets with VFP extension enabled.", "example": "VPUSH {r0-r3", "pseudocode": "address ← SP; for each register in list (in descending order): address ← address - 4 or 8 (depending on register width); [address] ← register; SP ← address;"} {"mnemonic": "adc.w", "architecture": "ARMv8-A", "full_name": "Add with Carry (Wide)", "summary": "Thumb-2 32-bit add with carry (Access high registers/large constants).", "syntax": "ADC.W , , ", "encoding": {"format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 1010 | 0 | Rn | 0 | imm3 | Rd | imm2 | stype | Rm", "hex_opcode": "0xEB400000", "visual_parts": [{"raw": "1110101", "clean": "1110101"}, {"raw": "1010", "clean": "1010"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "0", "clean": "0"}, {"raw": "imm3", "clean": "imm3"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "imm2", "clean": "imm2"}, {"raw": "stype", "clean": "stype"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Operand2", "desc": "Flexible second operand (register or shifted register)"}], "extension": "T32 (Thumb2)", "description": "Adds Rn and Operand2 plus the Carry flag value, storing the result in Rd. If S=1, the N, Z, C, V flags are updated based on the result; otherwise flags are unaffected. This is a Thumb-2 32-bit instruction that allows use of high registers (R8-R15) and larger constant operands than 16-bit Thumb ADC.", "example": "ADC.W r0, r1, r2", "pseudocode": "result ← Rn + Operand2 + C; Rd ← result; if S == 1 then: N ← result[31]; Z ← (result == 0); C ← CarryOut(Rn, Operand2, C); V ← OverflowFrom(Rn, Operand2, C);"} {"mnemonic": "add.w", "architecture": "ARMv8-A", "full_name": "Add (Wide)", "summary": "Thumb-2 32-bit add.", "syntax": "ADD.W , , ", "encoding": {"format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 1000 | 0 | Rn | 0 | imm3 | Rd | imm2 | stype | Rm", "hex_opcode": "0xEB000000", "visual_parts": [{"raw": "1110101", "clean": "1110101"}, {"raw": "1000", "clean": "1000"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "0", "clean": "0"}, {"raw": "imm3", "clean": "imm3"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "imm2", "clean": "imm2"}, {"raw": "stype", "clean": "stype"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Operand2", "desc": "Flexible second operand (register or shifted register)"}], "extension": "T32 (Thumb2)", "description": "Adds Rn and Operand2, storing the result in Rd. If S=1, the N, Z, C, V flags are updated based on the result; otherwise flags are unaffected. This is a Thumb-2 32-bit instruction that allows use of high registers (R8-R15) and larger constant operands than 16-bit Thumb ADD.", "example": "ADD.W r0, r1, r2", "pseudocode": "result ← Rn + Operand2; Rd ← result; if S == 1 then: N ← result[31]; Z ← (result == 0); C ← CarryOut(Rn, Operand2); V ← OverflowFrom(Rn, Operand2);"} {"mnemonic": "sub.w", "architecture": "ARMv8-A", "full_name": "Subtract (Wide)", "summary": "Thumb-2 32-bit subtract.", "syntax": "SUB.W , , ", "encoding": {"format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 1101 | 0 | Rn | 0 | imm3 | Rd | imm2 | stype | Rm", "hex_opcode": "0xEBA00000", "visual_parts": [{"raw": "1110101", "clean": "1110101"}, {"raw": "1101", "clean": "1101"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "0", "clean": "0"}, {"raw": "imm3", "clean": "imm3"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "imm2", "clean": "imm2"}, {"raw": "stype", "clean": "stype"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Operand2", "desc": "Flexible second operand (register or shifted register)"}], "extension": "T32 (Thumb2)", "description": "Subtracts Operand2 from Rn, storing the result in Rd. If S=1, the N, Z, C, V flags are updated based on the result; otherwise flags are unaffected. This is a Thumb-2 32-bit instruction that allows use of high registers (R8-R15) and larger constant operands than 16-bit Thumb SUB.", "example": "SUB.W r0, r1, r2", "pseudocode": "result ← Rn - Operand2; Rd ← result; if S == 1 then: N ← result[31]; Z ← (result == 0); C ← NOT BorrowFrom(Rn, Operand2); V ← OverflowFrom(Rn, -Operand2);"} {"mnemonic": "sbc.w", "architecture": "ARMv8-A", "full_name": "Subtract with Carry (Wide)", "summary": "Thumb-2 32-bit subtract with carry.", "syntax": "SBC.W , , ", "encoding": {"format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 1011 | 0 | Rn | 0 | imm3 | Rd | imm2 | stype | Rm", "hex_opcode": "0xEB600000", "visual_parts": [{"raw": "1110101", "clean": "1110101"}, {"raw": "1011", "clean": "1011"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "0", "clean": "0"}, {"raw": "imm3", "clean": "imm3"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "imm2", "clean": "imm2"}, {"raw": "stype", "clean": "stype"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Operand2", "desc": "Flexible second operand (register or shifted register)"}], "extension": "T32 (Thumb2)", "description": "Subtracts Operand2 and the inverted Carry flag from Rn, storing the result in Rd. If S=1, the N, Z, C, V flags are updated based on the result; otherwise flags are unaffected. This is a Thumb-2 32-bit instruction used for multi-word arithmetic with carry propagation.", "example": "SBC.W r0, r1, r2", "pseudocode": "result ← Rn - Operand2 - (NOT C); Rd ← result; if S == 1 then: N ← result[31]; Z ← (result == 0); C ← NOT BorrowFrom(Rn, Operand2, NOT C); V ← OverflowFrom(Rn, -Operand2, NOT C);"} {"mnemonic": "rsb.w", "architecture": "ARMv8-A", "full_name": "Reverse Subtract (Wide)", "summary": "Thumb-2 32-bit reverse subtract.", "syntax": "RSB.W , , ", "encoding": {"format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 1110 | 0 | Rn | 0 | imm3 | Rd | imm2 | stype | Rm", "hex_opcode": "0xEBC00000", "visual_parts": [{"raw": "1110101", "clean": "1110101"}, {"raw": "1110", "clean": "1110"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "0", "clean": "0"}, {"raw": "imm3", "clean": "imm3"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "imm2", "clean": "imm2"}, {"raw": "stype", "clean": "stype"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Operand2", "desc": "Flexible second operand (register or shifted register)"}], "extension": "T32 (Thumb2)", "description": "Reverse-subtracts Rn from Operand2, storing the result in Rd (computes Operand2 - Rn). If S=1, the N, Z, C, V flags are updated based on the result; otherwise flags are unaffected. This is a Thumb-2 32-bit instruction allowing negation and complex arithmetic patterns.", "example": "RSB.W r0, r1, r2", "pseudocode": "result ← Operand2 - Rn; Rd ← result; if S == 1 then: N ← result[31]; Z ← (result == 0); C ← NOT BorrowFrom(Operand2, Rn); V ← OverflowFrom(Operand2, -Rn);"} {"mnemonic": "and.w", "architecture": "ARMv8-A", "full_name": "Bitwise AND (Wide)", "summary": "Thumb-2 32-bit AND.", "syntax": "AND.W , , ", "encoding": {"format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 0000 | 0 | Rn | 0 | imm3 | Rd | imm2 | stype | Rm", "hex_opcode": "0xEA000000", "visual_parts": [{"raw": "1110101", "clean": "1110101"}, {"raw": "0000", "clean": "0000"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "0", "clean": "0"}, {"raw": "imm3", "clean": "imm3"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "imm2", "clean": "imm2"}, {"raw": "stype", "clean": "stype"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Operand2", "desc": "Flexible second operand (register or shifted register)"}], "extension": "T32 (Thumb2)", "description": "Performs a bitwise AND of Rn and the shifted Operand2, storing the result in Rd. In Thumb-2, this is a 32-bit instruction that can update the condition flags (N, Z, C) when the S bit is set; V is unaffected. The operand2 can be a register with optional shift or an immediate value.", "example": "AND.W r0, r1, r2", "pseudocode": "result ← Rn AND Operand2\nRd ← result\nif S == 1 then\n CPSR.N ← result[31]\n CPSR.Z ← (result == 0)\n CPSR.C ← CarryOut(Operand2)\nelse\n CPSR.C ← CPSR.C"} {"mnemonic": "orr.w", "architecture": "ARMv8-A", "full_name": "Bitwise OR (Wide)", "summary": "Thumb-2 32-bit OR.", "syntax": "ORR.W , , ", "encoding": {"format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 0010 | 0 | Rn | 0 | imm3 | Rd | imm2 | stype | Rm", "hex_opcode": "0xEA400000", "visual_parts": [{"raw": "1110101", "clean": "1110101"}, {"raw": "0010", "clean": "0010"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "0", "clean": "0"}, {"raw": "imm3", "clean": "imm3"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "imm2", "clean": "imm2"}, {"raw": "stype", "clean": "stype"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Operand2", "desc": "Flexible second operand (register or shifted register)"}], "extension": "T32 (Thumb2)", "description": "Performs a bitwise OR of Rn and the shifted Operand2, storing the result in Rd. In Thumb-2, this is a 32-bit instruction that can update the condition flags (N, Z, C) when the S bit is set; V is unaffected. The operand2 can be a register with optional shift or an immediate value.", "example": "ORR.W r0, r1, r2", "pseudocode": "result ← Rn OR Operand2\nRd ← result\nif S == 1 then\n CPSR.N ← result[31]\n CPSR.Z ← (result == 0)\n CPSR.C ← CarryOut(Operand2)\nelse\n CPSR.C ← CPSR.C"} {"mnemonic": "eor.w", "architecture": "ARMv8-A", "full_name": "Bitwise Exclusive OR (Wide)", "summary": "Thumb-2 32-bit XOR.", "syntax": "EOR.W , , ", "encoding": {"format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 0100 | 0 | Rn | 0 | imm3 | Rd | imm2 | stype | Rm", "hex_opcode": "0xEA800000", "visual_parts": [{"raw": "1110101", "clean": "1110101"}, {"raw": "0100", "clean": "0100"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "0", "clean": "0"}, {"raw": "imm3", "clean": "imm3"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "imm2", "clean": "imm2"}, {"raw": "stype", "clean": "stype"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Operand2", "desc": "Flexible second operand (register or shifted register)"}], "extension": "T32 (Thumb2)", "description": "Performs a bitwise exclusive-OR (XOR) of Rn and the shifted Operand2, storing the result in Rd. In Thumb-2, this is a 32-bit instruction that can update the condition flags (N, Z, C) when the S bit is set; V is unaffected. The operand2 can be a register with optional shift or an immediate value.", "example": "EOR.W r0, r1, r2", "pseudocode": "result ← Rn XOR Operand2\nRd ← result\nif S == 1 then\n CPSR.N ← result[31]\n CPSR.Z ← (result == 0)\n CPSR.C ← CarryOut(Operand2)\nelse\n CPSR.C ← CPSR.C"} {"mnemonic": "bic.w", "architecture": "ARMv8-A", "full_name": "Bitwise Bit Clear (Wide)", "summary": "Thumb-2 32-bit AND NOT.", "syntax": "BIC.W , , ", "encoding": {"format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 0001 | 0 | Rn | 0 | imm3 | Rd | imm2 | stype | Rm", "hex_opcode": "0xEA200000", "visual_parts": [{"raw": "1110101", "clean": "1110101"}, {"raw": "0001", "clean": "0001"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "0", "clean": "0"}, {"raw": "imm3", "clean": "imm3"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "imm2", "clean": "imm2"}, {"raw": "stype", "clean": "stype"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Operand2", "desc": "Flexible second operand (register or shifted register)"}], "extension": "T32 (Thumb2)", "description": "Performs a bitwise AND of Rn with the bitwise NOT of the shifted Operand2, effectively clearing bits in Rn where Operand2 has set bits. In Thumb-2, this is a 32-bit instruction that can update the condition flags (N, Z, C) when the S bit is set; V is unaffected. The operand2 can be a register with optional shift or an immediate value.", "example": "BIC.W r0, r1, r2", "pseudocode": "result ← Rn AND NOT Operand2\nRd ← result\nif S == 1 then\n CPSR.N ← result[31]\n CPSR.Z ← (result == 0)\n CPSR.C ← CarryOut(Operand2)\nelse\n CPSR.C ← CPSR.C"} {"mnemonic": "orn.w", "architecture": "ARMv8-A", "full_name": "Bitwise OR NOT (Wide)", "summary": "Thumb-2 32-bit OR NOT.", "syntax": "ORN.W , , ", "encoding": {"format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 0011 | 0 | Rn | 0 | imm3 | Rd | imm2 | stype | Rm", "hex_opcode": "0xEA600000", "visual_parts": [{"raw": "1110101", "clean": "1110101"}, {"raw": "0011", "clean": "0011"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "0", "clean": "0"}, {"raw": "imm3", "clean": "imm3"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "imm2", "clean": "imm2"}, {"raw": "stype", "clean": "stype"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Operand2", "desc": "Flexible second operand (register or shifted register)"}], "extension": "T32 (Thumb2)", "description": "Bitwise OR NOT: computes Rd = Rn | ~Operand2, performing a logical OR between Rn and the bitwise NOT of Operand2. The N and Z flags are updated based on the result; C is updated by the shifter; V is unaffected. This is a Thumb-2 (32-bit) instruction available in T32 execution state.", "example": "ORN.W r0, r1, r2", "pseudocode": "result ← Rn | (NOT Operand2)\nRd ← result\nN ← result[31]\nZ ← (result == 0)\nC ← CarryOut(NOT Operand2)\nV ← unchanged"} {"mnemonic": "mov.w", "architecture": "ARMv8-A", "full_name": "Move (Wide)", "summary": "Thumb-2 32-bit Move.", "syntax": "MOV.W , ", "encoding": {"format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 0010 | 0 | 1111 | 0 | imm3 | Rd | imm2 | stype | Rm", "hex_opcode": "0xEA4F0000", "visual_parts": [{"raw": "1110101", "clean": "1110101"}, {"raw": "0010", "clean": "0010"}, {"raw": "0", "clean": "0"}, {"raw": "1111", "clean": "1111"}, {"raw": "0", "clean": "0"}, {"raw": "imm3", "clean": "imm3"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "imm2", "clean": "imm2"}, {"raw": "stype", "clean": "stype"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Operand2", "desc": "Flexible second operand (register or shifted register)"}], "extension": "T32 (Thumb2)", "description": "Moves Operand2 into Rd without affecting any flags (the S bit is fixed to 0 in this variant). This is a Thumb-2 32-bit instruction that allows encoding of larger immediates (via modified immediate) and access to high registers (R8-R15), providing greater flexibility than 16-bit Thumb MOV.", "example": "MOV.W r0, r2", "pseudocode": "Rd ← Operand2;"} {"mnemonic": "mvn.w", "architecture": "ARMv8-A", "full_name": "Move NOT (Wide)", "summary": "Thumb-2 32-bit Move Inverse.", "syntax": "MVN.W , ", "encoding": {"format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 0011 | 0 | 1111 | 0 | imm3 | Rd | imm2 | stype | Rm", "hex_opcode": "0xEA6F0000", "visual_parts": [{"raw": "1110101", "clean": "1110101"}, {"raw": "0011", "clean": "0011"}, {"raw": "0", "clean": "0"}, {"raw": "1111", "clean": "1111"}, {"raw": "0", "clean": "0"}, {"raw": "imm3", "clean": "imm3"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "imm2", "clean": "imm2"}, {"raw": "stype", "clean": "stype"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Operand2", "desc": "Flexible second operand (register or shifted register)"}], "extension": "T32 (Thumb2)", "description": "Thumb-2 32-bit bitwise NOT: Rd ← NOT(Operand2). The second operand can be a register or a shifted register. If the S suffix is present, the condition flags N and Z are updated based on the result, and C is updated from the shifter carry-out; V is unaffected. Execution state: T32 only.", "example": "MVN.W r0, r2", "pseudocode": "result ← NOT(Operand2)\nRd ← result\nif S then\n N ← result[31]\n Z ← (result == 0)\n C ← shifter_carry_out"} {"mnemonic": "tst.w", "architecture": "ARMv8-A", "full_name": "Test (Wide)", "summary": "Thumb-2 32-bit Test (AND and update flags).", "syntax": "TST.W , ", "encoding": {"format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 0000 | 1 | Rn | 0 | imm3 | 1111 | imm2 | stype | Rm", "hex_opcode": "0xEA100F00", "visual_parts": [{"raw": "1110101", "clean": "1110101"}, {"raw": "0000", "clean": "0000"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "0", "clean": "0"}, {"raw": "imm3", "clean": "imm3"}, {"raw": "1111", "clean": "1111"}, {"raw": "imm2", "clean": "imm2"}, {"raw": "stype", "clean": "stype"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0"}, "operands": [{"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Operand2", "desc": "Flexible second operand (register or shifted register)"}], "extension": "T32 (Thumb2)", "description": "Test (AND and update flags): computes the bitwise AND of Rn and Operand2, updating the N and Z flags based on the result without writing to a destination register. C is updated by the shifter; V is unaffected. This is a Thumb-2 (32-bit) instruction available in T32 execution state.", "example": "TST.W r1, r2", "pseudocode": "result ← Rn AND Operand2\nN ← result[31]\nZ ← (result == 0)\nC ← CarryOut(Operand2)\nV ← unchanged"} {"mnemonic": "teq.w", "architecture": "ARMv8-A", "full_name": "Test Equivalence (Wide)", "summary": "Thumb-2 32-bit Test Equivalence (XOR and update flags).", "syntax": "TEQ.W , ", "encoding": {"format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 0100 | 1 | Rn | 0 | imm3 | 1111 | imm2 | stype | Rm", "hex_opcode": "0xEA900F00", "visual_parts": [{"raw": "1110101", "clean": "1110101"}, {"raw": "0100", "clean": "0100"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "0", "clean": "0"}, {"raw": "imm3", "clean": "imm3"}, {"raw": "1111", "clean": "1111"}, {"raw": "imm2", "clean": "imm2"}, {"raw": "stype", "clean": "stype"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0"}, "operands": [{"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Operand2", "desc": "Flexible second operand (register or shifted register)"}], "extension": "T32 (Thumb2)", "description": "Test Equivalence (XOR and update flags): computes the bitwise XOR of Rn and Operand2, updating the N and Z flags based on the result without writing to a destination register. C is updated by the shifter; V is unaffected. This is a Thumb-2 (32-bit) instruction available in T32 execution state.", "example": "TEQ.W r1, r2", "pseudocode": "result ← Rn XOR Operand2\nN ← result[31]\nZ ← (result == 0)\nC ← CarryOut(Operand2)\nV ← unchanged"} {"mnemonic": "cmp.w", "architecture": "ARMv8-A", "full_name": "Compare (Wide)", "summary": "Thumb-2 32-bit Compare (Subtract and update flags).", "syntax": "CMP.W , ", "encoding": {"format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 1101 | 1 | Rn | 0 | imm3 | 1111 | imm2 | stype | Rm", "hex_opcode": "0xEBB00F00", "visual_parts": [{"raw": "1110101", "clean": "1110101"}, {"raw": "1101", "clean": "1101"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "0", "clean": "0"}, {"raw": "imm3", "clean": "imm3"}, {"raw": "1111", "clean": "1111"}, {"raw": "imm2", "clean": "imm2"}, {"raw": "stype", "clean": "stype"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0"}, "operands": [{"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Operand2", "desc": "Flexible second operand (register or shifted register)"}], "extension": "T32 (Thumb2)", "description": "Compare (Subtract and update flags): computes Rn - Operand2, updating the N, Z, C, and V flags based on the result without writing to a destination register. This is a Thumb-2 (32-bit) instruction available in T32 execution state and is commonly used to set condition flags for subsequent conditional branches.", "example": "CMP.W r1, r2", "pseudocode": "result ← Rn - Operand2\nN ← result[31]\nZ ← (result == 0)\nC ← NOT BorrowFrom(Rn - Operand2)\nV ← OverflowFrom(Rn - Operand2)"} {"mnemonic": "cmn.w", "architecture": "ARMv8-A", "full_name": "Compare Negative (Wide)", "summary": "Thumb-2 32-bit Compare Negative (Add and update flags).", "syntax": "CMN.W , ", "encoding": {"format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 1000 | 1 | Rn | 0 | imm3 | 1111 | imm2 | stype | Rm", "hex_opcode": "0xEB100F00", "visual_parts": [{"raw": "1110101", "clean": "1110101"}, {"raw": "1000", "clean": "1000"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "0", "clean": "0"}, {"raw": "imm3", "clean": "imm3"}, {"raw": "1111", "clean": "1111"}, {"raw": "imm2", "clean": "imm2"}, {"raw": "stype", "clean": "stype"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0"}, "operands": [{"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Operand2", "desc": "Flexible second operand (register or shifted register)"}], "extension": "T32 (Thumb2)", "description": "Compare Negative (Add and update flags): computes Rn + Operand2, updating the N, Z, C, and V flags based on the result without writing to a destination register. This is a Thumb-2 (32-bit) instruction available in T32 execution state and is commonly used to compare a register against the negation of a value.", "example": "CMN.W r1, r2", "pseudocode": "result ← Rn + Operand2\nN ← result[31]\nZ ← (result == 0)\nC ← CarryOut(Rn + Operand2)\nV ← OverflowFrom(Rn + Operand2)"} {"mnemonic": "cdp", "architecture": "ARMv8-A", "full_name": "Coprocessor Data Processing (A32)", "summary": "Initiates a coprocessor data processing operation.", "syntax": "CDP , , , , , ", "encoding": {"format": "Coprocessor", "binary_pattern": "cond | 1110 | opc1 | CRn | CRd | coproc | opc2 | 0 | CRm", "hex_opcode": "0x0E000000", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "1110", "clean": "1110"}, {"raw": "opc1", "clean": "opc1"}, {"raw": "CRn", "clean": "CRn"}, {"raw": "CRd", "clean": "CRd"}, {"raw": "coproc", "clean": "coproc"}, {"raw": "opc2", "clean": "opc2"}, {"raw": "0", "clean": "0"}, {"raw": "CRm", "clean": "CRm"}]}, "operands": [{"name": "coproc", "desc": "CP Num"}, {"name": "CRd", "desc": "Destination coprocessor register"}, {"name": "CRn", "desc": "First source coprocessor register"}, {"name": "CRm", "desc": "Second source coprocessor register"}], "extension": "A32 (System)", "description": "Coprocessor Data Processing: initiates a data processing operation in the specified coprocessor using three coprocessor registers and two operation codes. The instruction is conditional based on the condition field and does not modify processor flags. This is an A32 instruction restricted to privileged execution states in systems with a coprocessor.", "example": "CDP p15, 0, c0, c1, c2, 0", "pseudocode": "if ConditionPassed() then\n Coprocessor[coproc].DataProcessing(opc1, CRd, CRn, CRm, opc2)"} {"mnemonic": "cdp2", "architecture": "ARMv8-A", "full_name": "Coprocessor Data Processing 2 (A32)", "summary": "Initiates a coprocessor operation (Extension encoding).", "syntax": "CDP2 , , , , , ", "encoding": {"format": "Coprocessor", "binary_pattern": "11111110 | opc1 | CRn | CRd | coproc | opc2 | 0 | CRm", "hex_opcode": "0xFE000000", "visual_parts": [{"raw": "11111110", "clean": "11111110"}, {"raw": "opc1", "clean": "opc1"}, {"raw": "CRn", "clean": "CRn"}, {"raw": "CRd", "clean": "CRd"}, {"raw": "coproc", "clean": "coproc"}, {"raw": "opc2", "clean": "opc2"}, {"raw": "0", "clean": "0"}, {"raw": "CRm", "clean": "CRm"}]}, "operands": [{"name": "coproc", "desc": "CP Num"}, {"name": "CRd", "desc": "Destination coprocessor register"}, {"name": "CRn", "desc": "First source coprocessor register"}, {"name": "CRm", "desc": "Second source coprocessor register"}], "extension": "A32 (System)", "description": "Coprocessor Data Processing 2 (unconditional extension): initiates a data processing operation in the specified coprocessor using three coprocessor registers and two operation codes. Unlike CDP, this instruction is unconditional and uses the extension encoding (always executes). Restricted to privileged execution states in systems with a coprocessor.", "example": "CDP2 p15, 0, c0, c1, c2, 0", "pseudocode": "Coprocessor[coproc].DataProcessing(opc1, CRd, CRn, CRm, opc2)"} {"mnemonic": "mcr2", "architecture": "ARMv8-A", "full_name": "Move to Coprocessor from Register 2 (A32)", "summary": "Writes a general-purpose register to a coprocessor (Extension encoding).", "syntax": "MCR2 , , , , {, }", "encoding": {"format": "Coprocessor", "binary_pattern": "11111110 | opc1 | 0 | CRn | Rt | coproc | opc2 | 1 | CRm", "hex_opcode": "0xFE000010", "visual_parts": [{"raw": "11111110", "clean": "11111110"}, {"raw": "opc1", "clean": "opc1"}, {"raw": "0", "clean": "0"}, {"raw": "CRn", "clean": "CRn"}, {"raw": "Rt", "clean": "Rt"}, {"raw": "coproc", "clean": "coproc"}, {"raw": "opc2", "clean": "opc2"}, {"raw": "1", "clean": "1"}, {"raw": "CRm", "clean": "CRm"}]}, "operands": [{"name": "coproc", "desc": "CP Num"}, {"name": "Rt", "desc": "Transfer general-purpose register (load/store)"}, {"name": "CRn", "desc": "Dest CP Reg"}], "extension": "A32 (System)", "description": "A32 coprocessor data transfer (extension encoding): writes the general-purpose register Rt to the coprocessor coproc, register CRm, with operation codes opc1 and opc2. Does not modify condition flags. Execution state: A32 only; requires coprocessor support. May cause an Undefined Instruction exception if the coprocessor does not exist.", "example": "MCR2 p15, 0, r3, c1, c2", "pseudocode": "Coprocessor[coproc].CRm[opc2] ← Rt"} {"mnemonic": "mrc2", "architecture": "ARMv8-A", "full_name": "Move to Register from Coprocessor 2 (A32)", "summary": "Reads a coprocessor register into a general-purpose register (Extension encoding).", "syntax": "MRC2 , , , , {, }", "encoding": {"format": "Coprocessor", "binary_pattern": "11111110 | opc1 | 1 | CRn | Rt | coproc | opc2 | 1 | CRm", "hex_opcode": "0xFE100010", "visual_parts": [{"raw": "11111110", "clean": "11111110"}, {"raw": "opc1", "clean": "opc1"}, {"raw": "1", "clean": "1"}, {"raw": "CRn", "clean": "CRn"}, {"raw": "Rt", "clean": "Rt"}, {"raw": "coproc", "clean": "coproc"}, {"raw": "opc2", "clean": "opc2"}, {"raw": "1", "clean": "1"}, {"raw": "CRm", "clean": "CRm"}]}, "operands": [{"name": "coproc", "desc": "CP Num"}, {"name": "Rt", "desc": "Transfer general-purpose register (load/store)"}, {"name": "CRn", "desc": "Src CP Reg"}], "extension": "A32 (System)", "description": "A32 coprocessor data transfer (extension encoding): reads a coprocessor register (CRn, CRm) from coproc into the general-purpose register Rt. The opc1 and opc2 fields specify the operation. Does not modify condition flags. Execution state: A32 only; requires coprocessor support. May cause an Undefined Instruction exception if the coprocessor does not exist.", "example": "MRC2 p15, 0, r3, c1, c2", "pseudocode": "Rt ← Coprocessor[coproc].CRn[opc1] or Coprocessor[coproc].CRm[opc2]"} {"mnemonic": "mcrr2", "architecture": "ARMv8-A", "full_name": "Move to Coprocessor from Two Registers 2 (A32)", "summary": "Writes two registers to a coprocessor (Extension encoding).", "syntax": "MCRR2 , , , , ", "encoding": {"format": "Coprocessor", "binary_pattern": "111111000100 | Rt2 | Rt | coproc | opc1 | CRm", "hex_opcode": "0xFC400000", "visual_parts": [{"raw": "111111000100", "clean": "111111000100"}, {"raw": "Rt2", "clean": "Rt2"}, {"raw": "Rt", "clean": "Rt"}, {"raw": "coproc", "clean": "coproc"}, {"raw": "opc1", "clean": "opc1"}, {"raw": "CRm", "clean": "CRm"}]}, "operands": [{"name": "coproc", "desc": "CP Num"}, {"name": "Rt", "desc": "Transfer general-purpose register (load/store)"}, {"name": "Rt2", "desc": "Second transfer register (load/store pair)"}], "extension": "A32 (System)", "description": "A32 coprocessor data transfer (extension encoding): writes two general-purpose registers (Rt, Rt2) to the coprocessor coproc, coprocessor register CRm, with operation code opc1. Does not modify condition flags. Execution state: A32 only; requires coprocessor support. May cause an Undefined Instruction exception if the coprocessor does not exist.", "example": "MCRR2 p15, 0, r3, r4, c2", "pseudocode": "Coprocessor[coproc].CRm ← (Rt2 : Rt)"} {"mnemonic": "mrrc2", "architecture": "ARMv8-A", "full_name": "Move to Two Registers from Coprocessor 2 (A32)", "summary": "Reads a coprocessor register into two registers (Extension encoding).", "syntax": "MRRC2 , , , , ", "encoding": {"format": "Coprocessor", "binary_pattern": "111111000101 | Rt2 | Rt | coproc | opc1 | CRm", "hex_opcode": "0xFC500000", "visual_parts": [{"raw": "111111000101", "clean": "111111000101"}, {"raw": "Rt2", "clean": "Rt2"}, {"raw": "Rt", "clean": "Rt"}, {"raw": "coproc", "clean": "coproc"}, {"raw": "opc1", "clean": "opc1"}, {"raw": "CRm", "clean": "CRm"}]}, "operands": [{"name": "coproc", "desc": "CP Num"}, {"name": "Rt", "desc": "Dest 1"}, {"name": "Rt2", "desc": "Dest 2"}], "extension": "A32 (System)", "description": "A32 coprocessor data transfer (extension encoding): reads a 64-bit value from coprocessor coproc register CRm into two general-purpose registers (Rt, Rt2), with operation code opc1. Does not modify condition flags. Execution state: A32 only; requires coprocessor support. May cause an Undefined Instruction exception if the coprocessor does not exist.", "example": "MRRC2 p15, 0, r3, r4, c2", "pseudocode": "(Rt2 : Rt) ← Coprocessor[coproc].CRm"} {"mnemonic": "ldc2", "architecture": "ARMv8-A", "full_name": "Load Coprocessor 2 (A32)", "summary": "Loads memory into a coprocessor (Extension encoding).", "syntax": "LDC2{L} , , [, #+/-]{!}", "encoding": {"format": "Coprocessor", "binary_pattern": "1111110 | P | U | N | W | 1 | Rn | CRd | coproc | imm8", "hex_opcode": "0xFD100000", "visual_parts": [{"raw": "1111110", "clean": "1111110"}, {"raw": "P", "clean": "P"}, {"raw": "U", "clean": "U"}, {"raw": "N", "clean": "N"}, {"raw": "W", "clean": "W"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "CRd", "clean": "CRd"}, {"raw": "coproc", "clean": "coproc"}, {"raw": "imm8", "clean": "imm8"}]}, "operands": [{"name": "coproc", "desc": "CP Num"}, {"name": "CRd", "desc": "Destination coprocessor register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}], "extension": "A32 (System)", "description": "Load Coprocessor 2 (unconditional extension): loads a word or multiple words from memory into a coprocessor register, with the memory address computed from Rn plus an optional offset. The P, U, W bits control pre/post-indexing and writeback; the instruction is unconditional and uses the extension encoding. Restricted to privileged execution states and requires a coprocessor.", "example": "LDC2 p15, c0, [r1, #+/-#16]!", "pseudocode": "if P == 0 and W == 1 then\n address ← Rn\n Rn ← Rn + (if U then imm8 << 2 else -(imm8 << 2))\nelse if P == 1 then\n address ← Rn + (if U then imm8 << 2 else -(imm8 << 2))\n if W == 1 then Rn ← address\nCoprocessor[coproc].LoadFromMemory(CRd, address)"} {"mnemonic": "stc2", "architecture": "ARMv8-A", "full_name": "Store Coprocessor 2 (A32)", "summary": "Stores coprocessor contents to memory (Extension encoding).", "syntax": "STC2{L} , , [, #+/-]{!}", "encoding": {"format": "Coprocessor", "binary_pattern": "1111110 | P | U | N | W | 0 | Rn | CRd | coproc | imm8", "hex_opcode": "0xFD000000", "visual_parts": [{"raw": "1111110", "clean": "1111110"}, {"raw": "P", "clean": "P"}, {"raw": "U", "clean": "U"}, {"raw": "N", "clean": "N"}, {"raw": "W", "clean": "W"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "CRd", "clean": "CRd"}, {"raw": "coproc", "clean": "coproc"}, {"raw": "imm8", "clean": "imm8"}]}, "operands": [{"name": "coproc", "desc": "CP Num"}, {"name": "CRd", "desc": "Destination coprocessor register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}], "extension": "A32 (System)", "description": "Stores coprocessor data to memory using an extension encoding (STC2 variant). The instruction computes an address from base register Rn and an offset (imm8 scaled by 4), and writes coprocessor register CRd to that memory location. The P, U, N, W bits control pre/post-indexing, up/down offset direction, narrow/wide transfer, and write-back. Condition flags are not affected.", "example": "STC2 p15, c0, [r1, #+/-#16]!", "pseudocode": "if ConditionPassed() then\n address ← ComputeAddress(Rn, imm8, P, U, W)\n memory[address] ← CP[coproc, CRd]\n if W == 1 then Rn ← address"} {"mnemonic": "rrx", "architecture": "ARMv8-A", "full_name": "Rotate Right with Extend (A32)", "summary": "Shifts register right by 1, inserting Carry flag into MSB.", "syntax": "RRX{S} , ", "encoding": {"format": "Data Proc", "binary_pattern": "cond | 00011 | 01 | 0 | 0000 | Rd | 00000 | 11 | 0 | Rm", "hex_opcode": "0x01A00060", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00011", "clean": "00011"}, {"raw": "01", "clean": "01"}, {"raw": "0", "clean": "0"}, {"raw": "0000", "clean": "0000"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "00000", "clean": "00000"}, {"raw": "11", "clean": "11"}, {"raw": "0", "clean": "0"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:7 | 6:5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (Base)", "description": "A32 Rotate Right with Extend by 1: Rd ← (C : Rm)[32:1], where the Carry flag is shifted into the MSB and the LSB is shifted out to C. If the S suffix is present, N and Z are updated from the result, and C is updated from the shifted-out bit; V is unaffected. Execution state: A32 only.", "example": "RRX r0, r2", "pseudocode": "shifted_result ← (C : Rm)[32:1]\nRd ← shifted_result\nif S then\n N ← shifted_result[31]\n Z ← (shifted_result == 0)\n C ← Rm[0]"} {"mnemonic": "rrx", "architecture": "ARMv8-A", "full_name": "Rotate Right with Extend (Thumb)", "summary": "Thumb-2 32-bit Rotate Right with Extend.", "syntax": "RRX{S}.W , ", "encoding": {"format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 0010 | 0 | 1111 | 0 | 000 | Rd | 00 | 11 | Rm", "hex_opcode": "0xEA4F0030", "visual_parts": [{"raw": "1110101", "clean": "1110101"}, {"raw": "0010", "clean": "0010"}, {"raw": "0", "clean": "0"}, {"raw": "1111", "clean": "1111"}, {"raw": "0", "clean": "0"}, {"raw": "000", "clean": "000"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "00", "clean": "00"}, {"raw": "11", "clean": "11"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "T32 (Thumb2)", "description": "Thumb-2 32-bit Rotate Right with Extend by 1: Rd ← (C : Rm)[32:1], where the Carry flag is rotated into the MSB and the LSB is shifted out to C. If the S suffix is present, N and Z are updated from the result, and C is updated from the shifted-out bit; V is unaffected. Execution state: T32 only.", "example": "RRX.W r0, r2", "pseudocode": "shifted_result ← (C : Rm)[32:1]\nRd ← shifted_result\nif S then\n N ← shifted_result[31]\n Z ← (shifted_result == 0)\n C ← Rm[0]"} {"mnemonic": "b.w", "architecture": "ARMv8-A", "full_name": "Branch (Wide)", "summary": "Thumb-2 32-bit Unconditional Branch (large range).", "syntax": "B.W
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 0111 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2000710", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "U", "clean": "U"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0111", "clean": "0111"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Dest/Acc"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "NEON Vector Absolute Difference and Accumulate: computes the absolute difference between corresponding elements in Qn and Qm, then adds the results to the corresponding elements in Qd (accumulation). The data type (dt) determined by sz (8, 16, 32 bits) specifies element width. NEON flags (FPSCR) are not modified; no general condition flags are affected.", "example": "VABA.dt q0, q1, q2", "pseudocode": "for i = 0 to num_elements(Qd, dt) - 1\n diff ← abs(Qn[i] - Qm[i])\n Qd[i] ← Qd[i] + diff"} {"mnemonic": "vabd", "architecture": "ARMv8-A", "full_name": "Vector Absolute Difference", "summary": "Computes absolute difference between elements.", "syntax": "VABD.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 0111 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2000700", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "U", "clean": "U"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0111", "clean": "0111"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "NEON Vector Absolute Difference: computes the absolute difference between corresponding elements in Qn and Qm and stores results in Qd. The data type (dt) determined by sz specifies element width (8, 16, or 32 bits). NEON flags are not modified; no general condition flags are affected.", "example": "VABD.dt q0, q1, q2", "pseudocode": "for i = 0 to num_elements(Qd, dt) - 1\n Qd[i] ← abs(Qn[i] - Qm[i])"} {"mnemonic": "vabs", "architecture": "ARMv8-A", "full_name": "Vector Absolute Value", "summary": "Calculates absolute value of integer/float elements.", "syntax": "VABS.
, ", "encoding": {"format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 01 | Vd | 0 | F | 110 | 0 | M | 0 | Vm", "hex_opcode": "0xF3B10300", "visual_parts": [{"raw": "111100111", "clean": "111100111"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "size", "clean": "size"}, {"raw": "01", "clean": "01"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0", "clean": "0"}, {"raw": "F", "clean": "F"}, {"raw": "110", "clean": "110"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10 | 9:7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "NEON Vector Absolute Value: computes the absolute value of each element in Qm and stores the result in Qd. Supports integer (8, 16, 32 bits) and floating-point (32 bits) data types as specified by sz. NEON flags are not modified; no general condition flags are affected.", "example": "VABS.dt q0, q2", "pseudocode": "for i = 0 to num_elements(Qd, dt) - 1\n Qd[i] ← abs(Qm[i])"} {"mnemonic": "vadd", "architecture": "ARMv8-A", "full_name": "Vector Add (Integer)", "summary": "Adds integer elements of two vectors.", "syntax": "VADD.I , , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 0 | D | size | Vn | Vd | 1000 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2000800", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1000", "clean": "1000"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Vector Add (Integer) performs element-wise addition of two NEON 128-bit registers, adding corresponding integer elements of size 8, 16, 32, or 64 bits. The instruction executes in Q-register (128-bit) mode and wraps on overflow without setting flags. This is a NEON SIMD instruction available in both A32 and T32 states when NEON is supported.", "example": "VADD.Isize q0, q1, q2", "pseudocode": "for each element i in Qd:\n Qd[i] ← Qn[i] + Qm[i]"} {"mnemonic": "vaddhn", "architecture": "ARMv8-A", "full_name": "Vector Add High Narrow", "summary": "Adds 2N-bit elements, selects high N-bits for result.", "syntax": "VADDHN.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 1 | D | size | Vn | Vd | 0100 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2800400", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0100", "clean": "0100"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Dd", "desc": "Dest Narrow"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Adds corresponding 2N-bit elements from two 128-bit NEON registers, then selects the high N bits of each result and stores them as N-bit elements in the destination 64-bit register. This instruction performs unsigned or signed addition at 2× the element width, then narrows the result. No flags are affected.", "example": "VADDHN.dt d0, q1, q2", "pseudocode": "for i = 0 to pairs-1\n Dd[i] ← (Qn[i] + Qm[i])[2*N-1:N]"} {"mnemonic": "vaddl", "architecture": "ARMv8-A", "full_name": "Vector Add Long", "summary": "Adds N-bit elements, producing 2N-bit results.", "syntax": "VADDL.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 1 | D | size | Vn | Vd | 000 | 0 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2800000", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "U", "clean": "U"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "000", "clean": "000"}, {"raw": "0", "clean": "0"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:9 | 8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Dest Wide"}, {"name": "Dn", "desc": "First source 64-bit SIMD/FP register"}, {"name": "Dm", "desc": "Second source 64-bit SIMD/FP register"}], "extension": "NEON (SIMD)", "description": "Adds corresponding N-bit elements from two 64-bit NEON registers and produces 2N-bit results stored in a 128-bit register. This instruction performs widening addition, doubling the element width and producing twice as many result bits. No flags are affected.", "example": "VADDL.dt q0, d1, d2", "pseudocode": "for i = 0 to pairs-1\n Qd[i] ← Dn[i] + Dm[i]"} {"mnemonic": "vaddw", "architecture": "ARMv8-A", "full_name": "Vector Add Wide", "summary": "Adds N-bit vector to 2N-bit vector.", "syntax": "VADDW.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 1 | D | size | Vn | Vd | 000 | 1 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2800100", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "U", "clean": "U"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "000", "clean": "000"}, {"raw": "1", "clean": "1"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:9 | 8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Dest Wide"}, {"name": "Qn", "desc": "Src Wide"}, {"name": "Dm", "desc": "Src Narrow"}], "extension": "NEON (SIMD)", "description": "Adds a 64-bit vector of N-bit elements to a 128-bit vector of 2N-bit elements, with the narrow operand implicitly widened before addition. The result is stored in the 128-bit destination. This instruction combines widening and addition in a single operation. No flags are affected.", "example": "VADDW.dt q0, q1, d2", "pseudocode": "for i = 0 to pairs-1\n Qd[i] ← Qn[i] + widen(Dm[i])"} {"mnemonic": "vand", "architecture": "ARMv8-A", "full_name": "Vector Bitwise AND", "summary": "Bitwise AND of two vectors.", "syntax": "VAND , , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 0 | D | 00 | Vn | Vd | 0001 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2000110", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "00", "clean": "00"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0001", "clean": "0001"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Performs bitwise AND on corresponding bits of two 128-bit NEON registers and stores the result in the destination register. This instruction is data-type agnostic and operates on the bit patterns directly. No flags are affected.", "example": "VAND q0, q1, q2", "pseudocode": "Qd ← Qn AND Qm"} {"mnemonic": "vbic", "architecture": "ARMv8-A", "full_name": "Vector Bitwise Bit Clear", "summary": "ANDs Vd with NOT of Vm (Vd & ~Vm).", "syntax": "VBIC , , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 0 | D | 01 | Vn | Vd | 0001 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2100110", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "01", "clean": "01"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0001", "clean": "0001"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Performs bitwise AND of the first operand with the bitwise NOT of the second operand (Qd ← Qn AND NOT Qm), storing the result in the destination register. This clears bits in Qn where the corresponding bits in Qm are set. No flags are affected.", "example": "VBIC q0, q1, q2", "pseudocode": "Qd ← Qn AND (NOT Qm)"} {"mnemonic": "vbif", "architecture": "ARMv8-A", "full_name": "Vector Bit Insert False", "summary": "Inserts bits from Vm into Vd where Vn (mask) is 0.", "syntax": "VBIF , , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | 1 | 0 | D | 11 | Vn | Vd | 0001 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF3300110", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0001", "clean": "0001"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}, {"name": "Qn", "desc": "Mask"}], "extension": "NEON (SIMD)", "description": "Selectively inserts bits from Qm into Qd where the corresponding bits in Qn (the mask) are 0. Where mask bits are 1, the original Qd bits are retained. This is a masked insert operation. No flags are affected.", "example": "VBIF q0, q2, q1", "pseudocode": "for i = 0 to 127\n if Qn[i] == 0 then Qd[i] ← Qm[i]"} {"mnemonic": "vbit", "architecture": "ARMv8-A", "full_name": "Vector Bit Insert True", "summary": "Inserts bits from Vm into Vd where Vn (mask) is 1.", "syntax": "VBIT , , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | 1 | 0 | D | 10 | Vn | Vd | 0001 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF3200110", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "10", "clean": "10"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0001", "clean": "0001"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}, {"name": "Qn", "desc": "Mask"}], "extension": "NEON (SIMD)", "description": "Selectively inserts bits from Qm into Qd where the corresponding bits in Qn (the mask) are 1. Where mask bits are 0, the original Qd bits are retained. This is the complement of VBIF. No flags are affected.", "example": "VBIT q0, q2, q1", "pseudocode": "for i = 0 to 127\n if Qn[i] == 1 then Qd[i] ← Qm[i]"} {"mnemonic": "vbsl", "architecture": "ARMv8-A", "full_name": "Vector Bit Select", "summary": "Selects bits from Vn or Vm based on Vd (mask).", "syntax": "VBSL , , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | 1 | 0 | D | 01 | Vn | Vd | 0001 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF3100110", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "01", "clean": "01"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0001", "clean": "0001"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Dest/Mask"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Performs a bit-select operation using Qd as the mask: selects bits from Qn where Qd bits are 1 and from Qm where Qd bits are 0. The result is stored in Qd. This implements the operation Qd ← (Qd AND Qn) OR (NOT Qd AND Qm). No flags are affected.", "example": "VBSL q0, q1, q2", "pseudocode": "for i = 0 to 127\n if Qd[i] == 1 then Qd[i] ← Qn[i] else Qd[i] ← Qm[i]"} {"mnemonic": "vceq", "architecture": "ARMv8-A", "full_name": "Vector Compare Equal", "summary": "Sets destination bits to all 1s if elements equal, else 0s.", "syntax": "VCEQ.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | 1 | 0 | D | size | Vn | Vd | 1000 | N | 1 | M | 1 | Vm", "hex_opcode": "0xF3000850", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1000", "clean": "1000"}, {"raw": "N", "clean": "N"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Vector Compare Equal performs element-wise equality comparison on 128-bit SIMD registers. For each element in Qn and Qm, if they are equal, the corresponding element in Qd is set to all 1s; otherwise, it is set to all 0s. No condition flags are affected. This is a NEON instruction available in both A32 and T32 states.", "example": "VCEQ.dt q0, q1, q2", "pseudocode": "for i = 0 to (128 / element_size) - 1 do\n if Qn[i] == Qm[i] then\n Qd[i] ← all_ones\n else\n Qd[i] ← all_zeros\n end if\nend for"} {"mnemonic": "vcge", "architecture": "ARMv8-A", "full_name": "Vector Compare Greater Than or Equal", "summary": "Compares elements (>=) and sets result mask.", "syntax": "VCGE.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 0011 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2000310", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "U", "clean": "U"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0011", "clean": "0011"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Vector Compare Greater Than or Equal performs signed element-wise comparison on 128-bit SIMD registers. For each element in Qn, if it is greater than or equal to the corresponding element in Qm, the result element in Qd is set to all 1s; otherwise, it is set to all 0s. No condition flags are affected. This is a NEON instruction available in both A32 and T32 states.", "example": "VCGE.dt q0, q1, q2", "pseudocode": "for i = 0 to (128 / element_size) - 1 do\n if Qn[i] >= Qm[i] then\n Qd[i] ← all_ones\n else\n Qd[i] ← all_zeros\n end if\nend for"} {"mnemonic": "vcgt", "architecture": "ARMv8-A", "full_name": "Vector Compare Greater Than", "summary": "Compares elements (>) and sets result mask.", "syntax": "VCGT.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 0011 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2000300", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "U", "clean": "U"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0011", "clean": "0011"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Vector Compare Greater Than performs signed element-wise comparison on 128-bit SIMD registers. For each element in Qn, if it is strictly greater than the corresponding element in Qm, the result element in Qd is set to all 1s; otherwise, it is set to all 0s. No condition flags are affected. This is a NEON instruction available in both A32 and T32 states.", "example": "VCGT.dt q0, q1, q2", "pseudocode": "for i = 0 to (128 / element_size) - 1 do\n if Qn[i] > Qm[i] then\n Qd[i] ← all_ones\n else\n Qd[i] ← all_zeros\n end if\nend for"} {"mnemonic": "vcle", "architecture": "ARMv8-A", "full_name": "Vector Compare Less Than or Equal", "summary": "Compares elements (<=). Alias for VCGE with swapped operands.", "syntax": "VCLE.
, , ", "encoding": {"format": "NEON Alias", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 0011 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2000310", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "U", "clean": "U"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0011", "clean": "0011"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Vector Compare Less Than or Equal is an alias that performs signed element-wise comparison on 128-bit SIMD registers with operands swapped relative to VCGE. For each element in Qn, if it is less than or equal to the corresponding element in Qm, the result element in Qd is set to all 1s; otherwise, it is set to all 0s. No condition flags are affected. This is a NEON instruction available in both A32 and T32 states.", "example": "VCLE.dt q0, q1, q2", "pseudocode": "for i = 0 to (128 / element_size) - 1 do\n if Qn[i] <= Qm[i] then\n Qd[i] ← all_ones\n else\n Qd[i] ← all_zeros\n end if\nend for"} {"mnemonic": "vclt", "architecture": "ARMv8-A", "full_name": "Vector Compare Less Than", "summary": "Compares elements (<). Alias for VCGT with swapped operands.", "syntax": "VCLT.
, , ", "encoding": {"format": "NEON Alias", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 0011 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2000300", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "U", "clean": "U"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0011", "clean": "0011"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Vector Compare Less Than is an alias that performs signed element-wise comparison on 128-bit SIMD registers with operands swapped relative to VCGT. For each element in Qn, if it is strictly less than the corresponding element in Qm, the result element in Qd is set to all 1s; otherwise, it is set to all 0s. No condition flags are affected. This is a NEON instruction available in both A32 and T32 states.", "example": "VCLT.dt q0, q1, q2", "pseudocode": "for i = 0 to (128 / element_size) - 1 do\n if Qn[i] < Qm[i] then\n Qd[i] ← all_ones\n else\n Qd[i] ← all_zeros\n end if\nend for"} {"mnemonic": "vcls", "architecture": "ARMv8-A", "full_name": "Vector Count Leading Sign Bits", "summary": "Counts number of consecutive sign bits.", "syntax": "VCLS.
, ", "encoding": {"format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 00 | Vd | 0 | 1000 | 1 | M | 0 | Vm", "hex_opcode": "0xF3B00440", "visual_parts": [{"raw": "111100111", "clean": "111100111"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "size", "clean": "size"}, {"raw": "00", "clean": "00"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0", "clean": "0"}, {"raw": "1000", "clean": "1000"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Vector Count Leading Sign Bits counts the number of consecutive sign bits (bits matching the sign bit) in each element of the source register. For each integer element in Qm, the result in Qd is the count of leading sign bits. The data type determines element size (8, 16, or 32 bits). No condition flags are affected. This is a NEON instruction available in both A32 and T32 states.", "example": "VCLS.dt q0, q2", "pseudocode": "for i = 0 to (128 / element_size) - 1 do\n sign_bit ← Qm[i] >> (element_size - 1)\n count ← 0\n for j = element_size - 2 downto 0 do\n if (Qm[i] >> j) & 1 == sign_bit then\n count ← count + 1\n else\n break\n end if\n end for\n Qd[i] ← count\nend for"} {"mnemonic": "vclz", "architecture": "ARMv8-A", "full_name": "Vector Count Leading Zeros", "summary": "Counts number of consecutive zeros.", "syntax": "VCLZ.
, ", "encoding": {"format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 00 | Vd | 0 | 1001 | 1 | M | 0 | Vm", "hex_opcode": "0xF3B004C0", "visual_parts": [{"raw": "111100111", "clean": "111100111"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "size", "clean": "size"}, {"raw": "00", "clean": "00"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0", "clean": "0"}, {"raw": "1001", "clean": "1001"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Vector Count Leading Zeros counts the number of consecutive zero bits from the most significant bit in each element of the source register. For each integer element in Qm, the result in Qd is the count of leading zeros. The data type determines element size (8, 16, or 32 bits). No condition flags are affected. This is a NEON instruction available in both A32 and T32 states.", "example": "VCLZ.dt q0, q2", "pseudocode": "for i = 0 to (128 / element_size) - 1 do\n count ← 0\n for j = element_size - 1 downto 0 do\n if (Qm[i] >> j) & 1 == 0 then\n count ← count + 1\n else\n break\n end if\n end for\n Qd[i] ← count\nend for"} {"mnemonic": "vcnt", "architecture": "ARMv8-A", "full_name": "Vector Count Set Bits", "summary": "Population count (number of 1s) per byte.", "syntax": "VCNT.8 , ", "encoding": {"format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 00 | Vd | 0 | 1010 | 0 | M | 0 | Vm", "hex_opcode": "0xF3B00500", "visual_parts": [{"raw": "111100111", "clean": "111100111"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "size", "clean": "size"}, {"raw": "00", "clean": "00"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0", "clean": "0"}, {"raw": "1010", "clean": "1010"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Vector Count Set Bits (population count) counts the number of set (1) bits in each 8-bit element of the source register. For each byte element in Qm, the result in Qd is the count of set bits within that byte. The data type is always .8 (8-bit elements). No condition flags are affected. This is a NEON instruction available in both A32 and T32 states.", "example": "VCNT.8 q0, q2", "pseudocode": "for i = 0 to 15 do\n count ← 0\n for j = 0 to 7 do\n if (Qm[8*i + j] & (1 << j)) != 0 then\n count ← count + 1\n end if\n end for\n Qd[8*i..8*i+7] ← count\nend for"} {"mnemonic": "vdup", "architecture": "ARMv8-A", "full_name": "Vector Duplicate (Scalar)", "summary": "Duplicates a scalar value to all lanes of a vector.", "syntax": "VDUP.
, ", "encoding": {"format": "NEON Scalar", "binary_pattern": "111100111 | D | 11 | imm4 | Vd | 11 | 000 | 0 | M | 0 | Vm", "hex_opcode": "0xF3B00C00", "visual_parts": [{"raw": "111100111", "clean": "111100111"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "imm4", "clean": "imm4"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "11", "clean": "11"}, {"raw": "000", "clean": "000"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Dm[x]", "desc": "Scalar"}], "extension": "NEON (SIMD)", "description": "Duplicates a scalar value from a lane of a NEON register to all lanes of a destination vector. The scalar is extracted from the indexed lane of Dm based on the element size, then broadcast to fill all lanes of Qd. No condition flags are affected. This is an ARMv7 Advanced SIMD (NEON) instruction, executable in both A32 and T32 states.", "example": "VDUP.dt q0, Dm[x]", "pseudocode": "lane_index ← imm4\nelement_size ← dt_in_bits\nscalar_value ← Dm[lane_index]\nfor i = 0 to (128 / element_size - 1)\n Qd[i] ← scalar_value"} {"mnemonic": "veor", "architecture": "ARMv8-A", "full_name": "Vector Exclusive OR", "summary": "Bitwise XOR of two vectors.", "syntax": "VEOR , , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | 1 | 0 | D | 00 | Vn | Vd | 0001 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF3000110", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "00", "clean": "00"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0001", "clean": "0001"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Performs a bitwise exclusive OR (XOR) of corresponding lanes in two 128-bit NEON vectors and stores the result in the destination. Each lane of Qn is XORed with the corresponding lane of Qm, producing Qd. No condition flags are affected. This is an ARMv7 Advanced SIMD instruction, executable in both A32 and T32 states.", "example": "VEOR q0, q1, q2", "pseudocode": "for i = 0 to 127\n Qd[i] ← Qn[i] XOR Qm[i]"} {"mnemonic": "vext", "architecture": "ARMv8-A", "full_name": "Vector Extract", "summary": "Extracts a new vector from a pair of vectors (Sliding window).", "syntax": "VEXT.8 , , , #", "encoding": {"format": "NEON Extract", "binary_pattern": "111100101 | D | 11 | Vn | Vd | imm4 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2B00000", "visual_parts": [{"raw": "111100101", "clean": "111100101"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "imm4", "clean": "imm4"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "Low Src"}, {"name": "Qm", "desc": "High Src"}, {"name": "imm", "desc": "Byte Offset"}], "extension": "NEON (SIMD)", "description": "Extracts a contiguous sequence of bytes from the concatenation of two 128-bit NEON vectors and stores the result in the destination. The vectors Qn and Qm are logically concatenated, then bytes [imm:imm+15] are extracted to form Qd. All operations are on 8-bit granularity. No condition flags are affected. This is an ARMv7 Advanced SIMD instruction, executable in both A32 and T32 states.", "example": "VEXT.8 q0, q1, q2, #16", "pseudocode": "combined ← (Qn << (imm * 8)) | (Qm >> ((16 - imm) * 8))\nQd ← combined[127:0]\nfor i = 0 to 15\n Qd[8*i+7:8*i] ← (Qn || Qm)[8*(imm+i)+7:8*(imm+i)]"} {"mnemonic": "vhadd", "architecture": "ARMv8-A", "full_name": "Vector Halving Add", "summary": "Add elements and shift right by 1 (Average).", "syntax": "VHADD.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 00 | 0 | 0 | N | 1 | M | 0 | Vm", "hex_opcode": "0xF2000040", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "U", "clean": "U"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "00", "clean": "00"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "N", "clean": "N"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Adds corresponding elements of two 128-bit NEON vectors and right-shifts the result by 1 bit (rounded toward zero), effectively computing the average. The operation is performed element-wise according to the data type. No condition flags are affected. This is an ARMv7 Advanced SIMD instruction, executable in both A32 and T32 states.", "example": "VHADD.dt q0, q1, q2", "pseudocode": "for each lane i of size specified by dt\n sum ← Qn[i] + Qm[i]\n Qd[i] ← sum >> 1"} {"mnemonic": "vhsub", "architecture": "ARMv8-A", "full_name": "Vector Halving Subtract", "summary": "Subtract elements and shift right by 1.", "syntax": "VHSUB.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 00 | 1 | 0 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2000200", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "U", "clean": "U"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Subtracts corresponding elements of two 128-bit NEON vectors and right-shifts the result by 1 bit (rounded toward zero). The operation is performed element-wise according to the data type. No condition flags are affected. This is an ARMv7 Advanced SIMD instruction, executable in both A32 and T32 states.", "example": "VHSUB.dt q0, q1, q2", "pseudocode": "for each lane i of size specified by dt\n diff ← Qn[i] - Qm[i]\n Qd[i] ← diff >> 1"} {"mnemonic": "vld1", "architecture": "ARMv8-A", "full_name": "Vector Load Multiple (Single Element)", "summary": "Loads vector data from memory (interleaved or sequential).", "syntax": "VLD1. , []{!}", "encoding": {"format": "NEON Load", "binary_pattern": "111101001 | D | 1 | 0 | Rn | Vd | 00 | 00 | index_align | 1101", "hex_opcode": "0xF4A0000D", "visual_parts": [{"raw": "111101001", "clean": "111101001"}, {"raw": "D", "clean": "D"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "00", "clean": "00"}, {"raw": "00", "clean": "00"}, {"raw": "index_align", "clean": "index_align"}, {"raw": "1101", "clean": "1101"}], "bit_positions": "31:23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:10 | 9:8 | 7:4 | 3:0"}, "operands": [{"name": "list", "desc": "Dest Registers"}, {"name": "Rn", "desc": "First source / base general-purpose register"}], "extension": "NEON (SIMD)", "description": "Loads one or more NEON vectors from memory at an address specified by a general-purpose register, with optional post-index update. The instruction supports contiguous or strided loading patterns depending on the type field. No condition flags are affected. This is an ARMv7 Advanced SIMD memory instruction, executable in both A32 and T32 states.", "example": "VLD1.size {r0-r3}, [r1]!", "pseudocode": "address ← Rn\nfor each register in list\n load vector from address\n address ← address + stride\nif writeback\n Rn ← Rn + total_bytes_loaded"} {"mnemonic": "vld2", "architecture": "ARMv8-A", "full_name": "Vector Load Multiple (2-Element Structure)", "summary": "De-interleaves 2 streams of data while loading.", "syntax": "VLD2. , []{!}", "encoding": {"format": "NEON Load", "binary_pattern": "111101001 | D | 1 | 0 | Rn | Vd | 00 | 01 | index_align | 1101", "hex_opcode": "0xF4A0010D", "visual_parts": [{"raw": "111101001", "clean": "111101001"}, {"raw": "D", "clean": "D"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "00", "clean": "00"}, {"raw": "01", "clean": "01"}, {"raw": "index_align", "clean": "index_align"}, {"raw": "1101", "clean": "1101"}], "bit_positions": "31:23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:10 | 9:8 | 7:4 | 3:0"}, "operands": [{"name": "list", "desc": "Dest Registers"}, {"name": "Rn", "desc": "First source / base general-purpose register"}], "extension": "NEON (SIMD)", "description": "Loads two streams of interleaved data from memory and de-interleaves them into separate 128-bit NEON vectors. The instruction handles 2-element structures, reading from memory and distributing elements to the destination registers in a de-interleaved pattern. No condition flags are affected. This is an ARMv7 Advanced SIMD memory instruction, executable in both A32 and T32 states.", "example": "VLD2.size {r0-r3}, [r1]!", "pseudocode": "address ← Rn\nfor each 2-element structure at address\n element0 ← memory[address]\n element1 ← memory[address + size_bytes]\n store element0 in first destination register\n store element1 in second destination register\n address ← address + 2 * size_bytes\nif writeback\n Rn ← Rn + total_bytes_loaded"} {"mnemonic": "vmax", "architecture": "ARMv8-A", "full_name": "Vector Maximum", "summary": "Selects maximum value from elements.", "syntax": "VMAX.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 0110 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2000600", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "U", "clean": "U"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0110", "clean": "0110"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Compares corresponding lanes of two 128-bit NEON vectors and stores the maximum value in each lane of the destination. The comparison is performed element-wise according to the data type (signed or unsigned integer). No condition flags are affected. This is an ARMv7 Advanced SIMD instruction, executable in both A32 and T32 states.", "example": "VMAX.dt q0, q1, q2", "pseudocode": "for each lane i of size specified by dt\n if Qn[i] > Qm[i]\n Qd[i] ← Qn[i]\n else\n Qd[i] ← Qm[i]"} {"mnemonic": "vmin", "architecture": "ARMv8-A", "full_name": "Vector Minimum", "summary": "Selects minimum value from elements.", "syntax": "VMIN.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 0110 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2000610", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "U", "clean": "U"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0110", "clean": "0110"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Performs element-wise minimum operation on two 128-bit SIMD registers, selecting the smaller value from each corresponding pair of elements. The data type (sz field) determines whether elements are 32-bit or 16-bit integers. Condition flags N, Z, C, V are unaffected. This is an A32/T32 NEON instruction with no privilege restrictions.", "example": "VMIN.dt q0, q1, q2", "pseudocode": "for i = 0 to (128 / element_width) - 1:\n Qd[i] ← min(Qn[i], Qm[i])"} {"mnemonic": "vmla", "architecture": "ARMv8-A", "full_name": "Vector Multiply Accumulate", "summary": "Multiplies and adds to accumulator.", "syntax": "VMLA.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 0 | D | size | Vn | Vd | 1001 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2000900", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1001", "clean": "1001"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Dest/Acc"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Multiplies corresponding elements from two source registers and accumulates (adds) the products into the destination register. Performs Qd ← Qd + (Qn × Qm) for each element. The sz field specifies 16-bit or 32-bit element width. Condition flags are unaffected. This is an A32/T32 NEON instruction with no privilege restrictions.", "example": "VMLA.dt q0, q1, q2", "pseudocode": "for i = 0 to (128 / element_width) - 1:\n product ← Qn[i] × Qm[i]\n Qd[i] ← Qd[i] + product"} {"mnemonic": "vmls", "architecture": "ARMv8-A", "full_name": "Vector Multiply Subtract", "summary": "Multiplies and subtracts from accumulator.", "syntax": "VMLS.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 0 | D | 1 | sz | Vn | Vd | 1101 | N | 1 | M | 1 | Vm", "hex_opcode": "0xF2200D50", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "1", "clean": "1"}, {"raw": "sz", "clean": "sz"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1101", "clean": "1101"}, {"raw": "N", "clean": "N"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Dest/Acc"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Multiplies corresponding elements from two source registers and subtracts the products from the accumulator. Performs Qd ← Qd - (Qn × Qm) for each element. The sz field specifies 16-bit or 32-bit element width. Condition flags are unaffected. This is an A32/T32 NEON instruction with no privilege restrictions.", "example": "VMLS.dt q0, q1, q2", "pseudocode": "for i = 0 to (128 / element_width) - 1:\n product ← Qn[i] × Qm[i]\n Qd[i] ← Qd[i] - product"} {"mnemonic": "vmov", "architecture": "ARMv8-A", "full_name": "Vector Move (Immediate)", "summary": "Moves immediate value into vector.", "syntax": "VMOV.
, #", "encoding": {"format": "NEON Imm", "binary_pattern": "1111001 | i | 1 | D | 000 | imm3 | Vd | cmode | 0 | 0 | 0 | 1 | imm4", "hex_opcode": "0xF2800010", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "i", "clean": "i"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "000", "clean": "000"}, {"raw": "imm3", "clean": "imm3"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "cmode", "clean": "cmode"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "imm4", "clean": "imm4"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:19 | 18:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "imm", "desc": "Value"}], "extension": "NEON (SIMD)", "description": "Vector Move (Immediate) moves an immediate value into all elements of a 128-bit NEON register. The immediate is replicated across elements according to the data type (8, 16, 32, or 64 bits) and element expansion mode (cmode). No flags are affected. This is a NEON instruction available in both A32 and T32 states when NEON is supported.", "example": "VMOV.dt q0, #16", "pseudocode": "imm_expanded ← ExpandImmediate(imm, cmode)\nfor each element i in Qd:\n Qd[i] ← imm_expanded"} {"mnemonic": "vmovl", "architecture": "ARMv8-A", "full_name": "Vector Move Long", "summary": "Copies N-bit elements to 2N-bit elements (Widening).", "syntax": "VMOVL.
, ", "encoding": {"format": "NEON 2-Reg", "binary_pattern": "1111001 | U | 1 | D | imm3H | 000 | Vd | 1010 | 0 | 0 | M | 1 | Vm", "hex_opcode": "0xF2800A10", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "U", "clean": "U"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "imm3H", "clean": "imm3H"}, {"raw": "000", "clean": "000"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1010", "clean": "1010"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:19 | 18:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Dest Wide"}, {"name": "Dm", "desc": "Src Narrow"}], "extension": "NEON (SIMD)", "description": "Widens N-bit elements from a 64-bit source register to 2N-bit elements in a 128-bit destination register, with zero or sign extension based on the data type. The Q field and element size encoding determine which half of the source to use and the widening operation. Condition flags are unaffected. This is an A32/T32 NEON instruction with no privilege restrictions.", "example": "VMOVL.dt q0, d2", "pseudocode": "for i = 0 to (64 / source_element_width) - 1:\n Qd[i] ← ZeroExtend(Dm[i]) or SignExtend(Dm[i])"} {"mnemonic": "vmovn", "architecture": "ARMv8-A", "full_name": "Vector Move Narrow", "summary": "Copies 2N-bit elements to N-bit elements (Narrowing).", "syntax": "VMOVN.
, ", "encoding": {"format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 10 | Vd | 0 | 0100 | 0 | M | 0 | Vm", "hex_opcode": "0xF3B20200", "visual_parts": [{"raw": "111100111", "clean": "111100111"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "size", "clean": "size"}, {"raw": "10", "clean": "10"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0", "clean": "0"}, {"raw": "0100", "clean": "0100"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Dd", "desc": "Dest Narrow"}, {"name": "Qm", "desc": "Src Wide"}], "extension": "NEON (SIMD)", "description": "Narrows 2N-bit elements from a 128-bit source register to N-bit elements in a 64-bit destination register, discarding the upper bits. The sz field determines the source element size (16, 32, or 64 bits) and corresponding destination size. Condition flags are unaffected. This is an A32/T32 NEON instruction with no privilege restrictions.", "example": "VMOVN.dt d0, q2", "pseudocode": "for i = 0 to (128 / source_element_width) - 1:\n Dd[i] ← Qm[i][destination_element_width-1:0]"} {"mnemonic": "vmul", "architecture": "ARMv8-A", "full_name": "Vector Multiply", "summary": "Multiplies elements.", "syntax": "VMUL.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | op | 0 | D | size | Vn | Vd | 1001 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2000910", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "op", "clean": "op"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1001", "clean": "1001"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Performs element-wise multiplication of two 128-bit SIMD registers, storing results in the destination. The sz field determines 16-bit or 32-bit element width. Condition flags N, Z, C, V are unaffected. This is an A32/T32 NEON instruction with no privilege restrictions.", "example": "VMUL.dt q0, q1, q2", "pseudocode": "for i = 0 to (128 / element_width) - 1:\n Qd[i] ← Qn[i] × Qm[i]"} {"mnemonic": "vmull", "architecture": "ARMv8-A", "full_name": "Vector Multiply Long", "summary": "Multiplies N-bit elements producing 2N-bit results.", "syntax": "VMULL.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 1 | D | size | Vn | Vd | 11 | op | 0 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2800C00", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "U", "clean": "U"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "11", "clean": "11"}, {"raw": "op", "clean": "op"}, {"raw": "0", "clean": "0"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Dest Wide"}, {"name": "Dn", "desc": "First source 64-bit SIMD/FP register"}, {"name": "Dm", "desc": "Second source 64-bit SIMD/FP register"}], "extension": "NEON (SIMD)", "description": "Multiplies N-bit elements from two 64-bit source registers to produce 2N-bit results in a 128-bit destination register. The sz field specifies 8, 16, or 32-bit source element width. Condition flags are unaffected. This is an A32/T32 NEON instruction with no privilege restrictions.", "example": "VMULL.dt q0, d1, d2", "pseudocode": "for i = 0 to (64 / source_element_width) - 1:\n Qd[i] ← Dn[i] × Dm[i]"} {"mnemonic": "vmvn", "architecture": "ARMv8-A", "full_name": "Vector Move NOT", "summary": "Moves bitwise inverse of immediate/register.", "syntax": "VMVN , ", "encoding": {"format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 00 | Vd | 0 | 1011 | 0 | M | 0 | Vm", "hex_opcode": "0xF3B00580", "visual_parts": [{"raw": "111100111", "clean": "111100111"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "size", "clean": "size"}, {"raw": "00", "clean": "00"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0", "clean": "0"}, {"raw": "1011", "clean": "1011"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Performs bitwise NOT (inversion) of all bits in a 128-bit SIMD register, storing the result in the destination. This is a data-type-independent operation that works on all bit patterns equally. Condition flags are unaffected. This is an A32/T32 NEON instruction with no privilege restrictions.", "example": "VMVN q0, q2", "pseudocode": "Qd ← ~Qm"} {"mnemonic": "vneg", "architecture": "ARMv8-A", "full_name": "Vector Negate", "summary": "Negates integer/float elements.", "syntax": "VNEG.
, ", "encoding": {"format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 01 | Vd | 0 | F | 111 | 0 | M | 0 | Vm", "hex_opcode": "0xF3B10380", "visual_parts": [{"raw": "111100111", "clean": "111100111"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "size", "clean": "size"}, {"raw": "01", "clean": "01"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0", "clean": "0"}, {"raw": "F", "clean": "F"}, {"raw": "111", "clean": "111"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10 | 9:7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Negates each element in the source vector and places the result in the destination register. For integer elements, the result is two's complement negation; for floating-point elements, only the sign bit is inverted. No condition flags are affected. Execution is available in both A32 and T32 instruction sets via NEON.", "example": "VNEG.dt q0, q2", "pseudocode": "for i = 0 to elements-1\n Qd[i] ← -Qm[i]"} {"mnemonic": "vorn", "architecture": "ARMv8-A", "full_name": "Vector OR NOT", "summary": "Bitwise OR with NOT (Vd = Vn | ~Vm).", "syntax": "VORN , , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 0 | D | 11 | Vn | Vd | 0001 | N | 1 | M | 1 | Vm", "hex_opcode": "0xF2300150", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0001", "clean": "0001"}, {"raw": "N", "clean": "N"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Performs bitwise OR of the first operand with the bitwise NOT of the second operand (Qd = Qn | ~Qm), element-wise. No condition flags are affected. Execution is available in both A32 and T32 instruction sets via NEON.", "example": "VORN q0, q1, q2", "pseudocode": "for i = 0 to 127\n Qd[i] ← Qn[i] | ~Qm[i]"} {"mnemonic": "vorr", "architecture": "ARMv8-A", "full_name": "Vector Logical OR", "summary": "Bitwise OR of two vectors.", "syntax": "VORR , , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 0 | D | 10 | Vn | Vd | 0001 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2200110", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "10", "clean": "10"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0001", "clean": "0001"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Performs bitwise OR of two vectors element-wise (Qd = Qn | Qm). No condition flags are affected. Execution is available in both A32 and T32 instruction sets via NEON.", "example": "VORR q0, q1, q2", "pseudocode": "for i = 0 to 127\n Qd[i] ← Qn[i] | Qm[i]"} {"mnemonic": "vpadd", "architecture": "ARMv8-A", "full_name": "Vector Pairwise Add", "summary": "Adds adjacent pairs of elements.", "syntax": "VPADD.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 0 | D | size | Vn | Vd | 1011 | N | Q | M | 1 | Vm", "hex_opcode": "0xF2000B10", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1011", "clean": "1011"}, {"raw": "N", "clean": "N"}, {"raw": "Q", "clean": "Q"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Dd", "desc": "Destination 64-bit SIMD/FP register"}, {"name": "Dn", "desc": "First source 64-bit SIMD/FP register"}, {"name": "Dm", "desc": "Second source 64-bit SIMD/FP register"}], "extension": "NEON (SIMD)", "description": "Adds adjacent pairs of elements from the source operands and places the results in the destination register, reducing dimensionality by half. For example, in 32-bit mode, pairs of adjacent 32-bit elements are summed to produce 4 results in the 64-bit destination. No condition flags are affected. Execution is available in both A32 and T32 instruction sets via NEON.", "example": "VPADD.dt d0, d1, d2", "pseudocode": "case dt of\n when I8: for i = 0 to 3: Dd[i] ← Dn[2*i] + Dn[2*i+1] + Dm[2*i] + Dm[2*i+1]\n when I16: for i = 0 to 1: Dd[i] ← Dn[2*i] + Dn[2*i+1] + Dm[2*i] + Dm[2*i+1]\n when I32: Dd[0] ← Dn[0] + Dn[1]; Dd[1] ← Dm[0] + Dm[1]\n when F32: Dd[0] ← Dn[0] + Dn[1]; Dd[1] ← Dm[0] + Dm[1]"} {"mnemonic": "vpmin", "architecture": "ARMv8-A", "full_name": "Vector Pairwise Minimum", "summary": "Minimum of adjacent pairs.", "syntax": "VPMIN.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 1010 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2000A10", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "U", "clean": "U"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1010", "clean": "1010"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Dd", "desc": "Destination 64-bit SIMD/FP register"}, {"name": "Dn", "desc": "First source 64-bit SIMD/FP register"}, {"name": "Dm", "desc": "Second source 64-bit SIMD/FP register"}], "extension": "NEON (SIMD)", "description": "Computes the minimum of adjacent pairs of elements from the source operands and places the results in the destination register, reducing dimensionality by half. For each pair, the smaller element is selected. No condition flags are affected. Execution is available in both A32 and T32 instruction sets via NEON.", "example": "VPMIN.dt d0, d1, d2", "pseudocode": "case dt of\n when I8: for i = 0 to 3: Dd[i] ← min(Dn[2*i], Dn[2*i+1], Dm[2*i], Dm[2*i+1])\n when I16: for i = 0 to 1: Dd[i] ← min(Dn[2*i], Dn[2*i+1], Dm[2*i], Dm[2*i+1])\n when I32: Dd[0] ← min(Dn[0], Dn[1]); Dd[1] ← min(Dm[0], Dm[1])\n when F32: Dd[0] ← min(Dn[0], Dn[1]); Dd[1] ← min(Dm[0], Dm[1])"} {"mnemonic": "vpmax", "architecture": "ARMv8-A", "full_name": "Vector Pairwise Maximum", "summary": "Maximum of adjacent pairs.", "syntax": "VPMAX.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 1010 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2000A00", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "U", "clean": "U"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1010", "clean": "1010"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Dd", "desc": "Destination 64-bit SIMD/FP register"}, {"name": "Dn", "desc": "First source 64-bit SIMD/FP register"}, {"name": "Dm", "desc": "Second source 64-bit SIMD/FP register"}], "extension": "NEON (SIMD)", "description": "Computes the maximum of adjacent pairs of elements from the source operands and places the results in the destination register, reducing dimensionality by half. For each pair, the larger element is selected. No condition flags are affected. Execution is available in both A32 and T32 instruction sets via NEON.", "example": "VPMAX.dt d0, d1, d2", "pseudocode": "case dt of\n when I8: for i = 0 to 3: Dd[i] ← max(Dn[2*i], Dn[2*i+1], Dm[2*i], Dm[2*i+1])\n when I16: for i = 0 to 1: Dd[i] ← max(Dn[2*i], Dn[2*i+1], Dm[2*i], Dm[2*i+1])\n when I32: Dd[0] ← max(Dn[0], Dn[1]); Dd[1] ← max(Dm[0], Dm[1])\n when F32: Dd[0] ← max(Dn[0], Dn[1]); Dd[1] ← max(Dm[0], Dm[1])"} {"mnemonic": "vqadd", "architecture": "ARMv8-A", "full_name": "Vector Saturating Add", "summary": "Adds elements with saturation.", "syntax": "VQADD.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 0000 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2000010", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "U", "clean": "U"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0000", "clean": "0000"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Adds corresponding elements from two vectors with saturation. If the result overflows or underflows, it is saturated to the data type's maximum or minimum representable value. No condition flags are affected; saturation status is not reflected in APSR. Execution is available in both A32 and T32 instruction sets via NEON.", "example": "VQADD.dt q0, q1, q2", "pseudocode": "for i = 0 to elements-1\n Qd[i] ← SatQ(Qn[i] + Qm[i], dt)"} {"mnemonic": "vqsub", "architecture": "ARMv8-A", "full_name": "Vector Saturating Subtract", "summary": "Subtracts elements with saturation.", "syntax": "VQSUB.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 0010 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2000210", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "U", "clean": "U"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0010", "clean": "0010"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Subtracts the second operand from the first with saturation. If the result overflows or underflows, it is saturated to the data type's maximum or minimum representable value. No condition flags are affected; saturation status is not reflected in APSR. Execution is available in both A32 and T32 instruction sets via NEON.", "example": "VQSUB.dt q0, q1, q2", "pseudocode": "for i = 0 to elements-1\n Qd[i] ← SatQ(Qn[i] - Qm[i], dt)"} {"mnemonic": "vrecpe", "architecture": "ARMv8-A", "full_name": "Vector Reciprocal Estimate", "summary": "Estimates reciprocal (1/x).", "syntax": "VRECPE.
, ", "encoding": {"format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 11 | Vd | 0 | 10 | F | 0 | 1 | M | 0 | Vm", "hex_opcode": "0xF3B30440", "visual_parts": [{"raw": "111100111", "clean": "111100111"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "size", "clean": "size"}, {"raw": "11", "clean": "11"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0", "clean": "0"}, {"raw": "10", "clean": "10"}, {"raw": "F", "clean": "F"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:9 | 8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Computes a vector reciprocal estimate (1/x) for each element in the source register and stores the result in the destination register. This is a Newton-Raphson reciprocal estimate; the result is not fully accurate and is intended as a starting point for iterative refinement. Condition flags (N, Z, C, V) are not affected. Executes in A32/T32 with NEON extension; requires FPEXC.EN = 1 for floating-point operation.", "example": "VRECPE.dt q0, q2", "pseudocode": "for i = 0 to 127 by element_size:\n element ← Vm[i+element_size-1:i]\n Qd[i+element_size-1:i] ← RecipEstimate(element)"} {"mnemonic": "vrsqrte", "architecture": "ARMv8-A", "full_name": "Vector Reciprocal Square Root Estimate", "summary": "Estimates reciprocal square root (1/sqrt(x)).", "syntax": "VRSQRTE.
, ", "encoding": {"format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 11 | Vd | 0 | 10 | F | 1 | 1 | M | 0 | Vm", "hex_opcode": "0xF3B304C0", "visual_parts": [{"raw": "111100111", "clean": "111100111"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "size", "clean": "size"}, {"raw": "11", "clean": "11"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0", "clean": "0"}, {"raw": "10", "clean": "10"}, {"raw": "F", "clean": "F"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:9 | 8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Computes a vector reciprocal square root estimate (1/√x) for each element in the source register and stores the result in the destination register. This is a Newton-Raphson reciprocal square root estimate; the result serves as a starting point for iterative refinement. Condition flags (N, Z, C, V) are not affected. Executes in A32/T32 with NEON extension; requires FPEXC.EN = 1 for floating-point operation.", "example": "VRSQRTE.dt q0, q2", "pseudocode": "for i = 0 to 127 by element_size:\n element ← Qm[i+element_size-1:i]\n Qd[i+element_size-1:i] ← RecipSqrtEstimate(element)"} {"mnemonic": "vrev16", "architecture": "ARMv8-A", "full_name": "Vector Reverse 16", "summary": "Reverses bytes within 16-bit halfwords.", "syntax": "VREV16.
, ", "encoding": {"format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 00 | Vd | 0 | 00 | 10 | 0 | M | 0 | Vm", "hex_opcode": "0xF3B00100", "visual_parts": [{"raw": "111100111", "clean": "111100111"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "size", "clean": "size"}, {"raw": "00", "clean": "00"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0", "clean": "0"}, {"raw": "00", "clean": "00"}, {"raw": "10", "clean": "10"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:9 | 8:7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Reverses the byte order within each 16-bit halfword element in the source register. For example, bytes [1,0] become [0,1] within each 16-bit element. Condition flags (N, Z, C, V) are not affected. Executes in A32/T32 with NEON extension; operates on integer data types.", "example": "VREV16.dt q0, q2", "pseudocode": "for i = 0 to 127 by 16:\n for j = 0 to 15 by 8:\n Qd[i+j+7:i+j] ← Qm[i+15-j:i+8-j]"} {"mnemonic": "vrev32", "architecture": "ARMv8-A", "full_name": "Vector Reverse 32", "summary": "Reverses elements within 32-bit words.", "syntax": "VREV32.
, ", "encoding": {"format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 00 | Vd | 0 | 00 | 01 | 0 | M | 0 | Vm", "hex_opcode": "0xF3B00080", "visual_parts": [{"raw": "111100111", "clean": "111100111"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "size", "clean": "size"}, {"raw": "00", "clean": "00"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0", "clean": "0"}, {"raw": "00", "clean": "00"}, {"raw": "01", "clean": "01"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:9 | 8:7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Reverses the byte or halfword order within each 32-bit word element in the source register, depending on element size. For 8-bit elements, reverses bytes within words; for 16-bit elements, reverses halfwords within words. Condition flags (N, Z, C, V) are not affected. Executes in A32/T32 with NEON extension; operates on integer data types.", "example": "VREV32.dt q0, q2", "pseudocode": "if element_size == 8:\n for i = 0 to 127 by 32:\n for j = 0 to 31 by 8:\n Qd[i+j+7:i+j] ← Qm[i+31-j:i+24-j]\nelse if element_size == 16:\n for i = 0 to 127 by 32:\n Qd[i+31:i+16] ← Qm[i+15:i+0]\n Qd[i+15:i+0] ← Qm[i+31:i+16]"} {"mnemonic": "vrev64", "architecture": "ARMv8-A", "full_name": "Vector Reverse 64", "summary": "Reverses elements within 64-bit doublewords.", "syntax": "VREV64.
, ", "encoding": {"format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 00 | Vd | 0 | 00 | 00 | 0 | M | 0 | Vm", "hex_opcode": "0xF3B00000", "visual_parts": [{"raw": "111100111", "clean": "111100111"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "size", "clean": "size"}, {"raw": "00", "clean": "00"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0", "clean": "0"}, {"raw": "00", "clean": "00"}, {"raw": "00", "clean": "00"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:9 | 8:7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Reverses the order of elements within each 64-bit doubleword in the source register. The granularity of reversal depends on element size: 8-bit elements are reversed within 64-bit units, 16-bit elements are reversed within 64-bit units, and 32-bit elements are reversed within 64-bit units. Condition flags (N, Z, C, V) are not affected. Executes in A32/T32 with NEON extension; operates on integer data types.", "example": "VREV64.dt q0, q2", "pseudocode": "if element_size == 8:\n for i = 0 to 127 by 64:\n for j = 0 to 63 by 8:\n Qd[i+j+7:i+j] ← Qm[i+63-j:i+56-j]\nelse if element_size == 16:\n for i = 0 to 127 by 64:\n for j = 0 to 48 by 16:\n Qd[i+j+15:i+j] ← Qm[i+63-j:i+48-j]\nelse if element_size == 32:\n for i = 0 to 127 by 64:\n Qd[i+63:i+32] ← Qm[i+31:i+0]\n Qd[i+31:i+0] ← Qm[i+63:i+32]"} {"mnemonic": "vshl", "architecture": "ARMv8-A", "full_name": "Vector Shift Left (Immediate)", "summary": "Shifts elements left.", "syntax": "VSHL.
, , #", "encoding": {"format": "NEON Shift", "binary_pattern": "1111001 | 0 | 1 | D | imm6 | Vd | 0101 | L | 0 | M | 1 | Vm", "hex_opcode": "0xF2800510", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "imm6", "clean": "imm6"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0101", "clean": "0101"}, {"raw": "L", "clean": "L"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}, {"name": "imm", "desc": "Signed immediate value"}], "extension": "NEON (SIMD)", "description": "Shifts each element in the source register left by an immediate number of bits and stores the result in the destination register. Bits shifted out of the left end are lost, and zeros are shifted in from the right. The shift amount is applied uniformly to all elements and is encoded in the imm6 field, with the interpretation dependent on element size (sz). Condition flags (N, Z, C, V) are not affected. Executes in A32/T32 with NEON extension.", "example": "VSHL.dt q0, q2, #16", "pseudocode": "shift_amount ← DecodeImmShift(imm6, sz) // Decodes imm6 based on element size\nfor i = 0 to 127 by element_size:\n element ← Qm[i+element_size-1:i]\n Qd[i+element_size-1:i] ← element << shift_amount"} {"mnemonic": "vshr", "architecture": "ARMv8-A", "full_name": "Vector Shift Right (Immediate)", "summary": "Shifts elements right.", "syntax": "VSHR.
, , #", "encoding": {"format": "NEON Shift", "binary_pattern": "1111001 | U | 1 | D | imm6 | Vd | 0000 | L | 0 | M | 1 | Vm", "hex_opcode": "0xF2800010", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "U", "clean": "U"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "imm6", "clean": "imm6"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0000", "clean": "0000"}, {"raw": "L", "clean": "L"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}, {"name": "imm", "desc": "Signed immediate value"}], "extension": "NEON (SIMD)", "description": "Shifts each element in the source register right by an immediate number of bits, performing a logical (unsigned) or arithmetic (signed) shift depending on the data type, and stores the result in the destination register. For unsigned types, zeros are shifted in from the left; for signed types, the sign bit is extended. Condition flags (N, Z, C, V) are not affected. Executes in A32/T32 with NEON extension.", "example": "VSHR.dt q0, q2, #16", "pseudocode": "shift_amount ← DecodeImmShift(imm6, sz) // Decodes imm6 based on element size\nfor i = 0 to 127 by element_size:\n element ← Qm[i+element_size-1:i]\n if is_signed_type:\n Qd[i+element_size-1:i] ← arithmetic_shift_right(element, shift_amount)\n else:\n Qd[i+element_size-1:i] ← element >> shift_amount"} {"mnemonic": "vshrn", "architecture": "ARMv8-A", "full_name": "Vector Shift Right Narrow", "summary": "Shifts right and narrows result.", "syntax": "VSHRN.
, , #", "encoding": {"format": "NEON Shift", "binary_pattern": "1111001 | 0 | 1 | D | imm6 | Vd | 1000 | 0 | 0 | M | 1 | Vm", "hex_opcode": "0xF2800810", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "imm6", "clean": "imm6"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1000", "clean": "1000"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Dd", "desc": "Dest Narrow"}, {"name": "Qm", "desc": "Src Wide"}, {"name": "imm", "desc": "Signed immediate value"}], "extension": "NEON (SIMD)", "description": "Shifts each element in the 128-bit source register right by an immediate number of bits, narrows the result to half-width, and stores the narrowed values in the 64-bit destination register. For example, 16-bit results from 32-bit elements are stored in a 64-bit destination. Condition flags (N, Z, C, V) are not affected. Executes in A32/T32 with NEON extension.", "example": "VSHRN.dt d0, q2, #16", "pseudocode": "shift_amount ← DecodeImmShift(imm6, input_element_size)\noutput_element_size ← input_element_size / 2\nfor i = 0 to 63 by output_element_size:\n element ← Qm[i*2+input_element_size*2-1:i*2]\n shifted ← element >> shift_amount\n Dd[i+output_element_size-1:i] ← shifted[output_element_size-1:0]"} {"mnemonic": "vst1", "architecture": "ARMv8-A", "full_name": "Vector Store Multiple (Single Element)", "summary": "Stores vector data to memory.", "syntax": "VST1. , []{!}", "encoding": {"format": "NEON Store", "binary_pattern": "111101001 | D | 0 | 0 | Rn | Vd | 00 | 00 | index_align | 1101", "hex_opcode": "0xF480000D", "visual_parts": [{"raw": "111101001", "clean": "111101001"}, {"raw": "D", "clean": "D"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "00", "clean": "00"}, {"raw": "00", "clean": "00"}, {"raw": "index_align", "clean": "index_align"}, {"raw": "1101", "clean": "1101"}], "bit_positions": "31:23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:10 | 9:8 | 7:4 | 3:0"}, "operands": [{"name": "list", "desc": "Src Registers"}, {"name": "Rn", "desc": "First source / base general-purpose register"}], "extension": "NEON (SIMD)", "description": "Stores one or more NEON vectors to memory at the address held in Rn. The specifies the vector registers to store (1-4 registers), and determines the element width (8, 16, 32, or 64 bits). If ! is present, Rn is post-indexed by the number of bytes stored. No flags are affected. Execution is restricted to A32/T32 with NEON support; privilege level is determined by the memory access.", "example": "VST1.size {r0-r3}, [r1]!", "pseudocode": "address ← Rn\nfor each register in list:\n [address] ← register value (element size as specified)\n address ← address + (register_width_in_bytes)\nif postindex:\n Rn ← Rn + (total_bytes_stored)"} {"mnemonic": "vsub", "architecture": "ARMv8-A", "full_name": "Vector Subtract (Integer)", "summary": "Subtracts integer elements.", "syntax": "VSUB.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 0 | D | 1 | sz | Vn | Vd | 1101 | N | 1 | M | 0 | Vm", "hex_opcode": "0xF2200D40", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "1", "clean": "1"}, {"raw": "sz", "clean": "sz"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1101", "clean": "1101"}, {"raw": "N", "clean": "N"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Vector Subtract (Integer) performs element-wise subtraction of two NEON 128-bit registers, subtracting corresponding integer elements of size 8, 16, 32, or 64 bits. The instruction executes in Q-register (128-bit) mode and wraps on underflow without setting flags. This is a NEON SIMD instruction available in both A32 and T32 states when NEON is supported.", "example": "VSUB.dt q0, q1, q2", "pseudocode": "for each element i in Qd:\n Qd[i] ← Qn[i] - Qm[i]"} {"mnemonic": "vtbl", "architecture": "ARMv8-A", "full_name": "Vector Table Lookup", "summary": "Look up elements in a vector table.", "syntax": "VTBL.8
, , ", "encoding": {"format": "NEON Table", "binary_pattern": "111100111 | D | 11 | Vn | Vd | 10 | len | N | 0 | M | 0 | Vm", "hex_opcode": "0xF3B00800", "visual_parts": [{"raw": "111100111", "clean": "111100111"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "len", "clean": "len"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Dd", "desc": "Destination 64-bit SIMD/FP register"}, {"name": "list", "desc": "Table"}, {"name": "Dm", "desc": "Indices"}], "extension": "NEON (SIMD)", "description": "Performs a table lookup where each element of Dm is used as an index into the table formed by one or more consecutive NEON registers in , and the corresponding table element is written to Dd. Out-of-range indices produce a zero result. No flags are affected. Execution is restricted to A32/T32 with NEON support; the table may span 1-4 consecutive registers, controlled by the encoding field.", "example": "VTBL.8 d0, {r0-r3}, d2", "pseudocode": "for i ← 0 to (size_of_Dd / 8) - 1:\n index ← Dm[i*8 +: 8]\n if index < (len + 1) * 16:\n Dd[i*8 +: 8] ← table[index]\n else:\n Dd[i*8 +: 8] ← 0"} {"mnemonic": "vtrn", "architecture": "ARMv8-A", "full_name": "Vector Transpose", "summary": "Transposes elements of two vectors.", "syntax": "VTRN.
, ", "encoding": {"format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 10 | Vd | 0 | 0001 | 1 | M | 0 | Vm", "hex_opcode": "0xF3B200C0", "visual_parts": [{"raw": "111100111", "clean": "111100111"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "size", "clean": "size"}, {"raw": "10", "clean": "10"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0", "clean": "0"}, {"raw": "0001", "clean": "0001"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Dest/Src1"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Transposes elements of two 128-bit NEON vectors Qd and Qm, swapping odd and even elements. The element size is determined by
(8, 16, or 32 bits). After execution, Qd and Qm contain interleaved even/odd elements from the original vectors. No flags are affected. Execution is restricted to A32/T32 with NEON support.", "example": "VTRN.dt q0, q2", "pseudocode": "temp_d ← Qd\ntemp_m ← Qm\nfor i ← 0 to (128 / element_width) - 1:\n if i is even:\n Qd[i * element_width +: element_width] ← temp_d[i * element_width +: element_width]\n Qm[i * element_width +: element_width] ← temp_m[i * element_width +: element_width]\n else:\n Qd[i * element_width +: element_width] ← temp_m[(i - 1) * element_width +: element_width]\n Qm[i * element_width +: element_width] ← temp_d[(i - 1) * element_width +: element_width]"} {"mnemonic": "vtst", "architecture": "ARMv8-A", "full_name": "Vector Test Bits", "summary": "Tests if any bits match (Vd = (Vn & Vm) != 0).", "syntax": "VTST.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 0 | D | size | Vn | Vd | 1000 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2000810", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1000", "clean": "1000"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Tests if any bits match by computing (Qn AND Qm) per element and writing all 1s (matching element size) to Qd if the result is nonzero, else all 0s. Element size is determined by
. No arithmetic flags are modified. Execution is restricted to A32/T32 with NEON support.", "example": "VTST.dt q0, q1, q2", "pseudocode": "for i ← 0 to (128 / element_width) - 1:\n result ← Qn[i * element_width +: element_width] AND Qm[i * element_width +: element_width]\n if result != 0:\n Qd[i * element_width +: element_width] ← (element_width bits of 1s)\n else:\n Qd[i * element_width +: element_width] ← 0"} {"mnemonic": "vuzp", "architecture": "ARMv8-A", "full_name": "Vector Unzip", "summary": "De-interleaves vectors.", "syntax": "VUZP.
, ", "encoding": {"format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 10 | Vd | 0 | 0010 | 1 | M | 0 | Vm", "hex_opcode": "0xF3B20140", "visual_parts": [{"raw": "111100111", "clean": "111100111"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "size", "clean": "size"}, {"raw": "10", "clean": "10"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0", "clean": "0"}, {"raw": "0010", "clean": "0010"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Dest/Src1"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "De-interleaves elements from two 128-bit NEON vectors by extracting all even-indexed or all odd-indexed elements and placing them into Qd and Qm respectively. Element size is determined by
. No flags are affected. Execution is restricted to A32/T32 with NEON support.", "example": "VUZP.dt q0, q2", "pseudocode": "temp_d ← Qd\ntemp_m ← Qm\nfor i ← 0 to (128 / (2 * element_width)) - 1:\n Qd[i * element_width +: element_width] ← temp_d[(2 * i) * element_width +: element_width]\n Qd[(64 + i) * element_width +: element_width] ← temp_m[(2 * i) * element_width +: element_width]\n Qm[i * element_width +: element_width] ← temp_d[(2 * i + 1) * element_width +: element_width]\n Qm[(64 + i) * element_width +: element_width] ← temp_m[(2 * i + 1) * element_width +: element_width]"} {"mnemonic": "vzip", "architecture": "ARMv8-A", "full_name": "Vector Zip", "summary": "Interleaves vectors.", "syntax": "VZIP.
, ", "encoding": {"format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 10 | Vd | 0 | 0011 | 1 | M | 0 | Vm", "hex_opcode": "0xF3B201C0", "visual_parts": [{"raw": "111100111", "clean": "111100111"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "size", "clean": "size"}, {"raw": "10", "clean": "10"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0", "clean": "0"}, {"raw": "0011", "clean": "0011"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Dest/Src1"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Interleaves elements from two 128-bit NEON vectors by mixing even-indexed elements from Qd with odd-indexed elements from Qm and vice versa. Element size is determined by
. No flags are affected. Execution is restricted to A32/T32 with NEON support.", "example": "VZIP.dt q0, q2", "pseudocode": "temp_d ← Qd\ntemp_m ← Qm\nfor i ← 0 to (128 / (2 * element_width)) - 1:\n Qd[2 * i * element_width +: element_width] ← temp_d[i * element_width +: element_width]\n Qd[(2 * i + 1) * element_width +: element_width] ← temp_m[i * element_width +: element_width]\n Qm[2 * i * element_width +: element_width] ← temp_d[(64 + i) * element_width +: element_width]\n Qm[(2 * i + 1) * element_width +: element_width] ← temp_m[(64 + i) * element_width +: element_width]"} {"mnemonic": "adc", "architecture": "ARMv8-A", "full_name": "Add with Carry", "summary": "Adds two register values and the Carry flag.", "syntax": "ADC , , ", "encoding": {"format": "Data Processing (3-source)", "binary_pattern": "0 | 0 | 0 | 11010000 | Rm | 000000 | Rn | Rd", "hex_opcode": "0x1A000000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11010000", "clean": "11010000"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "000000", "clean": "000000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Wd", "desc": "Dest (32-bit)"}, {"name": "Wn", "desc": "First source / base 32-bit integer register"}, {"name": "Wm", "desc": "Second source / offset 32-bit integer register"}], "extension": "Base", "description": "Adds Wn and Wm plus the Carry flag (C), placing the 32-bit result in Wd. The C flag is read but not modified by this instruction; use ADCS to update flags. Execution is available in AArch64 only.", "example": "ADC w0, w1, w2", "pseudocode": "result ← Wn + Wm + C\nWd ← result[0:31]"} {"mnemonic": "adc", "architecture": "ARMv8-A", "full_name": "Add with Carry (64-bit)", "summary": "Adds two 64-bit register values and the Carry flag.", "syntax": "ADC , , ", "encoding": {"format": "Data Processing (3-source)", "binary_pattern": "1 | 0 | 0 | 11010000 | Rm | 000000 | Rn | Rd", "hex_opcode": "0x9A000000", "visual_parts": [{"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11010000", "clean": "11010000"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "000000", "clean": "000000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Xd", "desc": "Dest (64-bit)"}, {"name": "Xn", "desc": "First source / base 64-bit integer register"}, {"name": "Xm", "desc": "Second source / offset 64-bit integer register"}], "extension": "Base", "description": "Add with Carry adds two 64-bit register values and the Carry flag, storing the result in a 64-bit register. The N, Z, C, and V flags are not modified; use ADCS to update flags. This instruction is AArch64-only and executes at any privilege level.", "example": "ADC x0, x1, x2", "pseudocode": "Xd ← Xn + Xm + C"} {"mnemonic": "adcs", "architecture": "ARMv8-A", "full_name": "Add with Carry and Set Flags", "summary": "Adds two register values and Carry, updating NZCV flags.", "syntax": "ADCS , , ", "encoding": {"format": "Data Processing (3-source)", "binary_pattern": "0 | 0 | 1 | 11010000 | Rm | 000000 | Rn | Rd", "hex_opcode": "0x3A000000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "11010000", "clean": "11010000"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "000000", "clean": "000000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Wd", "desc": "Destination 32-bit integer register"}, {"name": "Wn", "desc": "First source / base 32-bit integer register"}, {"name": "Wm", "desc": "Second source / offset 32-bit integer register"}], "extension": "Base", "description": "Adds Wn and Wm plus the Carry flag (C), placing the 32-bit result in Wd and updating the NZCV condition flags. The N, Z, C, and V flags are set based on the result: N if bit 31 is set, Z if the result is zero, C if an unsigned overflow occurs, V if a signed overflow occurs. Execution is available in AArch64 only.", "example": "ADCS w0, w1, w2", "pseudocode": "result ← Wn + Wm + C\nWd ← result[0:31]\nN ← result[31]\nZ ← (result[0:31] == 0)\nC ← result[32] (unsigned overflow)\nV ← (overflow from signed addition)"} {"mnemonic": "adcs", "architecture": "ARMv8-A", "full_name": "Add with Carry and Set Flags (64-bit)", "summary": "Adds two 64-bit register values and Carry, updating NZCV flags.", "syntax": "ADCS , , ", "encoding": {"format": "Data Processing (3-source)", "binary_pattern": "1 | 0 | 1 | 11010000 | Rm | 000000 | Rn | Rd", "hex_opcode": "0xBA000000", "visual_parts": [{"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "11010000", "clean": "11010000"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "000000", "clean": "000000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Xd", "desc": "Destination 64-bit integer register"}, {"name": "Xn", "desc": "First source / base 64-bit integer register"}, {"name": "Xm", "desc": "Second source / offset 64-bit integer register"}], "extension": "Base", "description": "Add with Carry and Set Flags adds two 64-bit register values and the Carry flag, updating the NZCV condition flags based on the result. The N flag reflects the sign of the result, Z is set if the result is zero, C is set on unsigned carry, and V is set on signed overflow. This instruction is AArch64-only and executes at any privilege level.", "example": "ADCS x0, x1, x2", "pseudocode": "result ← Xn + Xm + C\nXd ← result\nN ← result[63]\nZ ← (result == 0)\nC ← UnsignedOverflow(Xn, Xm, C)\nV ← SignedOverflow(Xn, Xm, C)"} {"mnemonic": "add", "architecture": "ARMv8-A", "full_name": "Add (Extended Register)", "summary": "Adds a register value and a sign/zero-extended register value.", "syntax": "ADD , , {, {#}}", "encoding": {"format": "Data Processing (Register)", "binary_pattern": "0 | 0 | 0 | 01011 | 00 | 1 | Rm | option | imm3 | Rn | Rd", "hex_opcode": "0x0B200000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "01011", "clean": "01011"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "option", "clean": "option"}, {"raw": "imm3", "clean": "imm3"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Wd", "desc": "Destination 32-bit integer register"}, {"name": "Wn", "desc": "First source / base 32-bit integer register"}, {"name": "Wm", "desc": "Second source / offset 32-bit integer register"}, {"name": "extend", "desc": "Extension type"}], "extension": "Base", "description": "Adds a sign/zero-extended 32-bit register value to another 32-bit register and stores the result in the destination register. The extension type and optional shift amount are specified via the extend operand. Condition flags (N, Z, C, V) are not affected by this instruction.", "example": "ADD Wd, Wn, w2", "pseudocode": "Wd ← Wn + ExtendValue(Wm, extend, amount)"} {"mnemonic": "add", "architecture": "ARMv8-A", "full_name": "Add (Extended Register 64-bit)", "summary": "Adds a 64-bit register and an extended register value.", "syntax": "ADD , , {, {#}}", "encoding": {"format": "Data Processing (Register)", "binary_pattern": "1 | 0 | 0 | 01011 | 00 | 1 | Rm | option | imm3 | Rn | Rd", "hex_opcode": "0x8B200000", "visual_parts": [{"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "01011", "clean": "01011"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "option", "clean": "option"}, {"raw": "imm3", "clean": "imm3"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Xd", "desc": "Destination 64-bit integer register"}, {"name": "Xn", "desc": "First source / base 64-bit integer register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "Base", "description": "Adds a sign/zero-extended 64-bit register value to another 64-bit register and stores the result in the destination register. The extension type and optional shift amount determine how Rm is extended. Condition flags (N, Z, C, V) are not affected by this instruction.", "example": "ADD x0, x1, Rm", "pseudocode": "Xd ← Xn + ExtendValue(Rm, extend, amount)"} {"mnemonic": "add", "architecture": "ARMv8-A", "full_name": "Add (Immediate)", "summary": "Adds a register value and an immediate value.", "syntax": "ADD , , # {, lsl #}", "encoding": {"format": "Data Processing (Immediate)", "binary_pattern": "0 | 0 | 0 | 100010 | sh | imm12 | Rn | Rd", "hex_opcode": "0x11000000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "100010", "clean": "100010"}, {"raw": "sh", "clean": "sh"}, {"raw": "imm12", "clean": "imm12"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:23 | 22 | 21:10 | 9:5 | 4:0"}, "operands": [{"name": "Wd", "desc": "Destination 32-bit integer register"}, {"name": "Wn", "desc": "First source / base 32-bit integer register"}, {"name": "imm", "desc": "Immediate (12-bit)"}], "extension": "Base", "description": "Adds a 12-bit immediate value (optionally shifted left by 0 or 12 bits) to a 32-bit register and stores the result in the destination register. Condition flags (N, Z, C, V) are not affected by this instruction. SP may be used as source or destination.", "example": "ADD Wd, Wn, #16", "pseudocode": "Wd ← Wn + (imm << (sh * 12))"} {"mnemonic": "add", "architecture": "ARMv8-A", "full_name": "Add (Immediate 64-bit)", "summary": "Adds a 64-bit register value and an immediate value.", "syntax": "ADD , , # {, lsl #}", "encoding": {"format": "Data Processing (Immediate)", "binary_pattern": "1 | 0 | 0 | 100010 | sh | imm12 | Rn | Rd", "hex_opcode": "0x91000000", "visual_parts": [{"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "100010", "clean": "100010"}, {"raw": "sh", "clean": "sh"}, {"raw": "imm12", "clean": "imm12"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:23 | 22 | 21:10 | 9:5 | 4:0"}, "operands": [{"name": "Xd", "desc": "Destination 64-bit integer register"}, {"name": "Xn", "desc": "First source / base 64-bit integer register"}, {"name": "imm", "desc": "Signed immediate value"}], "extension": "Base", "description": "Adds a 12-bit immediate value (optionally shifted left by 0 or 12 bits) to a 64-bit register and stores the result in the destination register. Condition flags (N, Z, C, V) are not affected by this instruction. SP may be used as source or destination.", "example": "ADD x0, x1, #16", "pseudocode": "Xd ← Xn + (imm << (sh * 12))"} {"mnemonic": "add", "architecture": "ARMv8-A", "full_name": "Add (Shifted Register)", "summary": "Adds a register value and a shifted register value.", "syntax": "ADD , , {, #}", "encoding": {"format": "Data Processing (Register)", "binary_pattern": "0 | 0 | 0 | 01011 | shift | 0 | Rm | imm6 | Rn | Rd", "hex_opcode": "0x0B000000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "01011", "clean": "01011"}, {"raw": "shift", "clean": "shift"}, {"raw": "0", "clean": "0"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "imm6", "clean": "imm6"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Wd", "desc": "Destination 32-bit integer register"}, {"name": "Wn", "desc": "First source / base 32-bit integer register"}, {"name": "Wm", "desc": "Second source / offset 32-bit integer register"}], "extension": "Base", "description": "Adds a shifted 32-bit register value to another 32-bit register and stores the result in the destination register. The shift type and amount are encoded in the imm6 field. Condition flags (N, Z, C, V) are not affected by this instruction.", "example": "ADD w0, w1, w2", "pseudocode": "Wd ← Wn + ShiftReg(Wm, shift_type, shift_amount)"} {"mnemonic": "add", "architecture": "ARMv8-A", "full_name": "Add (Shifted Register 64-bit)", "summary": "Adds a 64-bit register value and a shifted register value.", "syntax": "ADD , , {, #}", "encoding": {"format": "Data Processing (Register)", "binary_pattern": "1 | 0 | 0 | 01011 | shift | 0 | Rm | imm6 | Rn | Rd", "hex_opcode": "0x8B000000", "visual_parts": [{"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "01011", "clean": "01011"}, {"raw": "shift", "clean": "shift"}, {"raw": "0", "clean": "0"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "imm6", "clean": "imm6"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Xd", "desc": "Destination 64-bit integer register"}, {"name": "Xn", "desc": "First source / base 64-bit integer register"}, {"name": "Xm", "desc": "Second source / offset 64-bit integer register"}], "extension": "Base", "description": "Adds a shifted 64-bit register value to another 64-bit register and stores the result in the destination register. The shift type and amount are encoded in the imm6 field. Condition flags (N, Z, C, V) are not affected by this instruction.", "example": "ADD x0, x1, x2", "pseudocode": "Xd ← Xn + ShiftReg(Xm, shift_type, shift_amount)"} {"mnemonic": "adds", "architecture": "ARMv8-A", "full_name": "Add and Set Flags (Extended Register)", "summary": "Adds and updates flags (Extended Register).", "syntax": "ADDS , , {, {#}}", "encoding": {"format": "Data Processing (Register)", "binary_pattern": "0 | 0 | 1 | 01011 | 00 | 1 | Rm | option | imm3 | Rn | Rd", "hex_opcode": "0x2B200000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "01011", "clean": "01011"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "option", "clean": "option"}, {"raw": "imm3", "clean": "imm3"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Wd", "desc": "Destination 32-bit integer register"}, {"name": "Wn", "desc": "First source / base 32-bit integer register"}, {"name": "Wm", "desc": "Second source / offset 32-bit integer register"}], "extension": "Base", "description": "Add and Set Flags adds a 32-bit register value (optionally extended or shifted) to a 32-bit register or stack pointer, updating the NZCV condition flags. The N flag reflects the sign of the result, Z is set if result is zero, C is set on unsigned carry, and V is set on signed overflow. This instruction is AArch64-only and executes at any privilege level.", "example": "ADDS w0, Wn, w2", "pseudocode": "shifted ← ExtendAndShift(Wm, option, imm3)\nresult ← Wn + shifted\nWd ← result\nN ← result[31]\nZ ← (result == 0)\nC ← UnsignedOverflow(Wn, shifted)\nV ← SignedOverflow(Wn, shifted)"} {"mnemonic": "adds", "architecture": "ARMv8-A", "full_name": "Add and Set Flags (Extended Register 64-bit)", "summary": "Adds and updates flags (Extended Register 64-bit).", "syntax": "ADDS , , {, {#}}", "encoding": {"format": "Data Processing (Register)", "binary_pattern": "1 | 0 | 1 | 01011 | 00 | 1 | Rm | option | imm3 | Rn | Rd", "hex_opcode": "0xAB200000", "visual_parts": [{"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "01011", "clean": "01011"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "option", "clean": "option"}, {"raw": "imm3", "clean": "imm3"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Xd", "desc": "Destination 64-bit integer register"}, {"name": "Xn", "desc": "First source / base 64-bit integer register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "Base", "description": "Add with extended register operand and set condition flags. Adds the sign-extended or zero-extended value of Rm to Xn, stores the result in Xd, and updates the N, Z, C, and V flags based on the result. AArch64-only instruction executing at any privilege level.", "example": "ADDS x0, x1, Rm", "pseudocode": "result ← Xn + ExtendValue(Rm, extend, amount)\nXd ← result\nN ← result[63]\nZ ← (result == 0)\nC ← CarryOut(Xn, ExtendValue(Rm, extend, amount))\nV ← OverflowFrom(Xn, ExtendValue(Rm, extend, amount))"} {"mnemonic": "adds", "architecture": "ARMv8-A", "full_name": "Add and Set Flags (Immediate)", "summary": "Adds immediate and updates flags.", "syntax": "ADDS , , # {, lsl #}", "encoding": {"format": "Data Processing (Immediate)", "binary_pattern": "0 | 0 | 1 | 100010 | sh | imm12 | Rn | Rd", "hex_opcode": "0x31000000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "100010", "clean": "100010"}, {"raw": "sh", "clean": "sh"}, {"raw": "imm12", "clean": "imm12"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:23 | 22 | 21:10 | 9:5 | 4:0"}, "operands": [{"name": "Wd", "desc": "Destination 32-bit integer register"}, {"name": "Wn", "desc": "First source / base 32-bit integer register"}, {"name": "imm", "desc": "Imm"}], "extension": "Base", "description": "Add immediate value to 32-bit register and set condition flags. Adds a 12-bit immediate (optionally left-shifted by 0 or 12 bits) to Wn, stores the result in Wd, and updates the N, Z, C, and V flags based on the result. AArch64-only instruction executing at any privilege level.", "example": "ADDS w0, Wn, #16", "pseudocode": "imm_val ← imm12 << (sh * 12)\nresult ← Wn + imm_val\nWd ← result\nN ← result[31]\nZ ← (result == 0)\nC ← CarryOut(Wn, imm_val)\nV ← OverflowFrom(Wn, imm_val)"} {"mnemonic": "adds", "architecture": "ARMv8-A", "full_name": "Add and Set Flags (Immediate 64-bit)", "summary": "Adds immediate and updates flags (64-bit).", "syntax": "ADDS , , # {, lsl #}", "encoding": {"format": "Data Processing (Immediate)", "binary_pattern": "1 | 0 | 1 | 100010 | sh | imm12 | Rn | Rd", "hex_opcode": "0xB1000000", "visual_parts": [{"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "100010", "clean": "100010"}, {"raw": "sh", "clean": "sh"}, {"raw": "imm12", "clean": "imm12"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:23 | 22 | 21:10 | 9:5 | 4:0"}, "operands": [{"name": "Xd", "desc": "Destination 64-bit integer register"}, {"name": "Xn", "desc": "First source / base 64-bit integer register"}, {"name": "imm", "desc": "Imm"}], "extension": "Base", "description": "Add immediate value to 64-bit register and set condition flags. Adds a 12-bit immediate (optionally left-shifted by 0 or 12 bits) to Xn, stores the result in Xd, and updates the N, Z, C, and V flags based on the result. AArch64-only instruction executing at any privilege level.", "example": "ADDS x0, x1, #16", "pseudocode": "imm_val ← imm12 << (sh * 12)\nresult ← Xn + imm_val\nXd ← result\nN ← result[63]\nZ ← (result == 0)\nC ← CarryOut(Xn, imm_val)\nV ← OverflowFrom(Xn, imm_val)"} {"mnemonic": "adds", "architecture": "ARMv8-A", "full_name": "Add and Set Flags (Shifted Register)", "summary": "Adds shifted register and updates flags.", "syntax": "ADDS , , {, #}", "encoding": {"format": "Data Processing (Register)", "binary_pattern": "0 | 0 | 1 | 01011 | shift | 0 | Rm | imm6 | Rn | Rd", "hex_opcode": "0x2B000000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "01011", "clean": "01011"}, {"raw": "shift", "clean": "shift"}, {"raw": "0", "clean": "0"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "imm6", "clean": "imm6"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Wd", "desc": "Destination 32-bit integer register"}, {"name": "Wn", "desc": "First source / base 32-bit integer register"}, {"name": "Wm", "desc": "Second source / offset 32-bit integer register"}], "extension": "Base", "description": "Add shifted 32-bit register to another and set condition flags. Adds the optionally shifted value of Wm to Wn, stores the result in Wd, and updates the N, Z, C, and V flags based on the result. AArch64-only instruction executing at any privilege level.", "example": "ADDS w0, w1, w2", "pseudocode": "shifted_val ← Wm << amount\nresult ← Wn + shifted_val\nWd ← result\nN ← result[31]\nZ ← (result == 0)\nC ← CarryOut(Wn, shifted_val)\nV ← OverflowFrom(Wn, shifted_val)"} {"mnemonic": "adds", "architecture": "ARMv8-A", "full_name": "Add and Set Flags (Shifted Register 64-bit)", "summary": "Adds shifted register and updates flags (64-bit).", "syntax": "ADDS , , {, #}", "encoding": {"format": "Data Processing (Register)", "binary_pattern": "1 | 0 | 1 | 01011 | shift | 0 | Rm | imm6 | Rn | Rd", "hex_opcode": "0xAB000000", "visual_parts": [{"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "01011", "clean": "01011"}, {"raw": "shift", "clean": "shift"}, {"raw": "0", "clean": "0"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "imm6", "clean": "imm6"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Xd", "desc": "Destination 64-bit integer register"}, {"name": "Xn", "desc": "First source / base 64-bit integer register"}, {"name": "Xm", "desc": "Second source / offset 64-bit integer register"}], "extension": "Base", "description": "Add shifted 64-bit register to another and set condition flags. Adds the optionally shifted value of Xm to Xn, stores the result in Xd, and updates the N, Z, C, and V flags based on the result. AArch64-only instruction executing at any privilege level.", "example": "ADDS x0, x1, x2", "pseudocode": "shifted_val ← Xm << amount\nresult ← Xn + shifted_val\nXd ← result\nN ← result[63]\nZ ← (result == 0)\nC ← CarryOut(Xn, shifted_val)\nV ← OverflowFrom(Xn, shifted_val)"} {"mnemonic": "adr", "architecture": "ARMv8-A", "full_name": "Form PC-relative Address", "summary": "Calculates the address of a label (PC +/- 1MB range).", "syntax": "ADR ,
, , ", "encoding": {"format": "VFP Misc", "binary_pattern": "11111110 | 0 | D | cc | Vn | Vd | 1011 | N | 0 | M | Vm", "hex_opcode": "0xFE000B00", "visual_parts": [{"raw": "11111110", "clean": "11111110"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "cc", "clean": "cc"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1011", "clean": "1011"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "Vm", "clean": "Vm"}]}, "operands": [{"name": "Dd", "desc": "Destination 64-bit SIMD/FP register"}, {"name": "Dn", "desc": "First source 64-bit SIMD/FP register"}, {"name": "Dm", "desc": "Second source 64-bit SIMD/FP register"}], "extension": "VFP (Float)", "description": "Vector Select (Double). This VFP instruction selects between two 64-bit floating-point operands (Dn and Dm) based on a condition code (cc) applied to the FPSCR condition flags, writing the selected value to Dd. The condition code determines which register's value is copied. No flags are set or cleared by this instruction.", "example": "VSELcond.F64 d0, d1, d2", "pseudocode": "if ConditionPassed(cc) then\n Dd ← Dn\nelse\n Dd ← Dm"} {"mnemonic": "vmaxnm", "architecture": "ARMv8-A", "full_name": "Vector Maximum Number (Double)", "summary": "Returns larger double-precision value, handling NaNs.", "syntax": "VMAXNM.F64
, , ", "encoding": {"format": "VFP Misc", "binary_pattern": "111111101 | D | 00 | Vn | Vd | 10 | 11 | N | 0 | M | 0 | Vm", "hex_opcode": "0xFE800B00", "visual_parts": [{"raw": "111111101", "clean": "111111101"}, {"raw": "D", "clean": "D"}, {"raw": "00", "clean": "00"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "11", "clean": "11"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Dd", "desc": "Destination 64-bit SIMD/FP register"}, {"name": "Dn", "desc": "First source 64-bit SIMD/FP register"}, {"name": "Dm", "desc": "Second source 64-bit SIMD/FP register"}], "extension": "VFP (Float)", "description": "Vector Maximum Number (Double). This VFP instruction compares two 64-bit floating-point values (Dn and Dm) and writes the larger value to Dd, with special handling for NaN: if one operand is NaN, the other is returned (not NaN). FPSCR exception flags may be set according to the IEEE 754 floating-point standard.", "example": "VMAXNM.F64 d0, d1, d2", "pseudocode": "if IsNaN(Dn) then\n Dd ← Dm\nelseif IsNaN(Dm) then\n Dd ← Dn\nelse if Dn ≥ Dm then\n Dd ← Dn\nelse\n Dd ← Dm"} {"mnemonic": "vminnm", "architecture": "ARMv8-A", "full_name": "Vector Minimum Number (Double)", "summary": "Returns smaller double-precision value, handling NaNs.", "syntax": "VMINNM.F64
, , ", "encoding": {"format": "VFP Misc", "binary_pattern": "111111101 | D | 00 | Vn | Vd | 10 | 11 | N | 1 | M | 0 | Vm", "hex_opcode": "0xFE800B40", "visual_parts": [{"raw": "111111101", "clean": "111111101"}, {"raw": "D", "clean": "D"}, {"raw": "00", "clean": "00"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "11", "clean": "11"}, {"raw": "N", "clean": "N"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Dd", "desc": "Destination 64-bit SIMD/FP register"}, {"name": "Dn", "desc": "First source 64-bit SIMD/FP register"}, {"name": "Dm", "desc": "Second source 64-bit SIMD/FP register"}], "extension": "VFP (Float)", "description": "Vector Minimum Number (Double). This VFP instruction compares two 64-bit floating-point values (Dn and Dm) and writes the smaller value to Dd, with special handling for NaN: if one operand is NaN, the other is returned (not NaN). FPSCR exception flags may be set according to the IEEE 754 floating-point standard.", "example": "VMINNM.F64 d0, d1, d2", "pseudocode": "if IsNaN(Dn) then\n Dd ← Dm\nelseif IsNaN(Dm) then\n Dd ← Dn\nelse if Dn ≤ Dm then\n Dd ← Dn\nelse\n Dd ← Dm"} {"mnemonic": "vrintr", "architecture": "ARMv8-A", "full_name": "Vector Round Floating-Point (Current)", "summary": "Rounds float to integral float using FPSCR rounding mode.", "syntax": "VRINTR.F32 , ", "encoding": {"format": "VFP Unary", "binary_pattern": "cond | 11101 | D | 11 | 0 | 110 | Vd | 10 | 10 | 0 | 1 | M | 0 | Vm", "hex_opcode": "0x0EB60A40", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "11101", "clean": "11101"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "0", "clean": "0"}, {"raw": "110", "clean": "110"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}, {"name": "Sm", "desc": "Second source 32-bit floating-point register"}], "extension": "VFP (Float)", "description": "Vector Round Floating-Point (Current). This VFP instruction rounds the 32-bit floating-point value in Sm to an integral floating-point value using the rounding mode specified in the FPSCR and writes the result to Sd. The rounding mode and exception behavior are controlled by FPSCR flags; inexact exceptions may be signaled.", "example": "VRINTR.F32 s0, s2", "pseudocode": "rounding_mode ← FPSCR.RMode\nSd ← RoundFP(Sm, rounding_mode)"} {"mnemonic": "vrintx", "architecture": "ARMv8-A", "full_name": "Vector Round Floating-Point (Exact)", "summary": "Rounds float to integral float, raising Inexact exception.", "syntax": "VRINTX.F32 , ", "encoding": {"format": "VFP Unary", "binary_pattern": "cond | 11101 | D | 11 | 0 | 111 | Vd | 10 | 10 | 0 | 1 | M | 0 | Vm", "hex_opcode": "0x0EB70A40", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "11101", "clean": "11101"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "0", "clean": "0"}, {"raw": "111", "clean": "111"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}, {"name": "Sm", "desc": "Second source 32-bit floating-point register"}], "extension": "VFP (Float)", "description": "Rounds each single-precision floating-point element to the nearest integral value, with round-to-nearest-even semantics. The Inexact exception is raised if the result differs from the input. Condition flags are not affected. This is an A32/T32 VFP instruction requiring the VFP extension.", "example": "VRINTX.F32 s0, s2", "pseudocode": "for i = 0 to 0 do\n Sd[i] ← RoundToNearest(Sm[i])\n if Sd[i] != Sm[i] then\n FPExc_IXC ← 1\n end if\nend for"} {"mnemonic": "sha512h", "architecture": "ARMv8-A", "full_name": "SHA512 Hash Part 1 (A32)", "summary": "SHA512 hash update part 1.", "syntax": "SHA512H.64 , , ", "encoding": {"format": "Crypto 3-Reg", "binary_pattern": "11001110011 | Rm | 1 | 0 | 00 | 00 | Rn | Rd", "hex_opcode": "0xCE608000", "visual_parts": [{"raw": "11001110011", "clean": "11001110011"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "00", "clean": "00"}, {"raw": "00", "clean": "00"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31:21 | 20:16 | 15 | 14 | 13:12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Qd", "desc": "State"}, {"name": "Qn", "desc": "Hash"}, {"name": "Qm", "desc": "Data"}], "extension": "Crypto (SHA512)", "description": "Performs the first part of the SHA-512 hash computation, processing hash values and round constants. The operation combines Qn (hash) and Qm (data) values and updates Qd (state) with intermediate results. This is an A32 Advanced SIMD instruction requiring the SHA512 Cryptographic Extension. Condition flags are not affected.", "example": "SHA512H.64 q0, q1, q2", "pseudocode": "Qd ← SHA512_H_Part1(Qd, Qn, Qm)"} {"mnemonic": "sha512h2", "architecture": "ARMv8-A", "full_name": "SHA512 Hash Part 2 (A32)", "summary": "SHA512 hash update part 2.", "syntax": "SHA512H2.64 , , ", "encoding": {"format": "Crypto 3-Reg", "binary_pattern": "11001110011 | Rm | 1 | 0 | 00 | 01 | Rn | Rd", "hex_opcode": "0xCE608400", "visual_parts": [{"raw": "11001110011", "clean": "11001110011"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "00", "clean": "00"}, {"raw": "01", "clean": "01"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31:21 | 20:16 | 15 | 14 | 13:12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Qd", "desc": "State"}, {"name": "Qn", "desc": "Hash"}, {"name": "Qm", "desc": "Data"}], "extension": "Crypto (SHA512)", "description": "Performs the second part of the SHA-512 hash computation, completing the hash update using state (Qd), hash values (Qn), and message data (Qm). This variant differs from SHA512H in the internal transformation applied. This is an A32 Advanced SIMD instruction requiring the SHA512 Cryptographic Extension. Condition flags are not affected.", "example": "SHA512H2.64 q0, q1, q2", "pseudocode": "Qd ← SHA512_H_Part2(Qd, Qn, Qm)"} {"mnemonic": "sha512su0", "architecture": "ARMv8-A", "full_name": "SHA512 Schedule Update 0 (A32)", "summary": "SHA512 schedule update instruction 0.", "syntax": "SHA512SU0.64 , ", "encoding": {"format": "Crypto 2-Reg", "binary_pattern": "11001110110000001000 | 00 | Rn | Rd", "hex_opcode": "0xCEC08000", "visual_parts": [{"raw": "11001110110000001000", "clean": "11001110110000001000"}, {"raw": "00", "clean": "00"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31:12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "Crypto (SHA512)", "description": "Performs the first schedule update operation for SHA-512 message scheduling, processing Qm and updating Qd with the first sigma operation. This is a unary operation used during SHA-512 preprocessing of the message schedule. This is an A32 Advanced SIMD instruction requiring the SHA512 Cryptographic Extension. Condition flags are not affected.", "example": "SHA512SU0.64 q0, q2", "pseudocode": "Qd ← SHA512_SU_0(Qm)"} {"mnemonic": "sha512su1", "architecture": "ARMv8-A", "full_name": "SHA512 Schedule Update 1 (A32)", "summary": "SHA512 schedule update instruction 1.", "syntax": "SHA512SU1.64 , , ", "encoding": {"format": "Crypto 3-Reg", "binary_pattern": "11001110011 | Rm | 1 | 0 | 00 | 10 | Rn | Rd", "hex_opcode": "0xCE608800", "visual_parts": [{"raw": "11001110011", "clean": "11001110011"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "00", "clean": "00"}, {"raw": "10", "clean": "10"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31:21 | 20:16 | 15 | 14 | 13:12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "Crypto (SHA512)", "description": "Performs the second schedule update operation for SHA-512 message scheduling, combining Qd and Qn with Qm to compute the next message schedule value. This operation incorporates previous schedule elements and the second sigma transformation. This is an A32 Advanced SIMD instruction requiring the SHA512 Cryptographic Extension. Condition flags are not affected.", "example": "SHA512SU1.64 q0, q1, q2", "pseudocode": "Qd ← SHA512_SU_1(Qd, Qn, Qm)"} {"mnemonic": "sm3ss1", "architecture": "ARMv8-A", "full_name": "SM3 Step 1 (A32)", "summary": "SM3 cryptographic hash step 1.", "syntax": "SM3SS1.32 , , ", "encoding": {"format": "Crypto 3-Reg", "binary_pattern": "110011100 | 10 | Rm | 0 | Ra | Rn | Rd", "hex_opcode": "0xCE400000", "visual_parts": [{"raw": "110011100", "clean": "110011100"}, {"raw": "10", "clean": "10"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "0", "clean": "0"}, {"raw": "Ra", "clean": "Ra"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31:23 | 22:21 | 20:16 | 15 | 14:10 | 9:5 | 4:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "Crypto (SM3)", "description": "Performs step 1 of the SM3 cryptographic hash function, combining three 128-bit operands to produce an intermediate result. The operation implements the SM3 compression function's linear transformation. This is an A32 Advanced SIMD instruction requiring the SM3 Cryptographic Extension. Condition flags are not affected.", "example": "SM3SS1.32 q0, q1, q2", "pseudocode": "Qd ← SM3_StepSS1(Qn, Qm)"} {"mnemonic": "sm3tt1a", "architecture": "ARMv8-A", "full_name": "SM3 Step 2A (A32)", "summary": "SM3 cryptographic hash step 2A.", "syntax": "SM3TT1A.32 , , , #", "encoding": {"format": "Crypto Imm", "binary_pattern": "11001110010 | Rm | 10 | imm2 | 00 | Rn | Rd", "hex_opcode": "0xCE408000", "visual_parts": [{"raw": "11001110010", "clean": "11001110010"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "10", "clean": "10"}, {"raw": "imm2", "clean": "imm2"}, {"raw": "00", "clean": "00"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31:21 | 20:16 | 15:14 | 13:12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Dn", "desc": "First source 64-bit SIMD/FP register"}, {"name": "Dm", "desc": "Second source 64-bit SIMD/FP register"}, {"name": "imm", "desc": "Rot"}], "extension": "Crypto (SM3)", "description": "Performs step 2A of the SM3 cryptographic hash, updating 32-bit word elements based on the specified rotation immediate. Operates on 64-bit source registers but stores results in a 128-bit destination. This is an A32 Advanced SIMD instruction requiring the SM3 Cryptographic Extension. Condition flags are not affected.", "example": "SM3TT1A.32 q0, d1, d2, #16", "pseudocode": "rot ← imm * 8\nQd ← SM3_TT1A(Dn, Dm, rot)"} {"mnemonic": "sm3tt1b", "architecture": "ARMv8-A", "full_name": "SM3 Step 2B (A32)", "summary": "SM3 cryptographic hash step 2B.", "syntax": "SM3TT1B.32 , , , #", "encoding": {"format": "Crypto Imm", "binary_pattern": "11001110010 | Rm | 10 | imm2 | 01 | Rn | Rd", "hex_opcode": "0xCE408400", "visual_parts": [{"raw": "11001110010", "clean": "11001110010"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "10", "clean": "10"}, {"raw": "imm2", "clean": "imm2"}, {"raw": "01", "clean": "01"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31:21 | 20:16 | 15:14 | 13:12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Dn", "desc": "First source 64-bit SIMD/FP register"}, {"name": "Dm", "desc": "Second source 64-bit SIMD/FP register"}, {"name": "imm", "desc": "Rot"}], "extension": "Crypto (SM3)", "description": "Performs step 2B of the SM3 cryptographic hash, updating 32-bit word elements with a different permutation than SM3TT1A, based on the specified rotation immediate. Operates on 64-bit source registers but stores results in a 128-bit destination. This is an A32 Advanced SIMD instruction requiring the SM3 Cryptographic Extension. Condition flags are not affected.", "example": "SM3TT1B.32 q0, d1, d2, #16", "pseudocode": "rot ← imm * 8\nQd ← SM3_TT1B(Dn, Dm, rot)"} {"mnemonic": "sm3tt2a", "architecture": "ARMv8-A", "full_name": "SM3 Step 3A (A32)", "summary": "SM3 cryptographic hash step 3A.", "syntax": "SM3TT2A.32 , , , #", "encoding": {"format": "Crypto Imm", "binary_pattern": "11001110010 | Rm | 10 | imm2 | 10 | Rn | Rd", "hex_opcode": "0xCE408800", "visual_parts": [{"raw": "11001110010", "clean": "11001110010"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "10", "clean": "10"}, {"raw": "imm2", "clean": "imm2"}, {"raw": "10", "clean": "10"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31:21 | 20:16 | 15:14 | 13:12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Dn", "desc": "First source 64-bit SIMD/FP register"}, {"name": "Dm", "desc": "Second source 64-bit SIMD/FP register"}, {"name": "imm", "desc": "Rot"}], "extension": "Crypto (SM3)", "description": "SM3 Step 3A performs part of the SM3 cryptographic hash compression function, processing two 32-bit words from the input with a rotation parameter. This instruction operates on 64-bit source registers and writes a 128-bit result, and does not affect any condition flags. The instruction is A32-only and requires the Crypto SM3 extension; it generates an Undefined Instruction exception if executed without the extension enabled.", "example": "SM3TT2A.32 q0, d1, d2, #16", "pseudocode": "Qd ← SM3_TT2A(Dn, Dm, imm2)"} {"mnemonic": "sm3tt2b", "architecture": "ARMv8-A", "full_name": "SM3 Step 3B (A32)", "summary": "SM3 cryptographic hash step 3B.", "syntax": "SM3TT2B.32 , , , #", "encoding": {"format": "Crypto Imm", "binary_pattern": "11001110010 | Rm | 10 | imm2 | 11 | Rn | Rd", "hex_opcode": "0xCE408C00", "visual_parts": [{"raw": "11001110010", "clean": "11001110010"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "10", "clean": "10"}, {"raw": "imm2", "clean": "imm2"}, {"raw": "11", "clean": "11"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31:21 | 20:16 | 15:14 | 13:12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Dn", "desc": "First source 64-bit SIMD/FP register"}, {"name": "Dm", "desc": "Second source 64-bit SIMD/FP register"}, {"name": "imm", "desc": "Rot"}], "extension": "Crypto (SM3)", "description": "SM3 Step 3B performs the second variant of SM3 compression function step 3, processing two 32-bit words with a different constant path than SM3TT2A. This instruction operates on 64-bit source registers and writes a 128-bit result, and does not affect condition flags. The instruction is A32-only and requires the Crypto SM3 extension; it generates an Undefined Instruction exception if executed without the extension enabled.", "example": "SM3TT2B.32 q0, d1, d2, #16", "pseudocode": "Qd ← SM3_TT2B(Dn, Dm, imm2)"} {"mnemonic": "sm3partw1", "architecture": "ARMv8-A", "full_name": "SM3 Part Word 1 (A32)", "summary": "SM3 schedule update part 1.", "syntax": "SM3PARTW1.32 , , ", "encoding": {"format": "Crypto 3-Reg", "binary_pattern": "11001110011 | Rm | 1 | 1 | 00 | 00 | Rn | Rd", "hex_opcode": "0xCE60C000", "visual_parts": [{"raw": "11001110011", "clean": "11001110011"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "00", "clean": "00"}, {"raw": "00", "clean": "00"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31:21 | 20:16 | 15 | 14 | 13:12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "Crypto (SM3)", "description": "SM3 Part Word 1 performs the first part of SM3 message schedule update, computing intermediate values from the previous message schedule words. This instruction operates on three 128-bit registers and does not affect condition flags. The instruction is A32-only and requires the Crypto SM3 extension; it generates an Undefined Instruction exception if executed without the extension enabled.", "example": "SM3PARTW1.32 q0, q1, q2", "pseudocode": "Qd ← SM3_PARTW1(Qn, Qm)"} {"mnemonic": "sm3partw2", "architecture": "ARMv8-A", "full_name": "SM3 Part Word 2 (A32)", "summary": "SM3 schedule update part 2.", "syntax": "SM3PARTW2.32 , , ", "encoding": {"format": "Crypto 3-Reg", "binary_pattern": "11001110011 | Rm | 1 | 1 | 00 | 01 | Rn | Rd", "hex_opcode": "0xCE60C400", "visual_parts": [{"raw": "11001110011", "clean": "11001110011"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "00", "clean": "00"}, {"raw": "01", "clean": "01"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31:21 | 20:16 | 15 | 14 | 13:12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "Crypto (SM3)", "description": "SM3 Part Word 2 performs the second part of SM3 message schedule update, completing the computation of new message schedule words from previous values. This instruction operates on three 128-bit registers and does not affect condition flags. The instruction is A32-only and requires the Crypto SM3 extension; it generates an Undefined Instruction exception if executed without the extension enabled.", "example": "SM3PARTW2.32 q0, q1, q2", "pseudocode": "Qd ← SM3_PARTW2(Qn, Qm)"} {"mnemonic": "sm4e", "architecture": "ARMv8-A", "full_name": "SM4 Encrypt (A32)", "summary": "SM4 encryption step.", "syntax": "SM4E.32 , ", "encoding": {"format": "Crypto 2-Reg", "binary_pattern": "11001110110000001000 | 01 | Rn | Rd", "hex_opcode": "0xCEC08400", "visual_parts": [{"raw": "11001110110000001000", "clean": "11001110110000001000"}, {"raw": "01", "clean": "01"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31:12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Key"}], "extension": "Crypto (SM4)", "description": "SM4 Encrypt performs one round of SM4 block cipher encryption, transforming a 128-bit state register using a 128-bit round key. This instruction does not affect condition flags. The instruction is A32-only and requires the Crypto SM4 extension; it generates an Undefined Instruction exception if executed without the extension enabled.", "example": "SM4E.32 q0, q2", "pseudocode": "Qd ← SM4_Encrypt(Qd, Qm)"} {"mnemonic": "sm4ekey", "architecture": "ARMv8-A", "full_name": "SM4 Key (A32)", "summary": "SM4 key schedule step.", "syntax": "SM4EKEY.32 , ", "encoding": {"format": "Crypto 2-Reg", "binary_pattern": "01000101 | 0 | 0 | 1 | Zm | 11110 | 0 | Zn | Zd", "hex_opcode": "0x4520F000", "visual_parts": [{"raw": "01000101", "clean": "01000101"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "Zm", "clean": "Zm"}, {"raw": "11110", "clean": "11110"}, {"raw": "0", "clean": "0"}, {"raw": "Zn", "clean": "Zn"}, {"raw": "Zd", "clean": "Zd"}], "bit_positions": "31:24 | 23 | 22 | 21 | 20:16 | 15:11 | 10 | 9:5 | 4:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Key"}], "extension": "Crypto (SM4)", "description": "SM4 Key performs one round of SM4 key schedule expansion, computing a derived key from the previous key material. This instruction does not affect condition flags. The instruction is A32-only and requires the Crypto SM4 extension; it generates an Undefined Instruction exception if executed without the extension enabled.", "example": "SM4EKEY.32 q0, q2", "pseudocode": "Qd ← SM4_KeySchedule(Qd, Qm)"} {"mnemonic": "ldaexb", "architecture": "ARMv8-A", "full_name": "Load Acquire Exclusive Byte (A32)", "summary": "Loads a byte, acquires semantics, marks exclusive.", "syntax": "LDAEXB , []", "encoding": {"format": "Load Excl", "binary_pattern": "cond | 00011 | 10 | 1 | Rn | Rt | 1 | 1 | 1 | 0 | 1001 | 1111", "hex_opcode": "0x01D00E9F", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00011", "clean": "00011"}, {"raw": "10", "clean": "10"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rt", "clean": "Rt"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "1001", "clean": "1001"}, {"raw": "1111", "clean": "1111"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rt", "desc": "Transfer general-purpose register (load/store)"}, {"name": "Rn", "desc": "First source / base general-purpose register"}], "extension": "A32 (Atomic)", "description": "Loads a byte from memory at the address in Rn with Acquire semantics and marks the location as exclusive. The loaded byte is zero-extended and placed in Rt. Acquire semantics ensure that subsequent memory operations are not reordered before this load. No condition flags are affected.", "example": "LDAEXB r3, [r1]", "pseudocode": "Rt ← ZeroExtend([Rn], 8); ExclusiveLocal ← TRUE; Acquire()"} {"mnemonic": "ldaexh", "architecture": "ARMv8-A", "full_name": "Load Acquire Exclusive Halfword (A32)", "summary": "Loads a halfword, acquires semantics, marks exclusive.", "syntax": "LDAEXH , []", "encoding": {"format": "Load Excl", "binary_pattern": "cond | 00011 | 11 | 1 | Rn | Rt | 1 | 1 | 1 | 0 | 1001 | 1111", "hex_opcode": "0x01F00E9F", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00011", "clean": "00011"}, {"raw": "11", "clean": "11"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rt", "clean": "Rt"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "1001", "clean": "1001"}, {"raw": "1111", "clean": "1111"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rt", "desc": "Transfer general-purpose register (load/store)"}, {"name": "Rn", "desc": "First source / base general-purpose register"}], "extension": "A32 (Atomic)", "description": "Loads a halfword from memory at the address in Rn with Acquire semantics and marks the location as exclusive. The loaded halfword is zero-extended and placed in Rt. Acquire semantics ensure that subsequent memory operations are not reordered before this load. No condition flags are affected.", "example": "LDAEXH r3, [r1]", "pseudocode": "Rt ← ZeroExtend([Rn], 16); ExclusiveLocal ← TRUE; Acquire()"} {"mnemonic": "ldaexd", "architecture": "ARMv8-A", "full_name": "Load Acquire Exclusive Double (A32)", "summary": "Loads a doubleword, acquires semantics, marks exclusive.", "syntax": "LDAEXD , , []", "encoding": {"format": "Load Excl", "binary_pattern": "cond | 00011 | 01 | 1 | Rn | Rt | 1 | 1 | 1 | 0 | 1001 | 1111", "hex_opcode": "0x01B00E9F", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00011", "clean": "00011"}, {"raw": "01", "clean": "01"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rt", "clean": "Rt"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "1001", "clean": "1001"}, {"raw": "1111", "clean": "1111"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rt", "desc": "Dest 1"}, {"name": "Rt2", "desc": "Dest 2"}, {"name": "Rn", "desc": "First source / base general-purpose register"}], "extension": "A32 (Atomic)", "description": "Loads a doubleword (64 bits) from memory at the address in Rn with Acquire semantics and marks the location as exclusive. The lower 32 bits are placed in Rt and the upper 32 bits in Rt2. Acquire semantics ensure that subsequent memory operations are not reordered before this load. No condition flags are affected.", "example": "LDAEXD r3, r4, [r1]", "pseudocode": "Rt ← [Rn]; Rt2 ← [Rn+4]; ExclusiveLocal ← TRUE; Acquire()"} {"mnemonic": "stlexb", "architecture": "ARMv8-A", "full_name": "Store Release Exclusive Byte (A32)", "summary": "Stores a byte with Release semantics if exclusive.", "syntax": "STLEXB , , []", "encoding": {"format": "Store Excl", "binary_pattern": "cond | 00011 | 10 | 0 | Rn | Rd | 1 | 1 | 1 | 0 | 1001 | Rt", "hex_opcode": "0x01C00E90", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00011", "clean": "00011"}, {"raw": "10", "clean": "10"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "1001", "clean": "1001"}, {"raw": "Rt", "clean": "Rt"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Status"}, {"name": "Rt", "desc": "Transfer general-purpose register (load/store)"}, {"name": "Rn", "desc": "First source / base general-purpose register"}], "extension": "A32 (Atomic)", "description": "Attempts to store a byte to memory at the address in Rn with Release semantics if the location is marked exclusive. The result of the store attempt (0 for success, 1 for failure) is written to Rd. Release semantics ensure that preceding memory operations are not reordered after this store. No condition flags are affected.", "example": "STLEXB r0, r3, [r1]", "pseudocode": "if ExclusiveLocal then [Rn] ← Rt[7:0]; Rd ← 0; Release(); ExclusiveLocal ← FALSE else Rd ← 1 endif"} {"mnemonic": "stlexh", "architecture": "ARMv8-A", "full_name": "Store Release Exclusive Halfword (A32)", "summary": "Stores a halfword with Release semantics if exclusive.", "syntax": "STLEXH , , []", "encoding": {"format": "Store Excl", "binary_pattern": "cond | 00011 | 11 | 0 | Rn | Rd | 1 | 1 | 1 | 0 | 1001 | Rt", "hex_opcode": "0x01E00E90", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00011", "clean": "00011"}, {"raw": "11", "clean": "11"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "1001", "clean": "1001"}, {"raw": "Rt", "clean": "Rt"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Status"}, {"name": "Rt", "desc": "Transfer general-purpose register (load/store)"}, {"name": "Rn", "desc": "First source / base general-purpose register"}], "extension": "A32 (Atomic)", "description": "Stores a halfword to memory with Release semantics if the exclusive monitor is set for the address. Writes a status value (0=success, 1=failure) to Rd and the value from Rt to the memory location addressed by Rn. This is an exclusive store with memory ordering guarantees. No condition flags are affected. Execution state: A32 only; requires privilege level dependent on the accessed address.", "example": "STLEXH r0, r3, [r1]", "pseudocode": "if ExclusiveMonitorsPass(address=Rn, size=2) then\n [Rn] ← Rt[15:0]\n Rd ← 0\n ClearExclusiveMonitors()\nelse\n Rd ← 1"} {"mnemonic": "stlexd", "architecture": "ARMv8-A", "full_name": "Store Release Exclusive Double (A32)", "summary": "Stores a doubleword with Release semantics if exclusive.", "syntax": "STLEXD , , , []", "encoding": {"format": "Store Excl", "binary_pattern": "cond | 00011 | 01 | 0 | Rn | Rd | 1 | 1 | 1 | 0 | 1001 | Rt", "hex_opcode": "0x01A00E90", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00011", "clean": "00011"}, {"raw": "01", "clean": "01"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "1001", "clean": "1001"}, {"raw": "Rt", "clean": "Rt"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Status"}, {"name": "Rt", "desc": "Transfer general-purpose register (load/store)"}, {"name": "Rt2", "desc": "Second transfer register (load/store pair)"}, {"name": "Rn", "desc": "First source / base general-purpose register"}], "extension": "A32 (Atomic)", "description": "Stores a doubleword (64-bit value) to memory with Release semantics if the exclusive monitor is set for the address. The value is loaded from the register pair [Rt, Rt2], and a status is written to Rd (0=success, 1=failure). This is an exclusive store with full Release memory ordering. No condition flags are affected. Execution state: A32 only; Rt must be even-numbered and Rt2=Rt+1.", "example": "STLEXD r0, r3, r4, [r1]", "pseudocode": "if ExclusiveMonitorsPass(address=Rn, size=8) then\n [Rn] ← Rt\n [Rn+4] ← Rt2\n Rd ← 0\n ClearExclusiveMonitors()\nelse\n Rd ← 1"} {"mnemonic": "vcadd", "architecture": "ARMv8-A", "full_name": "Vector Complex Add (A32)", "summary": "Complex integer addition with rotation (NEON).", "syntax": "VCADD.I , , , #", "encoding": {"format": "NEON Complex", "binary_pattern": "1111110 | rot | 1 | D | 0 | S | Vn | Vd | 1 | 0 | 0 | 0 | N | 1 | M | 0 | Vm", "hex_opcode": "0xFC800840", "visual_parts": [{"raw": "1111110", "clean": "1111110"}, {"raw": "rot", "clean": "rot"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "0", "clean": "0"}, {"raw": "S", "clean": "S"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "N", "clean": "N"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}, {"name": "rot", "desc": "Rot"}], "extension": "NEON (Complex)", "description": "Performs complex addition on pairs of elements within 128-bit SIMD registers, treating each pair as a complex number (real, imaginary), with rotation applied before addition. The rotation is either 90° or 270° as specified by rot. Operates on 32-bit or 64-bit element pairs. NEON extension; no condition flags affected.", "example": "VCADD.Isize q0, q1, q2, #rot", "pseudocode": "rotation_angle ← if rot == 0 then 90 else 270\nfor i = 0 to elements_per_128bit_register/2 - 1 do\n real_n ← Qn[2*i]\n imag_n ← Qn[2*i+1]\n real_m ← Qm[2*i]\n imag_m ← Qm[2*i+1]\n rotated_real ← rotate(real_m, imag_m, rotation_angle).real\n rotated_imag ← rotate(real_m, imag_m, rotation_angle).imag\n Qd[2*i] ← real_n + rotated_real\n Qd[2*i+1] ← imag_n + rotated_imag"} {"mnemonic": "vcmla", "architecture": "ARMv8-A", "full_name": "Vector Complex Multiply Accumulate (A32)", "summary": "Complex integer multiply-accumulate with rotation.", "syntax": "VCMLA.I , , , #", "encoding": {"format": "NEON Complex", "binary_pattern": "1111110 | rot | D | 1 | S | Vn | Vd | 1 | 0 | 0 | 0 | N | 1 | M | 0 | Vm", "hex_opcode": "0xFC200840", "visual_parts": [{"raw": "1111110", "clean": "1111110"}, {"raw": "rot", "clean": "rot"}, {"raw": "D", "clean": "D"}, {"raw": "1", "clean": "1"}, {"raw": "S", "clean": "S"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "N", "clean": "N"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24:23 | 22 | 21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}, {"name": "rot", "desc": "Rot"}], "extension": "NEON (Complex)", "description": "Vector Complex Multiply-Accumulate performs complex multiplication of two vectors with a specified rotation (0°, 90°, 180°, or 270°) and accumulates the result into the destination register, operating on 32-bit or 64-bit integer elements. This instruction does not affect condition flags. The instruction is A32-only and requires the NEON Complex extension; it generates an Undefined Instruction exception if executed without the extension enabled.", "example": "VCMLA.Isize q0, q1, q2, #rot", "pseudocode": "for i = 0 to (128 / esize) - 1 do\n real_part = Qn[2*i] * Qm[2*i] - Qn[2*i+1] * Qm[2*i+1]\n imag_part = Qn[2*i] * Qm[2*i+1] + Qn[2*i+1] * Qm[2*i]\n (real_part, imag_part) = RotateByRot(real_part, imag_part, rot)\n Qd[2*i] = Qd[2*i] + real_part\n Qd[2*i+1] = Qd[2*i+1] + imag_part"} {"mnemonic": "vdot", "architecture": "ARMv8-A", "full_name": "Vector BFloat16 Dot Product (A32)", "summary": "BFloat16 dot product to float32 accumulator.", "syntax": "VDOT.BF16 , , ", "encoding": {"format": "NEON BFloat16", "binary_pattern": "1111110 | 00 | D | 00 | Vn | Vd | 1 | 1 | 0 | 1 | N | 1 | M | 0 | Vm", "hex_opcode": "0xFC000D40", "visual_parts": [{"raw": "1111110", "clean": "1111110"}, {"raw": "00", "clean": "00"}, {"raw": "D", "clean": "D"}, {"raw": "00", "clean": "00"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "N", "clean": "N"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24:23 | 22 | 21:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (BFloat16)", "description": "Vector BFloat16 Dot Product computes the dot product of two vectors of BFloat16 (brain floating-point 16-bit) values and accumulates the result as a 32-bit floating-point value in the destination. This instruction does not affect condition flags. The instruction is A32-only and requires the NEON BFloat16 extension; it generates an Undefined Instruction exception if executed without the extension enabled.", "example": "VDOT.BF16 q0, q1, q2", "pseudocode": "for i = 0 to 3 do\n acc = 0.0\n for j = 0 to 1 do\n bf16_a = Qn[4*i + 2*j : 4*i + 2*j + 1]\n bf16_b = Qm[4*i + 2*j : 4*i + 2*j + 1]\n acc = acc + BF16_to_FP32(bf16_a) * BF16_to_FP32(bf16_b)\n Qd[i] = Qd[i] + acc"} {"mnemonic": "vbfmmla", "architecture": "ARMv8-A", "full_name": "Vector BFloat16 Matrix Multiply (A32)", "summary": "BFloat16 matrix multiply-accumulate.", "syntax": "VBFMMLA.BF16 , , ", "encoding": {"format": "NEON BFloat16", "binary_pattern": "11111100 | 0 | 0 | 11 | Vn | Vd | 1100 | N | Q | M | 1 | Vm", "hex_opcode": "0xFC000C40", "visual_parts": [{"raw": "11111100", "clean": "11111100"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11", "clean": "11"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1100", "clean": "1100"}, {"raw": "N", "clean": "N"}, {"raw": "Q", "clean": "Q"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}]}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (BFloat16)", "description": "Multiplies two 128-bit SIMD registers containing BFloat16 (16-bit brain floating-point) elements in 2×2 matrix format and accumulates the result into the destination register. Each 2×2 matrix multiplication processes four BFloat16 values, producing single-precision results that are accumulated. Condition flags (N, Z, C, V) are unaffected. This instruction requires the NEON BFloat16 extension and executes in A32 (ARM) instruction set only.", "example": "VBFMMLA.BF16 q0, q1, q2", "pseudocode": "for i = 0 to 3 do\n // Extract 2x2 BF16 matrix from Qn\n matrix_a[0] = BF16_to_F32(Qn[i*2*16 + 0:15])\n matrix_a[1] = BF16_to_F32(Qn[i*2*16 + 16:31])\n matrix_a[2] = BF16_to_F32(Qn[i*2*16 + 32:47])\n matrix_a[3] = BF16_to_F32(Qn[i*2*16 + 48:63])\n // Extract 2x2 BF16 matrix from Qm\n matrix_b[0] = BF16_to_F32(Qm[i*2*16 + 0:15])\n matrix_b[1] = BF16_to_F32(Qm[i*2*16 + 16:31])\n matrix_b[2] = BF16_to_F32(Qm[i*2*16 + 32:47])\n matrix_b[3] = BF16_to_F32(Qm[i*2*16 + 48:63])\n // Multiply and accumulate\n Qd[i*32 + 0:31] = Qd[i*32 + 0:31] + matrix_a[0] * matrix_b[0] + matrix_a[1] * matrix_b[2]\n Qd[i*32 + 32:63] = Qd[i*32 + 32:63] + matrix_a[2] * matrix_b[0] + matrix_a[3] * matrix_b[2]"} {"mnemonic": "vbfcvt", "architecture": "ARMv8-A", "full_name": "Vector Convert BFloat16 (A32)", "summary": "Converts Float32 to BFloat16.", "syntax": "VBFCVT.BF16.F32 , ", "encoding": {"format": "NEON BFloat16", "binary_pattern": "11110011 | 1 | D | 11 | 01 | 10 | Vd | 00110 | Q | M | 0 | Vm", "hex_opcode": "0xF3B60640", "visual_parts": [{"raw": "11110011", "clean": "11110011"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "01", "clean": "01"}, {"raw": "10", "clean": "10"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "00110", "clean": "00110"}, {"raw": "Q", "clean": "Q"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}]}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (BFloat16)", "description": "Converts 128-bit SIMD register containing single-precision floating-point elements to BFloat16 (16-bit brain floating-point) format by rounding the mantissa to 7 bits and preserving the sign and exponent. The result is stored as 64 BFloat16 elements in the destination 128-bit register. Condition flags are unaffected. This instruction requires the NEON BFloat16 extension and executes in A32 (ARM) instruction set only.", "example": "VBFCVT.BF16.F32 q0, q2", "pseudocode": "for i = 0 to 3 do\n f32_val = Qm[i*32 + 0:31]\n bf16_val = F32_to_BF16(f32_val)\n Qd[i*16 + 0:15] = bf16_val"} {"mnemonic": "vusdot", "architecture": "ARMv8-A", "full_name": "Vector Unsigned-Signed Dot Product (A32)", "summary": "Dot product of unsigned (src1) and signed (src2) bytes.", "syntax": "VUSDOT.S8 , , ", "encoding": {"format": "NEON DotProd", "binary_pattern": "1111110 | 01 | D | 10 | Vn | Vd | 1 | 1 | 0 | 1 | N | 1 | M | 0 | Vm", "hex_opcode": "0xFCA00D40", "visual_parts": [{"raw": "1111110", "clean": "1111110"}, {"raw": "01", "clean": "01"}, {"raw": "D", "clean": "D"}, {"raw": "10", "clean": "10"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "N", "clean": "N"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24:23 | 22 | 21:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "Unsigned"}, {"name": "Qm", "desc": "Signed"}], "extension": "NEON (DotProd)", "description": "Computes the dot product of unsigned 8-bit integers from Qn and signed 8-bit integers from Qm, accumulating four dot products (one per 32-bit lane) into the corresponding 32-bit signed integer elements of Qd. Each lane multiplies and sums four pairs of unsigned×signed bytes. Condition flags are unaffected. This instruction requires the NEON DotProd extension and executes in A32 (ARM) instruction set only.", "example": "VUSDOT.S8 q0, q1, q2", "pseudocode": "for i = 0 to 3 do\n acc = Qd[i*32 + 0:31]\n for j = 0 to 3 do\n unsigned_byte = ZeroExtend(Qn[(i*4 + j)*8 + 0:7])\n signed_byte = SignExtend(Qm[(i*4 + j)*8 + 0:7])\n acc = acc + (unsigned_byte * signed_byte)\n Qd[i*32 + 0:31] = acc"} {"mnemonic": "vsmmla", "architecture": "ARMv8-A", "full_name": "Vector Signed Int8 Matrix Multiply (A32)", "summary": "Matrix multiply-accumulate (Signed Int8).", "syntax": "VSMMLA.S8 , , ", "encoding": {"format": "NEON MatMul", "binary_pattern": "1111110 | 0 | 0 | D | 10 | Vn | Vd | 1 | 1 | 0 | 0 | N | 1 | M | 0 | Vm", "hex_opcode": "0xFC200C40", "visual_parts": [{"raw": "1111110", "clean": "1111110"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "10", "clean": "10"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "N", "clean": "N"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (MatMul)", "description": "Multiplies two 128-bit SIMD registers containing signed 8-bit integer elements in 4×4 matrix format and accumulates the result into the destination register as signed 32-bit integers. Processes four 4×4 matrices, each producing four 32-bit signed results that are added to Qd. Condition flags are unaffected. This instruction requires the NEON MatMul extension and executes in A32 (ARM) instruction set only.", "example": "VSMMLA.S8 q0, q1, q2", "pseudocode": "for i = 0 to 3 do\n // Extract 4x4 S8 matrix from Qn\n for r = 0 to 3 do\n for c = 0 to 3 do\n matrix_a[r][c] = SignExtend(Qn[(i*16 + r*4 + c)*8 + 0:7])\n // Extract 4x4 S8 matrix from Qm\n for r = 0 to 3 do\n for c = 0 to 3 do\n matrix_b[r][c] = SignExtend(Qm[(i*16 + r*4 + c)*8 + 0:7])\n // Multiply and accumulate\n for r = 0 to 3 do\n result = Qd[(i*4 + r)*32 + 0:31]\n for k = 0 to 3 do\n result = result + matrix_a[r][k] * matrix_b[k][r]\n Qd[(i*4 + r)*32 + 0:31] = result"} {"mnemonic": "vusmmla", "architecture": "ARMv8-A", "full_name": "Vector Unsigned-Signed Matrix Multiply (A32)", "summary": "Matrix multiply-accumulate (Unsigned x Signed Int8).", "syntax": "VUSMMLA.S8 , , ", "encoding": {"format": "NEON MatMul", "binary_pattern": "1111110 | 0 | 1 | D | 10 | Vn | Vd | 1 | 1 | 0 | 0 | N | 1 | M | 0 | Vm", "hex_opcode": "0xFCA00C40", "visual_parts": [{"raw": "1111110", "clean": "1111110"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "10", "clean": "10"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "N", "clean": "N"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "Unsigned"}, {"name": "Qm", "desc": "Signed"}], "extension": "NEON (MatMul)", "description": "Multiplies two 128-bit SIMD registers containing unsigned 8-bit integers from Qn and signed 8-bit integers from Qm in 4×4 matrix format and accumulates the result into the destination register as signed 32-bit integers. Processes four 4×4 matrices, each producing four 32-bit signed results. Condition flags are unaffected. This instruction requires the NEON MatMul extension and executes in A32 (ARM) instruction set only.", "example": "VUSMMLA.S8 q0, q1, q2", "pseudocode": "for i = 0 to 3 do\n // Extract 4x4 U8 matrix from Qn\n for r = 0 to 3 do\n for c = 0 to 3 do\n matrix_a[r][c] = ZeroExtend(Qn[(i*16 + r*4 + c)*8 + 0:7])\n // Extract 4x4 S8 matrix from Qm\n for r = 0 to 3 do\n for c = 0 to 3 do\n matrix_b[r][c] = SignExtend(Qm[(i*16 + r*4 + c)*8 + 0:7])\n // Multiply and accumulate\n for r = 0 to 3 do\n result = Qd[(i*4 + r)*32 + 0:31]\n for k = 0 to 3 do\n result = result + matrix_a[r][k] * matrix_b[k][r]\n Qd[(i*4 + r)*32 + 0:31] = result"} {"mnemonic": "vummla", "architecture": "ARMv8-A", "full_name": "Vector Unsigned Matrix Multiply (A32)", "summary": "Matrix multiply-accumulate (Unsigned Int8).", "syntax": "VUMMLA.U8 , , ", "encoding": {"format": "NEON MatMul", "binary_pattern": "1111110 | 0 | 0 | D | 10 | Vn | Vd | 1 | 1 | 0 | 0 | N | 1 | M | 1 | Vm", "hex_opcode": "0xFC200C50", "visual_parts": [{"raw": "1111110", "clean": "1111110"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "10", "clean": "10"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "N", "clean": "N"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (MatMul)", "description": "Multiplies two 128-bit SIMD registers containing unsigned 8-bit integer elements in 4×4 matrix format and accumulates the result into the destination register as unsigned 32-bit integers. Processes four 4×4 matrices, each producing four 32-bit unsigned results that are added to Qd. Condition flags are unaffected. This instruction requires the NEON MatMul extension and executes in A32 (ARM) instruction set only.", "example": "VUMMLA.U8 q0, q1, q2", "pseudocode": "for i = 0 to 3 do\n // Extract 4x4 U8 matrix from Qn\n for r = 0 to 3 do\n for c = 0 to 3 do\n matrix_a[r][c] = ZeroExtend(Qn[(i*16 + r*4 + c)*8 + 0:7])\n // Extract 4x4 U8 matrix from Qm\n for r = 0 to 3 do\n for c = 0 to 3 do\n matrix_b[r][c] = ZeroExtend(Qm[(i*16 + r*4 + c)*8 + 0:7])\n // Multiply and accumulate\n for r = 0 to 3 do\n result = Qd[(i*4 + r)*32 + 0:31]\n for k = 0 to 3 do\n result = result + matrix_a[r][k] * matrix_b[k][r]\n Qd[(i*4 + r)*32 + 0:31] = result"} {"mnemonic": "vjcvt", "architecture": "ARMv8-A", "full_name": "Vector Javascript Convert (A32)", "summary": "Converts double to signed 32-bit integer (JS semantics).", "syntax": "VJCVT.S32.F64 , ", "encoding": {"format": "VFP Convert", "binary_pattern": "cond | 11101 | D | 11 | 1 | 001 | Vd | 10 | 11 | 1 | 1 | M | 0 | Vm", "hex_opcode": "0x0EB90BC0", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "11101", "clean": "11101"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "1", "clean": "1"}, {"raw": "001", "clean": "001"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "11", "clean": "11"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}, {"name": "Dm", "desc": "Second source 64-bit SIMD/FP register"}], "extension": "VFP (JS)", "description": "Converts a 64-bit double-precision floating-point value to a signed 32-bit integer using JavaScript semantics (NaN maps to 0, out-of-range values saturate). The result is stored as a single-precision floating-point value in the destination 32-bit register. Condition flags are unaffected. This instruction requires the VFP JavaScript extension and executes in A32 (ARM) instruction set only.", "example": "VJCVT.S32.F64 s0, d2", "pseudocode": "f64_val = Dm[0:63]\nif IsNaN(f64_val) then\n s32_val = 0\nelse if f64_val > 2147483647.0 then\n s32_val = 2147483647\nelse if f64_val < -2147483648.0 then\n s32_val = -2147483648\nelse\n s32_val = RoundTowardsZero(f64_val)\nSd[0:31] = F32(s32_val)"} {"mnemonic": "pldw", "architecture": "ARMv8-A", "full_name": "Preload Data for Write (A32)", "summary": "Hints memory system to bring data into cache for writing.", "syntax": "PLDW [, #]", "encoding": {"format": "Load/Store", "binary_pattern": "1111010 | 1 | U | 0 | 01 | Rn | 1 | 1 | 1 | 1 | imm12", "hex_opcode": "0xF510F000", "visual_parts": [{"raw": "1111010", "clean": "1111010"}, {"raw": "1", "clean": "1"}, {"raw": "U", "clean": "U"}, {"raw": "0", "clean": "0"}, {"raw": "01", "clean": "01"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "imm12", "clean": "imm12"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15 | 14 | 13 | 12 | 11:0"}, "operands": [{"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "imm", "desc": "Signed immediate value"}], "extension": "A32 (Base)", "description": "Preloads data for write by hinting the memory system to allocate cache line(s) in an exclusive state at the address computed from the base register and 12-bit immediate offset. This is a hint instruction and does not cause exceptions on address translation or access faults. Condition flags and general-purpose registers are unaffected. This instruction executes in A32 (ARM) instruction set only.", "example": "PLDW [r1, #16]", "pseudocode": "address = Rn + imm12\n// Hint to memory system to preload for exclusive access (write)\nPreloadDataForWrite(address)"} {"mnemonic": "pldw", "architecture": "ARMv8-A", "full_name": "Preload Data for Write (Thumb)", "summary": "Hints memory system to bring data into cache for writing (Thumb).", "syntax": "PLDW [, #]", "encoding": {"format": "Thumb Load/Store", "binary_pattern": "111110001 | 0 | 1 | 1 | Rn | 1111 | imm12", "hex_opcode": "0xF8B0F000", "visual_parts": [{"raw": "111110001", "clean": "111110001"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "1111", "clean": "1111"}, {"raw": "imm12", "clean": "imm12"}], "bit_positions": "31:23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:0"}, "operands": [{"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "imm", "desc": "Signed immediate value"}], "extension": "T32 (Thumb2)", "description": "Preload Data for Write provides a hint to the memory system to bring a cache line into the cache hierarchy in preparation for a write operation. The instruction does not modify any registers or condition flags and serves only as a performance optimization hint. It is available in Thumb (T32) instruction set and has no architectural side effects if the hint is ignored.", "example": "PLDW [r1, #16]", "pseudocode": "// Hint to memory system to preload data for write at address [Rn + imm]\n// No architectural effect on registers or flags\nHint_PreloadForWrite(address: Rn + imm)"} {"mnemonic": "sb", "architecture": "ARMv8-A", "full_name": "Speculation Barrier (A32)", "summary": "Prevents speculative execution across the barrier (v8.0).", "syntax": "SB", "encoding": {"format": "System Hint", "binary_pattern": "111101010111 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0111 | 0000", "hex_opcode": "0xF57FF070", "visual_parts": [{"raw": "111101010111", "clean": "111101010111"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0111", "clean": "0111"}, {"raw": "0000", "clean": "0000"}], "bit_positions": "31:20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7:4 | 3:0"}, "operands": [], "extension": "A32 (v8.0)", "description": "Speculation Barrier (v8.0) prevents speculative execution from crossing the barrier in either direction, creating a serialization point for instruction execution. This instruction acts as a full execution barrier that completes all prior instructions before allowing subsequent instructions to execute speculatively. Available in A32 instruction set; does not modify condition flags.", "example": "SB", "pseudocode": "// Serialize execution; prevent speculative execution across this point\nSpeculationBarrier()\n// All prior instructions complete before any subsequent instruction executes speculatively"} {"mnemonic": "ssbb", "architecture": "ARMv8-A", "full_name": "Speculative Store Bypass Barrier (A32)", "summary": "Prevents speculative loads bypassing earlier stores (v8.0).", "syntax": "SSBB", "encoding": {"format": "System Hint", "binary_pattern": "111101010111 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0100 | 0000", "hex_opcode": "0xF57FF040", "visual_parts": [{"raw": "111101010111", "clean": "111101010111"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0100", "clean": "0100"}, {"raw": "0000", "clean": "0000"}], "bit_positions": "31:20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7:4 | 3:0"}, "operands": [], "extension": "A32 (v8.0)", "description": "Speculative Store Bypass Barrier (v8.0) prevents speculative loads from bypassing earlier stores, ensuring that load operations wait for all prior store operations to complete. This is a lighter-weight barrier than SB, specifically targeting store-to-load forwarding speculation. Available in A32 instruction set; does not modify condition flags.", "example": "SSBB", "pseudocode": "// Prevent speculative load execution past prior stores\nStoreBypassBarrier()\n// All prior stores complete before subsequent loads can execute"} {"mnemonic": "pssbb", "architecture": "ARMv8-A", "full_name": "Physical Speculative Store Bypass Barrier (A32)", "summary": "Prevents speculation on physical resources (v8.0).", "syntax": "PSSBB", "encoding": {"format": "System Hint", "binary_pattern": "111101010111 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0100 | 0100", "hex_opcode": "0xF57FF044", "visual_parts": [{"raw": "111101010111", "clean": "111101010111"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0100", "clean": "0100"}, {"raw": "0100", "clean": "0100"}], "bit_positions": "31:20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7:4 | 3:0"}, "operands": [], "extension": "A32 (v8.0)", "description": "Physical Speculative Store Bypass Barrier (v8.0) prevents speculative load bypassing on physical memory operations, operating at a more restrictive level than SSBB by affecting physical resource speculation. This barrier is typically used in security contexts to prevent cross-VM or cross-process speculation. Available in A32 instruction set; does not modify condition flags.", "example": "PSSBB", "pseudocode": "// Prevent speculative load bypass on physical resources\nPhysicalStoreBypassBarrier()\n// All prior physical stores complete before subsequent loads can execute on physical resources"} {"mnemonic": "tsb", "architecture": "ARMv8-A", "full_name": "Trace Synchronization Barrier (A32)", "summary": "Ensures trace generation is complete (v8.2).", "syntax": "TSB CSYNC", "encoding": {"format": "System Hint", "binary_pattern": "cond | 00110 | 0 | 10 | 0000 | 1 | 1 | 1 | 1 | 000000010010", "hex_opcode": "0x0320F012", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00110", "clean": "00110"}, {"raw": "0", "clean": "0"}, {"raw": "10", "clean": "10"}, {"raw": "0000", "clean": "0000"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "000000010010", "clean": "000000010010"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15 | 14 | 13 | 12 | 11:0"}, "operands": [], "extension": "A32 (Trace)", "description": "Trace Synchronization Barrier with CSYNC operand (v8.2) ensures that trace generation is synchronized and complete before subsequent instructions execute, used to maintain consistency in trace output. This instruction is primarily used in debug and tracing scenarios and does not modify general-purpose registers or condition flags. Available in A32 instruction set.", "example": "TSB CSYNC", "pseudocode": "// Synchronize trace generation (CSYNC variant)\nTraceBarrier(CSYNC)\n// Trace context switches complete before proceeding"} {"mnemonic": "dfb", "architecture": "ARMv8-A", "full_name": "Debug Flush Barrier (A32)", "summary": "Deprecated alias for DSB.", "syntax": "DFB", "encoding": {"format": "System Hint", "binary_pattern": "11110101011111111111000001001100", "hex_opcode": "0xF57FF04C", "visual_parts": [{"raw": "11110101011111111111000001001100", "clean": "11110101011111111111000001001100"}]}, "operands": [], "extension": "A32 (Legacy)", "description": "Debug Flush Barrier (Legacy) is a deprecated alias for DSB that is retained for compatibility; it flushes the debug pipeline and ensures all debug operations complete. This instruction should not be used in new code as it is superseded by explicit DSB instructions. Available in A32 instruction set; does not modify condition flags.", "example": "DFB", "pseudocode": "// Deprecated: Flush debug pipeline (equivalent to DSB)\nDebugFlushBarrier()\n// All debug operations complete (legacy behavior)"} {"mnemonic": "bxj", "architecture": "ARMv8-A", "full_name": "Branch and Exchange Jazelle (A32)", "summary": "Legacy instruction to enter Jazelle state (Now behaves like BX).", "syntax": "BXJ ", "encoding": {"format": "Branch", "binary_pattern": "cond | 00010010 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0010 | Rm", "hex_opcode": "0x012FFF20", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00010010", "clean": "00010010"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0010", "clean": "0010"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (Legacy)", "description": "Legacy instruction that branches to the address in Rm with exchange (Thumb/ARM mode switching based on bit [0] of Rm). In current ARMv8 architecture, BXJ behaves identically to BX due to Jazelle being obsolete. Bit [0] of Rm determines the target state (0=ARM, 1=Thumb). No condition flags are affected. Execution state: A32 only.", "example": "BXJ r2", "pseudocode": "next_address ← Rm\nif next_address[0] == 1 then\n CPSR.T ← 1\nelse\n CPSR.T ← 0\nPC ← next_address AND NOT(0x1)"} {"mnemonic": "vrintm", "architecture": "ARMv8-A", "full_name": "Vector Round Floating-Point (Minus Infinity)", "summary": "Rounds float towards Minus Infinity (Floor).", "syntax": "VRINTM.F32 , ", "encoding": {"format": "VFP Unary", "binary_pattern": "111111101 | D | 111 | 0 | 11 | Vd | 10 | 10 | 0 | 1 | M | 0 | Vm", "hex_opcode": "0xFEBB0A40", "visual_parts": [{"raw": "111111101", "clean": "111111101"}, {"raw": "D", "clean": "D"}, {"raw": "111", "clean": "111"}, {"raw": "0", "clean": "0"}, {"raw": "11", "clean": "11"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:19 | 18 | 17:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}, {"name": "Sm", "desc": "Second source 32-bit floating-point register"}], "extension": "VFP (Float)", "description": "Rounds a 32-bit floating-point value towards minus infinity (floor) and stores the result in the destination register. This instruction does not modify the condition code flags. It is available in A32 and T32 with the VFP extension, and requires floating-point support.", "example": "VRINTM.F32 s0, s2", "pseudocode": "Sd ← RoundTowardMinusInfinity(Sm)"} {"mnemonic": "vrintp", "architecture": "ARMv8-A", "full_name": "Vector Round Floating-Point (Plus Infinity)", "summary": "Rounds float towards Plus Infinity (Ceil).", "syntax": "VRINTP.F32 , ", "encoding": {"format": "VFP Unary", "binary_pattern": "111111101 | D | 111 | 0 | 10 | Vd | 10 | 10 | 0 | 1 | M | 0 | Vm", "hex_opcode": "0xFEBA0A40", "visual_parts": [{"raw": "111111101", "clean": "111111101"}, {"raw": "D", "clean": "D"}, {"raw": "111", "clean": "111"}, {"raw": "0", "clean": "0"}, {"raw": "10", "clean": "10"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "10", "clean": "10"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:19 | 18 | 17:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}, {"name": "Sm", "desc": "Second source 32-bit floating-point register"}], "extension": "VFP (Float)", "description": "Rounds a 32-bit floating-point value towards plus infinity (ceiling) and stores the result in the destination register. This instruction does not modify the condition code flags. It is available in A32 and T32 with the VFP extension, and requires floating-point support.", "example": "VRINTP.F32 s0, s2", "pseudocode": "Sd ← RoundTowardPlusInfinity(Sm)"} {"mnemonic": "vrintm", "architecture": "ARMv8-A", "full_name": "Vector Round Floating-Point Double (Minus Infinity)", "summary": "Rounds double towards Minus Infinity (Floor).", "syntax": "VRINTM.F64
, ", "encoding": {"format": "VFP Unary", "binary_pattern": "111111101 | D | 111 | 0 | 11 | Vd | 10 | 11 | 0 | 1 | M | 0 | Vm", "hex_opcode": "0xFEBB0B40", "visual_parts": [{"raw": "111111101", "clean": "111111101"}, {"raw": "D", "clean": "D"}, {"raw": "111", "clean": "111"}, {"raw": "0", "clean": "0"}, {"raw": "11", "clean": "11"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "11", "clean": "11"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:19 | 18 | 17:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Dd", "desc": "Destination 64-bit SIMD/FP register"}, {"name": "Dm", "desc": "Second source 64-bit SIMD/FP register"}], "extension": "VFP (Float)", "description": "Rounds a 64-bit floating-point value towards minus infinity (floor) and stores the result in the destination register. This instruction does not modify the condition code flags. It is available in A32 and T32 with the VFP extension, and requires floating-point support.", "example": "VRINTM.F64 d0, d2", "pseudocode": "Dd ← RoundTowardMinusInfinity(Dm)"} {"mnemonic": "vrintp", "architecture": "ARMv8-A", "full_name": "Vector Round Floating-Point Double (Plus Infinity)", "summary": "Rounds double towards Plus Infinity (Ceil).", "syntax": "VRINTP.F64
, ", "encoding": {"format": "VFP Unary", "binary_pattern": "111111101 | D | 111 | 0 | 10 | Vd | 10 | 11 | 0 | 1 | M | 0 | Vm", "hex_opcode": "0xFEBA0B40", "visual_parts": [{"raw": "111111101", "clean": "111111101"}, {"raw": "D", "clean": "D"}, {"raw": "111", "clean": "111"}, {"raw": "0", "clean": "0"}, {"raw": "10", "clean": "10"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "11", "clean": "11"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:19 | 18 | 17:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Dd", "desc": "Destination 64-bit SIMD/FP register"}, {"name": "Dm", "desc": "Second source 64-bit SIMD/FP register"}], "extension": "VFP (Float)", "description": "Rounds a 64-bit floating-point value towards plus infinity (ceiling) and stores the result in the destination register. This instruction does not modify the condition code flags. It is available in A32 and T32 with the VFP extension, and requires floating-point support.", "example": "VRINTP.F64 d0, d2", "pseudocode": "Dd ← RoundTowardPlusInfinity(Dm)"} {"mnemonic": "hlt", "architecture": "ARMv8-A", "full_name": "Halting Debug (A32)", "summary": "Enters halting debug state (A32 encoding).", "syntax": "HLT #", "encoding": {"format": "System", "binary_pattern": "cond | 00010 | 00 | 0 | imm12 | 0111 | imm4", "hex_opcode": "0x01000070", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00010", "clean": "00010"}, {"raw": "00", "clean": "00"}, {"raw": "0", "clean": "0"}, {"raw": "imm12", "clean": "imm12"}, {"raw": "0111", "clean": "0111"}, {"raw": "imm4", "clean": "imm4"}], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:8 | 7:4 | 3:0"}, "operands": [{"name": "imm", "desc": "ID"}], "extension": "A32 (Base)", "description": "Halts execution and enters the debugger, with an optional 16-bit immediate value providing debug information. The instruction is unconditional in A32 and causes an exception to the debugger if enabled, otherwise it behaves as an unpredictable instruction. This is an A32-only instruction and is typically privileged.", "example": "HLT #16", "pseudocode": "DebugState ← Halted; DebugID ← imm16"} {"mnemonic": "msr", "architecture": "ARMv8-A", "full_name": "Move Immediate to Special Register (A32)", "summary": "Writes an immediate to a status register (A32).", "syntax": "MSR , #", "encoding": {"format": "System", "binary_pattern": "cond | 00110 | R | 10 | mask | 1 | 1 | 1 | 1 | imm12", "hex_opcode": "0x0320F000", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00110", "clean": "00110"}, {"raw": "R", "clean": "R"}, {"raw": "10", "clean": "10"}, {"raw": "mask", "clean": "mask"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "imm12", "clean": "imm12"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15 | 14 | 13 | 12 | 11:0"}, "operands": [{"name": "spec_reg", "desc": "CPSR/SPSR"}, {"name": "imm", "desc": "Value"}], "extension": "A32 (System)", "description": "Writes an immediate value to a status register (CPSR or SPSR) with mask control in A32. The immediate is expanded by a rotate amount encoded in the instruction. Only the register fields specified by the mask are updated. This is a privileged instruction if writing to SPSR or certain CPSR fields. Condition flags (N, Z, C, V) may be updated depending on mask. Execution state: A32 only.", "example": "MSR nzcv, #16", "pseudocode": "imm_value ← rotate_right(imm8, 2 * rotate)\nif spec_reg == CPSR then\n if mask[0] then CPSR[7:0] ← imm_value[7:0]\n if mask[1] then CPSR[15:8] ← imm_value[15:8]\n if mask[2] then CPSR[23:16] ← imm_value[23:16]\n if mask[3] then CPSR[31:24] ← imm_value[31:24]\nelse if spec_reg == SPSR then\n if mask[0] then SPSR[7:0] ← imm_value[7:0]\n if mask[1] then SPSR[15:8] ← imm_value[15:8]\n if mask[2] then SPSR[23:16] ← imm_value[23:16]\n if mask[3] then SPSR[31:24] ← imm_value[31:24]"} {"mnemonic": "msr", "architecture": "ARMv8-A", "full_name": "Move Immediate to Special Register (Thumb)", "summary": "Writes an immediate to a status register (Thumb).", "syntax": "MSR , #", "encoding": {"format": "Thumb System", "binary_pattern": "11110011100 | R | Rn | 10 | 0 | 0 | mask | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0", "hex_opcode": "0xF3808000", "visual_parts": [{"raw": "11110011100", "clean": "11110011100"}, {"raw": "R", "clean": "R"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "10", "clean": "10"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "mask", "clean": "mask"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}], "bit_positions": "31:21 | 20 | 19:16 | 15:14 | 13 | 12 | 11:8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0"}, "operands": [{"name": "spec_reg", "desc": "CPSR/SPSR"}, {"name": "imm", "desc": "Value"}], "extension": "T32 (System)", "description": "Writes an immediate value to a status register (CPSR or SPSR) in T32/Thumb state. The immediate is zero-extended and only the lowest 8 bits are used to update certain CPSR/SPSR fields. This is a privileged instruction. Condition flags may be modified based on the target register and field selection. Execution state: T32 only.", "example": "MSR nzcv, #16", "pseudocode": "imm_value ← ZeroExtend(imm8, 32)\nif spec_reg == CPSR then\n CPSR[31:24] ← imm_value[31:24]\nelse if spec_reg == SPSR then\n SPSR[31:24] ← imm_value[31:24]"} {"mnemonic": "eret", "architecture": "ARMv8-A", "full_name": "Exception Return (A32)", "summary": "Returns from an exception (A32).", "syntax": "ERET", "encoding": {"format": "System", "binary_pattern": "cond | 00010110 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0110 | 1 | 1 | 1 | 0", "hex_opcode": "0x0160006E", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "00010110", "clean": "00010110"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0110", "clean": "0110"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}], "bit_positions": "31:28 | 27:20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7:4 | 3 | 2 | 1 | 0"}, "operands": [], "extension": "A32 (System)", "description": "Returns from an exception by restoring the PC from ELR_ELx and the PSTATE from SPSR_ELx. This instruction is unconditional and is only available in A32 AArch32 execution state. It requires privilege level sufficient to execute exception-handling code (typically EL1 or higher) and is used at the end of exception handlers.", "example": "ERET", "pseudocode": "PC ← ELR_ELx; PSTATE ← SPSR_ELx"} {"mnemonic": "subs", "architecture": "ARMv8-A", "full_name": "Subtract and Return (A32)", "summary": "Subs PC, LR, #imm (Exception return mechanism).", "syntax": "SUBS PC, LR, #", "encoding": {"format": "Data Proc", "binary_pattern": "cond | 0010 | 010 | 1 | Rn | Rd | imm12", "hex_opcode": "0x02500000", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "0010", "clean": "0010"}, {"raw": "010", "clean": "010"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "imm12", "clean": "imm12"}], "bit_positions": "31:28 | 27:24 | 23:21 | 20 | 19:16 | 15:12 | 11:0"}, "operands": [{"name": "imm", "desc": "Signed immediate value"}], "extension": "A32 (Base)", "description": "Subtracts an immediate from the LR register and stores the result in PC, causing an exception return with automatic CPSR restoration from SPSR. All condition flags (N, Z, C, V) are updated from the subtraction result. This instruction is the preferred exception return mechanism in A32 and must execute in a privileged mode. Execution state: A32 only.", "example": "SUBS PC, LR, #16", "pseudocode": "result ← LR - imm12\nN ← result[31]\nZ ← (result == 0)\nC ← (LR >= imm12) \nV ← OverflowFrom(LR - imm12)\nPC ← result\nCPSR ← SPSR"} {"mnemonic": "ldr", "architecture": "ARMv8-A", "full_name": "Load Register PC-Relative (A32)", "summary": "Loads a word from a label.", "syntax": "LDR ,
, .", "encoding": {"format": "NEON Scalar", "binary_pattern": "01011110 | 11110001 | 101110 | Rn | Rd", "hex_opcode": "0x5E31B800", "visual_parts": [{"raw": "01011110", "clean": "01011110"}, {"raw": "11110001", "clean": "11110001"}, {"raw": "101110", "clean": "101110"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}]}, "operands": [{"name": "Dd", "desc": "Destination 64-bit SIMD/FP register"}, {"name": "Vn", "desc": "First source SIMD/FP vector register"}], "extension": "NEON (Scalar)", "description": "Adds the two 64-bit elements of a NEON vector register pairwise and stores the scalar 64-bit result in a destination register. Condition flags (N, Z, C, V) are set according to the result. AArch64 only with NEON extension.", "example": "ADDP d0, v1.4s.T", "pseudocode": "result ← (Vn[0] as i64) + (Vn[1] as i64)\nDd ← result\nN ← result[63]\nZ ← (result == 0)\nC ← Carry_Out(Vn[0], Vn[1])\nV ← Overflow_From_Add(Vn[0], Vn[1])"} {"mnemonic": "fmaxv", "architecture": "ARMv8-A", "full_name": "Floating-Point Maximum Reduction (NEON)", "summary": "Finds max float in a vector.", "syntax": "FMAXV , .", "encoding": {"format": "NEON Reduction", "binary_pattern": "0 | Q | 0 | 01110 | 0 | 011000 | 01111 | 10 | Rn | Rd", "hex_opcode": "0x0E30F800", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "Q", "clean": "Q"}, {"raw": "0", "clean": "0"}, {"raw": "01110", "clean": "01110"}, {"raw": "0", "clean": "0"}, {"raw": "011000", "clean": "011000"}, {"raw": "01111", "clean": "01111"}, {"raw": "10", "clean": "10"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23 | 22:17 | 16:12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}, {"name": "Vn", "desc": "First source SIMD/FP vector register"}], "extension": "NEON (v8.0)", "description": "Floating-point maximum reduction across vector elements. Scans all floating-point elements in the source vector and writes the maximum value to the destination scalar register. FPSR is updated with cumulative exception flags from all comparisons; condition flags (N, Z, C, V) are unaffected. AArch64-only instruction requiring NEON support.", "example": "FMAXV s0, v1.4s.T", "pseudocode": "elements ← VecReduction(Vn, 'max')\nSd ← FPMaxReduction(elements)\nFPSR.IOC ← FPSRAccum from comparisons"} {"mnemonic": "fminv", "architecture": "ARMv8-A", "full_name": "Floating-Point Minimum Reduction (NEON)", "summary": "Finds min float in a vector.", "syntax": "FMINV , .", "encoding": {"format": "NEON Reduction", "binary_pattern": "0 | Q | 0 | 01110 | 1 | 011000 | 01111 | 10 | Rn | Rd", "hex_opcode": "0x0EB0F800", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "Q", "clean": "Q"}, {"raw": "0", "clean": "0"}, {"raw": "01110", "clean": "01110"}, {"raw": "1", "clean": "1"}, {"raw": "011000", "clean": "011000"}, {"raw": "01111", "clean": "01111"}, {"raw": "10", "clean": "10"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23 | 22:17 | 16:12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}, {"name": "Vn", "desc": "First source SIMD/FP vector register"}], "extension": "NEON (v8.0)", "description": "Floating-point minimum reduction across vector elements. Scans all floating-point elements in the source vector and writes the minimum value to the destination scalar register. FPSR is updated with cumulative exception flags from all comparisons; condition flags (N, Z, C, V) are unaffected. AArch64-only instruction requiring NEON support.", "example": "FMINV s0, v1.4s.T", "pseudocode": "elements ← VecReduction(Vn, 'min')\nSd ← FPMinReduction(elements)\nFPSR.IOC ← FPSRAccum from comparisons"} {"mnemonic": "frint32x", "architecture": "ARMv8-A", "full_name": "Floating-Point Round to 32-bit Integer (Exact)", "summary": "Rounds to 32-bit integer, exact exception.", "syntax": "FRINT32X , ", "encoding": {"format": "Float Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 10100 | 01 | 10000 | Rn | Rd", "hex_opcode": "0x1E28C000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "10100", "clean": "10100"}, {"raw": "01", "clean": "01"}, {"raw": "10000", "clean": "10000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:17 | 16:15 | 14:10 | 9:5 | 4:0"}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}, {"name": "Sn", "desc": "First source 32-bit floating-point register"}], "extension": "FEAT_FRINTTS", "description": "Rounds a 32-bit floating-point value to the nearest 32-bit integer value using the current rounding mode, signaling an inexact exception. Condition flags are unaffected. Requires FEAT_FRINTTS; AArch64 only.", "example": "FRINT32X s0, s1", "pseudocode": "result ← FP_RoundToInt(Sn, RMode_FromFPCR, exact=true)\nif result != Sn\n FP_InexactException()\nSd ← result"} {"mnemonic": "frint32z", "architecture": "ARMv8-A", "full_name": "Floating-Point Round to 32-bit Integer (Zero)", "summary": "Rounds to 32-bit integer towards zero.", "syntax": "FRINT32Z , ", "encoding": {"format": "Float Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 10100 | 00 | 10000 | Rn | Rd", "hex_opcode": "0x1E284000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "10100", "clean": "10100"}, {"raw": "00", "clean": "00"}, {"raw": "10000", "clean": "10000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:17 | 16:15 | 14:10 | 9:5 | 4:0"}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}, {"name": "Sn", "desc": "First source 32-bit floating-point register"}], "extension": "FEAT_FRINTTS", "description": "Rounds the source single-precision floating-point value to a 32-bit signed integer using round towards zero (truncate) rounding mode, and writes the result as a single-precision floating-point value to the destination. Does not update the NZCV condition flags. Requires FEAT_FRINTTS extension; AArch64 only.", "example": "FRINT32Z s0, s1", "pseudocode": "Xn_bits ← Sn\nint32_val ← RoundTowardsZero(FPUnpack(Xn_bits), 32)\nSd ← FPPack(int32_val as single-precision floating-point)"} {"mnemonic": "frint64x", "architecture": "ARMv8-A", "full_name": "Floating-Point Round to 64-bit Integer (Exact)", "summary": "Rounds to 64-bit integer, exact exception.", "syntax": "FRINT64X , ", "encoding": {"format": "Float Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 10100 | 11 | 10000 | Rn | Rd", "hex_opcode": "0x1E29C000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "10100", "clean": "10100"}, {"raw": "11", "clean": "11"}, {"raw": "10000", "clean": "10000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:17 | 16:15 | 14:10 | 9:5 | 4:0"}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}, {"name": "Sn", "desc": "First source 32-bit floating-point register"}], "extension": "FEAT_FRINTTS", "description": "Rounds the source single-precision floating-point value to a 64-bit signed integer using the current rounding mode, and writes the result as a single-precision floating-point value to the destination. Signals an inexact exception if the input was not exactly representable as a 64-bit integer. Does not update the NZCV condition flags. Requires FEAT_FRINTTS extension; AArch64 only.", "example": "FRINT64X s0, s1", "pseudocode": "Xn_bits ← Sn\nint64_val ← RoundUsingCurrentMode(FPUnpack(Xn_bits), 64)\nif int64_val is inexact then signal_inexact_exception()\nSd ← FPPack(int64_val as single-precision floating-point)"} {"mnemonic": "frint64z", "architecture": "ARMv8-A", "full_name": "Floating-Point Round to 64-bit Integer (Zero)", "summary": "Rounds to 64-bit integer towards zero.", "syntax": "FRINT64Z , ", "encoding": {"format": "Float Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 10100 | 10 | 10000 | Rn | Rd", "hex_opcode": "0x1E294000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "10100", "clean": "10100"}, {"raw": "10", "clean": "10"}, {"raw": "10000", "clean": "10000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:17 | 16:15 | 14:10 | 9:5 | 4:0"}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}, {"name": "Sn", "desc": "First source 32-bit floating-point register"}], "extension": "FEAT_FRINTTS", "description": "Rounds the source single-precision floating-point value to a 64-bit signed integer using round towards zero (truncate) rounding mode, and writes the result as a single-precision floating-point value to the destination. Does not update the NZCV condition flags. Requires FEAT_FRINTTS extension; AArch64 only.", "example": "FRINT64Z s0, s1", "pseudocode": "Xn_bits ← Sn\nint64_val ← RoundTowardsZero(FPUnpack(Xn_bits), 64)\nSd ← FPPack(int64_val as single-precision floating-point)"} {"mnemonic": "chkfeat", "architecture": "ARMv8-A", "full_name": "Check", "summary": "Check feature status (FEAT_CHK).", "syntax": "CHK <#imm>", "encoding": {"format": "System", "binary_pattern": "11010101000000110010 | 0101 | 000 | 11111", "hex_opcode": "0xD503251F", "visual_parts": [{"raw": "11010101000000110010", "clean": "11010101000000110010"}, {"raw": "0101", "clean": "0101"}, {"raw": "000", "clean": "000"}, {"raw": "11111", "clean": "11111"}], "bit_positions": "31:12 | 11:8 | 7:5 | 4:0"}, "operands": [{"name": "imm", "desc": "Feature ID"}], "extension": "FEAT_CHK", "description": "Checks the status of a system feature identified by the immediate operand and raises a CHK exception if the feature is not available or in the expected state. The specific behavior depends on the feature ID encoded in the immediate. Requires FEAT_CHK extension; AArch64 only; may only execute at EL0 and EL1 (subject to CHKFEATURE_EL0 register control).", "example": "CHK #imm", "pseudocode": "feature_id ← imm\nif not CheckFeature(feature_id) then raise_exception(CHK_EXCEPTION)"} {"mnemonic": "clrex", "architecture": "ARMv8-A", "full_name": "Clear Exclusive (System)", "summary": "Clears the local monitor state (AArch64 variant).", "syntax": "CLREX {#}", "encoding": {"format": "System", "binary_pattern": "11010101000000110011 | CRm | 010 | 11111", "hex_opcode": "0xD503305F", "visual_parts": [{"raw": "11010101000000110011", "clean": "11010101000000110011"}, {"raw": "CRm", "clean": "CRm"}, {"raw": "010", "clean": "010"}, {"raw": "11111", "clean": "11111"}], "bit_positions": "31:12 | 11:8 | 7:5 | 4:0"}, "operands": [{"name": "imm", "desc": "Optional"}], "extension": "Base (Atomic)", "description": "Clears the local monitor state associated with the current PE, removing any exclusive accesses held by this processor. Subsequent LDEX/STEX instructions will treat the exclusive monitor as clear. Does not update condition flags. AArch64 only; optional immediate operand is typically 0xF (ignored).", "example": "CLREX", "pseudocode": "local_monitor_state ← CLEAR"} {"mnemonic": "fadd", "architecture": "ARMv8-A", "full_name": "Floating-point Add (Single)", "summary": "Adds two single-precision floating-point registers.", "syntax": "FADD , , ", "encoding": {"format": "Float Data Proc", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | 001 | 0 | 10 | Rn | Rd", "hex_opcode": "0x1E202800", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "001", "clean": "001"}, {"raw": "0", "clean": "0"}, {"raw": "10", "clean": "10"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:13 | 12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Sd", "desc": "Dest (32-bit)"}, {"name": "Sn", "desc": "First source 32-bit floating-point register"}, {"name": "Sm", "desc": "Second source 32-bit floating-point register"}], "extension": "F.P.", "description": "Floating-point addition of two single-precision (32-bit) values. Adds operand Sn and operand Sm and writes the result to Sd. FPSR exception flags are updated; condition flags (N, Z, C, V) are unaffected. AArch64-only instruction; uses IEEE 754 rounding mode from FPCR.", "example": "FADD s0, s1, s2", "pseudocode": "operand1 ← Sn (32-bit float)\noperand2 ← Sm (32-bit float)\nresult ← FPAdd(operand1, operand2)\nSd ← result\nUpdateFPSR(exception_flags)"} {"mnemonic": "fadd", "architecture": "ARMv8-A", "full_name": "Floating-point Add (Double)", "summary": "Adds two double-precision floating-point registers.", "syntax": "FADD
, , ", "encoding": {"format": "Float Data Proc", "binary_pattern": "0 | 0 | 0 | 11110 | 01 | 1 | Rm | 001 | 0 | 10 | Rn | Rd", "hex_opcode": "0x1E602800", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "01", "clean": "01"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "001", "clean": "001"}, {"raw": "0", "clean": "0"}, {"raw": "10", "clean": "10"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:13 | 12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Dd", "desc": "Dest (64-bit)"}, {"name": "Dn", "desc": "First source 64-bit SIMD/FP register"}, {"name": "Dm", "desc": "Second source 64-bit SIMD/FP register"}], "extension": "F.P.", "description": "Floating-point addition of two double-precision (64-bit) values. Adds operand Dn and operand Dm and writes the result to Dd. FPSR exception flags are updated; condition flags (N, Z, C, V) are unaffected. AArch64-only instruction; uses IEEE 754 rounding mode from FPCR.", "example": "FADD d0, d1, d2", "pseudocode": "operand1 ← Dn (64-bit float)\noperand2 ← Dm (64-bit float)\nresult ← FPAdd(operand1, operand2)\nDd ← result\nUpdateFPSR(exception_flags)"} {"mnemonic": "fsub", "architecture": "ARMv8-A", "full_name": "Floating-point Subtract (Single)", "summary": "Subtracts two single-precision floating-point registers.", "syntax": "FSUB , , ", "encoding": {"format": "Float Data Proc", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | 001 | 1 | 10 | Rn | Rd", "hex_opcode": "0x1E203800", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "001", "clean": "001"}, {"raw": "1", "clean": "1"}, {"raw": "10", "clean": "10"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:13 | 12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}, {"name": "Sn", "desc": "First source 32-bit floating-point register"}, {"name": "Sm", "desc": "Second source 32-bit floating-point register"}], "extension": "F.P.", "description": "Floating-point subtraction of two single-precision (32-bit) values. Subtracts operand Sm from operand Sn and writes the result to Sd. FPSR exception flags are updated; condition flags (N, Z, C, V) are unaffected. AArch64-only instruction; uses IEEE 754 rounding mode from FPCR.", "example": "FSUB s0, s1, s2", "pseudocode": "operand1 ← Sn (32-bit float)\noperand2 ← Sm (32-bit float)\nresult ← FPSub(operand1, operand2)\nSd ← result\nUpdateFPSR(exception_flags)"} {"mnemonic": "fsub", "architecture": "ARMv8-A", "full_name": "Floating-point Subtract (Double)", "summary": "Subtracts two double-precision floating-point registers.", "syntax": "FSUB
, , ", "encoding": {"format": "Float Data Proc", "binary_pattern": "0 | 0 | 0 | 11110 | 01 | 1 | Rm | 001 | 1 | 10 | Rn | Rd", "hex_opcode": "0x1E603800", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "01", "clean": "01"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "001", "clean": "001"}, {"raw": "1", "clean": "1"}, {"raw": "10", "clean": "10"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:13 | 12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Dd", "desc": "Destination 64-bit SIMD/FP register"}, {"name": "Dn", "desc": "First source 64-bit SIMD/FP register"}, {"name": "Dm", "desc": "Second source 64-bit SIMD/FP register"}], "extension": "F.P.", "description": "Floating-point subtraction of two double-precision (64-bit) values. Subtracts operand Dm from operand Dn and writes the result to Dd. FPSR exception flags are updated; condition flags (N, Z, C, V) are unaffected. AArch64-only instruction; uses IEEE 754 rounding mode from FPCR.", "example": "FSUB d0, d1, d2", "pseudocode": "operand1 ← Dn (64-bit float)\noperand2 ← Dm (64-bit float)\nresult ← FPSub(operand1, operand2)\nDd ← result\nUpdateFPSR(exception_flags)"} {"mnemonic": "fmul", "architecture": "ARMv8-A", "full_name": "Floating-point Multiply (Single)", "summary": "Multiplies two single-precision floating-point registers.", "syntax": "FMUL , , ", "encoding": {"format": "Float Data Proc", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | 0 | 00010 | Rn | Rd", "hex_opcode": "0x1E200800", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "0", "clean": "0"}, {"raw": "00010", "clean": "00010"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15 | 14:10 | 9:5 | 4:0"}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}, {"name": "Sn", "desc": "First source 32-bit floating-point register"}, {"name": "Sm", "desc": "Second source 32-bit floating-point register"}], "extension": "F.P.", "description": "Floating-point multiplication of two single-precision (32-bit) values. Multiplies operand Sn by operand Sm and writes the result to Sd. FPSR exception flags are updated; condition flags (N, Z, C, V) are unaffected. AArch64-only instruction; uses IEEE 754 rounding mode from FPCR.", "example": "FMUL s0, s1, s2", "pseudocode": "operand1 ← Sn (32-bit float)\noperand2 ← Sm (32-bit float)\nresult ← FPMul(operand1, operand2)\nSd ← result\nUpdateFPSR(exception_flags)"} {"mnemonic": "fmul", "architecture": "ARMv8-A", "full_name": "Floating-point Multiply (Double)", "summary": "Multiplies two double-precision floating-point registers.", "syntax": "FMUL
, , ", "encoding": {"format": "Float Data Proc", "binary_pattern": "0 | 0 | 0 | 11110 | 01 | 1 | Rm | 0 | 00010 | Rn | Rd", "hex_opcode": "0x1E600800", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "01", "clean": "01"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "0", "clean": "0"}, {"raw": "00010", "clean": "00010"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15 | 14:10 | 9:5 | 4:0"}, "operands": [{"name": "Dd", "desc": "Destination 64-bit SIMD/FP register"}, {"name": "Dn", "desc": "First source 64-bit SIMD/FP register"}, {"name": "Dm", "desc": "Second source 64-bit SIMD/FP register"}], "extension": "F.P.", "description": "Floating-point multiplication of two double-precision (64-bit) values. Multiplies operand Dn by operand Dm and writes the result to Dd. FPSR exception flags are updated; condition flags (N, Z, C, V) are unaffected. AArch64-only instruction; uses IEEE 754 rounding mode from FPCR.", "example": "FMUL d0, d1, d2", "pseudocode": "operand1 ← Dn (64-bit float)\noperand2 ← Dm (64-bit float)\nresult ← FPMul(operand1, operand2)\nDd ← result\nUpdateFPSR(exception_flags)"} {"mnemonic": "fdiv", "architecture": "ARMv8-A", "full_name": "Floating-point Divide (Single)", "summary": "Divides two single-precision floating-point registers.", "syntax": "FDIV , , ", "encoding": {"format": "Float Data Proc", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | 0001 | 10 | Rn | Rd", "hex_opcode": "0x1E201800", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "0001", "clean": "0001"}, {"raw": "10", "clean": "10"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Sd", "desc": "Destination 32-bit floating-point register"}, {"name": "Sn", "desc": "Dividend"}, {"name": "Sm", "desc": "Divisor"}], "extension": "F.P.", "description": "Divides the single-precision floating-point value in Sn by the value in Sm and stores the result in Sd. This instruction operates on 32-bit IEEE 754 floating-point values. The NZCV flags are updated based on the result: N is set if the result is negative, Z if zero, C and V are set according to IEEE 754 semantics. This is an AArch64-only instruction requiring the Floating-Point extension.", "example": "FDIV s0, s1, s2", "pseudocode": "Sd ← Sn ÷ Sm\nN ← Sd[31]\nZ ← (Sd == 0.0)\nC ← (overflow or underflow)\nV ← (invalid operation or overflow)"} {"mnemonic": "fdiv", "architecture": "ARMv8-A", "full_name": "Floating-point Divide (Double)", "summary": "Divides two double-precision floating-point registers.", "syntax": "FDIV
, , ", "encoding": {"format": "Float Data Proc", "binary_pattern": "0 | 0 | 0 | 11110 | 01 | 1 | Rm | 0001 | 10 | Rn | Rd", "hex_opcode": "0x1E601800", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "01", "clean": "01"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "0001", "clean": "0001"}, {"raw": "10", "clean": "10"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Dd", "desc": "Destination 64-bit SIMD/FP register"}, {"name": "Dn", "desc": "Dividend"}, {"name": "Dm", "desc": "Divisor"}], "extension": "F.P.", "description": "Divides the double-precision floating-point value in Dn by the value in Dm and stores the result in Dd. This instruction operates on 64-bit IEEE 754 floating-point values. The NZCV flags are updated based on the result: N is set if the result is negative, Z if zero, C and V are set according to IEEE 754 semantics. This is an AArch64-only instruction requiring the Floating-Point extension.", "example": "FDIV d0, d1, d2", "pseudocode": "Dd ← Dn ÷ Dm\nN ← Dd[63]\nZ ← (Dd == 0.0)\nC ← (overflow or underflow)\nV ← (invalid operation or overflow)"} {"mnemonic": "fcmp", "architecture": "ARMv8-A", "full_name": "Floating-point Compare (Single)", "summary": "Compares two single-precision registers and updates NZCV flags.", "syntax": "FCMP , ", "encoding": {"format": "Float Compare", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | 00 | 1000 | Rn | 00 | 000", "hex_opcode": "0x1E202000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "00", "clean": "00"}, {"raw": "1000", "clean": "1000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "00", "clean": "00"}, {"raw": "000", "clean": "000"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:14 | 13:10 | 9:5 | 4:3 | 2:0"}, "operands": [{"name": "Sn", "desc": "First source 32-bit floating-point register"}, {"name": "Sm", "desc": "Second source 32-bit floating-point register"}], "extension": "F.P.", "description": "Compares two single-precision floating-point registers (Sn and Sm) and updates the NZCV condition flags based on the result. Handles NaN operands by setting both N and V flags; neither operand being NaN results in N, Z, C, V being set according to the comparison outcome. AArch64 only.", "example": "FCMP s1, s2", "pseudocode": "op1 ← FPUnpack(Sn)\nop2 ← FPUnpack(Sm)\nresult ← FPCompare(op1, op2)\nif isNaN(op1) or isNaN(op2) then\n N ← 1; Z ← 0; C ← 1; V ← 1\nelse if op1 == op2 then\n N ← 0; Z ← 1; C ← 1; V ← 0\nelse if op1 < op2 then\n N ← 1; Z ← 0; C ← 0; V ← 0\nelse\n N ← 0; Z ← 0; C ← 1; V ← 0"} {"mnemonic": "fcmp", "architecture": "ARMv8-A", "full_name": "Floating-point Compare (Double)", "summary": "Compares two double-precision registers and updates NZCV flags.", "syntax": "FCMP , ", "encoding": {"format": "Float Compare", "binary_pattern": "0 | 0 | 0 | 11110 | 01 | 1 | Rm | 00 | 1000 | Rn | 00 | 000", "hex_opcode": "0x1E602000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "01", "clean": "01"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "00", "clean": "00"}, {"raw": "1000", "clean": "1000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "00", "clean": "00"}, {"raw": "000", "clean": "000"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:14 | 13:10 | 9:5 | 4:3 | 2:0"}, "operands": [{"name": "Dn", "desc": "First source 64-bit SIMD/FP register"}, {"name": "Dm", "desc": "Second source 64-bit SIMD/FP register"}], "extension": "F.P.", "description": "Compares two double-precision floating-point registers (Dn and Dm) and updates the NZCV condition flags based on the result. Handles NaN operands by setting both N and V flags; neither operand being NaN results in N, Z, C, V being set according to the comparison outcome. AArch64 only.", "example": "FCMP d1, d2", "pseudocode": "op1 ← FPUnpack(Dn)\nop2 ← FPUnpack(Dm)\nresult ← FPCompare(op1, op2)\nif isNaN(op1) or isNaN(op2) then\n N ← 1; Z ← 0; C ← 1; V ← 1\nelse if op1 == op2 then\n N ← 0; Z ← 1; C ← 1; V ← 0\nelse if op1 < op2 then\n N ← 1; Z ← 0; C ← 0; V ← 0\nelse\n N ← 0; Z ← 0; C ← 1; V ← 0"} {"mnemonic": "fmov", "architecture": "ARMv8-A", "full_name": "Floating-point Move (Register)", "summary": "Copies value between floating-point registers.", "syntax": "FMOV
, ", "encoding": {"format": "Float Data Proc", "binary_pattern": "0 | 0 | 0 | 11110 | 01 | 10000 | 00 | 10000 | Rn | Rd", "hex_opcode": "0x1E604000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "01", "clean": "01"}, {"raw": "10000", "clean": "10000"}, {"raw": "00", "clean": "00"}, {"raw": "10000", "clean": "10000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:17 | 16:15 | 14:10 | 9:5 | 4:0"}, "operands": [{"name": "Dd", "desc": "Destination 64-bit SIMD/FP register"}, {"name": "Dn", "desc": "First source 64-bit SIMD/FP register"}], "extension": "F.P.", "description": "Copies a 64-bit double-precision floating-point value from Dn to Dd without any conversion or modification. The condition flags NZCV are not affected. This is an AArch64-only instruction requiring the Floating-Point extension.", "example": "FMOV d0, d1", "pseudocode": "Dd ← Dn"} {"mnemonic": "fmov", "architecture": "ARMv8-A", "full_name": "Floating-point Move (Immediate)", "summary": "Moves immediate value into floating-point register.", "syntax": "FMOV
, #", "encoding": {"format": "Float Imm", "binary_pattern": "0 | 0 | 0 | 11110 | 01 | 1 | imm8 | 100 | 00000 | Rd", "hex_opcode": "0x1E601000", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "01", "clean": "01"}, {"raw": "1", "clean": "1"}, {"raw": "imm8", "clean": "imm8"}, {"raw": "100", "clean": "100"}, {"raw": "00000", "clean": "00000"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:13 | 12:10 | 9:5 | 4:0"}, "operands": [{"name": "Dd", "desc": "Destination 64-bit SIMD/FP register"}, {"name": "imm", "desc": "Signed immediate value"}], "extension": "F.P.", "description": "Moves an 8-bit encoded immediate value into a 64-bit double-precision floating-point register Dd. The immediate is expanded to a full 64-bit floating-point value according to the VFPv3 expanded-immediate encoding scheme. The condition flags NZCV are not affected. This is an AArch64-only instruction requiring the Floating-Point extension.", "example": "FMOV d0, #16", "pseudocode": "Dd ← ExpandImmediate(imm8)"} {"mnemonic": "scvtf", "architecture": "ARMv8-A", "full_name": "Signed Integer Convert to Floating-point", "summary": "Converts signed integer (scalar) to floating-point.", "syntax": "SCVTF
, ", "encoding": {"format": "Float Conversion", "binary_pattern": "1 | 0 | 0 | 11110 | 00 | 1 | 00 | 010 | 000000 | Rn | Rd", "hex_opcode": "0x9E220000", "visual_parts": [{"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "00", "clean": "00"}, {"raw": "010", "clean": "010"}, {"raw": "000000", "clean": "000000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Dd", "desc": "Dest (Double)"}, {"name": "Xn", "desc": "Src (Int64)"}], "extension": "F.P.", "description": "Converts a 64-bit signed integer value from Xn to a double-precision floating-point value using the current rounding mode, and writes the result to Dd. Does not update the NZCV condition flags. AArch64 only.", "example": "SCVTF d0, x1", "pseudocode": "int_val ← X[n]\nfp_result ← ConvertSignedIntegerToFP(int_val, double-precision, current_rounding_mode)\nD[d] ← FPPack(fp_result)"} {"mnemonic": "fcvtzs", "architecture": "ARMv8-A", "full_name": "Floating-point Convert to Signed Integer (Round towards Zero)", "summary": "Converts floating-point to signed integer.", "syntax": "FCVTZS , ", "encoding": {"format": "Float Conversion", "binary_pattern": "1 | 0 | 0 | 11110 | 00 | 1 | 11 | 000 | 000000 | Rn | Rd", "hex_opcode": "0x9E380000", "visual_parts": [{"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "11110", "clean": "11110"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "11", "clean": "11"}, {"raw": "000", "clean": "000"}, {"raw": "000000", "clean": "000000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Xd", "desc": "Dest (Int64)"}, {"name": "Dn", "desc": "Src (Double)"}], "extension": "F.P.", "description": "Converts a 64-bit double-precision floating-point value in Dn to a signed 64-bit integer, rounding towards zero, and stores the result in Xd. If the result overflows the signed 64-bit range, the result is the most negative or most positive 64-bit integer depending on the input sign. The condition flags NZCV are not affected. This is an AArch64-only instruction requiring the Floating-Point extension.", "example": "FCVTZS x0, d1", "pseudocode": "Xd ← ConvertToSignedInteger(Dn, RoundTowardZero)\nif (overflow) then\n Xd ← (Dn < 0) ? INT64_MIN : INT64_MAX"} {"mnemonic": "rev", "architecture": "ARMv8-A", "full_name": "Reverse Bytes (32-bit)", "summary": "Reverses the byte order in a 32-bit register (Endianness swap).", "syntax": "REV , ", "encoding": {"format": "Data Processing", "binary_pattern": "0 | 1 | 0 | 11010110 | 00000 | 0000 | 10 | Rn | Rd", "hex_opcode": "0x5AC00800", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "11010110", "clean": "11010110"}, {"raw": "00000", "clean": "00000"}, {"raw": "0000", "clean": "0000"}, {"raw": "10", "clean": "10"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:12 | 11:10 | 9:5 | 4:0"}, "operands": [{"name": "Wd", "desc": "Destination 32-bit integer register"}, {"name": "Wn", "desc": "First source / base 32-bit integer register"}], "extension": "Base", "description": "Reverses the byte order of a 32-bit value in Wn and stores the result in Wd, performing endianness conversion. The upper 32 bits of the destination register are zeroed. The condition flags NZCV are not affected. This is an AArch64-only instruction available in the Base instruction set.", "example": "REV w0, w1", "pseudocode": "Wd ← ReverseBytes(Wn)\nXd[63:32] ← 0"} {"mnemonic": "rbit", "architecture": "ARMv8-A", "full_name": "Reverse Bits (64-bit)", "summary": "Reverses the bit order in a 64-bit register.", "syntax": "RBIT , ", "encoding": {"format": "Data Processing", "binary_pattern": "1 | 1 | 0 | 11010110 | 00000 | 000000 | Rn | Rd", "hex_opcode": "0xDAC00000", "visual_parts": [{"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "11010110", "clean": "11010110"}, {"raw": "00000", "clean": "00000"}, {"raw": "000000", "clean": "000000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Xd", "desc": "Destination 64-bit integer register"}, {"name": "Xn", "desc": "First source / base 64-bit integer register"}], "extension": "Base", "description": "Reverses the bit order in a 64-bit register, placing the least significant bit at the most significant position. No condition flags are affected. This is an AArch64 instruction with no privilege requirements.", "example": "RBIT x0, x1", "pseudocode": "Xd ← BitReverse(Xn)"} {"mnemonic": "sxtb", "architecture": "ARMv8-A", "full_name": "Sign Extend Byte", "summary": "Extracts the lowest 8 bits and sign-extends to 32 bits (Alias for SBFM).", "syntax": "SXTB , ", "encoding": {"format": "Bitfield", "binary_pattern": "0 | 00 | 100110 | 0 | 000000 | 000111 | Rn | Rd", "hex_opcode": "0x13001C00", "visual_parts": [{"raw": "0", "clean": "0"}, {"raw": "00", "clean": "00"}, {"raw": "100110", "clean": "100110"}, {"raw": "0", "clean": "0"}, {"raw": "000000", "clean": "000000"}, {"raw": "000111", "clean": "000111"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30:29 | 28:23 | 22 | 21:16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Wd", "desc": "Destination 32-bit integer register"}, {"name": "Wn", "desc": "First source / base 32-bit integer register"}], "extension": "Base", "description": "Extracts the lowest 8 bits of a 32-bit register and sign-extends the result to fill all 32 bits. No condition flags are affected. This is an AArch64 alias for SBFM (Signed Bitfield Move) with bit positions 0 and 7.", "example": "SXTB w0, w1", "pseudocode": "Wd ← SignExtend(Wn[7:0], 32)"} {"mnemonic": "sxtw", "architecture": "ARMv8-A", "full_name": "Sign Extend Word", "summary": "Sign-extends a 32-bit register to 64 bits (Alias for SBFM).", "syntax": "SXTW , ", "encoding": {"format": "Bitfield", "binary_pattern": "1 | 00 | 100110 | 1 | 000000 | 011111 | Rn | Rd", "hex_opcode": "0x93407C00", "visual_parts": [{"raw": "1", "clean": "1"}, {"raw": "00", "clean": "00"}, {"raw": "100110", "clean": "100110"}, {"raw": "1", "clean": "1"}, {"raw": "000000", "clean": "000000"}, {"raw": "011111", "clean": "011111"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}], "bit_positions": "31 | 30:29 | 28:23 | 22 | 21:16 | 15:10 | 9:5 | 4:0"}, "operands": [{"name": "Xd", "desc": "Dest (64)"}, {"name": "Wn", "desc": "Source (32)"}], "extension": "Base", "description": "Sign-extends a 32-bit value to fill 64 bits, replicating bit 31 into all upper bits. No condition flags are affected. This is an AArch64 alias for SBFM with bit positions 0 and 31.", "example": "SXTW x0, w1", "pseudocode": "Xd ← SignExtend(Wn, 64)"} {"mnemonic": "adc", "architecture": "ARMv8-A", "full_name": "Add with Carry (A32)", "summary": "Adds two 32-bit values and the Carry flag.", "syntax": "ADC{S} , , {, }", "encoding": {"format": "Data Proc", "binary_pattern": "cond | 0000 | 101 | 0 | Rn | Rd | imm5 | stype | 0 | Rm", "hex_opcode": "0x00A00000", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "0000", "clean": "0000"}, {"raw": "101", "clean": "101"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "imm5", "clean": "imm5"}, {"raw": "stype", "clean": "stype"}, {"raw": "0", "clean": "0"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:24 | 23:21 | 20 | 19:16 | 15:12 | 11:7 | 6:5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (Base)", "description": "Adds two 32-bit values from Rn and Rm along with the Carry flag (C) and stores the result in Rd. If the S bit is set, the condition flags are updated: N and Z reflect the result, C is set on unsigned overflow, V is set on signed overflow. The shift operand is optional and applies a shift to Rm before the addition. This is an A32 instruction with conditional execution.", "example": "ADC r0, r1, r2", "pseudocode": "shifted_Rm ← ApplyShift(Rm, shift)\nresult ← Rn + shifted_Rm + C\nRd ← result\nif S then\n N ← result[31]\n Z ← (result == 0)\n C ← CarryOut(Rn + shifted_Rm + C)\n V ← OverflowFrom(Rn + shifted_Rm + C)"} {"mnemonic": "add", "architecture": "ARMv8-A", "full_name": "Add (A32)", "summary": "Adds two 32-bit values.", "syntax": "ADD{S} , , {, }", "encoding": {"format": "Data Proc", "binary_pattern": "cond | 0000 | 100 | 0 | Rn | Rd | imm5 | stype | 0 | Rm", "hex_opcode": "0x00800000", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "0000", "clean": "0000"}, {"raw": "100", "clean": "100"}, {"raw": "0", "clean": "0"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "imm5", "clean": "imm5"}, {"raw": "stype", "clean": "stype"}, {"raw": "0", "clean": "0"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:24 | 23:21 | 20 | 19:16 | 15:12 | 11:7 | 6:5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (Base)", "description": "Adds two 32-bit operands and stores the result in the destination register. If the S bit is set, the condition flags (N, Z, C, V) are updated based on the result; otherwise they are unaffected. This is an A32 instruction where the condition code (cond) field determines execution based on the current condition flags.", "example": "ADD r0, r1, r2", "pseudocode": "result ← Rn + (Rm << shift_amount)\nRd ← result[31:0]\nif S then\n N ← result[31]\n Z ← (result == 0)\n C ← CarryOut(Rn, Rm << shift_amount)\n V ← OverflowFrom(Rn, Rm << shift_amount)"} {"mnemonic": "adr", "architecture": "ARMv8-A", "full_name": "Form PC-relative Address (A32)", "summary": "Adds an immediate value to the PC register.", "syntax": "ADR ,
, , #", "encoding": {"format": "NEON Shift", "binary_pattern": "1111001 | U | 1 | D | imm6 | Vd | 0001 | L | 0 | M | 1 | Vm", "hex_opcode": "0xF2800110", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "U", "clean": "U"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "imm6", "clean": "imm6"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0001", "clean": "0001"}, {"raw": "L", "clean": "L"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Dest/Acc"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}, {"name": "imm", "desc": "Signed immediate value"}], "extension": "NEON (SIMD)", "description": "Shifts each element in the source register right by the immediate shift amount and accumulates (adds) the shifted result into the corresponding element of the destination register. The shift amount is treated as unsigned. No condition flags are modified. This is a NEON instruction available in both A32 and T32 instruction sets.", "example": "VSRA.dt q0, q2, #16", "pseudocode": "for i = 0 to elements_in_Qd - 1\n shift_amount ← imm6\n shifted ← Qm[i] >> shift_amount\n Qd[i] ← Qd[i] + shifted\nendfor"} {"mnemonic": "vrsra", "architecture": "ARMv8-A", "full_name": "Vector Rounding Shift Right and Accumulate", "summary": "Shifts right with rounding and adds to accumulator.", "syntax": "VRSRA.
, , #", "encoding": {"format": "NEON Shift", "binary_pattern": "1111001 | U | 1 | D | imm6 | Vd | 0011 | L | 0 | M | 1 | Vm", "hex_opcode": "0xF2800310", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "U", "clean": "U"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "imm6", "clean": "imm6"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0011", "clean": "0011"}, {"raw": "L", "clean": "L"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Dest/Acc"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}, {"name": "imm", "desc": "Signed immediate value"}], "extension": "NEON (SIMD)", "description": "Shifts each element in the source register right by the immediate shift amount with rounding (adding 1 to bit position before the round point), then accumulates the rounded result into the destination register. The shift amount is unsigned. No condition flags are modified. This is a NEON instruction available in both A32 and T32 instruction sets.", "example": "VRSRA.dt q0, q2, #16", "pseudocode": "for i = 0 to elements_in_Qd - 1\n shift_amount ← imm6\n if shift_amount > 0 then\n rounded ← (Qm[i] + (1 << (shift_amount - 1))) >> shift_amount\n else\n rounded ← Qm[i]\n endif\n Qd[i] ← Qd[i] + rounded\nendfor"} {"mnemonic": "vsli", "architecture": "ARMv8-A", "full_name": "Vector Shift Left and Insert", "summary": "Shifts bits left and inserts into destination (merging).", "syntax": "VSLI. , , #", "encoding": {"format": "NEON Shift", "binary_pattern": "1111001 | 1 | 1 | D | imm6 | Vd | 0101 | L | 1 | M | 1 | Vm", "hex_opcode": "0xF3800550", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "imm6", "clean": "imm6"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0101", "clean": "0101"}, {"raw": "L", "clean": "L"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}, {"name": "imm", "desc": "Signed immediate value"}], "extension": "NEON (SIMD)", "description": "Shifts each element in the source register left by the immediate shift amount and inserts the shifted bits into the low bits of the destination element, leaving the high bits of the destination unchanged (merging operation). The shift amount is unsigned. No condition flags are modified. This is a NEON instruction available in both A32 and T32 instruction sets.", "example": "VSLI.size q0, q2, #16", "pseudocode": "for i = 0 to elements_in_Qd - 1\n shift_amount ← imm6\n shifted ← Qm[i] << shift_amount\n mask ← (1 << shift_amount) - 1\n Qd[i] ← (Qd[i] & ~mask) | (shifted & mask)\nendfor"} {"mnemonic": "vsri", "architecture": "ARMv8-A", "full_name": "Vector Shift Right and Insert", "summary": "Shifts bits right and inserts into destination.", "syntax": "VSRI. , , #", "encoding": {"format": "NEON Shift", "binary_pattern": "1111001 | 1 | 1 | D | imm6 | Vd | 0100 | L | 1 | M | 1 | Vm", "hex_opcode": "0xF3800450", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "imm6", "clean": "imm6"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0100", "clean": "0100"}, {"raw": "L", "clean": "L"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}, {"name": "imm", "desc": "Signed immediate value"}], "extension": "NEON (SIMD)", "description": "Shifts each element in the source register right by the immediate shift amount and inserts the shifted bits into the high bits of the destination element, leaving the low bits of the destination unchanged (merging operation). The shift amount is unsigned. No condition flags are modified. This is a NEON instruction available in both A32 and T32 instruction sets.", "example": "VSRI.size q0, q2, #16", "pseudocode": "for i = 0 to elements_in_Qd - 1\n shift_amount ← imm6\n shifted ← Qm[i] >> shift_amount\n mask ← ((1 << (element_size - shift_amount)) - 1) << shift_amount\n Qd[i] ← (Qd[i] & ~mask) | (shifted & mask)\nendfor"} {"mnemonic": "vrshl", "architecture": "ARMv8-A", "full_name": "Vector Rounding Shift Left", "summary": "Shifts left with rounding based on a register value.", "syntax": "VRSHL.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 0101 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2000500", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "U", "clean": "U"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0101", "clean": "0101"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}, {"name": "Qn", "desc": "Shift Reg"}], "extension": "NEON (SIMD)", "description": "Shifts each element in Qm left or right by the amount specified in the corresponding element of Qn with rounding applied when shifting right. Positive shift amounts shift left; negative amounts shift right with rounding. Results are stored in Qd. No condition flags are modified. This is a NEON instruction available in both A32 and T32 instruction sets.", "example": "VRSHL.dt q0, q2, q1", "pseudocode": "for i = 0 to elements_in_Qd - 1\n shift_amount ← signed(Qn[i])\n if shift_amount >= 0 then\n Qd[i] ← Qm[i] << shift_amount\n else\n if shift_amount <= -element_size then\n Qd[i] ← 0\n else\n rounded ← Qm[i] + (1 << (-shift_amount - 1))\n Qd[i] ← rounded >> (-shift_amount)\n endif\n endif\nendfor"} {"mnemonic": "vrshr", "architecture": "ARMv8-A", "full_name": "Vector Rounding Shift Right", "summary": "Shifts right with rounding based on immediate.", "syntax": "VRSHR.
, , #", "encoding": {"format": "NEON Shift", "binary_pattern": "1111001 | U | 1 | D | imm6 | Vd | 0010 | L | 0 | M | 1 | Vm", "hex_opcode": "0xF2800210", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "U", "clean": "U"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "imm6", "clean": "imm6"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0010", "clean": "0010"}, {"raw": "L", "clean": "L"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}, {"name": "imm", "desc": "Signed immediate value"}], "extension": "NEON (SIMD)", "description": "Shifts each element in the source register right by the immediate shift amount with rounding (the bit at the shift position and all bits to the right are rounded according to ARM rounding rules). Results are stored in the destination register. No condition flags are modified. This is a NEON instruction available in both A32 and T32 instruction sets.", "example": "VRSHR.dt q0, q2, #16", "pseudocode": "for i = 0 to elements_in_Qd - 1\n shift_amount ← imm6\n if shift_amount >= element_size then\n Qd[i] ← 0\n else\n rounding_bit ← (Qm[i] >> (shift_amount - 1)) & 1\n Qd[i] ← (Qm[i] >> shift_amount) + rounding_bit\n endif\nendfor"} {"mnemonic": "vrshrn", "architecture": "ARMv8-A", "full_name": "Vector Rounding Shift Right Narrow", "summary": "Shifts right, rounds, and narrows (2N -> N bits).", "syntax": "VRSHRN.
, , #", "encoding": {"format": "NEON Shift", "binary_pattern": "111100111 | D | 11 | size | 10 | Vd | 0 | 0100 | 0 | M | 0 | Vm", "hex_opcode": "0xF3B20200", "visual_parts": [{"raw": "111100111", "clean": "111100111"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "size", "clean": "size"}, {"raw": "10", "clean": "10"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0", "clean": "0"}, {"raw": "0100", "clean": "0100"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Dd", "desc": "Dest Narrow"}, {"name": "Qm", "desc": "Src Wide"}, {"name": "imm", "desc": "Signed immediate value"}], "extension": "NEON (SIMD)", "description": "Shifts each element of the 128-bit source register right by the immediate shift amount with rounding, then narrows the result from 2N bits to N bits (halving the element width), and stores into the 64-bit destination register. The high half of the shift result is kept. No condition flags are modified. This is a NEON instruction available in both A32 and T32 instruction sets.", "example": "VRSHRN.dt d0, q2, #16", "pseudocode": "for i = 0 to elements_in_Dd - 1\n shift_amount ← imm6\n if shift_amount > 2 × element_size then\n Dd[i] ← 0\n else\n value ← Qm[i]\n rounding_correction ← (1 << (shift_amount - 1))\n rounded ← (value + rounding_correction) >> shift_amount\n Dd[i] ← saturate(rounded, element_size / 2)\n endif\nendfor"} {"mnemonic": "vqshl", "architecture": "ARMv8-A", "full_name": "Vector Saturating Shift Left (Register)", "summary": "Shifts left with saturation based on register.", "syntax": "VQSHL.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 0100 | N | 1 | M | 1 | Vm", "hex_opcode": "0xF2000450", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "U", "clean": "U"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0100", "clean": "0100"}, {"raw": "N", "clean": "N"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}, {"name": "Qn", "desc": "Shift Reg"}], "extension": "NEON (SIMD)", "description": "Vector Saturating Shift Left (Register) shifts each element in Qm left by the amount specified by the corresponding element in Qn, saturating the result to the range of the operand data type. The shift amount is interpreted as a signed value; negative amounts perform a right shift. All condition flags (N, Z, C, V) remain unaffected. This is an A32/T32 NEON instruction that operates on 128-bit quad registers.", "example": "VQSHL.dt q0, q2, q1", "pseudocode": "for i = 0 to elements-1 do\n shift_amount ← SignExtend(Qn[i])\n if shift_amount >= 0 then\n result ← SatQ(Qm[i] << shift_amount, esize)\n else\n result ← SatQ(Qm[i] >> (-shift_amount), esize)\n Qd[i] ← result"} {"mnemonic": "vqshl", "architecture": "ARMv8-A", "full_name": "Vector Saturating Shift Left (Immediate)", "summary": "Shifts left with saturation based on immediate.", "syntax": "VQSHL.
, , #", "encoding": {"format": "NEON Shift", "binary_pattern": "1111001 | U | 1 | D | imm6 | Vd | 011 | 1 | L | 0 | M | 1 | Vm", "hex_opcode": "0xF2800710", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "U", "clean": "U"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "imm6", "clean": "imm6"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "011", "clean": "011"}, {"raw": "1", "clean": "1"}, {"raw": "L", "clean": "L"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:16 | 15:12 | 11:9 | 8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}, {"name": "imm", "desc": "Signed immediate value"}], "extension": "NEON (SIMD)", "description": "Vector Saturating Shift Left (Immediate) shifts each element in Qm left by an immediate value, saturating the result to the range of the operand data type. The immediate is a signed value encoded in imm6; positive values shift left, negative values (when sign-extended) would shift right. All condition flags (N, Z, C, V) remain unaffected. This is an A32/T32 NEON instruction.", "example": "VQSHL.dt q0, q2, #16", "pseudocode": "shift_amount ← SignExtend(imm6, 6)\nfor i = 0 to elements-1 do\n result ← SatQ(Qm[i] << shift_amount, esize)\n Qd[i] ← result"} {"mnemonic": "vqshr", "architecture": "ARMv8-A", "full_name": "Vector Saturating Shift Right (Unsigned)", "summary": "Shifts right with saturation (Unsigned).", "syntax": "VQSHR.U , , #", "encoding": {"format": "NEON Shift", "binary_pattern": "11110010 | 1 | D | imm6 | Vd | 1101 | L | Q | M | 1 | Vm", "hex_opcode": "0xF2800910", "visual_parts": [{"raw": "11110010", "clean": "11110010"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "imm6", "clean": "imm6"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1101", "clean": "1101"}, {"raw": "L", "clean": "L"}, {"raw": "Q", "clean": "Q"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}]}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}, {"name": "imm", "desc": "Signed immediate value"}], "extension": "NEON (SIMD)", "description": "Vector Saturating Shift Right (Unsigned) shifts each unsigned element in Qm right by an immediate value, saturating underflow to zero. The immediate specifies the right shift count. All condition flags (N, Z, C, V) remain unaffected. This is an A32/T32 NEON instruction for unsigned data types.", "example": "VQSHR.Usize q0, q2, #16", "pseudocode": "shift_amount ← imm6\nfor i = 0 to elements-1 do\n if shift_amount > 0 then\n result ← SatQ(Qm[i] >> shift_amount, 0, max_unsigned_value)\n else\n result ← Qm[i]\n Qd[i] ← result"} {"mnemonic": "vqshrn", "architecture": "ARMv8-A", "full_name": "Vector Saturating Shift Right Narrow", "summary": "Shifts right, saturates, and narrows.", "syntax": "VQSHRN.
, , #", "encoding": {"format": "NEON Shift", "binary_pattern": "1111001 | U | 1 | D | imm6 | Vd | 100 | 1 | 0 | 0 | M | 1 | Vm", "hex_opcode": "0xF2800910", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "U", "clean": "U"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "imm6", "clean": "imm6"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "100", "clean": "100"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:16 | 15:12 | 11:9 | 8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Dd", "desc": "Dest Narrow"}, {"name": "Qm", "desc": "Src Wide"}, {"name": "imm", "desc": "Signed immediate value"}], "extension": "NEON (SIMD)", "description": "Vector Saturating Shift Right Narrow shifts each element in Qm right by an immediate value, saturates to the range of the narrower result type, then packs the narrowed results into the destination Dd. This operation reduces element size by half and narrows the register from 128-bit to 64-bit. All condition flags (N, Z, C, V) remain unaffected. This is an A32/T32 NEON instruction.", "example": "VQSHRN.dt d0, q2, #16", "pseudocode": "shift_amount ← imm6\nfor i = 0 to narrow_elements-1 do\n wide_value ← Qm[i]\n shifted ← wide_value >> shift_amount\n result ← SatQ(shifted, narrow_esize)\n Dd[i] ← result"} {"mnemonic": "vqshlu", "architecture": "ARMv8-A", "full_name": "Vector Saturating Shift Left Unsigned", "summary": "Shifts signed elements left, saturating to unsigned result.", "syntax": "VQSHLU.
, , #", "encoding": {"format": "NEON Shift", "binary_pattern": "1111001 | 1 | 1 | D | imm6 | Vd | 011 | 0 | L | 1 | M | 1 | Vm", "hex_opcode": "0xF3800650", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "imm6", "clean": "imm6"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "011", "clean": "011"}, {"raw": "0", "clean": "0"}, {"raw": "L", "clean": "L"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:16 | 15:12 | 11:9 | 8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}, {"name": "imm", "desc": "Signed immediate value"}], "extension": "NEON (SIMD)", "description": "Vector Saturating Shift Left Unsigned shifts each signed element in Qm left by an immediate value and saturates the result to an unsigned range. Elements that overflow are clamped to the maximum unsigned value of the result type. All condition flags (N, Z, C, V) remain unaffected. This is an A32/T32 NEON instruction.", "example": "VQSHLU.dt q0, q2, #16", "pseudocode": "shift_amount ← imm6\nfor i = 0 to elements-1 do\n result ← SatQ(Qm[i] << shift_amount, 0, max_unsigned_value)\n Qd[i] ← result"} {"mnemonic": "vqrshl", "architecture": "ARMv8-A", "full_name": "Vector Saturating Rounding Shift Left", "summary": "Shifts left with saturation and rounding.", "syntax": "VQRSHL.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 0101 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2000510", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "U", "clean": "U"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0101", "clean": "0101"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}, {"name": "Qn", "desc": "Shift Reg"}], "extension": "NEON (SIMD)", "description": "Vector Saturating Rounding Shift Left shifts each element in Qm left by the amount specified in the corresponding element of Qn, with saturation and rounding applied. When the shift amount is negative, a right shift with rounding is performed. All condition flags (N, Z, C, V) remain unaffected. This is an A32/T32 NEON instruction.", "example": "VQRSHL.dt q0, q2, q1", "pseudocode": "for i = 0 to elements-1 do\n shift_amount ← SignExtend(Qn[i])\n if shift_amount >= 0 then\n result ← SatQ(Qm[i] << shift_amount, esize)\n else\n rounding_bit ← Qm[i][(-shift_amount-1)]\n shifted ← Qm[i] >> (-shift_amount)\n result ← SatQ(shifted + rounding_bit, esize)\n Qd[i] ← result"} {"mnemonic": "vqrshrn", "architecture": "ARMv8-A", "full_name": "Vector Saturating Rounding Shift Right Narrow", "summary": "Shifts right, saturates, rounds, and narrows.", "syntax": "VQRSHRN.
, , #", "encoding": {"format": "NEON Shift", "binary_pattern": "111100111 | D | 11 | size | 10 | Vd | 0 | 010 | op | M | 0 | Vm", "hex_opcode": "0xF3B20280", "visual_parts": [{"raw": "111100111", "clean": "111100111"}, {"raw": "D", "clean": "D"}, {"raw": "11", "clean": "11"}, {"raw": "size", "clean": "size"}, {"raw": "10", "clean": "10"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0", "clean": "0"}, {"raw": "010", "clean": "010"}, {"raw": "op", "clean": "op"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:8 | 7:6 | 5 | 4 | 3:0"}, "operands": [{"name": "Dd", "desc": "Dest Narrow"}, {"name": "Qm", "desc": "Src Wide"}, {"name": "imm", "desc": "Signed immediate value"}], "extension": "NEON (SIMD)", "description": "Vector Saturating Rounding Shift Right Narrow shifts each element in Qm right by an immediate value with rounding, saturates to the narrower result type, and packs the narrowed results into Dd. Rounding is applied before truncation and narrowing. This reduces element size by half and narrows the register from 128-bit to 64-bit. All condition flags (N, Z, C, V) remain unaffected. This is an A32/T32 NEON instruction.", "example": "VQRSHRN.dt d0, q2, #16", "pseudocode": "shift_amount ← imm6\nfor i = 0 to narrow_elements-1 do\n wide_value ← Qm[i]\n rounding_bit ← wide_value[shift_amount-1]\n shifted ← wide_value >> shift_amount\n rounded ← shifted + rounding_bit\n result ← SatQ(rounded, narrow_esize)\n Dd[i] ← result"} {"mnemonic": "vacge", "architecture": "ARMv8-A", "full_name": "Vector Absolute Compare Greater or Equal", "summary": "Compares absolute values (|Vn| >= |Vm|).", "syntax": "VACGE.F32 , , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | 1 | 0 | D | 0 | sz | Vn | Vd | 1110 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF3000E10", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "0", "clean": "0"}, {"raw": "sz", "clean": "sz"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1110", "clean": "1110"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Dest Mask"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Vector Absolute Compare Greater or Equal compares the absolute values of corresponding floating-point elements in Qn and Qm, setting each element in Qd to all 1s (true) if |Qn[i]| >= |Qm[i]|, or all 0s (false) otherwise. The comparison is per-element on 32-bit floating-point values. All condition flags (N, Z, C, V) remain unaffected. This is an A32/T32 NEON floating-point instruction.", "example": "VACGE.F32 q0, q1, q2", "pseudocode": "for i = 0 to elements-1 do\n if FPAbs(Qn[i]) >= FPAbs(Qm[i]) then\n Qd[i] ← 0xFFFFFFFF\n else\n Qd[i] ← 0x00000000"} {"mnemonic": "vacgt", "architecture": "ARMv8-A", "full_name": "Vector Absolute Compare Greater Than", "summary": "Compares absolute values (|Vn| > |Vm|).", "syntax": "VACGT.F32 , , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | 1 | 0 | D | 1 | sz | Vn | Vd | 1110 | N | 1 | M | 1 | Vm", "hex_opcode": "0xF3200E50", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "1", "clean": "1"}, {"raw": "sz", "clean": "sz"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1110", "clean": "1110"}, {"raw": "N", "clean": "N"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "1", "clean": "1"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Dest Mask"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Performs a vector absolute comparison of floating-point elements, setting each element of the destination to all 1s if |Vn| > |Vm|, otherwise 0s. This is a NEON floating-point comparison that operates on F32 elements in 128-bit registers. No condition flags are modified; the result is a per-element mask stored in the destination register.", "example": "VACGT.F32 q0, q1, q2", "pseudocode": "for i = 0 to 3\n if abs(Qn[i]) > abs(Qm[i]) then\n Qd[i] ← 0xFFFFFFFF\n else\n Qd[i] ← 0x00000000"} {"mnemonic": "vabal", "architecture": "ARMv8-A", "full_name": "Vector Absolute Difference and Accumulate Long", "summary": "Computes absolute difference of narrow elements and adds to wide acc.", "syntax": "VABAL.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 1 | D | size | Vn | Vd | 0101 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2800500", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "U", "clean": "U"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0101", "clean": "0101"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Dest Wide"}, {"name": "Dn", "desc": "First source 64-bit SIMD/FP register"}, {"name": "Dm", "desc": "Second source 64-bit SIMD/FP register"}], "extension": "NEON (SIMD)", "description": "Computes the absolute difference of narrow elements from two double-width registers and accumulates (adds) the widened result to a quad-width accumulator register. The operand size is determined by the data type specifier (sz field controls .I8, .I16, or .I32 variants). No condition flags are affected; saturation may occur and set the QC flag if enabled.", "example": "VABAL.dt q0, d1, d2", "pseudocode": "for i = 0 to (64 / esize - 1)\n diff ← abs(Dn[i] - Dm[i])\n Qd[i] ← Qd[i] + diff_widened"} {"mnemonic": "vabdl", "architecture": "ARMv8-A", "full_name": "Vector Absolute Difference Long", "summary": "Computes absolute difference of narrow elements to wide result.", "syntax": "VABDL.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 1 | D | size | Vn | Vd | 0111 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2800700", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "U", "clean": "U"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0111", "clean": "0111"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Dest Wide"}, {"name": "Dn", "desc": "First source 64-bit SIMD/FP register"}, {"name": "Dm", "desc": "Second source 64-bit SIMD/FP register"}], "extension": "NEON (SIMD)", "description": "Computes the absolute difference of narrow elements from two double-width registers and widens the result to quad-width. The operand size is determined by the data type specifier (sz field controls .I8, .I16, or .I32 variants). No condition flags are affected; the result is written to the destination without saturation.", "example": "VABDL.dt q0, d1, d2", "pseudocode": "for i = 0 to (64 / esize - 1)\n diff ← abs(Dn[i] - Dm[i])\n Qd[i] ← diff_widened"} {"mnemonic": "vraddhn", "architecture": "ARMv8-A", "full_name": "Vector Rounding Add High Narrow", "summary": "Adds wide elements, rounds, and returns high narrow half.", "syntax": "VRADDHN.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | 1 | 1 | D | size | Vn | Vd | 0100 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF3800400", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0100", "clean": "0100"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Dd", "desc": "Dest Narrow"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Adds corresponding wide elements from two quad-width registers, applies rounding (round to nearest, ties to even), and returns the high half of each widened result as narrow elements in a double-width destination. The operand size is determined by the data type specifier (sz field controls .I16, .I32, or .I64 variants). No condition flags are affected.", "example": "VRADDHN.dt d0, q1, q2", "pseudocode": "for i = 0 to (128 / (esize * 2) - 1)\n sum ← Qn[i] + Qm[i]\n rounded ← sum + (1 << (esize - 1))\n Dd[i] ← (rounded >> esize)[esize - 1:0]"} {"mnemonic": "vsubhn", "architecture": "ARMv8-A", "full_name": "Vector Subtract High Narrow", "summary": "Subtracts wide elements and returns high narrow half.", "syntax": "VSUBHN.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 1 | D | size | Vn | Vd | 0110 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2800600", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0110", "clean": "0110"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Dd", "desc": "Dest Narrow"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Subtracts wide elements of the second quad-width register from the first, and returns the high half of the result as narrow elements in a double-width destination. The operand size is determined by the data type specifier (sz field controls .I16, .I32, or .I64 variants). No condition flags are affected; no rounding is applied.", "example": "VSUBHN.dt d0, q1, q2", "pseudocode": "for i = 0 to (128 / (esize * 2) - 1)\n diff ← Qn[i] - Qm[i]\n Dd[i] ← (diff >> esize)[esize - 1:0]"} {"mnemonic": "vrsubhn", "architecture": "ARMv8-A", "full_name": "Vector Rounding Subtract High Narrow", "summary": "Subtracts wide elements, rounds, and returns high narrow half.", "syntax": "VRSUBHN.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | 1 | 1 | D | size | Vn | Vd | 0110 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF3800600", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "0110", "clean": "0110"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Dd", "desc": "Dest Narrow"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Subtracts wide elements of the second quad-width register from the first, applies rounding (round to nearest), and returns the high half of the result as narrow elements in a double-width destination. The operand size is determined by the data type specifier (sz field controls .I16, .I32, or .I64 variants). No condition flags are affected.", "example": "VRSUBHN.dt d0, q1, q2", "pseudocode": "for i = 0 to (128 / (esize * 2) - 1)\n diff ← Qn[i] - Qm[i]\n rounded ← diff + (1 << (esize - 1))\n Dd[i] ← (rounded >> esize)[esize - 1:0]"} {"mnemonic": "vqdmlal", "architecture": "ARMv8-A", "full_name": "Vector Saturating Doubling Multiply Accumulate Long", "summary": "Multiplies, doubles, saturates, and adds to accumulator (High precision DSP).", "syntax": "VQDMLAL.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 1 | D | size | Vn | Vd | 10 | 0 | 1 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2800900", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Dest Wide"}, {"name": "Dn", "desc": "First source 64-bit SIMD/FP register"}, {"name": "Dm", "desc": "Second source 64-bit SIMD/FP register"}], "extension": "NEON (SIMD)", "description": "Performs a saturating doubling multiply of corresponding narrow elements, then accumulates (adds) the doubled products to a quad-width destination register. The multiplication is doubled with saturation; the operand size is determined by the data type specifier (sz field controls .S16 or .S32 variants). The QC (saturation) flag may be set if overflow occurs during doubling or accumulation.", "example": "VQDMLAL.dt q0, d1, d2", "pseudocode": "for i = 0 to (64 / esize - 1)\n product ← Dn[i] * Dm[i]\n doubled ← SatMul(product, 2) ; saturating double\n Qd[i] ← SatAdd(Qd[i], doubled)"} {"mnemonic": "vqdmlsl", "architecture": "ARMv8-A", "full_name": "Vector Saturating Doubling Multiply Subtract Long", "summary": "Multiplies, doubles, saturates, and subtracts from accumulator.", "syntax": "VQDMLSL.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 1 | D | size | Vn | Vd | 10 | 1 | 1 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2800B00", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "10", "clean": "10"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Dest Wide"}, {"name": "Dn", "desc": "First source 64-bit SIMD/FP register"}, {"name": "Dm", "desc": "Second source 64-bit SIMD/FP register"}], "extension": "NEON (SIMD)", "description": "Performs a saturating doubling multiply of corresponding narrow elements, then subtracts the doubled products from a quad-width destination register. The multiplication is doubled with saturation; the operand size is determined by the data type specifier (sz field controls .S16 or .S32 variants). The QC (saturation) flag may be set if overflow occurs during doubling or subtraction.", "example": "VQDMLSL.dt q0, d1, d2", "pseudocode": "for i = 0 to (64 / esize - 1)\n product ← Dn[i] * Dm[i]\n doubled ← SatMul(product, 2) ; saturating double\n Qd[i] ← SatSub(Qd[i], doubled)"} {"mnemonic": "vqdmulh", "architecture": "ARMv8-A", "full_name": "Vector Saturating Doubling Multiply High", "summary": "Multiplies, doubles, saturates, and keeps high half.", "syntax": "VQDMULH.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 0 | D | size | Vn | Vd | 1011 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2000B00", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1011", "clean": "1011"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Performs signed fixed-point saturating doubling multiply on NEON vector elements, returning the high half of the doubled result. Each element in Qn is multiplied by the corresponding element in Qm, the result is doubled, saturated to the data type range, and the high half is written to Qd. The NEON condition flags are not affected; saturation is indicated via the FPSCR QC bit if the result overflows.", "example": "VQDMULH.dt q0, q1, q2", "pseudocode": "for i = 0 to elements_in_128bit(dt) - 1 do\n product ← (Qn[i] * Qm[i]) * 2\n Qd[i] ← SignedSaturate(product, dt)\nFPSCR.QC ← FPSCR.QC OR (product overflowed)"} {"mnemonic": "vqrdmulh", "architecture": "ARMv8-A", "full_name": "Vector Saturating Rounding Doubling Multiply High", "summary": "Fixed-point multiply with rounding and saturation.", "syntax": "VQRDMULH.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | 1 | 0 | D | size | Vn | Vd | 1011 | N | 1 | M | 0 | Vm", "hex_opcode": "0xF3000B40", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1011", "clean": "1011"}, {"raw": "N", "clean": "N"}, {"raw": "1", "clean": "1"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Destination 128-bit SIMD register"}, {"name": "Qn", "desc": "First source 128-bit SIMD register"}, {"name": "Qm", "desc": "Second source 128-bit SIMD register"}], "extension": "NEON (SIMD)", "description": "Performs signed fixed-point saturating rounding doubling multiply on NEON vector elements, returning the high half with rounding. Each element in Qn is multiplied by the corresponding element in Qm, the result is doubled with rounding applied (via addition of 0x80000000 for 32-bit or 0x8000 for 16-bit before right-shift), saturated to the data type range, and the high half is written to Qd. The NEON condition flags are not affected; saturation is indicated via the FPSCR QC bit.", "example": "VQRDMULH.dt q0, q1, q2", "pseudocode": "for i = 0 to elements_in_128bit(dt) - 1 do\n product ← (Qn[i] * Qm[i]) * 2\n if dt == S32 then\n product ← (product + 0x80000000) >> 32\n else\n product ← (product + 0x8000) >> 16\n Qd[i] ← SignedSaturate(product, dt)\nFPSCR.QC ← FPSCR.QC OR (saturation occurred)"} {"mnemonic": "vqdmull", "architecture": "ARMv8-A", "full_name": "Vector Saturating Doubling Multiply Long", "summary": "Multiplies narrow elements, doubles, and saturates into wide elements.", "syntax": "VQDMULL.
, , ", "encoding": {"format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 1 | D | size | Vn | Vd | 1101 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2800D00", "visual_parts": [{"raw": "1111001", "clean": "1111001"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "D", "clean": "D"}, {"raw": "size", "clean": "size"}, {"raw": "Vn", "clean": "Vn"}, {"raw": "Vd", "clean": "Vd"}, {"raw": "1101", "clean": "1101"}, {"raw": "N", "clean": "N"}, {"raw": "0", "clean": "0"}, {"raw": "M", "clean": "M"}, {"raw": "0", "clean": "0"}, {"raw": "Vm", "clean": "Vm"}], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0"}, "operands": [{"name": "Qd", "desc": "Dest Wide"}, {"name": "Dn", "desc": "First source 64-bit SIMD/FP register"}, {"name": "Dm", "desc": "Second source 64-bit SIMD/FP register"}], "extension": "NEON (SIMD)", "description": "Performs signed fixed-point saturating doubling multiply long on NEON vectors, widening narrow elements to double-width results. Each element in Dn is multiplied by the corresponding element in Dm, the result is doubled, saturated to the wider data type range, and written to the corresponding location in Qd. The NEON condition flags are not affected; saturation is indicated via the FPSCR QC bit.", "example": "VQDMULL.dt q0, d1, d2", "pseudocode": "for i = 0 to elements_in_64bit(dt) - 1 do\n product ← (Dn[i] * Dm[i]) * 2\n Qd[i] ← SignedSaturate(product, widen(dt))\nFPSCR.QC ← FPSCR.QC OR (saturation occurred)"} {"mnemonic": "sxtab", "architecture": "ARMv8-A", "full_name": "Signed Extend and Add Byte", "summary": "Sign-extends a byte from Rm and adds to Rn.", "syntax": "SXTAB , , {, }", "encoding": {"format": "Data Proc", "binary_pattern": "cond | 01101 | 0 | 10 | Rn | Rd | rotate | 0 | 0 | 0111 | Rm", "hex_opcode": "0x06A00070", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01101", "clean": "01101"}, {"raw": "0", "clean": "0"}, {"raw": "10", "clean": "10"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "rotate", "clean": "rotate"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0111", "clean": "0111"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "Accumulator"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Sign-extends the least significant byte of Rm (optionally rotated), adds it to Rn, and writes the result to Rd. This is an A32 instruction that operates on general-purpose registers and does not affect the condition flags. The rotation parameter is optional (ROR by 0, 8, 16, or 24 bits before sign-extension).", "example": "SXTAB r0, r1, r2", "pseudocode": "rotated ← ROR(Rm, rotation)\nbyte_value ← rotated[7:0]\nsign_extended ← SignExtend(byte_value, 32)\nRd ← Rn + sign_extended"} {"mnemonic": "sxtab16", "architecture": "ARMv8-A", "full_name": "Signed Extend and Add Byte 16", "summary": "Sign-extends two bytes and adds to two halfwords.", "syntax": "SXTAB16 , , {, }", "encoding": {"format": "Data Proc", "binary_pattern": "cond | 01101 | 0 | 00 | Rn | Rd | rotate | 0 | 0 | 0111 | Rm", "hex_opcode": "0x06800070", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01101", "clean": "01101"}, {"raw": "0", "clean": "0"}, {"raw": "00", "clean": "00"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "rotate", "clean": "rotate"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0111", "clean": "0111"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "Accumulator"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Sign-extends the least significant byte and the most significant byte of the low halfword from Rm (optionally rotated), adds them separately to the two halfwords of Rn, and writes the results to Rd. This is an A32 instruction that operates on general-purpose registers and does not affect the condition flags. Useful for parallel byte-to-halfword sign-extension and accumulation.", "example": "SXTAB16 r0, r1, r2", "pseudocode": "rotated ← ROR(Rm, rotation)\nbyte0 ← rotated[7:0]\nbyte1 ← rotated[15:8]\nsign_ext0 ← SignExtend(byte0, 16)\nsign_ext1 ← SignExtend(byte1, 16)\nRd[15:0] ← Rn[15:0] + sign_ext0\nRd[31:16] ← Rn[31:16] + sign_ext1"} {"mnemonic": "sxtah", "architecture": "ARMv8-A", "full_name": "Signed Extend and Add Halfword", "summary": "Sign-extends a halfword and adds to Rn.", "syntax": "SXTAH , , {, }", "encoding": {"format": "Data Proc", "binary_pattern": "cond | 01101 | 0 | 11 | Rn | Rd | rotate | 0 | 0 | 0111 | Rm", "hex_opcode": "0x06B00070", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01101", "clean": "01101"}, {"raw": "0", "clean": "0"}, {"raw": "11", "clean": "11"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "rotate", "clean": "rotate"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0111", "clean": "0111"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "Accumulator"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Sign-extends the least significant halfword of Rm (optionally rotated), adds it to Rn, and writes the result to Rd. This is an A32 instruction that operates on general-purpose registers and does not affect the condition flags. The rotation parameter is optional (ROR by 0, 8, 16, or 24 bits before sign-extension).", "example": "SXTAH r0, r1, r2", "pseudocode": "rotated ← ROR(Rm, rotation)\nhalfword_value ← rotated[15:0]\nsign_extended ← SignExtend(halfword_value, 32)\nRd ← Rn + sign_extended"} {"mnemonic": "uxtab", "architecture": "ARMv8-A", "full_name": "Unsigned Extend and Add Byte", "summary": "Zero-extends a byte and adds to Rn.", "syntax": "UXTAB , , {, }", "encoding": {"format": "Data Proc", "binary_pattern": "cond | 01101 | 1 | 10 | Rn | Rd | rotate | 0 | 0 | 0111 | Rm", "hex_opcode": "0x06E00070", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01101", "clean": "01101"}, {"raw": "1", "clean": "1"}, {"raw": "10", "clean": "10"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "rotate", "clean": "rotate"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0111", "clean": "0111"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "Accumulator"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Zero-extends the least significant byte of Rm (optionally rotated), adds it to Rn, and writes the result to Rd. This is an A32 instruction that operates on general-purpose registers and does not affect the condition flags. The rotation parameter is optional (ROR by 0, 8, 16, or 24 bits before zero-extension).", "example": "UXTAB r0, r1, r2", "pseudocode": "rotated ← ROR(Rm, rotation)\nbyte_value ← rotated[7:0]\nzero_extended ← ZeroExtend(byte_value, 32)\nRd ← Rn + zero_extended"} {"mnemonic": "uxtab16", "architecture": "ARMv8-A", "full_name": "Unsigned Extend and Add Byte 16", "summary": "Zero-extends two bytes and adds to two halfwords.", "syntax": "UXTAB16 , , {, }", "encoding": {"format": "Data Proc", "binary_pattern": "cond | 01101 | 1 | 00 | Rn | Rd | rotate | 0 | 0 | 0111 | Rm", "hex_opcode": "0x06C00070", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01101", "clean": "01101"}, {"raw": "1", "clean": "1"}, {"raw": "00", "clean": "00"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "rotate", "clean": "rotate"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0111", "clean": "0111"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "Accumulator"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Zero-extends the least significant byte and the most significant byte of the low halfword from Rm (optionally rotated), adds them separately to the two halfwords of Rn, and writes the results to Rd. This is an A32 instruction that operates on general-purpose registers and does not affect the condition flags. Useful for parallel byte-to-halfword zero-extension and accumulation.", "example": "UXTAB16 r0, r1, r2", "pseudocode": "rotated ← ROR(Rm, rotation)\nbyte0 ← rotated[7:0]\nbyte1 ← rotated[15:8]\nzero_ext0 ← ZeroExtend(byte0, 16)\nzero_ext1 ← ZeroExtend(byte1, 16)\nRd[15:0] ← Rn[15:0] + zero_ext0\nRd[31:16] ← Rn[31:16] + zero_ext1"} {"mnemonic": "uxtah", "architecture": "ARMv8-A", "full_name": "Unsigned Extend and Add Halfword", "summary": "Zero-extends a halfword and adds to Rn.", "syntax": "UXTAH , , {, }", "encoding": {"format": "Data Proc", "binary_pattern": "cond | 01101 | 1 | 11 | Rn | Rd | rotate | 0 | 0 | 0111 | Rm", "hex_opcode": "0x06F00070", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01101", "clean": "01101"}, {"raw": "1", "clean": "1"}, {"raw": "11", "clean": "11"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "rotate", "clean": "rotate"}, {"raw": "0", "clean": "0"}, {"raw": "0", "clean": "0"}, {"raw": "0111", "clean": "0111"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "Accumulator"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Zero-extends a halfword (16-bit) from Rm, optionally rotates it by 0, 8, 16, or 24 bits, and adds the result to Rn, storing the sum in Rd. The instruction executes conditionally based on the condition code and does not update the condition flags. This is an A32 DSP extension instruction.", "example": "UXTAH r0, r1, r2", "pseudocode": "rotated ← ROR(Rm, rotation)\nextended ← ZeroExtend(rotated[15:0], 32)\nRd ← Rn + extended"} {"mnemonic": "smuad", "architecture": "ARMv8-A", "full_name": "Signed Multiply Add Dual", "summary": "Performs two 16x16 multiplies and adds results (Top*Top + Bot*Bot).", "syntax": "SMUAD{X} , , ", "encoding": {"format": "Multiply", "binary_pattern": "cond | 01110 | 000 | Rd | 1111 | Rm | 00 | 0 | 1 | Rn", "hex_opcode": "0x0700F010", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01110", "clean": "01110"}, {"raw": "000", "clean": "000"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1111", "clean": "1111"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "00", "clean": "00"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11:8 | 7:6 | 5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Multiplies two pairs of signed 16-bit values: (Rn[31:16] × Rm[31:16]) + (Rn[15:0] × Rm[15:0]), storing the 32-bit signed result in Rd. The {X} variant swaps the operands of one multiply. The instruction does not update condition flags. A32 DSP extension only.", "example": "SMUAD r0, r1, r2", "pseudocode": "if X then\n prod1 ← SignExtend(Rn[31:16], 32) × SignExtend(Rm[15:0], 32)\n prod2 ← SignExtend(Rn[15:0], 32) × SignExtend(Rm[31:16], 32)\nelse\n prod1 ← SignExtend(Rn[31:16], 32) × SignExtend(Rm[31:16], 32)\n prod2 ← SignExtend(Rn[15:0], 32) × SignExtend(Rm[15:0], 32)\nRd ← prod1 + prod2"} {"mnemonic": "smusd", "architecture": "ARMv8-A", "full_name": "Signed Multiply Subtract Dual", "summary": "Performs two 16x16 multiplies and subtracts results.", "syntax": "SMUSD{X} , , ", "encoding": {"format": "Multiply", "binary_pattern": "cond | 01110 | 000 | Rd | 1111 | Rm | 01 | 0 | 1 | Rn", "hex_opcode": "0x0700F050", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01110", "clean": "01110"}, {"raw": "000", "clean": "000"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1111", "clean": "1111"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "01", "clean": "01"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11:8 | 7:6 | 5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Multiplies two pairs of signed 16-bit values and subtracts: (Rn[31:16] × Rm[31:16]) - (Rn[15:0] × Rm[15:0]), storing the 32-bit signed result in Rd. The {X} variant swaps the operands of one multiply. The instruction does not update condition flags. A32 DSP extension only.", "example": "SMUSD r0, r1, r2", "pseudocode": "if X then\n prod1 ← SignExtend(Rn[31:16], 32) × SignExtend(Rm[15:0], 32)\n prod2 ← SignExtend(Rn[15:0], 32) × SignExtend(Rm[31:16], 32)\nelse\n prod1 ← SignExtend(Rn[31:16], 32) × SignExtend(Rm[31:16], 32)\n prod2 ← SignExtend(Rn[15:0], 32) × SignExtend(Rm[15:0], 32)\nRd ← prod1 - prod2"} {"mnemonic": "smlad", "architecture": "ARMv8-A", "full_name": "Signed Multiply Accumulate Dual", "summary": "Dual multiply add + accumulate.", "syntax": "SMLAD{X} , , , ", "encoding": {"format": "Multiply", "binary_pattern": "cond | 01110 | 000 | Rd | Ra | Rm | 00 | 0 | 1 | Rn", "hex_opcode": "0x07000010", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01110", "clean": "01110"}, {"raw": "000", "clean": "000"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "Ra", "clean": "Ra"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "00", "clean": "00"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11:8 | 7:6 | 5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}, {"name": "Ra", "desc": "Acc"}], "extension": "A32 (DSP)", "description": "Multiplies two pairs of signed 16-bit values and adds the products, then adds the accumulator Ra: (Rn[31:16] × Rm[31:16]) + (Rn[15:0] × Rm[15:0]) + Ra, storing the 32-bit signed result in Rd. The {X} variant swaps operands of one multiply. Does not update condition flags. A32 DSP extension only.", "example": "SMLAD r0, r1, r2, r5", "pseudocode": "if X then\n prod1 ← SignExtend(Rn[31:16], 32) × SignExtend(Rm[15:0], 32)\n prod2 ← SignExtend(Rn[15:0], 32) × SignExtend(Rm[31:16], 32)\nelse\n prod1 ← SignExtend(Rn[31:16], 32) × SignExtend(Rm[31:16], 32)\n prod2 ← SignExtend(Rn[15:0], 32) × SignExtend(Rm[15:0], 32)\nRd ← prod1 + prod2 + Ra"} {"mnemonic": "smlsd", "architecture": "ARMv8-A", "full_name": "Signed Multiply Subtract Dual", "summary": "Dual multiply subtract + accumulate.", "syntax": "SMLSD{X} , , , ", "encoding": {"format": "Multiply", "binary_pattern": "cond | 01110 | 000 | Rd | Ra | Rm | 01 | 0 | 1 | Rn", "hex_opcode": "0x07000050", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01110", "clean": "01110"}, {"raw": "000", "clean": "000"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "Ra", "clean": "Ra"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "01", "clean": "01"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11:8 | 7:6 | 5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}, {"name": "Ra", "desc": "Acc"}], "extension": "A32 (DSP)", "description": "Multiplies two pairs of signed 16-bit values, subtracts the products, then adds accumulator Ra: (Rn[31:16] × Rm[31:16]) - (Rn[15:0] × Rm[15:0]) + Ra, storing the 32-bit signed result in Rd. The {X} variant swaps operands of one multiply. Does not update condition flags. A32 DSP extension only.", "example": "SMLSD r0, r1, r2, r5", "pseudocode": "if X then\n prod1 ← SignExtend(Rn[31:16], 32) × SignExtend(Rm[15:0], 32)\n prod2 ← SignExtend(Rn[15:0], 32) × SignExtend(Rm[31:16], 32)\nelse\n prod1 ← SignExtend(Rn[31:16], 32) × SignExtend(Rm[31:16], 32)\n prod2 ← SignExtend(Rn[15:0], 32) × SignExtend(Rm[15:0], 32)\nRd ← prod1 - prod2 + Ra"} {"mnemonic": "smlald", "architecture": "ARMv8-A", "full_name": "Signed Multiply Accumulate Long Dual", "summary": "Dual multiply add + 64-bit accumulate.", "syntax": "SMLALD{X} , , , ", "encoding": {"format": "Multiply", "binary_pattern": "cond | 01110 | 100 | RdHi | RdLo | Rm | 00 | 0 | 1 | Rn", "hex_opcode": "0x07400010", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01110", "clean": "01110"}, {"raw": "100", "clean": "100"}, {"raw": "RdHi", "clean": "RdHi"}, {"raw": "RdLo", "clean": "RdLo"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "00", "clean": "00"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11:8 | 7:6 | 5 | 4 | 3:0"}, "operands": [{"name": "RdLo", "desc": "Dest Lo"}, {"name": "RdHi", "desc": "Dest Hi"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Multiplies two pairs of signed 16-bit values and adds the products to a 64-bit accumulator: (Rn[31:16] × Rm[31:16]) + (Rn[15:0] × Rm[15:0]) + (RdHi:RdLo), storing the 64-bit signed result in RdHi:RdLo. The {X} variant swaps operands of one multiply. Does not update condition flags. A32 DSP extension only.", "example": "SMLALD r1, r0, r1, r2", "pseudocode": "if X then\n prod1 ← SignExtend(Rn[31:16], 64) × SignExtend(Rm[15:0], 64)\n prod2 ← SignExtend(Rn[15:0], 64) × SignExtend(Rm[31:16], 64)\nelse\n prod1 ← SignExtend(Rn[31:16], 64) × SignExtend(Rm[31:16], 64)\n prod2 ← SignExtend(Rn[15:0], 64) × SignExtend(Rm[15:0], 64)\naccum ← (RdHi << 32) | RdLo\nresult ← prod1 + prod2 + accum\nRdHi ← result[63:32]\nRdLo ← result[31:0]"} {"mnemonic": "smlsld", "architecture": "ARMv8-A", "full_name": "Signed Multiply Subtract Long Dual", "summary": "Dual multiply subtract + 64-bit accumulate.", "syntax": "SMLSLD{X} , , , ", "encoding": {"format": "Multiply", "binary_pattern": "cond | 01110 | 100 | RdHi | RdLo | Rm | 01 | 0 | 1 | Rn", "hex_opcode": "0x07400050", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01110", "clean": "01110"}, {"raw": "100", "clean": "100"}, {"raw": "RdHi", "clean": "RdHi"}, {"raw": "RdLo", "clean": "RdLo"}, {"raw": "Rm", "clean": "Rm"}, {"raw": "01", "clean": "01"}, {"raw": "0", "clean": "0"}, {"raw": "1", "clean": "1"}, {"raw": "Rn", "clean": "Rn"}], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11:8 | 7:6 | 5 | 4 | 3:0"}, "operands": [{"name": "RdLo", "desc": "Dest Lo"}, {"name": "RdHi", "desc": "Dest Hi"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Multiplies two pairs of signed 16-bit values, subtracts the products, and adds to a 64-bit accumulator: (Rn[31:16] × Rm[31:16]) - (Rn[15:0] × Rm[15:0]) + (RdHi:RdLo), storing the 64-bit signed result in RdHi:RdLo. The {X} variant swaps operands of one multiply. Does not update condition flags. A32 DSP extension only.", "example": "SMLSLD r1, r0, r1, r2", "pseudocode": "if X then\n prod1 ← SignExtend(Rn[31:16], 64) × SignExtend(Rm[15:0], 64)\n prod2 ← SignExtend(Rn[15:0], 64) × SignExtend(Rm[31:16], 64)\nelse\n prod1 ← SignExtend(Rn[31:16], 64) × SignExtend(Rm[31:16], 64)\n prod2 ← SignExtend(Rn[15:0], 64) × SignExtend(Rm[15:0], 64)\naccum ← (RdHi << 32) | RdLo\nresult ← prod1 - prod2 + accum\nRdHi ← result[63:32]\nRdLo ← result[31:0]"} {"mnemonic": "qadd8", "architecture": "ARMv8-A", "full_name": "Saturating Add 8", "summary": "Parallel saturating add of 4 signed bytes.", "syntax": "QADD8 , , ", "encoding": {"format": "SIMD Integer", "binary_pattern": "cond | 01100 | 010 | Rn | Rd | 1 | 1 | 1 | 1 | 1 | 00 | 1 | Rm", "hex_opcode": "0x06200F90", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01100", "clean": "01100"}, {"raw": "010", "clean": "010"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Performs four parallel saturating additions on signed bytes: each byte of Rn is added to the corresponding byte of Rm with signed saturation, and the four 8-bit saturated results are packed into Rd. The GE[3:0] condition flags are updated to indicate which byte operations did not saturate. A32 DSP extension only.", "example": "QADD8 r0, r1, r2", "pseudocode": "for i = 0 to 3\n byte_index ← i × 8\n a ← SignExtend(Rn[byte_index + 7 : byte_index], 9)\n b ← SignExtend(Rm[byte_index + 7 : byte_index], 9)\n sum ← a + b\n if sum > 127 then\n result_byte ← 127\n GE[i] ← 0\n elsif sum < -128 then\n result_byte ← -128\n GE[i] ← 0\n else\n result_byte ← sum[7:0]\n GE[i] ← 1\n Rd[byte_index + 7 : byte_index] ← result_byte"} {"mnemonic": "qadd16", "architecture": "ARMv8-A", "full_name": "Saturating Add 16", "summary": "Parallel saturating add of 2 signed halfwords.", "syntax": "QADD16 , , ", "encoding": {"format": "SIMD Integer", "binary_pattern": "cond | 01100 | 010 | Rn | Rd | 1 | 1 | 1 | 1 | 0 | 00 | 1 | Rm", "hex_opcode": "0x06200F10", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01100", "clean": "01100"}, {"raw": "010", "clean": "010"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Performs parallel saturating addition of two signed 16-bit halfwords in Rn and Rm, storing results in Rd. Each halfword is independently saturated to the signed 16-bit range [-32768, 32767] if overflow occurs. No condition flags are affected. Execution restricted to A32 with DSP extension; requires ARMv6 or later.", "example": "QADD16 r0, r1, r2", "pseudocode": "Rd[31:16] ← SignedSat(Rn[31:16] + Rm[31:16], 16)\nRd[15:0] ← SignedSat(Rn[15:0] + Rm[15:0], 16)"} {"mnemonic": "qsub8", "architecture": "ARMv8-A", "full_name": "Saturating Subtract 8", "summary": "Parallel saturating subtract of 4 signed bytes.", "syntax": "QSUB8 , , ", "encoding": {"format": "SIMD Integer", "binary_pattern": "cond | 01100 | 010 | Rn | Rd | 1 | 1 | 1 | 1 | 1 | 11 | 1 | Rm", "hex_opcode": "0x06200FF0", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01100", "clean": "01100"}, {"raw": "010", "clean": "010"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "11", "clean": "11"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Performs parallel saturating subtraction of four signed 8-bit bytes in Rm from Rn, storing results in Rd. Each byte is independently saturated to the signed 8-bit range [-128, 127] if underflow occurs. No condition flags are affected. Execution restricted to A32 with DSP extension; requires ARMv6 or later.", "example": "QSUB8 r0, r1, r2", "pseudocode": "Rd[31:24] ← SignedSat(Rn[31:24] - Rm[31:24], 8)\nRd[23:16] ← SignedSat(Rn[23:16] - Rm[23:16], 8)\nRd[15:8] ← SignedSat(Rn[15:8] - Rm[15:8], 8)\nRd[7:0] ← SignedSat(Rn[7:0] - Rm[7:0], 8)"} {"mnemonic": "qsub16", "architecture": "ARMv8-A", "full_name": "Saturating Subtract 16", "summary": "Parallel saturating subtract of 2 signed halfwords.", "syntax": "QSUB16 , , ", "encoding": {"format": "SIMD Integer", "binary_pattern": "cond | 01100 | 010 | Rn | Rd | 1 | 1 | 1 | 1 | 0 | 11 | 1 | Rm", "hex_opcode": "0x06200F70", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01100", "clean": "01100"}, {"raw": "010", "clean": "010"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "11", "clean": "11"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Performs parallel saturating subtraction of two signed 16-bit halfwords in Rm from Rn, storing results in Rd. Each halfword is independently saturated to the signed 16-bit range [-32768, 32767] if underflow occurs. No condition flags are affected. Execution restricted to A32 with DSP extension; requires ARMv6 or later.", "example": "QSUB16 r0, r1, r2", "pseudocode": "Rd[31:16] ← SignedSat(Rn[31:16] - Rm[31:16], 16)\nRd[15:0] ← SignedSat(Rn[15:0] - Rm[15:0], 16)"} {"mnemonic": "shadd8", "architecture": "ARMv8-A", "full_name": "Signed Halving Add 8", "summary": "Signed add and halving (average) of 4 bytes.", "syntax": "SHADD8 , , ", "encoding": {"format": "SIMD Integer", "binary_pattern": "cond | 01100 | 011 | Rn | Rd | 1 | 1 | 1 | 1 | 1 | 00 | 1 | Rm", "hex_opcode": "0x06300F90", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01100", "clean": "01100"}, {"raw": "011", "clean": "011"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Performs parallel addition of four signed 8-bit bytes from Rn and Rm, then arithmetically shifts each result right by 1 bit (halving), storing in Rd. No saturation occurs; results are always in the range [-128, 127]. No condition flags are affected. Execution restricted to A32 with DSP extension; requires ARMv6 or later.", "example": "SHADD8 r0, r1, r2", "pseudocode": "Rd[31:24] ← (SignExtend(Rn[31:24]) + SignExtend(Rm[31:24])) >> 1\nRd[23:16] ← (SignExtend(Rn[23:16]) + SignExtend(Rm[23:16])) >> 1\nRd[15:8] ← (SignExtend(Rn[15:8]) + SignExtend(Rm[15:8])) >> 1\nRd[7:0] ← (SignExtend(Rn[7:0]) + SignExtend(Rm[7:0])) >> 1"} {"mnemonic": "shadd16", "architecture": "ARMv8-A", "full_name": "Signed Halving Add 16", "summary": "Signed add and halving (average) of 2 halfwords.", "syntax": "SHADD16 , , ", "encoding": {"format": "SIMD Integer", "binary_pattern": "cond | 01100 | 011 | Rn | Rd | 1 | 1 | 1 | 1 | 0 | 00 | 1 | Rm", "hex_opcode": "0x06300F10", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01100", "clean": "01100"}, {"raw": "011", "clean": "011"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Performs parallel addition of two signed 16-bit halfwords from Rn and Rm, then arithmetically shifts each result right by 1 bit (halving), storing in Rd. No saturation occurs; results are always in the range [-32768, 32767]. No condition flags are affected. Execution restricted to A32 with DSP extension; requires ARMv6 or later.", "example": "SHADD16 r0, r1, r2", "pseudocode": "Rd[31:16] ← (SignExtend(Rn[31:16]) + SignExtend(Rm[31:16])) >> 1\nRd[15:0] ← (SignExtend(Rn[15:0]) + SignExtend(Rm[15:0])) >> 1"} {"mnemonic": "shsub8", "architecture": "ARMv8-A", "full_name": "Signed Halving Subtract 8", "summary": "Signed subtract and halving of 4 bytes.", "syntax": "SHSUB8 , , ", "encoding": {"format": "SIMD Integer", "binary_pattern": "cond | 01100 | 011 | Rn | Rd | 1 | 1 | 1 | 1 | 1 | 11 | 1 | Rm", "hex_opcode": "0x06300FF0", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01100", "clean": "01100"}, {"raw": "011", "clean": "011"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "11", "clean": "11"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Performs parallel subtraction of four signed 8-bit bytes in Rm from Rn, then arithmetically shifts each result right by 1 bit (halving), storing in Rd. No saturation occurs; results are always in the range [-128, 127]. No condition flags are affected. Execution restricted to A32 with DSP extension; requires ARMv6 or later.", "example": "SHSUB8 r0, r1, r2", "pseudocode": "Rd[31:24] ← (SignExtend(Rn[31:24]) - SignExtend(Rm[31:24])) >> 1\nRd[23:16] ← (SignExtend(Rn[23:16]) - SignExtend(Rm[23:16])) >> 1\nRd[15:8] ← (SignExtend(Rn[15:8]) - SignExtend(Rm[15:8])) >> 1\nRd[7:0] ← (SignExtend(Rn[7:0]) - SignExtend(Rm[7:0])) >> 1"} {"mnemonic": "shsub16", "architecture": "ARMv8-A", "full_name": "Signed Halving Subtract 16", "summary": "Signed subtract and halving of 2 halfwords.", "syntax": "SHSUB16 , , ", "encoding": {"format": "SIMD Integer", "binary_pattern": "cond | 01100 | 011 | Rn | Rd | 1 | 1 | 1 | 1 | 0 | 11 | 1 | Rm", "hex_opcode": "0x06300F70", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01100", "clean": "01100"}, {"raw": "011", "clean": "011"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "11", "clean": "11"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Performs parallel subtraction of two signed 16-bit halfwords in Rm from Rn, then arithmetically shifts each result right by 1 bit (halving), storing in Rd. No saturation occurs; results are always in the range [-32768, 32767]. No condition flags are affected. Execution restricted to A32 with DSP extension; requires ARMv6 or later.", "example": "SHSUB16 r0, r1, r2", "pseudocode": "Rd[31:16] ← (SignExtend(Rn[31:16]) - SignExtend(Rm[31:16])) >> 1\nRd[15:0] ← (SignExtend(Rn[15:0]) - SignExtend(Rm[15:0])) >> 1"} {"mnemonic": "uqadd8", "architecture": "ARMv8-A", "full_name": "Unsigned Saturating Add 8", "summary": "Unsigned saturating add of 4 bytes.", "syntax": "UQADD8 , , ", "encoding": {"format": "SIMD Integer", "binary_pattern": "cond | 01100 | 110 | Rn | Rd | 1 | 1 | 1 | 1 | 1 | 00 | 1 | Rm", "hex_opcode": "0x06600F90", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01100", "clean": "01100"}, {"raw": "110", "clean": "110"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Performs parallel saturating addition of four unsigned 8-bit bytes from Rn and Rm, storing results in Rd. Each byte is independently saturated to the unsigned 8-bit range [0, 255] if overflow occurs. No condition flags are affected. Execution restricted to A32 with DSP extension; requires ARMv6 or later.", "example": "UQADD8 r0, r1, r2", "pseudocode": "Rd[31:24] ← UnsignedSat(Rn[31:24] + Rm[31:24], 8)\nRd[23:16] ← UnsignedSat(Rn[23:16] + Rm[23:16], 8)\nRd[15:8] ← UnsignedSat(Rn[15:8] + Rm[15:8], 8)\nRd[7:0] ← UnsignedSat(Rn[7:0] + Rm[7:0], 8)"} {"mnemonic": "uqadd16", "architecture": "ARMv8-A", "full_name": "Unsigned Saturating Add 16", "summary": "Unsigned saturating add of 2 halfwords.", "syntax": "UQADD16 , , ", "encoding": {"format": "SIMD Integer", "binary_pattern": "cond | 01100 | 110 | Rn | Rd | 1 | 1 | 1 | 1 | 0 | 00 | 1 | Rm", "hex_opcode": "0x06600F10", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01100", "clean": "01100"}, {"raw": "110", "clean": "110"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Performs unsigned saturating addition of two 16-bit halfwords in parallel. Each halfword of Rn is added to the corresponding halfword of Rm; if the result exceeds the unsigned 16-bit range (0-65535), it saturates to 65535. No condition flags are affected; saturation status is not recorded.", "example": "UQADD16 r0, r1, r2", "pseudocode": "half1_rn ← Rn[15:0]; half2_rn ← Rn[31:16]\nhalf1_rm ← Rm[15:0]; half2_rm ← Rm[31:16]\nsum1 ← half1_rn + half1_rm; sum2 ← half2_rn + half2_rm\nRd[15:0] ← (sum1 > 0xFFFF) ? 0xFFFF : sum1\nRd[31:16] ← (sum2 > 0xFFFF) ? 0xFFFF : sum2"} {"mnemonic": "uqsub8", "architecture": "ARMv8-A", "full_name": "Unsigned Saturating Subtract 8", "summary": "Unsigned saturating subtract of 4 bytes.", "syntax": "UQSUB8 , , ", "encoding": {"format": "SIMD Integer", "binary_pattern": "cond | 01100 | 110 | Rn | Rd | 1 | 1 | 1 | 1 | 1 | 11 | 1 | Rm", "hex_opcode": "0x06600FF0", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01100", "clean": "01100"}, {"raw": "110", "clean": "110"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "11", "clean": "11"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Performs unsigned saturating subtraction of four 8-bit bytes in parallel. Each byte of Rm is subtracted from the corresponding byte of Rn; if the result would be negative, it saturates to 0. No condition flags are affected; saturation status is not recorded.", "example": "UQSUB8 r0, r1, r2", "pseudocode": "for i = 0 to 3 do\n byte_rn ← Rn[8*i+7:8*i]; byte_rm ← Rm[8*i+7:8*i]\n diff ← byte_rn - byte_rm\n Rd[8*i+7:8*i] ← (diff < 0) ? 0 : diff"} {"mnemonic": "uqsub16", "architecture": "ARMv8-A", "full_name": "Unsigned Saturating Subtract 16", "summary": "Unsigned saturating subtract of 2 halfwords.", "syntax": "UQSUB16 , , ", "encoding": {"format": "SIMD Integer", "binary_pattern": "cond | 01100 | 110 | Rn | Rd | 1 | 1 | 1 | 1 | 0 | 11 | 1 | Rm", "hex_opcode": "0x06600F70", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01100", "clean": "01100"}, {"raw": "110", "clean": "110"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "11", "clean": "11"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Performs unsigned saturating subtraction of two 16-bit halfwords in parallel. Each halfword of Rm is subtracted from the corresponding halfword of Rn; if the result would be negative, it saturates to 0. No condition flags are affected; saturation status is not recorded.", "example": "UQSUB16 r0, r1, r2", "pseudocode": "half1_rn ← Rn[15:0]; half2_rn ← Rn[31:16]\nhalf1_rm ← Rm[15:0]; half2_rm ← Rm[31:16]\ndiff1 ← half1_rn - half1_rm; diff2 ← half2_rn - half2_rm\nRd[15:0] ← (diff1 < 0) ? 0 : diff1\nRd[31:16] ← (diff2 < 0) ? 0 : diff2"} {"mnemonic": "uhadd8", "architecture": "ARMv8-A", "full_name": "Unsigned Halving Add 8", "summary": "Unsigned average of 4 bytes.", "syntax": "UHADD8 , , ", "encoding": {"format": "SIMD Integer", "binary_pattern": "cond | 01100 | 111 | Rn | Rd | 1 | 1 | 1 | 1 | 1 | 00 | 1 | Rm", "hex_opcode": "0x06700F90", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01100", "clean": "01100"}, {"raw": "111", "clean": "111"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Performs unsigned halving addition of four 8-bit bytes in parallel, effectively computing the average. Each byte of Rn is added to the corresponding byte of Rm and the result is divided by 2 (rounded down). No condition flags are affected.", "example": "UHADD8 r0, r1, r2", "pseudocode": "for i = 0 to 3 do\n byte_rn ← Rn[8*i+7:8*i]; byte_rm ← Rm[8*i+7:8*i]\n sum ← byte_rn + byte_rm\n Rd[8*i+7:8*i] ← sum >> 1"} {"mnemonic": "uhadd16", "architecture": "ARMv8-A", "full_name": "Unsigned Halving Add 16", "summary": "Unsigned average of 2 halfwords.", "syntax": "UHADD16 , , ", "encoding": {"format": "SIMD Integer", "binary_pattern": "cond | 01100 | 111 | Rn | Rd | 1 | 1 | 1 | 1 | 0 | 00 | 1 | Rm", "hex_opcode": "0x06700F10", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01100", "clean": "01100"}, {"raw": "111", "clean": "111"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "00", "clean": "00"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Performs unsigned halving addition of two 16-bit halfwords in parallel, computing the average of each pair. Each halfword of Rn is added to the corresponding halfword of Rm and the result is divided by 2 (rounded down). No condition flags are affected.", "example": "UHADD16 r0, r1, r2", "pseudocode": "half1_rn ← Rn[15:0]; half2_rn ← Rn[31:16]\nhalf1_rm ← Rm[15:0]; half2_rm ← Rm[31:16]\nsum1 ← half1_rn + half1_rm; sum2 ← half2_rn + half2_rm\nRd[15:0] ← sum1 >> 1\nRd[31:16] ← sum2 >> 1"} {"mnemonic": "uhsub8", "architecture": "ARMv8-A", "full_name": "Unsigned Halving Subtract 8", "summary": "Unsigned halving subtract of 4 bytes.", "syntax": "UHSUB8 , , ", "encoding": {"format": "SIMD Integer", "binary_pattern": "cond | 01100 | 111 | Rn | Rd | 1 | 1 | 1 | 1 | 1 | 11 | 1 | Rm", "hex_opcode": "0x06700FF0", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01100", "clean": "01100"}, {"raw": "111", "clean": "111"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "11", "clean": "11"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Performs unsigned halving subtraction of four 8-bit bytes in parallel. Each byte of Rm is subtracted from the corresponding byte of Rn and the result is divided by 2 (rounded down). No condition flags are affected.", "example": "UHSUB8 r0, r1, r2", "pseudocode": "for i = 0 to 3 do\n byte_rn ← Rn[8*i+7:8*i]; byte_rm ← Rm[8*i+7:8*i]\n diff ← byte_rn - byte_rm\n Rd[8*i+7:8*i] ← diff >> 1"} {"mnemonic": "uhsub16", "architecture": "ARMv8-A", "full_name": "Unsigned Halving Subtract 16", "summary": "Unsigned halving subtract of 2 halfwords.", "syntax": "UHSUB16 , , ", "encoding": {"format": "SIMD Integer", "binary_pattern": "cond | 01100 | 111 | Rn | Rd | 1 | 1 | 1 | 1 | 0 | 11 | 1 | Rm", "hex_opcode": "0x06700F70", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01100", "clean": "01100"}, {"raw": "111", "clean": "111"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "0", "clean": "0"}, {"raw": "11", "clean": "11"}, {"raw": "1", "clean": "1"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Performs unsigned halving subtraction of two 16-bit halfwords in parallel. Each halfword of Rm is subtracted from the corresponding halfword of Rn and the result is divided by 2 (rounded down). No condition flags are affected.", "example": "UHSUB16 r0, r1, r2", "pseudocode": "half1_rn ← Rn[15:0]; half2_rn ← Rn[31:16]\nhalf1_rm ← Rm[15:0]; half2_rm ← Rm[31:16]\ndiff1 ← half1_rn - half1_rm; diff2 ← half2_rn - half2_rm\nRd[15:0] ← diff1 >> 1\nRd[31:16] ← diff2 >> 1"} {"mnemonic": "sel", "architecture": "ARMv8-A", "full_name": "Select Bytes", "summary": "Selects bytes from Rn or Rm based on GE flags.", "syntax": "SEL , , ", "encoding": {"format": "Data Proc", "binary_pattern": "cond | 01101000 | Rn | Rd | 1 | 1 | 1 | 1 | 1011 | Rm", "hex_opcode": "0x06800FB0", "visual_parts": [{"raw": "cond", "clean": "cond"}, {"raw": "01101000", "clean": "01101000"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rd", "clean": "Rd"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1", "clean": "1"}, {"raw": "1011", "clean": "1011"}, {"raw": "Rm", "clean": "Rm"}], "bit_positions": "31:28 | 27:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0"}, "operands": [{"name": "Rd", "desc": "Destination general-purpose register"}, {"name": "Rn", "desc": "First source / base general-purpose register"}, {"name": "Rm", "desc": "Second source / offset general-purpose register"}], "extension": "A32 (DSP)", "description": "Selects bytes from Rn or Rm based on the GE (Greater-than-or-Equal) condition flags, placing the selected bytes into Rd. For each byte position i, if GE[i] is set, the byte from Rn[8*i+7:8*i] is selected; otherwise, the byte from Rm[8*i+7:8*i] is selected. Condition flags are not affected by this instruction.", "example": "SEL r0, r1, r2", "pseudocode": "for i = 0 to 3 do\n if GE[i] == 1 then\n Rd[8*i+7:8*i] ← Rn[8*i+7:8*i]\n else\n Rd[8*i+7:8*i] ← Rm[8*i+7:8*i]"} {"mnemonic": "prfm", "architecture": "ARMv8-A", "full_name": "Prefetch Memory (Immediate)", "summary": "Signals the memory system to prefetch data into cache.", "syntax": "PRFM , [, #]", "encoding": {"format": "Load/Store Imm", "binary_pattern": "11 | 111 | 0 | 01 | 10 | imm12 | Rn | Rt", "hex_opcode": "0xF9800000", "visual_parts": [{"raw": "11", "clean": "11"}, {"raw": "111", "clean": "111"}, {"raw": "0", "clean": "0"}, {"raw": "01", "clean": "01"}, {"raw": "10", "clean": "10"}, {"raw": "imm12", "clean": "imm12"}, {"raw": "Rn", "clean": "Rn"}, {"raw": "Rt", "clean": "Rt"}], "bit_positions": "31:30 | 29:27 | 26 | 25:24 | 23:22 | 21:10 | 9:5 | 4:0"}, "operands": [{"name": "prfop", "desc": "Type (PLDL1KEEP, etc)"}, {"name": "Xn", "desc": "Base Addr"}, {"name": "pimm", "desc": "Positive immediate offset"}], "extension": "Base", "description": "Prefetch Memory (Immediate) signals the memory system to prefetch data from an address calculated by adding a scaled 12-bit immediate offset to a base register. This is a hint instruction that does not architecturally affect register state or condition flags. Execution is AArch64-only and no exceptions are generated for invalid addresses.", "example": "PRFM prfop, [x1, #16]", "pseudocode": "address ← Xn|SP + (imm12 << 3); Prefetch(address, prfop);"} {"mnemonic": "prfm", "architecture": "ARMv8-A", "full_name": "Prefetch Memory (Literal)", "summary": "Prefetches data from a PC-relative address.", "syntax": "PRFM ,