cp.async is a non-blocking instruction which initiates an asynchronous copy operation of data from the location specified by source address operand src to the location specified by destination address… (see the official PTX ISA docs for the full description)

cp.async.ca.shared.global  [shrd],    [gbl + 4], 4;
cp.async.ca.shared::cta.global  [%r0 + 8], [%r1],     8;
cp.async.cg.shared.global  [%r2],     [%r3],     16;

cp.async.cg.shared.global.L2::64B   [%r2],      [%r3],     16;
cp.async.cg.shared.global.L2::128B  [%r0 + 16], [%r1],     16;
// (truncated - see the official PTX ISA docs for the full example)

cp.async is a non-blocking instruction which initiates an asynchronous copy operation of data
from the location specified by source address operand src to the location specified by
destination address operand dst. Operand src specifies a location
in the global state space and dst specifies a location in the shared state space.
Operand cp-size is an integer constant which specifies the size of data in bytes to be copied to
the destination dst. cp-size can only be 4, 8 and 16.
Instruction cp.async allows optionally specifying a 32-bit integer operand src-size. Operand src-size represents the size of the data in bytes to be copied from src to dst and must
be less than cp-size. (see the official PTX ISA docs for the full description)


Data Movement and Conversion Instructions

// global -> shared::cta
cp.async.bulk{.sem}.dst.src.completion_mechanism{.level::cache_hint}{.ignore_oob}
[dstMem], [srcMem], size{, ignoreBytesLeft, ignoreBytesRight}, [mbar] {, cache_policy};

cp.async.bulk is a non-blocking instruction which initiates an asynchronous bulk-copy operation from the location specified by source address operand srcMem to the location specified by destination ad… (see the official PTX ISA docs for the full description)

// .global -> .shared::cta (strictly non-remote):
cp.async.bulk.shared::cta.global.mbarrier::complete_tx::bytes [dstMem], [srcMem], size, [mbar];

cp.async.bulk.shared::cta.global.mbarrier::complete_tx::bytes.L2::cache_hint
                                             [dstMem], [srcMem], size, [mbar], cache_policy;
// (truncated - see the official PTX ISA docs for the full example)

cp.async.bulk is a non-blocking instruction which initiates an asynchronous bulk-copy operation
from the location specified by source address operand srcMem to the location specified by
destination address operand dstMem.
The direction of bulk-copy is from the state space specified by the.src modifier to the state
space specified by the.dst modifiers.
The 32-bit operand size specifies the amount of memory to be copied, in terms of number of
bytes. size must be a multiple of 16. If the value is not a multiple of 16, then the behavior is
undefined. (see the official PTX ISA docs for the full description)


Summary: cp.async.bulk.commit_group instruction creates a new per-thread bulk async-group and batches all prior cp{.reduce}.async.bulk{.prefetch}{.tensor} instructions satisfying the following conditions into…

cp.async.bulk.commit_group instruction creates a new per-thread bulk async-group and batches
all prior cp{.reduce}.async.bulk{.prefetch}{. (see the official PTX ISA docs for the full description)

cp.async.bulk.commit_group instruction creates a new per-thread bulk async-group and batches
all prior cp{.reduce}.async.bulk{.prefetch}{.tensor} instructions satisfying the following
conditions into the new bulk async-group:
The prior cp{.reduce}.async.bulk{.prefetch}{.tensor} instructions use bulk_group based
completion mechanism, and They are initiated by the executing thread but not committed to any bulk async-group.
If there are no uncommitted cp{.reduce}.async.bulk{.prefetch}{.tensor} instructions then cp.async.bulk.commit_group results in an empty bulk async-group.
An executing thread can wait for the completion of all cp{.reduce}.async.bulk{.prefetch}{. (see the official PTX ISA docs for the full description)


cp.async.bulk.prefetch.L2.src{.level::cache_hint}   [srcMem], size {, cache_policy};

cp.async.bulk.prefetch is a non-blocking instruction which may initiate an asynchronous prefetch
of data from the location specified by source address operand srcMem, in. (see the official PTX ISA docs for the full description)

cp.async.bulk.prefetch.L2.global                 [srcMem], size;

cp.async.bulk.prefetch.L2.global.L2::cache_hint  [srcMem], size, policy;

cp.async.bulk.prefetch is a non-blocking instruction which may initiate an asynchronous prefetch
of data from the location specified by source address operand srcMem, in.src statespace, to
the L2 cache.
The 32-bit operand size specifies the amount of memory to be prefetched in terms of number of
bytes. size must be a multiple of 16. If the value is not a multiple of 16, then the behavior is
undefined.  The address srcMem must be aligned to 16 bytes.
When the optional argument cache_policy is specified, the qualifier.level::cache_hint is
required. (see the official PTX ISA docs for the full description)


// global -> L2:
cp.async.bulk.prefetch.tensor.dim.L2.src{.load_mode}{.level::cache_hint} [tensorMap, tensorCoords]
{, im2colInfo } {, cache_policy}

cp.async.bulk.prefetch.tensor is a non-blocking instruction which may initiate an asynchronous
prefetch of tensor data from the location in.src statespace to the L2 cache. (see the official PTX ISA docs for the full description)

.reg .b16 ctaMask, im2colwHalo, im2colOff;
.reg .u16 i2cOffW, i2cOffH, i2cOffD;
.reg .b64 l2CachePolicy;

cp.async.bulk.prefetch.tensor.1d.L2.global.tile  [tensorMap0, {tc0}];
// (truncated - see the official PTX ISA docs for the full example)

cp.async.bulk.prefetch.tensor is a non-blocking instruction which may initiate an asynchronous
prefetch of tensor data from the location in.src statespace to the L2 cache.
The operand tensorMap is the generic address of the opaque tensor-map object which resides
in.param space or.const space or.global space. The operand tensorMap specifies
the properties of the tensor copy operation, as described in Tensor-map.
The tensorMap is accessed in tensormap proxy. (see the official PTX ISA docs for the full description)


// global -> shared::cta
cp.async.bulk.tensor.dim.dst.src{.load_mode}.completion_mechanism{.cta_group}{.level::cache_hint}
[dstMem], [tensorMap, tensorCoords], [mbar]{, im2colInfo} {, cache_policy}

cp.async.bulk.tensor is a non-blocking instruction which initiates an asynchronous copy
operation of tensor data from the location in.src state space to the location in the.dst state space. (see the official PTX ISA docs for the full description)

.reg .b16 ctaMask;
.reg .u16 i2cOffW, i2cOffH, i2cOffD;
.reg .b64 l2CachePolicy;

cp.async.bulk.tensor.1d.shared::cta.global.mbarrier::complete_tx::bytes.tile  [sMem0], [tensorMap0, {tc0}], [mbar0];
// (truncated - see the official PTX ISA docs for the full example)

cp.async.bulk.tensor is a non-blocking instruction which initiates an asynchronous copy
operation of tensor data from the location in.src state space to the location in the.dst state space.
The operand dstMem specifies the location in the.dst state space into which the tensor data
has to be copied and srcMem specifies the location in the.src state space from which the
tensor data has to be copied.
When.dst is specified as.shared::cta, the address dstMem must be in the shared memory
of the executing CTA within the cluster, otherwise the behavior is undefined. (see the official PTX ISA docs for the full description)


cp.async.bulk.wait_group instruction will cause the executing thread to wait until only N or fewer of the most recent bulk async-groups are pending and all the prior bulk async-groups committed by the… (see the official PTX ISA docs for the full description)

cp.async.bulk.wait_group.read   0;
cp.async.bulk.wait_group        2;

cp.async.bulk.wait_group instruction will cause the executing thread to wait until only N or
fewer of the most recent bulk async-groups are pending and all the prior bulk async-groups committed by the executing threads are complete. For example, when N is 0, the executing thread
waits on all the prior bulk async-groups to complete. Operand N is an integer constant.
By default, cp.async.bulk.wait_group instruction will cause the executing thread to wait until
completion of all the bulk async operations in the specified bulk async-group. A bulk async
operation includes the following:
Optionally, reading from the tensormap. Reading from the source locations. (see the official PTX ISA docs for the full description)


cp.async.commit_group instruction creates a new cp.async-group per thread and batches all
prior cp.async instructions initiated by the executing thread but not committed to any cp. (see the official PTX ISA docs for the full description)

// Example 1:
cp.async.ca.shared.global [shrd], [gbl], 4;
cp.async.commit_group ; // Marks the end of a cp.async group

// Example 2:
cp.async.ca.shared.global [shrd1],   [gbl1],   8;
// (truncated - see the official PTX ISA docs for the full example)

cp.async.commit_group instruction creates a new cp.async-group per thread and batches all
prior cp.async instructions initiated by the executing thread but not committed to any cp.async-group into the new cp.async-group. If there are no uncommitted cp.async instructions then cp.async.commit_group results in an empty cp.async-group.
An executing thread can wait for the completion of all cp.async operations in a cp.async-group using cp.async.wait_group.
There is no memory ordering guarantee provided between any two cp.async operations within the
same cp.async-group. So two or more cp.async operations within a cp.async-group copying data
to the same location results in undefined behavior.


Parallel Synchronization and Communication Instructions

Causes an arrive-on operation to be
triggered by the system on the mbarrier object upon the completion of all prior cp.async operations initiated by the
executing thread. (see the official PTX ISA docs for the full description)

// Example 1: no .noinc
mbarrier.init.shared.b64 [shMem], threadCount;
....
cp.async.ca.shared.global [shard1], [gbl1], 4;
cp.async.cg.shared.global [shard2], [gbl2], 16;
....
// (truncated - see the official PTX ISA docs for the full example)

Causes an arrive-on operation to be
triggered by the system on the mbarrier object upon the completion of all prior cp.async operations initiated by the
executing thread. The mbarrier object is at the location specified by the operand addr. The arrive-on operation is
asynchronous to execution of cp.async.mbarrier.arrive.
When.noinc modifier is not specified, the pending count of the mbarrier object is incremented
by 1 prior to the asynchronous arrive-on operation. This
results in a zero-net change for the pending count from the asynchronous arrive-on operation
during the current phase. (see the official PTX ISA docs for the full description)


Summary: cp.async.wait_all instruction will cause the executing thread to wait until all the prior cp.async operations are complete. It is equivalent to cp.async.commit_group immediately followed by cp.async.wait_group 0.

// Example of .wait_all:
cp.async.ca.shared.global [shrd1], [gbl1], 4;
cp.async.cg.shared.global [shrd2], [gbl2], 16;
cp.async.wait_all;  // waits for all prior cp.async to complete

// Example of .wait_group :
// (truncated - see the official PTX ISA docs for the full example)


cp.async.wait_group instruction will cause executing thread to wait till only N or fewer of
the most recent cp.async-group s are pending and all the prior cp. (see the official PTX ISA docs for the full description)

cp.async.wait_group instruction will cause executing thread to wait till only N or fewer of
the most recent cp.async-group s are pending and all the prior cp.async-group s committed by
the executing threads are complete. For example, when N is 0, the executing thread waits on all
the prior cp.async-group s to complete. Operand N is an integer constant.
cp.async.wait_all is equivalent to:
cp.async.commit_group;
cp.async.wait_group 0;
An empty cp.async-group is considered to be trivially complete.
Writes performed by cp.async operations are made visible to the executing thread only after:
The completion of cp.async.wait_all or The completion of cp.async.wait_group on the cp. (see the official PTX ISA docs for the full description)


cp.reduce.async.bulk is a non-blocking instruction which initiates an asynchronous reduction operation on an array of memory locations specified by the destination address operand dstMem with the sour… (see the official PTX ISA docs for the full description)

cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.add.u64
                                                                  [dstMem], [srcMem], size, [mbar];

cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.min.s32
                                                                  [dstMem], [srcMem], size, [mbar];
// (truncated - see the official PTX ISA docs for the full example)

cp.reduce.async.bulk is a non-blocking instruction which initiates an asynchronous reduction
operation on an array of memory locations specified by the destination address operand dstMem with the source array whose location is specified by the source address operand srcMem. The size
of the source and the destination array must be the same and is specified by the operand size.
Each data element in the destination array is reduced inline with the corresponding data element in
the source array with the reduction operation specified by the modifier.redOp. (see the official PTX ISA docs for the full description)


// shared::cta -> global:
cp.reduce.async.bulk.tensor.dim.dst.src.redOp{.load_mode}.completion_mechanism{.level::cache_hint}
[tensorMap, tensorCoords], [srcMem] {,cache_policy}

cp.reduce.async.bulk.tensor is a non-blocking instruction which initiates an asynchronous
reduction operation of tensor data in the.dst state space with tensor data in the.src state space. (see the official PTX ISA docs for the full description)

cp.reduce.async.bulk.tensor.1d.global.shared::cta.add.tile.bulk_group
                                             [tensorMap0, {tc0}], [sMem0];

cp.reduce.async.bulk.tensor.2d.global.shared::cta.and.bulk_group.L2::cache_hint
                                             [tensorMap1, {tc0, tc1}], [sMem1] , policy;
// (truncated - see the official PTX ISA docs for the full example)

cp.reduce.async.bulk.tensor is a non-blocking instruction which initiates an asynchronous
reduction operation of tensor data in the.dst state space with tensor data in the.src state space.
The operand srcMem specifies the location of the tensor data in the.src state space using
which the reduction operation has to be performed.
The operand tensorMap is the generic address of the opaque tensor-map object which resides
in.param space or.const space or.global space. The operand tensorMap specifies
the properties of the tensor copy operation, as described in Tensor-map.
The tensorMap is accessed in tensormap proxy. (see the official PTX ISA docs for the full description)


// Range-based policy
createpolicy.range{.global}.level::primary_priority{.level::secondary_priority}.b64
cache_policy, [a], primary-size, total-size;

The createpolicy instruction creates a cache eviction policy for the specified cache level in an
opaque 64-bit register specified by the destination operand cache_policy. (see the official PTX ISA docs for the full description)

createpolicy.fractional.L2::evict_last.b64                      policy, 1.0;
createpolicy.fractional.L2::evict_last.L2::evict_unchanged.b64  policy, 0.5;

createpolicy.range.L2::evict_last.L2::evict_first.b64
                                            policy, [ptr], 0x100000, 0x200000;
// (truncated - see the official PTX ISA docs for the full example)

The createpolicy instruction creates a cache eviction policy for the specified cache level in an
opaque 64-bit register specified by the destination operand cache_policy. The cache eviction
policy specifies how cache eviction priorities are applied to global memory addresses used in memory
operations with.level::cache_hint qualifier.
There are two types of cache eviction policies:
Range-based policy The cache eviction policy created using createpolicy.range specifies the cache eviction
behaviors for the following three address ranges: [a.. a + (primary-size - 1)] referred to as primary range. [a + primary-size.. a + (total-size - 1)] referred to as trailing secondary range. (see the official PTX ISA docs for the full description)


Summary: Convert a value between integer and/or floating-point types with an explicit rounding mode.

Type conversion between the source (atype) and destination (dtype) types.

Floating-point narrowing/widening conversion with explicit IEEE rounding mode.

d = convert(a, atype -> dtype) using the specified rounding mode; saturating forms clamp on overflow.

cvt.f32.s32 f,i;
cvt.s32.f64 j,r;     // float-to-int saturates by default
cvt.rni.f32.f32 x,y; // round to nearest int, result is fp
cvt.f32.f32 x,y;     // note .ftz behavior for sm_1x targets
cvt.rn.relu.f16.f32      b, f;        // result is saturated with .relu saturation mode
cvt.rz.f16x2.f32         b1, f, f1;   // convert two fp32 values to packed fp16 outputs
// (truncated - see the official PTX ISA docs for the full example)

Convert between different types and sizes.
For.f16x2 and.bf16x2 instruction type, two inputs a and b of.f32 type are
converted into.f16 or.bf16 type and the converted values are packed in the destination
register d, such that the value converted from input a is stored in the upper half of d and the value converted from input b is stored in the lower half of d
For.f16x2 instruction type, destination operand d has.f16x2 or.b32 type. For.bf16 instruction type, operand d has.b16 type. For.bf16x2 instruction type,
operand d has.b32 type. For.tf32 instruction type, operand d has.b32 type.
When converting to.e4m3x2 /.e5m2x2 data formats, the destination operand d has.b16 type. (see the official PTX ISA docs for the full description)


cvt.pack.sat.convertType.abType  d, a, b;

Convert two 32-bit integers a and b into specified type and pack the results into d.
Destination d is an unsigned 32-bit integer. (see the official PTX ISA docs for the full description)

ta = a < MIN(convertType) ? MIN(convertType) : a;
ta = a > MAX(convertType) ? MAX(convertType) : a;
tb = b < MIN(convertType) ? MIN(convertType) : b;
tb = b > MAX(convertType) ? MAX(convertType) : b;

size = sizeInBits(convertType);
td = tb ;
for (i = size; i <= 2 * size - 1; i++) {
    td[i] = ta[i - size];
}

if (isU16(convertType) || isS16(convertType)) {
    d = td;
} else {
    for (i = 0; i < 2 * size; i++) {
        d[i] = td[i];
    }
    for (i = 2 * size; i <= 31; i++) {
        d[i] = c[i - 2 * size];
    }
}

cvt.pack.sat.s16.s32      %r1, %r2, %r3;           // 32-bit to 16-bit conversion
cvt.pack.sat.u8.s32.b32   %r4, %r5, %r6, 0;        // 32-bit to 8-bit conversion
cvt.pack.sat.u8.s32.b32   %r7, %r8, %r9, %r4;      // %r7 = { %r5, %r6, %r8, %r9 }
cvt.pack.sat.u4.s32.b32   %r10, %r12, %r13, %r14;  // 32-bit to 4-bit conversion
cvt.pack.sat.s2.s32.b32   %r15, %r16, %r17, %r18;  // 32-bits to 2-bit conversion

Convert two 32-bit integers a and b into specified type and pack the results into d.
Destination d is an unsigned 32-bit integer. Source operands a and b are integers of
type.abType and the source operand c is an integer of type.cType.
The inputs a and b are converted to values of type specified by.convertType with
saturation and the results after conversion are packed into lower bits of d.
If operand c is specified then remaining bits of d are copied from lower bits of c.


// convert const, global, local, or shared address to generic address
cvta.space.size  p, a;        // source address in register a

Convert a const, Kernel Function Parameters (.param ), global, local, or shared address to a generic address, or vice-versa. The
source and destination addresses must be the same size. (see the official PTX ISA docs for the full description)

cvta.const.u32   ptr,cvar;
cvta.local.u32   ptr,lptr;
cvta.shared::cta.u32  p,As+4;
cvta.shared::cluster.u32 ptr, As;
cvta.to.global.u32  p,gptr;
cvta.param.u64   ptr,pvar;
// (truncated - see the official PTX ISA docs for the full example)

Convert a const, Kernel Function Parameters (.param ), global, local, or shared address to a generic address, or vice-versa. The
source and destination addresses must be the same size. Use cvt.u32.u64 or cvt.u64.u32 to
truncate or zero-extend addresses.
For variables declared in.const, Kernel Function Parameters (.param ),.global,.local, or.shared state space, the generic address of the variable may be taken using cvta. (see the official PTX ISA docs for the full description)


Semantically, this behaves like a weak write of an unstable indeterminate value: reads of memory locations with unstable indeterminate values may return different bit patterns each time until the memo… (see the official PTX ISA docs for the full description)

discard.global.L2 [ptr], 128;
ld.weak.u32 r0, [ptr];
ld.weak.u32 r1, [ptr];
// The values in r0 and r1 may differ!

Semantically, this behaves like a weak write of an unstable indeterminate value:
reads of memory locations with unstable indeterminate values may return different
bit patterns each time until the memory is overwritten.
This operation hints to the implementation that data in the specified cache.level can be destructively discarded without writing it back to memory.
The operand size is an integer constant that specifies the length in bytes of the
address range [a, a + size) to write unstable indeterminate values into.
The only supported value for the size operand is 128.
If no state space is specified then Generic Addressing is used. (see the official PTX ISA docs for the full description)


Summary: Divide the first operand by the second.

Integer division.

Fast approximate single-precision division.

IEEE-754 round-to-nearest double-precision division.

div.s32  b,n,i;

div.approx.ftz.f32  diam,circum,3.14159;
div.full.ftz.f32    x, y, z;
div.rn.f64          xd, yd, zd;

Divides a by b, stores result in d.


Two-way 16-bit to 8-bit dot product which is accumulated in 32-bit result.
Operand a and b are 32-bit inputs. (see the official PTX ISA docs for the full description)

d = c;
// Extract two 16-bit values from a 32-bit input and sign or zero extend
// based on input type.
Va = extractAndSignOrZeroExt_2(a, .atype);

// Extract four 8-bit values from a 32-bit input and sign or zer extend
// based on input type.
Vb = extractAndSignOrZeroExt_4(b, .btype);

b_select = (.mode == .lo) ? 0 : 2;

for (i = 0; i < 2; ++i) {
    d += Va[i] * Vb[b_select + i];
}

Two-way 16-bit to 8-bit dot product which is accumulated in 32-bit result.
Operand a and b are 32-bit inputs. Operand a holds two 16-bits inputs in packed form and
operand b holds 4 byte inputs in packed form for dot product.
Depending on the.mode specified, either lower half or upper half of operand b will be used
for dot product.
Operand c has type.u32 if both.atype and.btype are.u32 else operand c has type.s32.


Four-way byte dot product which is accumulated in 32-bit result.
Operand a and b are 32-bit inputs which hold 4 byte inputs in packed form for dot product.
Operand c has type.u32 if both.atype and. (see the official PTX ISA docs for the full description)

d = c;

// Extract 4 bytes from a 32bit input and sign or zero extend
// based on input type.
Va = extractAndSignOrZeroExt_4(a, .atype);
Vb = extractAndSignOrZeroExt_4(b, .btype);

for (i = 0; i < 4; ++i) {
    d += Va[i] * Vb[i];
}

Four-way byte dot product which is accumulated in 32-bit result.
Operand a and b are 32-bit inputs which hold 4 byte inputs in packed form for dot product.
Operand c has type.u32 if both.atype and.btype are.u32 else operand c has type.s32.


elect.sync elects one predicated active leader thread from among a set of threads specified by membermask. laneid of the elected thread is returned in the 32-bit destination operand d. (see the official PTX ISA docs for the full description)

elect.sync elects one predicated active leader thread from among a set of threads specified by membermask. laneid of the elected thread is returned in the 32-bit destination operand d. The sink symbol ‘_’ can be used for destination operand d. The predicate destination p is set to True for the leader thread, and False for all other threads.
Operand membermask specifies a 32-bit integer indicating the set of threads from which a leader
is to be elected. The behavior is undefined if the executing thread is not in membermask.
Election of a leader thread happens deterministically, i.e. (see the official PTX ISA docs for the full description)


Half Precision Floating-Point Instructions

Summary: Raise 2 to the power a.

Raise 2 to the power a.

Raise 2 to the power a.
The type of operands d and a are as specified by.type.
For.f16x2 or. (see the official PTX ISA docs for the full description)

ex2.approx.ftz.f32  xa, a;

ex2.approx.f16         h1, h0;
ex2.approx.f16x2       hd1, hd0;
ex2.approx.ftz.bf16    b1, b2;
ex2.approx.ftz.bf16x2  hb1, hb2;

Raise 2 to the power a.
The type of operands d and a are as specified by.type.
For.f16x2 or.bf16x2 instruction type, each of the half-word operands are operated in
parallel and the results are packed appropriately into a.f16x2 or.bf16x2.
For.f16 instruction type, operands d and a have.f16 or.b16 type.
For.f16x2 instruction type, operands d and a have.f16x2 or.b32 type.
For.bf16 instruction type, operands d and a have.b16 type.
For.bf16x2 instruction type, operands d and a have.b32 type.


Summary:
Ends execution of a thread.
Barriers exclusively waiting on arrivals from exited threads are always released.


Submits prior fabric operations issued by the current thread. (see the official PTX ISA docs for the full description)

Submits prior fabric operations issued by the current thread. For any thread to observe completion
of fabric operations via an mbarrier object, the issuing thread is required to submit those
operations before the barrier phase tracking these operations advances. Otherwise, the behavior is
undefined. See Life of a Fabric Operation.
If.op_restrict::fetching is specified, then only prior fabric.try_get and fabric.try_pullred operations issued by the current thread are submitted. Otherwise, all prior
fabric operations issued by the current thread are submitted.
This operation has no effect on fabric operations that have already been submitted.


Summary: Asynchronously copies size bytes from fabric handle [srcLeId, srcDataOff] to destination memory [dst], where srcLeId is a 32-bit unsigned value denoting the logical endpoint identifier, and…

fabric.try_get.async.dst.completion_mechanism.sem.scope.b128 [dst], [srcLeId, srcDataOff], size, [bar];

Asynchronously copies size bytes from fabric handle [srcLeId, srcDataOff] to destination memory [dst], where srcLeId is a 32-bit unsigned value denoting the logical endpoint identifier, and srcDataOff… (see the official PTX ISA docs for the full description)

fabric.try_get.async.shared::cta.mbarrier::complete_tx::bytes.mbarrier::report::fabric.relaxed.sys.b128 [dstSmem], [srcLeId, srcLeOff], 0x100, [mbar];

fabric.try_get.async.shared::cta.relaxed.sys.mbarrier::complete_tx::bytes.mbarrier::report::fabric.b128 [dstSmem], [srcLeId, srcLeOff], sizeBytes, [mbar];

Asynchronously copies size bytes from fabric handle [srcLeId, srcDataOff] to destination
memory [dst], where srcLeId is a 32-bit unsigned value denoting the logical endpoint
identifier, and srcDataOff is a 64-bit unsigned value denoting the base offset of the
resource to access within the logical endpoint associated with srcLeId.
The logical endpoint associated with srcLeId must be a unicast logical endpoint.
The size operand is 32 bits and specifies the number of bytes to be copied. It must be a
multiple of 16; otherwise, the behavior is undefined. The range [dst, dst + size - 1] must be
in bounds of the destination memory space. (see the official PTX ISA docs for the full description)


fabric.try_pullred.async.multimem.dst.completion_mechanism.sem.scope.redOpBit.typeBit.sync [dst], [srcLeId, srcDataOff], size, [bar], imm-membermask;

Initiates asynchronous loads from multiple resources pointed to by multicast fabric handle [srcLeId, srcDataOff], of size bytes, and performs element-wise reduction on data across
each of the loads. (see the official PTX ISA docs for the full description)

fabric.try_pullred.async.multimem.mbarrier::complete_tx::bytes.mbarrier::report::fabric.shared::cta.f32.add.sync.relaxed.sys [dst], [leId, offset], size, [mbar], imm-membermask;

Initiates asynchronous loads from multiple resources pointed to by multicast fabric handle [srcLeId, srcDataOff], of size bytes, and performs element-wise reduction on data across
each of the loads. The result is stored in [dst, dst + size - 1]. srcLeId is a 32-bit
unsigned value denoting the logical endpoint identifier, and srcDataOff is a 64-bit unsigned
value denoting the base offset of the resources to access within the multicast logical endpoint
associated with srcLeId.
The size operand is 32 bits and specifies the number of bytes to be copied. It must be a
multiple of 16; otherwise, the behavior is undefined. (see the official PTX ISA docs for the full description)


Summary: Asynchronously copies size bytes from [src] to destination fabric handle [dstLeId, dstDataOff], where dstLeId is a 32-bit unsigned value denoting the logical endpoint identifier, and dstDataOff is a…

fabric.try_put.async{.multimem}.src.completion_mechanism0.sem.scope.b128 [dstLeId, dstDataOff], [src], size, [bar];

Asynchronously copies size bytes from [src] to destination fabric handle [dstLeId, dstDataOff], where dstLeId is a 32-bit unsigned value denoting the logical
endpoint identifier, and dstDataOff is a 6 (see the official PTX ISA docs for the full description)

fabric.try_put.async.shared::cta.mbarrier::complete_tx::16B.mbarrier::report::fabric.relaxed.sys.b128 [dstLeId, dstLeOffData], [srcSmem], 0x100, [mbar];

fabric.try_put.async.counted::bytes.shared::cta.mbarrier::complete_tx::16B.mbarrier::report::fabric.relaxed.sys.b128 [dstLeId, dstLeOffData, dstLeOffCntr], [srcSmem], size, [mbar];

Asynchronously copies size bytes from [src] to destination fabric handle [dstLeId, dstDataOff], where dstLeId is a 32-bit unsigned value denoting the logical
endpoint identifier, and dstDataOff is a 64-bit unsigned value denoting the base offset of
the resource to access within the logical endpoint associated with dstLeId.
The size operand is 32 bits and specifies the number of bytes to be copied. It must be a
multiple of 16; otherwise, the behavior is undefined. The range [src, src + size - 1] must
be in bounds of the source memory space. (see the official PTX ISA docs for the full description)


Summary: Asynchronously copies size bytes from [src] to destination fabric handle [dstLeId, dstDataOff] with element-wise reduction, where dstLeId is a 32-bit unsigned value denoting the logical endpoint…

fabric.try_red.async{.multimem}.src.completion_mechanism0.sem.scope.redOpBit.typeBit [dstLeId, dstDataOff], [src], size, [bar];

Asynchronously copies size bytes from [src] to destination fabric handle [dstLeId, dstDataOff] with element-wise reduction, where dstLeId is a 32-bit unsigned value denoting the logical endpoint ident… (see the official PTX ISA docs for the full description)

fabric.try_red.async.shared::cta.mbarrier::complete_tx::16B.mbarrier::report::fabric.relaxed.sys.add.u32 [dstLeId, dstLeOffData], [srcSmem], size, [mbar];

fabric.try_red.async.counted::bytes.shared::cta.mbarrier::complete_tx::16B.mbarrier::report::fabric.add.u32 [dstLeId, dstLeOffData, dstLeOffCntr], [srcSmem], size, [mbar];

Asynchronously copies size bytes from [src] to destination fabric handle [dstLeId, dstDataOff] with element-wise reduction, where dstLeId is a 32-bit unsigned
value denoting the logical endpoint identifier, and dstDataOff is a 64-bit unsigned value
denoting the base offset of the resource to access within the logical endpoint associated with dstLeId.
The size operand is 32 bits and specifies the number of bytes to be copied. It must be a
multiple of 16; otherwise, the behavior is undefined. The source range [src, src + size - 1] must be in bounds of the source memory space. (see the official PTX ISA docs for the full description)


Fabric-read completion mechanism instruction fabric.wait waits on the local
shared memory (.shared::cta ) reads of submitted fabric operations. (see the official PTX ISA docs for the full description)

Fabric-read completion mechanism instruction fabric.wait waits on the local
shared memory (.shared::cta ) reads of submitted fabric operations. This enables
overwriting the shared memory read by these operations before they complete.


Summary: The fence instruction establishes an ordering between memory accesses requested by this thread, as described by the memory consistency model.

membar.gl;
membar.cta;
membar.sys;
fence.sc.cta;
fence.sc.cluster;
fence.proxy.alias;
// (truncated - see the official PTX ISA docs for the full example)

The fence instruction establishes an ordering between memory accesses requested by this thread (ld, st, atom and red instructions), as described by the memory consistency model. fence.acq_rel is a light-weight fence sufficient for memory synchronization in most programs, while fence.sc is a slower fence that can restore sequential consistency when used in sufficient places, at the cost of performance. The legacy membar instruction covers the thread-scope membar.level forms.


Summary: Compute (a * b) + c with a single rounding step for improved precision over mad.

Double-precision fused multiply-add.

Single-precision fused multiply-add.

d = round_once(a * b + c), the product is not rounded before the addition.

fma.rn.ftz.f32  w,x,y,z;
@p  fma.rn.f64      d,a,b,c;
    fma.rp.ftz.f32x2 p,q,r,s;

// scalar f16 fused multiply-add
fma.rn.f16         d0, a0, b0, c0;
fma.rn.f16         d1, a1, b1, c1;
fma.rn.relu.f16    d1, a1, b1, c1;
fma.rn.oob.f16      d1, a1, b1, c1;
fma.rn.oob.relu.f16 d1, a1, b1, c1;
// (truncated - see the official PTX ISA docs for the full example)

.reg .f32 fc, fd;
.reg .f16 ha, hb;
fma.rz.sat.f32.f16.sat   fd, ha, hb, fc;

Performs a fused multiply-add with no loss of precision in the intermediate product and addition.
For.f16x2 and.bf16x2 instruction type, forms input vectors by half word values from source
operands. Half-word operands are then operated in parallel to produce.f16x2 or.bf16x2 result in destination.
For.f16 instruction type, operands d, a, b and c have.f16 or.b16 type. For.f16x2 instruction type, operands d, a, b and c have.b32 type. For.bf16 instruction type, operands d, a, b and c have.b16 type. For.bf16x2 instruction type, operands d, a, b and c have.b32 type.


Given a 32-bit value mask and an integer value base (between 0 and 31), find the n-th (given
by offset) set bit in mask from the base bit, and store the bit position in d. (see the official PTX ISA docs for the full description)

d = 0xffffffff;
if (offset == 0) {
    if (mask[base] == 1) {
        d = base;
    }
} else {
    pos = base;
    count = |offset| - 1;
    inc = (offset > 0) ? 1 : -1;

    while ((pos >= 0) && (pos < 32)) {
        if (mask[pos] == 1) {
            if (count == 0) {
              d = pos;
              break;
           } else {
               count = count - 1;
           }
        }
        pos = pos + inc;
    }
}

fns.b32 d, 0xaaaaaaaa, 3, 1;   // d = 3
fns.b32 d, 0xaaaaaaaa, 3, -1;  // d = 3
fns.b32 d, 0xaaaaaaaa, 2, 1;   // d = 3
fns.b32 d, 0xaaaaaaaa, 2, -1;  // d = 1

Given a 32-bit value mask and an integer value base (between 0 and 31), find the n-th (given
by offset) set bit in mask from the base bit, and store the bit position in d. If not
found, store 0xffffffff in d.
Operand mask has a 32-bit type. Operand base has.b32,.u32 or.s32 type. Operand offset has.s32 type. Destination d has type.b32.
Operand base must be <= 31, otherwise behavior is undefined.


Write the destination register d with the rank of the CTA which contains the address specified
in operand a.
Instruction type.type indicates the type of source operand a.
When space is. (see the official PTX ISA docs for the full description)

getctarank.shared::cluster.u32 d1, addr;
getctarank.shared::cluster.u64 d2, sh + 4;
getctarank.u64                 d3, src;

Write the destination register d with the rank of the CTA which contains the address specified
in operand a.
Instruction type.type indicates the type of source operand a.
When space is.shared::cluster, source a is either a shared memory variable or a register
containing a valid shared memory address. When the optional qualifier.space is not specified, a is a register containing a generic addresses pointing to shared memory. Destination d is
always a 32-bit register which holds the rank of the CTA.


The griddepcontrol instruction allows the dependent grids and prerequisite grids as defined by
the runtime, to control execution in the following way:. (see the official PTX ISA docs for the full description)

The griddepcontrol instruction allows the dependent grids and prerequisite grids as defined by
the runtime, to control execution in the following way:.launch_dependents modifier signals that specific dependents the runtime system designated to
react to this instruction can be scheduled as soon as all other CTAs in the grid issue the same
instruction or have completed. The dependent may launch before the completion of the current
grid. There is no guarantee that the dependent will launch before the completion of the current
grid. Repeated invocations of this instruction by threads in the current CTA will have no additional
side effects past that of the first invocation. (see the official PTX ISA docs for the full description)


isspacep.space  p, a;    // result is .pred

Write predicate register p with 1 if generic address a falls within the specified state
space window and with 0 otherwise. (see the official PTX ISA docs for the full description)

isspacep.const           iscnst, cptr;
isspacep.global          isglbl, gptr;
isspacep.local           islcl,  lptr;
isspacep.shared          isshrd, sptr;
isspacep.param::entry    isparam, pptr;
isspacep.shared::cta     isshrdcta, sptr;
// (truncated - see the official PTX ISA docs for the full example)

Write predicate register p with 1 if generic address a falls within the specified state
space window and with 0 otherwise. Destination p has type.pred; the source address
operand must be of type.u32 or.u64.
isspacep.param{::entry} returns 1 if the generic address falls within the window of Kernel Function Parameters, otherwise returns 0. If.param is specified without any sub-qualifiers then it defaults to.param::entry.
isspacep.global returns 1 for Kernel Function Parameters as.param window is contained within the.global window.
If no sub-qualifier is specified with.shared state space, then::cta is assumed by default.
Note ispacep. (see the official PTX ISA docs for the full description)


istypep.type   p, a;  // result is .pred

Write predicate register p with 1 if register a points to an opaque variable of the
specified type, and with 0 otherwise. Destination p has type.pred; the source address
operand must be of type.u64.

istypep.texref istex, tptr;
istypep.samplerref issampler, sptr;
istypep.surfref issurface, surfptr;


Summary: Load a value from the specified state space into a register.

Load from an explicit state space.

Load through the read-only (non-coherent) data cache.

ld.global.f32    d,[a];
ld.shared.v4.b32 Q,[p];
ld.const.s32     d,[p+4];
ld.local.b32     x,[p+-8]; // negative offset
ld.local.b64     x,[240];  // immediate address
// (truncated - see the official PTX ISA docs for the full example)

Load register variable d from the location specified by the source address operand a in
specified state space. If no state space is given, perform the load using Generic Addressing.
If no sub-qualifier is specified with.shared state space, then::cta is assumed by default.
Supported addressing modes for operand a and alignment requirements are described in Addresses as Operands
If no sub-qualifier is specified with.param state space, then:::func is assumed when access is inside a device function.::entry is assumed when accessing kernel function parameters from entry function. (see the official PTX ISA docs for the full description)


ld.global{.cop}.nc{.level::cache_hint}{.level::prefetch_size}.type                 d, [a]{, cache_policy};

Load register variable d from the location specified by the source address operand a in the
global state space, and optionally cache in non-coherent read-only cache. (see the official PTX ISA docs for the full description)

d = a;             // named variable a
d = *(&a+immOff)   // variable-plus-offset
d = *a;            // register
d = *(a+immOff);   // register-plus-offset
d = *(immAddr);    // immediate address

ld.global.nc.f32           d, [a];
ld.gloal.nc.L1::evict_last.u32 d, [a];

createpolicy.fractional.L2::evict_last.b64 cache_policy, 0.5;
ld.global.nc.L2::cache_hint.f32  d, [a], cache_policy;
// (truncated - see the official PTX ISA docs for the full example)

Load register variable d from the location specified by the source address operand a in the
global state space, and optionally cache in non-coherent read-only cache.
Note On some architectures, the texture cache is larger, has higher bandwidth, and longer latency than
the global memory cache. For applications with sufficient parallelism to cover the longer
latency, ld.global.nc should offer better performance than ld.global on such
architectures.
The address operand a shall contain a global address.
Supported addressing modes for operand a and alignment requirements are
described in Addresses as Operands.
The.v8 (.vec ) qualifier is supported if:.type is.b32,.s32,.u32, or. (see the official PTX ISA docs for the full description)


Warp Level Matrix Multiply-Accumulate Instructions

Collectively load one or more matrices across all threads in a warp from the location indicated by
the address operand p, from.shared state space into destination register r. (see the official PTX ISA docs for the full description)

// Load a single 8x8 matrix using 64-bit addressing
.reg .b64 addr;
.reg .b32 d;
ldmatrix.sync.aligned.m8n8.x1.shared::cta.b16 {d}, [addr];

// Load two 8x8 matrices in column-major format
// (truncated - see the official PTX ISA docs for the full example)

Collectively load one or more matrices across all threads in a warp from the location indicated by
the address operand p, from.shared state space into destination register r. If no state
space is provided, generic addressing is used, such that the address in p points into.shared space. If the generic address doesn’t fall in.shared state space, then the behavior
is undefined.
The.shape qualifier indicates the dimensions of the matrices being loaded. (see the official PTX ISA docs for the full description)


ldu{.ss}.type      d, [a];       // load from address

Load read-only data into register variable d from the location specified by the source address operand a in the global state space, where the address is guaranteed to be the same across all threads in… (see the official PTX ISA docs for the full description)

ldu.global.f32    d,[a];
ldu.global.b32    d,[p+4];
ldu.global.v4.f32 Q,[p];
ldu.global.b128   d,[a];

Load read-only data into register variable d from the location specified by the source address
operand a in the global state space, where the address is guaranteed to be the same across all
threads in the warp. If no state space is given, perform the load using Generic Addressing.
Supported addressing modes for operand a and alignment requirements are described in Addresses as Operands.


Summary: Fast hardware approximation of log2(x).

Reduced-precision base-2 logarithm.

Determine the log 2 of a.


Compute bitwise logical operation on inputs a, b, c and store the result in destination d.
Optionally,. (see the official PTX ISA docs for the full description)

F = GetFunctionFromTable(immLut); // returns the function corresponding to immLut value
d = F(a, b, c);
if (BoolOp specified) {
    p = (d != 0) BoolOp q;
}

Compute bitwise logical operation on inputs a, b, c and store the result in destination d.
Optionally,.BoolOp can be specified to compute the predicate result p by performing a
Boolean operation on the destination operand d with the predicate q in the following manner:
p = (d != 0) BoolOp q;
The sink symbol ‘_’ may be used in place of the destination operand d when.BoolOp qualifier
is specified.
The logical operation is defined by a look-up table which, for 3 inputs, can be represented as an
8-bit value specified by operand immLut as described below. (see the official PTX ISA docs for the full description)


Summary: Compute (a * b) + c as two rounding steps (unlike fma, which fuses them into one).

Integer multiply-add.

Single-precision floating-point multiply-add (not fused).

@p  mad.lo.s32 d,a,b,c;
    mad.lo.s32 r,p,q,r;

@p  mad.f32  d,a,b,c;

Multiplies two values, optionally extracts the high or low half of the intermediate result, and adds
a third value. Writes the result into a destination register.


Extended-Precision Integer Arithmetic Instructions

Multiplies two values, extracts either the high or low part of the result, and adds a third
value. (see the official PTX ISA docs for the full description)

t = a * b;
d = t<63..32> + c;    // for .hi variant
d = t<31..0> + c;     // for .lo variant

@p  mad.lo.cc.u32 d,a,b,c;
    mad.lo.cc.u32 r,p,q,r;

Multiplies two values, extracts either the high or low part of the result, and adds a third
value. Writes the result to the destination register and the carry-out from the addition into the
condition code register.


Compute the product of two 24-bit integer values held in 32-bit source registers, and add a third,
32-bit value to either the high or low 32-bits of the 48-bit result. (see the official PTX ISA docs for the full description)

t = a * b;
d = t<47..16> + c;   // for .hi variant
d = t<31..0> + c;    // for .lo variant

mad24.lo.s32 d,a,b,c;   // low 32-bits of 24x24-bit signed multiply.

Compute the product of two 24-bit integer values held in 32-bit source registers, and add a third,
32-bit value to either the high or low 32-bits of the 48-bit result. Return either the high or low
32-bits of the 48-bit result.


Multiplies two values, extracts either the high or low part of the result, and adds a third value
along with carry-in. (see the official PTX ISA docs for the full description)

t = a * b;
d = t<63..32> + c + CC.CF;     // for .hi variant
d = t<31..0> + c + CC.CF;      // for .lo variant

// extended-precision multiply:  [r3,r2,r1,r0] = [r5,r4] * [r7,r6]
mul.lo.u32     r0,r4,r6;      // r0=(r4*r6).[31:0], no carry-out
mul.hi.u32     r1,r4,r6;      // r1=(r4*r6).[63:32], no carry-out
mad.lo.cc.u32  r1,r5,r6,r1;   // r1+=(r5*r6).[31:0], may carry-out
madc.hi.u32    r2,r5,r6,0;    // r2 =(r5*r6).[63:32]+carry-in,
                              // no carry-out
// (truncated - see the official PTX ISA docs for the full example)

Multiplies two values, extracts either the high or low part of the result, and adds a third value
along with carry-in. Writes the result to the destination register and optionally writes the
carry-out from the addition into the condition code register.


Get address in the CTA specified by operand b which corresponds to the address specified by
operand a.
Instruction type.type indicates the type of the destination operand d and the source
operand a.
W (see the official PTX ISA docs for the full description)

mapa.shared::cluster.u64 d1, %reg1, cta;
mapa.shared::cluster.u32 d2, sh, 3;
mapa.u64                 d3, %reg2, cta;

Get address in the CTA specified by operand b which corresponds to the address specified by
operand a.
Instruction type.type indicates the type of the destination operand d and the source
operand a.
When space is.shared::cluster, source a is either a shared memory variable or a register
containing a valid shared memory address and register d contains a shared memory address. When
the optional qualifier.space is not specified, both a and d are registers containing
generic addresses pointing to shared memory.
b is a 32-bit integer operand representing the rank of the target CTA.
Destination register d will hold an address in CTA b corresponding to operand a.


match.sync will cause executing thread to wait until all non-exited threads from membermask have executed match.sync with the same qualifiers and same membermask value before resuming
execution. (see the official PTX ISA docs for the full description)

match.all.sync.type  d[|p], a, membermask;

match.all returns the mask only if all non-exited threads in membermask share the same value of operand a; the optional predicate p is set accordingly.

match.any.sync.b32    d, a, 0xffffffff;
match.all.sync.b64    d|p, a, mask;

match.sync will cause executing thread to wait until all non-exited threads from membermask have executed match.sync with the same qualifiers and same membermask value before resuming
execution.
Operand membermask specifies a 32-bit integer which is a mask indicating threads participating
in this instruction where the bit position corresponds to thread’s laneid.
match.sync performs broadcast and compare of operand a across all non-exited threads in membermask and sets destination d and optional predicate p based on mode.
Operand a has instruction type and d has.b32 type.
Destination d is a 32-bit mask where bit position in mask corresponds to thread’s laneid. (see the official PTX ISA docs for the full description)


Summary: Select the larger of two operands.

Integer or floating-point maximum.

d = (a > b) ? a : b, with type-specific NaN-handling rules for floating-point forms.

max.u32  d,a,b;
max.s32  q,q,0;
max.relu.s16x2 t,t,u;
max.u8x4 p, q, r;

max.ftz.f32  f0,f1,f2;
max.f64      a,b,c;
// fp32 max with .NaN
max.NaN.f32  f0,f1,f2;
// fp32 max with .xorsign.abs
max.xorsign.abs.f32 Rd, Ra, Rb;

max.ftz.f16       h0,h1,h2;
max.f16x2         b0,b1,b2;
// SIMD fp16 max with NaN
max.NaN.f16x2     b0,b1,b2;
// scalar f16 max with xorsign.abs
max.xorsign.abs.f16 Rd, Ra, Rb;
// (truncated - see the official PTX ISA docs for the full example)

Store the maximum of a and b in d.
For.f16x2 and.bf16x2 instruction types, input vectors are formed with half-word values
from source operands. Half-word operands are then processed in parallel to store.f16x2 or.bf16x2 result in destination.
For.f16 instruction type, operands d and a have.f16 or.b16 type. For.f16x2 instruction type, operands d and a have.f16x2 or.b32 type. For.bf16 instruction type, operands d and a have.b16 type. (see the official PTX ISA docs for the full description)


mbarrier.arrive{.sem.scope}{.shared{::cta}}.b64           state, [addr]{, count};

A thread executing mbarrier.arrive performs an arrive-on operation
on the mbarrier object at the location specified by the address operand addr. (see the official PTX ISA docs for the full description)

.reg .b32 cnt, remoteAddr32, remoteCTAId, addr32;
.reg .b64 %r<5>, addr, remoteAddr64;
.shared .b64 shMem, shMem2;

cvta.shared.u64            addr, shMem2;
mov.b32                    addr32, shMem2;
// (truncated - see the official PTX ISA docs for the full example)

A thread executing mbarrier.arrive performs an arrive-on operation
on the mbarrier object at the location specified by the address operand addr. The 32-bit
unsigned integer operand count specifies the count argument to the arrive-on operation.
If no state space is specified then Generic Addressing is
used. If the address specified by addr does not fall within the address window of.shared::cta state space then the behavior is undefined.
Supported addressing modes for operand addr is as described in Addresses as Operands.
Alignment for operand addr is as described in the Size and alignment of mbarrier object.
The optional qualifier. (see the official PTX ISA docs for the full description)


mbarrier.arrive_drop{.sem.scope}{.shared{::cta}}.b64              state, [addr] {, count};

A thread executing mbarrier.arrive_drop on the mbarrier object at the location specified by the address operand addr performs the following steps: Decrements the expected arrival count of the mbarrier… (see the official PTX ISA docs for the full description)

.reg .b32 cnt;
.reg .b64 %r1;
.shared .b64 shMem;

// Example 1
@p mbarrier.arrive_drop.shared.b64 _, [shMem];
// (truncated - see the official PTX ISA docs for the full example)

A thread executing mbarrier.arrive_drop on the mbarrier object at the location specified by
the address operand addr performs the following steps:
Decrements the expected arrival count of the mbarrier object by the value specified by the
32-bit integer operand count. If count operand is not specified, it defaults to 1. Performs an arrive-on operation on the mbarrier object. The operand count specifies the count argument to the arrive-on operation.
The decrement done in the expected arrivals count of the mbarrier object will be for all the
subsequent phases of the mbarrier object.
If no state space is specified then Generic Addressing is
used. (see the official PTX ISA docs for the full description)


The layout of the opaque mbarrier object can be queried using mbarrier.check_layout.
The address operand addr specifies the memory location of the mbarrier object whose
layout is being inspected. (see the official PTX ISA docs for the full description)

.reg    .pred p;
.shared .b64  shMem;

mbarrier.check_layout.layout::v1.shared::cta.b64 p, [shMem];
@!p bra exit
// ... mbarrier operations on shMem
// (truncated - see the official PTX ISA docs for the full example)

The layout of the opaque mbarrier object can be queried using mbarrier.check_layout.
The address operand addr specifies the memory location of the mbarrier object whose
layout is being inspected. The instruction sets the predicate operand p to True if the
layout of the mbarrier object exactly matches the.layout qualifier. Refer Layouts of the mbarrier object for
more details.
If no state space is specified then Generic Addressing is used. If the address specified
by addr does not fall within the address window of.shared::cta state space then the
behavior is undefined.


A thread executing mbarrier.complete_tx performs a complete-tx operation on the mbarrier object at the location specified by the address operand addr. (see the official PTX ISA docs for the full description)

mbarrier.complete_tx.b64             [addr],     32;
mbarrier.complete_tx.shared.b64      [mbarObj1], 512;
mbarrier.complete_tx.relaxed.cta.b64 [addr2],    32;

A thread executing mbarrier.complete_tx performs a complete-tx operation on the mbarrier object at the location specified by the address operand addr. The
32-bit unsigned integer operand txCount specifies the completeCount argument to the complete-tx operation.
mbarrier.complete_tx does not involve any asynchronous memory operations and only simulates the
completion of an asynchronous memory operation and its side effect of signaling to the mbarrier
object.
If no state space is specified then Generic Addressing is
used. (see the official PTX ISA docs for the full description)


A thread executing mbarrier.expect_tx performs an expect-tx operation on the mbarrier object at the location specified by the address operand addr. (see the official PTX ISA docs for the full description)

mbarrier.expect_tx.b64                       [addr], 32;
mbarrier.expect_tx.relaxed.cta.shared.b64    [mbarObj1], 512;
mbarrier.expect_tx.relaxed.cta.shared.b64    [mbarObj2], 512;

A thread executing mbarrier.expect_tx performs an expect-tx operation on the mbarrier object at the location specified by the address operand addr. The
32-bit unsigned integer operand txCount specifies the expectCount argument to the expect-tx operation.
If no state space is specified then Generic Addressing is
used. If the address specified by addr does not fall within the address window of.shared::cta or.shared::cluster state space then the behavior is undefined.
Supported addressing modes for operand addr are as described in Addresses as Operands.
Alignment for operand addr is as described in the Size and alignment of mbarrier object.
The optional. (see the official PTX ISA docs for the full description)


mbarrier.init initializes the mbarrier object at the location specified by the address operand addr with the unsigned 32-bit integer count.
The. (see the official PTX ISA docs for the full description)

.shared .b64 shMem, shMem2, shMem3;
.reg    .b64 addr;
.reg    .b32 %r1;

cvta.shared.u64          addr, shMem2;
mbarrier.init.b64        [addr],   %r1;
// (truncated - see the official PTX ISA docs for the full example)

mbarrier.init initializes the mbarrier object at the location specified by the address operand addr with the unsigned 32-bit integer count.
The.layout qualifier specifies the layout that is used to initialize the mbarrier object.
If not specified explicitly, a.layout::v0 mbarrier is initialized.
Refer Layouts of the mbarrier object for more details.
The valid range of values for the operand count varies depending upon.layout as
specified below:
[1, …, 2 20 - 1] for mbarrier with.layout::v0 [1, …, 2 9 - 1] for mbarrier with.layout::v1
The constituents of the mbarrier object are initialized as follows:
The primary and conditional phases are initialized to zero. (see the official PTX ISA docs for the full description)


mbarrier.inval invalidates the mbarrier object at the location specified by the address
operand addr.
The invalidation is supported for all layouts described in Layouts of the mbarrier object. (see the official PTX ISA docs for the full description)

.shared .b64 shmem;
.reg    .b64 addr;
.reg    .b32 %r1;
.reg    .pred t0;

// Example 1 :
// (truncated - see the official PTX ISA docs for the full example)

mbarrier.inval invalidates the mbarrier object at the location specified by the address
operand addr.
The invalidation is supported for all layouts described in Layouts of the mbarrier object.
An mbarrier object must be invalidated before using its memory location for any other purpose.
Performing any mbarrier operation except mbarrier.init on a memory location that does not
contain a valid mbarrier object, results in undefined behaviour.
If no state space is specified then Generic Addressing is
used. (see the official PTX ISA docs for the full description)


The pending count can be queried from the opaque mbarrier state using mbarrier.pending_count.
The state operand is a 64-bit register that must be the result of a prior mbarrier.arrive. (see the official PTX ISA docs for the full description)

.reg .b32 %r1;
.reg .b64 state;
.shared .b64 shMem;

mbarrier.arrive.noComplete.b64 state, [shMem], 1;
mbarrier.pending_count.layout::v0.b64 %r1, state;

The pending count can be queried from the opaque mbarrier state using mbarrier.pending_count.
The state operand is a 64-bit register that must be the result of a prior mbarrier.arrive.noComplete or mbarrier.arrive_drop.noComplete instruction. Otherwise, the
behavior is undefined.
The destination register count is a 32-bit unsigned integer representing the pending count of
the mbarrier object prior to the arrive-on operation from
which the state register was obtained.
The optional qualifier.layout::v0 denotes the layout of the corresponding mbarrier object as
described in the section Layouts of the mbarrier object.


// without parity
mbarrier.test_wait{.phase_type::primary}{.sem.scope}{.ss}.b64      waitComplete, [addr], state;

The test_wait and try_wait operations test for the completion of the current or the immediately
preceding phase of an mbarrier object at the location specified by the operand addr.
mbarrier. (see the official PTX ISA docs for the full description)

// Example 1a, thread synchronization with test_wait:

.reg .b64 %r1;
.shared .b64 shMem;

mbarrier.init.shared.b64 [shMem], N;  // N threads participating in the mbarrier.
// (truncated - see the official PTX ISA docs for the full example)

The test_wait and try_wait operations test for the completion of the current or the immediately
preceding phase of an mbarrier object at the location specified by the operand addr.
mbarrier.test_wait is a non-blocking instruction which tests for the completion of the phase.
mbarrier.try_wait is a potentially blocking instruction which tests for the completion of the
phase. If the phase is not complete, the executing thread may be suspended. Suspended thread resumes
execution when the specified phase completes OR before the phase completes following a
system-dependent time limit. (see the official PTX ISA docs for the full description)


// without parity
mbarrier.try_wait{.phase_type::primary}{.sem.scope}{.ss}.b64      waitComplete, [addr], state {, timeHint};


Summary: Order this thread's prior memory accesses relative to later ones, visible to a given scope.

level selects the visibility scope: CTA, whole GPU, or system (including other GPUs/host).

All memory operations issued by this thread before the fence become visible, in order, to other threads within the given scope before any operation issued after the fence.

membar.gl;
membar.cta;
membar.sys;
fence.sc.cta;
fence.sc.cluster;
fence.proxy.alias;
// (truncated - see the official PTX ISA docs for the full example)

The membar instruction guarantees that prior memory accesses requested by this thread ( ld, st, atom and red instructions) are performed at the specified level, before later
memory operations requested by this thread following the membar instruction. The level qualifier specifies the set of threads that may observe the ordering effect of this operation.
A memory read (e.g., by ld or atom ) has been performed when the value read has been
transmitted from memory and cannot be modified by another thread at the indicated level. (see the official PTX ISA docs for the full description)


Summary: Select the smaller of two operands.

Integer or floating-point minimum.

d = (a < b) ? a : b, with type-specific NaN-handling rules for floating-point forms.

min.s32  r0,a,b;
@p  min.u16  h,i,j;
    min.s16x2.relu u,v,w;
    min.u8x4 p, q, r;

@p  min.ftz.f32  z,z,x;
    min.f64      a,b,c;
    // fp32 min with .NaN
    min.NaN.f32  f0,f1,f2;
    // fp32 min with .xorsign.abs
    min.xorsign.abs.f32 Rd, Ra, Rb;

min.ftz.f16       h0,h1,h2;
min.f16x2         b0,b1,b2;
// SIMD fp16 min with .NaN
min.NaN.f16x2     b0,b1,b2;
min.bf16          h0, h1, h2;
// SIMD bf16 min with NaN
// (truncated - see the official PTX ISA docs for the full example)

Store the minimum of a and b in d.
For.f16x2 and.bf16x2 instruction types, input vectors are formed with half-word values
from source operands. Half-word operands are then processed in parallel to store.f16x2 or.bf16x2 result in destination.
For.f16 instruction type, operands d and a have.f16 or.b16 type. For.f16x2 instruction type, operands d and a have.f16x2 or.b32 type. For.bf16 instruction type, operands d and a have.b16 type. (see the official PTX ISA docs for the full description)


Matrix Multiply-Accumulate (Tensor Core)

Summary: Cooperative, warp-wide matrix-multiply-accumulate executed on tensor-core hardware.

mma.sync.aligned.shape.row.col.dtype.atype.btype.ctype d, a, b, c;

Synchronizing warp-wide MMA for a fixed tile shape (e.g. m16n8k16); operand fragments are distributed across the warp's lanes per a hardware-defined layout.

D = A * B + C for the fixed tile shape, computed cooperatively across all 32 lanes of the warp.

Perform a MxNxK matrix multiply and accumulate operation, D = A*B+C, where the A matrix is MxK, the B matrix is KxN, and the C and D matrices are MxN.
Qualifier.block_scale specifies that the matrices A and B are scaled with scale_A and scale_B matrices respectively before performing the matrix multiply and accumulate operation
as specified in the section Block Scaling for mma.sync. The data type
corresponding to each of the element within scale_A and Scale_B matrices is specified
by.stype. Qualifier.scale_vec_size specifies the number of columns of scale_A matrix
and number of rows in the matrix scale_B.
The valid combinations of.kind,.stype and.scale_vec_size are described in Table 39. (see the official PTX ISA docs for the full description)


Summary: Copy a value into a register, or materialize an address/immediate.

Register-to-register move, or load of an immediate/address.

a

Source (register, immediate, or address expression)

mov.f32  d,a;
mov.u16  u,v;
mov.f32  k,0.1;
mov.u32  ptr, A;        // move address of A into ptr
mov.u32  ptr, A[5];     // move address of A[5] into ptr
mov.u32  ptr, A+20;     // move address with offset into ptr
// (truncated - see the official PTX ISA docs for the full example)

mov.b32 %r1,{a,b};      // a,b have type .u16
mov.b64 {lo,hi}, %x;    // %x is a double; lo,hi are .u32
mov.b32 %r1,{x,y,z,w};  // x,y,z,w have type .b8
mov.b32 {r,g,b,a},%r1;  // r,g,b,a have type .u8
mov.b64 {%r1, _}, %x;   // %x is.b64, %r1 is .b32
mov.b128 {%b1, %b2}, %y;   // %y is.b128, %b1 and % b2 are .b64
// (truncated - see the official PTX ISA docs for the full example)

Write register d with the value of a.
Operand a may be a register, special register, variable with optional offset in an addressable
memory space, or function name.
For variables declared in.const,.global,.local, and.shared state spaces, mov places the non-generic address of the variable (i.e., the address of the variable in its state
space) into the destination register. (see the official PTX ISA docs for the full description)


Move a row-major matrix across all threads in a warp, reading elements from source a, and
writing the transposed elements to destination d.
The. (see the official PTX ISA docs for the full description)

.reg .b32 d, a;
movmatrix.sync.aligned.m8n8.trans.b16 d, a;

Move a row-major matrix across all threads in a warp, reading elements from source a, and
writing the transposed elements to destination d.
The.shape qualifier indicates the dimensions of the matrix being transposed. Each matrix
element holds 16-bit data as indicated by the.type qualifier.
The mandatory.sync qualifier indicates that movmatrix causes the executing thread to wait
until all threads in the warp execute the same movmatrix instruction before resuming execution.
The mandatory.aligned qualifier indicates that all threads in the warp must execute the same movmatrix instruction. (see the official PTX ISA docs for the full description)


Summary: Multiply two operands, selecting the low, high, or widened part of an integer product.

Integer multiply; mode selects which part of the full product is written to d.

Single-precision floating-point multiply.

Double-precision floating-point multiply with explicit round-to-nearest-even.

d = a * b, truncated to the selected result slice for integer forms.

mul.wide.s16 fa,fxs,fys;   // 16*16 bits yields 32 bits
mul.lo.s16 fa,fxs,fys;     // 16*16 bits, save only the low 16 bits
mul.wide.s32 z,x,y;        // 32*32 bits, creates 64 bit result

mul.ftz.f32 circumf,radius,pi  // a single-precision multiply

// scalar f16 multiplications
mul.f16        d0, a0, b0;
mul.rn.f16     d1, a1, b1;
mul.bf16       bd0, ba0, bb0;
mul.rn.bf16    bd1, ba1, bb1;
// (truncated - see the official PTX ISA docs for the full example)

Performs multiplication and writes the resulting value into a destination register.
For.f16x2 and.bf16x2 instruction type, forms input vectors by half word values from source
operands. Half-word operands are then multiplied in parallel to produce.f16x2 or.bf16x2 result in destination.
For.f16 instruction type, operands d, a and b have.f16 or.b16 type. For.f16x2 instruction type, operands d, a and b have.b32 type. For.bf16 instruction type, operands d, a, b have.b16 type. For.bf16x2 instruction type,
operands d, a, b have.b32 type.


Summary:
Compute the product of two 24-bit integer values held in 32-bit source registers, and return either
the high or low 32-bits of the 48-bit result.

t = a * b;
d = t<47..16>;    // for .hi variant
d = t<31..0>;     // for .lo variant

mul24.lo.s32 d,a,b;   // low 32-bits of 24x24-bit signed multiply.


Instruction multimem.cp.async.bulk initiates an asynchronous bulk-copy operation from source address range [srcMem, srcMem + size) to memory locations residing on each GPU’s memory referred to by the… (see the official PTX ISA docs for the full description)

multimem.cp.async.bulk.global.shared::cta.bulk_group [dstMem], [srcMem], size;

multimem.cp.async.bulk.global.shared::cta.bulk_group [dstMem], [srcMem], 512;

multimem.cp.async.bulk.global.shared::cta.bulk_group.cp_mask [dstMem], [srcMem], size, byteMask;
// (truncated - see the official PTX ISA docs for the full example)

Instruction multimem.cp.async.bulk initiates an asynchronous bulk-copy operation from source
address range [srcMem, srcMem + size) to memory locations residing on each GPU’s memory referred
to by the destination multimem address range [dstMem, dstMem + size). The direction of
bulk-copy is from the state space specified by the.src modifier to the state space specified
by the.dst modifiers.
The 32-bit operand size specifies the amount of memory to be copied, in terms of number of
bytes. Operand size must be a multiple of 16. The memory range [dstMem, dstMem + size) must not overflow the destination multimem memory space. (see the official PTX ISA docs for the full description)


multimem.cp.reduce.async.bulk{.sem.scope}.dst.src.completion_mechanism.redOp.type  [dstMem], [srcMem], size;

Instruction multimem.cp.reduce.async.bulk initiates an element-wise asynchronous reduction operation with elements from source memory address range [srcMem, srcMem + size) to memory locations residing… (see the official PTX ISA docs for the full description)

multimem.cp.reduce.async.bulk.global.shared::cta.bulk_group.add.u32 [dstMem], [srcMem], size;

multimem.cp.reduce.async.bulk.global.shared::cta.bulk_group.xor.b64 [dstMem], [srcMem], size;

multimem.cp.reduce.async.bulk.global.shared::cta.bulk_group.inc.u32 [dstMem], [srcMem], size;
// (truncated - see the official PTX ISA docs for the full example)

Instruction multimem.cp.reduce.async.bulk initiates an element-wise asynchronous reduction
operation with elements from source memory address range [srcMem, srcMem + size) to memory
locations residing on each GPU’s memory referred to by the multimem destination address range [dstMem, dstMem + size).
Each data element in the destination array is reduced inline with the corresponding data element in
the source array with the reduction operation specified by the modifier.redOp. (see the official PTX ISA docs for the full description)


Summary:
The multimem.* operations operate on multimem addresses and accesses all of the multiple memory
locations which the multimem address points to.
Multimem addresses can be accessed only by multimem.* operations. Accessing a multimem address
with ld, st or any other memory operations results in undefined behavior.
Refer to CUDA programming guide for creation and management of the multimem addresses.

// Integer type:
multimem.ld_reduce{.ldsem}{.scope}{.ss}.op.type      d, [a];

Instruction multimem.ld_reduce performs the following operations: load operation on the multimem address a, which involves loading of data from all of the multiple memory locations pointed to by the m… (see the official PTX ISA docs for the full description)

multimem.ld_reduce.and.b32                    val1_b32, [addr1];
multimem.ld_reduce.acquire.gpu.global.add.u32 val2_u32, [addr2];

multimem.st.relaxed.gpu.b32                [addr3], val3_b32;
multimem.st.release.cta.global.u32         [addr4], val4_u32;
// (truncated - see the official PTX ISA docs for the full example)

Instruction multimem.ld_reduce performs the following operations:
load operation on the multimem address a, which involves loading of data from all of the
multiple memory locations pointed to by the multimem address a, reduction operation specified by.op on the multiple data loaded from the multimem address a.
The result of the reduction operation in returned in register d.
Instruction multimem.st performs a store operation of the input operand b to all the memory
locations pointed to by the multimem address a.
Instruction multimem.red performs a reduction operation on all the memory locations pointed to
by the multimem address a, with operand b.
Instruction multimem. (see the official PTX ISA docs for the full description)


// Integer type:
multimem.red{.redsem}{.scope}{.ss}.op.type           [a], b;


multimem.red.async is a non-blocking instruction which initiates an asynchronous
reduction operation specified by. (see the official PTX ISA docs for the full description)

// Asynchronous add reduction, GPU scope, explicit .global, 32-bit unsigned.
multimem.red.async.release.gpu.global.add.u32 [mm_addr], src_u32;

// System scope, generic addressing.
multimem.red.async.release.sys.add.s32 [mm_addr], src_s32;
// (truncated - see the official PTX ISA docs for the full example)

multimem.red.async is a non-blocking instruction which initiates an asynchronous
reduction operation specified by.op, with operand b and the value at memory
locations residing on each GPU’s memory referred to by the destination multimem address
operand a.
Address operand a must be a multimem address. Otherwise, the behavior is undefined.


// Integer type:
multimem.st{.stsem}{.scope}{.ss}.type                [a], b;


multimem.st.async is a non-blocking instruction which initiates an asynchronous store operation that stores the value specified by source operand b to the memory locations residing on each GPU’s memor… (see the official PTX ISA docs for the full description)

// Release store to multimem address, GPU scope, explicit .global state space.
multimem.st.async.release.gpu.global.u32 [mm_addr], src_u32;

// Release store, system scope, generic addressing for multimem operand.
multimem.st.async.release.sys.f64 [mm_addr], src_f64;

multimem.st.async is a non-blocking instruction which initiates an asynchronous store
operation that stores the value specified by source operand b to the memory locations
residing on each GPU’s memory referred to by the destination multimem address operand a.
Address operand a must be a multimem address. Otherwise, the behavior is undefined.


Suspends the thread for a sleep duration approximately close to the delay t, specified in
nanoseconds. (see the official PTX ISA docs for the full description)

.reg .b32 r;
.reg .pred p;

nanosleep.u32 r;
nanosleep.u32 42;
@p nanosleep.u32 r;

Suspends the thread for a sleep duration approximately close to the delay t, specified in
nanoseconds. t may be a register or an immediate value.
The sleep duration is approximated, but guaranteed to be in the interval [0, 2*t]. The maximum
sleep duration is 1 millisecond. The implementation may reduce the sleep duration for individual
threads within a warp such that all sleeping threads in the warp wake up together.


Summary: Negate a signed or floating-point operand.

Arithmetic negation.

neg.s32  r0,a;
neg.s8x4 p, q, r;

neg.ftz.f32  x,f0;

neg.ftz.f16  x,f0;
neg.bf16     x,b0;
neg.bf16x2   x1,b1;

Negate the sign of a and store the result in d.
For.f16x2 and.bf16x2 instruction type, forms input vector by extracting half word values
from the source operand. Half-word operands are then negated in parallel to produce.f16x2 or.bf16x2 result in destination.
For.f16 instruction type, operands d and a have.f16 or.b16 type. For.f16x2 instruction type, operands d and a have.b32 type. For.bf16 instruction
type, operands d and a have.b16 type. For.bf16x2 instruction type, operands d and a have.b32 type.


Summary: Bitwise complement of an operand.

Bitwise complement, including a predicate form.

Invert the bits in a.


Summary: Bitwise OR of two operands.

Bitwise OR, including a predicate form.

or.b32  mask mask,0x00010001
or.pred  p,q,r;

Compute the bit-wise or operation for the bits in a and b.


pmevent       a;    // trigger a single performance monitor event

Triggers one or more of a fixed number of performance monitor events, with event index or mask
specified by immediate operand a.
pmevent (without modifier. (see the official PTX ISA docs for the full description)

pmevent      1;
@p  pmevent      7;
@q  pmevent.mask 0xff;

Triggers one or more of a fixed number of performance monitor events, with event index or mask
specified by immediate operand a.
pmevent (without modifier.mask ) triggers a single performance monitor event indexed by
immediate operand a, in the range 0..15.
pmevent.mask triggers one or more of the performance monitor events. Each bit in the 16-bit
immediate operand a controls an event.
Programmatic performance moniter events may be combined with other hardware events using Boolean
functions to increment one of the four performance counters. The relationship between events and
counters is programmed via API calls from the host.


Summary: Count the number of set bits in an integer operand.

Population count.

popc.b32  d, a;
popc.b64  cnt, X;  // cnt is .u32

Count the number of one bits in a and place the resulting population count in 32-bit
destination register d. Operand a has the instruction type and destination d has type.u32.


prefetch{.space}.level                    [a];   // prefetch to data cache

The prefetch instruction brings the cache line containing the specified address in global or
local memory state space into the specified cache level.
If the. (see the official PTX ISA docs for the full description)

prefetch.global.L1             [ptr];
prefetch.global.L2::evict_last [ptr];
prefetchu.L1  [addr];
prefetch.const.tensormap       [ptr];

The prefetch instruction brings the cache line containing the specified address in global or
local memory state space into the specified cache level.
If the.tensormap qualifier is specified then the prefetch instruction brings the cache line
containing the specified address in the.const or.param memory state space for subsequent
use by the cp.async.bulk.tensor instruction.
If no state space is given, the prefetch uses Generic Addressing.
Optionally, the eviction priority to be applied on the prefetched cache line can be specified by the
modifier.level::eviction_priority. (see the official PTX ISA docs for the full description)


Summary: The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. A prefetch to a shared memory location performs no operation.

prefetchu.L1  [a];   // prefetch to uniform cache


Pick four arbitrary bytes from two 32-bit registers, and reassemble them into a 32-bit destination
register. (see the official PTX ISA docs for the full description)

Pick four arbitrary bytes from two 32-bit registers, and reassemble them into a 32-bit destination
register.
In the generic form (no mode specified), the permute control consists of four 4-bit selection
values. The bytes in the two source registers are numbered from 0 to 7: {b, a} = {{b7, b6, b5, b4}, {b3, b2, b1, b0}}. For each byte in the target register, a 4-bit selection value is defined.
The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the
target position. (see the official PTX ISA docs for the full description)


Summary: Compute 1/a, store result in d.

rcp.approx{.ftz}.f32  d, a;  // fast, approximate reciprocal

Compute 1/a, store result in d.

rcp.approx.ftz.f32  ri,r;
rcp.rn.ftz.f32      xi,x;
rcp.rn.f64          xi,x;

Compute 1/a, store result in d.


Summary: Compute a fast, gross approximation to the reciprocal as follows: extract the most-significant 32 bits of.f64 operand a in 1.11.20 IEEE floating-point format (i.e., ignore the least-significant 32…

Compute a fast, gross approximation to the reciprocal as follows:
extract the most-significant 32 bits of.f64 operand a in 1.11.20 IEEE floating-point
format (i.e. (see the official PTX ISA docs for the full description)

Compute a fast, gross approximation to the reciprocal as follows:
extract the most-significant 32 bits of.f64 operand a in 1.11.20 IEEE floating-point
format (i.e., ignore the least-significant 32 bits of a ), compute an approximate.f64 reciprocal of this value using the most-significant 20 bits of
the mantissa of operand a, place the resulting 32-bits in 1.11.20 IEEE floating-point format in the most-significant 32-bits
of destination d,and zero the least significant 32 mantissa bits of.f64 destination d.


Summary: Atomically read-modify-write a memory location without returning the prior value.

Same read-modify-write as atom, but discards the prior value - cheaper when the old value isn't needed.

red.global.add.s32  [a],1;
red.shared::cluster.max.u32  [x+4],0;
@p  red.global.and.b32  [p],my_val;
red.global.sys.add.u32 [a], 1;
red.global.acquire.sys.add.u32 [gbl], 1;
red.add.noftz.f16x2 [a], b;
// (truncated - see the official PTX ISA docs for the full example)

Performs a reduction operation with operand b and the value in location a, and stores the
result of the specified operation at location a, overwriting the original value. Operand a specifies a location in the specified state space. If no state space is given, perform the memory
accesses using Generic Addressing. red with scalar type may
be used only with.global and.shared spaces and with generic addressing, where the address
points to.global or.shared space. (see the official PTX ISA docs for the full description)


// Increment and Decrement reductions
red.async.sem.scope{.ss}.completion_mechanism.op.type [a], b, [mbar];

red.async is a non-blocking instruction which initiates an asynchronous reduction operation
specified by. (see the official PTX ISA docs for the full description)

red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.min.u32 [addr], b, [mbar_addr];

red.async.release.sys.global.add.u32 [addr], b;

red.async is a non-blocking instruction which initiates an asynchronous reduction operation
specified by.op, with the operand b and the value at destination shared memory location
specified by operand a.
red.async is performed in the generic proxy.


redux.sync.op.type dst, src, membermask;

redux.sync will cause the executing thread to wait until all non-exited threads corresponding to membermask have executed redux. (see the official PTX ISA docs for the full description)

.reg .b32 dst, src, init, mask;
redux.sync.add.s32 dst, src, 0xff;
redux.sync.xor.b32 dst, src, mask;

redux.sync.min.abs.NaN.f32 dst, src, mask;

redux.sync will cause the executing thread to wait until all non-exited threads corresponding to membermask have executed redux.sync with the same qualifiers and same membermask value
before resuming execution.
Operand membermask specifies a 32-bit integer which is a mask indicating threads participating
in this instruction where the bit position corresponds to thread’s laneid.
redux.sync performs a reduction operation.op of the 32 bit source register src across
all non-exited threads in the membermask. (see the official PTX ISA docs for the full description)


Summary: Compute the integer remainder of division.

Integer remainder.

Divides a by b, store the remainder in d.


Return execution to caller’s environment. A divergent return suspends threads until all threads are
ready to return to the caller. (see the official PTX ISA docs for the full description)

Return execution to caller’s environment. A divergent return suspends threads until all threads are
ready to return to the caller. This allows multiple divergent ret instructions.
A ret is assumed to be divergent unless the.uni suffix is present, indicating that the
return is guaranteed to be non-divergent.
Any values returned from a function should be moved into the return parameter variables prior to
executing the ret instruction.
A return instruction executed in a top-level entry routine will terminate thread execution.


Summary: Fast hardware approximation of 1/sqrt(x).

Reduced-precision reciprocal square root.

d ≈ 1 / sqrt(a), with a hardware-specific ULP error bound rather than a fully IEEE-rounded result.

rsqrt.approx.ftz.f32  isr, x;
rsqrt.approx.f64      ISR, X;

Compute 1/sqrt(a) and store the result in d.


Compute a double-precision (.f64 ) approximation of the square root reciprocal of a value. The
least significant 32 bits of the double-precision (.f64 ) destination d are all zeros.


Summary: Adds the absolute value of a-b to c and writes the resulting value into d.

sad.s32  d,a,b,c;
sad.u32  d,a,b,d;  // running sum


Summary: Select between two operands based on a predicate, without branching.

Branchless select.

selp.s32  r0,r,g,p;
@q  selp.f32  f0,t,x,xp;

Conditional selection. If c is True, a is stored in d, b otherwise. Operands d, a, and b must be of the same type. Operand c is a predicate.


Summary: Compare two operands and write a numeric (not predicate) 0/1 or all-ones/all-zeros result.

Comparison producing a value, useful when the result feeds arithmetic rather than a guarded branch.

d = CmpOp(a, b) ? (all-ones or 1) : 0, encoding depends on dtype.

@p  set.lt.and.f32.s32  d,a,b,r;
    set.eq.u32.u32      d,i,n;

set.lt.and.f16.f16  d,a,b,r;
set.eq.f16x2.f16x2  d,i,n;
set.eq.u32.f16x2    d,i,n;
set.lt.and.u16.f16  d,a,b,r;
set.ltu.or.bf16.f16    d,u,v,s;
set.equ.bf16x2.bf16x2  d,j,m;
// (truncated - see the official PTX ISA docs for the full example)

Compares two numeric values and optionally combines the result with another predicate value by
applying a Boolean operator.
Result of this computation is written in destination register in the following way:
If result is True, 0xffffffff is written for destination types.u32 /.s32. 0xffff is written for destination types.u16 /.s16. 1.0 in target precision floating point format is written for destination type.f16,.bf16. If result is False, 0x0 is written for all integer destination types. (see the official PTX ISA docs for the full description)


setmaxnreg provides a hint to the system to update the maximum number of per-thread registers
owned by the executing warp to the value specified by the imm-reg-count operand.
Qualifier. (see the official PTX ISA docs for the full description)

setmaxnreg.dec.sync.aligned.u32 64;
setmaxnreg.inc.sync.aligned.u32 192;

setmaxnreg provides a hint to the system to update the maximum number of per-thread registers
owned by the executing warp to the value specified by the imm-reg-count operand.
Qualifier.dec is used to release extra registers such that the absolute per-thread maximum
register count is reduced from its current value to imm-reg-count. Qualifier.inc is used to
request additional registers such that the absolute per-thread maximum register count is increased
from its current value to imm-reg-count.
A pool of available registers is maintained per-CTA. (see the official PTX ISA docs for the full description)


Summary: Compare two operands and write the boolean result to a predicate register.

Comparison writing a predicate register, consumed by @p-guarded instructions.

setp.lt.and.s32  p|q,a,b,r;
@q  setp.eq.u32      p,i,n;

setp.lt.and.f16x2  p|q,a,b,r;
@q  setp.eq.f16    p,i,n;

setp.gt.or.bf16x2  u|v,c,d,s;
@q  setp.eq.bf16   u,j,m;

Compares two values and combines the result with another predicate value by applying a Boolean
operator. This result is written to the first destination operand. A related value computed using
the complement of the compare result is written to the second destination operand.
Applies to all numeric types. Operands a and b have type.type; operands p, q,
and c have type.pred. The sink symbol ‘_’ may be used in place of any one of the
destination operands.


shf.l.mode.b32  d, a, b, c;  // left shift

Shift the 64-bit value formed by concatenating operands a and b left or right by the amount
specified by the unsigned 32-bit value in c. (see the official PTX ISA docs for the full description)

u32  n = (.mode == .clamp) ? min(c, 32) : c & 0x1f;
switch (shf.dir) {  // shift concatenation of [b, a]
    case shf.l:     // extract 32 msbs
           u32  d = (b << n)      | (a >> (32-n));
    case shf.r:     // extract 32 lsbs
           u32  d = (b << (32-n)) | (a >> n);
}

Shift the 64-bit value formed by concatenating operands a and b left or right by the amount
specified by the unsigned 32-bit value in c. Operand b holds bits 63:32 and operand a
holds bits 31:0 of the 64-bit source value. The source is shifted left or right by the clamped
or wrapped value in c. For shf.l, the most-significant 32-bits of the result are written
into d; for shf.r, the least-significant 32-bits of the result are written into d.


Summary: Exchange a value directly between lanes of the same warp.

Legacy (unsynchronized) warp shuffle; deprecated since PTX ISA 6.0 in favor of shfl.sync.

shfl.sync.mode.b32 d[|p], a, b, c, membermask;

Warp shuffle that also synchronizes the specified member lanes before exchanging data.

membermask

Mask of participating lanes (sync form only)

d = value of operand a as seen by another lane in the warp, selected by mode/b; optional predicate p reports whether the source lane was valid.

shfl.sync.up.b32  Ry|p, Rx, 0x1,  0x0, 0xffffffff;

Exchange register data between threads of a warp.
shfl.sync will cause executing thread to wait until all non-exited threads corresponding to membermask have executed shfl.sync with the same qualifiers and same membermask value
before resuming execution.
Operand membermask specifies a 32-bit integer which is a mask indicating threads participating
in barrier where the bit position corresponds to thread’s laneid.
shfl.sync exchanges register data between threads in membermask.
Each thread in the currently executing warp will compute a source lane index j based on input
operands b and c and the mode. (see the official PTX ISA docs for the full description)


Summary: Shift bits left, filling with zero.

Logical left shift by an unsigned shift amount b.

Shift a left by the amount specified by unsigned 32-bit value in b.


Summary: Shift bits right, arithmetic or logical depending on the operand's signedness.

Right shift: arithmetic (sign-extending) for signed types, logical for unsigned types.

Shift a right by the amount specified by unsigned 32-bit value in b. Signed shifts fill with
the sign bit, unsigned and untyped shifts fill with 0.


Summary: Fast hardware approximation of sin(x).

Reduced-precision sine, valid over a hardware-defined input range.

Find the sine of the angle a (in radians).


Summary: Conditional selection.

Conditional selection. If c >= 0, a is stored in d, otherwise b is stored in d. (see the official PTX ISA docs for the full description)

slct.u32.s32  x, y, z, val;
slct.ftz.u64.f32  A, B, C, fval;

Conditional selection. If c >= 0, a is stored in d, otherwise b is stored in d. Operands d, a, and b are treated as a bitsize type of the same width as the first
instruction type; operand c must match the second instruction type (.s32 or.f32 ). The
selected input is copied to the output without modification.


Summary: Compute sqrt( a ) and store the result in d.

sqrt.approx{.ftz}.f32  d, a; // fast, approximate square root

sqrt.approx.ftz.f32  r,x;
sqrt.rn.ftz.f32      r,x;
sqrt.rn.f64          r,x;


Summary: Store a register value into the specified state space.

Store to an explicit state space.

st.global.f32    [a],b;
st.local.b32     [q+4],a;
st.global.v4.s32 [p],Q;
st.local.b32     [q+-8],a; // negative offset
st.local.s32     [100],r7; // immediate address
// (truncated - see the official PTX ISA docs for the full example)

Store the value of operand b in the location specified by the destination address
operand a in specified state space. If no state space is given, perform the store using Generic Addressing. Stores to const memory are illegal.
If no sub-qualifier is specified with.shared state space, then::cta is assumed by default.
Supported addressing modes for operand a and alignment requirements are described in Addresses as Operands.
If.param is specified without any sub-qualifiers then it defaults to.param::func.
Instruction st.param{::func} used for passing arguments to device function cannot be predicated. (see the official PTX ISA docs for the full description)


st.async{.weak}{.ss}.completion_mechanism{.vec}.type [a], b, [mbar];

st.async is a non-blocking instruction which initiates an asynchronous store operation that
stores the value specified by source operand b to the destination memory location
specified by operand a. (see the official PTX ISA docs for the full description)

st.async.shared::cluster.mbarrier::complete_tx::bytes.u32 [addr], b, [mbar_addr];

st.async.sys.release.global.u32 [addr], b;

st.async.mbarrier::complete_tx::bytes.b128 [addr], b, [mbar_addr];
// (truncated - see the official PTX ISA docs for the full example)

st.async is a non-blocking instruction which initiates an asynchronous store operation that
stores the value specified by source operand b to the destination memory location
specified by operand a.
st.async is performed in the generic proxy.


st.bulk{.weak}{.shared::cta}  [a], size, initval; // initval must be zero

st.bulk instruction initializes a region of shared memory starting from the location specified
by destination address operand a. (see the official PTX ISA docs for the full description)

st.bulk.weak.shared::cta  [dst], n, 0;

st.bulk                   [gdst], 4096, 0;

st.bulk instruction initializes a region of shared memory starting from the location specified
by destination address operand a.
The 32-bit or 64-bit integer operand size specifies the amount of memory to be initialized in terms of
number of bytes. size must be a multiple of 8. If the value is not a multiple of 8, then the
behavior is undefined. The maximum value of size operand can be 16777216.
The integer immediate operand initval specifies the initialization value for the memory
locations. The only numeric value allowed for operand initval is 0.
If no state space is specified then Generic Addressing is used. (see the official PTX ISA docs for the full description)


Sets the current stack pointer to source register a. (see the official PTX ISA docs for the full description)

.reg .u32 ra;
stacksave.u32 ra;
// Code that may modify stack pointer
...
stackrestore.u32 ra;

Sets the current stack pointer to source register a.
When stackrestore is used with operand a written by a prior stacksave instruction, it
will effectively restore the state of stack as it was before stacksave was executed. Note that
if stackrestore is used with an arbitrary value of a, it may cause corruption of stack
pointer. This implies that the correct use of this feature requires that stackrestore.type a is
used after stacksave.type a without redefining the value of a between them.
Operand a has the same type as the instruction type.


Copies the current value of stack pointer into the destination register d. Pointer returned by stacksave can be used in a subsequent stackrestore instruction to restore the stack
pointer. (see the official PTX ISA docs for the full description)

.reg .u32 rd;
stacksave.u32 rd;

.reg .u64 rd1;
stacksave.u64 rd1;

Copies the current value of stack pointer into the destination register d. Pointer returned by stacksave can be used in a subsequent stackrestore instruction to restore the stack
pointer. If d is modified prior to use in stackrestore instruction, it may corrupt data in
the stack.
Destination operand d has the same type as the instruction type.


Collectively store one or more matrices across all threads in a warp to the location indicated by
the address operand p, in.shared state space. (see the official PTX ISA docs for the full description)

// Store a single 8x8 matrix using 64-bit addressing
.reg .b64 addr;
.reg .b32 r;
stmatrix.sync.aligned.m8n8.x1.shared.b16 [addr], {r};

// Store two 8x8 matrices in column-major format
// (truncated - see the official PTX ISA docs for the full example)

Collectively store one or more matrices across all threads in a warp to the location indicated by
the address operand p, in.shared state space. If no state space is provided, generic
addressing is used, such that the address in p points into.shared space. If the generic
address doesn’t fall in.shared state space, then the behavior is undefined.
The.shape qualifier indicates the dimensions of the matrices being loaded. (see the official PTX ISA docs for the full description)


Summary: Subtract the second operand from the first, with optional saturation for signed 32-bit integers.

Generic subtract across integer and floating-point types.

Signed 32-bit subtract with saturation.

sub.s32 c,a,b;
sub.u8x4 p, q, r;

sub.f32 c,a,b;
sub.rn.ftz.f32  f1,f2,f3;

// scalar f16 subtractions
sub.f16        d0, a0, b0;
sub.rn.f16     d1, a1, b1;
sub.bf16       bd0, ba0, bb0;
sub.rn.bf16    bd1, ba1, bb1;
// (truncated - see the official PTX ISA docs for the full example)

.reg .f32 fc, fd;
.reg .f16 ha;
sub.rz.f32.f16.sat   fd, ha, fc;

Performs subtraction and writes the resulting value into a destination register.
For.f16x2 and.bf16x2 instruction type, forms input vectors by half word values from source
operands. Half-word operands are then subtracted in parallel to produce.f16x2 or.bf16x2 result in destination.
For.f16 instruction type, operands d, a and b have.f16 or.b16 type. For.f16x2 instruction type, operands d, a and b have.b32 type. For.bf16 instruction type, operands d, a, b have.b16 type. For.bf16x2 instruction type,
operands d, a, b have.b32 type.


Summary: Performs integer subtraction and writes the borrow-out value into the condition code register.

@p  sub.cc.u32   x1,y1,z1;   // extended-precision subtraction
@p  subc.cc.u32  x2,y2,z2;   // of two 128-bit values
@p  subc.cc.u32  x3,y3,z3;
@p  subc.u32     x4,y4,z4;


Summary:
Performs integer subtraction with borrow-in and optionally writes the borrow-out value into the
condition code register.


suld.b.geom{.cop}.vec.dtype.clamp  d, [a, b];  // unformatted

suld.b.{1d,2d,3d}
Load from surface memory using a surface coordinate vector. The instruction loads data from the
surface named by operand a at coordinates given by operand b into destination d. (see the official PTX ISA docs for the full description)

suld.b.1d.v4.b32.trap  {s1,s2,s3,s4}, [surf_B, {x}];
suld.b.3d.v2.b64.trap  {r1,r2}, [surf_A, {x,y,z,w}];
suld.b.a1d.v2.b32      {r0,r1}, [surf_C, {idx,x}];
suld.b.a2d.b32         r0, [surf_D, {idx,x,y,z}];  // z ignored

suld.b.{1d,2d,3d}
Load from surface memory using a surface coordinate vector. The instruction loads data from the
surface named by operand a at coordinates given by operand b into destination d. Operand a is a.surfref variable or.u64 register. Operand b is a scalar or singleton tuple
for 1d surfaces; is a two-element vector for 2d surfaces; and is a four-element vector for 3d
surfaces, where the fourth element is ignored. Coordinate elements are of type.s32.
suld.b performs an unformatted load of binary data. (see the official PTX ISA docs for the full description)