Packed Compare Explicit Length Strings, Return Index

Summary: Complex string search/compare; returns index in ECX.

Performs explicit-length packed string comparison between two 128-bit operands using element size and comparison operation encoded in imm8, returning the index of the first match (or mismatch, depending on control bits) in ECX and setting CF and ZF flags. The lengths of the strings are provided implicitly in EAX and EDX; this is a SSE4.2 instruction that can serialize the pipeline and is available in 64-bit and protected modes.

pcmp_control ← imm8[2:0]
string_type ← imm8[5:4]
polarity ← imm8[7:6]
len1 ← EAX & 0xFFFF
len2 ← EDX & 0xFFFF
intres ← perform_string_compare(dest, src, string_type, pcmp_control, len1, len2)
ECX ← intres
CF ← (intres < string_length)
ZF ← (intres == string_length)
SF ← OF ← undefined


Packed Compare Explicit Length Strings, Return Mask

Summary: Complex string search/compare; returns mask in XMM0.

128-bit XMM SIMD register or Memory operand

Performs explicit-length packed string comparison between two 128-bit operands using element size and comparison operation encoded in imm8, returning a 128-bit mask of comparison results in XMM0 and setting CF and ZF flags. The string lengths are provided implicitly in EAX and EDX; this is a SSE4.2 instruction that can serialize the pipeline and is available in 64-bit and protected modes.

pcmp_control ← imm8[2:0]
string_type ← imm8[5:4]
polarity ← imm8[7:6]
len1 ← EAX & 0xFFFF
len2 ← EDX & 0xFFFF
mask ← perform_string_compare_mask(dest, src, string_type, pcmp_control, len1, len2)
XMM0 ← mask
CF ← (any_match_found)
ZF ← (all_matches_found)
SF ← OF ← undefined


Packed Compare Implicit Length Strings, Return Index

Summary: String search (null-terminated); returns index in ECX.

Performs implicit-length (null-terminated) packed string comparison between two 128-bit operands using element size and comparison operation encoded in imm8, returning the index of the first match in ECX and setting CF and ZF flags. String lengths are determined by scanning for zero terminators; this is a SSE4.2 instruction that can serialize the pipeline and is available in 64-bit and protected modes.

pcmp_control ← imm8[2:0]
string_type ← imm8[5:4]
polarity ← imm8[7:6]
len1 ← scan_for_null(dest, string_type)
len2 ← scan_for_null(src, string_type)
intres ← perform_string_compare(dest, src, string_type, pcmp_control, len1, len2)
ECX ← intres
CF ← (intres < max_length)
ZF ← (intres == max_length)
SF ← OF ← undefined


Summary: Scalar FMA: Dest = (Dest * Src2) + Src1.

Performs a scalar fused multiply-add of three operands using VEX encoding: computes (Dest * Src2) + Src1 and stores the result in Dest with only the lower 32-bit scalar single-precision element affected while preserving upper 96 bits. The operand order '132' indicates destination is the first operand, first source is the second register operand, and second source is the third operand. No CPU flags are modified; this is a FMA3 instruction available in 64-bit mode on processors supporting the FMA3 extension.


Summary: Scalar FMA: Dest = (Src1 * Dest) + Src2.

Fused multiply-add scalar single: performs (Src1 * Dest) + Src2, storing the result in Dest with a single rounding step. Only the lowest 32-bit float element is operated on; upper 96 bits of Dest are preserved. No EFLAGS are modified; rounding is controlled by MXCSR.


Summary: Scalar FMA: Dest = (Src1 * Src2) + Dest.

Fused multiply-add scalar single: performs (Src1 * Src2) + Dest, storing the result in Dest with a single rounding step. Only the lowest 32-bit float element is operated on; upper 96 bits of Dest are preserved. No EFLAGS are modified; rounding is controlled by MXCSR.


Summary: Shuffles floats within 128-bit lanes (AVX).

256-bit YMM AVX register or Memory operand

Permutes 32-bit float elements within 128-bit lanes independently using an 8-bit immediate, allowing shuffles within the lower and upper halves of a 256-bit register. No EFLAGS are affected. The immediate encoding selects 2-bit indices per float element.


Summary: Shuffles doubles within 128-bit lanes (AVX).

Permutes 64-bit double elements within 128-bit lanes independently using an 8-bit immediate, allowing shuffles within the lower and upper halves of a 256-bit register. No EFLAGS are affected. The immediate encoding selects 1-bit indices per double element.


Summary: Loads one float and replicates it to all YMM elements.

Loads a single 32-bit float from memory and replicates it to all eight 32-bit elements in a 256-bit YMM register. No EFLAGS are modified. Requires AVX support.

value ← [Src]
for i ← 0 to 7:
  Dest[i*32 : i*32 + 31] ← value


Summary: Loads one integer and replicates it to all YMM elements.

Loads a single 32-bit integer from a register or memory and replicates it to all eight 32-bit elements in a 256-bit YMM register. No EFLAGS are modified. Requires AVX2 support.

if Src is xmm register:
  value ← Src[0..31]
else (Src is m32):
  value ← [Src]
for i ← 0 to 7:
  Dest[i*32 : i*32 + 31] ← value


Summary: Performs carry-less multiplication (Galois Field math for AES-GCM).

Performs carry-less multiplication of two 64-bit operands extracted from 128-bit XMM operands, producing a 128-bit result. Used in Galois/Counter Mode (GCM) for AES authentication. No EFLAGS are modified. The immediate selects which 64-bit halves of the operands participate.

if Imm[0] == 0:
  a ← Src1[0..63]
else:
  a ← Src1[64..127]
if Imm[4] == 0:
  b ← Src2[0..63]
else:
  b ← Src2[64..127]
Dest ← GF_multiply(a, b)  // Carry-less multiplication in GF(2^64), result fits in 128 bits


Summary: Accumulates CRC32C value using polynomial 0x11EDC6F41.

dest

32-bit general-purpose register (e.g. EAX)

Accumulates a CRC32C checksum using the Castagnoli polynomial (0x11EDC6F41) into the destination register. The source operand size (8/16/32/64-bit) determines the operation width; destination is zero-extended to full register width. No EFLAGS are modified. Requires SSE4.2.

if Src is 8-bit:
  Dest[0..31] ← CRC32C(Dest[0..31], [Src])
  Dest[32..63] ← 0 (if 64-bit destination)
else if Src is 16-bit:
  Dest[0..31] ← CRC32C(Dest[0..31], [Src])
  Dest[32..63] ← 0 (if 64-bit destination)
else if Src is 32-bit:
  Dest[0..31] ← CRC32C(Dest[0..31], [Src])
  Dest[32..63] ← 0 (if 64-bit destination)
else if Src is 64-bit:
  Dest ← CRC32C(Dest, [Src])


Convert Signed Quadword Integer to Scalar Single-Precision

Summary: Converts 64-bit integer to float.

Converts a signed 64-bit integer to a single-precision floating-point value and stores it in the low 32 bits of the destination XMM register; the upper 96 bits are zeroed. The conversion uses the current rounding mode from MXCSR. This instruction is only available in 64-bit mode and sets no flags.

dest[31:0] ← ConvertInt64ToSinglePrecision(src);
dest[127:32] ← 0;


Convert Signed Quadword Integer to Scalar Double-Precision

Summary: Converts 64-bit integer to double.

Converts a signed 64-bit integer to a double-precision floating-point value and stores it in the low 64 bits of the destination XMM register; the upper 64 bits are zeroed. The conversion uses the current rounding mode from MXCSR. This instruction is only available in 64-bit mode and sets no flags.

dest[63:0] ← ConvertInt64ToDoublePrecision(src);
dest[127:64] ← 0;


Convert Scalar Single-Precision to Signed Quadword Integer

Summary: Converts float to 64-bit integer (Rounded).

64-bit general-purpose register (e.g. RAX)

Converts the low 32-bit single-precision floating-point value from the source XMM register or memory to a signed 64-bit integer, using the current rounding mode from MXCSR. The result is stored in the destination 64-bit general-purpose register. This instruction is only available in 64-bit mode and sets no flags.


Convert Scalar Double-Precision to Signed Quadword Integer

Summary: Converts double to 64-bit integer (Rounded).

Converts the low 64-bit double-precision floating-point value from the source XMM register or memory to a signed 64-bit integer, using the current rounding mode from MXCSR. The result is stored in the destination 64-bit general-purpose register. This instruction is only available in 64-bit mode and sets no flags.


Convert with Truncation Scalar Single-Precision to Signed Quadword Integer

Summary: Converts float to 64-bit integer (Truncated).

Converts the low 32-bit single-precision floating-point value from the source XMM register or memory to a signed 64-bit integer by truncating toward zero (ignoring MXCSR rounding mode). The result is stored in the destination 64-bit general-purpose register. This instruction is only available in 64-bit mode and sets no flags.


Convert with Truncation Scalar Double-Precision to Signed Quadword Integer

Summary: Converts double to 64-bit integer (Truncated).

Converts the low 64-bit double-precision floating-point value from the source XMM register or memory to a signed 64-bit integer by truncating toward zero (ignoring MXCSR rounding mode). The result is stored in the destination 64-bit general-purpose register. This instruction is only available in 64-bit mode and sets no flags.


Summary: Adds adjacent double-precision elements horizontally.

Horizontally adds adjacent pairs of double-precision floating-point elements: the first destination element is the sum of the two low double elements, and the second destination element is the sum of the two high double elements. The source operand may be an XMM register or 128-bit memory. No flags are modified.


Horizontal Subtract Packed Single-Precision

Summary: Subtracts adjacent single-precision elements horizontally.

Horizontally subtracts adjacent pairs of single-precision floating-point elements: the first destination element is the difference of the two low single elements, and the second destination element is the difference of the two high single elements. The source operand may be an XMM register or 128-bit memory. No flags are modified.


Horizontal Subtract Packed Double-Precision

Summary: Subtracts adjacent double-precision elements horizontally.

Performs horizontal subtraction of adjacent pairs of double-precision floating-point values in the source and destination XMM registers, storing results in the destination. Specifically, it subtracts the upper element from the lower element of each 128-bit lane (result[63:0] = dest[63:0] - dest[127:64]; result[127:64] = src[63:0] - src[127:64]). All floating-point exception flags may be set based on the operation; no integer flags are affected. This is an SSE3 instruction operating exclusively on 128-bit XMM registers.


Summary: Adds odd elements, subtracts even elements (Double).

Performs lane-wise alternating addition and subtraction on packed double-precision floating-point values: even-indexed elements (0, 2, ...) are subtracted, odd-indexed elements (1, 3, ...) are added. The operation is (dest[63:0] - src[63:0]) in the low qword and (dest[127:64] + src[127:64]) in the high qword. All floating-point exception flags may be set; no integer flags are affected. This is an SSE3 instruction operating on 128-bit XMM registers.


Summary: Shuffles quadwords from two ZMM registers into destination.

512-bit ZMM AVX-512 register or Memory operand

Performs a two-source permutation of 64-bit quadwords using indices from the destination register (zmm1), which acts as the index/control vector. Each 6-bit index in zmm1 selects a quadword from either zmm2 (index 0-7) or zmm3 (index 8-15), with the selected element placed into the corresponding position in the destination. The instruction supports AVX-512F masking via the k1 opmask register and operates on 512-bit ZMM registers. Memory operands are supported for zmm3/m512.


Permute Two-Source Quadwords (Overwrite)

Summary: Shuffles 2 sources, overwriting the index register (Quadword).

Performs a two-source permutation of 64-bit quadwords using indices from the second source register (zmm2), which acts as the control vector. Each 6-bit index in zmm2 selects a quadword from either zmm1 (index 0-7) or zmm3 (index 8-15), and the result is stored in the destination (zmm1), overwriting the original source data. The instruction supports AVX-512F masking via the k1 opmask register and operates on 512-bit ZMM registers. Memory operands are supported for zmm3/m512.


Variable Bit Shift Left Logical Doubleword

Summary: Shifts doublewords left by individual counts.

Performs variable left logical bit shift on packed 32-bit doublewords, where each element is shifted by the corresponding count value from the third operand (bits 4:0 of each 32-bit element determine the shift amount, max 31 bits). Bits shifted out are lost; positions vacated are filled with zeros. The instruction operates on 256-bit YMM registers with AVX2 encoding and does not affect any integer flags.


Variable Bit Shift Left Logical Quadword

Summary: Shifts quadwords left by individual counts.

Performs variable left logical bit shift on packed 64-bit quadwords, where each element is shifted by the corresponding count value from the third operand (bits 5:0 of each 64-bit element determine the shift amount, max 63 bits). Bits shifted out are lost; positions vacated are filled with zeros. The instruction operates on 256-bit YMM registers with AVX2 encoding and does not affect any integer flags.


Variable Bit Shift Right Arithmetic Doubleword

Summary: Shifts doublewords right arithmetic by individual counts.

Performs variable arithmetic right shift on packed 32-bit signed doublewords, where each element is shifted by the corresponding count value from the third operand (bits 4:0 of each 32-bit element determine the shift amount, max 31 bits). The sign bit is replicated into vacated positions. The instruction operates on 256-bit YMM registers with AVX2 encoding and does not affect any integer flags.


Variable Bit Shift Right Arithmetic Quadword

Summary: Shifts quadwords right arithmetic by individual counts.

Performs variable arithmetic right shift on packed 64-bit signed quadwords, where each element is shifted by the corresponding count value from the third operand (bits 5:0 of each 64-bit element determine the shift amount, max 63 bits). The sign bit is replicated into vacated positions. The instruction supports AVX-512F masking via the k1 opmask register and operates on 512-bit ZMM registers. Memory operands are supported for zmm3/m512; no integer flags are affected.


Variable Bit Shift Right Logical Doubleword

Summary: Shifts doublewords right logical by individual counts.

Performs variable logical right shifts on packed 32-bit doublewords in the first source operand (ymm2) by the amounts specified in the corresponding doubleword elements of the second source operand (ymm3/m256), storing results in the destination (ymm1). Each doubleword is shifted independently; shift amounts > 31 produce zero. No flags are affected; this is an AVX2 instruction available in 256-bit form.

for i in 0 to 7:
  shift_amount = src2[i*32 : i*32+31]
  if shift_amount > 31:
    dest[i*32 : i*32+31] = 0
  else:
    dest[i*32 : i*32+31] = src1[i*32 : i*32+31] >> shift_amount


Variable Bit Shift Right Logical Quadword

Summary: Shifts quadwords right logical by individual counts.

Performs variable logical right shifts on packed 64-bit quadwords in the first source operand (ymm2) by the amounts specified in the corresponding quadword elements of the second source operand (ymm3/m256), storing results in the destination (ymm1). Each quadword is shifted independently; shift amounts > 63 produce zero. No flags are affected; this is an AVX2 instruction available in 256-bit form.

for i in 0 to 3:
  shift_amount = src2[i*64 : i*64+63]
  if shift_amount > 63:
    dest[i*64 : i*64+63] = 0
  else:
    dest[i*64 : i*64+63] = src1[i*64 : i*64+63] >> shift_amount


Summary: Returns minimum of signed bytes.

Compares packed signed byte integers in the destination operand (xmm1) with those in the source operand (xmm2/m128) and stores the minimum of each pair in the destination. Each of the 16 bytes is compared independently as a signed 8-bit value. No flags are affected; this is an SSE4.1 instruction that operates on 128-bit XMM registers.

for i in 0 to 15:
  byte_a = sign_extend(dest[i*8 : i*8+7])
  byte_b = sign_extend(src[i*8 : i*8+7])
  dest[i*8 : i*8+7] = (byte_a < byte_b) ? byte_a : byte_b


Summary: Returns maximum of signed bytes.

Compares packed signed byte integers in the destination operand (xmm1) with those in the source operand (xmm2/m128) and stores the maximum of each pair in the destination. Each of the 16 bytes is compared independently as a signed 8-bit value. No flags are affected; this is an SSE4.1 instruction that operates on 128-bit XMM registers.

for i in 0 to 15:
  byte_a = sign_extend(dest[i*8 : i*8+7])
  byte_b = sign_extend(src[i*8 : i*8+7])
  dest[i*8 : i*8+7] = (byte_a > byte_b) ? byte_a : byte_b


Minimum of Packed Unsigned Word Integers

Summary: Returns minimum of unsigned words.

Compares packed unsigned word integers in the destination operand (xmm1) with those in the source operand (xmm2/m128) and stores the minimum of each pair in the destination. Each of the 8 words is compared independently as an unsigned 16-bit value. No flags are affected; this is an SSE4.1 instruction that operates on 128-bit XMM registers.

for i in 0 to 7:
  word_a = dest[i*16 : i*16+15]
  word_b = src[i*16 : i*16+15]
  dest[i*16 : i*16+15] = (word_a < word_b) ? word_a : word_b


Maximum of Packed Unsigned Word Integers

Summary: Returns maximum of unsigned words.

Compares packed unsigned word integers in the destination operand (xmm1) with those in the source operand (xmm2/m128) and stores the maximum of each pair in the destination. Each of the 8 words is compared independently as an unsigned 16-bit value. No flags are affected; this is an SSE4.1 instruction that operates on 128-bit XMM registers.

for i in 0 to 7:
  word_a = dest[i*16 : i*16+15]
  word_b = src[i*16 : i*16+15]
  dest[i*16 : i*16+15] = (word_a > word_b) ? word_a : word_b


Minimum of Packed Unsigned Doubleword Integers

Summary: Returns minimum of unsigned doublewords.

Compares packed unsigned doubleword integers in the destination operand (xmm1) with those in the source operand (xmm2/m128) and stores the minimum of each pair in the destination. Each of the 4 doublewords is compared independently as an unsigned 32-bit value. No flags are affected; this is an SSE4.1 instruction that operates on 128-bit XMM registers.

for i in 0 to 3:
  dword_a = dest[i*32 : i*32+31]
  dword_b = src[i*32 : i*32+31]
  dest[i*32 : i*32+31] = (dword_a < dword_b) ? dword_a : dword_b


Maximum of Packed Unsigned Doubleword Integers

Summary: Returns maximum of unsigned doublewords.

Compares packed unsigned doubleword integers in the destination operand (xmm1) with those in the source operand (xmm2/m128) and stores the maximum of each pair in the destination. Each of the 4 doublewords is compared independently as an unsigned 32-bit value. No flags are affected; this is an SSE4.1 instruction that operates on 128-bit XMM registers.

for i in 0 to 3:
  dword_a = dest[i*32 : i*32+31]
  dword_b = src[i*32 : i*32+31]
  dest[i*32 : i*32+31] = (dword_a > dword_b) ? dword_a : dword_b


Minimum of Packed Signed Doubleword Integers

Summary: Returns minimum of signed doublewords.

Compares packed signed 32-bit integers in xmm1 with xmm2/m128 and writes the minimum of each pair to xmm1. This is a SIMD operation with no effect on the CPU flags. Available in SSE4.1 and later; operates on 128-bit XMM registers containing four 32-bit signed doublewords.


Maximum of Packed Signed Doubleword Integers

Summary: Returns maximum of signed doublewords.

Compares packed signed 32-bit integers in xmm1 with xmm2/m128 and writes the maximum of each pair to xmm1. This is a SIMD operation with no effect on the CPU flags. Available in SSE4.1 and later; operates on 128-bit XMM registers containing four 32-bit signed doublewords.


Summary: Inserts a doubleword from register to XMM.

General-purpose register or Memory operand

Inserts a 32-bit doubleword from a general-purpose register or memory into an XMM register at the position specified by an 8-bit immediate index. The remaining XMM lanes are unchanged. Available in SSE4.1 and later; no flags are affected by this instruction.


Summary: Inserts a quadword from register to XMM.

Inserts a 64-bit quadword from a general-purpose register or memory into an XMM register at the position specified by an 8-bit immediate index. The other 64-bit lane remains unchanged. Available in SSE4.1 and later (64-bit mode only); no flags are affected by this instruction.

index ← imm8[0];
case index of
  0: xmm1[63:0] ← (r64/m64 is register) ? r64 : [r64/m64];
  1: xmm1[127:64] ← (r64/m64 is register) ? r64 : [r64/m64];
endcase;


Summary: Extracts a doubleword from XMM to register.

Extracts a 32-bit doubleword from an XMM register at the position specified by an 8-bit immediate and writes it to a general-purpose register or memory. Zero-extends the extracted value when writing to a 32-bit register. Available in SSE4.1 and later; no flags are affected by this instruction.

index ← imm8[1:0];
case index of
  0: value ← xmm1[31:0];
  1: value ← xmm1[63:32];
  2: value ← xmm1[95:64];
  3: value ← xmm1[127:96];
endcase;
if (r32/m32 is register) then
  r32 ← value;
else
  [r32/m32] ← value;
endif;


Summary: Extracts a quadword from XMM to register.

Extracts a 64-bit quadword from an XMM register at the position specified by an 8-bit immediate and writes it to a general-purpose register or memory. Available in SSE4.1 and later (64-bit mode only); no flags are affected by this instruction.

index ← imm8[0];
case index of
  0: value ← xmm1[63:0];
  1: value ← xmm1[127:64];
endcase;
if (r64/m64 is register) then
  r64 ← value;
else
  [r64/m64] ← value;
endif;


Load Double Quadword Non-Temporal Aligned

Summary: Efficiently loads 128-bits from WC memory (Streaming Load).

Loads 128 bits from write-combining (WC) memory into an XMM register using a non-temporal hint to minimize cache pollution. This instruction bypasses the normal cache coherency protocol and is optimized for streaming data loads. Available in SSE4.1 and later; no flags are affected. The memory address should be 16-byte aligned for best performance.


Summary: Compares quadwords for greater than (signed).

Compares packed signed 64-bit integers in xmm1 with xmm2/m128 for greater-than, writing a mask (all-1s for true, all-0s for false) of each comparison to xmm1. This is a SIMD comparison with no effect on the CPU flags. Available in SSE4.2 and later; operates on 128-bit XMM registers containing two 64-bit signed quadwords.


Pack with Unsigned Saturation Doubleword to Word

Summary: Converts signed dwords to unsigned words with saturation.

Packs four signed doublewords (32-bit) from each 128-bit operand into eight unsigned words (16-bit) with unsigned saturation, storing the result in the destination XMM register. Values outside the range [0, 65535] are saturated to the nearest boundary. No flags are affected.


Summary: Sets byte to 1 if SF=1 (Negative).

Sets the destination byte to 1 if the Sign Flag (SF) is set (indicating a negative result from the previous operation), otherwise sets it to 0. No flags are affected by this instruction. Available in all x86/x64 modes.

if (SF == 1) {
  dest ← 0xFF
} else {
  dest ← 0x00
}


Summary: Sets byte to 1 if SF=0 (Positive).

Sets the destination byte to 1 if the Sign Flag (SF) is clear (indicating a positive or zero result from the previous operation), otherwise sets it to 0. No flags are affected by this instruction. Available in all x86/x64 modes.

if (SF == 0) {
  dest ← 0xFF
} else {
  dest ← 0x00
}


Summary: Sets byte to 1 if PF=1 (Even Parity).

Sets the destination byte to 1 if the Parity Flag (PF) is set (indicating an even number of 1-bits in the low byte of the result), otherwise sets it to 0. No flags are affected by this instruction. Available in all x86/x64 modes.

if (PF == 1) {
  dest ← 0xFF
} else {
  dest ← 0x00
}


Summary: Sets byte to 1 if PF=0 (Odd Parity).

Sets the destination byte to 1 if the Parity Flag (PF) is clear (indicating an odd number of 1-bits in the low byte of the result), otherwise sets it to 0. No flags are affected by this instruction. Available in all x86/x64 modes.

if (PF == 0) {
  dest ← 0xFF
} else {
  dest ← 0x00
}


Summary: Sets byte to 1 if SF!=OF.

Sets the destination byte to 1 if the previous signed comparison or arithmetic result indicates a less-than condition (SF ≠ OF), otherwise sets it to 0. No flags are affected by this instruction. Used after signed compare or arithmetic operations.

if (SF != OF) {
  dest ← 0xFF
} else {
  dest ← 0x00
}


Summary: Sets byte to 1 if ZF=1 or SF!=OF.

Sets the destination byte to 1 if the previous signed comparison or arithmetic result indicates a less-than-or-equal condition (ZF = 1 or SF ≠ OF), otherwise sets it to 0. No flags are affected by this instruction. Used after signed compare or arithmetic operations.

if ((ZF == 1) || (SF != OF)) {
  dest ← 0xFF
} else {
  dest ← 0x00
}


Summary: Sets byte to 1 if ZF=0 and SF=OF.

Sets the destination byte to 1 if the previous signed comparison or arithmetic result indicates a greater-than condition (ZF = 0 and SF = OF), otherwise sets it to 0. No flags are affected by this instruction. Used after signed compare or arithmetic operations.

if ((ZF == 0) && (SF == OF)) {
  dest ← 0xFF
} else {
  dest ← 0x00
}


Summary: Sets byte to 1 if SF=OF.

Sets the destination byte to 1 if the signed comparison condition is true (SF = OF, indicating greater-than-or-equal for signed integers), or to 0 otherwise. This instruction reads the SF and OF flags from EFLAGS and does not modify any flags. It operates only on 8-bit destinations in all modes.


Summary: Sets byte to 1 if CF=1.

Sets the destination byte to 1 if the carry flag (CF) is set, indicating an unsigned borrow or carry condition, or to 0 otherwise. This instruction reads CF from EFLAGS and does not modify any flags. It operates only on 8-bit destinations in all modes.


Summary: Sets byte to 1 if CF=1 or ZF=1.

Sets the destination byte to 1 if the unsigned comparison condition is true (CF = 1 or ZF = 1, indicating below-or-equal for unsigned integers), or to 0 otherwise. This instruction reads the CF and ZF flags from EFLAGS and does not modify any flags. It operates only on 8-bit destinations in all modes.


Summary: Sets byte to 1 if CF=0 and ZF=0.

Sets the destination byte to 1 if the unsigned comparison condition is true (CF = 0 and ZF = 0, indicating above for unsigned integers), or to 0 otherwise. This instruction reads the CF and ZF flags from EFLAGS and does not modify any flags. It operates only on 8-bit destinations in all modes.


Summary: Sets byte to 1 if CF=0.

Sets the destination byte to 1 if the carry flag (CF) is clear, indicating no unsigned borrow (above-or-equal for unsigned integers), or to 0 otherwise. This instruction reads CF from EFLAGS and does not modify any flags. It operates only on 8-bit destinations in all modes.


Unpack and Interleave Masks Word to Doubleword

Summary: Interleaves 16-bit masks into 32-bit mask.

Unpacks and interleaves two 16-bit mask registers into a 32-bit mask register, with src2 supplying the high 16 bits and src1 supplying the low 16 bits of the result. This instruction is part of AVX-512BW and operates only on opmask registers (k0-k7); it does not modify any EFLAGS flags. The opmask register k0 cannot be used as a write mask.


Unpack and Interleave Masks Doubleword to Quadword

Summary: Interleaves 32-bit masks into 64-bit mask.

Unpacks and interleaves two 32-bit mask registers into a 64-bit mask register, with src2 supplying the high 32 bits and src1 supplying the low 32 bits of the result. This instruction is part of AVX-512BW and operates only on opmask registers (k0-k7); it does not modify any EFLAGS flags. The opmask register k0 cannot be used as a write mask.


Detect Conflicts Within a Vector of Packed Quadword Values

Summary: Detects duplicate values in a quadword vector.

Detects conflicts (duplicate values) within a vector of 64-bit quadword values and writes a conflict mask to the destination; each element in the result contains a bitmask indicating which earlier elements in the source vector have the same value. This instruction is part of AVX-512CD, supports embedded masking via k1, and does not modify EFLAGS. Zeroing masking clears masked elements in the destination.

for i ← 0 to 7 do { dest[i*64+63:i*64] ← 0; for j ← 0 to i-1 do if src[i*64+63:i*64] == src[j*64+63:j*64] then dest[i*64+j] ← 1; } if k1_mask[i] == 0 and zeroing then dest[i*64+63:i*64] ← 0;


Summary: Counts leading zeros for each quadword element.

Counts the number of leading zero bits in each 64-bit quadword element of the source operand and stores the results in the destination register. Operates element-wise on 8 quadwords (512-bit / 64-bit per element). The instruction does not modify CPU flags; it is a pure SIMD data-parallel operation with AVX-512 opmask support for conditional write-masking.

for i = 0 to 7:
  src_qw = src2[64*i : 64*i+63]
  dest[64*i : 64*i+63] ← count_leading_zeros_64(src_qw)


Summary: Full permutation of 32 words using indices.

Performs a full permutation of 32 word (16-bit) elements across the entire 512-bit register using indices from a second vector operand. The index operand specifies which source element to copy to each destination position. Supports AVX-512 opmask write-masking; does not affect CPU flags.


Summary: Shuffles quadwords within 256-bit lanes using immediate.

Shuffles four 64-bit quadword elements within each 256-bit lane using a 2-bit immediate index for each element. The immediate controls the permutation pattern within the two halves of the 256-bit operand independently. Does not affect CPU flags; operates on 256-bit YMM registers under AVX2.


Summary: Rotates quadwords left by amounts in second vector.

Rotates each 64-bit quadword element in the first source left by the number of bits specified in the corresponding element of the second source operand. Operates on 8 quadwords in parallel; supports AVX-512 opmask write-masking. Does not modify CPU flags.

for i = 0 to 7:
  value = src1[64*i : 64*i+63]
  shift_count = src2[64*i : 64*i+63] & 0x3F
  dest[64*i : 64*i+63] ← rotate_left_64(value, shift_count)


Summary: Rotates doublewords right by amounts in second vector.

Rotates each 32-bit doubleword element in the first source right by the number of bits specified in the corresponding element of the second source operand. Operates on 16 doublewords in parallel; supports AVX-512 opmask write-masking. Does not modify CPU flags.

for i = 0 to 15:
  value = src1[32*i : 32*i+31]
  shift_count = src2[32*i : 32*i+31] & 0x1F
  dest[32*i : 32*i+31] ← rotate_right_32(value, shift_count)


Summary: Rotates quadwords right by amounts in second vector.

Rotates each 64-bit quadword element in the first source right by the number of bits specified in the corresponding element of the second source operand. Operates on 8 quadwords in parallel; supports AVX-512 opmask write-masking. Does not modify CPU flags.

for i = 0 to 7:
  value = src1[64*i : 64*i+63]
  shift_count = src2[64*i : 64*i+63] & 0x3F
  dest[64*i : 64*i+63] ← rotate_right_64(value, shift_count)


Summary: Moves byte integer mask from ZMM to k-register.

Extracts the most significant bit (MSB) from each byte element in a 512-bit ZMM register and compacts them into a 64-bit opmask register. The resulting mask register has one bit per original byte, forming a 64-bit result. Does not modify CPU flags; operates in 64-bit mode only with AVX-512BW.

mask_result = 0
for i = 0 to 63:
  if (src[8*i+7] != 0):
    mask_result |= (1 << i)
dest ← mask_result


Summary: Moves word integer mask from ZMM to k-register.

Extracts the most significant bit (MSB) from each word (16-bit) element in a 512-bit ZMM register and compacts them into a 32-bit opmask register. The resulting mask register has one bit per original word, forming a 32-bit result. Does not modify CPU flags; operates in 64-bit mode only with AVX-512BW.

mask_result = 0
for i = 0 to 31:
  if (src[16*i+15] != 0):
    mask_result |= (1 << i)
dest ← mask_result


Summary: Moves doubleword integer mask from ZMM to k-register.

Extracts the sign bit (MSB) from each 32-bit doubleword element in a 512-bit ZMM register and compacts these bits into an 8-bit mask register (k1). This instruction performs a vectorized comparison-to-mask operation, setting each bit in the destination k-register based on the corresponding doubleword's sign bit. No flags are affected by this instruction.


Summary: Moves quadword integer mask from ZMM to k-register.

Extracts the sign bit (MSB) from each 64-bit quadword element in a 512-bit ZMM register and compacts these bits into an 8-bit mask register (k1). This instruction performs a vectorized comparison-to-mask operation on 64-bit elements, setting each bit in the destination k-register based on the corresponding quadword's sign bit. No flags are affected by this instruction.


Summary: Expands k-register bits to byte elements in ZMM.

Expands each bit from an 8-bit mask register into a full byte (0x00 or 0xFF) in a 512-bit ZMM register, producing 64 byte elements. Each set bit in the source k-register generates a byte of all 1s (0xFF) in the destination; each clear bit generates a byte of all 0s (0x00). No flags are affected; this is a mask-expansion operation with no conditional behavior.


Summary: Expands k-register bits to word elements in ZMM.

Expands each bit from an 8-bit mask register into a full word (0x0000 or 0xFFFF) in a 512-bit ZMM register, producing 32 word elements. Each set bit in the source k-register generates a word of all 1s (0xFFFF) in the destination; each clear bit generates a word of all 0s (0x0000). No flags are affected; this is a mask-expansion operation with no conditional behavior.


Summary: Expands k-register bits to doubleword elements in ZMM.

Expands each bit from an 8-bit mask register into a full doubleword (0x00000000 or 0xFFFFFFFF) in a 512-bit ZMM register, producing 16 doubleword elements. Each set bit in the source k-register generates a doubleword of all 1s (0xFFFFFFFF) in the destination; each clear bit generates a doubleword of all 0s (0x00000000). No flags are affected; this is a mask-expansion operation with no conditional behavior.


Summary: Expands k-register bits to quadword elements in ZMM.

Expands each bit from an 8-bit mask register into a full quadword (0x0000000000000000 or 0xFFFFFFFFFFFFFFFF) in a 512-bit ZMM register, producing 8 quadword elements. Each set bit in the source k-register generates a quadword of all 1s (0xFFFFFFFFFFFFFFFF) in the destination; each clear bit generates a quadword of all 0s (0x0000000000000000). No flags are affected; this is a mask-expansion operation with no conditional behavior.


Summary: Logically shifts 8-bit mask right.

Logically shifts the 8-bit contents of the source k-register right by the count specified in an 8-bit immediate, storing the result in the destination k-register. Vacated bit positions are filled with zeros; bits shifted out are discarded. No flags are affected by this mask shift operation.

shift_count ← imm8 & 0x07
k1 ← k2 >> shift_count
k1[8:63] ← 0


Summary: Logically shifts 16-bit mask right.

Logically shifts the 16-bit contents of the source k-register right by the count specified in an 8-bit immediate, storing the result in the destination k-register. Vacated bit positions are filled with zeros; bits shifted out are discarded. No flags are affected by this mask shift operation.

shift_count ← imm8 & 0x0F
k1 ← k2 >> shift_count
k1[16:63] ← 0


Summary: Logically shifts 32-bit mask right.

Logically shifts the 32-bit content of the source mask register right by the amount specified in the immediate operand, storing the result in the destination mask register. Bits shifted out are discarded; vacant bit positions are filled with zeros. No flags are affected; this is an AVX-512BW instruction that operates only on opmask registers (k0-k7).


Summary: Logically shifts 64-bit mask right.

Logically shifts the 64-bit content of the source mask register right by the amount specified in the immediate operand, storing the result in the destination mask register. Bits shifted out are discarded; vacant bit positions are filled with zeros. No flags are affected; this is an AVX-512BW instruction that operates only on opmask registers (k0-k7).

dest ← (src1 >> imm8) & 0xFFFFFFFFFFFFFFFF;


Summary: Logically shifts 8-bit mask left.

Logically shifts the 8-bit content of the source mask register left by the amount specified in the immediate operand, storing the result in the destination mask register. Bits shifted out are discarded; vacant bit positions are filled with zeros. No flags are affected; this is an AVX-512DQ instruction that operates only on opmask registers (k0-k7).


Summary: Logically shifts 16-bit mask left.

Logically shifts the 16-bit content of the source mask register left by the amount specified in the immediate operand, storing the result in the destination mask register. Bits shifted out are discarded; vacant bit positions are filled with zeros. No flags are affected; this is an AVX-512F instruction that operates only on opmask registers (k0-k7).


Summary: Logically shifts 32-bit mask left.

Logically shifts the 32-bit content of the source mask register left by the amount specified in the immediate operand, storing the result in the destination mask register. Bits shifted out are discarded; vacant bit positions are filled with zeros. No flags are affected; this is an AVX-512BW instruction that operates only on opmask registers (k0-k7).


Summary: Logically shifts 64-bit mask left.

Logically shifts the 64-bit content of the source mask register left by the amount specified in the immediate operand, storing the result in the destination mask register. Bits shifted out are discarded; vacant bit positions are filled with zeros. No flags are affected; this is an AVX-512BW instruction that operates only on opmask registers (k0-k7).

dest ← (src1 << imm8) & 0xFFFFFFFFFFFFFFFF;


Summary: Bitwise NOT of 8-bit mask.

Performs a bitwise NOT of the 8-bit content of the source mask register, storing the result in the destination mask register. Only the lower 8 bits are affected; other bits are zeroed. No flags are affected; this is an AVX-512DQ instruction that operates only on opmask registers (k0-k7).


Summary: Bitwise NOT of 32-bit mask.

Performs a bitwise NOT of the 32-bit content of the source mask register, storing the result in the destination mask register. Only the lower 32 bits are affected; other bits are zeroed. No flags are affected; this is an AVX-512BW instruction that operates only on opmask registers (k0-k7).


Summary: Bitwise OR of 8-bit masks.

Performs a bitwise OR of two 8-bit AVX-512 opmask registers and stores the result in the destination opmask. This instruction operates on the mask registers (k0-k7) and does not affect EFLAGS. It is part of the AVX-512DQ extension and executes with minimal latency on modern AVX-512 capable processors.


Summary: Bitwise OR of 32-bit masks.

Performs a bitwise OR of two 32-bit AVX-512 opmask registers and stores the result in the destination opmask. This instruction operates on mask registers (k0-k7) treating them as 32-bit values and does not affect EFLAGS. It is part of the AVX-512BW extension and executes with minimal latency.


Summary: Bitwise XOR of 64-bit masks.

Performs a bitwise XOR of two 64-bit AVX-512 opmask registers and stores the result in the destination opmask. This instruction operates on mask registers (k0-k7) treating them as 64-bit values and does not affect EFLAGS. It is part of the AVX-512BW extension and executes with minimal latency.


Summary: Bitwise XOR of 32-bit masks.

Performs a bitwise XOR of two 32-bit AVX-512 opmask registers and stores the result in the destination opmask. This instruction operates on mask registers (k0-k7) treating them as 32-bit values and does not affect EFLAGS. It is part of the AVX-512BW extension and executes with minimal latency.


Summary: Bitwise XOR of 8-bit masks.

Performs a bitwise XOR of two 8-bit AVX-512 opmask registers and stores the result in the destination opmask. This instruction operates on mask registers (k0-k7) and does not affect EFLAGS. It is part of the AVX-512DQ extension and executes with minimal latency.


Summary: ORs 8-bit masks and sets EFLAGS (ZF/CF).

ORs two 8-bit AVX-512 opmask registers and sets EFLAGS based on the result without storing the OR result. Sets ZF if the OR result is all zeros, and CF if the first source opmask is all zeros. Part of the AVX-512DQ extension, this instruction is useful for testing mask conditions.

temp ← k1 | k2; ZF ← (temp == 0); CF ← (k1 == 0);


Summary: ORs 64-bit masks and sets EFLAGS (ZF/CF).

ORs two 64-bit AVX-512 opmask registers and sets EFLAGS based on the result without storing the OR result. Sets ZF if the OR result is all zeros, and CF if the first source opmask is all zeros. Part of the AVX-512BW extension, this instruction is useful for testing mask conditions.


Summary: ANDs 8-bit masks and sets EFLAGS (ZF/CF).

ANDs two 8-bit AVX-512 opmask registers and sets EFLAGS based on the result without storing the AND result. Sets ZF if the AND result is all zeros, and CF if the first source opmask is all zeros. Part of the AVX-512DQ extension, this instruction is useful for testing mask bit intersections.

temp ← k1 & k2; ZF ← (temp == 0); CF ← (k1 == 0);


Summary: ANDs 16-bit masks and sets EFLAGS (ZF/CF).

Performs a bitwise AND of two 16-bit AVX-512 opmask registers and updates EFLAGS based on the result without storing the AND product. Sets ZF if the result is zero, clears ZF otherwise; sets CF if all bits of the first operand are zero, clears CF otherwise. This instruction executes in 64-bit mode only and is part of AVX-512F.

temp ← k1 AND k2
ZF ← (temp == 0)
CF ← (k1 == 0)
OF ← 0
SF ← 0
AF ← undefined
PF ← undefined


Summary: ANDs 32-bit masks and sets EFLAGS (ZF/CF).

Performs a bitwise AND of two 32-bit AVX-512 opmask registers and updates EFLAGS based on the result without storing the AND product. Sets ZF if the result is zero, clears ZF otherwise; sets CF if all bits of the first operand are zero, clears CF otherwise. This instruction executes in 64-bit mode only and requires AVX-512BW.


Summary: ANDs 64-bit masks and sets EFLAGS (ZF/CF).

Performs a bitwise AND of two 64-bit AVX-512 opmask registers and updates EFLAGS based on the result without storing the AND product. Sets ZF if the result is zero, clears ZF otherwise; sets CF if all bits of the first operand are zero, clears CF otherwise. This instruction executes in 64-bit mode only and requires AVX-512BW.


Convert Packed Unsigned Doubleword to Double

Summary: Converts unsigned 32-bit integers to 64-bit doubles.

Converts four unsigned 32-bit doublewords (from a 256-bit YMM or memory operand) to four 64-bit double-precision floating-point values, storing the result in a 512-bit ZMM register with optional opmask write control. The conversion uses the current rounding mode from MXCSR. Executes in 64-bit mode only and requires AVX-512F; precision may be lost for large unsigned integers that exceed 2^53.

for i ← 0 to 3
  if k1[i] or no mask:
    zmm1[64*i:64*i+63] ← convert_udq_to_pd(ymm2_or_mem[32*i:32*i+31])
  else if zeroing:
    zmm1[64*i:64*i+63] ← 0


Convert Packed Double to Unsigned Doubleword

Summary: Converts 64-bit doubles to unsigned 32-bit integers.

Converts eight 64-bit double-precision floating-point values (from a 512-bit ZMM or memory operand) to eight unsigned 32-bit doublewords, storing the result in a 256-bit YMM register with optional opmask write control. The conversion uses the current rounding mode from MXCSR; out-of-range values saturate to the maximum unsigned 32-bit integer (2^32-1). Executes in 64-bit mode only and requires AVX-512F.

for i ← 0 to 7
  if k1[i] or no mask:
    ymm1[32*i:32*i+31] ← convert_pd_to_udq_saturate(zmm2_or_mem[64*i:64*i+63])
  else if zeroing:
    ymm1[32*i:32*i+31] ← 0


Convert Packed Single to Unsigned Doubleword

Summary: Converts 32-bit floats to unsigned 32-bit integers.

Converts sixteen 32-bit single-precision floating-point values (from a 512-bit ZMM or memory operand) to sixteen unsigned 32-bit doublewords, storing the result in a 512-bit ZMM register with optional opmask write control. The conversion uses the current rounding mode from MXCSR; out-of-range values saturate to the maximum unsigned 32-bit integer (2^32-1). Executes in 64-bit mode only and requires AVX-512F.

for i ← 0 to 15
  if k1[i] or no mask:
    zmm1[32*i:32*i+31] ← convert_ps_to_udq_saturate(zmm2_or_mem[32*i:32*i+31])
  else if zeroing:
    zmm1[32*i:32*i+31] ← 0


Convert Packed Unsigned Quadword to Single

Summary: Converts unsigned 64-bit integers to 32-bit floats.

Converts eight unsigned 64-bit quadwords (from a 512-bit ZMM or memory operand) to eight 32-bit single-precision floating-point values, storing the result in a 256-bit YMM register with optional opmask write control. The conversion uses the current rounding mode from MXCSR. Executes in 64-bit mode only and requires AVX-512F; precision may be lost for large unsigned integers that exceed 2^24.

for i ← 0 to 7
  if k1[i] or no mask:
    ymm1[32*i:32*i+31] ← convert_uq_to_ps(zmm2_or_mem[64*i:64*i+63])
  else if zeroing:
    ymm1[32*i:32*i+31] ← 0


Convert Packed Unsigned Quadword to Double

Summary: Converts unsigned 64-bit integers to 64-bit doubles.

Converts eight unsigned 64-bit quadwords (from a 512-bit ZMM or memory operand) to eight 64-bit double-precision floating-point values, storing the result in a 512-bit ZMM register with optional opmask write control. The conversion uses the current rounding mode from MXCSR. Executes in 64-bit mode only and requires AVX-512F; full precision is maintained since IEEE 754 double can exactly represent all 64-bit unsigned integers.

for i ← 0 to 7
  if k1[i] or no mask:
    zmm1[64*i:64*i+63] ← convert_uq_to_pd(zmm2_or_mem[64*i:64*i+63])
  else if zeroing:
    zmm1[64*i:64*i+63] ← 0


Convert Packed Single to Unsigned Quadword

Summary: Converts 32-bit floats to unsigned 64-bit integers.

Converts packed 32-bit single-precision floating-point values to unsigned 64-bit integers. The instruction reads 256 bits (4 × 32-bit floats from ymm2/m256) and produces 512 bits (4 × 64-bit unsigned integers in zmm1). EVEX encoding enables masking via k1 and rounding mode control; results are undefined if any value overflows the unsigned 64-bit range, and invalid floating-point exceptions are raised on NaN inputs. The instruction operates in 64-bit, protected, and real modes with AVX-512F support.

zmm1[63:0] ← (src[31:0] is valid && src[31:0] ≤ 2^64-1) ? convert_float_to_uint64(src[31:0]) : undefined; zmm1[127:64] ← convert_float_to_uint64(src[63:32]); zmm1[191:128] ← convert_float_to_uint64(src[95:64]); zmm1[255:192] ← convert_float_to_uint64(src[127:96]);


Convert Packed Double to Unsigned Quadword

Summary: Converts 64-bit doubles to unsigned 64-bit integers.

Converts packed 64-bit double-precision floating-point values to unsigned 64-bit integers. The instruction reads 512 bits (4 × 64-bit doubles from zmm2/m512) and produces 512 bits (4 × 64-bit unsigned integers in zmm1). EVEX masking via k1 and rounding control are supported; overflow conditions and NaN inputs trigger invalid floating-point exceptions. Operates in 64-bit, protected, and real modes with AVX-512F support.

zmm1[63:0] ← convert_double_to_uint64(src[63:0]); zmm1[127:64] ← convert_double_to_uint64(src[127:64]); zmm1[191:128] ← convert_double_to_uint64(src[191:128]); zmm1[255:192] ← convert_double_to_uint64(src[255:192]);


Summary: Complex multiply-add for half-precision.

Performs complex multiply-add on packed half-precision (FP16) complex numbers. Each ZMM register holds 16 FP16 values (8 complex pairs); the instruction computes (src1 × src2) + dest for each complex pair and stores the result in dest. EVEX masking (k1) and embedded rounding are supported. Intermediate calculations use extended precision to minimize rounding errors. Requires AVX-512-FP16 support.


Summary: Complex conjugate multiply-add for half-precision.

Performs complex conjugate multiply-add on packed half-precision (FP16) complex numbers. Each ZMM holds 16 FP16 values (8 complex pairs); the instruction computes (src1 × conj(src2)) + dest for each pair, where conj() negates the imaginary component. EVEX masking (k1) and embedded rounding control are supported. Intermediate precision extension minimizes rounding artifacts. Requires AVX-512-FP16 support.


Summary: Complex multiply-add for scalar half-precision.

Performs scalar complex multiply-add on half-precision (FP16) complex numbers. The lower 32 bits of xmm1 and xmm2 represent a single complex number (two FP16 values: real and imaginary); the instruction computes (src1 × src2) + dest for that pair and updates only the lower 32 bits of xmm1. EVEX masking (k1) and embedded rounding are supported. Requires AVX-512-FP16 support.


Summary: Compares packed floats (AVX version with immediate).

Compares packed 32-bit single-precision floats and stores the boolean result (all-ones or all-zeros per element) in the destination YMM register. The comparison operator is encoded in the imm8 field (0=EQ, 1=LT, 2=LE, 4=NEQ, 5=NLT, 6=NLE, etc.). Quiet NaNs produce false results; signaling NaNs trigger invalid floating-point exceptions (unless masked). VEX encoding supports 256-bit operations; three-operand form allows non-destructive destination. Operates in 64-bit, protected, and real modes with AVX support.

for i = 0 to 7 do: cmp_result ← compare_float(src1[32*i+31:32*i], src2[32*i+31:32*i], imm8); dest[32*i+31:32*i] ← cmp_result ? 0xFFFFFFFF : 0x00000000;


Summary: Compares packed doubles (AVX version with immediate).

Compares packed 64-bit double-precision floats and stores the boolean result (all-ones or all-zeros per element) in the destination YMM register. The comparison predicate is encoded in imm8 (0=EQ, 1=LT, 2=LE, 4=NEQ, 5=NLT, 6=NLE, etc.). Quiet NaNs return false; signaling NaNs trigger invalid floating-point exceptions (unless masked). VEX encoding supports 256-bit operations; three-operand form enables non-destructive destination. Operates in 64-bit, protected, and real modes with AVX support.

for i = 0 to 3 do: cmp_result ← compare_double(src1[64*i+63:64*i], src2[64*i+63:64*i], imm8); dest[64*i+63:64*i] ← cmp_result ? 0xFFFFFFFFFFFFFFFF : 0x0000000000000000;


Summary: Compares bytes and stores result in k-register mask.

Compares packed 8-bit signed integers and stores the boolean result in an AVX-512 opmask register (k1). The comparison operator is encoded in imm8 (0=EQ, 1=LT, 2=LE, 4=NEQ, 5=NLT, 6=NLE, etc.). EVEX encoding enables masking via k2 (merge-with-zero or keep-unchanged per bit). The destination k1 register holds 64 single-bit results corresponding to 64 bytes. Operates in 64-bit mode with AVX-512BW support.

for i = 0 to 63 do: if k2[i] == 1 or k2 is unused then: cmp_result ← compare_signed_byte(src1[8*i+7:8*i], src2[8*i+7:8*i], imm8); k1[i] ← cmp_result ? 1 : 0; else: k1[i] ← 0;


Summary: Compares words and stores result in k-register mask.

Compares packed signed 16-bit integers in zmm2 against zmm3/m512 using the comparison predicate specified in imm8, storing the boolean results in the opmask k1 (optionally merged with k2). The instruction operates on 32 word elements in 512-bit vectors and does not modify EFLAGS; the predicate selector in imm8 determines the comparison type (equal, less, less-equal, unordered, etc.). Available only in 64-bit mode with AVX-512BW extension.

for i in 0..31:
  elem1 ← zmm2[16*i : 16*i+15] as signed 16-bit
  elem2 ← zmm3/m512[16*i : 16*i+15] as signed 16-bit
  k1[i] ← (mask_merge) ? k2[i] : 0
  if pred(elem1, elem2, imm8) then k1[i] ← 1


Summary: Compares doublewords and stores result in k-register mask.

Compares packed signed 32-bit integers in zmm2 against zmm3/m512 using the comparison predicate in imm8, storing boolean results in opmask k1 (optionally merged with k2). Operates on 16 doubleword elements in 512-bit vectors without affecting EFLAGS; the imm8 predicate determines comparison semantics (EQ, LT, LE, NEQ, NLT, NLE, etc.). Available in 64-bit mode with AVX-512F extension.

for i in 0..15:
  elem1 ← zmm2[32*i : 32*i+31] as signed 32-bit
  elem2 ← zmm3/m512[32*i : 32*i+31] as signed 32-bit
  k1[i] ← (mask_merge) ? k2[i] : 0
  if pred(elem1, elem2, imm8) then k1[i] ← 1


Summary: Compares quadwords and stores result in k-register mask.

Compares packed signed 64-bit integers in zmm2 against zmm3/m512 using the comparison predicate in imm8, storing boolean results in opmask k1 (optionally merged with k2). Operates on 8 quadword elements in 512-bit vectors without modifying EFLAGS; the imm8 predicate encodes the comparison condition (equal, less-than, less-than-or-equal, etc.). Available in 64-bit mode with AVX-512F extension.

for i in 0..7:
  elem1 ← zmm2[64*i : 64*i+63] as signed 64-bit
  elem2 ← zmm3/m512[64*i : 64*i+63] as signed 64-bit
  k1[i] ← (mask_merge) ? k2[i] : 0
  if pred(elem1, elem2, imm8) then k1[i] ← 1


Summary: Compares unsigned bytes and stores result in k-register.

Compares packed unsigned 8-bit integers in zmm2 against zmm3/m512 using the comparison predicate in imm8, storing boolean results in opmask k1 (optionally merged with k2). Operates on 64 byte elements in 512-bit vectors; comparison is performed as unsigned and imm8 specifies the predicate (equal, less, less-equal, etc.). Available in 64-bit mode with AVX-512BW extension; EFLAGS are not modified.

for i in 0..63:
  elem1 ← zmm2[8*i : 8*i+7] as unsigned 8-bit
  elem2 ← zmm3/m512[8*i : 8*i+7] as unsigned 8-bit
  k1[i] ← (mask_merge) ? k2[i] : 0
  if pred(elem1, elem2, imm8) then k1[i] ← 1


Summary: Compares unsigned words and stores result in k-register.

Compares packed unsigned 16-bit integers in zmm2 against zmm3/m512 using the comparison predicate in imm8, storing boolean results in opmask k1 (optionally merged with k2). Operates on 32 word elements in 512-bit vectors; comparison is performed as unsigned and imm8 encodes the predicate type (equal, less, less-equal, not-equal, etc.). Available in 64-bit mode with AVX-512BW extension; EFLAGS remain unaffected.

for i in 0..31:
  elem1 ← zmm2[16*i : 16*i+15] as unsigned 16-bit
  elem2 ← zmm3/m512[16*i : 16*i+15] as unsigned 16-bit
  k1[i] ← (mask_merge) ? k2[i] : 0
  if pred(elem1, elem2, imm8) then k1[i] ← 1


Compare Packed Unsigned Doubleword Integers

Summary: Compares unsigned doublewords and stores result in k-register.

Compares packed unsigned 32-bit integers in zmm2 against zmm3/m512 using the comparison predicate in imm8, storing boolean results in opmask k1 (optionally merged with k2). Operates on 16 doubleword elements in 512-bit vectors; all comparisons are unsigned and imm8 specifies the predicate (equal, less, less-equal, not-equal, etc.). Available in 64-bit mode with AVX-512F extension; EFLAGS are not modified.

for i in 0..15:
  elem1 ← zmm2[32*i : 32*i+31] as unsigned 32-bit
  elem2 ← zmm3/m512[32*i : 32*i+31] as unsigned 32-bit
  k1[i] ← (mask_merge) ? k2[i] : 0
  if pred(elem1, elem2, imm8) then k1[i] ← 1


Compare Packed Unsigned Quadword Integers

Summary: Compares unsigned quadwords and stores result in k-register.

Compares packed unsigned 64-bit integers in zmm2 against zmm3/m512 using the comparison predicate in imm8, storing boolean results in opmask k1 (optionally merged with k2). Operates on 8 quadword elements in 512-bit vectors; all comparisons are unsigned and imm8 encodes the predicate (equal, less-than, less-equal, not-equal, etc.). Available in 64-bit mode with AVX-512F extension; EFLAGS remain unchanged.

for i in 0..7:
  elem1 ← zmm2[64*i : 64*i+63] as unsigned 64-bit
  elem2 ← zmm3/m512[64*i : 64*i+63] as unsigned 64-bit
  k1[i] ← (mask_merge) ? k2[i] : 0
  if pred(elem1, elem2, imm8) then k1[i] ← 1


Summary: Tests byte integers and sets k-register mask.

Tests packed 8-bit integers by performing a bitwise AND of zmm2 and zmm3/m512, setting each bit in opmask k1 if the result is nonzero (optionally merged with k2). Operates on 64 byte elements in 512-bit vectors and does not modify EFLAGS; this is a destructive AND-test operation that sets mask bits based on non-zero results. Available in 64-bit mode with AVX-512BW extension.

for i in 0..63:
  elem1 ← zmm2[8*i : 8*i+7]
  elem2 ← zmm3/m512[8*i : 8*i+7]
  k1[i] ← (mask_merge) ? k2[i] : 0
  if (elem1 & elem2) != 0 then k1[i] ← 1


Summary: Tests word integers and sets k-register mask.

Tests packed word integers by performing a bitwise AND between two 512-bit ZMM sources and sets the result bits in the destination k-register mask. Each bit in the k-register corresponds to whether the AND result for that word element is nonzero. No arithmetic flags (OF, SF, ZF, AF, CF, PF) are modified; only the k-register mask is updated. This is an AVX-512BW instruction that operates on 16-bit elements.


Summary: Tests doubleword integers and sets k-register mask.

Tests packed doubleword integers by performing a bitwise AND between two 512-bit ZMM sources and sets the result bits in the destination k-register mask. Each bit in the k-register corresponds to whether the AND result for that doubleword element is nonzero. No arithmetic flags (OF, SF, ZF, AF, CF, PF) are modified; only the k-register mask is updated. This is an AVX-512F instruction that operates on 32-bit elements.


Summary: Tests quadword integers and sets k-register mask.

Tests packed quadword integers by performing a bitwise AND between two 512-bit ZMM sources and sets the result bits in the destination k-register mask. Each bit in the k-register corresponds to whether the AND result for that quadword element is nonzero. No arithmetic flags (OF, SF, ZF, AF, CF, PF) are modified; only the k-register mask is updated. This is an AVX-512F instruction that operates on 64-bit elements.


Summary: Sets up a monitor address (AMD extension).

Sets up a monitor address and optional extensions for memory monitoring (AMD-specific extension). The instruction uses the address in EAX (or RAX in 64-bit mode) as the monitor target, with optional parameters in ECX (monitor extensions/timeout) and EDX (optional threshold). This instruction primes the CPU's monitoring hardware for use with MWAITX and does not modify any arithmetic flags. MONITORX is a privileged instruction available on AMD Zen and later processors.

monitor_address ← EAX
monitor_extensions ← ECX
monitor_threshold ← EDX


Summary: Waits for a write to monitored address (AMD extension).

Waits for a write to the address set by MONITORX, with optional timeout support (AMD-specific extension). The instruction operates with implicit operands: EAX contains the monitor address, ECX contains extensions/flags, and EDX contains a timeout value in clock cycles (if ECX[1] is set for timeout mode). The instruction is interruptible and will exit on an interrupt, cache line write to the monitored address, or timeout expiration. No arithmetic flags are modified; this is a privileged instruction available on AMD Zen and later processors.

while (memory[monitor_address] has not been written) {
  if (ECX[1] == 1 && timeout_expired(EDX)) break
  if (interrupt_pending()) break
  wait()
}


Summary: Subtracts the low single-precision floating-point value.

Subtracts the low 32-bit single-precision floating-point value in the source from the destination XMM register, following IEEE 754 semantics. The high 96 bits of the destination XMM register are left unchanged. The result may raise floating-point exceptions (invalid operation, overflow, underflow, inexact) but does not modify the general-purpose arithmetic flags (OF, SF, ZF, AF, CF, PF). This is an SSE instruction available in 32-bit and 64-bit modes.

xmm1[31:0] ← xmm1[31:0] - src[31:0] (IEEE 754 single-precision)
xmm1[127:32] ← unchanged
FP_exceptions may be raised


Summary: Subtracts the low double-precision floating-point value.

Subtracts the low 64-bit double-precision floating-point value in the source from the destination XMM register, following IEEE 754 semantics. The high 64 bits of the destination XMM register are left unchanged. The result may raise floating-point exceptions (invalid operation, overflow, underflow, inexact) but does not modify the general-purpose arithmetic flags (OF, SF, ZF, AF, CF, PF). This is an SSE2 instruction available in 32-bit and 64-bit modes.

xmm1[63:0] ← xmm1[63:0] - src[63:0] (IEEE 754 double-precision)
xmm1[127:64] ← unchanged
FP_exceptions may be raised


Summary: Multiplies the low single-precision floating-point value.

Multiplies the low 32-bit single-precision floating-point value in the source by the destination XMM register, following IEEE 754 semantics. The high 96 bits of the destination XMM register are left unchanged. The result may raise floating-point exceptions (invalid operation, overflow, underflow, inexact) but does not modify the general-purpose arithmetic flags (OF, SF, ZF, AF, CF, PF). This is an SSE instruction available in 32-bit and 64-bit modes.

xmm1[31:0] ← xmm1[31:0] * src[31:0] (IEEE 754 single-precision)
xmm1[127:32] ← unchanged
FP_exceptions may be raised


Summary: Multiplies the low double-precision floating-point value.

Multiplies the low 64-bit double-precision floating-point value in xmm1 by the low 64-bit value from xmm2/m64, storing the result in xmm1; the high 64-bit value in xmm1 is preserved. This operation follows IEEE 754 semantics for floating-point multiplication and does not modify EFLAGS.


Summary: Divides the low single-precision floating-point value.

Divides the low 32-bit single-precision floating-point value in xmm1 by the low 32-bit value from xmm2/m32, storing the result in xmm1; the upper 96 bits of xmm1 are preserved. This operation follows IEEE 754 semantics and does not modify EFLAGS; division by zero produces infinity or NaN per IEEE rules.


Summary: Divides the low double-precision floating-point value.

Divides the low 64-bit double-precision floating-point value in xmm1 by the low 64-bit value from xmm2/m64, storing the result in xmm1; the high 64-bit value in xmm1 is preserved. This operation follows IEEE 754 semantics and does not modify EFLAGS; division by zero produces infinity or NaN per IEEE rules.


Summary: Computes square root of the low float.

Computes the square root of the low 32-bit single-precision floating-point value in xmm2/m32 and stores the result in the low 32 bits of xmm1; the upper 96 bits of xmm1 are set to zero. This operation follows IEEE 754 semantics and does not modify EFLAGS; negative operands produce NaN.


Summary: Computes square root of the low double.

Computes the square root of the low 64-bit double-precision floating-point value in xmm2/m64 and stores the result in the low 64 bits of xmm1; the high 64 bits of xmm1 are set to zero. This operation follows IEEE 754 semantics and does not modify EFLAGS; negative operands produce NaN.


Summary: Returns the minimum of two low single-precision values.

Returns the minimum of the low 32-bit single-precision floating-point values from xmm1 and xmm2/m32, storing the result in xmm1; the upper 96 bits of xmm1 are preserved. Comparison follows IEEE 754 rules where NaN comparisons return NaN and negative zero is less than positive zero; EFLAGS are not modified.


Summary: Returns the minimum of two low double-precision values.

Returns the minimum of the low 64-bit double-precision floating-point values from xmm1 and xmm2/m64, storing the result in xmm1; the high 64 bits of xmm1 are preserved. Comparison follows IEEE 754 rules where NaN comparisons return NaN and negative zero is less than positive zero; EFLAGS are not modified.


Summary: Returns the maximum of two low single-precision values.

Returns the maximum of the low 32-bit single-precision floating-point values from xmm1 and xmm2/m32, storing the result in xmm1; the upper 96 bits of xmm1 are preserved. Comparison follows IEEE 754 rules where NaN comparisons return NaN and positive zero is greater than negative zero; EFLAGS are not modified.


Summary: Returns the maximum of two low double-precision values.

Compares the low 64-bit double-precision floating-point values in the destination and source operands, returns the maximum value, and stores it in the low 64 bits of the destination XMM register while leaving the high 64 bits unchanged. No CPU flags are affected. This instruction operates only on the scalar (low) element; the upper 64 bits of xmm1 are preserved.


Summary: Compares low single-precision values and returns mask.

Performs a scalar single-precision floating-point comparison between the low 32-bit elements of xmm1 and xmm2/m32 according to the condition specified by the immediate byte, storing a mask (all 1s or all 0s) in the low 32 bits of xmm1 while the upper 96 bits are preserved. No CPU flags are modified. The comparison predicate is encoded in imm8[2:0].

condition ← imm8[2:0]; result ← compare(xmm1[0:31], src[0:31], condition); xmm1[0:31] ← result ? 0xFFFFFFFF : 0; xmm1[32:127] ← xmm1[32:127];


Summary: Compares low double-precision values and returns mask.

Performs a scalar double-precision floating-point comparison between the low 64-bit elements of xmm1 and xmm2/m64 according to the condition specified by the immediate byte, storing a mask (all 1s or all 0s) in the low 64 bits of xmm1 while the upper 64 bits are preserved. No CPU flags are modified. The comparison predicate is encoded in imm8[2:0].

condition ← imm8[2:0]; result ← compare(xmm1[0:63], src[0:63], condition); xmm1[0:63] ← result ? 0xFFFFFFFFFFFFFFFF : 0; xmm1[64:127] ← xmm1[64:127];


Summary: Computes approximate reciprocal (1/x) of low float.

Computes an approximate reciprocal (1/x) of the low 32-bit single-precision floating-point value in the source operand and stores the result in the low 32 bits of the destination XMM register, while preserving the upper 96 bits of xmm1. No CPU flags are affected. The result has a maximum relative error of approximately 1.5×2^-12.


Reciprocal Square Root Scalar Single-Precision

Summary: Computes approximate reciprocal sqrt (1/sqrt(x)) of low float.

Computes an approximate reciprocal square root (1/√x) of the low 32-bit single-precision floating-point value in the source operand and stores the result in the low 32 bits of the destination XMM register, while preserving the upper 96 bits of xmm1. No CPU flags are affected. The result has a maximum relative error of approximately 1.5×2^-12.


Summary: Rounds low float according to immediate mode.

Rounds the low 32-bit single-precision floating-point value in xmm2/m32 according to the rounding mode specified in imm8 and stores the rounded result in the low 32 bits of xmm1, while preserving the upper 96 bits of xmm1. No CPU flags are affected. Rounding mode is selected via imm8[1:0]; bit 2 can suppress inexact exceptions.

mode ← imm8[1:0]; precision_exception_suppress ← imm8[2]; xmm1[0:31] ← round(src[0:31], mode, precision_exception_suppress); xmm1[32:127] ← xmm1[32:127];


Summary: Rounds low double according to immediate mode.

Rounds the low 64-bit double-precision floating-point value in xmm2/m64 according to the rounding mode specified in imm8 and stores the rounded result in the low 64 bits of xmm1, while preserving the upper 64 bits of xmm1. No CPU flags are affected. Rounding mode is selected via imm8[1:0]; bit 2 can suppress inexact exceptions.

mode ← imm8[1:0]; precision_exception_suppress ← imm8[2]; xmm1[0:63] ← round(src[0:63], mode, precision_exception_suppress); xmm1[64:127] ← xmm1[64:127];


Convert with Truncation Packed Single to Packed Integer (MMX)

Summary: Converts packed floats to packed MMX integers (Truncate).

Converts the two low single-precision floating-point values (32 bits each) from an XMM register or 64-bit memory location to two packed 32-bit signed integers via truncation, storing the result in an MMX register. The upper two single-precision values in the XMM operand are ignored. No CPU flags are affected; the instruction operates on the MMX register state.


Summary: Converts lower two floats to doubles.

Converts the lower two packed single-precision floats (32-bit) to two packed double-precision floats (64-bit), storing the result in the destination XMM register. The conversion rounds according to the MXCSR rounding mode; #IA (invalid operation) and #D (denormal) exceptions may be signaled. No flags are affected.

dest[0:63] ← convert_sp_to_dp(src[0:31]);
dest[64:127] ← convert_sp_to_dp(src[32:63]);


Summary: Converts two doubles to two floats.

Converts two packed double-precision floats (64-bit each) to two packed single-precision floats (32-bit each), storing the result in the lower 64 bits of the destination XMM register and zeroing the upper 64 bits. The conversion rounds according to the MXCSR rounding mode; #IA and #O (overflow) exceptions may be signaled. No flags are affected.


Summary: Jump near if overflow flag is 1.

Performs a near jump to the target address if the overflow flag (OF) is set (1). The jump is relative to the instruction pointer; this is a conditional branch with no effect on CPU flags. Available in all modes (real, protected, 64-bit).

if (OF == 1) {
  RIP ← RIP + sign_extend(rel8_or_rel32);
}


Summary: Jump near if overflow flag is 0.

Performs a near jump to the target address if the overflow flag (OF) is clear (0). The jump is relative to the instruction pointer; this is a conditional branch with no effect on CPU flags. Available in all modes (real, protected, 64-bit).

if (OF == 0) {
  RIP ← RIP + sign_extend(rel8_or_rel32);
}


Summary: Jump near if sign flag is 1 (Negative).

Performs a near jump to the target address if the sign flag (SF) is set (1), indicating a negative result from a prior arithmetic operation. The jump is relative to the instruction pointer; this is a conditional branch with no effect on CPU flags. Available in all modes (real, protected, 64-bit).

if (SF == 1) {
  RIP ← RIP + sign_extend(rel8_or_rel32);
}


Summary: Jump near if sign flag is 0 (Positive).

Performs a near jump to the target address if the sign flag (SF) is clear (0), indicating a non-negative result from a prior arithmetic operation. The jump is relative to the instruction pointer; this is a conditional branch with no effect on CPU flags. Available in all modes (real, protected, 64-bit).

if (SF == 0) {
  RIP ← RIP + sign_extend(rel8_or_rel32);
}


Summary: Jump near if parity flag is 1 (Even parity).

Performs a near jump to the target address if the parity flag (PF) is set (1), indicating even parity in the low-order byte of a prior operation result. The jump is relative to the instruction pointer; this is a conditional branch with no effect on CPU flags. Available in all modes (real, protected, 64-bit).

if (PF == 1) {
  RIP ← RIP + sign_extend(rel8_or_rel32);
}


Summary: Jump near if parity flag is 0 (Odd parity).

Performs a near jump to the target address if the parity flag (PF) is clear (0), indicating odd parity in the low-order byte of a prior operation result. The jump is relative to the instruction pointer; this is a conditional branch with no effect on CPU flags. Available in all modes (real, protected, 64-bit).

if (PF == 0) {
  RIP ← RIP + sign_extend(rel8_or_rel32);
}


Summary: Sets byte to 1 if OF=1.

Sets the destination byte to 1 if the Overflow Flag (OF) is set, otherwise sets it to 0. This instruction does not modify any flags. Available in 32-bit and 64-bit modes; commonly used after arithmetic operations to test for signed overflow.


Summary: Sets byte to 1 if OF=0.

Sets the destination byte to 1 if the Overflow Flag (OF) is clear, otherwise sets it to 0. This instruction does not modify any flags. Available in 32-bit and 64-bit modes; used to test when no signed overflow has occurred.


Summary: Sets byte to 1 if ZF=1.

Sets the destination byte to 1 if the Zero Flag (ZF) is set, otherwise sets it to 0. This instruction does not modify any flags. Available in 32-bit and 64-bit modes; commonly used after comparisons or arithmetic to test if the result was zero.


Summary: Sets byte to 1 if ZF=0.

Sets the destination byte to 1 if the Zero Flag (ZF) is clear, otherwise sets it to 0. This instruction does not modify any flags. Available in 32-bit and 64-bit modes; commonly used after comparisons or arithmetic to test if the result was non-zero.


Summary: Move if ZF=0 and SF=OF.

Conditionally moves the source operand to the destination register if the signed greater-than condition is true (ZF=0 and SF=OF). No flags are modified by this instruction. The operand size can be 16, 32, or 64 bits (determined by REX.W and operand-size prefix). Requires the CMOV extension; available in 32-bit and 64-bit modes.


Summary: Move if SF=OF.

Conditionally moves the source operand to the destination register if the signed greater-than-or-equal condition is true (SF=OF). No flags are modified by this instruction. The operand size can be 16, 32, or 64 bits (determined by REX.W and operand-size prefix). Requires the CMOV extension; available in 32-bit and 64-bit modes.


Summary: Move if SF!=OF.

Conditionally moves the source operand to the destination register if the signed less-than condition is true (SF≠OF). No flags are modified by this instruction. The operand size can be 16, 32, or 64 bits (determined by REX.W and operand-size prefix). Requires the CMOV extension; available in 32-bit and 64-bit modes.


Summary: Move if ZF=1 or SF!=OF.

Conditionally moves the source operand to the destination register if the signed less-than-or-equal condition is true (ZF=1 or SF≠OF). No flags are modified by this instruction. The operand size can be 16, 32, or 64 bits (determined by REX.W and operand-size prefix). Requires the CMOV extension; available in 32-bit and 64-bit modes.


Summary: Move if ZF=1.

Conditionally moves the source operand to the destination register if the Zero Flag (ZF) is set to 1, otherwise the destination register remains unchanged. This instruction operates on 16/32/64-bit operands and does not modify any CPU flags. It is available in protected mode and 64-bit mode on processors supporting the CMOV extension.


Summary: Move if ZF=0.

Conditionally moves the source operand to the destination register if the Zero Flag (ZF) is cleared to 0 (i.e., result was non-zero), otherwise the destination register remains unchanged. This instruction operates on 16/32/64-bit operands and does not modify any CPU flags. It is available in protected mode and 64-bit mode on processors supporting the CMOV extension.


Summary: Adds 16-bit words with unsigned saturation.

Adds eight pairs of 16-bit unsigned integers in parallel from the destination and source operands, with unsigned saturation applied to each pair independently. The result is stored in the destination XMM register; overflow is clamped to 0xFFFF and does not set CPU flags. Available in SSE2 and later extensions.

for (i = 0; i < 8; i++) { result[i] = UNSIGNED_SAT_16(dest[i] + src[i]); } dest ← result;


Summary: Adds 16-bit words with signed saturation.

Adds eight pairs of 16-bit signed integers in parallel from the destination and source operands, with signed saturation applied to each pair independently. The result is stored in the destination XMM register; overflow is clamped to 0x7FFF and underflow to 0x8000, and no CPU flags are modified. Available in SSE2 and later extensions.

for (i = 0; i < 8; i++) { result[i] = SIGNED_SAT_16(dest[i] + src[i]); } dest ← result;


Packed Subtract Unsigned Saturation Word

Summary: Subtracts 16-bit words with unsigned saturation.

Subtracts eight pairs of 16-bit unsigned integers in parallel; the source is subtracted from the destination with unsigned saturation applied to each pair independently. The result is stored in the destination XMM register; underflow is clamped to 0x0000 and does not set CPU flags. Available in SSE2 and later extensions.

for (i = 0; i < 8; i++) { result[i] = UNSIGNED_SAT_16(dest[i] - src[i]); } dest ← result;


Summary: Subtracts 16-bit words with signed saturation.

Subtracts eight pairs of 16-bit signed integers in parallel; the source is subtracted from the destination with signed saturation applied to each pair independently. The result is stored in the destination XMM register; overflow is clamped to 0x7FFF and underflow to 0x8000, and no CPU flags are modified. Available in SSE2 and later extensions.

for (i = 0; i < 8; i++) { result[i] = SIGNED_SAT_16(dest[i] - src[i]); } dest ← result;


Summary: Multiplies 16-bit words and stores low 16-bit result.

Multiplies eight pairs of 16-bit signed integers from the destination and source operands in parallel; the low 16 bits of each 32-bit product are stored in the destination XMM register while the high 16 bits are discarded. No CPU flags are modified, and this instruction does not generate saturation. Available in SSE2 and later extensions.

for (i = 0; i < 8; i++) { product = (int32_t)dest[i] * (int32_t)src[i]; result[i] = (int16_t)(product & 0xFFFF); } dest ← result;


Packed Multiply and Add Word to Doubleword

Summary: Multiplies words, adds adjacent pairs to doublewords.

Multiplies four pairs of 16-bit signed integers from the destination and source operands in parallel; adjacent pairs of 32-bit products are then summed with signed saturation, and the four 32-bit saturated results are stored in the destination XMM register. No CPU flags are modified. Available in SSE2 and later extensions.

for (i = 0; i < 4; i++) { prod0 = (int32_t)dest[2*i] * (int32_t)src[2*i]; prod1 = (int32_t)dest[2*i+1] * (int32_t)src[2*i+1]; result[i] = SIGNED_SAT_32(prod0 + prod1); } dest ← result;


Summary: Compares bytes for greater than (signed).

Compares packed signed bytes in xmm1 against xmm2/m128, setting each byte in xmm1 to 0xFF if the comparison is true or 0x00 if false. This is a SIMD integer comparison with no CPU flags affected; the result mask is stored directly in the destination XMM register.

for i = 0 to 15:
  if xmm1[byte_i] > xmm2/m128[byte_i] (signed):
    xmm1[byte_i] ← 0xFF
  else:
    xmm1[byte_i] ← 0x00


Summary: Compares words for greater than (signed).

Compares packed signed words in xmm1 against xmm2/m128, setting each word in xmm1 to 0xFFFF if the comparison is true or 0x0000 if false. This is a SIMD integer comparison with no CPU flags affected; the result mask is stored directly in the destination XMM register.

for i = 0 to 7:
  if xmm1[word_i] > xmm2/m128[word_i] (signed):
    xmm1[word_i] ← 0xFFFF
  else:
    xmm1[word_i] ← 0x0000


Summary: Compares doublewords for greater than (signed).

Compares packed signed doublewords in xmm1 against xmm2/m128, setting each doubleword in xmm1 to 0xFFFFFFFF if the comparison is true or 0x00000000 if false. This is a SIMD integer comparison with no CPU flags affected; the result mask is stored directly in the destination XMM register.

for i = 0 to 3:
  if xmm1[dword_i] > xmm2/m128[dword_i] (signed):
    xmm1[dword_i] ← 0xFFFFFFFF
  else:
    xmm1[dword_i] ← 0x00000000


Summary: Inserts a word from integer register into XMM.

Inserts a 16-bit word from a general-purpose register or memory into an XMM register at the position specified by an 8-bit index. The low 16 bits of the source are extracted; other bits in the destination XMM register remain unchanged. No CPU flags are affected.

index ← imm8 & 0x7
word_value ← (r32/m16) & 0xFFFF
xmm1[word_index * 16 : word_index * 16 + 15] ← word_value


Summary: Extracts a word from XMM to integer register.

Extracts a 16-bit word from an XMM register at the position specified by an 8-bit index and zero-extends it into a 32-bit general-purpose register. The upper 16 bits of the destination register are zeroed. No CPU flags are affected.

index ← imm8 & 0x7
word_value ← xmm1[word_index * 16 : word_index * 16 + 15]
r32 ← zero_extend(word_value, 32)


Summary: Shuffles the low 4 words of XMM.

Shuffles the low 4 words of an XMM register using an 8-bit immediate that specifies the source indices for each destination word; the high 4 words are unchanged. This is a data permutation with no CPU flags affected.

order ← imm8
for i = 0 to 3:
  src_index ← (order >> (i * 2)) & 0x3
  xmm1[word_i] ← (xmm2/m128)[word_src_index]
for i = 4 to 7:
  xmm1[word_i] ← (xmm2/m128)[word_i]


Summary: Shuffles the high 4 words of XMM.

Shuffles the high 4 words of an XMM register using an 8-bit immediate that specifies the source indices for each destination word; the low 4 words are unchanged. This is a data permutation with no CPU flags affected.

order ← imm8
for i = 0 to 3:
  xmm1[word_i] ← (xmm2/m128)[word_i]
for i = 4 to 7:
  src_index ← (order >> ((i - 4) * 2)) & 0x3
  xmm1[word_i] ← (xmm2/m128)[word_(4 + src_index)]


Summary: Stores 64-bit MMX data bypassing cache.

Stores a 64-bit quadword from an MMX register directly to memory, bypassing the L1 and L2 caches (non-temporal hint). This instruction provides a memory-ordering serialization point and can improve performance for streaming writes that do not benefit from caching. No CPU flags are affected.


Summary: Stores integer register to memory bypassing cache.

Stores a 32-bit or 64-bit general-purpose register to memory while bypassing the L1 and L2 caches, using a non-temporal hint to the memory subsystem. This instruction is useful for streaming writes that are unlikely to be reused soon. No flags are affected; the instruction may serialize the store buffer but does not guarantee memory ordering with respect to other instructions.


Summary: Atomically compares 128-bit memory with RDX:RAX.

Atomically compares a 128-bit memory operand with the implicit 128-bit value in RDX:RAX; if they match, writes RCX:RBX to memory and sets ZF to 1; otherwise, loads the memory value into RDX:RAX and clears ZF. This instruction requires 16-byte alignment and is only available in 64-bit mode; it serializes the memory bus and guarantees atomic execution.

if ([dest] == (RDX:RAX)) {
  [dest] ← (RCX:RBX);
  ZF ← 1;
} else {
  (RDX:RAX) ← [dest];
  ZF ← 0;
}


Summary: Moves data swapping bytes (Big Endian load/store).

Loads data from memory or register and reverses the byte order (big-endian conversion) while storing to the destination register or memory. Supports 16-bit, 32-bit, and 64-bit operands; no flags are affected. Available on processors with the MOVBE extension; useful for endianness conversion in multi-byte data transfers.

if (dest is register) {
  dest ← byte_reverse(src);
} else {
  [dest] ← byte_reverse(src);
}


Summary: Blends doubles based on variable mask in XMM0.

Implicit XMM0 register (blend control mask)

Blends two packed double-precision floating-point values in XMM registers or memory based on per-lane sign bits of an implicit mask in XMM0; for each 64-bit lane, if the sign bit is 1, the value from the second source is selected, otherwise from the first source. Part of SSE4.1; no flags are affected. The result is stored in the first source operand (xmm1).

for i = 0 to 1 {
  if (XMM0.qword[i] < 0) {
    xmm1.double[i] ← src1.double[i];
  } else {
    xmm1.double[i] ← xmm1.double[i];
  }
}


Summary: Blends floats based on variable mask in XMM0.

Blends two packed single-precision floating-point values in XMM registers or memory based on per-lane sign bits of an implicit mask in XMM0; for each 32-bit lane, if the sign bit is 1, the value from the second source is selected, otherwise from the first source. Part of SSE4.1; no flags are affected. The result is stored in the first source operand (xmm1).

for i = 0 to 3 {
  if (XMM0.dword[i] < 0) {
    xmm1.float[i] ← src1.float[i];
  } else {
    xmm1.float[i] ← xmm1.float[i];
  }
}


Summary: Blends bytes based on variable mask in XMM0.

Blends two packed byte values in XMM registers or memory based on per-byte sign bits of an implicit mask in XMM0; for each byte, if the sign bit is 1, the value from the second source is selected, otherwise from the first source. Part of SSE4.1; no flags are affected. The result is stored in the first source operand (xmm1).

for i = 0 to 15 {
  if (XMM0.byte[i] < 0) {
    xmm1.byte[i] ← src1.byte[i];
  } else {
    xmm1.byte[i] ← xmm1.byte[i];
  }
}


Summary: Switch to guest VM (AMD SVM).

Switches execution from host to guest virtual machine context by loading guest state from the VMCB (Virtual Machine Control Block) addressed by RAX; serializes the processor and triggers a full context switch including segment registers, control registers, and TLB state. Available only in 64-bit mode with AMD SVM (Secure Virtual Machine) enabled and appropriate privilege level; no flags are affected from the host perspective as execution transfers to guest.

VMCB_addr ← RAX;
load_guest_state(VMCB_addr);
execute_guest();


Summary: Loads processor state from VMCB (AMD SVM).

Loads processor state (segments, control registers, debug registers, and other hidden state) from the VMCB (Virtual Machine Control Block) referenced by RAX without switching to guest mode execution. Part of AMD SVM; requires 64-bit mode and appropriate privilege level; no flags are affected. This instruction is typically used in host or nested virtualization contexts to synchronize host state.

VMCB_addr ← RAX;
load_state_from_VMCB(VMCB_addr);


Summary: Saves processor state to VMCB (AMD SVM).

Saves the current processor state to the VMCB (Virtual Machine Control Block) at the address specified in RAX. This is a privileged SVM instruction that serializes the processor and must execute at privilege level 0. The instruction writes guest state registers and internal processor state to memory; it does not modify flags.

[RAX + offset] ← processor_state; // VMCB state save


Summary: Disables global interrupts (AMD SVM).

Clears the Global Interrupt Flag (GIF) in the VMCB, which disables interrupts and exceptions at the SVM guest level. This is a privileged instruction that requires CPL=0 and SVM capability. It does not modify EFLAGS but affects the processor's ability to accept external interrupts.

GIF ← 0; // Global interrupt flag disabled


Summary: Enables global interrupts (AMD SVM).

Sets the Global Interrupt Flag (GIF) in the VMCB, enabling interrupts and exceptions at the SVM guest level. This is a privileged instruction requiring CPL=0 and SVM capability. After execution, the processor will accept maskable interrupts; no EFLAGS are modified.

GIF ← 1; // Global interrupt flag enabled


Summary: Invalidates TLB entry for specific ASID (AMD SVM).

Invalidates TLB entries for a linear address using the ASID (Address Space Identifier) specified in ECX, applicable only within the current VMCB context. This is a privileged SVM instruction that selectively flushes TLB entries without serializing the entire pipeline. The linear address is implicitly taken from RAX.

TLB_entry ← invalidate(RAX, ECX); // Invalidate TLB with ASID


Summary: Adds two packed floats (3DNow!).

Adds two packed single-precision floating-point values (two 32-bit floats per 64-bit operand) using 3DNow! arithmetic. The result is written to the destination MMX register with round-to-nearest mode. This instruction does not modify EFLAGS; floating-point exceptions may be masked or pending.


Summary: Subtracts packed floats (3DNow!).

Subtracts two packed single-precision floating-point values (two 32-bit floats per 64-bit operand) using 3DNow! arithmetic. The result is written to the destination MMX register. This instruction does not modify EFLAGS; floating-point exceptions may be masked or pending.


Summary: Multiplies packed floats (3DNow!).

Multiplies two packed single-precision floating-point values (two 32-bit floats per 64-bit operand) using 3DNow! arithmetic. The result is written to the destination MMX register. This instruction does not modify EFLAGS; floating-point exceptions may be masked or pending.


Summary: Approximates reciprocal (3DNow!).

Computes a fast approximation of the reciprocal (1/x) for each packed single-precision floating-point value using 3DNow!. The result is written to the destination MMX register with reduced precision (typically 14-15 bits of accuracy). This instruction does not modify EFLAGS; it may generate floating-point exceptions.

dest[31:0] ← float_reciprocal_approx(src[31:0]); dest[63:32] ← float_reciprocal_approx(src[63:32]);


Packed Floating-Point Reciprocal Square Root

Summary: Approximates reciprocal sqrt (3DNow!).

Computes a fast approximation of the reciprocal square root (1/√x) for two packed single-precision floating-point values in parallel. This is a 3DNow! extension instruction that performs low-precision approximation suitable for iterative refinement; the approximation has limited accuracy (typically ~11-12 bits). No EFLAGS are modified.

dest[0:31] ← approx_rsqrt(src[0:31]);
dest[32:63] ← approx_rsqrt(src[32:63]);


Summary: Adds low FP16 value.

Adds the low-order half-precision (FP16) element from two XMM registers and stores the scalar result in the low 16 bits of the destination, with upper 112 bits cleared or preserved based on write-mask. Uses EVEX encoding with optional masking and suppression of exceptions. Rounding mode is determined by MXCSR[15:13].


Summary: Subtracts low FP16 value.

Subtracts the low-order half-precision (FP16) element of the second operand from the first and stores the scalar result in the low 16 bits of the destination, with upper 112 bits cleared or preserved based on write-mask. Uses EVEX encoding with optional masking and exception suppression. Rounding controlled by MXCSR[15:13].


Summary: Multiplies low FP16 value.

Multiplies the low-order half-precision (FP16) element from two operands and stores the scalar result in the low 16 bits of the destination, with upper 112 bits cleared or preserved based on write-mask. Uses EVEX encoding with optional masking and exception control. Rounding mode determined by MXCSR[15:13].


Summary: Divides low FP16 value.

Divides the low-order half-precision (FP16) element of the first operand by the second and stores the scalar result in the low 16 bits of the destination, with upper 112 bits cleared or preserved based on write-mask. Uses EVEX encoding with optional masking and exception suppression. Rounding controlled by MXCSR[15:13]; may generate precision/underflow/overflow exceptions.


Summary: Square root of low FP16 value.

Computes the square root of the low-order half-precision (FP16) element and stores the scalar result in the low 16 bits of the destination, with upper 112 bits cleared or preserved based on write-mask. Uses EVEX encoding with optional masking and exception suppression. Rounding mode determined by MXCSR[15:13].

if (k1[0] || !masking_enabled) {
  dest[0:15] ← sqrt_FP16(src[0:15]);
} else {
  dest[0:15] ← preserve_or_zero(dest[0:15]);
}
dest[16:127] ← 0;


Fused Multiply-Add Scalar Half-Precision (132)

Summary: Scalar FMA (Dest * Src2 + Src1) for FP16.

Performs fused multiply-add on scalar half-precision (FP16) values: multiplies the destination by src2, adds src1, and stores result in destination. The '132' form computes (dest × src2) + src1. Uses EVEX encoding with optional masking and exception suppression. Single rounding applied to the final result per MXCSR[15:13].


Summary: Multiplies 64-bit integers and keeps low 64-bit result.

Multiplies eight packed 64-bit signed integers and stores the low 64-bit results of each multiplication in eight 64-bit elements of the destination ZMM register. Uses EVEX encoding with optional per-element masking via write-mask register. No overflow flags are set; overflow is silently truncated to 64 bits.


Summary: Computes absolute value of 32-bit integers.

Computes the absolute value of packed 32-bit signed integers in the source operand and stores the results in the destination register. Each 32-bit element is independently processed; if the input is 0x80000000 (minimum signed 32-bit), the result remains 0x80000000 due to two's complement representation. Operates on 512-bit data with EVEX prefix, supporting write-masking via k1.


Summary: Extracts 512-bits from two concatenated ZMMs shifted by count.

VALIGNQ zmm1 {k1}, zmm2, zmm3/m512, imm8

Extracts 512 bits from two concatenated 512-bit quadword vectors, with the extraction window shifted by an immediate count (in quadword units). The operation concatenates src1 and src2, then shifts right by count*64 bits. The lowest 512 bits of the result are stored in dest. Operates under EVEX with write-masking support.

shift_bits = (imm8 & 0x7) * 64
concatenated = (src2 << 512) | src1
shifted = concatenated >> shift_bits
dest = shifted[511:0]


Double Block Packed Sum-Absolute-Differences

Summary: Computes SAD on 16-bit blocks.

VDBPSADBW zmm1 {k1}, zmm2, zmm3/m512, imm8

Computes double-block packed sum-of-absolute-differences on 16-bit blocks between src1 and src2, producing 16-bit results. The operation partitions each 128-bit lane into blocks of 16 bits, computes SAD across specified block boundaries controlled by imm8, and accumulates results into 16-bit fields. Requires AVX-512BW; operates on 512-bit vectors with EVEX masking.

for lane = 0 to 3 {
  for block = 0 to 3 {
    result = 0
    block_offset = (imm8 >> (block*2)) & 0x3
    for j = 0 to 1 {
      idx1 = lane*128 + block*32 + j*16
      idx2 = lane*128 + block_offset*32 + j*16
      result += abs(src1[idx1+15:idx1] - src2[idx2+15:idx2])
    }
    dest[lane*128 + block*16 + 15 : lane*128 + block*16] = result[15:0]
  }
}


Range Restriction Calculation Scalar Single

Summary: Calculates range (min/max/abs) of low float.

VRANGESS xmm1 {k1}, xmm2, xmm3/m32, imm8

Restricts the range of the low single-precision float in xmm2 and the corresponding float from xmm3/m32 according to the range specification in imm8, storing the result in xmm1. The imm8 encodes operations such as minimum, maximum, and absolute value selection. Upper three floats of xmm1 are copied from xmm2 unchanged. Operates in 32-bit scalar mode with EVEX write-masking via k1; requires AVX-512DQ.

range_op = imm8[3:0]
op1_float = xmm2[31:0]
op2_float = xmm3/m32[31:0]
xmm1[31:0] = perform_range_restriction(op1_float, op2_float, range_op)
xmm1[127:32] = xmm2[127:32]


Summary: Fixes special cases (NaN, Inf) in low float using table.

VFIXUPIMMSS xmm1 {k1}, xmm2, xmm3/m32, imm8

Fixes up special floating-point values (NaN, infinity, denormal, sign) in the low single-precision float using a table lookup controlled by imm8. The lookup uses xmm2[31:0] as one input and xmm3/m32[31:0] as reference, producing a corrected value in xmm1[31:0]. Upper three floats in xmm1 are copied from xmm2. Operates under EVEX with write-masking; AVX-512F compliant.

op1 = xmm2[31:0]
op2 = xmm3/m32[31:0]
lookup_index = (sign_of(op1)<<4) | (class_of(op1)<<1) | (class_of(op2))
fixed_value = fixup_table[lookup_index][imm8[7:0]]
xmm1[31:0] = fixed_value
xmm1[127:32] = xmm2[127:32]


Perform Reduction Transformation Scalar Single

Summary: Performs reduction on low float.

VREDUCESS xmm1 {k1}, xmm2, xmm3/m32, imm8

Performs a reduction transformation (rounding, exponent manipulation) on the low single-precision float from xmm2 and xmm3/m32 according to the control specified in imm8, storing the scalar result in xmm1[31:0]. Upper three floats in xmm1 are copied from xmm2. Reduction includes operations like round-to-integral, exponent bias removal, or truncation. Requires AVX-512DQ with EVEX masking.

reduction_op = (imm8[3:0])
signaling_bit = imm8[4]
op1_float = xmm2[31:0]
op2_float = xmm3/m32[31:0]
xmm1[31:0] = perform_reduction(op1_float, op2_float, reduction_op, signaling_bit)
xmm1[127:32] = xmm2[127:32]


Summary: Bitwise AND of 64-bit mask registers.

Performs a bitwise logical AND on two 64-bit mask registers (k2 and k3) and stores the result in the destination mask register (k1). All 64 bits of the mask registers are operated on. This is a low-latency operation with no flag modifications. Requires AVX-512BW for 64-bit mask register support.


Summary: Bitwise OR of 64-bit mask registers.

Performs a bitwise logical OR on two 64-bit mask registers (k2 and k3) and stores the result in the destination mask register (k1). All 64 bits of the mask registers participate in the operation. This is a low-latency mask manipulation instruction with no EFLAGS modification. Requires AVX-512BW for 64-bit mask operations.


Summary: Bitwise NOT of 64-bit mask register.

Performs a bitwise logical NOT operation on a 64-bit AVX-512 opmask register, inverting all bits. The instruction operates only on opmask registers (k0-k7) and does not affect general EFLAGS. This is an AVX-512BW extension instruction with no flag side effects.


Summary: Performs AES InvMixColumns transformation (decryption helper).

Performs the AES InvMixColumns transformation on a 128-bit XMM register, applying the inverse MixColumns step used in AES block cipher decryption. This is a cryptographic acceleration instruction from the AES-NI extension that operates on 128-bit values and produces no flag modifications.


Summary: Non-temporal store of selected MMX bytes.

Conditionally stores selected bytes from a 64-bit MMX register to memory based on byte-granularity mask bits from another MMX register, using the implicit address in EDI (32-bit) or RDI (64-bit). The instruction writes non-temporally where supported and does not affect EFLAGS; it requires real or protected mode for address generation.


Summary: Multiplies 32-bit integers, stores low 32-bit result.

Multiplies four pairs of 32-bit signed integers in parallel, storing the low 32 bits of each product in the destination XMM register. This SSE4.1 instruction operates on 128-bit vectors and does not modify EFLAGS; overflow is silently discarded.


Packed Move with Sign Extend Byte to Word

Summary: Sign extends 8-bit integers to 16-bit.

Sign-extends four 8-bit signed integers from the lower 32 bits of the source to four 16-bit signed integers in the destination XMM register. This SSE4.1 instruction performs element-wise sign extension with no flag side effects; the upper 64 bits of the source are ignored.


Packed Move with Zero Extend Byte to Word

Summary: Zero extends 8-bit integers to 16-bit.

Zero-extends four 8-bit unsigned integers from the lower 32 bits of the source to four 16-bit unsigned integers in the destination XMM register. This SSE4.1 instruction performs element-wise zero extension with no flag modifications; the upper 64 bits of the source are ignored.


Summary: Inserts a byte from integer register into XMM.

Inserts an 8-bit integer value from a general-purpose register or memory into a byte position within the destination XMM register, as specified by an immediate index. This SSE4.1 instruction does not affect EFLAGS; the immediate selects one of 16 byte lanes (0-15) in the 128-bit register.

index ← src2 & 0xF
dest[index*8 : index*8+7] ← src1[0:7]


Summary: Extracts a byte from XMM to integer register.

Extracts an 8-bit byte from a specified position within the source XMM register and stores it into a general-purpose register or memory location. This SSE4.1 instruction does not modify EFLAGS; the immediate selects one of 16 byte lanes (0-15), and destination registers are zero-extended to 32 bits when writing to r32.

index ← src2 & 0xF
dest ← src1[index*8 : index*8+7]