VSX Scalar Convert with round to zero Quad-Precision to Signed Doubleword format X-form

Summary: Converts a quad-precision floating-point value to a signed doubleword integer, rounding towards zero.

Converts a quad-precision floating-point value from the source VSR to a signed 64-bit doubleword integer using round-toward-zero mode and stores the result in the target VSR. Only the scalar element is processed. Invalid conversions saturate to the appropriate signed limit; FPSCR status is updated.

VRT[0:63] ← ConvertToSignedDoubleword_RoundTowardZero(VRB[0:127])
VRT[64:127] ← 0

FPSCR.FPRF, FPSCR.FR, FPSCR.FI, FPSCR.VXSNAN, FPSCR.VXCVI, FPSCR.XX

The xscvqpsdz instruction is used to convert a quad-precision floating-point value to a signed doubleword integer, rounding towards zero. Ensure that the VSX facility is enabled (MSR.VSX=1) before using this instruction; otherwise, it will raise an exception. Be cautious of NaN and infinity values, as they result in specific outputs and set flags indicating exceptions. The instruction handles overflow by saturating to the maximum or minimum signed doubleword value.


VSX Scalar Convert with round to zero Quad-Precision to Signed Quadword

Summary: Converts a quad-precision floating-point value to a signed quadword integer, rounding towards zero.

Converts a quad-precision floating-point value from the source VSR to a signed 128-bit quadword integer using round-toward-zero mode and stores the result in the target VSR. Only the scalar element is processed. Out-of-range conversions saturate; FPSCR status flags are set appropriately.

The xscvqpsqz instruction converts a quad-precision floating-point value to a signed quadword integer, rounding towards zero. It handles NaNs and infinities by setting VXSNAN or VXCVI flags and raising an exception. Ensure the source register contains a valid quad-precision float; otherwise, handle exceptions appropriately.


VSX Scalar Convert with round to zero Quad-Precision to Signed Word format

Summary: Converts a quad-precision floating-point value to a signed word format.

Converts a quad-precision floating-point value from the source VSR to a signed 32-bit word integer using round-toward-zero mode and stores the result in the target VSR. Only the scalar element is processed. Out-of-range values saturate to the limits of signed 32-bit representation; FPSCR is updated.

VRT[0:31] ← ConvertToSignedWord_RoundTowardZero(VRB[0:127])
VRT[32:127] ← 0

The xscvqpswz instruction converts a quad-precision floating-point value to a signed word, rounding towards zero. It handles NaNs by setting the result to 0xFFFF_FFFF_8000_0000 and flags VXSNAN and VXCVI accordingly. For infinities, it sets the result to the maximum or minimum signed word value based on the sign of the infinity. Ensure that VSX is enabled (MSR.VSX=1) before using this instruction; otherwise, a VSX_Unavailable exception will be raised.


VSX Scalar Convert with round to zero Quad-Precision to Unsigned Quadword

Summary: Converts a quad-precision floating-point value to an unsigned quadword integer, rounding towards zero.

The instruction converts the quad-precision floating-point value in VSR[VRB+32] to an unsigned quadword integer and places the result into VSR[VRT+32]. The conversion rounds towards zero. If the source is a NaN or Infinity, an Invalid Operation exception occurs.

if MSR.VSX=0 then
    VSypX_Unavailable()
else if src.class.QNaN=1 | src.class.SNaN=1 then do
    vxsnan_flag ←src.class.SNaN
    vxcvi_flag ←1
    result ←0x0000_0000_0000_0000_0000_0000_0000_0000
end
else if src.class.Infinity=1 then do
    vxcvi_flag ←1
    if src.sign=0 then
        result ←0xFFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF
    else
        result ←0x0000_0000_0000_0000_0000_0000_0000_0000
end
else if src.class.Zero=1 then
    result ←0x0000_0000_0000_0000_0000_0000_0000_0000
else do
    rnd ←bfp_ROUND_TO_INTEGER(0b001,src)
    if bfp_COMPARE_GT(rnd, +2128-1) then do
        result ←0xFFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF
        vxcvi_flag ←1
    end
    else if bfp_COMPARE_LT(rnd, 0) then do
        result ←0x0000_0000_0000_0000_0000_0000_0000_0000
        vxcvi_flag ←1
    end
    else do
        result ←si128_CONVERT_FROM_BFP(rnd)
        if xx_flag=1 then SetFX(FPSCR.XX)
    end
end
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vxcvi_flag=1  then SetFX(FPSCR.VXCVI)
vx_flag ←vxsnan_flag | vxcvi_flag
ex_flag ←FPSCR.VE & vx_flag
if ex_flag=0 then do
    VSR[VRT+32] ←result
    FPSCR.FPRF ←0bUUUUU
end
FPSCR.FR ←(vx_flag=0) & inc_flag
FPSCR.FI ←(vx_flag=0) & xx_flag

FPSCR.FR, FPSCR.FI, FPSCR.FPRF, FPSCR.FX

This instruction is used to convert a quad-precision floating-point number to an unsigned quadword integer, rounding towards zero. Be cautious with NaNs and infinities, as they will trigger exceptions. Ensure VSX is enabled in the MSR register before using this instruction.


VSX Scalar Convert with round to zero Quad-Precision to Unsigned Word format

Summary: Converts a quad-precision floating-point value to an unsigned word format.

Converts a quad-precision floating-point value from the source VSR to an unsigned 32-bit word integer using round-toward-zero mode and stores the result in the target VSR. Only the scalar element is processed. Out-of-range or negative values saturate; FPSCR status is updated with conversion exception flags.

VRT[0:31] ← ConvertToUnsignedWord_RoundTowardZero(VRB[0:127])
VRT[32:127] ← 0

This instruction is used to convert a quad-precision floating-point number to an unsigned 32-bit integer, rounding towards zero. Be cautious with NaN and out-of-range values, as they can trigger exceptions and set specific flags in the FPSCR register. Ensure that the source vector register (VRB+32) contains a valid quad-precision value to avoid unexpected behavior.


Vector Convert Double-Precision to Signed Word format with round to zero

Summary: Converts double-precision floating-point values in a vector to signed 32-bit integers with rounding towards zero.

Converts each double-precision floating-point element in XB to a signed 32-bit integer in XT, rounding towards zero (truncation). This is a VSX instruction that operates on vector elements independently. No condition registers or status fields are affected by this instruction.

xvcvdpsxws rounds using Round towards Zero rounding mode. Previous versions of the architecture allowed the contents of words 1 and 3 of the result register to be undefined. However, all processors that support this instruction write the result into words 0 and 1 and words 2 and 3 of the result register.


Vector Convert Double-Precision to Unsigned Word format with round to zero

Summary: Converts double-precision floating-point values in a vector to unsigned 32-bit integers with rounding towards zero.

The instruction converts each element of the input vector from double-precision floating-point format to an unsigned 32-bit integer using round towards zero. If the rounded value is greater than 2^32 - 1, it results in 0xFFFF_FFFF and VXCVI is set to 1. If less than 0, it results in 0x0000_0000 and VXCVI is set to 1.

for i = 0 to 1 do
    src <- VSR[XB][i]
    if src is a QNaN then
        T(Nmin), fx(VXCVI)
        if FPSCR.VXCVI=0 and MSR.FE0!=ignore-exception-mode or MSR.FE1!=ignore-exception-mode then
            error()
        end if
    else if src is a SNaN then
        T(Nmin), fx(VXCVI), fx(VXSNAN)
        if FPSCR.VXSNAN=0 and MSR.FE0!=ignore-exception-mode or MSR.FE1!=ignore-exception-mode then
            error()
        end if
    else if src ≤ Nmin-1 then
        T(Nmin), fx(VXCVI)
        if FPSCR.VXCVI=0 and MSR.FE0!=ignore-exception-mode or MSR.FE1!=ignore-exception-mode then
            error()
        end if
    else if Nmin-1 < src < Nmin then
        T(Nmin), fx(XX)
        if FPSCR.XX=0 and MSR.FE0!=ignore-exception-mode or MSR.FE1!=ignore-exception-mode then
            error()
        end if
    else if src = Nmin then
        T(Nmin)
    else if Nmin < src < Nmax then
        T(f2i(trunc(src))), fx(XX)
        if FPSCR.XX=0 and MSR.FE0!=ignore-exception-mode or MSR.FE1!=ignore-exception-mode then
            error()
        end if
    else if src = Nmax then
        T(Nmax)
    else if Nmax < src < Nmax+1 then
        T(Nmax), fx(XX)
        if FPSCR.XX=0 and MSR.FE0!=ignore-exception-mode or MSR.FE1!=ignore-exception-mode then
            error()
        end if
    else if src ≥ Nmax+1 then
        T(Nmax), fx(VXCVI)
        if FPSCR.VXCVI=0 and MSR.FE0!=ignore-exception-mode or MSR.FE1!=ignore-exception-mode then
            error()
        end if
    end if
end for

xvcvdpuxws rounds using Round towards Zero rounding mode. Previous versions of the architecture allowed the contents of words 1 and 3 of the result register to be undefined. However, all processors that support this instruction write the result into words 0 and 1 and words 2 and 3 of the result register.


Vector Convert with round to zero Single-Precision to Signed Word format

Summary: Converts a vector of single-precision floating-point numbers to signed integers using round towards zero.

Converts each single-precision floating-point element in XB to a signed 32-bit integer in XT, rounding towards zero. This is a VSX instruction operating element-wise on a vector of single-precision values. No condition registers or status fields are modified.

xvcvspsxws rounds using Round towards Zero rounding mode. For other rounding modes, software must use a Round to Single-Precision Integer instruction that corresponds to the desired rounding mode.


Vector Convert with round to zero Single-Precision to Unsigned Doubleword format

Summary: Converts a single-precision floating-point value to an unsigned doubleword integer, rounding according to the current rounding mode.

Converts single-precision floating-point elements in XB to unsigned 64-bit integer elements in XT, using the current rounding mode. This is a VSX instruction that processes elements independently. No condition registers or status fields are affected.

xvcvspuxds rounds using Round towards Zero rounding mode. For other rounding modes, software must use a Round to Single-Precision Integer instruction that corresponds to the desired rounding mode, including xvrspic which uses the rounding mode specified by RN.


Vector Convert with round to zero Single-Precision to Unsigned Word format

Summary: Converts a single-precision floating-point value to an unsigned word using round towards zero.

The instruction converts each element of the source vector (VSR[XB]) from single-precision floating-point format to an unsigned 32-bit integer, rounding towards zero. If the result is out of range, it saturates to either 0x0000_0000 or 0xFFFF_FFFF.

for i = 0 to 3 do
    src <- VSR[XB][i]
    if src ≤ Nmin-1 then
        T(Nmin)
    else if Nmin-1 < src < Nmin then
        if FPSCR.VE = 0 then
            T(Nmin)
        else
            fx(VXCVI), error()
        end if
    else if src = Nmin then
        T(Nmin)
    else if Nmin < src < Nmax then
        if FPSCR.XE = 0 then
            T(f2i(trunc(src)))
        else
            fx(XX), error()
        end if
    else if src = Nmax then
        T(Nmax)
    else if Nmax < src < Nmax+1 then
        if FPSCR.XE = 0 then
            T(Nmax)
        else
            fx(XX), error()
        end if
    else if src ≥ Nmax+1 then
        if FPSCR.VE = 0 then
            T(Nmin)
        else
            fx(VXCVI), error()
        end if
    else if src is a QNaN then
        if FPSCR.VE = 0 then
            T(Nmin)
        else
            fx(VXCVI), error()
        end if
    else if src is a SNaN then
        if FPSCR.VE = 0 then
            T(Nmin)
        else
            fx(VXCVI), fx(VXSNAN), error()
        end if
    end if
end for

xvcvspuxws rounds using Round towards Zero rounding mode. For other rounding modes, software must use a Round to Single-Precision Integer instruction that corresponds to the desired rounding mode.


VSX Scalar Convert with round Signed Quadword to Quad-Precision

Summary: Converts a signed quadword integer to a quad-precision floating-point number and rounds it.

The instruction converts the 128-bit signed integer value in VSR[VRB+32] to an unbounded-precision floating-point value, rounds it to quad-precision using the rounding mode specified by RN, and places the result into VSR[VRT+32].

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src ←bfp_CONVERT_FROM_SI128(VSR[VRB+32])
rnd ←bfp_ROUND_TO_BFP128(0, FPSCR.RN, src)
result ←bfp128_CONVERT_FROM_BFP(rnd)
if xx_flag=1 then SetFX(XX)
VSR[VRT+32] ←result
FPSCR.FPRF ←fprf_CLASS_BFP128(result)
FPSCR.FR ←inc_flag
FPSCR.FI ←xx_flag

This instruction is used to convert a 128-bit signed integer to a quad-precision floating-point number with rounding. Ensure the VSX feature is enabled in the MSR register. Be cautious of the rounding mode specified by FPSCR.RN, as it affects the precision and result of the conversion. The instruction updates several special registers like FPSCR.FPRF, FPSCR.FR, and FPSCR.FI to reflect the operation's outcome.


VSX Scalar Convert with round Signed Doubleword to Single-Precision format

Summary: Converts a signed doubleword integer in a VSX register to a single-precision floating-point number and rounds it.

The instruction converts the contents of doubleword element 0 of VSR[XB] from a signed integer to a single-precision floating-point number, rounds it according to the rounding mode specified by FPSCR.RN, and places the result in doubleword element 0 of VSR[XT] in double-precision format. Doubleword element 1 of VSR[XT] is set to zero.

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src ← bfp_CONVERT_FROM_SI64(VSR[32×BX+B].dword[0])
rnd ← bfp_ROUND_TO_BFP32(FPSCR.RN,v)
result32 ← bfp32_CONVERT_FROM_BFP(rnd)
result64 ← bfp64_CONVERT_FROM_BFP(rnd)
if xx_flag=1 then SetFX(FPSCR.XX)
VSR[32×TX+T].dword[0] ← result64
VSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000
FPSCR.FPRF ← fprf_CLASS_BFP32(result32)
FPSCR.FR ← inc_flag
FPSCR.FI ← xx_flag

Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.


VSX Vector Convert with round Signed Doubleword to Double-Precision format

Summary: Converts signed doublewords from a vector register to double-precision floating-point values and rounds them.

The instruction converts each signed doubleword in the source vector register (VSR[XB]) to a double-precision floating-point value, rounds it according to the rounding mode specified by FPSCR.RN, and stores the result in the target vector register (VSR[XT]).

if MSR.VSX=0 then VSX_Unavailable()

ex_flag ←0b0

do i = 0 to 1
    reset_xflags()

    src ←bfp_CONVERT_FROM_SI64(VSR[32×BX+B].dword[i])
    rnd ←bfp_ROUND_TO_BFP64(0b0,FPSCR.RN,v)

    vresult.dword[i] ←bfp64_CONVERT_FROM_BFP(rnd)

    if xx_flag=1 then SetFX(FPSCR.XX)

    ex_flag ←ex_flag | (FPSCR.XE & xx_flag)
end

if ex_flag=0 then VSR[32×TX+T] ←vresult

This instruction is commonly used for converting signed doubleword integers to double-precision floating-point numbers in vector operations. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking and setting the MSR.VSX bit. Be aware of rounding modes specified in FPSCR.RN, as they affect the precision of the conversion. Handle exceptions by checking FPSCR.XE and FPSCR.XX flags after execution.


VSX Vector Convert Signed Word to Double-Precision format XX2-form

Summary: Converts signed word elements from a vector register to double-precision floating-point elements in another vector register.

The instruction converts each signed integer value in bits 0:31 of doubleword element i of VSR[XB] into double-precision format and places it into doubleword element i of VSR[XT].

if MSR.VSX=0 then VSX_Unavailable()
do i = 0 to 1
    src ←bfp_CONVERT_FROM_SI32(VSR[32×BX+B].dword[i].word[0])
    VSR[32×TX+T].dword[i] ←bfp64_CONVERT_FROM_BFP(src)
end

This instruction is used to convert signed 32-bit integers in a VSX register to double-precision floating-point format. Ensure that the VSX facility is enabled (MSR.VSX=1) before using this instruction; otherwise, it will raise an exception. The conversion is performed for each of the two doublewords in the source register and stored in the corresponding positions of the target register.


VSX Vector Convert with round Signed Doubleword to Single-Precision format

Summary: Converts signed doubleword elements of a vector register to single-precision floating-point and rounds the result.

The instruction converts each signed doubleword element in VSR[XB] to an unbounded-precision floating-point value, rounds it to single-precision using the rounding mode specified by FPSCR.RN, and places the result into bits 0:31 and 32:63 of the corresponding doubleword element in VSR[XT].

if MSR.VSX=0 then VSX_Unavailable()

ex_flag ←0b0

do i = 0 to 1
    reset_xflags()

    src ←bfp_CONVERT_FROM_SI64(VSR[32×BX+B].dword[i])
    rnd ←bfp_ROUND_TO_BFP32(FPSCR.RN,v)

    vresult.dword[i].word[0] ←bfp32_CONVERT_FROM_BFP(rnd)
    vresult.dword[i].word[1] ←bfp32_CONVERT_FROM_BFP(rnd)

    if xx_flag=1 then SetFX(FPSCR.XX)

    ex_flag ←ex_flag | (FPSCR.XE & xx_flag)
end

if ex_flag=0 then VSR[32×TX+T] ←vresult

Previous versions of the architecture allowed the contents of words 1 and 3 of the result register to be undefined. However, all processors that support these instructions write the result into words 0 and 1 and words 2 and 3 of the result register, as is required by this version of the architecture.


VSX Scalar Insert Exponent Quad-Precision

Summary: Inserts the exponent from a doubleword element of one vector register into another vector register.

The contents of bit 0 of VSR[VRA+32] are placed into bit 0 of VSR[VRT+32]. The contents of bits 49:63 of doubleword element 0 of VSR[VRB+32] are placed into bits 1:15 of VSR[VRT+32]. The contents of bits 16:127 of VSR[VRA+32] are placed into bits 16:127 of VSR[VRT+32].

if MSR.VSX=0 then
    VSX_Unavailable()
else
    VSR[VRT+32].bit[0]     ←VSR[VRA+32].bit[0]
    VSR[VRT+32].bit[1:15] ← VSR[VRB+32].dword[0].bit[49:63]
    VSR[VRT+32].bit[16:127] ←VSR[VRA+32].bit[16:127]

This instruction is used to manipulate the exponent and sign of a quad-precision floating-point number. Ensure that VSX (Vector Scalar Extensions) is enabled in the MSR register before using this instruction; otherwise, it will raise an exception. The operation requires proper alignment of the input registers, specifically for doubleword access in VRB. This instruction operates at the user privilege level and does not generate exceptions under normal conditions.


VSX Vector Insert Exponent Double-Precision

Summary: Inserts the exponent from one vector register into another for double-precision floating-point numbers.

Inserts the exponent field from XB into the exponent of XA to form a new double-precision floating-point value in XT. This is a VSX instruction used for constructing floating-point values with specific exponents. No condition registers or status fields are affected.

for i in 0 to 1 do
  exp ← XB[i*64+52:i*64+62]
  sig ← XA[i*64:i*64+51]
  XT[i*64:(i+1)*64-1] ← CONSTRUCT_FP64(exp, sig)
end for

The xviexpdp instruction is used to insert the exponent from one vector register into another for double-precision floating-point numbers. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR.VSX bit before using this instruction, otherwise a VSX_Unavailable exception will be raised. The instruction operates on 64-bit elements and requires proper alignment of the source and target registers to avoid undefined behavior.


VSX Vector Test Data Class Double-Precision

Summary: Tests each double-precision floating-point element in a vector against specified data classes and sets the corresponding elements in another vector to either all ones or all zeros based on the match.

For xvtstdcdp, each double-precision floating-point value in VSR[XB] is tested against the data classes specified by DCMX. If a match is found, the corresponding element in VSR[XT] is set to 0xFFFF_FFFF_FFFF_FFFF; otherwise, it is set to 0x0000_0000_0000_0000.

DCMX

Data Class Mask (concatenation of dc, dm, and dx)

if MSR.VSX=0 then VSX_Unavailable()

DCMX ← dc || dm || dx
XT ← 32×TX + T
do i = 0 to 1
    src ← VSR[32×BX+B].dword[i]
    sign ← src.bit[0]
    exponent ← src.bit[1:11]
    fraction ← src.bit[12:63]

    class.Infinity ← (exponent = 0x7FF) & (fraction = 0)
    class.NaN ← (exponent = 0x7FF) & (fraction ≠ 0)
    class.Zero ← (exponent = 0x000) & (fraction = 0)
    class.Denormal ← (exponent = 0x000) & (fraction ≠ 0)

    match ←
        (DCMX.bit[0] & class.NaN) |
        (DCMX.bit[1] & class.Infinity & !sign) |
        (DCMX.bit[2] & class.Infinity & sign) |
        (DCMX.bit[3] & class.Zero & !sign) |
        (DCMX.bit[4] & class.Zero & sign) |
        (DCMX.bit[5] & class.Denormal & !sign) |
        (DCMX.bit[6] & class.Denormal & sign)

    if match = 1 then
        VSR[XT].dword[i] ← 0xFFFF_FFFF_FFFF_FFFF
    else
        VSR[XT].dword[i] ← 0x0000_0000_0000_0000
end

This instruction is used to test each double-precision floating-point value in a vector register against specified data classes. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking and setting the appropriate bit in the Machine State Register (MSR). The instruction requires proper alignment of the source and target vector registers. Be cautious with the data class mask (DCMX) as incorrect settings can lead to unexpected results. This operation is performed at the user privilege level, but it may trigger exceptions if VSX is not available or if there are issues with register access.


VSX Vector Test Data Class Single-Precision

Summary: Tests each single-precision floating-point element in a vector against specified data classes and sets the corresponding elements in another vector based on the match.

This instruction tests each single-precision floating-point element in VSR[XB] against the data classes specified by DCMX. If an element matches one of the specified data classes, the corresponding element in VSR[XT] is set to 0xFFFF_FFFF; otherwise, it is set to 0x0000_0000.

if MSR.VSX=0 then VSX_Unavailable()

DCMX ←dc || dm || dx
do i = 0 to 3
    src           ←VSR[32×BX+B].word[i]
    sign         ←src.bit[0]
    exponent      ←src.bit[1:8]
    fraction      ←src.bit[9:31]
    class.Infinity ←(exponent = 0xFF) & (fraction  = 0)
    class.NaN     ←(exponent = 0xFF) & (fraction != 0)
    class.Zero    ←(exponent = 0x00) & (fraction  = 0)
    class.Denormal ←(exponent = 0x00) & (fraction != 0)

    match ←
        (DCMX.bit[0] & class.NaN)              |
        (DCMX.bit[1] & class.Infinity & !sign) |
        (DCMX.bit[2] & class.Infinity &  sign) |
        (DCMX.bit[3] & class.Zero     & !sign) |
        (DCMX.bit[4] & class.Zero     &  sign) |
        (DCMX.bit[5] & class.Denormal & !sign) |
        (DCMX.bit[6] & class.Denormal &  sign)

    if match = 1 then
        VSR[32×TX+T].dword[i] ←0xFFFF_FFFF
    else
        VSR[32×TX+T].dword[i] ←0x0000_0000
end

This instruction is useful for identifying specific data classes in single-precision floating-point vectors. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking and setting the appropriate bits in the MSR register. The instruction does not require any special alignment, but it operates on 32-bit elements within the vector registers. Be cautious with the DCMX mask to avoid unintended matches, as incorrect settings can lead to all elements being set to zero or all being set to 0xFFFFFFFF.


VSX Vector Extract Exponent Double-Precision

Summary: Extracts the exponent from each double-precision floating-point value in a vector and places it into another vector.

For xvxexpdp, the exponent field of each double-precision floating-point value in VSR[XB] is extracted and placed into VSR[XT].

if MSR.VSX=0 then VSX_Unavailable()
do i = 0 to 1
    src ←VSR[32×BX+B].dword[i]
    VSR[32×TX+T].dword[i] ←EXTZ64(src.bit[1:11])
end

This instruction extracts the exponent from each double-precision floating-point value in the source vector and stores it in the destination vector. Ensure that VSX is enabled; otherwise, a VSX_Unavailable exception will be raised. The operation processes two elements per vector register (64 bits each), extracting the 11-bit exponent field and zero-extending it to 64 bits.


Vector Extract Significand Double-Precision

Summary: Extracts the significand of double-precision floating-point values from a vector register and places them into another vector register.

For xvxsigdp, the significand of each double-precision floating-point value in the source vector register VSR[XB] is extracted and placed into the target vector register VSR[XT].

if MSR.VSX=0 then VSX_Unavailable()
do i = 0 to 1
    src ←VSR[32×BX+B].dword[i]
    exponent ←EXTZ(src.bit[1:11])
    fraction ←EXTZ64(src.bit[12:63])
    if (exponent != 0) & (exponent != 2047) then
        fraction ←fraction | (0x001 || 520)
    VSR[32×TX+T].dword[i] ←fraction
end

This instruction extracts the significand from each double-precision floating-point value in the source vector register and places it into the target vector register. Ensure that the VSX (Vector Scalar Extensions) is enabled, as attempting to use this instruction when VSX is unavailable will result in an exception. The operation does not modify the exponent or sign bit of the original values.


VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) with Saturation Positive multiply, Positive accumulate

Summary: Performs a vector-scalar operation on 8-bit signed and unsigned integers with saturation.

Performs a 4×4 generalized outer product (GER) on 8-bit signed/unsigned integers from XA and XB, accumulating the products into the 32-bit accumulator AT with saturation applied. Results with positive products and positive accumulation ('pp' suffix) are saturated to the signed 32-bit range. This is a VSX instruction requiring the MMA category support.

acc ← AT
for i in 0 to 3 do
  for j in 0 to 3 do
    a ← sign_extend(XA[i*8:(i+1)*8-1], 8)
    b ← sign_extend(XB[j*8:(j+1)*8-1], 8)
    prod ← a × b
    acc[i*32+j*8:(i*32+j*8+31)] ← SATURATE_S32(acc[i*32+j*8:(i*32+j*8+31)] + prod)
  end for
end for
AT ← acc

This instruction is used for performing vector-scalar operations on 8-bit signed and unsigned integers, multiplying corresponding elements of two vectors and accumulating the results into an accumulator with saturation handling. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid a 'VSX_Unavailable' exception. The operation involves multiple steps of multiplication and accumulation, which can be computationally intensive; consider optimizing vector sizes and operations for performance.


Prefixed Masked VSX Vector bfloat16 GER (rank-2 update) Negative multiply, Positive accumulate

Summary: Performs a masked vector operation with bfloat16 elements using negative multiplication and positive accumulation.

This instruction performs a masked vector operation with bfloat16 elements using negative multiplication and positive accumulation. It updates the accumulator register based on the specified masks and rounding mode.

if MSR.VSX=0 then VSX_Unavailable()

if 'xvbf16ger2' | 'xvbf16ger2pp' | 'xvbf16ger2pn' | 'xvbf16ger2np' | 'xvbf16ger2nn' then
do
   PMSK ←0b11      // enable all rank updates
   XMSK ←0b1111    // enable all ACC[AT] rows
   YMSK ←0b1111    // enable all ACC[AT] columns
end

do i = 0 to 3
   do j = 0 to 3
      if XMSK.bit[i]=1 & YMSK.bit[j]=1 then do
         src11 ←(PMSK.bit[0]=0) ? bfp_ZERO :
                       bfp_CONVERT_FROM_BFLOAT16(VSR[32×AX+A].word[i].hword[0])
         src21 ←(PMSK.bit[0]=0) ? bfp_ZERO :
                       bfp_CONVERT_FROM_BFLOAT16(VSR[32×BX+B].word[j].hword[0])
         src12 ←(PMSK.bit[1]=0) ? bfp_ZERO :
                       bfp_CONVERT_FROM_BFLOAT16(VSR[32×AX+A].word[i].hword[1])
         src22 ←(PMSK.bit[1]=0) ? bfp_ZERO :
                       bfp_CONVERT_FROM_BFLOAT16(VSR[32×BX+B].word[j].hword[1])

         reset_flags()

         p1 ←bfp_MULTIPLY(src11, src21)
         v1 ←bfp_MULTIPLY_ADD(src12, src22, p1)
         r1 ←bfp_ROUND_TO_BFP32_SIGNIFICAND(v1)

         if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
         if vximz_flag=1 then SetFX(FPSCR.VXIMZ)
         if vxisi_flag=1 then SetFX(FPSCR.VXISI)
         if xx_flag=1 then SetFX(FPSCR.XX)

         if 'pmxvbf16ger2' then do
            reset_flags()

            r2 ←bfp_ROUND_TO_BFP32_DEFAULT(FPSCR.RN,r1)
            ACC[AT][i].word[j] ←bfp32_CONVERT_FROM_BFP(r2)

            if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
            if vxisi_flag=1 then SetFX(FPSCR.VXISI)
            if ox_flag=1 then SetFX(FPSCR.OX)
            if ux_flag=1 then SetFX(FPSCR.UX)
            if xx_flag=1 then SetFX(FPSCR.XX)
         end

         else do
            acc ←bfp_CONVERT_FROM_BFP32(ACC[AT][i].word[j])

            reset_flags()
      end
   end
end

This instruction is used for performing a masked vector operation with bfloat16 elements, using negative multiplication and positive accumulation. It requires the VSX feature to be enabled in the MSR register. The instruction updates the accumulator register based on specified masks and rounding mode. Ensure that the VSX feature is available and properly configured before using this instruction.

pmxvbf16ger2np acc0, vs2, vs3, 15, 15, 3


Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative multiply, Positive accumulate

Summary: Performs a masked vector operation with negative multiplication and positive accumulation.

The instruction performs a masked vector operation where the elements of two vectors are multiplied and accumulated based on the mask values provided.

if MSR.VSX=0 then VSX_Unavailable()

if 'xvf16ger2' | 'xvf16ger2pp' | 'xvf16ger2pn' | 'xvf16ger2np' | 'xvf16ger2nn' then do
   PMSK ←0b11
   XMSK ←0b1111
   YMSK ←0b1111
end

do i = 0 to 3
   do j = 0 to 3
      if XMSK.bit[i] & YMSK.bit[j] then do
         reset_flags()

         src10 ←bfp_CONVERT_FROM_BFP16((PMSK.bit[0]=0) ? 0x0000 : VSR[32×AX+A].word[i].hword[0])
         src11 ←bfp_CONVERT_FROM_BFP16((PMSK.bit[1]=0) ? 0x0000 : VSR[32×AX+A].word[i].hword[1])
         src20 ←bfp_CONVERT_FROM_BFP16((PMSK.bit[0]=0) ? 0x0000 : VSR[32×BX+B].word[j].hword[0])
         src21 ←bfp_CONVERT_FROM_BFP16((PMSK.bit[1]=0) ? 0x0000 : VSR[32×BX+B].word[j].hword[1])

         p1    ←bfp_MULTIPLY(src10, src20)
         v1    ←bfp_MULTIPLY_ADD(src11, src21, p1)
         r1    ←bfp_ROUND_TO_BFP32_DEFAULT(FPSCR.RN, v1)

         if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
         if vximz_flag=1 then SetFX(FPSCR.VXIMZ)
         if vxisi_flag=1 then SetFX(FPSCR.VXISI)
         if ox_flag=1 then SetFX(FPSCR.OX)
         if ux_flag=1 then SetFX(FPSCR.UX)
         if xx_flag=1 then SetFX(FPSCR.XX)

         reset_flags()

         if '[pm]xvf16ger2' then
            ACC[AT][i].word[j] ←bfp32_CONVERT_FROM_BFP(r1)

         else do
            acc ←bfp_CONVERT_FROM_BFP32(ACC[AT][i].word[j])

            if '[pm]xvf16ger2pp' then v2 ←bfp_ADD(r1, acc)
            if '[pm]xvf16ger2pn' then v2 ←bfp_ADD(r1, bfp_NEGATE(acc))
            if '[pm]xvf16ger2np' then v2 ←bfp_ADD(bfp_NEGATE(r1), acc)
            if '[pm]xvf16ger2nn' then v2 ←bfp_ADD(bfp_NEGATE(r1), bfp_NEGATE(acc))

            r2 ←bfp_ROUND_TO_BFP32_DEFAULT(FPSCR.RN, v2)
      end
   end
end

This instruction is used for performing masked vector operations on 16-bit floating-point numbers, with specific handling of negative and positive accumulations. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. Pay attention to the mask values (PMSK, XMSK, YMSK) as they control which elements are processed. Be aware of potential floating-point exceptions such as VXSNAN, VXIMZ, VXISI, OX, UX, and XX, and handle them appropriately in your code.


Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate

Performs a masked 4×4 generalized outer product (rank-1 update GER) on 32-bit floating-point elements, using negative multiplication and positive accumulation ('np' suffix). The XMSK and YMSK operands control which rows and columns participate in the operation. This is a prefixed VSX instruction requiring VSX and prefix support.

acc ← AT
for i in 0 to 3 do
  if XMSK[i] = 1 then
    for j in 0 to 3 do
      if YMSK[j] = 1 then
        a ← XA[i*32:(i+1)*32-1]
        b ← XB[j*32:(j+1)*32-1]
        prod ← -1.0 × a × b
        acc[i*32+j*8:(i*32+j*8+31)] ← acc[i*32+j*8:(i*32+j*8+31)] + prod
      end if
    end for
  end if
end for
AT ← acc

This instruction is used for performing masked vector operations on single-precision floating-point values, specifically a GER (rank-1 update) operation with negative multiplication and positive accumulation. Ensure that the VSX feature is enabled in the MSR register to avoid exceptions. The instruction processes 4x4 elements, checking masks before performing operations. Be cautious of potential overflow or underflow conditions, as they can trigger exceptions and set flags in the FPSCR register.


Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate

Summary: Performs a masked vector floating-point operation with negative multiplication and positive accumulation.

Performs a masked 2×2 generalized outer product (rank-1 update GER) on 64-bit floating-point elements, using negative multiplication and positive accumulation ('np' suffix). The XMSK and YMSK operands control participation of rows and columns respectively. This is a prefixed VSX instruction requiring VSX and prefix support.

acc ← AT
for i in 0 to 1 do
  if XMSK[i] = 1 then
    for j in 0 to 1 do
      if YMSK[j] = 1 then
        a ← XAp[i*64:(i+1)*64-1]
        b ← XB[j*64:(j+1)*64-1]
        prod ← -1.0 × a × b
        acc[i*64+j*64:(i*64+j*64+63)] ← acc[i*64+j*64:(i*64+j*64+63)] + prod
      end if
    end for
  end if
end for
AT ← acc

This instruction is used for performing masked vector floating-point operations with negative multiplication and positive accumulation. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid a VSX_Unavailable exception. The operation involves converting BFP64 values, performing arithmetic operations, rounding, and handling exceptions based on flags set during computation.


Summary: Reverses the bytes of each doubleword element in a vector register.

The contents of byte 5 of doubleword element i of VSR[XB] are placed into byte 2 of doubleword element i of VSR[XT]. Similarly, the contents of byte 4 of doubleword element i of VSR[XB] are placed into byte 3 of doubleword element i of VSR[XT], and so on.

if MSR.VSX=0 then VSX_Unavailable()
do i = 0 to 1
    vsrc ← VSR[32×BX+B].dword[i]
    do j = 0 to 7
        VSR[32×TX+T].dword[i].byte[j] ← vsrc.byte[7-j]
    end
end

The xxbrd instruction reverses the bytes within each doubleword of a VSX vector. Ensure that the VSX facility is enabled in the MSR register to avoid an exception. This instruction operates on 128-bit vectors, processing two 64-bit doublewords. There are no specific alignment requirements for the source or target registers.


Summary: Reverses the bytes of each halfword in a vector register.

Reverses the byte order within each 16-bit (halfword) element in XB and stores the result in XT. This is a VSX instruction commonly used for endianness conversion on 16-bit data granules. No condition registers or status fields are affected.

for i in 0 to 7 do
  hw ← XB[i*16:(i+1)*16-1]
  XT[i*16:(i+1)*16-1] ← REVERSE_BYTES(hw, 2)
end for

The xxbrh instruction is useful for reversing the byte order of each halfword in a vector, which can be necessary for data format conversion or compatibility. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking and setting the appropriate bit in the MSR register. This instruction operates on 128-bit vectors and requires proper alignment of the source and target registers. Be cautious of endianness issues when using this instruction, as it directly manipulates byte order.


Summary: Reverses the bytes of each word in a vector register.

Reverses the byte order within each 32-bit word of the source VSX vector register XB and places the result in XT. This is a VSX extension instruction with no effect on condition registers or status fields.

do i = 0 to 3
  word ← XB[i*32:(i+1)*32-1]
  XT[i*32:(i+1)*32-1] ← reverse_bytes(word)
enddo

The xxbrw instruction is used to reverse the byte order of each word in a vector register. Ensure that VSX (Vector Scalar Extensions) is enabled by checking and setting the appropriate bit in the MSR register. This instruction operates on 128-bit vector registers, processing four 32-bit words per operation. Be cautious of alignment requirements; source and target vectors must be properly aligned to avoid exceptions.


VSX Vector Shift Left Double by Word Immediate

Summary: Shifts the contents of two vector registers left by a specified number of words and places the result into another vector register.

Shifts the concatenation of VSX vector registers XA and XB left by SHW words (0-3) and stores the result in XT. This instruction treats the two 128-bit source registers as a 256-bit value and extracts a 128-bit aligned window. No condition registers or status fields are affected.

shw ← SHW[1:0]
temp ← (XA || XB)  # concatenate as 256-bit value
XT ← temp[shw*32:(shw*32)+127]

The xxsldwi instruction is commonly used for shifting vector elements by a specified number of words. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. The shift amount must be within the range of 0 to 3, as it specifies the word position to align the result. This instruction operates at the user privilege level and does not generate exceptions for valid shifts; however, misalignment or exceeding the shift limit can lead to undefined behavior.


Summary: Loads a special value into a VSX vector register.

Loads a special constant vector value into VSX vector register XT based on the 5-bit unsigned immediate UIM. The instruction provides a fast way to initialize vectors with commonly used special values. No condition registers or status fields are affected.

UIM

Unspecified Immediate, specifies which special value to load

Loads a VSX register with a constant vector value determined by UIM. The 5-bit UIM field selects from a set of predefined quadword constants (e.g., IEEE infinity, NaN, zero). No memory access is performed. This instruction cannot be used to load arbitrary immediates.


VSX Vector Test Least-Significant Bit by Byte

Summary: Tests the least-significant bit of each byte in a VSX vector register and sets a condition register field based on the results.

Tests the least-significant bit of each byte in VSX vector register XB and sets condition register field BF based on whether all tested bits are zero. Sets BF to reflect if all LSBs are 0 (CR field = 0b0010) or if any LSB is 1 (CR field = 0b0011). This is a VSX extension instruction.

all_zero ← 1
do i = 0 to 15
  if XB[i*8+7] = 1 then all_zero ← 0
enddo
if all_zero then
  CR[BF] ← 0b0010
else
  CR[BF] ← 0b0011
endif

This instruction following any Vector Compare provides the ability to direct the summary status of the Vector Compare to any CR field, not just CR field 6 when Rc=1.


Summary: Branches to a target address if the condition 'less than' is true.

The instruction checks if the condition 'less than' in the specified CR field is true and branches to the target address if it is.

if CR[CR field][LT] then
    PC <- target_address

The blt instruction is commonly used for conditional branching based on comparison results. Ensure that the correct condition register (CR) field is specified, as this directly affects the branch decision. The target address must be properly calculated to avoid incorrect jumps. This instruction operates at user privilege level and does not generate exceptions under normal circumstances.


Summary: Branches to the target address if CR0 reflects condition 'less than', predicting the branch will be taken.

The instruction branches to the specified target address if the less-than condition is set in CR0. The prediction hint indicates that the branch is almost always taken.

1 | LK | AA | LI | BO | BI | BH | A | AT

Use blt+ when branching based on a less-than comparison where the branch is expected to be taken frequently. Ensure CR0 is correctly set with the result of the comparison before using this instruction. The prediction hint can improve performance by reducing pipeline stalls, but it should match the actual branch behavior.


Summary: Compares a doubleword immediate value with the contents of a register and updates the condition register.

For cmpdi, the immediate value SI is compared with the contents of register RA. The result is placed into CR Field BF.

if 'cmpdi' then
    if (RA) < SI then CR[bF] <- 0b00000001
    else if (RA) > SI then CR[bF] <- 0b00000010
    else CR[bF] <- 0b00000100

Use cmpdi to compare a register with an immediate value and set the condition register field accordingly. Ensure the immediate value fits within the signed 16-bit range. The comparison result is used in conditional branches, so check CR Field BF after execution.


Summary: Extracts a field of n bits starting at bit position b in the source register, left justifies this field in the target register, and clears all other bits of the target register to 0.

For extldi, the field of n bits starting at bit position b in the source register is extracted, left justified in the target register, and all other bits are cleared to 0.

if 'extldi' then
    ra <- (rs >> b) & ((1 << n) - 1)

Use extldi to extract a specific bit field from a source register, left-justifying it in the target register. Ensure that the bit position and length are correctly specified to avoid data corruption. This instruction operates at user privilege level.


Summary: Extracts a specified number of bits from the source register, left-justifies them, and places them in the target register.

Extracts n bits starting at bit position b from GPR rs, left-justifies them in the target GPR ra, and zeros the remaining bits. This is a pseudo-instruction (alias) for rlwimi with specific parameters and operates in 32-bit mode. The instruction updates CR0 if the record bit (Rc) is set.

n

Number of bits to extract (must be greater than 0)

mask ← MASK(0, n-1)
ra ← (rs >> b) & mask
ra ← ra << (32 - n)
if Rc then CR0 ← record_cr(ra) endif

The extlwi instruction is useful for extracting a specific bit field from a source register and left-justifying it in the target register. Ensure that the bit positions 'b' and 'n' are correctly specified to avoid data corruption. The operation preserves or rotates the high-order bits of the target register, so be aware of this behavior if you need to maintain specific register contents.


Summary: Loads a word from memory atomically.

Loads a 32-bit word from memory at an address computed from RA with atomic semantics determined by function code FC. The loaded value is placed in GPR RT. This instruction requires alignment and may be restricted to hypervisor mode depending on FC value.

EA ← RA
RT ← [EA]
# Atomic load with fence behavior determined by FC

EA must be a multiple of 4, and the portion of mem(EA-4,12) accessed by the instruction must be contained within an aligned 32-byte block of storage. If either of these requirements is not satisfied, the system alignment error handler is invoked.


Summary: Stores a word atomically to memory.

Stores a 32-bit word from GPR RS to memory at an address in RA with atomic semantics specified by function code FC. The store is performed atomically with fence behavior determined by FC. Alignment requirements and potential privilege restrictions apply.

EA ← RA
[EA] ← RS
# Atomic store with fence behavior determined by FC

The stwat instruction atomically updates a word in memory at the address specified by register RA. Ensure that RA is properly aligned to avoid exceptions. The function code FC determines the specific update operation; consult the ISA documentation for valid operations. This instruction operates at user privilege level and does not generate any exceptions under normal conditions.


Summary: Reverses the bytes in a doubleword.

Reverses the byte order of a 64-bit doubleword from the source register and places the result in the target register. This instruction operates at the architectural level to perform a complete byte reversal (byte 0 ↔ byte 7, byte 1 ↔ byte 6, etc.). No status fields are affected. This is a Base category instruction with no privilege requirements.

The brd instruction is useful for reversing the byte order of a doubleword in a register, which can be necessary for data format conversion between big-endian and little-endian systems. Ensure that the source register (RA) contains a valid doubleword value to avoid undefined behavior. This operation does not require any special privileges or alignment considerations.


Vector Count Leading Zeros Doubleword under bit Mask

Summary: Counts the number of leading zeros in each doubleword element of a vector, considering a mask.

Counts the number of leading zero bits in each doubleword element of the source vector, using a bit mask from a second source vector to selectively apply the count operation. The results are placed in the target vector as doubleword elements. This is a VMX (AltiVec) category instruction that does not affect condition register or status fields.

Use vclzdm to efficiently count leading zeros in masked bit positions within doublewords. Ensure that VRB contains a valid mask where 1s indicate bits to be considered for zero counting. This instruction operates at user privilege level and does not generate exceptions under normal conditions.


Load Byte and Zero Caching Inhibited Indexed

Summary: Loads a byte from memory into a register, zeroing the upper bits of the target register.

The effective address (EA) is calculated as the sum of RA and RB. The byte at EA is loaded into RT56:63, while RT0:55 are set to 0. The storage access is performed as though the location is Caching Inhibited and Guarded.

if RA = 0 then
    b ← 0
else
    b ← (RA)
EA ← b + (RB)
RT ← 560 || MEM(EA, 1)

The lbzcix instruction is useful for loading a single byte from memory into the upper bits of a register while zeroing out the lower bits. It ensures that the access is treated as caching inhibited and guarded, which can be crucial for accessing special memory regions. Be cautious with RA being zero, as it results in an effective address equal to RB, potentially leading to unintended memory accesses if not handled properly.


Store Byte Caching Inhibited Indexed X-form

Summary: Stores a byte from a register to memory with caching inhibited and guarded.

The instruction stores the byte (RS)56:63 into the memory location addressed by the effective address (EA), which is calculated as the sum of RA and RB. The storage access is performed as though the specified storage location is Caching Inhibited and Guarded.

if RA = 0 then
    b ← 0
else
    b ← (RA)
EA ← b + (RB)
MEM(EA, 1) ← (RS)56:63

This instruction is hypervisor privileged.


Summary: Invalidates SLB entries based on the contents of registers RS and RB.

Invalidates one or more entries in the Segment Lookaside Buffer (SLB) based on the effective address class and segment size specified in RB and the process ID specified in RS, with global scope affecting all processors. This is a privileged instruction (Hypervisor-level) that requires supervisor privileges and does not affect condition register or status fields. It is used for SLB maintenance in virtual memory operations.

RS

Source General Purpose Register containing the target PID (and optionally the target LPID)

RB

Source General Purpose Register containing the EA, class, and segment size

for each SLB entry matching (RS and RB parameters) do
  INVALIDATE_SLB_ENTRY(entry)
end for

slbieg does aﬀect SLBs on other threads.


Summary: Invalidates all SLBs for a specified LPID and PID.

The instruction invalidates all SLB entries for the target LPID and PID. If L=0, the target PID is taken from RS0:31. If executed in hypervisor state, the target LPID is taken from RS32:63; otherwise, it is taken from LPIDR.

if 'slbiag' then
    if L=0 then target_PID = RS0:31
    if MSRHV=1 then target_LPID = RS32:63
    else target_LPID = LPIDR
    for each nest SLB
        for each SLBE with LPID=target_LPID and (PID=target_PID | L=1)
            SLBEV ←0
            all other fields of SLBE ←undefined

slbiag does not affect SLBs on processor threads. slbiag serves as both a basic and an extended mnemonic. The Assembler will recognize an slbiag mnemonic with two operands as the basic form, and an slbiag mnemonic with one operand as the extended form. In the extended form the L operand is omitted and assumed to be 0.


Summary: Searches the SLB for an entry that matches the effective address specified by register RB.

The SLB is searched for an entry that matches the effective address specified by register RB. If exactly one matching entry is found, the contents of the B, VSID, Ks, Kp, N, L, C, and LP fields of the entry are placed into register RT. If no matching entry is found, register RT is set to 0. If more than one matching entry is found, either one of the matching entries is used, or a Machine Check occurs.

if LPCRUPRT=1 then
    // Instruction is nonfunctional
else
    search SLB for entry matching (RB)0:63-s
    if exactly one match found then
        RT <- B | VSID | KsKpNLC | LP
    else if no match found then
        RT <- 0
    else
        // More than one match, Machine Check occurs
end

The contents of registers RT and RB are interpreted as shown below.
RT0:1   B
RT2:51   VSID
RT52     Ks
RT53    Kp
RT54   N
RT55    L
RT56   C
RT57     set to 0b0
RT58:59  LP
RT60:63   set to 0b0000
RB0:35   ESID
RB36:39  must be 0b0000
RB40:63  must be 0x000000
If s > 28, RT80-s:51 are set to zeros. On implementations that support a virtual address size of only n bits, n < 78, RT2:79-n are set to zeros.
CR Field 0 is set as follows. j is a 1-bit value that is equal to 0b1 if a matching entry was found. Otherwise, j is 0b0. When LPCRUPRT̸=0, j=0b0.
CR0LT GT EQ SO = 0b00 || j || XERSO


Summary: Sends a message to other threads in the system.

The instruction sends a message to other threads in the system. The message type and destination thread(s) are specified in RB.

msgtype ← GPR(RB)32:36
payload ← GPR(RB)37:63
if (msgtype = 0x05)
then
    send_msg(msgtype, payload)

If msgsndu is used to notify the receiver that updates have been made to storage, a sync should be placed between the stores and the msgsndu. See Section 6.9.2.


Move to Vector Scalar Register with Bit Mask Immediate

Summary: Moves a bit mask immediate value into a vector scalar register, setting each byte element based on corresponding bits of the immediate.

Moves an 8-bit immediate value into a VSR (Vector Scalar Register) with each bit of the immediate controlling whether the corresponding byte element is set to all-ones (0xFF) or all-zeros (0x00). This is a Base category instruction that does not affect condition register or other status fields. The instruction provides a quick way to create byte-level masks in vector registers.

VRT

Target vector scalar register that receives the byte mask pattern generated from the immediate value.

8-bit immediate value where each bit controls the corresponding byte element (1 = 0xFF, 0 = 0x00).

for i in 0 to 7 do
  if IMM[i] = 1 then
    VSR_target[i*8:(i+1)*8] ← 0xFF
  else
    VSR_target[i*8:(i+1)*8] ← 0x00
end for

The mtvsrbmi instruction is useful for initializing vector registers with specific byte patterns based on an immediate bit mask. Ensure that the immediate value correctly reflects the desired byte-wise initialization to avoid unexpected results. This instruction operates at user privilege level and does not raise exceptions under normal conditions.


Summary: Subtracts the contents of one register from the complement of another and updates the carry-out flag.

For subfc., the complement of the contents of register RB is subtracted from the contents of register RA, and the result is placed into register RT. The carry-out flag is updated based on the operation.

if 'subfc.' then
    RT <- (RA) - (~RB)
    XER.CA <- carry-out

Use subfc. to subtract the bitwise complement of one register from another, updating the carry-out flag in XER.CA. Ensure registers are properly aligned and consider the effect on CR0 for conditional branching.


Summary: Shifts the contents of a register left by a specified number of bits and updates the condition register.

For slw., the contents of register RA are shifted left by the amount specified in RB, and the result is placed into register RT. The shift count is masked to 5 bits.

The slw instruction shifts the contents of RA left by a number of bits specified in RB, with the shift count masked to 5 bits. This operation is useful for bit manipulation tasks but be cautious as shifting large values can lead to overflow. The result is stored in RT, and this instruction operates at user privilege level.


Summary: Adds the contents of two double precision floating-point registers and updates the condition register.

Adds two double-precision decimal floating-point operands and places the result in the target register, then updates CR1 based on the result, exception status, and FPSCR flags. This instruction requires the Decimal Floating-Point (DFP) category and updates FPSCR condition bits and CR1 field based on the result classification and exception conditions.

FRD

Target Double Precision Floating-Point Register

FRB

Source Double Precision Floating-Point Register

FRD ← FRB + FRC
CR1 ← FPSCR[FPRF]
FPSCR[exception bits] ← updated based on result

The dadd. instruction is used for adding two double-precision decimal floating-point numbers. It updates Condition Register Field 1 to indicate the result, which can be useful for conditional operations. Ensure that the input registers contain valid decimal floating-point values to avoid undefined behavior.


Summary: Divides the contents of two single precision floating point registers.

For fdivs, the value in register FRB is divided by the value in register FRA, and the result is placed into register FRT.

The fdivs instruction performs a single-precision floating-point division. Ensure that neither operand is zero to avoid division by zero exceptions. The FPSCR register may be updated with status flags such as overflow or underflow. This operation can raise exceptions if the result overflows, underflows, or is invalid (e.g., NaN).


Summary: Copies the sign of one floating-point number to another.

The fcpsgn. instruction copies the sign bit from the source operand B to the target operand A and places the result in the destination operand C.

Source Floating-Point Register (sign source)

FRA

Source Floating-Point Register (magnitude source)

if 'fcpsgn.' then
    RT <- (RA) with sign of (RB)

The fcpsgn. instruction is useful for manipulating the sign of floating-point numbers without changing their magnitude. Ensure that operands A and B are properly aligned in memory to avoid alignment faults. This operation does not require any special privileges and will not generate exceptions under normal circumstances.


Summary: Divides the contents of two floating-point registers and updates the condition register.

For fdiv., the quotient of the contents of register FA and FB is placed into register FC.

The fdiv. instruction performs a floating-point division, storing the result in register FC. Ensure that registers FA and FB are properly initialized to avoid undefined behavior. This operation may raise exceptions if FB is zero or if there are overflow/underflow conditions; check FPSCR for exception flags after execution.


Summary: Estimates the reciprocal of a floating-point number.

The fre. instruction estimates the reciprocal of the contents of register RA and places the result into register RT.

if 'fre.' then
    RT <- estimate_reciprocal(RA)

The fre. instruction provides a fast, approximate reciprocal value, useful for performance-critical applications like graphics or scientific computing where precision can be traded for speed. Ensure that the input register RA contains a non-zero value to avoid undefined behavior; otherwise, consider adding checks to handle zero inputs gracefully.


Double-Precision Floating-Point Fix to Quadword

Summary: Converts a double-precision floating-point value to a quadword integer.

Converts a double-precision decimal floating-point value to a 128-bit signed quadword integer, storing the result in a GPR pair or related register file location. This Floating-Point category instruction does not update condition registers but may set exception flags in FPSCR. The conversion uses the current rounding mode from FPSCR.

RT ← CONVERT_DFP_TO_INT128(FRA, FPSCR[RN])

The dcffixqq instruction is commonly used for converting double-precision floating-point numbers to integers, rounding towards zero. Ensure that the input value in RA is within the range representable by a quadword integer to avoid overflow or underflow exceptions. This instruction operates at user privilege level and does not require any specific ordering or alignment of registers.


Vector Insert Halfword from VSR using GPR-specified Right-Index VX-form

Summary: Inserts a halfword from a vector register into another vector register at a position specified by a general-purpose register.

Inserts a halfword-sized element from one vector register into another vector register at a byte position determined by the contents of a general-purpose register. This VMX (AltiVec) category instruction does not affect condition register or status fields. The GPR value specifies the insertion position within the destination vector.

VRT

Target vector register. Bits 48:63 of VSR[VRB+32] are placed into its byte elements 14-index:15-index.

RA

General purpose register whose bits 60:63 supply the byte index, counted from the right end of the target.

VRB

Source vector register supplying the halfword held in its bits 48:63.

index ← GPR[RA].bit[60:63]
VSR[VRT+32].byte[14-index:15-index] ← VSR[VRB+32].bit[48:63]
If index is greater than 14, the result is undefined.

The vinshvrx instruction is useful for selectively updating a halfword within a vector register based on a dynamic index provided by a general-purpose register. Ensure that the right-index specified in the GPR does not exceed the bounds of the 16-byte vector to avoid undefined behavior. This instruction operates at user privilege level and does not generate exceptions under normal circumstances, but incorrect indexing can lead to data corruption.


Summary: Sets the condition register field to 1 if the corresponding fields of two source registers are equal, otherwise sets it to 0.

Performs a bitwise equivalence operation on two condition register fields and places the result in the target condition register field (setting the target bit to 1 if both source bits are equal, 0 otherwise). This Base category instruction operates entirely within the condition register and does not affect other status fields. It is commonly used in conditional branch logic and CR field manipulation.

CR[CRb] ← CR[CRA] XNOR CR[CRB]
CR[CRb] ← (CR[CRA] AND CR[CRB]) OR (NOT CR[CRA] AND NOT CR[CRB])

The creqv instruction is useful for comparing two condition register fields and determining where they are equivalent. It's important to ensure that the source registers (CRA and CRB) are correctly set before using this instruction, as incorrect values can lead to unexpected results in subsequent conditional logic. This instruction operates at the user privilege level and does not generate exceptions under normal circumstances.


Summary: Atomically loads a doubleword from memory.

Atomically loads a doubleword from memory at the address formed by RA + RB and places the result in RT. This instruction provides atomic semantics for load operations on Power10 and later processors. The instruction updates CR0 when Rc=1.

Places a reservation on the cache line containing the effective address. The subsequent store-conditional (stwcx./stdcx. etc.) will fail if the reservation has been lost due to an intervening store from any processor or an exception. Always check the EQ bit in CR0 after the store-conditional.


Summary: Adds the contents of two registers and subtracts one, then updates the condition register.

For addme., the sum of the contents of register RA and RB minus one is placed into register RT.

if 'addme.' then
    RT <- (RA) + (RB) - 1

The addme. instruction adds two registers, subtracts one from the result, and stores it in a third register. It updates the CR0 and XER special registers with the arithmetic results. Ensure that the input registers RA and RB are correctly aligned for optimal performance. This instruction is available at user privilege level.


Store VSX Vector Rightmost Doubleword Indexed X-form

Summary: Stores the rightmost doubleword of a VSX vector register to memory.

Stores the rightmost (low-order) doubleword of the VSX vector register VX to memory at the address formed by RA + RB. This instruction is part of the VSX extension and operates on the 64-bit portion of the 128-bit VSX register.

The stxvrdx instruction is used to store the rightmost doubleword (8 bytes) of a VSX vector register to memory. Ensure that the effective address formed by RA and RB is properly aligned to 8 bytes to avoid alignment faults. This instruction requires supervisor or hypervisor privilege level.


Prefixed Load Floating-Point Double MLS:D-form

Summary: Loads a double-precision floating-point value from memory into a VSX register.

A prefixed load instruction that loads a double-precision floating-point value from memory into a VSX register using a 34-bit immediate displacement. The effective address is formed using a prefix word and suffix word together, supporting a much larger displacement range than standard instructions.

The plfd instruction is used to load a double-precision floating-point value from memory into a VSX register. Ensure that the base and index registers point to a correctly aligned 8-byte boundary to avoid alignment faults. This instruction operates at user privilege level.


Summary: Quantizes a DFP value to an immediate number of decimal digits.

Quantizes a decimal floating-point (DFP) value in FRB to the number of decimal digits specified by immediate UI, storing the result in FRT. This instruction is part of the Decimal Floating-Point category and updates FPSCR and CR1 when Rc=1.

FRT ← Quantize(FRB, UI)
FPSCR ← updated with DFP status
CR1 ← (FRT is NaN, FRT is Infinity, FRT is Zero, FRT is Negative) if Rc=1

The dquai. instruction is used for quantizing DFP values with an immediate quantum, rounding as necessary. Ensure that the immediate field UI specifies a valid quantum and that the source operand FRB is correctly formatted. This instruction operates at the problem state privilege level.


VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate XX3-form

Summary: Performs a VSX Vector 64-bit Floating-Point GER (rank-1 update) with negative multiply and negative accumulate, updating an accumulator register.

Performs a VSX vector 64-bit floating-point outer-product update (GER rank-1 update) with negative multiply and negative accumulate. This MMA instruction is part of the Matrix Multiply Accumulate facility and requires MMA support; it reads two VSX vector registers and updates a 512-bit accumulator.

AT

Target accumulator. ACC[AT] holds a 4x2 matrix of double-precision values.

XAp

Source VSR pair (even/odd). VSR[XAp] and VSR[XAp+1] are concatenated to supply the four row values.

XB

Source VSR supplying the two column values.

vsrcX ← VSR[XAp] || VSR[XAp+1]
vsrcY ← VSR[XB]
do i = 0 to 3
  do j = 0 to 1
    ACC[AT][i].dword[j] ← -( vsrcX.dword[i] × vsrcY.dword[j] + ACC[AT][i].dword[j] )
The product and the accumulated value are negated together.

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.


Floating Convert with round Unsigned Doubleword to Single-Precision format

Summary: Converts an unsigned doubleword integer in a floating-point register to a single-precision floating-point number, rounding the result.

The instruction converts the contents of the source floating-point register (FRB) from an unsigned doubleword integer to a single-precision floating-point number and stores it in the target floating-point register (FRT).

FRT <- ConvertToSinglePrecision(FRB, unsigned)

Use fcfidus. when converting unsigned 64-bit integers to single-precision floats. Ensure the source register contains a valid unsigned integer; otherwise, the result is undefined. This instruction operates at user privilege level and does not raise exceptions for invalid input values.


VSX Scalar Multiply-Add Type-M Single-Precision

Summary: Multiplies two single-precision floating-point values and adds a third, storing the result in the target register (Type-M form).

Performs a scalar single-precision floating-point multiply-add operation (Type-M form) using VSX registers, computing FRB × FRC + FRT and storing the result in FRT. The Type-M form provides additional semantics for rounding and exception handling in VSX scalar operations.

The xsmaddmsp instruction is commonly used for efficient scalar floating-point arithmetic operations, particularly in applications requiring high performance and precision. Ensure that the input registers are properly aligned to avoid potential exceptions. This instruction operates at a privilege level that allows it to be executed by user-mode programs, making it accessible for general-purpose computations. Be aware of the FPSCR register's impact on rounding modes and exception flags.


VSX Vector Negative Multiply-Add Type-M Single-Precision

Summary: Performs a vector single-precision floating-point negative multiply-add operation (Type-M), computing the negation of (XB * XT + XA) for each single-precision element.

Performs a VSX vector single-precision floating-point negative multiply-add operation (Type-M form), computing -(XA + XB × XT) for each single-precision element. This instruction is part of the VSX extension and operates on four single-precision values per 128-bit vector.

XT

Target VSX vector register that serves as both the third multiplicand and destination for negated results.

XA

Source VSX vector register providing the first operand (addend).

XB

Source VSX vector register providing the first multiplier operand.

This instruction is useful for performing complex vector operations involving single-precision floating-point arithmetic. Ensure that all input and output vectors are properly aligned to avoid performance penalties or exceptions. The operation is performed at the user privilege level, so no special privileges are required. Be cautious of potential overflow or underflow conditions during multiplication and addition steps.


VSX Vector Convert with round Unsigned Doubleword to Double-Precision format

Summary: Converts an unsigned doubleword vector element to a double-precision floating-point value.

For each doubleword element in the source vector register VRB, the instruction converts the unsigned 64-bit integer value to a double-precision floating-point value and places the result in the corresponding doubleword element of the target vector register VRT. The conversion uses the current rounding mode. Two elements are processed in parallel, one per doubleword lane.

do i = 0 to 1
  VRT.dword[i] ← ConvertUnsignedFixed64ToFP64(VRB.dword[i])

This instruction is useful for converting unsigned 64-bit integers in a vector to double-precision floating-point numbers. Ensure that the source vector elements are correctly aligned and consider the current rounding mode's effect on conversion results. This operation processes two elements per cycle, making it efficient for bulk conversions.


Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Positive accumulate

Summary: Performs a prefixed masked VSX vector 16-bit floating-point GER rank-2 update with positive multiply and positive accumulate.

A prefixed masked VSX vector 16-bit floating-point outer-product update (GER rank-2 update) with positive multiply and positive accumulate. This 64-bit MMA instruction requires both prefix and suffix encoding and supports register-based masking for selective accumulator updates.

AT

Target accumulator. ACC[AT] holds a 4x4 matrix of 32-bit floating-point values.

XA

Source VSR supplying four words, each holding two 16-bit values.

XMSK

4-bit row mask. Row i is updated only when bit i is 1; a masked-off element is set to zero.

YMSK

4-bit column mask. Column j is updated only when bit j is 1; a masked-off element is set to zero.

PMSK

2-bit product mask selecting which of the two 16-bit lanes contribute to each product.

do i = 0 to 3
  do j = 0 to 3
    if XMSK.bit[i]=1 & YMSK.bit[j]=1 then
      a0 ← (PMSK.bit[0]=1) ? VSR[XA].word[i].hword[0] : 0
      a1 ← (PMSK.bit[1]=1) ? VSR[XA].word[i].hword[1] : 0
      b0 ← (PMSK.bit[0]=1) ? VSR[XB].word[j].hword[0] : 0
      b1 ← (PMSK.bit[1]=1) ? VSR[XB].word[j].hword[1] : 0
      ACC[AT][i].word[j] ← round(a0 × b0 + a1 × b1) + ACC[AT][i].word[j]
    else
      ACC[AT][i].word[j] ← 0


Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) Positive multiply, Positive accumulate

Summary: Performs a prefixed masked VSX vector 8-bit signed/unsigned integer GER rank-4 update with positive multiply and positive accumulate, adding the result to the accumulator.

Performs a prefixed masked VSX vector 8-bit signed/unsigned integer generalized matrix multiply (GER) rank-4 update with positive multiply and positive accumulate semantics, adding the outer product result to the target accumulator register. This instruction is part of the MMA (Matrix-Multiply Assist) extension and uses masking to selectively update the accumulator based on mask fields AT, AX, and BX.

AT

Target accumulator. ACC[AT] holds a 4x4 matrix of 32-bit signed integer values.

XA

Source VSR supplying four words, each holding four signed 8-bit values.

XB

Source VSR supplying four words, each holding four unsigned 8-bit values.

PMSK

4-bit product mask selecting which of the four byte lanes contribute to each product.

do i = 0 to 3
  do j = 0 to 3
    if XMSK.bit[i]=1 & YMSK.bit[j]=1 then
      psum ← 0
      do k = 0 to 3
        if PMSK.bit[k]=1 then
          psum ← psum + EXTS(VSR[XA].word[i].byte[k]) × EXTZ(VSR[XB].word[j].byte[k])
      ACC[AT][i].word[j] ← CHOP32( psum + EXTS(ACC[AT][i].word[j]) )
    else
      ACC[AT][i].word[j] ← 0


VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Negative accumulate

Summary: Performs a rank-2 update of an accumulator register using 16-bit floating-point outer product, with positive multiply and negative accumulate.

Performs a VSX rank-2 generalized matrix multiply (GER) update using 16-bit floating-point elements with positive multiply and negative accumulate semantics. The instruction computes an outer product of two 2-element vectors and subtracts the result from the target accumulator. This is an MMA extension instruction that updates a 2×2 block of the accumulator.

AT

Accumulator target index (specifies which accumulator register in the range ACC0-ACC7)

XA

Source VSX register containing 2 16-bit floating-point elements

AX

Accumulator mask for rows (2 16-bit FP values, positive multiply)

BX

Source mask for columns (2 16-bit FP values, negative accumulate)

acc ← acc - (outer product of 2 16-bit FP elements from XA and 2 from XB)


VSX Scalar Extract Significand Quad-Precision

Summary: Extracts the significand of a quad-precision floating-point number.

Extracts the significand (mantissa) field from a quad-precision (128-bit) floating-point value in the source VSX register and places the extracted significand into the target VSX register. The result preserves the sign of the original significand and right-justifies it within a 64-bit field. The instruction does not modify condition registers or exception flags.

significand ← extract_significand(VRA[0:127])
VRT[0:127] ← sign_extend_to_128bit(significand)

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.


VSX Scalar Negative Multiply-Subtract Type-M Single-Precision

Summary: Performs a scalar negative multiply-subtract operation in single-precision floating-point, storing the result using the Type-M (multiplicand) form where the target register provides one of the multiplicand operands.

Performs a VSX scalar negative multiply-subtract operation on single-precision floating-point values using the Type-M form, where the target register (VRT) provides the subtrahend multiplicand operand. Computes -(VRA × VRT - VRB) and stores the result in VRT. This operation uses the FPSCR rounding mode and may set exception flags FPSCR[VXSNAN, VXISI, VXSQRT, VXCVI, XX, ZX, UX, OX].

XT

Target VSR. In the Type-M form it also supplies the multiplier, and it receives the negated result.

XB

Second source VSR, subtracted from the product.

VSR[XT].dword[0] ← -( VSR[XA].dword[0] × VSR[XT].dword[0] - VSR[XB].dword[0] )
The result is rounded to single precision and FPSCR exception flags are updated.

The xsnmsubmsp instruction is useful for performing complex floating-point calculations involving multiplication, subtraction, and negation in a single operation. Ensure that the target register (XT) is properly aligned and contains valid single-precision floating-point values to avoid undefined behavior. This instruction operates at user privilege level and may raise exceptions if operands are out of range or if there are NaNs involved.


VSX Scalar Negative Multiply-Add Type-M Double-Precision

Summary: Computes the negative of the fused multiply-add of the double-precision floating-point operands, storing the result in the target scalar VSX register (Type-M: target register is used as the addend).

Performs a VSX scalar fused negative multiply-add operation on double-precision floating-point values using the Type-M form, where VRT is used as the addend operand. Computes -(VRA × VRB + VRT) and stores the result in VRT. The instruction operates on scalar elements (bits 0:63 of the VSX registers) and updates FPSCR exception flags accordingly.

VRT[0:63] ← -(VRA[0:63] × VRB[0:63] + VRT[0:63])
Update FPSCR exception flags based on floating-point result

Use xsnmaddmdp for performing a fused multiply-add operation on double-precision floating-point numbers, negating the result. Ensure that the target register provides the addend, and be aware that this instruction operates as a single fused step without intermediate rounding.


VSX Vector Multiply-Subtract Type-M Double-Precision

Summary: Multiplies corresponding double-precision floating-point elements of two VSX registers, subtracts the corresponding element of a third register, and stores the results, using the Type-M (multiplicand) form.

For each of the two double-precision floating-point elements, the instruction multiplies the corresponding elements of VRA and VRT, subtracts the corresponding element of VRB, and places the result into the corresponding element of VRT. This is the Type-M variant, meaning VRT serves as both a source (multiplicand) and the destination register. The operation computes VRT ← (VRA × VRT) - VRB for each element.

do i = 0 to 1
  VRT.fpr[i] ← RND(VRA.fpr[i] × VRT.fpr[i] - VRB.fpr[i])
end

This instruction is commonly used in applications requiring complex floating-point arithmetic operations, such as scientific computations and graphics processing. Ensure that the input registers (VRA, VRT, VRB) are properly aligned to avoid performance penalties or exceptions. The Type-M variant requires careful handling since VRT is both a source and destination register, which can lead to unexpected results if not managed correctly. This instruction operates at user privilege level but may raise exceptions for invalid operations like division by zero or overflow.


Summary: Inserts the biased exponent from a source register into a destination register in quad format.

Inserts a biased exponent from a source general-purpose register into a quad-precision decimal floating-point number, replacing the exponent field of the destination. The instruction requires Decimal Floating-Point (DFP) support. The update form (indicated by the dot) sets condition register field CR0 based on the result classification (zero, normal, infinity, or NaN).

exponent ← RA[32:63]
RT ← insert_exponent_into_DFP_quad(RB, exponent)
if Rc = 1 then CR0 ← classify_DFP_result(RT)


Store Halfword Caching Inhibited Indexed X-form

Summary: Stores a halfword from a general-purpose register to memory, with caching inhibited.

The contents of the lower 16 bits (bits 48:63) of register RS are stored into the halfword in memory addressed by the effective address (EA). The EA is the sum of the contents of register RA and register RB. The store is performed with caching inhibited, meaning the data is written directly to memory bypassing the cache. This instruction is a privileged hypervisor instruction available in Book III.

This instruction is used for storing data directly to memory without caching, which can be useful for ensuring data consistency in hypervisor environments. It requires supervisor privilege level and should be used with caution as it bypasses the cache, potentially affecting performance. Ensure that registers RA and RB contain valid addresses, and RS contains the data to be stored in its lower 16 bits.


Vector Compare Greater Than or Equal Floating-Point

Summary: Compares the elements of two vector registers and sets the result in a third vector register based on whether each element is greater than or equal to the corresponding element in the other vector.

The vcmpgefp. instruction compares corresponding single-precision floating-point elements of vector registers VRA and VRB. For each of the four 32-bit floating-point elements, if the element in VRA is greater than or equal to the corresponding element in VRB, the corresponding element in VRT is set to all 1s (0xFFFFFFFF); otherwise, it is set to all 0s (0x00000000). The dot form (vcmpgefp.) additionally updates the CR6 field of the Condition Register to reflect whether all elements, some elements, or no elements satisfied the comparison.

for i = 0 to 7 do
    if (VRA[i] >= VRB[i]) then
        VRT[i] <- 1
    else
        VRT[i] <- 0
    end if
end for

Use vcmpgefp. to compare four single-precision floating-point elements in two vector registers. Ensure both input vectors are properly aligned and initialized. The dot form updates CR6, indicating the comparison results, which can be useful for conditional branching.


Summary: Multiplies the contents of two registers and places the high-order 64 bits of the product into a target register.

For mulhd., the product of the contents of register RA and RB is computed, and the high-order 64 bits of this product are placed into register RT.

The mulhd. instruction multiplies two 64-bit integers and stores the high 64 bits of the result in a destination register. It does not affect any special registers like CR0 or XER, so developers should be cautious when relying on carry flags or overflow conditions. This instruction is commonly used in cryptographic algorithms where large integer multiplication is required without needing the lower half of the product.


Load Byte and Zero with Update Indexed X-form

Summary: Loads a byte from memory into a register, zero-extends it to 32 bits, and updates the base address.

The sum of the contents of general-purpose register RA and the contents of general-purpose register RB is the effective address (EA). The byte in memory addressed by EA is loaded into the low-order 8 bits of general-purpose register RT, and the remaining bits of RT are cleared to 0. The effective address EA is placed into register RA. If RA = 0 or RA = RT, the instruction form is invalid.

EA ← (RA) + (RB)
RT ← 0x000000 || MEM(EA, 1)
RA ← EA

The base register (RA) is updated with the effective address after the memory access. RA must not be 0 and must differ from the destination register; violating this constraint produces undefined results.


Summary: Performs a bitwise OR operation on the contents of two registers and updates the condition register.

For or., the bitwise OR of the contents of register RA and RB is placed into register RT.

The or. instruction performs a bitwise OR operation between two registers, storing the result in another register. This instruction does not require any special alignment and can be executed at any privilege level. It is commonly used for combining flags or setting specific bits in a register.


Summary: Adds the contents of two registers and updates the condition register.

For add., the sum of the contents of register RA and RB is placed into register RT.

The add. instruction adds the values in registers RA and RB, storing the result in RT. It updates the CR0 and XER special registers to reflect overflow and carry conditions. Ensure that the operands are correctly aligned for optimal performance.


Floating Convert with truncate Double-Precision To Unsigned Word format

Summary: Converts a double-precision floating-point number to an unsigned integer word.

The double-precision floating-point operand in FRB is converted to a 32-bit unsigned integer using truncation (round toward zero), and the result is placed in the low-order 32 bits of FRT. If the operand is a NaN or less than 0, the result is 0. If the operand is greater than the maximum unsigned 32-bit value, the result is 0xFFFFFFFF. The high-order 32 bits of FRT are undefined. The FPSCR is updated to reflect the result of the operation.

if FPSCR[VXSNAN] then FRT ← undefined
else
  src ← (FRB)
  if src is NaN or src < 0 then
    result ← 0x00000000
    FPSCR[VXCVI] ← 1
  else if src > 2^32 - 1 then
    result ← 0xFFFFFFFF
    FPSCR[VXCVI] ← 1
  else
    result ← truncate(src) converted to unsigned 32-bit integer
  FRT[32:63] ← result
  FRT[0:31] ← undefined

The fctiwuz instruction converts a double-precision floating-point number to an unsigned 32-bit integer by truncating towards zero. If the input is NaN, negative, or exceeds the maximum unsigned 32-bit value, it results in 0 or 0xFFFFFFFF respectively, and sets VXCVI in FPSCR. The high-order bits of FRT are undefined after this operation.


Load Floating-Point Single Indexed X-form

Summary: Loads a single-precision floating-point value from memory into a floating-point register.

Loads a single-precision floating-point value from memory into a floating-point register using indexed addressing. The effective address is computed as RA + RB. If RA is 0, the address is simply RB. The instruction does not affect condition registers or exception flags; any floating-point exceptions are determined by the loaded value itself.

EA ← (RA = 0) ? RB : RA + RB
FT ← [EA:EA+3]

The lfsx instruction is commonly used to load single-precision floating-point values from memory into a floating-point register. Ensure that the base and index registers contain valid addresses, and be aware of potential alignment issues that may affect performance or cause exceptions. This instruction operates at user privilege level.


Prefixed Store Floating-Point Double MLS:D-form

Summary: Stores a double-precision floating-point value from a register to memory.

Stores a double-precision floating-point value from a floating-point register to memory using a prefixed instruction format (64 bits total: 32-bit prefix + 32-bit instruction). The addressing mode uses a base register and a displacement that can be formed from the prefix and suffix portions, allowing for a wider displacement range than non-prefixed forms. This instruction does not update condition registers.

displacement ← (prefix_immediate || suffix_immediate) [sign-extended to 64 bits]
EA ← RA + displacement
[EA:EA+7] ← FRT[0:63]

The pstfd instruction is used to store a double-precision floating-point value from a register into memory. Ensure that the effective address calculation does not result in an overflow or underflow. This instruction requires the EA to be aligned on an 8-byte boundary for optimal performance and correctness.


Store Word Caching Inhibited Indexed X-form

Summary: Stores a word from a source register to memory with caching inhibited.

Stores a 32-bit word from register RS to memory at the address formed by adding RA and RB, with caching inhibited to bypass L1 cache. This instruction is used for I/O operations and memory-mapped device access where cache coherency is not desired. No condition registers or status fields are modified.

The stwcix instruction is used to store a 32-bit word from a register to memory with caching inhibited, which can be useful for ensuring data consistency between the CPU and external storage. This instruction requires hypervisor privilege (level HV) and should be used sparingly due to its performance impact. Ensure that the destination address is properly aligned to avoid potential exceptions.


Vector Extract Unsigned Word to GPR using GPR-specified Right-Index VX-form

Summary: Extracts an unsigned word from a vector register and places it into a general-purpose register.

Extracts a 32-bit unsigned word from vector register RB using a byte-offset index contained in GPR RA, and places the extracted value into GPR VRT. The index specifies which 4-byte element to extract from the 128-bit vector. This instruction requires VMX/AltiVec support and no condition flags are affected.

Use vextuwrx to extract a 32-bit unsigned word from a vector register using a right-index specified by a GPR. Ensure the index is correctly calculated to avoid out-of-bounds access. The result is zero-extended to 64 bits before being stored in the target GPR.


Vector Multiply-by-10 Extended & write Carry-out Unsigned Quadword

Summary: Multiplies the unsigned quadword integer in vector register VA by 10, adds the least-significant bit of VB as a carry-in digit, and writes the carry-out of the result to vector register VX.

Multiplies the unsigned 128-bit quadword in vector register VA by 10, adds the least-significant bit of VB as a carry-in, and writes only the carry-out (overflow) of the result to vector register VX. The result discards the low 128 bits, retaining only the high carry. This instruction requires VMX/AltiVec support and no condition registers are modified.

product ← (VA) × 10 + ((VB)[127] as carry-in)
VX ← product[128:191]

This instruction is ideal for high-performance multi-precision decimal arithmetic, especially when performing chained multiply-by-10 operations. Ensure that the input values in VA and VB are correctly aligned as unsigned 128-bit integers to avoid unexpected results. The carry-out written to VX should be used as the extended carry-in for subsequent operations to maintain precision.


Vector Pack Signed Word Unsigned Saturate

Summary: Packs signed words from two source vectors into one destination vector with unsigned saturation.

Packs signed 32-bit word elements from vectors VSRA and VSRB into 16-bit unsigned elements in VRT, saturating to the unsigned 16-bit range [0, 65535] if any source element overflows. The operation interleaves words from VSRA and VSRB into the result. This instruction requires VMX/AltiVec support and no condition registers are modified.

The vpkswus instruction is useful for efficiently packing and converting signed 32-bit integers to unsigned 16-bit integers with saturation. Ensure that the input vectors are correctly aligned and that the operation does not exceed the bounds of the target vector register. This instruction operates at user privilege level and will raise an exception if any invalid operand access occurs.


Summary: Aborts any in-progress copy-paste operation, discarding any pending copy target set by a previous Copy instruction.

Aborts any in-progress copy-paste operation initiated by a previous Copy instruction, discarding the pending copy buffer and resetting the copy-paste state. This is a privileged Base instruction that has no operands and does not modify any condition or status registers.

Use cpabort to safely terminate an ongoing copy-paste sequence, preventing any subsequent paste operations from completing with the reserved data. This is useful in error handling scenarios where a copy operation needs to be aborted without allowing further processing of the copied data. Ensure that cpabort is called at the appropriate privilege level and consider its impact on performance if used frequently.


Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive multiply, Positive accumulate

Summary: Performs a prefixed masked VSX vector 32-bit floating-point GER rank-1 update with positive multiply and positive accumulate.

A prefixed MMA instruction that performs a masked rank-1 matrix update using 32-bit floating-point elements, with positive multiply (no sign flip) and positive accumulate semantics. The prefix word controls masking and additional configuration. This instruction requires MMA support and updates the accumulator register; no condition registers are directly modified by this operation.

Accumulator ← Accumulator + (masked_multiply_by_vsrX(XA) ⊗ masked_multiply_by_vsrY(XB))

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.


Summary: Rerounds a decimal floating-point number to the specified precision.

Rerounds a decimal floating-point number from FRB to the precision specified by the rounding mode control, placing the result in FRA and setting CR1 based on the result (if Rc=1). The instruction handles overflow, underflow, and inexact exceptions according to FPSCR settings. This instruction requires Decimal Floating-Point support and modifies CR1 and FPSCR when Rc is set.

FRA

Source Floating-Point Register containing the reference significance

FRB

Source Floating-Point Register containing the value to be rounded

FRA ← dround(FRB, RMC)
if Rc = 1 then CR1 ← (FRA_exception_flags)

The drrnd instruction is used to reround a decimal floating-point number in register RA according to the rounding mode specified in the FPSCR. Ensure that the FPSCR's rounding mode is set appropriately before executing this instruction to achieve the desired precision. This instruction operates at user privilege level and does not raise exceptions under normal circumstances, but it may alter the contents of CR0 if an exception occurs during execution.


Load Vector Element Halfword Indexed X-form

Summary: Loads a halfword element from memory into the corresponding halfword element of a vector register, with the address computed as the sum of RA and RB, aligned to a halfword boundary.

Loads a halfword (16-bit) element from memory at the address formed by RA + RB into the corresponding halfword element of vector register VRT. The effective address is aligned to a halfword boundary. This is a VMX/AltiVec instruction with no effect on condition or status registers.

EA ← (RA) + (RB)
VRT[element] ← MEM(EA, 2)

The lvehx instruction loads a halfword from memory into a specific element of a vector register. Ensure the effective address is halfword-aligned to avoid alignment faults. The operation does not require any special privileges, but it may raise an exception if the access violates memory protection rules.


Summary: Loads a 128-bit VSX vector from memory into a VSX register using a prefixed instruction with a large displacement.

Loads a 128-bit VSX vector from memory into VSX register RT using a prefixed instruction with a 34-bit signed displacement. The address is computed as RA + displacement (scaled by 4). This is a VSX instruction requiring the VSX category and the Prefixed instruction set.

EA ← (RA) + (DQ || Disp)
RT ← MEM(EA, 16)

The plxv instruction is used for loading a 128-bit VSX vector from memory into a target register, using an extended displacement field provided by the prefix word. Ensure that the base address register (RA) contains the correct pointer or is zero if no base address is needed. This instruction requires the VSX facility and is available in PowerISA v3.1 and later.


Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate

Summary: Performs a prefixed masked VSX vector 64-bit floating-point GER (rank-1 update) with negative multiply and negative accumulate.

A prefixed MMA instruction that performs a masked 64-bit floating-point GER (generalized matrix element rank-1 update) with negative multiply and negative accumulate into an accumulator. The operation updates a 4×4 matrix accumulator using VSX registers with optional row and column masking. This instruction requires MMA support and updates FPSCR.

AT

Target accumulator. ACC[AT] holds a 4x2 matrix of double-precision values.

XAp

Source VSR pair (even/odd). VSR[XAp] and VSR[XAp+1] are concatenated to supply the four row values.

XB

Source VSR supplying the two column values.

XMSK

4-bit row mask. Row i is updated only when bit i is 1; a masked-off element is set to zero.

YMSK

2-bit column mask. Column j is updated only when bit j is 1; a masked-off element is set to zero.

vsrcX ← VSR[XAp] || VSR[XAp+1]
vsrcY ← VSR[XB]
do i = 0 to 3
  do j = 0 to 1
    if XMSK.bit[i]=1 & YMSK.bit[j]=1 then
      ACC[AT][i].dword[j] ← -( vsrcX.dword[i] × vsrcY.dword[j] + ACC[AT][i].dword[j] )
    else
      ACC[AT][i].dword[j] ← 0


Prefixed Store Floating-Point Single MLS:D-form

Summary: Stores a single-precision floating-point value from a register to memory.

The double-precision floating-point value in register FRS is converted to single-precision and stored as a 32-bit single-precision value at the effective address (EA). The EA is formed by adding the sign-extended 34-bit immediate displacement D to the contents of general-purpose register RA (or zero if RA=0). This is the prefixed form of the stfs instruction, allowing a larger displacement field than the non-prefixed variant.

EA ← (RA|0) + D
MEM(EA, 4) ← SINGLE(FRS)

The pstfs instruction is useful for storing single-precision floating-point values with an extended displacement. Ensure that the EA calculation does not result in an invalid memory address to avoid exceptions. This instruction operates at user privilege level and requires proper alignment of the EA for optimal performance.


Summary: Shifts the contents of a doubleword register right algebraically, shifting in sign bits.

The contents of register RA are shifted right by the number of bits specified by the low-order 7 bits of register RB. Bits shifted out of position 63 are lost. Sign bits are shifted into the high-order bits, replicating the sign bit (RA[0]). If the shift amount is greater than 63, each bit of the result is equal to the sign bit of RA. The XER[CA] bit is set if the result is negative and any '1' bits are shifted out; otherwise XER[CA] is cleared. If the Rc bit is set, CR0 is updated.

n ← rB[58:63]
if rB[57] = 0 then
   r ← ROTL64(rA, 64-n)
   mask ← MASK(n, 63)
   rT ← r & mask | (64)rA[0] & ¬mask
else
   rT ← (64)rA[0]
XER[CA] ← rA[0] & (rT ≠ rA)
XER[CA32] ← rA[0] & (rT[32:63] ≠ rA[32:63])

The srad. instruction is commonly used for right-shifting signed integers while preserving the sign bit. Be cautious with shift amounts greater than 63, as they result in a full replication of the sign bit. The XER[CA] flag indicates if negative bits were shifted out, which can be useful for overflow detection. Ensure that register RB contains a valid shift amount to avoid unexpected results.


Summary: Stores a vector element to memory, with the last element being stored if the index is out of bounds.

Stores a vector from register VS to memory at the address formed by RA + RB. The address is aligned to the vector element size. This is a Base category instruction with no effect on condition or status registers.

Use stvxl when storing vector data with a 'last touch' hint, potentially reducing cache line allocations. Ensure RA and RB are correctly set to form the aligned 16-byte address. This instruction is useful for optimizing memory usage in performance-critical sections.


VSX Vector Convert with round Unsigned Doubleword to Single-Precision format

Summary: Converts an unsigned doubleword to a single-precision floating-point value with rounding.

Converts a 64-bit unsigned doubleword integer (in the doubleword elements of VS64) to 32-bit single-precision floating-point format with rounding and stores the result in the corresponding word elements of VS32. This is a VSX instruction that performs IEEE-compliant rounding and may update FPSCR.

for i in 0 to 1:
  VS32[2*i:2*i+1] ← CONVERT_UNSIGNED_DWORD_TO_SINGLE_PRECISION_ROUNDED(VS64[i])

This instruction is useful for converting unsigned 64-bit integers to single-precision floating-point numbers. Ensure that the source vector elements are properly aligned and consider the current rounding mode's effect on conversion results. The target vector register will have its lower words zeroed out, so handle this if you need to preserve data in those positions.


VSX Vector Negative Multiply-Subtract Type-M Double-Precision

Summary: Performs a negative multiply-subtract operation on double-precision floating-point values.

For each double-precision floating-point element, the instruction multiplies the corresponding elements of VRA and VRT, subtracts the corresponding element of VRB from the product, negates the result, and stores it in VRT. This is the Type-M variant, meaning VRT serves as both a source operand (multiplicand) and the destination register. The operation is performed in double-precision floating-point arithmetic with IEEE 754 rounding rules applied.

do i = 0 to 1
  VRT.dword[i] ← RoundFP64(-(FP64(VRA.dword[i]) × FP64(VRT.dword[i])) - FP64(VRB.dword[i]))

This instruction is commonly used in scenarios requiring complex floating-point arithmetic operations, such as in scientific computations or graphics processing. Be cautious of potential overflow or underflow conditions due to the nature of double-precision multiplication and subtraction. Ensure that VRT is properly aligned for optimal performance, as misalignment can lead to significant slowdowns. This instruction operates at user privilege level but may generate exceptions if invalid operations occur, such as division by zero or NaN results.