Summary: Extract an unsigned bitfield from the first input using field offset and size encoded in the second input, store the result into a scalar register…

Extract an unsigned bitfield from the first input using field offset and size encoded in the second input, store the result into a scalar register and set SCC iff the result is nonzero.


Summary: Calculate a bitfield mask given a field offset and size and store the result in a scalar register.


Summary: Extract a bit from the first scalar input based on an index in the second scalar input, and set SCC to 1 iff the extracted bit is equal to 0.


Summary: Extract a bit from the first scalar input based on an index in the second scalar input, and set SCC to 1 iff the extracted bit is equal to 1.


Summary: Substitute each bit of a 32 bit scalar input with two instances of itself and store the result into a 64 bit scalar register.

This opcode can be used to convert a quad mask into a pixel mask; given quad mask in s0, the following sequence produces a pixel mask in s2: s_bitreplicate_b64 s2, s0 s_bitreplicate_b64 s2, s2 To perform the inverse operation see S_QUADMASK_B64.


Summary: Given a bit offset in a scalar input, set the indicated bit in the destination scalar register to 0.


Summary: Given a bit offset in a scalar input, set the indicated bit in the destination scalar register to 1.


Summary: Unconditional relative branch.

Jump to a constant offset relative to the current PC.

s_branch  label   // unconditional jump to label


Summary: Reverse the order of bits in a scalar input and store the result into a scalar register.


Summary: Prefetch data into the scalar data cache, relative to a base address provided in a resource descriptor constant.


Summary: AMDGPU SOPK scalar instruction operating on i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Conditional branch join point (end of conditional branch block). S0 is saved CSP value. See S_CBRANCH_G_FORK and S_CBRANCH_I_FORK for related instructions.

saved_csp = S0.u32;
if WAVE_MODE.CSP.u32 == saved_csp then
PC += 4LL;
// Second time to JOIN: continue with program.
else
WAVE_MODE.CSP -= 3'1U;
// First time to JOIN; jump to other FORK path.
{ PC, EXEC } = SGPR[WAVE_MODE.CSP.u32 * 4U].b128;
// Read 128 bits from 4 consecutive SGPRs.
endif


Summary: Conditional relative branch, taken when the SCC (scalar condition code) flag is set.

If SCC is 1 then jump to a constant offset relative to the current PC.

if (SCC == 1) PC = PC + 4 + signed_offset * 4.

s_cbranch_scc1  label   // jump to label if SCC == 1


Summary: Round the half-precision float input up to next integer and store the result in floating point format into a scalar register.


Summary: Round the single-precision float input up to next integer and store the result in floating point format into a scalar register.


Count the number of leading bits that are the same as the sign bit of a scalar input and store the result into a scalar register. Store -1 if all input bits are the same.


Count the number of leading "0" bits before the first "1" in a scalar input and store the result into a scalar register. Store -1 if there are no "1" bits.


Summary: Move scalar input into a scalar register iff SCC is nonzero.


Summary: Move the sign extension of a literal 16-bit constant into a scalar register iff SCC is nonzero.

if SCC then
D0.i32 = 32'I(signext(S0.i16))
endif


Summary: Set SCC to 1 iff the first scalar input is equal to the second scalar input.


Summary: Scalar signed-32-bit equality compare, result written to SCC.


Note that S_CMP_EQ_I32 and S_CMP_EQ_U32 are identical opcodes, but both are provided for symmetry.


Summary: Set SCC to 1 iff the first scalar input is greater than or equal to the second scalar input.


Summary: Set SCC to 1 iff the first scalar input is greater than the second scalar input.


Summary: Set SCC to 1 iff the first scalar input is less than or equal to the second scalar input.


Summary: Set SCC to 1 iff the first scalar input is less than or greater than the second scalar input.


Note that S_CMP_LG_I32 and S_CMP_LG_U32 are identical opcodes, but both are provided for symmetry.


Summary: Set SCC to 1 iff the first scalar input is less than the second scalar input.


Summary: Set SCC to 1 iff the first scalar input is not equal to the second scalar input.


Summary: Set SCC to 1 iff the first scalar input is not greater than or equal to the second scalar input.


Summary: Set SCC to 1 iff the first scalar input is not greater than the second scalar input.


Summary: Set SCC to 1 iff the first scalar input is not less than or equal to the second scalar input.


Summary: Set SCC to 1 iff the first scalar input is not less than or greater than the second scalar input.


Summary: Set SCC to 1 iff the first scalar input is not less than the second scalar input.


Summary: Set SCC to 1 iff the first scalar input is orderable to the second scalar input.


Summary: Set SCC to 1 iff the first scalar input is not orderable to the second scalar input.


Summary: Set SCC to 1 iff scalar input is equal to the sign extension of a literal 16-bit constant.


Summary: Set SCC to 1 iff scalar input is equal to the zero extension of a literal 16-bit constant.


Summary: Set SCC to 1 iff scalar input is greater than or equal to the sign extension of a literal 16-bit constant.


Summary: Set SCC to 1 iff scalar input is greater than or equal to the zero extension of a literal 16-bit constant.


Summary: Set SCC to 1 iff scalar input is greater than the sign extension of a literal 16-bit constant.


Summary: Set SCC to 1 iff scalar input is greater than the zero extension of a literal 16-bit constant.


Summary: Set SCC to 1 iff scalar input is less than or equal to the sign extension of a literal 16-bit constant.


Summary: Set SCC to 1 iff scalar input is less than or equal to the zero extension of a literal 16-bit constant.


Summary: Set SCC to 1 iff scalar input is less than or greater than the sign extension of a literal 16-bit constant.


Summary: Set SCC to 1 iff scalar input is less than or greater than the zero extension of a literal 16-bit constant.


Summary: Set SCC to 1 iff scalar input is less than the sign extension of a literal 16-bit constant.


Summary: Set SCC to 1 iff scalar input is less than the zero extension of a literal 16-bit constant.


Summary: Select the first input if SCC is true otherwise select the second input, then store the selected input into a scalar register.


Count the number of trailing "0" bits before the first "1" in a scalar input and store the result into a scalar register. Store -1 if there are no "1" bits in the input.


Summary: Convert from a single-precision float input to a half-precision float value and store the result into a scalar register.


Summary: Convert from a half-precision float input to a single-precision float value and store the result into a scalar register.


Summary: Convert from a signed 32-bit integer input to a single-precision float value and store the result into a scalar register.


Summary: Convert from an unsigned 32-bit integer input to a single-precision float value and store the result into a scalar register.


Summary: Convert from a half-precision float value in the high 16 bits of a scalar input to a single-precision float value and store the result into a scalar…

Convert from a half-precision float value in the high 16 bits of a scalar input to a single-precision float value and store the result into a scalar register.


Summary: Convert from a single-precision float input to a signed 32-bit integer value and store the result into a scalar register.


Summary: Convert two single-precision float inputs into a packed half-precision float result using round toward zero semantics (ignore the current rounding…

Convert two single-precision float inputs into a packed half-precision float result using round toward zero semantics (ignore the current rounding mode), and store the result into a scalar register.


Summary: Convert from a single-precision float input to an unsigned 32-bit integer value and store the result into a scalar register.


Summary: Invalidate the scalar (L0) data cache.

Invalidate the scalar (L0) data cache.


Summary: Invalidate the scalar (L0) data cache volatile lines.


Summary: Write back dirty data in the scalar (L0) data cache.


Summary: Write back dirty data in the scalar (L0) data cache volatile lines.


Summary: Decrement performance counter specified in SIMM16[3:0] by 1.


Summary: Insert delay between dependent SALU/VALU instructions.


Summary: End of program; terminate wavefront.

End of program; terminate wavefront. The hardware implicitly executes S_WAITCNT 0 before executing this instruction. See S_ENDPGM_SAVED for the context-switch version of this instruction.


End of program; signal that a wave has been saved by the context-switch trap handler and terminate wavefront. The hardware implicitly executes S_WAITCNT 0 before executing this instruction. See S_ENDPGM for additional variants.


Count the number of trailing "1" bits before the first "0" in a scalar input and store the result into a scalar register. Store -1 if there are no "0" bits in the input.

tmp = -1;
// Set if no zeros are found
for i in 0 : 31 do
// Search from LSB
if S0.u32[i] == 1'0U then
tmp = i;
break
endif
endfor;
D0.i32 = tmp


tmp = -1;
// Set if no zeros are found
for i in 0 : 63 do
// Search from LSB
if S0.u64[i] == 1'0U then
tmp = i;
break
endif
endfor;
D0.i32 = tmp


Count the number of trailing "0" bits before the first "1" in a scalar input and store the result into a scalar register. Store -1 if there are no "1" bits in the input.

tmp = -1;
// Set if no ones are found
for i in 0 : 31 do
// Search from LSB
if S0.u32[i] == 1'1U then
tmp = i;
break
endif
endfor;
D0.i32 = tmp


tmp = -1;
// Set if no ones are found
for i in 0 : 63 do
// Search from LSB
if S0.u64[i] == 1'1U then
tmp = i;
break
endif
endfor;
D0.i32 = tmp


Count the number of leading bits that are the same as the sign bit of a scalar input and store the result into a scalar register. Store -1 if all input bits are the same.

tmp = -1;
// Set if all bits are the same
for i in 1 : 31 do
// Search from MSB
if S0.u32[31 - i] != S0.u32[31] then
tmp = i;
break
endif
endfor;
D0.i32 = tmp


Count the number of leading "0" bits before the first "1" in a scalar input and store the result into a scalar register. Store -1 if there are no "1" bits.

tmp = -1;
// Set if no ones are found
for i in 0 : 31 do
// Search from MSB
if S0.u32[31 - i] == 1'1U then
tmp = i;
break
endif
endfor;
D0.i32 = tmp


tmp = -1;
// Set if no ones are found
for i in 0 : 63 do
// Search from MSB
if S0.u64[63 - i] == 1'1U then
tmp = i;
break
endif
endfor;
D0.i32 = tmp


tmp = -1;
// Set if all bits are the same
for i in 1 : 63 do
// Search from MSB
if S0.u64[63 - i] != S0.u64[63] then
tmp = i;
break
endif
endfor;
D0.i32 = tmp


Summary: Round the half-precision float input down to previous integer and store the result in floating point format into a scalar register.


Summary: Round the single-precision float input down to previous integer and store the result in floating point format into a scalar register.


Summary: AMDGPU SOP1 scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU SOP1 scalar instruction operating on i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU SOP1 scalar instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Return the wave's ID within a workgroup 0-(N-1). Return zero if wave is not in a workgroup. ID reflects the order in which waves were created within each workgroup.


Store the address of the next instruction to a scalar register. The byte address of the instruction immediately following this instruction is saved to the destination.


Summary: Invalidate the GL1 cache only.

Invalidate the GL1 cache only.


Invalidate entire first level instruction cache. There must be 16 separate S_NOP instructions or a jump/branch instruction after this instruction to ensure the internal instruction buffers are also invalidated.


Summary: Increment performance counter specified in SIMM16[3:0] by 1.


Summary: Load one 32-bit dword from memory into a scalar register, wavefront-uniform.

Load 32 bits of data from the scalar memory into a scalar register.

SDST = *(SBASE + offset); intended for uniform (not per-lane-varying) addresses such as descriptors and kernel arguments.


Summary: Calculate the logical shift left of the first input by 1, then add the second input, store the result into a scalar register and set SCC iff the…

Calculate the logical shift left of the first input by 1, then add the second input, store the result into a scalar register and set SCC iff the summation results in an unsigned overflow.


Summary: Calculate the logical shift left of the first input by 2, then add the second input, store the result into a scalar register and set SCC iff the…

Calculate the logical shift left of the first input by 2, then add the second input, store the result into a scalar register and set SCC iff the summation results in an unsigned overflow.


Summary: Calculate the logical shift left of the first input by 3, then add the second input, store the result into a scalar register and set SCC iff the…

Calculate the logical shift left of the first input by 3, then add the second input, store the result into a scalar register and set SCC iff the summation results in an unsigned overflow.


Summary: Calculate the logical shift left of the first input by 4, then add the second input, store the result into a scalar register and set SCC iff the…

Calculate the logical shift left of the first input by 4, then add the second input, store the result into a scalar register and set SCC iff the summation results in an unsigned overflow.


Summary: Given a shift count in the second scalar input, calculate the logical shift left of the first scalar input, store the result into a scalar register…

Given a shift count in the second scalar input, calculate the logical shift left of the first scalar input, store the result into a scalar register and set SCC iff the result is nonzero.


Summary: Given a shift count in the second scalar input, calculate the logical shift right of the first scalar input, store the result into a scalar register…

Given a shift count in the second scalar input, calculate the logical shift right of the first scalar input, store the result into a scalar register and set SCC iff the result is nonzero.


Summary: Select the maximum of two half-precision float inputs and store the selected value into a scalar register.


Summary: Select the maximum of two single-precision float inputs and store the selected value into a scalar register.


Summary: Select the maximum of two signed 32-bit integer inputs, store the selected value into a scalar register and set SCC iff the first value is selected.


Summary: Select the IEEE maximumNumber() of two half-precision float inputs and store the selected value into a scalar register.


Summary: Select the IEEE maximumNumber() of two single-precision float inputs and store the selected value into a scalar register.


Summary: Select the maximum of two unsigned 32-bit integer inputs, store the selected value into a scalar register and set SCC iff the first value is selected.


Summary: Select the IEEE maximum() of two half-precision float inputs and store the selected value into a scalar register.


Summary: Select the IEEE maximum() of two single-precision float inputs and store the selected value into a scalar register.


Summary: Return current 64-bit RTC.

Return current 64-bit RTC.


Summary: Return current 64-bit timestamp.

Return current 64-bit timestamp.


Summary: Select the minimum of two half-precision float inputs and store the selected value into a scalar register.


Summary: Select the minimum of two single-precision float inputs and store the selected value into a scalar register.


Summary: Select the minimum of two signed 32-bit integer inputs, store the selected value into a scalar register and set SCC iff the first value is selected.


Summary: Select the IEEE minimumNumber() of two half-precision float inputs and store the selected value into a scalar register.


Summary: Select the IEEE minimumNumber() of two single-precision float inputs and store the selected value into a scalar register.


Summary: Select the minimum of two unsigned 32-bit integer inputs, store the selected value into a scalar register and set SCC iff the first value is selected.


Summary: Select the IEEE minimum() of two half-precision float inputs and store the selected value into a scalar register.


Summary: Select the IEEE minimum() of two single-precision float inputs and store the selected value into a scalar register.


Summary: AMDGPU SOPP scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Move scalar input into a scalar register.


Summary: Sign extend a literal 16-bit constant and store the result into a scalar register.


Summary: Move data from a scalar input into a relatively-indexed scalar register.

addr = DST.u32;
// Raw value from instruction
addr += M0.u32[31 : 0];
SGPR[addr].b32 = S0.b32

Example: The following instruction sequence performs the move s15 <= s7: s_mov_b32 m0, 10 s_movreld_b32 s5, s7


Move data from a scalar input into a relatively-indexed scalar register. The index in M0.u and the operand address in DST.u must be even for this operation.

addr = DST.u32;
// Raw value from instruction
addr += M0.u32[31 : 0];
SGPR[addr].b64 = S0.b64


Summary: Move data from a relatively-indexed scalar register into another scalar register.

addr = SRC0.u32;
// Raw value from instruction
addr += M0.u32[31 : 0];
D0.b32 = SGPR[addr].b32

Example: The following instruction sequence performs the move s5 <= s17: s_mov_b32 m0, 10 s_movrels_b32 s5, s7


Move data from a relatively-indexed scalar register into another scalar register. The index in M0.u and the operand address in SRC0.u must be even for this operation.

addr = SRC0.u32;
// Raw value from instruction
addr += M0.u32[31 : 0];
D0.b64 = SGPR[addr].b64


Summary: Move data from a relatively-indexed scalar register into another relatively-indexed scalar register, using different offsets for each index.


Summary: Multiply two floating point inputs and store the result into a scalar register.


Summary: Multiply two signed integers and store the high 32 bits of the result into a scalar register.


Summary: Multiply two unsigned integers and store the high 32 bits of the result into a scalar register.


Summary: Multiply two 32-bit signed scalar operands, wavefront-uniform, low 32 bits of the product.

Multiply two signed 32-bit integer inputs and store the result into a scalar register.


Summary: Multiply two unsigned 64-bit integer inputs and store the result into a scalar register.


Summary: Multiply a scalar input with the sign extension of a literal 16-bit constant and store the result into a scalar register.


Summary: Calculate bitwise NAND on two scalar inputs, store the result into a scalar register and set SCC if the result is nonzero.


Summary: Calculate bitwise NAND on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is…

Calculate bitwise NAND on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register.


saveexec = EXEC.u64;
EXEC.u64 = ~(S0.u64 & EXEC.u64);
D0.u64 = saveexec.u64;
SCC = EXEC.u64 != 0ULL


Summary: Do nothing.

Do nothing. Delay issue of next instruction by a small, fixed amount. Insert 0..15 wait states based on SIMM16[3:0]. 0x0 means the next instruction can issue on the next clock, 0xf means the next instruction can issue 16 clocks later.

for i in 0U : SIMM16.u16[3 : 0].u32 do
nop()
endfor

Examples: s_nop 0         // Wait 1 cycle. s_nop 0xf       // Wait 16 cycles.


Summary: Calculate bitwise NOR on two scalar inputs, store the result into a scalar register and set SCC if the result is nonzero.


Summary: Calculate bitwise NOR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is…

Calculate bitwise NOR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register.


saveexec = EXEC.u64;
EXEC.u64 = ~(S0.u64 | EXEC.u64);
D0.u64 = saveexec.u64;
SCC = EXEC.u64 != 0ULL


Summary: Calculate bitwise negation on a scalar input, store the result into a scalar register and set SCC iff the result is nonzero.


Summary: Calculate bitwise OR on two scalar inputs, store the result into a scalar register and set SCC iff the result is nonzero.


Summary: Calculate bitwise OR on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the…

Calculate bitwise OR on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register.


Summary: Calculate bitwise OR with the first input and the negation of the second input, store the result into a scalar register and set SCC if the result is…

Calculate bitwise OR with the first input and the negation of the second input, store the result into a scalar register and set SCC if the result is nonzero.


Summary: Calculate bitwise OR on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the…

Calculate bitwise OR on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register.


Summary: Calculate bitwise OR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is…

Calculate bitwise OR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register.


Calculate bitwise OR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. The original EXEC mask is saved to the destination SGPRs before the bitwise operation is performed.

saveexec = EXEC.u64;
EXEC.u64 = (S0.u64 | EXEC.u64);
D0.u64 = saveexec.u64;
SCC = EXEC.u64 != 0ULL


Calculate bitwise OR on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. The original EXEC mask is saved to the destination SGPRs before the bitwise operation is performed.

saveexec = EXEC.u64;
EXEC.u64 = (~S0.u64 | EXEC.u64);
D0.u64 = saveexec.u64;
SCC = EXEC.u64 != 0ULL


Calculate bitwise OR on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. The original EXEC mask is saved to the destination SGPRs before the bitwise operation is performed.

saveexec = EXEC.u64;
EXEC.u64 = (S0.u64 | ~EXEC.u64);
D0.u64 = saveexec.u64;
SCC = EXEC.u64 != 0ULL


Summary: Pack two 16-bit scalar values into a scalar register.


Summary: Prefetch data into the scalar data cache, relative to a base address provided.


Summary: Prefetch data into the scalar data cache, relative to the current PC address.


Summary: Prefetch instructions into the shader instruction cache, relative to a base address provided.


Summary: Prefetch instructions into the shader instruction cache, relative to the current PC address.


Summary: Reduce a pixel mask from the scalar input into a quad mask, store the result in a scalar register and set SCC iff the result is nonzero.

To perform the inverse operation see S_BITREPLICATE_B64_B32.


tmp = 0ULL;
for i in 0 : 15 do
tmp[i] = S0.u64[i * 4 +: 4] != 0ULL
endfor;
D0.u64 = tmp;
SCC = D0.u64 != 0ULL


Summary: Return from the exception handler.

Return from the exception handler. Clear the wave's PRIV bit and then jump to an address specified by the scalar input. The argument is a byte address of the instruction to jump to; this address is likely derived from the state passed into the trap handler. This instruction may only be used within a trap handler.


Summary: AMDGPU SOP1 scalar instruction operating on i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Round the half-precision float input to the nearest even integer and store the result in floating point format into a scalar register.


Summary: Round the single-precision float input to the nearest even integer and store the result in floating point format into a scalar register.


Summary: Send a message upstream to graphics control hardware. SIMM16[9:0] contains the message type.


Summary: Send a message to upstream control hardware and then HALT the wavefront; see S_SENDMSG for details.


Summary: Set the index used in vector GPR indexing. S_SET_GPR_IDX_ON, S_SET_GPR_IDX_OFF, S_SET_GPR_IDX_MODE and S_SET_GPR_IDX_IDX are related instructions.


Summary: Modify the mode used for vector GPR indexing.

The raw contents of the source field are read and used to set the enable bits. SIMM16[0] = VSRC0_REL,
SIMM16[1] = VSRC1_REL, SIMM16[2] = VSRC2_REL and SIMM16[3] = VDST_REL.
S_SET_GPR_IDX_ON, S_SET_GPR_IDX_OFF, S_SET_GPR_IDX_MODE and S_SET_GPR_IDX_IDX are related
instructions.
M0[15 : 12] = SIMM16.u16[3 : 0].b4


Summary: Clear GPR indexing mode.

Clear GPR indexing mode. Vector operations after this do not perform relative GPR addressing regardless of the contents of M0. This instruction does not modify M0. S_SET_GPR_IDX_ON, S_SET_GPR_IDX_OFF, S_SET_GPR_IDX_MODE and S_SET_GPR_IDX_IDX are related instructions.


Summary: Change instruction prefetch mode. This controls how many cachelines ahead of the current PC the shader attempts to prefetch.


Summary: AMDGPU SOPP scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Set or clear the HALT status bit.

Set or clear the HALT status bit.

Set HALT bit to value of SIMM16[0]; 1 = halt, 0 = clear HALT bit. The halt flag is ignored while PRIV == 1 (inside
trap handlers) but the shader halts after the handler returns if HALT is still set at that time.


Summary: Kill this wave if the least significant bit of the immediate constant is 1. Used primarily for debugging kill wave host command behavior.


Summary: Jump to an address specified in a scalar register. The argument is a byte address of the instruction to jump to.


Summary: Change wave user priority.

Change wave user priority.

User settable wave priority is set to SIMM16[1:0]. 0 = lowest, 3 = highest. The overall wave priority is
{SPIPrio[1:0], UserPrio[1:0], WaveAge[3:0]}.


Summary: Enables or disables VSKIP mode.

Enables or disables VSKIP mode. When VSKIP is enabled, no VOP*/M*BUF/MIMG/DS/FLAT instructions are issued. Note that VSKIPped memory instructions do not manipulate the waitcnt counters; as a result, if there are outstanding memory requests the shader may want to issue S_WAITCNT 0 prior to enabling VSKIP, otherwise the shader must be careful not to count VSKIPped instructions in waitcnt calculations.

s_setvskip 1, 0     // Enable vskip mode.
s_setvskip 0, 0     // Disable vskip mode.


Summary: Sign extend a signed 16 bit scalar input to 32 bits and store the result into a scalar register.


Summary: Sign extend a signed 8 bit scalar input to 32 bits and store the result into a scalar register.


Cause a wave to sleep for up to ~8000 clocks. The wave sleeps for (64*(SIMM16[6:0]-1) .. 64*SIMM16[6:0]) clocks. The exact amount of delay is approximate. Compare with S_NOP. When SIMM16[6:0] is zero then no sleep occurs.

Examples: s_sleep 0       // Wait for 0 clocks. s_sleep 1       // Wait for 1-64 clocks. s_sleep 2       // Wait for 65-128 clocks.


Summary: Cause a wave to sleep for up to ~8000 clocks, or to sleep until an external event wakes the wave up.


Summary: AMDGPU SOPK scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Subtract the second unsigned 32-bit integer input from the first input, subtract the carry-in bit, store the result into a scalar register and store…

Subtract the second unsigned 32-bit integer input from the first input, subtract the carry-in bit, store the result into a scalar register and store the carry-out bit into SCC.


Summary: Subtract the second signed 32-bit integer input from the first input, store the result into a scalar register and store the carry-out bit into SCC.


Summary: Subtract the second unsigned 32-bit integer input from the first input, store the result into a scalar register and store the carry-out bit into SCC.


Summary: Subtract the second floating point input from the first input and store the result in a scalar register.


This opcode is not suitable for use with S_SUBB_U32 for implementing 64-bit operations.


Summary: Subtract the second unsigned 64-bit integer input from the first input and store the result into a scalar register.


Summary: Subtract two 32-bit unsigned scalar operands, wavefront-uniform.

SDST = S0.u32 - S1.u32; SCC = borrow-out.


Summary: AMDGPU SOP2 scalar instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


tmp = S0.u32 - S1.u32 - SCC.u32;
SCC = 64'U(S1.u32) + SCC.u64 > 64'U(S0.u32) ? 1'1U : 1'0U;
// unsigned overflow or carry-out for S_SUBB_U32.
D0.u32 = tmp.u32


Summary: Begin execution of a subvector block of code.


Summary: End execution of a subvector block of code.


Summary: AMDGPU SOP1 scalar instruction operating on i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Store the address of the next instruction to a scalar register and then jump to an address specified in the scalar input. The argument is a byte address of the instruction to jump to. The byte address of the instruction immediately following this instruction is saved to the destination.

jump_addr = S0.i64;
D0.i64 = PC + 4LL;
PC = jump_addr.i64


Summary: Enter the trap handler.

Enter the trap handler.

This instruction may be generated internally as well in response to a host trap (HT = 1) or an exception. TrapID
0 is reserved for hardware use and should not be used in a shader-generated trap.
TrapID = SIMM16.u16[7 : 0];
"Wait for all instructions to complete";
// PC passed into trap handler points to S_TRAP itself,
// *not* to the next instruction.
{ TTMP[1], TTMP[0] } = { 3'0, PCRewind[3 : 0], HT[0], TrapID[7 : 0], PC[47 : 0] };
PC = TBA.i64;
// trap base address
WAVE_STATUS.PRIV = 1'1U


Summary: Compute the integer part of a half-precision float input using round toward zero semantics and store the result in floating point format into a…

Compute the integer part of a half-precision float input using round toward zero semantics and store the result in floating point format into a scalar register.


Summary: Compute the integer part of a single-precision float input using round toward zero semantics and store the result in floating point format into a…

Compute the integer part of a single-precision float input using round toward zero semantics and store the result in floating point format into a scalar register.


Summary: Send M0 as user data to the thread trace stream.


Summary: Wait for one or more ALU-centric counters to fall below specified values.


Summary: Wait for an event to occur or a condition to be satisfied before continuing. The SIMM16 argument specifies which event(s) to wait on.


Summary: Wait for the counts of outstanding local data share, vector memory and export instructions to be at or below the specified levels.

SIMM16[3:0] = vmcount (vector memory operations) lower bits [3:0],
SIMM16[6:4] = export/mem-write-data count,
SIMM16[11:8] = LGKMcnt (scalar-mem/GDS/LDS count),
SIMM16[15:14] = vmcount (vector memory operations) upper bits [5:4].


Summary: Wait for the EXPCNT counter to be at or below the specified level. The EXPCNT counter tracks the number of outstanding export events.


Wait for the LGKMCNT counter to be at or below the specified level. The LGKMCNT counter tracks the number of outstanding local data share (L), global data share (G), scalar memory (K) and message (M) events.


Wait for the VMCNT counter to be at or below the specified level. The VMCNT counter tracks the number of outstanding vector memory loads and atomics that do return data. When in 'all-in-order' mode, wait for all load and store vector memory events.


Wait for the VSCNT counter to be at or below the specified level. The VSCNT counter tracks the number of outstanding vector memory stores and atomics that do not return data. This counter is not used in 'all-in-order' mode.


Allow a wave to 'ping' all the other waves in its threadgroup to force them to wake up early from an S_SLEEP instruction. The ping is ignored if the waves are not sleeping. This allows for efficient polling on a memory location. The waves which are polling can sit in a long S_SLEEP between memory reads, but the wave which writes the value can tell them all to wake up early now that the data is available. This method is also safe from races since any waves that miss the ping resume when they complete their S_SLEEP. If the wave executing S_WAKEUP is in a threadgroup (in_tg set), then it wakes up all waves associated with the same threadgroup ID. Otherwise, S_WAKEUP is treated as an S_NOP.


Summary: AMDGPU SOP1 scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Given an active pixel mask in a scalar input, calculate whole quad mode mask for that input, store the result into a scalar register and set SCC iff…

Given an active pixel mask in a scalar input, calculate whole quad mode mask for that input, store the result into a scalar register and set SCC iff the result is nonzero. In whole quad mode, if any pixel in a quad is active then all pixels of the quad are marked active.


tmp = 0ULL;
declare i : 6'U;
for i in 6'0U : 6'63U do
tmp[i] = S0.u64[i & 6'60U +: 6'4U] != 0ULL
endfor;
D0.u64 = tmp;
SCC = D0.u64 != 0ULL


Summary: Calculate bitwise XNOR on two scalar inputs, store the result into a scalar register and set SCC if the result is nonzero.


Summary: Calculate bitwise XNOR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is…

Calculate bitwise XNOR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register.


saveexec = EXEC.u64;
EXEC.u64 = ~(S0.u64 ^ EXEC.u64);
D0.u64 = saveexec.u64;
SCC = EXEC.u64 != 0ULL


Summary: Calculate bitwise XOR on two scalar inputs, store the result into a scalar register and set SCC iff the result is nonzero.


Summary: Calculate bitwise XOR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is…

Calculate bitwise XOR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register.


Calculate bitwise XOR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. The original EXEC mask is saved to the destination SGPRs before the bitwise operation is performed.

saveexec = EXEC.u64;
EXEC.u64 = (S0.u64 ^ EXEC.u64);
D0.u64 = saveexec.u64;
SCC = EXEC.u64 != 0ULL


Summary: Load a block of data from the scratch aperture.


Summary: Load 32 bits of data from the scratch aperture into a vector register.


Summary: Load 64 bits of data from the scratch aperture into a vector register.

addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
VDATA[31 : 0] = MEM[addr].b32;
VDATA[63 : 32] = MEM[addr + 4U].b32


Summary: Load 96 bits of data from the scratch aperture into a vector register.

addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
VDATA[31 : 0] = MEM[addr].b32;
VDATA[63 : 32] = MEM[addr + 4U].b32;
VDATA[95 : 64] = MEM[addr + 8U].b32


Summary: Load 128 bits of data from the scratch aperture into a vector register.

addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
VDATA[31 : 0] = MEM[addr].b32;
VDATA[63 : 32] = MEM[addr + 4U].b32;
VDATA[95 : 64] = MEM[addr + 8U].b32;
VDATA[127 : 96] = MEM[addr + 12U].b32


Summary: Load 32 bits of untyped data from the scratch aperture and store the result into a data share.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
VDATA[31 : 0] = MEM[addr].b32


Summary: Load 8 bits of untyped data from the scratch aperture, sign extend to 32 bits and store the result into a data share.


Summary: Load 16 bits of untyped data from the scratch aperture, sign extend to 32 bits and store the result into a data share.


Summary: Load 8 bits of untyped data from the scratch aperture, zero extend to 32 bits and store the result into a data share.


Summary: Load 16 bits of untyped data from the scratch aperture, zero extend to 32 bits and store the result into a data share.


Summary: Load 8 bits of signed data from the scratch aperture, sign extend to 32 bits and store the result into a vector register.


Summary: Load 8 bits of signed data from the scratch aperture, sign extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register.

addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
VDATA[15 : 0].i16 = 16'I(signext(MEM[addr].i8));
// VDATA[31:16] is preserved.


Summary: Load 8 bits of signed data from the scratch aperture, sign extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register.

addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
VDATA[31 : 16].i16 = 16'I(signext(MEM[addr].i8));
// VDATA[15:0] is preserved.


Summary: Load 16 bits of unsigned data from the scratch aperture and store the result into the low 16 bits of a 32-bit vector register.

addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
VDATA[15 : 0].b16 = MEM[addr].b16;
// VDATA[31:16] is preserved.


Summary: Load 16 bits of unsigned data from the scratch aperture and store the result into the high 16 bits of a 32-bit vector register.

addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
VDATA[31 : 16].b16 = MEM[addr].b16;
// VDATA[15:0] is preserved.


Summary: Load 16 bits of signed data from the scratch aperture, sign extend to 32 bits and store the result into a vector register.


Summary: Load 8 bits of unsigned data from the scratch aperture, zero extend to 32 bits and store the result into a vector register.


Summary: Load 8 bits of unsigned data from the scratch aperture, zero extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register.

addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
VDATA[15 : 0].u16 = 16'U({ 8'0U, MEM[addr].u8 });
// VDATA[31:16] is preserved.


Summary: Load 8 bits of unsigned data from the scratch aperture, zero extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register.

addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
VDATA[31 : 16].u16 = 16'U({ 8'0U, MEM[addr].u8 });
// VDATA[15:0] is preserved.


Summary: Load 16 bits of unsigned data from the scratch aperture, zero extend to 32 bits and store the result into a vector register.


Summary: Store a block of data to the scratch aperture.


Summary: Store 8 bits of data from a vector register into the scratch aperture.

addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
MEM[addr].b8 = VDATA[7 : 0]


Summary: Store 8 bits of data from the high 16 bits of a 32-bit vector register into the scratch aperture.

addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
MEM[addr].b8 = VDATA[23 : 16]


Summary: Store 32 bits of data from vector input registers into the scratch aperture.

addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
MEM[addr].b32 = VDATA[31 : 0]


Summary: Store 64 bits of data from vector input registers into the scratch aperture.

addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
MEM[addr].b32 = VDATA[31 : 0];
MEM[addr + 4U].b32 = VDATA[63 : 32]


Summary: Store 96 bits of data from vector input registers into the scratch aperture.

addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
MEM[addr].b32 = VDATA[31 : 0];
MEM[addr + 4U].b32 = VDATA[63 : 32];
MEM[addr + 8U].b32 = VDATA[95 : 64]


Summary: Store 128 bits of data from vector input registers into the scratch aperture.

addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
MEM[addr].b32 = VDATA[31 : 0];
MEM[addr + 4U].b32 = VDATA[63 : 32];
MEM[addr + 8U].b32 = VDATA[95 : 64];
MEM[addr + 12U].b32 = VDATA[127 : 96]


Summary: Store 16 bits of data from a vector register into the scratch aperture.

addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
MEM[addr].b16 = VDATA[15 : 0]


Summary: Store 16 bits of data from the high 16 bits of a 32-bit vector register into the scratch aperture.

addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
MEM[addr].b16 = VDATA[31 : 16]


Summary: Load 1-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result…

Load 1-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result into a vector register. The instruction specifies the data format of the surface, overriding the resource descriptor.

tbuffer_load_d16_format_x v255, off, s[8:11], s3, format:1 offset:4095


Summary: Load 2-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result…

Load 2-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result into a vector register. The instruction specifies the data format of the surface, overriding the resource descriptor.

tbuffer_load_d16_format_xy v255, off, s[8:11], s3, format:6 offset:4095


Summary: Load 3-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result…

Load 3-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result into a vector register. The instruction specifies the data format of the surface, overriding the resource descriptor.

tbuffer_load_d16_format_xyz v[4:5], off, ttmp[4:7], 61, format:13 offset:4095


Summary: Load 4-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result…

Load 4-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result into a vector register. The instruction specifies the data format of the surface, overriding the resource descriptor.

tbuffer_load_d16_format_xyzw v[4:5], off, ttmp[4:7], 61, format:18 offset:4095


addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);
VDATA[15 : 0].b16 = 16'B(ConvertFromFormat(MEM[addr + ChannelOffsetX()]));
// Mem access size depends on format
// VDATA[31:16].b16 is preserved.


addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);
VDATA[15 : 0].b16 = 16'B(ConvertFromFormat(MEM[addr + ChannelOffsetX()]));
// Mem access size depends on format
VDATA[31 : 16].b16 = 16'B(ConvertFromFormat(MEM[addr + ChannelOffsetY()]))


addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);
VDATA[15 : 0].b16 = 16'B(ConvertFromFormat(MEM[addr + ChannelOffsetX()]));
// Mem access size depends on format
VDATA[31 : 16].b16 = 16'B(ConvertFromFormat(MEM[addr + ChannelOffsetY()]));
VDATA[47 : 32].b16 = 16'B(ConvertFromFormat(MEM[addr + ChannelOffsetZ()]));
// VDATA[63:48].b16 is preserved.


addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);
VDATA[15 : 0].b16 = 16'B(ConvertFromFormat(MEM[addr + ChannelOffsetX()]));
// Mem access size depends on format
VDATA[31 : 16].b16 = 16'B(ConvertFromFormat(MEM[addr + ChannelOffsetY()]));
VDATA[47 : 32].b16 = 16'B(ConvertFromFormat(MEM[addr + ChannelOffsetZ()]));
VDATA[63 : 48].b16 = 16'B(ConvertFromFormat(MEM[addr + ChannelOffsetW()]))


Summary: Load 1-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a…

Load 1-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a vector register. The instruction specifies the data format of the surface, overriding the resource descriptor.

addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);
VDATA[31 : 0].b32 = ConvertFromFormat(MEM[addr + ChannelOffsetX()]);
// Mem access size depends on format

tbuffer_load_format_x v255, off, s[8:11], s3, format:21 offset:4095


Summary: Load 2-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a…

Load 2-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a vector register. The instruction specifies the data format of the surface, overriding the resource descriptor.

addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);
VDATA[31 : 0].b32 = ConvertFromFormat(MEM[addr + ChannelOffsetX()]);
// Mem access size depends on format
VDATA[63 : 32].b32 = ConvertFromFormat(MEM[addr + ChannelOffsetY()])

tbuffer_load_format_xy v[4:5], off, ttmp[4:7], 61, format:28 offset:4095


Summary: Load 3-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a…

Load 3-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a vector register. The instruction specifies the data format of the surface, overriding the resource descriptor.

addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);
VDATA[31 : 0].b32 = ConvertFromFormat(MEM[addr + ChannelOffsetX()]);
// Mem access size depends on format
VDATA[63 : 32].b32 = ConvertFromFormat(MEM[addr + ChannelOffsetY()]);
VDATA[95 : 64].b32 = ConvertFromFormat(MEM[addr + ChannelOffsetZ()])

tbuffer_load_format_xyz v[4:6], off, ttmp[4:7], 61, format:33 offset:4095


Summary: Load 4-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a…

Load 4-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a vector register. The instruction specifies the data format of the surface, overriding the resource descriptor.

addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);
VDATA[31 : 0].b32 = ConvertFromFormat(MEM[addr + ChannelOffsetX()]);
// Mem access size depends on format
VDATA[63 : 32].b32 = ConvertFromFormat(MEM[addr + ChannelOffsetY()]);
VDATA[95 : 64].b32 = ConvertFromFormat(MEM[addr + ChannelOffsetZ()]);
VDATA[127 : 96].b32 = ConvertFromFormat(MEM[addr + ChannelOffsetW()])

tbuffer_load_format_xyzw v[4:7], off, ttmp[4:7], 61, format:38 offset:4095


Convert 16 bits of data from vector input registers into 1-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor.

tbuffer_store_d16_format_x v255, off, s[8:11], s3, format:41 offset:4095


Convert 32 bits of data from vector input registers into 2-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor.

tbuffer_store_d16_format_xy v255, off, s[8:11], s3, format:46 offset:4095


Convert 48 bits of data from vector input registers into 3-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor.

tbuffer_store_d16_format_xyz v[4:5], off, ttmp[4:7], 61, format:53 offset:4095


Convert 64 bits of data from vector input registers into 4-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor.

tbuffer_store_d16_format_xyzw v[4:5], off, ttmp[4:7], 61, format:58 offset:4095


addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);
MEM[addr + ChannelOffsetX()] = ConvertToFormat(32'B(VDATA[15 : 0].b16));
// Mem access size depends on format


addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);
MEM[addr + ChannelOffsetX()] = ConvertToFormat(32'B(VDATA[15 : 0].b16));
// Mem access size depends on format
MEM[addr + ChannelOffsetY()] = ConvertToFormat(32'B(VDATA[31 : 16].b16))


addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);
MEM[addr + ChannelOffsetX()] = ConvertToFormat(32'B(VDATA[15 : 0].b16));
// Mem access size depends on format
MEM[addr + ChannelOffsetY()] = ConvertToFormat(32'B(VDATA[31 : 16].b16));
MEM[addr + ChannelOffsetZ()] = ConvertToFormat(32'B(VDATA[47 : 32].b16))


addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);
MEM[addr + ChannelOffsetX()] = ConvertToFormat(32'B(VDATA[15 : 0].b16));
// Mem access size depends on format
MEM[addr + ChannelOffsetY()] = ConvertToFormat(32'B(VDATA[31 : 16].b16));
MEM[addr + ChannelOffsetZ()] = ConvertToFormat(32'B(VDATA[47 : 32].b16));
MEM[addr + ChannelOffsetW()] = ConvertToFormat(32'B(VDATA[63 : 48].b16))


Convert 32 bits of data from vector input registers into 1-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor.

addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);
MEM[addr + ChannelOffsetX()] = ConvertToFormat(VDATA[31 : 0].b32);
// Mem access size depends on format

tbuffer_store_format_x v255, off, s[8:11], s3, format:61 offset:4095


Convert 64 bits of data from vector input registers into 2-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor.

addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);
MEM[addr + ChannelOffsetX()] = ConvertToFormat(VDATA[31 : 0].b32);
// Mem access size depends on format
MEM[addr + ChannelOffsetY()] = ConvertToFormat(VDATA[63 : 32].b32)

tbuffer_store_format_xy v[4:5], off, s[8:11], 0, format:[BUF_FMT_16_SINT] offset:4095


Convert 96 bits of data from vector input registers into 3-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor.

addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);
MEM[addr + ChannelOffsetX()] = ConvertToFormat(VDATA[31 : 0].b32);
// Mem access size depends on format
MEM[addr + ChannelOffsetY()] = ConvertToFormat(VDATA[63 : 32].b32);
MEM[addr + ChannelOffsetZ()] = ConvertToFormat(VDATA[95 : 64].b32)

tbuffer_store_format_xyz v[4:6], off, s[8:11], s3, format:[BUF_FMT_32_FLOAT] offset:4095


Convert 128 bits of data from vector input registers into 4-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor.

addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);
MEM[addr + ChannelOffsetX()] = ConvertToFormat(VDATA[31 : 0].b32);
// Mem access size depends on format
MEM[addr + ChannelOffsetY()] = ConvertToFormat(VDATA[63 : 32].b32);
MEM[addr + ChannelOffsetZ()] = ConvertToFormat(VDATA[95 : 64].b32);
MEM[addr + ChannelOffsetW()] = ConvertToFormat(VDATA[127 : 96].b32)

tbuffer_store_format_xyzw v[4:7], off, s[8:11], 0, format:[BUF_FMT_8_8_8_8_UNORM] offset:4095


Summary: AMDGPU FLAT vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Move data from one accumulator register to another accumulator register.


Summary: AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Add three unsigned inputs and store the result into a vector register. No carry-in or carry-out support.


Summary: Add two unsigned 32-bit integer inputs, store the result into a vector register and store the carry-out mask into a scalar register.

tmp = 64'U(S0.u32) + 64'U(S1.u32);
VCC.u64[laneId] = tmp >= 0x100000000ULL ? 1'1U : 1'0U;
// VCC is an UNSIGNED overflow/carry-out for V_ADDC_CO_U32.
D0.u32 = tmp.u32

In VOP3 the VCC destination may be an arbitrary SGPR-pair. Supports saturation (unsigned 32-bit integer domain).


Summary: Add two floating point inputs and store the result into a vector register.

0.5ULP precision. Supports denormals, round mode, exception flags and saturation.


Summary: Per-lane single-precision floating-point add.

VDST[lane] = S0[lane].f32 + S1[lane].f32 for each active lane, per the EXEC mask.


Summary: AMDGPU VOP2 vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Add two signed 16-bit integer inputs and store the result into a vector register. No carry-in or carry-out support.

Supports saturation (signed 16-bit integer domain).


Summary: Add two signed 32-bit integer inputs and store the result into a vector register. No carry-in or carry-out support.


Summary: Add the first two integer inputs, then given a shift count in the third input, calculate the logical shift left of the intermediate result, then…

Add the first two integer inputs, then given a shift count in the third input, calculate the logical shift left of the intermediate result, then store the final result into a vector register.


Summary: AMDGPU VOP3 vector instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU VOP3 vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Add two unsigned 16-bit integer inputs and store the result into a vector register. No carry-in or carry-out support.


Summary: AMDGPU VOP2 vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Supports saturation (unsigned 16-bit integer domain).


Summary: Per-lane add of two 32-bit unsigned vector operands.

Add two unsigned 32-bit integer inputs and store the result into a vector register. No carry-in or carry-out support.

VDST[lane] = S0[lane].u32 + S1[lane].u32 for each active lane, per the EXEC mask.

v_add_u32  v2, v0, v1   // per-lane v2 = v0 + v1


Summary: Add two unsigned 32-bit integer inputs and a bit from a carry-in mask, store the result into a vector register and store the carry-out mask into a…

Add two unsigned 32-bit integer inputs and a bit from a carry-in mask, store the result into a vector register and store the carry-out mask into a scalar register.

tmp = 64'U(S0.u32) + 64'U(S1.u32) + VCC.u64[laneId].u64;
VCC.u64[laneId] = tmp >= 0x100000000ULL ? 1'1U : 1'0U;
// VCC is an UNSIGNED overflow/carry-out for V_ADDC_CO_U32.
D0.u32 = tmp.u32

In VOP3 the VCC destination may be an arbitrary SGPR-pair, and the VCC source comes from the SGPR-pair at S2.u. Supports saturation (unsigned 32-bit integer domain).


Summary: AMDGPU VOP2 vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Align a 64-bit value encoded in the first two inputs to a bit position specified in the third input, then store the result into a 32-bit vector…

Align a 64-bit value encoded in the first two inputs to a bit position specified in the third input, then store the result into a 32-bit vector register.

 S0 carries the MSBs and S1 carries the LSBs of the value being aligned.


Summary: AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Align a 64-bit value encoded in the first two inputs to a byte position specified in the third input, then store the result into a 32-bit vector…

Align a 64-bit value encoded in the first two inputs to a byte position specified in the third input, then store the result into a 32-bit vector register.


Summary: Calculate bitwise AND on two vector inputs and store the result into a vector register.


Summary: AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Input and output modifiers not supported.


Summary: Calculate bitwise AND on the first two vector inputs, then compute the bitwise OR of the intermediate result and the third vector input, then store…

Calculate bitwise AND on the first two vector inputs, then compute the bitwise OR of the intermediate result and the third vector input, then store the final result into a vector register.


Summary: AMDGPU VOP2 vector instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU VOP3 vector instruction operating on i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Given two signed 32-bit integers and a shift count, calculate the arithmetic shift right (preserving sign bit) of the two integers, saturate the two…

Given two signed 32-bit integers and a shift count, calculate the arithmetic shift right (preserving sign bit) of the two integers, saturate the two results in the signed 8-bit interval [-128, 127], pack the bytes and store the result into a vector register.


Given two signed 32-bit integers and a shift count, calculate the arithmetic shift right (preserving sign bit) of the two integers, saturate the two results in the unsigned 8-bit interval [0, 255], pack the bytes and store the result into a vector register.


Summary: Given a shift count in the first vector input, calculate the arithmetic shift right (preserving sign bit) of the second vector input and store the…

Given a shift count in the first vector input, calculate the arithmetic shift right (preserving sign bit) of the second vector input and store the result into a vector register.


Summary: Per-lane accumulating population count.

Count the number of "1" bits in the vector input and store the result into a vector register.

VDST[lane] = popcount(S0[lane]) + S1[lane] for each active lane; pass a zero S1 to match a plain population count.


Summary: Extract a signed bitfield from the first input using field offset from the second input and size from the third input, then store the result into a…

Extract a signed bitfield from the first input using field offset from the second input and size from the third input, then store the result into a vector register.


Summary: Extract an unsigned bitfield from the first input using field offset from the second input and size from the third input, then store the result into…

Extract an unsigned bitfield from the first input using field offset from the second input and size from the third input, then store the result into a vector register.


Summary: Overwrite a bitfield in the third input with a bitfield from the second input using a mask from the first input, then store the result into a vector…

Overwrite a bitfield in the third input with a bitfield from the second input using a mask from the first input, then store the result into a vector register.


Summary: Calculate a bitfield mask given a field offset and size and store the result into a vector register.


Summary: Reverse the order of bits in a vector input and store the result into a vector register.


Summary: Calculate the generic bitwise operation of three 16-bit vector inputs using a truth table encoded in the instruction and store the result into a…

Calculate the generic bitwise operation of three 16-bit vector inputs using a truth table encoded in the instruction and store the result into a vector register.


Summary: AMDGPU VOP3 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Calculate the generic bitwise operation of three 32-bit vector inputs using a truth table encoded in the instruction and store the result into a…

Calculate the generic bitwise operation of three 32-bit vector inputs using a truth table encoded in the instruction and store the result into a vector register.


Summary: Round the half-precision float input up to next integer and store the result in floating point format into a vector register.


Summary: Round the single-precision float input up to next integer and store the result in floating point format into a vector register.


Summary: Round the double-precision float input up to next integer and store the result in floating point format into a vector register.


Summary: Clear this wave's exception state in the vector ALU.


Summary: Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a half-precision float, and set the…

Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a half-precision float, and set the per-lane condition code to the result. Store the result into VCC or a scalar register. The function reports true if the floating point value is any of the numeric types selected in the 10 bit mask according to the following list: S1.u[0] value is a signaling NAN. S1.u[1] value is a quiet NAN. S1.u[2] value is negative infinity. S1.u[3] value is a negative normal value. S1.u[4] value is a negative denormal value. S1.u[5] value is negative zero. S1.u[6] value is positive zero. S1.u[7] value is a positive denormal value. S1.u[8] value is a positive normal value. S1.u[9] value is positive infinity.

declare result : 1'U;
if isSignalNAN(64'F(S0.f16)) then
result = S1.u32[0]
elsif isQuietNAN(64'F(S0.f16)) then
result = S1.u32[1]
elsif exponent(S0.f16) == 31 then
// +-INF
result = S1.u32[sign(S0.f16) ? 2 : 9]
elsif exponent(S0.f16) > 0 then
// +-normal value
result = S1.u32[sign(S0.f16) ? 3 : 8]
elsif 64'F(abs(S0.f16)) > 0.0 then
// +-denormal value
result = S1.u32[sign(S0.f16) ? 4 : 7]
else
// +-0.0
result = S1.u32[sign(S0.f16) ? 5 : 6]
endif;
D0.u64[laneId] = result;
// D0 = VCC in VOPC encoding.

Note that the S1 has a format of f16 since floating point literal constants are interpreted as 16 bit value for this opcode.


Summary: Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a single-precision float, and set the…

Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a single-precision float, and set the per-lane condition code to the result. Store the result into VCC or a scalar register. The function reports true if the floating point value is any of the numeric types selected in the 10 bit mask according to the following list: S1.u[0] value is a signaling NAN. S1.u[1] value is a quiet NAN. S1.u[2] value is negative infinity. S1.u[3] value is a negative normal value. S1.u[4] value is a negative denormal value. S1.u[5] value is negative zero. S1.u[6] value is positive zero. S1.u[7] value is a positive denormal value. S1.u[8] value is a positive normal value. S1.u[9] value is positive infinity.

declare result : 1'U;
if isSignalNAN(64'F(S0.f32)) then
result = S1.u32[0]
elsif isQuietNAN(64'F(S0.f32)) then
result = S1.u32[1]
elsif exponent(S0.f32) == 255 then
// +-INF
result = S1.u32[sign(S0.f32) ? 2 : 9]
elsif exponent(S0.f32) > 0 then
// +-normal value
result = S1.u32[sign(S0.f32) ? 3 : 8]
elsif 64'F(abs(S0.f32)) > 0.0 then
// +-denormal value
result = S1.u32[sign(S0.f32) ? 4 : 7]
else
// +-0.0
result = S1.u32[sign(S0.f32) ? 5 : 6]
endif;
D0.u64[laneId] = result;
// D0 = VCC in VOPC encoding.


Summary: Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a double-precision float, and set the…

Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a double-precision float, and set the per-lane condition code to the result. Store the result into VCC or a scalar register. The function reports true if the floating point value is any of the numeric types selected in the 10 bit mask according to the following list: S1.u[0] value is a signaling NAN. S1.u[1] value is a quiet NAN. S1.u[2] value is negative infinity. S1.u[3] value is a negative normal value. S1.u[4] value is a negative denormal value. S1.u[5] value is negative zero. S1.u[6] value is positive zero. S1.u[7] value is a positive denormal value. S1.u[8] value is a positive normal value. S1.u[9] value is positive infinity.

declare result : 1'U;
if isSignalNAN(S0.f64) then
result = S1.u32[0]
elsif isQuietNAN(S0.f64) then
result = S1.u32[1]
elsif exponent(S0.f64) == 2047 then
// +-INF
result = S1.u32[sign(S0.f64) ? 2 : 9]
elsif exponent(S0.f64) > 0 then
// +-normal value
result = S1.u32[sign(S0.f64) ? 3 : 8]
elsif abs(S0.f64) > 0.0 then
// +-denormal value
result = S1.u32[sign(S0.f64) ? 4 : 7]
else
// +-0.0
result = S1.u32[sign(S0.f64) ? 5 : 6]
endif;
D0.u64[laneId] = result;
// D0 = VCC in VOPC encoding.


Summary: Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register.

D0.u64[laneId] = S0.f16 == S1.f16;
// D0 = VCC in VOPC encoding.


Summary: Per-lane single-precision equality compare, result written as an execution-mask-width bitmask.

VCC

Destination mask (VCC, or an arbitrary SGPR pair for the _e64 encoding)

VCC[lane] = (S0[lane].f32 == S1[lane].f32) for each active lane; VCC is 32 bits wide in wave32 mode, 64 bits in wave64 mode.

v_cmp_eq_f32  vcc, v0, v1   // vcc[lane] = (v0[lane] == v1[lane])


D0.u64[laneId] = S0.f64 == S1.f64;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.i16 == S1.i16;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.i32 == S1.i32;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.i64 == S1.i64;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.u16 == S1.u16;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.u32 == S1.u32;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.u64 == S1.u64;
// D0 = VCC in VOPC encoding.


Summary: Set the per-lane condition code to 0. Store the result into VCC or a scalar register.

D0.u64[laneId] = 1'0U;
// D0 = VCC in VOPC encoding.


Summary: Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register.

D0.u64[laneId] = S0.f16 >= S1.f16;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.f32 >= S1.f32;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.f64 >= S1.f64;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.i16 >= S1.i16;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.i32 >= S1.i32;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.i64 >= S1.i64;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.u16 >= S1.u16;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.u32 >= S1.u32;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.u64 >= S1.u64;
// D0 = VCC in VOPC encoding.


Summary: Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register.

D0.u64[laneId] = S0.f16 > S1.f16;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.f32 > S1.f32;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.f64 > S1.f64;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.i16 > S1.i16;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.i32 > S1.i32;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.i64 > S1.i64;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.u16 > S1.u16;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.u32 > S1.u32;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.u64 > S1.u64;
// D0 = VCC in VOPC encoding.


Summary: Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register.

D0.u64[laneId] = S0.f16 <= S1.f16;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.f32 <= S1.f32;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.f64 <= S1.f64;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.i16 <= S1.i16;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.i32 <= S1.i32;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.i64 <= S1.i64;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.u16 <= S1.u16;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.u32 <= S1.u32;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.u64 <= S1.u64;
// D0 = VCC in VOPC encoding.


Set the per-lane condition code to 1 iff the first input is less than or greater than the second input. Store the result into VCC or a scalar register.

D0.u64[laneId] = S0.f16 <> S1.f16;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.f32 <> S1.f32;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.f64 <> S1.f64;
// D0 = VCC in VOPC encoding.


Summary: Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register.

D0.u64[laneId] = S0.f16 < S1.f16;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.f32 < S1.f32;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.f64 < S1.f64;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.i16 < S1.i16;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.i32 < S1.i32;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.i64 < S1.i64;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.u16 < S1.u16;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.u32 < S1.u32;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.u64 < S1.u64;
// D0 = VCC in VOPC encoding.


Summary: Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register.

D0.u64[laneId] = S0.i16 <> S1.i16;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.i32 <> S1.i32;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.i64 <> S1.i64;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.u16 <> S1.u16;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.u32 <> S1.u32;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = S0.u64 <> S1.u64;
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = !(S0.f16 == S1.f16);
// With NAN inputs this is not the same operation as !=
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = !(S0.f32 == S1.f32);
// With NAN inputs this is not the same operation as !=
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = !(S0.f64 == S1.f64);
// With NAN inputs this is not the same operation as !=
// D0 = VCC in VOPC encoding.


Set the per-lane condition code to 1 iff the first input is not greater than or equal to the second input. Store the result into VCC or a scalar register.

D0.u64[laneId] = !(S0.f16 >= S1.f16);
// With NAN inputs this is not the same operation as <
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = !(S0.f32 >= S1.f32);
// With NAN inputs this is not the same operation as <
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = !(S0.f64 >= S1.f64);
// With NAN inputs this is not the same operation as <
// D0 = VCC in VOPC encoding.


Summary: Set the per-lane condition code to 1 iff the first input is not greater than the second input. Store the result into VCC or a scalar register.

D0.u64[laneId] = !(S0.f16 > S1.f16);
// With NAN inputs this is not the same operation as <=
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = !(S0.f32 > S1.f32);
// With NAN inputs this is not the same operation as <=
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = !(S0.f64 > S1.f64);
// With NAN inputs this is not the same operation as <=
// D0 = VCC in VOPC encoding.


Set the per-lane condition code to 1 iff the first input is not less than or equal to the second input. Store the result into VCC or a scalar register.

D0.u64[laneId] = !(S0.f16 <= S1.f16);
// With NAN inputs this is not the same operation as >
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = !(S0.f32 <= S1.f32);
// With NAN inputs this is not the same operation as >
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = !(S0.f64 <= S1.f64);
// With NAN inputs this is not the same operation as >
// D0 = VCC in VOPC encoding.


Set the per-lane condition code to 1 iff the first input is not less than or greater than the second input. Store the result into VCC or a scalar register.

D0.u64[laneId] = !(S0.f16 <> S1.f16);
// With NAN inputs this is not the same operation as ==
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = !(S0.f32 <> S1.f32);
// With NAN inputs this is not the same operation as ==
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = !(S0.f64 <> S1.f64);
// With NAN inputs this is not the same operation as ==
// D0 = VCC in VOPC encoding.


Summary: Set the per-lane condition code to 1 iff the first input is not less than the second input. Store the result into VCC or a scalar register.

D0.u64[laneId] = !(S0.f16 < S1.f16);
// With NAN inputs this is not the same operation as >=
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = !(S0.f32 < S1.f32);
// With NAN inputs this is not the same operation as >=
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = !(S0.f64 < S1.f64);
// With NAN inputs this is not the same operation as >=
// D0 = VCC in VOPC encoding.


Summary: Set the per-lane condition code to 1 iff the first input is orderable to the second input. Store the result into VCC or a scalar register.

D0.u64[laneId] = (!isNAN(64'F(S0.f16)) && !isNAN(64'F(S1.f16)));
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = (!isNAN(64'F(S0.f32)) && !isNAN(64'F(S1.f32)));
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = (!isNAN(S0.f64) && !isNAN(S1.f64));
// D0 = VCC in VOPC encoding.


Summary: Set the per-lane condition code to 1. Store the result into VCC or a scalar register.


D0.u64[laneId] = 1'1U;
// D0 = VCC in VOPC encoding.


Summary: Set the per-lane condition code to 1 iff the first input is not orderable to the second input. Store the result into VCC or a scalar register.

D0.u64[laneId] = (isNAN(64'F(S0.f16)) || isNAN(64'F(S1.f16)));
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = (isNAN(64'F(S0.f32)) || isNAN(64'F(S1.f32)));
// D0 = VCC in VOPC encoding.


D0.u64[laneId] = (isNAN(S0.f64) || isNAN(S1.f64));
// D0 = VCC in VOPC encoding.


Summary: AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a half-precision float, and set the…

Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a half-precision float, and set the per-lane condition code to the result. Store the result into the EXEC mask and to VCC or a scalar register. The function reports true if the floating point value is any of the numeric types selected in the 10 bit mask according to the following list: S1.u[0] value is a signaling NAN. S1.u[1] value is a quiet NAN. S1.u[2] value is negative infinity. S1.u[3] value is a negative normal value. S1.u[4] value is a negative denormal value. S1.u[5] value is negative zero. S1.u[6] value is positive zero. S1.u[7] value is a positive denormal value. S1.u[8] value is a positive normal value. S1.u[9] value is positive infinity.

declare result : 1'U;
if isSignalNAN(64'F(S0.f16)) then
result = S1.u32[0]
elsif isQuietNAN(64'F(S0.f16)) then
result = S1.u32[1]
elsif exponent(S0.f16) == 31 then
// +-INF
result = S1.u32[sign(S0.f16) ? 2 : 9]
elsif exponent(S0.f16) > 0 then
// +-normal value
result = S1.u32[sign(S0.f16) ? 3 : 8]
elsif 64'F(abs(S0.f16)) > 0.0 then
// +-denormal value
result = S1.u32[sign(S0.f16) ? 4 : 7]
else
// +-0.0
result = S1.u32[sign(S0.f16) ? 5 : 6]
endif;
EXEC.u64[laneId] = D0.u64[laneId] = result


Summary: Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a single-precision float, and set the…

Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a single-precision float, and set the per-lane condition code to the result. Store the result into the EXEC mask and to VCC or a scalar register. The function reports true if the floating point value is any of the numeric types selected in the 10 bit mask according to the following list: S1.u[0] value is a signaling NAN. S1.u[1] value is a quiet NAN. S1.u[2] value is negative infinity. S1.u[3] value is a negative normal value. S1.u[4] value is a negative denormal value. S1.u[5] value is negative zero. S1.u[6] value is positive zero. S1.u[7] value is a positive denormal value. S1.u[8] value is a positive normal value. S1.u[9] value is positive infinity.

declare result : 1'U;
if isSignalNAN(64'F(S0.f32)) then
result = S1.u32[0]
elsif isQuietNAN(64'F(S0.f32)) then
result = S1.u32[1]
elsif exponent(S0.f32) == 255 then
// +-INF
result = S1.u32[sign(S0.f32) ? 2 : 9]
elsif exponent(S0.f32) > 0 then
// +-normal value
result = S1.u32[sign(S0.f32) ? 3 : 8]
elsif 64'F(abs(S0.f32)) > 0.0 then
// +-denormal value
result = S1.u32[sign(S0.f32) ? 4 : 7]
else
// +-0.0
result = S1.u32[sign(S0.f32) ? 5 : 6]
endif;
EXEC.u64[laneId] = D0.u64[laneId] = result


Summary: Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a double-precision float, and set the…

Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a double-precision float, and set the per-lane condition code to the result. Store the result into the EXEC mask and to VCC or a scalar register. The function reports true if the floating point value is any of the numeric types selected in the 10 bit mask according to the following list: S1.u[0] value is a signaling NAN. S1.u[1] value is a quiet NAN. S1.u[2] value is negative infinity. S1.u[3] value is a negative normal value. S1.u[4] value is a negative denormal value. S1.u[5] value is negative zero. S1.u[6] value is positive zero. S1.u[7] value is a positive denormal value. S1.u[8] value is a positive normal value. S1.u[9] value is positive infinity.

declare result : 1'U;
if isSignalNAN(S0.f64) then
result = S1.u32[0]
elsif isQuietNAN(S0.f64) then
result = S1.u32[1]
elsif exponent(S0.f64) == 2047 then
// +-INF
result = S1.u32[sign(S0.f64) ? 2 : 9]
elsif exponent(S0.f64) > 0 then
// +-normal value
result = S1.u32[sign(S0.f64) ? 3 : 8]
elsif abs(S0.f64) > 0.0 then
// +-denormal value
result = S1.u32[sign(S0.f64) ? 4 : 7]
else
// +-0.0
result = S1.u32[sign(S0.f64) ? 5 : 6]
endif;
EXEC.u64[laneId] = D0.u64[laneId] = result


Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.

EXEC.u64[laneId] = D0.u64[laneId] = S0.f16 == S1.f16;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.f32 == S1.f32;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.f64 == S1.f64;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.i16 == S1.i16;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.i32 == S1.i32;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.i64 == S1.i64;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.u16 == S1.u16;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.u32 == S1.u32;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.u64 == S1.u64;
// D0 = VCC in VOPC encoding.


Summary: Set the per-lane condition code to 0. Store the result into the EXEC mask and to VCC or a scalar register.

EXEC.u64[laneId] = D0.u64[laneId] = 1'0U;
// D0 = VCC in VOPC encoding.


Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.

EXEC.u64[laneId] = D0.u64[laneId] = S0.f16 >= S1.f16;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.f32 >= S1.f32;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.f64 >= S1.f64;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.i16 >= S1.i16;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.i32 >= S1.i32;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.i64 >= S1.i64;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.u16 >= S1.u16;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.u32 >= S1.u32;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.u64 >= S1.u64;
// D0 = VCC in VOPC encoding.


Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into the EXEC mask and to VCC or a scalar register.

EXEC.u64[laneId] = D0.u64[laneId] = S0.f16 > S1.f16;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.f32 > S1.f32;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.f64 > S1.f64;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.i16 > S1.i16;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.i32 > S1.i32;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.i64 > S1.i64;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.u16 > S1.u16;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.u32 > S1.u32;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.u64 > S1.u64;
// D0 = VCC in VOPC encoding.


Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.

EXEC.u64[laneId] = D0.u64[laneId] = S0.f16 <= S1.f16;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.f32 <= S1.f32;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.f64 <= S1.f64;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.i16 <= S1.i16;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.i32 <= S1.i32;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.i64 <= S1.i64;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.u16 <= S1.u16;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.u32 <= S1.u32;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.u64 <= S1.u64;
// D0 = VCC in VOPC encoding.


Set the per-lane condition code to 1 iff the first input is less than or greater than the second input. Store the result into the EXEC mask and to VCC or a scalar register.

EXEC.u64[laneId] = D0.u64[laneId] = S0.f16 <> S1.f16;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.f32 <> S1.f32;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.f64 <> S1.f64;
// D0 = VCC in VOPC encoding.


Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into the EXEC mask and to VCC or a scalar register.

EXEC.u64[laneId] = D0.u64[laneId] = S0.f16 < S1.f16;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.f32 < S1.f32;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.f64 < S1.f64;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.i16 < S1.i16;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.i32 < S1.i32;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.i64 < S1.i64;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.u16 < S1.u16;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.u32 < S1.u32;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.u64 < S1.u64;
// D0 = VCC in VOPC encoding.


Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.

EXEC.u64[laneId] = D0.u64[laneId] = S0.i16 <> S1.i16;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.i32 <> S1.i32;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.i64 <> S1.i64;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.u16 <> S1.u16;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.u32 <> S1.u32;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = S0.u64 <> S1.u64;
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f16 == S1.f16);
// With NAN inputs this is not the same operation as !=
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f32 == S1.f32);
// With NAN inputs this is not the same operation as !=
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f64 == S1.f64);
// With NAN inputs this is not the same operation as !=
// D0 = VCC in VOPC encoding.


Set the per-lane condition code to 1 iff the first input is not greater than or equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.

EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f16 >= S1.f16);
// With NAN inputs this is not the same operation as <
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f32 >= S1.f32);
// With NAN inputs this is not the same operation as <
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f64 >= S1.f64);
// With NAN inputs this is not the same operation as <
// D0 = VCC in VOPC encoding.


Set the per-lane condition code to 1 iff the first input is not greater than the second input. Store the result into the EXEC mask and to VCC or a scalar register.

EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f16 > S1.f16);
// With NAN inputs this is not the same operation as <=
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f32 > S1.f32);
// With NAN inputs this is not the same operation as <=
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f64 > S1.f64);
// With NAN inputs this is not the same operation as <=
// D0 = VCC in VOPC encoding.


Set the per-lane condition code to 1 iff the first input is not less than or equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.

EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f16 <= S1.f16);
// With NAN inputs this is not the same operation as >
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f32 <= S1.f32);
// With NAN inputs this is not the same operation as >
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f64 <= S1.f64);
// With NAN inputs this is not the same operation as >
// D0 = VCC in VOPC encoding.


Set the per-lane condition code to 1 iff the first input is not less than or greater than the second input. Store the result into the EXEC mask and to VCC or a scalar register.

EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f16 <> S1.f16);
// With NAN inputs this is not the same operation as ==
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f32 <> S1.f32);
// With NAN inputs this is not the same operation as ==
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f64 <> S1.f64);
// With NAN inputs this is not the same operation as ==
// D0 = VCC in VOPC encoding.


Set the per-lane condition code to 1 iff the first input is not less than the second input. Store the result into the EXEC mask and to VCC or a scalar register.

EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f16 < S1.f16);
// With NAN inputs this is not the same operation as >=
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f32 < S1.f32);
// With NAN inputs this is not the same operation as >=
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f64 < S1.f64);
// With NAN inputs this is not the same operation as >=
// D0 = VCC in VOPC encoding.


Set the per-lane condition code to 1 iff the first input is orderable to the second input. Store the result into the EXEC mask and to VCC or a scalar register.

EXEC.u64[laneId] = D0.u64[laneId] = (!isNAN(64'F(S0.f16)) && !isNAN(64'F(S1.f16)));
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = (!isNAN(64'F(S0.f32)) && !isNAN(64'F(S1.f32)));
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = (!isNAN(S0.f64) && !isNAN(S1.f64));
// D0 = VCC in VOPC encoding.


Summary: Set the per-lane condition code to 1. Store the result into the EXEC mask.


Summary: Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register.

EXEC.u64[laneId] = D0.u64[laneId] = 1'1U;
// D0 = VCC in VOPC encoding.


Set the per-lane condition code to 1 iff the first input is not orderable to the second input. Store the result into the EXEC mask and to VCC or a scalar register.

EXEC.u64[laneId] = D0.u64[laneId] = (isNAN(64'F(S0.f16)) || isNAN(64'F(S1.f16)));
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = (isNAN(64'F(S0.f32)) || isNAN(64'F(S1.f32)));
// D0 = VCC in VOPC encoding.


EXEC.u64[laneId] = D0.u64[laneId] = (isNAN(S0.f64) || isNAN(S1.f64));
// D0 = VCC in VOPC encoding.


Summary: Copy data from one of two inputs based on the per-lane condition code and store the result into a vector register.


Summary: AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


In VOP3 the VCC source may be a scalar GPR specified in S2. Floating-point modifiers are valid for this instruction if S0 and S1 are 32-bit floating point values. This instruction is suitable for negating or taking the absolute value of a floating-point value.


Summary: AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Calculate the trigonometric cosine of a half-precision float value using IEEE rules and store the result into a vector register. The operand is calculated by scaling the vector input by 2 PI.

Denormals are supported. Full range input is supported.


Calculate the trigonometric cosine of a single-precision float value using IEEE rules and store the result into a vector register. The operand is calculated by scaling the vector input by 2 PI.


Compute the cubemap face ID of a 3D coordinate specified as three single-precision float inputs. Store the result in single-precision float format into a vector register.

// Set D0.f = cubemap face ID ({0.0, 1.0, ..., 5.0}).
// XYZ coordinate is given in (S0.f, S1.f, S2.f).
// S0.f = x
// S1.f = y
// S2.f = z
if ((abs(S2.f32) >= abs(S0.f32)) && (abs(S2.f32) >= abs(S1.f32))) then
if S2.f32 < 0.0F then
D0.f32 = 5.0F
else
D0.f32 = 4.0F
endif
elsif abs(S1.f32) >= abs(S0.f32) then
if S1.f32 < 0.0F then
D0.f32 = 3.0F
else
D0.f32 = 2.0F
endif
else
if S0.f32 < 0.0F then
D0.f32 = 1.0F
else
D0.f32 = 0.0F
endif
endif


Compute the cubemap major axis of a 3D coordinate specified as three single-precision float inputs. Store the result in single-precision float format into a vector register.


Compute the cubemap S coordinate of a 3D coordinate specified as three single-precision float inputs. Store the result in single-precision float format into a vector register.

// D0.f = cubemap S coordinate.
// XYZ coordinate is given in (S0.f, S1.f, S2.f).
// S0.f = x
// S1.f = y
// S2.f = z
if ((abs(S2.f32) >= abs(S0.f32)) && (abs(S2.f32) >= abs(S1.f32))) then
if S2.f32 < 0.0F then
D0.f32 = -S0.f32
else
D0.f32 = S0.f32
endif
elsif abs(S1.f32) >= abs(S0.f32) then
D0.f32 = S0.f32
else
if S0.f32 < 0.0F then
D0.f32 = S2.f32
else
D0.f32 = -S2.f32
endif
endif


Compute the cubemap T coordinate of a 3D coordinate specified as three single-precision float inputs. Store the result in single-precision float format into a vector register.

// D0.f = cubemap T coordinate.
// XYZ coordinate is given in (S0.f, S1.f, S2.f).
// S0.f = x
// S1.f = y
// S2.f = z
if ((abs(S2.f32) >= abs(S0.f32)) && (abs(S2.f32) >= abs(S1.f32))) then
D0.f32 = -S1.f32
elsif abs(S1.f32) >= abs(S0.f32) then
if S1.f32 < 0.0F then
D0.f32 = -S2.f32
else
D0.f32 = S2.f32
endif
else
D0.f32 = -S1.f32
endif


Summary: AMDGPU VOP1 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Convert from a single-precision float input to a half-precision float value and store the result into a vector register.

0.5ULP accuracy, supports input modifiers and creates FP16 denormals when appropriate. Flush denorms on output if specified based on DP denorm mode. Output rounding based on DP rounding mode.


Summary: AMDGPU VOP1 vector instruction operating on f16/f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Convert from a signed 16-bit integer input to a half-precision float value and store the result into a vector register.

0.5ULP accuracy, supports denormals, rounding, exception flags and saturation.


Summary: Convert from an unsigned 16-bit integer input to a half-precision float value and store the result into a vector register.


Summary: Convert from a BF16 float input to a single-precision float value and store the result into a vector register.


Summary: Convert from a BF8 float input to a single-precision float value and store the result into a vector register.

if SDWA_SRC0_SEL == BYTE1.b3 then
D0.f32 = bf8_to_f32(S0[15 : 8].bf8)
elsif SDWA_SRC0_SEL == BYTE2.b3 then
D0.f32 = bf8_to_f32(S0[23 : 16].bf8)
elsif SDWA_SRC0_SEL == BYTE3.b3 then
D0.f32 = bf8_to_f32(S0[31 : 24].bf8)
else
// BYTE0 implied
D0.f32 = bf8_to_f32(S0[7 : 0].bf8)
endif

SDWA encoding allows SRC0_SEL to control which byte of S0 is converted. Only the BYTE selects of SRC0_SEL are legal. If this instruction is not encoded in SDWA then BYTE0 is implied.


Summary: AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Convert from a half-precision float input to a single-precision float value and store the result into a vector register.

0ULP accuracy, FP16 denormal inputs are accepted. Flush denorms on input if specified based on DP denorm mode.


Summary: Convert from a double-precision float input to a single-precision float value and store the result into a vector register.

0.5ULP accuracy, denormals are supported.


Summary: Convert from an FP8 float input to a single-precision float value and store the result into a vector register.

if SDWA_SRC0_SEL == BYTE1.b3 then
D0.f32 = fp8_to_f32(S0[15 : 8].fp8)
elsif SDWA_SRC0_SEL == BYTE2.b3 then
D0.f32 = fp8_to_f32(S0[23 : 16].fp8)
elsif SDWA_SRC0_SEL == BYTE3.b3 then
D0.f32 = fp8_to_f32(S0[31 : 24].fp8)
else
// BYTE0 implied
D0.f32 = fp8_to_f32(S0[7 : 0].fp8)
endif


Summary: Per-lane conversion from signed 32-bit integer to single-precision float.

Convert from a signed 32-bit integer input to a single-precision float value and store the result into a vector register.

VDST[lane] = convert_i32_to_f32(S0[lane]) for each active lane.

v_cvt_f32_i32  v1, v0   // per-lane v1 = (float) v0


Summary: Convert from an unsigned 32-bit integer input to a single-precision float value and store the result into a vector register.


Summary: Convert an unsigned byte in byte 0 of the input to a single-precision float value and store the result into a vector register.


Summary: Convert an unsigned byte in byte 1 of the input to a single-precision float value and store the result into a vector register.


Summary: Convert an unsigned byte in byte 2 of the input to a single-precision float value and store the result into a vector register.


Summary: Convert an unsigned byte in byte 3 of the input to a single-precision float value and store the result into a vector register.


Summary: Convert from a single-precision float input to a double-precision float value and store the result into a vector register.


Summary: Convert from a signed 32-bit integer input to a double-precision float value and store the result into a vector register.


Summary: Convert from an unsigned 32-bit integer input to a double-precision float value and store the result into a vector register.


Summary: Convert from a single-precision float input to a signed 32-bit integer value using round-down semantics (ignore the default rounding mode) and store…

Convert from a single-precision float input to a signed 32-bit integer value using round-down semantics (ignore the default rounding mode) and store the result into a vector register.


Summary: Convert from a half-precision float input to a signed 16-bit integer value and store the result into a vector register.

1ULP accuracy, supports rounding, exception flags and saturation. FP16 denormals are accepted. Conversion is done with truncation. Generation of the INEXACT exception is controlled by the CLAMP bit. INEXACT exceptions are enabled for this conversion iff CLAMP == 1.


Summary: Convert from a single-precision float input to a signed 32-bit integer value and store the result into a vector register.

1ULP accuracy, out-of-range floating point values (including infinity) saturate. NAN is converted to 0. Generation of the INEXACT exception is controlled by the CLAMP bit. INEXACT exceptions are enabled for this conversion iff CLAMP == 1.