Vector Extract Unsigned Halfword to GPR using GPR-specified Left-Index

Summary: Extracts an unsigned halfword from a vector register and places it into a general-purpose register using the left index specified in another general-purpose register.

The instruction extracts an unsigned halfword from VSR[VRB+32] based on the left index specified in bits 60:63 of GPR[RA]. The extracted halfword is placed into bits 48:63 of GPR[RT], and bits 0:47 of GPR[RT] are set to zero. If the index is greater than 14, the results are undefined.

if MSR.VEC=0 then
    Vector_Unavailable()
index ← GPR[RA].bit[60:63]
GPR[RT] ← EXTZ64(VSR[VRB+32].byte[index:index+1])
if index > 14 then
    undefined

This instruction is used to extract an unsigned halfword from a vector register into a general-purpose register. Ensure the left index specified in bits 60:63 of GPR[RA] does not exceed 14 to avoid undefined behavior. The result is zero-extended to 64 bits, so only the upper 16 bits of GPR[RT] will contain valid data.


Vector Extract Double Unsigned Byte to VSR Using GPR-specified Left-Index VA-form

Summary: Extracts a double unsigned byte from two vector registers using a left-index specified by a general-purpose register and places it into another vector register.

The instruction extracts a double unsigned byte from the concatenation of two vector registers (VRA+32 and VRB+32) based on an index derived from bits 59:63 of GPR[RC]. The extracted byte is zero-extended and placed into the first doubleword of VSR[VRT+32], while the second doubleword is set to zero.

RC

General Purpose Register containing the index

if MSR.VEC=0 then
    Vector_Unavailable()
index ← GPR[RC].bit[59:63]
vsrc.qword[0] ← VSR[VRA+32]
vsrc.qword[1] ← VSR[VRB+32]
VSR[VRT+32].dword[0] ← EXTZ64(vsrc.byte[index])
VSR[VRT+32].dword[1] ← 0x0000_0000_0000_0000

This instruction is useful for extracting a specific byte from two concatenated vector registers and placing it into the first doubleword of another VSR, with the second doubleword zeroed. Ensure that the index derived from GPR[RC] bits 59:63 is within bounds to avoid undefined behavior. The instruction requires the Vector Facility to be enabled; otherwise, a Vector_Unavailable exception will be raised.


Summary: Performs a bitwise NOR operation on the specified bits of the Condition Registers and stores the result in another bit of the Condition Register.

The bit in the Condition Register specified by BA+32 is ORed with the bit in the Condition Register specified by BB+32, and the complemented result is placed into the bit in the Condition Register specified by BT+32.

The crnor instruction performs a bitwise OR operation on two condition register bits, then complements the result and stores it in another condition register bit. Ensure that the BA, BB, and BT fields are correctly set to avoid unintended behavior. This instruction operates at user privilege level.


Summary: Loads a halfword from memory into a register and extends it to a full word, with indexed addressing.

The effective address (EA) is the sum of the contents of registers RA and RB. The halfword in storage addressed by EA is loaded into RT48:63, and RT0:47 are filled with a copy of bit 0 of the loaded halfword.

if RA = 0 then
    b ← 0
else
    b ← (RA)
EA ← b + (RB)
RT ← EXTS(MEM(EA, 2))

The lhax instruction is commonly used for loading a signed halfword from memory into the upper half of a register. Ensure that RA and RB are correctly set to avoid incorrect effective address calculation. This instruction requires the operands to be properly aligned; accessing unaligned data can lead to exceptions. The result is sign-extended, so be cautious when interpreting the value in RT.


Summary: Loads a word from memory into a register using an indexed address.

Loads a 32-bit signed word from memory at address RA+RB, sign-extends it to 64 bits, and stores the result in GPR RT. This instruction is part of the Base category and does not update condition registers or the XER.

RA

Source General Purpose Register (base address)

RB

Source General Purpose Register (offset)

EA ← (RA = 0 ? 0 : GPR(RA)) + GPR(RB)
GPR(RT) ← EXTS([EA])

The lwax instruction is commonly used for loading a word from memory into a register using an indexed addressing mode. Ensure that the base address in RA is properly aligned to avoid misaligned access exceptions. This instruction operates at user privilege level and can raise an exception if the EA is out of bounds or if there are memory protection violations.


Summary: Stores a doubleword from a register to memory using an indexed address.

Stores a doubleword (64 bits) from register RS to memory at the address formed by adding the contents of RA and RB. The effective address is calculated as (RA|0) + RB. No condition registers or status fields are modified by this instruction.

The stdx instruction is commonly used for storing a doubleword from a register into memory at an address derived from the sum of two registers. Ensure that RA and RB are correctly set to avoid incorrect memory addresses. This instruction operates in user mode and can raise exceptions if there's a protection fault or alignment error.


Summary: Adds the contents of two registers and an alternate carry bit, updating the condition register.

For addex, the sum of the contents of register RA, RB, and CY is placed into register RT. If CY=0, the sum (RA) + (RB) + OV is placed into register RT. For CY=0, OV is set to 1 if there is a carry out of bit 0 of the sum in 64-bit mode or there is a carry out of bit 32 of the sum in 32-bit mode, and set to 0 otherwise. OV32 is set to 1 if there is a carry out of bit 32 of the sum.

An addc-equivalent instruction using OV is not provided. An equivalent capability can be emulated by first initializing OV to 0, then using addex. OV can be initialized to 0 using subfo, subtracting any operand from itself.


Summary: Multiplies two 64-bit operands and adds the result to a third 64-bit operand, placing the high-order 64 bits of the sum into a target register.

The 64-bit operands (RA) and (RB) are multiplied to produce a 128-bit product. This product is then added to the 64-bit operand (RC). The high-order 64 bits of the resulting sum are placed into register RT.

prod0:127 ← (RA) × (RB)
sum0:127 ← prod + EXTS(RC)
RT ← sum0:63

The maddhd instruction is useful for performing high-precision arithmetic operations where the product of two 64-bit numbers needs to be added to another 64-bit number, and only the high-order bits of the result are required. Ensure that the operands are correctly aligned and consider the potential for overflow in the intermediate product before adding RC. This instruction operates at a privilege level that allows it to be used in both user and supervisor modes.


Summary: Counts the number of one bits in each byte of a register.

A count of the number of one bits in each byte of register RS is placed into the corresponding byte of register RA. This number ranges from 0 to 8, inclusive.

for i = 0 to 7
    n ← 0
    for j = 0 to 7
        if (RS)(i×8)+j = 1 then
            n ← n+1
    RA(i×8):(i×8)+7 ← n


Summary: Rotates the contents of register RS left by a variable number of bits specified by (RB)58:63, and clears the rightmost bits.

The contents of register RS are rotated 64 bits to the left by the number of bits specified by (RB)58:63. A mask is generated having 1-bits from bit 0 through bit ME and 0-bits elsewhere. The rotated data are ANDed with the generated mask, and the result is placed into register RA.

if 'rldcr' then
    n ← (RB)58:63
    r ← ROTL64((RS), n)
    ME ← me5 || me0:4
    m ← MASK(0, ME)
    RA ← r & m
if 'rldcr.' then
    CR0 <- updated based on result

rldcr can be used to extract an n-bit field that starts at variable bit position b in register RS, left-justified RA), by setting RB58:63=b and ME=n-1. It can also be used to rotate the contents of a register left (right) by variable n bits, by setting RB58:63=n (64-n) and ME=63.


Extend Sign Word and Shift Left Immediate

Summary: Sign-extends the low-order 32 bits of a register, shifts it left by SH bits, and places the result in another register.

The contents of the low order 32 bits of RS are sign-extended to 64 bits and then shifted left SH bits. Bits shifted out of bit 0 are lost. Zeros are supplied to vacated bits on the right. The result is placed in register RA.

SH ← sh5 || sh0:4
r  ← ROTL64(EXTS64(RS32:63), SH)
m  ← MASK(0, 63-SH)
RA ← r & m

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.


Summary: Reverses the byte order of a halfword in a register.

The contents of bits 0:15 of register RS are placed into bits 0:15 of register RA in byte-reversed order. The contents of bits 16:31 of register RS are placed into bits 16:31 of register RA in byte-reversed order.

The brh instruction is useful for reversing the byte order of 16-bit halves within a 32-bit register. Ensure that the source and destination registers are correctly specified to avoid data corruption. This operation does not require any special privileges or alignment considerations.


Summary: No operation is performed.

A prefixed 64-bit no-operation instruction that performs no operation and has no side effects. This instruction is available in the Prefixed instruction set extension and occupies 64 bits in memory.

The pnop instruction behaves as a b $+8 instruction regardless of its suffix. However, it does not cause any side effects such as modification of the Come From Address Register. If the value in the suffix of a pnop instruction corresponds to a Branch instruction, an rfebb instruction, a context synchronizing instruction other than isync, or a “Service Processor Attention” instruction, the instruction form is invalid.


Summary: Loads a double-precision floating-point value from memory into a floating-point register.

The instruction loads the doubleword in storage addressed by EA into register FRT. The effective address (EA) is the sum of the contents of register RA, or the value 0 if RA=0, and the value D, sign-extended to 64 bits.

if RA = 0 then
    b ← 0
else
    b ← (RA)
EA ← b + EXTS64(D)
FRT ← MEM(EA, 8)

The lfd instruction is commonly used to load double-precision floating-point numbers from memory into a floating-point register. Ensure that the address specified by RA and D is properly aligned on an 8-byte boundary to avoid alignment exceptions. This instruction operates at user privilege level, so no special privileges are required.


Summary: Stores a single-precision floating-point value from an FPR to memory.

The contents of register FRS are converted to single format and stored into the word in storage addressed by EA. The effective address (EA) is the sum of the contents of register RA, or the value 0 if RA=0, and the value D, sign-extended to 64 bits.

EA ← (RA|0) + EXTS64(D)
MEM(EA, 4) ← SINGLE((FRS))

The stfs instruction stores a single-precision floating-point value from FRS into memory. Ensure that the destination address is properly aligned to avoid alignment faults. The instruction operates at user privilege level and may raise an exception if the EA exceeds the storage limits or if there are access violations.


Summary: Stores a double-precision floating-point value from a register to memory.

The contents of the specified floating-point register (FRS) are stored into the double-word in storage addressed by the effective address (EA). The EA is calculated as the sum of the contents of register RA or 0 if RA=0, and the sign-extended value D.

if RA = 0 then
    b ← 0
else
    b ← (RA)
EA ← b + EXTS64(D)
MEM(EA, 8) ← (FRS)

The stfd instruction stores a double-precision floating-point value from a specified register into memory. Ensure the destination address is properly aligned to avoid alignment faults. The effective address is calculated by adding the base address in RA (or zero if RA is 0) and the sign-extended displacement D. This instruction operates at user privilege level.


Summary: Loads a doubleword-pair from storage into an even-odd pair of FPRs.

For lfdp, the doubleword-pair in storage addressed by EA is loaded into an even-odd pair of FPRs with the even-numbered FPR being loaded with the leftmost doubleword from storage and the odd-numbered FPR being loaded with the rightmost doubleword.

if RA = 0 then
    b ← 0
else
    b ← (RA)
EA ← b + EXTS(DS || 0b00)
FRTpeven ← MEM(EA, 8)
FRTpodd ← MEM(EA + 8, 8)

The instructions described in this section should not be used to access an operand in DFP Extended format when the processor is in Little-Endian mode.


Floating Convert with round Double-Precision To Unsigned Doubleword format

Summary: Converts a double-precision floating-point value to an unsigned 64-bit integer using rounding.

Let src be the double-precision floating-point value in FRB. If src is a NaN, then the result is 0x0000_0000_0000_0000, VXCVI is set to 1, and if src is an SNaN, VXSNAN is set to 1. Otherwise, src is rounded to a floating-point integer using the rounding mode specified by RN. If the rounded value is greater than 264-1, then the result is 0xFFFF_FFFF_FFFF_FFFF, and VXCVI is set to 1. Otherwise, if the rounded value is less than 0, then the result is 0x0000_0000_0000_0000, and VXCVI is set to 1. Otherwise, the result is the rounded value converted to 64-bit unsigned-integer format, and XX is set to 1 if the result is inexact.

if src is a NaN then
    FRT <- 0x0000_0000_0000_0000
    VXCVI <- 1
    if src is an SNaN then VXSNAN <- 1
else
    rounded_value <- round(src, RN)
    if rounded_value > 264-1 then
        FRT <- 0xFFFF_FFFF_FFFF_FFFF
        VXCVI <- 1
    else if rounded_value < 0 then
        FRT <- 0x0000_0000_0000_0000
        VXCVI <- 1
    else
        FRT <- convert_to_unsigned_integer(rounded_value)
        XX <- is_inexact(FRT)
if not enabled Invalid Operation Exception then
    place result into FRT

FPSCR, (FR, FI, FX, XX, VXSNAN, VXCVI), CR1, (if, Rc=1), CR0

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.


Floating Convert with round Double-Precision To Unsigned Word format

Summary: Converts a double-precision floating-point value to an unsigned integer using rounding.

The instruction converts the double-precision floating-point value in FRB to an unsigned integer using the rounding mode specified by RN. If the result is out of range, it sets VXCVI and returns 0xFFFF_FFFF or 0x0000_0000. The result is placed into FRT32:63 and FRT0:31 is undefined.

if src is NaN then
    result <- 0x0000_0000
    VXCVI <- 1
    if src is SNaN then VXSNAN <- 1
else
    rounded_value <- round(src, RN)
    if rounded_value > 2^32 - 1 then
        result <- 0xFFFF_FFFF
        VXCVI <- 1
    else if rounded_value < 0 then
        result <- 0x0000_0000
        VXCVI <- 1
    else
        result <- convert_to_unsigned_int(rounded_value)
        XX <- is_inexact(result)
FRT32:63 <- result
FRT0:31 is undefined


Summary: Rounds a floating-point operand towards +infinity and places the result into a register.

The floating-point operand in register FRB is rounded to an integral value using the rounding mode round toward +infinity, and the result is placed into register FRT. FPRF is set to the class and sign of the result, except for Invalid Operation Exceptions when VE=1.

if 'frip' then
    FRT <- round_towards_plus_infinity(FRB)
else if 'frip.' then
    FRT <- round_towards_plus_infinity(FRB)
    update_CR1_based_on_result(FRT)


Summary: Moves the control and non-sticky status bits from the FPSCR to a general-purpose register.

The contents of the control bits in the FPSCR (bits 29:31) and the non-sticky status bits (bits 45:51) are placed into the corresponding bits in register FRT. All other bits in register FRT are set to 0.

mffsl permits software to read the control and non-sticky status bits in the FPSCR without the higher latency typically associated with accessing the sticky status bits.


Summary: Tests the data class of a DFP operand and sets the CR field.

Tests the data class of the DFP operand in FRA against the data class mask DCM and stores the test result in condition register field BF. The instruction sets CR field BF based on whether FRA belongs to any of the classes specified by the 8-bit mask DCM. This is a Decimal Floating-Point instruction that requires the DFP category.

if (FRA matches any data class in DCM) then
  CR[BF] ← 0b0010
else
  CR[BF] ← 0b0000

The dtstdc instruction is used to test the data class of a decimal floating-point operand against a specified mask. Ensure that the DFP operand is correctly aligned and that the DCM mask accurately reflects the desired data classes for testing. The instruction updates the CR field BF and FPSCR FPCC based on the sign and data class match, which can be used in conditional logic within your program.


Decimal Floating-Point Test Significance Single

Summary: Tests the significance of a DFP value in FPR[FRB] against a reference significance.

Compares the number of significant digits (NSDb) of the DFP value in FPR[FRB] with the reference significance specified by bits 58:63 of FPR[FRA]. The result is placed into CR field BF and FPCC.

let k be the contents of bits 58:63 of FPR[FRA]
let NSDb be the number of significant digits of the DFP value in FPR[FRB]
if k != 0 and k < NSDb then
    CR field BF <- 0b0010
    FPCC <- 0b0010
else if k != 0 and k > NSDb, or k = 0 then
    CR field BF <- 0b0100
    FPCC <- 0b0100
else if k != 0 and k = NSDb then
    CR field BF <- 0b1000
    FPCC <- 0b1000
else
    CR field BF <- 0b0001
    FPCC <- 0b0001

The dtstsf instruction is used to compare the number of significant digits in a decimal floating-point value with a reference significance. Ensure that the FPR registers are correctly aligned and initialized before use. The instruction modifies both CR and FPSCR, so check these registers after execution for the comparison result. This instruction operates at user privilege level but may raise exceptions if the input values are invalid or out of range.


Summary: Adjusts the value to a form having the specified exponent in the range -16 to 15.

The DFP operand in FRB is converted and rounded to the form with the exponent specified by TE based on the rounding mode specified in the RMC field. The result of that form is placed in FRT. The sign of the result is the same as the sign of the operand in FRB.

if 'dquai' then
    FRT <- (FRB) adjusted to exponent TE with rounding based on RMC
    if result would cause overflow from the most significant digit, then
        FRT <- default QNaN
    else
        FRT <- adjusted value (left shifted with matching exponent)
if 'dquai.' then
    FRT <- (FRB) adjusted to exponent TE with rounding based on RMC
    if result would cause overflow from the most significant digit, then
        FRT <- default QNaN
    else
        FRT <- adjusted value (left shifted with matching exponent)
    CR1 <- updated

FPSCR(FPRF, FR, FI, FX, XX, VXSNAN, VXCVI), CR(CR1), CR0

DFP Quantize Immediate can be used to adjust values to a form having the specified exponent in the range -16 to 15. If the adjustment requires the significand to be shifted left, then: if the result would cause overflow from the most significant digit, the result is a default QNaN; otherwise the result is the adjusted value (left shifted with matching exponent). If the adjustment requires the significand to be shifted right, the result is rounded based on the value of the RMC field.


Summary: Converts a decimal floating-point value to a fixed-point integer.

Converts a Decimal Floating-Point value in FRA to a fixed-point integer representation and stores the result in FRT. This instruction requires the Decimal Floating-Point category and may set exception flags in FPSCR if conversion fails or overflow/underflow occurs.

FRT ← convert_dfp_to_fixed(FRA)
# FPSCR exception flags updated as needed

The ctfix instruction is used to convert floating-point numbers to fixed-point integers. Ensure the source operand is properly aligned and within valid range to avoid exceptions. Be cautious of rounding modes as they can affect the result significantly. This instruction operates at user privilege level but may trigger exceptions like inexact conversion or invalid operations, which need to be handled appropriately.


Store Vector Element Halfword Indexed X-form

Summary: Stores a halfword element from a vector register to memory.

Stores a halfword (16 bits) element from vector register VRS to memory at the indexed address (RA|0) + RB. The element is selected based on the least significant bits of the effective address to determine alignment. This is a VMX/AltiVec instruction that accesses memory with vector element granularity.

EA ← (RA|0) + RB
element_index ← EA[61:62]
[EA & ~0x1] ← VRS[element_index * 16 : element_index * 16 + 15]

Unless bits 60:62 of the address are known to match the halfword offset of the subject halfword element in VSR[VRS+32], software should use Vector Splat to splat the subject halfword element before performing the store.


Summary: Packs the upper halves of doublewords from two source vectors into a destination vector.

Packs unsigned doubleword elements from source vectors VRA and VRB into a destination vector VRT by selecting the upper halves of each doubleword and concatenating them in pack order. This VMX/AltiVec instruction performs modulo packing without saturation and operates on 64-bit elements.

This instruction is used for packing the upper halves of doublewords from two source vectors into a destination vector. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set; otherwise, a Vector Unavailable exception will be raised. The operation processes each element independently, so there are no ordering requirements between elements, but alignment of input vectors to doubleword boundaries is recommended for optimal performance.


Summary: Shifts the contents of vector elements left by a variable amount.

Shifts each element of the source vector left by a variable amount specified in the corresponding element of the shift amount vector. The shift amount for each element is taken from the least significant bits of the corresponding element in VRB. No status flags are affected.

The vslv instruction is used to perform variable left shifts on each byte of a vector register. Ensure that the shift amounts in VSR[VRB+32] are within the valid range (0-7) to avoid unexpected results. This instruction operates at user privilege level and will raise an exception if the Vector Facility is not enabled.


Summary: Shifts each element of the source vector right by a variable amount specified in another vector.

Shifts each element of the source vector right by a variable amount specified in the corresponding element of the shift count vector. The shift amount for each element is taken from the least significant bits of the corresponding element in VRB. No status flags are affected.

The vsrv instruction shifts each element of the source vector right by a variable amount specified in another vector. Ensure that the shift amounts are within the range of 0 to 127 to avoid undefined behavior. This instruction operates at user privilege level and does not generate exceptions for normal operation.


Vector Extract Unsigned Byte to GPR using GPR-specified Left-Index VX-form

Summary: Extracts an unsigned byte from a vector register and places it into a general-purpose register using the left-index specified in another general-purpose register.

The contents of byte element index of VSR[VRB+32] are placed into bits 56:63 of GPR[RT], where index is the contents of bits 60:63 of GPR[RA]. The contents of bits 0:55 of GPR[RT] are set to 0.

RA

Source General Purpose Register containing the index

if MSR.VEC=0 then
    Vector_Unavailable()
index ← GPR[RA].bit[60:63]
GPR[RT] ← EXTZ64(VSR[VRB+32].byte[index])
// The contents of bits 0:55 of GPR[RT] are set to 0.

This instruction extracts an unsigned byte from a vector register and places it into the upper 8 bits of a general-purpose register, zeroing out the lower 56 bits. Ensure that the index in GPR[RA] is within bounds (0-15) to avoid undefined behavior. This operation requires the Vector Facility to be enabled; otherwise, a Vector Unavailable exception will occur.


Vector Extract Unsigned Word to GPR using GPR-specified Left-Index VX-form

Summary: Extracts an unsigned word from a vector register and places it into a general-purpose register.

The instruction extracts an unsigned word from the specified byte index in VSR[VRB+32] and places it into bits 32:63 of GPR[RT]. The contents of bits 0:31 of GPR[RT] are set to 0. If MSR.VEC=0, a Vector_Unavailable() exception is raised.

Source General Purpose Register (contains the index)

if MSR.VEC=0 then
    Vector_Unavailable()
index ← GPR[RA].bit[60:63]
GPR[RT] ← EXTZ64(VSR[VRB+32].byte[index:index+3])
if index > 12 then
    undefined

This instruction is used to extract an unsigned word from a vector register and place it into the upper half of a general-purpose register. Ensure that the MSR.VEC bit is set to avoid a Vector_Unavailable exception. The index for extraction is derived from the top 4 bits of the RA register, so be cautious with the value in RA to prevent undefined behavior when the index exceeds 12.


Vector Extract Double Unsigned Halfword to VSR using GPR-specified Left-Index VA-form

Summary: Extracts a double unsigned halfword from two vector registers and places it into another vector register based on the index specified in a general-purpose register.

The instruction extracts a double unsigned halfword from the concatenation of VSR[VRA+32] and VSR[VRB+32] using the index specified in bits 59:63 of GPR[RC]. The extracted byte elements are zero-extended and placed into doubleword 0 of VSR[VRT+32], while doubleword 1 is set to zero.

RC

General Purpose Register specifying the index

if MSR.VEC=0 then
    Vector_Unavailable()
index ← GPR[RC].bit[59:63]
vsrc.qword[0] ← VSR[VRA+32]
vsrc.qword[1] ← VSR[VRB+32]
VSR[VRT+32].dword[0] ← EXTZ64(vsrc.byte[index:index+1])
VSR[VRT+32].dword[1] ← 0x0000_0000_0000_0000

This instruction is used to extract a double unsigned halfword from two vector registers and place it into another vector register. Ensure that the index specified in GPR[RC] is within bounds to avoid undefined behavior. The operation requires the VEC bit in the MSR to be set; otherwise, a Vector Unavailable exception will occur.


Vector Extract Double Unsigned Word to VSR using GPR-specified Left-Index VA-form

Summary: Extracts a doubleword from the concatenation of two vector registers based on an index specified in a general-purpose register.

The instruction extracts a doubleword from the concatenation of the contents of VSR[VRA+32] and VSR[VRB+32] based on the index derived from bits 59:63 of GPR[RC]. The extracted bytes are zero-extended into the first doubleword of VSR[VRT+32], and the second doubleword is set to zero.

if MSR.VEC=0 then
    Vector_Unavailable()
index ← GPR[RC].bit[59:63]
src.qword[0] ← VSR[VRA+32]
src.qword[1] ← VSR[VRB+32]
VSR[VRT+32].dword[0] ← EXTZ64(src.byte[index:index+3])
VSR[VRT+32].dword[1] ← 0x0000_0000_0000_0000
if index > 28 then
    undefined result

This instruction is used to extract a doubleword from the concatenation of two vector registers based on an index specified in a general-purpose register. Ensure that the index does not exceed 28 to avoid undefined results. The operation requires the VEC bit in the Machine State Register (MSR) to be set; otherwise, a Vector Unavailable exception will occur.


Vector Extract Double Doubleword to VSR using GPR-specified Left-Index VA-form

The instruction extracts a doubleword from the concatenation of the contents of VSR[VRA+32] and VSR[VRB+32] using an index derived from bits 59:63 of GPR[RC]. The extracted byte elements are placed into doubleword 0 of VSR[VRT+32], while doubleword 1 is set to zero.

if MSR.VEC=0 then
    Vector_Unavailable()
index ← GPR[RC].bit[59:63]
src.qword[0] ← VSR[VRA+32]
src.qword[1] ← VSR[VRB+32]
VSR[VRT+32].dword[0] ← src.byte[index:index+7]
VSR[VRT+32].dword[1] ← 0x0000_0000_0000_0000

This instruction is useful for extracting a specific doubleword from two VSX registers based on an index specified in a GPR. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise a Vector Unavailable exception. The index is derived from bits 59:63 of the GPR, so ensure these bits are correctly set to access the desired doubleword. Note that the upper doubleword of the destination register is always zeroed.


Vector Insert Byte from GPR using GPR-specified Left-Index VX-form

Summary: Inserts a byte from a general-purpose register into a vector register at an index specified by another general-purpose register.

The contents of bits 56:63 of GPR[RB] are placed into byte element index of VSR[VRT+32], where index is the contents of bits 60:63 of GPR[RA]. All other byte elements of VSR[VRT+32] remain unchanged.

if MSR.VEC=0 then
    Vector_Unavailable()
index ← GPR[RA].bit[60:63]
src.byte[0:15] ← 0
VSR[VRT+32].byte[index] ← GPR[RB].bit[56:63]

The vinsblx instruction is used to insert a byte from a general-purpose register (GPR) into a vector register, using another GPR to specify the index. Ensure that the MSR.VEC bit is set to 1; otherwise, a Vector_Unavailable exception will be raised. The index must be within the range of 0-15, as it specifies which byte element in the vector register to update. This instruction does not require any special alignment and operates at privilege level 0.


Vector Insert Halfword from GPR using GPR-specified Left-Index VX-form

Summary: Inserts the high halfword of a general-purpose register into a vector register at a position specified by another general-purpose register.

The contents of bits 48:63 of GPR[RB] are placed into byte elements index:index+1 of VSR[VRT+32], where index is the contents of bits 60:63 of GPR[RA].

if MSR.VEC=0 then
    Vector_Unavailable()
index ← GPR[RA].bit[60:63]
src.byte[0:15] ← 0
VSR[VRT+32].byte[index:index+1] ← GPR[RB].bit[48:63]

The vinshlx instruction is used to insert the upper halfword of a general-purpose register (GPR) into specific byte elements of a vector register. Ensure that the index specified in bits 60-63 of RA is within valid bounds to avoid undefined behavior. This instruction requires the Vector Facility to be enabled; otherwise, it will raise an exception.


Vector Insert Word from GPR using GPR-specified Left-Index VX-form

Summary: Inserts the contents of bits 32:63 of a general-purpose register into byte elements of a vector register based on an index specified in another general-purpose register.

The instruction inserts the contents of bits 32:63 of GPR[RB] into byte elements index:index+3 of VSR[VRT+32], where index is the value of bits 60:63 of GPR[RA].

RB

Source General Purpose Register containing the data to insert

if MSR.VEC=0 then
    Vector_Unavailable()
index ← GPR[RA].bit[60:63]
VSR[VRT+32].byte[index:index+3] ← GPR[RB].bit[32:63]

This instruction is used to insert the upper 32 bits of a general-purpose register (GPR) into specific byte elements of a vector register. Ensure that the index specified by the top 4 bits of GPR[RA] is within the valid range for the target vector register. This operation requires the Vector Facility to be enabled; otherwise, it will raise an exception.


Vector Insert Doubleword from GPR using GPR-specified Left-Index VX-form

Summary: Inserts a doubleword from a general-purpose register into a vector register at a position specified by another general-purpose register.

The contents of GPR[RB] are placed into byte elements index:index+7 of VSR[VRT+32], where index is the contents of bits 60:63 of GPR[RA]. All other byte elements of VSR[VRT+32] remain unchanged.

RA

Source General Purpose Register (contains index)

RB

Source General Purpose Register (contains data to insert)

if MSR.VEC=0 then
    Vector_Unavailable()
index ← GPR[RA].bit[60:63]
VSR[VRT+32].byte[index:index+7] ← GPR[RB]

The vinsdlx instruction is used to insert the contents of a general-purpose register (GPR) into a specific byte range within a vector register. Ensure that the index specified in bits 60:63 of the RA register is within the valid range (0-15) to avoid undefined behavior. This instruction requires the Vector Facility to be enabled; otherwise, it will raise an exception.


Vector Insert Word from GPR using Immediate-specified Index

Summary: Inserts the contents of a word from a general-purpose register into a vector register at an immediate-specified index.

The contents of bits 32:63 of GPR[RB] are placed into byte elements UIM:UIM+3 of VSR[VRT+32]. All other byte elements of VSR[VRT+32] are not modified. If UIM is greater than 12, the result is undefined.

if MSR.VEC=0 then
    Vector_Unavailable()
VSR[VRT+32].byte[UIM:UIM+3] ← GPR[RB].bit[32:63]

The vinsw instruction is used to insert the upper 32 bits of a general-purpose register (GPR) into a specific byte range within a vector register. Ensure that the immediate index (UIM) does not exceed 12 to avoid undefined behavior. This instruction operates at user privilege level and will raise an exception if the Vector Facility is unavailable.


Vector Insert Byte from VSR using GPR-specified Left-Index VX-form

Summary: Inserts a byte from one vector register into another based on an index specified in a general-purpose register.

The instruction inserts the contents of bits 56:63 of VSR[VRB+32] into byte element 'index' of VSR[VRT+32], where 'index' is the value of bits 60:63 of GPR[RA].

if MSR.VEC=0 then
    Vector_Unavailable()
index ← GPR[RA].bit[60:63]
VSR[VRT+32].byte[index] ← VSR[VRB+32].bit[56:63]

This instruction is used to insert a byte from one vector register into another, with the target index specified by bits 60-63 of a general-purpose register. Ensure that the MSR.VEC bit is set to enable vector operations; otherwise, a Vector_Unavailable exception will be raised. The index must be within the valid range for vector elements to avoid undefined behavior.


Vector Insert Halfword from VSR using GPR - specified Left-Index VX-form

Summary: Inserts halfword from a vector register into another vector register at a position specified by a general-purpose register.

The instruction inserts the contents of bits 48:63 of VSR[VRB+32] into byte elements index:index+1 of VSR[VRT+32], where index is the contents of bits 60:63 of GPR[RA].

if MSR.VEC=0 then
    Vector_Unavailable()
index ← GPR[RA].bit[60:63]
src.byte[0:15] ← 0
VSR[VRT+32].byte[index:index+1] ← VSR[VRB+32].bit[48:63]

This instruction is used to insert the upper halfword of a vector register into specific byte elements of another vector register, based on an index derived from a general-purpose register. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. The index must be within the valid range for vector operations to avoid undefined behavior.


Vector Insert Word from VSR using GPR-specified Left-Index VX-form

Summary: Inserts a word from a vector register into another vector register at a position specified by a general-purpose register.

The contents of bits 32:63 of VSR[VRB+32] are placed into byte elements index:index+3 of VSR[VRT+32], where index is the contents of bits 60:63 of GPR[RA].

if MSR.VEC=0 then
    Vector_Unavailable()
index ← GPR[RA].bit[60:63]
VSR[VRT+32].byte[index:index+3] ← VSR[VRB+32].bit[32:63]

This instruction is used to insert a 4-byte word from one vector register into another, with the destination index specified by the upper 4 bits of a general-purpose register. Ensure that the MSR.VEC bit is set to enable vector operations; otherwise, a Vector_Unavailable exception will be raised. The source and destination registers must be in the range V32-V63. Be cautious of alignment issues if the index does not align with byte boundaries.


Vector Multiply Even Unsigned Doubleword

Summary: Multiplies the even doublewords of two vector registers and places the result in another vector register.

The instruction multiplies the unsigned integer values in the even doublewords of VSR[VRA+32] and VSR[VRB+32], and stores the 128-bit product in VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
src1 ←EXTZ(VSR[VRA+32].dword[0])
src2 ←EXTZ(VSR[VRB+32].dword[0])
VSR[VRT+32] ←CHOP128(src1 × src2)

This instruction is used for multiplying unsigned integers in the even doublewords of two vector registers and storing the 128-bit product. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. The operation is performed on the least significant doubleword of each input register, and the result is truncated to 128 bits before being stored.


The instruction multiplies the signed integer values in the even doublewords of VSR[VRA+32] and VSR[VRB+32], and stores the 128-bit product in VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
src1 ←EXTS(VSR[VRA+32].dword[0])
src2 ←EXTS(VSR[VRB+32].dword[0])
VSR[VRT+32] ←CHOP128(src1 × src2)

This instruction is used for multiplying signed integers in the even doublewords of two vector registers and storing the 128-bit product. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. The operation is performed on the first doubleword of each input register, and the result is truncated to 128 bits before being stored in the destination register.


Summary: Multiplies the contents of two vector registers and places the low-order 32 bits of each product into a target vector register.

For vmuluwm, each word element in VSR[VRA+32] is multiplied by the corresponding word element in VSR[VRB+32]. The low-order 32 bits of each product are placed into the corresponding word element in VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ←EXTZ(VSR[VRA+32].word[i])
    src2 ←EXTZ(VSR[VRB+32].word[i])
    VSR[VRT+32].word[i] ←CHOP32(src1 × src2)
end

vmuluwm can be used for unsigned or signed integers.


Summary: Multiplies the contents of two vector registers and places the low-order 64 bits of each product into a target vector register.

For vmulld, the integer values in doubleword elements of VSR[VRA+32] are multiplied by the corresponding integer values in doubleword elements of VSR[VRB+32]. The low-order 64 bits of each product are placed into doubleword elements of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    src1 ←EXTS(VSR[VRA+32].dword[i])
    src2 ←EXTS(VSR[VRB+32].dword[i])
    VSR[VRT+32].dword[i] ←CHOP64(src1 × src2)
end

This instruction multiplies the integer values in doubleword elements of two vector registers and stores the low-order 64 bits of each product into another vector register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. The operation processes two doublewords per iteration, so be cautious with loop bounds if using this in a larger computation.


Vector Multiply-High-Add Signed Halfword Saturate

Summary: Performs a vector multiply-high-add signed halfword operation with saturation.

For each integer value i from 0 to 7, the signed integer value in halfword element i of VSR[VRA+32] is multiplied by the signed integer value in halfword element i of VSR[VRB+32], producing a 32-bit signed integer product. Bits 0:16 of the product are added to the signed integer value in halfword element i of VSR[VRC+32]. The low-order 16 bits of the result are placed into halfword element i of VSR[VRT+32]. If the intermediate result is greater than 2^15-1, the result saturates to 2^15 -1 and SAT is set to 1. If the intermediate result is less than -2^15, the result saturates to -2^15 and SAT is set to 1.

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 7
    src1 ←EXTS(VSR[VRA+32].hword[i])
    src2 ←EXTS(VSR[VRB+32].hword[i])
    src3 ←EXTS(VSR[VRC+32].hword[i])
    result ←((src1 × src2) >> 15) + src3
    VSR[VRT+32].hword[i] ←si16_CLAMP(result)
    VSCR.SAT ←sat_flag

This instruction is commonly used in applications requiring vectorized operations on signed halfwords, such as audio processing or graphics rendering. Ensure that the input vectors are properly aligned to avoid performance penalties. Be aware of saturation conditions; if any result exceeds the 16-bit signed integer range, it will be clamped and the VSCR.SAT flag will be set. This instruction operates at user privilege level.


Vector Multiply-Low-Add Unsigned Halfword Modulo

Summary: Performs a vector multiply-low-add unsigned halfword modulo operation.

For each integer value i from 0 to 7, the unsigned integer value in halfword element i of VSR[VRA+32] is multiplied by the unsigned integer value in halfword element i in VSR[VRB+32]. The product is added to the unsigned integer value in halfword element i of VSR[VRC+32]. The low-order 16 bits of the sum are placed into halfword element i of VSR[VRT+32].

if MSR.VEC=0 then Vector_Unavailable()
do i = 0 to 7
    src1 ←EXTZ(VSR[VRA+32].hword[i])
    src2 ←EXTZ(VSR[VRB+32].hword[i])
    src3 ←EXTZ(VSR[VRC+32].hword[i])
    VSR[VRT+32].hword[i] ← CHOP16((src1 × src2) + src3)
end

vmladduhm can be used for unsigned or signed integers.


Summary: Performs a vector multiply-sum operation with mixed byte elements.

For each integer value i from 0 to 3, do the following. For each integer value j from 0 to 3, do the following. The signed integer value in byte element j of word element i of VSR[VRA+32] is multiplied by the unsigned integer value in byte element j of word element i of VSR[VRB+32]. The sum of the four products is added to the signed integer value in word element i of VSR[VRC+32]. The low-order 32 bits of the result are placed into word element i of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    temp ←EXTS(VSR[VRC+32].word[i])
    do j = 0 to 3
        src1 ←EXTS(VSR[VRA+32].word[i].byte[j])
        src2 ←EXTZ(VSR[VRB+32].word[i].byte[j])
        temp ←temp + (src1 × src2)
    end
    VSR[VRT+32].word[i] ←CHOP32(temp)
end

This instruction is useful for performing vectorized multiply-sum operations on byte elements. Ensure that the vector registers are properly aligned and that the Vector Facility (MSR.VEC) is enabled to avoid exceptions. The result is truncated to 32 bits, so be cautious of overflow if the sum exceeds this range.


Vector Multiply-Sum Unsigned Halfword Saturate

Summary: Performs a vector multiply-sum operation on unsigned halfwords and saturates the result.

Computes the sum of products of unsigned halfword elements from VRA and VRB, adds the result to the corresponding word element in VRC, and saturates the final result to unsigned 32-bit range. This instruction requires VMX support and no condition flags are affected.

The vmsumuhs instruction is commonly used for performing vectorized multiply-sum operations on unsigned halfwords, which can be particularly useful in graphics and signal processing applications. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will occur. The operation saturates results to prevent overflow, setting the VSCR.SAT flag if saturation occurs. This instruction operates on 128-bit vectors, so ensure proper alignment of vector registers for optimal performance.


Vector Multiply-Sum Unsigned Doubleword Modulo

Summary: Performs a horizontal add of the doubleword elements in VSR[VRA+32] using vmsumudm.

The instruction performs a horizontal add of the doubleword elements in VSR[VRA+32]. It can also be used for horizontal subtract, multiply even unsigned doubleword, and multiply odd unsigned doubleword operations by setting specific values in VSR[VRB+32] and VSR[VRC+32].

if MSR.VEC=0 then
    Vector_Unavailable()
temp ←EXTZ(VSR[VRC+32])
do i = 0 to 1
    src1  ←EXTZ(VSR[VRA+32].dword[i])
    src2  ←EXTZ(VSR[VRB+32].dword[i])
    temp ←temp + (src1 × src2)
end
VSR[VRT+32] ←CHOP128(temp)

A horizontal add of the doubleword elements in VSR[VRA+32] can be performed using vmsumudm when VSR[VRB+32] contains the doubleword integer values {1,1} and VSR[VRC+32] contains the quad-word integer value 0. A horizontal subtract of the doubleword elements in VSR[VRA+32] can be performed using vmsumudm when VSR[VRB+32] contains the doubleword integer values {1,-1} and VSR[VRC+32] contains the quad-word integer value 0. A multiply even unsigned doubleword operation can be performed using vmsumudm when the contents of doubleword element 1 of VSR[VRA+32] or VSR[VRB+32] are 0 and the contents of VSR[VRC+32] to 0. A multiply odd unsigned doubleword operation can be performed using vmsumudm when the contents of doubleword element 0 of VSR[VRA+32] or VSR[VRB+32] are 0 and the contents of VSR[VRC+32] to 0.


Vector Multiply-Sum & write Carry-out Unsigned Doubleword

Summary: Performs vector multiply-sum and writes the carry-out of the low-order 128 bits to a destination register.

The instruction performs two unsigned doubleword multiplications, sums the results along with an additional source register, and writes the carry-out of the low-order 128 bits to the destination register.

if MSR.VEC=0 then Vector_Unavailable()

temp ←EXTZ(VSR[VRC+32])
do i = 0 to 1
    src1  ←EXTZ(VSR[VRA+32].dword[i])
    src2  ←EXTZ(VSR[VRB+32].dword[i])
    temp ←temp + (src1 × src2)
end

VSR[VRT+32] ←CHOP128(temp >> 128)

This instruction is useful for performing high-precision arithmetic operations involving unsigned doublewords. Ensure that the vector facility is enabled by checking and setting the appropriate bits in the Machine State Register (MSR). Be cautious of overflow conditions, as the carry-out from the low-order 128 bits is written to the destination register. The instruction operates on 64-bit elements, so ensure proper alignment for optimal performance.


Summary: Divides the contents of two vector registers and updates the result in another vector register.

For vdivsw, each word element of VSR[VRA+32] is divided by the corresponding word element of VSR[VRB+32]. The quotient is placed into the corresponding word element of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    dividend ←EXTS(VSR[VRA+32].word[i])
    divisor  ←EXTS(VSR[VRB+32].word[i])
    VSR[VRT+32].word[i] ←CHOP32(dividend ÷ divisor)
end

vdivsw performs element-wise signed word division. Ensure that the vector facility is enabled (MSR.VEC=1) to avoid a Vector_Unavailable exception. Handle potential division by zero and overflow conditions in your application logic.


For vdivesw, each word element of VSR[VRA+32] is treated as a signed integer, shifted left by 32 bits, and divided by the corresponding word element of VSR[VRB+32], which is also treated as a signed integer. The quotient is placed into the corresponding word element of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    dividend ←EXTS(VSR[VRA+32].word[i]) << 32
    divisor  ←EXTS(VSR[VRB+32].word[i])
    VSR[VRT+32].word[i] ←CHOP32(dividend ÷ divisor)
end

The vdivesw instruction performs a signed division on each word element of the input vectors, shifting the dividend left by 32 bits before dividing. Ensure that the vector facility is enabled (MSR.VEC=1) to avoid exceptions. Be cautious of division by zero, which may result in undefined behavior or exceptions. The operation is performed at the user privilege level unless otherwise specified.


For vdivsd, each doubleword element in VSR[VRA+32] is divided by the corresponding doubleword element in VSR[VRB+32]. The quotient is placed into the corresponding doubleword element in VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    dividend ←EXTS(VSR[VRA+32].dword[i])
    divisor  ←EXTS(VSR[VRB+32].dword[i])
    VSR[VRT+32].dword[i] ←CHOP64(dividend ÷ divisor)
end

This instruction performs element-wise division of signed doublewords. Ensure that the vector facility is enabled (MSR.VEC=1) to avoid exceptions. Handle potential division by zero and overflow conditions in your application logic.


Vector Divide Extended Signed Doubleword

Summary: Performs extended signed doubleword division on vector elements.

For vdivesd, each element of the source vectors VRA and VRB is treated as a signed doubleword. The dividend is shifted left by 64 bits, then divided by the divisor. The quotient is placed into the corresponding element of the destination vector VRT.

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    dividend ←EXTS(VSR[VRA+32].dword[i]) << 64
    divisor  ←EXTS(VSR[VRB+32].dword[i])
    VSR[VRT+32].dword[i] ←CHOP64(dividend ÷ divisor)
end

This instruction is used for performing extended signed doubleword division on vector elements. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation involves shifting each dividend left by 64 bits and then dividing it by the corresponding divisor, with the quotient being stored in the destination vector. Be cautious of potential division by zero errors, which may result in undefined behavior or exceptions.


Summary: Divides the contents of two vector registers and updates the destination register with the quotient.

For vdivsq, the signed integer value in VSR[VRA+32] is divided by the signed integer value in VSR[VRB+32], and the result is placed into VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()

dividend ← EXTS(VSR[VRA+32])
divisor ← EXTS(VSR[VRB+32])
VSR[VRT+32] ← CHOP128(dividend ÷ divisor)

Let src1 be the signed integer value in VSR[VRA+32].
Let src2 be the signed integer value in VSR[VRB+32].
The quotient of src1 divided by src2 is placed into VSR[VRT+32].
The quotient is the unique signed integer that satisfies dividend = (quotient × divisor) + r where 0 ≤ remainder < |divisor| if the dividend is nonnegative, and -|divisor| < remainder ≤ 0 if the dividend is negative.

If an attempt is made to perform any of the divisions <anything> ÷ 0 or 0x8000_0000_0000_0000_0000_0000_0000_0000 ÷ -1 then the contents of VSR[VRT+32] are undefined.

The vdivsq instruction performs a signed division of two 64-bit integers stored in vector registers. Ensure that the divisor is not zero to avoid undefined results. The operation requires the Vector Facility (MSR.VEC) to be enabled; otherwise, a Vector_Unavailable exception will occur. Be cautious with edge cases like dividing the smallest possible negative number by -1, which results in an undefined quotient.


For vdivesq, the signed integer value in VSR[VRA+32] concatenated with 128 0s is divided by the signed integer value in VSR[VRB+32]. The quotient is placed into VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()

dividend ← EXTS(VSR[VRA+32]) << 128
divisor ← EXTS(VSR[VRB+32])
VSR[VRT+32] ← CHOP128(dividend ÷ divisor)

This instruction is used for dividing a signed quadword value by another signed quadword value. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The operation involves extending the sign of the operands and handling division with potential overflow or zero divisor scenarios carefully.


Summary: Performs modulo operation on signed integers in vector registers.

For vmodsw, the signed integer in word element i of VSR[VRA+32] is divided by the signed integer in word element i of VSR[VRB+32]. The remainder is placed into word element i of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    dividend ←EXTS(VSR[VRA+32].word[i])
    divisor  ←EXTS(VSR[VRB+32].word[i])
    VSR[VRT+32].word[i] ←CHOP32(dividend % divisor)
end

The vmodsw instruction performs element-wise signed modulo division on vectors. Ensure that the vector registers are properly aligned and that the Vector Facility is enabled (MSR.VEC=1). Be cautious of division by zero, which may result in undefined behavior or exceptions. This operation is typically used in scenarios requiring periodic or cyclic calculations with signed integers.


Summary: Performs vector modulo signed doubleword operation.

For vmodsd, each integer value i from 0 to 1, the signed integer in doubleword element i of VSR[VRA+32] is divided by the signed integer in doubleword element i of VSR[VRB+32]. The remainder is placed into doubleword element i of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    dividend ←EXTS(VSR[VRA+32].dword[i])
    divisor  ←EXTS(VSR[VRB+32].dword[i])
    VSR[VRT+32].dword[i] ←CHOP64(dividend % divisor)
end

The vmodsd instruction performs element-wise signed modulo division on doublewords. Ensure that the vector facility is enabled (MSR.VEC=1) to avoid a Vector_Unavailable exception. Handle potential division by zero, as it will result in an undefined remainder. The operation is performed on elements 0 and 1 of the specified vector registers.


Summary: Performs signed modulo operation on quadword elements of two vector registers and stores the result in another vector register.

Computes the signed modulo operation on quadword elements: each quadword element of VRA is divided by the corresponding quadword element of VRB and the remainder is stored in VRT. Division by zero results in undefined behavior. No condition flags are affected.

for i in 0 to 1 do
  dividend ← (s128)VRA[i*128:(i+1)*128-1]
  divisor ← (s128)VRB[i*128:(i+1)*128-1]
  VRT[i*128:(i+1)*128-1] ← dividend mod divisor
end for

The vmodsq instruction performs a signed modulo operation on quadword elements. Ensure that the vector facility is enabled (MSR.VEC=1) to avoid exceptions. Be cautious with division by zero and handle cases where the dividend is 0x8000_0000_0000_0000_0000_0000_0000_0000 and the divisor is -1, as the result is undefined.


Summary: Compares the signed doublewords of two vector registers and stores the maximum value in a third vector register.

For vmaxsd, each pair of corresponding doublewords from VSR[VRA+32] and VSR[VRB+32] are compared. The larger value is stored in the corresponding position in VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    src1 ← VSR[VRA+32].dword[i]
    src2 ← VSR[VRB+32].dword[i]
    gt_flag ← EXTS(src1) > EXTS(src2)
    VSR[VRT+32].dword[i] ← gt_flag=1 ? src1 : src2
end

The vmaxsd instruction is used to perform element-wise maximum operations on signed doublewords from two vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation compares each pair of corresponding elements and stores the larger value in the destination register. This instruction operates at the user privilege level.


Summary: Compares the signed doublewords of two vector registers and stores the minimum values in a third vector register.

For vminsd, each pair of corresponding doublewords from VSR[VRA+32] and VSR[VRB+32] is compared. The smaller value is stored in the corresponding position in VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    src1 ← VSR[VRA+32].dword[i]
    src2 ← VSR[VRB+32].dword[i]
    lt_flag ← EXTS(src1) < EXTS(src2)
    VSR[VRT+32].dword[i] ← lt_flag=1 ? src1 : src2
end

This instruction is used to perform element-wise minimum comparison on signed doublewords from two vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation respects the sign of the operands, so negative numbers are correctly handled. There are no specific alignment requirements for the data in the vector registers.


Summary: Compares two quadwords and sets the result to all ones if they are equal, otherwise all zeros.

Compares each quadword element of VRA with the corresponding quadword element of VRB for equality; the result for each quadword is all ones if equal or all zeros if not equal. If the Rc bit is set, CR6 is updated with summary information. Requires VMX support.

for i in 0 to 1 do
  if VRA[i*128:(i+1)*128-1] = VRB[i*128:(i+1)*128-1] then
    VRT[i*128:(i+1)*128-1] ← 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
  else
    VRT[i*128:(i+1)*128-1] ← 0x00000000000000000000000000000000
  end if
end for
if Rc then
  CR6 ← summary of results
end if

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.


Vector Compare Greater Than Signed Quadword

Summary: Compares two signed quadwords and sets the result based on whether the first is greater than the second.

For vcmpgtsq, the contents of VSR[VRA+32] (src1) are compared to the contents of VSR[VRB+32] (src2). If src1 > src2, VSR[VRT+32] is set to all 1s; otherwise, it is set to all 0s. If Rc=1, CR field 6 is updated.

if MSR.VEC=0 then
    Vector_Unavailable()
all_true ←1
all_false ←1
src1 ←EXTS(VSR[VRA+32])
src2 ←EXTS(VSR[VRB+32])
if src1 > src2 then do
    VSR[VRT+32] ← 0xFFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF
    all_false ←0
end else do
    VSR[VRT+32] ← 0x0000_0000_0000_0000_0000_0000_0000_0000
    all_true ←0
end
if Rc=1 then
    CR.field[6] ←all_true || 0b0 || all_false || 0b0


Summary: Compares the signed integer values in two vector registers and updates the condition register.

For vcmpsq, the signed integer value in VSR[VRA+32] is compared with the signed integer value in VSR[VRB+32]. The comparison flags are placed into CR field BF.

if MSR.VEC=0 then
    Vector_Unavailable()
src1 ←EXTS(VSR[VRA+32])
src2 ←EXTS(VSR[VRB+32])
lt_flag ←src1 < src2
gt_flag ←src1 > src2
eq_flag ←src1 = src2
CR.field[BF] ←lt_flag<<3 | gt_flag<<2 | eq_flag<<1

The vcmpsq instruction compares two signed quadword values from vector registers and sets the condition register (CR) field BF based on the comparison results. Ensure that the Vector Facility is enabled by checking and setting MSR.VEC before using this instruction. Be cautious of potential exceptions if the Vector Facility is not available.


Summary: Performs a logical equivalence operation on the contents of two vector registers and stores the result in another vector register.

The contents of VSR[VRA+32] are XORed with the contents of VSR[VRB+32] and the complemented result is placed into VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
else
    VSR[VRT+32] ← ¬(VSR[VRA+32] ≡ VSR[VRB+32])

The veqv instruction performs a logical equivalence operation between two vector registers, followed by a bitwise NOT on the result. This is useful for comparing vectors and determining where they differ. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised.


Vector Rotate Left Word then AND with Mask

Summary: Rotates each word element of the source vector left by a specified number of bits and then performs a bitwise AND operation with a mask.

For vrlwnm, each word element of VSR[VRA+32] is rotated left by the number of bits specified in the corresponding word element of VSR[VRB+32]. The result is then ANDed with a mask generated from bits 11:15 and 19:23 of the same source vector element. The final result is stored in VSR[VRT+32].

if MSR.VEC=0 then Vector_Unavailable()
do i = 0 to 3
    src1.word[0] ← VSR[VRA+32].word[i]
    src1.word[1] ← VSR[VRA+32].word[i]
    src2 ← VSR[VRB+32].word[i]
    b ← src2.bit[11:15]
    e ← src2.bit[19:23]
    n ← src2.bit[27:31]
    r ← src1.bit[n:n+31]
    m ← MASK(b, e)
    VSR[VRT+32].word[i] ← r & m

The vrlwnm instruction is useful for performing bitwise operations on vector elements. Ensure that the mask bits (11:15 and 19:23) are set correctly to achieve the desired AND operation. This instruction operates at the user privilege level and does not generate exceptions under normal conditions, but it requires the vector facility to be enabled in the MSR register.


Vector Rotate Left Quadword then AND with Mask VX-form

Summary: Rotates the contents of a vector register left by a specified number of bits and performs a bitwise AND operation with a mask derived from another vector register.

Rotates the quadword element in VRA left by a number of bits specified in VRB, then performs a bitwise AND with a mask derived from the lower bits of VRB to produce the result in VRT. No condition flags are affected.

shamt ← (VRB[120:127]) & 0x7F
mask_bits ← (VRB[120:127]) & 0x3F
rotated ← (VRA << shamt) | (VRA >> (128 - shamt))
mask ← Generate_Mask(mask_bits)
VRT ← rotated & mask

The vrlqnm instruction is used for vectorized operations involving rotation and masking of quadword data. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to 1, otherwise a Vector_Unavailable exception will be raised. The mask generation from bits 41:47 and 49:55 of VSR[VRB+32] should be carefully managed to achieve the desired bitwise AND operation result.


Vector Rotate Left Word then Mask Insert VX-form

Summary: Rotates the contents of each word element in a vector left by a specified number of bits and inserts the result into another vector under control of a mask.

Rotates each word element of VRA left by the number of bits specified in VRB, then inserts the rotated result into VRT under control of a mask generated from VRB. No condition flags are affected.

for i in 0 to 3 do
  shamt ← (VRB[i*32+27:i*32+31]) & 0x1F
  word ← (u32)VRA[i*32:(i*32+31)]
  rotated ← (word << shamt) | (word >> (32 - shamt))
  mask ← Generate_Mask_From_VRB(i)
  VRT[i*32:(i*32+31)] ← (VRT[i*32:(i*32+31)] & ~mask) | (rotated & mask)
end for

The vrlwmi instruction is useful for performing masked insertions after rotating word elements. Ensure that the mask bits (11:15 and 19:23) are set correctly to achieve the desired insertion pattern. This instruction operates on vector registers, so ensure that the Vector Facility is enabled in the Machine State Register (MSR).


Vector Rotate Left Doubleword then Mask Insert

Summary: Rotates the contents of a vector register left by a specified number of bits and inserts the result into another vector register under control of a mask.

Rotates each doubleword element of VRA left by the number of bits specified in VRB, then inserts the rotated result into VRT under control of a mask derived from corresponding bits in VRB. No condition flags are affected.

for i in 0 to 1 do
  shamt ← (VRB[i*64+58:i*64+63]) & 0x3F
  dword ← (u64)VRA[i*64:(i*64+63)]
  rotated ← (dword << shamt) | (dword >> (64 - shamt))
  mask ← Generate_Mask_From_VRB(i)
  VRT[i*64:(i*64+63)] ← (VRT[i*64:(i*64+63)] & ~mask) | (rotated & mask)
end for

The vrldmi instruction is used for rotating doubleword elements and performing masked insertions. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. Be cautious with the alignment of source and target vectors to avoid unexpected results. This operation requires supervisor privilege level.


Summary: Performs a multiply-add operation on vector elements.

For vmaddfp, the instruction multiplies each element of VSR[VRA+32] by the corresponding element of VSR[VRC+32], adds the result to the corresponding element of VSR[VRB+32], and stores the final result in VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ← VSR[VRA+32].word[i]
    src2 ← VSR[VRB+32].word[i]
    src3 ← VSR[VRC+32].word[i]
    result ← bfp32_MULTIPLY_ADD(src1,src3,src2)
    VSR[VRT+32].word[i] ← result
end

To use a multiply-add to perform an IEEE or Java compliant multiply, the addend must be -0.0.


Summary: Performs element-wise maximum of two vector registers and stores the result in a third vector register.

For vmaxfp, for each integer value i from 0 to 3, the single-precision floating-point values in word elements i of VSR[VRA+32] and VSR[VRB+32] are compared. The larger of the two values is placed into word element i of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ← VSR[VRA+32].word[i]
    src2 ← VSR[VRB+32].word[i]
    VSR[VRT+32].word[i] ← bfp32_MAXIMUM(src1,src2)
end

The vmaxfp instruction is used to perform element-wise maximum comparison of single-precision floating-point values in vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. This instruction operates on 4 elements per vector register and requires proper alignment of the input vectors for accurate results.


Vector Exponentiate Estimate Floating Point

Summary: Estimates the result of raising 2 to the power of each element in a vector.

For vexptefp, the single-precision floating-point estimate of 2 raised to the power of each element in VSR[VRB+32] is placed into corresponding elements in VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src ← VSR[VRB+32].word[i]
    VSR[VRT+32].word[i] ← bfp32_POWER2_ESTIMATE(src)
end

The result for various special cases of the source value is given below.

Value          Result
-Infinity         +0
-0           +1
+0           +1
+Infinity          +Infinity
NaN         QNaN


Vector Log Base 2 Estimate Floating-Point

Summary: Estimates the base 2 logarithm of single-precision floating-point elements in a vector register.

For vlogefp, the single-precision floating-point estimate of the base 2 logarithm of each element in VSR[VRB+32] is placed into the corresponding element in VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src ← VSR[VRB+32].word[i]
    VSR[VRT+32].word[i] ← bfp32_LOG_BASE2_ESTIMATE(src)
end

This instruction is used for estimating the base 2 logarithm of single-precision floating-point numbers in vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation processes four elements at a time, so ensure proper alignment and data handling to avoid unexpected results.


Vector Reciprocal Estimate Floating-Point VX-form

Summary: Estimates the reciprocal of single-precision floating-point elements in a vector.

For vrefp, the single-precision floating-point estimate of the reciprocal of each element in VSR[VRB+32] is placed into corresponding elements in VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src ← VSR[VRB+32].word[i]
    VSR[VRT+32].word[i] ← bfp32_RECIPROCAL_ESTIMATE(src)
end

The vrefp instruction estimates the reciprocal of each single-precision floating-point element in the source vector and stores it in the destination vector. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on vectors containing 32-bit floating-point numbers, and it does not raise exceptions for invalid operations like division by zero; instead, it returns a NaN or infinity as appropriate.


Summary: Performs a bit permute operation on doublewords of two vector registers and stores the result in another vector register.

Performs a bit permutation on doubleword elements of two vector registers. For each of the two doubleword elements in VRA, the bits are rearranged according to indices specified in the corresponding doubleword of VRB, with the result stored in VRT. No condition registers or status fields are affected.

for i in 0 to 1:
  for j in 0 to 63:
    bit_index ← VRB[i].doubleword[j][0:5]
    VRT[i].doubleword[j] ← VRA[i].doubleword[bit_index]

The vbpermd instruction is used to perform bit-level permutation on doublewords of two source vectors. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. Each byte in VRB acts as an index to select bits from VRA; if the index exceeds 63, the corresponding bit in the result is set to zero. This operation is useful for tasks requiring precise control over bit manipulation within vector registers.


Summary: Performs a bit permutation on two vector registers and stores the result in another vector register.

Performs a bit permutation on the 128-bit quadword formed by concatenating two vector registers. The bits of the concatenated source are rearranged according to indices in VRB, with the 64-bit result placed in the left doubleword of VRT and the right doubleword cleared. No condition registers or status fields are affected.

source ← VRA || VRB
result ← 0
for i in 0 to 63:
  bit_index ← VRB.doubleword[i][0:6]
  result[i] ← source[bit_index]
VRT[0].doubleword ← result
VRT[1].doubleword ← 0

The fact that the permuted bit is 0 if the corresponding index value exceeds 127 permits the permuted bits to be selected from a 256-bit quantity, using a single index register.


Summary: Moves a byte mask from a GPR to a VSR.

The contents of bits 48:63 of GPR[RB] are used to create a field mask in VSR[VRT+32]. Each bit in the GPR determines whether the corresponding byte in the VSR is set to all 0s or all 1s.

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 15
    if GPR[RB].bit[48+i]=0 then
        VSR[VRT+32].byte[i] ←0x00
    else
        VSR[VRT+32].byte[i] ←0xFF
end

This instruction is used to set each byte in a vector register to either all zeros or all ones based on the bits in a general-purpose register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The instruction processes 16 bytes, so ensure that the GPR contains valid bit values for positions 48 to 63.


Summary: Moves a word mask from a general-purpose register to a vector scalar register.

The contents of bits 60-63 of GPR[RB] are used to set the corresponding word elements in VSR[VRT+32] to either all 0s or all 1s based on the bit value.

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    if GPR[RB].bit[60+i]=0 then
        VSR[VRT+32].word[i] ←0x0000_0000
    else
        VSR[VRT+32].word[i] ←0xFFFF_FFFF
end

This instruction is used to set each word in a vector register to either all zeros or all ones based on the corresponding bits in a general-purpose register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The instruction operates on 32-bit words and requires the source general-purpose register to be properly aligned for bit manipulation.


Summary: Moves a quadword mask from a general-purpose register to a vector scalar register.

The contents of GPR[RB] are used to determine the mask for VSR[VRT+32]. If bit 63 of GPR[RB] is 0, VSR[VRT+32] is set to all zeros. If bit 63 is 1, VSR[VRT+32] is set to all ones.

if MSR.VEC=0 then
    Vector_Unavailable()
else if GPR[RB].bit[63]=0 then
    VSR[VRT+32] ← 0x0000_0000_0000_0000_0000_0000_0000_0000
else
    VSR[VRT+32] ← 0xFFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF
end

This instruction sets the mask for a vector register based on the most significant bit of a general-purpose register. Ensure that the Vector Facility is enabled in the Machine State Register (MSR) before using this instruction; otherwise, it will raise an exception. The instruction does not require any specific alignment or ordering of operations.


Summary: Counts the number of true (or false) mask bits in a VSR and places the count in the leftmost byte of a GPR.

Counts the number of byte elements in VRB that have bit 0 set to the value specified by MP (0 or 1), and places the count in the leftmost byte of the target GPR RT. This instruction is part of the VMX category and does not affect condition registers or status fields.

count ← 0
for i in 0 to 15:
  if (VRB.byte[i][0] == MP) then
    count ← count + 1
RT[56:63] ← count
RT[0:55] ← 0

This instruction is useful for counting the number of bytes in a vector register where the least significant bit matches a specified mask value (MP). Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the Machine State Register (MSR) before using this instruction. The result is left-shifted 56 bits, so only the lower byte of GPR[RT] contains the count. This instruction operates at the problem state privilege level.


Summary: Counts the number of word elements in a vector register that have bit 0 set to a specified value.

Counts the number of word elements in VRB that have bit 0 set to the value specified by MP (0 or 1), and places the count in the leftmost byte of the target GPR RT. This instruction is part of the VMX category and does not affect condition registers or status fields.

count ← 0
for i in 0 to 3:
  if (VRB.word[i][0] == MP) then
    count ← count + 1
RT[56:63] ← count
RT[0:55] ← 0

The vcntmbw instruction is useful for counting the number of word elements in a vector register that have their least significant bit set to a specified value. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The result is stored in the upper bits of the target GPR, so be cautious when interpreting the output.


Vector String Isolate Halfword Right-justified

Summary: Isolates the rightmost non-zero halfword in a vector string.

From right to left, the contents of each halfword element of VSR[VRB+32] are placed into the corresponding halfword element in VSR[VRT+32]. If a halfword element in VSR[VRB+32] is found to contain 0, the corresponding halfword element and all halfword elements to the left of that halfword element in VSR[VRT+32] are set to 0.

if MSR.VEC=0 then
    Vector_Unavailable()
null_found ← 0
while (!null_found) do i = 0 to 7
    null_found ← (VSR[VRB+32].hword[7-i] = 0)
    VSR[VRT+32].hword[7-i] ← VSR[VRB+32].hword[7-i]
end
do j = i to 7
    VSR[VRT+32].hword[7-j] ← 0
end
if Rc=1 then
    CR.field[6] ← 0b00 || null_found || 0b0

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.


Summary: Adds two packed decimal integers and updates the condition register.

The bcdadd. instruction adds two binary coded decimal numbers stored in vector registers VRA and VRB, and stores the result in vector register VRT. The PS field specifies whether to set the sign code to 0b1100 or 0b1111 if the unbounded result is zero.

RA

Source General Purpose Register containing the first packed decimal integer

RB

Source General Purpose Register containing the second packed decimal integer

if MSR.VEC=0 then
    Vector_Unavailable()
VRT[32] ← bcd_ADD(VRA[32], VRB[32], PS)
CR.bit[56] ← inv_flag ? 0b0 : lt_flag
CR.bit[57] ← inv_flag ? 0b0 : gt_flag
CR.bit[58] ← inv_flag ? 0b0 : eq_flag
CR.bit[59] ← ox_flag | inv_flag

When bit 3 of CR field 6 is set to 1 by bcdadd. or bcdsub., either an overflow occurred or one or both operands are not valid encodings of decimal values.


Summary: Multiplies the contents of a vector register by 10 and places the result in another vector register.

The rightmost 128 bits of the product of src multiplied by the value 10 are placed into VSR[VRT+32]. Let src be the unsigned integer value in VSR[VRA+32].

if MSR.VEC=0 then
    Vector_Unavailable()
src ←EXTZ(VSR[VRA+32])
prod ←(src << 3) + (src << 1)
VSR[VRT+32] ←CHOP128(prod)

This instruction multiplies the upper 64 bits of a vector register by 10 and stores the result in another vector register. Ensure that the Vector Facility is enabled (MSR.VEC=1); otherwise, a Vector_Unavailable exception will be raised. The operation involves shifting and adding to achieve multiplication by 10, so be cautious with overflow if the input value is close to the maximum unsigned 64-bit integer.


Vector Multiply-by-10 Extended Unsigned Quadword

Summary: Multiplies the contents of two vector registers by 10 and extends the result.

The instruction multiplies the unsigned integer value in VSR[VRA+32] by 10, adds the unsigned packed decimal value from bits 124:127 of VSR[VRB+32], and places the rightmost 128 bits of the result into VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
src ← EXTZ(VSR[VRA+32])
cin ← EXTZ(VSR[VRB+32].bit[124:127])
prod ← (src << 3) + (src << 1) + cin
VSR[VRT+32] ← CHOP128(prod)

This instruction is used for multiplying an unsigned integer by 10 and adding a packed decimal value. Ensure that the Vector Facility is enabled in the MSR register to avoid exceptions. The operation requires proper alignment of input values, specifically focusing on bits 124:127 of the second source vector. Be cautious with overflow conditions as the result is truncated to 128 bits.


Summary: Copies the sign of a decimal value from one register to another while preserving the magnitude.

The bcdcpsgn. instruction copies the sign of the decimal value in VSR[VRB+32] to the decimal value in VSR[VRA+32], placing the result into VSR[VRT+32]. If either input is an invalid encoding, the result is undefined.

if MSR.VEC=0 then
    Vector_Unavailable()
inv_flag ←(VSR[VRA+32].nibble[31] < 0xA) |
            (VSR[VRB+32].nibble[31] < 0xA)
do i = 0 to 30
    inv_flag ←inv_flag |
                (VSR[VRA+32].nibble[i] > 0x9) |
                (VSR[VRB+32].nibble[i] > 0x9)
end
src_sign ←(VSR[VRB+32].nibble[31] = 0xB) |
            (VSR[VRB+32].nibble[31] = 0xD)
eq_flag  ←(VSR[VRA+32].nibble[0:30] = 0)
lt_flag  ←(eq_flag=0) & (src_sign=1)
gt_flag  ←(eq_flag=0) & (src_sign=0)
result.nibble[0:30] ←VSR[VRA+32].nibble[0:30]
result.nibble[31]   ←VSR[VRB+32].nibble[31]
VSR[VRT+32] ←inv_flag ? undefined : result
CR.bit[56]  ←inv_flag ? 0b0 : lt_flag
CR.bit[57]  ←inv_flag ? 0b0 : gt_flag
CR.bit[58]  ←inv_flag ? 0b0 : eq_flag
CR.bit[59]  ←inv_flag

The bcdcpsgn. instruction is used to copy the sign of a decimal value from one vector register to another, while preserving the magnitude. Ensure that both input vectors are valid decimal encodings; otherwise, the result is undefined. This instruction operates at the user privilege level and does not raise exceptions for invalid inputs, instead setting CR6 bits accordingly.


Summary: Sets the sign of a packed decimal value in a vector register based on the specified conditions.

The bcdsetsgn. instruction sets the sign of a packed decimal value in VSR[VRT+32] based on the contents of VSR[VRB+32] and the PS flag.

if MSR.VEC=0 then
    Vector_Unavailable()

inv_flag ←(VSR[VRB+32].nibble[31] < 0xA)
do i = 0 to 30
    inv_flag ←inv_flag |
               (VSR[VRB+32].nibble[i] > 0x9)
end

src_sign ←(VSR[VRB+32].nibble[31] = 0xB) |
           (VSR[VRB+32].nibble[31] = 0xD)

eq_flag  ←(VSR[VRB+32].nibble[0:30] = 0)
lt_flag  ←(eq_flag=0) & (src_sign=1)
gt_flag  ←(eq_flag=0) & (src_sign=0)

result.nibble[0:30] ←VSR[VRB+32].nibble[0:30]
result.nibble[31] ←
   (src_sign=0) ? ((PS=0) ? 0xC:0xF) : 0xD

VSR[VRT+32] ←inv_flag ? undefined : result

CR.bit[56]  ←inv_flag ? 0b0 : lt_flag
CR.bit[57]  ←inv_flag ? 0b0 : gt_flag
CR.bit[58]  ←inv_flag ? 0b0 : eq_flag
CR.bit[59]  ←inv_flag

The bcdsetsgn. instruction is used to set the sign of a packed decimal value in VSR[VRT+32] based on the contents of VSR[VRB+32]. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. The instruction checks for invalid characters in the input and sets the sign accordingly, updating condition register bits CR[56-59] to reflect the result's status.


Summary: Shifts a signed packed decimal value by a specified number of digits and rounds the result.

The bcds. instruction shifts a signed packed decimal value in VSR[VRB+32] by a number of digits specified in byte element 7 of VSR[VRA+32]. The result is placed into VSR[VRT+32].

VRA

Source Vector Register containing the shift count

VRB

Source Vector Register containing the packed decimal value to be shifted

if MSR.VEC=0 then Vector_Unavailable()
n ← EXTS(VSR[VRA+32].byte[7])
inv_flag ← (VSR[VRB+32].nibble[31] < 0xA)
do i = 0 to 30
    inv_flag ← inv_flag | (VSR[VRB+32].nibble[i] > 0x9)
end
src_sign ← (VSR[VRB+32].nibble[31] = 0xB) | (VSR[VRB+32].nibble[31] = 0xD)
eq_flag ← (VSR[VRB+32].nibble[0:30] = 0)
lt_flag ← (eq_flag=0) & (src_sign=1)
gt_flag ← (eq_flag=0) & (src_sign=0)
if n > 0 then do     // shift left
    shcnt ← (n<32) ? n : 31
    src.nibble[0:30] ← VSR[VRB+32].nibble[0:30]
    src.nibble[31:61] ← 0
    ox_flag ← (shcnt > 0) & (src.nibble[0:shcnt-1] != 0)
end else do              // shift right
    shcnt ← ((¬n+1)<32) ? (¬n+1) : 31
    src.nibble[0:30] ← 0
    src.nibble[31:61] ← VSR[VRB+32].nibble[0:30]
    result.nibble[0:30] ← src.nibble[31-shcnt:61-shcnt]
    ox_flag ← 0b0
end
result.nibble[31] ← (src_sign=0) ? ((PS=0) ? 0xC : 0xF) : 0xD
VSR[VRT+32] ← inv_flag ? undefined : result
CR.bit[56] ← inv_flag ? 0b0 : lt_flag
CR.bit[57] ← inv_flag ? 0b0 : gt_flag
CR.bit[58] ← inv_flag ? 0b0 : eq_flag
CR.bit[59] ← inv_flag | ox_flag

The bcds. instruction is used for shifting signed packed decimal values in vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will occur. The shift amount is determined by byte element 7 of the source register, and the result is stored in the target register. Be cautious with negative shifts as they are treated as right shifts. The instruction updates condition registers for comparison purposes.


Summary: Performs an unsigned shift on packed decimal values in vector registers.

The bcdus. instruction shifts the contents of VSR[VRB+32] by a number of digits specified by the signed integer value in byte element 7 of VSR[VRA+32]. The result is placed into VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()

inv_flag ←0
do i = 0 to 31
    inv_flag ←inv_flag | (VSR[VRB+32].nibble[i] > 0x9)
end
eq_flag  ←(VSR[VRB+32].nibble[0:31] = 0)
gt_flag  ←(eq_flag=0)

if n > 0 then do     // shift left
    shcnt ←(n<33) ? n : 32
    src.nibble[0:31] ←VSR[VRB+32]
    src.nibble[32:63] ←0
    ox_flag ←(shcnt > 0) & (src.nibble[0:shcnt-1] != 0)
end else do              // shift right
    shcnt ←((¬n+1)<33) ? (¬n+1) : 32
    src.nibble[0:31] ←0
    src.nibble[32:63] ←VSR[VRB+32]
    result ←src.nibble[32-shcnt:63-shcnt]
    ox_flag ←0
end

VSR[VRT+32] ←inv_flag ? undefined : result

CR.bit[56] ←0b0
CR.bit[57] ←inv_flag ? 0b0 : gt_flag
CR.bit[58] ←inv_flag ? 0b0 : eq_flag
CR.bit[59] ←inv_flag | ox_flag

The bcdus. instruction is used for shifting Binary Coded Decimal (BCD) values within vector registers. Ensure that the shift count in byte element 7 of VSR[VRA+32] is valid; otherwise, the result is undefined. This instruction operates at the user privilege level and may raise an exception if vector processing is unavailable. Be cautious with alignment as it affects the interpretation of BCD digits.


Summary: Shifts a binary coded decimal value by a specified number of digits and rounds the result.

The bcdsr. instruction shifts a signed packed decimal value in VSR[VRB+32] by a number of digits specified by the signed integer value in byte element 7 of VSR[VRA+32]. The result is rounded and placed into VSR[VRT+32].

Source Vector Register containing the packed decimal value to be shifted and rounded

if MSR.VEC=0 then
    Vector_Unavailable()
inv_flag ←(VSR[VRB+32].nibble[31] < 0xA)
do i = 0 to 30
    inv_flag ←inv_flag | (VSR[VRB+32].nibble[i] > 0x9)
end
src_sign ←(VSR[VRB+32].nibble[31] = 0xB) | (VSR[VRB+32].nibble[31] = 0xD)
eq_flag  ←(VSR[VRB+32].nibble[0:30] = 0)
gt_flag  ←(eq_flag=0) & (src_sign=0)
lt_flag  ←(eq_flag=0) & (src_sign=1)
n ←EXTS(VSR[VRA+32].byte[7])
if n > 0 then do     // shift left
    shcnt ←Clamp(n, 0, 31)
    src.nibble[0:30] ←VSR[VRB+32].nibble[0:30]
    src.nibble[31:61] ←0
    result.nibble[0:30] ←src.nibble[shcnt:shcnt+30]
    ox_flag ←(shcnt > 0) & (src.nibble[0:shcnt-1] != 0)
    g_flag ←0
end else do              // shift right
    shcnt ←Clamp(¬n + 1, 0, 31)
    src.nibble[31:61] ←VSR[VRB+32].nibble[0:30]
    ox_flag ←0
g_flag  ←(shcnt > 0) & (EXTZ(src.nibble[62-shcnt]) >= 5)
end
result.nibble[31] ← (src_sign=0) ? ((PS=0) ? 0xC : 0xF) : 0xD
result ←(g_flag=0) ? result : bcd_INCREMENT(result)
VSR[VRT+32] ←inv_flag ? undefined : result
CR.bit[56] ←inv_flag ? 0b0 : lt_flag
CR.bit[57] ←inv_flag ? 0b0 : gt_flag
CR.bit[58] ←inv_flag ? 0b0 : eq_flag
CR.bit[59] ←inv_flag | ox_flag

The bcdsr. instruction is used for shifting and rounding packed decimal values in vector registers. Ensure the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will occur. The instruction handles both left and right shifts based on the sign of the shift count in byte element 7 of the source register. Be cautious with invalid input detection, as any nibble outside the range 0x0 to 0x9 or special nibbles (0xB, 0xD) will set the CR6[3] bit and result in undefined output.


Summary: Truncates a decimal value to a specified length and updates the condition register.

The bcdtrunc. instruction truncates a packed decimal value in VSR[VRB+32] to a specified length and stores the result in VSR[VRT+32]. The length is determined by bits 48:63 of VSR[VRA+32].

VRA

Source Vector Register containing the length

VRB

Source Vector Register containing the packed decimal value

if MSR.VEC=0 then
    Vector_Unavailable()
inv_flag ←(VSR[VRB+32].nibble[31] < 0xA)
do i = 0 to 30
    inv_flag ←inv_flag |
                (VSR[VRB+32].nibble[i] > 0x9)
end
length  ←VSR[VRA+32].bit[48:63]
ox_flag ←0
src_sign ←(VSR[VRB+32].nibble[31] = 0xB) |
            (VSR[VRB+32].nibble[31] = 0xD)
eq_flag  ←(VSR[VRB+32].nibble[0:30] = 0)
lt_flag ←  src_sign & ¬eq_flag
gt_flag  ←¬src_sign & ¬eq_flag
if length < 31 then do
do i = 0 to 30-length
    if VSR[VRB+32].nibble[i]!=0b0000 then
       ox_flag ←1
    result.nibble[i] ←0b0000
end
if length > 0 then do
do i = 31-length to 30
    result.nibble[i] ←VSR[VRB+32].nibble[i]
end
end
else
    result.nibble[0:30] ←VSR[VRB+32].nibble[0:30]
result.nibble[31] ←
    (src_sign=0) ? ((PS=0) ? 0xC : 0xF) : 0xD
VSR[VRT+32] ←inv_flag ? undefined : result
CR.bit[56] ←inv_flag ? 0b0 : lt_flag
CR.bit[57] ←inv_flag ? 0b0 : gt_flag
CR.bit[58] ←inv_flag ? 0b0 : eq_flag
CR.bit[59] ←inv_flag | ox_flag

The bcdtrunc. instruction is used to truncate a packed decimal value in VSR[VRB+32] to a specified length, determined by bits 48:63 of VSR[VRA+32]. Ensure that the vector facility (MSR.VEC) is enabled before using this instruction. The instruction checks for invalid nibbles and sets flags accordingly. Be cautious with alignment and ensure proper handling of special cases like overflow and sign preservation.


Summary: Truncates the unsigned decimal value in VRB to a specified length and places it into VRT.

The instruction truncates the unsigned decimal value in VSR[VRB+32] to the length specified by the integer value in bits 48:63 of VSR[VRA+32]. The result is placed into VSR[VRT+32].

Source Vector Register containing the unsigned decimal value

if MSR.VEC=0 then
    Vector_Unavailable()
inv_flag ←0
do i = 0 to 31
    inv_flag ←inv_flag |
                (VSR[VRB+32].nibble[i] > 0x9)
end
length ←VSR[VRA+32].bit[48:63]
ox_flag ←0
eq_flag  ←(VSR[VRB+32].nibble[0:31] = 0)
gt_flag  ←(VSR[VRB+32].nibble[0:31] != 0)
if length < 32 then do
    do i = 0 to 31-length
        ox_flag ←1
        result.nibble[i] ←0b0000
    end
    if length > 0 then do
        do i = 32-length to 31
            result.nibble[i] ←VSR[VRB+32].nibble[i]
        end
    end
end
else result ←VSR[VRB+32]
VSR[VRT+32] ←inv_flag ? undefined : result
CR.bit[56] ←0b0
CR.bit[57] ←inv_flag ? 0b0 : gt_flag
CR.bit[58] ←inv_flag ? 0b0 : eq_flag
CR.bit[59] ←inv_flag | ox_flag

The bcdutrunc. instruction is used to truncate an unsigned decimal value stored in a vector register. Ensure that the length specified in VSR[VRA+32] does not exceed 32 nibbles, as truncating beyond this will result in undefined behavior. The instruction sets various condition register bits (CR6) based on the operation's outcome, such as overflow and equality flags. Be cautious of invalid nibble values greater than 0x9, which can lead to incorrect results.


Move To Vector Status and Control Register

Summary: Moves the contents of a vector register word into the VSCR.

The contents of word element 3 of VSR[VRB+32] are placed into the VSCR.

if MSR.VEC=0 then
    Vector_Unavailable()
VSCR ← VSR[VRB+32].word[3]

The mtvscr instruction is used to transfer a value from a vector register to the VSCR. Ensure that the Vector Facility (MSR.VEC) is enabled before executing this instruction; otherwise, a Vector_Unavailable exception will be raised. This instruction requires proper alignment of the source vector register and operates at user privilege level.


Summary: Accesses a floating-point operand in single-precision format from storage, converts it to double-precision format, and loads it into a VSR.

When Big-Endian byte ordering is employed, the contents of the word in storage at address EA are placed into load_data in such an order that; the contents of the byte in storage at address EA are placed into byte 0 of load_data, the contents of the byte in storage at address EA+1 are placed into byte 1 of load_data, the contents of the byte in storage at address EA+2 are placed into byte 2 of load_data, and the contents of the byte in storage at address EA+3 are placed into byte 3 of load_data. When Little-Endian byte ordering is employed, the contents of the word in storage at address EA are placed into load_data in such an order that; the contents of the byte in storage at address EA are placed into byte 3 of load_data, the contents of the byte in storage at address EA+1 are placed into byte 2 of load_data, the contents of the byte in storage at address EA+2 are placed into byte 1 of load_data, and the contents of the byte in storage at address EA+3 are placed into byte 0 of load_data. The contents of doubleword element 1 of VSR[VRT+32] are set to 0.

if MSR.VEC=0 then Vector_Unavailable()
EA ← (RA|0) + EXTS64(DS||0b00)
load_data ← MEM(EA,4)
result ← bfp_CONVERT_FROM_BFP32(MEM(EA,4))
VSR[VRT+32].dword[0] ← bfp64_CONVERT_FROM_BFP(result)
VSR[VRT+32].dword[1] ← 0x0000_0000_0000_0000

The lxssp instruction loads a single-precision floating-point value from memory into the VSX register, ensuring proper byte ordering based on the system's endianness. It is commonly used for loading scalar floating-point data into VSX registers for further processing. Ensure that the address (EA) is properly aligned to avoid potential performance penalties or exceptions. This instruction operates at user privilege level and will raise a Vector_Unavailable exception if the VEC bit in the MSR register is not set.


Round to Floating-Point Integer (Double-Precision)

Summary: Rounds a double-precision floating-point value to an integer using the specified rounding mode.

The result is placed into doubleword element 0 of VSR[XT] in double-precision format. The contents of doubleword element 1 of VSR[XT] are set to 0.

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src ← bfp_CONVERT_FROM_BFP64(VSR[VRB+32].dword[0])
rnd ← bfp_ROUND_TO_INTEGER(0b100, src)
result ← bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
vex_flag ← FPSCR.VE & vxsnan_flag
if vex_flag=0 then do
    VSR[32×TX+T].dword[0] ← result
    VSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000
    FPSCR.FPRF ← fprf_CLASS_BFP64(result)
end
FPSCR.FR ← 0b0
FPSCR.FI ← 0b0

This instruction can be used to operate on a single-precision source operand. Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.


VSX Scalar Convert with round to zero Double-Precision to Signed Word

Summary: Converts a double-precision floating-point number to a signed word, rounding towards zero.

This instruction converts the double-precision floating-point number in VSR[XB] to a signed word and places it into word elements 0 and 1 of VSR[XT]. If the operand is positive or +Infinity, 0x7FFF_FFFF is placed. If negative, -Infinity, or NaN, 0x8000_0000 is placed.

if (VSR[XB][0] is positive or +Infinity) then
    VSR[XT][0:31] <- 0x7FFF_FFFF
else if (VSR[XB][0] is negative, -Infinity, or NaN) then
    VSR[XT][0:31] <- 0x8000_0000
VSR[XT][32:63] <- 0

This instruction is useful for converting double-precision floating-point numbers to a signed word format, with specific handling for edge cases like infinity and NaN. Ensure that the input register contains valid double-precision values to avoid unexpected results. The instruction operates at user privilege level and does not generate exceptions under normal conditions.


VSX Scalar Convert with round Signed Doubleword to Double-Precision format

Summary: Converts a signed doubleword integer from VSX register XB to a double-precision floating-point number in VSX register XT, rounding according to the FPSCR.RN setting.

The instruction converts the signed integer value in doubleword element 0 of VSR[XB] to an unbounded-precision floating-point value and rounds it to double-precision format using the rounding mode specified by RN. The result is placed into doubleword element 0 of VSR[XT], with doubleword element 1 set to zero.

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src ← bfp_CONVERT_FROM_SI64(VSR[32×BX+B].dword[0])
rnd ← bfp_ROUND_TO_BFP64(0b0, FPSCR.RN, v)
result ← bfp64_CONVERT_FROM_BFP(rnd)
if xx_flag=1 then SetFX(FPSCR.XX)
VSR[32×TX+T].dword[0] ← result
VSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000
FPSCR.FPRF ← fprf_CLASS_BFP64(result)
FPSCR.FR ← inc_flag
FPSCR.FI ← xx_flag

Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.


Summary: Loads a doubleword from memory into a VSX scalar register.

When Big-Endian byte ordering is employed, the contents of the doubleword in storage at address EA are placed into load_data in such an order that; the contents of the byte in storage at address EA are placed into byte 0 of load_data, and so forth until the contents of the byte in storage at address EA+7 are placed into byte 7 of load_data. When Little-Endian byte ordering is employed, let load_data be the contents of the doubleword in storage at address EA such that; the contents of the byte in storage at address EA are placed into byte 7 of load_data, and so forth until the contents of the byte in storage at address EA+7 are placed into byte 0 of load_data.

The lxsd instruction loads a doubleword from memory into the VSX register, handling both Big-Endian and Little-Endian byte orderings. Ensure that the address is properly aligned to avoid potential performance penalties or exceptions. This instruction operates at user privilege level.


Loads a doubleword from memory at the address computed as (RA) + (RB) and places it into the specified VSX scalar register XT. The upper 64 bits of the VSX register remain unchanged. This is a VSX instruction and does not affect condition registers or status fields.

RA

Source General Purpose Register (Base Address)

ea ← (RA) + (RB)
XT.doubleword[1] ← [ea]

The lxsdx instruction is commonly used to load a doubleword from memory into a VSX scalar register. Ensure that the VSX facility is enabled by checking and setting the appropriate bit in the MSR register. Be cautious of alignment requirements; while the instruction can handle unaligned accesses, performance may be improved with aligned data. This instruction operates at user privilege level but will raise an exception if the VSX facility is not available.


Load VSX Scalar as Integer Byte & Zero Indexed X-form

Summary: Loads a byte from memory and places it into the specified VSX register, zeroing the upper half.

Loads a signed byte from memory at address (RA) + (RB), converts it to a 64-bit integer, and places the result into the right element of VSX register XT. The left element of XT is cleared. This is a VSX instruction and does not affect condition registers or status fields.

ea ← (RA) + (RB)
byte_value ← [ea] (sign-extended to 64 bits)
XT.doubleword[1] ← byte_value
XT.doubleword[0] ← 0

The lxsibzx instruction is commonly used to load an unsigned byte from memory into a VSX register, with the upper 64 bits set to zero. Ensure that the effective address (EA) is properly aligned and within bounds to avoid exceptions. This instruction requires VSX or Vector facility enabled in the MSR register, depending on the transactional execution context.


Load VSX Scalar Single-Precision Indexed X-form

Summary: Loads a single-precision floating-point value from memory and converts it to double-precision format in a VSX register.

Loads a single-precision floating-point value from memory at address (RA) + (RB), converts it to double-precision format, and places the result into the right doubleword of VSX register XT. The left doubleword is cleared. This is a VSX instruction and does not affect condition registers or status fields.

ea ← (RA) + (RB)
sp_value ← [ea] (single-precision)
dp_value ← convert_sp_to_dp(sp_value)
XT.doubleword[1] ← dp_value
XT.doubleword[0] ← 0

The lxsspx instruction is used to load a single-precision floating-point value from memory into a VSX register, converting it to double-precision format. Ensure that the VSX facility is enabled by checking and setting the MSR.VSX bit. The instruction requires 4-byte alignment for the source data in memory to avoid potential exceptions. This instruction operates at user privilege level.


Summary: Stores the contents of doubleword element 0 of VSR[XS] to memory.

The instruction stores the contents of doubleword element 0 of VSR[XS] to memory at the effective address (EA) calculated from RA and DS.

if MSR.VEC=0 then Vector_Unavailable()
EA ← (RA|0) + EXTS64(DS||0b00)
MEM(EA,8) ← VSR[VRS+32].dword[0]

The stxsd instruction stores the first doubleword of a VSX register to memory. Ensure that the Vector Facility is enabled by checking and setting MSR.VEC if necessary. The EA must be 8-byte aligned for optimal performance, though unaligned accesses are supported with potential performance penalties.


Store VSX Scalar Doubleword Indexed X-form

Summary: Stores a doubleword from a VSX scalar register to memory.

The instruction stores the contents of the specified doubleword element of a VSX scalar register into memory at an address calculated from two general-purpose registers.

if MSR.VSX=0 then
    VSX_Unavailable()
EA ←((RA=0) ? 0 : GPR[RA]) + GPR[RB]
MEM(EA,8)    ←VSR[XS].dword[0]

The stxsdx instruction stores a doubleword from a VSX scalar register into memory. Ensure the VSX facility is enabled by checking and setting the MSR.VSX bit. The effective address (EA) is calculated by adding the contents of two general-purpose registers, RA and RB. This instruction requires 8-byte alignment for the memory address to avoid exceptions.