Summary: Tests for category (NaN, Inf, Denormal) for floats.

Tests each single-precision float in the source operand against a class mask (imm8) and sets the corresponding bit in the destination opmask register. The mask specifies FP classes: positive/negative zero, denormal, normal, infinity, and quiet/signaling NaN. The operation is merged or zeroed based on the opmask k2; no arithmetic flags are affected.

for i in 0 to 15:
  if k2[i] == 1 or k2_merge_mode == 0:
    class_bits ← classify_fp32(src[i])
    k1[i] ← (imm8 & (1 << class_bits)) != 0
  else:
    k1[i] ← 0


Summary: Tests for category (NaN, Inf, Denormal) for doubles.

512-bit ZMM AVX-512 register or Memory operand

Tests each double-precision float in the source operand against a class mask (imm8) and sets the corresponding bit in the destination opmask register. The mask specifies FP classes: positive/negative zero, denormal, normal, infinity, and quiet/signaling NaN. The operation is merged or zeroed based on the opmask k2; no arithmetic flags are affected.

for i in 0 to 7:
  if k2[i] == 1 or k2_merge_mode == 0:
    class_bits ← classify_fp64(src[i])
    k1[i] ← (imm8 & (1 << class_bits)) != 0
  else:
    k1[i] ← 0


Range Restriction Calculation Packed Single

Summary: Calculates range (min/max/abs) of float values.

VRANGEPS zmm1 {k1}, zmm2, zmm3/m512, imm8

Computes range restrictions on packed single-precision floats by selecting minimum, maximum, or absolute value operations controlled by an immediate operand. The result is the restricted range of two input operands after applying the imm8-controlled transformation. Results are merged or zeroed to the destination based on the opmask k1; no arithmetic flags are set.

for i in 0 to 15:
  if k1[i] == 1 or k1_merge_mode == 0:
    val1 ← src1.f32[i]
    val2 ← src2.f32[i]
    transformed ← apply_range_transform(val1, val2, imm8[2:0])
    dest.f32[i] ← transformed
  else:
    dest.f32[i] ← 0


Perform Reduction Transformation Packed Single

Summary: Performs reduction on floats (e.g. range reduction for trig).

Performs reduction transformations (e.g., range reduction for trigonometric functions) on packed single-precision floats. The imm8 operand selects the reduction mode and rounding behavior. The transformed values are written to the destination with masking controlled by opmask k1; no arithmetic flags are affected.

for i in 0 to 15:
  if k1[i] == 1 or k1_merge_mode == 0:
    result ← apply_reduction(src.f32[i], imm8[2:0])
    dest.f32[i] ← result_with_rounding(result, imm8[7:4])
  else:
    dest.f32[i] ← 0


Summary: Fixes special cases (NaN, Inf) using a table (Float32).

VFIXUPIMMPS zmm1 {k1}, zmm2, zmm3/m512, imm8

Fixes special floating-point cases (NaN, infinity, denormal) in packed single-precision data using a lookup table indexed by the immediate operand. The first source operand provides the primary value, the second provides a backup value for special cases, and the imm8 configures the fixup behavior. Results are masked by k1; no arithmetic flags are affected.

for i in 0 to 15:
  if k1[i] == 1 or k1_merge_mode == 0:
    primary ← src1.f32[i]
    backup ← src2.f32[i]
    fixup_class ← classify_special_fp32(primary)
    if is_special(fixup_class):
      dest.f32[i] ← lookup_fixup_table(backup, fixup_class, imm8)
    else:
      dest.f32[i] ← primary
  else:
    dest.f32[i] ← 0


Compute Approximate Reciprocal Square Root (14-bit)

Summary: Approximate 1/sqrt(x) with 2^-14 error.

Computes approximate reciprocal square root (1/√x) with 2^-14 relative error for packed single-precision floats. This fast approximation is suitable for iterative refinement or low-precision applications. Results are merged or zeroed to the destination based on opmask k1; no arithmetic flags are affected.

for i in 0 to 15:
  if k1[i] == 1 or k1_merge_mode == 0:
    dest.f32[i] ← approx_rsqrt14(src.f32[i])
  else:
    dest.f32[i] ← 0


Summary: Approximate 1/x with 2^-14 error.

Computes a 14-bit reciprocal approximation (1/x) for each single-precision float in the source operand, writing results to the destination with a maximum relative error of 2^-14. The instruction operates on 512-bit vectors (16 × 32-bit floats) in AVX-512, supports writemask control via k1, and sets no CPU flags. Denormalized inputs produce denormalized outputs; NaN, zero, and infinity operands behave according to IEEE 754 semantics.

for i = 0 to 15:
  if k1[i] or no mask:
    zmm1[32*i+31:32*i] ← approximate_reciprocal_14bit(zmm2/m512[32*i+31:32*i])
  else if zeroing:
    zmm1[32*i+31:32*i] ← 0


Summary: Clears the User Interrupt Flag (UIF).

Clears the User Interrupt Flag (UIF) in the UINTR register, preventing delivery of user-level interrupts to the current process. This is a privileged-equivalent instruction that requires the UINTR CPU feature and operates only in user mode; it has no effect on standard CPU flags or other processor state. Execution in a context where UINTR is unavailable causes a #UD exception.


Summary: Sets the User Interrupt Flag (UIF).

Sets the User Interrupt Flag (UIF) in the UINTR register, enabling delivery of user-level interrupts to the current process. This is a privileged-equivalent instruction that requires the UINTR CPU feature and operates only in user mode; it modifies no standard CPU flags. Execution in a context where UINTR is unavailable causes a #UD exception.


Summary: Sets CF if UIF is 1, ZF if User Interrupt Pending.

Tests the User Interrupt Flag (UIF) and User Interrupt Pending (UIP) status, setting CF if UIF is 1 and ZF if a user interrupt is pending. This instruction requires the UINTR CPU feature and operates only in user mode; it does not modify other flags. Execution without UINTR support causes a #UD exception.

CF ← UINTR.UIF
ZF ← UINTR.UIP
OF ← 0
SF ← 0
AF ← 0
PF ← 0


Summary: Pushes a floating-point value onto the FPU register stack (ST0).

Loads a floating-point value (32-bit single, 64-bit double, or 80-bit extended precision) from memory, converts if necessary to 80-bit extended precision, and pushes it onto the x87 FPU register stack (ST(0)). Stack pointer (TOP) is decremented by one; overflow to an invalid slot raises #IS (stack fault). No CPU flags are modified; the instruction may set x87 exception flags (PE, UE, OE, IE) in the x87 status word.

ST(0) ← load_and_convert(memory)
TOP ← TOP - 1
if TOP underflow: raise x87_stack_fault


Summary: Copies the value in ST(0) to memory or another register.

Stores the value in ST(0) to memory as either 32-bit single or 64-bit double precision (converting from 80-bit extended if necessary), without popping the stack. The source remains in ST(0); floating-point exceptions (PE, UE, OE) may be raised in the x87 status word if conversion underflows, overflows, or loses precision. No CPU flags are modified.

memory ← convert_to_32or64bit(ST(0))
if conversion_error: raise x87_exception


Summary: Copies ST(0) to destination and pops the register stack.

Stores the value in ST(0) to memory (as 32-bit single, 64-bit double, or 80-bit extended precision, converting if necessary), then pops the register stack by incrementing TOP. The source register is invalidated after the pop; floating-point exceptions may be raised in the x87 status word during conversion. No CPU flags are modified.

memory ← convert_and_store(ST(0))
TOP ← TOP + 1
if conversion_error: raise x87_exception


Summary: Converts integer in memory to double-extended-precision float and pushes to ST(0).

Loads a signed integer (16-bit, 32-bit, or 64-bit) from memory, converts it to 80-bit extended precision floating-point, and pushes onto the x87 register stack (ST(0)). Stack pointer is decremented; conversion is exact and raises no precision or rounding exceptions unless stack overflow occurs. No CPU flags are modified.

ST(0) ← convert_integer_to_fp80(memory)
TOP ← TOP - 1
if TOP underflow: raise x87_stack_fault


Summary: Converts ST(0) to integer and stores in memory.

Converts the floating-point value in ST(0) to a signed integer using the current rounding mode and stores the result in the specified 16-bit or 32-bit memory location. The x87 FPU status flags (C0, C1, C2, C3) may be set depending on rounding or overflow conditions. The stack top (ST(0)) remains unchanged after the operation.

dest ← convert_to_integer(ST(0), rounding_mode);
update_x87_status_flags();


Summary: Converts ST(0) to integer, stores in memory, and pops stack.

Converts the floating-point value in ST(0) to a signed integer using the current rounding mode, stores the result in the specified 16-bit, 32-bit, or 64-bit memory location, and then pops the FPU stack. The x87 status flags may be updated based on rounding or overflow conditions. The stack top pointer is decremented after the operation.

dest ← convert_to_integer(ST(0), rounding_mode);
update_x87_status_flags();
ST(0) is popped; stack_top ← stack_top - 1;


Summary: Adds src to dest (ST(0) += src).

Adds the floating-point operand in memory (m32fp or m64fp) to ST(0) and stores the result in ST(0). The operation follows IEEE 754 semantics with the current rounding mode. The x87 FPU status flags (C0, C1, C2, C3) are updated based on the result; invalid operation, underflow, overflow, or precision exceptions may be raised.

src_value ← load_from_memory(src);
ST(0) ← ST(0) + src_value;
update_x87_status_flags();


Summary: Subtracts src from dest.

Subtracts the floating-point operand in memory (m32fp or m64fp) from ST(0) and stores the result in ST(0). The operation follows IEEE 754 semantics with the current rounding mode. The x87 FPU status flags (C0, C1, C2, C3) are updated; invalid operation, underflow, overflow, or precision exceptions may be raised.

src_value ← load_from_memory(src);
ST(0) ← ST(0) - src_value;
update_x87_status_flags();


Summary: Multiplies dest by src.

Multiplies ST(0) by the floating-point operand in memory (m32fp or m64fp) and stores the result in ST(0). The operation follows IEEE 754 semantics with the current rounding mode. The x87 FPU status flags (C0, C1, C2, C3) are updated; invalid operation, underflow, overflow, or precision exceptions may be raised.

src_value ← load_from_memory(src);
ST(0) ← ST(0) × src_value;
update_x87_status_flags();


Summary: Divides dest by src.

Divides ST(0) by the floating-point operand in memory (m32fp or m64fp) and stores the result in ST(0). The operation follows IEEE 754 semantics with the current rounding mode. The x87 FPU status flags (C0, C1, C2, C3) are updated; division-by-zero, invalid operation, underflow, overflow, or precision exceptions may be raised.

src_value ← load_from_memory(src);
ST(0) ← ST(0) ÷ src_value;
update_x87_status_flags();


Summary: Computes remainder of ST(0) / ST(1).

Computes the IEEE partial remainder of ST(0) divided by ST(1), storing the result in ST(0). This instruction performs an iterative reduction and may require multiple iterations to complete; the C2 flag indicates whether the result is incomplete (more iterations needed). The x87 status flags (C0, C1, C2, C3) encode the sign and partial quotient information.

quotient ← ST(0) ÷ ST(1);
remainder ← ST(0) - (rounded_quotient × ST(1));
ST(0) ← remainder;
C0, C1, C2, C3 ← encode_quotient_and_status(quotient, remainder);


Summary: Replaces ST(0) with its absolute value.

Replaces the value in ST(0) with its absolute value by clearing the sign bit. The operation does not modify the x87 status flags and does not raise exceptions. This is a fast unary operation that operates solely on the register stack.


Summary: Reverses the sign of ST(0).

Reverses the sign bit of the value in ST(0), converting positive to negative and vice versa. This is a single-bit operation on the sign bit of the extended-precision floating-point format. No flags are affected; the instruction operates entirely within the x87 FPU stack.


Summary: Computes square root of ST(0).

Computes the square root of ST(0) and replaces ST(0) with the result using extended-precision floating-point arithmetic. The x87 FPU C1 flag may be set based on stack conditions; other x87 status flags (C0, C2, C3) are updated according to the result. This is a transcendental operation with typical latency of 70-100 cycles.


Summary: Computes sine of ST(0) (in radians).

Computes the sine of ST(0), where the argument is interpreted as an angle in radians. The result replaces ST(0); the x87 FPU status flags are updated. This transcendental instruction has high latency and may trigger a C2 flag if the argument is outside the acceptable range (roughly ±2^63).


Summary: Computes cosine of ST(0) (in radians).

Computes the cosine of ST(0), where the argument is interpreted as an angle in radians. The result replaces ST(0); the x87 FPU status flags are updated. This transcendental instruction may set the C2 flag if the argument exceeds the acceptable range.


Summary: Computes sine and cosine of ST(0), pushing both to stack.

Computes both sine and cosine of ST(0) in a single operation, pushing the cosine result onto the stack and leaving the sine in ST(0). The stack pointer is incremented after the push, so the sine ends up in ST(0) and cosine in ST(1). The x87 status flags are updated; C2 may be set if the argument is out of range.

temp ← ST(0); ST(0) ← sin(temp); push(cos(temp)); TOS ← TOS + 1


Summary: Computes tangent of ST(0) and pushes 1.0.

Computes the tangent of ST(0) and then pushes 1.0 onto the stack, so ST(0) becomes tan(original ST(0)) and the constant 1.0 moves to ST(1). The x87 status flags are updated; C2 may be set if the argument is out of the acceptable range. This is used in conjuction with FPATAN to compute arctangent.

temp ← ST(0); ST(0) ← tan(temp); push(1.0); TOS ← TOS + 1


Summary: Computes arctan(ST(1)/ST(0)).

Computes the two-argument arctangent of ST(1)/ST(0) and replaces both stack entries with the result in ST(0); the stack pointer is decremented. The result is in the range [-π/2, π/2] or [-π, π] depending on the signs of ST(1) and ST(0). The x87 status flags are updated accordingly.

ST(0) ← atan2(ST(1), ST(0)); pop(); TOS ← TOS - 1


Summary: Computes ST(1) * log2(ST(0)).

Computes ST(1) * log₂(ST(0)) and replaces both stack entries with the result in ST(0); the stack pointer is decremented. ST(0) must be strictly positive; the result is typically used for computing logarithmic and exponential functions. The x87 status flags are updated; C2 may be set for out-of-range arguments.

ST(0) ← ST(1) * log2(ST(0)); pop(); TOS ← TOS - 1


Summary: Exchanges contents of ST(0) and ST(i).

Exchanges the contents of ST(0) and ST(i), swapping the top of the x87 FPU stack with another stack register. This is a register-only operation with no impact on EFLAGS. The instruction is part of the x87 FPU instruction set and does not cause pipeline serialization.

temp ← ST(0);
ST(0) ← ST(i);
ST(i) ← temp;


Summary: Compares ST(0) with source.

Compares ST(0) with a single-precision (m32fp) or double-precision (m64fp) floating-point memory operand and sets the FPU condition code flags (C0, C2, C3) in the status word. The comparison result is reflected only in FPU flags, not in CPU EFLAGS. This instruction does not modify the stack.

src_value ← [memory];
if (ST(0) > src_value) { C0←0; C2←0; C3←0; }
else if (ST(0) < src_value) { C0←1; C2←0; C3←0; }
else if (ST(0) == src_value) { C0←0; C2←0; C3←1; }
else { C0←1; C2←1; C3←1; }


Summary: Compares ST(0) with ST(i) and sets CPU EFLAGS directly.

Compares ST(0) with ST(i) and directly sets the CPU EFLAGS (ZF, PF, CF) to reflect the comparison result, enabling use of standard conditional jumps without FSTSW. Available on P6 and later processors. The comparison does not pop the stack and affects CPU flags rather than FPU condition codes.

if (ST(0) > ST(i)) { ZF←0; PF←0; CF←0; }
else if (ST(0) < ST(i)) { ZF←0; PF←0; CF←1; }
else if (ST(0) == ST(i)) { ZF←1; PF←0; CF←0; }
else { ZF←1; PF←1; CF←1; }


Summary: Resets FPU to default state.

Initializes the x87 FPU to its default state, clearing the stack, setting control word to 0x037F (round to nearest, all exceptions masked), and clearing all status flags and exception flags. The instruction is preceded by FWAIT (0x9B) to ensure any pending FPU operations complete before reinitializing. This causes full FPU state reset with no impact on integer registers or EFLAGS.

FPU_Control_Word ← 0x037F;
FPU_Status_Word ← 0x0000;
FPU_Tag_Word ← 0xFFFF;
for (i = 0; i < 8; i++) ST(i) ← 0.0;
FPU_Exception_Flags ← 0;


Summary: Clears floating-point exception flags.

Clears all floating-point exception flags (IE, DE, ZE, OE, UE, PE) in the FPU status word without clearing the condition codes or the stack. The instruction is preceded by FWAIT (0x9B) to synchronize with any pending FPU operations. Does not affect CPU EFLAGS or FPU control/tag words.

FPU_Status_Word.IE ← 0;
FPU_Status_Word.DE ← 0;
FPU_Status_Word.ZE ← 0;
FPU_Status_Word.OE ← 0;
FPU_Status_Word.UE ← 0;
FPU_Status_Word.PE ← 0;


Summary: Stores FPU status word to AX or memory.

Stores the FPU status word (16-bit value containing exception flags, condition codes, stack pointer, and busy bit) into AX or memory. When destination is AX, the instruction may be used to examine FPU state from integer code without memory operands. The encoding shown (9B DF E0) uses FWAIT prefix and stores to AX; memory forms use D9 /7.

if (destination == AX) {
  AX ← FPU_Status_Word;
} else {
  [memory] ← FPU_Status_Word;
}


Summary: Loads FPU control word from memory.

Loads a 16-bit control word from memory into the FPU control word register, affecting rounding mode, exception masks, precision control, and other FPU operating parameters. This instruction does not require FWAIT and takes effect immediately on subsequent FPU instructions. Changes to rounding mode and exception masks apply only to future floating-point operations.


Summary: Stores FPU control word to memory.

Stores the current FPU control word (16-bit value) to memory, preserving rounding mode, exception mask bits, precision control, and infinity control settings. The instruction is preceded by FWAIT (0x9B) to ensure any pending FPU operations complete before the store. Does not affect CPU EFLAGS or FPU stack contents.


Summary: Loads FPU state from memory.

Loads the complete x87 FPU state (108 bytes) from memory, including all eight floating-point registers, control word, status word, tag word, instruction pointer, and data pointer. This instruction does not set any CPU flags and is not serializing. It is available in all CPU modes (real, protected, 64-bit) and requires memory operand addressing.

FPU_state ← [m108byte]
// Restores: FPR0-FPR7, CW, SW, TW, IP, DP, DS, opcode


Summary: Stores FPU state to memory and re-initializes FPU.

Saves the entire x87 FPU state (108 bytes) to memory and reinitializes the FPU to its default state. The instruction issues an implicit FWAIT (0x9B prefix) to ensure prior floating-point operations complete before saving. No CPU flags are set; the instruction is serializing with respect to x87 operations. Available in all modes.

[m108byte] ← FPU_state
// Saves: FPR0-FPR7, CW, SW, TW, IP, DP, DS, opcode
FPU_state ← initial_state


Summary: Loads the GDT register (Privileged).

Loads the Global Descriptor Table (GDT) register with a limit (16 bits) and base address (32 bits in 32-bit mode, 64 bits in 64-bit mode) from a 6-byte or 10-byte memory operand. This is a privileged instruction (requires CPL=0) and causes a pipeline flush. No flags are affected. In 64-bit mode, the operand is 10 bytes (16-bit limit + 64-bit base).

GDTR.limit ← [m16&32 + 0:1]
GDTR.base ← [m16&32 + 2:5]  // 32-bit or 64-bit depending on mode


Load Interrupt Descriptor Table Register

Summary: Loads the IDT register (Privileged).

Loads the Interrupt Descriptor Table (IDT) register with a limit (16 bits) and base address (32 bits in 32-bit mode, 64 bits in 64-bit mode) from a 6-byte or 10-byte memory operand. This is a privileged instruction (requires CPL=0) and causes a pipeline flush. No flags are affected. In 64-bit mode, the operand is 10 bytes (16-bit limit + 64-bit base).

IDTR.limit ← [m16&32 + 0:1]
IDTR.base ← [m16&32 + 2:5]  // 32-bit or 64-bit depending on mode


Summary: Stores GDT limit and base address to memory.

Stores the current Global Descriptor Table (GDT) register contents (limit and base address) to memory. The format is 2-byte limit followed by 4-byte base in 32-bit mode, or 2-byte limit followed by 8-byte base in 64-bit mode. No flags are affected. This instruction is not privileged and can be executed at any CPL.

[m + 0:1] ← GDTR.limit
[m + 2:5] ← GDTR.base  // 4 or 8 bytes depending on mode


Store Interrupt Descriptor Table Register

Summary: Stores IDT limit and base address to memory.

Stores the current Interrupt Descriptor Table (IDT) register contents (limit and base address) to memory. The format is 2-byte limit followed by 4-byte base in 32-bit mode, or 2-byte limit followed by 8-byte base in 64-bit mode. No flags are affected. This instruction is not privileged and can be executed at any CPL.

[m + 0:1] ← IDTR.limit
[m + 2:5] ← IDTR.base  // 4 or 8 bytes depending on mode


Summary: Loads LDT segment selector (Privileged).

Loads the Local Descriptor Table (LDT) register with a 16-bit segment selector from a register or memory. This is a privileged instruction (requires CPL=0) and causes a pipeline flush. The selector must reference a valid LDT descriptor in the GDT; an invalid selector clears the LDT register. No flags are affected.

LDTR ← r/m16
// Selector is validated; if invalid, LDTR is cleared


Summary: Stores LDT segment selector.

Stores the current Local Descriptor Table (LDT) register contents (16-bit segment selector) into a register or memory. If the destination is a 32-bit or 64-bit register, the selector is zero-extended. No flags are affected. This instruction is not privileged and can be executed at any CPL.

r/m16 ← LDTR  // For 32/64-bit dest: zero-extended


Summary: Loads Task Register (Privileged).

Loads a 16-bit Task Register selector from a register or memory operand. This privileged instruction (CPL=0 only) loads the TR register with a task gate descriptor selector, initiating task switching if the selector points to a valid TSS descriptor. No flags are affected.

TR ← source[15:0]; (task switch occurs if source is valid TSS selector)


Summary: Stores Task Register.

Stores the current Task Register selector into a 16-bit register or memory operand. This non-privileged instruction reads the TR register and writes its selector value; it operates in all modes and does not affect any flags.


Summary: Moves data to/from Control Registers (CR0, CR3, etc.) (Privileged).

Moves a 32-bit or 64-bit value from a general-purpose register to a control register (CR0, CR2, CR3, CR4, CR8 in 64-bit mode). This privileged instruction (CPL=0 only) performs hardware state modification with potential serialization effects; certain CR writes invalidate TLBs or flush caches. No arithmetic flags are affected.

CRn ← r (where n ∈ {0,2,3,4,8}); TLB and cache invalidation may occur


Summary: Moves data to/from Debug Registers (DR0-DR7) (Privileged).

Moves a 32-bit or 64-bit value from a general-purpose register to a debug register (DR0-DR7). This privileged instruction (CPL=0 only) performs hardware debug state modification; writes to DR6 and DR7 may clear breakpoint conditions and alter breakpoint control. No arithmetic flags are affected.

DRn ← r (where n ∈ {0,1,2,3,6,7}); breakpoint state may change


Summary: Loads Machine Status Word (Legacy CR0 modification).

Loads the lower 4 bits of a 16-bit operand into the lower 4 bits of CR0 (the machine status word: PE, MP, EM, TS). This privileged instruction (CPL=0 only) affects processor mode and FPU handling; it can enable protected mode but cannot disable it or modify higher CR0 bits. No flags are affected.

CR0[3:0] ← source[3:0]; (legacy CR0 access, cannot clear PE or modify bits 31:4)


Summary: Stores Machine Status Word.

Stores the lower 16 bits of CR0 (the machine status word: PE, MP, EM, TS, and reserved bits) into a 16-bit register or memory operand. This non-privileged instruction reads CR0[15:0]; in 64-bit mode, a 32-bit destination is zero-extended to 64 bits. No flags are affected.

dest ← CR0[15:0]; (in 64-bit with r64 operand: dest ← CR0[15:0] zero-extended to 64 bits)


Summary: Clears the TS flag in CR0 (Privileged).

Clears the Task-Switched flag (TS, bit 3) in CR0. This privileged instruction (CPL=0 only) allows the processor to use the FPU without raising a #NM exception; it is typically executed after an FPU context save. No flags are affected.


Summary: Flushes internal caches without writing back data (Privileged).

Invalidates all internal cache lines without writing back modified data to memory. This privileged instruction (CPL=0 only) causes a complete pipeline flush and memory ordering barrier; dirty cache lines are discarded, potentially losing uncommitted writes, making it dangerous for general use. No flags are affected.


Summary: Writes back modified data and invalidates caches (Privileged).

Writes back all modified cache lines to memory and invalidates all internal caches, ensuring cache coherency across the system. This is a privileged instruction (CPL 0 only) that serializes the pipeline and may take hundreds of cycles. No flags are affected.

for each cache line in all caches:
  if (cache_line.modified) write_to_memory(cache_line);
  invalidate(cache_line);
Pipeline_Serialization();


Summary: Invalidates a specific TLB entry (Privileged).

Invalidates the TLB entry for the linear address specified by the memory operand, forcing a TLB reload on next access. This is a privileged instruction (CPL 0 only) used after page table modifications. No flags are affected; pipeline serialization may occur depending on implementation.

linear_address ← address_of(m);
TLB[linear_address].valid ← 0;


Summary: Reads MSR specified by ECX into EDX:EAX (Privileged).

Reads a 64-bit Model Specific Register (MSR) whose index is in ECX and stores the result in EDX:EAX (EDX holds bits 63-32, EAX holds bits 31-0). This is a privileged instruction (CPL 0 only) that may cause a general protection fault if ECX selects an invalid or inaccessible MSR. No EFLAGS are modified.

msr_index ← ECX;
msr_value ← MSR[msr_index];
EAX ← msr_value[31:0];
EDX ← msr_value[63:32];


Summary: Writes EDX:EAX to MSR specified by ECX (Privileged).

Writes a 64-bit value from EDX:EAX to the Model Specific Register (MSR) whose index is in ECX (EDX holds bits 63-32, EAX holds bits 31-0). This is a privileged instruction (CPL 0 only) that serializes execution and may cause a general protection fault if ECX selects an invalid or write-protected MSR. No EFLAGS are modified.

msr_index ← ECX;
msr_value ← (EDX << 32) | EAX;
MSR[msr_index] ← msr_value;
Pipeline_Serialization();


Summary: Reads performance counter specified by ECX into EDX:EAX.

Reads a 40-bit performance monitoring counter whose index is in ECX and stores the result in EDX:EAX (EDX holds bits 39-32, EAX holds bits 31-0). User-mode execution may be permitted depending on RDPMC flag in CR4; a general protection fault occurs if not allowed. No EFLAGS are modified.

counter_index ← ECX;
counter_value ← PMC[counter_index];
EAX ← counter_value[31:0];
EDX ← counter_value[39:32] & 0xFF;


Summary: Fast call to level 0 system procedures.

Fast transition from user mode (CPL 3) to kernel mode (CPL 0) by loading CS, SS, EIP, and ESP from IA32_SYSENTER_* MSRs. This instruction serializes the pipeline, disables interrupts, and clears EFLAGS.IF. It is the fast-path alternative to INT for system calls.

if (CPL != 3) raise_exception(INVALID_OPCODE);
CS ← IA32_SYSENTER_CS & ~3; // load kernel code segment
SS ← (IA32_SYSENTER_CS + 8) | 0; // load kernel stack segment
EIP ← IA32_SYSENTER_EIP;
ESP ← IA32_SYSENTER_ESP;
EFLAGS.IF ← 0;
Pipeline_Serialization();


Summary: Fast return to level 3 user code.

Fast return from kernel mode (CPL 0) to user mode (CPL 3) by restoring CS, SS, EIP, and ESP from implicit registers or operands. This instruction serializes the pipeline and re-enables interrupts. It complements SYSENTER for rapid system call returns.

if (CPL != 0) raise_exception(INVALID_OPCODE);
CS ← (IA32_SYSENTER_CS + 16) | 3; // load user code segment
SS ← (IA32_SYSENTER_CS + 24) | 3; // load user stack segment
EIP ← ECX;
ESP ← EDX;
EFLAGS.IF ← 1;
Pipeline_Serialization();


Summary: Reads access rights from segment descriptor.

Loads the access rights byte from the segment descriptor referenced by the 16-bit selector in r/m16 into the destination general-purpose register (zero-extended to 32 or 64 bits). The ZF flag is cleared if the selector is invalid or references a data segment; ZF is set if successful. No other flags are modified.

selector ← r/m16;
if (selector is invalid || descriptor_type(selector) != code_segment) {
  ZF ← 0;
} else {
  dest ← zero_extend(descriptor_access_rights_byte(selector));
  ZF ← 1;
}


Summary: Reads segment limit from descriptor.

Loads the segment limit from the descriptor table entry referenced by the source selector into the destination register. The instruction reads the descriptor from the GDT or LDT, extracts the limit field, and writes it to the destination. The ZF flag is cleared if the selector is valid and the descriptor is accessible; ZF is set if the selector is invalid or the descriptor type is unsuitable. This instruction is privileged and operates only in protected mode or 64-bit mode.

selector ← src[15:0];
descriptor ← load_descriptor(selector);
if (descriptor is valid AND descriptor.type in {code, data, tss, gate}) {
  dest ← descriptor.limit;
  ZF ← 0;
} else {
  ZF ← 1;
}


Summary: Checks if segment can be read; sets ZF.

Verifies that the segment referenced by the selector can be read by the current code. The instruction loads the descriptor table entry and checks the segment type and privilege level. ZF is set to 1 if the selector is valid and readable at the current privilege level; ZF is cleared if the selector is invalid, the descriptor type is unsuitable, or privilege checks fail. This instruction is privileged and operates only in protected or 64-bit mode.

selector ← src[15:0];
descriptor ← load_descriptor(selector);
if (descriptor is valid AND descriptor.type in {data, code-readable} AND cpl_check_passes) {
  ZF ← 1;
} else {
  ZF ← 0;
}


Summary: Checks if segment can be written; sets ZF.

Verifies that the segment referenced by the selector can be written by the current code. The instruction loads the descriptor table entry and checks the segment type and privilege level. ZF is set to 1 if the selector is valid and writable at the current privilege level; ZF is cleared if the selector is invalid, the descriptor type is unsuitable (e.g., code segment or read-only data), or privilege checks fail. This instruction is privileged and operates only in protected or 64-bit mode.

selector ← src[15:0];
descriptor ← load_descriptor(selector);
if (descriptor is valid AND descriptor.type in {data-writable} AND cpl_check_passes) {
  ZF ← 1;
} else {
  ZF ← 0;
}


Summary: Adjusts RPL of selector to match current CPL (Legacy).

Adjusts the Requested Privilege Level (RPL) field of a selector to match the current Code Privilege Level (CPL) if the selector's current RPL is less privileged than CPL. If the adjustment occurs, ZF is set; otherwise ZF is cleared. This is a legacy instruction used in 32-bit protected mode to enforce privilege level consistency; it is not supported in 64-bit mode. All flags except ZF are unchanged.

selector ← dest[15:0];
rpl ← selector[1:0];
cpl ← current_cpl;
if (rpl < cpl) {
  selector[1:0] ← cpl;
  dest ← selector;
  ZF ← 1;
} else {
  ZF ← 0;
}


Summary: Exits SMM and returns to previous state (Privileged).

Resumes normal CPU operation from System Management Mode (SMM), restoring processor state from the SMM state save area and resuming execution at the return instruction pointer saved at SMM entry. This instruction is privileged and can only be executed inside SMM. The CPU context (all registers, segment descriptors, and memory-type ranges) is restored atomically, and control flow returns to the interrupted code or handler.

restore_cpu_state_from_smm_save_area();
return_eip ← SMM_SAVE_AREA[return_address_offset];
jump(return_eip);


Summary: Reverses the byte order of a 32/64-bit register.

Reverses the byte order within a 32-bit or 64-bit general-purpose register. In 32-bit mode, bits [7:0] swap with [31:24] and bits [15:8] swap with [23:16]. In 64-bit mode, all 8 bytes are reversed. No flags are modified. For 16-bit operands, the instruction is undefined on modern processors.


Summary: Atomically compares EDX:EAX with memory; swaps if equal.

Atomically compares the 64-bit value in EDX:EAX with the 64-bit memory operand; if equal, the instruction exchanges the value in ECX:EBX with memory and clears ZF, otherwise it loads memory into EDX:EAX and sets ZF. The operation is atomic at the memory bus level on single-processor systems and uses locked semantics on multiprocessor systems. All arithmetic flags (OF, SF, ZF, AF, CF, PF) are updated based on the compare result; other flags are undefined.

value_memory ← [dest];
if (EDX:EAX == value_memory) {
  [dest] ← ECX:EBX;
  ZF ← 1;
} else {
  EDX:EAX ← value_memory;
  ZF ← 0;
}
OF, SF, AF, CF, PF undefined;


Summary: Adds odd elements, subtracts even elements (Complex Math).

src

128-bit XMM SIMD register or Memory operand

Performs packed single-precision floating-point addition on odd-indexed elements (1, 3) and subtraction on even-indexed elements (0, 2) within 128-bit XMM operands. The first operand is destination and implicitly source; the second operand is source from register or memory. Exceptions are not masked and follow standard SIMD exception handling. No flags are modified; denormalized inputs may generate exceptions depending on MXCSR settings.


Summary: Adds adjacent float elements horizontally.

Adds adjacent pairs of single-precision floating-point values horizontally within 128-bit XMM registers. The instruction pairs elements from the destination and source operands, computing the sum of adjacent elements and storing results in the destination. No CPU flags are affected by this instruction.


Summary: Loads 64-bit double and duplicates it to fill 128-bit register.

Loads a 64-bit double-precision floating-point value from the source operand and duplicates it to fill the entire 128-bit XMM register destination. The lower 64 bits of the source are replicated to both the lower and upper 64 bits of the destination. No CPU flags are affected by this instruction.

temp64 ← src[0:63]
dest[0:63] ← temp64
dest[64:127] ← temp64


Summary: Loads unaligned data avoiding split-line penalties.

Loads 128 bits of unaligned integer data from memory into an XMM register without causing split-cache-line penalties on processors that support this instruction. This instruction provides better performance than MOVDQU for certain memory alignments. No CPU flags are affected by this instruction.


Summary: Shuffles bytes according to indices in source operand.

Shuffles bytes within 128-bit operands using a shuffle control mask in the source operand. For each byte in the destination, the corresponding control byte in the source specifies which byte from the destination is placed in that position; if bit 7 of the control byte is set, the result byte is zeroed. No CPU flags are affected by this instruction.

for i ← 0 to 15 do
  if src[i*8+7] == 1 then
    dest[i*8:i*8+7] ← 0
  else
    j ← src[i*8:i*8+3]
    dest[i*8:i*8+7] ← dest[j*8:j*8+7]
  end if
end for


Summary: Adds adjacent 16-bit integers horizontally.

Adds adjacent pairs of signed 16-bit integer values horizontally within 128-bit XMM registers. Two pairs are summed from the destination operand and two pairs from the source operand, with results placed in the lower and upper halves of the destination. No CPU flags are affected by this instruction.


Summary: Concatenates dest and src, extracts 128 bits byte-aligned.

Concatenates the 128-bit destination and 128-bit source operands into a 256-bit intermediate value, then extracts a 128-bit aligned region starting at a byte offset specified by an 8-bit immediate value. The result is stored in the destination operand. No CPU flags are affected by this instruction.

concat[0:255] ← (src[0:127] << 128) | dest[0:127]
shift_amount ← imm8 * 8
if shift_amount >= 128 then
  result ← 0
else
  result ← concat[shift_amount:shift_amount+127]
end if
dest[0:127] ← result


Packed Multiply High with Round and Scale

Summary: Multiplies signed 16-bit words, rounds, and scales.

Multiplies signed 16-bit integers from destination and source operands, returning the scaled and rounded high 16 bits of the 32-bit product (result = (product + 0x4000) >> 15). Saturation occurs if the result exceeds the signed 16-bit range. No CPU flags are affected by this instruction.

for i ← 0 to 7 do
  product[i] ← dest[i*16:i*16+15] * src[i*16:i*16+15]
  intermediate[i] ← product[i] + 0x4000
  result[i] ← intermediate[i] >> 15
  if result[i] > 32767 then
    dest[i*16:i*16+15] ← 32767
  else if result[i] < -32768 then
    dest[i*16:i*16+15] ← -32768
  else
    dest[i*16:i*16+15] ← result[i]
  end if
end for


Summary: Negates/Zeroes bytes in dest based on sign of src.

Negates or zeros bytes in the destination operand based on the sign of corresponding bytes in the source operand. If the source byte is negative, the destination byte is negated; if zero, the destination byte is zeroed; if positive, the destination byte is unchanged. No CPU flags are affected by this instruction.

for i ← 0 to 15 do
  if src[i*8:i*8+7] < 0 then
    dest[i*8:i*8+7] ← -dest[i*8:i*8+7]
  else if src[i*8:i*8+7] == 0 then
    dest[i*8:i*8+7] ← 0
  else
    dest[i*8:i*8+7] ← dest[i*8:i*8+7]
  end if
end for


Summary: Computes absolute value of bytes.

Computes the absolute value of each signed byte in the source operand and stores the result in the destination XMM register. All 16 bytes are processed in parallel; the value 0x80 (-128) is handled specially and remains 0x80. No flags are affected by this instruction.

for i = 0 to 15:
  byte = src[i]
  if byte == 0x80:
    dest[i] ← 0x80
  else if byte < 0:
    dest[i] ← -byte
  else:
    dest[i] ← byte


Summary: Selects floats from two sources based on immediate mask.

Selects single-precision floating-point values from two sources based on bit positions in an 8-bit immediate; bits 0-3 each control selection of one 32-bit element (0 selects dest, 1 selects src). Requires SSE4.1. No flags are affected.


Summary: Selects words from two sources based on immediate mask.

Selects 16-bit word values from two sources based on bit positions in an 8-bit immediate; bits 0-7 each control selection of one 16-bit word element (0 selects dest, 1 selects src). Requires SSE4.1. No flags are affected.


Summary: Adds operands and the Carry Flag (CF).

Adds the source operand and the Carry Flag (CF) to the destination operand, storing the result in the destination. Supports 8/16/32/64-bit sizes (64-bit in long mode only). Sets CF on unsigned overflow, SF/ZF/AF/OF/PF based on result; CF is critical for multi-precision arithmetic chains.

result ← dest + src + CF
dest ← result
CF ← unsigned_overflow(dest_old, src, CF)
OF ← signed_overflow(dest_old, src, result)
ZF ← (result == 0)
SF ← (result_sign_bit == 1)
AF ← ((dest_old & 0xF) + (src & 0xF) + CF) > 0xF
PF ← popcount(result & 0xFF) is even


Summary: Subtracts operands and the Carry Flag (CF).

Subtracts the source operand and the Carry Flag (CF) from the destination operand, storing the result in the destination. Supports 8/16/32/64-bit sizes (64-bit in long mode only). Sets CF on unsigned borrow, SF/ZF/AF/OF/PF based on result; CF enables multi-precision subtraction chains.

result ← dest - src - CF
dest ← result
CF ← unsigned_borrow(dest_old, src, CF)
OF ← signed_overflow(dest_old, src, result)
ZF ← (result == 0)
SF ← (result_sign_bit == 1)
AF ← ((dest_old & 0xF) - (src & 0xF) - CF) has unsigned borrow
PF ← popcount(result & 0xFF) is even


Summary: Shifts dest left, filling with bits from src.

Shifts the destination operand left by a count, filling the vacated bits from the most-significant bits of the source operand. Supports 16/32/64-bit operands; count comes from the immediate or implicitly from CL. Sets CF to the last bit shifted out, OF if count=1, SF/ZF/PF based on the result.

if count > operand_width:
  count ← count mod (operand_width + 1)
if count == 0:
  skip
else:
  CF ← bit_shifted_out_from_left
  dest ← (dest << count) | (src >> (operand_width - count))
  if count == 1:
    OF ← (dest_sign_bit_after != CF)
  else:
    OF ← undefined
  ZF ← (dest == 0)
  SF ← (dest_sign_bit == 1)
  PF ← popcount(dest & 0xFF) is even


Summary: Shifts dest right, filling with bits from src.

Shifts the destination operand right by a count, filling the vacated bits from the least-significant bits of the source operand. Supports 16/32/64-bit operands; count comes from the immediate or implicitly from CL. Sets CF to the last bit shifted out, OF if count=1, SF/ZF/PF based on the result.

if count > operand_width:
  count ← count mod (operand_width + 1)
if count == 0:
  skip
else:
  CF ← bit_shifted_out_from_right
  dest ← (dest >> count) | (src << (operand_width - count))
  if count == 1:
    OF ← (dest_sign_bit_after != bit_was_at_position_width_1)
  else:
    OF ← undefined
  ZF ← (dest == 0)
  SF ← (dest_sign_bit == 1)
  PF ← popcount(dest & 0xFF) is even


Summary: Permutes bytes in ZMM based on index vector.

Permutes bytes within 64-byte blocks of a ZMM register using a 512-bit index vector; each byte in the index selects a source byte (bits 3-0 select lane, bits 6-4 select byte within 64-byte lane). Requires AVX-512-VBMI. Supports write-masking via {k1}. No flags are affected.

for lane = 0 to 7:
  for byte_in_lane = 0 to 63:
    idx_byte = zmm2[lane*64 + byte_in_lane]
    src_lane = idx_byte & 0x7
    src_byte_offset = idx_byte >> 3
    if src_byte_offset < 64:
      selected = zmm3[src_lane*64 + src_byte_offset]
    else:
      selected = 0
    if k1[byte_in_lane] or k1 is not used:
      zmm1[lane*64 + byte_in_lane] ← selected


Summary: Shuffles bytes from two ZMM registers into destination.

Permutes bytes from two ZMM registers (destination and source) using byte indices in the second source, storing results in the destination. The instruction performs a gather-like operation where each byte index selects from either the destination or source register based on the high bit. No flags are modified; the operation is masked by the opmask register k1, with zeroing or merging semantics.


Summary: Shuffles bytes from two sources, overwriting index.

Permutes bytes from two sources using indices in the destination register (which is overwritten), selecting from either the index register or the second source based on the index's high bit. This is the two-operand form where indices reside in what becomes the output. No flags are modified; masking via k1 applies to the result with optional zeroing.


Select Packed Unaligned Bytes from Quadword Sources

Summary: Selects bytes from each 64-bit element based on shift control.

VPMULTISHIFTQB zmm1 {k1}, zmm2, zmm3/m512

Selects bytes from each 64-bit element by using 4-bit shift control values extracted from the control ZMM register. Each 8-bit control field specifies which of 8 bytes within its 64-bit source element to extract into each output byte. No flags are modified; the operation respects the opmask k1 for selective writing.


Summary: Funnel shift left of doublewords.

VPSHLDD zmm1 {k1}, zmm2, zmm3/m512, imm8

Performs a funnel left-shift (double concatenate) on 32-bit doublewords: each output doubleword is the logical left-shift result of concatenating src2 into src1, shifted left by the immediate count. Bits shifted out on the left are discarded; bits from src2 fill in on the right. No arithmetic flags are modified; the operation is EVEX-encoded with masking support via k1.

for i = 0 to 15:  // 16 doublewords
  concatenated = (zmm2[32*i+31:32*i] << 32) | zmm3[32*i+31:32*i]
  shift_amount = cnt & 0x1F
  zmm1[32*i+31:32*i] ← (concatenated >> (32 - shift_amount)) & 0xFFFFFFFF
  zmm1[32*i+31:32*i] ← zmm1[32*i+31:32*i] & k1_mask[i]


Summary: Funnel shift right of doublewords.

VPSHRDD zmm1 {k1}, zmm2, zmm3/m512, imm8

Performs a funnel right-shift (double concatenate) on 32-bit doublewords: each output doubleword is the logical right-shift result of concatenating src1 and src2, shifted right by the immediate count. Bits shifted out on the right are discarded; bits from src1 fill in on the left. No arithmetic flags are modified; masking via k1 applies to the result.

for i = 0 to 15:  // 16 doublewords
  concatenated = (zmm2[32*i+31:32*i] << 32) | zmm3[32*i+31:32*i]
  shift_amount = cnt & 0x1F
  zmm1[32*i+31:32*i] ← (concatenated >> shift_amount) & 0xFFFFFFFF
  zmm1[32*i+31:32*i] ← zmm1[32*i+31:32*i] & k1_mask[i]


Summary: Compresses active bytes from ZMM to memory.

Stores bytes from ZMM into memory at sparse, mask-selected positions: only bytes where the corresponding opmask bit k1 is set are written to consecutive memory locations. The instruction performs a contiguous write of active bytes while maintaining their relative order. No flags are modified; this is a memory write operation with variable length determined by the popcount of the mask.

byte_count = 0
for i = 0 to 63:
  if k1_mask[i] == 1:
    mem[byte_count] ← zmm1[8*i+7:8*i]
    byte_count += 1


Summary: Expands bytes from memory into sparse locations in ZMM.

Loads bytes from memory into sparse, mask-selected positions in ZMM: bytes at consecutive memory locations are placed into ZMM positions where the opmask k1 is set, with unmasked positions remaining zero or unchanged. This is the inverse of compress. No flags are modified; the operation fills a sparse vector from compact memory data.

byte_count = 0
for i = 0 to 63:
  if k1_mask[i] == 1:
    zmm1[8*i+7:8*i] ← mem[byte_count]
    byte_count += 1
  else:
    zmm1[8*i+7:8*i] ← 0  // or unchanged if merging mode


Summary: Counts set bits in each byte.

Counts the number of set bits (population count) in each byte of the source, writing the count (0-8) into the corresponding byte of the destination. This operates independently on each of 64 bytes in the ZMM register. No arithmetic flags are modified; the instruction is part of AVX-512-BITALG and supports masking via k1.

for i = 0 to 63:
  count = 0
  byte_val = zmm2[8*i+7:8*i]
  for bit = 0 to 7:
    if byte_val[bit] == 1:
      count += 1
  zmm1[8*i+7:8*i] ← count & k1_mask[i]


Shuffle Bits from Quadword Elements to Mask

Summary: Extracts bits from bytes and packs into a mask register.

Extracts bits from quadword elements using a shuffle pattern and packs them into a mask register. The operation uses zmm3/m512 as a bit-select control for each bit position in zmm2, extracting one bit per control byte and combining results into an 8-bit or 16-bit mask. This is a non-SIMD operation that produces only a mask output; no arithmetic flags are modified.


Summary: Computes intersection of two ZMM registers into mask pair.

Computes the intersection of two sets of doublewords and produces a pair of mask registers (k1 and k1+1). Each 32-bit element in zmm2 is compared against all elements in zmm3/m512; k1 contains matches at each position, and k1+1 contains match counts or indices. No arithmetic flags are modified; results are written only to the mask pair.

match_mask = 0;
match_count = 0;
for (i = 0; i < 16; i++) {
  matches = 0;
  for (j = 0; j < 16; j++) {
    if (zmm2[32*i : 32*i+31] == zmm3[32*j : 32*j+31]) {
      matches = 1;
      break;
    }
  }
  match_mask = match_mask | (matches << i);
  if (matches) match_count++;
}
k1 = match_mask;
k2 = match_count;


Packed Multiply-Add Unsigned 52-bit Integers (Low)

Summary: Fused multiply-add for 52-bit integers (Low 52 bits).

Performs a fused multiply-add operation on 52-bit unsigned integers, extracting the lower 52 bits of the 104-bit product and accumulating into the destination. For each 64-bit lane: compute (zmm2[63:0] * zmm3[63:0]) + (zmm1[63:0]), extract bits [51:0], and write back to zmm1. Supports masking via k1; no arithmetic flags are modified.

for (i = 0; i < 8; i++) {
  idx = 64*i;
  product = zmm2[idx+63 : idx] * zmm3[idx+63 : idx];
  sum = (product + zmm1[idx+63 : idx]);
  result = sum & 0xFFFFFFFFFFFFF;  // 52 bits
  zmm1[idx+63 : idx] = result;
  if (k1[i]) zmm1[idx+63 : idx] = result;
}


Packed Multiply-Add Unsigned 52-bit Integers (High)

Summary: Fused multiply-add for 52-bit integers (High 52 bits).

Performs a fused multiply-add operation on 52-bit unsigned integers, extracting the upper 52 bits of the 104-bit product and accumulating into the destination. For each 64-bit lane: compute (zmm2[63:0] * zmm3[63:0]) + (zmm1[63:0]), extract bits [103:52], and write back to zmm1. Supports masking via k1; no arithmetic flags are modified.

for (i = 0; i < 8; i++) {
  idx = 64*i;
  product = zmm2[idx+63 : idx] * zmm3[idx+63 : idx];
  sum = (product + zmm1[idx+63 : idx]);
  result = (sum >> 52) & 0xFFFFFFFFFFFFF;  // upper 52 bits
  if (k1[i]) zmm1[idx+63 : idx] = result;
}


Summary: Atomically adds a value to a remote memory location.

Atomically adds a 32-bit register value to a memory location without acquiring a lock and without returning the old value. This is a remote atomic operation that guarantees atomicity at the hardware level via cache coherency; the instruction does not serialize the entire pipeline but may have store ordering implications. No flags are modified; this is a write-only operation to memory.

atomic_add([dest], src);
// Semantically: [dest] ← [dest] + src


Summary: Atomically ANDs a value to a remote memory location.

Atomically ANDs a 32-bit register value with a memory location without acquiring a lock and without returning the old value. This remote atomic operation guarantees atomicity via cache coherency mechanisms; it does not serialize the entire pipeline but provides store-ordering guarantees. No flags are modified.

atomic_and([dest], src);
// Semantically: [dest] ← [dest] & src


Summary: Atomically ORs a value to a remote memory location.

Atomically ORs a 32-bit register value with a memory location without acquiring a lock and without returning the old value. This remote atomic operation uses cache coherency to guarantee atomicity; it does not serialize the full pipeline but enforces store ordering. No flags are modified.

atomic_or([dest], src);
// Semantically: [dest] ← [dest] | src


Summary: Atomically XORs a value to a remote memory location.

Atomically XORs a 32-bit register value with a memory location without acquiring a lock and without returning the old value. This remote atomic operation guarantees atomicity through cache coherency; it does not serialize the entire pipeline but maintains store-ordering properties. No flags are modified.

atomic_xor([dest], src);
// Semantically: [dest] ← [dest] ^ src


Summary: Atomically adds if condition is met.

Atomically compares a value in memory with an operand and adds a second operand to memory if the condition is met. This instruction is part of the APX (Advanced Performance eXtensions) and operates under EVEX encoding with implicit condition code selection via the embedded immediate. The instruction performs a compare-and-add loop at the CPU microarchitecture level, setting ZF based on the comparison result and CF/OF/SF based on the add operation if executed.

temp ← [dest]; ZF ← (temp == src1); if (condition_met) { [dest] ← [dest] + src2; CF ← carry_from_add; OF ← overflow_from_add; SF ← sign_of_result; } src1 ← temp;


Summary: Returns from an event handler to supervisor mode (FRED).

Returns from a FRED (Flexible Return and Event Delivery) event handler in supervisor mode, restoring the interrupted execution context from the event stack. This instruction is part of the FRED extension and performs implicit stack unwinding and privilege level restoration. No flags are modified; this is a serializing instruction that also flushes the instruction cache.

// Returns from an event handler to supervisor mode (FRED)


Summary: Returns from an event handler to user mode (FRED).

Returns from a FRED (Flexible Return and Event Delivery) event handler to user mode, restoring the interrupted user-level execution context from the event stack. This instruction is part of the FRED extension and performs implicit stack unwinding with privilege level transition. No flags are modified; this is a serializing instruction that flushes the instruction cache and clears sensitive state.

// Returns from an event handler to user mode (FRED)


Summary: Loads the kernel GS base address (FRED support).

Loads a 16-bit selector or handle into the kernel GS base register, supporting FRED event delivery. The instruction reads from the specified register and updates the MSR-backed kernel GS base, used for exception handler context. This is a privileged instruction (CPL = 0) and does not modify any flags.


Summary: Writes a command to a device (DSA/IAA accelerator).

Atomically enqueues a 512-bit command descriptor from memory to a device queue (DSA/IAA accelerator), writing a doorbell or status register via the destination register. The instruction performs an atomic write to the device, and ZF is set to indicate success or failure of the enqueue operation. This is a non-temporal memory operation and does not cache the 512-bit data.

// Writes a command to a device (DSA/IAA accelerator)


Summary: Configures platform features like MKTME (Memory Encryption).

Performs platform configuration operations such as MKTME (Memory Key Total Memory Encryption) setup, with the operation type specified implicitly via EAX. This is a privileged instruction (CPL = 0) that modifies platform encryption keys and memory encryption metadata. The instruction may serialize the pipeline and has implementation-dependent effects on cache coherency.

// Configures platform features like MKTME (Memory Encryption)


Summary: Writes back modified lines but keeps them valid in cache.

Writes back all modified cache lines to memory but keeps them valid in the L3 cache, improving performance compared to WBINVD which invalidates. This instruction is non-privileged and does not modify any flags. It provides write-back semantics without the full cache flush, useful for cache coherency operations while maintaining data locality.

// Writes back modified lines but keeps them valid in cache


Summary: Encrypts 8 blocks using 128-bit Key Locker handle.

Encrypts eight 128-bit blocks in parallel using a 128-bit Key Locker handle, performing wide-block AES encryption for high-throughput scenarios. The handle is loaded from memory and used to derive keys without exposing them, setting ZF to indicate success. This instruction operates on XMM0-XMM7 implicitly as input and output blocks, and clears sensitive key material after use.

handle ← [handle_mem]; if (valid_handle) { XMM0-XMM7 ← AES_ENC_WIDE_128(XMM0-XMM7, handle); ZF ← 0; } else { ZF ← 1; }


Summary: Encrypts 8 blocks using 256-bit Key Locker handle.

Encrypts 8 consecutive 128-bit blocks using AES in ECB mode with a 256-bit key loaded from a Key Locker handle. This instruction is part of the Key Locker extension and requires the handle at the memory operand to be a valid, initialized 512-bit Key Locker structure. The instruction reads plaintext from XMM0-XMM7, encrypts all blocks in parallel, and writes ciphertext back to XMM0-XMM7; ZF is set to 0 on success or 1 if the handle is invalid or key usage limit exceeded.

handle ← [mem128]
if (handle is invalid or usage_limit_exceeded) {
  ZF ← 1
} else {
  for i = 0 to 7:
    XMM[i] ← AES_Encrypt_256(XMM[i], key_from_handle)
  ZF ← 0
}


Summary: Compares ST(0) with source (supports NaNs).

Compares the top of the x87 FPU stack (ST(0)) with an operand (ST(i) by default) and sets condition code bits in the FPU status word. Unlike FCOM, FUCOM treats QNaN operands as comparable rather than signaling. The C3, C2, and C0 bits are set based on the comparison result (unordered, greater than, less than, or equal), and C1 is cleared.

if (is_unordered(ST(0), ST(i))) {
  C3 ← 1; C2 ← 1; C0 ← 1
} else if (ST(0) > ST(i)) {
  C3 ← 0; C2 ← 0; C0 ← 0
} else if (ST(0) < ST(i)) {
  C3 ← 0; C2 ← 0; C0 ← 1
} else {
  C3 ← 1; C2 ← 0; C0 ← 0
}
C1 ← 0


Summary: Rounds ST(0) to integer according to RC field.

Rounds the value in ST(0) to an integer according to the rounding control (RC) field in the FPU control word (bits 10-11). The result remains in ST(0) as a floating-point number with zero fractional part. This instruction does not pop the stack and does not set exception flags.

ST(0) ← round_to_integer(ST(0), RC_field)


Summary: Scales ST(0) by ST(1) (ST(0) * 2^ST(1)).

Scales ST(0) by raising 2 to the power of ST(1): ST(0) ← ST(0) × 2^ST(1). ST(1) must be an integer within the range [-2^31, 2^31-1]; if out of range or NaN, an invalid-operation exception is generated. The stack is not popped; ST(0) is replaced with the scaled result.

if (ST(1) is not integer or out_of_range) {
  raise_exception(invalid_operation)
} else {
  ST(0) ← ST(0) * (2 ^ trunc(ST(1)))
}


Summary: Separates exponent and significand of ST(0).

Separates ST(0) into its exponent (as an integer) and significand (as a number in [1, 2) or [0, ∞) for special values). The exponent is pushed onto the stack, and ST(0) is replaced with the significand, so the original value can be recovered as significand × 2^exponent. This operation logically duplicates and replaces ST(0), increasing stack depth.

exponent ← extract_exponent(ST(0))
significand ← extract_significand(ST(0))
FPU_stack_push(exponent)
ST(0) ← significand


Summary: Computes (2^ST(0)) - 1.

Computes 2^ST(0) - 1 and stores the result back in ST(0). ST(0) must be in the range [-1, 1] for accurate results; values outside this range produce undefined behavior or reduced accuracy. This instruction is used as part of logarithm and exponential function approximations in transcendental math libraries.

if (ST(0) < -1 or ST(0) > 1) {
  undefined_behavior()
} else {
  ST(0) ← (2 ^ ST(0)) - 1
}


Summary: Computes ST(1) * log2(ST(0) + 1).

Computes ST(1) × log₂(ST(0) + 1) and stores the result in ST(1), then pops ST(0). ST(0) must be in the range (-1, 1) for full accuracy. This instruction is optimized for computing logarithms of numbers close to 1 and is used in transcendental function implementations to reduce rounding error.

if (ST(0) <= -1 or ST(0) >= 1) {
  undefined_behavior()
} else {
  result ← ST(1) * log2(ST(0) + 1)
  FPU_stack_pop()
  ST(0) ← result
}


Summary: Clears the busy flag in the shadow stack token.

Clears the busy flag (bit 0) of a shadow stack token located at the memory address specified by the operand. This instruction is part of Control-flow Enforcement Technology (CET) Shadow Stack and is used to mark a shadow stack token as no longer busy (e.g., after an exception handler has completed). ZF is set to 0 on success or 1 if the token address is misaligned or the token is invalid.

token_addr ← m64
if (token_addr is misaligned or not_valid_token) {
  ZF ← 1
} else {
  [token_addr] ← [token_addr] & ~(1)  // Clear bit 0
  ZF ← 0
}


Summary: Matrix multiply (FP16 * FP16) accumulating to Float32.

Performs a tile matrix multiply-accumulate operation where two FP16 matrices (tmm2 and tmm3) are multiplied element-wise and accumulated into tmm1 as FP32 results. This is a specialized AMX instruction that leverages tile registers for high-throughput matrix operations. No standard CPU flags are affected; results that overflow to infinity or underflow to zero follow IEEE 754 semantics.

tmm1 ← tmm1 + (tmm2 * tmm3)  // FP16 × FP16 → FP32 accumulation, per tile dimensions


Summary: Moves a single float (low 32 bits) between XMM/Memory.

Moves a scalar single-precision (32-bit) floating-point value from the source to the low 32 bits of the destination XMM register. The upper 96 bits of the destination XMM register are preserved. No CPU flags are modified. This instruction operates in 32-bit mode or higher.


Summary: Moves a single double (low 64 bits) between XMM/Memory.

Moves a scalar double-precision (64-bit) floating-point value from the source to the low 64 bits of the destination XMM register. The upper 64 bits of the destination XMM register are preserved. No CPU flags are modified. This instruction operates in 32-bit mode or higher.


Convert Packed Doubleword to Packed Double-Precision

Summary: Converts two 32-bit integers to two 64-bit doubles.

Converts the lower two 32-bit signed doublewords from the source to two 64-bit IEEE 754 double-precision floating-point values in the destination XMM register. The conversion is exact (no rounding error for representable integers). No CPU flags are modified. Operates in 32-bit mode or higher with SSE2 support.

dest[63:0] ← CVTF64(src[31:0])   // lower 32-bit int to double
dest[127:64] ← CVTF64(src[63:32])  // upper 32-bit int to double


Convert Packed Double-Precision to Packed Doubleword

Summary: Converts two doubles to two 32-bit integers (Rounded).

Converts two 64-bit double-precision floating-point values from the source to two 32-bit signed doublewords in the destination XMM register, using the rounding mode specified by MXCSR. Overflow results are saturated to 0x80000000 (INT32_MIN) or 0x7FFFFFFF (INT32_MAX); invalid/NaN inputs produce 0x80000000. The upper 64 bits of the destination are zeroed. No CPU flags are modified.

rounding_mode ← MXCSR[13:11]
dest[31:0] ← CVTI32(src[63:0], rounding_mode)   // lower double to 32-bit int
dest[63:32] ← CVTI32(src[127:64], rounding_mode) // upper double to 32-bit int
dest[127:64] ← 0


Convert with Truncation Packed Double to Packed Doubleword

Summary: Converts two doubles to two 32-bit integers (Truncated).

Converts two 64-bit double-precision floating-point values from the source to two 32-bit signed doublewords in the destination XMM register, always using truncation (rounding towards zero), ignoring MXCSR. Overflow results are saturated to 0x80000000 (INT32_MIN) or 0x7FFFFFFF (INT32_MAX); invalid/NaN inputs produce 0x80000000. The upper 64 bits of the destination are zeroed. No CPU flags are modified.

dest[31:0] ← CVTI32_TRUNC(src[63:0])   // lower double to 32-bit int (truncate)
dest[63:32] ← CVTI32_TRUNC(src[127:64]) // upper double to 32-bit int (truncate)
dest[127:64] ← 0


Summary: Converts low float to integer (Rounded according to MXCSR).

dest

32-bit general-purpose register (e.g. EAX)

Converts the low 32-bit single-precision floating-point value from the source to a 32-bit signed integer in the destination general-purpose register, using the rounding mode specified by MXCSR. Overflow and invalid/NaN inputs produce 0x80000000 (INT32_MIN). In 64-bit mode, the destination register is zero-extended to 64 bits. No CPU flags are modified.

rounding_mode ← MXCSR[13:11]
dest[31:0] ← CVTI32(src[31:0], rounding_mode)
// In 64-bit mode: dest[63:32] ← 0


Summary: Converts low double to integer (Rounded according to MXCSR).

Converts the low 64-bit double-precision floating-point value from the source to a 32-bit signed integer in the destination general-purpose register, using the rounding mode specified by MXCSR. Overflow and invalid/NaN inputs produce 0x80000000 (INT32_MIN). In 64-bit mode, the destination register is zero-extended to 64 bits. No CPU flags are modified.

rounding_mode ← MXCSR[13:11]
dest[31:0] ← CVTI32(src[63:0], rounding_mode)
// In 64-bit mode: dest[63:32] ← 0


Summary: Converts half-precision floats to single-precision.

Converts four 16-bit half-precision floating-point values to four 32-bit single-precision floating-point values. The source contains up to four FP16 values packed in the lower 64 bits; the destination receives four FP32 results in a 128-bit XMM register. No flags are modified; this is a data conversion instruction.

dest[127:0] ← CONVERT_FP16_TO_FP32(src[63:0]); // upper 64 bits of dest are zeroed


Summary: Converts single-precision floats to half-precision.

Converts four 32-bit single-precision floating-point values to four 16-bit half-precision floating-point values using a rounding mode specified by imm8[2:0]. Results are packed into the lower 64 bits of the destination (register or memory); the upper 64 bits are cleared if destination is XMM. No flags are modified.

rounding_mode ← imm8[2:0]; dest[63:0] ← CONVERT_FP32_TO_FP16(src1[127:0], rounding_mode); dest[127:64] ← 0;


Summary: Sets ZF/CF based on sign bit comparisons of floats.

Performs a bitwise AND of two packed single-precision float vectors and sets ZF based on whether all result bits are zero, and CF based on whether all sign bits are set. No other flags are modified; OF, SF, AF, PF are undefined after execution.

temp ← dest[127:0] AND src[127:0]; ZF ← (temp == 0); CF ← ((dest[127] AND src[127]) AND (dest[95] AND src[95]) AND (dest[63] AND src[63]) AND (dest[31] AND src[31]));


Summary: Sets ZF/CF based on sign bit comparisons of doubles.

Performs a bitwise AND of two packed double-precision float vectors and sets ZF based on whether all result bits are zero, and CF based on whether both sign bits are set. No other flags are modified; OF, SF, AF, PF are undefined after execution.

temp ← dest[127:0] AND src[127:0]; ZF ← (temp == 0); CF ← ((dest[127] AND src[127]) AND (dest[63] AND src[63]));


Summary: Shuffles 128-bit float lanes between YMM registers.

256-bit YMM AVX register or Memory operand

Rearranges two 128-bit blocks from two 256-bit YMM operands into the destination 256-bit YMM register according to an 8-bit immediate selector. Bits [3:0] select which 128-bit half goes to the low 128 bits, bits [7:4] select the high 128 bits; bit 3 can zero-out the selected half. No flags are modified.


Summary: Hints to fetch data to L2 and L3 caches.

Non-binding hint to the memory system to fetch the byte at the given address into the L2 and L3 caches. The instruction is a no-op to program semantics; it has no effect on registers, flags, or memory, and serves only as a performance hint to reduce cache misses.

// Hints to fetch data to L2 and L3 caches


Summary: Hints to fetch data to L3 cache only.

Non-binding hint to the memory system to fetch the byte at the given address into the L3 cache. The instruction is a no-op to program semantics; it has no effect on registers, flags, or memory, and serves only as a performance hint.


Summary: Sign-extends 32-bit register to 64-bit.

64-bit general-purpose register (e.g. RAX)

Sign-extends a 32-bit value from a register or memory location to a 64-bit value and stores it in a 64-bit destination register. Only valid in 64-bit mode; the upper 32 bits of the destination are filled with sign-extended copies of bit 31 of the source. No flags are modified.


Summary: Single byte opcode (0xF1) used for In-Circuit Emulation.

Raises a single-byte breakpoint exception (SIMD debugger breakpoint) with opcode 0xF1, used primarily for In-Circuit Emulation (ICE) debugging. This instruction generates an INT 1 exception (vector 1) immediately without privilege level change. The instruction does not set or clear EFLAGS; it is a synchronous trap that suspends execution and invokes the debugger.

push_to_stack(EIP + 1);
push_to_stack(EFLAGS);
jump_to_IDT_entry(1);


Summary: Bitwise conditional move based on selector.

Performs bitwise conditional move on packed 128-bit XMM data using a selector register. For each bit in the selector (xmm4), if the bit is set (1), the corresponding bit from xmm3 is selected; otherwise, the bit from xmm2 is selected. Result is stored in xmm1. No flags are modified.

for i in 0 to 127:
  if (xmm4[i] == 1):
    xmm1[i] ← xmm3[i]
  else:
    xmm1[i] ← xmm2[i]


Summary: Compares bytes using immediate condition.

Compares 16 packed bytes in xmm2 and xmm3/m128 using the condition specified in imm8, storing comparison results (all-1s or all-0s per byte) in xmm1. Supports eight comparison predicates (EQ, LT, LE, etc.). No EFLAGS are modified; results are encoded as packed byte masks.

for i in 0 to 15:
  byte_a ← xmm2[i*8 : i*8+7]
  byte_b ← xmm3[i*8 : i*8+7]
  result ← evaluate_condition(byte_a, byte_b, imm8)
  xmm1[i*8 : i*8+7] ← result ? 0xFF : 0x00


Summary: Sets all bits below the lowest clear bit (x & (x+1)).

Fills all bits from the lowest clear bit position downward; computes (src & (src+1)) and stores the result in dest. This sets all bits below and including the position of the lowest 0-bit in the source. No flags are modified by this TBM instruction.


Summary: Extracts exponent from low float.

Extracts the biased exponent from the low 32-bit single-precision floating-point element of xmm3/m32 and stores the result as a float in xmm1. The exponent is converted to a normalized floating-point representation. Supports EVEX masking and rounding modes; other three 32-bit elements in xmm1 are preserved from xmm2.

float32 src_val ← xmm3[0:31]
int32 exponent ← extract_biased_exponent(src_val)
xmm1[0:31] ← convert_exponent_to_float(exponent)
xmm1[32:127] ← xmm2[32:127]


Summary: Extracts mantissa from low double.

VGETMANTSD xmm1 {k1}, xmm2, xmm3/m64, imm8

Extracts the mantissa (significand) from the low 64-bit double-precision floating-point element of xmm3/m64 using the normalization mode in imm8, storing the result as a double in xmm1. Supports EVEX masking and rounding modes; the high 64 bits of xmm1 are preserved from xmm2.

float64 src_val ← xmm3[0:63]
int8 mode ← imm8
float64 mantissa ← extract_mantissa(src_val, mode)
xmm1[0:63] ← mantissa
xmm1[64:127] ← xmm2[64:127]


Summary: Moves 64-bit data between MMX registers/memory.

Moves a 64-bit quadword from an MMX register or memory location to an MMX register. This instruction clears the upper 64 bits of the 128-bit XMM register if used with XMM operands (SSE variant). No flags are modified.


Summary: Adds 8 unsigned bytes with saturation (MMX).

Adds 8 pairs of packed unsigned 8-bit integers from the MMX register and memory/register source with saturation. If the sum exceeds 255, the result is saturated to 255. No flags are modified; the 64-bit result is stored in the destination MMX register.

for i in 0 to 7:
  byte_a ← dest[i*8 : i*8+7]
  byte_b ← src[i*8 : i*8+7]
  sum ← byte_a + byte_b
  dest[i*8 : i*8+7] ← min(sum, 255)


Summary: Adds 8 signed bytes with saturation (MMX).

Adds 8 signed byte pairs in parallel with saturation; if the result overflows (exceeds 127) or underflows (below -128), the result saturates to 127 or -128 respectively. This MMX instruction does not modify any EFLAGS; it operates entirely within the 64-bit MMX register or memory operand.

for i = 0 to 7:
  temp ← (signed8)dest[i*8+7:i*8] + (signed8)src[i*8+7:i*8]
  if temp > 127:
    dest[i*8+7:i*8] ← 127
  else if temp < -128:
    dest[i*8+7:i*8] ← -128
  else:
    dest[i*8+7:i*8] ← temp


Summary: Adds 4 unsigned words with saturation (MMX).

Adds 4 unsigned word pairs in parallel with saturation; overflow is clamped to 65535 (0xFFFF). This MMX instruction does not modify any EFLAGS and operates entirely within the 64-bit MMX register or memory operand.


Summary: Adds 4 signed words with saturation (MMX).

Adds 4 signed word pairs in parallel with saturation; overflow saturates to 32767 and underflow to -32768. This MMX instruction does not modify any EFLAGS and operates entirely within the 64-bit MMX register or memory operand.


Packed Subtract Unsigned Saturate Byte (MMX)

Summary: Subtracts 8 unsigned bytes with saturation (MMX).

Subtracts 8 unsigned byte pairs in parallel with saturation; underflow is clamped to 0. This MMX instruction does not modify any EFLAGS and operates entirely within the 64-bit MMX register or memory operand.

for i = 0 to 7:
  if (unsigned8)dest[i*8+7:i*8] < (unsigned8)src[i*8+7:i*8]:
    dest[i*8+7:i*8] ← 0
  else:
    dest[i*8+7:i*8] ← (unsigned8)dest[i*8+7:i*8] - (unsigned8)src[i*8+7:i*8]


Packed Subtract Signed Saturate Byte (MMX)

Summary: Subtracts 8 signed bytes with saturation (MMX).

Subtracts 8 signed byte pairs in parallel with saturation; underflow saturates to -128 and overflow to 127. This MMX instruction does not modify any EFLAGS and operates entirely within the 64-bit MMX register or memory operand.

for i = 0 to 7:
  temp ← (signed8)dest[i*8+7:i*8] - (signed8)src[i*8+7:i*8]
  if temp > 127:
    dest[i*8+7:i*8] ← 127
  else if temp < -128:
    dest[i*8+7:i*8] ← -128
  else:
    dest[i*8+7:i*8] ← temp


Packed Subtract Unsigned Saturate Word (MMX)

Summary: Subtracts 4 unsigned words with saturation (MMX).

Subtracts 4 unsigned word pairs in parallel with saturation; underflow is clamped to 0. This MMX instruction does not modify any EFLAGS and operates entirely within the 64-bit MMX register or memory operand.


Packed Subtract Signed Saturate Word (MMX)

Summary: Subtracts 4 signed words with saturation (MMX).

Subtracts 4 signed word pairs in parallel with saturation; underflow saturates to -32768 and overflow to 32767. This MMX instruction does not modify any EFLAGS and operates entirely within the 64-bit MMX register or memory operand.


Summary: Multiplies 4 words and stores low 16 bits (MMX).

Multiplies 4 word pairs in parallel and stores the low 16 bits of each product; the high 16 bits are discarded. This MMX instruction does not modify any EFLAGS and operates entirely within the 64-bit MMX register or memory operand.


Summary: Multiplies 4 signed words and stores high 16 bits (MMX).

Multiplies four signed 16-bit words in the destination MMX register by four signed 16-bit words in the source operand, and stores the high 16 bits of each 32-bit product in the destination register. This instruction operates on packed 16-bit signed integers and does not affect any flags. It requires MMX support and is commonly used in multimedia and DSP applications.


Packed Multiply Add Word to Doubleword (MMX)

Summary: Multiplies words and adds adjacent pairs (MMX).

Multiplies four pairs of signed 16-bit words, then adds the high and low results of adjacent pairs to produce two signed 32-bit doublewords. The destination MMX register receives the two packed 32-bit sums. This instruction does not affect any flags and is frequently used in audio/video processing and convolution operations.


Summary: Bitwise AND of 64-bit MMX registers.

Performs a bitwise AND of the 64-bit destination MMX register and a 64-bit source operand, storing the result in the destination. All 64 bits are treated as a single operand; no flag bits are affected. This instruction has no size variants and is available in all processors with MMX support.


Summary: Bitwise OR of 64-bit MMX registers.

Performs a bitwise OR of the 64-bit destination MMX register and a 64-bit source operand, storing the result in the destination. All 64 bits participate in the operation as a single unit; no flags are affected. This instruction is available on all MMX-capable processors and has no size variants.


Summary: Bitwise XOR of 64-bit MMX registers.

Performs a bitwise XOR of the 64-bit destination MMX register and a 64-bit source operand, storing the result in the destination. The operation treats all 64 bits as a single logical unit and does not affect any flags. Notably, PXOR with the same register as both operands can be used to zero a register in one cycle.


Summary: Bitwise AND NOT of 64-bit MMX registers.

Performs a bitwise AND NOT operation: the destination is AND'ed with the bitwise complement of the source, storing the result in the destination. Equivalent to (dest & ~src). No flags are modified and the operation processes all 64 bits in a single cycle on MMX-capable processors.


Summary: Compares bytes for greater than (MMX).

Compares four signed 8-bit bytes in the destination MMX register with four signed 8-bit bytes in the source operand. Each byte position in the destination is set to 0xFF if the destination byte is greater than the source byte, or 0x00 otherwise. No EFLAGS are affected by this comparison; results are returned as a packed mask in the MMX register.

FOR i = 0 TO 7 STEP 8:
  IF INT8(dest[i:i+7]) > INT8(src[i:i+7]) THEN
    dest[i:i+7] ← 0xFF;
  ELSE
    dest[i:i+7] ← 0x00;
  ENDIF;
ENDFOR;


Summary: Compares words for greater than (MMX).

Compares two signed 16-bit words in the destination MMX register with two signed 16-bit words in the source operand. Each word position in the destination is set to 0xFFFF if the destination word is greater than the source word, or 0x0000 otherwise. No EFLAGS are modified; comparison results are returned as a packed mask directly in the destination MMX register.

FOR i = 0 TO 2 STEP 16:
  IF INT16(dest[i:i+15]) > INT16(src[i:i+15]) THEN
    dest[i:i+15] ← 0xFFFF;
  ELSE
    dest[i:i+15] ← 0x0000;
  ENDIF;
ENDFOR;


Packed Compare Greater Than Doubleword (MMX)

Summary: Compares doublewords for greater than (MMX).

Performs a signed greater-than comparison on four packed 32-bit doublewords in the destination MMX register and source operand, setting each corresponding doubleword in the destination to all 1s if the comparison is true, or all 0s if false. No EFLAGS are affected; this is a data-parallel operation that operates entirely within the MMX register file.

for i = 0 to 1 {
  if (signed(dest.dword[i]) > signed(src.dword[i])) {
    dest.dword[i] ← 0xFFFFFFFF
  } else {
    dest.dword[i] ← 0x00000000
  }
}


Summary: Compares bytes for equality (MMX).

Performs an equality comparison on eight packed 8-bit bytes in the destination MMX register and source operand, setting each corresponding byte in the destination to all 1s if equal, or all 0s if not equal. No EFLAGS are affected; the result is a byte-wise mask suitable for conditional data selection.

for i = 0 to 7 {
  if (dest.byte[i] == src.byte[i]) {
    dest.byte[i] ← 0xFF
  } else {
    dest.byte[i] ← 0x00
  }
}


Summary: Compares words for equality (MMX).

Performs an equality comparison on four packed 16-bit words in the destination MMX register and source operand, setting each corresponding word in the destination to all 1s if equal, or all 0s if not equal. No EFLAGS are affected; this is used for creating word-level masks in SIMD operations.

for i = 0 to 3 {
  if (dest.word[i] == src.word[i]) {
    dest.word[i] ← 0xFFFF
  } else {
    dest.word[i] ← 0x0000
  }
}


Summary: Compares doublewords for equality (MMX).

Performs an equality comparison on two packed 32-bit doublewords in the destination MMX register and source operand, setting each corresponding doubleword in the destination to all 1s if equal, or all 0s if not equal. No EFLAGS are affected; the result is a doubleword-wise mask suitable for conditional operations.

for i = 0 to 1 {
  if (dest.dword[i] == src.dword[i]) {
    dest.dword[i] ← 0xFFFFFFFF
  } else {
    dest.dword[i] ← 0x00000000
  }
}


Summary: Shifts words left (MMX).

Performs a logical left shift on four packed 16-bit words in the destination MMX register by the count specified in the 8-bit immediate operand, shifting bits out to the left and filling vacated positions with zeros. No EFLAGS are affected; shift counts greater than or equal to 16 result in all zeros for the affected words.

count ← src & 0xFF
for i = 0 to 3 {
  if (count >= 16) {
    dest.word[i] ← 0x0000
  } else {
    dest.word[i] ← dest.word[i] << count
  }
}


Packed Shift Left Logical Doubleword (MMX)

Summary: Shifts doublewords left (MMX).

Performs a logical left shift on two packed 32-bit doublewords in the destination MMX register by the count specified in the 8-bit immediate operand, shifting bits out to the left and filling vacated positions with zeros. No EFLAGS are affected; shift counts greater than or equal to 32 result in all zeros for the affected doublewords.

count ← src & 0xFF
for i = 0 to 1 {
  if (count >= 32) {
    dest.dword[i] ← 0x00000000
  } else {
    dest.dword[i] ← dest.dword[i] << count
  }
}


Packed Shift Left Logical Quadword (MMX)

Summary: Shifts quadword left (MMX).

Performs a logical left shift on one packed 64-bit quadword in the destination MMX register by the count specified in the 8-bit immediate operand, shifting bits out to the left and filling vacated positions with zeros. No EFLAGS are affected; shift counts greater than or equal to 64 result in zero.

count ← src & 0xFF
if (count >= 64) {
  dest.qword[0] ← 0x0000000000000000
} else {
  dest.qword[0] ← dest.qword[0] << count
}


Summary: Shifts words right logical (MMX).

Performs a logical right shift on four packed 16-bit words in the destination MMX register by the count specified in the 8-bit immediate operand, shifting bits out to the right and filling vacated positions with zeros. No EFLAGS are affected; shift counts greater than or equal to 16 result in all zeros for the affected words.

count ← src & 0xFF
for i = 0 to 3 {
  if (count >= 16) {
    dest.word[i] ← 0x0000
  } else {
    dest.word[i] ← dest.word[i] >> count
  }
}


Packed Shift Right Logical Doubleword (MMX)

Summary: Shifts doublewords right logical (MMX).

Shifts each 32-bit doubleword element in an MMX register right by an immediate count, filling vacated high-order bits with zeros. This is a logical right shift (sign-insensitive) operating on packed doubleword elements. No flags are affected; the shift amount is masked to 5 bits (0-31).

count ← src AND 31;
for i ← 0 to 1 do
  dest.dw[i] ← dest.dw[i] >> count;
end;


Packed Shift Right Logical Quadword (MMX)

Summary: Shifts quadword right logical (MMX).

Shifts the 64-bit quadword in an MMX register right by an immediate count, filling vacated high-order bits with zeros. This is a logical right shift operating on a single 64-bit element. No flags are affected; the shift amount is masked to 6 bits (0-63).

count ← src AND 63;
dest.qw ← dest.qw >> count;


Packed Shift Right Arithmetic Word (MMX)

Summary: Shifts words right arithmetic (MMX).

Shifts each 16-bit word element in an MMX register right by an immediate count, filling vacated high-order bits with the sign bit (arithmetic shift). This preserves the sign of signed 16-bit integers. No flags are affected; the shift amount is masked to 4 bits (0-15).

count ← src AND 15;
for i ← 0 to 3 do
  dest.w[i] ← ARITHMETIC_SHIFT_RIGHT(dest.w[i], count);
end;


Packed Shift Right Arithmetic Doubleword (MMX)

Summary: Shifts doublewords right arithmetic (MMX).

Shifts each 32-bit doubleword element in an MMX register right by an immediate count, filling vacated high-order bits with the sign bit (arithmetic shift). This preserves the sign of signed 32-bit integers. No flags are affected; the shift amount is masked to 5 bits (0-31).

count ← src AND 31;
for i ← 0 to 1 do
  dest.dw[i] ← ARITHMETIC_SHIFT_RIGHT(dest.dw[i], count);
end;


Summary: Copies data from source to destination.

MOV EAX, 5    ; Load 5 into EAX
MOV [EBX], EAX ; Store EAX to memory at EBX

Copies data from the source register to the destination register or memory location. Operates on 16-bit, 32-bit, or 64-bit operands (size determined by operand-size prefix and REX.W in 64-bit mode). No flags are affected; memory ordering is not guaranteed with respect to other threads without explicit synchronization.


Summary: Adds src to dest and stores result in dest.

result ← dest + src;
OF ← overflow_occurred(dest, src, result);
SF ← (result < 0);
ZF ← (result == 0);
AF ← carry_from_bit(3);
PF ← parity(result);
CF ← carry_out;
dest ← result;

ADD EAX, EBX  ; Add EBX to EAX
ADD [EAX], 5  ; Add 5 to the 32-bit integer at address EAX

Adds the source operand to the destination operand and stores the result in the destination; the sum is computed modulo 2^(operand size). Sets OF, SF, ZF, AF, CF, and PF based on the result. Available in 16-bit, 32-bit, and 64-bit forms; operand size is determined by the prefix and REX.W in 64-bit mode.


Summary: Subtracts src from dest.

result ← dest - src;
OF ← overflow_occurred(dest, src, result);
SF ← (result < 0);
ZF ← (result == 0);
AF ← borrow_from_bit(3);
PF ← parity(result);
CF ← borrow_out;
dest ← result;

SUB EAX, 10   ; Subtract 10 from EAX
SUB ECX, EDX  ; Subtract EDX from ECX

Subtracts the source operand from the destination operand and stores the result in the destination; the difference is computed modulo 2^(operand size). Sets OF, SF, ZF, AF, CF, and PF based on the result. Available in 16-bit, 32-bit, and 64-bit forms; operand size is determined by the prefix and REX.W in 64-bit mode.


Summary: Performs bitwise AND.

Performs a bitwise logical AND of the destination and source operands, storing the result in the destination. Sets SF, ZF, and PF based on the result; clears OF and CF; AF is undefined. Available in 16-bit, 32-bit, and 64-bit forms; operand size is determined by the prefix and REX.W in 64-bit mode.

result ← dest AND src;
SF ← (result < 0);
ZF ← (result == 0);
PF ← parity(result);
OF ← 0;
CF ← 0;
AF ← undefined;
dest ← result;

AND EAX, 0xFF ; Keep lowest 8 bits
AND ECX, EDX  ; Bitwise AND of ECX and EDX


Summary: Performs bitwise OR.

Performs a bitwise logical OR between the destination and source operands, storing the result in the destination. Sets ZF, SF, and PF based on the result; clears OF and CF; AF is undefined. Available in 8, 16, 32, and 64-bit variants across all modes.

dest ← dest | src; ZF ← (result == 0); SF ← (result < 0); PF ← parity(result); CF ← 0; OF ← 0; AF ← undefined;

OR EAX, 1     ; Set lowest bit
OR EAX, EAX   ; Check if EAX is zero (sets ZF)


Summary: Performs bitwise XOR.

Performs a bitwise logical exclusive OR (XOR) between the destination and source operands, storing the result in the destination. Sets ZF, SF, and PF based on the result; clears OF and CF; AF is undefined. Available in 8, 16, 32, and 64-bit variants across all modes.

dest ← dest ^ src; ZF ← (result == 0); SF ← (result < 0); PF ← parity(result); CF ← 0; OF ← 0; AF ← undefined;

XOR EAX, EAX  ; Clear EAX (set to 0)
XOR EAX, 5    ; Toggle bits 0 and 2


Summary: Subtracts src from dest and updates flags (dest not modified).

Subtracts the source operand from the destination operand and updates the EFLAGS register without modifying the destination. Sets or clears CF, PF, AF, ZF, SF, and OF based on the subtraction result. Available in 8, 16, 32, and 64-bit variants across all modes.

temp ← dest - src; CF ← (dest < src); ZF ← (temp == 0); SF ← (temp < 0); OF ← overflow(dest, src); PF ← parity(temp); AF ← half_borrow(dest, src);

CMP EAX, 10   ; Compare EAX with 10
JE label      ; Jump if Equal


Summary: ANDs operands and updates flags (result discarded).

temp ← dest & src; ZF ← (temp == 0); SF ← (temp < 0); PF ← parity(temp); CF ← 0; OF ← 0; AF ← undefined;

TEST EAX, EAX ; Check if EAX is 0
TEST AL, 1    ; Check if lowest bit is set

Performs a bitwise logical AND between the destination and source operands, updating EFLAGS without modifying either operand. Sets ZF, SF, and PF based on the AND result; clears OF and CF; AF is undefined. Available in 8, 16, 32, and 64-bit variants across all modes.


Summary: Serializes load operations (Wait for prior loads to complete).

Serializes all load instructions that precede it in program order; subsequent loads wait until prior loads complete and their data is globally visible. Provides acquire-like semantics for loads on TSO (Total Store Order) architectures. No flags are affected. SSE2 extension; acts as a no-op on non-TSO systems without explicit serialization requirements.


Summary: Serializes store operations (Wait for prior stores to complete).

Serializes all store instructions that precede it in program order; subsequent stores wait until prior stores complete and are globally visible. Provides release-like semantics for stores. No flags are affected. SSE extension; acts as a no-op on processors where stores are already globally ordered.


Summary: Serializes all load and store operations.

Serializes all load and store instructions (both prior and subsequent) with respect to one another; acts as a full memory barrier. Ensures all prior memory operations complete and are globally visible before any subsequent memory operations begin. No flags are affected. SSE2 extension; commonly used for cross-CPU synchronization.


Summary: Flushes the cache line containing the operand from all caches.

Flushes the cache line containing the specified memory address from all cache levels (L1, L2, L3) without writing dirty data back to memory. Serializes the instruction stream and ensures all prior memory operations complete before execution. No flags are modified. Supported in protected and 64-bit modes; requires SSE2 or equivalent.

cache_line ← address_of(memory_address)
for each cache_level in (L1, L2, L3):
  invalidate(cache_line in cache_level)


Read Time-Stamp Counter and Processor ID

Summary: Reads TSC into EDX:EAX and Processor ID into ECX.

Reads the 64-bit Time-Stamp Counter (TSC) into EDX:EAX and writes the low byte of the IA32_TSC_AUX MSR into ECX. Acts as a serializing instruction, ensuring all prior instructions have completed before TSC is captured. No arithmetic flags are modified. Requires RDTSCP capability; available in both 32-bit and 64-bit modes.

EDX:EAX ← TSC
ECX ← (IA32_TSC_AUX MSR)[0:31]


Summary: Saves specified state components (AVX, SSE, etc.) to memory.

Saves processor extended state components (selected by EDX:EAX, typically FPU, SSE, AVX, and AVX-512 state) to a memory region starting at the address specified in the operand. Serializes the instruction stream and performs a context save without modifying any flags. Requires XSAVE capability; privilege level may be restricted depending on state component being saved.

state_mask ← EDX:EAX
for each enabled_state in state_components:
  if state_mask & enabled_state:
    memory_region ← save(enabled_state)


Summary: Restores specified state components from memory.

Restores processor extended state components (selected by EDX:EAX) from a memory region at the specified address. Loads FPU, SSE, AVX, and AVX-512 state as indicated by the state mask. Serializes the instruction stream and does not modify arithmetic flags. Requires XRSTOR capability; memory layout must match that produced by XSAVE.

state_mask ← EDX:EAX
for each enabled_state in state_components:
  if state_mask & enabled_state:
    enabled_state ← memory_region[offset]


Summary: Reads the state of XCR0 (feature mask) into EDX:EAX.

Reads the 64-bit value of extended control register XCR0 (feature mask indicating which extended processor states are enabled) into EDX:EAX. Does not modify any arithmetic flags. Requires XSAVE capability and typically requires execution at privilege level 0, though user-mode access may be permitted with UMWAIT or in certain OS configurations.


Summary: Writes EDX:EAX to XCR0 (Enables/disables AVX/SSE states).

Writes the 64-bit value from EDX:EAX into extended control register XCR0, enabling or disabling processor extended states (AVX, SSE, AVX-512, etc.). Serializes the instruction stream and forces all prior instructions to complete. No arithmetic flags are modified. Requires privilege level 0 and XSAVE capability.


Summary: Shuffles 32-bit floats between two XMM registers.

Shuffles four 32-bit single-precision floating-point values from the destination XMM register and source XMM/memory operand according to a 2-bit control value in the immediate byte, placing the result in the destination. The immediate selects which of the four source elements populate each destination element. No arithmetic flags are affected. Supported in SSE and later.


Summary: Shuffles 64-bit doubles between two XMM registers.

Shuffles two 64-bit double-precision floating-point values from the destination XMM register and source XMM/memory operand according to a 2-bit control value in the immediate byte, placing the result in the destination. The low bit selects element 0 of the result (from dest or src), the high bit selects element 1. No arithmetic flags are affected. Requires SSE2 or later.


Summary: Interleaves low floats from two registers.

Interleaves the low 64 bits (two 32-bit floats) from the destination XMM register with the low 64 bits from the source, producing [src[31:0], dest[31:0], src[63:32], dest[63:32]] in the destination. This SIMD instruction has no effect on CPU flags and operates only on the XMM register file. It is part of the SSE extension and works identically across all modern 64-bit modes.


Summary: Interleaves high floats from two registers.

Interleaves the high 64 bits (two 32-bit floats) from the destination XMM register with the high 64 bits from the source, producing [src[95:64], dest[95:64], src[127:96], dest[127:96]] in the destination. This SIMD instruction has no effect on CPU flags and operates only on the XMM register file. It is part of the SSE extension and works identically across all modern 64-bit modes.


Summary: Stores float vectors directly to RAM, bypassing cache.

Writes 128 bits from an XMM register directly to memory without bringing the cache line into the L1 data cache, using a write-combining memory type. This non-temporal store is optimal for streaming data that will not be reused soon. The instruction has no effect on CPU flags and executes as a store-to-memory operation without fence semantics.


Summary: Stores double vectors directly to RAM, bypassing cache.

Writes 128 bits from an XMM register directly to memory without bringing the cache line into the L1 data cache, using a write-combining memory type, operating on two 64-bit double-precision floats. This non-temporal store is optimal for streaming data that will not be reused soon. The instruction has no effect on CPU flags and executes as a store-to-memory operation without fence semantics.


Summary: Selects doubles from two sources based on immediate mask.

Selects each 64-bit double-precision element from the destination or source register based on the corresponding bit in an 8-bit immediate mask (bit 0 for element 0, bit 1 for element 1). If the bit is 0, the element from xmm1 is retained; if 1, the element from the source is used. No CPU flags are affected by this SIMD operation, which is part of the SSE4.1 extension.


Summary: Inserts a single float into a specific index of XMM.

Inserts a single 32-bit float from a source (register or memory) into a specific lane of the destination XMM register as specified by bits [5:4] of the immediate operand, and optionally zeros lanes specified by bits [3:0]. No CPU flags are affected by this SIMD operation, which is part of the SSE4.1 extension.

imm ← imm8;
count_d ← (imm >> 4) & 0x3;
zero_mask ← imm & 0xF;
src_dword ← src[31:0];
xmm1[count_d*32 + 31 : count_d*32] ← src_dword;
for i in 0 to 3:
  if (zero_mask & (1 << i)) then xmm1[i*32 + 31 : i*32] ← 0;


Summary: Extracts a single float from XMM to an integer register.

General-purpose register or Memory operand

Extracts a single 32-bit float from a source XMM register at a lane specified by bits [1:0] of the immediate operand and writes it to a 32-bit destination (GP register or memory). The extracted value is zero-extended if written to a 32-bit register. No CPU flags are affected by this SIMD operation, which is part of the SSE4.1 extension.

imm ← imm8;
index ← imm & 0x3;
src_dword ← xmm1[index*32 + 31 : index*32];
dest[31:0] ← src_dword;


Summary: Computes the dot product of two float vectors.

Computes the dot product of the four 32-bit float elements in the destination and source registers, then selectively masks the result and zeros based on an 8-bit immediate. The result (or zero) is replicated into each 32-bit element of the destination according to the mask. No CPU flags are affected by this SIMD operation, which is part of the SSE4.1 extension.

imm ← imm8;
product ← 0.0;
for i in 0 to 3:
  if (imm & (1 << (i+4))) then
    product ← product + (dest[i*32+31:i*32] * src[i*32+31:i*32]);
for i in 0 to 3:
  if (imm & (1 << i)) then
    dest[i*32+31:i*32] ← product;
  else
    dest[i*32+31:i*32] ← 0.0;


Summary: Computes the dot product of two double vectors.

Computes the dot product of two packed double-precision floating-point vectors (2 doubles per 128-bit operand) and stores the result in the destination. The imm8 byte controls which elements participate in the dot product and which output elements are zeroed. No flags are affected; this is a SSE4.1 instruction that operates only in 64-bit and protected modes.

select_mask ← imm8[7:4]
product_mask ← imm8[3:0]
temp ← 0.0
for i in 0..1:
  if (product_mask[i] == 1):
    temp ← temp + (xmm1[i*64+63:i*64] * src1[i*64+63:i*64])
for i in 0..1:
  if (select_mask[i] == 1):
    dest[i*64+63:i*64] ← temp
  else:
    dest[i*64+63:i*64] ← 0.0


Summary: Rounds all packed floats according to immediate mode.

Rounds each packed single-precision floating-point element in the source operand according to the rounding mode specified in imm8 and stores the result in the destination. The rounding mode imm8[2:0] selects between round-to-nearest, round-down, round-up, or truncate; bit 3 selects whether to suppress inexact exceptions. No CPU flags are modified; this is a SSE4.1 instruction available in 64-bit and protected modes.

rounding_mode ← imm8[2:0]
suppress_inexact ← imm8[3]
for i in 0..3:
  f32 ← src[i*32+31:i*32]
  if (rounding_mode == 0):  /* round to nearest */
    result ← round_nearest(f32)
  elif (rounding_mode == 1):  /* round down */
    result ← round_down(f32)
  elif (rounding_mode == 2):  /* round up */
    result ← round_up(f32)
  elif (rounding_mode == 3):  /* truncate */
    result ← truncate(f32)
  dest[i*32+31:i*32] ← result


Summary: Rounds all packed doubles according to immediate mode.

Rounds each packed double-precision floating-point element in the source operand according to the rounding mode specified in imm8 and stores the result in the destination. The rounding mode imm8[2:0] selects between round-to-nearest, round-down, round-up, or truncate; bit 3 controls inexact exception suppression. No CPU flags are modified; this is a SSE4.1 instruction available in 64-bit and protected modes.

rounding_mode ← imm8[2:0]
suppress_inexact ← imm8[3]
for i in 0..1:
  f64 ← src[i*64+63:i*64]
  if (rounding_mode == 0):  /* round to nearest */
    result ← round_nearest(f64)
  elif (rounding_mode == 1):  /* round down */
    result ← round_down(f64)
  elif (rounding_mode == 2):  /* round up */
    result ← round_up(f64)
  elif (rounding_mode == 3):  /* truncate */
    result ← truncate(f64)
  dest[i*64+63:i*64] ← result


Summary: Checks if 64-bit integer elements are equal.

Compares packed 64-bit signed integer elements in the destination and source operands for equality, setting all bits to 1 in the corresponding 64-bit result element if equal, or 0 if not equal. No CPU flags are affected; this is a SSE4.1 instruction available in 64-bit and protected modes.