VSX Scalar Convert with round to zero Quad-Precision to Unsigned Doubleword format X-form

Summary: Converts a quad-precision floating-point value to an unsigned doubleword integer, rounding towards zero.

The instruction converts the quad-precision floating-point value in VSR[VRB+32] to an unsigned doubleword integer, rounding towards zero. The result is placed into doubleword element 0 of VSR[VRT+32]. Doubleword element 1 of VSR[VRT+32] is set to 0.

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src ←bfp_CONVERT_FROM_BFP128(VSR[VRB+32])
vxsnan_flag ←0
vxcvi_flag ←0
if src.class.QNaN=1 | src.class.SNaN=1 then do
    result ←0x0000_0000_0000_0000
    vxsnan_flag ←src.class.SNaN
    vxcvi_flag ←1
end else if src.class.Infinity=1 then do
    vxcvi_flag ←1
    if src.sign=0 then
        result ←0xFFFF_FFFF_FFFF_FFFF
    else
        result ←0x0000_0000_0000_0000
    end
end else if src.class.Zero then
    result ←0x0000_0000_0000_0000
else do
    rnd ←bfp_ROUND_TO_INTEGER(0b001,src)
    if bfp_COMPARE_GT(rnd, +264-1) then do
        result ←0xFFFF_FFFF_FFFF_FFFF
        vxcvi_flag ←1
    end else if bfp_COMPARE_LT(rnd, 0) then do
        result ←0x0000_0000_0000_0000
        vxcvi_flag ←1
    end else do
        result ←ui64_CONVERT_FROM_BFP(rnd)
        if xx_flag=1 then SetFX(FPSCR.XX)
    end
end
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vxcvi_flag=1  then SetFX(FPSCR.VXCVI)
vx_flag ←vxsnan_flag | vxcvi_flag
ex_flag ←FPSCR.VE & vx_flag
if ex_flag=0 then do
    VSR[VRT+32].dword[0] ←result
    VSR[VRT+32].dword[1] ←0x0000_0000_0000_0000
end
FPSCR.FR ←(vx_flag=0) & inc_flag
FPSCR.FI ←(vx_flag=0) & xx_flag

FPSCR.FPRF, FPSCR.FR, FPSCR.FI, FPSCR.XX, FPSCR.VXSNAN, FPSCR.VXCVI

This instruction is used to convert a quad-precision floating-point number to an unsigned doubleword integer, rounding towards zero. Ensure the VSX facility is enabled; otherwise, it will raise an exception. Be cautious of NaNs and infinities, as they result in specific values and set condition flags. The operation does not require any particular alignment or privilege level.


Summary: Multiplies the contents of two registers and places the low-order 64 bits of the product into a target register.

prod0:127 ← (RA) × (RB)
RT ← prod0:63
if OE=1 then
    OV and OV32 are set to 1 if the product cannot be represented in 64 bits.

The 64-bit operands are (RA) and (RB). The low-order 64 bits of the 128-bit product of the operands are placed into register RT. Both operands and the product are interpreted as signed integers.

The XO-form Multiply instructions may execute faster on some implementations if RB contains the operand having the smaller absolute value.


Summary: Complements the contents of one register and places the result into another register.

The 'not' instruction complements the contents of register Ry and places the result into register Rx. This mnemonic can be coded with a final '.' to cause the Rc bit to be set in the underlying instruction.

if 'not' then
    Rx <- ~Ry
if 'not.' then
    Rx <- ~Ry
    Rc = 1

The 'not' instruction is commonly used for bitwise negation of a register's contents. Be cautious with the '.' suffix as it affects the condition register (CR0) by setting the Rc bit, which can impact subsequent conditional branches. Ensure that the registers are properly aligned and accessible at the privilege level required for execution.


Rotate Left Word Immediate Then AND with Mask (Record)

Summary: Rotates the low-order 32 bits of a register left by a specified number of bit positions, generates a mask, and performs an AND operation.

The contents of register RS are rotated32 left SH bits. A mask is generated having 1-bits from bit MB+32 through bit ME+32 and 0-bits elsewhere. The rotated data are ANDed with the generated mask and the result is placed into register RA.

if 'rlwinm' then
    n ← SH
    r ← ROTL32((RS)32:63, n)
    m ← MASK(MB+32, ME+32)
    RA ← r & m

Let RSL represent the low-order 32 bits of register RS, with the bits numbered from 0 through 31. rlwinm can be used to extract an n-bit field that starts at bit position b in RSL, right-justified into the low-order 32 bits of register RA (clearing the remaining 32-n bits of the low-order 32 bits of RA), by setting SH=b+n, MB=32-n, and ME=31. It can be used to extract an n-bit field that starts at bit position b in RSL, left-justified into the low-order 32 bits of register RA (clearing the remaining 32-n bits of the low-order 32 bits of RA), by setting SH=b, MB = 0, and ME=n-1. It can be used to rotate the contents of the low-order 32 bits of a register left (right) by n bits, by setting SH=n (32-n), MB=0, and ME=31. It can be used to shift the contents of the low-order 32 bits of a register right by n bits, by setting SH=32-n, MB=n, and ME=31. It can be used to clear the high-order b bits of the low-order 32 bits of the contents of a register and then shift the result left by n bits, by setting SH=n, MB=b-n, and ME=31-n. It can be used to clear the low-order n bits of the low-order 32 bits of a register, by setting SH=0, MB=0, and ME=31-n.


Rotate Left Word Then AND with Mask (Record)

Summary: Rotates the contents of register RS left by the number of bits specified by (RB)59:63, and then performs a bitwise AND operation with a mask.

The contents of register RS are rotated 32 left the number of bits specified by (RB)59:63. A mask is generated having 1-bits from bit MB+32 through bit ME+32 and 0-bits elsewhere. The rotated data are ANDed with the generated mask and the result is placed into register RA.

if 'rlwnm' then
    n ← (RB)59:63
    r ← ROTL32((RS)32:63, n)
    m ← MASK(MB+32, ME+32)
    RA ← r & m
else if 'rlwnm.' then
    n ← (RB)59:63
    r ← ROTL32((RS)32:63, n)
    m ← MASK(MB+32, ME+32)
    RA ← r & m

RS, with the bits numbered from 0 through 31. rlwnm can be used to extract an n-bit field that starts at variable bit position b in RSL, right-justified into the low-order 32 bits of register RA (clearing the remaining 32-n bits of the low-order 32 bits of RA), by setting RB59:63=b+n, MB=32-n, and ME=31. It can be used to extract an n-bit field that starts at variable bit position b in RSL, left-justified into the low-order 32 bits of register RA (clearing the remaining 32-n bits of the low-order 32 bits of RA), by setting RB59:63=b, MB = 0, and ME=n-1. It can be used to rotate the contents of the low-order 32 bits of a register left (right) by variable n bits, by setting RB59:63=n (32-n), MB=0, and ME=31.


Rotate Left Doubleword Immediate Clear (Record)

Summary: Rotates a 64-bit register left, then clears bits based on a mask. 64-bit equivalent of rlwinm.

if 'rldic' then
    SH ← sh5 || sh0:4
    r ← ROTL64((RS), SH)
    MB ← mb5 || mb0:4
    m ← MASK(MB, 63-SH)
    RA ← r & m

The contents of register RS are rotated64 left SH bits. A mask is generated having 1-bits from bit MB through bit 63-SH and 0-bits elsewhere. The rotated data are ANDed with the generated mask and the result is placed into register RA.

rldic can be used to clear the high-order b bits of the contents of a register and then shift the result left by n bits, by setting SH=n and MB=b-n. It can be used to clear the high-order n bits of a register, by setting SH=0 and MB=n.


Summary: Sign extends the low byte of a register to the full width.

The contents of the specified byte (RS)56 are placed into RA56:63, and RA0:55 are filled with a copy of (RS)56.

if 'extsb' then
    s ← (RS)56
    RA56:63 ← (RS)56:63
    RA0:55 ← 56s
else if 'extsb.' then
    s ← (RS)56
    RA56:63 ← (RS)56:63
    RA0:55 ← 56s

The extsb instruction is commonly used to sign-extend a byte value into a full word. Ensure the source register contains the correct byte to avoid unexpected results. This instruction operates at user privilege level and does not generate exceptions under normal conditions.


Summary: Sign extends the low word (32-bit) to 64 bits.

The contents of register RS are extended to fill the upper 32 bits of register RA, and the lower 32 bits of RA are filled with a copy of the upper 32 bits of RS.

if 'extsw' then
    s ← (RS)32
    RA32:63 ← (RS)32:63
    RA0:31 ← 32s
else if 'extsw.' then
    s ← (RS)32
    RA32:63 ← (RS)32:63
    RA0:31 ← 32s

The extsw instruction is commonly used to sign-extend a 32-bit value in RS to a 64-bit value in RA. Ensure that the source register RS contains the correct 32-bit signed integer to avoid unexpected results. This instruction operates at user privilege level and does not generate exceptions under normal circumstances.


Summary: Performs a bitwise OR operation between the contents of two registers and the complement of the third register.

The contents of register RS are ORed with the complement of the contents of register RB, and the result is placed into register RA.

if 'orc' then
    RA <- (RS) | ¬(RB)
else if 'orc.' then
    RA <- (RS) | ¬(RB)
    CR0 <- result of OR operation

The orc instruction is useful for setting bits in a register based on the complement of another register. Be cautious with bit manipulation as incorrect usage can lead to unexpected results. The instruction operates at user privilege level and does not generate exceptions under normal conditions. Performance may vary depending on the specific implementation and architecture.


Summary: Moves the contents of the Floating-Point Status and Control Register (FPSCR) into a floating-point register.

Moves the contents of the Floating-Point Status and Control Register (FPSCR) into floating-point register FRT. If Rc=1 (mffs.), the instruction updates CR1 based on the moved FPSCR value. This is a privileged instruction that does not alter FPSCR itself.

FRT ← FPSCR
if Rc = 1 then
  CR1 ← (FRT[0:3])

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.


Summary: Moves the contents of a floating-point register into specified fields of the FPSCR.

The FPSCR is modified as specified by the FLM, L, and W fields. If L=0, the contents of register FRB are placed into the FPSCR under control of the W field and the field mask specified by FLM. If L=1, the contents of register FRB are placed into the FPSCR.

if 'mtfsf' then
    if L=0 then
        for i from 0 to 7 do
            if FLMi=1 then
                FPSCR[k] <- FRB[i+8*(1-W)]
            end if
        end for
    else if L=1 then
        FPSCR <- FRB
    end if
end if

Bits 33 and 34 (FEX and VX) cannot be explicitly reset.
If L=1 or if L=0 and FPSCR32:35 is specified, bits 32 (FX) and 35 (OX) are set to the values of (FRB)32 and (FRB)35.


Floating Reciprocal Square Root Estimate (Record)

Summary: Estimates the reciprocal of the square root of a floating-point operand.

A estimate of the reciprocal of the square root of the floating-point operand in register FRB is placed into register FRT. The estimate placed into register FRT is correct to a precision of one part in 32 of the reciprocal of the square root of (FRB).

The frsqrte instruction provides a fast, approximate reciprocal square root calculation. It is useful for performance-critical applications where precision can be traded for speed. Ensure the input in FRB is positive to avoid undefined behavior. The result may need refinement for higher precision applications.


Summary: Compares two vector registers element by element as unsigned bytes and sets the target vector register based on the comparison.

The Vector Integer Compare instructions compare two VSRs element by element, interpreting the elements as unsigned or signed integers depending on the instruction, and set the corresponding element of the target VSR to all 1s if the relation being tested is true and to all 0s if the relation being tested is false.

if MSR.VEC=0 then Vector_Unavailable()
all_true ←1
all_false ←1
do i = 0 to 15
    src1 ←VSR[VRA+32].byte[i]
    src2 ←VSR[VRB+32].byte[i]
    if src1 = src2 then do
        VSR[VRT+32].byte[i] ←0xFF
        all_false ←0
    end
    else do
        VSR[VRT+32].byte[i] ←0x00
        all_true ←0
    end
end
if Rc=1 then
    CR.field[6] ←all_true || 0b0 || all_false || 0b0

vcmpequb[.], vcmpequh[.], vcmpequw[.], and vcmpequd[.] can be used for unsigned or signed integers.


Summary: Compares each halfword of two vector registers and sets the corresponding halfword in the target register to all 1s if they are equal, otherwise all 0s.

For vcmpequh, each halfword of VSR[VRA+32] is compared with the corresponding halfword of VSR[VRB+32]. If they are equal, the corresponding halfword in VSR[VRT+32] is set to all 1s (0xFFFF); otherwise, it is set to all 0s (0x0000).

if MSR.VEC=0 then Vector_Unavailable()

all_true ←1
all_false ←1
do i = 0 to 7
   src1 ←VSR[VRA+32].hword[i]
   src2 ←VSR[VRB+32].hword[i]
   if src1 = src2 then do
      VSR[VRT+32].hword[i] ←0xFFFF
      all_false ←0
   end
   else do
      VSR[VRT+32].hword[i] ←0x0000
      all_true ←0
   end
end
do i = 0 to 7
   src1 ←VSR[VRA+32].hword[i]
   src2 ←VSR[VRB+32].hword[i]
   if src1 = src2 then do
      VSR[VRT+32].hword[i] ←0xFFFF
      all_false ←0
   end
   else do
      VSR[VRT+32].hword[i] ←0x0000
      all_true ←0
   end
end
if Rc=1 then
   CR.field[6] ←all_true || 0b0 || all_false || 0b0


Vector Compare Equal Doubleword (Record)

Summary: Compares two vector registers for equality on an unsigned doubleword basis and stores the result in a third vector register.

Compares two vector registers element-wise for equality on an unsigned doubleword basis (2 64-bit elements) and stores a mask in the destination vector register, with all 1s where elements are equal and all 0s where unequal. When the record bit (.) is set, the CR6 field is updated to reflect whether any or all comparisons are equal.

for i in 0 to 1 do
  if VRA[i] = VRB[i] then
    VRT[i] ← 0xFFFF_FFFF_FFFF_FFFF
  else
    VRT[i] ← 0x0000_0000_0000_0000
if Rc = 1 then CR6 ← comparison results


Vector Compare Greater Than Signed Byte (Record)

Summary: Compares each byte of two vector registers and sets the corresponding result byte to all 1s if the signed byte in the first source register is greater than the signed byte in the second source register, otherwise sets it to all 0s.

For vcmpgtsb, each byte of VSR[VRA+32] is compared with the corresponding byte of VSR[VRB+32]. If the signed byte in VSR[VRA+32] is greater than the signed byte in VSR[VRB+32], then the corresponding byte in VSR[VRT+32] is set to all 1s (0xFF). Otherwise, it is set to all 0s (0x00).

if MSR.VEC=0 then Vector_Unavailable()
all_true ←1
all_false ←1
do i = 0 to 15
    src1 ←EXTS(VSR[VRA+32].byte[i])
    src2 ←EXTS(VSR[VRB+32].byte[i])
    if src1 > src2 then do
        VSR[VRT+32].byte[i] ←0xFF
        all_false ←0
    end
    else do
        VSR[VRT+32].byte[i] ←0x00
        all_true ←0
    end
end
if Rc=1 then
    CR.field[6] ←all_true || 0b0 || all_false || 0b0


Vector Compare Greater Than Signed Halfword (Record)

Summary: Compares each halfword of two vector registers and sets the corresponding result element to all 1s if the first operand is greater than the second, otherwise all 0s.

For vcmpgtsh, each halfword of VSR[VRA+32] is compared with the corresponding halfword of VSR[VRB+32]. If the signed value in VSR[VRA+32].hword[i] is greater than that in VSR[VRB+32].hword[i], then VSR[VRT+32].hword[i] is set to 0xFFFF; otherwise, it is set to 0x0000.

if MSR.VEC=0 then Vector_Unavailable()
all_true ←1
all_false ←1
do i = 0 to 7
    src1 ←EXTS(VSR[VRA+32].hword[i])
    src2 ←EXTS(VSR[VRB+32].hword[i])
    if src1 > src2 then do
        VSR[VRT+32].hword[i] ←0xFFFF
        all_false ←0
    end
    else do
        VSR[VRT+32].hword[i] ←0x0000
        all_true ←0
    end
end
if Rc=1 then
    CR.field[6] ←all_true || 0b0 || all_false || 0b0


Vector Compare Greater Than Signed Word (Record)

Summary: Compares each word of two vector registers and sets the corresponding word in the target vector register to all 1s if the first operand is greater than the second, otherwise to all 0s.

For vcmpgtsw, each word of VSR[VRA+32] is compared with the corresponding word of VSR[VRB+32]. If the signed integer value in the word element i of VSR[VRA+32] is greater than that in VSR[VRB+32], then the contents of word element i of VSR[VRT+32] are set to all 1s; otherwise, they are set to all 0s.

if MSR.VEC=0 then
    Vector_Unavailable()
all_true ←1
all_false ←1
do i = 0 to 3
    src1 ←EXTS(VSR[VRA+32].word[i])
    src2 ←EXTS(VSR[VRB+32].word[i])
    if src1 > src2 then do
        VSR[VRT+32].word[i] ←0xFFFF_FFFF
        all_false ←0
    end
    else do
        VSR[VRT+32].word[i] ←0x0000_0000
        all_true ←0
    end
end
if Rc=1 then
    CR.field[6] ←all_true || 0b0 || all_false || 0b0


Vector Compare Greater Than Signed Doubleword (Record)

Summary: Compares two doublewords of signed integers and sets the result vector based on the comparison.

For vcmpgtsd, each doubleword in VSR[VRA+32] is compared to the corresponding doubleword in VSR[VRB+32]. If a doubleword in VSR[VRA+32] is greater than the corresponding doubleword in VSR[VRB+32], the corresponding doubleword in VSR[VRT+32] is set to all 1s; otherwise, it is set to all 0s.

if MSR.VEC=0 then Vector_Unavailable()
all_true ←1
all_false ←1
do i = 0 to 1
    src1 ←EXTS(VSR[VRA+32].dword[i])
    src2 ←EXTS(VSR[VRB+32].dword[i])
    if src1 > src2 then do
        VSR[VRT+32].dword[i] ←0xFFFF_FFFF_FFFF_FFFF
        all_false ←0
    end
    else do
        VSR[VRT+32].dword[i] ←0x0000_0000_0000_0000
        all_true ←0
    end
end
if Rc=1 then
    CR.field[6] ←all_true || 0b0 || all_false || 0b0


VSX Vector Compare Equal Double-Precision (Record)

Summary: Compares two double-precision floating-point values in vector registers and sets the target register based on equality.

For xvcmpeqdp, each element of the source vectors VSR[XA] and VSR[XB] is compared. The result is stored in VSR[XT]. If Rc=1, CR field 6 is updated with comparison results.

if MSR.VSX=0 then VSX_Unavailable()
ex_flag ←0b0
all_false ←0b1
all_true ←0b1
do i = 0 to 1
    reset_xflags()
    src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[i])
    src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])
    vxsnan_flag ←IsSNaN(src1) | IsSNaN(src2)
    if src1 = src2 then do
        all_false ←0b0
    end
    else do
        vresult.dword[i] ←0x0000_0000_0000_0000
        all_true ←0b0
    end
    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag)
end
if Rc=1 then do
    if vex_flag=0 then
        CR[6] ←all_true || 0b0 || all_false || 0b0
    else
        CR[6] ←0bUUUU
end


VSX Vector Compare Greater Than Double-Precision (Record)

Summary: Compares two double-precision floating-point values and sets the target vector register based on the comparison.

For xvcmpgtdp, each element of the source vectors VSR[XA] and VSR[XB] is compared. The result is stored in VSR[XT]. If Rc=1, CR Field 6 is updated with the results of the comparison.

if MSR.VSX=0 then VSX_Unavailable()

ex_flag ← 0b0
all_false ← 0b1
all_true ← 0b1
do i = 0 to 1
    reset_xflags()
    src1 ← bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[i])
    src2 ← bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])
    if src1.class.SNaN | src2.class.SNaN then do
        vxsnan_flag ← 0b1
        if FPSCR.VE=0 then vxvc_flag ← 0b1
    end else vxvc_flag ← IsQNaN(src1) | IsQNaN(src2)
    if src1 > src2 then do
        vresult.dword[i] ← 0xFFFF_FFFF_FFFF_FFFF
        all_false ← 0b0
    end else do
        all_true ← 0b0
        vresult.dword[i] ← 0x0000_0000_0000_0000
    end
    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    if vxvc_flag=1 then SetFX(FPSCR.VXVC)
    ex_flag ← ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vxvc_flag)
end
if ex_flag=0 then VSR[32×TX+T] ← vresult
if Rc=1 then do
    if vex_flag=0 then CR.field[6] ← all_true || 0b0 || all_false || 0b0 else CR.field[6] ← 0bUUUU
end


VSX Vector Compare Greater or Equal Double-Precision (Record)

For xvcmpgedp, each integer value i from 0 to 1, the double-precision floating-point operand in doubleword element i of VSR[XA] is compared to the double-precision floating-point operand in doubleword element i of VSR[XB]. The contents of doubleword element i of VSR[XT] are set to all 1s if src1 is greater than or equal to src2, and is set to all 0s otherwise.

if MSR.VSX=0 then VSX_Unavailable()
ex_flag ←0b0
all_false ←0b1
all_true ←0b1
do i = 0 to 1
    reset_xflags()
    src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[i])
    src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])
    if src1.class.SNaN | src2.class.SNaN then do
        vxsnan_flag ←0b1
        if FPSCR.VE=0 then vxvc_flag ←0b1
    end
    else vxvc_flag ←IsQNaN(src1) | IsQNaN(src2)
    if src1 >= src2 then do
        vresult.dword[i] ←0xFFFF_FFFF_FFFF_FFFF
        all_false ←0b0
    end
    else do
        vresult.dword[i] ←0x0000_0000_0000_0000
        all_true ←0b0
    end
    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    if vxvc_flag=1 then SetFX(FPSCR.VXVC)
    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vxvc_flag)
end
if ex_flag=0 then VSR[32×TX+T] ←vresult
if Rc=1 then do
    if vex_flag=0 then CR.field[6] ←all_true || 0b0 || all_false || 0b0
    else CR.field[6] ←0bUUUU
end


VSX Vector Compare Equal Single-Precision (Record)

Summary: Compares each single-precision floating-point element of two VSX registers and sets the corresponding element in the target register to all 1s if they are equal, otherwise all 0s.

For xvcmpeqsp, each integer value i from 0 to 3, the single-precision floating-point operand in word element i of VSR[XA] is compared to the single-precision floating-point operand in word element i of VSR[XB]. The contents of word element i of VSR[XT] are set to all 1s if they are equal, and all 0s otherwise.

if MSR.VSX=0 then VSX_Unavailable()
ex_flag ←0b0
all_false ←0b1
all_true ←0b1
do i = 0 to 3
    reset_xflags()
    src1 ←bfp_CONVERT_FROM_BFP32(VSR[32×AX+A].word[i])
    src2 ←bfp_CONVERT_FROM_BFP32(VSR[32×BX+B].word[i])
    vxsnan_flag ←IsSNaN(src1) | IsSNaN(src2)
    if src1 = src2 then do
        all_false ←0b0
    end
    else do
        vresult.word[i] ←0x0000_0000
        all_true ←0b0
    end
    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag)
end
if Rc=1 then do
    if vex_flag=0 then
        CR.field[6] ←all_true || 0b0 || all_false || 0b0
    else
        CR.field[6] ←0bUUUU
end


VSX Vector Compare Greater Than Single-Precision (Record)

Summary: Compares each single-precision floating-point element in two vector registers and sets the corresponding element in a target vector register to all 1s if the first element is greater than the second, otherwise all 0s.

For xvcmpgtsp, each integer value i from 0 to 3, the single-precision floating-point operand in word element i of VSR[XA] is compared to the single-precision floating-point operand in word element i of VSR[XB]. The contents of word element i of VSR[XT] are set to all 1s if the first operand is greater than the second, and all 0s otherwise.

if MSR.VSX=0 then VSX_Unavailable()

ex_flag ←0b0
all_false ←0b1
all_true ←0b1
do i = 0 to 3
    reset_xflags()
    src1 ←bfp_CONVERT_FROM_BFP32(VSR[32×AX+A].word[i])
    src2 ←bfp_CONVERT_FROM_BFP32(VSR[32×BX+B].word[i])
    if IsSNaN(src1)=1 | IsSNaN(src2)=1 then do
        vxsnan_flag ←0b1
        if FPSCR.VE=0 then vxvc_flag ←0b1
    end
    else
        vxvc_flag ←src1.class.QNaN | src2.class.QNaN
    if src1 > src2 then do
        vresult.word[i] ←0xFFFF_FFFF
        all_false ←0b0
    end
    else
        vresult.word[i] ←0x0000_0000
        all_true ←0b0
    end
    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    if vxvc_flag=1 then SetFX(FPSCR.VXVC)
    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vxvc_flag)
end
if ex_flag=0 then VSR[32×TX+T] ←vresult
if Rc=1 then do
    if vex_flag=0 then
        CR.field[6] ←all_true || 0b0 || all_false || 0b0
    else
        CR.field[6] ←0bUUUU
end


VSX Vector Compare Greater or Equal Single-Precision (Record)

Summary: Compares each element of two single-precision floating-point vectors and sets the target vector elements to all 1s if the corresponding source elements are greater than or equal, otherwise all 0s.

For xvcmpgesp, each element of the single-precision floating-point vector in VSR[XA] is compared with the corresponding element in VSR[XB]. The result is stored in VSR[XT]. If Rc=1, CR field 6 is updated based on the comparison results.

if 'xvcmpgesp' then
    for each integer value i from 0 to 3 do
        src1 ← bfp_CONVERT_FROM_BFP32(VSR[32×AX+A].word[i])
        src2 ← bfp_CONVERT_FROM_BFP32(VSR[32×BX+B].word[i])
        if src1.class.SNaN | src2.class.SNaN then
            vxsnan_flag ← 0b1
            if FPSCR.VE=0 then vxvc_flag ← 0b1
        else vxvc_flag ← IsQNaN(src1) | IsQNaN(src2)
        if src1 >= src2 then
            vresult.word[i] ← 0xFFFF_FFFF
        else
            vresult.word[i] ← 0x0000_0000
        ex_flag ← ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vxvc_flag)
    end
    if ex_flag=0 then VSR[32×TX+T] ← vresult
    if Rc=1 then do
        CR.field[6] ← all_true || 0b0 || all_false || 0b0
    end


Vector Compare Equal Floating-Point (Record)

Summary: Compares the elements of two vector registers for equality and stores the result in a third vector register.

For vcmpeqfp, each element of VSR[VRA+32] is compared to the corresponding element of VSR[VRB+32]. If they are equal, the corresponding element of VSR[VRT+32] is set to all 1s; otherwise, it is set to all 0s.

if MSR.VEC=0 then
    Vector_Unavailable()
all_true ←1
all_false ←1
do i = 0 to 3
    src1 ←VSR[VRA+32].word[i]
    src2 ←VSR[VRB+32].word[i]
    if bool_COMPARE_EQ_BFP32(src1,src2)=1 then
        VSR[VRT+32].word[i] ←0xFFFF_FFFF
        all_false ←0
    else
        VSR[VRT+32].word[i] ←0x0000_0000
        all_true ←0
end
if Rc=1 then
    CR.field[6] ←all_true || 0b0 || all_false || 0b0


Vector Compare Greater Than Floating-Point (Record)

Summary: Compares the contents of two vector registers and sets the target vector register based on whether each element is greater than the corresponding element in the other vector.

For vcmpgtfp, the contents of VSR[VRA+32] are compared to the contents of VSR[VRB+32]. The result is stored in VSR[VRT+32], with each word set to all 1s if the corresponding element in VSR[VRA+32] is greater than that in VSR[VRB+32], and all 0s otherwise.

if MSR.VEC=0 then
    Vector_Unavailable()
all_true ←1
all_false ←1
do i = 0 to 3
    src1 ←VSR[VRA+32].word[i]
    src2 ←VSR[VRB+32].word[i]
    if bool_COMPARE_GT_BFP32(src1,src2)=1 then
        VSR[VRT+32].word[i] ←0xFFFF_FFFF
        all_false ←0
    else
        all_true ←0
        VSR[VRT+32].word[i] ←0x0000_0000
end
if Rc=1 then
    CR.field[6] ←all_true || 0b0 || all_false || 0b0


Vector Compare Bounds Floating-Point (Record)

Summary: Compares two VSRs word element by word and sets the target VSR if Rc=1.

Performs a bounds check comparing each of four 32-bit floating-point elements in VRA against the range defined by two bounds in VRB. The result is stored in VRT as a 4-bit value per element indicating which bound(s) the value violates. When the Rc bit is set (vcmpbfp.), the CR6 field is updated based on the result.

Each single-precision floating-point value in VSR[VRB+32] should be non-negative; if it is negative, the corresponding element in VSR[VRA+32] will necessarily be out of bounds. One exception to this is when the value of an element in VSR[VRB+32] is -0.0 and the value of the corresponding element in VSR[VRA+32] is either +0.0 or -0.0. +0.0 and -0.0 compare equal to -0.0.


Summary: Counts the number of consecutive 0 bits starting from bit 0 (MSB of 64-bit reg).

n ← 0
while n < 64 and RS[n] = 0 do n ← n + 1
RT ← n
if Rc = 1 then CR0 ← (RT = 0, RT < 0, RT > 0, SO)

Counts the number of consecutive zero bits from the MSB (bit 0) of the 64-bit doubleword in RS and stores the result in RT. The count ranges from 0 to 64. If Rc=1, CR0 is updated based on the result.

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.


Summary: Branches to the target address and sets the Link Register to the return address.

if AA then NIA <- EXTS(LI || 0b00)
else NIA <- CIA + EXTS(LI || 0b00)
if LK then LR <- CIA + 4

If LK=1 then the effective address of the instruction following the branch is placed into the Link Register. Used for subroutine calls.

The b instruction is used for unconditional branching. The AA and LK fields control whether the address is absolute or relative and whether to link back to the current instruction.


Summary: Branches to the target address if the specified condition is met.

Conditional branch - see bc for the full BO/BI semantics. AA selects absolute vs. relative addressing; LK selects whether the Link Register is set to the return address.

The bc instruction branches to a target address based on the condition bits in the Condition Register (CR). Ensure that the branch condition and target address are correctly set. The instruction operates at user privilege level, but care must be taken with conditional logic to avoid unintended execution paths.


Branch Conditional to Link Register (Link)

Summary: Branches to the address in the Link Register if the specified condition is met, and sets the Link Register to the return address.

Conditional branch to the Link Register (see bclr) with LK=1 -- the Link Register is set to the return address after the branch is taken.

bclr, bclrl, bcctr, and bcctrl each serve as both a basic and an extended mnemonic. The Assembler will recognize a bclr, bclrl, bcctr, or bcctrl mnemonic with three operands as the basic form, and a bclr, bclrl, bcctr, or bcctrl mnemonic with two operands as the extended form. In the extended form the BH operand is omitted and assumed to be 0b00.

Page 73-78 (verified, Appendix C Table C.2)


Summary: Adds the contents of two floating-point registers and places the result into another register.

if 'fadd' then
    FRT <- (FRA) + (FRB)
else if 'fadd.' then
    FRT <- (FRA) + (FRB)
    CR1 <- result class and sign

The floating-point operand in register FRA is added to the floating-point operand in register FRB. The result is rounded to the target precision under control of RN and placed into register FRT.


Summary: Multiplies the contents of two floating-point registers and places the result into another register.

if 'fmul' then
    FRT <- (FRA) * (FRC)
else if 'fmul.' then
    FRT <- (FRA) * (FRC)

The floating-point operand in register FRA is multiplied by the floating-point operand in register FRC. The result is rounded to the target precision under control of RN and placed into register FRT.


Summary: Performs (A * C) + B with a single rounding step. (The classic FMA).

FRT ←[(FRA)×(FRC)] + (FRB)
if 'fmadd.' then
    CR1 <- result class and sign

The instruction multiplies the contents of register FRA by the contents of register FRC, then adds the result to the contents of register FRB. The final result is placed into register FRT.


Floating Convert with round Double-Precision To Signed Word format (Record)

Summary: Converts a float to a 32-bit signed integer (using the current rounding mode) and stores it in the lower half of the FPR.

round_mode ← FPSCRRN
tgt_precision ← '32-bit signed integer'

sign ← (FRB)0
if (FRB)1:11 = 2047 and (FRB)12:63 = 0 then goto Infinity Operand
if (FRB)1:11 = 2047 and (FRB)12 = 0 then goto SNaN Operand
if (FRB)1:11 = 2047 and (FRB)12 = 1 then goto QNaN Operand
if (FRB)1:11 > 1086 then goto Large Operand

if (FRB)1:11 > 0 then exp ← (FRB)1:11 - 1023   /* exp - bias */
if (FRB)1:11 = 0 then exp ← -1022
if (FRB)1:11 > 0 then frac0:64 ← 0b01 || (FRB)12:63 || 110   /* normal */
if (FRB)1:11 = 0 then frac0:64 ← 0b00 || (FRB)12:63 || 110   /* denormal */

rbit || xbit ← 0b00
for i=1,63-exp    /* do the loop 0 times if exp = 63 */
    frac0:64 || rbit || xbit ← 0b0 || frac0:64 || (rbit | xbit)
end

FRT ← Round Integer(sign, frac0:64, gbit, rbit, xbit, round_mode)

The instruction converts the double-precision floating-point value in FRB to a signed word using the specified rounding mode. If the result is out of range, it saturates to the maximum or minimum signed integer value.

FPSCR, (FR, FI, FX, XX, VXSNAN, VXCVI), CR1, (if, Rc=1), CR0


Summary: Multiplies the contents of two DFP registers and places the result in another DFP register.

FPR[FRT] ← DFP_multiply(FPR[FRA], FPR[FRB])
FPSCR ← updated with exception flags
if Rc = 1 then CR0 ← condition_code(FPR[FRT])

Multiplies two 64-bit Decimal Floating Point (DFP) numbers held in FPRs and stores the result in another FPR. DFP multiplication preserves decimal precision required for financial calculations. The instruction can optionally update CR0 (via the dot form); FPSCR is always updated with exception flags and rounding information.

dmul[q][.] are treated as Floating-Point instructions in terms of resource availability.


Summary: Adjusts the exponent of a DFP number to match a reference. Critical for aligning decimal points before addition.

0 | FRT | FRA | FRB | RMC | Rc | 3 | 21 | 23

FPR[FRT] ← DFP_quantize(FPR[FRA], FPR[FRB], RMC)
FPSCR ← updated with exception flags
if Rc = 1 then CR0 ← condition_code(FPR[FRT])

Adjusts the exponent of a 64-bit DFP number to match a reference exponent, rounding the significand as needed according to the RMC control bits. This operation is essential for aligning decimal points before addition in financial calculations. The instruction can optionally update CR0 via the dot form; FPSCR is always updated with exception flags.

FPSCR, FPRF, FR, FI, FX, XX, VXSNAN, VXCVI, CR1

DFP Quantize can be used to adjust one DFP value to a form having the same exponent as another DFP value. If the adjustment requires the significand to be shifted left and would cause overflow from the most significant digit, the result is a default QNaN.


Summary: Compares each byte of two vector registers and sets the result register to all 1s if the bytes are not equal, otherwise all 0s.

For vcmpneb, each byte of VSR[VRA+32] is compared with the corresponding byte of VSR[VRB+32]. If they are not equal, the corresponding byte in VSR[VRT+32] is set to 0xFF; otherwise, it is set to 0x00.

if MSR.VEC=0 then
    Vector_Unavailable()
all_true ←1
all_false ←1
do i = 0 to 15
    src1 ←VSR[VRA+32].byte[i]
    src2 ←VSR[VRB+32].byte[i]
    if src1 != src2 then do
        VSR[VRT+32].byte[i] ←0xFF
        all_false ←0
    end
    else do
        VSR[VRT+32].byte[i] ←0x00
        all_true ←0
    end
end
if Rc=1 then
    CR.field[6] ←all_true || 0b0 || all_false || 0b0


Vector Compare Not Equal Halfword (Record)

Summary: Compares the contents of two vector registers and sets the result register to all 1s if the elements are not equal, otherwise all 0s.

For vcmpneh, each halfword element in VSR[VRA+32] is compared with the corresponding element in VSR[VRB+32]. If they are not equal, the corresponding element in VSR[VRT+32] is set to all 1s; otherwise, it is set to all 0s.

if MSR.VEC=0 then
    Vector_Unavailable()
all_true ←1
all_false ←1
do i = 0 to 7
    src1 ←VSR[VRA+32].hword[i]
    src2 ←VSR[VRB+32].hword[i]
    if src1 != src2 then do
        VSR[VRT+32].hword[i] ←0xFFFF
        all_false ←0
    end
    else do
        VSR[VRT+32].hword[i] ←0x0000
        all_true ←0
    end
end
if Rc=1 then
    CR.field[6] ←all_true || 0b0 || all_false || 0b0


Summary: Compares each word of two vector registers and sets the corresponding word in the target vector register to all 1s if the words are not equal, otherwise to all 0s.

For vcmpnew, each word of VSR[VRA+32] is compared with the corresponding word of VSR[VRB+32]. If they are not equal, the corresponding word in VSR[VRT+32] is set to 0xFFFF_FFFF; otherwise, it is set to 0x0000_0000.

if MSR.VEC=0 then
    Vector_Unavailable()
all_true ←1
all_false ←1
do i = 0 to 3
    src1 ←VSR[VRA+32].word[i]
    src2 ←VSR[VRB+32].word[i]
    if src1 != src2 then do
        VSR[VRT+32].word[i] ←0xFFFF_FFFF
        all_false ←0
    end
    else do
        VSR[VRT+32].word[i] ←0x0000_0000
        all_true ←0
    end
end
if Rc=1 then
    CR.field[6] ←all_true || 0b0 || all_false || 0b0


Vector String Isolate Byte Right (Record)

Summary: Isolates the rightmost non-zero byte in a vector string and shifts it to the left.

Isolates the rightmost non-zero byte in each 16-byte element of the source vector and shifts it to the leftmost position of the corresponding result element; all other bytes in the result are zeroed. When Rc=1, the instruction updates CR6 based on whether a zero vector was produced.

for i in 0 to 15:
  byte_value ← VRB[i*8:(i+1)*8]
  if byte_value ≠ 0 then
    VRT[i*8:(i+1)*8] ← byte_value
  else
    VRT[i*8:(i+1)*8] ← 0
if Rc = 1 then CR6 ← record_zero_vector(VRT)


Summary: Adds the contents of two registers and a carry bit, placing the result in a target register.

if 'addc' then
    RT <- (RA) + (RB)
else if 'addc.' then
    RT <- (RA) + (RB)
    if Rc=1 then update CR0
else if 'addco' then
    RT <- (RA) + (RB)
    if OE=1 then update XER[SO], XER[OV]
else if 'addco.' then
    RT <- (RA) + (RB)
    if Rc=1 then update CR0
    if OE=1 then update XER[SO], XER[OV]

The sum (RA) + (RB) is placed into register RT.


Summary: Subtracts the contents of register RA from register RB and places the result in RT.

The sum ¬(RA) + (RB) + 1 is placed into register RT. This is equivalent to RB - RA.

CR CR0 (if Rc=1); XER SO OV OV32 (if OE=1)

Page 110 (verified, corrected from addic's mis-scraped block)

The subf instruction subtracts the contents of register RA from register RB (RT = RB - RA); note the 'subtract from' operand order. Assemblers provide the extended mnemonic sub RT,RA,RB, implemented as subf RT,RB,RA. This instruction operates at user privilege level.


Summary: Adds the contents of a register and a constant minus one, with optional overflow exception.

The sum (RA) + CA - 1 is placed into register RT. The carry bit (CA) is used in the calculation.


Summary: Performs a bitwise AND operation on the contents of two registers and places the result into another register.

if 'and' then
    RT <- (RS) & (RB)
else if 'and.' then
    RT <- (RS) & (RB)

The contents of register RS are ANDed with the contents of register RB and the result is placed into register RA.

Some forms of and Rx, Rx, Rx provide special functions; see Section 11.3 of Book III.


Summary: Copies a float register (Pseudo: for FRB).

The contents of register FRB are placed into register FRT.

The fmr instruction is used to copy the contents of one floating-point register (FRB) to another (FRT). It does not alter any special registers unless Rc=1, in which case it updates CR1. Ensure that both source and destination registers are properly aligned for optimal performance.


Summary: Selects FRA if FRC >= 0, else FRB (Optional).

Selects between FRA and FRB based on the sign of FRC: if FRC ≥ 0, the result is FRA; otherwise, the result is FRB. The optional dot (.) form sets CR1 based on the result's FPRF. This is an optional category instruction.

if FRC ≥ 0.0 then
  FRT ← FRA
else
  FRT ← FRB
if Rc = 1 then CR1 ← FPRF(FRT)

Warning: Care must be taken in using fsel if IEEE compatibility is required, or if the values being tested can be NaNs or infinities.


Summary: Computes the square root of a floating-point number.

The square root of the floating-point operand in register FRB is placed into register FRT. If the most significant bit of the resultant significand is not 1, the result is normalized. The result is rounded to the target precision under control of RN and placed into register FRT.

if FRB < 0 then
    FRT ← QNaN
    if VE = 1 then raise VXSQRT exception
else
    FRT ← sqrt(FRB)
    if most significant bit of FRT's significand is not 1 then normalize FRT
    round FRT to target precision under control of RN
end if
FPSCR.FPRF ← class and sign of FRT
if VE = 1 and result is invalid operation exception then raise VXSQRT exception

The fsqrt instruction computes the square root of a floating-point number. It handles negative inputs by returning a quiet NaN (QNaN) and may raise an exception if enabled. Ensure the input is non-negative to avoid unexpected results. The result is normalized and rounded according to the current rounding mode, which can affect precision.


Summary: Performs a floating-point negative multiply-add operation.

The operation FRT ←- ( [(FRA)×(FRC)] + (FRB) ) is performed. The result is negated and placed into register FRT.

FRT ←- ( [(FRA)×(FRC)] + (FRB) )
if 'fnmadd.' then
    update CR1 and FPSCR fields

The fnmadd instruction is useful for performing a negated multiply-add operation on floating-point numbers. Ensure that the input registers FRA, FRC, and FRB are correctly aligned and contain valid floating-point values to avoid exceptions. If using the 'fnmadd.' form, be aware that it updates CR1 and FPSCR, which can affect subsequent conditional operations or exception handling.


Floating Round to Single-Precision (Record)

Summary: Rounds the contents of a floating-point register to single-precision.

The floating-point operand in register FRB is rounded to single-precision using the rounding mode specified by RN and placed into register FRT.

if (FRB)1:11 < 897 and (FRB)1:63 > 0 then
    if FPSCRUE = 0 then goto Disabled Exponent Underflow
    if FPSCRUE = 1 then goto Enabled Exponent Underflow
end

if (FRB)1:11 > 1150 and (FRB)1:11 < 2047 then
    if FPSCROE = 0 then goto Disabled Exponent Overflow
    if FPSCROE = 1 then goto Enabled Exponent Overflow
end

if (FRB)1:11 > 896 and (FRB)1:11 < 1151 then goto Normal Operand

if (FRB)1:63 = 0 then goto Zero Operand

if (FRB)1:11 = 2047 then
    if (FRB)12:63 = 0 then goto Infinity Operand
    if (FRB)12 = 1 then goto QNaN Operand
    if (FRB)12 = 0 and (FRB)13:63 > 0 then goto SNaN Operand
end

Disabled Exponent Underflow:
    sign ←(FRB)0
    if (FRB)1:11 = 0 then
        exp ←-1022
        frac0:52 ←0b0 || (FRB)12:63
    end
    if (FRB)1:11 > 0 then
        exp ←(FRB)1:11 -1023
        frac0:52 ←0b1 || (FRB)12:63
    end
    Denormalize operand:
        G || R || X ←0b000
        do while exp < -126
            exp ←exp + 1
            frac0:52 || G || R || X ←0b0 || frac0:52 || G || (R | X)
        end
    FPSCRUX ←(frac24:52 || G || R || X) > 0
    Round Single(sign,exp,frac0:52,G,R,X)
    FPSCRXX ←FPSCRXX | FPSCRFI

FPSCR (FPRF FR FI FX OX UX XX VXSNAN), CR1

The frsp instruction rounds a double-precision floating-point number to single precision. It handles various cases like underflow, overflow, and NaNs, setting appropriate flags in the FPSCR register. Ensure that the input register FRB is correctly set before calling this instruction.


Floating Convert with round Signed Doubleword to Double-Precision format (Record)

Summary: Converts a signed doubleword integer to a double-precision floating-point number.

The 64-bit signed fixed-point operand in register FRB is converted to an infinitely precise floating-point integer. The result of the conversion is rounded to double-precision, using the rounding mode specified by RN, and placed into register FRT.

if 'fcfid' then
    FRT <- (FRB) converted to double-precision floating-point integer
    round result using RN
    if Rc=1 then update CR1

Converting a signed integer word to double-precision floating-point can be accomplished by loading the word from storage using Load Float Word Algebraic Indexed and then using fcfid.


Floating Convert with round Signed Doubleword to Single-Precision format (Record)

Summary: Converts a 64-bit signed fixed-point operand in register FRB to single-precision floating-point.

The 64-bit signed fixed-point operand in register FRB is converted to an infinitely precise floating-point integer. The result of the conversion is rounded to single-precision, using the rounding mode specified by RN, and placed into register FRT.

FPSCR (FPRF, FR, FI, FX, XX), CR1 (if Rc=1)

Converting a signed integer word to single-precision floating-point can be accomplished by loading the word from storage using Load Float Word Algebraic and then using fcfids.

FRT ← ConvertToFloat(FRB, RN)
SetFlags(FPRF, FR, FI)


Summary: Compares each word of two vector registers and sets the corresponding word in the target register to all 1s if they are equal, otherwise all 0s.

if MSR.VEC=0 then Vector_Unavailable()

all_true ←1
all_false ←1
do i = 0 to 3
   src1 ←VSR[VRA+32].word[i]
   src2 ←VSR[VRB+32].word[i]
   if src1 = src2 then do
      VSR[VRT+32].word[i] ←0xFFFF_FFFF
      all_false ←0
   end
   else do
      VSR[VRT+32].word[i] ←0x0000_0000
      all_true ←0
   end
end
do i = 0 to 3
   src1 ←VSR[VRA+32].word[i]
   src2 ←VSR[VRB+32].word[i]
   if src1 = src2 then do
      VSR[VRT+32].word[i] ←0xFFFF_FFFF
      all_false ←0
   end
   else do
      VSR[VRT+32].word[i] ←0x0000_0000
      all_true ←0
   end
end
if Rc=1 then
   CR.field[6] ←all_true || 0b0 || all_false || 0b0

For vcmpequw, each word of VSR[VRA+32] is compared with the corresponding word of VSR[VRB+32]. If they are equal, the corresponding word in VSR[VRT+32] is set to 0xFFFF_FFFF; otherwise, it is set to 0x0000_0000.

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.


Summary: Divides the contents of two decimal floating-point registers and places the result in a target register.

The DFP operand in FRA is divided by the DFP operand in FRB. The result is rounded to the target-format precision under control of the DRN (bits 29:31 of the FPSCR). An appropriate form of the rounded result is selected based on the ideal exponent and is placed in FRT.

if 'ddiv' then
    FRT <- (FRA) / (FRB)
    if Rc=1 then
        CR1 <- result of comparison

The ddiv instruction performs a decimal division, rounding the result according to the precision control bits in FPSCR. Ensure that operands are properly aligned and check for division by zero or overflow conditions, which may trigger exceptions. The result can be compared if Rc is set, updating CR1 accordingly.


Summary: Rounds DFP Long (64-bit) to DFP Short (32-bit compressed).

The DFP long operand in FRB is converted and rounded to DFP short format. The DFP short value is extended on the left with zeros to form a 64-bit entity and placed into FRT. The sign of the result is the same as the sign of the source operand.

if 'drsp' then
    FRT <- (FRB) rounded to DFP short format
    if Rc=1 then
        CR0, CR1 <- updated based on result

Note that DFP short format is a storage-only format. Therefore, conversion of a long SNaN to short for mat will not cause an exception.


Summary: Converts a decimal floating-point number to a fixed-point integer.

The DFP operand in FRB is rounded to an integer value and placed into FRT in the 64-bit signed binary integer format. The sign of the result is the same as the sign of the source operand, except when the source operand is a NaN or a zero.

if 'dctfix' then
    FRT <- round(FRB)
else if 'dctfix.' then
    FRT <- round(FRB)
    CR1 <- result of comparison

FPSCR (FPRF, FR, FI, FX, VXSNAN, VXCVI, XX), CR1 (if Rc=1)

It is recommended that software pre-round the operand to a floating-point integral using drintx[q] or drintn[q] if a rounding mode other than the current rounding mode specified by DRN is needed.


Decode DPD To BCD (Single Precision) (Record)

Summary: Converts a portion of the significand of a DFP operand to a signed or unsigned BCD number.

The rightmost 16 digits of the significand (32 digits for ddedpdq) is converted to an unsigned BCD number and the result is placed into FRT[p].

if 'ddedpd' then
    if SP = 0 then
        FRT <- unsigned BCD conversion of rightmost 16 digits of FRB[p]
    else if SP = 1 then
        FRT <- signed BCD conversion of rightmost 15 digits of FRB[p] with the same sign as FRB[p]
    end if

FPSCR, (FPRF, FX, VXCVI), FPSCR, (FR, set, to, 0), CR1, (if, Rc=1), CR0


Summary: Extracts the biased exponent of a DFP operand in FRB and places it into FRT.

The biased exponent of the operand in FRB is extracted and placed into FRT in the 64-bit signed binary integer format. Special codes are returned for infinity, QNaN, or SNaN operands.

if 'dxex' then
    a <- biased exponent of FRB[p]
    if a > MBE1 then
        FRT[p] <- QNaNSNaN
    else if 0 ≤a ≤MBE then
        FRT[p] <- Finite number with biased exponent a
    else if a = -1 then
        FRT[p] <- Infinity
    else if a = -2 then
        FRT[p] <- QNaN
    else if a = -3 then
        FRT[p] <- SNaN
    else if a < -3 then
        FRT[p] <- QNaN

The exponent bias value is 101 for DFP Short, 398 for DFP Long, and 6176 for DFP Extended.


Floating Round to Integer Nearest (Record)

Summary: Rounds the floating-point operand in register FRB to an integral value using the rounding mode round to nearest.

The floating-point operand in register FRB is rounded to an integral value as follows, with the result placed into register FRT. If the sign of the operand is positive, (FRB) + 0.5 is truncated to an integral value, otherwise (FRB) - 0.5 is truncated to an integral value.

if 'frin' then
    if (FRB) >= 0 then
        FRT <- truncate((FRB) + 0.5)
    else
        FRT <- truncate((FRB) - 0.5)

FPSCR, (FPRF, FX, VXSNAN), FPSCR, (FR, FI), CR1, (if, Rc=1), CR0

These instructions set FR and FI to 0b00 regardless of whether the result is inexact or rounded because there is a desire to preserve the value of XX.


Decimal Floating-Point Round To FP Integer With Inexact (Record)

Summary: Rounds a decimal floating-point number to the nearest integer and places it into a floating-point register.

The DFP operand in FRB is rounded to a floating-point integer and placed into FRT. The sign of the result is the same as the sign of the operand in FRB. The ideal exponent is the larger value of zero and the exponent of the operand in FRB. The rounding mode used is specified by RMC.

if 'drintx' then
    FRT <- round(FRB, RMC)
    if result differs from FRB then
        raise inexact exception

FPSCR, (FPRF, FR, FI, FX, XX), VXSNAN, CR1, (if, Rc=1), CR0


Decimal Floating-Point Round To FP Integer Without Inexact (Record)

Summary: Rounds a decimal floating-point number to an integer without recognizing an inexact exception.

This operation rounds the value in FRB to an integer using the specified rounding mode (RMC) and places the result in FRT. It does not recognize an inexact exception.

if 'drintn' then
    FRT <- Round(FRB, RMC)
    FI <- 0
    FR <- 0
    VXSNAN <- 0
    if Rc=1 then
        CR1 <- ClassAndSign(FRT)
else if 'drintn.' then
    FRT <- Round(FRB, RMC)
    FI <- 0
    FR <- 0
    VXSNAN <- 0
    CR1 <- ClassAndSign(FRT)

FPSCR, (FPRF, FX, VXSNAN), FPSCR, (FR, FI), CR1, CR0

The DFP Round To FP Integer Without Inexact and DFP Round To FP Integer Without Inexact Quad instructions can be used to implement decimal equivalents of several C99 rounding functions by specifying the appropriate R and RMC field values.


Rotate Left Doubleword then Clear Right (Record)

Summary: Rotates the contents of register RS left by a variable number of bits specified by (RB)58:63, and clears the rightmost bits.

The contents of register RS are rotated 64 bits to the left by the number of bits specified by (RB)58:63. A mask is generated having 1-bits from bit 0 through bit ME and 0-bits elsewhere. The rotated data are ANDed with the generated mask, and the result is placed into register RA.

if 'rldcr' then
    n ← (RB)58:63
    r ← ROTL64((RS), n)
    ME ← me5 || me0:4
    m ← MASK(0, ME)
    RA ← r & m
if 'rldcr.' then
    CR0 <- updated based on result

rldcr can be used to extract an n-bit field that starts at variable bit position b in register RS, left-justified RA), by setting RB58:63=b and ME=n-1. It can also be used to rotate the contents of a register left (right) by variable n bits, by setting RB58:63=n (64-n) and ME=63.


Summary: Rounds a floating-point operand towards +infinity and places the result into a register.

The floating-point operand in register FRB is rounded to an integral value using the rounding mode round toward +infinity, and the result is placed into register FRT. FPRF is set to the class and sign of the result, except for Invalid Operation Exceptions when VE=1.

if 'frip' then
    FRT <- round_towards_plus_infinity(FRB)
else if 'frip.' then
    FRT <- round_towards_plus_infinity(FRB)
    update_CR1_based_on_result(FRT)


Summary: Compares two quadwords and sets the result to all ones if they are equal, otherwise all zeros.

Compares each quadword element of VRA with the corresponding quadword element of VRB for equality; the result for each quadword is all ones if equal or all zeros if not equal. If the Rc bit is set, CR6 is updated with summary information. Requires VMX support.

for i in 0 to 1 do
  if VRA[i*128:(i+1)*128-1] = VRB[i*128:(i+1)*128-1] then
    VRT[i*128:(i+1)*128-1] ← 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
  else
    VRT[i*128:(i+1)*128-1] ← 0x00000000000000000000000000000000
  end if
end for
if Rc then
  CR6 ← summary of results
end if


Vector Compare Greater Than Signed Quadword (Record)

Summary: Compares two signed quadwords and sets the result based on whether the first is greater than the second.

For vcmpgtsq, the contents of VSR[VRA+32] (src1) are compared to the contents of VSR[VRB+32] (src2). If src1 > src2, VSR[VRT+32] is set to all 1s; otherwise, it is set to all 0s. If Rc=1, CR field 6 is updated.

if MSR.VEC=0 then
    Vector_Unavailable()
all_true ←1
all_false ←1
src1 ←EXTS(VSR[VRA+32])
src2 ←EXTS(VSR[VRB+32])
if src1 > src2 then do
    VSR[VRT+32] ← 0xFFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF
    all_false ←0
end else do
    VSR[VRT+32] ← 0x0000_0000_0000_0000_0000_0000_0000_0000
    all_true ←0
end
if Rc=1 then
    CR.field[6] ←all_true || 0b0 || all_false || 0b0


Vector String Isolate Halfword Right-justified (Record)

Summary: Isolates the rightmost non-zero halfword in a vector string.

From right to left, the contents of each halfword element of VSR[VRB+32] are placed into the corresponding halfword element in VSR[VRT+32]. If a halfword element in VSR[VRB+32] is found to contain 0, the corresponding halfword element and all halfword elements to the left of that halfword element in VSR[VRT+32] are set to 0.

if MSR.VEC=0 then
    Vector_Unavailable()
null_found ← 0
while (!null_found) do i = 0 to 7
    null_found ← (VSR[VRB+32].hword[7-i] = 0)
    VSR[VRT+32].hword[7-i] ← VSR[VRB+32].hword[7-i]
end
do j = i to 7
    VSR[VRT+32].hword[7-j] ← 0
end
if Rc=1 then
    CR.field[6] ← 0b00 || null_found || 0b0


VSX Scalar Multiply-Subtract Quad-Precision (Overflow)

Summary: Performs a multiply-subtract operation on quad-precision floating-point values.

Performs a scalar multiply-subtract operation on quad-precision floating-point values, computing VRT = VRT - (VRA × VRB). The result is rounded according to the current rounding mode in FPSCR. This instruction requires VSX support and updates FPSCR exception flags based on the operation result.

VRT[0:127] ← VRT[0:127] - (VRA[0:127] × VRB[0:127])
FPSCR ← update_exception_flags(FPSCR, result)

The xsmsubqp instruction is used for performing a multiply-subtract operation on quad-precision floating-point numbers. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid an exception. Be cautious of rounding modes and exceptions, as they can affect the result and set flags in the FPSCR register. This instruction operates on 128-bit aligned data in vector registers VSR[VRA+32], VSR[VRT+32], and VSR[VRB+32].


VSX Scalar Negative Multiply-Add Quad-Precision (Overflow)

Summary: Performs a negative multiply-add operation on quad-precision floating-point values.

Performs a scalar negative multiply-add operation on quad-precision floating-point values, computing VRT = -(VRA × VRB) + VRT. The result is rounded according to the current rounding mode in FPSCR. This instruction requires VSX support and updates FPSCR exception flags based on the operation result.

VRT[0:127] ← -(VRA[0:127] × VRB[0:127]) + VRT[0:127]
FPSCR ← update_exception_flags(FPSCR, result)

FPSCR FPRF FR FI FX VXSNAN VXIMZ VXISI OX UX XX

This instruction is used for performing a scalar negative multiply-add operation on quad-precision floating-point numbers. Ensure that the VSX feature is enabled in the MSR register to avoid exceptions. Be cautious of potential overflow and underflow conditions, as indicated by the OX and UX flags in the FPSCR register. The result is rounded according to the rounding mode specified in FPSCR.RN.


Summary: Computes vd = vs2 & ~vs1 (bitwise AND with inverted source).

foreach(i < vl): vd[i] = vs2[i] & ~vs1[i];

Performs element-wise AND with inverted source (vs2 op ~vs1), writing results to vd.


Summary: Rotates bits in elements of vs2 left by amounts in vs1.

Rotates each vector element left by the corresponding shift amount.


Summary: Rotates bits in elements of vs2 right by amounts in vs1.

Rotates each vector element right by the corresponding shift amount.


Summary: Rotates bits in elements of vs2 left by scalar rs1.

foreach(i < vl): vd[i] = rotate_left(vs2[i], rs1);


Summary: Rotates bits in elements of vs2 right by scalar rs1.

foreach(i < vl): vd[i] = rotate_right(vs2[i], rs1);


Summary: Reverses the bits within each byte of the source elements.

foreach(i < vl): vd[i] = reverse_bits_in_bytes(vs2[i]);

Reverses the bit or byte order within each vector element.


Summary: Reverses the order of bytes within each element (Endian swap).


Summary: Counts the number of leading zero bits in each element.

foreach(i < vl): vd[i] = count_leading_zeros(vs2[i]);

Counts the number of leading zero bits in each active vector element, writing counts to vd.


Summary: Counts the number of trailing zero bits in each element.

foreach(i < vl): vd[i] = count_trailing_zeros(vs2[i]);

Counts the number of trailing zero bits in each active vector element, writing counts to vd.


Summary: Counts the number of set bits (1s) in each element.

foreach(i < vl): vd[i] = count_set_bits(vs2[i]);

Counts the number of set bits in mask register vs2 that are active (within vl), writing the count to scalar rd.


Summary: Shifts N-bit elements left to produce 2*N-bit results.

foreach(i < vl): vd[i] = zext(vs2[i]) << vs1[i];

Performs a widening operation, producing results twice as wide as the source elements. Results are written to vd using 2× the element grouping (EEW). The number of elements and masking are governed by vl and vm.


Summary: Performs the final AES decryption round.

Performs a vectorised AES cryptographic round operation. Each element group undergoes one step of the cipher algorithm in parallel. See the Zvk vector crypto extension for full semantic details.


Summary: Performs a middle AES decryption round.


Summary: Performs the final AES encryption round.


Summary: Performs a middle AES encryption round.


Summary: Generates the next round key for AES (Step 1).


Summary: Generates the next round key for AES (Step 2).


Summary: Performs SHA-256 compression (high 128 bits).

vd = SHA256_Compress_High(vd, vs1, vs2);

Performs a vectorised SHA cryptographic round operation. Each element group undergoes one step of the cipher algorithm in parallel. See the Zvk vector crypto extension for full semantic details.


Summary: Performs SHA-256 compression (low 128 bits).


Summary: Generates SHA-256 message schedule words.


Summary: Performs GHASH multiply-add for AES-GCM.

Performs a vectorised GHASH cryptographic round operation. Each element group undergoes one step of the cipher algorithm in parallel. See the Zvk vector crypto extension for full semantic details.


Summary: Performs carry-less multiplication on vector elements (GF(2^n)).

foreach(i < vl): vd[i] = clmul(vs1[i], vs2[i]);

Performs carry-less multiplication of vector elements (GF(2^n)), used in GHASH for GCM mode and CRC computation.


Summary: Performs carry-less multiplication, keeping the high half.

foreach(i < vl): vd[i] = clmulh(vs1[i], vs2[i]);


Summary: Counts set bits in the source mask register.


Summary: Finds the index of the first set bit in the mask.

Finds the index of the lowest-numbered active set bit in mask register vs2, writing the index to rd. Returns -1 if no bit is set.


Summary: Sets mask bits before the first set bit in the source mask.

Sets each destination mask bit to 1 for elements before the first active set bit in vs2.


Summary: Sets mask bits up to and including the first set bit in the source.

Set 1s up to and including the first 1 in vs2.

Sets each destination mask bit to 1 for elements up to and including the first active set bit in vs2.


Summary: Sets only the first set bit from the source mask.

Sets only the destination mask bit corresponding to the first active set bit in vs2.


Summary: Computes vd = vs2 & ~rs1.


Vector Widening Shift Left Logical Scalar

Summary: Shifts elements left by scalar rs1, widening the result.

foreach(i < vl): vd[i] = zext(vs2[i]) << rs1;


Vector Widening Shift Left Logical Immediate

Summary: Shifts elements left by immediate, widening the result.

foreach(i < vl): vd[i] = zext(vs2[i]) << imm;


Summary: Take the branch if rs1 is less than rs2 (unsigned comparison).

if (R[rs1] <u R[rs2]) PC += sext(offset);

BLTU takes the branch if rs1 is less than rs2, treating both as unsigned integers. The branch target is the PC plus the sign-extended B-immediate.


Summary: Take the branch if rs1 is greater than or equal to rs2 (unsigned comparison).

if (R[rs1] >=u R[rs2]) PC += sext(offset);

BGEU takes the branch if rs1 is greater than or equal to rs2, treating both as unsigned integers. The branch target is the PC plus the sign-extended B-immediate.


Summary: Moves the bit pattern of a 64-bit floating-point register to an integer register (RV64).

Moves bits from a floating-point register to an integer register (or vice versa) without conversion. The bit pattern is preserved exactly.


Summary: Moves the bit pattern of a 64-bit integer register to a floating-point register (RV64).


Summary: Injects the XOR of signs of rs1 and rs2 (Double Precision).

Produces a result with the magnitude of rs1 and the sign bit taken from the source rs2. Used to implement floating-point absolute value, negate, and copy-sign.


Summary: Performs no operation (Compressed encoding).

No operation. Equivalent to C.ADDI x0, 0.


Summary: Adds a signed immediate to a register (32-bit result sign-extended, RV64).

Adds a 6-bit sign-extended immediate to rd (RV64/RV128 only), truncates to 32 bits, sign-extends to 64 bits.


Summary: Adds two registers (32-bit result sign-extended, RV64).

Adds rd and rs2 (16-bit), sign-extends the 32-bit result to 64 bits (RV64/RV128 only).


Summary: Subtracts two registers (32-bit result sign-extended, RV64).

Subtracts rs2′ from rd′, truncates to 32 bits, sign-extends to 64 bits (RV64).


Compressed Load Doubleword from Stack Pointer

Summary: Loads a 64-bit value from the stack pointer (RV64).

? | 011 | c_uimm9sphi | rd_n0 | c_uimm9splo | 10

Loads a 64-bit doubleword from a stack-pointer-relative address into rd (RV64).


Compressed Store Doubleword to Stack Pointer

Summary: Stores a 64-bit value to the stack pointer (RV64).

Stores a 64-bit doubleword from rs2 to a stack-pointer-relative address (RV64).


Compressed Float Load Word from Stack Pointer

Summary: Loads a single-precision float from the stack pointer.

? | 011 | c_uimm8sphi | rd | c_uimm8splo | 10

Loads a single-precision FP value from a stack-pointer-relative address into fd (RV32 only).


Compressed Float Store Word to Stack Pointer

Summary: Stores a single-precision float to the stack pointer.

Stores a single-precision FP value from fd to a stack-pointer-relative address (RV32 only).


Compressed Float Load Double from Stack Pointer

Summary: Loads a double-precision float from the stack pointer.

? | 001 | c_uimm9sphi | rd | c_uimm9splo | 10

Loads a double-precision FP value from a stack-pointer-relative address into fd.


Compressed Float Store Double to Stack Pointer

Summary: Stores a double-precision float to the stack pointer.

Stores a double-precision FP value from fd to a stack-pointer-relative address.


Summary: Subtracts elements of two vector registers.

foreach(i < vl): vd[i] = vs1[i] - vs2[i];

Performs element-wise integer subtraction on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Subtracts vector elements from a scalar value (scalar - vector).

Performs element-wise reverse integer subtraction on a vector and a scalar register, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Computes the signed minimum of elements in two vectors.

foreach(i < vl): vd[i] = min(vs1[i], vs2[i]);

Performs element-wise signed minimum on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Computes the signed maximum of elements in two vectors.

foreach(i < vl): vd[i] = max(vs1[i], vs2[i]);

Performs element-wise signed maximum on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Computes the unsigned minimum of elements in two vectors.

foreach(i < vl): vd[i] = min_u(vs1[i], vs2[i]);

Performs element-wise unsigned minimum on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Computes the unsigned maximum of elements in two vectors.

foreach(i < vl): vd[i] = max_u(vs1[i], vs2[i]);

Performs element-wise unsigned maximum on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Performs bitwise OR on elements of two vectors.

foreach(i < vl): vd[i] = vs1[i] | vs2[i];

Performs element-wise bitwise OR on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Performs bitwise XOR on elements of two vectors.

foreach(i < vl): vd[i] = vs1[i] ^ vs2[i];

Performs element-wise bitwise XOR on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Shifts elements of vector vs2 left by amounts in vs1.

foreach(i < vl): vd[i] = vs2[i] << (vs1[i] & Mask);

Performs element-wise left logical shift on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Shifts elements of vector vs2 right (logical) by amounts in vs1.

foreach(i < vl): vd[i] = vs2[i] >> (vs1[i] & Mask);

Performs element-wise right logical shift on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Shifts elements of vector vs2 right (arithmetic) by amounts in vs1.

foreach(i < vl): vd[i] = vs2[i] >>s (vs1[i] & Mask);

Performs element-wise right arithmetic shift on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Sets destination mask bit if elements are equal.

Compares elements element-wise for equal and writes a mask result to vd.


Summary: Sets destination mask bit if vs2 < vs1 (signed).

Compares elements element-wise for less than and writes a mask result to vd.


Summary: Sets destination mask bit if vs2 < vs1 (unsigned).


Summary: Reduces a vector to a scalar by summing all elements.

Performs a vector reduction: applies the operation across all active elements of vs2, using vs1[0] as the initial accumulator, and writes the scalar result to vd[0]. Active elements are determined by vl.


Summary: Loads elements from memory with a fixed stride.

foreach(i < vl): vd[i] = M[rs1 + i * rs2];

Performs a vector strided load of 32-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.


Summary: Stores elements to memory with a fixed stride.

foreach(i < vl): M[rs1 + i * rs2] = vs3[i];

Performs a vector strided store of 32-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.


Vector Load Unordered Indexed (32-bit indices)

Summary: Loads elements from memory using a vector of indices (Gather).

foreach(i < vl): vd[i] = M[rs1 + vs2[i]];

Performs a vector indexed unordered load of 32-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.


Vector Store Unordered Indexed (32-bit indices)

Summary: Stores elements to memory using a vector of indices (Scatter).

foreach(i < vl): M[rs1 + vs2[i]] = vs3[i];

Performs a vector indexed unordered store of 32-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.


Summary: Moves elements up by a scalar amount (vd[i] = vs2[i - rs1]).

foreach(i): if i < rs1: vd[i] = vd[i] (unchanged); else: vd[i] = vs2[i - rs1];

Slides vector elements up by the specified offset, filling vacated positions with zero or the value from vs1[0].


Summary: Moves elements down by a scalar amount (vd[i] = vs2[i + rs1]).

Slides vector elements down by the specified offset, filling vacated positions with zero or the value from vs1[0].


Summary: Performs bitwise NAND on vector mask registers. Used to invert masks (NOT).

Performs element-wise mask NAND on the mask registers vm1 and vm2, writing to vd.


Summary: Reads the old value of the CSR, then clears bits in the CSR based on the mask in rs1.

t = CSRs[csr]; CSRs[csr] = t & ~R[rs1]; R[rd] = t;

CSRRC atomically reads CSR csr into rd, then clears the bits in the CSR that correspond to bits set in rs1. If rs1 is x0, no bits are modified.


Summary: Updates a CSR using a 5-bit unsigned immediate (zimm) instead of a register.

t = CSRs[csr]; CSRs[csr] = zext(uimm); R[rd] = t;

CSRRWI atomically reads CSR csr into rd, then writes the zero-extended 5-bit immediate to the CSR. If rd is x0, the read is skipped.


Summary: Sets bits in a CSR using a 5-bit unsigned immediate.

t = CSRs[csr]; CSRs[csr] = t | zext(uimm); R[rd] = t;

CSRRSI atomically reads CSR csr into rd, then sets bits in the CSR corresponding to set bits in the zero-extended 5-bit immediate. If the immediate is zero, no bits are modified.


Summary: Clears bits in a CSR using a 5-bit unsigned immediate.

t = CSRs[csr]; CSRs[csr] = t & ~zext(uimm); R[rd] = t;

CSRRCI atomically reads CSR csr into rd, then clears bits in the CSR corresponding to set bits in the zero-extended 5-bit immediate. If the immediate is zero, no bits are modified.


Summary: Loads a 64-bit double-precision floating-point value from memory.

Loads a 64-bit doubleword from memory at address rs1+sext(offset) into floating-point register rd.


Summary: Stores a 64-bit double-precision floating-point value to memory.

Stores a floating-point register to memory at address rs1+sext(offset).


Summary: Performs double-precision floating-point addition.

Performs double-precision (64-bit) floating-point addition. The operation adds the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.


Summary: Performs double-precision floating-point subtraction.

Performs double-precision (64-bit) floating-point subtraction. The operation subtracts the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.


Summary: Performs double-precision floating-point multiplication.

Performs double-precision (64-bit) floating-point multiplication. The operation multiplies the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.


Summary: Performs double-precision floating-point division.

Performs double-precision (64-bit) floating-point division. The operation divides the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.


Summary: Atomically performs bitwise OR on a word in memory.

temp = M[R[rs1]]; M[R[rs1]] = temp | R[rs2]; R[rd] = temp;

AMOOR.W atomically loads a word from the address in rs1 into rd, ORs it with rs2, and stores the result back.


Summary: Atomically performs bitwise XOR on a word in memory.

temp = M[R[rs1]]; M[R[rs1]] = temp ^ R[rs2]; R[rd] = temp;

AMOXOR.W atomically loads a word, XORs it with rs2, and stores the result back.


Summary: Atomically updates memory with the maximum of the memory value and register value (Signed).

temp = M[R[rs1]]; M[R[rs1]] = max(temp, R[rs2]); R[rd] = temp;

AMOMAX.W atomically loads a word, writes the signed maximum of the loaded value and rs2 back to memory, and returns the original value in rd.


Summary: Atomically updates memory with the minimum of the memory value and register value (Signed).

temp = M[R[rs1]]; M[R[rs1]] = min(temp, R[rs2]); R[rd] = temp;

AMOMIN.W atomically computes the signed minimum of a memory word and rs2, stores the result, and returns the original in rd.


Summary: Returns from a user-mode trap handler (requires N extension).

URET returns from a user-level trap (N extension). It restores PC from uepc and restores interrupt-enable state.


Summary: Loads a vector of 8-bit elements from memory.

Performs a vector unit-stride load of 8-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.


Summary: Loads a vector of 16-bit elements from memory.

Performs a vector unit-stride load of 16-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.


Summary: Loads a vector of 64-bit elements from memory.

Performs a vector unit-stride load of 64-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.


Summary: Stores a vector of 8-bit elements to memory.

Performs a vector unit-stride store of 8-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.


Summary: Stores a vector of 16-bit elements to memory.

Performs a vector unit-stride store of 16-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.


Summary: Stores a vector of 64-bit elements to memory.

Performs a vector unit-stride store of 64-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.


Summary: Moves a single vector register to another, ignoring VL and VTYPE (used for spilling).

vd = vs2; // Copies entire register content

Copies 1 vector register(s) from vs2 to vd, independent of vtype or vl. No masking.


Summary: Moves 2 consecutive vector registers, ignoring VL and VTYPE.

Copies 2 vector register(s) from vs2 to vd, independent of vtype or vl. No masking.


Summary: Moves 4 consecutive vector registers, ignoring VL and VTYPE.

Copies 4 vector register(s) from vs2 to vd, independent of vtype or vl. No masking.


Summary: Moves 8 consecutive vector registers, ignoring VL and VTYPE.

Copies 8 vector register(s) from vs2 to vd, independent of vtype or vl. No masking.


Summary: Sets vector length (VL) and type (VTYPE) using a 5-bit immediate for the requested length.

vl = set_config(uimm, vtypei); R[rd] = vl;

Sets the vector length (vl) and vector type (vtype) registers based on the requested application vector length (AVL) and element width/grouping. The actual vector length set is written to rd. vtype encodes SEW (element width), LMUL (register grouping), and tail/mask policies.


Summary: Loads a vector mask register from memory.

Performs a vector mask register load of element-sized-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.


Summary: Stores a vector mask register to memory.

Performs a vector mask register store of element-sized-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.


Summary: Atomically updates memory with the minimum of the memory value and register value (Unsigned 64-bit).

temp = M[R[rs1]]; M[R[rs1]] = min_u(temp, R[rs2]); R[rd] = temp;

AMOMINU.D performs an atomic unsigned minimum doubleword operation (RV64 only).


Summary: Atomically updates memory with the maximum of the memory value and register value (Unsigned 64-bit).

temp = M[R[rs1]]; M[R[rs1]] = max_u(temp, R[rs2]); R[rd] = temp;

AMOMAXU.D performs an atomic unsigned maximum doubleword operation (RV64 only).


Summary: Computes (rs1 * rs2) - rs3 with a single rounding.

Performs single-precision (32-bit) floating-point fused multiply-subtract. The operation computes fused multiply-subtract on the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.


Float Negated Fused Multiply-Add (Single)

Summary: Computes -(rs1 * rs2) - rs3 with a single rounding.

Performs single-precision (32-bit) floating-point fused negate-multiply-add. The operation computes fused negate-multiply-add on the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.


Float Negated Fused Multiply-Subtract (Single)

Summary: Computes -(rs1 * rs2) + rs3 with a single rounding.

Performs single-precision (32-bit) floating-point fused negate-multiply-subtract. The operation computes fused negate-multiply-subtract on the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.


Summary: Computes the square root of a double-precision floating-point number.

Stores a floating-point register to memory at address rs1+sext(offset).


Summary: Writes the smaller of two double-precision floating-point values to rd.

Returns the double-precision (64-bit) floating-point minimum of rs1 and rs2, following IEEE 754-2019 minNum/maxNum semantics. Quiet NaN inputs return the non-NaN operand; signalling NaN inputs raise invalid-operation.


Summary: Writes the larger of two double-precision floating-point values to rd.

Returns the double-precision (64-bit) floating-point maximum of rs1 and rs2, following IEEE 754-2019 minNum/maxNum semantics. Quiet NaN inputs return the non-NaN operand; signalling NaN inputs raise invalid-operation.


Summary: Computes (rs1 * rs2) - rs3 with a single rounding (Double).

Performs double-precision (64-bit) floating-point fused multiply-subtract. The operation computes fused multiply-subtract on the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.


Float Negated Fused Multiply-Add (Double)

Summary: Computes -(rs1 * rs2) - rs3 with a single rounding (Double).

Performs double-precision (64-bit) floating-point fused negate-multiply-add. The operation computes fused negate-multiply-add on the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.


Float Negated Fused Multiply-Subtract (Double)

Summary: Computes -(rs1 * rs2) + rs3 with a single rounding (Double).

Performs double-precision (64-bit) floating-point fused negate-multiply-subtract. The operation computes fused negate-multiply-subtract on the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.


Summary: Converts a double-precision float to a 32-bit unsigned integer.

Converts between floating-point types or between floating-point and integer. Result is rounded according to the dynamic rounding mode. Invalid conversions produce the IEEE default NaN or the appropriate integer saturation value.


Summary: Converts a 32-bit unsigned integer to a double-precision float.


Summary: Loads a single-precision float from memory (Compressed).

? | 011 | c_uimm7hi | rs1_p | c_uimm7lo | rd_p | 00

Loads a single-precision FP value from memory into fd′ (RV32 only).


Summary: Stores a single-precision float to memory (Compressed).

? | 111 | c_uimm7hi | rs1_p | c_uimm7lo | rs2_p | 00

Stores a single-precision FP value from fd′ to memory (RV32 only).


Summary: Loads a 64-bit value from memory (Compressed, RV64).

? | 011 | c_uimm8hi | rs1_p | c_uimm8lo | rd_p | 00

Loads a 64-bit doubleword from memory at an 8-bit unsigned offset from rs1′ into rd′ (RV64).


Summary: Stores a 64-bit value to memory (Compressed, RV64).

? | 111 | c_uimm8hi | rs1_p | c_uimm8lo | rs2_p | 00

Stores a 64-bit doubleword from rs2′ to memory at an 8-bit offset from rs1′ (RV64).


Summary: Adds elements of two vector registers (Floating Point).

foreach(i < vl): vd[i] = vs1[i] + vs2[i];

Performs element-wise floating-point addition on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Gathers elements from a vector register using indices from another vector register.

foreach(i < vl): vd[i] = (vs1[i] >= vlmax) ? 0 : vs2[vs1[i]];

Gathers elements from vs2 using indices in vs1 (or an immediate), writing to vd. Out-of-range indices produce zero.


Summary: Performs bitwise AND on vector mask registers.

Performs element-wise mask AND on the mask registers vm1 and vm2, writing to vd.


Summary: Atomically adds a value to a 64-bit doubleword in memory.

temp = M[R[rs1]]; M[R[rs1]] = temp + R[rs2]; R[rd] = temp;

AMOADD.D atomically loads a doubleword from the address in rs1 into rd, adds rs2, and stores the result back (RV64 only).


Summary: Atomically swaps a 64-bit value in memory with a register.

temp = M[R[rs1]]; M[R[rs1]] = R[rs2]; R[rd] = temp;

AMOSWAP.D atomically loads a doubleword, writes it to rd, and stores rs2 to that address (RV64 only).


Summary: Atomically performs bitwise AND on a 64-bit doubleword in memory.

temp = M[R[rs1]]; M[R[rs1]] = temp & R[rs2]; R[rd] = temp;

AMOAND.D atomically loads a doubleword, ANDs with rs2, and stores the result back (RV64 only).


Summary: Atomically performs bitwise OR on a 64-bit doubleword in memory.

AMOOR.D atomically loads a doubleword, ORs with rs2, and stores the result back (RV64 only).


Summary: Atomically performs bitwise XOR on a 64-bit doubleword in memory.

AMOXOR.D atomically loads a doubleword, XORs with rs2, and stores the result back (RV64 only).


Summary: Atomically updates memory with the maximum of the memory value and register value (64-bit Signed).

AMOMAX.D performs an atomic signed maximum doubleword operation (RV64 only).


Summary: Atomically updates memory with the minimum of the memory value and register value (64-bit Signed).

AMOMIN.D performs an atomic signed minimum doubleword operation (RV64 only).


Summary: Conditionally stores a 64-bit value to memory if the reservation is valid.

if (ReservationValid) { M[R[rs1]] = R[rs2]; R[rd] = 0; } else { R[rd] = 1; }

SC.D conditionally stores the doubleword in rs2 to the address in rs1, only if the reservation set by LR.D is still valid (RV64 only). It writes 0 to rd on success and a non-zero value on failure.


Summary: Computes (rs1 * rs2) + rs3 with a single rounding.

Performs single-precision (32-bit) floating-point fused multiply-add. The operation computes fused multiply-add on the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.


Summary: Computes (rs1 * rs2) + rs3 with a single rounding (64-bit).

Performs double-precision (64-bit) floating-point fused multiply-add. The operation computes fused multiply-add on the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.


Summary: Subtracts rs2 from rs1.

SUB subtracts the value in rs2 from rs1 and writes the result to rd. Arithmetic overflow is ignored; the result is the low XLEN bits of the mathematical difference.


Summary: Sets rd to 1 if rs1 < rs2 (unsigned comparison), otherwise 0.

SLTU performs an unsigned comparison of rs1 and rs2, writing 1 to rd if rs1 < rs2 (unsigned), and 0 otherwise. Note: SLTU rd, x0, rs2 sets rd to 1 if rs2 is non-zero (assembler pseudoinstruction SNEZ).


Summary: Sets rd to 1 if rs1 < immediate (unsigned comparison), otherwise 0.

SLTIU compares rs1 against the sign-extended immediate treating both as unsigned integers, writing 1 to rd if rs1 < imm (unsigned), else 0. SLTIU rd, rs1, 1 implements SEQZ (set if equal to zero).


Summary: Generates an environment call exception (system call).

ECALL makes a service request to the execution environment. It generates an environment-call exception, whose handling depends on the privilege level (U, S, or M).


Summary: Performs unsigned multiplication and returns the upper XLEN bits.

MULHU multiplies rs1 and rs2 as unsigned values and writes the upper XLEN bits of the product to rd.


Summary: Multiplies signed rs1 by unsigned rs2 and returns the upper XLEN bits.

R[rd] = (sext(R[rs1]) * zext(R[rs2])) >> XLEN;

MULHSU multiplies rs1 (signed) by rs2 (unsigned) and writes the upper XLEN bits of the product to rd.


Summary: Computes the unsigned remainder of division.

REMU computes the unsigned remainder of rs1 ÷ rs2, writing the result to rd. Remainder by zero yields the dividend.


Summary: Atomically updates memory with the minimum of the memory value and register value (Unsigned).

AMOMINU.W atomically computes the unsigned minimum of a memory word and rs2, stores the result, and returns the original in rd.


Summary: Atomically updates memory with the maximum of the memory value and register value (Unsigned).

AMOMAXU.W atomically computes the unsigned maximum of a memory word and rs2, stores the result, and returns the original in rd.


Summary: Performs single-precision floating-point subtraction.

Performs single-precision (32-bit) floating-point subtraction. The operation subtracts the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.


Summary: Performs single-precision floating-point multiplication.

Performs single-precision (32-bit) floating-point multiplication. The operation multiplies the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.


Summary: Performs single-precision floating-point division.

Performs single-precision (32-bit) floating-point division. The operation divides the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.


Summary: Computes the square root of a single-precision floating-point number.

Stores a floating-point register to memory at address rs1+sext(offset).


Summary: Writes the smaller of two single-precision floating-point values to rd.

Returns the single-precision (32-bit) floating-point minimum of rs1 and rs2, following IEEE 754-2019 minNum/maxNum semantics. Quiet NaN inputs return the non-NaN operand; signalling NaN inputs raise invalid-operation.


Summary: Writes the larger of two single-precision floating-point values to rd.

Returns the single-precision (32-bit) floating-point maximum of rs1 and rs2, following IEEE 754-2019 minNum/maxNum semantics. Quiet NaN inputs return the non-NaN operand; signalling NaN inputs raise invalid-operation.


Summary: Reads the value of a CSR into a register.

CSRR is an assembler pseudoinstruction for CSRRS rd, csr, x0. It reads the CSR into rd without modifying it.


Summary: Writes a register value to a CSR.

CSRW is an assembler pseudoinstruction for CSRRW x0, csr, rs1. It writes rs1 to the CSR without reading it.


Summary: Sets bits in a CSR (bitwise OR).

CSRS is an assembler pseudoinstruction for CSRRS x0, csr, rs1. It sets bits in the CSR based on rs1 without reading.


Summary: Clears bits in a CSR (bitwise AND NOT).

CSRC is an assembler pseudoinstruction for CSRRC x0, csr, rs1. It clears bits in the CSR based on rs1 without reading.


Summary: Converts a double-precision float to a 64-bit unsigned integer.

Converts between floating-point types or between floating-point and integer. Result is rounded according to the dynamic rounding mode. Invalid conversions produce the IEEE default NaN or the appropriate integer saturation value.


Summary: Loads a 16-bit half-precision float from memory.

Loads a 16-bit halfword from memory at address rs1+sext(offset) into floating-point register rd.


Summary: Stores a 16-bit half-precision float to memory.


Summary: Performs 16-bit floating-point addition.

Performs half-precision (16-bit) floating-point addition. The operation adds the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.


Summary: Converts a 16-bit half-precision float to a 32-bit single-precision float.


Summary: Converts a 32-bit single-precision float to a 16-bit half-precision float.


Summary: Subtracts the lower 32 bits of rs2 from rs1 and sign-extends the result to 64 bits.

SUBW subtracts rs2 from rs1, truncates to 32 bits, sign-extends to 64 bits, and writes to rd.


Summary: Performs a 32-bit logical left shift on rs1 by the amount in rs2 (lower 5 bits), sign-extending the result.

SLLW performs a logical left shift of the lower 32 bits of rs1 by the shift amount in the lower 5 bits of rs2, sign-extends the 32-bit result to 64 bits, and writes to rd.


Summary: Performs a 32-bit logical right shift on rs1 by the amount in rs2, sign-extending the result.

SRLW performs a logical right shift of the lower 32 bits of rs1 by the shift amount in the lower 5 bits of rs2, sign-extends the 32-bit result to 64 bits, and writes to rd.


Summary: Performs a 32-bit arithmetic right shift on rs1, sign-extending the result.

SRAW performs an arithmetic right shift of the lower 32 bits of rs1 by the shift amount in the lower 5 bits of rs2, sign-extends the 32-bit result to 64 bits, and writes to rd.


Summary: Shifts the lower 32 bits of rs1 left by a constant, sign-extending the result.

SLLIW performs a logical left shift of the lower 32 bits of rs1 by the 5-bit immediate, sign-extends the 32-bit result to 64 bits, and writes it to rd.


Summary: Logically shifts the lower 32 bits of rs1 right by a constant, sign-extending the result.

SRLIW performs a logical right shift of the lower 32 bits of rs1 by the 5-bit immediate, sign-extends the 32-bit result to 64 bits, and writes it to rd.


Summary: Arithmetically shifts the lower 32 bits of rs1 right by a constant, sign-extending the result.

SRAIW performs an arithmetic right shift of the lower 32 bits of rs1 by the 5-bit immediate, sign-extends the 32-bit result to 64 bits, and writes it to rd.


Summary: Performs 32-bit multiplication of rs1 and rs2, sign-extending the 32-bit result to 64 bits.

MULW multiplies the lower 32 bits of rs1 and rs2, sign-extends the lower 32 bits of the product to 64 bits, and writes to rd (RV64 only).


Summary: Performs 32-bit signed division of rs1 by rs2, sign-extending the result.

DIVW performs signed 32-bit division of the lower 32 bits of rs1 by rs2, sign-extends the quotient to 64 bits, and writes to rd (RV64 only). Division by zero yields -1.


Summary: Performs 32-bit unsigned division of rs1 by rs2, sign-extending the result.

DIVUW performs unsigned 32-bit division of the lower 32 bits of rs1 by rs2, zero-extends the quotient to 64 bits, and writes to rd (RV64 only). Division by zero yields 2^32 - 1.


Summary: Computes the remainder of 32-bit signed division, sign-extending the result.

REMW computes the signed 32-bit remainder of rs1 ÷ rs2, sign-extends to 64 bits, and writes to rd (RV64 only).


Summary: Computes the remainder of 32-bit unsigned division, sign-extending the result.

REMUW computes the unsigned 32-bit remainder of rs1 ÷ rs2, zero-extends to 64 bits, and writes to rd (RV64 only).


Summary: Synchronizes the instruction cache with the data cache (used after self-modifying code).

Flushes I-Cache; ensures previous writes are visible to instruction fetch.

FENCE.I synchronises the instruction and data streams. It ensures that any stores to instruction memory visible to the current hart are made visible to subsequent instruction fetches by that hart.


Summary: Loads a byte from Guest Physical Memory (VS-stage translation only).

HLV.B performs a virtual-machine load of a byte from the address in rs1, using the virtual supervisor address space (VS-mode translation). The result is sign-extended and written to rd.


Summary: Loads a word from Guest Physical Memory (VS-stage translation only).

HLV.W performs a virtual-machine load of a word using VS-mode translation. In RV64 the result is sign-extended.


Summary: Stores a byte to Guest Physical Memory.

HSV.B stores the least-significant byte of rs2 to the VS-mode virtual address in rs1.


Summary: Stores a word to Guest Physical Memory.

HSV.W stores the least-significant word of rs2 to the VS-mode virtual address in rs1.


Summary: Hints to hardware to bring the cache block containing the instruction at the address into the instruction cache.

PREFETCH.I is a hint to the memory system to prefetch the cache block at the address rs1+offset into the instruction cache.


Summary: Hints to hardware to bring the cache block at the address into the data cache for reading.

Prefetch(D-Cache, Read, R[rs1] + offset);

Prepare D-Cache for reading next cache line.

PREFETCH.R is a hint to the memory system to prefetch the cache block at rs1+offset into the data cache for a read access.


Summary: Hints to hardware to bring the cache block at the address into the data cache for writing (exclusive ownership).

Prefetch(D-Cache, Write, R[rs1] + offset);

PREFETCH.W is a hint to the memory system to prefetch the cache block at rs1+offset into the data cache for a write access.


Summary: Returns from Debug Mode to the mode defined in the 'dcsr' register.

DRET returns from debug mode. It restores PC from dpc and restores the privilege mode recorded before entering debug mode.


Summary: Configures the vector length (vl) and vector type (vtype) based on application needs.

vl = set_config(rs1, vtypei); R[rd] = vl;

Request VL=a0, 32-bit elements, 1 register group.

Sets the vector length (vl) and vector type (vtype) registers based on the requested application vector length (AVL) and element width/grouping. The actual vector length set is written to rd. vtype encodes SEW (element width), LMUL (register grouping), and tail/mask policies.


Summary: Loads a vector of 32-bit elements from memory into a vector register.

foreach(i < vl): vd[i] = Mem[rs1 + i*4];

Load 32-bit integers from address in a0 to v8.

Performs a vector unit-stride load of 32-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.


Summary: Stores a vector of 32-bit elements from a vector register to memory.

foreach(i < vl): Mem[rs1 + i*4] = vs3[i];

Performs a vector unit-stride store of 32-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.


Summary: Adds elements of two vector registers.

Performs element-wise integer addition on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Multiplies elements of two vector registers.

foreach(i < vl): vd[i] = vs1[i] * vs2[i];

Performs element-wise integer multiplication (low bits) on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.


Summary: Counts the number of 0 bits at the MSB end of the register.

int count = 0; while(rs1[XLEN-1-count] == 0) count++; R[rd] = count;

CLZ counts the number of leading (most-significant) zero bits in rs1, writing the count to rd. Returns XLEN if rs1 is zero.


Summary: Counts the number of 0 bits at the LSB end of the register.

int count = 0; while(rs1[count] == 0) count++; R[rd] = count;

CTZ counts the number of trailing (least-significant) zero bits in rs1, writing the count to rd. Returns XLEN if rs1 is zero.


Summary: Counts the number of set bits (1s) in the register.

CPOP counts the number of set bits (population count / Hamming weight) in rs1 and writes the count to rd.


Summary: Performs bitwise AND with the bitwise negation of rs2 (rs1 & ~rs2).

ANDN computes the bitwise AND of rs1 with the bitwise NOT of rs2, writing the result to rd. Equivalent to rd = rs1 & ~rs2.


Summary: Performs bitwise OR with the bitwise negation of rs2 (rs1 | ~rs2).

ORN computes the bitwise OR of rs1 with the bitwise NOT of rs2. Equivalent to rd = rs1 | ~rs2.


Summary: Performs bitwise exclusive-NOR (rs1 ^ ~rs2).

XNOR computes the bitwise XNOR of rs1 and rs2. Equivalent to rd = ~(rs1 ^ rs2).


Summary: Rotates the bits in rs1 left by the amount in rs2.

shamt = R[rs2] & (XLEN-1); R[rd] = (R[rs1] << shamt) | (R[rs1] >> (XLEN-shamt));

ROL rotates rs1 left by the shift amount in the lower log2(XLEN) bits of rs2, writing the result to rd.


Summary: Rotates the bits in rs1 right by the amount in rs2.

shamt = R[rs2] & (XLEN-1); R[rd] = (R[rs1] >> shamt) | (R[rs1] << (XLEN-shamt));

ROR rotates rs1 right by the shift amount in the lower log2(XLEN) bits of rs2, writing the result to rd.


Summary: Computes the signed maximum of two registers.

MAX computes the signed maximum of rs1 and rs2, writing the result to rd.


Summary: Computes the signed minimum of two registers.

MIN computes the signed minimum of rs1 and rs2, writing the result to rd.


Summary: Sign-extends the lowest byte (8 bits) to XLEN bits.

SEXT.B sign-extends the least-significant byte of rs1 to XLEN bits.


Summary: Sign-extends the lowest halfword (16 bits) to XLEN bits.

SEXT.H sign-extends the least-significant halfword of rs1 to XLEN bits.


Summary: Zero-extends the lowest halfword (16 bits) to XLEN bits.

ZEXT.H zero-extends the least-significant halfword of rs1 to XLEN bits, writing to rd.


Summary: Sets each byte of the result to 0xFF if the corresponding byte of the source is non-zero, else 0x00.

For each byte i: R[rd].byte[i] = (R[rs1].byte[i] != 0) ? 0xFF : 0x00;

Used for string processing (strlen, strcpy).

ORC.B sets each byte of rd to 0xFF if the corresponding byte of rs1 is non-zero, or 0x00 if it is zero. Useful for detecting null bytes in strings.


Summary: Reverses the order of bytes in a register (Endian swap).

REV8 reverses the byte order of rs1 (byte-swap / endianness conversion), writing the result to rd.