Summary: Bitwise compare of 128-bit value (AND) setting flags.

Performs a bitwise AND of the 128-bit source operand with the 128-bit destination operand and sets EFLAGS based on the result, without modifying the destination. Sets ZF if the AND result is all zeros, sets CF if the AND of the source with the bitwise NOT of the destination is all zeros. Does not update OF, SF, AF, or PF. Available only in SSE4.1 and later; operates on 128-bit XMM registers.


Summary: Performs one round of AES encryption flow.

src

128-bit XMM SIMD register or Memory operand

Performs a single round of AES encryption on the 128-bit state in the destination XMM register using the round key in the source operand. The operation includes SubBytes, ShiftRows, MixColumns, and AddRoundKey transformations. Does not modify EFLAGS. Requires the AES-NI instruction set extension; operates on 128-bit XMM registers or memory.

dest[127:0] ← AES_EncryptionRound(dest[127:0], src[127:0]);
OF ← 0; CF ← 0; ZF ← 0; SF ← 0; AF ← 0; PF ← 0;


Summary: Performs the last round of AES encryption.

Performs the final round of AES encryption on the 128-bit state in the destination XMM register using the round key in the source operand. The final round excludes the MixColumns transformation compared to aesenc. Does not modify EFLAGS. Requires the AES-NI instruction set extension; operates on 128-bit XMM registers or memory.

dest[127:0] ← AES_EncryptionLastRound(dest[127:0], src[127:0]);
OF ← 0; CF ← 0; ZF ← 0; SF ← 0; AF ← 0; PF ← 0;


Summary: Performs one round of AES decryption flow.

Performs a single round of AES decryption on the 128-bit state in the destination XMM register using the round key in the source operand. The operation includes InvSubBytes, InvShiftRows, InvMixColumns, and AddRoundKey transformations. Does not modify EFLAGS. Requires the AES-NI instruction set extension; operates on 128-bit XMM registers or memory.

dest[127:0] ← AES_DecryptionRound(dest[127:0], src[127:0]);
OF ← 0; CF ← 0; ZF ← 0; SF ← 0; AF ← 0; PF ← 0;


Summary: Generates round key for AES encryption.

Generates a round key for AES encryption by performing key schedule computation on the 128-bit source operand and an immediate byte, storing the result in the destination XMM register. Used to facilitate AES key expansion during encryption key setup. Does not modify EFLAGS. Requires the AES-NI instruction set extension; operates on 128-bit XMM registers or memory with an 8-bit immediate.

dest[127:0] ← AES_KeyGenAssist(src[127:0], imm8);
OF ← 0; CF ← 0; ZF ← 0; SF ← 0; AF ← 0; PF ← 0;


Summary: Adds packed floats (256-bit YMM support).

256-bit YMM AVX register or Memory operand

Adds four packed single-precision floating-point values from the source operand to the corresponding values in the first source operand and stores the result in the destination YMM register. Floating-point exceptions and rounding mode are controlled by MXCSR. Does not modify EFLAGS. Requires AVX and is available in 64-bit mode; operates on 256-bit YMM registers or memory with three-operand form.


Summary: Multiplies packed floats (256-bit).

Multiplies four packed single-precision floating-point values from the source operand by the corresponding values in the first source operand and stores the result in the destination YMM register. Floating-point exceptions and rounding mode are controlled by MXCSR. Does not modify EFLAGS. Requires AVX and is available in 64-bit mode; operates on 256-bit YMM registers or memory with three-operand form.


Summary: Computes (Dest * Src2) + Src1.

Performs a fused multiply-add operation: multiplies the destination operand by the third operand and adds the result to the second operand, storing the result in the destination YMM register. The 231 variant computes (dest * src2) + src1 in a single operation with one rounding step, improving precision over separate multiply and add. Does not modify EFLAGS. Requires FMA3 and is available in 64-bit mode; operates on 256-bit YMM registers or memory.


Summary: Inserts 128-bits into a YMM register.

Inserts a 128-bit float vector into a 256-bit YMM register at either the lower or upper 128-bit lane, with the remaining lane copied from the first source operand. This is a non-destructive three-operand instruction where the immediate byte (bits 0-7) selects the destination lane (0=lower, 1=upper). No flags are affected; this is purely a data movement and lane selection operation.


Summary: Extracts 128-bits from YMM register.

Extracts a 128-bit float vector from a 256-bit YMM register based on an immediate selector and stores it to an XMM register or 128-bit memory location. The immediate byte (bit 0) selects which 128-bit lane to extract (0=lower, 1=upper). No flags are affected; this is a data extraction and movement operation only.


Summary: Clears bits 128-255 of all YMM registers (Avoids AVX-SSE transition penalty).

Clears bits 128-255 of all 16 YMM registers (YMM0-YMM15 in 64-bit mode, YMM0-YMM7 in 32-bit mode), leaving bits 0-127 unchanged. This eliminates the AVX-to-SSE transition penalty by ensuring the upper 128-bit portions are zero before executing SSE instructions. No flags are affected. This instruction must be executed in protected or 64-bit mode.


Summary: Clears all YMM registers.

Clears all bits of all 16 YMM registers (YMM0-YMM15 in 64-bit mode, YMM0-YMM7 in 32-bit mode) to zero. This is a faster alternative to clearing individual YMM registers via multiple VXORPS or similar instructions. No flags are affected. Execution is restricted to protected or 64-bit mode.


Summary: Clears the FPU tag word to allow FP instructions after MMX.

Sets all tag bits in the x87 FPU tag word to 1 (all entries marked empty), allowing the x87 FPU to be used immediately after MMX instructions without a transition penalty. This instruction clears the MMX state and must be executed before mixing MMX and x87 floating-point operations. No general-purpose flags are affected, but internal x87 state is modified.


Summary: Moves 32 bits between GPR and XMM/MMX register.

dest

64-bit MMX register or 128-bit XMM SIMD register

src

General-purpose register or Memory operand

Moves a 32-bit value from a general-purpose register or memory location into the lower 32 bits of an MMX or XMM register, zero-extending or copying the upper bits depending on context. When destination is MMX, the upper 32 bits become undefined; when destination is XMM, the upper 96 bits are zeroed (for SSE2 and later). No flags are affected. Supported in MMX and SSE2 extensions.


Summary: Moves 64 bits between XMM registers or memory.

Moves a 64-bit quadword between XMM registers or from/to 64-bit memory. When the source is memory, only the lower 64 bits of the destination XMM register are updated and the upper 64 bits are zeroed. When both operands are XMM registers, all 128 bits of the destination are affected (lower 64 from source, upper 64 zeroed). No flags are affected. This instruction is part of SSE2 and later.


Summary: Moves 128-bit packed float data (Must be 16-byte aligned).

Moves 128 bits of packed single-precision floating-point data between XMM registers or between an XMM register and 16-byte aligned memory. The memory operand must be 16-byte aligned; unaligned memory access results in a general-protection exception (#GP). This is a cache-efficient operation for aligned data. No flags are affected. Supported in SSE and later extensions.


Summary: Moves 128-bit packed float data (Unaligned).

Moves 128 bits of unaligned packed single-precision floating-point data from source to destination XMM register. No alignment requirement on memory operand. Does not affect any flags; operates only on XMM state.


Summary: Moves 128-bit packed double data (Must be 16-byte aligned).

Moves 128 bits of aligned packed double-precision floating-point data from source to destination XMM register. Memory operand must be 16-byte aligned; unaligned access generates #GP(0). Does not affect any flags; operates only on XMM state.


Summary: Moves 128-bit packed double data (Unaligned).

Moves 128 bits of unaligned packed double-precision floating-point data from source to destination XMM register. No alignment requirement on memory operand. Does not affect any flags; operates only on XMM state.


Summary: Moves 128-bit integer data (Aligned).

Moves 128 bits of aligned packed integer data from source to destination XMM register. Memory operand must be 16-byte aligned; unaligned access generates #GP(0). Does not affect any flags; operates only on XMM state.


Summary: Moves 128-bit integer data (Unaligned).

Moves 128 bits of unaligned packed integer data from source to destination XMM register. No alignment requirement on memory operand. Does not affect any flags; operates only on XMM state.


Summary: Adds four 32-bit floats.

Adds four 32-bit single-precision floating-point values element-wise from source to destination XMM register, storing results in destination. Each element addition produces IEEE 754 floating-point result; does not affect integer flags. Available in 128-bit (XMM) form.


Summary: Adds two 64-bit doubles.

Adds two 64-bit double-precision floating-point values element-wise from source to destination XMM register, storing results in destination. Each element addition produces IEEE 754 floating-point result; does not affect integer flags. Available in 128-bit (XMM) form.


Summary: Adds the low 32-bit float.

Adds the low 32-bit single-precision floating-point values from source to destination XMM register; upper three 32-bit elements of destination are unchanged. Scalar operation on lowest element; does not affect integer flags. Result follows IEEE 754 floating-point semantics.


Summary: Adds the low 64-bit double.

Adds the low 64-bit double-precision floating-point value in the source operand to the low 64-bit double-precision value in the destination XMM register, storing the result in the destination. The high 64 bits of the destination remain unchanged. This instruction operates on scalar (single) values and respects IEEE 754 rounding modes controlled by MXCSR.


Summary: Subtracts four 32-bit floats.

Subtracts four 32-bit single-precision floating-point values in the source operand from the four 32-bit single-precision values in the destination XMM register, storing all four results in the destination. Operates on packed values in parallel and respects IEEE 754 rounding modes controlled by MXCSR.


Summary: Subtracts two 64-bit doubles.

Subtracts two 64-bit double-precision floating-point values in the source operand from the two 64-bit double-precision values in the destination XMM register, storing both results in the destination. Operates on packed values in parallel and respects IEEE 754 rounding modes controlled by MXCSR.


Summary: Multiplies four 32-bit floats.

Multiplies four 32-bit single-precision floating-point values in the source operand by the four 32-bit single-precision values in the destination XMM register, storing all four products in the destination. Operates on packed values in parallel and respects IEEE 754 rounding modes controlled by MXCSR.


Summary: Multiplies two 64-bit doubles.

Multiplies two 64-bit double-precision floating-point values in the source operand by the two 64-bit double-precision values in the destination XMM register, storing both products in the destination. Operates on packed values in parallel and respects IEEE 754 rounding modes controlled by MXCSR.


Summary: Divides four 32-bit floats.

Divides four 32-bit single-precision floating-point values in the destination XMM register by the four 32-bit single-precision values in the source operand, storing all four quotients in the destination. Operates on packed values in parallel and respects IEEE 754 rounding modes controlled by MXCSR; division by zero produces infinity or NaN according to IEEE 754 rules.


Summary: Divides two 64-bit doubles.

Divides two 64-bit double-precision floating-point values in the destination XMM register by the two 64-bit double-precision values in the source operand, storing both quotients in the destination. Operates on packed values in parallel and respects IEEE 754 rounding modes controlled by MXCSR; division by zero produces infinity or NaN according to IEEE 754 rules.


Summary: Computes square root of four 32-bit floats.

Computes the square root of four 32-bit single-precision floating-point values in the source operand and stores all four results in the destination XMM register. Operates on packed values in parallel and respects IEEE 754 rounding modes controlled by MXCSR; negative values produce NaN according to IEEE 754 rules.


Summary: Computes square root of two 64-bit doubles.

Computes the square root of two packed 64-bit double-precision floating-point values and stores the results in the destination XMM register. This instruction operates at the FPU execution unit and sets MXCSR exception flags according to IEEE 754 rounding mode and precision; no general-purpose flags are affected. Requires SSE2 support.

dest[0:63] ← sqrt(src[0:63])
dest[64:127] ← sqrt(src[64:127])
MXCSR exception flags ← updated based on IEEE 754 result


Summary: Approximate reciprocal (1/x) of four 32-bit floats.

Computes the approximate reciprocal (1/x) of four packed 32-bit single-precision floating-point values with a relative error of at most 1.5×2⁻¹² and stores results in the destination XMM register. This is a fast approximation instruction suitable for iterative refinement; no general-purpose flags are affected. Requires SSE support.

dest[0:31] ← approx_reciprocal(src[0:31])
dest[32:63] ← approx_reciprocal(src[32:63])
dest[64:95] ← approx_reciprocal(src[64:95])
dest[96:127] ← approx_reciprocal(src[96:127])


Reciprocal Square Root Packed Single-Precision

Summary: Approximate reciprocal sqrt (1/sqrt(x)) of four 32-bit floats.

Computes the approximate reciprocal square root (1/√x) of four packed 32-bit single-precision floating-point values with a relative error of at most 1.5×2⁻¹² and stores results in the destination XMM register. This is a fast approximation instruction useful for physics simulations and graphics; no general-purpose flags are affected. Requires SSE support.

dest[0:31] ← approx_reciprocal_sqrt(src[0:31])
dest[32:63] ← approx_reciprocal_sqrt(src[32:63])
dest[64:95] ← approx_reciprocal_sqrt(src[64:95])
dest[96:127] ← approx_reciprocal_sqrt(src[96:127])


Summary: Returns maximum of packed floats.

Compares four packed 32-bit single-precision floating-point values element-wise and stores the maximum of each pair in the destination XMM register. Special values (NaN, signed zeros) follow IEEE 754 comparison semantics; no general-purpose flags are affected. Requires SSE support.


Summary: Returns minimum of packed floats.

Compares four packed 32-bit single-precision floating-point values element-wise and stores the minimum of each pair in the destination XMM register. Special values (NaN, signed zeros) follow IEEE 754 comparison semantics; no general-purpose flags are affected. Requires SSE support.


Bitwise Logical AND Packed Single-Precision

Summary: Bitwise AND of 128 bits.

Performs a bitwise logical AND of all 128 bits in the destination and source XMM registers and stores the result in the destination. This is a pure logical operation treating the packed single-precision floats as integer bit patterns; no general-purpose flags are affected. Requires SSE support.


Bitwise Logical AND Packed Double-Precision

Summary: Bitwise AND of 128 bits.

Performs a bitwise logical AND of all 128 bits in the destination and source XMM registers and stores the result in the destination. This is a pure logical operation treating the packed double-precision floats as integer bit patterns; no general-purpose flags are affected. Requires SSE2 support.


Bitwise Logical OR Packed Single-Precision

Summary: Bitwise OR of 128 bits.

Performs a bitwise logical OR of all 128 bits in the destination and source XMM registers and stores the result in the destination. This is a pure logical operation treating the packed single-precision floats as integer bit patterns; no general-purpose flags are affected. Requires SSE support.


Bitwise Logical XOR Packed Single-Precision

Summary: Bitwise XOR of 128 bits (Used to clear registers).

Performs a bitwise XOR of two 128-bit packed single-precision floating-point values, storing the result in the destination XMM register. No flags are affected by this operation. This instruction is commonly used to zero XMM registers efficiently (xorps xmm0, xmm0) as a dependency-breaking micro-optimization.


Summary: Adds 16 bytes (Wraparound).

Performs 16 independent 8-bit unsigned or signed integer additions in parallel on packed byte data, wrapping on overflow without affecting flags. Results are stored in the destination XMM register with no saturation; overflow is silent and wraps modulo 256.


Summary: Adds 8 words (Wraparound).

Performs 8 independent 16-bit unsigned or signed integer additions in parallel on packed word data, wrapping on overflow without affecting flags. Results are stored in the destination XMM register with no saturation; overflow wraps modulo 65536.


Summary: Adds 4 doublewords (Wraparound).

Performs 4 independent 32-bit unsigned or signed integer additions in parallel on packed doubleword data, wrapping on overflow without affecting flags. Results are stored in the destination XMM register with no saturation; overflow wraps modulo 2^32.


Summary: Adds 2 quadwords (Wraparound).

Performs 2 independent 64-bit unsigned or signed integer additions in parallel on packed quadword data, wrapping on overflow without affecting flags. Results are stored in the destination XMM register with no saturation; overflow wraps modulo 2^64.

for i = 0 to 1:
  dest[i*64 + 63 : i*64] ← (dest[i*64 + 63 : i*64] + src[i*64 + 63 : i*64]) AND 0xFFFFFFFFFFFFFFFF


Summary: Adds 16 signed bytes with saturation.

Performs 16 independent 8-bit signed integer additions in parallel with signed saturation on packed byte data. If the result overflows or underflows the signed 8-bit range [-128, 127], the value is clamped to the nearest boundary; no flags are affected.

for i = 0 to 15:
  temp ← (int32)(int8)dest[i*8 + 7 : i*8] + (int32)(int8)src[i*8 + 7 : i*8]
  if temp > 127: dest[i*8 + 7 : i*8] ← 127
  else if temp < -128: dest[i*8 + 7 : i*8] ← -128
  else: dest[i*8 + 7 : i*8] ← temp AND 0xFF


Summary: Adds 16 unsigned bytes with saturation.

Performs 16 independent 8-bit unsigned integer additions in parallel with unsigned saturation on packed byte data. If the result exceeds 255, the value is clamped to 255; no flags are affected.

for i = 0 to 15:
  temp ← (uint16)dest[i*8 + 7 : i*8] + (uint16)src[i*8 + 7 : i*8]
  if temp > 255: dest[i*8 + 7 : i*8] ← 255
  else: dest[i*8 + 7 : i*8] ← temp AND 0xFF


Summary: Subtracts 16 bytes.

Performs 16 independent 8-bit unsigned or signed integer subtractions in parallel on packed byte data, wrapping on underflow without affecting flags. Results are stored in the destination XMM register with no saturation; underflow wraps modulo 256.


Summary: Subtracts 8 words.

Subtracts packed 16-bit words element-wise: each of the 8 words in the destination XMM register is decremented by the corresponding word in the source XMM register or 128-bit memory operand, with wrapping on underflow. No flags are affected; the operation is performed modulo 2^16 for each element.

for i = 0 to 7 do
  dest.word[i] ← (dest.word[i] - src.word[i]) mod 2^16
end for


Summary: Subtracts 4 doublewords.

Subtracts packed 32-bit doublewords element-wise: each of the 4 doublewords in the destination XMM register is decremented by the corresponding doubleword in the source XMM register or 128-bit memory operand, with wrapping on underflow. No flags are affected; the operation is performed modulo 2^32 for each element.

for i = 0 to 3 do
  dest.dword[i] ← (dest.dword[i] - src.dword[i]) mod 2^32
end for


Summary: Bitwise AND of 128-bit integers.

Performs a bitwise logical AND operation on the entire 128-bit content of the destination XMM register with the source XMM register or 128-bit memory operand, storing the result back in the destination. No flags are affected; the operation is a pure bitwise AND with no carry or borrow semantics.


Summary: Bitwise OR of 128-bit integers.

Performs a bitwise logical OR operation on the entire 128-bit content of the destination XMM register with the source XMM register or 128-bit memory operand, storing the result back in the destination. No flags are affected; the operation is a pure bitwise OR with no carry or borrow semantics.


Summary: Bitwise XOR of 128-bit integers.

Performs a bitwise logical exclusive OR operation on the entire 128-bit content of the destination XMM register with the source XMM register or 128-bit memory operand, storing the result back in the destination. No flags are affected; the operation is a pure bitwise XOR with no carry or borrow semantics.


Summary: Shifts words left.

Shifts each of the 8 packed 16-bit words in the destination XMM register left logically by the number of bits specified in the 8-bit immediate operand, with zero fill on the right. Shift amounts greater than or equal to 16 zero out the corresponding word. No flags are affected.

count ← imm8 AND 0xFF
for i = 0 to 7 do
  if count >= 16 then
    dest.word[i] ← 0
  else
    dest.word[i] ← (dest.word[i] << count) AND 0xFFFF
  end if
end for


Summary: Shifts doublewords left.

Shifts each of the 4 packed 32-bit doublewords in the destination XMM register left logically by the number of bits specified in the 8-bit immediate operand, with zero fill on the right. Shift amounts greater than or equal to 32 zero out the corresponding doubleword. No flags are affected.

count ← imm8 AND 0xFF
for i = 0 to 3 do
  if count >= 32 then
    dest.dword[i] ← 0
  else
    dest.dword[i] ← (dest.dword[i] << count) AND 0xFFFFFFFF
  end if
end for


Summary: Shifts words right logical.

Shifts each of the 8 packed 16-bit words in the destination XMM register right logically (unsigned) by the number of bits specified in the 8-bit immediate operand, with zero fill on the left. Shift amounts greater than or equal to 16 zero out the corresponding word. No flags are affected.

count ← imm8 AND 0xFF
for i = 0 to 7 do
  if count >= 16 then
    dest.word[i] ← 0
  else
    dest.word[i] ← (dest.word[i] >> count) AND 0xFFFF
  end if
end for


Summary: Shifts doublewords right logical.

Shifts each 32-bit doubleword element in the XMM register right logically by the count specified in the immediate value. Bits shifted out are discarded, and vacated positions are filled with zeros. No flags are affected. Available in SSE2 and later; operates on 128-bit packed data (four 32-bit elements).

for i ← 0 to 3 do
  xmm.dword[i] ← xmm.dword[i] >> imm8
end for


Summary: Shifts words right arithmetic (sign bit).

Shifts each 16-bit word element in the XMM register right arithmetically by the count specified in the immediate value. The sign bit is replicated into vacated positions. No flags are affected. Available in SSE2 and later; operates on 128-bit packed data (eight 16-bit elements).

for i ← 0 to 7 do
  sign_bit ← xmm.word[i][15]
  xmm.word[i] ← arithmetic_shift_right(xmm.word[i], imm8)
  if imm8 >= 16 then xmm.word[i] ← sign_bit ? 0xFFFF : 0x0000 end if
end for


Packed Shift Right Arithmetic Doubleword

Summary: Shifts doublewords right arithmetic.

Shifts each 32-bit doubleword element in the XMM register right arithmetically by the count specified in the immediate value. The sign bit is replicated into vacated positions. No flags are affected. Available in SSE2 and later; operates on 128-bit packed data (four 32-bit elements).

for i ← 0 to 3 do
  sign_bit ← xmm.dword[i][31]
  xmm.dword[i] ← arithmetic_shift_right(xmm.dword[i], imm8)
  if imm8 >= 32 then xmm.dword[i] ← sign_bit ? 0xFFFFFFFF : 0x00000000 end if
end for


Summary: Compares bytes for equality (Result mask 0xFF or 0x00).

Performs a packed comparison for equality on 8-bit byte elements. For each byte position, the result is 0xFF if the elements are equal, or 0x00 if they are not equal. No traditional flags (OF, SF, ZF, etc.) are affected; results are stored in the destination register. Available in SSE2 and later; operates on 128-bit vectors (sixteen 8-bit elements).

for i ← 0 to 15 do
  if dest.byte[i] == src.byte[i] then
    dest.byte[i] ← 0xFF
  else
    dest.byte[i] ← 0x00
  end if
end for


Summary: Compares words for equality.

Performs a packed comparison for equality on 16-bit word elements. For each word position, the result is 0xFFFF if the elements are equal, or 0x0000 if they are not equal. No traditional flags are affected; results are stored in the destination register. Available in SSE2 and later; operates on 128-bit vectors (eight 16-bit elements).

for i ← 0 to 7 do
  if dest.word[i] == src.word[i] then
    dest.word[i] ← 0xFFFF
  else
    dest.word[i] ← 0x0000
  end if
end for


Summary: Compares doublewords for equality.

Performs a packed comparison for equality on 32-bit doubleword elements. For each doubleword position, the result is 0xFFFFFFFF if the elements are equal, or 0x00000000 if they are not equal. No traditional flags are affected; results are stored in the destination register. Available in SSE2 and later; operates on 128-bit vectors (four 32-bit elements).

for i ← 0 to 3 do
  if dest.dword[i] == src.dword[i] then
    dest.dword[i] ← 0xFFFFFFFF
  else
    dest.dword[i] ← 0x00000000
  end if
end for


Summary: Shuffles 32-bit integers.

Rearranges the four 32-bit doubleword elements in an XMM register according to the shuffle pattern encoded in the 8-bit immediate operand. Each pair of bits in the immediate selects which source doubleword populates each destination position. No flags are affected. Available in SSE2 and later; operates on 128-bit vectors.

temp ← src
for i ← 0 to 3 do
  selector ← (imm8 >> (i * 2)) & 0x3
  dest.dword[i] ← temp.dword[selector]
end for


Convert Doubleword Integer to Scalar Single-Precision

Summary: Converts 32-bit int to float.

Converts a 32-bit signed integer operand to a scalar single-precision floating-point value and stores the result in the low 32-bit lane of the destination XMM register, leaving the upper 96 bits unchanged. No traditional flags are affected. Available in SSE and later; the conversion follows IEEE 754 rounding rules.

src_int ← [src] (sign-extended if r/m32)
fp_value ← convert_int32_to_float(src_int)
dest.float32[0] ← fp_value
// dest.float32[1..3] unchanged


Convert Doubleword Integer to Scalar Double-Precision

Summary: Converts 32-bit int to double.

Converts a 32-bit signed integer to a 64-bit double-precision floating-point value and stores the result in the low 64 bits of the destination XMM register, leaving the upper 64 bits unchanged. The conversion uses the current rounding mode from MXCSR. No EFLAGS are affected by this instruction.


Convert with Truncation Scalar Single to Integer

Summary: Converts float to 32-bit int (Truncate).

dest

32-bit general-purpose register (e.g. EAX)

Converts a 32-bit single-precision floating-point value to a 32-bit signed integer using truncation towards zero, regardless of the rounding mode in MXCSR. If a NaN or overflow occurs, the result is INT32_MIN (0x80000000) and no exception is raised by default.

dest32 ← (int32)truncate(src32_float); CF ← 0; OF ← 0; SF ← 0; ZF ← 0; AF ← 0; PF ← 0;


Convert with Truncation Scalar Double to Integer

Summary: Converts double to 32-bit int (Truncate).

Converts a 64-bit double-precision floating-point value to a 32-bit signed integer using truncation towards zero, independent of the MXCSR rounding mode. If a NaN or overflow occurs, the result is INT32_MIN (0x80000000) with no exception raised by default.

dest32 ← (int32)truncate(src64_double); CF ← 0; OF ← 0; SF ← 0; ZF ← 0; AF ← 0; PF ← 0;


Summary: Converts float to double.

Converts a 32-bit single-precision floating-point value to a 64-bit double-precision floating-point value and stores the result in the low 64 bits of the destination XMM register, preserving the upper 64 bits. The conversion uses the current rounding mode from MXCSR, though single-to-double conversion is typically lossless.


Summary: Converts double to float.

Converts a 64-bit double-precision floating-point value to a 32-bit single-precision floating-point value and stores the result in the low 32 bits of the destination XMM register, leaving bits 32-127 unchanged. The conversion uses the current rounding mode from MXCSR and may result in precision loss or denormalized results.


Unordered Compare Scalar Single-Precision

Summary: Compares low float and sets EFLAGS.

Performs an unordered comparison of two single-precision floating-point values and sets EFLAGS (ZF, PF, CF) based on the result. If either operand is a signaling NaN, the comparison is treated as unordered; quiet NaNs also produce an unordered result. EFLAGS are set such that ZF=1, PF=1, CF=1 for unordered, ZF=0 for less, ZF=0 CF=1 for greater, and ZF=1 for equal.

cmp_result ← unordered_compare(dest.low32_float, src.low32_float); ZF ← (cmp_result == equal); PF ← (cmp_result == unordered); CF ← (cmp_result == less || cmp_result == unordered); AF ← 0; OF ← 0; SF ← 0;


Unordered Compare Scalar Double-Precision

Summary: Compares low double and sets EFLAGS.

Performs an unordered comparison of two double-precision floating-point values and sets EFLAGS (ZF, PF, CF) based on the result. If either operand is a signaling NaN, the comparison is unordered; quiet NaNs also produce an unordered result. EFLAGS reflect unordered (ZF=PF=CF=1), less, greater, or equal conditions.

cmp_result ← unordered_compare(dest.low64_double, src.low64_double); ZF ← (cmp_result == equal); PF ← (cmp_result == unordered); CF ← (cmp_result == less || cmp_result == unordered); AF ← 0; OF ← 0; SF ← 0;


Summary: Interleaves low bytes from two sources.

Interleaves the low 64 bits (8 bytes) of the destination and source XMM registers, expanding them to 128 bits with alternating bytes from each source: byte 0 from dest, byte 0 from src, byte 1 from dest, byte 1 from src, and so on. No EFLAGS are affected.

for i ← 0 to 7 do dest.byte[2*i] ← dest.byte[i]; dest.byte[2*i+1] ← src.byte[i];


Summary: Interleaves low words.

Interleaves the low 64 bits (4 words) of the destination XMM register with the low 64 bits (4 words) of the source XMM/memory operand, placing results back in the destination. No flags are affected. This SSE2 instruction operates on 128-bit packed word data and is available in 64-bit and protected modes.


Summary: Interleaves low doublewords.

Interleaves the low 64 bits (2 doublewords) of the destination XMM register with the low 64 bits (2 doublewords) of the source XMM/memory operand, placing results back in the destination. No flags are affected. This SSE2 instruction operates on 128-bit packed doubleword data and is available in 64-bit and protected modes.


Summary: Interleaves low quadwords.

Interleaves the low 64 bits (1 quadword) of the destination XMM register with the low 64 bits (1 quadword) of the source XMM/memory operand, placing results back in the destination. No flags are affected. This SSE2 instruction operates on 128-bit packed quadword data and is available in 64-bit and protected modes.


Pack with Signed Saturation Word to Byte

Summary: Converts words to bytes with saturation.

Packs 8 signed word values from the destination and source XMM registers into 16 signed byte values using signed saturation, storing the result in the destination. Values outside the range [-128, 127] are clamped to the boundaries. No flags are affected. This SSE2 instruction is available in 64-bit and protected modes.

for i in 0..7:
  dest[8*i+7:8*i] = SaturateSignedWordToByte(dest[16*i+15:16*i])
for i in 0..7:
  dest[8*(i+8)+7:8*(i+8)] = SaturateSignedWordToByte(src[16*i+15:16*i])


Pack with Signed Saturation Doubleword to Word

Summary: Converts doublewords to words with saturation.

Packs 4 signed doubleword values from the destination and source XMM registers into 8 signed word values using signed saturation, storing the result in the destination. Values outside the range [-32768, 32767] are clamped to the boundaries. No flags are affected. This SSE2 instruction is available in 64-bit and protected modes.

for i in 0..3:
  dest[16*i+15:16*i] = SaturateSignedDwordToWord(dest[32*i+31:32*i])
for i in 0..3:
  dest[16*(i+4)+15:16*(i+4)] = SaturateSignedDwordToWord(src[32*i+31:32*i])


Summary: Creates a mask from the MSB of each byte in XMM.

Extracts the most significant bit from each of the 16 bytes in the source XMM register and packs them into the low 16 bits of the destination 32-bit register; the upper 16 bits of the destination are zeroed. No flags are affected. This SSE2 instruction is useful for creating byte masks and is available in 64-bit and protected modes.


Summary: Non-temporal store of selected bytes (masked).

Conditionally stores bytes from the first XMM register to memory at the address in EDI/RDI, using the second XMM register as a write mask (only bytes with MSB set are written). This is a weakly-ordered operation; memory ordering is not guaranteed without explicit serialization. The first operand is the source of data, the second is the mask. No flags are affected. This SSE2 instruction is available in 64-bit and protected modes.

address = EDI (32-bit mode) or RDI (64-bit mode)
for i in 0..15:
  if src[8*i+7] == 1:
    [address + i] = dest[8*i+7:8*i]


Summary: Loads the MXCSR control/status register from memory.

Loads the MXCSR control and status register from a 32-bit memory operand, updating all SSE floating-point rounding modes, exception masks, exception flags, and DAZ/FTZ controls. This instruction serializes the CPU pipeline on many implementations. The instruction is available in 64-bit and protected modes with SSE support.


Summary: Stores the MXCSR register to memory.

Stores the 32-bit MXCSR control and status register to a 32-bit memory location. This instruction serializes execution and is typically used to save the SSE/SSE2/SSE3 floating-point state. No flags are modified by this instruction.


Summary: Prefetches data to L1 cache.

Issues a prefetch hint to load data from the specified memory address into all levels of the cache hierarchy (L1, L2, L3). This is a non-binding hint; the CPU may optimize or ignore it. No flags are modified and no exception is raised for invalid addresses.


Summary: Prefetches data to non-temporal cache structure (minimize pollution).

Issues a prefetch hint to load data from the specified memory address into the L1 cache using non-temporal access semantics, minimizing cache pollution for data that will not be reused. This is a non-binding hint; execution continues without waiting. No flags are modified.


Summary: Computes (Dest * Src2) + Src1.

Fused multiply-add on four packed single-precision floats: computes (dest × src2) + src1 with a single rounding operation, reducing latency and improving accuracy compared to separate multiply and add. Requires FMA3 extension (Intel Haswell+, AMD Piledriver+). Floating-point exceptions may be raised per IEEE 754; no integer flags are modified.

dest ← (dest * src2) + src1;  // single rounding, 256-bit YMM


Summary: Computes (Src1 * Dest) + Src2.

Fused multiply-add on four packed single-precision floats: computes (src1 × dest) + src2 with a single rounding operation. The operand order differs from vfmadd132ps. Requires FMA3 extension. Floating-point exceptions may be raised per IEEE 754; no integer flags are modified.

dest ← (src1 * dest) + src2;  // single rounding, 256-bit YMM


Fused Multiply-Subtract (132) Packed Single

Summary: Computes (Dest * Src2) - Src1.

Fused multiply-subtract on four packed single-precision floats: computes (dest × src2) - src1 with a single rounding operation. Requires FMA3 extension. Floating-point exceptions may be raised per IEEE 754; no integer flags are modified.

dest ← (dest * src2) - src1;  // single rounding, 256-bit YMM


Fused Negative Multiply-Add (132) Packed Single

Summary: Computes -(Dest * Src2) + Src1.

Fused negative multiply-add on four packed single-precision floats: computes -(dest × src2) + src1 with a single rounding operation, negating the product before the addition. Requires FMA3 extension. Floating-point exceptions may be raised per IEEE 754; no integer flags are modified.

dest ← -(dest * src2) + src1;  // single rounding, 256-bit YMM


Summary: Adds 8 integers (256-bit).

Adds eight packed 32-bit signed/unsigned integers from two 256-bit YMM registers or memory, storing the result in the destination. Integer overflow wraps around; no overflow flag is set. Requires AVX2 extension (Intel Haswell+, AMD Excavator+). No flags are modified.


Summary: Adds 32 bytes (256-bit).

Adds packed byte integers element-wise across two 256-bit YMM registers (or one YMM and one memory operand), producing 32 sums in the destination. No arithmetic flags are affected; wrapping occurs on overflow. This is a non-destructive three-operand instruction (VEX encoding allows the first source to remain unchanged).


Summary: Subtracts 8 integers (256-bit).

Subtracts packed doubleword (32-bit) integers element-wise from two 256-bit YMM registers (or one YMM and one memory operand), producing 8 differences in the destination. No arithmetic flags are affected; wrapping occurs on underflow. This is a non-destructive three-operand instruction (VEX encoding).


Summary: Multiplies 8 integers (256-bit).

Multiplies packed doubleword (32-bit) integers element-wise across two 256-bit YMM registers (or one YMM and one memory operand), producing 8 low 32-bit products in the destination. No arithmetic flags are affected; the high 32 bits of each product are discarded. This is a non-destructive three-operand instruction (VEX encoding requires AVX2).


Summary: Shuffles 32 bytes based on indices.

Shuffles 32 bytes within 256-bit YMM register using per-byte indices from another YMM register or memory; the operation works within 128-bit lanes (bytes 0-15 and 16-31 are shuffled independently). If the index's high bit (bit 7) is set, the result byte is zeroed; otherwise the low 4 bits select which source byte to copy within the lane. No arithmetic flags are affected.


Summary: Shuffles two 128-bit lanes between registers.

Permutes two 128-bit lanes from two 256-bit YMM registers based on an 8-bit immediate control value. The low nibble selects which 128-bit lane to take from src1, and the high nibble selects from src2; a lane can be zeroed by setting its selector to 0x8. The result fills the destination's two 128-bit halves independently. No arithmetic flags are affected.


Summary: Full permutation of 8 integers using indices from a register.

Performs a full permutation of 8 doublewords (32-bit integers) within a 256-bit YMM register using per-element indices from another YMM register or memory. The low 3 bits of each index select which of the 8 source doublewords to place at that position; if bit 31 is set in the index, the result element is zeroed. No arithmetic flags are affected.


Summary: Full permutation of 8 floats using indices.

Performs a full permutation of 8 single-precision floating-point values within a 256-bit YMM register using per-element indices from another YMM register or memory. The low 3 bits of each index select which of the 8 source floats to place at that position; if bit 31 is set in the index, the result element is zeroed. No arithmetic flags are affected.


Summary: Broadcasts a byte from memory/register to all elements of YMM.

Broadcasts a single byte from an XMM register or memory location to all 32 byte positions in a 256-bit YMM destination register. The source byte is replicated 32 times, filling the entire YMM with the same byte value. No arithmetic flags are affected.

src_byte = src[7:0]
for i = 0 to 31:
  dest[i*8 + 7 : i*8] ← src_byte


Summary: Loads floats from non-contiguous memory using indices.

VGATHERDPS ymm1, [base+ymm_idx*scale], ymm_mask

AVX scatter: base register + scaled YMM vector index

YMM register acting as gather/scatter mask and result destination

Gathers four single-precision floating-point values from non-contiguous memory locations using a base address and a YMM vector of 32-bit indices with optional scaling, storing results in the destination YMM register. The mask register controls which elements are loaded (set bits indicate active gather); masked-out elements are zeroed. Sets ZF if all mask bits are zero, clears CF and OF; other flags undefined.


Summary: Loads doubles from non-contiguous memory using indices.

VGATHERDPD ymm1, [base+xmm_idx*scale], ymm_mask

AVX gather: base register + scaled XMM vector index

Gathers two double-precision floating-point values from non-contiguous memory locations using a base address and an XMM vector of 32-bit indices with optional scaling, storing results in the destination YMM register. The mask register (YMM) controls which of the two elements are loaded; masked-out elements are zeroed. Sets ZF if all mask bits are zero, clears CF and OF; other flags undefined.


Summary: Calculates (NOT src1) AND src2. Non-destructive.

Performs bitwise AND of the logical NOT of src1 with src2, storing the result in dest without modifying src1. ZF is set if result is zero; CF and OF are cleared; AF and PF are undefined. Available in 32-bit and 64-bit operand sizes; requires BMI1 extension.

dest ← (~src1) & src2
ZF ← (dest == 0)
CF ← 0
OF ← 0
AF ← undefined
PF ← undefined


Summary: Extracts sequence of bits from source using index/length.

Extracts a contiguous sequence of bits from src1 specified by the start position and length encoded in src2 (bits 7:0 = start, bits 15:8 = length), storing the extracted bits in dest. ZF is set if the result is zero; CF and OF are cleared; AF and PF are undefined. Available in 32-bit and 64-bit sizes; requires BMI1 extension.

start ← src2[0:7]
length ← src2[8:15]
if length == 0:
  dest ← 0
else if (start + length) > 32:
  dest ← 0
else:
  dest ← (src1 >> start) & ((1 << length) - 1)
ZF ← (dest == 0)
CF ← 0
OF ← 0
AF ← undefined
PF ← undefined


Summary: Extracts the lowest set bit (x & -x).

Extracts the lowest set bit from src by computing (src & -src), storing the result in dest. ZF is set if src is zero; CF is set if src is zero; OF is cleared; AF and PF are undefined. Available in 32-bit and 64-bit sizes; requires BMI1 extension.

dest ← src & (-src)
ZF ← (src == 0)
CF ← (src == 0)
OF ← 0
AF ← undefined
PF ← undefined


Summary: Creates mask up to lowest set bit (x ^ (x-1)).

Creates a mask of all bits set from bit 0 up to and including the lowest set bit in src by computing (src ^ (src - 1)), storing the result in dest. ZF is set if src is zero; CF is set if src is zero; OF is cleared; AF and PF are undefined. Available in 32-bit and 64-bit sizes; requires BMI1 extension.

dest ← src ^ (src - 1)
ZF ← (src == 0)
CF ← (src == 0)
OF ← 0
AF ← undefined
PF ← undefined


Summary: Clears the lowest set bit (x & (x-1)).

Clears the lowest set bit in src by computing (src & (src - 1)), storing the result in dest. ZF is set if the result is zero; CF is set if src is zero; OF is cleared; AF and PF are undefined. Available in 32-bit and 64-bit sizes; requires BMI1 extension.

dest ← src & (src - 1)
ZF ← (dest == 0)
CF ← (src == 0)
OF ← 0
AF ← undefined
PF ← undefined


Summary: Counts the number of trailing zeros.

Counts the number of trailing zero bits in src, storing the count in dest. If src is zero, dest is set to the operand size (32 for r/m32); ZF is set if src is zero; CF is cleared; other flags undefined. Available in 32-bit and 64-bit operand sizes; BMI1 extension provides faster behavior than BSF.

if src == 0:
  dest ← 32
  ZF ← 1
else:
  count ← 0
  while (src & 1) == 0:
    count ← count + 1
    src ← src >> 1
  dest ← count
  ZF ← 0
CF ← 0


Summary: Clears high bits starting at index.

Zero High Bits Starting with Specified Bit Position clears all bits in the source operand at positions greater than or equal to the bit index specified in the third operand, storing the result in the destination. No flags are modified. Supported in 32-bit and 64-bit modes with BMI2 extension; the operand size can be 32 or 64 bits.

count ← src2[7:0] & 0x3F; mask ← (1 << count) - 1; dest ← src1 & mask;


Summary: Extracts bits from source using mask and packs them to LSB.

Parallel Bits Extract copies bits from the first source operand to the destination at positions where the mask operand has set bits, compacting them toward the LSB. No flags are modified. Supported in 32-bit and 64-bit modes with BMI2 extension; operand size can be 32 or 64 bits.

result ← 0; dest_bit ← 0; for (i = 0; i < operand_size; i++) { if (src2[i]) { result[dest_bit] ← src1[i]; dest_bit += 1; } } dest ← result;


Summary: Scatters bits from LSB of source to positions marked in mask.

Parallel Bits Deposit scatters bits from the LSB of the first source operand to positions marked by set bits in the mask operand, storing the result in the destination. No flags are modified. Supported in 32-bit and 64-bit modes with BMI2 extension; operand size can be 32 or 64 bits.

result ← 0; src_bit ← 0; for (i = 0; i < operand_size; i++) { if (src2[i]) { result[i] ← src1[src_bit]; src_bit += 1; } } dest ← result;


Summary: Unsigned multiply of RDX * Src. Result in Hi:Lo. No flags.

Unsigned Multiply Without Affecting Flags multiplies the implicit RDX register by the source operand and stores the 128-bit product in two destination registers (high part in the first operand, low part in the second), without modifying any arithmetic flags. Supported in 32-bit and 64-bit modes with BMI2 extension; the operand size can be 32 or 64 bits.

product ← RDX * src; dest_hi ← product[127:64]; dest_lo ← product[63:0];


Summary: Logical left shift, count in register. No flags update.

Shift Logical Left Without Affecting Flags performs a left shift of the source operand by a count held in a register, storing the result in the destination, without modifying any arithmetic flags. Supported in 32-bit and 64-bit modes with BMI2 extension; operand size can be 32 or 64 bits.

count ← src2 & ((operand_size == 64) ? 0x3F : 0x1F); dest ← src1 << count;


Summary: Logical right shift, count in register. No flags update.

Shift Logical Right Without Affecting Flags performs a logical right shift of the source operand by a count held in a register, storing the result in the destination, without modifying any arithmetic flags. Supported in 32-bit and 64-bit modes with BMI2 extension; operand size can be 32 or 64 bits.

count ← src2 & ((operand_size == 64) ? 0x3F : 0x1F); dest ← src1 >> count;


Summary: Arithmetic right shift, count in register. No flags update.

Shift Arithmetic Right Without Affecting Flags performs an arithmetic right shift of the source operand by a count held in a register, storing the result in the destination, without modifying any arithmetic flags. Supported in 32-bit and 64-bit modes with BMI2 extension; operand size can be 32 or 64 bits; the sign bit is extended into vacated positions.

count ← src2 & ((operand_size == 64) ? 0x3F : 0x1F); dest ← (signed)src1 >> count;


Summary: Rotate right with immediate. No flags update.

Rotate Right Logical Without Affecting Flags rotates the source operand right by an immediate count, storing the result in the destination, without modifying any arithmetic flags. Supported in 32-bit and 64-bit modes with BMI2 extension; operand size can be 32 or 64 bits.

count ← src2 & ((operand_size == 64) ? 0x3F : 0x1F); dest ← (src1 >> count) | (src1 << (operand_size - count));


Summary: Retrieves a hardware-generated random number.

Retrieves a cryptographically secure random number from the CPU's hardware random number generator and stores it in the destination register. The CF flag is set to 1 if a random number was successfully generated within the timeout period, or cleared to 0 if the generator failed to produce a value. No other flags are affected. This instruction is available only on processors with the RDRAND extension and cannot be used in real mode.

temp ← hardware_RNG();
if (RNG_success) {
  dest ← temp;
  CF ← 1;
} else {
  CF ← 0;
}


Summary: Retrieves a random seed from hardware entropy source.

Retrieves an entropy seed value from the CPU's hardware entropy source and stores it in the destination register. The CF flag is set to 1 if the seed was successfully obtained within the timeout period, or cleared to 0 on failure. No other flags are affected. This instruction requires the RDSEED extension and operates in protected and 64-bit modes only.

temp ← hardware_entropy_source();
if (entropy_success) {
  dest ← temp;
  CF ← 1;
} else {
  CF ← 0;
}


Summary: Invalidates TLB entries based on PCID.

Invalidates TLB entries based on the PCID (Process-Context Identifier) specified in the 128-bit memory operand, with the invalidation type determined by the descriptor type field. The source register provides an address (typically a general register holding PCID context information), and the memory operand contains the full 128-bit invalidation descriptor. This is a privileged instruction (CPL 0 only) that serializes the pipeline and requires the INVPCID extension. No flags are affected.

descriptor ← [src + 0:127];
invalidation_type ← descriptor.type;
pcid ← descriptor.pcid;
switch(invalidation_type) {
  case 0: invalidate_tlb_entry_by_pcid(pcid); break;
  case 1: invalidate_all_tlb_entries_by_pcid(pcid); break;
  case 2: invalidate_all_tlb_entries(); break;
  case 3: invalidate_all_tlb_entries_except_global(); break;
}
pipeline_serialization();


Unsigned Integer Addition of Two Operands with Carry Flag

Summary: Adds with Carry Flag (distinct from ADC, affects CF only).

Adds the source operand and the Carry Flag (CF) to the destination operand, storing the result in the destination. Only the CF flag is modified (set to 1 if unsigned overflow occurs, cleared to 0 otherwise); OF, SF, ZF, AF, and PF are left unchanged. This instruction is distinct from ADC in that it does not affect other flags, making it useful for parallel carry-chain operations with ADOX. Available in 32-bit and 64-bit operand sizes with the ADX extension.

temp ← dest + src + CF;
CF ← (temp > 0xFFFFFFFF) ? 1 : 0;
dest ← temp & 0xFFFFFFFF;


Unsigned Integer Addition of Two Operands with Overflow Flag

Summary: Adds with Overflow Flag (Parallel addition with ADCX).

Adds the source operand and the Overflow Flag (OF) to the destination operand, storing the result in the destination. Only the OF flag is modified (set to 1 if signed overflow occurs, cleared to 0 otherwise); CF, SF, ZF, AF, and PF are left unchanged. This instruction is designed to execute in parallel with ADCX for independent carry and overflow chains in multi-precision arithmetic. Available in 32-bit and 64-bit operand sizes with the ADX extension.

temp ← dest + src + OF;
OF ← (signed_overflow(dest, src, temp)) ? 1 : 0;
dest ← temp & 0xFFFFFFFF;


Summary: Inserts 128-bits of integer data into a YMM register.

Inserts a 128-bit integer value from the source operand into the destination YMM register at the position specified by the immediate operand. The lower 128 bits of the source YMM register (src1) are preserved or replaced depending on the immediate; typically imm8[0]=0 replaces the lower 128 bits, and imm8[0]=1 replaces the upper 128 bits. No flags are affected. This is a VEX-encoded AVX2 instruction that supports 32-bit or 64-bit vector elements.


Summary: Extracts 128-bits of integer data from YMM.

Extracts a 128-bit integer value from the source YMM register and stores it in the destination XMM register or memory location. The specific 128-bit lane extracted is determined by the immediate operand (imm8[0]=0 for lower 128 bits, imm8[0]=1 for upper 128 bits). No flags are affected. This is a VEX-encoded AVX2 instruction that complements VINSERTI128 for manipulating 256-bit vectors.


Summary: Clears Alignment Check flag (SMAP prevention).

Clears the Alignment Check (AC) flag in EFLAGS, disabling alignment checking for user-mode code. When combined with SMAP (Supervisor Mode Access Prevention), this instruction allows the kernel to temporarily disable SMAP protections. This is a privileged instruction (CPL 0 only) available with the SMAP extension. No other flags are affected.


Summary: Sets Alignment Check flag (Allow user memory access).

Sets the Alignment Check (AC) flag in EFLAGS, enabling alignment checking and allowing user-mode access to supervisor-mode data structures when SMAP protection is present. This instruction requires SMAP support and ring 0 privilege. Only the AC flag is modified; all other flags remain unchanged.


Summary: Computes affine transformation in GF(2^8).

Performs byte-wise affine transformation in Galois Field GF(2^8) on 128-bit XMM operands using a constant 8-bit immediate as the affine constant. Each byte in the destination is transformed using the corresponding byte from the source operand. No flags are affected; this is a pure data-parallel cryptographic operation.

for i in 0..15:
  dest[i] ← GF2P8_AFFINE_TRANSFORM(dest[i], src[i], imm8);


Summary: Multiplies bytes in GF(2^8).

Multiplies each byte in the destination XMM register by the corresponding byte in the source operand within Galois Field GF(2^8). The result replaces the destination operand byte-wise. No flags are affected; this is a pure cryptographic SIMD operation with full latency parallelism.

for i in 0..15:
  dest[i] ← GF2P8_MULTIPLY(dest[i], src[i]);


Summary: Performs intermediate calculation for SHA1 message schedule.

Performs the first intermediate step of SHA-1 message schedule expansion on 128-bit XMM operands, computing partial W values (message words) for rounds 16-19. The destination is updated with results of the schedule computation; no flags are affected.


Summary: Performs final calculation for SHA1 message schedule.

Performs the second final step of SHA-1 message schedule expansion on 128-bit XMM operands, completing W value computation and applying left rotation. The destination is updated with final message schedule results; no flags are affected.


Summary: Calculates SHA1 state variable E.

Calculates intermediate SHA-1 state variable E for one round, adding the source operand (containing message schedule and round constants) to the destination operand and applying left rotation. The result updates the destination with the next E value; no flags are affected.

E ← dest[0];
W ← src[0];
dest[0] ← ROTL32(E, 5) + W;
dest[1..3] ← dest[1..3] rotated left by 30 bits from the previous round state;


Summary: Performs 4 rounds of SHA1 operation.

Executes 4 rounds of the SHA-1 compression function, performing circular left shift, addition, and XOR operations on the five 32-bit state variables (A, B, C, D, E). The immediate byte selects the round function constant (K value 0-3); no flags are affected.

for round in 0..3:
  f ← SHA1_FUNCTION(round + imm8*4, B, C, D);
  K ← SHA1_CONSTANT(round + imm8*4);
  T ← ROTL32(A, 5) + f + E + K + W[round + imm8*4];
  E ← D; D ← C; C ← ROTL32(B, 30); B ← A; A ← T;


Summary: Performs intermediate calculation for SHA256 message schedule.

Performs the first intermediate step of SHA-256 message schedule expansion on 128-bit XMM operands, computing partial W values for the message schedule. The destination is updated with results of the partial expansion; no flags are affected.


Summary: Performs final calculation for SHA256 message schedule.

Performs the final calculation of the SHA256 message schedule for the next 4 message words. The instruction operates on 128-bit XMM registers containing 32-bit message schedule values and combines them with the previous message schedule state. All flags (CF, PF, AF, ZF, SF, OF) remain unchanged; this is a pure data-transformation instruction with no flag effects.


Summary: Performs 2 rounds of SHA256 operation.

Executes two rounds of the SHA256 compression function on the working variables. The instruction reads round constants from XMM0 and processes the destination register in-place using the source operand as input to the SHA256 rounds. All flags remain unchanged; this instruction has no flag side effects and requires the SHA CPU extension.


Summary: Enters VMX root operation (Host Mode).

Enters VMX root operation (host/hypervisor mode) using a 64-bit VMXON region pointer loaded from memory. The instruction validates the VMXON region, sets the VMXON flag in CR4, and transitions the processor to VMX root mode; failure causes #UD or sets RFLAGS.CF/ZF. This is a privileged instruction (requires CPL=0) and available only on processors with VMX support.

if (CPL != 0 || VMX_ENABLED == 0) raise #UD
VMXON_PTR ← [m64]
if (!validate_vmxon_region(VMXON_PTR)) { RFLAGS.CF ← 1; RFLAGS.ZF ← 0; } else { VMX_ROOT ← 1; RFLAGS.CF ← 0; RFLAGS.ZF ← 0; }


Summary: Guest VM calls the Hypervisor (VM Exit).

Initiates a VM exit from guest mode to invoke the VM monitor (hypervisor). The instruction immediately transitions control to the hypervisor and is available only when running in VMX non-root mode; execution in root mode raises #UD. RFLAGS.CF and ZF may be set on VM exit depending on the exit reason; other flags are preserved across the transition.

if (CPL != 0 || VMX_ROOT == 1) raise #UD
VMEXIT(VMCALL_EXIT_REASON)
if (exit_error) { RFLAGS.CF ← 1; RFLAGS.ZF ← 1; }


Summary: Initializes a VMCS region in memory.

Initializes a Virtual Machine Control Structure (VMCS) region in memory by clearing its launch state and marking it as inactive. The instruction loads a 64-bit VMCS pointer from memory, validates the region, and sets CF/ZF on validation failure. This is a privileged instruction (CPL=0) requiring VMX support and must be executed in VMX root mode.

if (CPL != 0 || VMX_ROOT == 0) raise #UD
VMCS_PTR ← [m64]
if (!validate_vmcs_region(VMCS_PTR)) { RFLAGS.CF ← 1; RFLAGS.ZF ← 0; } else { clear_vmcs(VMCS_PTR); RFLAGS.CF ← 0; RFLAGS.ZF ← 0; }


Summary: Launches a VM managed by the current VMCS.

Launches a virtual machine using the current VMCS. The instruction reads guest state from the current VMCS, validates it, and transitions to VMX non-root mode; on success, control transfers to the guest; on failure, returns to the instruction with CF/ZF set. This is a privileged instruction (CPL=0) available only in VMX root mode on processors with VMX support.

if (CPL != 0 || VMX_ROOT == 0) raise #UD
if (!validate_vmcs_state()) { RFLAGS.CF ← 1; RFLAGS.ZF ← 0; } else { load_guest_state_from_vmcs(); VMX_ROOT ← 0; transfer_control_to_guest(); }


Summary: Resumes a VM from the current VMCS.

Resumes a suspended virtual machine from the current VMCS. The instruction restores guest CPU state from the VMCS and returns control to the guest; on validation failure, CF/ZF are set and control returns to the hypervisor. This is a privileged instruction (CPL=0) available only in VMX root mode and following a prior VMLAUNCH or VM exit.

if (CPL != 0 || VMX_ROOT == 0) raise #UD
if (!validate_vmcs_state()) { RFLAGS.CF ← 1; RFLAGS.ZF ← 0; } else { restore_guest_state_from_vmcs(); VMX_ROOT ← 0; transfer_control_to_guest(); }


Summary: Loads the current VMCS pointer from memory.

Loads a pointer to the Virtual Machine Control Structure (VMCS) from memory and sets it as the current VMCS. The instruction reads a 64-bit VMCS physical address from memory, validates the region, and sets CF/ZF on failure. This is a privileged instruction (CPL=0) requiring VMX support and execution in VMX root mode; the VMCS region must be 4KB-aligned.

if (CPL != 0 || VMX_ROOT == 0) raise #UD
VMCS_PTR ← [m64]
if (!validate_vmcs_region(VMCS_PTR)) { RFLAGS.CF ← 1; RFLAGS.ZF ← 0; } else { CURRENT_VMCS ← VMCS_PTR; RFLAGS.CF ← 0; RFLAGS.ZF ← 0; }


Summary: Stores the current VMCS pointer to memory.

Stores the current VMCS pointer (from the VMCS pointer register) to a 64-bit memory location. This instruction is privileged and requires VMX root operation; it clears the memory destination with the active VMCS pointer value. The CF flag is set if an error occurs (invalid VMCS pointer state); ZF is set to indicate success or failure.

if (VMX_mode == ROOT && VMCS_pointer != INVALID) {
  [dest] ← VMCS_pointer_register;
  CF ← 0;
  ZF ← 0;
} else {
  CF ← 1;
  ZF ← 1;
}


Summary: Reads a field from the Virtual Machine Control Structure.

src

64-bit general-purpose register (e.g. RAX)

Reads a 64-bit field from the current VMCS (specified by the index in the source operand) and writes the value to the destination register or memory. Requires active VMCS and VMX root or non-root operation; CF is set on error, ZF indicates field validity.

if (VMCS_pointer_valid && VMX_mode_active) {
  field_index ← src;
  value ← VMCS[field_index];
  dest ← value;
  CF ← 0;
  ZF ← 0;
} else {
  CF ← 1;
  ZF ← 1;
}


Summary: Writes a field to the Virtual Machine Control Structure.

Writes a 64-bit value to a field in the current VMCS (specified by the index in the destination operand). Requires active VMCS and VMX root or non-root operation; CF is set on error, ZF indicates write success.

if (VMCS_pointer_valid && VMX_mode_active) {
  field_index ← dest;
  value ← src;
  VMCS[field_index] ← value;
  CF ← 0;
  ZF ← 0;
} else {
  CF ← 1;
  ZF ← 1;
}


Summary: Leaves VMX root operation.

Exits VMX root operation and returns the processor to non-VMX mode. This instruction requires VMX root operation and clears the VMXE bit in CR4. CF and ZF flags are set to indicate error conditions if the operation fails; execution may be serialized.

if (VMX_root_operation) {
  VMX_mode ← OFF;
  CR4.VMXE ← 0;
  CF ← 0;
  ZF ← 0;
} else {
  CF ← 1;
  ZF ← 1;
}


Invalidate Translations Derived from EPT

Summary: Invalidates Extended Page Table entries.

Invalidates Extended Page Table (EPT) translation cache entries based on the invalidation type and operand descriptor. The destination register specifies the invalidation type (1=single context, 2=all contexts), and the source memory operand contains EPTP and VPID information. CF/ZF flags indicate success or error; this instruction may serialize execution.

if (EPT_enabled && VMX_mode_active) {
  invalidation_type ← dest;
  descriptor ← [src];
  if (invalidation_type == 1) {
    invalidate_EPT_context(descriptor);
  } else if (invalidation_type == 2) {
    invalidate_all_EPT();
  }
  CF ← 0;
  ZF ← 0;
} else {
  CF ← 1;
  ZF ← 1;
}


Summary: Invalidates TLB entries based on Virtual Processor ID.

Invalidates TLB entries based on Virtual Processor ID (VPID). The destination register specifies the invalidation type (1=individual address, 2=single VPID context, 3=all VPID contexts, 4=individual address keeping globals), and the source memory operand contains VPID and address information. CF/ZF flags indicate success or error; this instruction serializes execution.

if (VPID_enabled && VMX_mode_active) {
  invalidation_type ← dest;
  descriptor ← [src];
  if (invalidation_type == 1) {
    invalidate_TLB_address(descriptor);
  } else if (invalidation_type == 2) {
    invalidate_TLB_VPID(descriptor);
  } else if (invalidation_type == 3) {
    invalidate_all_TLB();
  } else if (invalidation_type == 4) {
    invalidate_TLB_address_keep_global(descriptor);
  }
  CF ← 0;
  ZF ← 0;
} else {
  CF ← 1;
  ZF ← 1;
}


Summary: Moves 16-bit mask to/from k-register.

AVX-512 opmask register (k0-k7) or Memory operand

Moves a 16-bit value between AVX-512 opmask registers (k0-k7) or from/to a 16-bit memory location. When moving from register/memory to k-register, the upper bits beyond 16 are zeroed. ZF is set based on source value; CF is typically cleared unless an error occurs.

if (source_is_register) {
  dest_k ← src_k & 0xFFFF;
} else {
  dest_k ← [src] & 0xFFFF;
}
ZF ← (dest_k == 0);
CF ← 0;


Summary: Moves 64-bit mask to/from k-register.

Moves a 64-bit value between AVX-512 opmask registers (k0-k7) or from/to a 64-bit memory location. Requires AVX-512BW support; destination k-register receives the full 64-bit mask. ZF is set based on source value; CF is typically cleared unless an error occurs.

if (source_is_register) {
  dest_k ← src_k;
} else {
  dest_k ← [src];
}
ZF ← (dest_k == 0);
CF ← 0;


Summary: Bitwise AND of 16-bit masks.

Performs a bitwise AND operation on two 16-bit AVX-512 opmask registers and stores the result in a third opmask register. This is a mask-only operation that does not affect EFLAGS. The instruction operates on the lower 16 bits of the k registers; bits above 16 are zeroed in the destination.


Summary: Bitwise AND NOT of 16-bit masks.

Performs a bitwise AND NOT operation (NOT src1 AND src2) on two 16-bit AVX-512 opmask registers and stores the result in a third opmask register. This is a mask-only operation that does not affect EFLAGS. Bits above 16 in the destination are zeroed.


Summary: Bitwise OR of 16-bit masks.

Performs a bitwise OR operation on two 16-bit AVX-512 opmask registers and stores the result in a third opmask register. This is a mask-only operation that does not affect EFLAGS. Bits above 16 in the destination are zeroed.


Summary: Bitwise XOR of 16-bit masks.

Performs a bitwise XOR operation on two 16-bit AVX-512 opmask registers and stores the result in a third opmask register. This is a mask-only operation that does not affect EFLAGS. Bits above 16 in the destination are zeroed.


Summary: Bitwise NOT of 16-bit mask.

Performs a bitwise NOT operation on a 16-bit AVX-512 opmask register and stores the result in another opmask register. This is a mask-only operation that does not affect EFLAGS. Bits above 16 in the destination are zeroed.


Summary: ORs two masks and sets EFLAGS (ZF, CF) based on result.

Performs a bitwise OR of two 16-bit AVX-512 opmask registers and sets EFLAGS based on the result. Sets ZF if the result is zero, CF if the result is 0xFFFF (all ones in the 16-bit field), and clears OF and SF. This instruction is typically used for predication and loop control in AVX-512 code.

temp ← k1[15:0] | k2[15:0]; ZF ← (temp == 0); CF ← (temp == 0xFFFF); OF ← 0; SF ← 0;


Summary: Performs one of 256 logical operations on 3 inputs.

VPTERNLOGD zmm1 {k1}, zmm2, zmm3/m512, imm8

512-bit ZMM AVX-512 register or Memory operand

Performs one of 256 possible three-input Boolean logical operations on 512-bit packed doublewords. The immediate operand selects which Boolean function to apply; supports opmask-controlled execution and writes to ZMM registers. No EFLAGS are affected; the instruction is fully predicated by {k1} if specified.


Summary: Performs one of 256 logical operations on 3 quadwords.

VPTERNLOGQ zmm1 {k1}, zmm2, zmm3/m512, imm8

Performs one of 256 possible three-input Boolean logical operations on 512-bit packed quadwords. The immediate operand selects which Boolean function to apply; supports opmask-controlled execution and writes to ZMM registers. No EFLAGS are affected; the instruction is fully predicated by {k1} if specified.


Store Sparse Packed Double-Precision Floating-Point Values

Summary: Compresses active elements from ZMM to memory.

Stores active (mask-enabled) 64-bit double-precision floating-point elements from a ZMM register to memory in compressed form, where only the elements selected by the opmask k1 are written consecutively to the destination address. No flags are modified. Requires AVX-512F; operates on 512-bit ZMM registers and writes up to 512 bits of memory depending on mask population.

count ← 0
for i in 0 to 7:
  if k1[i] == 1:
    [dest + count * 8] ← ZMM2[i*64 : (i+1)*64]
    count ← count + 1


Store Sparse Packed Single-Precision Floating-Point Values

Stores active (mask-enabled) 32-bit single-precision floating-point elements from a ZMM register to memory in compressed form, where only the elements selected by the opmask k1 are written consecutively to the destination address. No flags are modified. Requires AVX-512F; operates on 512-bit ZMM registers and writes up to 512 bits of memory depending on mask population.

count ← 0
for i in 0 to 15:
  if k1[i] == 1:
    [dest + count * 4] ← ZMM2[i*32 : (i+1)*32]
    count ← count + 1


Load Sparse Packed Double-Precision Floating-Point Values

Summary: Expands data from memory into sparse locations in ZMM.

Loads 64-bit double-precision floating-point elements from memory into a ZMM register at positions selected by the opmask k1, leaving masked-out positions unchanged if zeroing is not enabled. No flags are modified. Requires AVX-512F; reads from memory and expands sparse data into the 512-bit destination register.

count ← 0
for i in 0 to 7:
  if k1[i] == 1:
    ZMM1[i*64 : (i+1)*64] ← [src + count * 8]
    count ← count + 1
  else if k1[i] == 0 and zeroing == false:
    ZMM1[i*64 : (i+1)*64] ← ZMM1[i*64 : (i+1)*64]


Load Sparse Packed Single-Precision Floating-Point Values

Loads 32-bit single-precision floating-point elements from memory into a ZMM register at positions selected by the opmask k1, leaving masked-out positions unchanged if zeroing is not enabled. No flags are modified. Requires AVX-512F; reads from memory and expands sparse data into the 512-bit destination register.

count ← 0
for i in 0 to 15:
  if k1[i] == 1:
    ZMM1[i*32 : (i+1)*32] ← [src + count * 4]
    count ← count + 1
  else if k1[i] == 0 and zeroing == false:
    ZMM1[i*32 : (i+1)*32] ← ZMM1[i*32 : (i+1)*32]


Summary: Shuffles doublewords from two ZMM registers into destination.

Permutes 32-bit doublewords from two source operands (zmm2 and zmm3/m512) using indices in zmm1 to produce a shuffled result in zmm1, where each 5-bit index selects one of 16 elements from each source. No flags are modified. Requires AVX-512F; results follow opmask k1 zeroing behavior. The index operand zmm1 is overwritten with the permuted result.


Permute Two-Source Doublewords (Overwrite)

Summary: Shuffles 2 sources, overwriting the index register.

Permutes 32-bit doublewords from two source operands (zmm2 and zmm3/m512) using indices in zmm1 to produce a shuffled result in zmm1, where each 5-bit index selects one of 16 elements from each source. No flags are modified. Requires AVX-512F; the index register zmm1 is overwritten with the permutation result and follows opmask k1 zeroing behavior.


Summary: Shuffles 128-bit blocks of single-precision floats.

VSHUFF32X4 zmm1 {k1}, zmm2, zmm3/m512, imm8

Shuffles 128-bit blocks (each containing four 32-bit floats) from two ZMM sources according to an 8-bit immediate control, writing the result to the destination ZMM register. No flags are modified. Requires AVX-512F; the immediate selects which 128-bit quadwords are interleaved from the two sources. Opmask k1 controls which result elements are written.


Summary: Down-converts 32-bit integers to 8-bit.

Truncates 16 32-bit doubleword integers from a ZMM register down to 8-bit bytes, writing the 16 resulting bytes to an XMM register or 128-bit memory location. No flags are modified. Requires AVX-512F; the conversion is a simple truncation (low 8 bits extracted). Opmask k1 controls which byte results are written.


Summary: Down-converts 32-bit to 8-bit with unsigned saturation.

Converts 16 packed 32-bit unsigned integers from a ZMM register to 16 packed 8-bit unsigned integers in an XMM register or memory, saturating values that exceed 255 to 255. The operation is element-wise; each 32-bit source value is independently clamped to the range [0, 255] and stored as an 8-bit result. Operates in 64-bit mode only and respects EVEX writemask {k1} for conditional element updates.


Round Packed Double-Precision Floating-Point with Scale

Summary: Rounds doubles to integer values using imm8 control.

Rounds 8 packed 64-bit floating-point values to integer values using rounding control specified in imm8 (bits 3:0 select round-to-nearest-even, round-down, round-up, or round-toward-zero; bits 5:4 control sign, bits 7:6 control exception behavior). Destination is written with the scaled and rounded results. The instruction may set or clear floating-point exception flags (ZF, CF, OF, SF, PF) depending on the rounding results and imm8 exception control.

for i = 0 to 7:
  src_val = zmm2/m512[i*64 + 63 : i*64]
  round_mode = imm8[3:0]
  scaled_val = 2^(-(imm8[5:4])) * src_val
  rounded = RoundToIntegerFP(scaled_val, round_mode)
  result[i*64 + 63 : i*64] = rounded
  if (imm8[6] == 0 and FP_exception_raised):
    set_FP_exception_flags()
if k1_mask[i] == 1:
  zmm1[i*64 + 63 : i*64] = result[i*64 + 63 : i*64]
else if {z} == 1:
  zmm1[i*64 + 63 : i*64] = 0


Summary: Fixes special cases (NaN, Inf) using a table.

VFIXUPIMMPD zmm1 {k1}, zmm2, zmm3/m512, imm8

Fixes up special floating-point cases (NaN, Infinity, denormalized) in 8 packed 64-bit values using a lookup table indexed by imm8 and the class/sign of each element. For each source element, the instruction examines the exceptional condition bits and uses imm8 to select a fixup value or pass-through behavior. The result is placed in the destination; may set floating-point exception flags (ZF, CF, OF, SF, PF) if exceptions are not suppressed.

for i = 0 to 7:
  src1_val = zmm2[i*64 + 63 : i*64]
  src2_val = zmm3/m512[i*64 + 63 : i*64]
  class_bits = ClassifyFP64(src1_val)
  index = (imm8[1:0] << 2) | class_bits[1:0]
  lookup_result = FIXUP_TABLE[index]
  if lookup_result == PASS_THROUGH:
    result[i*64 + 63 : i*64] = src1_val
  else if lookup_result == USE_SRC2:
    result[i*64 + 63 : i*64] = src2_val
  else:
    result[i*64 + 63 : i*64] = lookup_result
  if (imm8[3:2] != 11 and exception_condition):
    set_FP_exception_flags()
if k1_mask[i] == 1:
  zmm1[i*64 + 63 : i*64] = result[i*64 + 63 : i*64]
else if {z} == 1:
  zmm1[i*64 + 63 : i*64] = 0


Summary: Extracts mantissas from doubles.

Extracts the mantissa (significand) from 8 packed 64-bit floating-point values and returns them as normalized floating-point results. The imm8 parameter controls which portion of the mantissa is returned (e.g., ±[1.0, 2.0), ±[0.5, 1.0), etc.) and the rounding mode for the mantissa extraction. Denormalized inputs and exceptional cases may be handled according to imm8 bits; floating-point exception flags may be set depending on exception handling mode.

for i = 0 to 7:
  src_val = zmm2/m512[i*64 + 63 : i*64]
  mantissa_mode = imm8[1:0]
  round_mode = imm8[3:2]
  suppress_exceptions = imm8[4]
  mantissa = ExtractMantissa(src_val, mantissa_mode)
  rounded_mantissa = RoundMantissa(mantissa, round_mode)
  result[i*64 + 63 : i*64] = rounded_mantissa
  if (suppress_exceptions == 0 and exception_condition):
    set_FP_exception_flags()
if k1_mask[i] == 1:
  zmm1[i*64 + 63 : i*64] = result[i*64 + 63 : i*64]
else if {z} == 1:
  zmm1[i*64 + 63 : i*64] = 0


Summary: Extracts exponents from doubles as float values.

Extracts the exponent from 8 packed 64-bit floating-point values and returns each exponent as a 64-bit floating-point value (i.e., the unbiased exponent is converted to a double-precision floating-point number). Special cases such as zero, denormalized, infinite, and NaN inputs follow IEEE 754 semantics; floating-point exception flags (ZF, CF, OF, SF, PF) may be set depending on the nature of the inputs and masking.

for i = 0 to 7:
  src_val = zmm2/m512[i*64 + 63 : i*64]
  if is_zero(src_val):
    result[i*64 + 63 : i*64] = -INF
  else if is_denormal(src_val):
    exp_val = MIN_EXPONENT
    result[i*64 + 63 : i*64] = ConvertToFP64(exp_val)
  else if is_infinity(src_val):
    result[i*64 + 63 : i*64] = +INF
  else if is_nan(src_val):
    result[i*64 + 63 : i*64] = NaN
  else:
    unbiased_exp = ExtractExponent(src_val) - BIAS
    result[i*64 + 63 : i*64] = ConvertToFP64(unbiased_exp)
if k1_mask[i] == 1:
  zmm1[i*64 + 63 : i*64] = result[i*64 + 63 : i*64]
else if {z} == 1:
  zmm1[i*64 + 63 : i*64] = 0


Scale Packed Float64 Values with Float64 Exponents

Summary: Scales doubles by exponents (x * 2^n).

Scales 8 packed 64-bit floating-point values by raising 2 to the power of the corresponding exponent value (dst = src1 * 2^src2) using floating-point exponentiation. Each element of src2 is treated as an integer exponent; the result is computed with full floating-point precision. The instruction may set or clear floating-point exception flags (ZF, CF, OF, SF, PF) based on overflow, underflow, or other exceptional conditions.

for i = 0 to 7:
  mantissa = zmm2[i*64 + 63 : i*64]
  exponent = zmm3/m512[i*64 + 63 : i*64]
  exp_int = ConvertToInt(exponent)
  if exp_int > MAX_EXP:
    result[i*64 + 63 : i*64] = INF (sign from mantissa)
    set_FP_exception_flag(OVERFLOW)
  else if exp_int < MIN_EXP:
    result[i*64 + 63 : i*64] = 0.0 (sign from mantissa)
    set_FP_exception_flag(UNDERFLOW)
  else:
    scaled = mantissa * (2.0 ^ exp_int)
    result[i*64 + 63 : i*64] = scaled
if k1_mask[i] == 1:
  zmm1[i*64 + 63 : i*64] = result[i*64 + 63 : i*64]
else if {z} == 1:
  zmm1[i*64 + 63 : i*64] = 0


Summary: Extracts 512-bits from two concatenated ZMMs shifted by count.

VALIGND zmm1 {k1}, zmm2, zmm3/m512, imm8

Extracts 512 bits from the concatenation of two ZMM registers (src2 || src1), where src2 is the high part, shifted right by imm8 * 32 bits, and writes the result to dest. This acts as a multi-element rotate-right or barrel-shift operation on the combined 1024-bit value. All 16 packed 32-bit doubleword elements shift by the same amount; elements that shift out are discarded, and zero-fill enters from the left. Operates only in 64-bit mode.

shift_amount = imm8 * 32
temp_concat = (zmm2[511:0] << 512) | zmm1[511:0]
result = temp_concat >> shift_amount
for i = 0 to 15:
  result_dword[i] = result[(i+1)*32 - 1 : i*32]
if k1_mask[i] == 1:
  zmm1[i*32 + 31 : i*32] = result_dword[i]
else if {z} == 1:
  zmm1[i*32 + 31 : i*32] = 0


Detect Conflicts Within a Vector of Packed Dword Values

Summary: Detects duplicate values in a vector (Conflict Detection).

Detects conflicting (duplicate) values within a vector of 16 packed 32-bit unsigned integers and writes a conflict mask to the destination. For each element, the instruction generates a 32-bit mask where bit j is set to 1 if the element at position i equals the element at position j (where j > i). This enables efficient identification of duplicate elements within a single vector. Operates only in 64-bit mode; no arithmetic flags are modified.


Summary: Counts leading zeros for each doubleword element.

Counts the number of leading zero bits in each 32-bit doubleword element of the source operand and writes the count to the corresponding doubleword in the destination. Operates on 512-bit vectors under EVEX encoding with optional write-mask (k1) and zeroing. No EFLAGS are affected by this instruction.

for i = 0 to 15 do
  src_val = zmm2[i*32 : (i+1)*32-1]
  count = 0
  for j = 31 downto 0 do
    if src_val[j] == 1 then break
    count++
  zmm1[i*32 : (i+1)*32-1] = count
end for


Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point

Summary: Converts unsigned int32 to float.

Converts each 32-bit unsigned integer in the source to a single-precision floating-point value and stores the result in the destination. Operates on 512-bit vectors under EVEX encoding with optional write-mask (k1) and rounding control. No EFLAGS are affected; rounding follows MXCSR or embedded rounding mode.

for i = 0 to 15 do
  src_val = zmm2[i*32 : (i+1)*32-1]
  zmm1[i*32 : (i+1)*32-1] = convert_uint32_to_float32(src_val, rounding_mode)
end for


Summary: Rotates doublewords left by amounts in second vector.

Rotates each 32-bit element in the first source left by the amount specified in the corresponding 32-bit element of the second source, storing results in the destination. Operates on 512-bit vectors under EVEX encoding with optional write-mask (k1). The rotation amount is taken modulo 32. No EFLAGS are affected.


Summary: Counts set bits in each doubleword element.

Counts the number of set bits (1s) in each 32-bit doubleword element of the source operand and writes the population count to the corresponding doubleword in the destination. Operates on 512-bit vectors under EVEX encoding with optional write-mask (k1) and zeroing. No EFLAGS are affected.

for i = 0 to 15 do
  src_val = zmm2[i*32 : (i+1)*32-1]
  count = 0
  for j = 0 to 31 do
    if src_val[j] == 1 then count++
  zmm1[i*32 : (i+1)*32-1] = count
end for


Summary: Executes an SGX supervisor function specified by EAX.

Executes an SGX supervisor enclave leaf function specified by a leaf number in EAX. The instruction serializes the CPU pipeline and transitions from non-root mode to root mode for executing privileged enclave operations. The actual operation depends on the leaf function code; CF flag may be set on error conditions, and various other registers may be modified based on the leaf function.

leaf_function = EAX
if (leaf_function == EBLOCK) then
  // Block enclave
elseif (leaf_function == ETRACK) then
  // Flush TLB
elseif (leaf_function == EWBLOCK) then
  // Write block enclave
else
  // Execute other supervisor leaf functions
end if


Summary: Executes an SGX user function specified by EAX.

Executes an SGX user enclave leaf function specified by a leaf number in EAX. The instruction serializes the CPU pipeline and may transition between user and enclave execution modes depending on the leaf function. The actual operation depends on the leaf function code; various registers and flags may be modified based on the requested operation.

leaf_function = EAX
if (leaf_function == EREPORT) then
  // Generate enclave report
elseif (leaf_function == EGETKEY) then
  // Get sealing/reporting key
elseif (leaf_function == EEXIT) then
  // Exit enclave
elseif (leaf_function == EENTER) then
  // Enter enclave
else
  // Execute other user leaf functions
end if


Summary: Extracts bit field from register (AMD SSE4a).

Extracts a bit field from the 128-bit xmm1 register using the field length and field position specified in xmm2 bits [13:8] and [5:0] respectively. The extracted field is zero-extended and placed in xmm1; bits not part of the extracted field are zeroed. No EFLAGS are affected; this is an AMD SSE4a extension instruction.

field_length = xmm2[13:8]
field_pos = xmm2[5:0]
if (field_length == 0) then
  field_length = 64
end if
mask = ((1 << field_length) - 1)
extracted = (xmm1 >> field_pos) & mask
xmm1 = extracted


Summary: Inserts bit field into register (AMD SSE4a).

Inserts a bit field from xmm2 into xmm1 at the position and length specified in xmm2 bits [13:8] and [5:0] respectively. The field from xmm2 is placed into xmm1 starting at the specified bit position; the rest of xmm1 remains unchanged. No EFLAGS are affected; this is an AMD SSE4a extension instruction.

field_length = xmm2[13:8]
field_pos = xmm2[5:0]
if (field_length == 0) then
  field_length = 64
end if
mask = ((1 << field_length) - 1)
insert_value = xmm2 & mask
xmm1 = (xmm1 & ~(mask << field_pos)) | (insert_value << field_pos)


Summary: Stores scalar float bypassing cache (AMD SSE4a).

Stores the low 32-bit scalar single-precision floating-point value from an XMM register to a 32-bit memory location, bypassing the cache hierarchy using non-temporal semantics. The instruction issues a weakly-ordered write that avoids polluting the L1/L2 caches, useful for streaming writes. No arithmetic flags are affected; this is a memory store only.


Summary: Stores scalar double bypassing cache (AMD SSE4a).

Stores the low 64-bit scalar double-precision floating-point value from an XMM register to a 64-bit memory location, bypassing the cache hierarchy using non-temporal semantics. Similar to MOVNTSS but for 64-bit double-precision values; useful for streaming writes of double-precision data. No arithmetic flags are affected; this is a memory store only.


Summary: Clears the cache line at address RAX/EAX (AMD).

Zeros (clears) a 64-byte cache line at the address held in RAX (in 64-bit mode) or EAX (in 32-bit mode), writing zeros to memory while bypassing caches. This instruction is a non-temporal operation useful for initializing large memory regions without cache pollution. No flags are affected; the memory is written directly and cache coherency is maintained.

lineaddr ← RAX & ~0x3F; memset([lineaddr], 0, 64);


Summary: Sets all bits to 0 except the lowest set bit inverted (x | ~(x+1)).

Computes (src | ~(src+1)) and stores the result in dest, isolating all bits except the lowest set bit (which is inverted). Part of the TBM (Trailing Bit Manipulation) extension; sets flags based on the result: ZF if result is zero, SF based on sign bit, and CF/OF/PF are undefined. Available in 32-bit and 64-bit variants.

result ← src | ~(src + 1); dest ← result; ZF ← (result == 0); SF ← result[31]; CF ← undefined; OF ← undefined; PF ← undefined;


Summary: Isolates lowest clear bit (~x & (x+1)).

Computes (~src & (src+1)) and stores the result in dest, isolating the lowest clear (zero) bit. Part of the TBM extension; sets ZF if result is zero and SF based on the sign bit of the result; CF, OF, and PF are undefined. Available in 32-bit and 64-bit variants.

result ← ~src & (src + 1); dest ← result; ZF ← (result == 0); SF ← result[31]; CF ← undefined; OF ← undefined; PF ← undefined;


Summary: Creates mask from lowest clear bit (x ^ (x+1)).

Computes (src ^ (src+1)) and stores the result in dest, creating a mask from the lowest clear bit to bit 0. Part of the TBM extension; sets ZF if result is zero and SF based on the sign bit of the result; CF, OF, and PF are undefined. Available in 32-bit and 64-bit variants.

result ← src ^ (src + 1); dest ← result; ZF ← (result == 0); SF ← result[31]; CF ← undefined; OF ← undefined; PF ← undefined;


Summary: Sets lowest clear bit (x | (x+1)).

Computes (src | (src+1)) and stores the result in dest, setting the lowest clear bit. Part of the TBM extension; sets ZF if result is zero and SF based on the sign bit of the result; CF, OF, and PF are undefined. Available in 32-bit and 64-bit variants.

result ← src | (src + 1); dest ← result; ZF ← (result == 0); SF ← result[31]; CF ← undefined; OF ← undefined; PF ← undefined;


Summary: Sets all bits below lowest set bit ((x-1) | x).

Computes ((src-1) | src) and stores the result in dest, filling all bits below and including the lowest set bit. Part of the TBM extension; sets ZF if result is zero and SF based on the sign bit of the result; CF, OF, and PF are undefined. Available in 32-bit and 64-bit variants.

result ← (src - 1) | src; dest ← result; ZF ← (result == 0); SF ← result[31]; CF ← undefined; OF ← undefined; PF ← undefined;


Summary: Isolates lowest set bit and complements (~x | (x-1)).

Isolates the lowest set bit and complements the result, computing ~src | (src - 1). This TBM instruction is useful for extracting bit masks and operates on 32-bit operands in protected/64-bit modes. No flags are modified by this instruction.


Summary: Creates mask from trailing ones (~x | (x+1)).

Creates a mask from trailing ones by computing ~src | (src + 1), isolating all bits from the least significant one through trailing ones. This TBM instruction operates on 32-bit operands and does not modify CPU flags.


Summary: Creates mask from trailing zeros (~x & (x-1)).

Creates a mask from trailing zeros by computing ~src & (src - 1), isolating only the trailing zero bits. This TBM instruction operates on 32-bit operands in protected/64-bit modes and does not modify any CPU flags.


Summary: Rotates bytes in XMM register.

Rotates each byte within a 128-bit XMM register by the amount specified in the 8-bit signed immediate, with rotation direction determined by the sign of the immediate (positive = left rotate, negative = right rotate). This XOP instruction is part of the AMD Bulldozer-era vector extensions and does not modify CPU flags.


Summary: Rotates words in XMM register.

Rotates each 16-bit word within a 128-bit XMM register by the amount specified in the 8-bit signed immediate, with rotation direction determined by sign (positive = left rotate, negative = right rotate). This XOP vector instruction does not modify CPU flags.


Summary: Rotates doublewords in XMM register.

Rotates each 32-bit doubleword within a 128-bit XMM register by the amount specified in the 8-bit signed immediate, with rotation direction determined by sign (positive = left rotate, negative = right rotate). This XOP instruction does not affect CPU flags.


Summary: Rotates quadwords in XMM register.

Rotates each 64-bit quadword within a 128-bit XMM register by the amount specified in the 8-bit signed immediate, with rotation direction determined by sign (positive = left rotate, negative = right rotate). This XOP vector instruction does not modify CPU flags.


Summary: Shifts bytes arithmetically.

Performs arithmetic left or right shift on each byte element within a 128-bit XMM register based on the 8-bit signed immediate, with positive values for left shift and negative for right shift (sign-extending). This XOP instruction does not modify CPU flags.


Summary: Shifts words arithmetically.

Shifts each 16-bit word in xmm2/m128 arithmetically by the signed immediate count, storing results in xmm1. Arithmetic right shifts replicate the sign bit; left shifts fill with zeros. This XOP extension instruction operates on 128-bit packed word data and does not affect EFLAGS.


Vector Packed Shift Arithmetic Doubleword

Summary: Shifts doublewords arithmetically.

Shifts each 32-bit doubleword in xmm2/m128 arithmetically by the signed immediate count, storing results in xmm1. Arithmetic right shifts preserve the sign bit; left shifts fill with zeros. This XOP extension instruction operates on 128-bit packed doubleword data and does not affect EFLAGS.


Summary: Shifts quadwords arithmetically.

Shifts each 64-bit quadword in xmm2/m128 arithmetically by the signed immediate count, storing results in xmm1. Arithmetic right shifts maintain the sign bit; left shifts fill with zeros. This XOP extension instruction operates on 128-bit packed quadword data and does not affect EFLAGS.


Vector Packed Horizontal Add Byte to Word

Summary: Adds adjacent bytes to words.

Horizontally adds adjacent pairs of signed 8-bit bytes from xmm2/m128, accumulating results as 16-bit words in xmm1. Each pair of bytes produces one 16-bit word result; the operation doubles the data width. This XOP extension instruction does not affect EFLAGS and handles signed arithmetic with saturation or wrapping semantics dependent on implementation.


Vector Packed Horizontal Add Byte to Doubleword

Summary: Adds adjacent bytes to doublewords.

Horizontally adds adjacent groups of four signed 8-bit bytes from xmm2/m128, accumulating results as 32-bit doublewords in xmm1. Four consecutive bytes are summed to produce one 32-bit result. This XOP extension instruction does not affect EFLAGS and performs signed arithmetic.


Vector Packed Horizontal Add Byte to Quadword

Summary: Adds adjacent bytes to quadwords.

Horizontally adds all eight signed 8-bit bytes from xmm2/m128 (lower half) and (upper half separately), accumulating results as 64-bit quadwords in xmm1. All bytes from each half are summed to produce two 64-bit results. This XOP extension instruction does not affect EFLAGS and performs signed arithmetic.


Vector Packed Horizontal Add Word to Doubleword

Summary: Adds adjacent words to doublewords.

Horizontally adds adjacent pairs of signed 16-bit words from xmm2/m128, accumulating results as 32-bit doublewords in xmm1. Each pair of words produces one 32-bit doubleword result; the operation doubles the data width. This XOP extension instruction does not affect EFLAGS and performs signed arithmetic.


Vector Packed Horizontal Add Word to Quadword

Summary: Adds adjacent words to quadwords.

Horizontally adds adjacent groups of four signed 16-bit words from xmm2/m128, accumulating results as 64-bit quadwords in xmm1. Four consecutive words are summed to produce one 64-bit result. This XOP extension instruction does not affect EFLAGS and performs signed arithmetic.


Vector Packed Horizontal Add Doubleword to Quadword

Summary: Adds adjacent doublewords to quadwords.

Adds pairs of adjacent 32-bit signed integers and stores the 64-bit sums in the destination XMM register. This is a horizontal operation that processes two 32-bit elements from each 64-bit lane, producing one 64-bit result per lane. No flags are affected.


Vector Packed Multiply Accumulate Signed Word

Summary: Multiply-accumulate signed words.

Multiplies pairs of signed 16-bit integers, accumulates the 32-bit products, and stores results in the destination XMM register without saturation. This is a 4-operand instruction encoding multiply-accumulate semantics: dest = src1 * src2 + src3. No flags are affected.

for i = 0 to 7:
  product ← sign_extend_32(src1[i*16:(i*16)+15]) *
            sign_extend_32(src2[i*16:(i*16)+15])
  result[i*32:(i*32)+31] ← product + sign_extend_32(src3[i*16:(i*16)+15])
dest ← result


Vector Packed Multiply Accumulate Signed Saturate Word

Summary: Multiply-accumulate signed words with saturation.

Multiplies pairs of signed 16-bit integers, accumulates the 32-bit products with saturation to signed 32-bit range, and stores results in the destination XMM register. This saturating variant clamps results to [-2³¹, 2³¹-1]. No flags are affected.

for i = 0 to 7:
  product ← sign_extend_32(src1[i*16:(i*16)+15]) *
            sign_extend_32(src2[i*16:(i*16)+15])
  sum ← product + sign_extend_32(src3[i*16:(i*16)+15])
  result[i*32:(i*32)+31] ← saturate_signed_32(sum)
dest ← result


Summary: Prefetches floats to L1 cache using indices.

dest

AVX-512 gather/scatter: base register + ZMM vector index

Prefetches cache lines to L1 for single-precision floats using 32-bit dword indices from a vector register. The instruction performs a gather-style prefetch where each ZMM element acts as an index offset from a base address, but does not load data into registers. The opmask register {k1} controls which prefetch operations execute. No flags are affected.

for i = 0 to 15:
  if k1[i] == 1:
    addr ← base + zmm_idx[i*32:(i*32)+31] * scale
    prefetch_L1(addr)
  endif


Gather Prefetch Packed Single (L1, Qword Indices)

Summary: Prefetches floats to L1 using 64-bit indices.

Prefetches cache lines to L1 for single-precision floats using 64-bit qword indices from a vector register. Each element of the ZMM vector is treated as a 64-bit index offset from a base address for gather-prefetch semantics. The opmask {k1} selects which prefetch operations occur. No flags are affected.

for i = 0 to 7:
  if k1[i] == 1:
    addr ← base + zmm_idx[i*64:(i*64)+63] * scale
    prefetch_L1(addr)
  endif


Summary: Prefetches doubles to L1 cache using indices.

AVX gather/scatter: base register + YMM vector index

Prefetches cache lines to L1 for double-precision floats using 32-bit dword indices from a vector register. Each 32-bit index in the YMM register is scaled and added to a base address for gathering-style prefetch operations. The opmask {k1} gates which prefetch operations execute. No flags are affected.

for i = 0 to 7:
  if k1[i] == 1:
    addr ← base + ymm_idx[i*32:(i*32)+31] * scale
    prefetch_L1(addr)
  endif


Gather Prefetch Packed Double (L1, Qword Indices)

Summary: Prefetches doubles to L1 using 64-bit indices.

Prefetches cache lines to L1 for double-precision floats using 64-bit qword indices from a vector register. Each 64-bit element in the ZMM index register is scaled and added to a base address for gather-prefetch semantics. The opmask {k1} controls which prefetch operations are active. No flags are affected.


Summary: Prefetches cache lines for scatter write (L1).

Prefetches cache lines to L1 in preparation for scatter write operations on single-precision floats using 32-bit dword indices. Unlike gather prefetch, this operation optimizes cache behavior for subsequent scatter stores. The opmask {k1} selects which prefetch operations occur. No flags are affected.

for i = 0 to 15:
  if k1[i] == 1:
    addr ← base + zmm_idx[i*32:(i*32)+31] * scale
    prefetch_L1_for_write(addr)
  endif


Scatter Prefetch Packed Single (L1, Qword Indices)

Summary: Prefetches lines for scatter write (L1, 64-bit idx).

Prefetches cache lines for scatter write operations using 64-bit (qword) indices into a ZMM vector, with L1 cache as the target. This is a non-faulting prefetch hint that does not load data or raise exceptions; it only triggers hardware prefetch logic based on the indexed addresses. Execution is masked by the k1 opmask register, and no flags are affected.

for (i = 0; i < 8; i++) {
  if (k1[i]) {
    addr = base + ZMM_idx[i];
    prefetch_l1(addr);
  }
}


Summary: Prefetches lines for scatter write (L1, Double).

Prefetches cache lines for scatter write operations using 32-bit (dword) indices into a YMM vector containing doubles, with L1 cache as the target. This is a non-faulting prefetch hint that does not load data or raise exceptions; masked execution by k1 is supported. No flags are affected.

for (i = 0; i < 4; i++) {
  if (k1[i]) {
    addr = base + ZeroExtend64(YMM_idx[i*32:i*32+31]);
    prefetch_l1(addr);
  }
}


Scatter Prefetch Packed Double (L1, Qword Indices)

Summary: Prefetches lines for scatter write (L1, Double, 64-bit idx).

Prefetches cache lines for scatter write operations using 64-bit (qword) indices into a ZMM vector containing doubles, with L1 cache as the target. This non-faulting prefetch hint is masked by the k1 opmask and does not load data or raise exceptions. No flags are affected.


Dot Product Signed Word to Signed Doubleword (4-iterations)

Summary: Neural Net 4-way dot product.

ZMM register pair (consecutive even+odd registers, for 4-iteration FMA)

Performs four iterations of fused multiply-add on signed word operands, accumulating into 32-bit signed doubleword results in zmm1. The instruction reads from a consecutive register pair (zmm2:zmm3) and a 128-bit memory operand, executing four parallel dot products per iteration. Masked by k1; no flags are affected; saturation does not occur (results wrap on overflow).


Dot Product Signed Word to Signed Doubleword Saturate (4-iter)

Summary: Neural Net 4-way dot product with saturation.

Performs four iterations of fused multiply-add on signed word operands, accumulating into 32-bit signed doubleword results in zmm1 with saturation. The instruction reads from a consecutive register pair (zmm2:zmm3) and a 128-bit memory operand, executing four parallel dot products per iteration. Results saturate to INT32_MIN/INT32_MAX on overflow; masked by k1; no flags are affected.


Fused Multiply-Add Packed Single (4-iterations)

Summary: 4-way FMA for Neural Nets (Single).

Performs four iterations of fused multiply-add on packed single-precision floating-point operands, accumulating results into zmm1. The instruction reads from a consecutive ZMM register pair (zmm2:zmm3) and a 128-bit memory operand, computing four parallel multiply-accumulate chains. Masked by k1; floating-point exceptions (precision, underflow, overflow, denormal) may be signaled; rounding is per MXCSR.