Store VSX Scalar as Integer Byte Indexed X-form

Summary: Stores a byte from a VSX scalar register into memory at an address formed by adding two general-purpose registers.

The instruction stores the byte element 7 of VSR[XS] into the memory location specified by the effective address (EA), which is the sum of GPR[RA] and GPR[RB]. If RA is zero, EA is simply GPR[RB].

if SX=0 & MSR.VSX=0 then
    VSX_Unavailable()
if SX=1 & MSR.VEC=0 then
    Vector_Unavailable()
EA ←((RA=0) ? 0 : GPR[RA]) + GPR[RB]
MEM(EA,1) ←VSR[32×SX+S].byte[7]

This instruction is used to store a specific byte from a VSX register into memory. Ensure that the appropriate privilege level and MSR bits (VSX or VEC) are set before using this instruction, as it may raise exceptions if not. The effective address is calculated based on GPR[RA] and GPR[RB], with special handling if RA is zero. Be cautious of alignment requirements to avoid potential performance penalties or exceptions.


Store VSX Scalar Single-Precision DS-form

Summary: Stores a single-precision floating-point value from a VSX register to memory.

The instruction stores the double-precision floating-point value in doubleword element 0 of VSR[XS] converted to single-precision format into memory at the effective address (EA). The EA is calculated as the sum of the contents of register RA and the sign-extended DS field. If MSR.VEC=0, a Vector_Unavailable() exception is raised.

if MSR.VEC=0 then
    Vector_Unavailable()
else if 'stxssp' then
    EA ← (RA|0) + EXTS64(DS||0b00)
    MEM(EA,4) ← bfp32_CONVERT_FROM_BFP64(VSR[VRS+32].dword[0])

The stxssp instruction stores a single-precision floating-point value from the VSX register into memory. Ensure that the Vector Facility is enabled (MSR.VEC=1) to avoid exceptions. The effective address is calculated by adding the contents of RA and the sign-extended DS field. This instruction requires 4-byte alignment for the memory address.


Store VSX Scalar Single-Precision Indexed X-form

Converts the value in the right doubleword of VSX register XS from double-precision to single-precision floating-point format and stores it to memory at address (RA) + (RB). This is a VSX instruction and does not affect condition registers or status fields.

RA

Source General Purpose Register (Base Address)

ea ← (RA) + (RB)
dp_value ← XS.doubleword[1]
sp_value ← convert_dp_to_sp(dp_value)
[ea] ← sp_value

The stxsspx instruction is used to store a single-precision floating-point value from the VSX register into memory. Ensure that the VSX facility is enabled by checking and setting the MSR.VSX bit. Be cautious of alignment requirements; the EA must be 4-byte aligned for optimal performance. If RA is zero, the effective address (EA) will be set to zero, which might lead to unexpected behavior if not intended.


Summary: Loads a vector of 16 byte elements from memory into a VSX register.

Loads a 128-bit vector containing 16 byte elements from memory into a VSX register. The effective address is computed as RA|0 + RB. No status fields are modified by this instruction.

EA ← (RA=0 ? 0 : GPR[RA]) + GPR[RB]
VSR[XT] ← MEM(EA, 16)

Exhibits identical behavior in Big-Endian mode.


Summary: Loads a vector of 8 halfwords from memory into a VSX register.

Loads a 128-bit vector containing 8 halfword elements from memory into a VSX register. The effective address is computed as RA|0 + RB. No status fields are modified by this instruction.

lxvh8x, lxvd2x, lxvw4x, lxvb16x, and lxvx exhibit identical behavior in Big-Endian mode.


Summary: Loads a quadword from memory into a VSX register.

Loads a 128-bit quadword from memory into a VSX register using indexed addressing. The effective address is computed as RA|0 + RB. No status fields are modified by this instruction.

The lxvx instruction is used to load vector data from memory into VSX registers.


Load VSX Vector Rightmost Byte Indexed X-form

Summary: Loads a byte from memory into the rightmost byte of a VSX vector register.

Loads a single byte from memory and places it in the rightmost (least significant) byte position of a VSX register, with all other bytes set to 0. The effective address is computed as RA|0 + RB. No status fields are modified by this instruction.

The lxvrbx instruction is used to load a single byte from memory into the rightmost byte of a VSX vector register. Ensure that the VSX facility is enabled in the MSR register; otherwise, an exception will be raised. The address calculation involves adding two general-purpose registers, RA and RB, where RA can be zero. This instruction zeroes out all other bytes in the target vector register except for the rightmost byte.


Load VSX Vector Rightmost Doubleword Indexed X-form

Summary: Loads a doubleword from memory into the rightmost element of a VSX vector register.

Loads a 64-bit doubleword from memory and places it in the rightmost (least significant) doubleword element of a VSX register, with the left doubleword set to 0. The effective address is computed as RA|0 + RB. No status fields are modified by this instruction.

Source General Purpose Register (address base)

RB

Source General Purpose Register (offset)

The lxvrdx instruction is used to load a doubleword from memory into the rightmost element of a VSX vector register. Ensure that the VSX facility is enabled in the MSR register; otherwise, a VSX_Unavailable exception will be raised. The address calculation uses two general-purpose registers, RA and RB, where RA can be zero. Be cautious of alignment requirements for optimal performance and to avoid potential exceptions.


Load VSX Vector Rightmost Halfword Indexed

Summary: Loads a halfword from memory into the rightmost element of a VSX vector register.

Loads a 16-bit halfword from memory and places it in the rightmost (least significant) halfword position of a VSX register, with all other bits set to 0. The effective address is computed as RA|0 + RB. No status fields are modified by this instruction.

The lxvrhx instruction is used to load a halfword from memory into the rightmost element of a VSX vector register. Ensure that the VSX facility is enabled in the MSR register; otherwise, an exception will be raised. The address calculation uses two general-purpose registers, RA and RB, where RA can be zero. The loaded halfword is placed in the rightmost halfword element (element 7) of the specified VSX vector register, with all other elements set to zero. Endianness affects how the halfword is stored in the vector register; ensure proper handling for both big-endian and little-endian systems.


Load VSX Vector Rightmost Word Indexed X-form

Summary: Loads a word from memory into the rightmost word of a VSX vector register.

Loads a 32-bit word from memory and places it in the rightmost (least significant) word position of a VSX register, with all other bits set to 0. The effective address is computed as RA|0 + RB. No status fields are modified by this instruction.

Source General Purpose Register (Offset)

The lxvrwx instruction is used to load a word from memory into the rightmost word of a VSX vector register. Ensure that the VSX facility is enabled in the MSR register; otherwise, an exception will be raised. The address calculation involves adding two general-purpose registers, RA and RB, with a special case where if RA is zero, the base address defaults to zero. This instruction zeroes out the first three words of the target vector register before placing the loaded word into the rightmost position.


Load VSX Vector with Length Left-justified X-form

Summary: Loads a variable-length vector from memory into a VSX register, left-justifying the data.

Loads a variable-length data element from memory into a VSX register, left-justifying the loaded bytes within the 128-bit register. The effective address is RA|0, and the length in bytes is taken from bits 0-6 of RB (capped at 16). Remaining bytes in the register are zeroed. No status fields are modified by this instruction.

RA

Source General Purpose Register (Effective Address)

RB

Source General Purpose Register (Length and Data)

EA ← (RA=0 ? 0 : GPR[RA])
len ← GPR[RB][0:6] & 0xF
for i ← 0 to (len - 1) do
  VSR[XT][i*8:(i*8)+7] ← MEM(EA + i, 1)
for i ← len to 15 do
  VSR[XT][i*8:(i*8)+7] ← 0

lxvll always performs storage accesses using Big-Endian byte-ordering. As such, care must be taken when using these instructions in Little-Endian systems.


Summary: Stores a vector of 16 byte elements from VSR[XS] into Big-Endian storage using stxvb16x, retaining left-to-right element ordering.

The instruction stores a vector of 16 byte elements from VSR[XS] into Big-Endian storage using stxvb16x, retaining left-to-right element ordering.

if SX=0 & MSR.VSX=0 then VSX_Unavailable()
if SX=1 & MSR.VEC=0 then Vector_Unavailable()
EA ←((RA=0) ? 0 : GPR[RA]) + GPR[RB]
do i = 0 to 15
    MEM(EA+i,1) ←VSR[32×SX+S].byte[i]
end

stxvd2x, stxvw4x, stxvh8x, stxvb16x, and stxvx exhibit identical behavior in Big-Endian mode.


Summary: Stores a vector of 8 halfword elements from VSR[X] into memory using indexed addressing.

Stores a 128-bit VSX vector containing 8 halfword elements to memory using indexed addressing. The effective address is computed as (RA|0) + RB. This is a VSX extension instruction that does not affect condition registers or status flags.


Summary: Stores a vector element from the VSX register file to memory.

Stores a 128-bit VSX vector element to memory using indexed addressing in X-form. The effective address is computed as (RA|0) + RB, and the vector is stored with element size determined by the instruction form. This VSX instruction does not affect condition registers or status flags.

RA

Source General Purpose Register for Base Address

RB

Source General Purpose Register for Offset

xW

VSX Register containing the vector to store

General Purpose Register (typically used as zero register)

rPW

Base address General Purpose Register for W

rPX

Base address General Purpose Register for X

rPY

Base address General Purpose Register for Y

rPZ

Base address General Purpose Register for Z

The stxvx instruction is used for storing VSX vectors to memory. The index value in XS is multiplied by 16 bytes.


Store VSX Vector Rightmost Byte Indexed X-form

Summary: Stores the rightmost byte of a VSX vector element to memory.

The contents of byte element 15 of VSR[XS] are placed into storage at address EA, which is the sum of GPR[RA] and GPR[RB]. If RA=0, EA is just GPR[RB].

if MSR.VSX=0 then VSX_Unavailable()
EA = ((RA=0) ? 0 : GPR[RA]) + GPR[RB];
MEM(EA,1) = VSR[32×SX+S].byte[15];

This instruction stores the rightmost byte of a VSX vector register into memory. Ensure that the VSX facility is enabled (MSR.VSX=1) to avoid an exception. The effective address (EA) is calculated by adding GPR[RA] and GPR[RB], unless RA is 0, in which case EA is just GPR[RB]. Be cautious of alignment; while not strictly required for a single byte, proper alignment can improve performance.


Store VSX Vector Rightmost Halfword Indexed X-form

Summary: Stores the rightmost halfword of a VSX vector element to memory.

Stores the rightmost halfword (least significant 16 bits) of the first double-precision element in a VSX vector to memory using indexed addressing. The effective address is computed as (RA|0) + RB. This VSX instruction does not affect condition registers or status flags.

The stxvrhx instruction stores the rightmost halfword of a VSX vector element into memory. Ensure that the VSX facility is enabled (MSR.VSX=1); otherwise, a VSX_Unavailable exception will occur. The effective address is calculated by adding GPR[RA] and GPR[RB], so ensure these registers contain valid addresses. This instruction operates at user privilege level.


Store VSX Vector with Length Left-justified

Summary: Stores a left-justified vector from a VSX register to memory.

Stores a variable-length left-justified portion of a VSX vector to memory. The number of bytes to store (0-16) is specified in the low-order 4 bits of RB; bytes are stored starting at the effective address (RA|0). This VSX instruction does not affect condition registers or status flags.

RB

General Purpose Register containing the number of bytes to store

EA ← (RA|0)
length ← RB[60:63]
for i ← 0 to length-1 do
  [EA+i] ← VSR[XS][8*i:8*i+7]
end for

stxvll always performs storage accesses using Big-Endian byte-ordering. As such, care must be taken when using these instructions in Little-Endian systems.


Summary: Loads a vector from memory into two VSR registers.

The contents of the octword in storage at address EA are placed into load_data. The order of bytes in load_data depends on the byte ordering (Little-Endian or Big-Endian). Bits 0-127 of load_data are placed into VSR[XTp], and bits 128-255 of load_data are placed into VSR[XTp+1].

XTp

Target Vector-Specific Register (VSR) index

if MSR.VSX=0 then
    VSX_Unavailable()
EA ←((RA=0) ? 0 : GPR[RA]) + GPR[RB]
load_data ←MEM(EA,32)
VSR[32×TX+2×Tp]   ←load_data.bit[  0:127]
VSR[32×TX+2×Tp+1] ←load_data.bit[128:255]

For best performance, EA should be word-aligned.


Summary: Stores a vector from two VSR registers into memory at the effective address.

The instruction stores an octword (128 bits) of data from two VSR registers into memory. The data is stored in big-endian order if the system is configured for big-endian byte ordering, and little-endian order if the system is configured for little-endian byte ordering.

if MSR.VSX=0 then
    VSX_Unavailable()
EA ←((RA=0) ? 0 : GPR[RA]) + GPR[RB]
store_data.bit[0:127] ← VSR[32×SX+2×Sp]
store_data.bit[128:255] ← VSR[32×SX+2×Sp+1]
MEM(EA,32) ← store_data


Summary: Copies the sign of a double-precision floating-point value from one register to another.

Copies the sign bit from the double-precision floating-point value in VSR[XA] to the double-precision value in VSR[XB], placing the result in VSR[XT]. The magnitude of the result comes from XB and the sign comes from XA. FPSCR is not affected; this instruction operates on the scalar element of the VSX register.

XA

Source Vector-Scalar Register for Sign Bit

XB

Source Vector-Scalar Register for Magnitude

This instruction can be used to operate on single-precision source operands.
Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.


VSX Scalar Negative Absolute Double-Precision

Summary: Computes the negative absolute value of a double-precision floating-point number.

The instruction computes the negative absolute value of the double-precision floating-point number in VSR[XB] and stores it in VSR[XT]. The result is zeroed out for the second doubleword.

if MSR.VSX=0 then
    VSX_Unavailable()
src ←VSR[32×BX+B].dword[0]
VSR[32×TX+T].dword[0] ←bfp64_NEGATIVE_ABSOLUTE(src)
VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000

This instruction can be used to operate on a single-precision source operand. Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register.


Summary: Copies the sign bit from one double-precision vector element to another.

For xvcpsgndp, the sign bit of each doubleword element in VSR[XB] is copied to the corresponding doubleword element in VSR[XT], while the magnitude bits remain unchanged.

if MSR.VSX=0 then VSX_Unavailable()
do i = 0 to 1
    src1 ←VSR[32×AX+A].dword[i] & 0x8000_0000_0000_0000
    src2 ←VSR[32×BX+B].dword[i] & 0x7FFF_FFFF_FFFF_FFFF
    VSR[32×TX+T].dword[i] ←src1 | src2
end

This instruction is useful for copying the sign of double-precision floating-point numbers while preserving their magnitude. Ensure that VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. The operation is performed on each doubleword element independently, so alignment requirements are per-element rather than per-vector.


Vector Negative Absolute Double-Precision

Summary: Computes the negative absolute value of each double-precision floating-point element in a vector.

For xvnabsdp, the negative absolute value of each double-precision floating-point element in VSR[XB] is computed and stored in VSR[XT].

if MSR.VSX=0 then VSX_Unavailable()
do i = 0 to 1
    src ←VSR[32×BX+B].dword[i]
    VSR[32×TX+T].dword[i] ←bfp64_NEGATIVE_ABSOLUTE(src)
end

This instruction computes the negative absolute value of each double-precision floating-point element in a vector. Ensure that VSX (Vector Scalar Extensions) is enabled by checking and setting the appropriate bit in the Machine State Register (MSR). The operation processes two elements per vector register, so ensure proper alignment if manipulating individual elements.


Summary: Divides the double-precision floating-point value in VSR[XA] by the double-precision floating-point value in VSR[XB].

Divides the scalar double-precision floating-point value in VSR[XA] by the scalar double-precision floating-point value in VSR[XB], storing the result in VSR[XT]. The operation follows IEEE 754 semantics; FPSCR is updated with exception flags and the result sign/exponent. This VSX instruction requires the VSX extension.

XT ← VSR[XA] ÷ VSR[XB]
FPSCR ← updated with exception flags and rounding

FPSCR FPRF FR FI FX OX UX ZX XX VXSNAN VXIDI VXZDZ

The xsdivdp instruction is used for dividing double-precision floating-point numbers. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. Handle special cases like NaNs and infinities by checking the FPSCR flags after execution. The result is rounded according to the rounding mode set in FPSCR.RN.


Summary: Multiplies two double-precision floating-point numbers and places the result in a vector register.

Multiplies the scalar double-precision floating-point value in VSR[XA] by the scalar double-precision floating-point value in VSR[XB], storing the result in VSR[XT]. The operation follows IEEE 754 semantics; FPSCR is updated with exception flags and rounding control. This VSX instruction requires the VSX extension.

XT ← VSR[XA] × VSR[XB]
FPSCR ← updated with exception flags and rounding

FPSCR.FPRF, FPSCR.FR, FPSCR.FI, FPSCR.FX, FPSCR.OX, FPSCR.UX, XX, VXSNAN, VXIMZ

Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.


Summary: Computes the square root of a single-precision floating-point number in VSX.

The unbounded-precision square root of src is produced. The intermediate result is rounded to single-precision using the rounding mode specified by RN. The result is placed into doubleword element 0 of VSR[XT] in double-precision format. The contents of doubleword element 1 of VSR[XT] are set to 0.

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
v ←bfp_SQUARE_ROOT(src)
rnd ←bfp_ROUND_TO_BFP32(FPSCR.RN,v)
result32 ←bfp32_CONVERT_FROM_BFP(rnd)
result64 ←bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vxsqrt_flag=1 then SetFX(FPSCR.VXSQRT)
if ox_flag=1 then SetFX(FPSCR.OX)
if ux_flag=1 then SetFX(FPSCR.UX)
if xx_flag=1 then SetFX(FPSCR.XX)
vx_flag ←vxsnan_flag | vxsqrt_flag
vex_flag ←FPSCR.VE & vx_flag
if vex_flag=0 then do
    VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000
    FPSCR.FPRF ←fprf_CLASS_BFP32(result32)
    FPSCR.FR  ←inc_flag
    FPSCR.FI  ←xx_flag
end else do
    FPSCR.FR  ←0b0
    FPSCR.FI  ←0b0
end

FPSCR, VSR[XT], FPRF, FR, FI, FX, OX, UX, VXSNAN, VXSQRT


Summary: Subtracts the contents of two double-precision floating-point registers and places the result in another register.

The instruction subtracts the value of src2 (negated) from src1, producing a sum with unbounded range and precision. The sum is normalized and rounded to double-precision using the rounding mode specified by RN. The result is placed into doubleword element 0 of VSR[XT], and doubleword element 1 of VSR[XT] is set to 0.

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src1 ← bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])
src2 ← bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
v ← bfp_ADD(src1, bfp_NEGATE(src2))
rnd ← bfp_ROUND_TO_BFP64(0b0, FPSCR.RN, v)
result ← bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vxisi_flag=1 then SetFX(FPSCR.VXISI)
if ox_flag=1 then SetFX(FPSCR.OX)
if ux_flag=1 then SetFX(FPSCR.UX)
if xx_flag=1 then SetFX(FPSCR.XX)
vx_flag ← vxsnan_flag | vxisi_flag
vex_flag ← FPSCR.VE & vx_flag
if vex_flag=0 then do
    VSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000
    FPSCR.FR ← inc_flag
    FPSCR.FI ← xx_flag
else do
    FPSCR.FR ← 0b0
    FPSCR.FI ← 0b0
end
VSR[32×TX+T].dword[0] ← result
FPSCR.FPRF ← fprf_CLASS_BFP64(result)

Let XT be the value 32×TX + T. Let XA be the value 32×AX + A. Let XB be the value 32×BX + B. Let src1 be the double-precision floating-point value in doubleword element 0 of VSR[XA]. Let src2 be the double-precision floating-point value in doubleword element 0 of VSR[XB].


VSX Scalar Multiply-Add Type-A Double-Precision

Summary: Performs a double-precision floating-point multiply-add operation.

For xsmaddadp, do the following. Let src1 be the double-precision floating-point value in doubleword element 0 of VSR[XA]. Let src2 be the double-precision floating-point value in doubleword element 0 of VSR[XT]. Let src3 be the double-precision floating-point value in doubleword element 0 of VSR[XB].

if 'xsmaddadp' then do
    src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])
    src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×TX+T].dword[0])
    src3 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
    v ←bfp_MULTIPLY_ADD(src1, src3, src2)
    rnd ←bfp_ROUND_TO_BFP64(0b0, FPSCR.RN, v)
    result ←bfp64_CONVERT_FROM_BFP(rnd)

    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    if vximz_flag=1 then SetFX(FPSCR.VXIMZ)
    if vxisi_flag=1 then SetFX(FPSCR.VXISI)
    if ox_flag=1 then SetFX(FPSCR.OX)
    if ux_flag=1 then SetFX(FPSCR.UX)
    if xx_flag=1 then SetFX(FPSCR.XX)

    vx_flag ←vxsnan_flag | vximz_flag | vxisi_flag
    vex_flag ←FPSCR.VE & vx_flag

    if vex_flag=0 then do
        VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000
        FPSCR.FPRF ←fprf_CLASS_BFP64(result)
        FPSCR.FR  ←inc_flag
        FPSCR.FI  ←xx_flag
    end else do
        FPSCR.FR  ←0b0
        FPSCR.FI  ←0b0
    end
end

This instruction performs a scalar multiply-add operation on double-precision floating-point values. Ensure that the VSX registers are properly aligned and initialized before use. The result is rounded according to the rounding mode specified in the FPSCR register. Be aware of potential exceptions such as NaNs, infinities, or underflows, which can set flags in the FPSCR.


VSX Scalar Multiply-Add Type-A Single-Precision

Summary: Performs a single-precision floating-point multiply-add operation.

For xsmaddasp, the double-precision floating-point value in doubleword element 0 of VSR[XA] is multiplied by the double-precision floating-point value in doubleword element 0 of VSR[XT], and then the result is added to the double-precision floating-point value in doubleword element 0 of VSR[XB]. The final result is normalized and rounded to single-precision format.

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])
src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×TX+T].dword[0])
src3 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
v ←bfp_MULTIPLY_ADD(src1, src3, src2)
rnd ←bfp_ROUND_TO_BFP32(FPSCR.RN, v)
result32 ←bfp32_CONVERT_FROM_BFP(rnd)
result64 ←bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vximz_flag=1 then SetFX(FPSCR.VXIMZ)
if vxisi_flag=1 then SetFX(FPSCR.VXISI)
if ox_flag=1 then SetFX(FPSCR.OX)
if ux_flag=1 then SetFX(FPSCR.UX)
if xx_flag=1 then SetFX(FPSCR.XX)
vx_flag ←vxsnan_flag | vximz_flag | vxisi_flag
vex_flag ←FPSCR.VE & vx_flag
if vex_flag=0 then do
  VSR[32×TX+T].dword[0] ←result64
  VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000
  FPSCR.FPRF ←fprf_CLASS_BFP32(result32)
  FPSCR.FR ←inc_flag
  FPSCR.FI ←xx_flag
else do
  FPSCR.FI ←0b0

See Table 7.10, “VSX Scalar Floating-Point Final Result,” on page 618.


Summary: Performs a quad-precision floating-point multiply-add operation with rounding to even.

This instruction multiplies two quad-precision floating-point numbers and adds the third number, rounding the result according to the specified mode.

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src1 ← bfp_CONVERT_FROM_BFP128(VSR[VRA+32])
src2 ← bfp_CONVERT_FROM_BFP128(VSR[VRT+32])
src3 ← bfp_CONVERT_FROM_BFP128(VSR[VRB+32])
v ← bfp_MULTIPLY_ADD(src1, src3, src2)
rnd ← bfp_ROUND_TO_BFP128(RO, FPSCR.RN, v)
result ← bfp128_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vximz_flag=1 then SetFX(FPSCR.VXIMZ)
if vxisi_flag=1 then SetFX(FPSCR.VXISI)
if ox_flag=1 then SetFX(FPSCR.OX)
if ux_flag=1 then SetFX(FPSCR.UX)
if xx_flag=1 then SetFX(FPSCR.XX)
vx_flag ← vxsnan_flag | vximz_flag | vxisi_flag
ex_flag ← FPSCR.VE & vx_flag
if ex_flag=0 then do
    VSR[VRT+32] ← result
    FPSCR.FPRF ← fprf_CLASS_BFP128(result)
end
FPSCR.FR ← (vx_flag=0) & inc_flag
FPSCR.FI ← (vx_flag=0) & xx_flag

This instruction is used for performing a multiply-add operation on quad-precision floating-point numbers. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. Be aware of rounding modes specified by FPSCR.RN and handle potential exceptions like VXSNAN, VXIMZ, Vxisi, OX, UX, and XX appropriately. The result is stored back into the destination register if no exceptions occur.


VSX Scalar Multiply-Subtract Type-A Double-Precision

Summary: Performs a double-precision floating-point multiply-subtract operation.

For xsmsubadp, the value in VSR[XA] is multiplied by the value in VSR[XT], and then the result is subtracted from the value in VSR[XB].

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])
src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×TX+T].dword[0])
src3 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
v ←bfp_MULTIPLY_ADD(src1, src3, bfp_NEGATE(src2))
rnd ←bfp_ROUND_TO_BFP64(0b0, FPSCR.RN, v)
result ←bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vximz_flag=1 then SetFX(FPSCR.VXIMZ)
if vxisi_flag=1 then SetFX(FPSCR.VXISI)
if ox_flag=1 then SetFX(FPSCR.OX)
if ux_flag=1 then SetFX(FPSCR.UX)
if xx_flag=1 then SetFX(FPSCR.XX)
vx_flag ←vxsnan_flag | vximz_flag | vxisi_flag
vex_flag ←FPSCR.VE & vx_flag
if vex_flag=0 then do
  VSR[32×TX+T].dword[0] ←result
  VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000
  FPSCR.FPRF ←fprf_CLASS_BFP64(result)
  FPSCR.FR ←inc_flag
  FPSCR.FI ←xx_flag
end else do
  FPSCR.FI ←0b0
end

This instruction is commonly used for performing complex floating-point arithmetic operations involving multiplication and subtraction. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. Be cautious of potential overflow or underflow conditions, as indicated by the FPSCR flags. The operation requires proper alignment of the input values, specifically 64-bit double-precision floating-point numbers.


VSX Scalar Multiply-Subtract Type-A Single-Precision

Summary: Performs a multiply-subtract operation on single-precision floating-point values.

For xmsubasp, the double-precision floating-point value in doubleword element 0 of VSR[XA] is multiplied by the double-precision floating-point value in doubleword element 0 of VSR[XB], and the result is subtracted from the double-precision floating-point value in doubleword element 0 of VSR[XT]. The result is then rounded to single-precision format and placed into doubleword element 0 of VSR[XT] in double-precision format.

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])
src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×TX+T].dword[0])
src3 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
v ←bfp_MULTIPLY_ADD(src1, src3, bfp_NEGATE(src2))
rnd ←bfp_ROUND_TO_BFP32(FPSCR.RN, v)
result32 ←bfp32_CONVERT_FROM_BFP(rnd)
result64 ←bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vximz_flag=1 then SetFX(FPSCR.VXIMZ)
if vxisi_flag=1 then SetFX(FPSCR.VXISI)
if ox_flag=1 then SetFX(FPSCR.OX)
if ux_flag=1 then SetFX(FPSCR.UX)
if xx_flag=1 then SetFX(FPSCR.XX)
vx_flag  ←vxsnan_flag | vximz_flag | vxisi_flag
vex_flag ←FPSCR.VE & vx_flag
if vex_flag=0 then do
    VSR[32×TX+T].dword[0] ←result64
    VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000
    FPSCR.FPRF ←fprf_CLASS_BFP32(result32)
    FPSCR.FR  ←inc_flag
    FPSCR.FI  ←xx_flag
else do
    FPSCR.FR  ←0b0
    FPSCR.FI  ←0b0

This instruction is commonly used for performing complex floating-point arithmetic operations in single-precision format while maintaining double-precision intermediate results. Ensure that the VSX (Vector Scalar Extensions) are enabled, as attempting to use this instruction without them will result in an unavailable exception. Be cautious of rounding modes and exceptions; check the FPSCR register for flags indicating overflow, underflow, or invalid operations. The instruction requires proper alignment of input values in VSR registers, specifically targeting doubleword elements.


VSX Scalar Multiply Subtract Add Pair Single Precision

Summary: Performs a multiply-subtract-add operation on single-precision floating-point values.

Performs a fused multiply-subtract-add operation on scalar single-precision floating-point values. The operation computes (XA × XB) - XT + implicit_addend and stores the result in XT. This MMA/VSX fusion instruction updates FPSCR with exception flags and follows IEEE 754 rounding semantics.

XT ← (XA × XB) - XT + (addend)
FPSCR ← updated with exception flags and rounding


VSX Scalar Multiply-Subtract Quad-Precision

Summary: Performs a multiply-subtract operation on quad-precision floating-point values.

Performs a scalar multiply-subtract operation on quad-precision floating-point values, computing VRT = VRT - (VRA × VRB). The result is rounded according to the current rounding mode in FPSCR. This instruction requires VSX support and updates FPSCR exception flags based on the operation result.

VRT[0:127] ← VRT[0:127] - (VRA[0:127] × VRB[0:127])
FPSCR ← update_exception_flags(FPSCR, result)

The xsmsubqp instruction is used for performing a multiply-subtract operation on quad-precision floating-point numbers. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid an exception. Be cautious of rounding modes and exceptions, as they can affect the result and set flags in the FPSCR register. This instruction operates on 128-bit aligned data in vector registers VSR[VRA+32], VSR[VRT+32], and VSR[VRB+32].


VSX Scalar Negative Multiply-Add Double-Precision Type-A

Summary: Performs a negative multiply-add operation on double-precision floating-point values.

For xsnmaddadp, the value in VSR[XA] is multiplied by the value in VSR[XB], and then the result is added to the value in VSR[XT]. The final result is negated and stored back into VSR[XT].

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])
src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×TX+T].dword[0])
src3 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
v ←bfp_MULTIPLY_ADD(src1, src3, src2)
rnd ←bfp_NEGATE(bfp_ROUND_TO_BFP64(0b0, FPSCR.RN, v))
result ←bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vximz_flag=1 then SetFX(FPSCR.VXIMZ)
if vxisi_flag=1 then SetFX(FPSCR.VXISI)
if ox_flag=1 then SetFX(FPSCR.OX)
if ux_flag=1 then SetFX(FPSCR.UX)
if xx_flag=1 then SetFX(FPSCR.XX)
vx_flag ←vxsnan_flag | vximz_flag | vxisi_flag
vex_flag ←FPSCR.VE & vx_flag
if vex_flag=0 then do
  VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000
  FPSCR.FPRF ←fprf_CLASS_BFP32(result)
  FPSCR.FI ←xx_flag
else do
  FPSCR.FR ←0b0
  FPSCR.FI ←0b0
end
VSR[32×TX+T].dword[0] ←result

This instruction is commonly used in applications requiring precise floating-point arithmetic, such as scientific computations and financial calculations. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking the MSR.VSX bit; otherwise, handle the VSX_Unavailable exception. Be cautious of potential exceptions like VXSNAN, VXIMZ, Vxisi, OX, UX, and XX, which can alter the FPSCR flags and affect program flow. The instruction operates on double-precision floating-point numbers and requires proper alignment of the input registers.


VSX Scalar Negative Multiply-Add Single-Precision Type-A

Summary: Performs a negative multiply-add operation on single-precision floating-point values.

For xsnmaddasp, the double-precision floating-point value in doubleword element 0 of VSR[XA] is multiplied by the double-precision floating-point value in doubleword element 0 of VSR[XB], and then added to the double-precision floating-point value in doubleword element 0 of VSR[XT]. The result is negated, rounded to single-precision format, and placed into doubleword element 0 of VSR[XT] in double-precision format.

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])
src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×TX+T].dword[0])
src3 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
v ←bfp_MULTIPLY_ADD(src1, src3, src2)
rnd ←bfp_NEGATE(bfp_ROUND_TO_BFP32(FPSCR.RN, v))
result32 ←bfp32_CONVERT_FROM_BFP(rnd)
result64 ←bfp64_CONVERT_FROM_BFP(rnd)
vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
vximz_flag=1 then SetFX(FPSCR.VXIMZ)
vxisi_flag=1 then SetFX(FPSCR.VXISI)
ox_flag=1 then SetFX(FPSCR.OX)
ux_flag=1 then SetFX(FPSCR.UX)
xx_flag=1 then SetFX(FPSCR.XX)
vx_flag  ←vxsnan_flag | vximz_flag | vxisi_flag
vex_flag ←FPSCR.VE & vx_flag
if vex_flag=0 then do
    VSR[32×TX+T].dword[0] ←result64
    VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000
    FPSCR.FPRF ←fprf_CLASS_BFP32(result32)
    FPSCR.FR  ←inc_flag
    FPSCR.FI  ←xx_flag
else do
    FPSCR.FR  ←0b0
    FPSCR.FI  ←0b0
end

See Table 7.32, “Scalar Floating-Point Final Result with Negation,” on page 669.


VSX Scalar Negative Multiply-Add Quad-Precision

Summary: Performs a negative multiply-add operation on quad-precision floating-point values.

Performs a scalar negative multiply-add operation on quad-precision floating-point values, computing VRT = -(VRA × VRB) + VRT. The result is rounded according to the current rounding mode in FPSCR. This instruction requires VSX support and updates FPSCR exception flags based on the operation result.

VRT[0:127] ← -(VRA[0:127] × VRB[0:127]) + VRT[0:127]
FPSCR ← update_exception_flags(FPSCR, result)

FPSCR FPRF FR FI FX VXSNAN VXIMZ VXISI OX UX XX

This instruction is used for performing a scalar negative multiply-add operation on quad-precision floating-point numbers. Ensure that the VSX feature is enabled in the MSR register to avoid exceptions. Be cautious of potential overflow and underflow conditions, as indicated by the OX and UX flags in the FPSCR register. The result is rounded according to the rounding mode specified in FPSCR.RN.


VSX Scalar Negative Multiply-Subtract Type-A Double-Precision

Summary: Performs a negative multiply-subtract operation on double-precision floating-point values.

For xsnmsubadp, the double-precision floating-point value in doubleword element 0 of VSR[XA] is multiplied by the double-precision floating-point value in doubleword element 0 of VSR[XT], and the result is added to the negated double-precision floating-point value in doubleword element 0 of VSR[XB]. The final result is normalized, rounded to double-precision using the rounding mode specified by RN, and placed into doubleword element 0 of VSR[XT] in double-precision format. Doubleword element 1 of VSR[XT] is set to 0.

if 'xsnmsubadp' then do
    src1 ← bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])
    src2 ← bfp_CONVERT_FROM_BFP64(VSR[32×TX+T].dword[0])
    src3 ← bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
end
v ← bfp_MULTIPLY_ADD(src1, src3, bfp_NEGATE(src2))
rnd ← bfp_NEGATE(bfp_ROUND_TO_BFP64(0b0, FPSCR.RN, v))
result ← bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vxisi_flag=1 then SetFX(FPSCR.VXISI)
if ux_flag=1 then SetFX(FPSCR.UX)
if xx_flag=1 then SetFX(FPSCR.XX)
vx_flag ← vxsnan_flag | vximz_flag | vxisi_flag
vex_flag ← FPSCR.VE & vx_flag
if vex_flag=0 then do
    VSR[32×TX+T].dword[0] ← result
    VSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000
    FPSCR.FPRF ← fprf_CLASS_BFP64(result)
    FPSCR.FR ← inc_flag
    FPSCR.FI ← xx_flag
end else do
    FPSCR.FR ← 0b0
    FPSCR.FI ← 0b0
end

This instruction is commonly used in applications requiring complex floating-point arithmetic, such as scientific computations and simulations. Ensure that the input values are properly aligned to avoid precision loss. The instruction operates at the user privilege level and may raise exceptions if invalid operations occur, such as division by zero or overflow. Performance can be optimized by ensuring that the VSX registers are preloaded with the necessary data.


VSX Scalar Negative Multiply-Subtract Type-A Single-Precision

Summary: Performs a negative multiply-subtract operation on single-precision floating-point values.

For xsnmsubasp, the double-precision floating-point value in doubleword element 0 of VSR[XA] is multiplied by the double-precision floating-point value in doubleword element 0 of VSR[XT], and then the result is negated and added to the double-precision floating-point value in doubleword element 0 of VSR[XB]. The final result is normalized, rounded to single-precision using the rounding mode specified by RN, negated, and placed into doubleword element 0 of VSR[XT] in double-precision format. Doubleword element 1 of VSR[XT] is set to 0.

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])
src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×TX+T].dword[0])
src3 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
v ←bfp_MULTIPLY_ADD(src1, src3, bfp_NEGATE(src2))
rnd ←bfp_NEGATE(bfp_ROUND_TO_BFP32(FPSCR.RN, v))
result32 ←bfp32_CONVERT_FROM_BFP(rnd)
result64 ←bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vximz_flag=1 then SetFX(FPSCR.VXIMZ)
if vxisi_flag=1 then SetFX(FPSCR.VXISI)
if ox_flag=1 then SetFX(FPSCR.OX)
if ux_flag=1 then SetFX(FPSCR.UX)
if xx_flag=1 then SetFX(FPSCR.XX)
vx_flag ←vxsnan_flag | vximz_flag | vxisi_flag
vex_flag ←FPSCR.VE & vx_flag
if vex_flag=0 then do
    VSR[32×TX+T].dword[0] ←result64
    VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000
    FPSCR.FPRF ←fprf_CLASS_BFP32(result32)
    FPSCR.FR  ←inc_flag
    FPSCR.FI  ←xx_flag
else do
    FPSCR.FI  ←0b0
end

This instruction is commonly used in applications requiring complex floating-point arithmetic, such as scientific computations and graphics processing. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking the MSR.VSX bit; otherwise, handle the VSX_Unavailable exception. Be cautious of potential exceptions like VXSNAN, VXIMZ, Vxisi, OX, UX, and XX, which can alter the FPSCR flags and affect program flow. The instruction operates on double-precision values but rounds the result to single-precision, so consider precision implications in your application.


VSX Scalar Negative Multiply-Subtract Quad-Precision

Summary: Performs a negative multiply-subtract operation on quad-precision floating-point values.

Performs a scalar negative multiply-subtract operation on quad-precision floating-point values, computing VRT = -(VRA × VRB) - VRT. The result is rounded according to the current rounding mode in FPSCR. This instruction requires VSX support and updates FPSCR exception flags based on the operation result.

VRT[0:127] ← -(VRA[0:127] × VRB[0:127]) - VRT[0:127]
FPSCR ← update_exception_flags(FPSCR, result)

FPSCR, VXSNAN, VXIMZ, Vxisi, OX, UX, XX, FPRF, FR, FI

The xsnmsubqp instruction is used for performing a scalar negative multiply-subtract operation on quad-precision floating-point numbers. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. Be cautious of potential overflow and underflow conditions, as indicated by the exception flags in FPSCR. The result is rounded using round-to-nearest mode by default.


Vector Scalar Reciprocal Estimate Double Precision

Summary: Estimates the reciprocal of a double-precision floating-point value.

Computes an estimate of the reciprocal (1/XB) for a double-precision floating-point scalar value, placing the result in XT. The estimate is accurate to about 15 bits of precision. This instruction requires VSX support and may update FPSCR exception flags if the source is invalid or zero.

XT[0:63] ← reciprocal_estimate(XB[0:63])
FPSCR ← update_exception_flags(FPSCR, result)

FPSCR.FR, FPSCR.FPRF, FPSCR.FI, FPSCR.VXSNAN, FPSCR.OX, FPSCR.UX, FPSCR.ZX


VSX Scalar Reciprocal Estimate Single-Precision

Summary: Estimates the reciprocal of a single-precision floating-point value.

Computes an estimate of the reciprocal (1/XB) for a single-precision floating-point scalar value, placing the result in XT. The estimate is accurate to about 7 bits of precision. This instruction requires VSX support and may update FPSCR exception flags if the source is invalid or zero.

XT[32:63] ← reciprocal_estimate(XB[32:63])
FPSCR ← update_exception_flags(FPSCR, result)

Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register.


Double-Precision XX2-form Scalar Reciprocal Square Root Estimate

Summary: Estimates the reciprocal square root of a double-precision floating-point value.

The instruction estimates the reciprocal square root of the double-precision floating-point value in doubleword element 0 of VSR[XB] and places the result into doubleword element 0 of VSR[XT]. Doubleword element 1 of VSR[XT] is set to 0.

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src ← bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
v ← bfp_RECIPROCAL_SQUARE_ROOT_ESTIMATE(src)
rnd ← bfp_ROUND_TO_BFP64(0b0, FPSCR.RN, v)
result ← bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vxsqrt_flag=1 then SetFX(FPSCR.VXSQRT)
if zx_flag=1 then SetFX(FPSCR.ZX)
vx_flag ← vxsnan_flag | vxsqrt_flag
vex_flag ← FPSCR.VE & vx_flag
zex_flag ← FPSCR.ZE & zx_flag
if vex_flag=0 & zex_flag=0 then do
    VSR[32×TX+T].dword[0] ← result
    VSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000
    FPSCR.FPRF ← fprf_CLASS_BFP64(result)
    FPSCR.FR ← 0bU
    FPSCR.FI ← 0bU
end


VSX Scalar Reciprocal Square Root Estimate (Single-Precision)

Summary: Estimates the reciprocal square root of a single-precision floating-point value.

The instruction estimates the reciprocal square root of a single-precision floating-point value in doubleword element 0 of VSR[XB] and places the result into doubleword element 0 of VSR[XT]. Doubleword element 1 of VSR[XT] is set to 0.

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src ← bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
v ← bfp_RECIPROCAL_SQUARE_ROOT_ESTIMATE(src)
rnd ← bfp_ROUND_TO_BFP32(FPSCR.RN, v)
result32 ← bfp32_CONVERT_FROM_BFP(rnd)
result64 ← bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vxsqrt_flag=1 then SetFX(FPSCR.VXSQRT)
if ox_flag=1 then SetFX(FPSCR.OX)
if ux_flag=1 then SetFX(FPSCR.UX)
if 0bU then SetFX(FPSCR.XX)
if zx_flag=1 then SetFX(FPSCR.ZX)
vx_flag ← vxsnan_flag | vxsqrt_flag
vex_flag ← FPSCR.VE & vx_flag
zex_flag ← FPSCR.ZE & zx_flag
if vex_flag=0 & zex_flag=0 then do
    VSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000
    FPSCR.FPRF ← fprf_CLASS_BFP32(result32)
    FPSCR.FR ← 0bU
    FPSCR.FI ← 0bU
else do
    FPSCR.FR ← 0b0
    FPSCR.FI ← 0b0
end

FPSCR (FPRF, FX, OX, UX, ZX, VXSNAN, VXSQRT, FR, FI, XX)


VSX Scalar Test for software Divide Double-Precision

Summary: Performs a double-precision floating-point division and sets condition flags based on the result.

Tests for special cases in double-precision floating-point division (such as division by zero or invalid operands) and sets a condition register field with the result. No actual division is performed; instead, the instruction is used to check operand validity before software performs the division. This instruction requires VSX support.

BF ← test_division(XA[0:63], XB[0:63])
CR[BF:BF+3] ← BF

The xstdivdp instruction is used for performing double-precision floating-point division and setting condition flags based on various error conditions or special cases. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking the MSR.VSX bit; otherwise, a VSX_Unavailable exception will be raised. Be cautious of division by zero, overflow, underflow, and NaN/Infinity values, as these can set specific condition flags in the CR register.


VSX Scalar Test for software Square Root, Double-Precision

Summary: Tests the double-precision floating-point value in VSR[XB] and sets condition register field BF based on various flags.

The instruction tests the double-precision floating-point value in VSR[XB].dword[0] and sets CR.field[BF] based on flags fe_flag, fg_flag, and fl_flag.

if MSR.VSX=0 then
    VSX_Unavailable()
src ← VSR[32×XB+B].dword[0]
e_b ← src.bit[1:11] - 1023
fe_flag ← IsNaN(src) | IsInf(src) | IsZero(src) |
           IsNeg(src) | (e_b <= -970)
fg_flag ← IsInf(src) | IsZero(src) | IsDen(src)
fl_flag ← xsrsqrtedp_error() <= 2-14
CR.field[BF] ← 0b1 || fg_flag || fe_flag || 0b0

This instruction is used to test a double-precision floating-point value for special conditions like NaN, infinity, zero, and denormal numbers. It sets the condition register field based on these flags. Ensure VSX is enabled in the MSR; otherwise, an exception will be raised. The instruction does not require any specific alignment or privilege level.


Vector Multiply-Add Single-Precision Type-A

Summary: Performs a single-precision floating-point multiply-add operation on vector elements.

Performs a vector multiply-add operation on single-precision floating-point elements, computing XT = XT + (XA × XB) for each element. The operation is fused, rounding only once at the end. This instruction requires VSX support and updates FPSCR exception flags based on the operation results.

The xvmaddasp instruction is commonly used for performing vectorized single-precision floating-point multiply-add operations. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid a VSX_Unavailable exception. Be cautious of potential exceptions such as VXSNAN, VXIMZ, Vxisi, OX, UX, and XX, which can be set based on the operation's result and FPSCR settings. The instruction operates on 128-bit vectors, so ensure proper alignment for optimal performance.


VSX Vector Multiply-Subtract Type-A Double-Precision

Summary: Performs a double-precision floating-point multiply-subtract operation on vector elements.

Performs a vector multiply-subtract operation on double-precision floating-point elements, computing XT = XT - (XA × XB) for each element. The operation is fused, rounding only once at the end. This instruction requires VSX support and updates FPSCR exception flags based on the operation results.

The xvmsubadp instruction is commonly used for complex floating-point arithmetic operations involving multiplication, subtraction, and addition. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid a VSX_Unavailable exception. Be cautious of potential exceptions such as VXSNAN, VXIMZ, VXISI, OX, UX, and XX, which can be triggered by invalid operations or overflow conditions. The instruction operates on double-precision floating-point numbers and requires proper alignment of the input vectors.


VSX Vector Multiply-Subtract Type-A Single-Precision

Summary: Performs a vector multiply-subtract operation on single-precision floating-point values.

Performs a single-precision floating-point multiply-subtract operation (XT ← (XA × XB) - XT) on vector elements using the Type-A fused operation. This VSX instruction operates on two 128-bit vector registers, each containing four single-precision floating-point elements. The instruction does not affect condition registers or status flags; rounding behavior follows the FPSCR settings.

The xvmsubasp instruction is commonly used for vectorized floating-point operations, particularly in scientific computing and graphics processing. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking the MSR.VSX bit; otherwise, a VSX_Unavailable exception will be raised. Be cautious of alignment requirements for vector registers to avoid performance penalties or exceptions. This instruction operates at user privilege level but can generate various floating-point exceptions based on the FPSCR settings, which should be handled appropriately in error-checking code.


Vector Negative Multiply-Add Type-A Double-Precision

Summary: Performs a negative multiply-add operation on double-precision floating-point elements.

For xvnmaddadp, for each integer value i from 0 to 1, the following operations are performed: src1 is multiplied by src3, then src2 is added to the product. The result is normalized and rounded to double precision using the rounding mode specified by RN. The final result is negated and placed into VSR[XT].

if MSR.VSX=0 then VSX_Unavailable()

ex_flag ←0b0
do i = 0 to 1
    reset_xflags()
    src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[i])
    src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×TX+T].dword[i])
    src3 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])

    v   ←bfp_MULTIPLY_ADD(src1,src3,src2)
    rnd ←bfp_NEGATE(bfp_ROUND_TO_BFP64(FPSCR.RN,v))
    vresult.dword[i] ←bfp64_CONVERT_FROM_BFP(rnd)

    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    if vximz_flag=1 then SetFX(FPSCR.VXIMZ)
    if vxisi_flag=1 then SetFX(FPSCR.VXISI)
    if ox_flag=1 then SetFX(FPSCR.OX)
    if ux_flag=1 then SetFX(FPSCR.UX)
    if xx_flag=1 then SetFX(FPSCR.XX)

    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vximz_flag) | (FPSCR.VE & vxisi_flag) | (FPSCR.OE & ox_flag) | (FPSCR.UE & ux_flag) | (FPSCR.XE & xx_flag)
end

if ex_flag=0 then VSR[32×TX+T] ←vresult

This instruction performs vectorized negative multiply-add operations on double-precision floating-point numbers. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. Be cautious with rounding modes specified by FPSCR.RN, as they can affect precision and performance. Handle exceptions properly by checking the VXSNAN, VXIMZ, Vxisi, OX, UX, and XX flags after execution.


Vector Negative Multiply-Add Single-Precision Type-A

Summary: Performs a negative multiply-add operation on single-precision floating-point elements.

Performs a negative multiply-add operation on single-precision floating-point vector elements (XT ← -(XA × XB) + XT) using Type-A fused arithmetic. This VSX instruction operates on 128-bit vector registers each containing four single-precision values. The operation does not affect condition registers; rounding and exception behavior follows FPSCR settings.

This instruction is commonly used in vectorized floating-point computations where negative multiplication and addition are required. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking MSR.VSX before using this instruction. Be aware of potential exceptions such as NaNs, infinities, or underflows, which can set flags in FPSCR and may trigger exceptions based on the current settings.


VSX Vector Negative Multiply-Subtract Type-A Double-Precision

Summary: Performs a negative multiply-subtract operation on double-precision floating-point elements.

For each integer value i from 0 to 1, the instruction performs the following operations: multiplies src1 by src3, negates src2, adds the result to the product, normalizes the sum, rounds it to double precision, and places the final result into VSR[XT].

if MSR.VSX=0 then VSX_Unavailable()

ex_flag ←0b0
do i = 0 to 1
    reset_xflags()
    src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[i])
    src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×TX+T].dword[i])
    src3 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])

    v   ←bfp_MULTIPLY_ADD(src1,src3,bfp_NEGATE(src2))
    rnd ←bfp_NEGATE(bfp_ROUND_TO_BFP64(FPSCR.RN,v))
    vresult.dword[i] ←bfp64_CONVERT_FROM_BFP(rnd)

    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    if vximz_flag=1 then SetFX(FPSCR.VXIMZ)
    if vxisi_flag=1 then SetFX(FPSCR.VXISI)
    if ox_flag=1 then SetFX(FPSCR.OX)
    if ux_flag=1 then SetFX(FPSCR.UX)
    if xx_flag=1 then SetFX(FPSCR.XX)

    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vximz_flag) | (FPSCR.VE & vxisi_flag) | (FPSCR.OE & ox_flag) | (FPSCR.UE & ux_flag) | (FPSCR.XE & xx_flag)
end

if ex_flag=0 then VSR[32×TX+T] ←vresult

This instruction is used for performing vectorized negative multiply-subtract operations on double-precision floating-point numbers. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. Be cautious of potential overflow and underflow conditions, as indicated by the exception flags. The operation processes two elements at a time, so ensure your data is correctly aligned for optimal performance.


VSX Vector Negative Multiply-Subtract Type-A Single-Precision

Summary: Performs a negative multiply-subtract operation on single-precision floating-point elements.

For xvnmsubasp, for each integer value i from 0 to 3, the following operations are performed: src1 is multiplied by src3, producing a product having unbounded range and precision. src2 is negated and added to the product, producing a sum having unbounded range and precision. The sum is normalized. The intermediate result is rounded to single-precision using the rounding mode specified by RN. The result is negated and placed into word element i of VSR[XT] in single-precision format.

if MSR.VSX=0 then VSX_Unavailable()
ex_flag ←0b0
do i = 0 to 3
    reset_xflags()
    src1 ←bfp_CONVERT_FROM_BFP32(VSR[32×AX+A].word[i])
    src2 ←bfp_CONVERT_FROM_BFP32(VSR[32×TX+T].word[i])
    src3 ←bfp_CONVERT_FROM_BFP32(VSR[32×BX+B].word[i])
    v   ←bfp_MULTIPLY_ADD(src1,src3,bfp_NEGATE(src2))
    rnd ←bfp_NEGATE(bfp_ROUND_TO_BFP32(FPSCR.RN,v))
    vresult.word[i] ←bfp32_CONVERT_FROM_BFP(rnd)
    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    if vximz_flag=1 then SetFX(FPSCR.VXIMZ)
    if vxisi_flag=1 then SetFX(FPSCR.VXISI)
    if ox_flag=1 then SetFX(FPSCR.OX)
    if ux_flag=1 then SetFX(FPSCR.UX)
    if xx_flag=1 then SetFX(FPSCR.XX)
    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vximz_flag) | (FPSCR.VE & vxisi_flag) | (FPSCR.OE & ox_flag) | (FPSCR.UE & ux_flag) | (FPSCR.XE & xx_flag)
end
if ex_flag=0 then VSR[32×TX+T] ←vresult

This instruction performs a vectorized negative multiply-subtract operation on single-precision floating-point numbers. Ensure that the VSX feature is enabled in the MSR register to avoid exceptions. Be cautious with rounding modes specified by FPSCR.RN, as they can affect precision and performance. Handle exceptions properly by checking the VXSNAN, VXIMZ, Vxisi, OX, UX, and XX flags after execution.


Vector Reciprocal Estimate Double-Precision

Summary: A double-precision floating-point estimate of the reciprocal of src is placed into doubleword element i of VSR[XT] in double-precision format.

Unless the reciprocal of src would be a zero, an infinity, or a QNaN, the estimate has a relative error in precision no greater than one part in 16384 of the reciprocal of src.

if MSR.VSX=0 then VSX_Unavailable()

reset_xflags()
vresult = bfp_RECIPROCAL_ESTIMATE(VSR[32×BX+B].dword[i])
rnd = bfp_ROUND_TO_BFP64(0b0, FPSCR.RN, vresult)
vresult.word[i] = bfp64_CONVERT_FROM_BFP(rnd)

if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if ox_flag=1 then SetFX(FPSCR.OX)
if ux_flag=1 then SetFX(FPSCR.UX)
if zx_flag=1 then SetFX(FPSCR.ZX)
ex_flag = ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.OE & ox_flag) | (FPSCR.UE & ux_flag) | (FPSCR.ZE & zx_flag)

if ex_flag=0 then VSR[32×TX+T] ←vresult

The xvredp instruction is used to estimate the reciprocal of a double-precision floating-point number with high precision. It's important to ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register, otherwise, an exception will be raised. Developers should also handle exceptions by checking the FPSCR flags for overflow (OX), underflow (UX), zero divide (ZX), and invalid operation (VXSNAN).


Vector Reciprocal Estimate Single-Precision

Summary: Estimates the reciprocal of single-precision floating-point values in a vector.

A single-precision floating-point estimate of the reciprocal of src is placed into word element i of VSR[XT] in single-precision format. Unless the reciprocal of src would be a zero, an infinity, or a QNaN, the estimate has a relative error in precision no greater than one part in 16384 of the reciprocal of src.

if MSR.VSX=0 then VSX_Unavailable()
ex_flag ←0b0
reset_xflags()
do i = 0 to 3
    src ←bfp_CONVERT_FROM_BFP32(VSR[32×BX+B].word[i])
    rnd ←bfp_ROUND_TO_BFP32(FPSCR.RN,v)
    vresult.word[i] ←bfp32_CONVERT_FROM_BFP(rnd)
    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    if ox_flag=1 then SetFX(FPSCR.OX)
    if ux_flag=1 then SetFX(FPSCR.UX)
    if zx_flag=1 then SetFX(FPSCR.ZX)
    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.OE & ox_flag) | (FPSCR.UE & ux_flag) | (FPSCR.ZE & zx_flag)
end
if ex_flag=0 then VSR[32×TX+T] ←vresult

The xvresp instruction is used to estimate the reciprocal of single-precision floating-point numbers in vector registers. It's important to ensure that the VSX (Vector Scalar Extensions) are enabled, as attempting to use this instruction when they are not will result in an exception. The instruction handles NaNs and infinities by setting appropriate flags in the FPSCR register, but developers should be cautious of potential precision loss due to the estimation process.


Vector Reciprocal Square Root Estimate Double-Precision

Summary: Estimates the reciprocal square root of double-precision floating-point values in vector registers.

This instruction estimates the reciprocal square root of each element in a double-precision floating-point vector and stores the result in another vector register. The estimate has a relative error no greater than one part in 16384 of the reciprocal of the square root of the source value.

if MSR.VSX=0 then VSX_Unavailable()

ex_flag ←0b0

do i = 0 to 1
    reset_xflags()
    src ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])
    v   ←bfp_RECIPROCAL_SQUARE_ROOT_ESTIMATE(src)
    rnd ←bfp_ROUND_TO_BFP64(0b0,FPSCR.RN,v)
    vresult.dword[i] ←bfp64_CONVERT_FROM_BFP(rnd)
    if vxsqrt_flag=1 then SetFX(FPSCR.VXSQRT)
    if zx_flag=1 then SetFX(FPSCR.ZX)
    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN) if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
end

if ex_flag=0 then VSR[32×TX+T] ←vresult

The xvrsqrtedp instruction is used to estimate the reciprocal square root of each element in a double-precision floating-point vector. It requires VSX (Vector Scalar Extensions) to be enabled, otherwise, it will raise an exception. The result has a relative error no greater than one part in 16384. Be cautious with special values like NaNs or zeros, as they can trigger exceptions and set specific flags in the FPSCR register.


VSX Vector Reciprocal Square Root Estimate Single-Precision

Summary: Estimates the reciprocal square root of single-precision floating-point values in a vector.

The instruction estimates the reciprocal square root of each element in the source vector and stores the result in the target vector. The estimate has a relative error no greater than one part in 16384 of the reciprocal of the square root of the source value.

if MSR.VSX=0 then VSX_Unavailable()

ex_flag ←0b0

do i = 0 to 3
    reset_xflags()
    src ←bfp_CONVERT_FROM_BFP32(VSR[32×BX+B].word[i])
    v   ←bfp_RECIPROCAL_SQUARE_ROOT_ESTIMATE(src)
    rnd ←bfp_ROUND_TO_BFP32(FPSCR.RN,v)
    vresult.word[i] ←bfp32_CONVERT_FROM_BFP(rnd)
    if vxsqrt_flag=1 then SetFX(FPSCR.VXSQRT)
    if zx_flag=1 then SetFX(FPSCR.ZX)
end

if ex_flag=0 then VSR[32×TX+T] ←vresult

The xvrsqrtesp instruction is commonly used for fast reciprocal square root estimation in single-precision floating-point operations. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking and setting the MSR.VSX bit. Be aware of potential exceptions such as VXSNAN or VXSQRT, which can be handled by examining the FPSCR register flags. The instruction operates on 4-element vectors, so ensure proper alignment and ordering of data for accurate results.


Vector Test for software Divide Double-Precision

Summary: Performs a double-precision floating-point division on vector elements and sets condition flags based on the results.

Tests whether a double-precision floating-point divide operation would be valid for each vector element and sets bits in the specified condition register field accordingly. This VSX instruction compares operands in XA and XB (two double-precision values per 128-bit register) against division validity conditions (divide-by-zero, invalid operands, etc.). The condition register field BF is set to reflect the test results; no other registers are modified.

for i in 0 to 1 do
  quotient_valid ← test_divide_conditions(XA[i], XB[i])
  CR[BF] ← (quotient_valid, 0, 0, 0)
end for

The xvtdivdp instruction is used for performing double-precision floating-point division on vector elements. It sets condition flags based on the results, which can be useful for error checking and conditional operations. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. Be cautious of division by zero and other special cases like NaNs or infinities, as these will set specific condition flags.


VSX Vector Test for software Divide Single-Precision XX3-form

Summary: Performs a vectorized single-precision floating-point division test.

Tests whether a single-precision floating-point divide operation would be valid for each vector element and sets the specified condition register field based on the results. This VSX instruction examines operands in XA and XB (four single-precision values per 128-bit register) for division validity conditions such as divide-by-zero or invalid operands. The condition register field BF is updated to reflect test outcomes; no other state is modified.

for i in 0 to 3 do
  quotient_valid ← test_divide_conditions(XA[i], XB[i])
  CR[BF] ← (quotient_valid, 0, 0, 0)
end for

The xvtdivsp instruction is used for vectorized single-precision floating-point division testing. It sets condition register flags based on the results of dividing elements from two VSX registers. Ensure that the VSX facility is enabled (MSR.VSX=1) before using this instruction. Be cautious with NaNs, infinities, and zero values in the operands, as they can trigger special flag conditions. The instruction operates on 4-element vectors, so ensure proper alignment of data in the VSX registers.


Vector Test for software Square Root, Double-Precision

Summary: Tests the double-precision floating-point operands in VSR[XB] and sets condition register field BF based on certain conditions.

This instruction tests each of the two double-precision floating-point elements in VSR[XB] and updates the condition register field BF accordingly. It checks for NaN, infinity, zero, negative values, and denormalized values, setting flags fe_flag and fg_flag based on these conditions.

if MSR.VSX=0 then
    VSX_Unavailable()

fe_flag ←0b0
fg_flag ←0b0

do i = 0 to 1
    src    ←VSR[32×BX+B].dword[i]
    e_b    ←src.bit[1:11] - 1023
    fe_flag ←fe_flag |
               IsNaN(src) | IsInf(src)  |
               IsZero(src) | IsNeg(src) |
               (e_a <= -970)
    fg_flag ←fg_flag |
               IsInf(src) | IsZero(src) | IsDen(src)
end

fl_flag ←xvrsqrtedp_error() <= 2-14
CR.field[BF] ←0b1 || fg_flag || fe_flag || 0b0

The xvtsqrtdp instruction is used to test double-precision floating-point elements for various conditions like NaN, infinity, zero, negative values, and denormalized values. It updates the condition register (CR) with flags indicating these conditions. Ensure that VSX is enabled in the MSR before using this instruction; otherwise, a VSX_Unavailable exception will occur. The instruction does not require specific alignment for its operands.


VSX Vector Test for software Square Root, Single-Precision

Summary: Tests each element of a vector for conditions related to square root operations.

Tests whether a square root operation would be valid for each single-precision floating-point vector element and sets the specified condition register field accordingly. This VSX instruction examines the four single-precision values in XB against square root validity conditions (e.g., negative operands). The condition register field BF is set to reflect the test outcome; no other registers are modified.

for i in 0 to 3 do
  sqrt_valid ← test_sqrt_conditions(XB[i])
  CR[BF] ← (sqrt_valid, 0, 0, 0)
end for

The xvtsqrtsp instruction is used to test each element of a vector for NaN, infinity, zero, negative values, and underflow conditions. It sets the condition register based on these tests. Ensure that VSX is enabled in the MSR before using this instruction; otherwise, it will raise an exception. The instruction does not require specific alignment but must be executed at a privilege level where VSX is available.


VSX Scalar Compare Ordered Quad-Precision

Summary: Compares two quad-precision floating-point values and updates the condition register.

The instruction compares the contents of VSR[VRA+32] (src1) and VSR[VRB+32] (src2) represented in quad-precision format. The comparison results are stored in the CR field BF and FPSCR fields FL, FG, FE, and FU.

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src1 ←bfp_CONVERT_FROM_BFP128(VSR[VRA+32])
src2 ←bfp_CONVERT_FROM_BFP128(VSR[VRB+32])
if src1.class.SNaN=1 | src2.class.SNaN=1 then do
    vxsnan_flag ←0b1
    if FPSCR.VE=0 then vxvc_flag ←0b1
end else
    vxvc_flag ←src1.class.QNaN | src2.class.QNaN
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vxvc_flag=1   then SetFX(FPSCR.VXVC)
CR.bit[4×BF+32] ←FPSCR.FL ←src1 < src2
CR.bit[4×BF+33] ←FPSCR.FG ←src1 > src2
CR.bit[4×BF+34] ←FPSCR.FE ←src1 = src2
CR.bit[4×BF+35] ←FPSCR.FU ←src1.class.SNaN | src1.class.QNaN | src2.class.SNaN | src2.class.QNaN

This instruction is used for comparing two quad-precision floating-point numbers. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid an exception. Be cautious with NaN values, as they can trigger exceptions and set specific flags in FPSCR. The comparison results update both the CR field and FPSCR fields, so always check these registers after execution for proper handling of unordered comparisons or exceptions.


VSX Scalar Compare Equal Double-Precision

Summary: Compares two double-precision floating-point values and sets the target vector register based on equality.

The instruction compares the double-precision floating-point values in the specified source vector registers. If either value is a SNaN, an Invalid Operation exception occurs. The result of the comparison is stored in the target vector register.

if MSR.VSX=0 then VSX_Unavailable()
src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])
src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
vxsnan_flag ←src1.class.SNaN | src2.class.SNaN
vex_flag ←FPSCR.VE & vxsnan_flag
if vxsnan_flag=1 SetFX(FPSCR.VXSNAN)
if vex_flag=0 then do
    if src1=src2 then
        VSR[32×TX+T].dword[0] ←0xFFFF_FFFF_FFFF_FFFF
        VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000
    else do
        VSR[32×TX+T].dword[0] ←0x0000_0000_0000_0000
        VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000
    end
end

xscmpeqdp can be used to implement the C/C++/Java conditional operation, RESULT = (x=y) ? a:b.
xscmpeqdp   fEQ,fX,fY
xxsel       fRESULT,fA,fB,fEQ


VSX Scalar Compare Equal Quad-Precision X-form

Summary: Compares two quad-precision floating-point values and sets the target vector register to all 1s if they are equal, otherwise all 0s.

The instruction compares the quad-precision floating-point values in VSR[VRA+32] and VSR[VRB+32]. If either value is a SNaN, an Invalid Operation exception occurs. The contents of VSR[VRT+32] are set to all 1s if the values are equal, otherwise all 0s.

src1 ← bfp_CONVERT_FROM_BFP128(VSR[VRA+32])
src2 ← bfp_CONVERT_FROM_BFP128(VSR[VRB+32])
vxsnan_flag ← src1.class.SNaN | src2.class.SNaN
vex_flag ← FPSCR.VE & vxsnan_flag
if vxsnan_flag=1 SetFX(FPSCR.VXSNAN)
if vex_flag=0 then do
   if bfp_COMPARE_EQ(src1, src2)=1 then
      VSR[VRT+32] ← 0xFFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF
   else
      VSR[VRT+32] ← 0x0000_0000_0000_0000_0000_0000_0000_0000

xscmpeqqp can be used to implement the C/C++ conditional operation, RESULT = (x=y) ? a : b.
xscmpeqqp   vEQ,vX,vY
xxsel       vRESULT,vA,vB,vEQ


VSX Scalar Compare Greater Than or Equal (Double-Precision)

Summary: Compares two double-precision floating-point values and sets the target vector register based on the comparison result.

The instruction compares the double-precision floating-point value in doubleword 0 of VSR[XA] with the double-precision floating-point value in doubleword 0 of VSR[XB]. If the first value is greater than or equal to the second, it sets the target vector register's doubleword 0 to 0xFFFF_FFFF_FFFF_FFFF and doubleword 1 to 0x0000_0000_0000_0000. Otherwise, both doublewords are set to 0x0000_0000_0000_0000.

if MSR.VSX=0 then VSX_Unavailable()

src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])
src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])

if src1.class.SNaN=1 | src2.class.SNaN=1 then do
   vxsnan_flag ←0b1
   if FPSCR.VE=0 then vxvc_flag ←0b1
end else
   vxvc_flag ←src1.class.QNaN | src2.class.QNaN
vex_flag ←FPSCR.VE & (vxsnan_flag | vxvc_flag)

if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vxvc_flag=1   then SetFX(FPSCR.VXVC)

if vex_flag=0 then do
   if src1 >= src2 then
      VSR[32×TX+T].dword[0] ←0xFFFF_FFFF_FFFF_FFFF
      VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000
   end else do
      VSR[32×TX+T].dword[0] ←0x0000_0000_0000_0000
      VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000
   end
end

xscmpgedp can be used to implement the C/C++/Java conditional operation, RESULT = (x>=y) ? a : b.
xscmpgedp   fGE,fX,fY
xxsel       fRESULT,fA,fB,fGE

xscmpgedp can also be used to implement the C/C++/Java conditional operation, RESULT = (x<=y) ? a : b.
xscmpgedp   fLE,fY,fX
xxsel       fRESULT,fA,fB,fLE


VSX Scalar Compare Greater Than or Equal Quad-Precision

Summary: Compares two quad-precision floating-point values and sets the target register based on the comparison.

The instruction compares the quad-precision floating-point value in VSR[VRA+32] with the value in VSR[VRB+32]. If the first value is greater than or equal to the second, VSR[VRT+32] is set to all 1s; otherwise, it is set to all 0s. Special handling is provided for NaN and QNaN values.

if MSR.VSX=0 then VSX_Unavailable()
src1 ←bfp_CONVERT_FROM_BFP128(VSR[VRA+32])
src2 ←bfp_CONVERT_FROM_BFP128(VSR[VRB+32])
if src1.class.SNaN=1 | src2.class.SNaN=1 then do
   vxsnan_flag ←0b1
   if FPSCR.VE=0 then vxvc_flag ←0b1
end
else
   vxvc_flag ←src1.class.QNaN | src2.class.QNaN
vex_flag ←FPSCR.VE & (vxsnan_flag | vxvc_flag)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vxvc_flag=1   then SetFX(FPSCR.VXVC)
if vex_flag=0 then do
   if bfp_COMPARE_GE(src1, src2)=1 then
      VSR[VRT+32] ← 0xFFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF
   else
      VSR[VRT+32] ← 0x0000_0000_0000_0000_0000_0000_0000_0000
end

xscmpgeqp can be used to implement the C/C++ conditional operation, RESULT = (x>=y) ? a : b.
xscmpgeqp   vGE,vX,vY
xxsel       vRESULT,vA,vB,vGE
xscmpgeqp can also be used to implement the C/C++ conditional operation, RESULT = (x<=y) ? a : b.
xscmpgeqp   vLE,vY,vX
xxsel       vRESULT,vA,vB,vLE


VSX Scalar Compare Greater Than Double-Precision

Summary: Compares two double-precision floating-point values and sets the target vector register based on the comparison.

Compares the double-precision floating-point value in the scalar portion of XA with that in XB and sets the corresponding elements in XT to all 1s (true) or all 0s (false) based on whether XA > XB. This VSX scalar instruction operates on the preferred slot (upper doubleword) of the registers. The comparison does not set condition registers but produces a vector result; quiet NaN operands compare as false without signaling.

if XA[0] > XB[0] then
  XT[0] ← 0xFFFFFFFFFFFFFFFF
else
  XT[0] ← 0x0000000000000000
end if
XT[1] ← undefined

xscmpgtdp can be used to implement the C/C++/Java conditional operation, RESULT = (x>y) ? a : b.
xscmpgtdp   fGT,fX,fY
xxsel       fRESULT,fA,fB,fGT
xscmpgtdp can also be used to implement the C/C++/Java conditional operation, RESULT = (x<y) ? a : b.
xscmpgtdp   fLT,fY,fX
xxsel       fRESULT,fA,fB,fLT


VSX Scalar Compare Greater Than Quad-Precision X-form

Summary: Compares two quad-precision floating-point values and sets the target vector register to all 1s if the first value is greater than the second, otherwise all 0s.

The instruction compares the contents of VSR[VRA+32] (src1) with the contents of VSR[VRB+32] (src2). If src1 is greater than src2, VSR[VRT+32] is set to all 1s; otherwise, it is set to all 0s. NaN comparisons result in false for the predicate.

if MSR.VSX=0 then VSX_Unavailable()
src1 ←bfp_CONVERT_FROM_BFP128(VSR[VRA+32])
src2 ←bfp_CONVERT_FROM_BFP128(VSR[VRB+32])
vxsnan_flag ←0b0
vxvc_flag ←src1.class.QNaN | src2.class.QNaN
vex_flag ←FPSCR.VE & (vxsnan_flag | vxvc_flag)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vxvc_flag=1   then SetFX(FPSCR.VXVC)
if vex_flag=0 then do
    if bfp_COMPARE_GT(src1, src2)=1 then
        VSR[VRT+32] ← 0xFFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF
    else
        VSR[VRT+32] ← 0x0000_0000_0000_0000_0000_0000_0000_0000
end

xscmpgtqp can be used to implement the C/C++ conditional operation, RESULT = (x>y) ? a : b.
xscmpgtqp   vGT,vX,vY
xxsel       vRESULT,vA,vB,vGT
xscmpgtqp can also be used to implement the C/C++ conditional operation, RESULT = (x<y) ? a : b.
xscmpgtqp   vLT,vY,vX
xxsel       vRESULT,vA,vB,vLT


VSX Scalar Round Quad-Precision to Extended-Precision

Summary: Rounds a quad-precision floating-point value to extended-precision.

Rounds a quad-precision floating-point value to extended-precision format, placing the result in the upper half of the target VSX register. This VSX instruction requires the quad-precision operand in the upper half of VRB and uses the rounding mode specified by RMC. The operation affects FPSCR status flags (inexact, underflow, overflow, invalid) and the R bit controls whether the result is placed in the target (R=0) or returned for testing (R=1).

rounding_mode ← (RMC == 0) ? FPSCR[RN] : RMC
VRT[0] ← round_quad_to_extended(VRB[0], rounding_mode)
if R == 1 then
  return VRT[0] for condition register testing
end if

The xsrqpxp instruction is used to round a quad-precision floating-point number to extended-precision format. Ensure that the VSX facility is enabled by checking MSR.VSX before using this instruction. The rounding mode is determined by the RMC field and can be overridden by the FPSCR.RN setting when R=0. Be aware of potential exceptions such as VXSNAN, OX, UX, and XX, which may set corresponding flags in the FPSCR register.


Summary: Rounds a double-precision floating-point value in VSR[XB] to single-precision and stores the result in VSR[XT].

The instruction rounds the double-precision floating-point value in doubleword element 0 of VSR[XB] to single-precision using the rounding mode specified by RN. The result is placed into doubleword element 0 of VSR[XT] in double-precision format, and doubleword element 1 of VSR[XT] is set to 0.

if MSR.VSX=0 then VSX_Unavailable()

reset_xflags()
src ← bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
rnd ← bfp_ROUND_TO_BFP32(FPSCR.RN, src)
result32 ← bfp32_CONVERT_FROM_BFP(rnd)
result64 ← bfp64_CONVERT_FROM_BFP(rnd)

if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if ux_flag=1 then SetFX(FPSCR.UX)
if xx_flag=1 then SetFX(FPSCR.XX)
vex_flag ← FPSCR.VE & vxsnan_flag

if vex_flag=0 then do
    VSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000
    FPSCR.FPRF ← fprf_CLASS_BFP32(result32)
    FPSCR.FR ← inc_flag
    FPSCR.FI ← xx_flag
end else do
    FPSCR.FR ← 0b0
    FPSCR.FI ← 0b0
end

Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.


VSX Scalar Convert Scalar Single-Precision to Vector Single-Precision format Non-signalling

Summary: Converts a scalar single-precision floating-point value to vector single-precision format without raising exceptions for inexact results.

The instruction converts the contents of doubleword element 0 of VSR[XB] represented in double-precision format to single-precision format and places it into word elements 0 and 1 of VSR[XT]. Word elements 2 and 3 of VSR[XT] are set to 0.

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src ← bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
result ← bfp32_CONVERT_FROM_BFP(src)
VSR[32×TX+T].word[0] ← result
VSR[32×TX+T].word[1] ← result
VSR[32×TX+T].word[2] ← 0x0000_0000
VSR[32×TX+T].word[3] ← 0x0000_0000

If x is not representable in single-precision, some exponent and/or significand bits will be discarded, likely producing undesirable results. The low-order 29 bits of the significand of x are discarded, more if the unbiased exponent of x is less than -126 (i.e., denormal). Finite values of x having an unbiased exponent less than -150 will return a result of Zero. Finite values of x having an unbiased exponent greater than +127 will result in discarding significant bits of the exponent. SNaN inputs having no significant bits in the upper 23 bits of the significand will return Infinity as the result. No status is set for any of these cases. xscvdpsp should be used to convert a scalar double-precision value to vector single-precision format. xscvdpspn should be used to convert a scalar single-precision value to vector single-precision format for non-signalling conversion.


Vector Convert Single-Precision to bfloat16 Format

Summary: Converts single-precision floating-point values in a vector register to bfloat16 format and stores them in another vector register.

Converts four single-precision floating-point values in the source VSX register XB to bfloat16 (16-bit brain float) format and stores the results in the destination VSX register XT. This VSX instruction performs element-wise truncation and rounding of the single-precision mantissa to 7 bits, preserving the sign and 8-bit exponent. Rounding behavior follows FPSCR settings; the upper 64 bits of XT are packed with converted values.

for i in 0 to 3 do
  XT[(i % 2)] ← convert_sp_to_bfloat16(XB[i])
end for

This instruction is used to convert four single-precision floating-point values to bfloat16 format. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register, otherwise, a VSX_Unavailable exception will occur. The conversion handles various special cases like NaNs and infinities according to the rounding mode set in FPSCR.RN. Be aware of potential exceptions indicated by flags such as VXSNAN, UX, XX, which can be checked in the FPSCR register.


VSX Vector Convert bfloat16 to Single-Precision format Non-signaling

Summary: Converts a vector of bfloat16 values to single-precision floating-point format.

Converts each bfloat16 value in the source VSR to single-precision (32-bit) floating-point format and stores the results in the target VSR. This is a non-signaling variant that does not raise exceptions for invalid operations. The instruction operates on two elements per 128-bit register in VSX mode.

XT[0:31] ← ConvertBF16toSP(XB[0:15])
XT[32:63] ← ConvertBF16toSP(XB[16:31])
XT[64:95] ← ConvertBF16toSP(XB[32:47])
XT[96:127] ← ConvertBF16toSP(XB[48:63])

This instruction is used to convert bfloat16 values in a vector to single-precision floating-point format. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking and setting the MSR.VSX bit. The operation processes four elements per iteration, converting the high 16 bits of each source element to the corresponding target element while zeroing out the lower 16 bits. This instruction does not raise exceptions for invalid operations.


VSX Scalar Round to Double-Precision Integer Exact using Current rounding mode

Summary: Rounds a double-precision floating-point value to an integer using the current rounding mode.

The instruction rounds the double-precision floating-point value in doubleword element 0 of VSR[XB] to an integer using the rounding mode specified by RN. The result is placed into doubleword element 0 of VSR[XT] in double-precision format, and doubleword element 1 of VSR[XT] is set to 0.

if MSR.VSX=0 then VSX_Unavailable()
src ←bfp_CONVERT_FROM_BFP64(VSR[VRB+32].dword[0])
if FPSCR.RN=0b00 then rnd ←bfp_ROUND_TO_INTEGER(0b000, src)
if FPSCR.RN=0b01 then rnd ←bfp_ROUND_TO_INTEGER(0b001, src)
if FPSCR.RN=0b10 then rnd ←bfp_ROUND_TO_INTEGER(0b010, src)
if FPSCR.RN=0b11 then rnd ←bfp_ROUND_TO_INTEGER(0b011, src)
result ←bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if xx_flag=1 then SetFX(FPSCR.XX)
vex_flag ←FPSCR.VE & vxsnan_flag
if vex_flag=0 then do
    VSR[32×TX+T].dword[0] ←result
    VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000
    FPSCR.FPRF ←fprf_CLASS_BFP64(result)
    FPSCR.FR  ←inc_flag
    FPSCR.FI  ←xx_flag
else do
    FPSCR.FR  ←0b0
    FPSCR.FI  ←0b0
end

This instruction can be used to operate on a single-precision source operand. Previous versions of the architecture allowed the end contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.


VSX Scalar Round to Double-Precision Integer using round toward -Infinity

Summary: Rounds a double-precision floating-point value in VSR[XB] towards negative infinity and places the result into VSR[XT].

The instruction rounds the double-precision floating-point value in VSR[XB] towards negative infinity. The result is placed into doubleword element 0 of VSR[XT], and doubleword element 1 of VSR[XT] is set to 0. FPRF is set to the class and sign of the result, while FR and FI are set to 0.

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src ← bfp_CONVERT_FROM_BFP64(VSR[VRB+32].dword[0])
rnd ← bfp_ROUND_TO_INTEGER(0b011, src)
result ← bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
vex_flag ← FPSCR.VE & vxsnan_flag
if vex_flag=0 then
do
    VSR[32×TX+T].dword[0] ← result
    VSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000
    FPSCR.FPRF ← fprf_CLASS_BFP64(result)
end
FPSCR.FR ← 0b0
FPSCR.FI ← 0b0

This instruction can be used to operate on a single-precision source operand. Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.


VSX Scalar Round to Double-Precision Integer using round toward +Infinity

Summary: Rounds a double-precision floating-point value towards positive infinity and stores the result in a vector scalar register.

The instruction rounds the contents of doubleword element 0 of VSR[XB] towards positive infinity. The result is placed into doubleword element 0 of VSR[XT], with doubleword element 1 set to zero. FPRF is updated based on the class and sign of the result, while FR and FI are reset to zero.

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src ← bfp_CONVERT_FROM_BFP64(VSR[VRB+32].dword[0])
rnd ← bfp_ROUND_TO_INTEGER(0b010, src)
result ← bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
vex_flag ← FPSCR.VE & vxsnan_flag
if vex_flag=0 then
do
    VSR[32×TX+T].dword[0] ← result
    VSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000
    FPSCR.FPRF ← fprf_CLASS_BFP64(result)
end
FPSCR.FR ← 0b0
FPSCR.FI ← 0b0


VSX Scalar Round to Double-Precision Integer

Summary: Rounds a double-precision floating-point value toward zero and places the result into a vector-scalar register.

The instruction rounds the contents of doubleword element 0 of VSR[XB] toward zero and stores the result in doubleword element 0 of VSR[XT]. Doubleword element 1 of VSR[XT] is set to 0. The FPRF, FR, and FI fields are updated accordingly.

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src ← bfp_CONVERT_FROM_BFP64(VSR[XB+32].dword[0])
rnd ← bfp_ROUND_TO_INTEGER(0b001, src)
result ← bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
vex_flag ← FPSCR.VE & vxsnan_flag
if vex_flag=0 then do
    VSR[32×TX+T].dword[0] ← result
    VSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000
    FPSCR.FPRF ← fprf_CLASS_BFP64(result)
end
FPSCR.FR ← 0b0
FPSCR.FI ← 0b0


VSX Vector Round to Double-Precision Integer using round to Nearest Away

Summary: Rounds each element of a double-precision floating-point vector to the nearest integer away from zero.

For xvrdpi, each element in the source vector VSR[XB] is rounded to an integer using the rounding mode Round to Nearest Away. The result is placed into the target vector VSR[XT]. If a Signalling NaN is encountered, it is converted to a Quiet NaN and VXSNAN is set to 1.

if MSR.VSX=0 then VSX_Unavailable()

ex_flag ←0b0
do i = 0 to 1
    reset_xflags()
    src ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])
    rnd ←bfp_ROUND_TO_INTEGER(0b100, src)
    vresult.dword[i] ←bfp64_CONVERT_FROM_BFP(rnd)
    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag)
end
if ex_flag=0 then VSR[32×TX+T] ←vresult

This instruction is commonly used for converting floating-point numbers to integers with rounding towards the nearest integer away from zero. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register; otherwise, an exception will be raised. Be cautious of Signalling NaNs, as they are converted to Quiet NaNs and VXSNAN is set, which might affect subsequent operations if not handled properly.


VSX Vector Round to Double-Precision Integer

Summary: Rounds each double-precision floating-point element of a vector to an integer using the current rounding mode.

For xvrdpic, each double-precision floating-point element in VSR[XB] is rounded to an integer using the rounding mode specified by FPSCR.RN. The result is placed into VSR[XT]. If any element results in a Signalling NaN, it is converted to a Quiet NaN and VXSNAN is set.

if MSR.VSX=0 then VSX_Unavailable()

ex_flag ←0b0
do i = 0 to 1
    reset_xflags()
    src ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])
    if FPSCR.RN=0b00 then rnd ←bfp_ROUND_TO_INTEGER(0b000, src)
    if FPSCR.RN=0b01 then rnd ←bfp_ROUND_TO_INTEGER(0b001, src)
    if FPSCR.RN=0b10 then rnd ←bfp_ROUND_TO_INTEGER(0b010, src)
    if FPSCR.RN=0b11 then rnd ←bfp_ROUND_TO_INTEGER(0b011, src)

    vresult.dword[i] ←bfp64_CONVERT_FROM_BFP(rnd)

    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    if xx_flag=1 then SetFX(FPSCR.XX)

    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag)
    ex_flag ←ex_flag | (FPSCR.XE & xx_flag)
end

if ex_flag=0 then VSR[32×TX+T] ←vresult

This instruction rounds each double-precision floating-point element in the source vector to an integer using the rounding mode specified by FPSCR.RN. Ensure that VSX is enabled; otherwise, a VSX_Unavailable exception will occur. Be cautious of NaN values, as they are converted to Quiet NaNs and VXSNAN is set. The instruction respects the rounding modes defined in FPSCR.RN, so ensure this register is correctly configured for your needs.


VSX Vector Round to Double-Precision Integer using round toward -Infinity

Summary: Rounds the contents of a vector register towards negative infinity and stores the result in another vector register.

Rounds each double-precision floating-point element in the source VSR towards negative infinity (-∞) and stores the result in the target VSR. The rounding mode is floor, affecting the FPSCR rounding control. This operation is performed on the two double-precision elements in each 128-bit VSR.

XT[0:63] ← RoundTowardMinusInfinity(XB[0:63])
XT[64:127] ← RoundTowardMinusInfinity(XB[64:127])

The xvrdpim instruction is commonly used for rounding double-precision floating-point numbers towards negative infinity in vector operations. Ensure that the VSX (Vector Scalar Extensions) are enabled, as attempting to use this instruction when they are not will result in an unavailable exception. Be cautious with signaling NaNs, as they are converted to quiet NaNs and VXSNAN is set in the FPSCR register.


Vector Round to Double-Precision Integer using round toward Zero

Summary: Rounds each double-precision floating-point element in a vector towards zero and stores the result as an integer.

The instruction rounds each double-precision floating-point element in VSR[XB] towards zero and stores the result in VSR[XT]. If any element is a Signalling NaN, it is converted to a Quiet NaN and VXSNAN is set. If a trap-enabled exception occurs, no results are written to VSR[XT].

if MSR.VSX=0 then VSX_Unavailable()

ex_flag ←0b0
do i = 0 to 1
    reset_xflags()
    src ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])
    rnd ←bfp_ROUND_TO_INTEGER(0b001, src)
    vresult.dword[i] ←bfp64_CONVERT_FROM_BFP(rnd)
    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag)
end

if ex_flag=0 then VSR[32×TX+T] ←vresult

This instruction is commonly used for converting double-precision floating-point numbers to integers by rounding towards zero. Be cautious with Signalling NaNs, as they are converted to Quiet NaNs and VXSNAN is set. Ensure that the VSX facility is enabled; otherwise, a VSX_Unavailable exception will occur. The instruction does not write results if any trap-enabled exceptions happen.


VSX Vector Round to Single-Precision Integer

Summary: Rounds each element of a vector from single-precision floating-point format to an integer using round to Nearest Away.

For xvrspi, each element of the source vector VSR[XB] is rounded to an integer using the rounding mode Round to Nearest Away. The result is placed into the corresponding element of the target vector VSR[XT]. If a Signalling NaN is encountered, it is converted to a Quiet NaN and VXSNAN is set to 1.

if MSR.VSX=0 then VSX_Unavailable()

ex_flag ←0b0

do i = 0 to 3
    reset_xflags()
    src ←bfp_CONVERT_FROM_BFP32(VSR[32×BX+B].word[i])
    rnd ←bfp_ROUND_TO_INTEGER(0b100, src)
    vresult.word[i] ←bfp32_CONVERT_FROM_BFP(rnd)

    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag)
end

if ex_flag=0 then VSR[32×TX+T] ←vresult

The xvrspi instruction rounds each element of the source vector to an integer using the Round to Nearest Away mode. It handles Signalling NaNs by converting them to Quiet NaNs and setting VXSNAN in the FPSCR register. Ensure that VSX is enabled (MSR.VSX=1) before using this instruction, as attempting to use it when VSX is unavailable will result in an exception.


Summary: Rounds each single-precision floating-point element of a vector to an integer using the current rounding mode.

For xvrspic, each single-precision floating-point operand in word elements i (0 to 3) of VSR[XB] is rounded to an integer value using the rounding mode specified by RN. The result is placed into word element i of VSR[XT]. If a trap-enabled exception occurs, no results are written to VSR[XT].

if MSR.VSX=0 then VSX_Unavailable()

ex_flag ←0b0
do i = 0 to 3
    reset_xflags()
    src ←bfp_CONVERT_FROM_BFP32(VSR[32×BX+B].word[i])
    if FPSCR.RN=0b00 then rnd ←bfp_ROUND_TO_INTEGER(0b000, src)
    if FPSCR.RN=0b01 then rnd ←bfp_ROUND_TO_INTEGER(0b001, src)
    if FPSCR.RN=0b10 then rnd ←bfp_ROUND_TO_INTEGER(0b010, src)
    if FPSCR.RN=0b11 then rnd ←bfp_ROUND_TO_INTEGER(0b011, src)

    vresult.word[i] ←bfp32_CONVERT_FROM_BFP(rnd)

    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    if xx_flag=1     then SetFX(FPSCR.XX)

    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag)
                   | (FPSCR.XE & xx_flag)
end

if ex_flag=0 then VSR[32×TX+T] ←vresult

This instruction rounds each single-precision floating-point element in the source vector to an integer using the rounding mode specified by FPSCR.RN. Ensure that VSX is enabled (MSR.VSX=1) before use. Be cautious of exceptions; if any occur, no results are written to the destination vector. Check the VXSNAN and XX flags for specific exception conditions.


VSX Vector Round to Single-Precision Integer using round toward -Infinity

Summary: Rounds each element of a vector from single-precision floating-point format to integer format, rounding towards negative infinity.

Rounds each single-precision floating-point element in the source VSR towards negative infinity (-∞) and stores the result in the target VSR using floor rounding semantics. This operates on four single-precision elements per 128-bit VSR in VSX mode.

XT[0:31] ← RoundTowardMinusInfinity(XB[0:31])
XT[32:63] ← RoundTowardMinusInfinity(XB[32:63])
XT[64:95] ← RoundTowardMinusInfinity(XB[64:95])
XT[96:127] ← RoundTowardMinusInfinity(XB[96:127])

The xvrspim instruction is commonly used for converting single-precision floating-point numbers to integers with rounding towards negative infinity. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register; otherwise, a VSX_Unavailable exception will be raised. Be cautious of NaN values, as they can set the VXSNAN flag in the FPSCR register and trigger an exception if VE is also set.


VSX Vector Round to Single-Precision Integer using round toward Zero

Summary: Rounds each single-precision floating-point element of a vector towards zero and stores the result in another vector.

For xvrspiz, each single-precision floating-point operand in word elements of VSR[XB] is rounded to an integer using the rounding mode Round toward Zero. The results are placed into corresponding word elements of VSR[XT]. If a Signalling NaN is encountered, it is converted to a Quiet NaN and VXSNAN is set.

if MSR.VSX=0 then VSX_Unavailable()

ex_flag ←0b0

do i = 0 to 3
    reset_xflags()

    src ←bfp_CONVERT_FROM_BFP32(VSR[32×BX+B].word[i])
    rnd ←bfp_ROUND_TO_INTEGER(0b001, src)

    vresult.word[i] ←bfp32_CONVERT_FROM_BFP(rnd)

    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag)
end

if ex_flag=0 then VSR[32×TX+T] ←vresult

This instruction is commonly used for converting single-precision floating-point numbers to integers by truncating towards zero. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register; otherwise, an exception will be raised. Be cautious with Signalling NaNs, as they are converted to Quiet NaNs and VXSNAN is set in the FPSCR register. The instruction processes four elements at a time, so ensure proper alignment of input vectors.


VSX Scalar Convert Double-Precision to Signed Word format with round to zero

Summary: Converts a double-precision floating-point value to a signed word format using round towards zero.

Converts a double-precision floating-point value from the source VSR to a signed 32-bit word integer using round-toward-zero mode and stores the result in the target VSR. Only the scalar (leftmost) element is processed. Invalid conversions produce a saturated value; the FPSCR is updated with status flags.

XT[0:31] ← ConvertToSignedWord_RoundTowardZero(XB[0:63])
XT[32:127] ← 0

Previous versions of the architecture allowed the contents of word 0 of the result register to be undefined. However, all processors that support this instruction write the result into words 0 and 1 of the result register, as is required by this version of the architecture. This instruction can be used to operate on a single-precision source operand. xscvdpsxws rounds using Round towards Zero rounding mode. For other rounding modes, software must use a Round to Double-Precision Integer instruction that corresponds to the desired rounding mode, including xsrdpic which uses the rounding mode specified by RN.


VSX Scalar Convert Double-Precision to Unsigned Word format with round to zero

Summary: Converts a double-precision floating-point value to an unsigned 32-bit integer, rounding towards zero.

The instruction converts the double-precision floating-point value in VSR[XB] to an unsigned 32-bit integer and places the result into word elements 0 and 1 of VSR[XT]. The contents of word elements 2 and 3 of VSR[XT] are set to 0. If the source is a NaN, the result is 0x0000_0000 and VXCVI is set to 1. If the source is an SNaN, VXSNAN is also set to 1.

if src ≤ Nmin-1 then
    T(Nmin)
    fr(0)
    fi(0)
    fx(VXCVI)
    if error() then invoke system error handler
else if Nmin-1 < src < Nmin then
    T(Nmin)
    fr(0)
    fi(1)
    fx(XX)
    if error() then invoke system error handler
else if src = Nmin then
    T(Nmin)
    fr(0)
    fi(0)
else if Nmin < src < Nmax then
    T(f2i(trunc(src)))
    fr(0)
    fi(1)
    fx(XX)
    if error() then invoke system error handler
else if src = Nmax then
    T(Nmax)
    fr(0)
    fi(0)
else if Nmax < src < Nmax+1 then
    T(Nmax)
    fr(0)
    fi(1)
    fx(XX)
    if error() then invoke system error handler
else if src ≥ Nmax+1 then
    T(Nmin)
    fr(0)
    fi(0)
    fx(VXCVI)
    if error() then invoke system error handler
else if src is a QNaN then
    T(Nmin)
    fr(0)
    fi(0)
    fx(VXCVI)
    if error() then invoke system error handler
else if src is a SNaN then
    T(Nmin)
    fr(0)
    fi(0)
    fx(VXCVI)
    fx(VXSNAN)
    if error() then invoke system error handler

Previous versions of the architecture allowed the contents of word 0 of the result register to be undefined. However, all processors that support this instruction write the result into words 0 and 1 of the result register, as is required by this version of the architecture. This instruction can be used to operate on a single-precision source operand. xscvdpuxws rounds using Round towards Zero rounding mode. For other rounding modes, software must use a Round to Double-Precision Integer instruction that corresponds to the desired rounding mode, including xsrdpic which uses the rounding mode specified by RN.