Summary: Compares the signed halfwords of two vector registers and stores the maximum values in a third vector register.

For vmaxsh, each pair of corresponding halfwords from VSR[VRA+32] and VSR[VRB+32] are compared. The larger value is stored in the corresponding halfword of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 7
    src1 ← VSR[VRA+32].hword[i]
    src2 ← VSR[VRB+32].hword[i]
    gt_flag ← EXTS(src1) > EXTS(src2)
    VSR[VRT+32].hword[i] ← gt_flag=1 ? src1 : src2
end

This instruction is used to perform element-wise signed halfword maximum operations between two vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation respects the sign of the halfwords and stores the larger value in the corresponding position of the destination register. Be cautious with alignment as unaligned access might lead to performance penalties or exceptions depending on the system configuration.


Summary: Selects maximum value per word (unsigned).

Compares four unsigned word elements from vA and vB, writing the maximum value of each pair to the corresponding word element in vD. This is a VMX (AltiVec) instruction that operates on all four 32-bit words in parallel with no condition register or status updates.

The vmaxuw instruction is used to perform element-wise comparison of unsigned 32-bit words in vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation does not require any specific alignment for the data being processed.


Summary: Compares the signed integer values in each word element of two vector registers and stores the larger value into a third vector register.

For vmaxsw, for each integer value i from 0 to 3, the signed integer value in word element i of VSR[VRA+32] is compared to the signed integer value in word element i of VSR[VRB+32]. The larger of the two values is placed into word element i of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ← VSR[VRA+32].word[i]
    src2 ← VSR[VRB+32].word[i]
    gt_flag ← EXTS(src1) > EXTS(src2)
    VSR[VRT+32].word[i] ← gt_flag=1 ? src1 : src2

The vmaxsw instruction compares each signed word element of two vector registers and stores the maximum value in the destination register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on 4-word elements, so input vectors must be properly aligned. Be cautious with signed integer overflow; if both operands are negative and one is closer to zero than the other, the result may not be as expected.


Summary: Interleaves high-order bytes from two vectors (Permutation).

For vmrghb, the high byte elements of VSR[VRA+32] and VSR[VRB+32] are merged into VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 7
    VSR[VRT+32].hword[i].byte[0] ← VSR[VRA+32].byte[i]
    VSR[VRT+32].hword[i].byte[1] ← VSR[VRB+32].byte[i]

This instruction is used to merge the high byte elements from two vector registers into a third. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. The operation processes each of the 8 high bytes, placing them alternately into the destination register. This instruction operates at the user privilege level and does not generate exceptions beyond those related to facility availability or invalid operand access.


Summary: Merges the high halfwords of two vector registers into a target vector register.

For vmrghh, the contents of halfword elements 0 to 3 of VSR[VRA+32] are placed into halfword elements 0 to 7 of VSR[VRT+32], and the contents of halfword elements 0 to 3 of VSR[VRB+32] are placed into halfword elements 1 to 8 of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    VSR[VRT+32].word[i].hword[0] ← VSR[VRA+32].hword[i]
    VSR[VRT+32].word[i].hword[1] ← VSR[VRB+32].hword[i]

The vmrghh instruction is used to merge the high halfwords from two vector registers into a single destination register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. This operation is useful for combining data from two sources into one vector, but be cautious of alignment issues if the data elements are not properly aligned to halfword boundaries.


Summary: Merges the high words of two vector registers into a target vector register.

O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O

The contents of word element 0 of VSR[VRA+32] are placed into word element 0 of VSR[VRT+32]. The contents of word element 0 of VSR[VRB+32] are placed into word element 1 of VSR[VRT+32]. The contents of word element 1 of VSR[VRA+32] are placed into word element 2 of VSR[VRT+32]. The contents of word element 1 of VSR[VRB+32] are placed into word element 3 of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
else
    VSR[VRT+32].word[0] ← VSR[VRA+32].word[0]
    VSR[VRT+32].word[1] ← VSR[VRB+32].word[0]
    VSR[VRT+32].word[2] ← VSR[VRA+32].word[1]
    VSR[VRT+32].word[3] ← VSR[VRB+32].word[1]

The vmrghw instruction is used to merge high words from two vector registers into a third. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. This operation is useful for combining specific elements from different vectors into a single output vector.


Summary: Interleaves low-order bytes.

Merges the eight low-order (rightmost) bytes from vA and vB in an alternating interleaved pattern into vD, with vA bytes in even positions and vB bytes in odd positions. This VMX instruction does not affect any condition or status registers.

The vmrglb instruction is useful for merging data from two vectors by alternating bytes into a third vector. Ensure that the target and source registers are properly aligned to avoid unexpected behavior. This instruction requires the Vector Facility to be enabled in the MSR register; otherwise, it will raise an exception. Performance may vary based on the specific implementation and alignment of the data.


Summary: Interleaves low-order halfwords.

Merges the four low-order (rightmost) halfwords from vA and vB in an alternating interleaved pattern into vD, with vA halfwords in even positions and vB halfwords in odd positions. This VMX instruction does not affect any condition or status registers.

The vmrglh instruction is used to merge the lower halfwords from two source vectors into a destination vector. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation interleaves the halfwords from the two sources, so the resulting vector will have elements from both sources in an alternating pattern.


Summary: Interleaves low-order words.

Merges the two low-order (rightmost) words from vA and vB in an alternating interleaved pattern into vD, with vA word in even position and vB word in odd position. This VMX instruction does not affect any condition or status registers.

The vmrglw instruction is used to merge the low words from two source vectors into a destination vector. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set; otherwise, a Vector_Unavailable exception will be raised. This instruction operates on 128-bit vector registers and requires proper alignment of the input vectors to avoid unexpected results.


Vector Pack Unsigned Halfword Unsigned Modulo

Summary: Packs the upper half of each 16-bit element from two vector registers into a single byte in another vector register.

The instruction packs the upper half of each 16-bit element from VSR[VRA+32] and VSR[VRB+32] into the corresponding byte elements of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
else
    vsrc.qword[0] ← VSR[VRA+32]
    vsrc.qword[1] ← VSR[VRB+32]
    for i = 0 to 15 do
        VSR[VRT+32].byte[i] ← vsrc.hword[i].bit[8:15]
    end
end

This instruction is used to pack the upper half of each 16-bit element from two source vectors into a destination vector. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set before using this instruction; otherwise, it will raise an exception. The operation processes 32 bytes (16 elements) from each source vector and packs them into the destination vector, maintaining the upper half of each element. This instruction does not require any specific alignment but must be executed in a privileged context where the VEC bit is enabled.


Vector Pack Unsigned Word Unsigned Modulo

Summary: Packs the upper half of each word from two vector registers into a single vector register using modulo arithmetic.

The instruction concatenates the contents of VSR[VRA+32] and VSR[VRB+32], then extracts the upper half of each word (bits 16:31) and places them into the corresponding halfword elements of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
vsrc.qword[0] ← VSR[VRA+32]
vsrc.qword[1] ← VSR[VRB+32]
do i = 0 to 7
    VSR[VRT+32].hword[i] ← vsrc.word[i].bit[16:31]
end

This instruction is used for packing the upper half of each word from two vector registers into a single destination register. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to 1; otherwise, a Vector Unavailable exception will be raised. The operation requires both source vectors to be aligned on 16-byte boundaries for optimal performance.


Vector Pack Unsigned Halfword Unsigned Saturate

Summary: Saturates 8 halfwords to 16 unsigned bytes.

Packs and saturates eight unsigned halfword elements from vA and vB into sixteen unsigned bytes in vD, discarding or saturating values that exceed 255. The saturation flag in VSCR is set if any saturation occurred. This VMX instruction operates in saturating mode for unsigned values.

for i in 0 to 3:
  vD[2*i:2*i+7] ← Saturate_UH_to_UB(vA[16*i:16*i+15])
  vD[2*i+8:2*i+15] ← Saturate_UH_to_UB(vB[16*i:16*i+15])
if any saturation occurred:
  VSCR[SAT] ← 1

The vpkuhus instruction is used to pack unsigned halfwords from two source vectors into a destination vector, with saturation applied if the values exceed 8 bits. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The operation processes each halfword from the input vectors and clamps the result to fit within an 8-bit unsigned integer range.


Vector Pack Signed Halfword Signed Saturate

Summary: Packs signed halfwords from two vector registers into a single vector register with signed saturation.

The instruction concatenates the contents of VSR[VRA+32] and VSR[VRB+32], then for each integer value i from 0 to 15, it places the signed integer value in halfword element i of the concatenated source into byte element i of VSR[VRT+32] in signed integer format. If the value is greater than 2^7 - 1 or less than -2^7, it saturates and sets SAT to 1.

if MSR.VEC=0 then
    Vector_Unavailable()
vsrc.qword[0] ← VSR[VRA+32]
vsrc.qword[1] ← VSR[VRB+32]
do i = 0 to 15
    VSR[VRT+32].byte[i] ← si8_CLAMP(EXTS(vsrc.hword[i]))
end

This instruction is useful for packing signed halfwords into bytes with saturation. Ensure that the source vectors are correctly aligned and that the vector facility (MSR.VEC) is enabled to avoid exceptions. Be aware of saturation conditions, as they will set the SAT bit in VSCR.


Summary: Packs signed words from two vector registers into a single vector register with signed saturation.

The instruction vpkswss packs the contents of VSR[VRA+32] and VSR[VRB+32] into VSR[VRT+32], converting each word to a halfword with signed saturation.

if MSR.VEC=0 then
    Vector_Unavailable()
vsrc.qword[0] ← VSR[VRA+32]
vsrc.qword[1] ← VSR[VRB+32]
do i = 0 to 7
    VSR[VRT+32].hword[i] ← si16_CLAMP(EXTS(vsrc.word[i]))
end

This instruction is commonly used for efficiently packing and saturating signed word values into halfwords. Ensure that the vector facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation involves extending each 32-bit word to 64 bits with sign extension, then clamping the result to fit within a 16-bit signed integer range. Be aware of potential saturation effects when dealing with values that exceed the halfword range.


Summary: Unpacks the high signed byte from each element of a vector register into halfwords of another vector register.

For vupkhsb, the signed integer value in byte element i of VSR[VRB+32] is sign-extended and placed into half-word element i in VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 7
    VSR[VRT+32].hword[i] ←EXTS16(VSR[VRB+32].byte[i])
end

This instruction is used to unpack the high signed bytes from one vector register into half-words of another. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector Unavailable exception will be raised. The operation processes each byte element, sign-extending it to a half-word, which can affect the result if the original byte values are negative.


Summary: Unpacks the high signed halfwords from a vector register into a new vector register.

The instruction unpacks the high signed halfwords from VSR[VRB+32] and places them into VSR[VRT+32]. Each halfword is sign-extended to form a word.

if MSR.VEC=0 then
    Vector_Unavailable()
for each integer value i from 0 to 3 do
    VSR[VRT+32].word[i] ←EXTS32(VSR[VRB+32].hword[i])

This instruction is used to extract the high signed halfwords from a vector register and sign-extend them into another vector register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The operation processes each of the four halfwords in the source register, so ensure proper alignment if dealing with specific data structures.


Summary: Unpacks low 8 signed bytes to 8 signed halfwords.

Unpacks the eight low-order (rightmost) signed bytes from vB into eight signed halfwords in vD, sign-extending each byte to 16 bits. This is a VMX instruction that does not modify condition or status registers.

This instruction is useful for processing byte data by converting it into signed halfwords, which can be beneficial for operations requiring sign extension. Ensure that the vector facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will occur. The input vector must be properly aligned to avoid unexpected results.


Summary: Unpacks low 4 signed halfwords to 4 signed words.

Unpacks the four low-order (rightmost) signed halfwords from vB into four signed words in vD, sign-extending each halfword to 32 bits. This is a VMX instruction that does not modify condition or status registers.

This instruction is used to unpack the low halfwords from a source vector register into a destination vector register, sign-extending each halfword to form words. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation targets the high 128 bits of the vector registers, so ensure that VRB and VRT are correctly set for the desired vector elements.


Summary: Adds the contents of two vector registers and updates the result in another vector register, modulo operation for bytes.

For vaddubm, each byte element of VSR[VRA+32] is added to the corresponding byte element of VSR[VRB+32], and the low-order 8 bits of the result are placed into the corresponding byte element of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 15
    src1 ←EXTZ(VSR[VRA+32].byte[i])
    src2 ←EXTZ(VSR[VRB+32].byte[i])
    VSR[VRT+32].byte[i] ←CHOP8(src1 + src2)
end

vaddubm can be used for unsigned or signed integers.


Summary: Adds 8 halfwords modulo 65536.

Adds eight pairs of unsigned halfword elements from vA and vB with modulo 65536 arithmetic (overflow wraps around) and stores the results in vD. This VMX instruction does not affect condition or status registers and operates in modulo mode without saturation.

This instruction is commonly used for vectorized addition of unsigned 16-bit integers with modulo behavior, useful in applications like image processing or cryptography. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation processes each halfword element independently, so there are no ordering requirements between elements, but alignment of input vectors to 16-byte boundaries can improve performance.


Summary: Adds 4 words modulo 2^32.

Adds each of four unsigned 32-bit words in vA to the corresponding word in vB, with results modulo 2^32 (wrapping on overflow). No status flags are affected; this is a basic VMX/AltiVec arithmetic operation.

This instruction is commonly used for performing element-wise addition of unsigned 32-bit integers in vector registers. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to avoid a Vector_Unavailable exception. The operation wraps around using modulo arithmetic, so there's no need to handle overflow separately. This instruction operates at the user privilege level and does not generate exceptions for normal arithmetic operations.


Summary: Adds 2 doublewords modulo 2^64.

Adds each of two unsigned 64-bit doublewords in vA to the corresponding doubleword in vB, with results modulo 2^64 (wrapping on overflow). No status flags are affected; this is a VMX/AltiVec arithmetic operation available on some implementations.

This instruction is commonly used for performing element-wise addition of two vectors treating each element as a 64-bit unsigned integer. Ensure that the vector registers are properly aligned and that the VEC bit in the MSR register is set to 1 to avoid exceptions. Be cautious of overflow, as the operation uses modulo arithmetic, which wraps around without generating an exception.


Summary: Adds the contents of two vector registers and saturates the result if it overflows.

For vaddubs, each byte element in VSR[VRA+32] is added to the corresponding byte element in VSR[VRB+32]. If the sum exceeds 255, it saturates to 255 and sets the SAT field in VSCR.

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 15
    src1 ←EXTZ(VSR[VRA+32].byte[i])
    src2 ←EXTZ(VSR[VRB+32].byte[i])
    VSR[VRT+32].byte[i] ←ui8_CLAMP(src1 + src2)
end

vaddubs is commonly used for adding unsigned byte elements in vector registers with saturation to handle overflow. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. The operation processes 16 bytes per instruction, and results are clamped to 255 if they exceed this value, setting the SAT field in VSCR accordingly.


Summary: Adds the contents of two vector registers and saturates the result.

Adds each of eight unsigned 16-bit halfwords in vA to the corresponding halfword in vB, with saturation at the unsigned range [0, 65535]. Any result exceeding 65535 is clamped to 65535; no status flags are affected.

The vadduhs instruction is commonly used for adding pairs of unsigned halfwords with saturation, which prevents overflow by clamping results to the maximum representable value. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation processes 8 halfword elements in parallel, and both source registers must be properly aligned for optimal performance.


Summary: Adds the contents of two vector registers and saturates the result if it exceeds 32 bits.

For vadduws, each word element in VSR[VRA+32] is added to the corresponding word element in VSR[VRB+32]. If the sum exceeds 2^32 - 1, it saturates to 2^32 - 1 and sets the SAT field in VSCR.

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ←EXTZ(VSR[VRA+32].word[i])
    src2 ←EXTZ(VSR[VRB+32].word[i])

    VSR[VRT+32].word[i] ←ui32_CLAMP(src1 + src2)
end

vadduws is used for adding unsigned 32-bit integers in vector registers with saturation. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will occur. The operation saturates sums exceeding 2^32 - 1 and sets the SAT field in VSCR to indicate saturation occurred.


Summary: Adds 16 signed bytes with saturation (-128..127).

Adds each of sixteen signed 8-bit bytes in vA to the corresponding byte in vB, with saturation at the signed range [-128, 127]. Results below -128 are clamped to -128, and results above 127 are clamped to 127; no status flags are affected.

The vaddsbs instruction is commonly used for vectorized addition of signed bytes, ensuring that results are clamped to the 8-bit signed integer range. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. This instruction operates on 16-byte vectors and processes each byte independently.


For vaddshs, each halfword element in VSR[VRA+32] is added to the corresponding halfword element in VSR[VRB+32]. The result is saturated if it exceeds the range of a signed 16-bit integer.

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 7
    src1 ←EXTS(VSR[VRA+32].hword[i])
    src2 ←EXTS(VSR[VRB+32].hword[i])
    VSR[VRT+32].hword[i] ←si16_CLAMP(src1 + src2)
end

vaddshs is used for adding signed halfwords with saturation. Ensure that the vector facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will occur. The operation saturates results if they exceed the 16-bit signed integer range, preventing overflow. This instruction operates on elements in the upper half of the VSX registers.


Summary: Adds 4 signed words with saturation.

Adds each of four signed 32-bit words in vA to the corresponding word in vB, with saturation at the signed range [-2^31, 2^31-1]. Results are clamped to the valid signed 32-bit range; no status flags are affected.

The vaddsws instruction is useful for adding signed integers with overflow protection, ensuring that results do not exceed the bounds of a 32-bit signed integer. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to 1 before using this instruction; otherwise, a Vector_Unavailable exception will be raised. Be cautious of potential performance overhead due to saturation checks, which can impact execution speed if many elements overflow.


Summary: Subtracts the contents of two vector registers and updates the result in another vector register using modulo operation for bytes.

For vsububm, each byte element in VSR[VRB+32] is subtracted from the corresponding byte element in VSR[VRA+32], and the result is placed into the corresponding byte element of VSR[VRT+32]. The operation uses modulo arithmetic.

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 15
    src1 ←EXTZ(VSR[VRA+32].byte[i])
    src2 ←EXTZ(VSR[VRB+32].byte[i])
    VSR[VRT+32].byte[i] ←CHOP8(src1 + ¬src2 + 1)
end

This instruction performs vectorized byte-wise subtraction with modulo arithmetic. Ensure that the Vector Facility is enabled by checking and setting the appropriate bit in the MSR register. Be cautious of potential overflow issues due to the modulo operation, which can wrap around values. This instruction operates at a privilege level where the Vector Facility is accessible.


Vector Subtract Unsigned Halfword Modulo

Summary: Subtracts 8 halfwords modulo 65536.

Subtracts each of eight unsigned 16-bit halfwords in vB from the corresponding halfword in vA, with results modulo 2^16 (wrapping on underflow). No status flags are affected; this is a basic VMX/AltiVec arithmetic operation.

This instruction is useful for performing element-wise subtraction of unsigned halfwords with modulo 65536, which can be particularly handy in graphics or audio processing where overflow needs to wrap around. Ensure that the vector registers are properly aligned and that the VEC bit in the MSR register is set to enable vector operations. Be cautious of potential performance overhead if used in tight loops without optimization.


Vector Subtract Unsigned Doubleword Modulo

Summary: Subtracts the contents of two vector registers and places the result in a third vector register, modulo operation.

Subtracts each of two unsigned 64-bit doublewords in vB from the corresponding doubleword in vA, with results modulo 2^64 (wrapping on underflow). No status flags are affected; this is a VMX/AltiVec arithmetic operation.

This instruction is used for performing unsigned doubleword subtraction with modulo arithmetic. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation is performed on each pair of elements from two source vectors, and the results are stored in the destination vector. Be cautious with alignment as it may affect performance or cause exceptions if not properly managed.


Summary: Subtracts the contents of two vector registers and saturates the result to zero if it underflows.

For vsububs, each byte element in VSR[VRA+32] is subtracted from the corresponding byte element in VSR[VRB+32]. If the result is less than zero, it saturates to zero and sets the SAT flag in VSCR.

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 15
    src1 ←EXTZ(VSR[VRA+32].byte[i])
    src2 ←EXTZ(VSR[VRB+32].byte[i])
    VSR[VRT+32].byte[i] ←ui8_CLAMP(src1 + ¬src2 + 1)
end

Use vsububs for subtracting unsigned byte elements with saturation. Ensure vectors are properly aligned and check VSCR.SAT to verify saturation occurred. Requires vector facility enabled; otherwise, triggers an exception.


Vector Subtract Unsigned Halfword Saturate

Summary: Subtracts 8 unsigned halfwords with saturation.

Subtracts each of eight unsigned 16-bit halfwords in vB from the corresponding halfword in vA, with saturation at the unsigned range [0, 65535]. Results below 0 are clamped to 0; no status flags are affected.

This instruction is useful for performing element-wise unsigned subtraction on vectors with saturation to handle overflow. Ensure that the vector registers are properly aligned and that the VEC bit in the MSR register is set to 1. Be aware of potential performance implications due to saturation handling, which may affect throughput.


Summary: Subtracts the contents of two vector registers and saturates the result if it underflows.

For vsubuws, each word element in VSR[VRB+32] is subtracted from the corresponding word element in VSR[VRA+32]. If the intermediate result is less than 0, it saturates to 0 and sets the SAT field in VSCR.

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ←EXTZ(VSR[VRA+32].word[i])
    src2 ←EXTZ(VSR[VRB+32].word[i])
    VSR[VRT+32].word[i] ←ui32_CLAMP(src1 + ¬src2 + 1)
end

This instruction is commonly used for vectorized unsigned word subtraction with saturation, useful in image processing and other applications requiring bounded arithmetic. Ensure that the Vector Status and Control Register (VSCR) is properly managed to handle saturation flags. The operation saturates underflows to zero, so be cautious of cases where results might wrap around unexpectedly.


Summary: Subtracts 16 signed bytes with saturation.

Subtracts each of 16 signed 8-bit elements in vB from the corresponding element in vA, with saturation to the signed 8-bit range [-128, 127]. If overflow or underflow occurs, the result saturates to the minimum or maximum signed byte value. No condition register fields are affected.

for i in 0 to 15 do
  result ← vA[8*i:8*i+7] - vB[8*i:8*i+7]
  if result < -128 then vD[8*i:8*i+7] ← -128
  elsif result > 127 then vD[8*i:8*i+7] ← 127
  else vD[8*i:8*i+7] ← result

This instruction is commonly used in applications requiring vectorized arithmetic operations on signed bytes, such as image processing or audio signal processing. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation saturates results to prevent overflow or underflow, which can be crucial for maintaining data integrity in certain applications.


Vector Subtract Signed Halfword Saturate

Summary: Subtracts the contents of two vector registers and saturates the result to halfword elements.

For vsubshs, each signed halfword element in VSR[VRB+32] is subtracted from the corresponding signed halfword element in VSR[VRA+32]. The result is saturated if it exceeds the range of a signed 16-bit integer.

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 7
    src1 ←EXTS(VSR[VRA+32].hword[i])
    src2 ←EXTS(VSR[VRB+32].hword[i])
    VSR[VRT+32].hword[i] ←si16_CLAMP(src1 + ¬src2 + 1)
end

vsubshs is used for subtracting signed halfwords with saturation. Ensure that the vector facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will occur. The operation saturates results if they exceed the signed 16-bit integer range, preventing overflow. This instruction operates on elements in VSR[VRB+32] and VSR[VRA+32], storing the result in VSR[VRT+32].


Summary: Subtracts 4 signed words with saturation.

Subtracts each of 4 signed 32-bit elements in vB from the corresponding element in vA, with saturation to the signed 32-bit range [-2147483648, 2147483647]. If overflow or underflow occurs, the result saturates to the minimum or maximum signed word value. No condition register fields are affected.

The vsubsws instruction is useful for performing vectorized subtraction of signed words with saturation, ensuring that results do not overflow. Ensure that the VEC bit in the MSR register is set to enable vector operations; otherwise, a Vector_Unavailable exception will be raised. Be aware that the SAT flag in the VSCR register indicates if any result was saturated during the operation.


Summary: Adds the contents of two single-precision floating-point numbers and places the result in a double-precision format.

The instruction adds the contents of src1 and src2, producing a sum with unbounded range and precision. The sum is normalized and rounded to single-precision using the rounding mode specified by RN. The result is placed into doubleword element 0 of VSR[XT] in double-precision format, while doubleword element 1 of VSR[XT] is set to 0.

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src1 ← bfp_CONVERT_FROM_BFP64(VSR[VRA+32].dword[0])
src2 ← bfp_CONVERT_FROM_BFP64(VSR[VRB+32].dword[0])
v ← bfp_ADD(src1, src2)
rnd ← bfp_ROUND_TO_BFP32(FPSCR.RN, v)
result32 ← bfp32_CONVERT_FROM_BFP(rnd)
result64 ← bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vxisi_flag=1 then SetFX(FPSCR.VXISI)
if ox_flag=1 then SetFX(FPSCR.OX)
if ux_flag=1 then SetFX(FPSCR.UX)
if xx_flag=1 then SetFX(FPSCR.XX)
vx_flag ← vxsnan_flag | vxisi_flag
vex_flag ← FPSCR.VE & vx_flag
if vex_flag=0 then do
    VSR[32×TX+T].dword[0] ← result64
    VSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000
    FPSCR.FPRF ← fprf_CLASS_BFP32(result32)
    FPSCR.FR ← inc_flag
    FPSCR.FI ← xx_flag
end else do
    FPSCR.FR ← 0b0
    FPSCR.FI ← 0b0
end

Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.


Summary: Subtracts the contents of two single-precision floating-point values and places the result in a vector register.

The instruction subtracts the double-precision floating-point value in doubleword element 0 of VSR[XB] from the double-precision floating-point value in doubleword element 0 of VSR[XA], negates the result, and adds it to src1. The result is normalized and rounded to single-precision using the rounding mode specified by RN.

if src1 is NaN or src2 is NaN then
    v <- Q(src1) if src1 is SNaN else Q(src2) if src2 is SNaN else dQNaN
else if src1 is +Infinity and src2 is +Infinity then
    v <- +Infinity
    vxisi_flag <- 1
else if src1 is -Infinity and src2 is -Infinity then
    v <- -Infinity
    vxisi_flag <- 1
else if src1 is NZF and src2 is NZF then
    v <- S(src1, src2)
else if src1 is Zero and src2 is Zero then
    v <- Rezd
else if src1 is +Zero and src2 is -Zero then
    v <- +Zero
else if src1 is -Zero and src2 is +Zero then
    v <- -Zero
else if src1 is NZF and src2 is Zero then
    v <- src1
else if src1 is Zero and src2 is NZF then
    v <- -src2
else if src1 is +Infinity and src2 is NZF then
    v <- +Infinity
    vxisi_flag <- 1
else if src1 is NZF and src2 is +Infinity then
    v <- -Infinity
    vxisi_flag <- 1
else if src1 is -Infinity and src2 is NZF then
    v <- -Infinity
    vxisi_flag <- 1
else if src1 is NZF and src2 is -Infinity then
    v <- +Infinity
    vxisi_flag <- 1
else if src1 is QNaN or src2 is QNaN then
    v <- src1 if src1 is QNaN else src2 if src2 is QNaN else dQNaN
else if src1 is SNaN or src2 is SNaN then
    v <- Q(src1) if src1 is SNaN else Q(src2) if src2 is SNaN else dQNaN
    vxsnan_flag <- 1


Summary: Multiplies two single-precision floating-point numbers and stores the result in a doubleword element of a VSX register.

Multiplies the single-precision floating-point value in the lower 32 bits of XA by the single-precision floating-point value in the lower 32 bits of XB, produces a single-precision result, and stores it in the lower 32 bits of XT. The upper 32 bits of XT are set to zero. FPSCR is updated with the exception flags and result class from the operation.

SP_A ← XA[32:63]
SP_B ← XB[32:63]
product ← SPFP_multiply(SP_A, SP_B)
XT[0:31] ← 0
XT[32:63] ← product
FPSCR ← update_fpscr(FPSCR, product)


Summary: Divides the contents of two doubleword elements in VSX registers and places the result in a single-precision format.

The instruction divides the double-precision floating-point value in doubleword element 0 of VSR[XB] by the double-precision floating-point value in doubleword element 0 of VSR[XA]. The quotient is normalized, rounded to single-precision using the rounding mode specified by RN, and placed into doubleword element 0 of VSR[XT] in double-precision format. Doubleword element 1 of VSR[XT] is set to 0.

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])
src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
v    ←bfp_DIVIDE(src1,src2)
rnd      ←bfp_ROUND_TO_BFP32(FPSCR.RN,v)
result32 ←bfp32_CONVERT_FROM_BFP(rnd)
result64 ←bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vxidi_flag=1 then SetFX(FPSCR.VXIDI)
if vxzdz_flag=1 then SetFX(FPSCR.VXZDZ)
vx_flag  ←vxsnan_flag | vxidi_flag | vxzdz_flag
vex_flag ←FPSCR.VE & vx_flag
zex_flag ←FPSCR.ZE & zx_flag
if vex_flag=0 & zex_flag=0 then do
   VSR[32×TX+T].dword[0] ←result64
   VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000
   FPSCR.FPRF ←fprf_CLASS_BFP32(result32)
   FPSCR.FR  ←inc_flag
   FPSCR.FI  ←xx_flag
else do
   FPSCR.FR  ←0b0
   FPSCR.FI  ←0b0
end

FPSCR, VXSNAN, VXIDI, VXZDZ, OX, UX, ZX, XX


Vector Scalar Maximum Double-Precision Floating-Point

Summary: Compares the doubleword elements of two vector scalar registers and stores the maximum value in another vector scalar register.

Compares the double-precision floating-point value in XA with the value in XB and stores the maximum (or quiet NaN if either operand is NaN) in XT. Following IEEE 754 semantics, quiet NaNs propagate, and negative zero is considered less than positive zero. FPSCR is updated with the comparison result flags.

result ← DPFP_maximum(XA[0:63], XB[0:63])
XT[0:63] ← result
FPSCR ← update_fpscr(FPSCR, result)

This instruction can be used to operate on single-precision source operands. Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.


Summary: Computes the minimum of two double-precision floating-point values and places the result into a vector scalar register.

Compares the double-precision floating-point value in XA with the value in XB and stores the minimum (or quiet NaN if either operand is NaN) in XT. Following IEEE 754 semantics, quiet NaNs propagate, and negative zero is considered less than positive zero. FPSCR is updated with the comparison result flags.

result ← DPFP_minimum(XA[0:63], XB[0:63])
XT[0:63] ← result
FPSCR ← update_fpscr(FPSCR, result)

The minimum of +0 and -0 is -0. The minimum of a QNaN and any value is that value. The minimum of any value and an SNaN is that SNaN converted to a QNaN. FPRF, FR and FI are not modified. If a trap-enabled invalid operation exception occurs, VSR[XT] is not modified. This instruction can be used to operate on single-precision source operands.


Summary: Computes the unbounded-precision square root of a double-precision floating-point value and rounds it to double-precision format.

The instruction computes the square root of the double-precision floating-point value in doubleword element 0 of VSR[XB]. The result is placed into doubleword element 0 of VSR[XT] in double-precision format, with doubleword element 1 set to 0. The FPRF is updated to reflect the class and sign of the result, and FR and FI are set based on rounding operations.

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src ← bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
v ← bfp_SQUARE_ROOT(src)
rnd ← bfp_ROUND_TO_BFP64(0b0, FPSCR.RN, v)
result ← bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vxsqrt_flag=1 then SetFX(FPSCR.VXSQRT)
if xx_flag=1 then SetFX(FPSCR.XX)
vx_flag ← vxsnan_flag | vxsqrt_flag
vex_flag ← FPSCR.VE & vx_flag
if vex_flag=0 then do
    VSR[32×TX+T].dword[0] ← result
    VSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000
    FPSCR.FPRF ← fprf_CLASS_BFP64(result)
    FPSCR.FR ← inc_flag
    FPSCR.FI ← xx_flag
end else do
    FPSCR.FR ← 0b0
    FPSCR.FI ← 0b0
end

FPSCR (FPRF, FR, FI, FX, XX), VXSNAN, VXSQRT


VSX Scalar Absolute Value Double-Precision

Summary: Computes the absolute value of a double-precision floating-point number.

The absolute value of the double-precision floating-point operand in doubleword element 0 of VSR[XB] is placed into doubleword element 0 of VSR[XT] in double-precision format. The contents of doubleword element 1 of VSR[XT] are set to 0.

if MSR.VSX=0 then VSX_Unavailable()
src ←VSR[32×BX+B].dword[0]
Let XT be the value 32×TX + T.
VSR[XT].dword[0] ←bfp64_ABSOLUTE(src)
VSR[XT].dword[1] ←0x0000_0000_0000_0000

This instruction can be used to operate on a single-precision source operand.
Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.


Summary: Negates the contents of a double-precision floating-point register and stores the result in another register.

The instruction negates the value in VSR[32×BX+B].dword[0] (which represents a single-precision floating-point number) and places the result into VSR[32×TX+T].dword[0]. The contents of doubleword element 1 of VSR[XT] are set to 0.

if MSR.VSX=0 then
    VSX_Unavailable()
src ←VSR[32×BX+B].dword[0]
VSR[32×TX+T].dword[0] ←bfp64_NEGATE(src)
VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000

This instruction can be used to operate on a single-precision source operand. Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.


VSX Scalar Compare Ordered Double-Precision

Summary: Compares two double-precision floating-point values and sets the condition register based on the comparison.

Performs an ordered comparison of the double-precision floating-point values in XA and XB, setting the specified CR field (BF) with the comparison result: less-than, greater-than, equal, or unordered. If either operand is a signaling NaN, an invalid operation exception is raised in FPSCR. Quiet NaNs result in an unordered condition.

This instruction can be used to operate on single-precision source operands.


VSX Scalar Compare Unordered Double-Precision

The instruction compares the double-precision floating-point value in doubleword element 0 of VSR[XA] with the double-precision floating-point value in doubleword element 0 of VSR[XB]. The result is placed into CR field BF and the FPCC. If either operand is a NaN, VXSNAN is set.

if 'xscmpudp' then
    src1 <- VSR[XA][0]
    src2 <- VSR[XB][0]
    cc <- C(src1, src2)
    FPCC <- cc
    CR[BF] <- cc
    if vxsnan_flag then
        fx(VXSNAN)
        if VE and not ignore-exception mode then
            error()

This instruction can be used to operate on single-precision source operands. Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register.


Summary: Shifts the contents of a vector register left by a specified number of bits.

The contents of VSR[VRA+32] are shifted left by the number of bits specified in bits 125:127 of VSR[VRB+32]. Bits shifted out of bit 0 are lost, and zeros are supplied to the vacated bits on the right. The result is placed into VSR[VRT+32], except if, for any byte element in VSR[VRB+32], the low-order 3 bits are not equal to the shift amount, then VSR[VRT+32] is undefined.

if MSR.VEC=0 then
    Vector_Unavailable()
sh ←VSR[VRB+32].bit[125:127]
t ←1
do i = 0 to 14
    t ←t & (VSR[VRB+32].byte[i].bit[5:7] = sh)
end
if t=1 then
    VSR[VRT+32] ←VSR[VRA+32] << sh
else
    VSR[VRT+32] ←UNDEFINED

The vsl instruction shifts the contents of a vector register left by a specified number of bits. Ensure that the shift amount is consistent across all byte elements in the control vector to avoid undefined results. This instruction requires the Vector Facility (MSR.VEC) to be enabled; otherwise, it will raise an exception.


Summary: Shifts vector right by octet count in vB.

Shifts the 128-bit value in vA right by the number of octets (bytes) specified in the low 5 bits of vB, filling vacated positions on the left with zeros. The shift amount is taken from bits 123-127 of vB (the low-order 5 bits). No condition register fields are affected.

The vsr instruction is commonly used for bit manipulation in vector operations, where each element of the vector is shifted right by a number of bits specified in a control register. Ensure that the control register contains valid shift amounts to avoid unexpected results. This operation does not require any specific privilege level and will not generate exceptions unless there are alignment issues with the vector data.

shift_count ← vB[123:127]
if shift_count > 16 then shift_count ← 16
vD ← vA >> (shift_count * 8)


Summary: Shifts the contents of a vector register left by a specified number of bytes.

The contents of VSR[VRA+32] are shifted left by the number of bytes specified in bits 121:124 of VSR[VRB+32]. Bytes shifted out of byte 0 are lost, and zeros are supplied to the vacated bytes on the right. The result is placed into VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
shb ← VSR[VRB+32].bit[121:124] << 3
VSR[VRT+32] ← VSR[VRA+32] << shb

A pair of these instructions, specifying the same shift count register, can be used to shift the contents of a VSR left or right by the number of bits (0-127) specified in the shift count register.


Summary: Shifts vector right by byte count.

Shifts the 128-bit value in vA right by the number of octets (bytes) specified in the low 4 bits of vB, filling vacated positions on the left with zeros. This instruction is similar to vsr but uses only the low 4 bits of the shift count, limiting the shift to 0-15 bytes. No condition register fields are affected.

shift_count ← vB[124:127]
vD ← vA >> (shift_count * 8)

The vsro instruction shifts the contents of a vector register right by a specified number of bytes. Ensure that the shift amount is within the valid range (0-15) to avoid undefined behavior. This instruction requires the VEC bit in the MSR to be set; otherwise, it will raise an exception. Be cautious with alignment as shifting by byte boundaries can lead to unexpected results if not handled properly.


Summary: Rotates each byte of the source vector left by a specified number of bits.

For vrlb, each byte in VSR[VRA+32] is rotated left by the number of bits specified in the low-order 3 bits of the corresponding byte in VSR[VRB+32]. The result is stored in VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 7
    src ← VSR[VRA+32].byte[i]
    sh  ← VSR[VRB+32].byte[i].bit[5:7]
    VSR[VRT+32].byte[i] ← src <<< sh

The vrlb instruction rotates each byte in the source vector left by a specified number of bits determined by another vector. Ensure that the Vector Facility is enabled (MSR.VEC=1) to avoid exceptions. The shift amount is derived from the high-order 3 bits of each byte in the second vector, so be cautious with bit manipulation to achieve the desired rotation.


Summary: Rotates each halfword left.

Rotates each of the eight 16-bit elements in vA left by the number of bits specified by the corresponding 16-bit element in vB. The rotate count is masked to bits 0-3 (modulo 16). No condition register or status flags are affected.

The vrlh instruction is commonly used for bit manipulation tasks that require rotating halfwords within a vector. Ensure that the source and destination vectors are properly aligned to avoid data corruption. This instruction operates at user privilege level, but if MSR.VEC is not set, it will raise a Vector_Unavailable exception. Performance may vary based on the specific implementation and the alignment of the input vectors.


Summary: Rotates each word element of the source vector left by a specified number of bits.

For vrlw, each word element in VSR[VRA+32] is rotated left by the number of bits specified in the low-order 5 bits of the corresponding word element in VSR[VRB+32]. The result is placed into the corresponding word element in VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ← VSR[VRA+32].word[i]
    sh ← VSR[VRB+32].word[i].bit[27:31]
    VSR[VRT+32].word[i] ← src1 <<< sh

The vrlw instruction is commonly used for performing bitwise rotations on vector elements. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to 1; otherwise, a Vector_Unavailable exception will be raised. The shift amount is determined by the low-order 5 bits of each word element in the second source vector register (VRB). Be cautious with alignment as unaligned access can lead to performance penalties or exceptions depending on the system configuration.


Summary: Rotates each doubleword left.

Rotates each of the two 64-bit elements in vA left by the number of bits specified by the corresponding 64-bit element in vB. The rotate count is masked to bits 0-5 (modulo 64). No condition register or status flags are affected.

The vrld instruction is commonly used for bit manipulation tasks that require rotating doublewords within a vector. Ensure that the source vectors are properly aligned to avoid unexpected behavior. This instruction operates at user privilege level and will raise an exception if the VEC bit in the MSR register is not set.


Summary: Adds two 128-bit DFP numbers.

Adds two 128-bit Decimal Floating-Point (DFP) values held in vA and vB, storing the result in vD. The operation follows DFP semantics, respecting the current rounding mode in FPSCR and producing an exact result or DFP overflow/underflow exception as appropriate. The FPSCR is updated with exception flags.

The daddq instruction is used for adding two quad-precision decimal numbers. Ensure that the operands are correctly aligned to avoid precision errors. Be aware of potential overflow conditions, which will be indicated in the FPSCR register. This operation requires floating-point privilege level access.

vD ← vA + vB (DFP arithmetic)
FPSCR ← updated with exception flags (XX, ZX, UX, OX, IE)


Summary: Subtracts two 128-bit DFP numbers.

Subtracts the 128-bit Decimal Floating-Point value in vB from vA, storing the result in vD. The operation follows DFP semantics, respecting the current rounding mode in FPSCR and producing an exact result or DFP exception as appropriate. The FPSCR is updated with exception flags.

vD ← vA - vB (DFP arithmetic)
FPSCR ← updated with exception flags (XX, ZX, UX, OX, IE)

The dsubq instruction is used for precise decimal subtraction of quad-precision numbers. Ensure that the operands are correctly aligned and formatted to avoid precision loss. The result's rounding mode is controlled by the FPSCR register, so verify DRN settings before execution. This operation requires floating-point privilege level.


Summary: Multiplies two 128-bit DFP numbers.

Multiplies two 128-bit Decimal Floating-Point values in vA and vB, storing the result in vD. The operation follows DFP semantics, respecting the current rounding mode in FPSCR. The result may be rounded or may signal overflow, underflow, or inexact exception. The FPSCR is updated with exception flags.

vD ← vA × vB (DFP arithmetic)
FPSCR ← updated with exception flags (XX, ZX, UX, OX, IE)

The dmulq instruction is used for multiplying two decimal floating-point numbers with quad-precision. Ensure that the operands are correctly aligned and formatted as DFP. The result's precision is controlled by the FPSCR register, specifically the DRN bits. Be aware of potential rounding errors based on the target format precision.


Summary: Divides two 128-bit DFP numbers.

Divides the 128-bit Decimal Floating-Point value in vA by the value in vB, storing the result in vD. The operation follows DFP semantics, respecting the current rounding mode in FPSCR. Division by zero signals the ZX exception, and inexact results are rounded according to FPSCR[RN]. The FPSCR is updated with exception flags.

vD ← vA ÷ vB (DFP arithmetic)
FPSCR ← updated with exception flags (XX, ZX, UX, OX, IE)

The ddivq instruction is used for performing decimal division with quad-precision operands. Ensure that the operands are correctly aligned and formatted to avoid precision loss. The result rounding mode is controlled by the DRN field in the FPSCR register, so verify this setting before execution. This instruction operates at a privilege level that allows access to floating-point registers and may raise exceptions if operands are invalid or division by zero occurs.


Decimal Compare Unordered Quad-Precision

Summary: Compares two 128-bit DFP numbers (Non-signaling).

Compares two 128-bit Decimal Floating-Point values in vA and vB without signaling an exception on QNaN operands (unordered comparison). The result is written to the condition register field BF as: LT, GT, EQ, or UN (unordered). NaN comparisons result in UN, and FPSCR[VXSNAN] is not set unless SNaN is present.

Use dcmpuq for comparing two DFP operands while handling unordered cases, which include NaNs. Ensure that the operands are properly aligned and check the FPSCR for exception conditions after execution.

if vA is NaN or vB is NaN then
  CR[BF] ← 0b0001 (UN)
else if vA < vB then
  CR[BF] ← 0b1000 (LT)
else if vA > vB then
  CR[BF] ← 0b0100 (GT)
else
  CR[BF] ← 0b0010 (EQ)


Summary: Compares two DFP values and sets the condition register based on their order.

if vA is SNaN or vB is SNaN then
  FPSCR[VXSNAN] ← 1
if vA is NaN or vB is NaN then
  CR[BF] ← 0b0001 (UN)
else if vA < vB then
  CR[BF] ← 0b1000 (LT)
else if vA > vB then
  CR[BF] ← 0b0100 (GT)
else
  CR[BF] ← 0b0010 (EQ)

Compares two 128-bit Decimal Floating-Point values in vA and vB with signaling behavior on NaN (ordered comparison). The result is written to the condition register field BF as: LT, GT, EQ, or UN (unordered). If either operand is QNaN, the VXSNAN exception is raised and FPSCR[VE] or FPSCR[FEX] handling applies; SNaN always signals VXSNAN.

The dcmpoq instruction is used to compare two quad-precision decimal floating-point numbers. It sets the CR0 register field to indicate whether the first operand is less than, greater than, or equal to the second operand. Ensure that operands are properly aligned and that the FPSCR (Floating Point Status and Control Register) is correctly configured for accurate comparison results.


Summary: Adjusts exponent of 128-bit DFP number.

Quantizes a 128-bit decimal floating-point number in vA to match the exponent of the reference value in vB, producing a result in vD. The operation adjusts the exponent and coefficient of the source operand while preserving the value's significance. Rounding is performed if necessary according to the current DFP rounding mode in FPSCR. The instruction is part of the Decimal Floating-Point extension.

The dquaq instruction is used to convert and round a decimal floating-point number to a specified exponent. Ensure the operand is correctly aligned and check the FPSCR for rounding mode settings. This instruction operates at the problem state privilege level and may raise exceptions if overflow occurs or if invalid operands are provided.


Summary: Rerounds a 128-bit DFP number to fewer digits.

Rerounds a 128-bit decimal floating-point number in vA to a precision specified by control information in vB, storing the result in vD. This operation reduces the number of significant digits while adjusting the exponent accordingly. Rounding uses the mode specified in FPSCR[RN]. The instruction is part of the Decimal Floating-Point extension.

The drrndq instruction is used for precise decimal arithmetic operations, particularly useful in financial applications where exact decimal representation is crucial. Ensure that the source operands (FRA and FRB) are correctly aligned and formatted as quad-precision decimals to avoid precision loss. The rounding mode control (RMC) should be set according to the desired rounding behavior, such as round-to-nearest or truncate. This instruction operates at a privilege level that allows access to floating-point operations, and it may raise exceptions if operands are out of range or if there are invalid operations.


Decimal Convert From Fixed Quad-Precision

Summary: Converts 64-bit integer to 128-bit DFP.

Converts a 64-bit signed fixed-point integer from vB into a 128-bit decimal floating-point number, storing the result in vD. The integer is interpreted as an exact value with an implied exponent of zero. No rounding is required since the conversion is exact. The instruction is part of the Decimal Floating-Point extension.


Summary: Converts 128-bit DFP to 64-bit integer.

Converts a 128-bit decimal floating-point number from vB into a 64-bit signed integer, storing the result in vD. The conversion rounds toward zero (truncates). If the DFP value is out of range for a 64-bit integer or is NaN, the result is undefined and FPSCR status flags may be set. The instruction is part of the Decimal Floating-Point extension.

vD ← ConvertToFixedDFP128(vB, FPSCR[RN])

The dctfixq instruction is used to convert a DFP Extended value to a 64-bit signed integer. It rounds the result and preserves the sign of the source operand. If the source is zero, the result is explicitly set to +0. This instruction operates at the FPSCR privilege level and may raise exceptions based on rounding modes or overflow conditions.


Summary: Extracts exponent from 128-bit DFP.

Extracts the exponent field from a 128-bit decimal floating-point number in vB and stores it as a 64-bit signed integer in vD. For normal numbers, the result is the biased exponent; for special values (zero, infinity, NaN), the result follows the DFP specification. The instruction is part of the Decimal Floating-Point extension.

The dxexq instruction is used to extract the biased exponent from a quad-precision decimal floating-point number. Ensure the source operand is properly aligned, as misalignment can lead to exceptions. This operation requires FPSCR (Floating Point Status and Control Register) to be correctly set for proper rounding modes and exception handling.


Summary: Inserts exponent into 128-bit DFP.

Inserts a 64-bit signed exponent from vB into a 128-bit DFP coefficient from vA, producing a complete 128-bit DFP number in vD. The coefficient in vA is interpreted as having an exponent of zero, and the exponent from vB replaces it. The resulting value may be a normal number, zero, or special value depending on the inputs. The instruction is part of the Decimal Floating-Point extension.

The `diexq` instruction is used to insert the biased exponent from one decimal floating-point (DFP) operand into another. Ensure both operands are properly aligned and that the FPSCR register is correctly configured for desired rounding modes and exception handling. This instruction operates at the problem state privilege level, so ensure your program has the appropriate privileges. Be cautious of potential exceptions such as invalid operations or overflow, which may require additional error handling code.


Summary: Encodes 128-bit DFP to BCD.

Encodes a 128-bit decimal floating-point number from vB into binary-coded decimal (BCD) format, storing the result in vD. The sign field S specifies how the sign is encoded. The instruction converts the DFP representation to BCD digits with appropriate sign handling. The instruction is part of the Decimal Floating-Point extension.

The denbcdq instruction is used to convert BCD values into DPD format, which is essential for handling high-precision decimal arithmetic. Ensure that the input data is correctly aligned and formatted as BCD before encoding. This instruction operates at user privilege level and may raise exceptions if the input data contains invalid BCD values.


Summary: Decodes BCD to 128-bit DFP.

Decodes a binary-coded decimal (BCD) value from vB into a 128-bit decimal floating-point number, storing the result in vD. The sign field SP specifies how to interpret the sign encoding in the BCD representation. The instruction converts BCD digits to the internal DFP representation. The instruction is part of the Decimal Floating-Point extension.

The ddedpdq instruction is used to convert a DPD-encoded decimal value from one register to BCD format in another. Ensure that the source register contains valid DPD data; otherwise, the result will be undefined. This operation does not require any specific privilege level but may alter the FPSCR register based on the conversion outcome.


Summary: Splat a byte from one vector element into all elements of another vector.

Splats (replicates) a single byte element from vB across all 16 byte elements of vD. The byte element selected is determined by the 4-bit unsigned immediate UIM (where UIM=0 selects byte 0, UIM=15 selects byte 15 in big-endian order). No status flags are affected. This is a VMX/AltiVec instruction.

index ← UIM
vD ← replicate(vB[index*8:index*8+7] to all 16 byte positions)

The Vector Splat instructions can be used in preparation for performing arithmetic for which one source vector is to consist of elements that all have the same value (e.g., multiplying all elements of a VSR by a constant).


Summary: Duplicates a halfword element across the vector.

Splats (replicates) a single halfword element from vB across all 8 halfword elements of vD. The halfword element selected is determined by the 3-bit unsigned immediate UIM (where UIM=0 selects halfword 0, UIM=7 selects halfword 7 in big-endian order). No status flags are affected. This is a VMX/AltiVec instruction.

index ← UIM
vD ← replicate(vB[index*16:index*16+15] to all 8 halfword positions)

The vsplth instruction is commonly used when you need to replicate a specific halfword from a source vector into all elements of a destination vector, which is useful for operations requiring uniform operands. Ensure the specified bit position (b) is within the valid range to avoid undefined behavior. This instruction operates at user privilege level and does not generate exceptions under normal circumstances.


Summary: Splat an immediate signed byte value into all elements of a vector register.

Splats a 5-bit signed immediate value into all 16 byte elements of vD, sign-extended to 8 bits per byte. The immediate SIM is a signed 5-bit value (range -16 to 15). No status flags are affected. This is a VMX/AltiVec instruction.

value ← sign_extend(SIM, 8)
vD ← replicate(value to all 16 byte positions)

This instruction is used to fill a vector register with the sign-extended value of an 8-bit immediate. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise a Vector Unavailable exception. The immediate value is sign-extended and replicated across all elements of the target vector register.


Summary: Fills vector with immediate 5-bit signed value.

Splats a 5-bit signed immediate value into all 8 halfword elements of vD, sign-extended to 16 bits per halfword. The immediate SIM is a signed 5-bit value (range -16 to 15). No status flags are affected. This is a VMX/AltiVec instruction.

value ← sign_extend(SIM, 16)
vD ← replicate(value to all 8 halfword positions)

The vspltish instruction is used to replicate a signed halfword value across all elements of a vector register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The immediate value is sign-extended to 16 bits and then replicated in each halfword element of the target vector register.


Summary: Splat a signed immediate value into all elements of a vector register.

Splats a 5-bit signed immediate value into all 4 word elements of vD, sign-extended to 32 bits per word. The immediate SIM is a signed 5-bit value (range -16 to 15). No status flags are affected. This is a VMX/AltiVec instruction.

value ← sign_extend(SIM, 32)
vD ← replicate(value to all 4 word positions)

The vspltisw instruction is commonly used to initialize a vector register with a repeated signed word value. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The immediate value is sign-extended from 16 bits to 32 bits and replicated across all four elements of the target vector register.


Summary: Shifts each byte element of the source vector left by a specified number of bits.

For vslb, each byte element of VSR[VRA+32] is shifted left by the number of bits specified in the low-order 3 bits of the corresponding byte element of VSR[VRB+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 15
    src1 ← VSR[VRA+32].byte[i]
    src2 ← VSR[VRB+32].byte[i].bit[5:7]
    VSR[VRT+32].byte[i] ← src1 << src2

The vslb instruction shifts each byte of the source vector left by a specified number of bits, determined by the lower 3 bits of the corresponding byte in the second source vector. Ensure that the Vector Facility is enabled (MSR.VEC=1) to avoid a Vector_Unavailable exception. This operation is useful for bit manipulation tasks but requires careful handling of alignment and privilege levels.


Summary: Shifts each halfword left.

Shifts each of the 8 halfword elements in vA left by a variable number of bits specified by the low 4 bits of the corresponding halfword element in vB. Bits shifted out are lost; positions vacated are filled with zeros. No status flags are affected. This is a VMX/AltiVec instruction.

for i ← 0 to 7 do
  shift_amount ← vB[i*16:i*16+3]
  vD[i*16:i*16+15] ← vA[i*16:i*16+15] << shift_amount

The vslh instruction shifts each halfword element of the source vector left by a specified number of bits. Ensure that the shift amount is within the valid range to avoid unexpected results. This instruction operates at the user privilege level and does not generate exceptions under normal conditions.


Summary: Shifts each byte element of the source vector right by a specified number of bits.

For vsrb, each byte element of VSR[VRA+32] is shifted right by the number of bits specified in the low-order 3 bits of the corresponding byte element in VSR[VRB+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 15
    src1 ← VSR[VRA+32].byte[i]
    src2 ← VSR[VRB+32].byte[i].bit[5:7]
    VSR[VRT+32].byte[i] ← CHOP8(EXTZ(src1) >> src2)
end

The vsrb instruction shifts each byte of the source vector right by a specified number of bits, determined by the lower 3 bits of the corresponding byte in another vector. Ensure that the Vector Facility is enabled (MSR.VEC=1); otherwise, a Vector_Unavailable exception will be raised. This operation is useful for bit manipulation tasks but requires careful handling of alignment and privilege levels to avoid exceptions.


Summary: Shifts the contents of each element in a vector right by a specified number of bits.

Shifts each of the 8 halfword elements in vA right (logically, without sign extension) by a variable number of bits specified by the low 4 bits of the corresponding halfword element in vB. Bits shifted out are lost; positions vacated are filled with zeros. No status flags are affected. This is a VMX/AltiVec instruction.

for i ← 0 to 7 do
  shift_amount ← vB[i*16:i*16+3]
  vD[i*16:i*16+15] ← vA[i*16:i*16+15] >> shift_amount

The vsrh instruction is used to perform element-wise right shifts on halfwords within a vector. Ensure that the shift amounts in the second source vector are within the range of 0-15 to avoid unexpected behavior. This instruction requires the VEC bit in the MSR register to be set; otherwise, it will raise an exception. Be cautious with alignment as unaligned access might lead to performance penalties or exceptions depending on the system configuration.


Summary: Shifts each word element of the source vector right by a specified number of bits.

For vsrw, each word element of VSR[VRA+32] is shifted right by the number of bits specified in the low-order 5 bits of the corresponding word element of VSR[VRB+32]. The result is placed into the corresponding word element of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ← VSR[VRA+32].word[i]
    src2 ← VSR[VRB+32].word[i].bit[27:31]
    VSR[VRT+32].word[i] ← CHOP32(EXTZ(src1) >> src2)
end

The vsrw instruction shifts each word element of the source vector right by a specified number of bits, determined by the corresponding word element in another vector. Ensure that the shift amount is within the range of 0 to 31 to avoid undefined behavior. This instruction requires the Vector Facility to be enabled; otherwise, it will raise an exception.


Summary: Shifts each byte of the source vector right by a specified number of bits, filling vacated bits with copies of the sign bit.

For vsrab, each byte element in VSR[VRA+32] is shifted right by the number of bits specified in the low-order 3 bits of the corresponding byte element in VSR[VRB+32]. The result is placed into the corresponding byte element in VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 15
    src1 ← VSR[VRA+32].byte[i]
    src2 ← VSR[VRB+32].byte[i].bit[5:7]
    VSR[VRT+32].byte[i] ← CHOP8(EXTS(src1) >> src2)
end

The vsrab instruction performs a right algebraic shift on each byte of the source vector, using the low-order 3 bits of the corresponding byte in the second source vector as the shift amount. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates at the user privilege level and does not generate exceptions for valid shifts; however, invalid shifts (e.g., shifting more than 7 bits) will result in undefined behavior.


Summary: Arithmetic right shift of halfwords.

Shifts each of the 8 halfword elements in vA right arithmetically (with sign extension) by a variable number of bits specified by the low 4 bits of the corresponding halfword element in vB. The sign bit is replicated into vacated positions; bits shifted out are lost. No status flags are affected. This is a VMX/AltiVec instruction.

for i ← 0 to 7 do
  shift_amount ← vB[i*16:i*16+3]
  vD[i*16:i*16+15] ← arithmetic_shift_right(vA[i*16:i*16+15], shift_amount)

The vsrah instruction is used to perform right algebraic shifts on halfword elements of a vector. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The shift amount for each element is determined by the low-order 4 bits of the corresponding element in the second source vector. Be cautious with alignment as halfword operations require proper alignment to avoid undefined behavior.


Summary: Shifts each word element of the source vector right by a specified number of bits, filling vacated bits with copies of the sign bit.

For vsraw, each word element of VSR[VRA+32] is shifted right by the number of bits specified in the low-order 5 bits of the corresponding word element of VSR[VRB+32]. The result is placed into the corresponding word element of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ← VSR[VRA+32].word[i]
    src2 ← VSR[VRB+32].word[i].bit[27:31]
    VSR[VRT+32].word[i] ← CHOP32(EXTS(src1) >> src2)
end

The vsraw instruction performs a right algebraic shift on each word element of the source vector, using the low-order 5 bits of the corresponding element in the second source vector as the shift count. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. Be cautious with alignment; while vsraw does not require specific alignment, incorrect alignment can lead to performance penalties or exceptions if data is not properly aligned in memory.


Summary: Merges even word elements from two vector registers into a third.

The contents of word element 0 of VSR[VRA+32] are placed into word element 0 of VSR[VRT+32]. The contents of word element 0 of VSR[VRB+32] are placed into word element 1 of VSR[VRT+32]. The contents of word element 2 of VSR[VRA+32] are placed into word element 2 of VSR[VRT+32]. The contents of word element 2 of VSR[VRB+32] are placed into word element 3 of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
else
    VSR[VRT+32].word[0] ←VSR[VRA+32].word[0]
    VSR[VRT+32].word[1] ←VSR[VRB+32].word[0]
    VSR[VRT+32].word[2] ←VSR[VRA+32].word[2]
    VSR[VRT+32].word[3] ←VSR[VRB+32].word[2]

vmrgew is treated as a Vector instruction in terms of resource availability.


Summary: Merges odd words from two vectors.

Merges the odd-indexed words (words 1 and 3) from vector registers vA and vB into vD. This instruction interleaves odd-positioned word elements: vD[0] ← vA[1], vD[1] ← vB[1], vD[2] ← vA[3], vD[3] ← vB[3]. No condition flags are affected.

The vmrgow instruction is used to merge odd-numbered words from two source vectors into a destination vector. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set; otherwise, a Vector_Unavailable exception will be raised. This instruction operates on 128-bit vectors and requires proper alignment of the source and destination registers.


Summary: Multiplies the even-indexed bytes of two vector registers and stores the results in a destination vector register.

For vmulesb, each pair of even-indexed bytes from VSR[VRA+32] and VSR[VRB+32] are multiplied, and the 16-bit products are stored in halfwords of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 7
    src1 ←EXTS(VSR[VRA+32].byte[2×i])
    src2 ←EXTS(VSR[VRB+32].byte[2×i])
    VSR[VRT+32].hword[i] ←CHOP16(src1 × src2)
end

The vmulesb instruction multiplies even-indexed bytes from two vector registers and stores the 16-bit products in another vector register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on 32-byte vectors, so ensure proper alignment of data for optimal performance. Be cautious with overflow conditions as the multiplication results are truncated to 16 bits.


Summary: Multiplies even-indexed bytes of two vector registers and stores the results in a destination vector register.

For vmuleub, each pair of even-indexed bytes from VSR[VRA+32] and VSR[VRB+32] are multiplied, and the 16-bit products are stored in halfwords of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 7
    src1 ←EXTZ(VSR[VRA+32].byte[2×i])
    src2 ←EXTZ(VSR[VRB+32].byte[2×i])
    VSR[VRT+32].hword[i] ←CHOP16(src1 × src2)
end

This instruction multiplies even-indexed bytes from two vector registers and stores the 16-bit products in another vector register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. Be cautious of overflow, as the multiplication results are truncated to 16 bits.


Summary: Multiplies the even-numbered halfwords of two vector registers and places the results into a destination vector register.

For vmulesh, the signed integer value in each even-numbered halfword element of VSR[VRA+32] is multiplied by the corresponding signed integer value in each even-numbered halfword element of VSR[VRB+32]. The 32-bit product is placed into each word element of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ←EXTS(VSR[VRA+32].hword[2×i])
    src2 ←EXTS(VSR[VRB+32].hword[2×i])
    VSR[VRT+32].word[i] ←CHOP32(src1 × src2)
end

This instruction is used for multiplying signed halfwords from two vector registers and storing the 32-bit results in another vector register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation processes even-numbered halfwords, so developers should ensure proper alignment of data within the vector registers to avoid unexpected results.


For vmuleuh, each pair of even-numbered halfwords from VSR[VRA+32] and VSR[VRB+32] are multiplied, and the 32-bit products are placed into corresponding word elements of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ← EXTZ(VSR[VRA+32].hword[2×i])
    src2 ← EXTZ(VSR[VRB+32].hword[2×i])
    VSR[VRT+32].word[i] ← CHOP32(src1 × src2)
end

This instruction multiplies even-numbered halfwords from two vector registers and stores the 32-bit products in another register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. Be cautious of overflow, as only the lower 32 bits of each product are stored. This operation requires the use of VSX (Vector Scalar Extensions) registers.


Summary: Multiplies odd signed bytes to halfwords.

Multiplies the odd-indexed signed bytes from vA and vB, producing signed halfword results in vD. Operates on bytes at indices 1, 3, 5, 7, 9, 11, 13, 15, generating four halfword products. No condition flags are affected.

This instruction is useful for performing element-wise multiplication of odd-numbered bytes from two vectors, storing the results as signed halfwords. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. The operation respects byte ordering, so developers must ensure proper alignment and data format to avoid unexpected results.


Summary: Multiplies odd unsigned bytes to halfwords.

Multiplies the odd-indexed unsigned bytes from vA and vB, producing unsigned halfword results in vD. Operates on bytes at indices 1, 3, 5, 7, 9, 11, 13, 15, generating eight halfword products without sign extension. No condition flags are affected.

This instruction is useful for performing element-wise multiplication of odd-numbered bytes from two vectors. Ensure that the input vectors are properly aligned to avoid unexpected results. The operation does not require any special privileges, but it's important to handle potential overflow by zero-extending the 8-bit result to 16 bits.


Summary: Multiplies odd signed halfwords to words.

Multiplies the odd-indexed signed halfwords from vA and vB, producing signed word results in vD. Operates on halfwords at indices 1 and 3, generating two word products. No condition flags are affected.

This instruction is useful for performing element-wise multiplication of odd-numbered signed halfwords from two vectors. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The result is stored as 32-bit words in the destination vector, so ensure proper alignment and size of the vectors to avoid unexpected behavior.


Summary: Multiplies odd unsigned halfwords to words.

Multiplies the odd-indexed unsigned halfwords from vA and vB, producing unsigned word results in vD. Operates on halfwords at indices 1 and 3, generating four word products without sign extension. No condition flags are affected.

This instruction is useful for performing element-wise multiplication of unsigned halfwords from two vectors. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation targets odd-numbered halfwords, so developers should align their data accordingly to achieve the desired results.


Vector Absolute Difference Unsigned Byte

Summary: Returns the absolute value of the difference of integer values in byte elements.

For vabsdub, the absolute value of the difference between corresponding byte elements of VSR[VRA+32] and VSR[VRB+32] is placed into corresponding byte elements of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 15
    src1 ← EXTZ(VSR[VRA+32].byte[i])
    src2 ← EXTZ(VSR[VRB+32].byte[i])
    if src1 > src2 then
        VSR[VRT+32].byte[i] ← CHOP8(src1 + ¬src2 + 1)
    else
        VSR[VRT+32].byte[i] ← CHOP8(src2 + ¬src1 + 1)
end

This instruction computes the absolute difference between corresponding bytes of two vector registers and stores the result in another register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. The operation does not require any specific alignment, but both input vectors must be properly loaded into the specified registers. This instruction operates at a high performance due to its parallel processing capabilities on vector elements.


Vector Absolute Difference Unsigned Halfword

Summary: Computes |A - B| for halfwords.

Computes the absolute value of the difference between corresponding unsigned halfwords in vA and vB, storing results in vD. Each result is calculated as |vA[i] - vB[i]| for each of four halfword elements. No condition flags are affected.

The vabsduh instruction is commonly used for vectorized image processing tasks where pixel intensity differences need to be calculated. Ensure that the input vectors are properly aligned to halfword boundaries to avoid misaligned access exceptions. This instruction operates at user privilege level and does not generate any exceptions under normal operation, but it will raise a Vector_Unavailable exception if the VEC bit in the MSR is not set.


Vector Absolute Difference Unsigned Word

Summary: Calculates the absolute difference of unsigned words from two vector registers and stores the result in another vector register.

For vabsduw, the absolute difference of each word element from VSR[VRA+32] and VSR[VRB+32] is calculated and stored in VSR[VRT+32].

if MSR.VEC=0 then Vector_Unavailable()
do i = 0 to 3
    src1 ←EXTZ(VSR[VRA+32].word[i])
    src2 ←EXTZ(VSR[VRB+32].word[i])

    if src1 > src2 then
        VSR[VRT+32].word[i] ←CHOP32(src1 + ¬src2 + 1)
    else
        VSR[VRT+32].word[i] ←CHOP32(src2 + ¬src1 + 1)
end

This instruction calculates the absolute difference of each word element between two vector registers and stores the result in another register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. The operation handles unsigned integers, so be cautious with negative values if they are interpreted as signed. This instruction does not require any specific alignment for the data it operates on.


VSX Scalar Maximum Type-C Quad-Precision

Summary: Compares two quad-precision floating-point values and selects the maximum.

Compares two quad-precision floating-point values in VSRs and returns the maximum, using Type-C comparison rules (NaN handling as per VSX specification). Results are written to the VSR specified by XT. No exception or condition register fields are altered unless Rc=1 for VSX comparisons.

fD ← max(fA, fB) using Type-C comparison
if fA is NaN or fB is NaN then
  fD ← QNaN
end if

xsmaxcqp can be used to implement the C/C++ conditional operation (x>y)?x:y for quad-precision arguments. VSR[VRT+32] ←result


VSX Scalar Minimum Type-C Quad-Precision

Summary: Compares two quad-precision floating-point values and selects the minimum value.

Compares two quad-precision floating-point values in VSRs and returns the minimum, using Type-C comparison rules (NaN handling as per VSX specification). Results are written to the VSR specified by XT. No exception or condition register fields are altered unless Rc=1 for VSX comparisons.

fD ← min(fA, fB) using Type-C comparison
if fA is NaN or fB is NaN then
  fD ← QNaN
end if

xsmincqp can be used to implement the C/C++ conditional operator (x<y)?x:y for quad-precision arguments.


Summary: Copies sign from B to A (128-bit).

Copies the sign bit from the quad-precision floating-point value in vB to the quad-precision value in vA, placing the result in vD. The magnitude of vA is preserved while the sign of vB is applied. No condition register or status flags are affected.

The xscpsgnqp instruction is used to copy the sign bit from one quad-precision floating-point number to another while keeping its magnitude unchanged. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking and setting the appropriate bit in the MSR register. This instruction operates on 128-bit values, so both source operands must be properly aligned. Be cautious of potential exceptions if the VSX is not available or if there are alignment issues.


VSX Scalar Test Data Class Quad-Precision

Summary: Tests the data class of a quad-precision floating-point value and sets condition register bits based on the result.

Tests the data class of a quad-precision floating-point value in vB against a data class mask (DCM) and stores the result in condition register field BF. The result is 1 if the value belongs to any class selected by the mask, 0 otherwise. This instruction requires VSX support and updates the specified CR field without affecting other status registers.

if (vB matches data class selected by DCM) then
  CR[BF] ← 0b100
else
  CR[BF] ← 0b000
endif

The xststdcqp instruction is used to test the data class of a quad-precision floating-point value. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register, otherwise, an exception will be raised. The result is stored in the condition register CR and FPSCR.FPCC, which can be used for conditional branching based on the data class match.


VSX Scalar Compare Exponents Quad-Precision

Summary: Compares the exponents of two quad-precision floating-point values and updates the condition register.

The exponent of src1 is compared with the exponent of src2 as unsigned integer values. The result of the compare is placed into FPCC and CR field BF.

if MSR.VSX=0 then VSX_Unavailable()

reset_flags()

src1 ← VSR[VRA+32]
src2 ← VSR[VRB+32]

src1.exponent ← EXTZ(src1.bit[1:15])
src2.exponent ← EXTZ(src2.bit[1:15])
src1.fraction ← EXTZ(src1.bit[16:127])
src2.fraction ← EXTZ(src2.bit[16:127])

src1.class.NaN ← (src1.exponent = 32767) & (src1.fraction != 0)
src2.class.NaN ← (src2.exponent = 32767) & (src2.fraction != 0)

lt_flag ← (src1.exponent < src2.exponent)
gt_flag ← (src1.exponent > src2.exponent)
eq_flag ← (src1.exponent = src2.exponent)
uo_flag ← src1.class.NaN | src2.class.NaN

CR.bit[4×BF+32] ← FPSCR.FL ← !uo_flag & lt_flag
CR.bit[4×BF+33] ← FPSCR.FG ← !uo_flag & gt_flag
CR.bit[4×BF+34] ← FPSCR.FE ← !uo_flag & eq_flag
CR.bit[4×BF+35] ← FPSCR.FU ← uo_flag

This instruction compares the exponents of two quad-precision floating-point numbers. Ensure that VSX is enabled in the MSR register to avoid exceptions. The result is stored in both the CR and FPSCR registers, with flags indicating less than, greater than, equal, or unordered comparisons. Handle NaN values appropriately as they set the unordered flag.


Summary: Checks transaction status and updates CR.

Transaction Check. Tests the state of the current transaction and sets CR field BF based on whether a transaction is active, suspended, or whether a failure has been recorded. No effect outside a transaction.

if Transactional_or_Suspended() then
  CR[4*BF:4*BF+3] ← transaction_state_bits()
else
  CR[4*BF:4*BF+3] ← 0b0000

The tcheck instruction is used to determine the state of the current transaction, setting the condition register field BF accordingly. It should be used within a transactional context; outside transactions, it will clear the specified CR field. Ensure proper alignment and ordering relative to other transactional instructions for accurate state checks.


Summary: Suspends the current transaction.

Suspends the current transaction without aborting it, allowing the processor to handle interrupts and other exceptions while preserving transactional state for later resumption via tresume. This instruction requires Transactional Memory support and always sets CR0 to indicate successful suspension. The instruction has a dot form that updates CR0.


Summary: Resumes a suspended transaction.

Resumes a transaction that was previously suspended via tsuspend, restoring the transactional state and continuing execution. This instruction requires Transactional Memory support and always sets CR0 to indicate successful resumption. The instruction has a dot form that updates CR0.


Summary: Locks a cache line in the L1 cache.

Locks a data cache line in the L1 data cache at the address computed from RA+RB. The cache target (CT) field specifies the cache level and operation type. This is a privileged instruction that provides cache locking hints to the processor and does not modify any general-purpose registers or condition flags.

EA ← (RA|0) + RB
Lock cache line at EA in L1 data cache based on CT


Summary: Provides an ordering function for the effects of all slbieg and slbiag instructions executed by the thread executing the slbsync instruction.

Provides a synchronization point ensuring that all slbieg and slbiag instructions executed by the current thread prior to this instruction have completed their effects before any subsequent memory operations are visible. This is a privileged instruction with no operands that enforces ordering of segment lookaside buffer (SLB) invalidation operations.

slbsync should not be used to synchronize the completion of slbie.

Synchronize all prior slbieg and slbiag effects


Summary: Loads a byte from memory and reserves the location for exclusive access.

Loads a single byte from memory at the address computed from RA+RB into RT, zero-extending to 64 bits, and reserves the location for exclusive access for a subsequent stbcx. instruction. The optional EH field provides a hint for the subsequent store. No condition register fields are affected by this load.

EA ← (RA|0) + RB
RT ← (56)0 || MEM[EA, 1]
RESERVED ← EA

lbarx serves as both a basic and an extended mnemonic. The Assembler will recognize a lbarx mnemonic with four operands as the basic form, and a lbarx mnemonic with three operands as the extended form. In the extended form the EH operand is omitted and assumed to be 0.


Summary: Atomic Load Halfword.

Load the halfword at the effective address into the low 16 bits of RT, sign-extending to 32 bits in 32-bit mode or 64 bits in 64-bit mode, and reserve the addressed halfword for atomic update. Sets the reservation granule; any store to the reserved address by any processor will clear the reservation. This instruction requires that RA or 0 is added to RB to form the effective address.

Places a reservation on the cache line containing the effective address. The subsequent store-conditional (stwcx./stdcx. etc.) will fail if the reservation has been lost due to an intervening store from any processor or an exception. Always check the EQ bit in CR0 after the store-conditional.

EA ← (RA | 0) + RB
RT ← EXTS(MEM(EA, 2), 16)
ReserveWord(EA)


Summary: Loads a quadword from memory and reserves the location for conditional store.

For lqarx, the quadword in storage addressed by EA is loaded into an even-odd pair of GPRs. In Big-Endian mode, the even-numbered GPR is loaded with the doubleword from storage addressed by EA and the odd-numbered GPR is loaded with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed by EA.

if RA = 0 then
    b ← 0
else
    b ← (RA)
EA ← b + (RB)
RESERVE ← 1
RESERVE_LENGTH ← 16
RESERVE_ADDR ← real_addr(EA)
RTp ← MEM(EA, 16)

lqarx serves as both a basic and an extended mnemonic. The Assembler will recognize a lqarx mnemonic with four operands as the basic form, and a lqarx mnemonic with three operands as the extended form. In the extended form the EH operand is omitted and assumed to be 0.

Equivalent to lqarx RTp,RA,RB,0


Summary: Stores a byte from a register to memory if the reservation is valid and matches the address.

The stbcx. instruction stores a byte from the specified source register (RS) into memory at an effective address calculated by adding the contents of two registers (RA and RB). The operation is conditional on whether a reservation exists and matches the target address.

if RA = 0 then
    b ← 0
else
    b ← (RA)
EA ← b + (RB)
if RESERVE then
    if RESERVE_LENGTH = 1 &
       RESERVE_ADDR = real_addr(EA) then
        MEM(EA, 1) ← (RS)56:63
        undefined_case ← 0
        store_performed ← 1
     else
        z ← smallest real page size supported by implementation
        if RESERVE_ADDR ÷ z = real_addr(EA) ÷ z then
          undefined_case ← 1
        else
          undefined_case ← 0
          store_performed ← 0
else
    undefined_case ← 0
    store_performed ← 0
if undefined_case then
    u1 ← undefined 1-bit value
    if u1 then
      MEM(EA, 1) ← (RS)56:63
    u2 ← undefined 1-bit value
    CR0 ← 0b00 || u2 || XERSO
else
    CR0 ← 0b00 || store_performed || XERSO
RESERVE ← 0

Succeeds only if a valid reservation exists on the target address. Sets CR0[EQ] to 1 on success, 0 on failure. Must always be used in a retry loop that re-executes the load-reserve instruction on failure.


Summary: Stores a halfword from a register to memory conditionally based on a reservation.

The sthcx. instruction stores the upper half of the contents of register RS into memory at the effective address (EA) if a reservation exists and meets certain conditions. The EA is calculated as the sum of RA and RB, with RA being zero-extended to 64 bits. If the reservation length is not 2 bytes or the real storage location does not match the reservation, the store may be undefined or no store may occur.

if RA = 0 then
    b ← 0
else
    b ← (RA)
EA ← b + (RB)
if RESERVE then
    if RESERVE_LENGTH = 2 &
       RESERVE_ADDR = real_addr(EA) then
        MEM(EA, 2) ← (RS)48:63
        undefined_case ← 0
        store_performed ← 1
    else
        z ← smallest real page size supported by implementation
        if RESERVE_ADDR ÷ z = real_addr(EA) ÷ z then
          undefined_case ← 1
        else
          undefined_case ← 0
          store_performed ← 0
else
    undefined_case ← 0
    store_performed ← 0
if undefined_case then
    u1 ← undefined 1-bit value
    if u1 then
      MEM(EA, 2) ← (RS)48:63
    u2 ← undefined 1-bit value
    CR0 ← 0b00 || u2 || XERSO
else
    CR0 ← 0b00 || store_performed || XERSO
RESERVE ← 0


Summary: Shifts a 32-bit register left by the amount specified in RB.

n ← (RB)59:63
r ← ROTL32((RS)32:63, n)
if (RB)58 = 0 then
    m ← MASK(32, 63-n)
else
    m ← 640
RA ← r & m

The contents of the low-order 32 bits of register RS are shifted left the number of bits specified by (RB)58:63. Bits shifted out of position 32 are lost. Zeros are supplied to the vacated positions on the right. The 32-bit result is placed into RA32:63. RA0:31 are set to zero. Shift amounts from 32 to 63 give a zero result.

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.


Summary: Performs a logical right shift (zeros shifted in) on a 32-bit word.

Logically shift the 32-bit word in RS right by the number of bits specified in RB[27:31] (only the low 5 bits are used), filling vacated positions with zeros. The result is placed in RA. If Rc=1, CR0 is updated based on the result.


Summary: Performs an arithmetic right shift (sign bit replicated) on a 32-bit word. Updates Carry (CA) if bits are shifted out.

n ← RB[27:31]
if n = 0 then
  RA ← RS
  CA ← 0
else if n < 32 then
  shifted ← RS >> n
  if RS[0] = 1 ∧ (RS & ((1 << n) - 1)) ≠ 0 then
    CA ← 1
  else
    CA ← 0
  RA ← shifted
else
  if RS[0] = 1 then
    RA ← -1
    CA ← 1
  else
    RA ← 0
    CA ← 0
if Rc = 1 then
  CR0 ← (RA = 0) || LT || GT || SO

Arithmetically shift the 32-bit word in RS right by the number of bits specified in RB[27:31], replicating the sign bit into vacated positions. The result is placed in RA. The CA bit in XER is set if any 1-bits are shifted out from a negative value, otherwise cleared. If Rc=1, CR0 is updated based on the result.


Summary: Shifts the contents of a register right by an immediate value and replicates the sign bit.

if 'srawi' then
    n ← SH
    r ← ROTL32((RS)32:63, 64-n)
    m ← MASK(n+32, 63)
    s ← (RS)32
    RA ← r&m | (64s) & ¬m
    carry ← s & ((r & ¬m)32:63 ≠ 0 )
    CA   ← carry
    CA32 ← carry

The low-order 32 bits of register RS are shifted right SH bits. Bits shifted out of position 63 are lost. Bit 32 of RS is replicated to fill the vacated positions on the left. The 32-bit result is placed into RA32:63. Bit 32 of RS is replicated to fill RA0:31. CA and CA32 are set to 1 if the low-order 32 bits of (RS) contain a negative number and any 1-bits are shifted out of position 63; otherwise CA and CA32 are set to 0. A shift amount of zero causes RA to receive EXTS((RS)32:63), and CA and CA32 to be set to 0.


Summary: Stores the low 8 bits of a register to memory.

Store the low 8 bits of RS to the byte in memory at the effective address formed by adding the displacement D (sign-extended) to RA, or to the displacement alone if RA is 0. This is a Base category instruction with no status field updates.

The stb instruction is commonly used to store a single byte from a register into memory. Ensure that the destination address is properly aligned for optimal performance and avoid accessing invalid or protected memory regions to prevent exceptions.


Summary: Stores the high half of a doubleword from a register to memory.

Store the low 16 bits of RS to the halfword in memory at the effective address formed by adding the displacement D (sign-extended) to RA, or to the displacement alone if RA is 0. This is a Base category instruction with no status field updates.

The sth instruction stores the high half of a register value into memory. Ensure that the destination address is properly aligned to avoid alignment faults. This instruction operates at user privilege level and will raise an exception if the EA is out of bounds or if there are insufficient permissions.


Summary: Stores the low 32 bits of a register to memory.

Store the low 32 bits of RS to the word in memory at the effective address formed by adding the displacement D (sign-extended) to RA, or to the displacement alone if RA is 0. This is a Base category instruction with no status field updates.

The stw instruction stores the lower 32 bits of a register into memory. Ensure that the destination address is properly aligned to avoid alignment faults. This instruction operates at user privilege level and will raise an exception if the EA is out of bounds or access permissions are violated.


Summary: Stores a 64-bit doubleword to memory.

Store the 64-bit doubleword in RS to memory at the effective address formed by adding the displacement DS (a 14-bit field shifted left 2 positions, thus a multiple of 4) to RA, or to the displacement alone if RA is 0. This is a Base category, 64-bit mode instruction with no status field updates.

The std instruction stores a doubleword from a source register into memory. Ensure that the destination address is properly aligned to avoid performance penalties or exceptions. This instruction operates at user privilege level and will raise an exception if the EA is out of bounds.


Summary: Unconditional trap. Forces an exception. (Encoded as tw 31, 0, 0).

Trap. Extended mnemonic for TW (tw 31,0,0). Unconditionally traps, transferring control to the system trap handler.

Generates a program exception (System Call or Trap type) when the trap condition is true. The condition codes in TO select which comparisons trigger the trap: bit 0 = LT, bit 1 = GT, bit 2 = EQ, bit 3 = LU (unsigned), bit 4 = GU (unsigned). TO=31 (all bits set) always traps.


Summary: Performs a bitwise Exclusive OR comparison.

RA ← RS ⊕ RB
if Rc = 1 then
  CR0 ← (RA = 0) || LT || GT || SO

Perform a bitwise XOR of RS and RB, storing the result in RA. If Rc=1, CR0 is updated with the comparison flags based on the result. This is a Base category logical instruction.


Summary: Performs a bitwise XOR with a 16-bit unsigned immediate.

XOR Immediate performs a bitwise XOR between the contents of GPR RS and a 16-bit zero-extended unsigned immediate, storing the result in GPR RA. This is a Base category instruction that does not affect condition registers or status fields.

The xori instruction is commonly used for setting or clearing specific bits in a register by XORing with a mask. Be cautious of overflow as this operation does not affect the carry flag. The immediate value is zero-extended to 64 bits before the XOR operation, so ensure that the upper bits are not inadvertently set if only lower bits are intended to be modified.


Summary: Performs a bitwise XOR with a 16-bit immediate shifted left by 16 bits.

XOR Immediate Shifted performs a bitwise XOR between the contents of GPR RS and a 16-bit unsigned immediate shifted left by 16 bits, storing the result in GPR RA. This is a Base category instruction that does not affect condition registers or status fields.

The xoris instruction is useful for performing bitwise operations with a large immediate value. Be cautious of overflow if the immediate value exceeds 16 bits, as only the lower 16 bits are considered. This instruction operates at user privilege level and does not generate exceptions under normal circumstances.