Summary: Loads halfwords without faulting.

Loads halfwords from memory into a scalable vector register without raising faults; elements that would fault are loaded as zero. Only elements where the predicate is true are accessed. This instruction is AArch64-only and requires SVE. No condition flags are set.

for i ← 0 to (VL/16 - 1) do if Pg[i] then if fault_would_occur then Zt[i*16+15:i*16] ← 0; else Zt[i*16+15:i*16] ← [Xn + i*2]; end if; end if; end for


Summary: Loads words without faulting.

Zt

Transfer scalable vector register (SVE load/store)

Xn

First source / base 64-bit integer register

Loads words from memory into a scalable vector register without raising faults; elements that would fault are loaded as zero. Only elements where the predicate is true are accessed. This instruction is AArch64-only and requires SVE. No condition flags are set.

for i ← 0 to (VL/32 - 1) do if Pg[i] then if fault_would_occur then Zt[i*32+31:i*32] ← 0; else Zt[i*32+31:i*32] ← [Xn + i*4]; end if; end if; end for


SVE Load Non-Fault Contiguous Doublewords

Summary: Loads doublewords without faulting.

Loads contiguous doublewords (64-bit elements) from memory into a scalable vector register without generating a fault if a load would be out-of-bounds or inaccessible. Only elements where the corresponding predicate bit in Pg is true are loaded; others are zeroed in the destination Zt. This instruction is AArch64-only, requires SVE support, and does not affect condition flags.

for i = 0 to VL/64-1
  if Pg[i] == 1 then
    Zt.D[i] ← [Xn + (i × 8)]
  else
    Zt.D[i] ← 0
  endif
endfor


Summary: Generates predicate for unsigned loop (while Xn < Xm).

Generates a predicate where each element is true if the corresponding loop counter (Xn + element_index) is less than Xm (unsigned comparison). The output predicate Pd has element width determined by <T> (byte, halfword, word, or doubleword). This is an AArch64-only SVE instruction; all condition flags are unaffected.

element_size ← size_in_bytes(<T>)
for i = 0 to VL/element_size-1
  if (Xn + i) < Xm then
    Pd[i] ← 1
  else
    Pd[i] ← 0
  endif
endfor


Summary: Generates predicate for unsigned loop (while Xn <= Xm).

Generates a predicate where each element is true if the corresponding loop counter (Xn + element_index) is less than or equal to Xm (unsigned comparison). The output predicate Pd has element width determined by <T>. This is an AArch64-only SVE instruction; all condition flags are unaffected.

element_size ← size_in_bytes(<T>)
for i = 0 to VL/element_size-1
  if (Xn + i) <= Xm then
    Pd[i] ← 1
  else
    Pd[i] ← 0
  endif
endfor


Summary: Generates predicate for unsigned loop (while Xn > Xm).

Generates a predicate where each element is true if the corresponding loop counter (Xn + element_index) is greater than Xm (unsigned comparison). The output predicate Pd has element width determined by <T>. This is an AArch64-only SVE instruction; all condition flags are unaffected.

element_size ← size_in_bytes(<T>)
for i = 0 to VL/element_size-1
  if (Xn + i) > Xm then
    Pd[i] ← 1
  else
    Pd[i] ← 0
  endif
endfor


Summary: Generates predicate for unsigned loop (while Xn >= Xm).

Generates a predicate where each element is true if the corresponding loop counter (Xn + element_index) is greater than or equal to Xm (unsigned comparison). The output predicate Pd has element width determined by <T>. This is an AArch64-only SVE instruction; all condition flags are unaffected.

element_size ← size_in_bytes(<T>)
for i = 0 to VL/element_size-1
  if (Xn + i) >= Xm then
    Pd[i] ← 1
  else
    Pd[i] ← 0
  endif
endfor


Summary: Counts the number of true elements in a predicate.

Counts the number of true bits in Pn.T (where the element size <T> determines the predicate width) that are also true in the governing predicate Pg, and writes the 64-bit count to the general-purpose register Xn. This is an AArch64-only SVE instruction; all condition flags are unaffected.

count ← 0
element_size ← size_in_bytes(<T>)
for i = 0 to VL/element_size-1
  if Pg[i] == 1 and Pn[i] == 1 then
    count ← count + 1
  endif
endfor
Xn ← count


Summary: Updates processor flags (NZCV) based on predicate state.

Tests the predicate Pn.B (byte-wide elements) under the control of governing predicate Pg and updates the condition flags (N, Z, C, V) to indicate the result. Sets Z=1 if all tested elements are false, C=1 if any tested element is true, N and V are set according to the logical AND and OR of tested bits. This is an AArch64-only SVE instruction.

result_any ← 0
result_all ← 1
for i = 0 to VL/8-1
  if Pg[i] == 1 then
    if Pn[i] == 1 then
      result_any ← 1
      result_all ← result_all AND 1
    else
      result_all ← 0
    endif
  endif
endfor
Z ← (result_any == 0)
C ← result_any
N ← result_all
V ← 0


Summary: Sets destination predicate to true only at the first active element.

Sets the destination predicate Pd.B such that only the first element (in vector order) where both Pg and Pn are true is set to true; all other elements are set to false. This is useful for scalar tail-processing in loops. This is an AArch64-only SVE instruction; all condition flags are unaffected.

for i = 0 to VL/8-1
  if Pg[i] == 1 and Pn[i] == 1 then
    Pd[i] ← 1
    break
  else
    Pd[i] ← 0
  endif
endfor
for j = i+1 to VL/8-1
  Pd[j] ← 0
endfor


Summary: Extracts element after the last active element.

Extracts the element immediately after the last active element (as determined by the predicate) from a SVE vector and writes it to a scalar register; if no active elements exist, the destination register is unchanged. This instruction operates only in AArch64 state and does not modify the condition flags.

activecount ← CountActiveLanes(Pg, esize)
if activecount == VL/esize then
  Rdn ← Zm[0]
else if activecount > 0 then
  Rdn ← Zm[activecount]
else
  Rdn ← Rdn


Summary: Extracts the last active element.

Extracts the last active element (as determined by the predicate) from a SVE vector and writes it to a scalar register; if no active elements exist, the destination register is unchanged. This instruction operates only in AArch64 state and does not modify the condition flags.

activecount ← CountActiveLanes(Pg, esize)
if activecount > 0 then
  Rdn ← Zm[activecount - 1]
else
  Rdn ← Rdn


Summary: Extracts element after last active (SIMD scalar destination).

Extracts the element immediately after the last active element (as determined by the predicate) from a SVE vector and writes it to a SIMD scalar register; if no active elements exist, the destination register is unchanged. This instruction operates only in AArch64 state and does not modify the condition flags.

activecount ← CountActiveLanes(Pg, esize)
if activecount == VL/esize then
  Vd ← Zn[0]
else if activecount > 0 then
  Vd ← Zn[activecount]
else
  Vd ← Vd


Summary: Extracts last active element (SIMD scalar destination).

Extracts the last active element (as determined by the predicate) from a SVE vector and writes it to a SIMD scalar register; if no active elements exist, the destination register is unchanged. This instruction operates only in AArch64 state and does not modify the condition flags.

activecount ← CountActiveLanes(Pg, esize)
if activecount > 0 then
  Vd ← Zn[activecount - 1]
else
  Vd ← Vd


Summary: Inserts scalar into bottom of vector, shifting other elements up.

Zdn

Combined destination/source scalable vector register (SVE)

Inserts a scalar register value into the bottom element of a SVE vector, shifting all other elements upward (toward higher element indices), with the top element discarded. This instruction operates only in AArch64 state and does not modify the condition flags.

elements ← VL / esize
for i = elements - 1 downto 1
  Zdn[i] ← Zdn[i-1]
Zdn[0] ← Rm


Summary: Extracts a vector from a pair (sliding window) using immediate byte index.

Extracts a contiguous sequence of bytes from the concatenation of two SVE vectors (the low vector followed by the high vector) starting at a byte offset, and places the result in the destination vector. This instruction operates only in AArch64 state and does not modify the condition flags.

offset ← imm
result ← Concatenate(Zdn, Zm)[offset:offset + (VL/8) - 1]
Zdn ← result


Summary: Reverses the order of elements in the vector.

Zd

Destination scalable vector register (SVE)

Zn

First source scalable vector register (SVE)

Reverses the order of elements within a SVE vector; the element at index 0 is moved to the last position, and the last element is moved to index 0. This instruction operates only in AArch64 state and does not modify the condition flags.

elements ← VL / esize
for i = 0 to elements - 1
  Zd[i] ← Zn[elements - 1 - i]


Summary: Reverses bytes within 16/32/64-bit elements.

Reverses the byte order within each element of a SVE vector under predicate control; for 16-bit elements 2 bytes are reversed, for 32-bit elements 4 bytes, and for 64-bit elements 8 bytes. This instruction operates only in AArch64 state and does not modify the condition flags.

elements ← VL / esize
for i = 0 to elements - 1
  if Pg[i] then
    Zd[i] ← ReverseBytes(Zn[i], esize)
  else
    Zd[i] ← Zd[i]


Summary: Reverses halfwords within 32/64-bit elements.

Reverses the byte order of halfwords (16-bit elements) within 32-bit or 64-bit SVE vector elements, operating under predicate control. No condition flags are affected. This instruction is AArch64-only and available with the SVE extension; it performs element-wise reversals where each 32-bit or 64-bit element has its constituent halfwords byte-reversed in place.

for i = 0 to VL/esize-1
  if Pg[i] then
    case esize of
      32: Zd[i+1:i] ← reverse_halfwords_in_32bit(Zn[i+1:i])
      64: Zd[i+1:i] ← reverse_halfwords_in_64bit(Zn[i+1:i])
  else
    Zd[i+1:i] ← Zd[i+1:i]


Summary: Reverses words within 64-bit elements.

Reverses the byte order of words (32-bit elements) within 64-bit SVE vector elements, operating under predicate control. No condition flags are affected. This instruction is AArch64-only and available with the SVE extension; it swaps the two 32-bit words in each 64-bit element.

for i = 0 to VL/64-1
  if Pg[i] then
    Zd[i+1:i] ← {Zn[i+31:i], Zn[i+63:i+32]}
  else
    Zd[i+1:i] ← Zd[i+1:i]


Summary: Reverses bits in each element.

Reverses the bit order within each SVE vector element, operating under predicate control. No condition flags are affected. This instruction is AArch64-only and available with the SVE extension; each element's bits are reversed such that bit 0 becomes the MSB and the MSB becomes bit 0.

for i = 0 to VL/esize-1
  if Pg[i] then
    Zd[i+1:i] ← reverse_bits(Zn[i+1:i], esize)
  else
    Zd[i+1:i] ← Zd[i+1:i]


Summary: Unpacks and sign-extends lower half of vector elements.

Unpacks the lower half of each source element and sign-extends it to the destination element size in SVE vectors. No condition flags are affected. This instruction is AArch64-only and available with the SVE extension; destination elements are twice the width of source elements, with sign extension applied to the lower elements.

for i = 0 to VL/esize_dst-1
  Zd[i+1:i] ← sign_extend(Zn[i+esize_src/2-1:i], esize_dst)


Summary: Unpacks and sign-extends upper half of vector elements.

Unpacks the upper half of each source element and sign-extends it to the destination element size in SVE vectors. No condition flags are affected. This instruction is AArch64-only and available with the SVE extension; destination elements are twice the width of source elements, with sign extension applied to the upper elements.

for i = 0 to VL/esize_dst-1
  Zd[i+1:i] ← sign_extend(Zn[i+esize_src-1:i+esize_src/2], esize_dst)


Summary: Unpacks and zero-extends lower half of vector elements.

Unpacks the lower half of each source element and zero-extends it to the destination element size in SVE vectors. No condition flags are affected. This instruction is AArch64-only and available with the SVE extension; destination elements are twice the width of source elements, with zero extension applied to the lower elements.

for i = 0 to VL/esize_dst-1
  Zd[i+1:i] ← zero_extend(Zn[i+esize_src/2-1:i], esize_dst)


Summary: Unpacks and zero-extends upper half of vector elements.

Unpacks the upper half of each source element and zero-extends it to the destination element size in SVE vectors. No condition flags are affected. This instruction is AArch64-only and available with the SVE extension; destination elements are twice the width of source elements, with zero extension applied to the upper elements.

for i = 0 to VL/esize_dst-1
  Zd[i+1:i] ← zero_extend(Zn[i+esize_src-1:i+esize_src/2], esize_dst)


Summary: Computes dot product of signed integers (AI Acceleration).

Zm

Second source scalable vector register (SVE)

Computes the dot product of signed integer vectors and accumulates the result into the destination register, supporting AI acceleration. No condition flags are affected. This instruction is AArch64-only and available with the SVE extension; the destination is widened relative to the sources, and the accumulation is added to existing values in Zda.

for i = 0 to VL/esize_dst-1
  product ← 0
  for j = 0 to (esize_dst / esize_src) - 1
    product ← product + sign_extend(Zn[i*esize_dst + (j+1)*esize_src - 1 : i*esize_dst + j*esize_src], esize_dst) * sign_extend(Zm[i*esize_dst + (j+1)*esize_src - 1 : i*esize_dst + j*esize_src], esize_dst)
  Zda[i+1:i] ← Zda[i+1:i] + product


Summary: Computes dot product of unsigned integers.

SVE unsigned dot product: accumulates the sum of element-wise products of unsigned integers from Zn and Zm into Zda. The element size of Zn and Zm (Tb) is half that of Zda (T), allowing 2, 4, or 8 products to be summed per destination element depending on the vector length. No condition flags are affected. This is an AArch64-only instruction requiring SVE support.

for e = 0 to VL/getElementSize(T)-1
  element_pairs = getElements(Zn[e], Tb) × getElements(Zm[e], Tb)
  Zda[e] ← Zda[e] + sum(element_pairs)
end for


Summary: Determines maximum signed value per element.

SVE signed maximum: computes the element-wise maximum of two signed integer vectors (Zdn and Zm), writing results to Zdn under predicate mask control (Pg). Only elements where the predicate is active are updated; inactive elements retain their original values in Zdn. No condition flags are affected. This is an AArch64-only instruction requiring SVE support.

for e = 0 to VL/getElementSize(T)-1
  if Pg[e] == 1 then
    Zdn[e] ← max_signed(Zdn[e], Zm[e])
  end if
end for


Summary: Determines minimum signed value per element.

SVE signed minimum: computes the element-wise minimum of two signed integer vectors (Zdn and Zm), writing results to Zdn under predicate mask control (Pg). Only elements where the predicate is active are updated; inactive elements retain their original values in Zdn. No condition flags are affected. This is an AArch64-only instruction requiring SVE support.

for e = 0 to VL/getElementSize(T)-1
  if Pg[e] == 1 then
    Zdn[e] ← min_signed(Zdn[e], Zm[e])
  end if
end for


Summary: Determines maximum unsigned value per element.

SVE unsigned maximum: computes the element-wise maximum of two unsigned integer vectors (Zdn and Zm), writing results to Zdn under predicate mask control (Pg). Only elements where the predicate is active are updated; inactive elements retain their original values in Zdn. No condition flags are affected. This is an AArch64-only instruction requiring SVE support.

for e = 0 to VL/getElementSize(T)-1
  if Pg[e] == 1 then
    Zdn[e] ← max_unsigned(Zdn[e], Zm[e])
  end if
end for


Summary: Determines minimum unsigned value per element.

SVE unsigned minimum: computes the element-wise minimum of two unsigned integer vectors (Zdn and Zm), writing results to Zdn under predicate mask control (Pg). Only elements where the predicate is active are updated; inactive elements retain their original values in Zdn. No condition flags are affected. This is an AArch64-only instruction requiring SVE support.

for e = 0 to VL/getElementSize(T)-1
  if Pg[e] == 1 then
    Zdn[e] ← min_unsigned(Zdn[e], Zm[e])
  end if
end for


Summary: Calculates absolute value of integers.

SVE absolute value: computes the element-wise absolute value of signed integers in Zdn, writing results back to Zdn under predicate mask control (Pg). Only elements where the predicate is active are updated; inactive elements retain their original values. No condition flags are affected. This is an AArch64-only instruction requiring SVE support.

for e = 0 to VL/getElementSize(T)-1
  if Pg[e] == 1 then
    Zdn[e] ← abs_signed(Zdn[e])
  end if
end for


Summary: Negates integers.

SVE negate: computes the element-wise negation (two's complement) of integers in Zdn, writing results back to Zdn under predicate mask control (Pg). Only elements where the predicate is active are updated; inactive elements retain their original values. No condition flags are affected. This is an AArch64-only instruction requiring SVE support.

for e = 0 to VL/getElementSize(T)-1
  if Pg[e] == 1 then
    Zdn[e] ← -Zdn[e]
  end if
end for


Summary: Inverts bits.

SVE bitwise NOT: inverts all bits in each element of Zdn under predicate mask control (Pg), writing the results back to Zdn. Only elements where the predicate is active are updated; inactive elements retain their original values. No condition flags are affected. This is an AArch64-only instruction requiring SVE support.

for e = 0 to VL/getElementSize(T)-1
  if Pg[e] == 1 then
    Zdn[e] ← ~Zdn[e]
  end if
end for


Summary: Divides signed integers.

SVE signed integer divide: divides each active element of Zdn (dividend) by the corresponding element of Zm (divisor), storing the quotient back in Zdn. Elements where the predicate is false are left unchanged. No condition flags are affected. This is an SVE-only instruction and does not raise exceptions on division by zero; instead, undefined results are written to inactive elements.

for i = 0 to VL-1
  if Pg[i] == '1' then
    Zdn[i] ← Zdn[i] / Zm[i]
  // else Zdn[i] unchanged


Summary: Divides unsigned integers.

SVE unsigned integer divide: divides each active element of Zdn (dividend) by the corresponding element of Zm (divisor) as unsigned values, storing the quotient back in Zdn. Elements where the predicate is false are left unchanged. No condition flags are affected. This is an SVE-only instruction and does not raise exceptions on division by zero.

for i = 0 to VL-1
  if Pg[i] == '1' then
    Zdn[i] ← UnsignedDivide(Zdn[i], Zm[i])
  // else Zdn[i] unchanged


Summary: Calculates square root of floats.

SVE floating-point square root: computes the square root of each active element in Zdn and stores the result back in Zdn. Elements where the predicate is false are left unchanged. Floating-point exception flags (IOC, DZC, OFC, UFC, IXC) are updated according to the IEEE 754 standard; no integer condition flags are affected. This is an SVE-only instruction.

for i = 0 to VL-1
  if Pg[i] == '1' then
    Zdn[i] ← FPSquareRoot(Zdn[i])
  // else Zdn[i] unchanged
// FP exception flags updated per IEEE 754


Summary: Calculates absolute value of floats.

SVE floating-point absolute value: computes the absolute value of each active element in Zdn and stores the result back in Zdn, clearing the sign bit. Elements where the predicate is false are left unchanged. No condition flags or floating-point exceptions are affected. This is an SVE-only instruction.

for i = 0 to VL-1
  if Pg[i] == '1' then
    Zdn[i] ← FPAbs(Zdn[i])
  // else Zdn[i] unchanged


Summary: Negates floats.

SVE floating-point negate: flips the sign bit of each active element in Zdn and stores the result back in Zdn. Elements where the predicate is false are left unchanged. No condition flags or floating-point exceptions are affected. This is an SVE-only instruction.

for i = 0 to VL-1
  if Pg[i] == '1' then
    Zdn[i] ← FPNegate(Zdn[i])
  // else Zdn[i] unchanged


Summary: Performs complex addition with rotation.

SVE floating-point complex add: performs a predicate-masked complex addition of Zdn and Zm with a 90° or 270° rotation applied to Zm before addition. For rot=90, computes Zdn + i*Zm; for rot=270, computes Zdn - i*Zm. Elements where the predicate is false are left unchanged. Floating-point exceptions are signaled per IEEE 754. This is an SVE-only instruction.

FCADD z0.s.T, p0/m/M, z0.s.T, z2.s.T, #rot

for i = 0 to VL-1
  if Pg[i] == '1' then
    rotated ← RotateComplex(Zm[i], rot)
    Zdn[i] ← FPAdd(Zdn[i], rotated)
  // else Zdn[i] unchanged


Summary: Performs complex multiply-accumulate.

Zda

Accumulator scalable vector register (SVE)

SVE floating-point complex multiply-add: performs a predicate-masked complex multiply-accumulate operation where Zn and Zm are multiplied with rotation, and the result is added to Zda. For each rotation value (0°, 90°, 180°, 270°), a different complex multiplication result is accumulated. Elements where the predicate is false leave Zda unchanged. Floating-point exceptions are signaled per IEEE 754. This is an SVE-only instruction.

FCMLA z0.s.T, p0/m/M, z1.s.T, z2.s.T, #rot

for i = 0 to VL-1
  if Pg[i] == '1' then
    product ← FPComplexMultiply(Zn[i], Zm[i], rot)
    Zda[i] ← FPAdd(Zda[i], product)
  // else Zda[i] unchanged


Summary: Sums all active signed elements into a scalar result.

SVE signed integer add reduction: sums all active signed elements of the SVE vector Zn across the vector length and accumulates the result into the scalar destination Vd, sign-extending to the element width. Only elements where the corresponding predicate bit is set participate in the reduction. No condition flags are affected. This is an SVE-only instruction.

result ← 0
for i = 0 to VL-1
  if Pg[i] == '1' then
    result ← result + SignExtend(Zn[i])
Vd ← result


Summary: Finds max signed element in vector.

SVE signed maximum reduction: finds the maximum signed element in vector Zn according to predicate mask Pg, and stores the result as a scalar in Vd. The operation reads all active elements from Zn, compares them as signed integers (element size determined by sz), and reduces to a single scalar value. No NZCV flags are affected by this instruction.

bits(esize) result = MIN_INT(esize);
for i = 0 to VL/esize - 1
  if Pg[i] == '1' then
    element = Zn[i*esize +: esize];
    if element > result (signed) then result = element;
Vd[0 +: esize] ← result;


Summary: Finds max unsigned element in vector.

SVE unsigned maximum reduction: finds the maximum unsigned element in vector Zn according to predicate mask Pg, and stores the result as a scalar in Vd. The operation compares all active elements as unsigned integers (element size determined by sz) and reduces to a single scalar. No NZCV flags are affected by this instruction.

bits(esize) result = 0;
for i = 0 to VL/esize - 1
  if Pg[i] == '1' then
    element = Zn[i*esize +: esize];
    if element > result (unsigned) then result = element;
Vd[0 +: esize] ← result;


Summary: Finds min signed element in vector.

SVE signed minimum reduction: finds the minimum signed element in vector Zn according to predicate mask Pg, and stores the result as a scalar in Vd. The operation reads all active elements from Zn, compares them as signed integers (element size determined by sz), and reduces to a single scalar value. No NZCV flags are affected by this instruction.

bits(esize) result = MAX_INT(esize);
for i = 0 to VL/esize - 1
  if Pg[i] == '1' then
    element = Zn[i*esize +: esize];
    if element < result (signed) then result = element;
Vd[0 +: esize] ← result;


Summary: Finds min unsigned element in vector.

SVE unsigned minimum reduction: finds the minimum unsigned element in vector Zn according to predicate mask Pg, and stores the result as a scalar in Vd. The operation compares all active elements as unsigned integers (element size determined by sz) and reduces to a single scalar. No NZCV flags are affected by this instruction.

bits(esize) result = ALL_ONES(esize);
for i = 0 to VL/esize - 1
  if Pg[i] == '1' then
    element = Zn[i*esize +: esize];
    if element < result (unsigned) then result = element;
Vd[0 +: esize] ← result;


Summary: Finds max float in vector.

SVE floating-point maximum reduction: finds the maximum floating-point element in vector Zn according to predicate mask Pg, and stores the result as a scalar in Vd. The operation compares all active elements as IEEE 754 floats (precision determined by sz: 0=half, 1=single or double) using quiet comparison semantics, and reduces to a single scalar. No NZCV flags are affected; SNaNs propagate as the maximum.

bits(esize) result = NegInfinity(esize);
for i = 0 to VL/esize - 1
  if Pg[i] == '1' then
    element = Zn[i*esize +: esize];
    if element > result (FP) || IsNaN(result) then result = element;
Vd[0 +: esize] ← result;


Summary: Finds min float in vector.

SVE floating-point minimum reduction: finds the minimum floating-point element in vector Zn according to predicate mask Pg, and stores the result as a scalar in Vd. The operation compares all active elements as IEEE 754 floats (precision determined by sz: 0=half, 1=single or double) using quiet comparison semantics, and reduces to a single scalar. No NZCV flags are affected; SNaNs propagate as the minimum.

bits(esize) result = PosInfinity(esize);
for i = 0 to VL/esize - 1
  if Pg[i] == '1' then
    element = Zn[i*esize +: esize];
    if element < result (FP) || IsNaN(result) then result = element;
Vd[0 +: esize] ← result;


Summary: ANDs all active elements into a scalar.

SVE bitwise AND reduction: performs a bitwise AND of all active elements in vector Zn according to predicate mask Pg, and stores the result as a scalar in Vd. The operation reduces a vector of integers to a single scalar by bitwise AND across all selected elements (element size determined by sz). No NZCV flags are affected by this instruction.

bits(esize) result = ALL_ONES(esize);
for i = 0 to VL/esize - 1
  if Pg[i] == '1' then
    element = Zn[i*esize +: esize];
    result = result AND element;
Vd[0 +: esize] ← result;


Summary: ORs all active elements into a scalar.

SVE bitwise OR reduction: performs a bitwise OR of all active elements in vector Zn according to predicate mask Pg, and stores the result as a scalar in Vd. The operation reduces a vector of integers to a single scalar by bitwise OR across all selected elements (element size determined by sz). No NZCV flags are affected by this instruction.

bits(esize) result = 0;
for i = 0 to VL/esize - 1
  if Pg[i] == '1' then
    element = Zn[i*esize +: esize];
    result = result OR element;
Vd[0 +: esize] ← result;


Summary: XORs all active elements into a scalar.

SVE bitwise XOR reduction that combines all active predicated elements of a scalable vector into a scalar result. The operation iteratively XORs each active element into the destination scalar register. No condition flags are affected by this instruction. This is an AArch64-only SVE instruction.

bits(smax(8*datasize,32)) result = Vd<smax(8*datasize,32)-1:0>;
for i = 0 to (VL/esize)-1
    if Pg[i]
        result = result XOR Zn[i*esize+esize-1:i*esize]
Vd = result<smax(8*datasize,32)-1:0>;


SVE Signed Integer Convert to Floating-Point

Summary: Converts signed integers to floats.

SVE instruction that converts signed integer elements in a scalable vector to floating-point representation. Only active predicated elements are converted; inactive elements are zeroed. The instruction operates under predicate control with zeroing (/Z) semantics. This is an AArch64-only SVE instruction with no NZCV flag effects.

for i = 0 to (VL/esize)-1
    if Pg[i]
        Zdn[i*esize+esize-1:i*esize] = ConvertSignedIntegerToFP(Zdn[i*esize+esize-1:i*esize])
    else
        Zdn[i*esize+esize-1:i*esize] = 0


SVE Unsigned Integer Convert to Floating-Point

Summary: Converts unsigned integers to floats.

SVE instruction that converts unsigned integer elements in a scalable vector to floating-point representation. Only active predicated elements are converted; inactive elements are zeroed. The instruction operates under predicate control with zeroing (/Z) semantics. This is an AArch64-only SVE instruction with no NZCV flag effects.

for i = 0 to (VL/esize)-1
    if Pg[i]
        Zdn[i*esize+esize-1:i*esize] = ConvertUnsignedIntegerToFP(Zdn[i*esize+esize-1:i*esize])
    else
        Zdn[i*esize+esize-1:i*esize] = 0


SVE Floating-Point Convert to Signed Integer

Summary: Converts floats to signed integers (Truncate).

SVE instruction that converts floating-point elements in a scalable vector to signed integer representation by truncation toward zero. Only active predicated elements are converted; inactive elements are zeroed. The instruction operates under predicate control with zeroing (/Z) semantics. This is an AArch64-only SVE instruction with no NZCV flag effects.

for i = 0 to (VL/esize)-1
    if Pg[i]
        Zdn[i*esize+esize-1:i*esize] = ConvertFPToSignedIntegerTruncate(Zdn[i*esize+esize-1:i*esize])
    else
        Zdn[i*esize+esize-1:i*esize] = 0


SVE Floating-Point Convert to Unsigned Integer

Summary: Converts floats to unsigned integers (Truncate).

SVE instruction that converts floating-point elements in a scalable vector to unsigned integer representation by truncation toward zero. Only active predicated elements are converted; inactive elements are zeroed. The instruction operates under predicate control with zeroing (/Z) semantics. This is an AArch64-only SVE instruction with no NZCV flag effects.

for i = 0 to (VL/esize)-1
    if Pg[i]
        Zdn[i*esize+esize-1:i*esize] = ConvertFPToUnsignedIntegerTruncate(Zdn[i*esize+esize-1:i*esize])
    else
        Zdn[i*esize+esize-1:i*esize] = 0


Summary: Multiplies bottom 16 bits of Rn and Rm.

Multiplies the bottom 16 bits (bits [15:0]) of Rn by the bottom 16 bits of Rm as signed integers, producing a 32-bit signed result in Rd. This is an A32 DSP instruction that does not update condition flags.

if ConditionPassed() then
  operand1 = SignExtend(Rn[15:0], 32)
  operand2 = SignExtend(Rm[15:0], 32)
  Rd = operand1 * operand2


Summary: Multiplies bottom 16 bits of Rn and top 16 bits of Rm.

A32 DSP multiply instruction that multiplies the bottom 16 bits (signed) of Rn by the top 16 bits (signed) of Rm and stores the 32-bit result in Rd. The instruction is conditional and does not affect the NZCV condition flags. Q flag behavior is not documented for this instruction in standard architectures.

operand1 = SignExtend(Rn<15:0>, 32)
operand2 = SignExtend(Rm<31:16>, 32)
Rd = (operand1 * operand2)<31:0>


Summary: Multiplies top 16 bits of Rn and bottom 16 bits of Rm.

A32 DSP multiply instruction that multiplies the top 16 bits (signed) of Rn by the bottom 16 bits (signed) of Rm and stores the 32-bit result in Rd. The instruction is conditional and does not affect the NZCV condition flags. Q flag behavior is not documented for this instruction in standard architectures.

operand1 = SignExtend(Rn<31:16>, 32)
operand2 = SignExtend(Rm<15:0>, 32)
Rd = (operand1 * operand2)<31:0>


Summary: Multiplies top 16 bits of Rn and top 16 bits of Rm.

A32 DSP multiply instruction that multiplies the top 16 bits (signed) of Rn by the top 16 bits (signed) of Rm and stores the 32-bit result in Rd. The instruction is conditional and does not affect the NZCV condition flags. Q flag behavior is not documented for this instruction in standard architectures.

operand1 = SignExtend(Rn<31:16>, 32)
operand2 = SignExtend(Rm<31:16>, 32)
Rd = (operand1 * operand2)<31:0>


Signed Multiply Accumulate (Bottom x Bottom)

Summary: Accumulates (Rn.B * Rm.B) into Ra.

Rn

First source / base general-purpose register

Rm

Second source / offset general-purpose register

Signed multiply-accumulate of the bottom 16-bit halfwords of Rn and Rm, with the 32-bit product added to Ra and stored in Rd. This is an A32 DSP instruction that operates on 16-bit subregisters. The Q flag may be set if overflow occurs during accumulation, but N, Z, C, V flags are unchanged.

temp ← SignExtend(Rn[15:0], 32) * SignExtend(Rm[15:0], 32);
result ← temp + Ra;
if OverflowFrom_Addition(temp, Ra) then Q ← 1; end if;
Rd ← result;


Signed Multiply Accumulate (Bottom x Top)

Summary: Accumulates (Rn.B * Rm.T) into Ra.

Signed multiply-accumulate of the bottom 16-bit halfword of Rn and the top 16-bit halfword of Rm, with the 32-bit product added to Ra and stored in Rd. This is an A32 DSP instruction that operates on 16-bit subregisters. The Q flag may be set if overflow occurs during accumulation, but N, Z, C, V flags are unchanged.

temp ← SignExtend(Rn[15:0], 32) * SignExtend(Rm[31:16], 32);
result ← temp + Ra;
if OverflowFrom_Addition(temp, Ra) then Q ← 1; end if;
Rd ← result;


Signed Multiply Accumulate (Top x Bottom)

Summary: Accumulates (Rn.T * Rm.B) into Ra.

Signed multiply-accumulate of the top 16-bit halfword of Rn and the bottom 16-bit halfword of Rm, with the 32-bit product added to Ra and stored in Rd. This is an A32 DSP instruction that operates on 16-bit subregisters. The Q flag may be set if overflow occurs during accumulation, but N, Z, C, V flags are unchanged.

temp ← SignExtend(Rn[31:16], 32) * SignExtend(Rm[15:0], 32);
result ← temp + Ra;
if OverflowFrom_Addition(temp, Ra) then Q ← 1; end if;
Rd ← result;


Summary: Accumulates (Rn.T * Rm.T) into Ra.

Signed multiply-accumulate of the top 16-bit halfwords of Rn and Rm, with the 32-bit product added to Ra and stored in Rd. This is an A32 DSP instruction that operates on 16-bit subregisters. The Q flag may be set if overflow occurs during accumulation, but N, Z, C, V flags are unchanged.

temp ← SignExtend(Rn[31:16], 32) * SignExtend(Rm[31:16], 32);
result ← temp + Ra;
if OverflowFrom_Addition(temp, Ra) then Q ← 1; end if;
Rd ← result;


Summary: Multiplies 32-bit Rn by bottom 16-bits of Rm, takes top 32-bits of result.

Signed multiply of the 32-bit Rn by the bottom 16-bit halfword of Rm, extracting the top 32 bits of the 48-bit product into Rd. This is an A32 DSP instruction that produces no flag changes; overflow is not indicated.

product ← SignExtend(Rn[31:0], 48) * SignExtend(Rm[15:0], 48);
Rd ← product[47:16];


Summary: Multiplies 32-bit Rn by top 16-bits of Rm, takes top 32-bits of result.

Signed multiply of the 32-bit Rn by the top 16-bit halfword of Rm, extracting the top 32 bits of the 48-bit product into Rd. This is an A32 DSP instruction that produces no flag changes; overflow is not indicated.

product ← SignExtend(Rn[31:0], 48) * SignExtend(Rm[31:16], 48);
Rd ← product[47:16];


Signed Multiply Accumulate (Word x Bottom)

Summary: Performs SMULWB and adds to accumulator.

Signed multiply-accumulate combining SMULWB with addition of Ra; multiplies 32-bit Rn by the bottom 16-bit halfword of Rm, takes the top 32 bits of the product, adds Ra, and stores in Rd. This is an A32 DSP instruction. The Q flag may be set if overflow occurs during accumulation, but N, Z, C, V flags are unchanged.

product ← SignExtend(Rn[31:0], 48) * SignExtend(Rm[15:0], 48);
temp ← product[47:16];
result ← temp + Ra;
if OverflowFrom_Addition(temp, Ra) then Q ← 1; end if;
Rd ← result;


Summary: Performs SMULWT and adds to accumulator.

Signed multiply-accumulate combining SMULWT with addition of Ra; multiplies 32-bit Rn by the top 16-bit halfword of Rm, takes the top 32 bits of the product, adds Ra, and stores in Rd. This is an A32 DSP instruction. The Q flag may be set if overflow occurs during accumulation, but N, Z, C, V flags are unchanged.

product ← SignExtend(Rn[31:0], 48) * SignExtend(Rm[31:16], 48);
temp ← product[47:16];
result ← temp + Ra;
if OverflowFrom_Addition(temp, Ra) then Q ← 1; end if;
Rd ← result;


Signed Multiply Accumulate Long (Bottom x Bottom)

Summary: Accumulates (Rn.B * Rm.B) into 64-bit pair.

Signed Multiply Accumulate Long (Bottom × Bottom) multiplies the bottom 16 bits of Rn by the bottom 16 bits of Rm, treating both as signed, and accumulates the 32-bit result into the 64-bit value formed by RdHi:RdLo. This A32 DSP extension instruction does not update condition flags and is not available in AArch64.

operand1 ← SignExtend(Rn[15:0], 32);
operand2 ← SignExtend(Rm[15:0], 32);
result ← operand1 * operand2;
RdHi:RdLo ← RdHi:RdLo + result;


Signed Multiply Accumulate Long (Bottom x Top)

Summary: Accumulates (Rn.B * Rm.T) into 64-bit pair.

Signed Multiply Accumulate Long (Bottom × Top) multiplies the bottom 16 bits of Rn by the top 16 bits of Rm, treating both as signed, and accumulates the 32-bit result into the 64-bit value formed by RdHi:RdLo. This A32 DSP extension instruction does not update condition flags and is not available in AArch64.

operand1 ← SignExtend(Rn[15:0], 32);
operand2 ← SignExtend(Rm[31:16], 32);
result ← operand1 * operand2;
RdHi:RdLo ← RdHi:RdLo + result;


Signed Multiply Accumulate Long (Top x Bottom)

Summary: Accumulates (Rn.T * Rm.B) into 64-bit pair.

Signed Multiply Accumulate Long (Top × Bottom) multiplies the top 16 bits of Rn by the bottom 16 bits of Rm, treating both as signed, and accumulates the 32-bit result into the 64-bit value formed by RdHi:RdLo. This A32 DSP extension instruction does not update condition flags and is not available in AArch64.

operand1 ← SignExtend(Rn[31:16], 32);
operand2 ← SignExtend(Rm[15:0], 32);
result ← operand1 * operand2;
RdHi:RdLo ← RdHi:RdLo + result;


Signed Multiply Accumulate Long (Top x Top)

Summary: Accumulates (Rn.T * Rm.T) into 64-bit pair.

Signed Multiply Accumulate Long (Top × Top) multiplies the top 16 bits of Rn by the top 16 bits of Rm, treating both as signed, and accumulates the 32-bit result into the 64-bit value formed by RdHi:RdLo. This A32 DSP extension instruction does not update condition flags and is not available in AArch64.

operand1 ← SignExtend(Rn[31:16], 32);
operand2 ← SignExtend(Rm[31:16], 32);
result ← operand1 * operand2;
RdHi:RdLo ← RdHi:RdLo + result;


Summary: Multiplies two 32-bit values and adds to 40-bit internal acc (XScale Legacy).

Multiply with Internal Accumulate multiplies two 32-bit values (Rn and Rm) and adds the 64-bit result to a 40-bit internal accumulator indexed by Acc. This XScale legacy A32 instruction is encoded as a coprocessor operation; condition flags are not updated, and this instruction is deprecated in modern ARM implementations.

operand1 ← SignExtend(Rn, 64);
operand2 ← SignExtend(Rm, 64);
product ← operand1 * operand2;
internalAccumulator[Acc] ← internalAccumulator[Acc] + product;


Summary: SIMD multiply of packed halfwords to internal acc (XScale Legacy).

Multiply with Internal Accumulate Packed Halfwords performs SIMD multiplication of two packed 16-bit signed halfwords from Rn and Rm, accumulating each product into corresponding 40-bit internal accumulators. This XScale legacy A32 instruction is encoded as a coprocessor operation; condition flags are not updated, and this instruction is deprecated in modern ARM implementations.

operand1_low ← SignExtend(Rn[15:0], 32);
operand1_high ← SignExtend(Rn[31:16], 32);
operand2_low ← SignExtend(Rm[15:0], 32);
operand2_high ← SignExtend(Rm[31:16], 32);
product_low ← operand1_low * operand2_low;
product_high ← operand1_high * operand2_high;
internalAccumulator[Acc] ← internalAccumulator[Acc] + product_low;
internalAccumulator[Acc+1] ← internalAccumulator[Acc+1] + product_high;


Summary: SHA256 hash update (part 1).

SHA256 Hash Part 1 performs the first half of a SHA256 hash update operation on 128-bit NEON registers, processing the W array intermediate values. Qd receives updated hash state W[t] and W[t+1]; Qn provides the previous hash state; Qm provides the input data block words. This A32 Crypto extension instruction does not update condition flags and requires NEON support.

hash_state ← Qd;
w_data ← Qn;
data_words ← Qm;
temp ← SHA256_CH(hash_state.word[1], hash_state.word[2], hash_state.word[3]);
temp ← temp + SHA256_SUM1(hash_state.word[1]);
temp ← temp + data_words;
Qd.word[0] ← Qd.word[0] + temp;
Qd.word[1] ← hash_state.word[0];


Summary: SHA256 hash update (part 2).

SHA256 Hash Part 2 performs the second half of a SHA256 hash update operation on 128-bit NEON registers, processing the W array and final hash update. Qd receives the final hash state; Qn provides the hash value from the previous SHA256H instruction; Qm provides the input data block words. This A32 Crypto extension instruction does not update condition flags and requires NEON support.

hash_state ← Qd;
w_data ← Qn;
data_words ← Qm;
temp ← SHA256_CH(hash_state.word[0], hash_state.word[1], hash_state.word[2]);
temp ← temp + SHA256_SUM1(hash_state.word[0]);
temp ← temp + data_words;
Qd.word[1] ← Qd.word[1] + temp;
Qd.word[0] ← hash_state.word[3];


Summary: SHA256 schedule update instruction 0.

SHA256 Schedule Update 0 performs the first part of SHA256 message schedule expansion on four 32-bit words held in a 128-bit SIMD register. It processes the sigma_0 function as part of the SHA256 cryptographic algorithm. No condition flags are modified. This instruction requires the ARM Cryptography Extensions and executes only in A32 (ARM) state.

W[t] ← (W[t] >>> 7) XOR (W[t] >>> 18) XOR (W[t] >> 3); Qd ← result of applying this transformation to each 32-bit element of Qm


Summary: SHA256 schedule update instruction 1.

SHA256 Schedule Update 1 performs the second part of SHA256 message schedule expansion, combining three 128-bit registers to compute new message schedule words. It implements the full sigma_0(W[t-15]) + W[t-7] + sigma_1(W[t-2]) + W[t-16] operation. No condition flags are modified. This instruction requires the ARM Cryptography Extensions and executes only in A32 (ARM) state.

Qd ← Qd + (Qn >>> 17) XOR (Qn >>> 19) XOR (Qn >> 10) + (Qm <<< 25) XOR (Qm <<< 14) XOR (Qm >> 6); (applied element-wise to 32-bit values)


Summary: Signed Dot Product (vector by vector).

Signed Dot Product computes the dot product of four signed 8-bit integer elements from Qn and Qm, accumulating the result into the corresponding 32-bit element of Qd. Four separate dot products are computed in parallel across the 128-bit vectors. No condition flags are modified. This instruction requires the NEON Dot Product extension and executes in A32 (ARM) state.


Summary: Unsigned Dot Product (vector by vector).

Unsigned Dot Product computes the dot product of four unsigned 8-bit integer elements from Qn and Qm, accumulating the result into the corresponding 32-bit element of Qd. Four separate dot products are computed in parallel across the 128-bit vectors. No condition flags are modified. This instruction requires the NEON Dot Product extension and executes in A32 (ARM) state.


Summary: Matrix multiply-accumulate (BFloat16/Int8).

Vector Matrix Multiply-Accumulate performs a 4×4 matrix multiply-accumulate operation on either 8-bit integers or BFloat16 values, with results accumulated into Qd. When sz=0, operates on signed/unsigned 8-bit elements; when sz=1, operates on BFloat16 elements. No condition flags are modified. This instruction requires the NEON Matrix Multiply extension and executes in A32 (ARM) state.

if sz == 0:
  Qd ← Qd + MatMul_Int8(Qn, Qm)  (4x4 matrix multiply of int8 elements)
else:
  Qd ← Qd + MatMul_BF16(Qn, Qm) (4x4 matrix multiply of bfloat16 elements)


Summary: Dot product of unsigned and signed integers.

Unsigned-Signed Dot Product computes the dot product of unsigned 8-bit integers from Qn and signed 8-bit integers from Qm, accumulating into the corresponding 32-bit element of Qd. Four separate dot products are computed in parallel. No condition flags are modified. This instruction requires the NEON Dot Product extension and executes in A32 (ARM) state.


Summary: Sign-extends byte to word (Thumb).

Sign-extends an 8-bit byte value to a 32-bit word in the T32 (Thumb) instruction set. The least-significant byte of Rm is sign-extended and written to Rd. No condition flags are affected.


Summary: Sign-extends halfword to word (Thumb).

Sign-extends a 16-bit halfword value to a 32-bit word in the T32 (Thumb) instruction set. The least-significant halfword of Rm is sign-extended and written to Rd. No condition flags are affected.


Summary: Zero-extends byte to word (Thumb).

Zero-extends an 8-bit byte value to a 32-bit word in the T32 (Thumb) instruction set. The least-significant byte of Rm is zero-extended and written to Rd. No condition flags are affected.


Summary: Zero-extends halfword to word (Thumb).

Zero-extends a 16-bit halfword value to a 32-bit word in the T32 (Thumb) instruction set. The least-significant halfword of Rm is zero-extended and written to Rd. No condition flags are affected.


Summary: Endian swap (Thumb).

Reverses the byte order of a 32-bit value in a general-purpose register. The four bytes of the source register are swapped to convert between big-endian and little-endian representations. This instruction does not affect the condition flags. Execution is restricted to T32 (Thumb) instruction set.


Summary: Reverse bytes in halfwords (Thumb).

Reverses the byte order within each 16-bit halfword of a 32-bit register independently. Bytes [7:0] and [15:8] are swapped, and bytes [23:16] and [31:24] are swapped. This instruction does not affect the condition flags. Execution is restricted to T32 (Thumb) instruction set.


Summary: Reverse bytes in low halfword, sign extend (Thumb).

Reverse Signed Halfword reverses the byte order of the low 16 bits of Rm, then sign-extends the result to 32 bits and writes it to Rd. This is commonly used to perform endian conversion on signed 16-bit values. No condition flags are modified. This instruction executes only in T32 (Thumb) state.

halfword ← Rm[15:0];
reversed ← (halfword[7:0] << 8) | halfword[15:8];
Rd ← SignExtend(reversed, 16)


Summary: Calculates the absolute value of a float.

Hd|Sd|Dd

Destination SIMD&FP register (half, single or double-precision)

Hn|Sn|Dn

First source SIMD&FP register (half, single or double-precision)

Computes the absolute value of a scalar floating-point operand, clearing the sign bit while preserving all other bits. Floating-point exception conditions (invalid operation, etc.) are not generated. The instruction operates on Half-precision (16-bit), Single-precision (32-bit), or Double-precision (64-bit) formats, determined by the type field. This is an AArch64-only instruction.

Rd ← abs(Rn)
if (type == 00) then Rd is H-register (16-bit)
else if (type == 01) then Rd is S-register (32-bit)
else if (type == 10) then Rd is D-register (64-bit)


Summary: Adds two floating-point values.

Hm|Sm|Dm

Second source SIMD&FP register (half, single or double-precision)

Adds two scalar floating-point operands and writes the result to the destination register. The operation respects IEEE 754 rounding modes and may generate floating-point exception conditions (invalid, overflow, underflow, inexact). The instruction operates on Half-precision (16-bit), Single-precision (32-bit), or Double-precision (64-bit) formats, determined by the type field. This is an AArch64-only instruction.

Rd ← FP_Add(Rn, Rm)
if (type == 00) then operands are H-registers (16-bit)
else if (type == 01) then operands are S-registers (32-bit)
else if (type == 10) then operands are D-registers (64-bit)


Summary: Subtracts two floating-point values.

Subtracts one scalar floating-point operand from another and writes the result to the destination register. The operation respects IEEE 754 rounding modes and may generate floating-point exception conditions (invalid, overflow, underflow, inexact). The instruction operates on Half-precision (16-bit), Single-precision (32-bit), or Double-precision (64-bit) formats, determined by the type field. This is an AArch64-only instruction.

Rd ← FP_Subtract(Rn, Rm)
if (type == 00) then operands are H-registers (16-bit)
else if (type == 01) then operands are S-registers (32-bit)
else if (type == 10) then operands are D-registers (64-bit)


Summary: Multiplies two floating-point values.

Multiplies two scalar floating-point operands and writes the result to the destination register. The operation respects IEEE 754 rounding modes and may generate floating-point exception conditions (invalid, overflow, underflow, inexact). The instruction operates on Half-precision (16-bit), Single-precision (32-bit), or Double-precision (64-bit) formats, determined by the type field. This is an AArch64-only instruction.

Rd ← FP_Multiply(Rn, Rm)
if (type == 00) then operands are H-registers (16-bit)
else if (type == 01) then operands are S-registers (32-bit)
else if (type == 10) then operands are D-registers (64-bit)


Summary: Divides two floating-point values.

Divides one scalar floating-point operand by another and writes the result to the destination register. The operation respects IEEE 754 rounding modes and may generate floating-point exception conditions (invalid, overflow, underflow, inexact, divide-by-zero). The instruction operates on Half-precision (16-bit), Single-precision (32-bit), or Double-precision (64-bit) formats, determined by the type field. This is an AArch64-only instruction.

Rd ← FP_Divide(Rn, Rm)
if (type == 00) then operands are H-registers (16-bit)
else if (type == 01) then operands are S-registers (32-bit)
else if (type == 10) then operands are D-registers (64-bit)


Floating-Point Fused Multiply-Add (Scalar)

Summary: Calculates (Vn * Vm) + Va without intermediate rounding.

FMADD <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>, <Ha|Sa|Da>

Ha|Sa|Da

Third source (accumulator) SIMD&FP register (half, single or double-precision)

Computes a fused multiply-add operation: (Rn × Rm) + Ra, with a single rounding step applied to the final result. This guarantees higher precision than separate multiply and add instructions. Floating-point exception conditions (invalid, overflow, underflow, inexact) may be generated. The instruction operates on Half-precision (16-bit), Single-precision (32-bit), or Double-precision (64-bit) formats, determined by the type field. This is an AArch64-only instruction.

Rd ← FP_FusedMultiplyAdd(Rn, Rm, Ra)
if (type == 00) then operands are H-registers (16-bit)
else if (type == 01) then operands are S-registers (32-bit)
else if (type == 10) then operands are D-registers (64-bit)


Floating-Point Fused Multiply-Subtract (Scalar)

Summary: Calculates (Vn * Vm) - Va.

FMSUB <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>, <Ha|Sa|Da>

Floating-point fused multiply-subtract: computes (Vn × Vm) - Va and stores the result in Vd as a single fused operation with a single rounding step. Supports half-precision (H), single-precision (S), and double-precision (D) floating-point formats. No condition flags are affected; exceptions may be generated for invalid operations, overflow, underflow, inexact results, or input denormals depending on FPCR settings. AArch64 only.

if HaveFPExt() then
  Vd ← FPMulSub(Vn, Vm, Va)
else
  UNDEFINED


Floating-Point Fused Negated Multiply-Add (Scalar)

Summary: Calculates -((Vn * Vm) + Va).

FNMADD <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>, <Ha|Sa|Da>

Floating-point fused negated multiply-add: computes -((Vn × Vm) + Va) and stores the result in Vd as a single fused operation with a single rounding step. Supports half-precision (H), single-precision (S), and double-precision (D) floating-point formats. No condition flags are affected; exceptions may be generated for invalid operations, overflow, underflow, inexact results, or input denormals depending on FPCR settings. AArch64 only.

if HaveFPExt() then
  Vd ← FPNegMulAdd(Vn, Vm, Va)
else
  UNDEFINED


Floating-Point Fused Negated Multiply-Subtract (Scalar)

Summary: Calculates -((Vn * Vm) - Va).

FNMSUB <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>, <Ha|Sa|Da>

Floating-point fused negated multiply-subtract: computes -((Vn × Vm) - Va) and stores the result in Vd as a single fused operation with a single rounding step. Supports half-precision (H), single-precision (S), and double-precision (D) floating-point formats. No condition flags are affected; exceptions may be generated for invalid operations, overflow, underflow, inexact results, or input denormals depending on FPCR settings. AArch64 only.

if HaveFPExt() then
  Vd ← FPNegMulSub(Vn, Vm, Va)
else
  UNDEFINED


Floating-Point Negated Multiply (Scalar)

Summary: Calculates -(Vn * Vm).

FNMUL <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>

Floating-Point Negated Multiply computes the negation of the product of two floating-point values: -(Vn × Vm), writing the result to Vd. Supports half-precision (type=0, 16-bit), single-precision (type=1, 32-bit), and double-precision (type=2, 64-bit) operands. FPSR exception flags may be set based on invalid, inexact, or overflow conditions. This instruction executes only in AArch64 state.

if type == 0:
  Vd ← -(Vn_float16 × Vm_float16)
else if type == 1:
  Vd ← -(Vn_float32 × Vm_float32)
else if type == 2:
  Vd ← -(Vn_float64 × Vm_float64)


Summary: Calculates square root.

Floating-point square root: computes the square root of Vn and stores the result in Vd. Supports half-precision (H), single-precision (S), and double-precision (D) floating-point formats. No condition flags are affected; exceptions may be generated for invalid operations (negative non-zero inputs), underflow, inexact results, or input denormals depending on FPCR settings. AArch64 only.

if HaveFPExt() then
  Vd ← FPSqrt(Vn)
else
  UNDEFINED


Summary: Negates the value (flips sign bit).

Floating-point negate: flips the sign bit of Vn and stores the result in Vd, converting positive to negative and vice versa (including sign of zero). Supports half-precision (H), single-precision (S), and double-precision (D) floating-point formats. No condition flags are affected; no floating-point exceptions are generated. AArch64 only.

if HaveFPExt() then
  Vd ← FPNeg(Vn)
else
  UNDEFINED


Summary: Returns the larger of two values.

Floating-point maximum: returns the larger of Vn and Vm and stores it in Vd. Supports half-precision (H), single-precision (S), and double-precision (D) floating-point formats. Follows IEEE 754 rules where if either operand is NaN, NaN is returned; if one operand is zero and the other is -0, returns +0. No condition flags are affected; exceptions may be generated for invalid operations or input denormals depending on FPCR settings. AArch64 only.

if HaveFPExt() then
  Vd ← FPMax(Vn, Vm)
else
  UNDEFINED


Summary: Returns the smaller of two values.

Floating-point minimum: returns the smaller of Vn and Vm and stores it in Vd. Supports half-precision (H), single-precision (S), and double-precision (D) floating-point formats. Follows IEEE 754 rules where if either operand is NaN, NaN is returned; if one operand is zero and the other is -0, returns -0. No condition flags are affected; exceptions may be generated for invalid operations or input denormals depending on FPCR settings. AArch64 only.

if HaveFPExt() then
  Vd ← FPMin(Vn, Vm)
else
  UNDEFINED


Summary: Returns larger value, handling NaNs according to IEEE 754-2008 'maxNum'.

FMAXNM <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>

Floating-point maximum number: returns the larger of two floating-point numbers Vn and Vm according to IEEE 754-2008 'maxNum' semantics, where if one operand is NaN and the other is a number, the number is returned. Supports half-precision (H), single-precision (S), and double-precision (D) floating-point formats. No condition flags are affected; exceptions may be generated for invalid operations or input denormals depending on FPCR settings. AArch64 only.

if HaveFPExt() then
  Vd ← FPMaxNum(Vn, Vm)
else
  UNDEFINED


Summary: Returns smaller value, handling NaNs according to IEEE 754-2008 'minNum'.

FMINNM <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>

Floating-point minimum of two scalar values, returning the number (non-NaN) operand when one operand is NaN, per IEEE 754-2008 minNum semantics. Condition flags (N, Z, C, V) are not affected. AArch64-only instruction.

if IsNaN(Vn) then
  result ← Vm
elsif IsNaN(Vm) then
  result ← Vn
else
  result ← min(Vn, Vm)
Vd ← result


Summary: Compares two floating-point values and updates process flags (NZCV).

Compares two floating-point scalar values and updates the NZCV condition flags based on the result. The comparison is performed on the values in the two source registers, and flags are set to reflect whether the first operand is less than, equal to, greater than, or unordered with respect to the second. This is an AArch64-only instruction that does not modify any registers, only the NZCV flags.

result ← FPCompare(Vn, Vm)
N ← result.N
Z ← result.Z
C ← result.C
V ← result.V


Floating-Point Conditional Compare (Scalar)

Summary: Compares floats only if condition is met, else sets flags to immediate.

FCCMP <Hn|Sn|Dn>, <Hm|Sm|Dm>, #<nzcv>, <cond>

Conditionally compares two floating-point scalar values if the specified condition is true, updating NZCV flags with the comparison result; if the condition is false, sets NZCV to the immediate value provided. This is an AArch64-only instruction that allows conditional flag updates without branching, useful for implementing conditional chains and complex control flow.

if ConditionHolds(cond) then
  result ← FPCompare(Vn, Vm)
  N ← result.N
  Z ← result.Z
  C ← result.C
  V ← result.V
else
  N ← nzcv[3]
  Z ← nzcv[2]
  C ← nzcv[1]
  V ← nzcv[0]


Floating-Point Conditional Select (Scalar)

Summary: Selects one of two floats based on condition flags.

FCSEL <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>, <cond>

Selects between two floating-point scalar values based on the current condition flags, writing the selected value to the destination register. If the condition is true, Vn is selected; otherwise, Vm is selected. This is an AArch64-only instruction that does not modify condition flags or any register other than the destination.

if ConditionHolds(cond) then
  Vd ← Vn
else
  Vd ← Vm


Summary: Converts between float precisions (e.g., Half <-> Single <-> Double).

Converts a scalar floating-point value between precision formats (e.g., Half ↔ Single ↔ Double). The rounding mode is determined by FPCR.RMode. Condition flags are not affected. AArch64-only instruction.

operand ← Vn
result ← ConvertFP(operand, source_precision, destination_precision, FPCR.RMode)
Vd ← result


Floating-Point Convert to Signed Integer (Nearest)

Summary: Converts float to signed integer, rounding to nearest.

Wd|Xd

Destination general-purpose register (32-bit/64-bit)

Converts a scalar floating-point value to a signed integer, rounding to nearest with ties away from zero. Sets condition flags based on the integer result. Raises Invalid Operation exception on overflow or invalid input. AArch64-only instruction.

operand ← Vn
intval ← RoundTowardNearestAwayFromZero(operand)
if intval > MaxInt(destination_width) or intval < MinInt(destination_width) then
  GenerateException(InvalidOperation)
else
  Rd ← SignExtend(intval)
  UpdateFlags(intval)
end


Floating-Point Convert to Unsigned Integer (Nearest)

Summary: Converts float to unsigned integer, rounding to nearest.

Converts a scalar floating-point value to an unsigned integer, rounding to nearest with ties away from zero. Sets condition flags based on the integer result. Raises Invalid Operation exception on overflow or invalid input. AArch64-only instruction.

operand ← Vn
intval ← RoundTowardNearestAwayFromZero(operand)
if intval > MaxUInt(destination_width) or intval < 0 then
  GenerateException(InvalidOperation)
else
  Rd ← ZeroExtend(intval)
  UpdateFlags(intval)
end


Floating-Point Convert to Signed Integer (Minus Infinity)

Summary: Converts float to signed integer, rounding towards minus infinity (Floor).

Converts a scalar floating-point value to a signed integer, rounding towards negative infinity (floor). Sets condition flags based on the integer result. Raises Invalid Operation exception on overflow or invalid input. AArch64-only instruction.

operand ← Vn
intval ← Floor(operand)
if intval > MaxInt(destination_width) or intval < MinInt(destination_width) then
  GenerateException(InvalidOperation)
else
  Rd ← SignExtend(intval)
  UpdateFlags(intval)
end


Floating-Point Convert to Unsigned Integer (Minus Infinity)

Summary: Converts float to unsigned integer, rounding towards minus infinity.

Converts a scalar floating-point value to an unsigned integer, rounding towards negative infinity (floor). Sets condition flags based on the integer result. Raises Invalid Operation exception on overflow or invalid input. AArch64-only instruction.

operand ← Vn
intval ← Floor(operand)
if intval > MaxUInt(destination_width) or intval < 0 then
  GenerateException(InvalidOperation)
else
  Rd ← ZeroExtend(intval)
  UpdateFlags(intval)
end


Floating-Point Convert to Signed Integer (Nearest, ties to Even)

Summary: Converts float to signed integer, rounding to nearest (bankers' round).

Converts a scalar floating-point value to a signed integer, rounding to nearest with ties to even (bankers' round). Sets condition flags based on the integer result. Raises Invalid Operation exception on overflow or invalid input. AArch64-only instruction.

operand ← Vn
intval ← RoundTowardNearestEven(operand)
if intval > MaxInt(destination_width) or intval < MinInt(destination_width) then
  GenerateException(InvalidOperation)
else
  Rd ← SignExtend(intval)
  UpdateFlags(intval)
end


Floating-Point Convert to Unsigned Integer (Nearest, ties to Even)

Summary: Converts float to unsigned integer, rounding to nearest (bankers' round).

Converts a scalar floating-point value to an unsigned integer, rounding to nearest with ties to even (bankers' round). Sets condition flags based on the integer result. Raises Invalid Operation exception on overflow or invalid input. AArch64-only instruction.

operand ← Vn
intval ← RoundTowardNearestEven(operand)
if intval > MaxUInt(destination_width) or intval < 0 then
  GenerateException(InvalidOperation)
else
  Rd ← ZeroExtend(intval)
  UpdateFlags(intval)
end


Floating-Point Convert to Signed Integer (Plus Infinity)

Summary: Converts float to signed integer, rounding towards plus infinity (Ceil).

Converts a floating-point value to a signed integer, rounding towards plus infinity (ceiling). The source is read from a half-precision (H), single-precision (S), or double-precision (D) FP register, and the result is written to a 32-bit (W) or 64-bit (X) general-purpose register. NZCV flags are not affected by this instruction. This is an AArch64-only instruction that executes at any privilege level.

if source_is_nan then
  result ← 0
else
  result ← round_to_plus_infinity(FP_to_signed_integer(Vn))
Rd ← result


Floating-Point Convert to Unsigned Integer (Plus Infinity)

Summary: Converts float to unsigned integer, rounding towards plus infinity.

Converts a floating-point value to an unsigned integer, rounding towards plus infinity (ceiling). The source is read from a half-precision (H), single-precision (S), or double-precision (D) FP register, and the result is written to a 32-bit (W) or 64-bit (X) general-purpose register. NZCV flags are not affected by this instruction. This is an AArch64-only instruction that executes at any privilege level.

if source_is_nan then
  result ← 0
else
  result ← round_to_plus_infinity(FP_to_unsigned_integer(Vn))
Rd ← result


Floating-Point Convert to Signed Integer (Zero)

Summary: Converts float to signed integer, rounding towards zero (Truncate).

Converts a floating-point value to a signed integer, rounding towards zero (truncation). The source is read from a half-precision (H), single-precision (S), or double-precision (D) FP register, and the result is written to a 32-bit (W) or 64-bit (X) general-purpose register. An optional fixed-point shift parameter (fbits) can scale the result by 2^fbits. NZCV flags are not affected by this instruction. This is an AArch64-only instruction that executes at any privilege level.

if source_is_nan then
  result ← 0
else
  if fbits_present then
    result ← round_towards_zero(FP_to_signed_integer(Vn) × 2^fbits)
  else
    result ← round_towards_zero(FP_to_signed_integer(Vn))
Rd ← result


Floating-Point Convert to Unsigned Integer (Zero)

Summary: Converts float to unsigned integer, rounding towards zero (Truncate).

Converts a floating-point value to an unsigned integer, rounding towards zero (truncation). The source is read from a half-precision (H), single-precision (S), or double-precision (D) FP register, and the result is written to a 32-bit (W) or 64-bit (X) general-purpose register. An optional fixed-point shift parameter (fbits) can scale the result by 2^fbits. NZCV flags are not affected by this instruction. This is an AArch64-only instruction that executes at any privilege level.

if source_is_nan then
  result ← 0
else
  if fbits_present then
    result ← round_towards_zero(FP_to_unsigned_integer(Vn) × 2^fbits)
  else
    result ← round_towards_zero(FP_to_unsigned_integer(Vn))
Rd ← result


Signed Integer Convert to Floating-Point

Summary: Converts signed integer (GPR) to floating-point.

Wn|Xn

First source general-purpose register (32-bit/64-bit)

Converts a signed integer value from a GPR to floating-point format and writes the result to an FP scalar register. The conversion respects an optional fixed-point scaling factor (fbits) if provided, effectively dividing the result by 2^fbits. This is an AArch64-only instruction that does not modify condition flags.

int_val ← SignExtend(Rn)
if fbits != 0 then
  fp_val ← ConvertToFP(int_val / 2^fbits)
else
  fp_val ← ConvertToFP(int_val)
Vd ← fp_val


Unsigned Integer Convert to Floating-Point

Summary: Converts unsigned integer (GPR) to floating-point.

Converts an unsigned integer value from a GPR to floating-point format and writes the result to an FP scalar register. The conversion respects an optional fixed-point scaling factor (fbits) if provided, effectively dividing the result by 2^fbits. This is an AArch64-only instruction that does not modify condition flags.

uint_val ← ZeroExtend(Rn)
if fbits != 0 then
  fp_val ← ConvertToFP(uint_val / 2^fbits)
else
  fp_val ← ConvertToFP(uint_val)
Vd ← fp_val


Floating-Point Round to Integral (Nearest)

Summary: Rounds float to nearest integral value (ties away from zero).

Rounds a floating-point scalar value to the nearest integral value, with ties rounded away from zero. The rounding mode is always "round to nearest, ties away from zero" regardless of the FPCR rounding mode setting. This is an AArch64-only instruction that does not modify condition flags.

rounded_val ← RoundToIntegral_TiesAwayFromZero(Vn)
Vd ← rounded_val


Floating-Point Round to Integral (Current)

Summary: Rounds float to integral value using current FPCR rounding mode.

Rounds a floating-point scalar value to an integral value using the current rounding mode specified in the FPCR (Floating-Point Control Register). The rounding behavior depends on the RMode field in FPCR. This is an AArch64-only instruction that does not modify condition flags.

rounded_val ← RoundToIntegral_CurrentMode(Vn)
Vd ← rounded_val


Floating-Point Round to Integral (Minus Infinity)

Summary: Rounds float to integral value towards minus infinity (Floor).

Rounds a floating-point scalar value towards negative infinity (floor). The rounding mode is always "round towards minus infinity" regardless of the FPCR rounding mode setting. This is an AArch64-only instruction that does not modify condition flags.

rounded_val ← RoundToIntegral_MinusInfinity(Vn)
Vd ← rounded_val


Floating-Point Round to Integral (Nearest Even)

Summary: Rounds float to integral value nearest, ties to even.

Rounds the floating-point value in the source register to the nearest integer using round-to-nearest-ties-to-even mode, and writes the result to the destination register. The instruction does not set any condition flags (N, Z, C, V remain unaffected). Execution is AArch64-only and may generate floating-point exceptions based on the source operand and enabled exception controls.


Floating-Point Round to Integral (Plus Infinity)

Summary: Rounds float to integral value towards plus infinity (Ceil).

Rounds the floating-point value in the source register to the nearest integer towards positive infinity (ceiling), and writes the result to the destination register. The instruction does not set any condition flags (N, Z, C, V remain unaffected). Execution is AArch64-only and may generate floating-point exceptions based on the source operand and enabled exception controls.


Floating-Point Round to Integral (Exact)

Summary: Rounds float to integral value using current mode, raising Inexact exception.

Rounds the floating-point value in the source register to the nearest integer using the current rounding mode and raises an Inexact floating-point exception if the result differs from the input. The instruction does not set condition flags (N, Z, C, V remain unaffected). Execution is AArch64-only and always signals the Inexact exception condition when rounding occurs.

Vd ← RoundToIntegral(Vn); if Vd ≠ Vn then RaiseInexactException()


Summary: Rounds float to integral value towards zero (Truncate).

Rounds the floating-point value in the source register to the nearest integer towards zero (truncation), and writes the result to the destination register. The instruction does not set any condition flags (N, Z, C, V remain unaffected). Execution is AArch64-only and may generate floating-point exceptions based on the source operand and enabled exception controls.


Summary: Moves a floating-point immediate into a scalar register.

Moves a floating-point immediate constant into a half-precision (H), single-precision (S), or double-precision (D) scalar FP register. The immediate is encoded as an 8-bit value and expanded to full precision according to the IEEE 754 floating-point format. NZCV flags are not affected. This is an AArch64-only instruction that executes at any privilege level.


Summary: Copies a value from one scalar FP register to another.

Copies a floating-point value from one scalar FP register to another, preserving the value and precision. Both source and destination must be the same type (half-precision, single-precision, or double-precision). NZCV flags are not affected. This is an AArch64-only instruction that executes at any privilege level.


Summary: Copies bits between a General-Purpose Register (W/X) and FP Register (S/D).

Sn|Dn

First source SIMD&FP register (single or double-precision)

Copies the bit pattern from a floating-point register (single-precision or double-precision) to a general-purpose register (32-bit or 64-bit), treating the value as an opaque bit sequence without any floating-point interpretation. NZCV flags are not affected. This is an AArch64-only instruction that executes at any privilege level.


Summary: Copies bits from a General-Purpose Register (W/X) to FP Register (S/D).

Sd|Dd

Destination SIMD&FP register (single or double-precision)

Copies the bit pattern from a general-purpose register (32-bit or 64-bit) to a floating-point register (single-precision or double-precision), treating the value as an opaque bit sequence without any floating-point interpretation. NZCV flags are not affected. This is an AArch64-only instruction that executes at any privilege level.


Summary: Loads a floating-point/SIMD register from memory.

LDR <Bt|Ht|St|Dt|Qt>, [<Xn|SP>, #<pimm>]

Bt|Ht|St|Dt|Qt

Transfer SIMD&FP register (byte, half, single, double or quad-precision)

Xn|SP

First source / base 64-bit integer register

The Load SIMD&FP Register instruction loads a floating-point/SIMD register from memory.


Summary: Stores a floating-point/SIMD register to memory.

STR <Bt|Ht|St|Dt|Qt>, [<Xn|SP>, #<pimm>]

The Store SIMD&FP Register instruction stores a floating-point/SIMD register to memory.


Summary: Loads two floating-point/SIMD registers.

First transfer SIMD&FP register (single, double or quad-precision)

Second transfer SIMD&FP register (single, double or quad-precision)

Loads two consecutive floating-point or SIMD vector registers from memory at an address calculated from a base register and a scaled signed immediate offset. The two values are loaded atomically as a pair, and no condition flags are affected. Execution is AArch64-only; the immediate is scaled by the operand size (4 bytes for 32-bit, 8 bytes for 64-bit, 16 bytes for 128-bit).

address ← (Xn | SP) + (imm7 << scale); Vt1 ← [address]; Vt2 ← [address + operand_size]


Summary: Stores two floating-point/SIMD registers.

Stores two consecutive floating-point or SIMD vector registers to memory at an address calculated from a base register and a scaled signed immediate offset. The two values are stored atomically as a pair, and no condition flags are affected. Execution is AArch64-only; the immediate is scaled by the operand size (4 bytes for 32-bit, 8 bytes for 64-bit, 16 bytes for 128-bit).

address ← (Xn | SP) + (imm7 << scale); [address] ← Vt1; [address + operand_size] ← Vt2


Summary: Loads a byte from memory (zero-extended) using immediate offset.

Wt

Transfer 32-bit integer register (load/store)

Loads an unsigned byte from memory using immediate offset and zero-extends it to 32 bits, writing the result to a 32-bit register. No condition flags are affected. This is an AArch64 Base instruction that executes in all privilege levels.

address ← Xn + (pimm << 0);
Wt ← ZeroExtend(Mem[address, 1], 32);


Summary: Loads a byte from memory (zero-extended) using register offset.

LDRB <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}]

Loads an unsigned byte from memory using register offset with optional shift/extension and zero-extends it to 32 bits. No condition flags are affected. This is an AArch64 Base instruction that executes in all privilege levels.

offset ← ExtendReg(Rm, extend_type, shift_amount);
address ← Xn + offset;
Wt ← ZeroExtend(Mem[address, 1], 32);


Summary: Loads a halfword from memory (zero-extended).

Loads an unsigned halfword from memory using immediate offset and zero-extends it to 32 bits. No condition flags are affected. This is an AArch64 Base instruction that executes in all privilege levels.

address ← Xn + (pimm << 1);
Wt ← ZeroExtend(Mem[address, 2], 32);


Summary: Loads a halfword from memory (zero-extended) using register offset.

LDRH <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}]

Loads an unsigned halfword from memory using register offset with optional extension and zero-extends it to 32 bits. No condition flags are affected. This is an AArch64 Base instruction that executes in all privilege levels.

offset ← ExtendReg(Rm, extend_type, shift_amount);
address ← Xn + offset;
Wt ← ZeroExtend(Mem[address, 2], 32);


Summary: Loads a byte and sign-extends it to 32-bits.

Loads a signed byte from memory using immediate offset and sign-extends it to 32 bits. No condition flags are affected. This is an AArch64 Base instruction that executes in all privilege levels.

address ← Xn + (pimm << 0);
Wt ← SignExtend(Mem[address, 1], 32);


Load Register Signed Byte (64-bit Immediate)

Summary: Loads a byte and sign-extends it to 64-bits.

Xt

Transfer 64-bit integer register (load/store)

Loads a signed byte from memory using immediate offset and sign-extends it to 64 bits. No condition flags are affected. This is an AArch64 Base instruction that executes in all privilege levels.

address ← Xn + (pimm << 0);
Xt ← SignExtend(Mem[address, 1], 64);


Summary: Loads a word and sign-extends it to 64-bits.

Loads a signed word from memory using immediate offset and sign-extends it to 64 bits. No condition flags are affected. This is an AArch64 Base instruction that executes in all privilege levels.

address ← Xn + (pimm << 2);
Xt ← SignExtend(Mem[address, 4], 64);


Summary: Loads a word from PC-relative address and sign-extends to 64-bits.

Loads a signed word from memory at a PC-relative address (literal) and sign-extends it to 64 bits. No condition flags are affected. This is an AArch64 Base instruction that executes in all privilege levels.

address ← PC + SignExtend(imm19 << 2, 64);
Xt ← SignExtend(Mem[address, 4], 64);


Summary: Loads a word as if in EL0 (User mode).

Loads a 32-bit word from memory using an address calculated from a base register and a signed immediate offset, with the access performed as if executing at EL0 (User mode) privilege level. This instruction is typically used for debugging or privilege crossing and does not affect condition flags (N, Z, C, V remain unaffected). Execution is AArch64-only and restricted to privileged exception levels (EL1 or higher); using it at EL0 results in an illegal instruction exception.

address ← (Xn | SP) + SignExtend(imm9, 64); Wt ← ZeroExtend([address]<31:0>, 64)


Summary: Loads a word using an unscaled immediate offset.

Loads a 32-bit word from memory using an address calculated from a base register and an unscaled signed immediate offset. No condition flags are affected (N, Z, C, V remain unaffected). Execution is AArch64-only; the offset is applied directly without scaling and allows for more flexible address formation than scaled-offset variants.


Summary: Loads a word and marks physical address as exclusive access.

Loads a 32-bit word from memory at the address in Xn|SP and marks the physical address as exclusive for subsequent store-exclusive operations. No condition flags are affected. This is an AArch64-only instruction that requires Execute permission on the accessed memory and generates an alignment fault if the address is not word-aligned.

address ← [Xn|SP]
Wt ← [address]
ExclusiveMonitors.MarkExclusive(address, ProcessorID, 4)


Summary: Loads two words as an exclusive operation.

Loads two consecutive 32-bit words from memory at the address in Xn|SP and marks the physical address pair as exclusive for subsequent store-exclusive operations. No condition flags are affected. This is an AArch64-only instruction that requires Execute permission and generates an alignment fault if the address is not 8-byte aligned.

address ← [Xn|SP]
Wt1 ← [address]
Wt2 ← [address + 4]
ExclusiveMonitors.MarkExclusive(address, ProcessorID, 8)


Summary: Shifts register left by variable amount.

Wn

First source / base 32-bit integer register

Logical Shift Left by variable register count. Shifts the value in Wn left by the number of bits specified in the lower 5 bits of Wm, shifting in zeros from the right. Does not affect the condition flags (N, Z, C, V remain unchanged). AArch64-only instruction.

shift_amount ← Wm[4:0]
Wd ← Wn << shift_amount


Summary: Shifts register right by variable amount.

Logical Shift Right by variable register count. Shifts the value in Wn right by the number of bits specified in the lower 5 bits of Wm, shifting in zeros from the left. Does not affect the condition flags (N, Z, C, V remain unchanged). AArch64-only instruction.

shift_amount ← Wm[4:0]
Wd ← Wn >> shift_amount


Summary: Calculates (Ra + (Rn * Rm)).

Wm

Second source / offset 32-bit integer register

Multiplies Wn by Wm and adds the result to Wa, storing the result in Wd. All intermediate values are computed with full 64-bit precision before truncating to 32 bits. No condition flags are affected. This is an AArch64-only instruction that does not generate any exceptions.


Summary: Calculates (Xa + (Xn * Xm)).

Xm

Second source / offset 64-bit integer register

Multiply-Add: multiplies Xn by Xm and adds the result to Xa, storing the 64-bit result in Xd. Does not affect condition flags. AArch64-only instruction with no privilege restrictions.


Summary: Calculates (Ra - (Rn * Rm)).

Multiplies Wn by Wm and subtracts the result from Wa, storing the result in Wd. All intermediate values are computed with full 64-bit precision before truncating to 32 bits. No condition flags are affected. This is an AArch64-only instruction that does not generate any exceptions.


Summary: Inserts a 16-bit immediate into a register, keeping other bits unchanged.

Inserts a 16-bit immediate value into Wd at the position specified by the shift, leaving other 16-bit half-words unchanged. No condition flags are affected. This is an AArch64-only instruction commonly used to build large constants or patch specific 16-bit fields in registers.

shift_amount ← hw × 16
mask ← 0xFFFF ≪ shift_amount
Wd ← (Wd ∧ ¬mask) ∨ (imm16 ≪ shift_amount)


Summary: Moves inverted 16-bit immediate to register.

Moves the bitwise NOT of a 16-bit immediate into Wd (at the position specified by shift), zeroing other 16-bit half-words. No condition flags are affected. This is an AArch64-only instruction useful for loading negative or inverted constants into registers.

shift_amount ← hw × 16
mask ← 0xFFFF ≪ shift_amount
Wd ← (Wd ∧ ¬mask) ∨ ((¬imm16) ≪ shift_amount)


Summary: Moves 16-bit immediate to register, zeroing other bits.

Moves a 16-bit immediate into Wd at the position specified by shift, zeroing all other 16-bit half-words. No condition flags are affected. This is an AArch64-only instruction commonly used as the first instruction when building large constants, often followed by MOVK instructions.

shift_amount ← hw × 16
Wd ← imm16 ≪ shift_amount


Summary: Moves system register to general-purpose register.

Reads the value of a system register and copies it to the 64-bit general-purpose register Xt. No condition flags are affected. This is an AArch64-only instruction that requires appropriate privilege level (EL0 or higher depending on register access permissions) and generates an exception if the register is not accessible at the current privilege level.


Summary: Moves general-purpose register to system register.

Moves the value from a 64-bit general-purpose register to a system register, enabling modification of processor state, exception handling, and memory management controls. The instruction is AArch64-only and typically requires sufficient privilege level to access the target system register; attempting to write a register without privilege raises an exception. Condition flags are not affected by this instruction.


Summary: ORs register with NOT of shifted register.

ORN <Wd>, <Wn>, <Wm> {, <shift> #<amount>}

Performs a bitwise OR between a register and the bitwise NOT of a second (optionally shifted) register, storing the result in the destination. All condition flags (N, Z, C, V) are updated based on the result; N and Z are set according to the result value, while C and V are cleared to zero. This is a 32-bit operation in the W-register form; a 64-bit X-register form also exists with identical semantics.

result ← Wn | ~(Wm << shift_amount)
Wd ← result
N ← result[31]
Z ← (result == 0)
C ← 0
V ← 0


Summary: ORs register with logical immediate.

Bitwise OR with logical immediate. Performs bitwise OR between Wn and a 32-bit bitmask immediate, storing the result in Wd. The immediate is expanded using the logical immediate encoding (N:immr:imms). Sets the Z flag if the result is zero; N, C, V flags are unaffected. AArch64-only instruction.

imm32 ← LogicalImmediate(N, immr, imms, 32)
Wd ← Wn | imm32
Z ← (Wd == 0)


Summary: ORs two registers.

ORR <Wd>, <Wn>, <Wm> {, <shift> #<amount>}

Bitwise OR with shifted register. Performs bitwise OR between Wn and a shifted version of Wm (shifted by amount in imm6), storing the result in Wd. Does not affect condition flags (N, Z, C, V remain unchanged). AArch64-only instruction.

shift_amount ← imm6
shift_type ← LSL
operand ← Wm << shift_amount
Wd ← Wn | operand


Summary: Reverses the bit order in a register.

Reverses the order of all bits in a 32-bit register, placing the least-significant bit in the most-significant position and vice versa. Condition flags are not affected by this instruction. This is a pure bit-reversal operation with no side effects.


Summary: Branches to address in LR (or specified register).

Performs an indirect branch to the address held in a register, with a default of the link register (X30/LR) if no register is specified, typically used to return from a subroutine. The instruction is AArch64-only and sets the program counter to the target address; no condition flags are affected. This instruction may generate an exception if branch target prediction is enabled and the target address prediction fails (Branch Target Prediction/BTI).

if Xn is not specified then
  target ← X30
else
  target ← Xn
PC ← target


Summary: Reverses byte order in a 64-bit register.

Reverse byte order in a 64-bit register. Reverses the byte order of the 64-bit value in Xn and stores the result in Xd. Does not affect condition flags. AArch64-only instruction.


Summary: Reverses bytes in each 16-bit halfword.

Reverses the byte order within each 16-bit halfword of a 32-bit register independently, leaving halfword boundaries intact. Condition flags are not affected by this instruction. This is useful for converting individual 16-bit values between endianness without affecting the halfword order.


Summary: Reverses bytes in each 32-bit word (64-bit op).

Reverses the byte order within each 32-bit word of a 64-bit register independently, leaving word boundaries intact. Condition flags are not affected by this instruction. This operation is performed on 64-bit registers (X-registers) and processes two 32-bit words in parallel.


Summary: Rotates register right by variable amount.

Rotate Right by variable register count. Rotates the value in Wn right by the number of bits specified in the lower 5 bits of Wm; bits rotated off the right are inserted at the left. Does not affect condition flags (N, Z, C, V remain unchanged). AArch64-only instruction.

shift_amount ← Wm[4:0]
Wd ← (Wn >> shift_amount) | (Wn << (32 - shift_amount))


Summary: Subtracts with borrow (Carry - 1).

Subtracts one register from another with a borrow (carry-in), computing Wd = Wn - (Wm + NOT(C)), where the carry flag is inverted before use as a borrow. All condition flags (N, Z, C, V) are updated: N and Z reflect the result, C is set if no borrow occurred (result ≥ 0 in unsigned arithmetic), and V is set if signed overflow occurred. This is a 32-bit operation; a 64-bit variant (SBC for X-registers) exists with identical semantics.

borrow ← NOT(C)
result ← Wn - (Wm + borrow)
Wd ← result
N ← result[31]
Z ← (result == 0)
C ← NOT(BorrowFrom(Wn - (Wm + borrow)))
V ← OverflowFrom(Wn - (Wm + borrow))


Summary: Subtracts with borrow and updates flags.

Subtracts the value in Wm and the inverted Carry flag from Wn, storing the result in Wd and updating the condition flags. The Carry flag is inverted before subtraction, so if C=0 (no carry), a borrow of 1 is subtracted. All four flags (N, Z, C, V) are updated based on the result. This instruction is available in AArch64 and A32/T32 variants.

result ← Wn - Wm - (1 - C)
Wd ← result[31:0]
N ← result[31]
Z ← (result == 0)
C ← NOT(BorrowFrom(Wn - Wm - (1 - C)))
V ← OverflowFrom(Wn - Wm - (1 - C))


Summary: Extracts/Inserts bitfield with sign extension.

Extracts a bitfield from Wn with sign extension and places it in Wd. The bitfield is defined by immr (rotate right amount) and imms (field size), with the field width determined by the difference between imms and immr (plus 1). The extracted value is sign-extended to fill the 32-bit destination. No condition flags are affected. This is an AArch64 instruction.

width ← imms - immr + 1
if imms >= immr then
  extracted ← ROR(Wn, immr)[width-1:0]
  Wd ← SignExtend(extracted, width)
else
  extracted ← ROR(Wn, immr)[width-1:0]
  Wd ← SignExtend(extracted, width)
N ← unchanged
Z ← unchanged
C ← unchanged
V ← unchanged


Summary: Divides two signed registers.

Divides the signed 32-bit integer in Wn by the signed 32-bit integer in Wm and places the quotient in Wd. If Wm is zero, the result is zero (no exception is raised). No condition flags are affected. This instruction is available in AArch64, ARMv7 with IDIV extension, and Thumb with IDIV extension.

if Wm == 0 then
  Wd ← 0
else
  Wd ← SignedDiv(Wn, Wm)
N ← unchanged
Z ← unchanged
C ← unchanged
V ← unchanged


Summary: Multiplies two 32-bit registers, adds to 64-bit register (64-bit result).

Multiplies the signed 32-bit values in Wn and Wm to produce a 64-bit result, then adds the 64-bit value in Xa and places the 64-bit sum in Xd. This is used for wider multiply-accumulate operations. No condition flags are affected. This instruction is AArch64-only.

product ← SignExtend(Wn, 64) * SignExtend(Wm, 64)
Xd ← product + Xa
N ← unchanged
Z ← unchanged
C ← unchanged
V ← unchanged


Summary: Calculates (Xa - (Wn * Wm)) (64-bit result).

Multiplies the signed 32-bit values in Wn and Wm to produce a 64-bit result, then subtracts this product from the 64-bit value in Xa and places the 64-bit difference in Xd. This is used for wider multiply-subtract operations. No condition flags are affected. This instruction is AArch64-only.

product ← SignExtend(Wn, 64) * SignExtend(Wm, 64)
Xd ← Xa - product
N ← unchanged
Z ← unchanged
C ← unchanged
V ← unchanged


Summary: Multiplies two 64-bit registers, keeps high 64 bits.

Multiplies two signed 64-bit integers in Xn and Xm and places the high 64 bits of the 128-bit result in Xd. This instruction is used when the full precision of a 64×64 signed multiplication is needed. No condition flags are affected. This instruction is AArch64-only.

result ← Xn * Xm
Xd ← result[127:64]
N ← unchanged
Z ← unchanged
C ← unchanged
V ← unchanged


Summary: Stores a word with Release semantics.

Stores the 32-bit value in Wt to memory at the address specified by Xn (or SP), with Release semantics for synchronization. The Release semantics ensure that all memory operations before this instruction are visible to observers before the store completes. No condition flags are affected. This instruction is AArch64-only and requires the Load-Acquire/Store-Release extension.

address ← Xn
MemoryOrder(Release)
[address] ← Wt[31:0]


Summary: Stores a byte with Release semantics.

Stores the least significant byte of Wt to memory at the address specified by Xn (or SP), with Release semantics for synchronization. The Release semantics ensure that all memory operations before this instruction are visible to observers before the byte store completes. No condition flags are affected. This instruction is AArch64-only and requires the Load-Acquire/Store-Release extension.

address ← Xn
MemoryOrder(Release)
[address] ← Wt[7:0]


Summary: Stores a halfword with Release semantics.

Stores a halfword from Wt to memory at the address in Xn with Release semantics, ensuring all prior memory operations are observed before the store completes. This is an AArch64-only instruction used for synchronization in multi-threaded code. No condition flags are affected.

[Xn] ← Wt<15:0>; Release semantics applied


Summary: Stores a word with Release Exclusive semantics.

Attempts an exclusive store of a 32-bit word from Wt to memory at the address in Xn with Release semantics, writing 0 to Ws if successful or 1 if the exclusive monitor was not held. This is an AArch64-only instruction used for atomic operations. No condition flags are affected.

if ExclusiveMonitorHeld(Xn) then { [Xn] ← Wt; Ws ← 0; Release semantics applied } else { Ws ← 1 }


Summary: Stores a byte with Release Exclusive semantics.

Attempts an exclusive store of a byte from Wt to memory at the address in Xn with Release semantics, writing 0 to Ws if successful or 1 if the exclusive monitor was not held. This is an AArch64-only instruction used for atomic byte operations. No condition flags are affected.

if ExclusiveMonitorHeld(Xn) then { [Xn] ← Wt<7:0>; Ws ← 0; Release semantics applied } else { Ws ← 1 }


Store-Release Exclusive Register Halfword

Summary: Stores a halfword with Release Exclusive semantics.

Attempts an exclusive store of a halfword from Wt to memory at the address in Xn with Release semantics, writing 0 to Ws if successful or 1 if the exclusive monitor was not held. This is an AArch64-only instruction used for atomic halfword operations. No condition flags are affected.

if ExclusiveMonitorHeld(Xn) then { [Xn] ← Wt<15:0>; Ws ← 0; Release semantics applied } else { Ws ← 1 }


Summary: Stores two registers, hinting non-temporal data.

First transfer 32-bit register (load/store pair)

Second transfer 32-bit register (load/store pair)

Store Pair (Non-temporal): stores two consecutive 32-bit registers (Wt1 and Wt2) to memory at the address computed from Xn plus a signed scaled offset (imm7 × 4). The non-temporal hint indicates the data is unlikely to be reused soon. Does not affect condition flags. AArch64-only instruction.

offset ← imm7 << 2
address ← Xn + offset
[address] ← Wt1
[address + 4] ← Wt2


Summary: Stores two 32-bit registers.

Stores a pair of 32-bit registers (Wt1 and Wt2) to consecutive memory locations at [Xn + (imm7 << 2)] with a signed immediate offset. This is an AArch64-only instruction commonly used for stack operations. No condition flags are affected.

address ← Xn + (imm7 << 2); [address] ← Wt1; [address + 4] ← Wt2


Summary: Stores two 64-bit registers.

First transfer 64-bit register (load/store pair)

Second transfer 64-bit register (load/store pair)

Stores two consecutive 64-bit registers to memory at an address calculated from a base register and a signed immediate offset (scaled by 8). Does not affect condition flags. AArch64-only instruction; the immediate offset is encoded as imm7 and scaled by 8 to form the actual offset.

address ← Xn + (imm7 << 3)
[address] ← Xt1
[address + 8] ← Xt2


Summary: Stores a register to memory (Immediate offset).

Stores a 32-bit register to memory at an address calculated from a base register and a positive immediate offset (scaled by 4). Does not affect condition flags. AArch64-only instruction; the immediate is encoded as imm12 and scaled by 4.

address ← Xn + (imm12 << 2)
[address] ← Wt[31:0]


Summary: Stores a register to memory (Register offset).

STR <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}]

Stores a 32-bit register to memory using register-based addressing with optional extension and shift of the offset register. Does not affect condition flags. AArch64-only; supports UXTW, UXTX, SXTW, SXTX extensions with optional left shift.

offset ← ExtendValue(Rm, option, S)
address ← Xn + offset
[address] ← Wt[31:0]


Summary: Stores the low byte of a register.

Stores the low byte (bits 7:0) of a 32-bit register to memory at an address calculated from a base register and a positive immediate offset (unscaled). Does not affect condition flags. AArch64-only instruction.

address ← Xn + imm12
[address] ← Wt[7:0]


Summary: Stores the low byte of a register using register offset.

STRB <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}]

Stores the low byte (bits 7:0) of a 32-bit register to memory using register-based addressing with optional extension and shift of the offset register. Does not affect condition flags. AArch64-only; supports UXTW, UXTX, SXTW, SXTX extensions.

offset ← ExtendValue(Rm, option, S)
address ← Xn + offset
[address] ← Wt[7:0]


Summary: Stores the low halfword of a register.

Stores the low halfword (bits 15:0) of a 32-bit register to memory at an address calculated from a base register and a positive immediate offset (scaled by 2). Does not affect condition flags. AArch64-only instruction.

address ← Xn + (imm12 << 1)
[address] ← Wt[15:0]


Summary: Stores the low halfword of a register using register offset.

STRH <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}]

Stores the low halfword (bits 15:0) of a 32-bit register to memory using register-based addressing with optional extension and shift of the offset register. Does not affect condition flags. AArch64-only; supports UXTW, UXTX, SXTW, SXTX extensions with optional left shift.

offset ← ExtendValue(Rm, option, S)
address ← Xn + offset
[address] ← Wt[15:0]


Summary: Stores a register as if in EL0 (User mode).

Stores a 32-bit word from Wt to memory at [Xn + simm] with unprivileged semantics, as if the access were made from EL0. This is an AArch64-only instruction that may be used from higher privilege levels. No condition flags are affected.

address ← Xn + SignExtend(imm9); [address] ← Wt; access performed at EL0 privilege level


Summary: Stores a byte as if in EL0.

Stores a byte from Wt to memory at [Xn + simm] with unprivileged semantics, as if the access were made from EL0. This is an AArch64-only instruction that may be used from higher privilege levels. No condition flags are affected.

address ← Xn + SignExtend(imm9); [address] ← Wt<7:0>; access performed at EL0 privilege level


Summary: Stores a halfword as if in EL0.

Stores a halfword from Wt to memory at [Xn + simm] with unprivileged semantics, as if the access were made from EL0. This is an AArch64-only instruction that may be used from higher privilege levels. No condition flags are affected.

address ← Xn + SignExtend(imm9); [address] ← Wt<15:0>; access performed at EL0 privilege level


Summary: Stores a register using an unscaled immediate offset.

Stores a 32-bit word from register Wt to memory at address Xn+simm using an unscaled immediate offset. No condition flags are affected. AArch64-only instruction that may generate an alignment fault or translation fault exception if the address is invalid or unaligned.

address ← Xn + SignExtend(imm9, 64)
[address, 4] ← Wt[31:0]


Summary: Stores a byte using an unscaled immediate offset.

Stores a single byte from the least-significant byte of register Wt to memory at address Xn+simm using an unscaled immediate offset. No condition flags are affected. AArch64-only instruction that may generate a translation fault exception if the address is invalid.

address ← Xn + SignExtend(imm9, 64)
[address, 1] ← Wt[7:0]


Summary: Stores a halfword using an unscaled immediate offset.

Stores a halfword (16 bits) from the least-significant halfword of register Wt to memory at address Xn+simm using an unscaled immediate offset. No condition flags are affected. AArch64-only instruction that may generate an alignment fault or translation fault exception if the address is invalid or unaligned.

address ← Xn + SignExtend(imm9, 64)
[address, 2] ← Wt[15:0]


Summary: Stores a word if exclusive monitor matches.

Conditionally stores a 32-bit word from Wt to memory at address Xn if the exclusive monitor for that address is marked exclusive; writes the store status (0=success, 1=failure) to Ws. No condition flags are affected. AArch64-only instruction that interacts with the exclusive monitor and may generate exception faults.

address ← Xn
if ExclusiveMonitorMatch(address, WORD) then
  [address, 4] ← Wt[31:0]
  Ws ← 0
  ClearExclusiveMonitor(address)
else
  Ws ← 1


Summary: Stores a byte if exclusive monitor matches.

Conditionally stores a single byte from Wt to memory at address Xn if the exclusive monitor for that address is marked exclusive; writes the store status (0=success, 1=failure) to Ws. No condition flags are affected. AArch64-only instruction that interacts with the exclusive monitor and may generate exception faults.

address ← Xn
if ExclusiveMonitorMatch(address, BYTE) then
  [address, 1] ← Wt[7:0]
  Ws ← 0
  ClearExclusiveMonitor(address)
else
  Ws ← 1


Summary: Stores a halfword if exclusive monitor matches.

Conditionally stores a halfword (16 bits) from Wt to memory at address Xn if the exclusive monitor for that address is marked exclusive; writes the store status (0=success, 1=failure) to Ws. No condition flags are affected. AArch64-only instruction that interacts with the exclusive monitor and may generate exception faults.

address ← Xn
if ExclusiveMonitorMatch(address, HALFWORD) then
  [address, 2] ← Wt[15:0]
  Ws ← 0
  ClearExclusiveMonitor(address)
else
  Ws ← 1