Summary: Dual multiply subtract + accumulate.

Multiplies two pairs of signed 16-bit values, subtracts the products, then adds accumulator Ra: (Rn[31:16] × Rm[31:16]) - (Rn[15:0] × Rm[15:0]) + Ra, storing the 32-bit signed result in Rd. The {X} variant swaps operands of one multiply. Does not update condition flags. A32 DSP extension only.

if X then
  prod1 ← SignExtend(Rn[31:16], 32) × SignExtend(Rm[15:0], 32)
  prod2 ← SignExtend(Rn[15:0], 32) × SignExtend(Rm[31:16], 32)
else
  prod1 ← SignExtend(Rn[31:16], 32) × SignExtend(Rm[31:16], 32)
  prod2 ← SignExtend(Rn[15:0], 32) × SignExtend(Rm[15:0], 32)
Rd ← prod1 - prod2 + Ra


Summary: Dual multiply add + 64-bit accumulate.

Rn

First source / base general-purpose register

Rm

Second source / offset general-purpose register

Multiplies two pairs of signed 16-bit values and adds the products to a 64-bit accumulator: (Rn[31:16] × Rm[31:16]) + (Rn[15:0] × Rm[15:0]) + (RdHi:RdLo), storing the 64-bit signed result in RdHi:RdLo. The {X} variant swaps operands of one multiply. Does not update condition flags. A32 DSP extension only.

if X then
  prod1 ← SignExtend(Rn[31:16], 64) × SignExtend(Rm[15:0], 64)
  prod2 ← SignExtend(Rn[15:0], 64) × SignExtend(Rm[31:16], 64)
else
  prod1 ← SignExtend(Rn[31:16], 64) × SignExtend(Rm[31:16], 64)
  prod2 ← SignExtend(Rn[15:0], 64) × SignExtend(Rm[15:0], 64)
accum ← (RdHi << 32) | RdLo
result ← prod1 + prod2 + accum
RdHi ← result[63:32]
RdLo ← result[31:0]


Summary: Dual multiply subtract + 64-bit accumulate.

Multiplies two pairs of signed 16-bit values, subtracts the products, and adds to a 64-bit accumulator: (Rn[31:16] × Rm[31:16]) - (Rn[15:0] × Rm[15:0]) + (RdHi:RdLo), storing the 64-bit signed result in RdHi:RdLo. The {X} variant swaps operands of one multiply. Does not update condition flags. A32 DSP extension only.

if X then
  prod1 ← SignExtend(Rn[31:16], 64) × SignExtend(Rm[15:0], 64)
  prod2 ← SignExtend(Rn[15:0], 64) × SignExtend(Rm[31:16], 64)
else
  prod1 ← SignExtend(Rn[31:16], 64) × SignExtend(Rm[31:16], 64)
  prod2 ← SignExtend(Rn[15:0], 64) × SignExtend(Rm[15:0], 64)
accum ← (RdHi << 32) | RdLo
result ← prod1 - prod2 + accum
RdHi ← result[63:32]
RdLo ← result[31:0]


Summary: Parallel saturating add of 4 signed bytes.

Performs four parallel saturating additions on signed bytes: each byte of Rn is added to the corresponding byte of Rm with signed saturation, and the four 8-bit saturated results are packed into Rd. The GE[3:0] condition flags are updated to indicate which byte operations did not saturate. A32 DSP extension only.

for i = 0 to 3
  byte_index ← i × 8
  a ← SignExtend(Rn[byte_index + 7 : byte_index], 9)
  b ← SignExtend(Rm[byte_index + 7 : byte_index], 9)
  sum ← a + b
  if sum > 127 then
    result_byte ← 127
    GE[i] ← 0
  elsif sum < -128 then
    result_byte ← -128
    GE[i] ← 0
  else
    result_byte ← sum[7:0]
    GE[i] ← 1
  Rd[byte_index + 7 : byte_index] ← result_byte


Summary: Parallel saturating add of 2 signed halfwords.

Performs parallel saturating addition of two signed 16-bit halfwords in Rn and Rm, storing results in Rd. Each halfword is independently saturated to the signed 16-bit range [-32768, 32767] if overflow occurs. No condition flags are affected. Execution restricted to A32 with DSP extension; requires ARMv6 or later.


Summary: Parallel saturating subtract of 4 signed bytes.

Performs parallel saturating subtraction of four signed 8-bit bytes in Rm from Rn, storing results in Rd. Each byte is independently saturated to the signed 8-bit range [-128, 127] if underflow occurs. No condition flags are affected. Execution restricted to A32 with DSP extension; requires ARMv6 or later.


Summary: Parallel saturating subtract of 2 signed halfwords.

Performs parallel saturating subtraction of two signed 16-bit halfwords in Rm from Rn, storing results in Rd. Each halfword is independently saturated to the signed 16-bit range [-32768, 32767] if underflow occurs. No condition flags are affected. Execution restricted to A32 with DSP extension; requires ARMv6 or later.


Summary: Signed add and halving (average) of 4 bytes.

Performs parallel addition of four signed 8-bit bytes from Rn and Rm, then arithmetically shifts each result right by 1 bit (halving), storing in Rd. No saturation occurs; results are always in the range [-128, 127]. No condition flags are affected. Execution restricted to A32 with DSP extension; requires ARMv6 or later.


Summary: Signed add and halving (average) of 2 halfwords.

Performs parallel addition of two signed 16-bit halfwords from Rn and Rm, then arithmetically shifts each result right by 1 bit (halving), storing in Rd. No saturation occurs; results are always in the range [-32768, 32767]. No condition flags are affected. Execution restricted to A32 with DSP extension; requires ARMv6 or later.


Summary: Signed subtract and halving of 4 bytes.

Performs parallel subtraction of four signed 8-bit bytes in Rm from Rn, then arithmetically shifts each result right by 1 bit (halving), storing in Rd. No saturation occurs; results are always in the range [-128, 127]. No condition flags are affected. Execution restricted to A32 with DSP extension; requires ARMv6 or later.


Summary: Signed subtract and halving of 2 halfwords.

Performs parallel subtraction of two signed 16-bit halfwords in Rm from Rn, then arithmetically shifts each result right by 1 bit (halving), storing in Rd. No saturation occurs; results are always in the range [-32768, 32767]. No condition flags are affected. Execution restricted to A32 with DSP extension; requires ARMv6 or later.


Summary: Unsigned saturating add of 4 bytes.

Performs parallel saturating addition of four unsigned 8-bit bytes from Rn and Rm, storing results in Rd. Each byte is independently saturated to the unsigned 8-bit range [0, 255] if overflow occurs. No condition flags are affected. Execution restricted to A32 with DSP extension; requires ARMv6 or later.


Summary: Unsigned saturating add of 2 halfwords.

Performs unsigned saturating addition of two 16-bit halfwords in parallel. Each halfword of Rn is added to the corresponding halfword of Rm; if the result exceeds the unsigned 16-bit range (0-65535), it saturates to 65535. No condition flags are affected; saturation status is not recorded.

half1_rn ← Rn[15:0]; half2_rn ← Rn[31:16]
half1_rm ← Rm[15:0]; half2_rm ← Rm[31:16]
sum1 ← half1_rn + half1_rm; sum2 ← half2_rn + half2_rm
Rd[15:0] ← (sum1 > 0xFFFF) ? 0xFFFF : sum1
Rd[31:16] ← (sum2 > 0xFFFF) ? 0xFFFF : sum2


Summary: Unsigned saturating subtract of 4 bytes.

Performs unsigned saturating subtraction of four 8-bit bytes in parallel. Each byte of Rm is subtracted from the corresponding byte of Rn; if the result would be negative, it saturates to 0. No condition flags are affected; saturation status is not recorded.

for i = 0 to 3 do
  byte_rn ← Rn[8*i+7:8*i]; byte_rm ← Rm[8*i+7:8*i]
  diff ← byte_rn - byte_rm
  Rd[8*i+7:8*i] ← (diff < 0) ? 0 : diff


Summary: Unsigned saturating subtract of 2 halfwords.

Performs unsigned saturating subtraction of two 16-bit halfwords in parallel. Each halfword of Rm is subtracted from the corresponding halfword of Rn; if the result would be negative, it saturates to 0. No condition flags are affected; saturation status is not recorded.

half1_rn ← Rn[15:0]; half2_rn ← Rn[31:16]
half1_rm ← Rm[15:0]; half2_rm ← Rm[31:16]
diff1 ← half1_rn - half1_rm; diff2 ← half2_rn - half2_rm
Rd[15:0] ← (diff1 < 0) ? 0 : diff1
Rd[31:16] ← (diff2 < 0) ? 0 : diff2


Summary: Unsigned average of 4 bytes.

Performs unsigned halving addition of four 8-bit bytes in parallel, effectively computing the average. Each byte of Rn is added to the corresponding byte of Rm and the result is divided by 2 (rounded down). No condition flags are affected.

for i = 0 to 3 do
  byte_rn ← Rn[8*i+7:8*i]; byte_rm ← Rm[8*i+7:8*i]
  sum ← byte_rn + byte_rm
  Rd[8*i+7:8*i] ← sum >> 1


Summary: Unsigned average of 2 halfwords.

Performs unsigned halving addition of two 16-bit halfwords in parallel, computing the average of each pair. Each halfword of Rn is added to the corresponding halfword of Rm and the result is divided by 2 (rounded down). No condition flags are affected.

half1_rn ← Rn[15:0]; half2_rn ← Rn[31:16]
half1_rm ← Rm[15:0]; half2_rm ← Rm[31:16]
sum1 ← half1_rn + half1_rm; sum2 ← half2_rn + half2_rm
Rd[15:0] ← sum1 >> 1
Rd[31:16] ← sum2 >> 1


Summary: Unsigned halving subtract of 4 bytes.

Performs unsigned halving subtraction of four 8-bit bytes in parallel. Each byte of Rm is subtracted from the corresponding byte of Rn and the result is divided by 2 (rounded down). No condition flags are affected.

for i = 0 to 3 do
  byte_rn ← Rn[8*i+7:8*i]; byte_rm ← Rm[8*i+7:8*i]
  diff ← byte_rn - byte_rm
  Rd[8*i+7:8*i] ← diff >> 1


Summary: Unsigned halving subtract of 2 halfwords.

Performs unsigned halving subtraction of two 16-bit halfwords in parallel. Each halfword of Rm is subtracted from the corresponding halfword of Rn and the result is divided by 2 (rounded down). No condition flags are affected.

half1_rn ← Rn[15:0]; half2_rn ← Rn[31:16]
half1_rm ← Rm[15:0]; half2_rm ← Rm[31:16]
diff1 ← half1_rn - half1_rm; diff2 ← half2_rn - half2_rm
Rd[15:0] ← diff1 >> 1
Rd[31:16] ← diff2 >> 1


Summary: Selects bytes from Rn or Rm based on GE flags.

Selects bytes from Rn or Rm based on the GE (Greater-than-or-Equal) condition flags, placing the selected bytes into Rd. For each byte position i, if GE[i] is set, the byte from Rn[8*i+7:8*i] is selected; otherwise, the byte from Rm[8*i+7:8*i] is selected. Condition flags are not affected by this instruction.


Summary: Signals the memory system to prefetch data into cache.

Prefetch Memory (Immediate) signals the memory system to prefetch data from an address calculated by adding a scaled 12-bit immediate offset to a base register. This is a hint instruction that does not architecturally affect register state or condition flags. Execution is AArch64-only and no exceptions are generated for invalid addresses.

address ← Xn|SP + (imm12 << 3); Prefetch(address, prfop);


Summary: Prefetches data from a PC-relative address.

Prefetch Memory (Literal) signals the memory system to prefetch data from a PC-relative address. The address is calculated by adding a signed 19-bit offset (scaled by 4) to the PC. This is a hint instruction that does not architecturally affect register state or condition flags. Execution is AArch64-only.

address ← PC + (imm19 << 2); Prefetch(address, prfop);


Summary: Prefetches data using a register offset.

PRFM <prfop>, [<Xn|SP>, <R><m> {, <extend> <amount>}]

Xn

First source / base 64-bit integer register

Prefetch Memory (Register) signals the memory system to prefetch data from an address calculated by adding an optionally shifted register offset to a base register. The shift amount and extension type are encoded in the option and S bits. This is a hint instruction that does not affect register state or condition flags. Execution is AArch64-only.

offset ← ExtendValue(Rm, option, S); address ← Xn|SP + offset; Prefetch(address, prfop);


Summary: Loads a 64-byte block of data atomically (Accelerator support).

Single-copy Atomic 64-byte Load reads a 64-byte block of memory into 8 consecutive X-registers starting at Xt, with all 64 bytes loaded as a single atomic operation. The address must be 64-byte aligned; misalignment raises an Alignment Fault. Condition flags are not affected. Execution is AArch64-only and requires Accelerator support (FEAT_LS64).

address ← Xn|SP; if address<5:0> != 0 then Fault(Alignment); [Xt, Xt+1, ..., Xt+7] ← [address]; // 64 bytes loaded atomically


Summary: Stores a 64-byte block of data atomically.

Single-copy Atomic 64-byte Store writes a 64-byte block from 8 consecutive X-registers starting at Xt to memory as a single atomic operation. The address must be 64-byte aligned; misalignment raises an Alignment Fault. Condition flags are not affected. Execution is AArch64-only and requires Accelerator support (FEAT_LS64).

address ← Xn|SP; if address<5:0> != 0 then Fault(Alignment); [address] ← [Xt, Xt+1, ..., Xt+7]; // 64 bytes stored atomically


Summary: Stores 64 bytes atomically and returns status (Success/Fail).

Single-copy Atomic 64-byte Store with Return writes a 64-byte block from 8 consecutive X-registers starting at Xt to memory and returns a status value in Ws indicating success (0) or failure (non-zero). The store is atomic; on failure, memory is not modified and Ws is written with a non-zero value. Address must be 64-byte aligned. Condition flags are not affected. Execution is AArch64-only (FEAT_LS64).

address ← Xn|SP; if address<5:0> != 0 then Fault(Alignment); success ← AtomicStore64B(address, [Xt, Xt+1, ..., Xt+7]); Ws ← if success then 0 else implementation_defined_nonzero;


Summary: Stores 64 bytes (eliding the first 8 bytes as zero) and returns status.

Single-copy Atomic 64-byte Store with Return (Zero) writes a 64-byte block to memory, treating the first 8 bytes as zero, and returns status in Ws. Xt, Xt+2, …, Xt+7 provide bytes 8-63; bytes 0-7 are zeroed. The store is atomic; on failure, Ws is non-zero and memory is unchanged. Address must be 64-byte aligned. Condition flags are not affected. Execution is AArch64-only (FEAT_LS64).

address ← Xn|SP; if address<5:0> != 0 then Fault(Alignment); data<63:0> ← 0; data<511:64> ← [Xt+1, Xt+2, ..., Xt+7]<447:0>; success ← AtomicStore64B(address, data); Ws ← if success then 0 else implementation_defined_nonzero;


Summary: Hints that multiple memory accesses should be merged.

Data Gathering Hint is a system hint instruction that suggests to the processor that multiple small memory accesses should be merged or optimized. It provides a hint to the memory system and does not cause side effects visible to software. This is an AArch64-only instruction; it is NOP-like and has no effect on condition flags or general registers.

// Hints that multiple memory accesses should be merged


Summary: Prevents speculative execution across the barrier.

Speculation Barrier. Prevents speculative execution from proceeding past this instruction. Acts as a full serializing barrier for speculative load operations; no younger instruction can execute until all older instructions have completed. Does not affect condition flags. AArch64-only; no privilege requirement.


Summary: Ensures trace generation is complete.

Trace Synchronization Barrier with CSYNC variant. Ensures that all trace generation for instructions prior to this barrier is complete before resuming. Provides a synchronization point for trace capture mechanisms. Does not affect condition flags. AArch64-only; requires trace generation support.


Summary: Prevents speculative data consumption.

Consumption of Speculative Data Barrier. Prevents speculative consumption of data values (e.g., use of speculatively loaded values in address calculations or control flow). Acts as a lighter-weight barrier than SB, constraining only data-dependent speculation. Does not affect condition flags. AArch64-only.


Summary: Waits for an event or a timeout (using a counter).

Wait For Event with Timeout. Suspends execution until an event is signaled or the timeout counter expires. The timeout value is provided in Wn as a 32-bit count value. Condition flags are not affected. AArch64-only; available from v8.7 onwards.

timeout ← Wn
while (timeout > 0 AND event_not_signaled()) {
  timeout ← timeout - 1
  enter_low_power_state()
}
Wn ← timeout


Summary: Waits for an interrupt or a timeout.

Wait For Interrupt with Timeout. Suspends execution until an interrupt is pending or the timeout counter expires. The timeout value is provided in Wn as a 32-bit count. Condition flags are not affected. AArch64-only; available from v8.7 onwards.

timeout ← Wn
while (timeout > 0 AND interrupt_not_pending()) {
  timeout ← timeout - 1
  enter_low_power_state()
}
Wn ← timeout


Summary: Branch if condition is met, with stronger ordering guarantees.

Branch Consistent Conditional. Performs a PC-relative conditional branch with stronger ordering guarantees (Branch Consistent semantics). If the condition is true, branches to the target label with full consistency; branch prediction is constrained to prevent speculation-based reordering. Condition flags are not modified by the branch itself. AArch64-only; available from v8.8 onwards.

if (ConditionHolds(cond)) {
  PC ← PC + SignExtend(imm19 << 2)
  ConsistencyBarrier()
}


Summary: Loads a byte with Release Consistency (process consistent) Acquire semantics.

Wt

Transfer 32-bit integer register (load/store)

Load-Acquire RCpc Register Byte. Loads an unsigned byte from memory with RCpc (Release Consistent process-consistent) Acquire semantics. Provides a one-way barrier: subsequent memory operations cannot be reordered before this load, but prior stores may be reordered after. The zero-extended byte is written to Wt. Condition flags are not affected. AArch64-only.

address ← Xn
data ← ZeroExtend([address], 8)
Wt ← data
AcquireBarrier(RCpc)


Summary: Loads a halfword with RCpc Acquire semantics.

Load-Acquire RCpc Register Halfword. Loads an unsigned halfword from memory with RCpc (Release Consistent process-consistent) Acquire semantics. Provides a one-way barrier: subsequent memory operations cannot be reordered before this load. The zero-extended halfword is written to Wt. Condition flags are not affected. AArch64-only.

address ← Xn
data ← ZeroExtend([address], 16)
Wt ← data
AcquireBarrier(RCpc)


Summary: Loads a word with RCpc Acquire semantics.

Loads a 32-bit word from memory into Wt with RCpc (Acquire) semantics, providing a weaker form of acquire synchronization that does not order prior memory operations against this load. The instruction does not modify the condition flags (N, Z, C, V remain unchanged). This AArch64-only instruction is available in the RCpc extension and requires natural 4-byte alignment of the memory address.

Wt ← [Xn]; // Load with RCpc acquire semantics; address alignment: 4 bytes


Summary: Prevents speculation on physical resources.

Issues a Physical Speculation Barrier to prevent speculation through the barrier on physical resources, typically used to mitigate certain transient execution side-channel attacks. This AArch64-only hint instruction does not modify any condition flags and has no visible register side effects; it may be a no-op on some implementations but carries architectural implications for speculation control. Introduced in ARMv8.5-A.

SpeculationBarrier(); // Physical speculation barrier; execution continues normally


Summary: Generates a trace packet.

Generates a trace instrumentation packet containing the value from Xt, allowing software to inject trace data into the trace stream for debugging and profiling. This AArch64-only instruction is part of the Trace extension and does not modify condition flags; the actual trace output is system-dependent and not architecturally specified. Requires appropriate trace system configuration and permissions.

TracedData ← Xt; // Inject Xt value into trace instrumentation stream


Summary: Loads two-element structures from memory into two registers (De-interleave).

Loads two consecutive 2-element SIMD structures from memory, de-interleaving them into two registers (Vt1 and Vt2). The element type T and Q field determine whether 64-bit (Q=0, per-register) or 128-bit (Q=1) structures are loaded; the base address in Xn is post-incremented by the number of bytes loaded. This AArch64 NEON instruction does not modify condition flags.

elements_per_struct ← 2; element_size ← GetElementSize(T); struct_bytes ← 2 * elements_per_struct * element_size; mem_addr ← Xn; (Vt1, Vt2) ← DeinterleaveLoad(mem_addr, struct_bytes, Q); Xn ← Xn + struct_bytes;


Summary: Stores two-element structures from two registers to memory (Interleave).

First transfer SIMD/FP register (load/store)

Second transfer SIMD/FP register (load/store)

Stores two SIMD registers to memory, interleaving their elements into two consecutive 2-element structures. The element type T and Q field determine the 64-bit (Q=0) or 128-bit (Q=1) store size per register; the base address in Xn is post-incremented by the total bytes stored. This AArch64 NEON instruction does not modify condition flags.

elements_per_struct ← 2; element_size ← GetElementSize(T); struct_bytes ← 2 * elements_per_struct * element_size; mem_addr ← Xn; InterleavedData ← InterleaveStore(Vt1, Vt2, Q); [mem_addr] ← InterleavedData; Xn ← Xn + struct_bytes;


Summary: Loads three-element structures (e.g., RGB) into three registers.

Loads three consecutive 3-element SIMD structures from memory, de-interleaving them into three registers (Vt1, Vt2, Vt3). The element type T and Q field control the 64-bit (Q=0) or 128-bit (Q=1) load size per register; the base address in Xn is post-incremented by the total bytes loaded. This AArch64 NEON instruction does not modify condition flags.

elements_per_struct ← 3; element_size ← GetElementSize(T); struct_bytes ← 3 * elements_per_struct * element_size; mem_addr ← Xn; (Vt1, Vt2, Vt3) ← DeinterleaveLoad(mem_addr, struct_bytes, Q); Xn ← Xn + struct_bytes;


Summary: Stores three-element structures from three registers (Interleave RGB).

Stores three SIMD registers to memory, interleaving their elements into three consecutive 3-element structures. The element type T and Q field control the 64-bit (Q=0) or 128-bit (Q=1) store size per register; the base address in Xn is post-incremented by the total bytes stored. This AArch64 NEON instruction does not modify condition flags.

elements_per_struct ← 3; element_size ← GetElementSize(T); struct_bytes ← 3 * elements_per_struct * element_size; mem_addr ← Xn; InterleavedData ← InterleaveStore(Vt1, Vt2, Vt3, Q); [mem_addr] ← InterleavedData; Xn ← Xn + struct_bytes;


Summary: Loads four-element structures (e.g., RGBA) into four registers.

Loads four consecutive 4-element SIMD structures from memory, de-interleaving them into four registers (Vt1, Vt2, Vt3, Vt4). The element type T and Q field determine the 64-bit (Q=0) or 128-bit (Q=1) load size per register; the base address in Xn is post-incremented by the total bytes loaded. This AArch64 NEON instruction does not modify condition flags.

elements_per_struct ← 4; element_size ← GetElementSize(T); struct_bytes ← 4 * elements_per_struct * element_size; mem_addr ← Xn; (Vt1, Vt2, Vt3, Vt4) ← DeinterleaveLoad(mem_addr, struct_bytes, Q); Xn ← Xn + struct_bytes;


Summary: Stores four-element structures from four registers (Interleave RGBA).

Stores four consecutive 4-element structures (e.g., RGBA pixels) from four NEON registers to memory with interleaved layout. The four registers (Vt1, Vt2, Vt3, Vt4) contain the elements to store; they are written as a block to the memory address in Xn|SP. The Q bit determines whether 64-bit (Q=0, 2 structures) or 128-bit (Q=1, 4 structures) operations are performed. No condition flags are affected; the instruction is AArch64 NEON-only.

address ← Xn|SP
element_size ← size_from_T
if Q == 1 then
  structures ← 4
else
  structures ← 2
for i = 0 to structures - 1 do
  mem[address + (i * element_size * 0)] ← Vt1[i]
  mem[address + (i * element_size * 1)] ← Vt2[i]
  mem[address + (i * element_size * 2)] ← Vt3[i]
  mem[address + (i * element_size * 3)] ← Vt4[i]
Xn|SP ← (post-index mode) ? Xn|SP + (4 * element_size * structures) : Xn|SP


Summary: Loads one element and replicates it to all lanes of the vector.

Vt

Transfer SIMD/FP vector register (load/store)

Loads a single element from memory and replicates it to all lanes of the destination NEON vector register. The element size is determined by the vector element type <T>. Q bit selects 64-bit (Q=0) or 128-bit (Q=1) vector. No condition flags are affected; the instruction is AArch64 NEON-only with no exception generation.

address ← Xn|SP
element_size ← size_from_T
element ← mem[address]
if Q == 1 then
  lanes ← 16 / element_size
else
  lanes ← 8 / element_size
for i = 0 to lanes - 1 do
  Vt[i] ← element
Xn|SP ← (post-index mode) ? Xn|SP + element_size : Xn|SP


Summary: Loads 2 elements and replicates them to all lanes.

Loads two consecutive elements from memory and replicates each to all corresponding lanes of two destination NEON vector registers. The two elements are interleaved in memory; Q bit selects 64-bit (Q=0, 1 pair) or 128-bit (Q=1, 2 pairs) operation. No condition flags are affected; the instruction is AArch64 NEON-only.

address ← Xn|SP
element_size ← size_from_T
element1 ← mem[address + 0 * element_size]
element2 ← mem[address + 1 * element_size]
if Q == 1 then
  lanes ← 16 / element_size
else
  lanes ← 8 / element_size
for i = 0 to lanes - 1 do
  Vt1[i] ← element1
  Vt2[i] ← element2
Xn|SP ← (post-index mode) ? Xn|SP + (2 * element_size) : Xn|SP


Summary: Moves an immediate value into every element of a vector.

Moves an 8-bit immediate value into every element of a NEON vector, with optional left shift by 0, 8, 16, or 24 bits. The immediate is replicated across all elements of the destination vector (64-bit or 128-bit depending on Q field). No condition flags are affected. This is an AArch64-only NEON instruction requiring SIMD support.

shift_amount ← cmode<1:0> * 8
if Q == 0 then
  Vd[63:0] ← replicate(imm8 << shift_amount, element_size)
else
  Vd[127:0] ← replicate(imm8 << shift_amount, element_size)
N ← unaffected; Z ← unaffected; C ← unaffected; V ← unaffected


Summary: Moves the inverse of an immediate value into every element.

Moves the bitwise NOT of an 8-bit immediate value into every element of a NEON vector, with optional left shift by 0, 8, 16, or 24 bits. The inverted immediate is replicated across all elements of the destination vector (64-bit or 128-bit depending on Q field). No condition flags are affected. This is an AArch64-only NEON instruction requiring SIMD support.

shift_amount ← cmode<1:0> * 8
inverted_imm ← ~(imm8 << shift_amount)
if Q == 0 then
  Vd[63:0] ← replicate(inverted_imm, element_size)
else
  Vd[127:0] ← replicate(inverted_imm, element_size)
N ← unaffected; Z ← unaffected; C ← unaffected; V ← unaffected


Summary: Extracts a vector from a pair of vectors (Sliding window).

Extracts a contiguous sequence of bytes from the concatenation of two NEON vectors (treated as a sliding window), producing a result vector. The extraction point is specified by the byte index operand. Q bit determines whether operation is on 64-bit (Q=0) or 128-bit (Q=1) vectors. No condition flags are affected; the instruction is AArch64 NEON-only.

concatenated ← (Vn || Vm)
byte_index ← index
if Q == 1 then
  result_bytes ← 16
else
  result_bytes ← 8
for i = 0 to result_bytes - 1 do
  Vd[i] ← concatenated[byte_index + i]
N ← unaffected; Z ← unaffected; C ← unaffected; V ← unaffected


Summary: Adds lower/upper halves of signed vectors, producing wider result (Widening).

Adds corresponding signed integer elements from the lower (or upper, depending on Q) halves of two narrow NEON vectors, producing a vector of wider elements. Q=0 operates on lower halves; Q=1 operates on upper halves. The result is placed in the wider destination vector. No condition flags are affected; the instruction is AArch64 NEON-only with signed saturation not applied (wrapping on overflow).

if Q == 0 then
  half ← "lower"
else
  half ← "upper"
for i = 0 to (length(Vd) / element_width(Td)) - 1 do
  Vn_element ← extract_half(Vn[i], half)
  Vm_element ← extract_half(Vm[i], half)
  Vd[i] ← signed_add(Vn_element, Vm_element)
N ← unaffected; Z ← unaffected; C ← unaffected; V ← unaffected


Summary: Adds lower/upper halves of unsigned vectors, producing wider result.

Adds corresponding unsigned integer elements from the lower (or upper, depending on Q) halves of two narrow NEON vectors, producing a vector of wider elements. Q=0 operates on lower halves; Q=1 operates on upper halves. The result is placed in the wider destination vector. No condition flags are affected; the instruction is AArch64 NEON-only with no saturation.

if Q == 0 then
  half ← "lower"
else
  half ← "upper"
for i = 0 to (length(Vd) / element_width(Td)) - 1 do
  Vn_element ← extract_half(Vn[i], half)
  Vm_element ← extract_half(Vm[i], half)
  Vd[i] ← unsigned_add(Vn_element, Vm_element)
N ← unaffected; Z ← unaffected; C ← unaffected; V ← unaffected


Summary: Adds a wide vector to the lower/upper half of a narrow vector.

Adds each element of a narrow signed vector to the corresponding element of a wide signed vector (which is already the destination width), producing a result stored in the wide destination vector. Q=0 operates on lower half of Vm; Q=1 operates on upper half. No condition flags are affected; the instruction is AArch64 NEON-only with wrapping on overflow.

if Q == 0 then
  half ← "lower"
else
  half ← "upper"
for i = 0 to (length(Vd) / element_width(Td)) - 1 do
  Vn_element ← Vn[i]
  Vm_element ← extract_half(Vm[i], half)
  Vd[i] ← signed_add(Vn_element, Vm_element)
N ← unaffected; Z ← unaffected; C ← unaffected; V ← unaffected


Summary: Adds a wide vector to the lower/upper half of a narrow vector (Unsigned).

Adds each element of a narrow unsigned vector to the corresponding element of a wide unsigned vector (already at destination width), producing a result stored in the wide destination vector. Q=0 operates on lower half of Vm; Q=1 operates on upper half. No condition flags are affected; the instruction is AArch64 NEON-only with wrapping on overflow.

if Q == 0 then
  half ← "lower"
else
  half ← "upper"
for i = 0 to (length(Vd) / element_width(Td)) - 1 do
  Vn_element ← Vn[i]
  Vm_element ← extract_half(Vm[i], half)
  Vd[i] ← unsigned_add(Vn_element, Vm_element)
N ← unaffected; Z ← unaffected; C ← unaffected; V ← unaffected


Summary: Subtracts signed narrow vectors, producing wider result.

Subtracts corresponding signed elements of two narrow SIMD vectors and places the results in a wider vector, sign-extending intermediate products. This is an AArch64-only NEON instruction that operates on integer element types (8, 16, or 32 bits) and produces results twice the width. Condition flags are not affected.

for i = 0 to (128 >> (size+1)) - 1 do
  op1 ← SignExtend(Vn[i], element_width)
  op2 ← SignExtend(Vm[i], element_width)
  Vd[i] ← op1 - op2
end for


Summary: Subtracts unsigned narrow vectors, producing wider result.

Subtracts corresponding unsigned elements of two narrow SIMD vectors and places the results in a wider vector, zero-extending intermediate products. This is an AArch64-only NEON instruction that operates on integer element types (8, 16, or 32 bits) and produces results twice the width. Condition flags are not affected.

for i = 0 to (128 >> (size+1)) - 1 do
  op1 ← ZeroExtend(Vn[i], element_width)
  op2 ← ZeroExtend(Vm[i], element_width)
  Vd[i] ← op1 - op2
end for


Summary: Performs polynomial multiplication over {0,1} producing wide result (Used for GCM).

Performs polynomial multiplication over GF(2) on pairs of narrow SIMD elements, producing wider polynomial results. This AArch64-only NEON instruction is primarily used for AES-GCM cryptographic operations and operates on 64-bit or 128-bit input vectors producing 128-bit or 256-bit results. Condition flags are not affected.

for i = 0 to (128 >> (size+1)) - 1 do
  result ← PolynomialMultiply(Vn[i], Vm[i])
  Vd[i] ← result
end for


Summary: Multiplies signed narrow vectors, producing wider result.

Multiplies corresponding signed elements of two narrow SIMD vectors and places the results in a wider vector, with sign-extension of operands. This is an AArch64-only NEON instruction that operates on integer element types (8, 16, or 32 bits) and produces results twice the width. Condition flags are not affected.

for i = 0 to (128 >> (size+1)) - 1 do
  op1 ← SignExtend(Vn[i], element_width)
  op2 ← SignExtend(Vm[i], element_width)
  Vd[i] ← op1 * op2
end for


Summary: Multiplies unsigned narrow vectors, producing wider result.

Multiplies corresponding unsigned elements of two narrow SIMD vectors and places the results in a wider vector, with zero-extension of operands. This is an AArch64-only NEON instruction that operates on integer element types (8, 16, or 32 bits) and produces results twice the width. Condition flags are not affected.

for i = 0 to (128 >> (size+1)) - 1 do
  op1 ← ZeroExtend(Vn[i], element_width)
  op2 ← ZeroExtend(Vm[i], element_width)
  Vd[i] ← op1 * op2
end for


Summary: Multiplies signed narrow vectors and adds to wide destination.

Multiplies corresponding signed elements of two narrow SIMD vectors and adds the widened products to the existing contents of a wider destination register. This is an AArch64-only NEON instruction that performs sign-extended multiplication followed by accumulation on integer element types (8, 16, or 32 bits). Condition flags are not affected.

for i = 0 to (128 >> (size+1)) - 1 do
  op1 ← SignExtend(Vn[i], element_width)
  op2 ← SignExtend(Vm[i], element_width)
  Vd[i] ← Vd[i] + (op1 * op2)
end for


Summary: Multiplies unsigned narrow vectors and adds to wide destination.

Multiplies corresponding unsigned elements of two narrow SIMD vectors and adds the widened products to the existing contents of a wider destination register. This is an AArch64-only NEON instruction that performs zero-extended multiplication followed by accumulation on integer element types (8, 16, or 32 bits). Condition flags are not affected.

for i = 0 to (128 >> (size+1)) - 1 do
  op1 ← ZeroExtend(Vn[i], element_width)
  op2 ← ZeroExtend(Vm[i], element_width)
  Vd[i] ← Vd[i] + (op1 * op2)
end for


Summary: Shifts narrow vector left, extending to wide result.

Shifts narrow SIMD vector elements left by an immediate amount and zero-extends them to twice the width, placing the results in a wider destination register. This is an AArch64-only NEON instruction that operates on 8, 16, or 32-bit integer elements and produces 16, 32, or 64-bit results respectively. Condition flags are not affected.

for i = 0 to (128 >> (size+1)) - 1 do
  operand ← ZeroExtend(Vn[i], element_width)
  Vd[i] ← operand << imm
end for


Summary: Shifts wide vector right, narrowing to destination (Upper/Lower).

Shifts each element of a wide vector right by an immediate amount, narrows the result to half the width, and stores in the destination register. The Q bit selects whether the operation produces the lower (Q=0) or upper (Q=1) half of the result. No flags are modified by this instruction. This is an AArch64 NEON instruction only.

for i = 0 to elements-1 do
  temp ← Vn[i] >> shift
  Vd[i] ← temp[element_width_dest-1:0]
endfor


Summary: Reads wide elements, saturates, and narrows.

Extracts each signed element from a wide source vector, saturates to the range of the narrower destination type, and stores the result. Sets the FPSR.QC flag if saturation occurs. This is an AArch64 NEON instruction; no general-purpose flags are modified.

for i = 0 to elements-1 do
  temp ← Vn[i]
  if temp > max_value_dest or temp < min_value_dest then
    Vd[i] ← Saturate(temp)
    FPSR.QC ← 1
  else
    Vd[i] ← temp
  endif
endfor


Summary: Reads wide unsigned elements, saturates, and narrows.

Extracts each unsigned element from a wide source vector, saturates to the range of the narrower unsigned destination type, and stores the result. Sets the FPSR.QC flag if saturation occurs. This is an AArch64 NEON instruction; no general-purpose flags are modified.

for i = 0 to elements-1 do
  temp ← Vn[i]
  if temp > max_value_dest then
    Vd[i] ← max_value_dest
    FPSR.QC ← 1
  else
    Vd[i] ← temp
  endif
endfor


Summary: Arithmetic right shift and add to destination.

Performs an arithmetic (sign-extending) right shift on each source element, then accumulates (adds) the shifted result into the corresponding destination element. No condition flags are modified. This is an AArch64 NEON instruction.

for i = 0 to elements-1 do
  shifted ← Vn[i] >> shift  (arithmetic shift)
  Vd[i] ← Vd[i] + shifted
endfor


Summary: Logical right shift and add to destination.

Performs a logical (zero-extending) right shift on each source element, then accumulates (adds) the shifted result into the corresponding destination element. No condition flags are modified. This is an AArch64 NEON instruction.

for i = 0 to elements-1 do
  shifted ← Vn[i] >> shift  (logical shift)
  Vd[i] ← Vd[i] + shifted
endfor


Summary: Shifts source right and inserts into destination.

Shifts each source element right by an immediate amount and inserts the result into the corresponding destination element, preserving the upper bits of the destination. No condition flags are modified. This is an AArch64 NEON instruction.

for i = 0 to elements-1 do
  shifted ← Vn[i] >> shift
  Vd[i] ← (Vd[i] & ~mask) | (shifted & mask)
endfor
where mask selects the lower (element_width - shift) bits


Summary: Shifts source left and inserts into destination.

Shifts each source element left by an immediate amount and inserts the result into the corresponding destination element, preserving the lower bits of the destination. No condition flags are modified. This is an AArch64 NEON instruction.

for i = 0 to elements-1 do
  shifted ← Vn[i] << shift
  Vd[i] ← (Vd[i] & mask) | (shifted & ~mask)
endfor
where mask selects the lower shift bits


Summary: Counts leading zeros for each element.

Counts the number of leading zero bits in each element of the source vector and stores the count in the corresponding destination element. No condition flags are modified. This is an AArch64 NEON instruction.

for i = 0 to elements-1 do
  Vd[i] ← CountLeadingZeros(Vn[i])
endfor


Summary: Counts set bits (population count) per byte.

Counts the number of set bits (population count) in each byte element of the source vector and places the result in the corresponding byte of the destination vector. This is a per-byte operation with no flag effects. The instruction is available in AArch64 NEON and operates on both 64-bit (Q=0) and 128-bit (Q=1) vectors.

for i = 0 to elements_in_vector - 1:
  Vd[i] ← PopulationCount(Vn[i])


Summary: Inverts all bits. (Alias for MVN).

Performs a bitwise NOT operation (one's complement) on each bit of the source vector, placing the inverted result in the destination vector. This instruction is an alias for MVN in NEON and operates on all vector element sizes. No condition flags are affected. Available in AArch64 NEON for both 64-bit and 128-bit vectors.

for i = 0 to bits_in_vector - 1:
  Vd[i] ← NOT Vn[i]


Summary: Estimates reciprocal for unsigned integers.

Computes an unsigned reciprocal estimate (1/x approximation) for each 32-bit element in the source vector and stores the result in the destination vector. The result is a 32-bit unsigned integer approximation with reduced precision, suitable as a starting point for Newton-Raphson refinement. No condition flags are affected. Available in AArch64 NEON operating on 32-bit integer elements only.

if size == 0b10 then
  for i = 0 to elements_in_vector - 1:
    Vd[i] ← UnsignedReciprocalEstimate(Vn[i])


Vector Floating-Point Reciprocal Estimate

Summary: Estimates reciprocal (1/x) for floats.

Computes a floating-point reciprocal estimate (1/x approximation) for each element in the source vector and stores the result in the destination vector. Operates on 32-bit (sz=0) or 64-bit (sz=1) floating-point elements. The result is reduced-precision and intended for refinement via Newton-Raphson steps. No condition flags are affected. Available in AArch64 NEON.

if sz == 0 then
  for i = 0 to elements_in_vector - 1:
    Vd[i] ← FloatReciprocalEstimate(Vn[i])  // 32-bit float
else
  for i = 0 to elements_in_vector - 1:
    Vd[i] ← FloatReciprocalEstimate(Vn[i])  // 64-bit float


Summary: Newton-Raphson step for reciprocal refinement.

Computes the Newton-Raphson reciprocal refinement step 2.0 - (Vn × Vm) for each floating-point element, storing the result in the destination. Operates on 32-bit (sz=0) or 64-bit (sz=1) floating-point elements. This instruction is typically used iteratively with FRECPE to converge toward an accurate reciprocal. No condition flags are affected. Available in AArch64 NEON.

if sz == 0 then
  for i = 0 to elements_in_vector - 1:
    Vd[i] ← 2.0 - (Vn[i] * Vm[i])  // 32-bit float
else
  for i = 0 to elements_in_vector - 1:
    Vd[i] ← 2.0 - (Vn[i] * Vm[i])  // 64-bit float


Vector Floating-Point Reciprocal Sqrt Estimate

Summary: Estimates reciprocal square root (1/sqrt(x)).

Computes a floating-point reciprocal square root estimate (1/sqrt(x) approximation) for each element in the source vector and stores the result in the destination vector. Operates on 32-bit (sz=0) or 64-bit (sz=1) floating-point elements. The result is reduced-precision and intended for refinement via Newton-Raphson steps. No condition flags are affected. Available in AArch64 NEON.

if sz == 0 then
  for i = 0 to elements_in_vector - 1:
    Vd[i] ← ReciprocalSquareRootEstimate(Vn[i])  // 32-bit float
else
  for i = 0 to elements_in_vector - 1:
    Vd[i] ← ReciprocalSquareRootEstimate(Vn[i])  // 64-bit float


Vector Floating-Point Reciprocal Sqrt Step

Summary: Newton-Raphson step for reciprocal square root refinement.

Computes the Newton-Raphson reciprocal square root refinement step (3.0 - Vn × Vm) / 2.0 for each floating-point element, storing the result in the destination. Operates on 32-bit (sz=0) or 64-bit (sz=1) floating-point elements. This instruction is typically used iteratively with FRSQRTE to converge toward an accurate reciprocal square root. No condition flags are affected. Available in AArch64 NEON.

if sz == 0 then
  for i = 0 to elements_in_vector - 1:
    Vd[i] ← (3.0 - (Vn[i] * Vm[i])) / 2.0  // 32-bit float
else
  for i = 0 to elements_in_vector - 1:
    Vd[i] ← (3.0 - (Vn[i] * Vm[i])) / 2.0  // 64-bit float


Summary: Converts narrow floats to wide floats (e.g., Half -> Single).

Converts floating-point elements from a narrower format to a wider format (e.g., float16 to float32, or float32 to float64). The lower half (or upper half if Q=1) of the source vector is converted and stored in the destination vector. No condition flags are affected. Available in AArch64 NEON.

if sz == 0 then
  for i = 0 to elements_in_vector - 1:
    Vd[i] ← ConvertFloat16ToFloat32(Vn[i])  // Half to Single
else
  for i = 0 to elements_in_vector - 1:
    Vd[i] ← ConvertFloat32ToFloat64(Vn[i])  // Single to Double


Summary: Converts wide floats to narrow floats (e.g., Single -> Half).

Converts a vector of wider floating-point elements to a vector of narrower floating-point elements by rounding toward zero (e.g., float32 to float16). The result is placed in the lower half of the destination register; the upper half is zeroed if Q=0 (64-bit result) or unmodified if Q=1 (128-bit result, lower half updated). Executes in AArch64 with NEON support; condition flags are not affected.

for i = 0 to elements_in_narrower_type-1 do
  Vd[i] ← ConvertFloatingPointNarrow(Vn[i])
if Q == 0 then
  Vd[upper_half] ← 0


Vector Floating-Point Convert to Signed Integer

Summary: Converts floats to signed integers (Truncate).

Converts a vector of floating-point elements to a vector of signed integer elements by truncating toward zero, with optional fixed-point scaling (fbits). Executes in AArch64 with NEON support; condition flags are not affected. Overflow wraps to the minimum/maximum signed integer value for the element size.

for i = 0 to num_elements-1 do
  if fbits specified then
    scaled ← Vn[i] * 2^fbits
  else
    scaled ← Vn[i]
  Vd[i] ← ConvertToSignedInteger(scaled, rounding_mode=toward_zero)


Vector Floating-Point Convert to Unsigned Integer

Summary: Converts floats to unsigned integers (Truncate).

Converts a vector of floating-point elements to a vector of unsigned integer elements by truncating toward zero, with optional fixed-point scaling (fbits). Executes in AArch64 with NEON support; condition flags are not affected. Overflow wraps to zero or the maximum unsigned integer value for the element size.

for i = 0 to num_elements-1 do
  if fbits specified then
    scaled ← Vn[i] * 2^fbits
  else
    scaled ← Vn[i]
  Vd[i] ← ConvertToUnsignedInteger(scaled, rounding_mode=toward_zero)


Summary: Adds adjacent pairs of elements.

Adds adjacent pairs of elements across the two source vectors element-wise, placing results in the destination. For example, with 32-bit elements, pairs (Vn[1],Vn[0]) and (Vm[1],Vm[0]) sum to (Vd[1],Vd[0]). Executes in AArch64 with NEON support; condition flags are not affected. Overflow wraps modulo 2^(element_width).


Summary: Adds adjacent pairs of float elements.

Adds adjacent pairs of floating-point elements across the two source vectors, placing results in the destination. For example, with 32-bit floats, (Vn[0]+Vn[1]) and (Vm[0]+Vm[1]) are computed and stored. Executes in AArch64 with NEON support; condition flags are not affected. Addition follows IEEE 754 floating-point semantics.


Summary: Max of adjacent float elements.

Computes the floating-point maximum of adjacent pairs of elements across the two source vectors, placing results in the destination. For example, with 32-bit floats, max(Vn[0],Vn[1]) and max(Vm[0],Vm[1]) are stored. Executes in AArch64 with NEON support; condition flags are not affected. Comparison follows IEEE 754 semantics (NaN handling rules apply).

for i = 0 to num_pairs-1 do
  Vd[2*i] ← FMax(Vn[2*i], Vn[2*i+1])
  Vd[2*i+1] ← FMax(Vm[2*i], Vm[2*i+1])


Summary: Min of adjacent float elements.

Computes the floating-point minimum of adjacent pairs of elements across the two source vectors, placing results in the destination. For example, with 32-bit floats, min(Vn[0],Vn[1]) and min(Vm[0],Vm[1]) are stored. Executes in AArch64 with NEON support; condition flags are not affected. Comparison follows IEEE 754 semantics (NaN handling rules apply).

for i = 0 to num_pairs-1 do
  Vd[2*i] ← FMin(Vn[2*i], Vn[2*i+1])
  Vd[2*i+1] ← FMin(Vm[2*i], Vm[2*i+1])


Summary: Performs one round of AES encryption.

Performs a single round of AES (Advanced Encryption Standard) encryption on the 128-bit value in the source register using the key in Vn, producing the result in Vd. This implements the AES encryption state transformation (SubBytes, ShiftRows, MixColumns, AddRoundKey) for one round. Executes in AArch64 with Crypto extension; condition flags are not affected. This instruction is part of the AES cryptographic instruction set.


Summary: Performs one round of AES decryption.

Performs one round of AES decryption on a 128-bit vector. The instruction applies the AES InvShiftRows, InvSubBytes, and AddRoundKey transformations to the state in Vn using a round key in Vd, storing the result in Vd. This is an AArch64-only instruction requiring the Crypto extension. No condition flags are affected.

Vd ← AES_InvShiftRows(AES_InvSubBytes(Vn ⊕ Vd))


Summary: Performs AES Mix Columns transformation.

Performs the AES Mix Columns transformation on a 128-bit vector. The instruction applies the MixColumns operation to the bytes in Vn and stores the result in Vd. This is an AArch64-only instruction requiring the Crypto extension. No condition flags are affected.


Summary: Performs AES Inverse Mix Columns transformation.

Performs the AES Inverse Mix Columns transformation on a 128-bit vector. The instruction applies the InvMixColumns operation to the bytes in Vn and stores the result in Vd. This is an AArch64-only instruction requiring the Crypto extension. No condition flags are affected.


Summary: SHA1 hash update (Choose function).

Performs one round of SHA-1 hash computation using the Choose function. The instruction updates the SHA-1 state in Qd by processing the 32-bit hash value in Sn and 128-bit data from Vm. This is an AArch64-only instruction requiring the Crypto extension. No condition flags are affected.

T ← SHA1_Choose(Sn)
Qd ← SHA1_Update_C(Qd, T, Vm)


Summary: SHA1 hash update (Majority function).

Performs one round of SHA-1 hash computation using the Majority function. The instruction updates the SHA-1 state in Qd by processing the 32-bit hash value in Sn and 128-bit data from Vm. This is an AArch64-only instruction requiring the Crypto extension. No condition flags are affected.

T ← SHA1_Majority(Sn)
Qd ← SHA1_Update_M(Qd, T, Vm)


Summary: SHA1 hash update (Parity function).

Performs one round of SHA-1 hash computation using the Parity function. The instruction updates the SHA-1 state in Qd by processing the 32-bit hash value in Sn and 128-bit data from Vm. This is an AArch64-only instruction requiring the Crypto extension. No condition flags are affected.

T ← SHA1_Parity(Sn)
Qd ← SHA1_Update_P(Qd, T, Vm)


Summary: SHA256 hash update (part 1).

Performs the first part of one round of SHA-256 hash computation. The instruction updates the lower 96 bits of the SHA-256 state in Qd using the full state in Qn and 128-bit message schedule data from Vm. This is an AArch64-only instruction requiring the Crypto extension. No condition flags are affected.


Summary: SHA256 hash update (part 2).

Performs the second part of one round of SHA-256 hash computation. The instruction updates the upper 96 bits of the SHA-256 state in Qd using the partial state in Qn and 128-bit message schedule data from Vm. This is an AArch64-only instruction requiring the Crypto extension. No condition flags are affected.


Summary: Updates CRC32 checksum with a byte.

Updates a 32-bit CRC32 checksum by processing an 8-bit (byte) value from the data register. The instruction computes a new CRC32 polynomial remainder using the ISO 3309 polynomial and stores the result in the destination register. No condition flags are affected; this instruction requires the CRC extension and executes only in AArch64.


Summary: Updates CRC32 checksum with a word.

Updates a 32-bit CRC32 checksum by processing a 32-bit (word) value from the data register. The instruction computes the CRC32 polynomial remainder using the ISO 3309 polynomial and stores the result in the destination register. No condition flags are affected; this instruction requires the CRC extension and executes only in AArch64.


Summary: Updates CRC32 checksum with a doubleword (64-bit).

Updates a 32-bit CRC32 checksum by processing a 64-bit (doubleword) value from the data register. The instruction computes the CRC32 polynomial remainder using the ISO 3309 polynomial and stores the result in the destination 32-bit register. No condition flags are affected; this instruction requires the CRC extension and executes only in AArch64.


Summary: Updates CRC32C (Castagnoli) checksum with a byte.

Updates a 32-bit CRC32C (Castagnoli) checksum by processing an 8-bit (byte) value from the data register. The instruction computes the CRC32C polynomial remainder (iSCSI polynomial) and stores the result in the destination register. No condition flags are affected; this instruction requires the CRC extension and executes only in AArch64.


VSX Vector Integer 4-bit GER (Rank-8 Update)

Summary: Performs an accumulation of eight outer products (rank 8 update) using signed 4-bit integers from two vector scalar registers.

The instruction multiplies corresponding elements of the matrices X and Y, accumulates the results, and stores them in the accumulator ACC[AT]. The result is chopped to a 32-bit signed integer.

if MSR.VSX=0 then VSX_Unavailable()

PMSK ←0b11111111
XMSK ←0b1111
YMSK ←0b1111

do i = 0 to 3
do j = 0 to 3
   if XMSK.bit[i] & YMSK.bit[j] then do
      prod0 ←(PMSK.bit[0]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].nibble[0]) * EXTS(VSR[32×BX+B].word[j].nibble[0])
      prod1 ←(PMSK.bit[1]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].nibble[1]) * EXTS(VSR[32×BX+B].word[j].nibble[1])
      prod2 ←(PMSK.bit[2]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].nibble[2]) * EXTS(VSR[32×BX+B].word[j].nibble[2])
      prod3 ←(PMSK.bit[3]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].nibble[3]) * EXTS(VSR[32×BX+B].word[j].nibble[3])
      prod4 ←(PMSK.bit[4]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].nibble[4]) * EXTS(VSR[32×BX+B].word[j].nibble[4])
      prod5 ←(PMSK.bit[5]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].nibble[5]) * EXTS(VSR[32×BX+B].word[j].nibble[5])
      prod6 ←(PMSK.bit[6]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].nibble[6]) * EXTS(VSR[32×BX+B].word[j].nibble[6])
      prod7 ←(PMSK.bit[7]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].nibble[7]) * EXTS(VSR[32×BX+B].word[j].nibble[7])

      psum ←prod0 + prod1 + prod2 + prod3 + prod4 + prod5 + prod6 + prod7

      ACC[AT][i].word[j] ←CHOP32( psum )
   end
   else
      ACC[AT][i].word[j] ←0x0000_0000
end
end

Let X be the 8×4 matrix of 4-bit signed integer values contained in VSR[XA] in row-major format.
Let Y be the 8×4 matrix of 4-bit signed integer values contained in VSR[XB] in row-major format.
Let ACC[AT] be the Accumulator containing a 4×4 matrix of 32-bit signed-integer values.


VSX Vector Integer 4-bit GER (Rank-8 Update) Plus/Plus

Summary: Unsigned 4-bit integer matrix multiply accumulate.

Performs an unsigned 4-bit integer matrix multiplication with rank-8 accumulation, accumulating the result with plus-signed saturation. This MMA instruction multiplies 4-bit elements from two VSX registers and adds the partial products to an MMA accumulator, treating both input and output as unsigned values. The plus/plus variant saturates on overflow using unsigned saturation semantics.

This instruction is commonly used for matrix multiplication and accumulation operations on VSX registers with saturation handling. Ensure that the input matrices are correctly aligned and masked as per requirements. The instruction operates at a privilege level that allows access to FPSCR and XER, and it may raise exceptions if there are issues with operand alignment or access rights. Performance can be optimized by ensuring that the masks (XMSK and YMSK) are efficiently set to minimize unnecessary computations.


Prefixed Masked VSX Vector Integer 4-bit GER

Summary: Masked 4-bit integer matrix multiply.

1 | 3 | PMSK | XMSK | YMSK | 0 | 59 | AT | / | XA | XB | 3 | AX | BX | /

Performs a masked unsigned 4-bit integer matrix multiplication with rank-8 accumulation using separate row and column masks. This prefixed MMA instruction multiplies 4-bit elements from two VSX registers and adds the partial products to an MMA accumulator, with XMSK controlling which rows and YMSK controlling which columns participate. The result is treated as unsigned.

AT ← ACC[AT] + ((XA & XMSK) × (XB & YMSK))

The pmxvi4ger8 instruction is useful for performing masked vector integer operations, multiplying and accumulating products of signed integers from two vectors based on a mask. Ensure that the mask registers (XMSK, YMSK) are correctly set to control which elements are processed. The operation requires proper alignment of VSX registers, and results are clamped to 32-bit signed integers to prevent overflow. This instruction operates at privilege level 0.


Prefixed Masked VSX Vector Integer 4-bit GER Plus/Plus

Summary: Masked unsigned 4-bit integer matrix multiply.

Performs a masked unsigned 4-bit integer matrix multiplication with rank-8 accumulation and plus-signed saturation using separate row and column masks. This prefixed MMA instruction multiplies masked 4-bit elements from two VSX registers and accumulates the partial products into an MMA accumulator with unsigned saturation on overflow. XMSK controls row participation and YMSK controls column participation.

AT ← ACC[AT] + sat_u((XA & XMSK) × (XB & YMSK))

This instruction is useful for performing masked vectorized integer operations with saturation, ideal for applications requiring precise control over overflow conditions. Ensure that the mask registers (XMSK and YMSK) are correctly set to avoid unintended computations. The operation is performed at the user privilege level, but care must be taken to handle potential exceptions related to invalid register access or alignment issues. Performance may vary based on the specific data patterns and the effectiveness of the masking applied.


Summary: Initiates a hardware data stream prefetch (AltiVec Legacy).

Initiates a hardware prefetch stream for data that is likely to be loaded in the near future. The instruction computes an effective address from RA and RB and hints to the memory subsystem to begin streaming data into the cache with the temporal locality specified by STRM. This is an advisory instruction with no architectural side effects if the hardware does not support data streaming.

EA ← (RA | 0) + RB; InitiateDataStream(EA, STRM, isStore=0, isTransient=0)


Summary: Initiates a transient (non-temporal) data stream prefetch.

Initiates a hardware prefetch stream for transient (non-temporal) data that is likely to be loaded in the near future and not reused. The instruction computes an effective address from RA and RB and hints to the memory subsystem to begin streaming data with transient semantics specified by STRM. This is an advisory instruction that may reduce cache pollution for one-time accesses.

EA ← (RA | 0) + RB; InitiateDataStream(EA, STRM, isStore=0, isTransient=1)


Summary: Initiates a prefetch for writing.

Initiates a hardware prefetch stream for data that is likely to be written in the near future. The instruction computes an effective address from RA and RB and hints to the memory subsystem to begin preparing the cache line for write-back operations with the temporal locality specified by STRM. This is an advisory instruction supporting store-stream prefetching.

EA ← (RA | 0) + RB; InitiateDataStream(EA, STRM, isStore=1, isTransient=0)


Summary: Initiates a transient prefetch for writing.

Initiates a hardware prefetch stream for transient (non-temporal) data that is likely to be written in the near future and not reused. The instruction computes an effective address from RA and RB and hints to the memory subsystem to prepare the cache line for write operations with transient semantics. This advisory instruction supports transient store-stream prefetching to reduce cache pollution.

EA ← (RA | 0) + RB; InitiateDataStream(EA, STRM, isStore=1, isTransient=1)


Summary: Stops a data stream prefetch operation.

Stops the hardware prefetch stream identified by STRM. This instruction terminates data stream prefetching for a specific stream, allowing the hardware to cease streaming operations and free associated resources. It is an advisory instruction with no architectural side effects if data streaming is not supported.


Summary: Stops all active data stream prefetch operations.

Stops all active data stream prefetch operations initiated by DSS instructions. This is a privileged instruction that terminates data prefetching without affecting general processor state or condition registers. Used to optimize cache behavior by halting speculative data stream operations.

Use dssall to halt all data stream operations, preventing any further processing or transfer of data. This instruction is typically used in scenarios where you need to ensure complete cessation of data flow, such as during system shutdowns or critical error handling. Ensure that this instruction is executed at a privilege level sufficient to control data streams, and be aware that it may trigger exceptions if not properly managed.

All data stream prefetch operations are terminated.


Summary: Allocates a cache block without loading from memory (optimization for overwrite).

Allocates a cache block at the effective address (RA + RB) into the data cache without loading data from memory. This instruction is used as an optimization hint when the application will overwrite the entire cache block, avoiding unnecessary memory traffic. No condition registers or status fields are modified.

EA ← (RA) + (RB)
Allocate cache block at EA without loading from memory


Summary: Invalidates a cache block (Privileged).

Privileged. Invalidates a cache block without writeback. Use only when you know the block is clean or its contents can be discarded.

Invalidates the data cache block at effective address (RA + RB), removing it from the cache. This is a privileged instruction used for cache management. The instruction does not modify condition registers and may trigger cache coherency operations on multiprocessor systems.

EA ← (RA) + (RB)
Invalidate cache block at EA


Summary: Loads a word from an external device using the EAR register.

Loads a 32-bit word from an external control device into RT, using address formation from RA + RB and device selection from the External Address Register (EAR). This instruction requires special external interface hardware support and does not affect condition registers. It is typically used in embedded or specialized processor configurations.

EA ← (RA) + (RB)
RT ← ExternalLoad32(EA, EAR)


Summary: Stores a word to an external device using the EAR register.

Stores a 32-bit word from RS to an external control device, using address formation from RA + RB and device selection from the External Address Register (EAR). This instruction requires special external interface hardware support and does not affect condition registers. It is typically used in embedded or specialized processor configurations.

EA ← (RA) + (RB)
ExternalStore32(EA, EAR, (RS))


Summary: Moves a field from the Floating-Point Status and Control Register (FPSCR) to the Condition Register.

FPSCRf

Floating-Point Status and Control Register Field

CR[4*BF:4*BF+3] ← FPSCR[4*BFA:4*BFA+3]
FPSCR[4*BFA:4*BFA+3] ← 0

Moves a 4-bit field from the Floating-Point Status and Control Register (FPSCR) into a 4-bit field of the Condition Register (CR). The source field is specified by BFA and the destination field by BF. The corresponding FPSCR field is cleared after the move, and no other status fields are affected.

The mcrfs instruction is commonly used to transfer floating-point status and control information from the FPSCR to a general-purpose register. Ensure that the destination register (FRT) is properly aligned for optimal performance. This instruction operates at user privilege level, but accessing certain bits may require higher privileges depending on system configuration. Be cautious of potential exceptions if the FPSCR contains invalid or unexpected values.


Summary: Moves the contents of the Machine State Register (MSR) into a general-purpose register.

Moves the entire Machine State Register (MSR) into the general-purpose register RT. This is a privileged instruction that allows reading of system state including interrupt enable, privilege level, and other control bits. No condition registers or status fields are modified by this instruction.


Summary: Sets the Machine State Register (MSR) based on the contents of a source register and a control bit.

The MSR is set based on the contents of register RS and the L field. If L=0, specific bits are modified based on logical operations involving RS and the current state of the MSR. If L=1, only certain bits (48 and 62) from RS are placed into the corresponding bits of the MSR.

If this instruction sets MSRPR to 1, it also sets MSREE, MSRIR, and MSRDR to 1. If this instruction results in MSRS HV PR being equal to 0b110, it also sets MSRIR and MSRDR to 0. This instruction does not alter MSRS, MSRME, or MSRLE. If the only MSR bits to be altered are MSREE RI, to obtain the best performance L=1 should be used. mtmsr serves as both a basic and an extended mnemonic. The Assembler will recognize an mtmsr mnemonic with two operands as the basic form, and an mtmsr mnemonic with one operand as the extended form. In the extended form the L operand is omitted and assumed to be 0.


Move To Machine State Register Doubleword

Summary: Sets the Machine State Register (MSR) based on the contents of a source register and an L field.

The MSR is set based on the contents of register RS and the value of the L field. If L=0, specific bits are updated based on logical operations involving the contents of RS and the current state of the MSR. If L=1, only certain bits (48 and 62) from RS are placed into the corresponding bits of the MSR.

if L = 0 then
    MSR48 ← (RS)48 | (RS)49
    if MSRPR = 1 then
        MSREE, MSRIR, MSRDR ← 1
    if MSRS HV PR = 0b110 then
        MSRIR, MSRDR ← 0
else
    MSR48 62 ← (RS)48 62

If this instruction sets MSRPR to 1, it also sets MSREE, MSRIR, and MSRDR to 1. If this instruction results in MSRS HV PR being equal to 0b110, it also sets MSRIR and MSRDR to 0.

If the only MSR bits to be altered are MSREE RI, to obtain the best performance L=1 should be used.

mtmsrd serves as both a basic and an extended mnemonic. The Assembler will recognize an mtmsrd mnemonic with two operands as the basic form, and an mtmsrd mnemonic with one operand as the extended form. In the extended form the L operand is omitted and assumed to be 0.


Summary: Invalidates the entire Translation Lookaside Buffer.

Invalidates all entries in the Translation Lookaside Buffer (TLB), flushing all virtual-to-physical address translations. This is a privileged instruction used for memory management and typically follows changes to page tables. No condition registers are modified; the instruction may have latency on some implementations.


Summary: Provides an ordering function for the effects of all tlbie instructions executed by the thread executing the tlbsync instruction.

Provides a memory ordering function that ensures all tlbie instructions executed by the thread before this instruction have completed before any instruction after tlbsync begins execution. This is a privileged instruction used to synchronize TLB invalidation operations. No condition registers or status fields are affected; this is purely an ordering barrier for memory management operations.

tlbsync should not be used to synchronize the completion of tlbiel.

Synchronize effects of all preceding tlbie instructions


Summary: Provides a hint that describes a block or data stream to which the program may perform a store access.

Issues a cache hint indicating that a data block or stream will be accessed for storage (write). The instruction takes a hint field (TH) and an effective address (RA + RB) but does not load data into cache; it merely communicates intent to the cache hierarchy. No registers are modified and no condition codes are affected.

See the Programming Notes at the beginning of this section.

EA ← (RA) + (RB)
// Hint to cache management that block at EA will be stored to
// No actual load or register modification occurs


Summary: Provides a hint that the program will soon execute code from the block containing the byte addressed by EA, and that the block should be loaded into the cache specified by the CT field.

Issues a hint that the program will soon execute code from a block and requests that the block be preloaded into the instruction cache. The effective address is computed from RA + RB, and an optional cache-type field (CT, encoded in bits 21-25 of the instruction) specifies which cache level. This is a hint only and does not guarantee a load; no registers are modified.

EA ← (RA) + (RB)
// Hint to instruction cache that block at EA should be preloaded
// CT field (from instruction bits 21-25) specifies cache type
// No register modification

The hint is ignored if the block is Caching Inhibited. This instruction treated as a Load (see Section 4.3), except that the system data storage error handler is not invoked, and reference and change recording need not be done.


Summary: Reads the PVR (Processor ID).

Move From Processor Version Register. Extended mnemonic for MFSPR (mfspr RT,287). Copies the Processor Version Register (PVR) into register RT. The PVR contains the processor version and revision numbers.

The mfpvr instruction is used to retrieve the Processor Version Register (PVR), which contains information about the processor's version and revision. This instruction is commonly used for software that needs to detect or adapt to specific processor features or versions. It operates at user privilege level, so no special privileges are required. There are no alignment requirements for this instruction.


Summary: Moves the contents of the Time Base Register (TBR) into a general-purpose register.

This instruction behaves as if it were an mfspr instruction. The TBR operand is omitted and assumed to be 268 (the value that corresponds to TB).

This instruction behaves as if it were an mfspr instruction; see the mfspr instruction description in Section 3.3.19 of Book I.
New programs should use mfspr instead of mftb to access the Time Base.


Summary: Reads the upper 32 bits of the Timebase (32-bit implementations).

Reads the upper 32 bits of the Timebase register and places the value into the target GPR. This instruction is primarily used in 32-bit implementations to obtain the high word of the 64-bit Timebase. It does not modify condition registers or status fields.

RT ← TBU
// TBU is the upper 32 bits of the 64-bit Timebase counter

Use mftbu to capture the high-order bits of the timebase for timestamping or performance measurement. Ensure that your application accounts for potential discrepancies between the upper and lower 32-bit reads due to timebase overflow.


Summary: Loads a byte from memory into the low 8 bits of a register and clears the upper 56 bits.

if 'lbz' then
    EA ← (RA|0) + EXTS64(D)
    RT ← EXTZ(MEM(EA, 1))

The effective address (EA) is computed as the sum of the contents of register RA and the sign-extended immediate value D. The byte at EA is loaded into RT, with the upper 56 bits set to zero.

The lbz instruction is commonly used for loading a single byte from memory into a register while zeroing out the upper bits. Ensure that the address is properly aligned to avoid potential performance penalties or exceptions. This instruction operates at user privilege level and will raise an exception if the EA is outside the valid address space.


Summary: Loads a halfword (16 bits) from memory and clears the upper 48 bits.

if RA = 0 then
  EA ← sign_extend(D)
else
  EA ← (RA) + sign_extend(D)
RT ← (0 || [EA+1:EA])
// Load halfword at EA, zero-extend to 64 bits

Loads a 16-bit halfword from memory at address (RA + sign_extend(D)) and places it into RT with the upper 48 bits cleared to zero. The base register may be R0 if RA is zero in the instruction, in which case the displacement is used as an absolute address. No condition or status registers are affected.

The lhz instruction is commonly used for loading halfword values from memory into a register while ensuring the upper 16 bits are zeroed. Ensure that the effective address (EA) is properly aligned to avoid unaligned access exceptions. This instruction operates at user privilege level and will raise an exception if the EA is invalid or if there's a protection fault.


Summary: Loads a halfword (16 bits) from memory and sign-extends it to 64 bits.

if RA = 0 then
  EA ← sign_extend(D)
else
  EA ← (RA) + sign_extend(D)
RT ← sign_extend([EA+1:EA])
// Load halfword at EA and sign-extend to 64 bits

Loads a 16-bit halfword from memory at address (RA + sign_extend(D)) and places it into RT with sign extension to the full 64-bit width. The base register may be R0 if RA is zero in the instruction. No condition or status registers are affected.

The lha instruction is commonly used for loading signed halfword values from memory into a register, ensuring proper sign extension. Ensure that the effective address (EA) is properly aligned to avoid alignment faults. This instruction operates at user privilege level and will raise an exception if the EA is invalid or if there are insufficient privileges.


Summary: Loads a word (32 bits) from memory and clears the upper 32 bits.

EA ← (RA|0) + EXTS64(D)
RT ← 320 || MEM(EA, 4)

The effective address (EA) is calculated as (RA|0) + EXTS64(D). The word in storage addressed by EA is loaded into RT32:63. RT0:31 are set to 0.

The lwz instruction is commonly used for loading a word from memory into a register while zeroing the upper half of the target register. Ensure that the address is properly aligned to avoid alignment exceptions. This instruction operates at user privilege level and does not generate any exceptions under normal circumstances.


Summary: Loads a word (32 bits) from memory and sign-extends it to 64 bits.

if RA = 0 then
  EA ← (DS || 0b00)
else
  EA ← (RA) + (DS || 0b00)
RT ← sign_extend([EA+3:EA])
// Load word at aligned EA and sign-extend to 64 bits

Loads a 32-bit word from memory at address (RA + (DS || 0b00)), where DS is a 14-bit signed displacement (making the effective address 4-byte aligned), and places it into RT with sign extension to 64 bits. This is a 64-bit instruction available only in 64-bit implementations. No condition or status registers are affected.

The lwa instruction is commonly used for loading a 32-bit word from memory into a target register while zeroing out the upper 32 bits. Ensure that the base address in RA and displacement D are correctly aligned to avoid alignment faults. This instruction operates at user privilege level and will raise an exception if the effective address is invalid or if there is a protection fault.


Summary: Loads a doubleword (64 bits) from memory.

DS

Displacement (14-bit Signed, Multiple of 4)

if 'ld' then
    EA ← (RA|0) + EXTS64(DS||0b00)
    RT ← MEM(EA, 8)

The doubleword in storage addressed by EA is loaded into RT. The effective address (EA) is the sum of RA and disp, sign-extended to 64 bits.

The ld instruction loads a doubleword from memory into a register. Ensure the address is properly aligned to avoid alignment faults. This instruction operates at user privilege level and will raise an exception if the EA is out of bounds or access permissions are violated.


Summary: Loads a word and creates a reservation for use with 'stwcx.'. Critical for implementing atomic primitives (mutexes).

EA ← (RA) + (RB)
RT ← sign_extend([EA+3:EA])
RESERVATION_VALID ← 1
RESERVATION_ADDR ← page_address(EA)
// EH field (bit 31) is a hint for subsequent stwcx.

Loads a 32-bit word from memory at address (RA + RB) and places it into RT, and creates a reservation on that cache line for atomic updates with stwcx. The optional EH field (bit 31) provides a hint about the expected success of a subsequent conditional store. This instruction is critical for implementing atomic operations and locks. No condition or status registers are modified by this instruction itself.

EH = 0 should be used when all accesses to a mutex variable are performed using an instruction sequence with Load And Reserve followed by Store Conditional. EH = 1 should be used when the program is obtaining a lock variable which it will subsequently release before another program attempts to perform a store to it.


Summary: Loads a doubleword and creates a reservation. 64-bit version of lwarx.

EA ← (RA) + (RB)
RT ← MEM(EA, 8)
Reserve(EA, 8)

Loads a doubleword from memory at address RA+RB and creates a reservation on that memory location for use with subsequent stdcx. instructions. The EH field provides a hint to the processor about the expected outcome of the following store-conditional. This is the 64-bit variant of lwarx and is essential for atomic operations and synchronization primitives.

Load Doubleword And Reserve Indexed X-form serves as both a basic and an extended mnemonic. The Assembler will recognize a ldarx mnemonic with four operands as the basic form, and a ldarx mnemonic with three operands as the extended form.


Summary: Copies a value from a general-purpose register to a system SPR (e.g., CTR, LR, XER).

SPR

Special Purpose Register ID (Reordered bits)

SPR_index ← (SPR[5:0] || SPR[10:5])
SPR[SPR_index] ← RS

Moves the contents of a general-purpose register to a special-purpose register (such as CTR, LR, XER, FPSCR, or others). The SPR field is reordered from its 10-bit encoding in the instruction. Privilege level and results depend on which SPR is targeted; some SPRs are supervisor-only. No condition register flags are set by this instruction itself.

AMR, IAMR, UAMOR, BESCR, BESCRU, HMER, TBL, TBU, SPR

spr0=1 if and only if writing the register is privileged. Execution of this instruction specifying an SPR number with spr0=1 when the privilege state of the thread does not permit the access causes one of the following: MSRPR=1: Privileged Instruction type Program interrupt, MSRHV PR=0b00 or MSRS HV PR=0b010 and the SPR is always an ultravisor resource (independent of the contents of SMFCTRL): Privileged Instruction type Program interrupt, LPCREVIRT=0: Privileged Instruction type Program interrupt, LPCREVIRT=1: Hypervisor Emulation Assistance interrupt, MSRS HV PR=0b010 and the SPR is PTCR, DAWRn, DAWRXn, or CIABR when they are ultravisor privileged for the operation: Hypervisor Emulation Assistance interrupt.


Summary: Moves the contents of a special purpose register into a general-purpose register.

SPR_index ← (SPR[5:0] || SPR[10:5])
RT ← SPR[SPR_index]

Moves the contents of a special-purpose register into a general-purpose register. The SPR field is reordered from its 10-bit encoding. Privilege level and results depend on which SPR is read; some SPRs are supervisor-only or hypervisor-only. No condition register flags are modified.

The SPR field denotes a Special Purpose Register, encoded as shown in the table below. If the SPR field contains a value from 808 through 811, the instruction specifies a reserved SPR, and is treated as a no-op; see Section 1.3.3, “Reserved Fields, Reserved Values, and Reserved SPRs”. Otherwise, the contents of the designated Special Purpose Register are placed into register RT. For Special Purpose Registers that are 32 bits long, the low-order 32 bits of RT receive the contents of the Special Purpose Register and the high-order 32 bits of RT are set to zero.


Summary: Multiplies two 32-bit integers and stores the lower 32 bits of the 64-bit result.

product ← (RA) ×signed (RB)
RT ← product[32:63]
if OE = 1 then
  OV ← (product[0:31] ≠ sign_extend(product[32:63]))
  SO ← SO | OV
if Rc = 1 then
  CR0 ← (RT < 0) || (RT > 0) || (RT = 0) || SO

Multiplies the contents of RA and RB as signed 32-bit integers and stores the lower 32 bits of the 64-bit result in RT. If OE=1, sets OV and SO in XER if the result overflows (i.e., if the upper 32 bits of the 64-bit product differ from the sign extension of bits 0-31). If Rc=1, updates CR0 based on the result.

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.


Summary: Multiplies the contents of two registers and places the low-order 64 bits of the product into a target register.

prod0:127 ← (RA) × (RB)
RT ← prod0:63
if OE=1 then
    OV and OV32 are set to 1 if the product cannot be represented in 64 bits.

The 64-bit operands are (RA) and (RB). The low-order 64 bits of the 128-bit product of the operands are placed into register RT. Both operands and the product are interpreted as signed integers.

The XO-form Multiply instructions may execute faster on some implementations if RB contains the operand having the smaller absolute value.


Summary: Copies contents of RS to RA. (Alias for 'or RA, RS, RS').

Move Register. Extended mnemonic for OR (or RA,RS,RS). Copies the contents of register RS into register RA.

The `mr` instruction is commonly used to copy values between general-purpose registers. It does not require any special alignment or privilege level. However, be cautious when using this instruction in performance-critical sections as it may introduce pipeline stalls if the destination register is already in use.


Summary: Provides the means by which a program can call upon the system to perform a service.

Triggers a system call, transferring control to the operating system (LEV=0) or hypervisor (LEV=1). The instruction is privileged; attempting to execute it in user mode or with an invalid LEV value may cause an exception. The LEV field indicates the target privilege level for the service request.

if LEV = 0 then
  SyscallOS()
else if LEV = 1 then
  SyscallHypervisor()
else
  raise exception

Executing this instruction with LEV=1 or LEV=2 is the only way that executing an instruction can cause a transition from non-hypervisor state to hypervisor state on the thread that executed the instruction. Executing this instruction with LEV=2 when SMFCTRLE=1 is the only way that executing an instruction can cause a transition from non-ultravisor state to ultravisor state on the thread that executed the instruction. In correct use, this instruction is used to 'call up' one privilege level (application program calls operating system, operating system calls hypervisor, hypervisor calls ultravisor). However, it is possible for a program to call up more than one level (e.g., for an application program to call the hypervisor). An attempt to call up more than one level should be considered a programming error.


Summary: Does nothing. (Alias for 'ori 0, 0, 0').

A no-operation instruction that performs no action and modifies no registers or status flags. It is commonly used for instruction alignment, timing, or as a placeholder. This is implemented as an alias for 'ori 0, 0, 0' in the base ISA.

The nop instruction is useful for optimizing code by reducing unnecessary operations, but it has no effect on program state or execution flow.


Summary: Loads a 16-bit signed immediate into a register. (Alias for 'addi RT, 0, SIM').

Loads a 16-bit signed immediate value into the target register. This is an assembly-language alias for 'addi RT, 0, SIM' that simplifies loading small constants. No condition register flags are affected.

The `li` instruction is commonly used for initializing or resetting registers to specific values. Ensure the immediate value fits within the 32-bit signed integer range to avoid unexpected behavior. This instruction operates at user privilege level and does not generate exceptions unless there are issues with the instruction encoding.


Summary: Loads a 16-bit immediate into the upper half of a 32-bit word. (Alias for 'addis RT, 0, SIM').

The 'lis' instruction loads an immediate value shifted left by 16 bits into a register. If the source register (RA) is zero, it uses the value 0; otherwise, it adds the contents of RA to the sign-extended immediate value.

if RA = 0 then
    RT ← EXTS(SI || 160)
else
    RT ← (RA) + EXTS(SI || 160)

The 'lis' instruction is commonly used to load large constants into a register by shifting the immediate value left by 16 bits. If the source register (RA) is not zero, its contents are added to the sign-extended immediate value. Be cautious with alignment as this can affect performance and correctness. This instruction operates at user privilege level.


Summary: Complements the contents of one register and places the result into another register.

The 'not' instruction complements the contents of register Ry and places the result into register Rx. This mnemonic can be coded with a final '.' to cause the Rc bit to be set in the underlying instruction.

if 'not' then
    Rx <- ~Ry
if 'not.' then
    Rx <- ~Ry
    Rc = 1

The 'not' instruction is commonly used for bitwise negation of a register's contents. Be cautious with the '.' suffix as it affects the condition register (CR0) by setting the Rc bit, which can impact subsequent conditional branches. Ensure that the registers are properly aligned and accessible at the privilege level required for execution.


Summary: Moves GPR to CTR. (Alias for 'mtspr 9, RS').

Moves a value from a general-purpose register into the Count register (CTR), typically used to set up loop counts or branch targets for branch-to-CTR instructions. This is an alias for 'mtspr 9, RS' where SPR 9 designates CTR. No condition register flags are modified.

The mtctr instruction is commonly used to set up loop counters by moving values from a general-purpose register into the Count Register (CTR). Ensure that the source register contains the correct value for the desired loop iterations. This instruction operates at user privilege level and does not generate exceptions under normal conditions, but incorrect usage can lead to infinite loops if not managed properly.


Summary: Moves CTR to GPR. (Alias for 'mfspr RT, 9').

Moves the Count Register (CTR) to a general-purpose register. This is an alias for mfspr RT, 9 and is commonly used to save the loop counter or retrieve branching information. No status registers are affected.

The mfctr instruction is commonly used to retrieve the current count value from the Count Register, which is often utilized in loop control. Ensure that the destination register (RT) is properly aligned and accessible at the privilege level where this instruction is executed. This instruction does not raise exceptions under normal circumstances but should be used with caution in critical loops to avoid unintended behavior.


Summary: Moves GPR to LR. (Alias for 'mtspr 8, RS').

Move To Link Register. Extended mnemonic for MTSPR (mtspr 8,RS). Copies the contents of register RS into the Link Register (LR).

The mtlr instruction is commonly used to update the Link Register with a new value, often during function calls or branch operations. Ensure that the source register contains the correct address or value before executing this instruction. This operation does not require any special privileges and will not generate exceptions under normal circumstances.


Summary: Moves LR to GPR. (Alias for 'mfspr RT, 8').

Moves the Link Register (LR) to a general-purpose register. This is an alias for mfspr RT, 8 and is commonly used to save the return address before modifying LR. No status registers are affected.

Use mflr to save the return address before making a function call, ensuring you can return correctly afterward. Ensure the target register (RT) is not reserved and is properly aligned for your architecture.


Rotate Left Word Immediate Then AND with Mask

Summary: Rotates the low-order 32 bits of a register left by a specified number of bit positions, generates a mask, and performs an AND operation.

The contents of register RS are rotated32 left SH bits. A mask is generated having 1-bits from bit MB+32 through bit ME+32 and 0-bits elsewhere. The rotated data are ANDed with the generated mask and the result is placed into register RA.

if 'rlwinm' then
    n ← SH
    r ← ROTL32((RS)32:63, n)
    m ← MASK(MB+32, ME+32)
    RA ← r & m

Let RSL represent the low-order 32 bits of register RS, with the bits numbered from 0 through 31. rlwinm can be used to extract an n-bit field that starts at bit position b in RSL, right-justified into the low-order 32 bits of register RA (clearing the remaining 32-n bits of the low-order 32 bits of RA), by setting SH=b+n, MB=32-n, and ME=31. It can be used to extract an n-bit field that starts at bit position b in RSL, left-justified into the low-order 32 bits of register RA (clearing the remaining 32-n bits of the low-order 32 bits of RA), by setting SH=b, MB = 0, and ME=n-1. It can be used to rotate the contents of the low-order 32 bits of a register left (right) by n bits, by setting SH=n (32-n), MB=0, and ME=31. It can be used to shift the contents of the low-order 32 bits of a register right by n bits, by setting SH=32-n, MB=n, and ME=31. It can be used to clear the high-order b bits of the low-order 32 bits of the contents of a register and then shift the result left by n bits, by setting SH=n, MB=b-n, and ME=31-n. It can be used to clear the low-order n bits of the low-order 32 bits of a register, by setting SH=0, MB=0, and ME=31-n.


Rotate Left Word Immediate Then Mask Insert

Summary: Rotates a word left, then inserts bits into the target under a mask. Used for inserting bitfields.

Rotates the contents of RS left by SH bit positions, creates a mask from bits MB through ME, and inserts the rotated value into RA under that mask, leaving other bits in RA unchanged. The condition register CR0 is updated if Rc=1.

n ← SH
mask ← MASK(MB, ME)
rotated ← ROTL32(RS, n)
RA ← (RA & ¬mask) | (rotated & mask)
if Rc = 1 then CR0 ← (RA < 0, RA > 0, RA = 0, SO)

The rlwimi instruction is commonly used for bit manipulation tasks such as rotating bits and selectively inserting them into a register. Be cautious with the shift amount (SH), mask bits (MB and ME), and ensure they are within valid ranges to avoid unexpected results. This instruction operates at user privilege level and does not generate exceptions under normal conditions, but improper use can lead to data corruption.


Summary: Rotates the contents of register RS left by the number of bits specified by (RB)59:63, and then performs a bitwise AND operation with a mask.

The contents of register RS are rotated 32 left the number of bits specified by (RB)59:63. A mask is generated having 1-bits from bit MB+32 through bit ME+32 and 0-bits elsewhere. The rotated data are ANDed with the generated mask and the result is placed into register RA.

if 'rlwnm' then
    n ← (RB)59:63
    r ← ROTL32((RS)32:63, n)
    m ← MASK(MB+32, ME+32)
    RA ← r & m
else if 'rlwnm.' then
    n ← (RB)59:63
    r ← ROTL32((RS)32:63, n)
    m ← MASK(MB+32, ME+32)
    RA ← r & m

RS, with the bits numbered from 0 through 31. rlwnm can be used to extract an n-bit field that starts at variable bit position b in RSL, right-justified into the low-order 32 bits of register RA (clearing the remaining 32-n bits of the low-order 32 bits of RA), by setting RB59:63=b+n, MB=32-n, and ME=31. It can be used to extract an n-bit field that starts at variable bit position b in RSL, left-justified into the low-order 32 bits of register RA (clearing the remaining 32-n bits of the low-order 32 bits of RA), by setting RB59:63=b, MB = 0, and ME=n-1. It can be used to rotate the contents of the low-order 32 bits of a register left (right) by variable n bits, by setting RB59:63=n (32-n), MB=0, and ME=31.


Summary: Rotates a 64-bit register left, then clears bits based on a mask. 64-bit equivalent of rlwinm.

if 'rldic' then
    SH ← sh5 || sh0:4
    r ← ROTL64((RS), SH)
    MB ← mb5 || mb0:4
    m ← MASK(MB, 63-SH)
    RA ← r & m

The contents of register RS are rotated64 left SH bits. A mask is generated having 1-bits from bit MB through bit 63-SH and 0-bits elsewhere. The rotated data are ANDed with the generated mask and the result is placed into register RA.

rldic can be used to clear the high-order b bits of the contents of a register and then shift the result left by n bits, by setting SH=n and MB=b-n. It can be used to clear the high-order n bits of a register, by setting SH=0 and MB=n.


Rotate Left Doubleword Immediate Clear Left

Summary: Rotates the contents of a register left by a specified number of bits and clears higher-order bits.

The contents of register RS are rotated 64 left SH bits. A mask is generated having 1-bits from bit MB through bit 63 and 0-bits elsewhere. The rotated data are ANDed with the generated mask and the result is placed into register RA.

SH ← SH5 || SH0:4
r ← ROTL64((RS), SH)
MB ← MB5 || MB0:4
m ← MASK(MB, 63)
RA ← r & m

rldicl can be used to extract an n-bit field that starts at bit position b in register RS, right-justified into register RA (clearing the remaining 64-n bits of RA), by setting SH=b+n and MB=64-n. It can be used to rotate the contents of a register left by n bits, by setting SH=n and MB=0. It can be used to shift the contents of a register right by n bits, by setting SH=64-n and MB=n. It can be used to clear the high-order n bits of a register, by setting SH=0 and MB=n.


Rotate Left Doubleword Immediate Clear Right

Summary: Rotates 64-bit RS left by SH, then clears the low-order bits (ME+1 to 63).

n ← SH
mask ← MASK(0, ME)
rotated ← ROTL64(RS, n)
RA ← rotated & mask
if Rc = 1 then CR0 ← (RA < 0, RA > 0, RA = 0, SO)

Rotates the 64-bit contents of RS left by SH positions, then clears bits (ME+1) through 63, effectively creating a mask from bit 0 through ME. The condition register CR0 is updated if Rc=1.

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.


Rotate Left Doubleword Immediate Mask Insert

Summary: Rotates 64-bit value and inserts into target under mask.

Rotates the 64-bit contents of RS left by SH positions and inserts the result into RA under a mask defined by MB and (63-SH), leaving other bits in RA unchanged. The condition register CR0 is updated if Rc=1.

n ← SH
mask ← MASK(MB, 63 - n)
rotated ← ROTL64(RS, n)
RA ← (RA & ¬mask) | (rotated & mask)
if Rc = 1 then CR0 ← (RA < 0, RA > 0, RA = 0, SO)

The rldimi instruction is useful for performing masked left rotations on 64-bit values. Ensure that the shift amount (SH) and mask bits (MB) are within valid ranges to avoid undefined behavior. This instruction operates at user privilege level and does not generate exceptions under normal conditions, but incorrect usage can lead to unexpected results.


Summary: Shifts a 64-bit register left by the amount specified in RB.

if (RB)57 = 0 then
    n ←(RB)58:63
    r ←ROTL64((RS), n)
    m ←MASK(0, 63-n)
else
    m ←640
RA ←r & m

The contents of register RS are shifted left the number of bits specified by (RB)57:63. Bits shifted out of position 0 are lost. Zeros are supplied to the vacated positions on the right. The result is placed into register RA. Shift amounts from 64 to 127 give a zero result.


Summary: Logical right shift of 64-bit value.

Logically shifts RS right by the number of bit positions specified in RB (bits 57-63), inserting zeros at the left. If RB ≥ 64, the result is zero. No status registers are affected.

n ← RB[57:63]
if n < 64 then RA ← RS >> n
else RA ← 0

The srd instruction is used to update the Machine State Register (MSR) based on the contents of a source register and the L field. When L=0, specific bits in the MSR are updated using logical operations involving bits from the source register and the current MSR state. When L=1, only bits 48 and 62 of the MSR are set to match those in the source register, while other bits remain unchanged. This instruction requires supervisor privilege level and can trigger exceptions if not executed properly.


Summary: Arithmetic right shift of 64-bit value (preserves sign).

Arithmetically shifts RS right by the number of bit positions specified in RB (bits 57-63), preserving the sign bit (bit 0) and shifting in sign-extended bits. If RB ≥ 64, the result is all 0s or all 1s depending on sign. The XER[CA] carry bit is set if any 1-bits are shifted out from a negative number.

n ← RB[57:63]
if n < 64 then
  RA ← RS >>a n
  XER[CA] ← 1 if (RS < 0 & (RS & MASK(64-n, 63)) ≠ 0) else 0
else
  if RS < 0 then RA ← -1; XER[CA] ← 1
  else RA ← 0; XER[CA] ← 0

The srad instruction is commonly used for right-shifting signed integers while preserving the sign bit. Be cautious with shift amounts of 32 or more, as they result in a full sign extension and clear the carry bits. Ensure that the input register RS contains valid data and that RB's upper 8 bits specify a valid shift amount (0-63).


Shift Right Algebraic Doubleword Immediate

Summary: Performs an arithmetic right shift on a 64-bit doubleword by a constant amount.

n ← SH
RA ← RS >>a n
if RS < 0 & (RS & MASK(64-n, 63)) ≠ 0 then XER[CA] ← 1
else XER[CA] ← 0
if Rc = 1 then CR0 ← (RA < 0, RA > 0, RA = 0, SO)

Arithmetically shifts RS right by SH bit positions (0-63), preserving the sign bit and shifting in sign-extended bits. Sets XER[CA] if any 1-bits are shifted out from a negative number. The condition register CR0 is updated if Rc=1.


Summary: Loads a halfword from memory, byte-reverses it, and stores it in a register.

Loads a halfword from memory at address (RA|0) + RB, byte-reverses it, and stores the result in RT. No status flags are affected. This is part of the Base category and is commonly used for endianness conversion when reading network or file data.

EA ← (RA|0) + RB
RT ← byte_reverse_16([EA])

These instructions have the effect of loading and storing data in the opposite byte ordering from that which would be used by other Load and Store instructions.


Summary: Loads a word and swaps bytes.

Loads a word (32-bit value) from memory at address (RA|0) + RB, byte-reverses it, and stores the result in RT. No status flags are affected. This instruction is used for converting word-sized data between big-endian and little-endian formats.

EA ← (RA|0) + RB
RT ← byte_reverse_32([EA])

The lwbrx instruction is commonly used to load a word from memory and reverse its byte order, which can be useful for handling data in big-endian or little-endian formats. Ensure that the base address (RA) and index (RB) registers are correctly set to avoid incorrect memory access. This instruction operates at user privilege level and will raise an exception if it accesses invalid memory addresses.


Summary: Swaps bytes and stores a halfword.

Byte-reverses the low 16 bits of RS and stores the result as a halfword in memory at address (RA|0) + RB. No status flags are affected. This is used to write halfword data in reversed byte order to memory.

EA ← (RA|0) + RB
[EA] ← byte_reverse_16(RS[48:63])

The sthbrx instruction is useful for storing a halfword in memory with byte-reversed order. Ensure that the base address register (RA) and index register (RB) are correctly set to avoid incorrect memory addresses. This instruction operates at user privilege level and will raise an exception if the effective address is out of bounds or if there is a protection fault.


Summary: Swaps bytes and stores a word.

Byte-reverses the low 32 bits of RS and stores the result as a word in memory at address (RA|0) + RB. No status flags are affected. This instruction is used for writing word-sized data in reversed byte order.

EA ← (RA|0) + RB
[EA] ← byte_reverse_32(RS[32:63])

The stwbrx instruction is useful for storing a word in memory with its byte order reversed, which can be necessary for compatibility with systems that use different endianness. Ensure that the effective address (EA) calculated from registers RA and RB is properly aligned to avoid alignment exceptions. This instruction operates at user privilege level but will raise an exception if the EA is out of bounds or if there are insufficient permissions.


Summary: Loads a doubleword from memory, byte-reversing it before storing in the target register.

Loads a doubleword (64-bit value) from memory at address (RA|0) + RB, byte-reverses it, and stores the result in RT. No status flags are affected. This is used for converting doubleword data between big-endian and little-endian byte orders.

EA ← (RA|0) + RB
RT ← byte_reverse_64([EA])

The ldbrx instruction is commonly used for loading and reversing the byte order of a doubleword from memory into a register. Ensure that the base address in RA (or 0 if using an absolute address) and the offset in RB are correctly set to avoid accessing invalid memory locations. This instruction operates at user privilege level, but care must be taken to handle potential exceptions such as alignment errors or access violations. Performance may vary depending on memory alignment; optimal performance is achieved when the effective address is 8-byte aligned.