Summary: Permutes bits from RS based on the index values in RB. Highly optimized for bit shuffling.

for i in 0 to 7 do; index ← RB[i*8+2:i*8+7]; if (index < 64) then RA[i] ← RS[index]; else RA[i] ← 0;

Permutes the bits of RS according to bit indices specified in RB, placing the result in RA. Each byte of RB contains a 6-bit index (0-63) that selects which bit from RS to place at that bit position in RA. This is a Base-category scalar instruction with no CR or XER updates.

The fact that the permuted bit is 0 if the corresponding index value exceeds 63 permits the permuted bits to be selected from a 128-bit quantity, using a single index register.


Summary: Separates bits of the source register into two groups based on a mask (Power10 Scalar).

Centrifuges a 64-bit doubleword by separating bits according to a mask RB, moving masked bits to the low order of the result and unmasked bits to the high order (Power10 Scalar). The result is placed in RA. No CR, XER, or FPSCR fields are affected.

do_mask ← RB; result_low ← []; result_high ← []; j_low ← 0; j_high ← 0; for i in 0 to 63 do; if (do_mask[i] = 1) then result_low[j_low] ← RS[i]; j_low ← j_low + 1; else result_high[j_high] ← RS[i]; j_high ← j_high + 1; RA ← result_low || result_high;

The cfuged instruction is useful for counting leading zeros in a doubleword value, but only considering the bits that are set to 1 in a mask. Ensure the mask register (RB) has bits set where you want to consider leading zeros in the source register (RS). The result is zero-extended to 64 bits before being stored in the destination register (RA). This instruction operates at user privilege level and does not generate exceptions under normal conditions.


Summary: Deposits bits from RS to RA under control of mask RB (Scalar).

Deposits bits from RS into RA at positions specified by the mask RB (Power10 Scalar). Bits set to 1 in RB indicate positions where bits from RS are placed in RA; bits set to 0 in RB receive zeros. No CR, XER, or FPSCR fields are affected.

mask ← RB; result ← [0]*64; src_idx ← 0; for i in 0 to 63 do; if (mask[i] = 1) then result[i] ← RS[src_idx]; src_idx ← src_idx + 1; RA ← result;

The pdepd instruction is useful for selectively depositing bits from one register into another based on a mask. Ensure that the source and destination registers are properly aligned to avoid unexpected behavior. This instruction operates at user privilege level, but care must be taken with the mask to prevent unintended data corruption.


Summary: Extracts bits from a source register based on a mask and places them into the target register.

The contents of the bits in register RS corresponding to bits in mask containing a 1 are packed into an n-bit value. The extracted value is placed into register RA.

result ← 0
mask ← (RB)
m ← 0
k ← 0
do while (m < 64)
    if ((RB)63-m == 1) then do
        result63-k ← (RS)63-m
        k ← k + 1
    end
    m ← m + 1
end
RA ← result

The pextd instruction is useful for extracting and packing bits from a source register based on a mask. Ensure the mask register (RB) has bits set to 1 where you want to extract corresponding bits from the source register (RS). The operation is performed in little-endian order, so the least significant bit of the result corresponds to the first bit set in the mask. This instruction operates at user privilege level and does not generate exceptions for normal use cases.


Count Leading Zeros Doubleword under Mask

Summary: Counts leading zeros in RS, but only considering bits set in mask RB.

Counts the number of leading zeros in RS considering only the bit positions set to 1 in the mask RB (Power10 Scalar). The count is placed in RA. No CR, XER, or FPSCR fields are affected.

mask ← RB; masked_value ← RS ∧ mask; if (masked_value = 0) then RA ← 64; else count ← 0; for i in 0 to 63 do; if (masked_value[i] = 1) then break; count ← count + 1; RA ← count;

The cntlzdm instruction is useful for counting leading zeros in a doubleword while considering only the bits that are set to 1 in a mask. Ensure that both the source and mask registers are correctly aligned and that the mask register has at least one bit set to 1 to avoid undefined behavior. This instruction operates at user privilege level and does not generate exceptions under normal conditions, but it may incur performance penalties on processors without hardware support for this operation.


Count Trailing Zeros Doubleword under Mask

Summary: Counts trailing zeros in RS, but only considering bits set in mask RB.

Counts the number of trailing zeros in RS considering only the bit positions set to 1 in the mask RB (Power10 Scalar). The count is placed in RA. No CR, XER, or FPSCR fields are affected.

mask ← RB; masked_value ← RS ∧ mask; if (masked_value = 0) then RA ← 64; else count ← 0; for i in 63 downto 0 do; if (masked_value[i] = 1) then break; count ← count + 1; RA ← count;

The cnttzdm instruction is useful for counting trailing zeros in a doubleword while applying a mask. Ensure that the mask register (RB) has bits set to 1 where you want to consider the corresponding bits in the source register (RS). The result is zero-extended to 64 bits before being stored in the destination register (RA). This instruction operates at user privilege level and does not generate any exceptions under normal conditions. Performance may vary based on the distribution of zeros and ones in the registers.


Summary: Accumulates a CRC32 checksum using the low byte of RS.

Accumulates a 32-bit CRC checksum using the low byte (bits 56-63) of RS, with the running CRC value in RA. The updated CRC result is written to RA. This is a Base-category instruction with no CR, XER, or FPSCR updates.

byte_val ← RS[56:63]; crc ← RA ⊕ (byte_val || [0]*24); for i in 0 to 7 do; if (crc[31] = 1) then crc ← (crc << 1) ⊕ 0x04C11DB7; else crc ← crc << 1; crc ← crc ∧ 0xFFFFFFFF; RA ← crc;


Summary: Accumulates a CRC32 checksum using the low halfword of RS.

Accumulates a 32-bit CRC checksum using the low halfword (bits 48-63) of RS, with the running CRC value in RA. The updated CRC result is written to RA. This is a Base-category instruction with no CR, XER, or FPSCR updates.

halfword_val ← RS[48:63]; crc ← RA ⊕ (halfword_val || [0]*16); for i in 0 to 15 do; if (crc[31] = 1) then crc ← (crc << 1) ⊕ 0x04C11DB7; else crc ← crc << 1; crc ← crc ∧ 0xFFFFFFFF; RA ← crc;


Summary: Accumulates a CRC32 checksum using the word in RS.

Accumulates a CRC32 checksum by processing the 32-bit word in RS using the Castagnoli polynomial. The result is XORed with the accumulator in RA and stored back to RA. This instruction is part of the Base extension and does not affect condition registers or status fields.


Cyclic Redundancy Check 32-bit Doubleword

Summary: Accumulates a CRC32 checksum using the doubleword in RS.

Accumulates a CRC32 checksum by processing the 64-bit doubleword in RS using the Castagnoli polynomial. The result is XORed with the accumulator in RA and stored back to RA. This instruction is part of the Base extension and does not affect condition registers or status fields.


Summary: Loads a 34-bit signed immediate into a register. (Replaces multiple 'lis/ori' instructions).

Loads a 34-bit signed immediate value into GPR RT, replacing the need for multiple lis/ori instructions. This is a prefixed instruction (2 words / 64 bits total) where the prefix encodes bits 0-17 and the main instruction encodes bits 18-33 of the immediate. No condition registers or status fields are affected.

The pli instruction is used to load an immediate value directly into a target register. This is useful for initializing registers with constants or small values. Ensure the immediate value fits within the 16-bit signed integer range to avoid overflow issues.


Summary: Permutes bytes from two source vectors using a control vector and a 3-bit selector.

Permutes bytes from source vectors XA and XB using byte indices in XC, with a 3-bit UIM field selecting between different permutation modes. The permutation control bytes in XC determine which source byte maps to each position in XT. This VSX instruction does not affect condition registers or status fields.

The following is an example of emulating 256-bit xxperm, where a 256-bit vector is contained in a pair of VSRs. The instruction is capable of emulating up to a 2048-bit xxperm.


Summary: Selects bytes from XA or XB based on the MSB of bytes in XC.

For xxblendvb, the contents of VSR[XT] are determined by the contents of VSR[XC]. If bit 0 of byte element i in VSR[XC] is 0, then byte element i of VSR[XT] is taken from VSR[XA]; otherwise, it is taken from VSR[XB].

if MSR.VSX=0 then VSX_Unavailable()
do i = 0 to 15
    if VSR[32×CX+C].byte[i].bit[0]=0 then
        VSR[32×TX+T].byte[i] ←VSR[32*AX+A].byte[i]
    else
        VSR[32×TX+T].byte[i] ←VSR[32*BX+B].byte[i]
end

The xxblendvb instruction blends bytes from two source vectors based on a control vector. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid an exception. The instruction operates on 16-byte vectors, and each byte is independently selected from either of the two source vectors based on the corresponding bit in the control vector. This instruction is useful for conditional data merging but requires careful handling of the control vector to achieve the desired result.


Summary: Selects halfwords from XA or XB based on the MSB of halfwords in XC.

For xxblendvh, the contents of each halfword in the target vector are selected from either the first or second source vector based on the corresponding bit in the control vector.

if MSR.VSX=0 then VSX_Unavailable()
do i = 0 to 7
    if VSR[32×CX+C].hword[i].bit[0]=0 then
        VSR[32×TX+T].hword[i] ←VSR[32×AX+A].hword[i]
    else
        VSR[32×TX+T].hword[i] ←VSR[32×BX+B].hword[i]
end

Ensure VSX is enabled by checking and setting the appropriate bit in the MSR register. This instruction blends halfwords from two source vectors into a target vector based on a control vector's bits. Be cautious of alignment requirements for vector registers to avoid undefined behavior.


Summary: Selects words from XA or XB based on the MSB of words in XC.

Selects whole words from XA or XB based on the MSB of the corresponding word in control register XC. If the MSB of a word in XC is 1, the word from XB is selected; otherwise the word from XA is selected. This VSX instruction does not affect condition registers or status fields.

The xxblendvw instruction is commonly used for conditional blending of word elements from two source vectors based on a control vector. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. This instruction operates on 16-word elements, so alignment and ordering of input registers must be correct to prevent data corruption or incorrect results.


Summary: Selects doublewords from XA or XB based on the MSB of doublewords in XC.

Selects whole doublewords from XA or XB based on the MSB of the corresponding doubleword in control register XC. If the MSB of a doubleword in XC is 1, the doubleword from XB is selected; otherwise the doubleword from XA is selected. This VSX instruction does not affect condition registers or status fields.

The xxblendvd instruction is useful for selectively blending elements from two source vectors (A and B) into a destination vector based on control bits derived from a third vector (C). Ensure that all input vectors are properly aligned to avoid alignment faults. This instruction operates at the user privilege level and may raise exceptions if the immediate field value exceeds valid range or if there are invalid operand types.


Summary: Loads a 32-bit word and replicates it across the vector.

Loads a 32-bit word from memory at address RA + RB, then replicates it across all four 32-bit word positions in the target VSX register XT. This VSX instruction does not affect condition registers or status fields.

EA ← RA + RB
word ← [EA:EA+3]
for i in 0 to 3:
  XT[32*i:32*i+31] ← word

The lxvwsx instruction is commonly used for loading a word from memory and replicating it across all elements of a VSX vector register. Ensure that the appropriate privilege levels (MSR.VSX or MSR.VEC) are enabled to avoid exceptions. The instruction requires 4-byte alignment for the memory address; unaligned accesses may result in performance penalties or exceptions depending on the system configuration.


Summary: Moves a 32-bit word from a GPR and replicates it across the vector.

Moves the low 32 bits from GPR RA into a VSX register, then replicates that 32-bit word across all four 32-bit word positions in XT. This VSX instruction does not affect condition registers or status fields.

word ← RA[32:63]
for i in 0 to 3:
  XT[32*i:32*i+31] ← word

The mtvsrws instruction is used to move the upper 32 bits of a general-purpose register into the first word element of a vector-scalar register and splat it across the remaining elements. Ensure that the VSX or Vector facility is enabled in the MSR before using this instruction, otherwise, an exception will be raised. This instruction treats the operation as a Vector instruction, so developers should consider resource availability accordingly.


VSX Scalar Maximum Type-C Double-Precision

Summary: Computes the maximum of two double-precision floating-point values and stores the result in a vector scalar register.

Computes the maximum of two double-precision floating-point scalar values and stores the result in the target VSR. The operation follows the IEEE 754 maximum semantics where positive zero is greater than negative zero, and any comparison with NaN returns NaN. This instruction is part of the VSX category and does not set CR or XER flags.

xsmaxcdp can be used to implement the C/C++/Java conditional operation (x>y)?x:y for single-precision and double-precision arguments. Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.


VSX Scalar Minimum Type-C Double-Precision

Summary: Computes the minimum of two double-precision floating-point numbers and handles NaNs according to Type-C rules.

If either src1 or src2 is a NaN, result is src2. Otherwise, if src1 is less than src2, result is src1. Otherwise, result is src2. The contents of doubleword 0 of VSR[XT] are set to the value result. The contents of doubleword 1 of VSR[XT] are set to 0.

if 'xsmincdp' then
    src1 <- VSR[XA]
    src2 <- VSR[XB]
    if src2 is QNaN or SNaN then
        fx(VXSNAN)
    else if src2 is -Infinity then
        T(src2) <- src2
    else if src2 is +Zero then
        T(src2) <- src2
    else if src2 is +NZF then
        T(src2) <- M(src1, src2)
    else if src2 is +Infinity then
        T(src2) <- src2
    VSR[XT] <- T(src2)

xsmincdp can be used to implement the C/C++/Java conditional operator (x<y)?x:y for single-precision and double-precision arguments. Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.


Vector Scalar Maximum of Double-Precision Floating-Point Values with Java Rounding

Summary: Compares two double-precision floating-point values and returns the larger one, with specific handling for zero and NaN values.

Computes the maximum of two double-precision floating-point scalar values using Java-compliant semantics, where -0.0 is greater than +0.0, and NaN handling follows Java rules. The result is stored in the target VSR. This instruction is part of the VSX category and does not update CR or XER.

xsmaxjdp can be used to implement the Java max() function for single-precision and double-precision arguments. Despite Java not recognizing the concept of exception status, VXSNAN is set to 1 if either operand is an SNaN.


Vector Scalar Minimum of Double-Precision Floating-Point Values

Summary: Compares two double-precision floating-point values and selects the minimum value, handling special cases like NaNs and zeros.

Computes the minimum of two double-precision floating-point scalar values using Java-compliant semantics, where +0.0 is less than -0.0, and NaN handling follows Java rules. The result is stored in the target VSR. This instruction is part of the VSX category and does not update CR or XER.

xsminjdp can be used to implement the Java min() function for single-precision and double-precision arguments. Java only recognizes the concept of a NaN, but does not distinguish any difference between different NaN encodings, including between a QNaN and a SNaN. As a result, a SNaN operand is propagated as a SNaN (i.e., not converted to a QNaN). Despite Java not recognizing the concept of exception status, VXSNAN is set to 1 if either operand is a SNaN. Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.


VSX Vector Generate Permute Control Vector from Byte Mask

Summary: Generates a permute control vector based on the byte mask in VSR[VRB+32].

vMASK

Source Vector Register containing the mask byte

Immediate value specifying the control vector type

Generates a permute control vector in XT based on a byte mask contained in XB and an immediate value that specifies the control vector type. The instruction uses the byte mask to determine which bytes are selected for permutation operations. This VSX instruction sets no CR or XER flags.

The xxgenpcvbm instruction is used to generate a permute control vector based on a byte mask. Ensure the VSX facility is enabled by checking and setting the MSR.VSX bit. The operation mode (expansion or compression) and endianness (big or little) are determined by the IMM field. Be cautious with alignment as VSR registers must be properly aligned for operations.


Summary: Generates a permute control vector (PCV) based on the halfword mask in VSR[VRB+32].

The instruction generates a permute control vector (PCV) based on the halfword mask in VSR[VRB+32] and stores it in VSR[XT]. The operation depends on the value of IMM.

if MSR.VSX=0 then VSX_Unavailable()

if IMM=0b00000 then do  // Big-Endian expansion
    j ←0
    do i = 0 to 7
        if VSR[VRB+32].hword[i].bit[0]=1 then do
            VSR[XT].hword[i].byte[0] ←2×j + 0x00
            VSR[XT].hword[i].byte[1] ←2×j + 0x01
            j ←j + 1
        end else do
            VSR[XT].hword[i].byte[0] ←2×i + 0x10
            VSR[XT].hword[i].byte[1] ←2×i + 0x11
        end
    end
end else if IMM=0b00001 then do  // Big-Endian compression
    j ←0
    do i = 0 to 7
        if VSR[VRB+32].hword[i].bit[0]=1 then do
            VSR[XT].hword[j].byte[0] ←2×i + 0x00
            VSR[XT].hword[j].byte[1] ←2×i + 0x01
            j ←j + 1
        end
    end
    do i = j to 7
        VSR[XT].hword[i] ←0xUUUU
    end
end else if IMM=0b00010 then do  // Little-Endian expansion
    j ←0
    do i = 0 to 7
        if VSR[VRB+32].hword[7-i].bit[0]=1 then do
            VSR[XT].hword[7-i].byte[1] ←2×j + 0x00
            VSR[XT].hword[7-i].byte[0] ←2×j + 0x01
            j ←j + 1
        end else do
            VSR[XT].hword[7-i].byte[1] ←2×i + 0x10
            VSR[XT].hword[7-i].byte[0] ←2×i + 0x11
        end
    end
end else if IMM=0b00011 then do  // Little-Endian compression
    j ←0
    do i = 0 to 7
        if VSR[VRB+32].hword[7-i].bit[0]=1 then do
            VSR[XT].hword[7-j].byte[1] ←2×i + 0x00
            VSR[XT].hword[7-j].byte[0] ←2×i + 0x01
            j ←j + 1
        end
    end
    do i = j to 7
        VSR[XT].hword[7-i] ←0xUUUU
    end
end

This instruction is used for generating permute control vectors based on a halfword mask. Ensure that the VSX facility is enabled in the MSR register to avoid an exception. The operation mode (expansion or compression) and byte order (big-endian or little-endian) are determined by the IMM field. Be cautious with alignment as it affects how the data is interpreted within the vector registers.


Summary: Generates a permute control vector (PCV) based on the word mask in VSR[VRB+32] and stores it in VSR[XT].

The instruction generates a permute control vector (PCV) based on the word mask in VSR[VRB+32] and stores it in VSR[XT]. The PCV is used to enable a left-indexed or right-indexed permute operation.

if MSR.VSX=0 then VSX_Unavailable()

Let TX be the value 32×TX + T.

if IMM=0b00000 then do  // Big-Endian expansion
    j ←0
    do i = 0 to 3
        if VSR[VRB+32].word[i].bit[0]=1 then do
            VSR[XT].word[i].byte[0] ←4×j + 0x00
            VSR[XT].word[i].byte[1] ←4×j + 0x01
            VSR[XT].word[i].byte[2] ←4×j + 0x02
            VSR[XT].word[i].byte[3] ←4×j + 0x03
            j = j + 1
        end
        else do
            VSR[XT].word[i].byte[0] ←4×i + 0x10
            VSR[XT].word[i].byte[1] ←4×i + 0x11
            VSR[XT].word[i].byte[2] ←4×i + 0x12
            VSR[XT].word[i].byte[3] ←4×i + 0x13
        end
    end
end
else if IMM=0b00001 then do  // Big-Endian compression
    j ←0
    do i = 0 to 3
        if VSR[VRB+32].word[i].bit[0]=1 then do
            VSR[XT].word[j].byte[1] ←4×i + 0x01
            VSR[XT].word[j].byte[2] ←4×i + 0x02
            VSR[XT].word[j].byte[3] ←4×i + 0x03
            j ←j + 1
        end
    end
    do i = j to 3
        VSR[XT].word[i] ←0xUUUU_UUUU
    end
end
else if IMM=0b00010 then do  // Little-Endian expansion
    j ←0
    do i = 0 to 3
        if VSR[VRB+32].word[3-i].bit[0]=1 then do
            VSR[XT].word[3-i].byte[3] ←4×j + 0x00
            VSR[XT].word[3-i].byte[2] ←4×j + 0x01
            VSR[XT].word[3-i].byte[1] ←4×j + 0x02
            VSR[XT].word[3-i].byte[0] ←4×j + 0x03
            j ←j + 1
        end
        else do
            VSR[XT].word[3-i].byte[3] ←4×i + 0x10
            VSR[XT].word[3-i].byte[2] ←4×i + 0x11
            VSR[XT].word[3-i].byte[1] ←4×i + 0x12
            VSR[XT].word[3-i].byte[0] ←4×i + 0x13
        end
    end
end
else if IMM=0b00011 then do  // Little-Endian compression
    j ←0
    do i = 0 to 3
        if VSR[VRB+32].word[3-i].bit[0]=1 then do
            VSR[XT].word[3-j].byte[3] ←4×i + 0x00
            VSR[XT].word[3-j].byte[2] ←4×i + 0x01
            VSR[XT].word[3-j].byte[1] ←4×i + 0x02
            VSR[XT].word[3-j].byte[0] ←4×i + 0x03
            j ←j + 1
        end
    end
    do i = j to 3
        VSR[XT].word[3-i] ←0xUUUU_UUUU
    end
end


Summary: Generates a permute control vector (PCV) based on the doubleword mask in VSR[VRB+32] and stores it in VSR[XT].

The instruction generates a permute control vector (PCV) based on the doubleword mask in VSR[VRB+32] and stores it in VSR[XT]. The operation depends on the value of IMM.

if MSR.VSX=0 then VSX_Unavailable()
XT ←32×TX+T
if IMM=0b00000 then do  // Big-Endian expansion
   j ←0
do i = 0 to 1
   if VSR[VRB+32].dword[i].bit[0]=1 then do
      VSR[XT].dword[i].byte[0] ←8×j + 0x00
      VSR[XT].dword[i].byte[1] ←8×j + 0x01
      VSR[XT].dword[i].byte[2] ←8×j + 0x02
      VSR[XT].dword[i].byte[3] ←8×j + 0x03
      VSR[XT].dword[i].byte[4] ←8×j + 0x04
      VSR[XT].dword[i].byte[5] ←8×j + 0x05
      VSR[XT].dword[i].byte[6] ←8×j + 0x06
      VSR[XT].dword[i].byte[7] ←8×j + 0x07
      j ←j + 1
   end
   else do
      VSR[XT].dword[i].byte[0] ←8×i + 0x10
      VSR[XT].dword[i].byte[1] ←8×i + 0x11
      VSR[XT].dword[i].byte[2] ←8×i + 0x12
      VSR[XT].dword[i].byte[3] ←8×i + 0x13
      VSR[XT].dword[i].byte[4] ←8×i + 0x14
      VSR[XT].dword[i].byte[5] ←8×i + 0x15
      VSR[XT].dword[i].byte[6] ←8×i + 0x16
      VSR[XT].dword[i].byte[7] ←8×i + 0x17
   end
end
do i = j to 1
   VSR[XT].dword[i] ←0xUUUU_UUUU_UUUU_UUUU
end
else if IMM=0b00001 then do  // Big-Endian compression
   j ←0
do i = 0 to 1
   if VSR[VRB+32].dword[i].bit[0]=1 then do
      VSR[XT].dword[j].byte[0] ←8×i + 0x00
      VSR[XT].dword[j].byte[1] ←8×i + 0x01
      VSR[XT].dword[j].byte[2] ←8×i + 0x02
      VSR[XT].dword[j].byte[3] ←8×i + 0x03
      VSR[XT].dword[j].byte[4] ←8×i + 0x04
      VSR[XT].dword[j].byte[5] ←8×i + 0x05
      VSR[XT].dword[j].byte[6] ←8×i + 0x06
      VSR[XT].dword[j].byte[7] ←8×i + 0x07
   end
   j ←j + 1
end
do i = j to 1
   VSR[XT].dword[i] ←0xUUUU_UUUU_UUUU_UUUU
end
else if IMM=0b00010 then do  // Little-Endian expansion
   j ←0
do i = 0 to 1
   if VSR[VRB+32].dword[1-i].bit[0]=1 then do
      VSR[XT].dword[1-i].byte[7] ←8×j + 0x00
      VSR[XT].dword[1-i].byte[6] ←8×j + 0x01
      VSR[XT].dword[1-i].byte[5] ←8×j + 0x02
      VSR[XT].dword[1-i].byte[4] ←8×j + 0x03
      VSR[XT].dword[1-i].byte[3] ←8×j + 0x04
      VSR[XT].dword[1-i].byte[2] ←8×j + 0x05
      VSR[XT].dword[1-i].byte[1] ←8×j + 0x06
      VSR[XT].dword[1-i].byte[0] ←8×j + 0x07
   end
   j ←j + 1
end
do i = j to 1
   VSR[XT].dword[i] ←0xUUUU_UUUU_UUUU_UUUU
end
else if IMM=0b00011 then do  // Little-Endian compression
   j ←0
do i = 0 to 1
   if VSR[VRB+32].dword[1-i].bit[0]=1 then do
      VSR[XT].dword[1-j].byte[7] ←8×i + 0x00
      VSR[XT].dword[1-j].byte[6] ←8×i + 0x01
      VSR[XT].dword[1-j].byte[5] ←8×i + 0x02
      VSR[XT].dword[1-j].byte[4] ←8×i + 0x03
      VSR[XT].dword[1-j].byte[3] ←8×i + 0x04
      VSR[XT].dword[1-j].byte[2] ←8×i + 0x05
      VSR[XT].dword[1-j].byte[1] ←8×i + 0x06
      VSR[XT].dword[1-j].byte[0] ←8×i + 0x07
   end
   j ←j + 1
end
do i = j to 1
   VSR[XT].dword[i] ←0xUUUU_UUUU_UUUU_UUUU
end
end

This instruction is used to generate a permute control vector (PCV) based on a doubleword mask. Ensure that the VSX facility is enabled in the MSR register before using this instruction. The operation mode (expansion or compression) is determined by the IMM field. Be cautious with alignment and ensure that the input and output vectors are correctly set up to avoid undefined behavior.


Vector Count Leading Zero Least Significant Bits Byte

Summary: Counts the number of contiguous leading byte elements in VSR[VRB+32] having a zero least-significant bit.

The instruction counts the number of contiguous leading byte elements in VSR[VRB+32] that have a zero least-significant bit and places the count into GPR[RT].

if MSR.VEC=0 then
    Vector_Unavailable()
count ←0
do while count < 16
    if VSR[VRB+32].byte[count].bit[7]=1 then
        break
    count ←count + 1
end
GPR[RT] ←EXTZ64(count)

This instruction is useful for counting leading zero least significant bits in a vector register. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. The operation processes 16 bytes, and the result is stored in a general-purpose register. Be cautious of alignment requirements when accessing vector registers.


Vector Count Trailing Zero Least Significant Bits Byte

Summary: Counts the number of trailing zero bits in each byte element of a vector.

Counts the number of trailing zero bits in each byte of the source vector and stores the scalar result (the count from the least-significant byte) in a GPR. This VMX instruction updates CR6 based on the result to indicate whether all bytes contain zero or not.

Use vctzlsbb to efficiently count the number of contiguous trailing zero bytes with a zero least-significant bit. Ensure that the input vector is properly aligned and that you have the necessary privileges to execute this instruction. The result is stored in a general-purpose register, so be mindful of register usage and dependencies.


Summary: Isolates the leftmost element that matches the condition.

Searches the source vector vB from left to right for the first null byte (0x00) and isolates it, placing the result in vD with all bytes after the found null set to zero. Updates CR6 to indicate whether a null byte was found. This VMX instruction operates on byte elements.

vD ← isolate_left_null_byte(vB); CR6 ← null_byte_found_flag


Summary: Isolates the rightmost element that matches the condition.

Searches the source vector vB from right to left for the first null byte (0x00) and isolates it, placing the result in vD with all bytes before the found null set to zero. Updates CR6 to indicate whether a null byte was found. This VMX instruction operates on byte elements.

vD ← isolate_right_null_byte(vB); CR6 ← null_byte_found_flag


VSX Vector Splat Immediate 32-bit Double Index

Summary: Splats a 32-bit immediate into a doubleword index.

Splats a sign-extended 32-bit immediate value into the doubleword at index IX within VSR XT. IX selects either the upper (0) or lower (1) doubleword; the 32-bit immediate is sign-extended to 64 bits and replicated. This is a VSX instruction that does not update condition flags.

imm64 ← SignExtend(IMM, 32)
if IX = 0 then
  XT[0:63] ← imm64
else
  XT[64:127] ← imm64

Use xxsplti32dx to initialize a VSX vector with a repeated 32-bit immediate value. Ensure the immediate value fits within 32 bits; otherwise, it will be truncated. This instruction is available in all privilege levels and does not raise exceptions for valid inputs.


Summary: Copies an immediate byte value into each byte element of a vector register.

Splats an 8-bit immediate byte value across all 16 byte elements of VSR XT. Each byte of XT is set to the same immediate value, providing an efficient way to initialize a vector with a constant. This is a VSX instruction that does not update condition flags.

byte_val ← IMM[0:7]
for i ← 0 to 15
  XT[i * 8 : i * 8 + 7] ← byte_val

The xxspltib instruction is used to fill a VSX vector register with an immediate byte value. Ensure that the appropriate privilege level (VSX or Vector) is enabled in the MSR register, otherwise, it will raise an exception. This instruction is useful for initializing vectors with a constant value.


Summary: Checks the hash of the Return Address Stack (ROP Protection).

Verifies the integrity of a hashed Return Address Stack entry at the address in RA to provide Return-Oriented Programming (ROP) protection. The instruction reads the hash stored at RA, recomputes it, and compares against an expected value; if they do not match, a program interrupt is triggered. This is a privileged instruction requiring supervisor-level access.

hash_addr ← RA
stored_hash ← [hash_addr]
expected_hash ← ComputeHash(RA)
if stored_hash ≠ expected_hash then
  TrapException()

If RA=0, the instruction form is invalid. EA must be a multiple of 8.


Summary: Checks the hash value of a memory location against a computed hash.

oﬀset

Offset to be added to the contents of RA to form the effective address EA.

The HashDigest function is used to compute a hash value from the contents of RA, RB, and the hypervisor privileged SPR HASHPKEYR. This instruction compares the computed hash with the doubleword in storage addressed by EA. If they are unequal, a system trap handler is invoked.

DW <- 32 * DX + D
d <- EXTS(0b111_1111 || DW || 0b000)
EA <- (RA) + d
temp <- HashDigest((RA), (RB), (HASHPKEYR))
temp1 <- MEM(EA, 8)
if (temp != temp1) then TRAP

See the Programming Notes that appear in the description of hashst and hashchk in Section 3.3.17.2 of Book I.


Summary: Stores the computed doubleword hash value to a doubleword storage location.

Offset to be added to the base address in RA

offset

Offset to be added to the base address in RB

Computes and stores a 64-bit hash value derived from the contents at the memory address RA. The hash is calculated based on the address and associated data, then written to the doubleword storage location at RA. This is a privileged instruction used for Return-Oriented Programming (ROP) protection.

hash_addr ← RA
hash_value ← ComputeHash(hash_addr)
[hash_addr] ← hash_value

The EA specified by the Hash instructions - (RA) + EXTS(0b111_1111 || DW || 0b000) - can be expressed as (RA) -(64-DW)×8. Therefore the Hash instructions can only access one of the 64 doublewords preceding the address provided by RA.


Summary: Privileged version of hash store.

Privileged instruction that stores a hash value to the address specified in RA. This instruction is used by privileged software (such as the hypervisor) to update hash tables for memory protection or integrity checking. Requires hypervisor privilege level and may affect storage subsystem state.

The hashstp instruction is used for storing a doubleword into memory while verifying its integrity against a previously computed hash. It requires privileged access and must be executed in a context where the MSR register allows such operations. Ensure that the effective address (EA) is correctly calculated and aligned to avoid exceptions. If the stored value does not match the expected hash, a trap will occur, necessitating proper error handling.


Summary: Loads a paired single from memory (Embedded/Legacy).

Loads a pair of single-precision floating-point values from memory into an FPR, with optional quantization/scaling applied. The W field controls element width, and the I field specifies the scale factor applied during load. This is a legacy VMX/AltiVec instruction primarily found on embedded PowerPC implementations.

EA ← (RA = 0 ? 0 : GPR[RA]) + D
data ← [EA] (quantized width W, scale I)
FPR[FRT] ← float32_pair(data)


Summary: Stores a paired single to memory (Embedded/Legacy).

Stores a pair of single-precision floating-point values from an FPR to memory, with optional quantization/scaling applied. The W field controls element width, and the I field specifies the scale factor applied during store. This is a legacy VMX/AltiVec instruction primarily found on embedded PowerPC implementations.

EA ← (RA = 0 ? 0 : GPR[RA]) + D
data ← quantize(FPR[FRS], width W, scale I)
[EA] ← data


Summary: Adds two paired singles.

Adds two pairs of single-precision floating-point values element-wise, storing the result in FRT. Each of the two single-precision elements in FRA and FRB is added independently. May set FPSCR status flags if exceptions occur.

FPR[FRT].upper ← FPR[FRA].upper + FPR[FRB].upper
FPR[FRT].lower ← FPR[FRA].lower + FPR[FRB].lower


Summary: Subtracts two paired singles.

Subtracts two pairs of single-precision floating-point values element-wise, storing the result in FRT. Each of the two single-precision elements in FRB is subtracted from FRA independently. May set FPSCR status flags if exceptions occur.

FPR[FRT].upper ← FPR[FRA].upper - FPR[FRB].upper
FPR[FRT].lower ← FPR[FRA].lower - FPR[FRB].lower


Summary: Multiplies two paired singles.

Multiplies two pairs of single-precision floating-point values element-wise, storing the result in FRT. Each of the two single-precision elements in FRA and FRC is multiplied independently. May set FPSCR status flags if exceptions occur.

FPR[FRT].upper ← FPR[FRA].upper × FPR[FRC].upper
FPR[FRT].lower ← FPR[FRA].lower × FPR[FRC].lower


Summary: Multiply-Add on paired singles.

Performs multiply-add on two pairs of single-precision floating-point values element-wise, computing FRA × FRC + FRB and storing the result in FRT. All three source registers contribute to the operation, with each element pair computed independently. May set FPSCR status flags if exceptions occur.

FPR[FRT].upper ← FPR[FRA].upper × FPR[FRC].upper + FPR[FRB].upper
FPR[FRT].lower ← FPR[FRA].lower × FPR[FRC].lower + FPR[FRB].lower


Load Byte and Zero External Process ID Indexed

Summary: Loads a byte using the External PID (for OS kernels accessing user memory).

Loads a byte from memory using the External Process ID (EPID), which allows privileged code to access memory belonging to an external process. The effective address is computed from RA and RB, and the loaded byte is zero-extended into the target GPR. This is an embedded/privileged instruction used by operating system kernels.


Load Halfword and Zero External Process ID Indexed

Summary: Loads a halfword using the External PID.

Loads a halfword (16-bit value) from memory using an address formed by adding RA and RB, performing the load using the External PID for address translation in embedded environments. The loaded halfword is zero-extended and placed into RT. No condition flags are affected.


Load Word and Zero External Process ID Indexed

Summary: Loads a word using the External PID.

Loads a word (32-bit value) from memory using an address formed by adding RA and RB, performing the load using the External PID for address translation in embedded environments. The loaded word is zero-extended and placed into RT. No condition flags are affected.


Summary: Stores a byte using the External PID.

Stores a byte (8-bit value) to memory using an address formed by adding RA and RB, performing the store using the External PID for address translation in embedded environments. The least significant byte of RS is written to memory. No condition flags are affected.


Store Halfword External Process ID Indexed

Summary: Stores a halfword using the External PID.

Stores a halfword (16-bit value) to memory using an address formed by adding RA and RB, performing the store using the External PID for address translation in embedded environments. The least significant halfword of RS is written to memory. No condition flags are affected.


Summary: Stores a word using the External PID.

Stores a word (32-bit value) to memory using an address formed by adding RA and RB, performing the store using the External PID for address translation in embedded environments. The least significant word of RS is written to memory. No condition flags are affected.


Summary: Reads a performance monitor register (Embedded).

Moves a value from a performance monitor register identified by PMRN into the general-purpose register RT. This instruction is available only in embedded Power ISA implementations with performance monitoring support and typically requires supervisor privilege. No condition flags are affected.


Summary: Writes a performance monitor register (Embedded).

Moves a value from the general-purpose register RS into the performance monitor register identified by PMRN. This instruction is available only in embedded Power ISA implementations with performance monitoring support and typically requires supervisor privilege. No condition flags are affected.


Summary: Clears a cache line lock.

Clears the lock bit associated with the cache line at the address formed by adding RA and RB. The CT field specifies the cache target (L1, L2, etc.). This embedded instruction is typically used in multiprocessor environments to release a previously locked cache line. No condition flags are affected.


Summary: Clears an instruction cache line lock.

Clears the instruction cache block lock at the address computed from RA + RB. The CT field specifies the cache block class to unlock. This is an embedded (SPE/VLE) instruction used in cache management and requires careful synchronization in multi-threaded environments.

EA ← (RA) + (RB)
Clear_ICacheBlockLock(EA, CT)


Summary: Waits for a specific implementation event.

Suspends instruction execution until an implementation-dependent event occurs. The exact event is determined by the processor implementation and may involve power-management, interrupt handling, or other microarchitectural conditions. This is a Base ISA instruction with no operands.


Summary: Waits until a reservation is lost (Multithreading sync).

Suspends instruction execution until the reservation created by a lwarx/ldarx instruction is lost. This synchronization primitive is used in multi-threaded code to wait for concurrent modifications to shared memory locations. The reservation is typically lost when another processor executes a store to the reserved address or on context switches.

Use waitrsv when you need to ensure that a storage location has not been modified by another processor since it was reserved. This instruction is useful in multi-processor environments where data consistency is critical. Ensure that the address is correctly aligned and that the reservation is properly set before using this instruction. If the reservation is lost, the instruction will return true; otherwise, it returns false.


Summary: Ensures that load/store instructions preceding the EIEIO complete before those following it. Used for Memory-Mapped I/O synchronization.

Enforces in-order completion of all load and store instructions issued before it with respect to all load and store instructions issued after it. This is essential for memory-mapped I/O synchronization and weak-ordering memory models. No condition register or status fields are affected.

The eieio instruction is intended for use in doing memory-mapped I/O. Because loads, and separately stores, to storage that is both Caching Inhibited and Guarded are performed in program order (see Section 1.7.1, “Storage Access Ordering ” on page 973), eieio is needed for such storage only when loads must be ordered with respect to stores.


Summary: Adds the contents of two floating-point registers and places the result into another register.

if 'fadd' then
    FRT <- (FRA) + (FRB)
else if 'fadd.' then
    FRT <- (FRA) + (FRB)
    CR1 <- result class and sign

The floating-point operand in register FRA is added to the floating-point operand in register FRB. The result is rounded to the target precision under control of RN and placed into register FRT.

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.


Summary: Multiplies the contents of two floating-point registers and places the result into another register.

if 'fmul' then
    FRT <- (FRA) * (FRC)
else if 'fmul.' then
    FRT <- (FRA) * (FRC)

The floating-point operand in register FRA is multiplied by the floating-point operand in register FRC. The result is rounded to the target precision under control of RN and placed into register FRT.


Summary: Performs (A * C) + B with a single rounding step. (The classic FMA).

FRT ←[(FRA)×(FRC)] + (FRB)
if 'fmadd.' then
    CR1 <- result class and sign

The instruction multiplies the contents of register FRA by the contents of register FRC, then adds the result to the contents of register FRB. The final result is placed into register FRT.


Summary: Compares two floating-point registers and sets the Condition Register (CR) field. Does not trap on NaNs.

if (FRA) is NaN or (FRB) is NaN then
  CR[BF] ← 0b0001
  FPSCR[VXCC] ← 1
elif (FRA) < (FRB) then
  CR[BF] ← 0b1000
elif (FRA) > (FRB) then
  CR[BF] ← 0b0100
else
  CR[BF] ← 0b0010

Compares two floating-point registers (FRA and FRB) and writes the result (less-than, equal, greater-than, or unordered) into the specified CR field (BF). Unlike fcmpo, this instruction does not trap on signaling NaN operands. The FPSCR may record VXCC (invalid operation) for signaling NaNs.

The fcmpu instruction is commonly used for unordered floating-point comparisons, which are useful in scenarios where NaN values need to be handled gracefully. Be cautious with signaling NaNs (SNaNs), as they can trigger exceptions and set the VXSNAN flag. Ensure that the FPSCR and CR registers are properly managed to handle comparison results and exceptions correctly.


Floating Convert with round Double-Precision To Signed Word format

Summary: Converts a float to a 32-bit signed integer (using the current rounding mode) and stores it in the lower half of the FPR.

round_mode ← FPSCRRN
tgt_precision ← '32-bit signed integer'

sign ← (FRB)0
if (FRB)1:11 = 2047 and (FRB)12:63 = 0 then goto Infinity Operand
if (FRB)1:11 = 2047 and (FRB)12 = 0 then goto SNaN Operand
if (FRB)1:11 = 2047 and (FRB)12 = 1 then goto QNaN Operand
if (FRB)1:11 > 1086 then goto Large Operand

if (FRB)1:11 > 0 then exp ← (FRB)1:11 - 1023   /* exp - bias */
if (FRB)1:11 = 0 then exp ← -1022
if (FRB)1:11 > 0 then frac0:64 ← 0b01 || (FRB)12:63 || 110   /* normal */
if (FRB)1:11 = 0 then frac0:64 ← 0b00 || (FRB)12:63 || 110   /* denormal */

rbit || xbit ← 0b00
for i=1,63-exp    /* do the loop 0 times if exp = 63 */
    frac0:64 || rbit || xbit ← 0b0 || frac0:64 || (rbit | xbit)
end

FRT ← Round Integer(sign, frac0:64, gbit, rbit, xbit, round_mode)

The instruction converts the double-precision floating-point value in FRB to a signed word using the specified rounding mode. If the result is out of range, it saturates to the maximum or minimum signed integer value.

FPSCR, (FR, FI, FX, XX, VXSNAN, VXCVI), CR1, (if, Rc=1), CR0


Summary: Conditionally copies RA or RB to RT based on a CR bit. (Equivalent to C ternary operator 'cond ? a : b').

BIT ← CR[BC]
if BIT = 1 then
  RT ← (RA)
else
  RT ← (RB)

Conditionally selects between RA and RB based on the value of a single bit in the Condition Register, writing the result to RT. If the CR bit BC is 1, RT ← RA (or 0 if RA=0); otherwise RT ← RB. This provides a branch-free ternary operation.

isel is used for conditional moves based on the condition register.


Summary: Invalidates the instruction cache block associated with the address. Critical for self-modifying code or JITs.

EA ← (RA) + (RB)
Invalidate_ICacheBlock(EA)

Invalidates the instruction cache block that contains the address RA + RB, forcing subsequent instruction fetches from that block to reload from lower cache levels or memory. Essential for self-modifying code and JIT compilers. May affect performance on some implementations.

Use icbi to ensure that changes to executable code in memory are reflected in the instruction cache. This is crucial after modifying code at runtime. Ensure the address is properly aligned; typically, block boundaries align with cache line sizes. This instruction operates at user privilege level and may raise an exception if the address is invalid or access is denied.


Summary: Ensures that all instructions preceding the isync instruction have completed before it completes, and that no subsequent instructions are initiated until after the isync instruction completes.

Executing an isync instruction ensures that all instructions preceding the isync instruction have completed before the isync instruction completes, and that no subsequent instructions are initiated until after the isync instruction completes. It also ensures that all instruction cache block invalidations caused by icbi instructions preceding the isync instruction have been performed with respect to the processor executing the isync instruction, and then causes any prefetched instructions to be discarded.

Except as described in the preceding sentence, the isync instruction may complete before storage accesses associated with instructions preceding the isync instruction have been performed.


Summary: Copies the contents of one Condition Register field to another. Used to save comparison results.

The contents of Condition Register field BFA are copied to Condition Register field BF.

Use mcrf to copy condition register fields, ensuring BFA and BF are valid. This instruction operates at user privilege level and does not raise exceptions under normal conditions.


Summary: Copies the entire 32-bit Condition Register into a General Purpose Register.

Moves the entire 32-bit Condition Register into the target GPR. All eight 4-bit CR fields (CR0-CR7) are copied as a single 32-bit value. No condition register or status fields are modified by this operation.

The mfcr instruction is commonly used to save the current state of the condition register for later use, such as before a function call or when implementing exception handling. It's important to note that this instruction does not affect any flags in the condition register itself; it merely copies its contents. Ensure that the target general-purpose register RT is properly aligned and accessible at the privilege level where the instruction is executed.


Summary: Copies bits from a register into the Condition Register, updated only the fields specified by the mask (FXM).

do i = 0 to 7
  if FXM[i] = 1 then
    CR[4*i:4*i+3] ← RS[4*i:4*i+3]
end do

Moves bits from the source register (RS) into the Condition Register (CR), updating only the fields specified by the mask FXM. Each bit in FXM corresponds to one of the eight 4-bit CR fields; a 1 indicates that field should be updated. This instruction affects the CR as specified by the mask, with no other status register modifications.

The mtcrf instruction is used to move specific fields of the Condition Register (CR) into general-purpose registers. It's important to note that if the SPR number is between 808 and 811, the instruction acts as a no-op. Ensure that the FXM field correctly specifies which CR fields to transfer to avoid unintended behavior.


Summary: Adds two 128-bit Quad-Precision floating-point numbers held in VSX registers (pairs).

FPR[vD:vD+1] ← quad_precision(FPR[vA:vA+1] + FPR[vB:vB+1])
FPSCR ← updated with exception flags

Adds two 128-bit quad-precision floating-point numbers held in VSX register pairs and stores the result in another VSX register pair. The operation uses full precision during computation and rounds the result to quad-precision format. This instruction requires VSX support and updates FPSCR with exception flags as appropriate.

The xsaddqp instruction is used for adding two quad-precision floating-point numbers. Ensure that the VSX feature is enabled by checking and setting MSR.VSX. Be aware of special cases like NaNs, which can set flags such as vxsnan_flag or vxisi_flag. The result is stored in VSR[VT+32], and proper rounding and exception handling are managed internally.


Summary: Multiplies two quad-precision floating-point numbers and rounds the result to odd.

FPR[vD:vD+1] ← quad_precision_round_to_odd(FPR[vA:vA+1] × FPR[vB:vB+1])
FPSCR ← updated with exception flags

Multiplies two 128-bit quad-precision floating-point numbers held in VSX register pairs and stores the result in another VSX register pair, rounding to odd. The operation computes the full product and rounds using the round-to-odd mode to ensure correct rounding behavior. This instruction requires VSX support and updates FPSCR with exception flags.

The xsmulqp instruction handles special cases like NaNs and infinities, setting flags accordingly. Ensure proper handling of these conditions to avoid unexpected results. The instruction operates at the VSX privilege level and may raise exceptions for invalid operations. Performance can vary based on input values and rounding modes.


VSX Scalar Convert Double-Precision to Quad-Precision format

Summary: Converts a double-precision floating-point value to a quad-precision floating-point value.

FPR[vD:vD+1] ← convert_to_quad_precision(FPR[vB])
FPSCR ← updated with exception flags

Converts a double-precision floating-point value held in a VSX register to quad-precision format and stores the result in a VSX register pair. The conversion is exact since double-precision has fewer significant bits than quad-precision. This instruction requires VSX support and updates FPSCR with exception flags as needed.

FPSCR.FPRF, FPSCR.FX, FPSCR.VXSNAN, FPSCR.FR, FPSCR.FI

This instruction is used to convert a double-precision floating-point number to a quad-precision format. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register, otherwise, an exception will be raised. Be cautious with signaling NaNs (SNaNs), as they are converted to quiet NaNs and may trigger exceptions based on the FPSCR settings.


Summary: Adds two 64-bit Decimal Floating Point (DFP) numbers. Used in financial calculations to avoid rounding errors.

FPR[FRT] ← DFP_add(FPR[FRA], FPR[FRB])
FPSCR ← updated with exception flags

Adds two 64-bit Decimal Floating Point (DFP) numbers held in FPRs and stores the result in another FPR. DFP arithmetic maintains decimal precision without binary rounding errors, making it essential for financial applications. This instruction updates FPSCR with exception flags and condition codes based on the result.

The dadd instruction is used for adding two decimal floating-point numbers. Ensure that the source registers FRA and FRB are correctly aligned and contain valid decimal floating-point values. The result will be rounded according to the rounding mode specified in the FPSCR register's DRN field. Be aware of potential exceptions such as overflow or underflow, which may require handling in your code.


Summary: Multiplies the contents of two DFP registers and places the result in another DFP register.

FPR[FRT] ← DFP_multiply(FPR[FRA], FPR[FRB])
FPSCR ← updated with exception flags
if Rc = 1 then CR0 ← condition_code(FPR[FRT])

Multiplies two 64-bit Decimal Floating Point (DFP) numbers held in FPRs and stores the result in another FPR. DFP multiplication preserves decimal precision required for financial calculations. The instruction can optionally update CR0 (via the dot form); FPSCR is always updated with exception flags and rounding information.

dmul[q][.] are treated as Floating-Point instructions in terms of resource availability.


Summary: Adjusts the exponent of a DFP number to match a reference. Critical for aligning decimal points before addition.

0 | FRT | FRA | FRB | RMC | Rc | 3 | 21 | 23

FPR[FRT] ← DFP_quantize(FPR[FRA], FPR[FRB], RMC)
FPSCR ← updated with exception flags
if Rc = 1 then CR0 ← condition_code(FPR[FRT])

Adjusts the exponent of a 64-bit DFP number to match a reference exponent, rounding the significand as needed according to the RMC control bits. This operation is essential for aligning decimal points before addition in financial calculations. The instruction can optionally update CR0 via the dot form; FPSCR is always updated with exception flags.

FPSCR, FPRF, FR, FI, FX, XX, VXSNAN, VXCVI, CR1

DFP Quantize can be used to adjust one DFP value to a form having the same exponent as another DFP value. If the adjustment requires the significand to be shifted left and would cause overflow from the most significant digit, the result is a default QNaN.


Summary: Reverses bytes within each halfword (Endian Swap).

Reverses the order of bytes within each halfword (16-bit element) of the source vector, effectively performing a 16-bit endianness swap. The operation processes all 8 halfwords in the 128-bit vector independently. This instruction requires VMX/AltiVec support and does not affect any status registers.

for i = 0 to 7 do
  VR[vD][i*16:i*16+15] ← reverse_bytes(VR[vB][i*16:i*16+15])
end for


Summary: Reverses bytes within each word.

Reverses the byte order within each 32-bit word of the source vector and stores the result in the destination vector. This instruction operates on four words in parallel across the 128-bit vector. No condition flags are affected; this is a VMX/AltiVec instruction.


Summary: Reverses bytes within each doubleword.

Reverses the byte order within each 64-bit doubleword of the source vector and stores the result in the destination vector. This instruction operates on two doublewords in parallel across the 128-bit vector. No condition flags are affected; this is a VMX/AltiVec instruction.


Summary: Reverses bytes within the entire 128-bit quadword.

Reverses the byte order across the entire 128-bit quadword of the source vector and stores the result in the destination vector. This is a single whole-vector operation. No condition flags are affected; this is a VMX/AltiVec instruction.


Summary: Sign-extends each byte in a vector to a word.

For vextsb2w, the signed integer in bits 24:31 of each word element of VSR[VRB+32] is sign-extended and placed into the corresponding word element of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src ← VSR[VRB+32].word[i].bit[24:31]
    VSR[VRT+32].word[i] ← EXTS32(src)
end

This instruction is used to sign-extend the most significant byte of each word in a vector register. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set; otherwise, a Vector Unavailable exception will be raised. The operation processes four words per vector register, and it's important to handle exceptions properly to avoid program crashes.


Summary: Sign-extends halfwords to words.

Sign-extends each of four 16-bit halfwords in the source vector to 32-bit words, filling the upper bits with the sign bit, and stores the result in the destination vector. The instruction operates on the four halfwords in the lower 64 bits of the source. No condition flags are affected; this is a VMX/AltiVec instruction.

This instruction is used to sign-extend the upper half of each word in a vector register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The operation processes four 32-bit words per vector register, and there are no specific alignment requirements for the data.


Summary: Sign-extends the byte elements of a vector register to doublewords.

For vextsb2d, each byte element in VSR[VRB+32] is sign-extended and placed into corresponding doubleword elements in VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    src ← VSR[VRB+32].dword[i].bit[56:63]
    VSR[VRT+32].dword[i] ← EXTS64(src)
end

This instruction is used to sign-extend each byte in the source vector register into a doubleword in the destination vector register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The operation processes two elements per iteration, and there are no specific alignment requirements for the data. This instruction operates at the user privilege level.


Vector Extend Sign Halfword To Doubleword

Summary: Extends the sign of each halfword in a vector to doubleword.

Sign-extends each of two 16-bit halfwords in the source vector to 64-bit doublewords, filling the upper bits with the sign bit, and stores the result in the destination vector. The instruction operates on the two halfwords in the lower 32 bits of the source. No condition flags are affected; this is a VMX/AltiVec instruction.

vD[0:63] ← (vB[0] replicated to 48 bits) || vB[0:15]
vD[64:127] ← (vB[16] replicated to 48 bits) || vB[16:31]

This instruction is used for sign-extending the upper 16 bits of each doubleword in a vector from VRB to VRT. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The operation processes two elements per instruction execution.


Summary: Extends the sign of each word in a vector to doubleword.

The signed integer in bits 32:63 of each doubleword element of VSR[VRB+32] is sign-extended and placed into the corresponding doubleword element of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    src ← VSR[VRB+32].dword[i].bit[32:63]
    VSR[VRT+32].dword[i] ← EXTS64(src)
end

This instruction is used to sign-extend the upper 32 bits of each doubleword in a vector register. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector Unavailable exception will be raised. The operation processes two elements per iteration, and it's important to verify that the source and target registers are correctly aligned for optimal performance.


Summary: Compares each byte of two vector registers and sets the result register to all 1s if the bytes are not equal, otherwise all 0s.

For vcmpneb, each byte of VSR[VRA+32] is compared with the corresponding byte of VSR[VRB+32]. If they are not equal, the corresponding byte in VSR[VRT+32] is set to 0xFF; otherwise, it is set to 0x00.

if MSR.VEC=0 then
    Vector_Unavailable()
all_true ←1
all_false ←1
do i = 0 to 15
    src1 ←VSR[VRA+32].byte[i]
    src2 ←VSR[VRB+32].byte[i]
    if src1 != src2 then do
        VSR[VRT+32].byte[i] ←0xFF
        all_false ←0
    end
    else do
        VSR[VRT+32].byte[i] ←0x00
        all_true ←0
    end
end
if Rc=1 then
    CR.field[6] ←all_true || 0b0 || all_false || 0b0

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.


Summary: Compares the contents of two vector registers and sets the result register to all 1s if the elements are not equal, otherwise all 0s.

For vcmpneh, each halfword element in VSR[VRA+32] is compared with the corresponding element in VSR[VRB+32]. If they are not equal, the corresponding element in VSR[VRT+32] is set to all 1s; otherwise, it is set to all 0s.

if MSR.VEC=0 then
    Vector_Unavailable()
all_true ←1
all_false ←1
do i = 0 to 7
    src1 ←VSR[VRA+32].hword[i]
    src2 ←VSR[VRB+32].hword[i]
    if src1 != src2 then do
        VSR[VRT+32].hword[i] ←0xFFFF
        all_false ←0
    end
    else do
        VSR[VRT+32].hword[i] ←0x0000
        all_true ←0
    end
end
if Rc=1 then
    CR.field[6] ←all_true || 0b0 || all_false || 0b0


Summary: Compares each word of two vector registers and sets the corresponding word in the target vector register to all 1s if the words are not equal, otherwise to all 0s.

For vcmpnew, each word of VSR[VRA+32] is compared with the corresponding word of VSR[VRB+32]. If they are not equal, the corresponding word in VSR[VRT+32] is set to 0xFFFF_FFFF; otherwise, it is set to 0x0000_0000.

if MSR.VEC=0 then
    Vector_Unavailable()
all_true ←1
all_false ←1
do i = 0 to 3
    src1 ←VSR[VRA+32].word[i]
    src2 ←VSR[VRB+32].word[i]
    if src1 != src2 then do
        VSR[VRT+32].word[i] ←0xFFFF_FFFF
        all_false ←0
    end
    else do
        VSR[VRT+32].word[i] ←0x0000_0000
        all_true ←0
    end
end
if Rc=1 then
    CR.field[6] ←all_true || 0b0 || all_false || 0b0


Summary: Adds the contents of two vector registers and updates the destination register with the result modulo 2^128.

For vadduqm, the sum of the contents of vector registers VRA and VRB is placed into vector register VRT. The operation is performed modulo 2^128.

if MSR.VEC=0 then
    Vector_Unavailable()
src1 ←EXTZ(VSR[VRA+32])
src2 ←EXTZ(VSR[VRB+32])
VSR[VRT+32] ←CHOP128(src1 + src2)

This instruction is used for adding two 128-bit unsigned integers stored in vector registers modulo 2^128. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to 1; otherwise, a Vector_Unavailable exception will be raised. The operation does not require any specific alignment for the data being processed.


Vector Subtract Unsigned Quadword Modulo

Summary: Subtracts the contents of two vector registers and places the result in another vector register, modulo operation.

For vsubuqm, the unsigned quadword subtraction of the contents of VSR[VRA+32] and the one's complement of VSR[VRB+32], plus 1, is placed into VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
src1 ←EXTZ(VSR[VRA+32])
src2 ←EXTZ(¬VSR[VRB+32])
VSR[VRT+32] ←CHOP128(src1 + src2 + 1)

This instruction performs an unsigned quadword subtraction modulo operation. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. Be cautious with alignment as it may affect performance or cause exceptions if not properly aligned. The result is placed in the destination vector register, and developers should handle potential overflow conditions appropriately.


Summary: Rotates the contents of a vector register left by a specified number of bits.

Rotates the 128-bit contents of the source vector left by the number of bits specified in the shift-count register and stores the result in the destination vector. The rotate amount is taken modulo 128; bits shifted out the left end wrap around to the right. No condition flags are affected; this is a VMX/AltiVec instruction.

The vrlq instruction is used to perform a left rotation of 128 bits in a vector register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The shift amount is determined by the upper 7 bits of another vector register, so ensure these bits are set correctly to avoid unexpected results.


Summary: Shifts the contents of a vector register left by a specified number of bits.

Shifts the 128-bit contents of the source vector left by the number of bits specified in the shift-count register and stores the result in the destination vector. Bits shifted out the left end are discarded; zeros are shifted in from the right. The shift amount is taken modulo 128. No condition flags are affected; this is a VMX/AltiVec instruction.

shiftAmount ← vB[121:127] mod 128
vD[0:127] ← vA[0:127] << shiftAmount
vD[shiftAmount:127] ← 0 (shifted-in zeros)

Ensure that the Vector Facility (MSR.VEC) is enabled before using vslq; otherwise, a Vector_Unavailable exception will occur. The shift amount is determined by the low-order 7 bits of the second source vector register, and shifts greater than 63 bits will result in zero being placed into the destination register.


Summary: Shifts the contents of a vector register right by a specified number of bits.

Shifts the 128-bit contents of the source vector right by the number of bits specified in the shift-count register and stores the result in the destination vector. Bits shifted out the right end are discarded; zeros are shifted in from the left. The shift amount is taken modulo 128. No condition flags are affected; this is a VMX/AltiVec instruction.

shiftAmount ← vB[121:127] mod 128
vD[0:127] ← vA[0:127] >> shiftAmount
vD[0:(127-shiftAmount)] ← 0 (shifted-in zeros)

The vsrq instruction requires the Vector Facility to be enabled in the MSR register. Ensure that the shift amount is within the range of 0-127 bits to avoid unexpected results. The operation is performed on quadword elements, so alignment considerations are not necessary for this specific instruction.


Summary: Shifts the contents of a vector register right algebraically by a specified number of bits.

Shifts the 128-bit contents of vector register vA right algebraically (with sign extension) by the number of bits specified in the low 7 bits of vB, placing the result in vD. Each of the two 64-bit doublewords in vA is independently shifted right with sign extension. No condition register or status field modifications occur.

shift_amount ← vB[57:63]
vD ← arithmetic_shift_right(vA, shift_amount)

The vsraq instruction is used for performing algebraic right shifts on quadword vector elements. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to 1; otherwise, a Vector_Unavailable exception will be raised. The shift amount is derived from the low-order 7 bits of the second source register, and the result is stored in the destination register. Be cautious with alignment as it affects performance and correctness.


Summary: Multiplies the signed integer values in each word element of two vector registers and places the high-order 32 bits of the 64-bit product into the corresponding word element of a third vector register.

For vmulhsw, the signed integer value in word element i of VSR[VRA+32] is multiplied by the signed integer value in word element i of VSR[VRB+32]. The high-order 32 bits of the 64-bit product are placed into word element i of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ←EXTS(VSR[VRA+32].word[i])
    src2 ←EXTS(VSR[VRB+32].word[i])
    VSR[VRT+32].word[i] ←CHOP32((src1 × src2) >> 32)
end

This instruction is used for multiplying signed integers stored in the high half of vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation processes four 32-bit words per vector register, and the result is the high-order 32 bits of each 64-bit product. Be cautious with overflow conditions as they are not handled by this instruction.


Summary: Multiplies unsigned words, returning the high 32 bits.

Multiplies each pair of unsigned 32-bit words from vA and vB, producing 64-bit products, and places the high 32 bits of each product into the corresponding 32-bit word of vD. Four independent word multiplications are performed. No condition register or status field modifications occur.

The vmulhuw instruction is used for multiplying pairs of unsigned 32-bit integers from two source vectors and storing the high-order 32 bits of each product in a destination vector. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to 1; otherwise, a Vector_Unavailable exception will be raised. This instruction operates on 128-bit vectors, so ensure proper alignment and ordering of data for accurate results.


Summary: Multiplies the signed doublewords of two vector registers and stores the high-order 64 bits of each product in a result vector register.

For vmulhsd, the signed integer value in doubleword element i of VSR[VRA+32] is multiplied by the signed integer value in doubleword element i of VSR[VRB+32]. The high-order 64 bits of the 128-bit product are placed into doubleword element i of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    src1 ←EXTS(VSR[VRA+32].dword[i])
    src2 ←EXTS(VSR[VRB+32].dword[i])
    VSR[VRT+32].dword[i] ←CHOP64((src1 × src2) >> 64)
end

This instruction is used for high-precision multiplication of signed doublewords. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation is performed on each pair of doubleword elements from the input vectors, and only the high 64 bits of the 128-bit product are stored in the result vector. Be cautious of overflow conditions as they can lead to unexpected results.


Vector Multiply High Unsigned Doubleword

Summary: Multiplies unsigned doublewords, returning the high 64 bits.

Multiplies each pair of unsigned 64-bit doublewords from vA and vB, producing 128-bit products, and places the high 64 bits of each product into the corresponding 64-bit doubleword of vD. Two independent doubleword multiplications are performed. No condition register or status field modifications occur.

The vmulhud instruction is used for high-precision multiplication of unsigned doublewords. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. This instruction processes each pair of elements from two source vectors and stores the upper 64 bits of their product in the destination vector. Be cautious with alignment as unaligned access can lead to exceptions.


Summary: vD = vA & ~vB

Performs a bitwise logical AND operation between XT and the bitwise complement of XB, storing the result in XT. The operation is XT ← XT & ~XB on all 128 bits. No condition register or status field modifications occur.

The xxlandc instruction is used for performing a bitwise logical AND operation between the contents of two vector registers, where one register's bits are complemented before the operation. Ensure that the VSX (Vector Scalar Extensions) facility is enabled in the MSR (Machine State Register) to avoid an exception. This instruction operates on 128-bit vectors and requires proper alignment of the input and output registers.


Summary: vD = vA | ~vB

Performs a bitwise logical OR operation between XA and the bitwise complement of XB, storing the result in XT. The operation is XT ← XA | ~XB on all 128 bits. No condition register or status field modifications occur.

The xxlorc instruction is useful for performing bitwise operations on VSX registers. Ensure that the VSX facility is enabled by checking and setting the MSR.VSX bit; otherwise, a VSX_Unavailable exception will occur. The operation is performed on 128-bit vectors, so ensure proper alignment of the data in the registers to avoid unexpected results.


Summary: vD = ~(vA & vB)

Performs a bitwise logical NAND operation on XA and XB, storing the result in XT. The operation is XT ← ~(XA & XB) on all 128 bits. No condition register or status field modifications occur.

The xxlnand instruction is commonly used for bitwise logical operations in VSX registers. Ensure that the source and target registers are properly aligned to avoid alignment faults. This instruction operates at user privilege level, but care should be taken to handle potential exceptions if unaligned access occurs.


Summary: vD = ~(vA ^ vB) (XNOR)

Performs a bitwise logical equivalence (XNOR) operation on XA and XB, storing the result in XT. The operation is XT ← ~(XA ^ XB) on all 128 bits, producing all 1-bits where XA and XB have the same bit value. No condition register or status field modifications occur.

The xxleqv instruction is used to perform a vector logical equivalence operation between two VSX registers. It's useful for comparing vectors and determining where elements are not equal, as it effectively computes the bitwise NOT of the equality result. Ensure that the input registers (XA and XB) are properly aligned and contain valid data to avoid unexpected results. This instruction operates at the user privilege level and does not generate exceptions under normal conditions.


Vector Gather Bits by Bytes by Doubleword

Summary: The contents of bit j of each byte of doubleword element i of VSR[VRB+32] are concatenated and placed into byte j of doubleword element i of VSR[VRT+32].

For vgbbd, the contents of bit j of each byte of doubleword element i of VSR[VRB+32] are concatenated and placed into byte j of doubleword element i of VSR[VRT+32]. An 8-bit × 8-bit bit-matrix transpose is performed on the contents of each doubleword element of VSR[VRB+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    do j = 0 to 7
        do k = 0 to 7
            b ← VSR[VRB+32].dword[i].byte[k].bit[j]
            VSR[VRT+32].dword[i].byte[j].bit[k] ← b
        end
    end
end

The vgbbd instruction performs a bit-matrix transpose on each doubleword element of the source vector, effectively rotating bits within bytes. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This operation requires aligned access to the vector registers. Be cautious with privilege levels; this instruction may require supervisor or hypervisor mode depending on system configuration.


Summary: Deposits bits from source to target under control of a mask (Power10).

The contents of bits in doubleword element i of VSR[VRT+32] corresponding to bits in doubleword element i of VSR[VRB+32] that contain a 0 are set to 0. The contents of the rightmost n bits of doubleword element i of VSR[VRA+32] are placed into doubleword element i of VSR[VRT+32] under control of the mask in doubleword element i of VSR[VRB+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    VSR[VRT+32].dword[i] ←0
    m ←0
    k ←0
    do while(m < 64)
        if VSR[VRB+32].dword[i].bit[63-m]=1 then do
            result ←VSR[VRA+32].dword[i].bit[63-k]
            VSR[VRT+32].dword[i].bit[63-m] ←result
            k ←k + 1
        end
        m ←m + 1
    end
end

The vpdepd instruction is used to deposit bits from one vector register into another based on a mask specified in a third vector register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The operation processes each doubleword element independently, and the alignment of the input vectors must be considered to avoid unexpected results. This instruction is particularly useful for bit manipulation tasks where selective depositing of bits is required.


Summary: Extracts bits from one vector register based on the bit positions specified in another vector register and places them into a third vector register.

Extracts bits from vA based on bit-position indices specified in vB, placing extracted bits into the corresponding doubleword elements of vD. The instruction operates on 64-bit doubleword elements, where vB contains bit indices (0-63) that select which bits from vA are gathered into vD. This is a VMX extension instruction with no condition register or status flag updates.

The vpextd instruction is used to extract bits from one vector register based on the bit positions specified in another vector register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. This operation is performed on each doubleword element of the vectors, so ensure proper alignment and indexing to avoid unexpected results.


Summary: Separates bits of source into two groups based on mask (Power10).

For vcfuged, the bits of VSR[VRA+32] are rearranged based on the mask in VSR[VRB+32]. Bits corresponding to 1s in the mask are placed in the rightmost positions, and other bits are placed in the leftmost positions.

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    ptr0 ←0
    ptr1 ←0
    do j = 0 to 63
        if VSR[VRB+32].dword[i].bit[j]=0b0 then do
            result.bit[ptr0] ←
               VSR[VRA+32].dword[i].bit[j]
            ptr0 ←ptr0 + 1
        end
        if VSR[VRB+32].dword[i].bit[63-j]=1 then do
            result.bit[63-ptr1] ←
               VSR[VRA+32].dword[i].bit[63-j]
            ptr1 ←ptr1 + 1
        end
    end
    VSR[VRT+32].dword[i] ←result
end

The vcfuged instruction rearranges bits in a vector register based on a mask from another vector register. Ensure the Vector Facility is enabled by checking and setting the MSR.VEC bit. The operation processes each doubleword independently, moving bits to the right or left based on the mask's 0s and 1s. Be cautious of alignment issues when accessing vector registers.


Summary: Gathers every Nth bit from a vector register and places it into a general-purpose register.

Gathers every Nth bit (where N is 2-7 as specified by UIM) from vector register vB and packs them into a 64-bit general-purpose register. The bits are gathered starting from bit 0 of vB and compacted into the lower bits of the result; unused upper bits are zeroed. This is a VMX extension instruction with no condition register or status flag updates.

N ← UIM
result ← 0
bit_pos ← 0
for i in 0 to 127 by N do
  if i < 128 then
    result[bit_pos] ← vB[i]
    bit_pos ← bit_pos + 1
vD[0:63] ← result


Summary: Clears the leftmost bytes in a vector register based on the value in a general-purpose register.

The contents of VSR[VRA+32] are placed into VSR[VRT+32] with the leftmost 16-N bytes set to 0, where N is the integer value in GPR[RB] or 16 if GPR[RB] > 15.

if MSR.VEC=0 then
    Vector_Unavailable()
N ← (GPR[RB] > 15) ? 16 : GPR[RB]
do i = 0 to N-1
    VSR[VRT+32].byte[15-i] ← VSR[VRA+32].byte[15-i]
end
do i = N to 15
    VSR[VRT+32].byte[15-i] ← 0x00
end

The vclrlb instruction is useful for clearing the leftmost bytes of a vector register based on the value in GPR[RB]. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. Be cautious with alignment and ensure that the values in VRA and VRT are correctly set to avoid unintended data manipulation.


Summary: Clears the N rightmost bytes of a vector.

Clears the rightmost N bytes of vector register vA (where N is derived from the low 4 bits of RB) and places the result in vD. Bits corresponding to the rightmost N bytes are set to zero while remaining bits are preserved. This is a VMX extension instruction with no condition register or status flag updates.

The vclrrb instruction is useful for clearing the rightmost bytes of a vector register based on a specified count. Ensure that the Vector Facility (MSR.VEC) is enabled to avoid a Vector_Unavailable exception. The value in GPR[RB] should be between 0 and 15; values greater than 15 will result in all bytes being cleared. This instruction operates on vector registers, so ensure proper alignment and privilege level as required by the system.


Summary: Loads 128 bits into two GPRs using a 34-bit offset.

Prefixed load of 128 bits from memory into two consecutive general-purpose registers (RT and RT+1) using a 34-bit signed offset. The effective address is computed as RA + D (if R=0) or the prefixed address. This is a prefixed instruction requiring the Prefixed extension; no condition register or status flags are affected.

if RA = 0 then
  EA ← D
else
  EA ← (RA) + D
RT ← [EA]
RT+1 ← [EA+8]

The plq instruction is used to load a quadword from memory into an even-odd pair of GPRs. Ensure that the effective address (EA) is properly aligned to 16 bytes for optimal performance and to avoid alignment exceptions. This instruction operates at the problem state privilege level, so it cannot be executed in supervisor or hypervisor states.


Summary: Stores 128 bits from two GPRs using a 34-bit offset.

Prefixed store of 128 bits from two consecutive general-purpose registers (RS and RS+1) to memory using a 34-bit signed offset. The effective address is computed as RA + D (if R=0) or the prefixed address. This is a prefixed instruction requiring the Prefixed extension; no condition register or status flags are affected.

if RA = 0 then
  EA ← D
else
  EA ← (RA) + D
[EA] ← RS
[EA+8] ← RS+1

The pstq instruction is used to store a quadword from registers RSp and RSp+1 into memory. It calculates the effective address based on the base register RA, displacement, and current instruction address CIA, depending on the prefix field R. Ensure proper alignment for optimal performance and be aware of byte ordering differences between Big-Endian and Little-Endian systems.


Summary: Merges the high words of two VSX registers into a target VSX register.

Merges the high-order words (words 0 and 1) from VSX registers XA and XB into XT, interleaving them as: XT[0:31] ← XA[0:31], XT[32:63] ← XB[0:31], XT[64:95] ← XA[32:63], XT[96:127] ← XB[32:63]. This is a VSX instruction with no condition register or status flag updates.

The xxmrghw instruction is commonly used to merge high words from two vector registers into a third register. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register; otherwise, a VSX_Unavailable exception will be raised. This instruction operates on 128-bit vectors and requires proper alignment of the input registers for optimal performance.


Summary: Merges low words from two VSRs.

Merges the low-order words (words 2 and 3) from VSX registers XA and XB into XT, interleaving them as: XT[0:31] ← XA[64:95], XT[32:63] ← XB[64:95], XT[64:95] ← XA[96:127], XT[96:127] ← XB[96:127]. This is a VSX instruction with no condition register or status flag updates.

The xxmrglw instruction is commonly used for merging specific word elements from two VSX vectors into a new vector. Ensure that the VSX facility is enabled by checking and setting the appropriate bit in the MSR register. This instruction operates on 128-bit vectors, so source and destination registers must be properly aligned. Be cautious of potential exceptions if the VSX facility is not available or if there are alignment issues with the vector registers.


Summary: Expands the mask from bit 0 of each byte element in the source VSR to all bits in the corresponding element in the target VSR.

Expands the mask bit (bit 0) of each byte element in vB to all 8 bits of the corresponding byte in vD. If vB[byte][0] = 1, the entire byte in vD becomes 0xFF; if vB[byte][0] = 0, the entire byte in vD becomes 0x00. This is a VMX extension instruction with no condition register or status flag updates.

for i in 0 to 15 do
  if vB[i*8] = 1 then
    vD[i*8:(i+1)*8] ← 0xFF
  else
    vD[i*8:(i+1)*8] ← 0x00

The vexpandbm instruction is useful for creating masks where each byte is either all zeros or all ones based on the least significant bit of the corresponding source byte. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. This operation is efficient for processing data in parallel across multiple bytes.


Summary: Expands bits from a GPR mask into a halfword-element vector.

Expands individual bits from a source vector register into halfword-sized elements in the destination vector register, where each bit controls whether the corresponding halfword is set to all 1s or all 0s. This is a VMX instruction with no effect on condition registers or status fields.

for i in 0 to 7 do
  if vB[i] = 1 then
    vD[i*16:(i+1)*16-1] ← 0xFFFF
  else
    vD[i*16:(i+1)*16-1] ← 0x0000
  end if
end for

The vexpandhm instruction is useful for creating masks based on the least significant bit of each halfword in the source vector. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to 1 before using this instruction, as attempting to execute it with VEC=0 will result in a Vector Unavailable exception. This instruction operates on 8 halfwords per vector register and does not require any specific alignment of the data.


Summary: Expands bits from a GPR mask into a word-element vector.

For vexpandwm, each word element of VSR[VRT+32] is set to all 0s or all 1s based on the value of bit 0 of the corresponding word element in VSR[VRB+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    let bmi be the contents of bit 0 of word element i of VSR[VRB+32]
    if bmi is equal to 0 then
        VSR[VRT+32].word[i] ←0xFFFF_FFFF
    else
        VSR[VRT+32].word[i] ←0x0000_0000
end

The vexpandwm instruction sets each word in the destination vector to all 1s or all 0s based on the least significant bit of the corresponding word in the source vector. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on 32-bit words, so ensure proper alignment if manipulating data directly. The operation is performed on vectors, so verify that the input vectors are correctly loaded before execution.


Summary: Expands bits from a GPR mask into a doubleword-element vector.

Expands individual bits from a source vector register into doubleword-sized elements in the destination vector register, where each bit controls whether the corresponding doubleword is set to all 1s or all 0s. This is a VMX instruction with no effect on condition registers or status fields.

for i in 0 to 3 do
  if vB[i] = 1 then
    vD[i*64:(i+1)*64-1] ← 0xFFFFFFFFFFFFFFFF
  else
    vD[i*64:(i+1)*64-1] ← 0x0000000000000000
  end if
end for

This instruction is useful for creating masks where each doubleword element in the target vector register is either all ones or all zeros based on the least significant bit of the corresponding source vector element. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to 1; otherwise, a Vector Unavailable exception will be raised. The instruction operates on doubleword elements, so ensure proper alignment and indexing when using this instruction.


Summary: Expands bits from a GPR mask into a quadword-element vector.

Expands individual bits from a source vector register into quadword-sized elements in the destination vector register, where each bit controls whether the corresponding quadword is set to all 1s or all 0s. This is a VMX instruction with no effect on condition registers or status fields.

for i in 0 to 1 do
  if vB[i] = 1 then
    vD[i*128:(i+1)*128-1] ← 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
  else
    vD[i*128:(i+1)*128-1] ← 0x00000000000000000000000000000000
  end if
end for

The vexpandqm instruction is used to set all elements in a vector register based on the value of a single mask bit. Ensure that the Vector Facility (VEC) is enabled in the MSR before using this instruction; otherwise, it will raise an exception. This instruction is useful for quickly initializing vectors with either all ones or all zeros based on a condition.


Summary: Extracts bit 0 of each byte element from a VSR into a GPR.

The contents of bit 0 of each byte element of VSR[VRB+32] are concatenated and placed into bits 48:63 of GPR[RT]. Bits 0:47 of GPR[RT] are set to 0.

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 15
    GPR[RT].bit[48+i] ← VSR[VRB+32].byte[i].bit[0]
end
GPR[RT].bit[0:47] ← 0

This instruction is used to extract the least significant bit from each byte of a vector register and pack them into the upper half of a general-purpose register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The lower half of the target GPR is always zeroed out, so be cautious if you need to preserve existing data in that portion.


Summary: Extracts MSB of each halfword into a GPR mask.

Extracts the most significant bit from each halfword element in the source vector and packs these bits into a general-purpose register as a mask. This is a VMX instruction with no effect on condition registers or status fields.

result ← 0
for i in 0 to 7 do
  if vB[i*16] = 1 then
    result[i] ← 1
  else
    result[i] ← 0
  end if
end for
RA ← result

The vextracthm instruction is useful for extracting the least significant bit of each halfword from a vector register and placing them into a general-purpose register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The upper 16 bits of the destination GPR will contain the extracted bits, with the lower 48 bits set to zero.


Summary: Extracts the least significant bit of each word element from a vector register and places them into a general-purpose register.

The contents of bit 0 of each word element of VSR[VRB+32] are concatenated and placed into bits 60:63 of GPR[RT]. Bits 0:59 of GPR[RT] are set to 0.

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    GPR[RT].bit[60+i] ← VSR[VRB+32].word[i].bit[0]
end
GPR[RT].bit[0:59] ← 0

This instruction is used to extract the least significant bit of each word from a vector register and pack them into the upper four bits of a general-purpose register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The lower 60 bits of the target GPR are always cleared, so be cautious if you need to preserve existing data in those positions.


Summary: Extracts MSB of each doubleword into a GPR mask.

Extracts the most significant bit from each doubleword element in the source vector and packs these bits into a general-purpose register as a mask. This is a VMX instruction with no effect on condition registers or status fields.

result ← 0
for i in 0 to 3 do
  if vB[i*64] = 1 then
    result[i] ← 1
  else
    result[i] ← 0
  end if
end for
RA ← result

This instruction is useful for extracting the least significant bit of each doubleword in a vector register and placing it into a general-purpose register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The result is stored in bits 62:63 of the target GPR, with all other bits set to zero.


Summary: Extracts the least significant bit of a vector register and places it into a general-purpose register.

The contents of bit 0 of VSR[VRB+32] are placed into bit 63 of GPR[RT]. Bits 0:62 of GPR[RT] are set to 0.

if MSR.VEC=0 then
    Vector_Unavailable()
GPR[RT] ← EXTZ64(VSR[VRB+32].bit[0])

This instruction extracts the least significant bit from a vector register and places it into the most significant bit of a general-purpose register, setting all other bits in the GPR to zero. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register before using this instruction. This operation is useful for extracting flags or status information from vector operations.


Summary: Moves the contents of two general-purpose registers into a vector-scalar register (VSR) as doublewords.

Moves the contents of two general-purpose registers into a VSR as doublewords, with RA forming the high doubleword and RB forming the low doubleword. This is a VSX instruction that does not affect condition registers or status fields.

For TX=0, mtvsrdd is treated as a VSX instruction in terms of resource availability.
For TX=1, mtvsrdd is treated as a Vector instruction in terms of resource availability.


Summary: Moves the lower doubleword of a vector register to a general-purpose register.

Moves the lower doubleword of a VSR to a general-purpose register. This is a VSX instruction that does not affect condition registers or status fields.

Use mfvsrld to transfer data from a vector register's lower doubleword into a general-purpose register. Ensure that the VSR index (determined by SX and S fields) is correctly specified to avoid unintended data access. This instruction operates at user privilege level but will raise an exception if executed in supervisor mode with invalid register indices.


Summary: Stores the leftmost byte of each element in a vector register to memory.

Isolates the leftmost non-zero byte in each element of the source vector register and stores the result in the destination vector register. This is a VMX instruction that does not affect condition registers or status fields.

The vstribl instruction is useful for extracting the first character from strings stored in vector registers. Ensure that the input vectors are properly aligned to avoid alignment faults. This instruction operates at user privilege level and will raise an exception if executed in a kernel context without proper permissions.

for i in 0 to 15 do
  found ← 0
  for j in 0 to 7 do
    if vB[i*8 + j] != 0 then
      vD[i*8:(i+1)*8-1] ← vB[j*8:(j+1)*8-1]
      found ← 1
      break
    end if
  end for
  if found = 0 then
    vD[i*8:(i+1)*8-1] ← 0
  end if
end for


Summary: Isolates the rightmost non-zero byte in a vector string and shifts it to the left.

Isolates the rightmost non-zero byte in each 16-byte element of the source vector and shifts it to the leftmost position of the corresponding result element; all other bytes in the result are zeroed. When Rc=1, the instruction updates CR6 based on whether a zero vector was produced.

for i in 0 to 15:
  byte_value ← VRB[i*8:(i+1)*8]
  if byte_value ≠ 0 then
    VRT[i*8:(i+1)*8] ← byte_value
  else
    VRT[i*8:(i+1)*8] ← 0
if Rc = 1 then CR6 ← record_zero_vector(VRT)

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.


VSX Scalar Test Data Class Single-Precision

Summary: Tests the data class of a single-precision floating-point value in a VSX register and sets condition bits accordingly.

XB

Index of VSX register containing the double-precision floating-point value

The instruction tests the data class of the double-precision floating-point value in the doubleword element 0 of VSR[XB] and sets the corresponding condition bits in CR field BF and FPCC based on the specified data classes in DCMX.

if MSR.VSX=0 then
    VSX_Unavailable()
src ← VSR[32×BX+B].dword[0]
exponent ← src.bit[1:11]
fraction ← src.bit[12:63]
class.Infinity ← (exponent = 0x7FF) & (fraction = 0)
class.NaN ← (exponent = 0x7FF) & (fraction != 0)
class.Zero ← (exponent = 0x000) & (fraction = 0)
class.Denormal ← (exponent = 0x000) & (fraction != 0) | (exponent > 0x000) & (exponent < 0x381)
match ← (DCMX.bit[0] & class.NaN) | (DCMX.bit[1] & class.Infinity & !sign) | (DCMX.bit[2] & class.Infinity & sign) | (DCMX.bit[3] & class.Zero & !sign) | (DCMX.bit[4] & class.Zero & sign) | (DCMX.bit[5] & class.Denormal & !sign) | (DCMX.bit[6] & class.Denormal & sign)
not_SP_value ← ¬bfp64_IS_BFP32_VALUE(src)
CR.bit[4×BF] ← FPSCR.FL ← src.sign
CR.bit[4×BF+1] ← FPSCR.FG ← 0b0
CR.bit[4×BF+2] ← FPSCR.FE ← match
CR.bit[4×BF+3] ← FPSCR.FU ← not_SP_value

This instruction is used to test the data class of a single-precision floating-point value in VSX registers. Ensure that the VSX facility is enabled (MSR.VSX=1) before using this instruction, otherwise it will raise an exception. The result sets condition bits in CR and FPSCR, which can be used for conditional branching based on the tested data class. Be cautious with alignment; the source value must be properly aligned within the VSR register to avoid undefined behavior.


Summary: Invalidates a TLB entry on the current processor only.

RS

Source General Purpose Register containing the LPID or PID

R

Effective Register bit, indicates if the operation affects effective registers

Invalidates a TLB entry on the current processor without affecting other processors. The operation is controlled by RIC (Radix Invalidate Control), PRS (Partition Scope), and R (Effective Radix) bits; RS contains the LPID or PID, and RB provides the address to invalidate. This is a privileged instruction requiring Hypervisor mode.

// Invalidate TLB entry based on address, LPID/PID, and control fields
if R = 0 then
  // Page Table (PT) invalidation
  tlb_invalidate_pt(RB, RS, PRS, RIC)
else
  // Radix Table (RT) invalidation
  tlb_invalidate_rt(RB, RS, PRS, RIC)

The tlbiel instruction is used to locally invalidate Translation Lookaside Buffer (TLB) entries based on various criteria specified by the RB, RS, RIC, PRS, and R fields. It is important to ensure that the correct values are set in these fields to achieve the desired TLB invalidation. This instruction operates at a privilege level that requires supervisor or higher authority, and it should be used carefully to avoid unintended side effects on system performance.


Summary: Provides an ordering function for stores relative to data accesses by other threads after a Directed Ultravisor Doorbell or Directed Hypervisor Doorbell interrupt.

Provides memory ordering semantics for stores relative to data accesses by other threads following a Directed Ultravisor Doorbell or Directed Hypervisor Doorbell interrupt. This privileged instruction acts as a synchronization point with no operands.

When used in conjunction with msgsndu or msgsnd, Synchronize with L = 0 or 2 is executed on the thread that will execute the msgsndu or msgsnd, and msgsync is executed on another thread, typically the thread that is the target of the msgsndu or msgsnd, but possibly any other thread (partly because the software that services the Directed Ultravisor Doorbell or Directed Hypervisor Doorbell interrupt may ultimately run on a thread other than that which received the exception). The Synchronize precedes the msgsndu or msgsnd; the msgsync is executed after the Directed Ultravisor Doorbell or Directed Hypervisor Doorbell interrupt occurs, and precedes all instructions that need to 'see' the values stored by the stores that are in set A of the memory barrier created by the Synchronize.

// Memory synchronization point for message-based interrupts
Memory_Synchronize()


Summary: Transitions the processor to a sleep state via message.

Transitions the processor to a sleep state via a message-based mechanism. The message content is provided in register RB. This is a privileged instruction that may put the processor into a low-power state pending an interrupt.


Summary: Negates the contents of each word element in a vector register.

For vnegw, the one's-complement of each signed integer in word elements of VSR[VRB+32] is added to 1 and placed into corresponding word elements of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src ←EXTS(VSR[VRB+32].word[i])
    VSR[VRT+32].word[i] ←CHOP32(¬src + 1)
end

The vnegw instruction negates each signed integer in the word elements of a vector register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on 32-bit words, so input data must be properly aligned. Be cautious of overflow conditions when negating large positive numbers.