Summary: Swaps bytes and stores 64 bits.

Byte-reverses all 64 bits of RS and stores the result as a doubleword in memory at address (RA|0) + RB. No status flags are affected. This instruction is used to write doubleword data in reversed byte order to memory.

EA ← (RA|0) + RB
[EA] ← byte_reverse_64(RS)

The stdbrx instruction is useful for storing a doubleword in memory with byte-reversed order. Ensure that the source register RS contains the data to be stored, and registers RA and RB are correctly set to calculate the effective address. This instruction operates at user privilege level and may raise an exception if there's a memory access violation.


Summary: Stores a word from a register to memory if the reservation is valid and matches the address used in the corresponding lwarx instruction.

The stwcx. instruction stores the upper half of the contents of register RS into memory at the effective address (EA) formed by adding the contents of registers RA and RB, provided that a reservation exists for this EA and the reservation length is 4 bytes. If the reservation does not exist or the conditions are not met, no store is performed.

if RA = 0 then
    b ← 0
else
    b ← (RA)
EA ← b + (RB)
if RESERVE then
    if RESERVE_LENGTH = 4 &
       RESERVE_ADDR = real_addr(EA) then
        MEM(EA, 4) ← (RS)32:63
        undefined_case ← 0
        store_performed ← 1
    else
        z ← smallest real page size supported by implementation
        if RESERVE_ADDR ÷ z = real_addr(EA) ÷ z then
          undefined_case ← 1
        else
          undefined_case ← 0
          store_performed ← 0
else
    undefined_case ← 0
    store_performed ← 0
if undefined_case then
    u1 ← undefined 1-bit value
    if u1 then
      MEM(EA, 4) ← (RS)32:63
    u2 ← undefined 1-bit value
    CR0 ← 0b00 || u2 || XERSO
else
    CR0 ← 0b00 || store_performed || XERSO
RESERVE ← 0

Succeeds only if a valid reservation exists on the target address. Sets CR0[EQ] to 1 on success, 0 on failure. Must always be used in a retry loop that re-executes the load-reserve instruction on failure.


Summary: Stores a doubleword from a register to memory if the reservation is valid and matches the address used for the reservation.

The stdcx. instruction stores the contents of register RS into memory at the effective address (EA) calculated as the sum of registers RA and RB, but only if there is a valid reservation that matches this EA and has a length of 8 bytes. The reservation is cleared after the operation.

if RA = 0 then
    b ← 0
else
    b ← (RA)
EA ← b + (RB)
if RESERVE then
    if RESERVE_LENGTH = 8 &
       RESERVE_ADDR = real_addr(EA) then
        MEM(EA, 8) ← (RS)
        undefined_case ← 0
        store_performed ← 1
    else
        z ← smallest real page size supported by implementation
        if RESERVE_ADDR ÷ z = real_addr(EA) ÷ z then
          undefined_case ← 1
        else
          undefined_case ← 0
          store_performed ← 0
else
    undefined_case ← 0
    store_performed ← 0
if undefined_case then
    u1 ← undefined 1-bit value
    if u1 then
      MEM(EA, 8) ← (RS)
    u2 ← undefined 1-bit value
    CR0 ← 0b00 || u2 || XERSO
else
    CR0 ← 0b00 || store_performed || XERSO
RESERVE ← 0


Summary: Traps if condition (comparison of words) is met.

Compares the 32-bit signed values in RA and RB according to the trap condition bits in TO. If the condition is true, a program interrupt (trap) is generated; otherwise execution continues. The TO field encodes up to five independent comparison conditions (less-than, greater-than, equal, unsigned less-than, unsigned greater-than).

if (TO[0] & (RA <s RB)) | (TO[1] & (RA >s RB)) | (TO[2] & (RA = RB)) | (TO[3] & (RA <u RB)) | (TO[4] & (RA >u RB)) then
  Trap_Exception ← 1
else
  Trap_Exception ← 0

Generates a program exception (System Call or Trap type) when the trap condition is true. The condition codes in TO select which comparisons trigger the trap: bit 0 = LT, bit 1 = GT, bit 2 = EQ, bit 3 = LU (unsigned), bit 4 = GU (unsigned). TO=31 (all bits set) always traps.


Summary: Compares the contents of register RA with an immediate value and invokes the system trap handler if any specified condition is met.

The contents of register RA are compared with the sign-extended value of the SI field. If any bit in the TO field is set to 1 and its corresponding condition is met by the result of the comparison, the system trap handler is invoked.

a ← EXTS((RA)32:63)
if (a < EXTS(SI)) & TO0 then TRAP
if (a > EXTS(SI)) & TO1 then TRAP
if (a = EXTS(SI)) & TO2 then TRAP
if (a <u EXTS(SI)) & TO3 then TRAP
if (a >u EXTS(SI)) & TO4 then TRAP


Summary: Traps if condition (comparison of doublewords) is met.

Compares the 64-bit signed values in RA and RB according to the trap condition bits in TO. If the condition is true, a program interrupt (trap) is generated; otherwise execution continues. The TO field encodes five independent doubleword comparison conditions (less-than, greater-than, equal, unsigned less-than, unsigned greater-than).


Summary: Compares the contents of a register with an immediate value and invokes a trap handler if specified conditions are met.

a ← (RA)
b ← EXTS(SI)
if (a < b) & TO0 then TRAP
if (a > b) & TO1 then TRAP
if (a = b) & TO2 then TRAP
if (a <u b) & TO3 then TRAP
if (a >u b) & TO4 then TRAP


Summary: Sign extends the low byte of a register to the full width.

The contents of the specified byte (RS)56 are placed into RA56:63, and RA0:55 are filled with a copy of (RS)56.

if 'extsb' then
    s ← (RS)56
    RA56:63 ← (RS)56:63
    RA0:55 ← 56s
else if 'extsb.' then
    s ← (RS)56
    RA56:63 ← (RS)56:63
    RA0:55 ← 56s

The extsb instruction is commonly used to sign-extend a byte value into a full word. Ensure the source register contains the correct byte to avoid unexpected results. This instruction operates at user privilege level and does not generate exceptions under normal conditions.


Summary: Sign extends the low halfword.

Sign-extends the low 16 bits (halfword) of the source register to fill all 64 bits of the destination register. The instruction replicates bit 15 of RS to all higher-order bits. No condition registers or status fields are affected unless an extended form with a recorded bit is used (extsH.).

The extsh instruction is commonly used to sign-extend a halfword value from the source register into the destination register. Ensure that the source register contains a valid halfword value, and be aware that this operation affects the entire 64-bit destination register. This instruction operates at user privilege level and does not generate exceptions under normal circumstances.


Summary: Sign extends the low word (32-bit) to 64 bits.

The contents of register RS are extended to fill the upper 32 bits of register RA, and the lower 32 bits of RA are filled with a copy of the upper 32 bits of RS.

if 'extsw' then
    s ← (RS)32
    RA32:63 ← (RS)32:63
    RA0:31 ← 32s
else if 'extsw.' then
    s ← (RS)32
    RA32:63 ← (RS)32:63
    RA0:31 ← 32s

The extsw instruction is commonly used to sign-extend a 32-bit value in RS to a 64-bit value in RA. Ensure that the source register RS contains the correct 32-bit signed integer to avoid unexpected results. This instruction operates at user privilege level and does not generate exceptions under normal circumstances.


Summary: Bitwise Equivalence (XNOR). RA = ~(RS ^ RB).

Performs a bitwise equivalence (XNOR) operation: RA ← ~(RS XOR RB). Each bit position in RA is set to 1 if the corresponding bits in RS and RB are equal, 0 otherwise. No condition registers or status fields are affected unless an extended form with a recorded bit is used (eqv.).

The eqv instruction is useful for performing bitwise equivalence operations, which can be applied in various logic and data manipulation tasks. Ensure that the input registers RS and RB are correctly aligned and contain the expected data to avoid unexpected results. This instruction operates at user privilege level and does not generate exceptions under normal conditions.


Summary: Bitwise NAND. RA = ~(RS & RB).

Performs a bitwise NAND operation: RA ← ~(RS AND RB). Each bit position in RA is set to 1 if the corresponding bits in RS and RB are not both 1, 0 otherwise. No condition registers or status fields are affected unless an extended form with a recorded bit is used (nand.).

The crnand instruction is useful for performing bitwise NAND operations on specific bits within the Condition Register. Ensure that the bit positions specified by BA, BB, and BT are valid to avoid undefined behavior. This instruction operates at user privilege level and does not generate exceptions under normal conditions.


Summary: Bitwise NOR. RA = ~(RS | RB).

Performs a bitwise NOR operation: RA ← ~(RS OR RB). Each bit position in RA is set to 1 if the corresponding bits in RS and RB are both 0, 0 otherwise. No condition registers or status fields are affected unless an extended form with a recorded bit is used (nor.).

The nor instruction performs a bitwise NOR of registers RS and RB and places the result in RA. Coding RB the same as RS forms the extended mnemonic not RA,RS, the standard way to complement a register. This instruction operates at user privilege level.


Summary: Performs a bitwise OR operation between the contents of two registers and the complement of the third register.

The contents of register RS are ORed with the complement of the contents of register RB, and the result is placed into register RA.

if 'orc' then
    RA <- (RS) | ¬(RB)
else if 'orc.' then
    RA <- (RS) | ¬(RB)
    CR0 <- result of OR operation

The orc instruction is useful for setting bits in a register based on the complement of another register. Be cautious with bit manipulation as incorrect usage can lead to unexpected results. The instruction operates at user privilege level and does not generate exceptions under normal conditions. Performance may vary depending on the specific implementation and architecture.


Summary: Multiply bottom half of RA by top half of RB, add to RT.

Multiplies the low halfword (bits 48-63) of RA by the high halfword (bits 0-15) of RB and adds the signed 32-bit product to the low 32 bits of RT, placing the result back in the low 32 bits of RT. This is part of the embedded (e200/e500) category. The instruction does not affect condition registers or XER unless an extended variant is used.


Multiply Accumulate Cross Halfword Signed

Summary: Signed Multiply Accumulate Cross Halfword with Saturation.

Signed multiply-accumulate of the low halfword of RA by the high halfword of RB, added to RT with saturation. The signed 32-bit product is added to the low 32 bits of RT; if overflow occurs, the result is saturated to the signed 32-bit range. This is an embedded (e200/e500) instruction. The SAT bit in XER is set if saturation occurs; other condition registers are not affected.


Multiply Accumulate Cross Halfword Unsigned

Summary: Unsigned Multiply Accumulate Cross Halfword.

Unsigned multiply-accumulate of the low halfword of RA by the high halfword of RB, added to RT. The unsigned 32-bit product is added to the low 32 bits of RT, with wraparound on overflow. This is an embedded (e200/e500) instruction. No condition registers or XER fields are affected.


Multiply Accumulate Cross Halfword Signed Unsigned

Summary: Mixed Sign Multiply Accumulate Cross Halfword with Saturation.

Mixed-sign multiply-accumulate of the signed low halfword of RA by the unsigned high halfword of RB, added to RT with saturation. The signed 32-bit product is added to the low 32 bits of RT; if overflow occurs, the result is saturated to the signed 32-bit range. This is an embedded (e200/e500) instruction. The SAT bit in XER is set if saturation occurs.


Summary: Multiply top half of RA by top half of RB, add to RT.

Multiplies the high halfword (bits 0-15) of RA by the high halfword of RB as signed integers, then adds the 32-bit product to RT and stores the result in RT. This is part of the Embedded (SPE) category and does not affect any condition or status registers.

product ← EXTS(RA[0:15]) × EXTS(RB[0:15])
RT ← RT + product


Multiply Accumulate High Halfword Signed

Summary: Signed Multiply Accumulate High Halfword with Saturation.

Multiplies the high halfword (bits 0-15) of RA by the high halfword of RB as signed integers, adds the 32-bit product to RT, and saturates the result to the signed 32-bit range if overflow occurs. This is part of the Embedded (SPE) category and sets the SAT bit in the SPEFSCR if saturation occurs.

product ← EXTS(RA[0:15]) × EXTS(RB[0:15])
result ← RT + product
if result > 2147483647 then
  RT ← 2147483647
  SPEFSCR[SAT] ← 1
elif result < -2147483648 then
  RT ← -2147483648
  SPEFSCR[SAT] ← 1
else
  RT ← result


Multiply Accumulate High Halfword Unsigned

Summary: Unsigned Multiply Accumulate High Halfword.

Multiplies the high halfword (bits 0-15) of RA by the high halfword of RB as unsigned integers, then adds the 32-bit product to RT and stores the result in RT. This is part of the Embedded (SPE) category and does not affect any condition or status registers.

product ← EXTZ(RA[0:15]) × EXTZ(RB[0:15])
RT ← RT + product


Multiply Accumulate High Halfword Signed Unsigned

Summary: Mixed Sign Multiply Accumulate High Halfword with Saturation.

Multiplies the high halfword (bits 0-15) of RA (signed) by the high halfword of RB (unsigned), adds the 32-bit product to RT, and saturates the result to the signed 32-bit range if overflow occurs. This is part of the Embedded (SPE) category and sets the SAT bit in SPEFSCR if saturation occurs.

product ← EXTS(RA[0:15]) × EXTZ(RB[0:15])
result ← RT + product
if result > 2147483647 then
  RT ← 2147483647
  SPEFSCR[SAT] ← 1
elif result < -2147483648 then
  RT ← -2147483648
  SPEFSCR[SAT] ← 1
else
  RT ← result


Summary: Multiply bottom half of RA by bottom half of RB, add to RT.

Multiplies the low halfword (bits 16-31) of RA by the low halfword of RB as signed integers, then adds the 32-bit product to RT and stores the result in RT. This is part of the Embedded (SPE) category and does not affect any condition or status registers.

product ← EXTS(RA[16:31]) × EXTS(RB[16:31])
RT ← RT + product


Summary: Signed Multiply Accumulate Low Halfword with Saturation.

Multiplies the low halfword (bits 16-31) of RA by the low halfword of RB as signed integers, adds the 32-bit product to RT, and saturates the result to the signed 32-bit range if overflow occurs. This is part of the Embedded (SPE) category and sets the SAT bit in SPEFSCR if saturation occurs.

product ← EXTS(RA[16:31]) × EXTS(RB[16:31])
result ← RT + product
if result > 2147483647 then
  RT ← 2147483647
  SPEFSCR[SAT] ← 1
elif result < -2147483648 then
  RT ← -2147483648
  SPEFSCR[SAT] ← 1
else
  RT ← result


Multiply Accumulate Low Halfword Unsigned

Summary: Unsigned Multiply Accumulate Low Halfword.

Multiplies the low halfword (bits 16-31) of RA by the low halfword of RB as unsigned integers, then adds the 32-bit product to RT and stores the result in RT. This is part of the Embedded (SPE) category and does not affect any condition or status registers.

product ← EXTZ(RA[16:31]) × EXTZ(RB[16:31])
RT ← RT + product


Multiply Accumulate Low Halfword Signed Unsigned

Summary: Mixed Sign Multiply Accumulate Low Halfword with Saturation.

Multiplies the low halfword (bits 16-31) of RA (signed) by the low halfword of RB (unsigned), adds the 32-bit product to RT, and saturates the result to the signed 32-bit range if overflow occurs. This is part of the Embedded (SPE) category and sets the SAT bit in SPEFSCR if saturation occurs.

product ← EXTS(RA[16:31]) × EXTZ(RB[16:31])
result ← RT + product
if result > 2147483647 then
  RT ← 2147483647
  SPEFSCR[SAT] ← 1
elif result < -2147483648 then
  RT ← -2147483648
  SPEFSCR[SAT] ← 1
else
  RT ← result


Summary: Multiply bottom half of RA by top half of RB.

Multiplies the sign-extended bottom halfword of RA by the sign-extended top halfword of RB, storing the low 32 bits of the product in RT. This is a signed 16×16→32 multiply operation. No condition register or status flags are affected.


Summary: Unsigned Multiply Cross Halfword.

Multiplies the zero-extended bottom halfword of RA by the zero-extended top halfword of RB, storing the low 32 bits of the product in RT. This is an unsigned 16×16→32 multiply operation. No condition register or status flags are affected.


Summary: Multiply top half of RA by top half of RB.

Multiplies the sign-extended top halfword of RA by the sign-extended top halfword of RB, storing the low 32 bits of the product in RT. This is a signed 16×16→32 multiply operation on the upper halves. No condition register or status flags are affected.


Summary: Unsigned Multiply High Halfword.

Multiplies the zero-extended top halfword of RA by the zero-extended top halfword of RB, storing the low 32 bits of the product in RT. This is an unsigned 16×16→32 multiply operation on the upper halves. No condition register or status flags are affected.


Summary: Multiply bottom half of RA by bottom half of RB.

Multiplies the sign-extended bottom halfword of RA by the sign-extended bottom halfword of RB, storing the low 32 bits of the product in RT. This is a signed 16×16→32 multiply operation on the lower halves. No condition register or status flags are affected.


Summary: Unsigned Multiply Low Halfword.

Multiplies the zero-extended bottom halfword of RA by the zero-extended bottom halfword of RB, storing the low 32 bits of the product in RT. This is an unsigned 16×16→32 multiply operation on the lower halves. No condition register or status flags are affected.


Negative Multiply Accumulate Cross Halfword

Summary: Negate product of cross halfwords and add to accumulator.

Multiplies the sign-extended bottom halfword of RA by the sign-extended top halfword of RB, negates the product, and adds it to the current value of RT (treating RT as a 32-bit accumulator). The result is stored back in RT. No condition register or status flags are affected.

a ← EXTS(RA[16:31])
b ← EXTS(RB[0:15])
product ← (a × b)[32:63]
RT ← RT + (¬product + 1)


Negative Multiply Accumulate Cross Halfword Signed

Summary: Negate product of cross halfwords and add to accumulator (Signed Saturation).

Multiplies the sign-extended bottom halfword of RA by the sign-extended top halfword of RB, negates the product, and adds it to RT with signed saturation to 32 bits. The saturated result is stored in RT, and the SAT bit in the SPEFSCR is set if saturation occurred. This instruction requires the SPE category.

a ← EXTS(RA[16:31])
b ← EXTS(RB[0:15])
product ← (a × b)[32:63]
result ← RT + (¬product + 1)
if result > 2147483647 then
  RT ← 2147483647
  SPEFSCR[SAT] ← 1
elif result < -2147483648 then
  RT ← -2147483648
  SPEFSCR[SAT] ← 1
else
  RT ← result


Negative Multiply Accumulate High Halfword

Summary: Negate product of high halfwords and add to accumulator.

Multiplies the high halfwords (bits 0-15) of RA and RB as signed 16-bit integers, negates the 32-bit product, and adds it to RT, storing the result in RT. This is an embedded SPE instruction that performs signed halfword multiply-accumulate with negation. The overflow bit (XER[OV]) is set if the result overflows a 32-bit signed integer.

prod ← EXTS((RA[0:15]) * (RB[0:15]))
RT ← RT + (-prod)
if overflow then XER[OV] ← 1 else XER[OV] ← 0
XER[SO] ← XER[SO] | XER[OV]


Negative Multiply Accumulate High Halfword Signed

Summary: Negate product of high halfwords and add to accumulator (Signed Saturation).

Multiplies the high halfwords (bits 0-15) of RA and RB as signed 16-bit integers, negates the 32-bit product, and adds it to RT with signed saturation, storing the result in RT. This is an embedded SPE instruction that performs signed halfword multiply-accumulate with negation and saturation. The overflow and saturation bits (XER[OV] and XER[SAT]) are set appropriately.

prod ← EXTS((RA[0:15]) * (RB[0:15]))
result ← RT + (-prod)
if result > 2147483647 then
  RT ← 2147483647
  XER[SAT] ← 1
else if result < -2147483648 then
  RT ← -2147483648
  XER[SAT] ← 1
else
  RT ← result
XER[OV] ← XER[SAT]


Negative Multiply Accumulate Low Halfword

Summary: Negate product of low halfwords and add to accumulator.

Multiplies the low halfwords (bits 16-31) of RA and RB as signed 16-bit integers, negates the 32-bit product, and adds it to RT, storing the result in RT. This is an embedded SPE instruction that performs signed halfword multiply-accumulate with negation. The overflow bit (XER[OV]) is set if the result overflows a 32-bit signed integer.

prod ← EXTS((RA[16:31]) * (RB[16:31]))
RT ← RT + (-prod)
if overflow then XER[OV] ← 1 else XER[OV] ← 0
XER[SO] ← XER[SO] | XER[OV]


Negative Multiply Accumulate Low Halfword Signed

Summary: Negate product of low halfwords and add to accumulator (Signed Saturation).

Multiplies the low halfwords (bits 16-31) of RA and RB as signed 16-bit integers, negates the 32-bit product, and adds it to RT with signed saturation, storing the result in RT. This is an embedded SPE instruction that performs signed halfword multiply-accumulate with negation and saturation. The overflow and saturation bits (XER[OV] and XER[SAT]) are set appropriately.

prod ← EXTS((RA[16:31]) * (RB[16:31]))
result ← RT + (-prod)
if result > 2147483647 then
  RT ← 2147483647
  XER[SAT] ← 1
else if result < -2147483648 then
  RT ← -2147483648
  XER[SAT] ← 1
else
  RT ← result
XER[OV] ← XER[SAT]


Summary: Invalidates a congruence class in the data cache (Embedded).

Invalidates a congruence class in the data cache at the address formed by RA + RB. This is an embedded cache-management instruction with no guaranteed semantics on all implementations; behavior is implementation-dependent and may require supervisor privilege. The instruction has no effect on data in higher-level caches or main memory.

addr ← (RA) + (RB)
Invalidate data cache congruence class at addr


Summary: Reads a data cache tag or data (Debug).

Reads and returns a data cache tag or data value from the address RA + RB into register RT. This is an embedded debug/diagnostic instruction used to inspect data cache contents; exact behavior (tag vs. data read, selection mechanism) is implementation-dependent. The instruction requires supervisor privilege and may not be available on all embedded PowerPC implementations.

addr ← (RA) + (RB)
RT ← Read data cache entry at addr


Instruction Cache Congruence Class Invalidate

Summary: Invalidates a congruence class in the instruction cache (Embedded).

Invalidates a congruence class in the instruction cache at the address formed by RA + RB. This is an embedded cache-management instruction with no guaranteed semantics on all implementations; behavior is implementation-dependent and may require supervisor privilege. The instruction has no effect on instruction cache entries in higher-level caches or main memory.

addr ← (RA) + (RB)
Invalidate instruction cache congruence class at addr


Summary: Reads an instruction cache tag or data (Debug).

Reads and returns an instruction cache tag or data value from the address RA + RB into a read port. This is an embedded debug/diagnostic instruction used to inspect instruction cache contents; exact behavior (tag vs. instruction read, selection mechanism) is implementation-dependent. The instruction requires supervisor privilege and may not be available on all embedded PowerPC implementations.

addr ← (RA) + (RB)
Read instruction cache entry at addr


Summary: Reads a TLB entry into MAS registers.

Reads a TLB entry specified by MAS0 into the MAS1-MAS3 registers. This instruction is privileged and requires hypervisor mode on some implementations. The TLB entry index and way are determined by the MAS0 register; the instruction populates MAS1-MAS3 with the corresponding entry data.

MAS1 ← TLB[MAS0.ESEL, MAS0.TLBSEL].MAS1
MAS2 ← TLB[MAS0.ESEL, MAS0.TLBSEL].MAS2
MAS3 ← TLB[MAS0.ESEL, MAS0.TLBSEL].MAS3


Summary: Writes a TLB entry from MAS registers.

Writes a TLB entry from MAS1-MAS3 registers into the TLB at the location specified by MAS0. This instruction is privileged and requires hypervisor mode on some implementations. The entry index and way are determined by MAS0; the instruction updates the corresponding TLB entry with data from MAS1-MAS3.

TLB[MAS0.ESEL, MAS0.TLBSEL].MAS1 ← MAS1
TLB[MAS0.ESEL, MAS0.TLBSEL].MAS2 ← MAS2
TLB[MAS0.ESEL, MAS0.TLBSEL].MAS3 ← MAS3


Summary: Searches the TLB for an address.

Searches the TLB for an entry matching the virtual address formed by combining RA and RB, and loads matching entry data into MAS0-MAS3 registers. If a match is found, MAS0.ESEL contains the entry index and MAS1-MAS3 contain the matching entry data. This instruction is privileged and affects MAS registers but not the general condition register.

EA ← (RA) + (RB)
if TLB.lookup(EA) then
  MAS0 ← TLB.index(EA)
  MAS1 ← TLB[index].MAS1
  MAS2 ← TLB[index].MAS2
  MAS3 ← TLB[index].MAS3
else
  MAS0.NOMPLT ← 1
end if


Summary: Invalidates a TLB entry by virtual address.

Invalidates a TLB entry matching the virtual address formed by RA and RB. This instruction is privileged and causes any TLB entry with a matching virtual address to be marked invalid. The exact behavior depends on the MMU implementation and may invalidate one or multiple entries.

EA ← (RA) + (RB)
for each TLB entry matching EA do
  TLB[entry].V ← 0
end for


Summary: Updates the EE bit of the MSR from a GPR.

Updates the Machine State Register (MSR) External Enable (EE) bit from the least significant bit of RS. This instruction is privileged and allows software to enable or disable external interrupts. The EE bit controls whether external interrupts are recognized by the processor.


Summary: Updates the EE bit of the MSR from an immediate.

Updates the Machine State Register (MSR) External Enable (EE) bit from the immediate value E (0 or 1). This instruction is privileged and provides a quick way to enable or disable external interrupts. The EE bit controls whether external interrupts are recognized by the processor.


Summary: Reads an on-chip peripheral register (DCR).

Reads a Device Control Register (DCR) and writes the value to general-purpose register RT. This instruction is privileged and device-specific; the DCR address is specified by DCRN. Access to DCR is implementation-dependent and may not be available on all processors.


Summary: Writes an on-chip peripheral register (DCR).

Writes the value from general-purpose register RS to a Device Control Register (DCR) specified by DCRN. This instruction is privileged and device-specific. Access to DCR is implementation-dependent and may not be available on all processors; the effects depend on the target DCR.


Summary: Returns a random number from the hardware RNG. (L=3: Raw, L=1: Conditioned, L=0: 32-bit).

Delivers a random number from the hardware random number generator into GPR RT. The L field controls the output mode: L=3 returns raw entropy, L=1 returns conditioned/whitened entropy, and L=0 returns a 32-bit conditioned value. This instruction requires the darn facility to be enabled and does not affect any condition or status registers.

if L = 3 then
  RT ← raw_random_64()
elif L = 1 then
  RT ← conditioned_random_64()
elif L = 0 then
  RT ← (0 || conditioned_random_32())
else
  UNDEFINED

The random number generator provides a minimum of 0.5 bits of entropy per bit. For L=0, the random number range is 0:0xFFFFFFFF. For L=1 and L=2, the random number range is 0:0xFFFFFFFF_FFFFFFFE. L=3 is reserved. A raw random number is unconditioned noise source output. A conditioned random number has been processed by hardware to reduce bias. 32-bit software running in an environment that does not preserve the high-order 32 bits of GPRs across invocations of the system error handler, signal handlers, event-based branch handlers, etc., may use the L=0 variant of darn and interpret the value 0xFFFFFFFF to indicate an error condition. When the error value is obtained, software is expected to repeat the operation. If a non-error value has not been obtained after several attempts, a software random number generation method should be used.


Summary: Moves the contents of the Floating-Point Status and Control Register (FPSCR) into a floating-point register.

Moves the contents of the Floating-Point Status and Control Register (FPSCR) into floating-point register FRT. If Rc=1 (mffs.), the instruction updates CR1 based on the moved FPSCR value. This is a privileged instruction that does not alter FPSCR itself.

FRT ← FPSCR
if Rc = 1 then
  CR1 ← (FRT[0:3])

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.


Summary: Moves the contents of a floating-point register into specified fields of the FPSCR.

The FPSCR is modified as specified by the FLM, L, and W fields. If L=0, the contents of register FRB are placed into the FPSCR under control of the W field and the field mask specified by FLM. If L=1, the contents of register FRB are placed into the FPSCR.

if 'mtfsf' then
    if L=0 then
        for i from 0 to 7 do
            if FLMi=1 then
                FPSCR[k] <- FRB[i+8*(1-W)]
            end if
        end for
    else if L=1 then
        FPSCR <- FRB
    end if
end if

Bits 33 and 34 (FEX and VX) cannot be explicitly reset.
If L=1 or if L=0 and FPSCR32:35 is specified, bits 32 (FX) and 35 (OX) are set to the values of (FRB)32 and (FRB)35.


Summary: Writes a 4-bit immediate to a specific FPSCR field.

Writes a 4-bit immediate value U into a 4-bit field of the FPSCR selected by BF. The target FPSCR field is at bits [4×BF : 4×BF+3]. This instruction directly modifies FPSCR state and may affect subsequent floating-point operations.

Use mtfsfi to directly manipulate specific fields in the FPSCR, such as enabling or disabling exceptions. Ensure the immediate value fits within the specified field size to avoid undefined behavior. This instruction operates at user privilege level and does not generate exceptions for valid immediate values.


Summary: Clears a specific bit in the FPSCR.

Clears (sets to 0) the FPSCR bit specified by BT. The FPSCR bits are numbered 0-31. Clearing certain FPSCR bits (e.g., exception bits or mode flags) can alter the behavior of subsequent floating-point operations.

The mtfsb0 instruction sets a specific bit in the FPSCR register to the value of the U field. It's commonly used for controlling floating-point exceptions and status flags. Be cautious when altering the FX bit, as it affects exception handling. This instruction operates at user privilege level.


Summary: Sets a specific bit in the FPSCR.

Sets (sets to 1) the FPSCR bit specified by BT. The FPSCR bits are numbered 0-31. Setting certain FPSCR bits (e.g., rounding mode or enable flags) can alter the behavior of subsequent floating-point operations.

This instruction is used to enable a specific floating-point exception. Ensure that the FPSCR register is properly managed to avoid unintended exceptions. This operation requires supervisor privilege level.


Hypervisor Return From Interrupt Doubleword

Summary: Returns from a hypervisor interrupt.

Returns from a hypervisor interrupt by restoring the program counter from HSRR0 and machine state from HSRR1, then resuming execution at the restored address. This is a hypervisor-privileged instruction and only valid when the processor is in hypervisor state. It acts as a serializing instruction.

NIA ← HSRR0
Restore MSR from HSRR1
Return

The hrfid instruction is crucial for hypervisors to manage interrupt returns, updating the MSR and setting the NIA based on values from HSRR. Ensure that HSRR registers are correctly populated before executing hrfid to avoid undefined behavior. This instruction operates at supervisor level and may trigger exceptions if executed in an inappropriate context.


Summary: Initiates a hardware copy (accelerator) operation.

The 'copy' instruction loads a 128-byte block of data and associated metadata from memory into the copy buffer. The effective address (EA) is calculated as the sum of RA and RB. If EA is not aligned to 128 bytes or if the storage is Caching Inhibited, appropriate error handlers are invoked.

if RA = 0 then
    b ← 0
else
    b ← (RA)
EA ← b + (RB)
copy_buffer ← memory(EA, 128) || MEMmetadata(EA, 128)

This instruction is treated as a Load, except that the data transfer ordering is described in Section 1.7.1.1.


Summary: Transfers data from the copy buffer to a specified memory location.

Transfers data from the processor's copy buffer to a memory location specified by the effective address formed from RA and RB. This instruction is part of the Copy/Paste facility and requires special kernel/hypervisor support. The L operand controls paste behavior (0=non-atomic, 1=atomic).

EA ← (RA) + (RB)
if L = 1 then
  Paste_Atomic(EA, Copy_Buffer)
else
  Paste_NonAtomic(EA, Copy_Buffer)

The paste instruction is commonly used to transfer data from the copy buffer to memory. Ensure that the effective address (EA) calculated from RA and RB is correctly aligned for optimal performance. If L=1, be aware that metadata bits in the copy buffer are cleared before the transfer, which might affect subsequent operations relying on these bits.


Summary: Counts the number of leading zero bits in each byte element of a vector register.

For vclzb, the number of consecutive zero bits starting at bit 0 of each byte element in VSR[VRB+32] is placed into the corresponding byte element in VSR[VRT+32]. The count ranges from 0 to 8, inclusive.

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 15
    n ←0
    do while n < 8
        if VSR[VRB+32].byte[i].bit[n] = 0b1 then
            leave
        n ←n + 1
    end
    VSR[VRT+32].byte[i] ←n
end

The vclzb instruction counts leading zeros in each byte of the input vector. Ensure that the Vector Facility is enabled by checking and setting the appropriate bit in the MSR register. This instruction operates on 16-byte vectors, processing each byte individually. Be cautious with alignment; while not strictly required, proper alignment can optimize performance. The result is a vector where each element contains the count of leading zeros from the corresponding input byte.


Summary: Counts leading zeros in each halfword.

Counts the number of leading zero bits in each of the four 16-bit halfwords of register VB and writes the count (0-16) into the corresponding halfword of register VD. Does not affect CR or FPSCR.

for i in 0 to 3 do
  halfword ← VB[16*i : 16*i+15]
  VD[16*i : 16*i+15] ← ctz(halfword) // count leading zeros in 16-bit value

The vclzh instruction is useful for counting leading zeros in each halfword of a vector, which can be helpful in various bit manipulation tasks. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The instruction processes 8 halfwords per vector register, and results are stored directly in the destination vector register.


Summary: Counts the number of leading zero bits in each word element of a vector register.

For vclzw, the number of consecutive zero bits starting at bit 0 of each word element in VSR[VRB+32] is counted and placed into the corresponding word element in VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    n ←0
do while n < 32
    if VSR[VRB+32].word[i].bit[n] = 0b1 then
        leave
    n ←n + 1
end
VSR[VRT+32].word[i] ←n
end

vclzw counts leading zeros in each word of the input vector. Ensure VSR[VRB+32] is properly aligned and accessible. This instruction operates at user privilege level unless MSR.VEC is set, in which case it raises an exception.


Summary: Counts the number of leading zero bits in each doubleword element of a vector register.

For vclzd, for each integer value i from 0 to 1, counts the number of consecutive zero bits starting at bit 0 of doubleword element i of VSR[VRB+32] and places this count into doubleword element i of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    n ←0
    do while (n<64) & (VSR[VRB+32].dword[i].bit[n]=0b0)
        n ←n + 1
    end
    VSR[VRT+32].dword[i] ←n
end

The vclzd instruction counts leading zeros in each doubleword of the input vector. Ensure that the Vector Facility is enabled by checking and setting the MSR.VEC bit. This instruction operates on 64-bit elements, so input vectors must be aligned accordingly. The result is stored in the destination vector register.


Summary: Counts the number of trailing zero bits in each byte element of a vector register.

For vctzb, the number of consecutive zero bits starting at bit 7 of each byte element in VSR[VRB+32] is placed into the corresponding byte element in VSR[VRT+32]. The count ranges from 0 to 8, inclusive.

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 15
    n ←0
    do while n < 8
        if VSR[VRB+32].byte[i].bit[7-n] = 0b1 then
            leave
        n ←n + 1
    end
    VSR[VRT+32].byte[i] ←CHOP8(EXTZ(n))
end

The vctzb instruction counts the number of trailing zero bits in each byte of the source vector, storing the result in the destination vector. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on 16-byte vectors and processes each byte independently. Be cautious with alignment; while not strictly required, proper alignment can improve performance.


Summary: Counts trailing zeros in each halfword.

Counts the number of trailing zero bits in each of the 8 halfword elements in vB and stores the result in the corresponding halfword of vD. Each result is an unsigned integer in the range 0-16. No status flags are affected. This instruction is part of the VMX (AltiVec) extension.

for i in 0 to 7 do
  count ← 0
  halfword ← vB[i*16 : i*16+15]
  if halfword = 0 then
    count ← 16
  else
    for j in 0 to 15 do
      if halfword[j] = 1 then
        break
      count ← count + 1
  vD[i*16 : i*16+15] ← count

The vctzh instruction is useful for counting trailing zeros in each halfword of a vector, which can be helpful in bit manipulation and data compression tasks. Ensure that the Vector Facility (VEC) is enabled in the MSR register to avoid a Vector_Unavailable exception. The instruction processes 8 halfwords per vector register, so ensure your data is properly aligned and structured for optimal performance.


Summary: Counts the number of trailing zero bits in each word element of a vector register.

For vctzw, the number of consecutive zero bits starting at bit 31 of each word element in VSR[VRB+32] is counted and placed into the corresponding word element in VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    n ←0
do while n < 32
    if VSR[VRB+32].word[i].bit[31-n] = 0b1 then
        leave
    n ←n + 1
end
VSR[VRT+32].word[i] ←CHOP32(EXTZ(n))
end

The vctzw instruction counts the number of trailing zeros in each word element of a vector register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on 32-bit words, so input data must be aligned accordingly. The result is stored in another vector register, preserving the original data unless explicitly overwritten.


Summary: Counts the number of consecutive zero bits starting at bit 63 of each doubleword element in VSR[VRB+32] and places the result into VSR[VRT+32].

For vctzd, for each integer value i from 0 to 1, a count of the number of consecutive zero bits starting at bit 63 of doubleword element i of VSR[VRB+32] is placed into doubleword element i of VSR[VRT+32]. This number ranges from 0 to 64, inclusive.

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    n ←0
    do while n < 64
        if VSR[VRB+32].dword[i].bit[63-n] = 0b1 then
            leave
        n ←n + 1
    end
    VSR[VRT+32].dword[i] ←CHOP64(EXTZ(n))
end

The vctzd instruction counts trailing zeros in each doubleword of the input vector. Ensure that the Vector Facility is enabled by checking and setting the MSR.VEC bit. This instruction operates on 64-bit elements, so input vectors must be aligned accordingly. The result is a count from 0 to 64 for each element, indicating the number of trailing zeros.


Summary: Counts the number of bits set to 1 in each byte of a vector register.

For vpopcntb, the number of bits set to 1 in each byte element of VSR[VRB+32] is counted and placed into the corresponding byte element of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 15
    n ←0
    do j = 0 to 7
        n ←n + VSR[VRB+32].byte[i].bit[j]
    end
    VSR[VRT+32].byte[i] ←n
end

This instruction is used to count the number of set bits (1s) in each byte of a vector register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. The operation processes 16 bytes, and the result is stored in another vector register. This instruction is available at user privilege level.


Summary: Counts set bits in each halfword.

Counts the number of set bits (population count) in each of the 8 halfword elements in vB and stores the result in the corresponding halfword of vD. Each result is an unsigned integer in the range 0-16. No status flags are affected. This instruction is part of the VMX (AltiVec) extension.

for i in 0 to 7 do
  count ← 0
  halfword ← vB[i*16 : i*16+15]
  for j in 0 to 15 do
    if halfword[j] = 1 then
      count ← count + 1
  vD[i*16 : i*16+15] ← count

This instruction is useful for counting the number of set bits in each halfword of a vector, which can be helpful in various bit manipulation tasks. Ensure that the Vector Facility (VEC) is enabled in the Machine State Register (MSR) before using this instruction; otherwise, it will raise an exception. The operation is performed on 8 halfwords per vector register, and there are no specific alignment requirements for the data being processed.


Summary: Counts the number of bits set to 1 in each word element of a vector register.

For vpopcntw, the number of bits set to 1 in each word element of VSR[VRB+32] is counted and placed into the corresponding word element of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    n ←0
    do j = 0 to 31
        n ←n + VSR[VRB+32].word[i].bit[j]
    end
    VSR[VRT+32].word[i] ←n
end

This instruction counts the number of set bits (1s) in each 32-bit word of the source vector and stores the result in the destination vector. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on 128-bit vectors, processing four 32-bit words per operation.


Summary: Counts set bits in each doubleword.

Counts the number of set bits (population count) in each of the 2 doubleword elements in vB and stores the result in the corresponding doubleword of vD. Each result is an unsigned integer in the range 0-64. No status flags are affected. This instruction is part of the VMX (AltiVec) extension.

for i in 0 to 1 do
  count ← 0
  doubleword ← vB[i*64 : i*64+63]
  for j in 0 to 63 do
    if doubleword[j] = 1 then
      count ← count + 1
  vD[i*64 : i*64+63] ← count

The vpopcntd instruction is useful for counting the number of set bits in each 64-bit element of a vector. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. This instruction operates on two doublewords per vector register, and results are stored in the corresponding positions of the destination vector.


Vector Extract Unsigned Byte to VSR using Immediate-specified Index VX-form

Summary: Extracts an unsigned byte from a vector register and places it into the upper byte of another vector register.

The contents of byte element UIM of VSR[VRB+32] are placed into bits 56:63 of VSR[VRT+32]. The contents of the remaining byte elements of VSR[VRT+32] are set to 0.

if MSR.VEC=0 then
    Vector_Unavailable()
src ←VSR[VRB+32].byte[UIM]
VSR[VRT+32].dword[0] ←EXTZ64(src)
VSR[VRT+32].dword[1] ←0x0000_0000_0000_0000

If the value of UIM is greater than 14, the results are undefined.


Summary: Extracts a halfword from a vector into a GPR.

Extracts an unsigned halfword element from vB at the position specified by UIM and stores the zero-extended 16-bit value into general-purpose register RA. The halfword index (0-7) is provided by the 3-bit immediate UIM. No status flags are affected. This instruction is part of the VMX (AltiVec) extension.

The vextractuh instruction extracts an unsigned halfword from a vector register at a specified index. Ensure the index is within bounds to avoid undefined behavior. This instruction operates in user privilege level and does not generate exceptions for valid indices.


Vector Extract Unsigned Word to VSR using Immediate-specified Index VX-form

Summary: Extracts an unsigned word from a vector register and places it into another vector register using an immediate-specified index.

The contents of byte elements UIM:UIM+3 of VSR[VRB+32] are placed into word element 1 of VSR[VRT+32]. The contents of the remaining word elements of VSR[VRT+32] are set to 0.

if MSR.VEC=0 then
    Vector_Unavailable()
src ←VSR[VRB+32].byte[UIM:UIM+3]
VSR[VRT+32].dword[0] ←EXTZ64(src)
VSR[VRT+32].dword[1] ←0x0000_0000_0000_0000

This instruction is used to extract a 4-byte unsigned word from a vector register and place it into another vector register. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. The source byte elements must be correctly specified by UIM, and the destination register will have its first dword set to the extracted value while the second dword is zeroed out.


Summary: Extracts a doubleword from a vector into a GPR.

Extracts an unsigned doubleword element from vB at the position specified by UIM and stores the 64-bit value into general-purpose register RA. The doubleword index (0-1) is provided by the 1-bit immediate UIM. No status flags are affected. This instruction is part of the VMX (AltiVec) extension.

index ← UIM[0:1]
RA ← vB[index*64 : index*64+63]

The vextractd instruction is used to extract an 8-byte doubleword from a source vector register into the destination vector register, starting at a specified byte index. Ensure that the MSR.VEC bit is set to enable vector operations; otherwise, a Vector_Unavailable exception will be raised. Be cautious with the UIM index; if it exceeds 8, the results are undefined. The destination register's second doubleword is zeroed out.


Vector Insert Byte from VSR using Immediate-specified Index

Summary: Inserts a byte element from one vector register into another at an immediate-specified index.

The contents of byte element 7 of VSR[VRB+32] are placed into byte element UIM of VSR[VRT+32]. The remaining byte elements of VSR[VRT+32] are not modified.

if MSR.VEC=0 then
    Vector_Unavailable()
VRT[32].byte[UIM] ← VRB[32].byte[7]

This instruction is used to insert a byte from one vector register into another at a specified index. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector Unavailable exception will be raised. The destination and source registers must be in the range of 32-63. Be cautious with alignment as it affects performance and correctness.


Summary: Inserts a halfword from a GPR into a vector.

Inserts the low-order 16 bits of general-purpose register vB into vD at the halfword position specified by UIM, leaving other halfword elements of vD unchanged. The halfword index (0-7) is provided by the 3-bit immediate UIM. No status flags are affected. This instruction is part of the VMX (AltiVec) extension.

index ← UIM[1:3]
vD[index*16 : index*16+15] ← vB[48:63]

The vinserth instruction is used to insert a halfword from one vector register into another at a specified index. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. The destination vector's remaining byte elements remain unchanged after the insertion.


Vector Insert Word from VSR using Immediate-specified Index

Summary: Inserts a word element from one vector register into another vector register at an immediate-specified index.

The contents of word element 1 of VSR[VRB+32] are placed into byte elements UIM:UIM+3 of VSR[VRT+32]. The contents of the remaining byte elements of VSR[VRT+32] are not modified. If the value of UIM is greater than 12, the results are undefined.

if MSR.VEC=0 then
    Vector_Unavailable()
VSR[VRT+32].byte[UIM:UIM+3] ← VSR[VRB+32].word[1]

This instruction is used to insert a word from one vector register into another, with the destination index specified by an immediate value. Ensure that the immediate index (UIM) does not exceed 12 to avoid undefined behavior. This operation requires the Vector Facility to be enabled in the Machine State Register (MSR).


Summary: Inserts a doubleword from a GPR into a vector.

Inserts the contents of general-purpose register vB into vD at the doubleword position specified by UIM, leaving the other doubleword element of vD unchanged. The doubleword index (0-1) is provided by the 1-bit immediate UIM. No status flags are affected. This instruction is part of the VMX (AltiVec) extension.

index ← UIM[0:1]
vD[index*64 : index*64+63] ← vB[0:63]

The vinsertd instruction is used to insert a doubleword from one vector register into another, with specific byte alignment. Ensure that the UIM value does not exceed 8 to avoid undefined behavior. This instruction requires the VEC bit in the MSR (Machine State Register) to be set; otherwise, it will raise an exception.


Summary: Adds the contents of two vector registers and writes the carry-out to another vector register.

For vaddcuw, the sum of the unsigned integer values in word elements of VSR[VRA+32] and VSR[VRB+32] is placed into word elements of VSR[VRT+32]. The carry out of the 32-bit sum is zero-extended to 32 bits and placed into word element i of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ←EXTZ(VSR[VRA+32].word[i])
    src2 ←EXTZ(VSR[VRB+32].word[i])
    VSR[VRT+32].word[i] ←CHOP32((src1 + src2) >> 32)
end

This instruction is used for adding unsigned integers in vector registers, with the carry out being zero-extended and stored alongside the result. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation processes each word element independently, so alignment of data within the vectors is not strictly required.


Summary: Adds the contents of two vector registers and writes the carry-out to another register.

The instruction adds the unsigned integer values in VSR[VRA+32] and VSR[VRB+32], placing the result in VSR[VRT+32]. The carry-out is also written into VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
src1 ←EXTZ(VSR[VRA+32])
src2 ←EXTZ(VSR[VRB+32])
sum  ←EXTZ(src1) + EXTZ(src2)
VSR[VRT+32] ←EXTZ128((src1 + src2) >> 128)

The Vector Add Unsigned Quadword instructions support efficient wide-integer addition.


Summary: Subtracts the unsigned integer values in word elements of two vector registers and writes the result to another vector register, along with the carry-out.

For vsubcuw, the unsigned integer value in word element i of VSR[VRB+32] is subtracted from the unsigned integer value in word element i of VSR[VRA+32]. The complement of the borrow out of bit 0 of the 32-bit difference is zero-extended to 32 bits and placed into word element i of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ←EXTZ(VSR[VRA+32].word[i])
    src2 ←EXTZ(¬VSR[VRB+32].word[i])
    VSR[VRT+32].word[i] ←EXTZ32((src1+src2+1) >> 32)
end

The vsubcuw instruction performs an unsigned subtraction with carryout on each word element of the input vectors. It is useful for operations requiring precise control over overflow handling. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation does not require any specific alignment, but inputs must be correctly aligned to 128-bit boundaries as per standard vector register usage.


Vector Subtract Carryout Unsigned Quadword

Summary: Subtracts the contents of two vector registers, adds one, and writes the carry-out to another register.

For vsubcuq, the difference between the contents of VSR[VRA+32] and the one's complement of VSR[VRB+32], plus one, is placed into VSR[VRT+32]. The carry out is also written to VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
src1 ←EXTZ(VSR[VRA+32])
src2 ←EXTZ(¬VSR[VRB+32])
VSR[VRT+32] ←CHOP128((src1 + src2 + 1) >> 128)

The Vector Subtract Unsigned Quadword instructions support efficient wide-integer subtraction.


Summary: Calculates the parity of each byte in a vector word and stores the result.

For vprtybw, the parity of each byte in the source vector register VRB is calculated and stored in the corresponding position in the target vector register VRT.

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    s ←0
    do j = 0 to 3
        s ←s ⊕VSR[VRB+32].word[i].byte[j].bit[7]
    end
    VSR[VRT+32].word[i] ←CHOP32(EXTZ(s))
end

The vprtybw instruction calculates the parity of each byte in the source vector register and stores the result in the target vector register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on 128-bit vectors, processing four 32-bit words per iteration. Be cautious with alignment; both source and target registers must be properly aligned to avoid exceptions.


Summary: Computes parity of bytes within doublewords.

Computes the parity (XOR of all bits) of each byte within the 2 doubleword elements of vB and stores a single parity bit (0 or 1) into the corresponding byte position of vD, with each doubleword's 8 bytes reduced to their individual parities. No status flags are affected. This instruction is part of the VMX (AltiVec) extension.

for i in 0 to 1 do
  for j in 0 to 7 do
    byte_index ← i*8 + j
    byte_val ← vB[byte_index*8 : byte_index*8+7]
    parity ← XOR(byte_val[0], byte_val[1], ..., byte_val[7])
    vD[byte_index*8 : byte_index*8+7] ← (0x00) || parity

This instruction is useful for calculating the parity of the least significant bit in each byte of a doubleword element. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The operation is performed on 64-bit elements, and the result is stored in the corresponding output vector register. There are no specific alignment requirements for the input data.


Summary: Calculates the parity of each byte in a vector register and stores the result in another vector register.

Computes the parity bit for each byte in the 128-bit source vector and stores the result in the destination vector. The parity of each byte is XORed across all 8 bits, producing a single bit (0 or 1) for each byte. This is a VMX/AltiVec extension instruction and does not affect condition registers or status fields.

for i in 0 to 15 do
  parity_bit ← 0
  for j in 0 to 7 do
    parity_bit ← parity_bit XOR vB[i*8 + j]
  vD[i*8:i*8+7] ← (0b0000000 || parity_bit)
end

The vprtybq instruction calculates the parity of each byte in the source vector register VRB and stores the result in the target vector register VRT. Ensure that the Vector Facility is enabled by checking and setting the MSR.VEC bit. The instruction processes 16 bytes from VRB, and the result is a single bit indicating the parity for each byte, which is then replicated across all 128 bits of VRT.


Summary: Adds two BCD (Binary Coded Decimal) vectors.

Adds two Binary Coded Decimal (BCD) vectors element-wise and stores the result in the destination vector. The PS field specifies the preferred sign convention for the result. This instruction requires the Vector Crypto extension and does not directly affect condition registers.

for i in 0 to 15 do
  BCD_digit_A ← vA[i*4:i*4+3]
  BCD_digit_B ← vB[i*4:i*4+3]
  sum ← BCD_digit_A + BCD_digit_B
  if sum > 9 then
    sum ← sum + 6
  vD[i*4:i*4+3] ← sum[3:0]
end
if PS then
  apply_sign_to_vD()
end


Summary: Tests the significance of a decimal floating-point value in FPR[FRB] against an immediate value UIM.

The instruction compares the number of significant digits (NSDb) of the DFP value in FPR[FRB] with the reference significance specified by UIM. The result is placed into CR field BF and FPCC.

NSDb <- number of significant digits in FPR[FRB]
if UIM != 0 and UIM < NSDb then
    CR[BF] <- 0b0010
    FPCC <- 0b0010
else if UIM != 0 and UIM > NSDb or UIM = 0 then
    CR[BF] <- 0b0100
    FPCC <- 0b0100
else if UIM != 0 and UIM = NSDb then
    CR[BF] <- 0b1000
    FPCC <- 0b1000
else
    CR[BF] <- 0b0001
    FPCC <- 0b0001

The dtstsfi instruction is used to compare the number of significant digits in a DFP value with a specified reference significance. Ensure that the UIM (Upper Immediate) is correctly set according to the desired comparison. This instruction operates at the problem state and may raise exceptions if the FPR[FRB] contains an invalid DFP value. Performance can be optimized by minimizing the use of this instruction in critical loops due to its dependency on floating-point operations.


Decimal Test Significance Immediate Quad

Summary: Tests DFP Quad significance.

Tests the significance of a Decimal Floating-Point Quad-precision operand based on the immediate value U and updates the specified condition register field. The result indicates whether the value is zero, subnormal, normal, or special (infinity/NaN). Requires the Decimal Floating-Point facility and updates the target CR field.

if isSpecial(FRB[0:127]) then
  CR[BF*4:BF*4+3] ← test_special(FRB[0:127], U)
elif isZero(FRB[0:127]) then
  CR[BF*4:BF*4+3] ← 0b0100
elif isSubnormal(FRB[0:127]) then
  CR[BF*4:BF*4+3] ← 0b0010
else
  CR[BF*4:BF*4+3] ← 0b0001
end

The dtstsfiq instruction is used to compare the number of significant digits in a DFP value with an immediate reference significance. Ensure that the UIM (immediate reference significance) is correctly set according to your comparison needs. The result is stored in both the condition register field BF and the FPSCR's FPCC field, allowing for easy conditional branching based on the comparison outcome.


Summary: Compares the contents of bits 56:63 of register RA with each byte in register RB and sets the condition register field BF.

Compares the least significant byte of register RS (bits 56:63) against each of the eight bytes in register RB, setting a byte in register RA to 0xFF where a match occurs and 0x00 where no match occurs. The instruction does not update condition registers directly but produces a byte-mask result in RA.

search_byte ← RS[56:63]
for i in 0 to 7 do
  if RB[i*8:i*8+7] = search_byte then
    RA[i*8:i*8+7] ← 0xFF
  else
    RA[i*8:i*8+7] ← 0x00
  end
end

cmpeqb is useful for implementing character typing functions such as isspace() that are implemented by comparing the character to 1 or more values. A function such as isspace() can be implemented by loading the 6 byte codes corresponding to characters considered as whitespace (HT, LF, VT, FF, CR, and SP) and using the cmpeqb to compare the subject character to those 6 values to determine if any match occurs.


Summary: Compares bytes in two GPRs, result is byte mask.

Compares each byte of register RS with the corresponding byte in register RB and stores a byte-mask result in register RA. For each byte, 0xFF is written to RA if the bytes are equal, and 0x00 is written if they differ. No condition register fields are updated.

for i in 0 to 7 do
  if RS[i*8:i*8+7] = RB[i*8:i*8+7] then
    RA[i*8:i*8+7] ← 0xFF
  else
    RA[i*8:i*8+7] ← 0x00
  end
end

The cmpb instruction is useful for performing byte-wise comparisons between two registers. Ensure that the input registers (RS and RB) are properly aligned to avoid unexpected results. The output register (RA) will contain 0xFF in bytes where the comparison was equal, and 0x00 elsewhere. This instruction operates at user privilege level.


Summary: Calculates parity of a word (Scalar).

Computes the parity of the entire 32-bit word in register RS by XORing all 32 bits and stores the result (a single bit) in the low bit of register RA. All other bits of RA are cleared to zero. No condition registers or status fields are affected.

parity_bit ← 0
for i in 0 to 31 do
  parity_bit ← parity_bit XOR RS[i]
end
RA ← (0 || parity_bit)

The prtyw instruction is useful for calculating the parity of each byte in a doubleword, which can be helpful in error detection. Ensure that the input register (RS) contains valid data; otherwise, the output may not reflect meaningful parity information. This instruction operates at user privilege level and does not generate exceptions under normal conditions.


Summary: Calculates parity of a doubleword (Scalar).

Computes the parity of the entire 64-bit doubleword in register RS by XORing all 64 bits and stores the result (a single bit) in the low bit of register RA. All other bits of RA are cleared to zero. No condition registers or status fields are affected.

The prtyd instruction is useful for parity checking on doubleword values. It sets the least significant bit of RA based on the parity of each byte in RS, which can be helpful for error detection. Ensure that RS and RA are properly aligned to avoid unexpected behavior. This instruction operates at user privilege level.


Summary: Calculates remainder of signed word division.

The 32-bit dividend is (RA)32:63. The 32-bit divisor is (RB)32:63. The 32-bit remainder of the dividend divided by the divisor is placed into RT32:63. The contents of RT0:31 are undefined.

dividend = (RA)32:63
 divisor = (RB)32:63
 if dividend >= 0 then
    quotient = floor(dividend / divisor)
 else
    quotient = ceil(dividend / divisor)
 RT32:63 <- dividend - (quotient * divisor)
 RT0:31 <- undefined

If an attempt is made to perform any of the divisions 0x8000_0000 % -1 or <anything> % 0, then the contents of register RT are undefined.


Summary: Calculates remainder of unsigned word division.

Calculates the unsigned remainder (modulo) of a 32-bit word division, storing the result in RT. The dividend is in RA and the divisor is in RB. No status flags are affected; division by zero is not trapped and produces undefined results.

The moduw instruction is used for performing modulo operations on unsigned integers. Ensure the divisor in RB32:63 is not zero to avoid division by zero exceptions. The result is placed in RT32:63, while RT0:31 remains undefined and should not be relied upon.


Summary: Calculates remainder of signed doubleword division.

The 64-bit dividend is (RA). The 64-bit divisor is (RB). The 64-bit remainder of the dividend divided by the divisor is placed into register RT. The quotient is not supplied as a result. Both operands and the remainder are interpreted as signed integers. The remainder is the unique signed integer that satisfies remainder = dividend - (quotient × divisor) where 0 ≤remainder < |divisor| if the dividend is nonnegative, and -|divisor| < remainder ≤0 if the dividend is negative.

dividend ← (RA)
divisor ← (RB)
RT ← dividend % divisor

If an attempt is made to perform any of the divisions <anything> % 0 or 0x8000_0000_0000_0000 % -1, then the contents of register RT are undefined.


Summary: Calculates remainder of unsigned doubleword division.

Calculates the unsigned remainder (modulo) of a 64-bit doubleword division, storing the result in RT. The dividend is in RA and the divisor is in RB. No status flags are affected; division by zero is not trapped and produces undefined results.

The modud instruction is used for performing an unsigned doubleword modulo operation. Ensure that the divisor in register RB is not zero to avoid undefined behavior. The result is placed in register RT, and this instruction operates at user privilege level.


Summary: Tests the double-precision floating-point operand in register FRB and sets flags based on certain conditions.

This instruction tests the double-precision floating-point operand in register FRB and sets flags based on certain conditions related to its value and exponent. The CR field BF is updated accordingly.

Let e_a be the unbiased exponent of the double-precision floating-point operand in register FRA.
Let e_b be the unbiased exponent of the double-precision floating-point operand in register FRB.

fe_flag is set to 1 if any of the following conditions occur:
• The double-precision floating-point operand in register FRA is a NaN or an Infinity.
• The double-precision floating-point operand in register FRB is a Zero, a NaN, or an Infinity.
• e_b is less than or equal to -1022.
• e_b is greater than or equal to 1021.
• The double-precision floating-point operand in register FRA is not a zero and the difference, e_a - e_b, is greater than or equal to 1023.
• The double-precision floating-point operand in register FRA is not a zero and the difference, e_a - e_b, is less than or equal to -1021.
• The double-precision floating-point operand in register FRA is not a zero and e_a is less than or equal to -970.

Otherwise fe_flag is set to 0.

gf_flag is set to 1 if the following condition occurs:
• The double-precision floating-point operand in register FRB is a Zero, an Infinity, or a denormalized value.
• The double-precision floating-point operand in register FRA is an Infinity.

Otherwise fg_flag is set to 0.

If the implementation guarantees a relative error of fre[s][.] of less than or equal to 2^-14, then fl_flag is set to 1. Otherwise fl_flag is set to 0.

CR field BF is set to the value fl_flag || fg_flag || fe_flag || 0b0.

ftdiv and ftsqrt are provided to accelerate software emulation of divide and square root operations, by performing the requisite special case checking. Software needs only a single branch, on FE=1 (in CR[BF]), to a special case handler. FG and FL may provide further acceleration opportunities.


Summary: Tests for conditions that would cause a sqrt exception.

Tests the floating-point value in FRB to determine if it would cause an exception when used as the operand to a square root instruction, setting the condition bits in CR field BF accordingly. The result encodes whether the operand is negative, zero, positive, or a special value (NaN, infinity). No floating-point result is produced and FPSCR is not modified.

if FRB < 0.0 then
  CR[BF] ← 0b1000
else if FRB = 0.0 then
  CR[BF] ← 0b0100
else if FRB > 0.0 then
  CR[BF] ← 0b0010
else
  CR[BF] ← 0b0001

The ftsqrt instruction is useful for checking special conditions of a floating-point number before performing square root operations. It sets the FE flag if the operand is zero, NaN, infinity, negative, or has an exponent less than or equal to -970. The FG flag is set if the operand is zero, infinity, or denormalized. Ensure the operand is properly aligned and in double-precision format to avoid unexpected results.


Summary: Estimates the reciprocal of a floating-point operand.

An estimate of the reciprocal of the floating-point operand in register FRB is placed into register FRT. Unless the reciprocal would be a zero, an infinity, the result of a trap-disabled Overflow exception, or a QNaN, the estimate is correct to a precision of one part in 256 of the reciprocal of (FRB).

FPSCR (FPRF, FX, OX, UX, ZX, VXSNAN), CR1 (if Rc=1)

For the Floating-Point Estimate instructions, some implementations might implement a precision higher than the minimum architected precision.

if 'fre' then
    FRT <- estimate(1 / (FRB))
else if 'fre.' then
    FRT <- estimate(1 / (FRB))
    CR1 <- result_class(FRT)


Summary: Estimates the reciprocal of a single-precision floating-point number.

Computes an estimate of the reciprocal (1/x) of the single-precision floating-point value in FRB and stores the result in FRT. The estimate is accurate to approximately 1 part in 256 for normalized values. If Rc=1, CR1 is set based on the result; FPSCR exception bits are set according to the floating-point exception enable controls.

FRT ← estimate(1.0 / FRB)
if Rc = 1 then
  CR1 ← (FRT_exception_summary)

The fres instruction provides a fast estimate of the reciprocal for single-precision floating-point numbers. It's useful in performance-critical applications where exact precision is not required, but speed is essential. Be cautious with inputs that have an unbiased exponent greater than +127, as they are treated as Infinity, which might lead to unexpected results if not handled properly.


Floating Reciprocal Square Root Estimate

Summary: Estimates the reciprocal of the square root of a floating-point operand.

A estimate of the reciprocal of the square root of the floating-point operand in register FRB is placed into register FRT. The estimate placed into register FRT is correct to a precision of one part in 32 of the reciprocal of the square root of (FRB).

The frsqrte instruction provides a fast, approximate reciprocal square root calculation. It is useful for performance-critical applications where precision can be traded for speed. Ensure the input in FRB is positive to avoid undefined behavior. The result may need refinement for higher precision applications.


Floating Reciprocal Square Root Estimate Single

Summary: Estimates 1/sqrt(x) (Single Precision).

Computes an estimate of the reciprocal of the square root (1/sqrt(x)) of the single-precision floating-point value in FRB and stores the result in FRT. The estimate is accurate to approximately 1 part in 256 for normalized positive values. If Rc=1, CR1 is set based on the result; FPSCR exception bits are set according to floating-point exception enable controls.

FRT ← estimate(1.0 / sqrt(FRB))
if Rc = 1 then
  CR1 ← (FRT_exception_summary)

The frsqrtes instruction provides a fast estimate of the reciprocal square root, suitable for performance-critical applications where precision is less critical than speed. Be aware that it may raise exceptions for special values like NaN or infinity, and results are only accurate to within one part in 32 of the true value.


Summary: Returns control to the address specified by EBBRR0:61 || 0b00 or 320 || EBBRR32:61 || 0b00, depending on MSRSF.

The instruction sets BESCRGE to S and updates NIA based on the event-based branch facility's state. If there are no pending exceptions, it fetches the next instruction from a specific address; otherwise, it generates an event-based branch.

if 'rfebb' then
    BESCRGE <- S
    if MSRSF=1 then
        NIA <- iea EBBRR0:61 || 0b00
    else
        NIA <- 320 || EBBRR32:61 || 0b00

rfebb serves as both a basic and an extended mnemonic. The Assembler will recognize an rfebb mnemonic with one operand as the basic form, and an rfebb mnemonic with no operand as the intended form. In the extended form, the S operand is omitted and assumed to be 1.


Summary: Sets the target register based on the condition register field BFA.

If bit 0 of CR field BFA is set to 1, the contents of register RT are set to 0xFFFF_FFFF_FFFF_FFFF. If bit 1 of CR field BFA is set to 1, the contents of register RT are set to 0x0000_0000_0000_0001. Otherwise, the contents of register RT are set to 0x0000_0000_0000_0000.

if CR4×BFA+32=1 then
    RT ←0xFFFF_FFFF_FFFF_FFFF
else if CR4×BFA+33=1 then
    RT ←0x0000_0000_0000_0001
else
    RT ←0x0000_0000_0000_0000

The setb instruction is commonly used to conditionally set a register based on the state of specific bits in the CR (Condition Register). Ensure that the BFA field correctly reflects the desired condition before executing this instruction. This instruction operates at user privilege level and does not generate exceptions under normal conditions.


Summary: Divides the contents of two registers and updates the condition register.

For divde, the quotient of the contents of register RA (dividend) divided by RB (divisor) is placed into register RT. The operands are interpreted as signed integers.

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.


Summary: 64-bit extended unsigned division.

Performs unsigned extended division of a 128-bit dividend (RA || R0) by the 64-bit unsigned divisor in RB, placing the 64-bit quotient in RT. If OE=1 and overflow occurs, the OV bit in XER is set; if Rc=1, CR0 is set based on the quotient. Division by zero produces undefined results.

dividend ← (RA || 0)  # 128-bit value: RA in high 64 bits, 0 in low 64 bits
RT ← dividend / RB
if OE = 1 then
  XER[OV] ← overflow_flag
if Rc = 1 then
  CR0 ← (RT_comparison_summary)


Summary: Performs a signed division of a 64-bit dividend by a 32-bit divisor and places the result in a 32-bit register.

The 64-bit dividend is formed from the upper 32 bits of RA (RA32:63) concatenated with 320. The 32-bit divisor is taken from RB (RB32:63). If the quotient can be represented in 32 bits, it is placed into RT32:63. The contents of RT0:31 are undefined.

if 'divwe' then
    dividend0:63 ← (RA)32:63 || 320
    divisor0:31 ← (RB)32:63
    RT32:63 ← dividend ÷ divisor
    RT0:31 ← undefined


Summary: Performs an unsigned division of a 64-bit dividend by a 32-bit divisor and returns the quotient in a 32-bit register.

Performs unsigned extended division of a 64-bit dividend (RA || R0) by the 32-bit unsigned divisor in RB, placing the 32-bit quotient in RT. If OE=1 and overflow occurs, the OV bit in XER is set; if Rc=1, CR0 is set based on the quotient. Division by zero produces undefined results.

dividend ← (RA || 0)  # 64-bit value: RA in high 32 bits, 0 in low 32 bits
RT ← dividend / RB
if OE = 1 then
  XER[OV] ← overflow_flag
if Rc = 1 then
  CR0 ← (RT_comparison_summary)


Summary: Performs a bitwise AND operation on the contents of two vector registers and stores the result in another vector register.

Performs a bitwise logical AND of the 128-bit contents of vector registers vA and vB, storing the 128-bit result in vector register vD. This operation is performed element-independently across all bits without regard to element boundaries. No status flags are affected.

The vand instruction requires the vector facility to be enabled (MSR.VEC=1); otherwise, it will raise a Vector_Unavailable exception. Ensure that the vector registers are properly aligned and initialized before performing operations.


Summary: Bitwise OR of two 128-bit vectors.

Performs a bitwise OR of two 128-bit vector registers and stores the result in a third vector register. Each bit position of the result is set if the corresponding bit in either input vector is set. No status flags are affected.

The vor instruction requires the Vector Facility to be enabled in the MSR register; otherwise, it will raise a Vector Unavailable exception. Ensure that the vector registers involved are properly aligned and contain valid data for accurate results.


Summary: Bitwise XOR of two 128-bit vectors.

Performs a bitwise XOR (exclusive OR) of two 128-bit vector registers and stores the result in a third vector register. Each bit position of the result is set if the corresponding bits in the two input vectors differ. No status flags are affected.

The vxor instruction is used to perform a bitwise XOR operation on two vector registers and store the result in another. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. This instruction operates on 128-bit vector registers.


Summary: Performs a logical NOR operation on the contents of two vector registers and stores the result in another vector register.

The contents of VSR[VRA+32] are ORed with the contents of VSR[VRB+32], and the complemented result is placed into VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
else
    VSR[VRT+32] ←¬( VSR[VRA+32] | VSR[VRB+32] )

The vnor instruction performs a bitwise NOR operation on two vector registers and stores the result in another register. Ensure that the Vector Facility is enabled by checking and setting the MSR.VEC bit; otherwise, a Vector_Unavailable exception will be raised. This instruction operates at the user privilege level.


Summary: Bitwise AND of vA with the ones' complement of vB (vA & ~vB).

Performs a bitwise AND of vA with the ones' complement of vB, effectively computing vA & ~vB, and stores the result in vD. Each bit is set in the result only if it is set in vA and clear in vB. No status flags are affected.

The vandc instruction requires the Vector Facility to be enabled; otherwise, it will raise an exception. Ensure that the MSR.VEC bit is set before using this instruction. This operation is useful for masking bits where you want to retain certain bits while complementing others.


Summary: Compares two vector registers element by element as unsigned bytes and sets the target vector register based on the comparison.

The Vector Integer Compare instructions compare two VSRs element by element, interpreting the elements as unsigned or signed integers depending on the instruction, and set the corresponding element of the target VSR to all 1s if the relation being tested is true and to all 0s if the relation being tested is false.

if MSR.VEC=0 then Vector_Unavailable()
all_true ←1
all_false ←1
do i = 0 to 15
    src1 ←VSR[VRA+32].byte[i]
    src2 ←VSR[VRB+32].byte[i]
    if src1 = src2 then do
        VSR[VRT+32].byte[i] ←0xFF
        all_false ←0
    end
    else do
        VSR[VRT+32].byte[i] ←0x00
        all_true ←0
    end
end
if Rc=1 then
    CR.field[6] ←all_true || 0b0 || all_false || 0b0

vcmpequb[.], vcmpequh[.], vcmpequw[.], and vcmpequd[.] can be used for unsigned or signed integers.


Summary: Compares each halfword of two vector registers and sets the corresponding halfword in the target register to all 1s if they are equal, otherwise all 0s.

For vcmpequh, each halfword of VSR[VRA+32] is compared with the corresponding halfword of VSR[VRB+32]. If they are equal, the corresponding halfword in VSR[VRT+32] is set to all 1s (0xFFFF); otherwise, it is set to all 0s (0x0000).

if MSR.VEC=0 then Vector_Unavailable()

all_true ←1
all_false ←1
do i = 0 to 7
   src1 ←VSR[VRA+32].hword[i]
   src2 ←VSR[VRB+32].hword[i]
   if src1 = src2 then do
      VSR[VRT+32].hword[i] ←0xFFFF
      all_false ←0
   end
   else do
      VSR[VRT+32].hword[i] ←0x0000
      all_true ←0
   end
end
do i = 0 to 7
   src1 ←VSR[VRA+32].hword[i]
   src2 ←VSR[VRB+32].hword[i]
   if src1 = src2 then do
      VSR[VRT+32].hword[i] ←0xFFFF
      all_false ←0
   end
   else do
      VSR[VRT+32].hword[i] ←0x0000
      all_true ←0
   end
end
if Rc=1 then
   CR.field[6] ←all_true || 0b0 || all_false || 0b0

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.


Summary: Compares two vector registers for equality on an unsigned doubleword basis and stores the result in a third vector register.

Compares two vector registers element-wise for equality on an unsigned doubleword basis (2 64-bit elements) and stores a mask in the destination vector register, with all 1s where elements are equal and all 0s where unequal. When the record bit (.) is set, the CR6 field is updated to reflect whether any or all comparisons are equal.

for i in 0 to 1 do
  if VRA[i] = VRB[i] then
    VRT[i] ← 0xFFFF_FFFF_FFFF_FFFF
  else
    VRT[i] ← 0x0000_0000_0000_0000
if Rc = 1 then CR6 ← comparison results


Vector Compare Greater Than Unsigned Byte

Summary: Unsigned > comparison for 16 bytes.

Performs an unsigned greater-than comparison of two vector registers on a byte-by-byte basis (16 bytes) and stores a mask in the destination vector register, with all 1s where the comparison is true and all 0s where false. No CR or XER flags are modified by this instruction.

for i in 0 to 15 do
  if vA[i] > vB[i] (unsigned) then
    vD[i] ← 0xFF
  else
    vD[i] ← 0x00

vcmpgtub is useful for comparing unsigned byte values in vectors. Ensure both source vectors are properly aligned to avoid alignment faults. The instruction updates CR field 6 if Rc=1, indicating comparison results; check this for conditional logic. Performance may vary based on vector length and data distribution.


Summary: Compares each byte of two vector registers and sets the corresponding result byte to all 1s if the signed byte in the first source register is greater than the signed byte in the second source register, otherwise sets it to all 0s.

For vcmpgtsb, each byte of VSR[VRA+32] is compared with the corresponding byte of VSR[VRB+32]. If the signed byte in VSR[VRA+32] is greater than the signed byte in VSR[VRB+32], then the corresponding byte in VSR[VRT+32] is set to all 1s (0xFF). Otherwise, it is set to all 0s (0x00).

if MSR.VEC=0 then Vector_Unavailable()
all_true ←1
all_false ←1
do i = 0 to 15
    src1 ←EXTS(VSR[VRA+32].byte[i])
    src2 ←EXTS(VSR[VRB+32].byte[i])
    if src1 > src2 then do
        VSR[VRT+32].byte[i] ←0xFF
        all_false ←0
    end
    else do
        VSR[VRT+32].byte[i] ←0x00
        all_true ←0
    end
end
if Rc=1 then
    CR.field[6] ←all_true || 0b0 || all_false || 0b0


Vector Compare Greater Than Unsigned Halfword

Summary: Unsigned > comparison for 8 halfwords.

Performs an unsigned greater-than comparison of two vector registers on a halfword-by-halfword basis (8 halfwords) and stores a mask in the destination vector register, with all 1s where the comparison is true and all 0s where false. No CR or XER flags are modified by this instruction.

for i in 0 to 7 do
  if vA[i] > vB[i] (unsigned) then
    vD[i] ← 0xFFFF
  else
    vD[i] ← 0x0000

The vcmpgtuh instruction is commonly used for comparing unsigned halfword elements in vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The instruction updates the CR field if Rc=1, which can be useful for conditional branching based on the comparison results.


Vector Compare Greater Than Signed Halfword

Summary: Compares each halfword of two vector registers and sets the corresponding result element to all 1s if the first operand is greater than the second, otherwise all 0s.

For vcmpgtsh, each halfword of VSR[VRA+32] is compared with the corresponding halfword of VSR[VRB+32]. If the signed value in VSR[VRA+32].hword[i] is greater than that in VSR[VRB+32].hword[i], then VSR[VRT+32].hword[i] is set to 0xFFFF; otherwise, it is set to 0x0000.

if MSR.VEC=0 then Vector_Unavailable()
all_true ←1
all_false ←1
do i = 0 to 7
    src1 ←EXTS(VSR[VRA+32].hword[i])
    src2 ←EXTS(VSR[VRB+32].hword[i])
    if src1 > src2 then do
        VSR[VRT+32].hword[i] ←0xFFFF
        all_false ←0
    end
    else do
        VSR[VRT+32].hword[i] ←0x0000
        all_true ←0
    end
end
if Rc=1 then
    CR.field[6] ←all_true || 0b0 || all_false || 0b0


Vector Compare Greater Than Unsigned Word

Summary: Unsigned > comparison for 4 words.

Performs an unsigned greater-than comparison of two vector registers on a word-by-word basis (4 words) and stores a mask in the destination vector register, with all 1s where the comparison is true and all 0s where false. No CR or XER flags are modified by this instruction.

for i in 0 to 3 do
  if vA[i] > vB[i] (unsigned) then
    vD[i] ← 0xFFFF_FFFF
  else
    vD[i] ← 0x0000_0000

This instruction is commonly used for element-wise comparison of unsigned integers in vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The result register must be aligned to 128 bits, and both source registers should contain valid data. If Rc=1, CR field 6 will reflect whether all comparisons were true or false, which can be useful for conditional branching based on vector comparison results.


Summary: Compares each word of two vector registers and sets the corresponding word in the target vector register to all 1s if the first operand is greater than the second, otherwise to all 0s.

For vcmpgtsw, each word of VSR[VRA+32] is compared with the corresponding word of VSR[VRB+32]. If the signed integer value in the word element i of VSR[VRA+32] is greater than that in VSR[VRB+32], then the contents of word element i of VSR[VRT+32] are set to all 1s; otherwise, they are set to all 0s.

if MSR.VEC=0 then
    Vector_Unavailable()
all_true ←1
all_false ←1
do i = 0 to 3
    src1 ←EXTS(VSR[VRA+32].word[i])
    src2 ←EXTS(VSR[VRB+32].word[i])
    if src1 > src2 then do
        VSR[VRT+32].word[i] ←0xFFFF_FFFF
        all_false ←0
    end
    else do
        VSR[VRT+32].word[i] ←0x0000_0000
        all_true ←0
    end
end
if Rc=1 then
    CR.field[6] ←all_true || 0b0 || all_false || 0b0


Vector Compare Greater Than Unsigned Doubleword

Summary: Compares the contents of two vector registers and sets a result based on whether each element in the first register is greater than the corresponding element in the second register.

for i in 0 to 1 do
  if vA[i] > vB[i] (unsigned) then
    vD[i] ← 0xFFFF_FFFF_FFFF_FFFF
  else
    vD[i] ← 0x0000_0000_0000_0000

Performs an unsigned greater-than comparison of two vector registers on a doubleword-by-doubleword basis (2 doublewords) and stores a mask in the destination vector register, with all 1s where the comparison is true and all 0s where false. No CR or XER flags are modified by this instruction.

This instruction is commonly used in scenarios where you need to compare unsigned integers stored in vector registers. Ensure that the input vectors are properly aligned and that the Rc flag is set if you need to use CR6 for further conditional logic. Be aware that this instruction operates on doublewords, so each element must be 32 bits wide.


Vector Compare Greater Than Signed Doubleword

Summary: Compares two doublewords of signed integers and sets the result vector based on the comparison.

For vcmpgtsd, each doubleword in VSR[VRA+32] is compared to the corresponding doubleword in VSR[VRB+32]. If a doubleword in VSR[VRA+32] is greater than the corresponding doubleword in VSR[VRB+32], the corresponding doubleword in VSR[VRT+32] is set to all 1s; otherwise, it is set to all 0s.

if MSR.VEC=0 then Vector_Unavailable()
all_true ←1
all_false ←1
do i = 0 to 1
    src1 ←EXTS(VSR[VRA+32].dword[i])
    src2 ←EXTS(VSR[VRB+32].dword[i])
    if src1 > src2 then do
        VSR[VRT+32].dword[i] ←0xFFFF_FFFF_FFFF_FFFF
        all_false ←0
    end
    else do
        VSR[VRT+32].dword[i] ←0x0000_0000_0000_0000
        all_true ←0
    end
end
if Rc=1 then
    CR.field[6] ←all_true || 0b0 || all_false || 0b0


Summary: Computes (a+b+1)/2 for bytes.

Computes the average of corresponding unsigned bytes in vA and vB using rounding (vA + vB + 1) >> 1, storing the result in vD. This is a vector operation that processes 16 independent byte elements in parallel. No condition flags or status fields are affected.

The vavgub instruction is commonly used for averaging pixel values in image processing tasks. Ensure that the source vectors are properly aligned to avoid performance penalties. This instruction operates at user privilege level and will raise an exception if the vector facility is not enabled (MSR.VEC=0).


Summary: Performs a signed byte-wise average of two vector registers and stores the result in another vector register.

For vavgsb, each byte element of VSR[VRA+32] is added to the corresponding byte element of VSR[VRB+32], incremented by 1, then right-shifted by 1 bit. The low-order 8 bits of the result are placed into the corresponding byte element of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 15
    src1 ←EXTS(VSR[VRA+32].byte[i])
    src2 ←EXTS(VSR[VRB+32].byte[i])
    VSR[VRT+32].byte[i] ←CHOP8((src1 + src2 + 1) >> 1)
end

The vavgsb instruction performs a signed byte average, rounding up by adding 1 before shifting. Ensure that the Vector Facility is enabled in the MSR register to avoid exceptions. This operation is useful for blending two images or averaging data with precision.


Summary: Computes (a+b+1)/2 for halfwords.

Computes the average of corresponding unsigned halfwords in vA and vB using rounding (vA + vB + 1) >> 1, storing the result in vD. This is a vector operation that processes 8 independent halfword elements in parallel. No condition flags or status fields are affected.

The vavguh instruction is used to compute the average of corresponding halfwords from two source vectors, rounding up. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set; otherwise, a Vector_Unavailable exception will be raised. This instruction operates on 16-bit unsigned integers and stores the result in the destination vector. Be cautious of overflow when adding the two source halfwords before rounding.


Summary: Performs a signed halfword average operation on vector elements.

For vavgsh, the sum of the contents of each corresponding pair of halfwords from VSR[VRA+32] and VSR[VRB+32] is calculated, incremented by 1, shifted right by 1 bit, and then placed into the corresponding halfword in VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 7
    src1 ←EXTS(VSR[VRA+32].hword[i])
    src2 ←EXTS(VSR[VRB+32].hword[i])
    VSR[VRT+32].hword[i] ← CHOP16((src1 + src2 + 1) >> 1)
end

The vavgsh instruction performs a signed halfword average, rounding up by adding 1 before shifting. Ensure that the vector facility is enabled in the MSR register to avoid exceptions. This operation processes each pair of halfwords independently, so alignment requirements are minimal.


Summary: Computes (a+b+1)/2 for words.

Computes the average of corresponding unsigned words in vA and vB using rounding (vA + vB + 1) >> 1, storing the result in vD. This is a vector operation that processes 4 independent word elements in parallel. No condition flags or status fields are affected.

The vavguw instruction is used to compute the average of unsigned word elements from two vectors. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set; otherwise, a Vector_Unavailable exception will be raised. This instruction processes each 32-bit word element independently, so alignment requirements are not strict. Be cautious with potential overflow when summing large unsigned integers.


Summary: Performs a vector average of signed words from two source vectors and stores the result in a destination vector.

For vavgsw, each word element in VSR[VRA+32] is added to the corresponding word element in VSR[VRB+32], incremented by 1, and then shifted right by 1 bit. The low-order 32 bits of the result are placed into the corresponding word element in VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ←EXTS(VSR[VRA+32].word[i])
    src2 ←EXTS(VSR[VRB+32].word[i])
    VSR[VRT+32].word[i] ← Chop32((src1 + src2 + 1) >> 1)

vavgsw is used for averaging signed word elements from two vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. The operation includes an implicit rounding by adding 1 before shifting right, which can affect results for negative numbers. This instruction operates on 32-bit word elements and requires proper alignment of input vectors.


Summary: Selects minimum value per byte (unsigned).

Selects the minimum unsigned value for each corresponding byte pair from vA and vB, storing the results in vD. This is a vector operation that performs 16 independent byte-wise minimum comparisons in parallel. No condition flags or status fields are affected.

for i in 0 to 15 do
  vD[8*i:8*i+7] ← MIN_UNSIGNED(vA[8*i:8*i+7], vB[8*i:8*i+7])
end for

The vminub instruction is used to perform element-wise minimum comparison of unsigned bytes between two vector registers and store the results in a third register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation is straightforward but requires both source vectors to be properly aligned for optimal performance.


Summary: Compares the signed byte elements of two vector registers and stores the minimum values in a third vector register.

For vminsb, each byte element of VSR[VRA+32] is compared to the corresponding byte element of VSR[VRB+32]. The smaller value is stored in the corresponding byte element of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 15
    src1 ← VSR[VRA+32].byte[i]
    src2 ← VSR[VRB+32].byte[i]
    lt_flag ← EXTS(src1) < EXTS(src2)
    VSR[VRT+32].byte[i] ← lt_flag=1 ? src1 : src2
end

This instruction is used to perform element-wise minimum comparison on signed byte values. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation respects the sign of the bytes, so it correctly handles negative numbers. There are no specific alignment requirements for the vector registers involved.


Summary: Selects minimum value per halfword (unsigned).

Selects the minimum unsigned value for each corresponding halfword pair from vA and vB, storing the results in vD. This is a vector operation that performs 8 independent halfword-wise minimum comparisons in parallel. No condition flags or status fields are affected.

The vminuh instruction is used to perform element-wise minimum operations on unsigned halfwords from two source vectors. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation does not require any specific alignment for the data, but both source and destination vectors must be properly loaded into the vector registers VRA, VRB, and VRT respectively.


Summary: Compares the signed halfwords of two vector registers and selects the minimum value for each corresponding pair.

For vminsh, the instruction compares the signed halfwords of VSR[VRA+32] and VSR[VRB+32]. The smaller value is placed into the corresponding halfword element of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 7
    src1 ← VSR[VRA+32].hword[i]
    src2 ← VSR[VRB+32].hword[i]
    lt_flag ← EXTS(src1) < EXTS(src2)
    VSR[VRT+32].hword[i] ← lt_flag=1 ? src1 : src2
end

This instruction is used to perform element-wise minimum comparison of signed halfwords from two vector registers and store the results in another vector register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation respects the sign of the halfwords, so negative values are correctly handled. There are no specific alignment requirements for the data being processed.


Summary: Selects minimum value per word (unsigned).

Selects the minimum unsigned value for each corresponding word pair from vA and vB, storing the results in vD. This is a vector operation that performs 4 independent word-wise minimum comparisons in parallel. No condition flags or status fields are affected.

The vminuw instruction is used to perform element-wise minimum operations on unsigned words from two vectors. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation is performed in parallel across four elements per vector register.


Summary: Compares the signed integer values in each word element of two vector registers and stores the smaller value into a target vector register.

For vminsw, the instruction compares the signed integer values in each word element of VSR[VRA+32] and VSR[VRB+32]. The smaller value is placed into the corresponding word element of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ← VSR[VRA+32].word[i]
    src2 ← VSR[VRB+32].word[i]
    lt_flag ← EXTS(src1) < EXTS(src2)
    VSR[VRT+32].word[i] ← lt_flag=1 ? src1 : src2

This instruction is used to perform element-wise minimum comparison of signed 32-bit integers in vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation respects the sign of the integers, so negative numbers are correctly handled as expected in signed comparisons.


Summary: Selects maximum value per byte (unsigned).

Selects the maximum unsigned value for each corresponding byte pair from vA and vB, storing the results in vD. This is a vector operation that performs 16 independent byte-wise maximum comparisons in parallel. No condition flags or status fields are affected.

for i in 0 to 15 do
  vD[8*i:8*i+7] ← MAX_UNSIGNED(vA[8*i:8*i+7], vB[8*i:8*i+7])
end for

The vmaxub instruction is used to perform element-wise comparison of unsigned bytes from two vector registers and store the maximum values in a third register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. This instruction operates on 16-byte vectors, so ensure proper alignment for optimal performance.


Summary: Performs a signed byte-wise maximum operation on two vector registers and stores the result in another vector register.

For vmaxsb, each byte element of VSR[VRA+32] is compared with the corresponding byte element of VSR[VRB+32]. The larger value is stored in the corresponding byte element of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 15
    src1 ← VSR[VRA+32].byte[i]
    src2 ← VSR[VRB+32].byte[i]
    gt_flag ← EXTS(src1) > EXTS(src2)
    VSR[VRT+32].byte[i] ← gt_flag=1 ? src1 : src2
end

This instruction is used to perform element-wise signed byte comparisons and store the maximum values in the destination vector. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation respects the signed nature of bytes, so developers should be cautious with negative values. This instruction operates on 16 byte elements and does not require any specific alignment for the vector registers.


Summary: Selects maximum value per halfword (unsigned).

Selects the maximum unsigned value for each corresponding halfword pair from vA and vB, storing the results in vD. This is a vector operation that performs 8 independent halfword-wise maximum comparisons in parallel. No condition flags or status fields are affected.

The vmaxuh instruction is used to perform element-wise comparisons of unsigned halfwords from two source vectors and store the maximum values in a destination vector. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. This instruction operates on 16-bit unsigned integers, so ensure proper alignment and data type handling to avoid unexpected results.