Summary: Calculate masked bitwise OR on an unsigned 32-bit integer location in a data share, given mask value and bits to OR in the data registers.

addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);
tmp = MEM[addr].b32;
MEM[addr].b32 = ((tmp & ~DATA.b32) | DATA2.b32);
RETURN_DATA.b32 = tmp


Summary: Calculate masked bitwise OR on an unsigned 64-bit integer location in a data share, given mask value and bits to OR in the data registers.

addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);
tmp = MEM[addr].b64;
MEM[addr].b64 = ((tmp & ~DATA.b64) | DATA2.b64);
RETURN_DATA.b64 = tmp


Summary: Do nothing.

Do nothing.


Summary: Calculate bitwise OR given two unsigned 32-bit integer values stored in the data register and a location in a data share.

addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);
tmp = MEM[addr].b32;
MEM[addr].b32 = (tmp | DATA.b32);
RETURN_DATA.b32 = tmp


Summary: Calculate bitwise OR given two unsigned 64-bit integer values stored in the data register and a location in a data share.

addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);
tmp = MEM[addr].b64;
MEM[addr].b64 = (tmp | DATA.b64);
RETURN_DATA.b64 = tmp


Calculate bitwise OR given two unsigned 32-bit integer values stored in the data register and a location in a data share. Store the original value from data share into a vector register.


Calculate bitwise OR given two unsigned 64-bit integer values stored in the data register and a location in a data share. Store the original value from data share into a vector register.


Summary: AMDGPU DS vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU DS vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: GDS-only.

GDS-only. Add (count_bits(exec_mask)) to one of 4 dedicated ordered-count counters (aka 'packers'). Additional bits of instr.offset field are overloaded to hold packer-id, 'last'.


Summary: Transfer parameter data from LDS to VGPRs and expand data in LDS using the NewPrimMask (provided in M0) to place per-quad data into lanes 0-3 of each…

Transfer parameter data from LDS to VGPRs and expand data in LDS using the NewPrimMask (provided in M0) to place per-quad data into lanes 0-3 of each quad as follows:


Summary: Forward-permute: each lane sends its value to a lane index computed by another lane, via the LDS crossbar (no LDS storage consumed).

Forward permute. This does not access LDS memory and may be called even if no LDS memory is allocated to the wave. It uses LDS to implement an arbitrary swizzle across threads in a wavefront.

VDST[dst_lane(lane)] = DATA[lane], where dst_lane is computed per-lane from ADDR; lanes that receive no value read undefined/zero depending on target.

ds_permute_b32  v1, v0, v2   // v1[lane] = v2[dest_lane(v0[lane])]


Summary: Add a packed 2-component BF16 float value in the data register to a location in a data share.

Floating-point addition handles NAN/INF/denorm.


Summary: Add a packed 2-component half-precision float value in the data register to a location in a data share.


Add a packed 2-component BF16 float value in the data register to a location in a data share. Store the original value from data share into a vector register.


Add a packed 2-component half-precision float value in the data register to a location in a data share. Store the original value from data share into a vector register.


Summary: Load 32 bits of data from one location in a data share and then 32 bits of data from a second location in a data share and store the results into a…

Load 32 bits of data from one location in a data share and then 32 bits of data from a second location in a data share and store the results into a 64-bit vector register.

addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);
RETURN_DATA[31 : 0] = MEM[addr + OFFSET0.u32 * 4U].b32;
addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);
RETURN_DATA[63 : 32] = MEM[addr + OFFSET1.u32 * 4U].b32


Summary: Load 64 bits of data from one location in a data share and then 64 bits of data from a second location in a data share and store the results into a…

Load 64 bits of data from one location in a data share and then 64 bits of data from a second location in a data share and store the results into a 128-bit vector register.

addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);
RETURN_DATA[31 : 0] = MEM[addr + OFFSET0.u32 * 8U].b32;
RETURN_DATA[63 : 32] = MEM[addr + OFFSET0.u32 * 8U + 4U].b32;
addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);
RETURN_DATA[95 : 64] = MEM[addr + OFFSET1.u32 * 8U].b32;
RETURN_DATA[127 : 96] = MEM[addr + OFFSET1.u32 * 8U + 4U].b32


Load 32 bits of data from one location in a data share and then 32 bits of data from a second location in a data share and store the results into a 64-bit vector register. Treat each offset as an index and multiply by a stride of 64 elements (256 bytes) to generate an offset for each DS address.

addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);
RETURN_DATA[31 : 0] = MEM[addr + OFFSET0.u32 * 256U].b32;
addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);
RETURN_DATA[63 : 32] = MEM[addr + OFFSET1.u32 * 256U].b32


Load 64 bits of data from one location in a data share and then 64 bits of data from a second location in a data share and store the results into a 128-bit vector register. Treat each offset as an index and multiply by a stride of 64 elements (256 bytes) to generate an offset for each DS address.

addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);
RETURN_DATA[31 : 0] = MEM[addr + OFFSET0.u32 * 512U].b32;
RETURN_DATA[63 : 32] = MEM[addr + OFFSET0.u32 * 512U + 4U].b32;
addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);
RETURN_DATA[95 : 64] = MEM[addr + OFFSET1.u32 * 512U].b32;
RETURN_DATA[127 : 96] = MEM[addr + OFFSET1.u32 * 512U + 4U].b32


Load 32 bits of data from a data share into a vector register. The memory base address is provided as an immediate value and the lane ID is used as an offset.

declare OFFSET0 : 8'U;
declare OFFSET1 : 8'U;
RETURN_DATA.u32 = MEM[32'I({ OFFSET1, OFFSET0 } + M0[15 : 0]) + laneID.i32 * 4].u32


Summary: Load 128 bits of data from a data share into a vector register.

addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);
RETURN_DATA[31 : 0] = MEM[addr + OFFSET.u32].b32;
RETURN_DATA[63 : 32] = MEM[addr + OFFSET.u32 + 4U].b32;
RETURN_DATA[95 : 64] = MEM[addr + OFFSET.u32 + 8U].b32;
RETURN_DATA[127 : 96] = MEM[addr + OFFSET.u32 + 12U].b32


Summary: Read one 32-bit value per lane from the Local Data Share (LDS).

Load 32 bits of data from a data share into a vector register.

VDST[lane] = LDS[ADDR[lane] + offset] for each active lane.


Summary: Load 64 bits of data from a data share into a vector register.

addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);
RETURN_DATA[31 : 0] = MEM[addr + OFFSET.u32].b32;
RETURN_DATA[63 : 32] = MEM[addr + OFFSET.u32 + 4U].b32


Read 64 bits of data per lane from data share. Interpret the data as a matrix with 16 bit elements and transpose the matrix. Store the result into vector registers.


Read 64 bits of data per lane from data share. Interpret the data as a matrix with 4 bit elements and transpose the matrix. Store the result into vector registers.


Read 64 bits of data per lane from data share. Interpret the data as a matrix with 8 bit elements and transpose the matrix. Store the result into vector registers.


Summary: Load 96 bits of data from a data share into a vector register.

addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);
RETURN_DATA[31 : 0] = MEM[addr + OFFSET.u32].b32;
RETURN_DATA[63 : 32] = MEM[addr + OFFSET.u32 + 4U].b32;
RETURN_DATA[95 : 64] = MEM[addr + OFFSET.u32 + 8U].b32


Read 96 bits of data per lane from data share. Interpret the data as a matrix with 6 bit elements and transpose the matrix. Store the result into vector registers.


Summary: Load 16 bits of signed data from a data share, sign extend to 32 bits and store the result into a vector register.


Summary: Load 8 bits of signed data from a data share, sign extend to 32 bits and store the result into a vector register.


Summary: Load 8 bits of signed data from a data share, sign extend to 16 bits and store the result into the low 16 bits of a vector register.

RETURN_DATA[15 : 0].i16 = 16'I(signext(MEM[ADDR].i8));
// RETURN_DATA[31:16] is preserved.


Summary: Load 8 bits of signed data from a data share, sign extend to 16 bits and store the result into the high 16 bits of a vector register.

RETURN_DATA[31 : 16].i16 = 16'I(signext(MEM[ADDR].i8));
// RETURN_DATA[15:0] is preserved.


Summary: Load 16 bits of unsigned data from a data share, zero extend to 32 bits and store the result into a vector register.


Summary: Load 16 bits of unsigned data from a data share and store the result into the low 16 bits of a vector register.

RETURN_DATA[15 : 0].u16 = MEM[ADDR].u16;
// RETURN_DATA[31:16] is preserved.


Summary: Load 16 bits of unsigned data from a data share and store the result into the high 16 bits of a vector register.

RETURN_DATA[31 : 16].u16 = MEM[ADDR].u16;
// RETURN_DATA[15:0] is preserved.


Summary: Load 8 bits of unsigned data from a data share, zero extend to 32 bits and store the result into a vector register.

RETURN_DATA.u32 = 32'U({ 24'0U, MEM[ADDR].u8 })


Summary: Load 8 bits of unsigned data from a data share, zero extend to 16 bits and store the result into the low 16 bits of a vector register.

RETURN_DATA[15 : 0].u16 = 16'U({ 8'0U, MEM[ADDR].u8 });
// RETURN_DATA[31:16] is preserved.


Summary: Load 8 bits of unsigned data from a data share, zero extend to 16 bits and store the result into the high 16 bits of a vector register.

RETURN_DATA[31 : 16].u16 = 16'U({ 8'0U, MEM[ADDR].u8 });
// RETURN_DATA[15:0] is preserved.


Subtract an unsigned 32-bit integer value stored in a location in a data share from a value stored in the data register. Store the original value from data share into a vector register.

addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);
tmp = MEM[addr].u32;
MEM[addr].u32 = DATA.u32 - MEM[addr].u32;
RETURN_DATA.u32 = tmp


Subtract an unsigned 64-bit integer value stored in a location in a data share from a value stored in the data register. Store the original value from data share into a vector register.

addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);
tmp = MEM[addr].u64;
MEM[addr].u64 = DATA.u64 - MEM[addr].u64;
RETURN_DATA.u64 = tmp


Summary: AMDGPU DS vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU DS vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Subtract an unsigned 32-bit integer value stored in a location in a data share from a value stored in the data register.


Subtract an unsigned 64-bit integer value stored in a location in a data share from a value stored in the data register.


Summary: Store 32 bits of data from one vector input register and then 32 bits of data from a second vector input register into a data share.


Summary: Store 64 bits of data from one vector input register and then 64 bits of data from a second vector input register into a data share.


Store 32 bits of data from one vector input register and then 32 bits of data from a second vector input register into a data share. Treat each offset as an index and multiply by a stride of 64 elements (256 bytes) to generate an offset for each DS address.


Store 64 bits of data from one vector input register and then 64 bits of data from a second vector input register into a data share. Treat each offset as an index and multiply by a stride of 64 elements (256 bytes) to generate an offset for each DS address.


Store 32 bits of data from a vector input register into a data share. The memory base address is provided as an immediate value and the lane ID is used as an offset.


Summary: Store 128 bits of data from a vector input register into a data share.


Summary: Store 16 bits of data from a vector register into a data share.


Summary: Store 16 bits of data from the high bits of a vector register into a data share.


Store 32 bits of data from a vector input register into a data share.


Summary: Store 64 bits of data from a vector input register into a data share.


Summary: Store 8 bits of data from a vector register into a data share.


Summary: Store 8 bits of data from the high bits of a vector register into a data share.


Summary: Store 96 bits of data from a vector input register into a data share.


Summary: Swap two unsigned 32-bit integer values in the data registers with two locations in a data share.

ds_storexchg_2addr_rtn_b32 v[5:6], v1, v2, v3


Summary: Swap two unsigned 64-bit integer values in the data registers with two locations in a data share.


Swap two unsigned 32-bit integer values in the data registers with two locations in a data share. Treat each offset as an index and multiply by a stride of 64 elements (256 bytes) to generate an offset for each DS address.

ds_storexchg_2addr_stride64_rtn_b32 v[5:6], v1, v2, v3


Swap two unsigned 64-bit integer values in the data registers with two locations in a data share. Treat each offset as an index and multiply by a stride of 64 elements (256 bytes) to generate an offset for each DS address.

ds_storexchg_2addr_stride64_rtn_b64 v[5:8], v1, v[2:3], v[3:4]


Summary: Swap an unsigned 32-bit integer value in the data register with a location in a data share.


Summary: Swap an unsigned 64-bit integer value in the data register with a location in a data share.


Subtract an unsigned 32-bit integer location in a data share from a value in the data register and clamp the result to zero. Store the original value from data share into a vector register.


Subtract an unsigned 32-bit integer location in a data share from a value in the data register and clamp the result to zero.


Perform an atomic subtraction from data in specific registers embedded in GDS rather than operating on GDS memory directly. This instruction returns the pre-op value. This instruction is only used by the GS stage and is used to facilitate streamout.


Subtract an unsigned 32-bit integer value stored in the data register from a value stored in a location in a data share. Store the original value from data share into a vector register.

addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);
tmp = MEM[addr].u32;
MEM[addr].u32 -= DATA.u32;
RETURN_DATA.u32 = tmp


Subtract an unsigned 64-bit integer value stored in the data register from a value stored in a location in a data share. Store the original value from data share into a vector register.

addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);
tmp = MEM[addr].u64;
MEM[addr].u64 -= DATA.u64;
RETURN_DATA.u64 = tmp


Summary: AMDGPU DS vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU DS vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Subtract an unsigned 32-bit integer value stored in the data register from a value stored in a location in a data share.


Subtract an unsigned 64-bit integer value stored in the data register from a value stored in a location in a data share.


Dword swizzle, no data is written to LDS memory. Swizzles input thread data based on offset mask and returns; note does not read or write the DS memory banks. Note that reading from an invalid thread results in 0x0. This opcode supports two specific modes, FFT and rotate, plus two basic modes which swizzle in groups of 4 or 32 consecutive threads.

The FFT mode (offset >= 0xe000) swizzles the input based on offset[4:0] to support FFT calculation. Example
swizzles using input {1, 2, … 20} are:
Offset[4:0]: Swizzle
0x00: {1,11,9,19,5,15,d,1d,3,13,b,1b,7,17,f,1f,2,12,a,1a,6,16,e,1e,4,14,c,1c,8,18,10,20}
0x10: {1,9,5,d,3,b,7,f,2,a,6,e,4,c,8,10,11,19,15,1d,13,1b,17,1f,12,1a,16,1e,14,1c,18,20}
0x1f: No swizzle
The rotate mode (offset >= 0xc000 and offset < 0xe000) rotates the input either left (offset[10] == 0) or right
(offset[10] == 1) a number of threads equal to offset[9:5]. The rotate mode also uses a mask value which can
alter the rotate result. For example, mask == 1 swaps the odd threads across every other even thread (rotate
left), or even threads across every other odd thread (rotate right).
Offset[9:5]: Swizzle
0x01, mask=0, rotate left:
{2,3,4,5,6,7,8,9,a,b,c,d,e,f,10,11,12,13,14,15,16,17,18,19,1a,1b,1c,1d,1e,1f,20,1}
0x01, mask=0, rotate right:
{20,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f,10,11,12,13,14,15,16,17,18,19,1a,1b,1c,1d,1e,1f}
0x01, mask=1, rotate left:
{1,4,3,6,5,8,7,a,9,c,b,e,d,10,f,12,11,14,13,16,15,18,17,1a,19,1c,1b,1e,1d,20,1f,2}
0x01, mask=1, rotate right:
{1f,2,1,4,3,6,5,8,7,a,9,c,b,e,d,10,f,12,11,14,13,16,15,18,17,1a,19,1c,1b,1e,1d,20}
If offset < 0xc000, one of the basic swizzle modes is used based on offset[15]. If offset[15] == 1, groups of 4
consecutive threads are swizzled together. If offset[15] == 0, all 32 threads are swizzled together.
The first basic swizzle mode (when offset[15] == 1) allows full data sharing between a group of 4 consecutive
threads. Any thread within the group of 4 can get data from any other thread within the group of 4, specified by
the corresponding offset bits --- [1:0] for the first thread, [3:2] for the second thread, [5:4] for the third thread,
[7:6] for the fourth thread. Note that the offset bits apply to all groups of 4 within a wavefront; thus if offset[1:0]
== 1, then thread0 grabs thread1, thread4 grabs thread5, etc.
The second basic swizzle mode (when offset[15] == 0) allows limited data sharing between 32 consecutive
threads. In this case, the offset is used to specify a 5-bit xor-mask, 5-bit or-mask, and 5-bit and-mask used to
generate a thread mapping. Note that the offset bits apply to each group of 32 within a wavefront. The details of
the thread mapping are listed below. Some example usages:
SWAPX16 : xor_mask = 0x10, or_mask = 0x00, and_mask = 0x1f
SWAPX8 : xor_mask = 0x08, or_mask = 0x00, and_mask = 0x1f
SWAPX4 : xor_mask = 0x04, or_mask = 0x00, and_mask = 0x1f
SWAPX2 : xor_mask = 0x02, or_mask = 0x00, and_mask = 0x1f
SWAPX1 : xor_mask = 0x01, or_mask = 0x00, and_mask = 0x1f
REVERSEX32 : xor_mask = 0x1f, or_mask = 0x00, and_mask = 0x1f
REVERSEX16 : xor_mask = 0x0f, or_mask = 0x00, and_mask = 0x1f
REVERSEX8 : xor_mask = 0x07, or_mask = 0x00, and_mask = 0x1f
REVERSEX4 : xor_mask = 0x03, or_mask = 0x00, and_mask = 0x1f
REVERSEX2 : xor_mask = 0x01 or_mask = 0x00, and_mask = 0x1f
BCASTX32: xor_mask = 0x00, or_mask = thread, and_mask = 0x00
BCASTX16: xor_mask = 0x00, or_mask = thread, and_mask = 0x10
BCASTX8: xor_mask = 0x00, or_mask = thread, and_mask = 0x18
BCASTX4: xor_mask = 0x00, or_mask = thread, and_mask = 0x1c
BCASTX2: xor_mask = 0x00, or_mask = thread, and_mask = 0x1e
Pseudocode follows:
offset = offset1:offset0;
if (offset >= 0xe000) {
// FFT decomposition
mask = offset[4:0];
for (i = 0; i < 64; i++) {
j = reverse_bits(i & 0x1f);
j = (j >> count_ones(mask));
j |= (i & mask);
j |= i & 0x20;
thread_out[i] = thread_valid[j] ? thread_in[j] : 0;
}
} elsif (offset >= 0xc000) {
// rotate
rotate = offset[9:5];
mask = offset[4:0];
if (offset[10]) {
rotate = -rotate;
}
for (i = 0; i < 64; i++) {
j = (i & mask) | ((i + rotate) & ~mask);
j |= i & 0x20;
thread_out[i] = thread_valid[j] ? thread_in[j] : 0;
}
} elsif (offset[15]) {
// full data sharing within 4 consecutive threads
for (i = 0; i < 64; i+=4) {
thread_out[i+0] = thread_valid[i+offset[1:0]]?thread_in[i+offset[1:0]]:0;
thread_out[i+1] = thread_valid[i+offset[3:2]]?thread_in[i+offset[3:2]]:0;
thread_out[i+2] = thread_valid[i+offset[5:4]]?thread_in[i+offset[5:4]]:0;
thread_out[i+3] = thread_valid[i+offset[7:6]]?thread_in[i+offset[7:6]]:0;
}
} else { // offset[15] == 0
// limited data sharing within 32 consecutive threads
xor_mask = offset[14:10];
or_mask = offset[9:5];
and_mask = offset[4:0];
for (i = 0; i < 64; i++) {
j = (((i & 0x1f) & and_mask) | or_mask) ^ xor_mask;
j |= (i & 0x20); // which group of 32
thread_out[i] = thread_valid[j] ? thread_in[j] : 0;
}
}


Summary: Given a minuend from a location in data share and a subtrahend from a vector register, subtract the two values iff the result is nonnegative…

Given a minuend from a location in data share and a subtrahend from a vector register, subtract the two values iff the result is nonnegative; otherwise add a value from a second vector register to the memory location. This calculation provides flexible wraparound semantics for subtraction.

tmp = MEM[ADDR].u32;
MEM[ADDR].u32 = tmp >= DATA.u32 ? tmp - DATA.u32 : tmp + DATA2.u32;
RETURN_DATA = tmp

This instruction is designed to for use in ring buffer management.


Summary: Store 32 bits of data from one vector input register and then 32 bits of data from a second vector input register into a data share.

addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);
MEM[addr + OFFSET0.u32 * 4U].b32 = DATA[31 : 0];
addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);
MEM[addr + OFFSET1.u32 * 4U].b32 = DATA2[31 : 0]


Summary: Store 64 bits of data from one vector input register and then 64 bits of data from a second vector input register into a data share.

addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);
MEM[addr + OFFSET0.u32 * 8U].b32 = DATA[31 : 0];
MEM[addr + OFFSET0.u32 * 8U + 4U].b32 = DATA[63 : 32];
addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);
MEM[addr + OFFSET1.u32 * 8U].b32 = DATA2[31 : 0];
MEM[addr + OFFSET1.u32 * 8U + 4U].b32 = DATA2[63 : 32]


Store 32 bits of data from one vector input register and then 32 bits of data from a second vector input register into a data share. Treat each offset as an index and multiply by a stride of 64 elements (256 bytes) to generate an offset for each DS address.

addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);
MEM[addr + OFFSET0.u32 * 256U].b32 = DATA[31 : 0];
addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);
MEM[addr + OFFSET1.u32 * 256U].b32 = DATA2[31 : 0]


Store 64 bits of data from one vector input register and then 64 bits of data from a second vector input register into a data share. Treat each offset as an index and multiply by a stride of 64 elements (256 bytes) to generate an offset for each DS address.

addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);
MEM[addr + OFFSET0.u32 * 512U].b32 = DATA[31 : 0];
MEM[addr + OFFSET0.u32 * 512U + 4U].b32 = DATA[63 : 32];
addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);
MEM[addr + OFFSET1.u32 * 512U].b32 = DATA2[31 : 0];
MEM[addr + OFFSET1.u32 * 512U + 4U].b32 = DATA2[63 : 32]


Store 32 bits of data from a vector input register into a data share. The memory base address is provided as an immediate value and the lane ID is used as an offset.

declare OFFSET0 : 8'U;
declare OFFSET1 : 8'U;
MEM[32'I({ OFFSET1, OFFSET0 } + M0[15 : 0]) + laneID.i32 * 4].u32 = DATA0.u32


Summary: Store 128 bits of data from a vector input register into a data share.

addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);
MEM[addr + OFFSET.u32].b32 = DATA[31 : 0];
MEM[addr + OFFSET.u32 + 4U].b32 = DATA[63 : 32];
MEM[addr + OFFSET.u32 + 8U].b32 = DATA[95 : 64];
MEM[addr + OFFSET.u32 + 12U].b32 = DATA[127 : 96]


Summary: Store 16 bits of data from a vector register into a data share.


Summary: Store 16 bits of data from the high bits of a vector register into a data share.


Summary: Write one 32-bit value per lane to the Local Data Share (LDS).

Store 32 bits of data from a vector input register into a data share.

LDS[ADDR[lane] + offset] = DATA[lane] for each active lane.


Summary: Store 64 bits of data from a vector input register into a data share.

addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);
MEM[addr + OFFSET.u32].b32 = DATA[31 : 0];
MEM[addr + OFFSET.u32 + 4U].b32 = DATA[63 : 32]


Summary: Store 8 bits of data from a vector register into a data share.


Summary: Store 8 bits of data from the high bits of a vector register into a data share.


Summary: Store 96 bits of data from a vector input register into a data share.

addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);
MEM[addr + OFFSET.u32].b32 = DATA[31 : 0];
MEM[addr + OFFSET.u32 + 4U].b32 = DATA[63 : 32];
MEM[addr + OFFSET.u32 + 8U].b32 = DATA[95 : 64]


Summary: AMDGPU DS vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU DS vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Swap two unsigned 32-bit integer values in the data registers with two locations in a data share.

addr1 = ADDR_BASE.u32 + OFFSET0.u32 * 4U;
addr2 = ADDR_BASE.u32 + OFFSET1.u32 * 4U;
tmp1 = MEM[addr1].b32;
tmp2 = MEM[addr2].b32;
MEM[addr1].b32 = DATA.b32;
MEM[addr2].b32 = DATA2.b32;
// Note DATA2 can be any other register
RETURN_DATA[31 : 0] = tmp1;
RETURN_DATA[63 : 32] = tmp2


Summary: Swap two unsigned 64-bit integer values in the data registers with two locations in a data share.

addr1 = ADDR_BASE.u32 + OFFSET0.u32 * 8U;
addr2 = ADDR_BASE.u32 + OFFSET1.u32 * 8U;
tmp1 = MEM[addr1].b64;
tmp2 = MEM[addr2].b64;
MEM[addr1].b64 = DATA.b64;
MEM[addr2].b64 = DATA2.b64;
// Note DATA2 can be any other register
RETURN_DATA[63 : 0] = tmp1;
RETURN_DATA[127 : 64] = tmp2


Swap two unsigned 32-bit integer values in the data registers with two locations in a data share. Treat each offset as an index and multiply by a stride of 64 elements (256 bytes) to generate an offset for each DS address.

addr1 = ADDR_BASE.u32 + OFFSET0.u32 * 256U;
addr2 = ADDR_BASE.u32 + OFFSET1.u32 * 256U;
tmp1 = MEM[addr1].b32;
tmp2 = MEM[addr2].b32;
MEM[addr1].b32 = DATA.b32;
MEM[addr2].b32 = DATA2.b32;
// Note DATA2 can be any other register
RETURN_DATA[31 : 0] = tmp1;
RETURN_DATA[63 : 32] = tmp2


Swap two unsigned 64-bit integer values in the data registers with two locations in a data share. Treat each offset as an index and multiply by a stride of 64 elements (256 bytes) to generate an offset for each DS address.

addr1 = ADDR_BASE.u32 + OFFSET0.u32 * 512U;
addr2 = ADDR_BASE.u32 + OFFSET1.u32 * 512U;
tmp1 = MEM[addr1].b64;
tmp2 = MEM[addr2].b64;
MEM[addr1].b64 = DATA.b64;
MEM[addr2].b64 = DATA2.b64;
// Note DATA2 can be any other register
RETURN_DATA[63 : 0] = tmp1;
RETURN_DATA[127 : 64] = tmp2


Summary: Swap an unsigned 32-bit integer value in the data register with a location in a data share.

addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);
tmp = MEM[addr].b32;
MEM[addr].b32 = DATA.b32;
RETURN_DATA.b32 = tmp


Summary: Swap an unsigned 64-bit integer value in the data register with a location in a data share.

addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);
tmp = MEM[addr].b64;
MEM[addr].b64 = DATA.b64;
RETURN_DATA.b64 = tmp


Summary: Calculate bitwise XOR given two unsigned 32-bit integer values stored in the data register and a location in a data share.

addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);
tmp = MEM[addr].b32;
MEM[addr].b32 = (tmp ^ DATA.b32);
RETURN_DATA.b32 = tmp


Summary: Calculate bitwise XOR given two unsigned 64-bit integer values stored in the data register and a location in a data share.

addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);
tmp = MEM[addr].b64;
MEM[addr].b64 = (tmp ^ DATA.b64);
RETURN_DATA.b64 = tmp


Calculate bitwise XOR given two unsigned 32-bit integer values stored in the data register and a location in a data share. Store the original value from data share into a vector register.


Calculate bitwise XOR given two unsigned 64-bit integer values stored in the data register and a location in a data share. Store the original value from data share into a vector register.


Add two unsigned 32-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the SC0 bit is set.

addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
tmp = MEM[addr].u32;
MEM[addr].u32 += DATA.u32;
RETURN_DATA.u32 = tmp


Add a single-precision float value in the data register to a location in the flat aperture. Store the original value from flat aperture into a vector register iff the SC0 bit is set.

tmp = MEM[ADDR].f32;
MEM[ADDR].f32 += DATA.f32;
RETURN_DATA = tmp


Add a double-precision float value in the data register to a location in the flat aperture. Store the original value from flat aperture into a vector register iff the SC0 bit is set.

tmp = MEM[ADDR].f64;
MEM[ADDR].f64 += DATA.f64;
RETURN_DATA = tmp


Add two unsigned 32-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.


Add two unsigned 64-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.


Add two unsigned 64-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the SC0 bit is set.

addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
tmp = MEM[addr].u64;
MEM[addr].u64 += DATA.u64;
RETURN_DATA.u64 = tmp


Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the SC0 bit is set.

addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
tmp = MEM[addr].b32;
MEM[addr].b32 = (tmp & DATA.b32);
RETURN_DATA.b32 = tmp


Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.


Calculate bitwise AND given two unsigned 64-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.


Calculate bitwise AND given two unsigned 64-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the SC0 bit is set.

addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
tmp = MEM[addr].b64;
MEM[addr].b64 = (tmp & DATA.b64);
RETURN_DATA.b64 = tmp


Compare two unsigned 32-bit integer values stored in the data comparison register and a location in the flat aperture. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from flat aperture into a vector register iff the SC0 bit is set. NOTE: RETURN_DATA[1] is not modified.

addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
tmp = MEM[addr].u32;
src = DATA[31 : 0].u32;
cmp = DATA[63 : 32].u32;
MEM[addr].u32 = tmp == cmp ? src : tmp;
RETURN_DATA.u32 = tmp


Compare two unsigned 32-bit integer values stored in the data comparison register and a location in the flat aperture. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.


Compare two unsigned 64-bit integer values stored in the data comparison register and a location in the flat aperture. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.


Compare two single-precision float values stored in the data comparison register and a location in the flat aperture. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from flat aperture into a vector register iff the GLC bit is set.


Compare two unsigned 64-bit integer values stored in the data comparison register and a location in the flat aperture. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from flat aperture into a vector register iff the SC0 bit is set. NOTE: RETURN_DATA[2:3] is not modified.

addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
tmp = MEM[addr].u64;
src = DATA[63 : 0].u64;
cmp = DATA[127 : 64].u64;
MEM[addr].u64 = tmp == cmp ? src : tmp;
RETURN_DATA.u64 = tmp


Summary: Subtract an unsigned 32-bit integer value in the data register from a location in the flat aperture only if the memory value is greater than or equal…

Subtract an unsigned 32-bit integer value in the data register from a location in the flat aperture only if the memory value is greater than or equal to the data register value. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.


Summary: AMDGPU FLAT vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Decrement an unsigned 32-bit integer value from a location in the flat aperture with wraparound to a value in the data register if the decrement…

Decrement an unsigned 32-bit integer value from a location in the flat aperture with wraparound to a value in the data register if the decrement yields a negative value. Store the original value from flat aperture into a vector register iff the SC0 bit is set.

addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
tmp = MEM[addr].u32;
src = DATA.u32;
MEM[addr].u32 = ((tmp == 0U) || (tmp > src)) ? src : tmp - 1U;
RETURN_DATA.u32 = tmp


Decrement an unsigned 32-bit integer value from a location in the flat aperture with wraparound to a value in the data register if the decrement yields a negative value. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.


Summary: Decrement an unsigned 64-bit integer value from a location in the flat aperture with wraparound to a value in the data register if the decrement…

Decrement an unsigned 64-bit integer value from a location in the flat aperture with wraparound to a value in the data register if the decrement yields a negative value. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.


Decrement an unsigned 64-bit integer value from a location in the flat aperture with wraparound to a value in the data register if the decrement yields a negative value. Store the original value from flat aperture into a vector register iff the SC0 bit is set.

addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
tmp = MEM[addr].u64;
src = DATA.u64;
MEM[addr].u64 = ((tmp == 0ULL) || (tmp > src)) ? src : tmp - 1ULL;
RETURN_DATA.u64 = tmp
addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
VDATA[31 : 0] = MEM[addr].b32


Compare two double-precision float values stored in the data comparison register and a location in the flat aperture. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from flat aperture into a vector register iff the GLC bit is set.


Select the maximum of two single-precision float inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the GLC bit is set.


Select the maximum of two double-precision float inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the GLC bit is set.


Select the minimum of two single-precision float inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the GLC bit is set.


Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the GLC bit is set.


Summary: Increment an unsigned 32-bit integer value from a location in the flat aperture with wraparound to 0 if the value exceeds a value in the data…

Increment an unsigned 32-bit integer value from a location in the flat aperture with wraparound to 0 if the value exceeds a value in the data register. Store the original value from flat aperture into a vector register iff the SC0 bit is set.

addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
tmp = MEM[addr].u32;
src = DATA.u32;
MEM[addr].u32 = tmp >= src ? 0U : tmp + 1U;
RETURN_DATA.u32 = tmp


Increment an unsigned 32-bit integer value from a location in the flat aperture with wraparound to 0 if the value exceeds a value in the data register. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.


Summary: Increment an unsigned 64-bit integer value from a location in the flat aperture with wraparound to 0 if the value exceeds a value in the data…

Increment an unsigned 64-bit integer value from a location in the flat aperture with wraparound to 0 if the value exceeds a value in the data register. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.


Increment an unsigned 64-bit integer value from a location in the flat aperture with wraparound to 0 if the value exceeds a value in the data register. Store the original value from flat aperture into a vector register iff the SC0 bit is set.

addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
tmp = MEM[addr].u64;
src = DATA.u64;
MEM[addr].u64 = tmp >= src ? 0ULL : tmp + 1ULL;
RETURN_DATA.u64 = tmp


Select the maximum of two double-precision float inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the SC0 bit is set.

addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
tmp = MEM[addr].f64;
src = DATA.f64;
MEM[addr].f64 = src > tmp ? src : tmp;
RETURN_DATA.f64 = tmp


Select the maximum of two signed 32-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.


Select the maximum of two signed 64-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.


Select the maximum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.


Select the maximum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.


Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the SC0 bit is set.

addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
tmp = MEM[addr].f64;
src = DATA.f64;
MEM[addr].f64 = src < tmp ? src : tmp;
RETURN_DATA.f64 = tmp


Select the minimum of two signed 32-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.


Select the minimum of two signed 64-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.


Select the minimum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.


Select the minimum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.


Calculate bitwise OR given two unsigned 32-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the SC0 bit is set.

addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
tmp = MEM[addr].b32;
MEM[addr].b32 = (tmp | DATA.b32);
RETURN_DATA.b32 = tmp


Calculate bitwise OR given two unsigned 32-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.


Calculate bitwise OR given two unsigned 64-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.


Calculate bitwise OR given two unsigned 64-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the SC0 bit is set.

addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
tmp = MEM[addr].b64;
MEM[addr].b64 = (tmp | DATA.b64);
RETURN_DATA.b64 = tmp


Add a packed 2-component BF16 float value in the data register to a location in the flat aperture. Store the original value from flat aperture into a vector register iff the SC0 bit is set.


Add a packed 2-component half-precision float value in the data register to a location in the flat aperture. Store the original value from flat aperture into a vector register iff the SC0 bit is set.


Select the maximum of two signed 32-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the SC0 bit is set.

addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
tmp = MEM[addr].i32;
src = DATA.i32;
MEM[addr].i32 = src >= tmp ? src : tmp;
RETURN_DATA.i32 = tmp


Select the maximum of two signed 64-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the SC0 bit is set.

addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
tmp = MEM[addr].i64;
src = DATA.i64;
MEM[addr].i64 = src >= tmp ? src : tmp;
RETURN_DATA.i64 = tmp


Select the minimum of two signed 32-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the SC0 bit is set.

addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
tmp = MEM[addr].i32;
src = DATA.i32;
MEM[addr].i32 = src < tmp ? src : tmp;
RETURN_DATA.i32 = tmp


Select the minimum of two signed 64-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the SC0 bit is set.

addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
tmp = MEM[addr].i64;
src = DATA.i64;
MEM[addr].i64 = src < tmp ? src : tmp;
RETURN_DATA.i64 = tmp


Subtract an unsigned 32-bit integer value stored in the data register from a value stored in a location in the flat aperture. Store the original value from flat aperture into a vector register iff the SC0 bit is set.

addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
tmp = MEM[addr].u32;
MEM[addr].u32 -= DATA.u32;
RETURN_DATA.u32 = tmp


Subtract an unsigned 32-bit integer value stored in the data register from a value stored in a location in the flat aperture. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.


Subtract an unsigned 64-bit integer value stored in the data register from a value stored in a location in the flat aperture. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.


Subtract an unsigned 64-bit integer value stored in the data register from a value stored in a location in the flat aperture. Store the original value from flat aperture into a vector register iff the SC0 bit is set.

addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
tmp = MEM[addr].u64;
MEM[addr].u64 -= DATA.u64;
RETURN_DATA.u64 = tmp


Swap an unsigned 32-bit integer value in the data register with a location in the flat aperture. Store the original value from flat aperture into a vector register iff the SC0 bit is set.

addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
tmp = MEM[addr].b32;
MEM[addr].b32 = DATA.b32;
RETURN_DATA.b32 = tmp


Swap an unsigned 32-bit integer value in the data register with a location in the flat aperture. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.


Swap an unsigned 64-bit integer value in the data register with a location in the flat aperture. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.


Swap an unsigned 64-bit integer value in the data register with a location in the flat aperture. Store the original value from flat aperture into a vector register iff the SC0 bit is set.

addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
tmp = MEM[addr].b64;
MEM[addr].b64 = DATA.b64;
RETURN_DATA.b64 = tmp


Select the maximum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the SC0 bit is set.

addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
tmp = MEM[addr].u32;
src = DATA.u32;
MEM[addr].u32 = src >= tmp ? src : tmp;
RETURN_DATA.u32 = tmp


Select the maximum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the SC0 bit is set.

addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
tmp = MEM[addr].u64;
src = DATA.u64;
MEM[addr].u64 = src >= tmp ? src : tmp;
RETURN_DATA.u64 = tmp


Select the minimum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the SC0 bit is set.

addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
tmp = MEM[addr].u32;
src = DATA.u32;
MEM[addr].u32 = src < tmp ? src : tmp;
RETURN_DATA.u32 = tmp


Select the minimum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the SC0 bit is set.

addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
tmp = MEM[addr].u64;
src = DATA.u64;
MEM[addr].u64 = src < tmp ? src : tmp;
RETURN_DATA.u64 = tmp


Calculate bitwise XOR given two unsigned 32-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the SC0 bit is set.

addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
tmp = MEM[addr].b32;
MEM[addr].b32 = (tmp ^ DATA.b32);
RETURN_DATA.b32 = tmp


Calculate bitwise XOR given two unsigned 32-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.


Calculate bitwise XOR given two unsigned 64-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.


Calculate bitwise XOR given two unsigned 64-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the SC0 bit is set.

addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
tmp = MEM[addr].b64;
MEM[addr].b64 = (tmp ^ DATA.b64);
RETURN_DATA.b64 = tmp


Summary: Load 128 bits of data from the flat aperture into a vector register.


Summary: Load 32 bits of data from the flat aperture into a vector register.


Summary: Load 64 bits of data from the flat aperture into a vector register.


Summary: Load 96 bits of data from the flat aperture into a vector register.


Summary: Load 16 bits of unsigned data from the flat aperture and store the result into the low 16 bits of a 32-bit vector register.


Summary: Load 16 bits of unsigned data from the flat aperture and store the result into the high 16 bits of a 32-bit vector register.


Summary: Load 8 bits of signed data from the flat aperture, sign extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register.


Summary: Load 8 bits of unsigned data from the flat aperture, zero extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register.


Summary: Load 8 bits of signed data from the flat aperture, sign extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register.


Summary: Load 8 bits of unsigned data from the flat aperture, zero extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register.


Summary: Load one 32-bit dword per lane through the flat (generic) address space, resolved to global/scratch/LDS at runtime.

VADDR

Per-lane 64-bit generic address (VGPR pair)

VDST[lane] = *(VADDR[lane]) for each active lane; the memory aperture (global, scratch, or LDS) is determined per-address at runtime rather than fixed by the instruction.

flat_load_dword  v2, v[0:1]   // v2 = *(v[0:1]), aperture resolved at runtime


addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
VDATA[31 : 0] = MEM[addr].b32;
VDATA[63 : 32] = MEM[addr + 4U].b32


addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
VDATA[31 : 0] = MEM[addr].b32;
VDATA[63 : 32] = MEM[addr + 4U].b32;
VDATA[95 : 64] = MEM[addr + 8U].b32


addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
VDATA[31 : 0] = MEM[addr].b32;
VDATA[63 : 32] = MEM[addr + 4U].b32;
VDATA[95 : 64] = MEM[addr + 8U].b32;
VDATA[127 : 96] = MEM[addr + 12U].b32


Summary: Load 16 bits of signed data from the flat aperture, sign extend to 32 bits and store the result into a vector register.


Summary: Load 8 bits of signed data from the flat aperture, sign extend to 32 bits and store the result into a vector register.


Summary: AMDGPU FLAT vector instruction operating on b128 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU FLAT vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU FLAT vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
VDATA[15 : 0].i16 = 16'I(signext(MEM[addr].i8));
// VDATA[31:16] is preserved.


addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
VDATA[31 : 16].i16 = 16'I(signext(MEM[addr].i8));
// VDATA[15:0] is preserved.


addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
VDATA[15 : 0].b16 = MEM[addr].b16;
// VDATA[31:16] is preserved.


addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
VDATA[31 : 16].b16 = MEM[addr].b16;
// VDATA[15:0] is preserved.


addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
VDATA.i32 = 32'I(signext(MEM[addr].i16))


Summary: Load 16 bits of unsigned data from the flat aperture, zero extend to 32 bits and store the result into a vector register.


Summary: Load 8 bits of unsigned data from the flat aperture, zero extend to 32 bits and store the result into a vector register.


addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
VDATA[15 : 0].u16 = 16'U({ 8'0U, MEM[addr].u8 });
// VDATA[31:16] is preserved.


addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
VDATA[31 : 16].u16 = 16'U({ 8'0U, MEM[addr].u8 });
// VDATA[15:0] is preserved.


addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
VDATA.u32 = 32'U({ 16'0U, MEM[addr].u16 })


Summary: AMDGPU FLAT vector instruction operating on b8 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Store 128 bits of data from vector input registers into the flat aperture.


Summary: Store 16 bits of data from a vector register into the flat aperture.


Summary: Store 32 bits of data from vector input registers into the flat aperture.


Summary: Store 64 bits of data from vector input registers into the flat aperture.


Summary: Store 8 bits of data from a vector register into the flat aperture.


Summary: Store 96 bits of data from vector input registers into the flat aperture.


addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
MEM[addr].b8 = VDATA[7 : 0]


Summary: Store 8 bits of data from the high 16 bits of a 32-bit vector register into the flat aperture.

addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
MEM[addr].b8 = VDATA[23 : 16]


Summary: Store 16 bits of data from the high 16 bits of a 32-bit vector register into the flat aperture.


addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
MEM[addr].b32 = VDATA[31 : 0]


addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
MEM[addr].b32 = VDATA[31 : 0];
MEM[addr + 4U].b32 = VDATA[63 : 32]


addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
MEM[addr].b32 = VDATA[31 : 0];
MEM[addr + 4U].b32 = VDATA[63 : 32];
MEM[addr + 8U].b32 = VDATA[95 : 64]


addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
MEM[addr].b32 = VDATA[31 : 0];
MEM[addr + 4U].b32 = VDATA[63 : 32];
MEM[addr + 8U].b32 = VDATA[95 : 64];
MEM[addr + 12U].b32 = VDATA[127 : 96]


addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
MEM[addr].b16 = VDATA[15 : 0]


addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
MEM[addr].b16 = VDATA[31 : 16]


Summary: Atomically add a per-lane value to a global-memory location.

Add two unsigned 32-bit integer values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the SC0 bit is set.

global_atomic_add VDST, VADDR, VDATA, SADDR

VDST

Optional destination VGPR (previous value)

old = *(VADDR[lane] + SADDR + offset); *(...) = old + VDATA[lane]; indivisible with respect to other lanes/waves targeting the same address. VDST optionally receives old.

global_atomic_add  v2, v[0:1], v2, off   // *(v[0:1]) += v2 per lane, v2 <- old value


Add a double-precision float value in the data register to a location in the global aperture. Store the original value from global aperture into a vector register iff the SC0 bit is set.

tmp = MEM[ADDR].f64;
MEM[ADDR].f64 += DATA.f64;
RETURN_DATA = tmp


Add two unsigned 64-bit integer values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the SC0 bit is set.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
tmp = MEM[addr].u64;
MEM[addr].u64 += DATA.u64;
RETURN_DATA.u64 = tmp


Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the SC0 bit is set.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
tmp = MEM[addr].b32;
MEM[addr].b32 = (tmp & DATA.b32);
RETURN_DATA.b32 = tmp


Calculate bitwise AND given two unsigned 64-bit integer values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the SC0 bit is set.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
tmp = MEM[addr].b64;
MEM[addr].b64 = (tmp & DATA.b64);
RETURN_DATA.b64 = tmp


Compare two unsigned 32-bit integer values stored in the data comparison register and a location in the global aperture. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from global aperture into a vector register iff the SC0 bit is set.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
tmp = MEM[addr].u32;
src = DATA[31 : 0].u32;
cmp = DATA[63 : 32].u32;
MEM[addr].u32 = tmp == cmp ? src : tmp;
RETURN_DATA.u32 = tmp


Compare two unsigned 64-bit integer values stored in the data comparison register and a location in the global aperture. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from global aperture into a vector register iff the SC0 bit is set.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
tmp = MEM[addr].u64;
src = DATA[63 : 0].u64;
cmp = DATA[127 : 64].u64;
MEM[addr].u64 = tmp == cmp ? src : tmp;
RETURN_DATA.u64 = tmp

global_atomic_cmpswap_x2 v1, v[2:5], vcc


Summary: Subtract an unsigned 32-bit integer value in the data register from a location in the global aperture only if the memory value is greater than or…

Subtract an unsigned 32-bit integer value in the data register from a location in the global aperture only if the memory value is greater than or equal to the data register value. Store the original value from global aperture into a vector register iff the temporal hint enables atomic return.


Subtract an unsigned 32-bit integer location in the global aperture from a value in the data register and clamp the result to zero. Store the original value from global aperture into a vector register iff the GLC bit is set.


Summary: Decrement an unsigned 32-bit integer value from a location in the global aperture with wraparound to a value in the data register if the decrement…

Decrement an unsigned 32-bit integer value from a location in the global aperture with wraparound to a value in the data register if the decrement yields a negative value. Store the original value from global aperture into a vector register iff the SC0 bit is set.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
tmp = MEM[addr].u32;
src = DATA.u32;
MEM[addr].u32 = ((tmp == 0U) || (tmp > src)) ? src : tmp - 1U;
RETURN_DATA.u32 = tmp


Summary: Decrement an unsigned 64-bit integer value from a location in the global aperture with wraparound to a value in the data register if the decrement…

Decrement an unsigned 64-bit integer value from a location in the global aperture with wraparound to a value in the data register if the decrement yields a negative value. Store the original value from global aperture into a vector register iff the SC0 bit is set.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
tmp = MEM[addr].u64;
src = DATA.u64;
MEM[addr].u64 = ((tmp == 0ULL) || (tmp > src)) ? src : tmp - 1ULL;
RETURN_DATA.u64 = tmp


Select the maximum of two double-precision float inputs, given two values stored in the data register and a location in the global aperture. Update the global aperture with the selected value. Store the original value from global aperture into a vector register iff the GLC bit is set.


Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in the global aperture. Update the global aperture with the selected value. Store the original value from global aperture into a vector register iff the GLC bit is set.


Summary: Increment an unsigned 32-bit integer value from a location in the global aperture with wraparound to 0 if the value exceeds a value in the data…

Increment an unsigned 32-bit integer value from a location in the global aperture with wraparound to 0 if the value exceeds a value in the data register. Store the original value from global aperture into a vector register iff the SC0 bit is set.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
tmp = MEM[addr].u32;
src = DATA.u32;
MEM[addr].u32 = tmp >= src ? 0U : tmp + 1U;
RETURN_DATA.u32 = tmp


Summary: Increment an unsigned 64-bit integer value from a location in the global aperture with wraparound to 0 if the value exceeds a value in the data…

Increment an unsigned 64-bit integer value from a location in the global aperture with wraparound to 0 if the value exceeds a value in the data register. Store the original value from global aperture into a vector register iff the SC0 bit is set.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
tmp = MEM[addr].u64;
src = DATA.u64;
MEM[addr].u64 = tmp >= src ? 0ULL : tmp + 1ULL;
RETURN_DATA.u64 = tmp


Select the maximum of two double-precision float inputs, given two values stored in the data register and a location in the global aperture. Update the global aperture with the selected value. Store the original value from global aperture into a vector register iff the SC0 bit is set.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
tmp = MEM[addr].f64;
src = DATA.f64;
MEM[addr].f64 = src > tmp ? src : tmp;
RETURN_DATA.f64 = tmp


Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in the global aperture. Update the global aperture with the selected value. Store the original value from global aperture into a vector register iff the SC0 bit is set.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
tmp = MEM[addr].f64;
src = DATA.f64;
MEM[addr].f64 = src < tmp ? src : tmp;
RETURN_DATA.f64 = tmp


Calculate bitwise OR given two unsigned 32-bit integer values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the SC0 bit is set.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
tmp = MEM[addr].b32;
MEM[addr].b32 = (tmp | DATA.b32);
RETURN_DATA.b32 = tmp


Calculate bitwise OR given two unsigned 64-bit integer values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the SC0 bit is set.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
tmp = MEM[addr].b64;
MEM[addr].b64 = (tmp | DATA.b64);
RETURN_DATA.b64 = tmp


Summary: Given an (ID, value) pair in memory, increment the value by a given amount if the ID matches an ID provided by the shader.


Add a packed 2-component BF16 float value in the data register to a location in the global aperture. Store the original value from global aperture into a vector register iff the SC0 bit is set.


Select the maximum of two signed 32-bit integer inputs, given two values stored in the data register and a location in the global aperture. Update the global aperture with the selected value. Store the original value from global aperture into a vector register iff the SC0 bit is set.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
tmp = MEM[addr].i32;
src = DATA.i32;
MEM[addr].i32 = src >= tmp ? src : tmp;
RETURN_DATA.i32 = tmp


Select the maximum of two signed 64-bit integer inputs, given two values stored in the data register and a location in the global aperture. Update the global aperture with the selected value. Store the original value from global aperture into a vector register iff the SC0 bit is set.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
tmp = MEM[addr].i64;
src = DATA.i64;
MEM[addr].i64 = src >= tmp ? src : tmp;
RETURN_DATA.i64 = tmp


Select the minimum of two signed 32-bit integer inputs, given two values stored in the data register and a location in the global aperture. Update the global aperture with the selected value. Store the original value from global aperture into a vector register iff the SC0 bit is set.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
tmp = MEM[addr].i32;
src = DATA.i32;
MEM[addr].i32 = src < tmp ? src : tmp;
RETURN_DATA.i32 = tmp


Select the minimum of two signed 64-bit integer inputs, given two values stored in the data register and a location in the global aperture. Update the global aperture with the selected value. Store the original value from global aperture into a vector register iff the SC0 bit is set.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
tmp = MEM[addr].i64;
src = DATA.i64;
MEM[addr].i64 = src < tmp ? src : tmp;
RETURN_DATA.i64 = tmp


Subtract an unsigned 32-bit integer value stored in the data register from a value stored in a location in the global aperture. Store the original value from global aperture into a vector register iff the SC0 bit is set.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
tmp = MEM[addr].u32;
MEM[addr].u32 -= DATA.u32;
RETURN_DATA.u32 = tmp


Subtract an unsigned 64-bit integer value stored in the data register from a value stored in a location in the global aperture. Store the original value from global aperture into a vector register iff the SC0 bit is set.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
tmp = MEM[addr].u64;
MEM[addr].u64 -= DATA.u64;
RETURN_DATA.u64 = tmp


Swap an unsigned 32-bit integer value in the data register with a location in the global aperture. Store the original value from global aperture into a vector register iff the SC0 bit is set.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
tmp = MEM[addr].b32;
MEM[addr].b32 = DATA.b32;
RETURN_DATA.b32 = tmp


Swap an unsigned 64-bit integer value in the data register with a location in the global aperture. Store the original value from global aperture into a vector register iff the SC0 bit is set.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
tmp = MEM[addr].b64;
MEM[addr].b64 = DATA.b64;
RETURN_DATA.b64 = tmp


Select the maximum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in the global aperture. Update the global aperture with the selected value. Store the original value from global aperture into a vector register iff the SC0 bit is set.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
tmp = MEM[addr].u32;
src = DATA.u32;
MEM[addr].u32 = src >= tmp ? src : tmp;
RETURN_DATA.u32 = tmp


Select the maximum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in the global aperture. Update the global aperture with the selected value. Store the original value from global aperture into a vector register iff the SC0 bit is set.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
tmp = MEM[addr].u64;
src = DATA.u64;
MEM[addr].u64 = src >= tmp ? src : tmp;
RETURN_DATA.u64 = tmp


Select the minimum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in the global aperture. Update the global aperture with the selected value. Store the original value from global aperture into a vector register iff the SC0 bit is set.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
tmp = MEM[addr].u32;
src = DATA.u32;
MEM[addr].u32 = src < tmp ? src : tmp;
RETURN_DATA.u32 = tmp


Select the minimum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in the global aperture. Update the global aperture with the selected value. Store the original value from global aperture into a vector register iff the SC0 bit is set.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
tmp = MEM[addr].u64;
src = DATA.u64;
MEM[addr].u64 = src < tmp ? src : tmp;
RETURN_DATA.u64 = tmp


Calculate bitwise XOR given two unsigned 32-bit integer values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the SC0 bit is set.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
tmp = MEM[addr].b32;
MEM[addr].b32 = (tmp ^ DATA.b32);
RETURN_DATA.b32 = tmp


Calculate bitwise XOR given two unsigned 64-bit integer values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the SC0 bit is set.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
tmp = MEM[addr].b64;
MEM[addr].b64 = (tmp ^ DATA.b64);
RETURN_DATA.b64 = tmp


Summary: Invalidate cache lines based on the SCOPE field. Increments/decrements LOAD_CNT.


Summary: AMDGPU GLOBAL vector instruction operating on b128 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU GLOBAL vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU GLOBAL vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU GLOBAL vector instruction operating on b8 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Load a block of data from the global aperture.


Summary: Load one 32-bit dword per lane from the global address space using a 64-bit per-lane address.

Load 32 bits of data from the global aperture into a vector register.

global_load_dword VDST, VADDR, SADDR, offset

VDST[lane] = *(VADDR[lane] + SADDR + offset) for each active lane.

global_load_dword  v2, v[0:1], off   // v2 = *(v[0:1]) per lane


Load 32 bits of data from the global aperture into a vector register. The memory base address is provided in a scalar register and the lane ID is used as an offset.


Summary: Load 64 bits of data from the global aperture into a vector register.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
VDATA[31 : 0] = MEM[addr].b32;
VDATA[63 : 32] = MEM[addr + 4U].b32


Summary: Load 96 bits of data from the global aperture into a vector register.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
VDATA[31 : 0] = MEM[addr].b32;
VDATA[63 : 32] = MEM[addr + 4U].b32;
VDATA[95 : 64] = MEM[addr + 8U].b32


Summary: Load 128 bits of data from the global aperture into a vector register.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
VDATA[31 : 0] = MEM[addr].b32;
VDATA[63 : 32] = MEM[addr + 4U].b32;
VDATA[95 : 64] = MEM[addr + 8U].b32;
VDATA[127 : 96] = MEM[addr + 12U].b32


Summary: Load 32 bits of untyped data from the global aperture and store the result into a data share.


Summary: Untyped buffer load 3 dwords, store result into data share.


Summary: Untyped buffer load 4 dwords, store result into data share.


Summary: Load 8 bits of untyped data from the global aperture, sign extend to 32 bits and store the result into a data share.


Summary: Load 16 bits of untyped data from the global aperture, sign extend to 32 bits and store the result into a data share.


Summary: Load 8 bits of untyped data from the global aperture, zero extend to 32 bits and store the result into a data share.


Summary: Load 16 bits of untyped data from the global aperture, zero extend to 32 bits and store the result into a data share.


Summary: AMDGPU GLOBAL vector instruction operating on b128 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU GLOBAL vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU GLOBAL vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Load 8 bits of signed data from the global aperture, sign extend to 32 bits and store the result into a vector register.


Summary: Load 8 bits of signed data from the global aperture, sign extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
VDATA[15 : 0].i16 = 16'I(signext(MEM[addr].i8));
// VDATA[31:16] is preserved.


Summary: Load 8 bits of signed data from the global aperture, sign extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
VDATA[31 : 16].i16 = 16'I(signext(MEM[addr].i8));
// VDATA[15:0] is preserved.


Summary: Load 16 bits of unsigned data from the global aperture and store the result into the low 16 bits of a 32-bit vector register.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
VDATA[15 : 0].b16 = MEM[addr].b16;
// VDATA[31:16] is preserved.


Summary: Load 16 bits of unsigned data from the global aperture and store the result into the high 16 bits of a 32-bit vector register.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
VDATA[31 : 16].b16 = MEM[addr].b16;
// VDATA[15:0] is preserved.


Summary: Load 16 bits of signed data from the global aperture, sign extend to 32 bits and store the result into a vector register.


Summary: AMDGPU GLOBAL vector instruction operating on b96 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Load a 16x16 matrix of 16-bit data from the global aperture, transpose data between row-major and column-major order, and store the result into a…

Load a 16x16 matrix of 16-bit data from the global aperture, transpose data between row-major and column-major order, and store the result into a 128-bit vector register.


Summary: Load a 16x16 matrix of 8-bit data from the global aperture, transpose data between row-major and column-major order, and store the result into a…

Load a 16x16 matrix of 8-bit data from the global aperture, transpose data between row-major and column-major order, and store the result into a 64-bit vector register.


Summary: Load 8 bits of unsigned data from the global aperture, zero extend to 32 bits and store the result into a vector register.


Summary: Load 8 bits of unsigned data from the global aperture, zero extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
VDATA[15 : 0].u16 = 16'U({ 8'0U, MEM[addr].u8 });
// VDATA[31:16] is preserved.


Summary: Load 8 bits of unsigned data from the global aperture, zero extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
VDATA[31 : 16].u16 = 16'U({ 8'0U, MEM[addr].u8 });
// VDATA[15:0] is preserved.


Summary: Load 16 bits of unsigned data from the global aperture, zero extend to 32 bits and store the result into a vector register.


Summary: AMDGPU GLOBAL vector instruction operating on b8 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU GLOBAL vector instruction operating on b128 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU GLOBAL vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU GLOBAL vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Store a block of data to the global aperture.


Summary: Store 8 bits of data from a vector register into the global aperture.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
MEM[addr].b8 = VDATA[7 : 0]


Summary: Store 8 bits of data from the high 16 bits of a 32-bit vector register into the global aperture.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
MEM[addr].b8 = VDATA[23 : 16]


Summary: Store one 32-bit dword per lane to the global address space using a 64-bit per-lane address.

Store 32 bits of data from vector input registers into the global aperture.

global_store_dword VADDR, VDATA, SADDR, offset

*(VADDR[lane] + SADDR + offset) = VDATA[lane] for each active lane.

global_store_dword  v[0:1], v2, off   // *(v[0:1]) = v2 per lane


Store 32 bits of data from a vector input register into the global aperture. The memory base address is provided as an immediate value and the lane ID is used as an offset.


Summary: Store 64 bits of data from vector input registers into the global aperture.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
MEM[addr].b32 = VDATA[31 : 0];
MEM[addr + 4U].b32 = VDATA[63 : 32]


Summary: Store 96 bits of data from vector input registers into the global aperture.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
MEM[addr].b32 = VDATA[31 : 0];
MEM[addr + 4U].b32 = VDATA[63 : 32];
MEM[addr + 8U].b32 = VDATA[95 : 64]


Summary: Store 128 bits of data from vector input registers into the global aperture.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
MEM[addr].b32 = VDATA[31 : 0];
MEM[addr + 4U].b32 = VDATA[63 : 32];
MEM[addr + 8U].b32 = VDATA[95 : 64];
MEM[addr + 12U].b32 = VDATA[127 : 96]


Summary: Store 16 bits of data from a vector register into the global aperture.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
MEM[addr].b16 = VDATA[15 : 0]


Summary: Store 16 bits of data from the high 16 bits of a 32-bit vector register into the global aperture.

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
MEM[addr].b16 = VDATA[31 : 16]


Summary: Write back dirty cache lines based on the SCOPE field. Increments/decrements STORE_CNT.


Summary: Write back and invalidate cache lines based on the SCOPE field. Increments/decrements STORE_CNT.


Add two unsigned 32-bit integer values stored in the data register and a location in an image surface. Store the original value from image surface into a vector register iff the GLC bit is set.

image_atomic_add v0, v[10:11], s[16:23] dmask:0x1 dim:SQ_RSRC_IMG_2D


Add two single-precision float values stored in the data register and a location in an image surface. Store the original value from image surface into a vector register iff the temporal hint enables atomic return.


Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in an image surface. Store the original value from image surface into a vector register iff the GLC bit is set.

image_atomic_and v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm


Compare two unsigned 32-bit integer values stored in the data comparison register and a location in an image surface. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from image surface into a vector register iff the GLC bit is set.

image_atomic_cmpswap v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm


Summary: Decrement an unsigned 32-bit integer value from a location in an image surface with wraparound to a value in the data register if the decrement…

Decrement an unsigned 32-bit integer value from a location in an image surface with wraparound to a value in the data register if the decrement yields a negative value. Store the original value from image surface into a vector register iff the GLC bit is set.

image_atomic_dec v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm


Compare two single-precision float values stored in the data comparison register and a location in an image surface. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from image surface into a vector register iff the GLC bit is set.


Select the maximum of two single-precision float inputs, given two values stored in the data register and a location in an image surface. Update the image surface with the selected value. Store the original value from image surface into a vector register iff the GLC bit is set.


Select the minimum of two single-precision float inputs, given two values stored in the data register and a location in an image surface. Update the image surface with the selected value. Store the original value from image surface into a vector register iff the GLC bit is set.


Increment an unsigned 32-bit integer value from a location in an image surface with wraparound to 0 if the value exceeds a value in the data register. Store the original value from image surface into a vector register iff the GLC bit is set.

image_atomic_inc v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm


Select the IEEE maximumNumber() of two single-precision float inputs, given two values stored in the data register and a location in an image surface. Update the image surface with the selected value. Store the original value from image surface into a vector register iff the temporal hint enables atomic return.


Summary: AMDGPU MIMG vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Select the IEEE minimumNumber() of two single-precision float inputs, given two values stored in the data register and a location in an image surface. Update the image surface with the selected value. Store the original value from image surface into a vector register iff the temporal hint enables atomic return.


Calculate bitwise OR given two unsigned 32-bit integer values stored in the data register and a location in an image surface. Store the original value from image surface into a vector register iff the GLC bit is set.

image_atomic_or v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm


Add a packed 2-component BF16 float value from the data register to a location in an image surface. Store the original value from image surface into a vector register iff the temporal hint enables atomic return.


Add a packed 2-component half-precision float value from the data register to a location in an image surface. Store the original value from image surface into a vector register iff the temporal hint enables atomic return.


Select the maximum of two signed 32-bit integer inputs, given two values stored in the data register and a location in an image surface. Update the image surface with the selected value. Store the original value from image surface into a vector register iff the GLC bit is set.

image_atomic_smax v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm


Select the minimum of two signed 32-bit integer inputs, given two values stored in the data register and a location in an image surface. Update the image surface with the selected value. Store the original value from image surface into a vector register iff the GLC bit is set.

image_atomic_smin v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm


Subtract an unsigned 32-bit integer value stored in the data register from a value stored in a location in an image surface. Store the original value from image surface into a vector register iff the GLC bit is set.

image_atomic_sub v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm


Swap an unsigned 32-bit integer value in the data register with a location in an image surface. Store the original value from image surface into a vector register iff the GLC bit is set.

image_atomic_swap v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm


Select the maximum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in an image surface. Update the image surface with the selected value. Store the original value from image surface into a vector register iff the GLC bit is set.

image_atomic_umax v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm


Select the minimum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in an image surface. Update the image surface with the selected value. Store the original value from image surface into a vector register iff the GLC bit is set.

image_atomic_umin v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm


Calculate bitwise XOR given two unsigned 32-bit integer values stored in the data register and a location in an image surface. Store the original value from image surface into a vector register iff the GLC bit is set.

image_atomic_xor v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm


Test the intersection of rays with either box nodes or triangle nodes within a bounded volume hierarchy using 64 bit node pointers. Store the results of the test into a vector register. This instruction does not take a sampler constant.


Summary: This instruction supports testing one BVH8 node against one ray per lane using both intersection engines.


This instruction supports testing two QBVH nodes against the same ray per lane using both intersection engines. It is typically used to implement the BVH4x2 traversal algorithm.


Test the intersection of rays with either box nodes or triangle nodes within a bounded volume hierarchy using 32 bit node pointers. Store the results of the test into a vector register. This instruction does not take a sampler constant.

image_bvh_intersect_ray v[5:8], v[1:11], s[8:11]


Gather 4 single-component texels from a 4x1 row vector on an image surface. Store the result into vector registers. The DMASK selects which channel to read from (R, G, B, A) and must only have one bit set to 1.


Summary: Return the calculated level of detail (LOD) for the provided input as two single-precision float values. No memory access is performed.

image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_1D


Gather resource information for a given miplevel provided in the address register. Returns 4 integer values into registers 3:0 as { num_mip_levels, depth, height, width }. No memory access is performed.

image_get_resinfo v[5:6], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D


Load a texel from the largest miplevel in an image surface and store the result into a vector register. Perform the format conversion specified by the resource descriptor. No sampling is performed.

image_load v[5:6], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D


Load a texel from a user-specified miplevel in an image surface and store the result into a vector register. Perform the format conversion specified by the resource descriptor. No sampling is performed.

image_load_mip v[5:6], v[1:2], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D


Load a texel from a user-specified miplevel in an image surface and store the result into a vector register. 8- and 16-bit components are zero-extended. The format specified in the resource descriptor is ignored. No sampling is performed.

image_load_mip_pck v[5:6], v[1:2], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D


Load a texel from a user-specified miplevel in an image surface and store the result into a vector register. 8- and 16-bit components are sign-extended. The format specified in the resource descriptor is ignored. No sampling is performed.

image_load_mip_pck_sgn v[5:6], v[1:2], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D


Load a texel from the largest miplevel in an image surface and store the result into a vector register. 8- and 16-bit components are zero-extended. The format specified in the resource descriptor is ignored. No sampling is performed.

image_load_pck v[5:6], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D


Load a texel from the largest miplevel in an image surface and store the result into a vector register. 8- and 16-bit components are sign-extended. The format specified in the resource descriptor is ignored. No sampling is performed.

image_load_pck_sgn v[5:6], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D


Summary: Load up to 4 samples of 1 component from an MSAA resource with a user-specified fragment ID. No sampling is performed.

image_msaa_load v[5:6], v[1:3], s[8:15] dmask:0x4 dim:SQ_RSRC_IMG_2D_MSAA d16


Store a texel from a vector register to the largest miplevel in an image surface. The texel data is converted using the format conversion specified by the resource descriptor prior to storage.

image_store v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm


Store a texel from a vector register to a user-specified miplevel in an image surface. The texel data is converted using the format conversion specified by the resource descriptor prior to storage.

image_store_mip v[1:2], v[2:3], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm


Store a texel from a vector register to a user-specified miplevel in an image surface. The texel data is already packed and the format specified in the resource descriptor is ignored.

image_store_mip_pck v[1:2], v[2:3], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm


Store a texel from a vector register to the largest miplevel in an image surface. The texel data is already packed and the format specified in the resource descriptor is ignored.

image_store_pck v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm


Read a single 32-bit value from LDS to all lanes. A single DWORD is read from LDS memory at ADDR[M0[15:0]], where M0[15:0] is a byte address and is dword-aligned. M0[18:16] specify the data type for the read and may be 0=UBYTE, 1=USHORT, 2=DWORD, 4=SBYTE, 5=SSHORT.


Summary: Transfer parameter data from LDS to VGPRs and expand data in LDS using the NewPrimMask (provided in M0) to place per-quad data into lanes 0-3 of each…

Transfer parameter data from LDS to VGPRs and expand data in LDS using the NewPrimMask (provided in M0) to place per-quad data into lanes 0-3 of each quad as follows:


Summary: Compute the absolute value of a scalar input, store the result into a scalar register and set SCC iff the result is nonzero.


Summary: Calculate the absolute value of difference between two scalar inputs, store the result into a scalar register and set SCC iff the result is nonzero.


Summary: Add two unsigned 32-bit integer inputs and a carry-in bit from SCC, store the result into a scalar register and store the carry-out bit into SCC.


Summary: Add two signed 32-bit integer inputs, store the result into a scalar register and store the carry-out bit into SCC.


Summary: Add two unsigned 32-bit integer inputs, store the result into a scalar register and store the carry-out bit into SCC.


Summary: Add two floating point inputs and store the result into a scalar register.


This opcode is not suitable for use with S_ADDC_U32 for implementing 64-bit operations.


Summary: Add two unsigned 64-bit integer inputs and store the result into a scalar register.


Summary: AMDGPU SOP1 scalar instruction operating on i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Add two 32-bit unsigned scalar operands, wavefront-uniform.

SDST = S0.u32 + S1.u32; SCC = carry-out.

s_add_u32  s2, s0, s1   // s2 = s0 + s1 (scalar, whole wavefront)


Summary: AMDGPU SOP2 scalar instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


tmp = 64'U(S0.u32) + 64'U(S1.u32) + SCC.u64;
SCC = tmp >= 0x100000000ULL ? 1'1U : 1'0U;
// unsigned overflow or carry-out for S_ADDC_U32.
D0.u32 = tmp.u32


Summary: Add a scalar input and the sign extension of a literal 16-bit constant, store the result into a scalar register and store the carry-out bit into SCC.


tmp = D0.i32;
// Save value to check sign bits for overflow later.
D0.i32 = D0.i32 + 32'I(signext(S0.i16));
SCC = ((tmp[31] == S0.i16[15]) && (tmp[31] != D0.i32[31]));
// signed overflow.


Attempt to set the wave's VGPR allocation to the specified number of VGPRs (or greater). The desired VGPR count may be specified as a constant or in an SGPR. The request is rounded up to the next block size so a successful allocation may include more than the requested number of VGPRs.


Summary: Calculate bitwise AND on two scalar inputs, store the result into a scalar register and set SCC iff the result is nonzero.


Summary: Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the…

Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register.


Summary: Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask and also into the scalar…

Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask and also into the scalar destination register, and set SCC iff the calculated result is nonzero.


Summary: Calculate bitwise AND with the first input and the negation of the second input, store the result into a scalar register and set SCC if the result is…

Calculate bitwise AND with the first input and the negation of the second input, store the result into a scalar register and set SCC if the result is nonzero.


Summary: Calculate bitwise AND on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the…

Calculate bitwise AND on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register.


Summary: Calculate bitwise AND on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask and also into the scalar…

Calculate bitwise AND on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask and also into the scalar destination register, and set SCC iff the calculated result is nonzero.


Summary: Calculate bitwise AND on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is…

Calculate bitwise AND on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register.


Calculate bitwise AND on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. The original EXEC mask is saved to the destination SGPRs before the bitwise operation is performed.

saveexec = EXEC.u64;
EXEC.u64 = (S0.u64 & EXEC.u64);
D0.u64 = saveexec.u64;
SCC = EXEC.u64 != 0ULL


Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. The original EXEC mask is saved to the destination SGPRs before the bitwise operation is performed.

saveexec = EXEC.u64;
EXEC.u64 = (~S0.u64 & EXEC.u64);
D0.u64 = saveexec.u64;
SCC = EXEC.u64 != 0ULL


Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask and also into the scalar destination register, and set SCC iff the calculated result is nonzero. Unlike the SAVEEXEC series of opcodes, the value written to destination SGPRs is the result of the bitwise-op result. EXEC and the destination SGPRs have the same value at the end of this instruction. This instruction is intended to help accelerate waterfalling.


Calculate bitwise AND on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. The original EXEC mask is saved to the destination SGPRs before the bitwise operation is performed.

saveexec = EXEC.u64;
EXEC.u64 = (S0.u64 & ~EXEC.u64);
D0.u64 = saveexec.u64;
SCC = EXEC.u64 != 0ULL


Calculate bitwise AND on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask and also into the scalar destination register, and set SCC iff the calculated result is nonzero. Unlike the SAVEEXEC series of opcodes, the value written to destination SGPRs is the result of the bitwise-op result. EXEC and the destination SGPRs have the same value at the end of this instruction. This instruction is intended to help accelerate waterfalling.

In particular, the following sequence of waterfall code is optimized by using a WREXEC instead of two separate scalar ops: // V0 holds the index value per lane
// save exec mask for restore at the end s_mov_b64 s2, exec // exec mask of remaining (unprocessed) threads s_mov_b64 s4, exec loop: // get the index value for the first active lane v_readfirstlane_b32  s0, v0 // find all other lanes with same index value v_cmpx_eq s0, v0 <OP>        // do the operation using the current EXEC mask. S0 holds the index. // mask out thread that was just executed
// s_andn2_b64  s4, s4, exec
// s_mov_b64    exec, s4 s_andn2_wrexec_b64 s4, s4     // replaces above 2 ops // repeat until EXEC==0 s_cbranch_scc1  loop s_mov_b64    exec, s2


Summary: Given a shift count in the second scalar input, calculate the arithmetic shift right (preserving sign bit) of the first scalar input, store the…

Given a shift count in the second scalar input, calculate the arithmetic shift right (preserving sign bit) of the first scalar input, store the result into a scalar register and set SCC iff the result is nonzero.


Summary: Synchronize all waves of the executing workgroup at this point.

Synchronize waves within a threadgroup.

Every wave belonging to the workgroup blocks until all waves of that workgroup have executed s_barrier.

s_barrier   // block until every wave in the workgroup arrives here


Summary: AMDGPU SOP1 scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: AMDGPU SOPP scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)


Summary: Signal that a wave has arrived at a barrier . The argument specifies which barrier to signal.


Signal that a wave has arrived at a barrier and set SCC to indicate if this is the first wave to signal the barrier. The argument specifies which barrier to signal.


Summary: Wait for a barrier to complete. The SIMM16 argument specifies which barrier to wait on.


Summary: Count the number of "0" bits in a scalar input, store the result into a scalar register and set SCC iff the result is nonzero.


Summary: Count the number of "1" bits in a scalar input, store the result into a scalar register and set SCC iff the result is nonzero.


Summary: Extract a signed bitfield from the first input using field offset and size encoded in the second input, store the result into a scalar register and…

Extract a signed bitfield from the first input using field offset and size encoded in the second input, store the result into a scalar register and set SCC iff the result is nonzero.