Summary: Atomic CAS with Release semantics.

Atomic compare and swap of a 32-bit word with release semantics. Compares Ws with memory at address Xn; if equal, stores Wt and loads old value into Ws; otherwise loads the memory value into Ws. This AArch64-only LSE instruction provides a release barrier for store operations, ensuring all prior memory operations complete before this store is observed. Condition flags are not affected.

address ← Xn; ReleaseSemantics(); old_value ← [address]; if Ws == old_value then [address] ← Wt; Ws ← old_value; else Ws ← old_value;


Summary: Atomic CAS with Acquire and Release semantics.

Xn

First source / base 64-bit integer register

Atomic compare and swap of a 32-bit word with acquire-release semantics. Compares Ws with memory at address Xn; if equal, stores Wt and loads old value into Ws; otherwise loads the memory value into Ws. This AArch64-only LSE instruction provides both acquire and release barriers, making it a full sequential consistency point for synchronization. Condition flags are not affected.

address ← Xn; AcquireReleaseSemantics(); old_value ← [address]; if Ws == old_value then [address] ← Wt; Ws ← old_value; else Ws ← old_value;


Summary: Atomic CAS of a pair of registers (128-bit or 64-bit pair).

Atomic compare and swap of a register pair (32-bit pair: 64 bits total, or 64-bit pair: 128 bits total depending on size variant). Compares the pair (Ws, W(s+1)) with memory; if equal, stores (Wt, W(t+1)) and loads old values back; otherwise loads the memory values. This AArch64-only LSE instruction requires even-numbered registers and provides full sequential consistency. Condition flags are not affected. Register numbers must be even and consecutive.

address ← Xn; old_value_pair ← [address]; if (Ws, W(s+1)) == old_value_pair then [address] ← (Wt, W(t+1)); (Ws, W(s+1)) ← old_value_pair; else (Ws, W(s+1)) ← old_value_pair;


Summary: Atomic swap of a word.

Wt

Transfer 32-bit integer register (load/store)

Atomic swap of a 32-bit word. Atomically exchanges the value in Ws with the memory location at address Xn, storing Ws to memory and loading the old memory value into Wt. This AArch64-only LSE instruction provides full sequential consistency without explicit acquire/release semantics. Condition flags are not affected.

address ← Xn; old_value ← [address]; [address] ← Ws; Wt ← old_value;


Summary: Atomic add to memory, return old value.

Atomic load-add of a 32-bit word. Atomically adds Ws to the memory location at address Xn and loads the original memory value into Wt. The sum is stored to memory; the original value (before the addition) is returned. This AArch64-only LSE instruction provides full sequential consistency without explicit acquire/release semantics. Condition flags are not affected.

address ← Xn; old_value ← [address]; [address] ← old_value + Ws; Wt ← old_value;


Summary: Atomic bit clear (AND NOT) to memory.

Atomic Load-Clear Word atomically loads a 32-bit value from memory, performs a bitwise AND with the complement of Ws (clearing specified bits), stores the result back, and returns the original loaded value in Wt. This is an AArch64-only instruction requiring LSE extension support. No condition flags are affected; this instruction provides release semantics for memory ordering.

address ← Xn
original_value ← [address]
new_value ← original_value AND NOT(Ws)
[address] ← new_value
Wt ← original_value
Memory ordering: Release semantics applied


Summary: Atomic XOR to memory.

Atomic Load-Exclusive OR Word atomically loads a 32-bit value from memory, performs a bitwise XOR with Ws, stores the result back, and returns the original loaded value in Wt. This is an AArch64-only instruction requiring LSE extension support. No condition flags are affected; this instruction provides release semantics for memory ordering.

address ← Xn
original_value ← [address]
new_value ← original_value XOR Ws
[address] ← new_value
Wt ← original_value
Memory ordering: Release semantics applied


Summary: Atomic bit set (OR) to memory.

Atomic Load-Set Word atomically loads a 32-bit value from memory, performs a bitwise OR with Ws (setting specified bits), stores the result back, and returns the original loaded value in Wt. This is an AArch64-only instruction requiring LSE extension support. No condition flags are affected; this instruction provides release semantics for memory ordering.

address ← Xn
original_value ← [address]
new_value ← original_value OR Ws
[address] ← new_value
Wt ← original_value
Memory ordering: Release semantics applied


Summary: Atomic signed max to memory.

Atomic Load-Signed Maximum Word atomically loads a 32-bit signed value from memory, computes the signed maximum of the loaded value and Ws, stores the result back, and returns the original loaded value in Wt. This is an AArch64-only instruction requiring LSE extension support. No condition flags are affected; this instruction provides release semantics for memory ordering.

address ← Xn
original_value ← [address]
new_value ← SignedMax(original_value, Ws)
[address] ← new_value
Wt ← original_value
Memory ordering: Release semantics applied


Summary: Atomic signed min to memory.

Atomic Load-Signed Minimum Word atomically loads a 32-bit signed value from memory, computes the signed minimum of the loaded value and Ws, stores the result back, and returns the original loaded value in Wt. This is an AArch64-only instruction requiring LSE extension support. No condition flags are affected; this instruction provides release semantics for memory ordering.

address ← Xn
original_value ← [address]
new_value ← SignedMin(original_value, Ws)
[address] ← new_value
Wt ← original_value
Memory ordering: Release semantics applied


Summary: Atomic unsigned max to memory.

Atomic Load-Unsigned Maximum Word atomically loads a 32-bit unsigned value from memory, computes the unsigned maximum of the loaded value and Ws, stores the result back, and returns the original loaded value in Wt. This is an AArch64-only instruction requiring LSE extension support. No condition flags are affected; this instruction provides release semantics for memory ordering.

address ← Xn
original_value ← [address]
new_value ← UnsignedMax(original_value, Ws)
[address] ← new_value
Wt ← original_value
Memory ordering: Release semantics applied


Summary: Atomic unsigned min to memory.

Atomic Load-Unsigned Minimum Word atomically loads a 32-bit unsigned value from memory, computes the unsigned minimum of the loaded value and Ws, stores the result back, and returns the original loaded value in Wt. This is an AArch64-only instruction requiring LSE extension support. No condition flags are affected; this instruction provides release semantics for memory ordering.

address ← Xn
original_value ← [address]
new_value ← UnsignedMin(original_value, Ws)
[address] ← new_value
Wt ← original_value
Memory ordering: Release semantics applied


Summary: Starts a memory transaction. Returns 0 if successful.

Transaction Start initiates a memory transaction and stores a status value in Xd; a return value of 0 indicates successful transaction start, while non-zero indicates transaction failure or nesting restriction. This is an AArch64-only instruction requiring TME (Transactional Memory Extension) support and must execute at EL0 or higher. No condition flags are affected; the instruction may cause transaction abort exceptions.

status ← AttemptTransactionStart()
Xd ← status
if status == 0 then
  EnterTransactionMode()
else
  Transaction not started, handle abort reason in status value
endif


Summary: Commits the current transaction.

Commits the current transactional region and exits transactional execution. If the transaction is successful, execution continues at the next instruction with all transactional memory updates committed atomically. If the transaction fails, execution aborts to the TSTART instruction and the failure reason is recorded. No condition flags are affected. AArch64-only; requires TME extension.

if PSTATE.TME == TRUE then
  Commit the current transaction
  if transaction fails then
    ABORT_TRANSACTION
  else
    Continue to next instruction
else
  UNDEFINED


Summary: Tests the transaction nesting depth.

Reads the current transaction nesting depth and state into a 64-bit register. The lower bits contain the nesting depth (0 if not in a transaction), and bits 31:0 contain transaction state information including the failure reason if a prior transaction aborted. No condition flags are affected. AArch64-only; requires TME extension.

Xd ← TME_NESTING_DEPTH
Xd[31:0] ← TME_STATE_AND_FAILURE_INFO
Xd[63:32] ← 0


Summary: Does nothing. Used for padding or timing.

Performs no operation and does not affect any processor state. NOP is an alias for HINT with immediate 0. No condition flags are affected. Execution state: AArch64-only.


Summary: Puts the processor into a low-power state until an event occurs.

Puts the processor core into a low-power wait state until a wakeup event occurs (SEV, SEVL, or external interrupt). Execution resumes transparently at the next instruction. No condition flags are affected. Execution state: AArch64-only.

# Enter low-power state
while (no_event_pending) do
  wait_for_event
PC ← PC + 4


Summary: Puts the processor into a low-power state until an interrupt occurs.

Puts the processor core into a low-power wait state until an interrupt occurs. Execution resumes transparently at the next instruction after the interrupt is serviced. No condition flags are affected. Execution state: AArch64-only.

# Enter low-power state
while (no_interrupt_pending) do
  wait_for_interrupt
PC ← PC + 4


Summary: Sends an event to all processors in the cluster (wakes up WFE).

Sends an event signal to all processor cores in the system cluster, waking any cores that are waiting in WFE. No condition flags are affected. Execution state: AArch64-only.

# Broadcast event to all cores in cluster
BROADCAST_EVENT_TO_ALL_CORES
PC ← PC + 4


Summary: Sends an event locally to the executing processor.

Sends an event signal locally to only the executing processor core, setting its local event flag so that the next WFE will not block. No condition flags are affected. Execution state: AArch64-only.

# Set local event flag
LOCAL_EVENT_FLAG ← 1
PC ← PC + 4


Summary: Hints that the current thread is performing a spin-wait loop.

Provides a hint to the processor that the current thread is executing a spin-wait loop and suggests yielding execution time to other threads. This is a performance hint with no architectural side effects. No condition flags are affected. Execution state: AArch64-only.

# Hint: current thread is spin-waiting
HINT_YIELD_EXECUTION_TIME
PC ← PC + 4


Summary: Synchronizes unrecoverable system errors.

Error Synchronization Barrier synchronizes unrecoverable system errors by ensuring that all error conditions are visible to the PE before proceeding. This is a system-level instruction that provides a point of synchronization for RAS (Reliability, Availability, Serviceability) error handling. No condition flags are affected. AArch64-only; requires EL1 or higher privilege.


Summary: Synchronizes the statistical profiling unit.

Profiling Synchronization Barrier (PSB CSYNC) ensures that all prior profiling events are synchronized and visible to the statistical profiling unit. This instruction provides a point of synchronization for performance monitoring and trace streams. No condition flags are affected. AArch64-only; available when profiling extensions are implemented.


Summary: Performs data cache maintenance (Clean, Invalidate, Flush).

Data Cache Operation performs maintenance on the data cache, including invalidate, clean, and flush operations on cache lines. The operation type and target address/set/way are specified by the op and Xt operands. This instruction affects the cache hierarchy and may cause memory barriers; no condition flags are modified. AArch64-only; may require EL1 or higher depending on the operation.

CacheMaintenance(op, address ← Xt); // Operation type determined by op, affecting DC_VAU, DC_IVAC, DC_ISW, etc.


Summary: Performs instruction cache maintenance.

Instruction Cache Operation performs maintenance on the instruction cache, including invalidation and synchronization of instruction streams. The operation type is specified by op, and Xt provides the target address (optional for some operations). No condition flags are affected. AArch64-only; may require EL1 or higher depending on the operation.

ICacheMaintenance(op, address ← Xt); // Operation type determined by op, affecting IC_IALLU, IC_IVAU, IC_IALLUIS


Summary: Invalidates Translation Lookaside Buffer entries.

TLB Invalidate invalidates one or more entries in the Translation Lookaside Buffer to ensure MMU coherency after page table modifications. The operation specifies the scope (single address, all, broadcast, etc.) and Xt provides the target address when applicable. No condition flags are affected. AArch64-only; requires EL1 or higher privilege and typically triggers ISB for completion.

TLBInvalidate(op, address ← Xt); // Operation type determined by op, affecting VMALLE1, VAE1, VAAE1, VALE1, etc.


Summary: Translates a virtual address to a physical address (for debug/software).

Address Translate translates a virtual address in Xt to its physical address and system attributes, writing the result to PAR_EL1 for debug and software inspection. The operation specifies the translation regime and access mode (S1E1R, S1E0W, S1E2R, etc.). No condition flags are affected. AArch64-only; requires appropriate EL privilege for the translation regime.

paResult ← TranslateAddress(op, virtAddr ← Xt); // Result written to PAR_EL1; op determines EL and access mode


Summary: Branches to label if register is zero (Thumb-only, does not affect flags).

Compares the value in Rn with zero and branches to the label if equal. The branch offset is encoded as an unsigned 6-bit immediate (i and imm5 combined, shifted left by 1 to form a 7-bit address offset). This instruction is T32 (Thumb)-only and does not affect condition flags. If the branch is not taken, execution continues sequentially.

if Rn == 0 then PC ← PC + (i:imm5:0 << 1) else PC ← PC + 2


Summary: Branches to label if register is not zero (Thumb-only).

Compares the value in Rn with zero and branches to the label if not equal. The branch offset is encoded as an unsigned 6-bit immediate (i and imm5 combined, shifted left by 1 to form a 7-bit address offset). This instruction is T32 (Thumb)-only and does not affect condition flags. If the branch is not taken, execution continues sequentially.

if Rn != 0 then PC ← PC + (i:imm5:0 << 1) else PC ← PC + 2


Summary: Makes up to 4 following instructions conditional (Thumb-only).

If-Then creates an IT block in Thumb mode, making up to 4 following instructions conditionally executed based on the condition code and optional xyz masks. The condition code and mask pattern determine which instructions execute. No condition flags are modified by IT itself; subsequent instructions execute based on the condition. T32-only; not available in AArch64 or A32 modes.

itState ← (condition, mask); // Sets IT block state; following 1-4 instructions are conditional based on itState


Summary: PC-relative branch using a table of bytes (Switch statements).

Table Branch Byte performs a PC-relative branch using a single-byte lookup table indexed by Rm. The branch offset is calculated as 2 × [Rn + Rm], enabling efficient switch statement implementations. No condition flags are affected. T32-only; updates PC implicitly to the target address.

index ← Rm; offset ← 2 × [Rn + index]; PC ← PC + offset + 4


Summary: PC-relative branch using a table of halfwords.

Loads a halfword from memory at the address computed as the sum of Rn and twice Rm, then branches to PC + 4 + (2 × halfword value). This instruction is used for efficient switch-statement jumps. No condition flags are affected. T32-only instruction; generates an exception if executed in AArch64 or A32.

address ← Rn + (Rm << 1)
table_entry ← ZeroExtend([address], 16)
PC ← PC + 4 + (table_entry << 1)


Summary: Adds two values and saturates the result.

Rm

Second source / offset general-purpose register

Rn

First source / base general-purpose register

Adds Rm to Rn and saturates the result; the saturated sum is placed in Rd. If overflow occurs (signed arithmetic), the result is saturated to 0x7FFFFFFF (positive overflow) or 0x80000000 (negative overflow). This instruction is A32-only, is conditional (respects condition code suffix), and does not affect condition flags. Requires ARMv5TE or later.

result ← Rn + Rm; if SignedOverflow(result) then Rd ← Saturate(result) else Rd ← result


Summary: Subtracts two values and saturates the result.

Subtracts Rm from Rn and saturates the result; the saturated difference is placed in Rd. If overflow occurs (signed arithmetic), the result is saturated to 0x7FFFFFFF (positive overflow) or 0x80000000 (negative overflow). This instruction is A32-only, is conditional (respects condition code suffix), and does not affect condition flags. Requires ARMv5TE or later.

result ← Rn - Rm; if SignedOverflow(result) then Rd ← Saturate(result) else Rd ← result


Summary: Doubles the second operand, adds to first, and saturates.

Saturates the doubling of Rm, then adds the result to Rn with saturation, writing the saturated sum to Rd. The Q flag is set if saturation occurred during either the doubling or addition; other flags are unaffected. A32-only instruction requiring the Saturating Arithmetic extension; must be executed in privileged mode for certain CPSR modifications.

doubled ← SignedSat(Rm << 1, 32)
result ← SignedSat(Rn + doubled, 32)
Rd ← result
if (overflow during doubling or addition) then Q ← 1


Summary: Doubles the second operand, subtracts from first, and saturates.

Saturates the doubling of Rm, then subtracts the result from Rn with saturation, writing the saturated difference to Rd. The Q flag is set if saturation occurred during either the doubling or subtraction; other flags are unaffected. A32-only instruction requiring the Saturating Arithmetic extension; must be executed in privileged mode for certain CPSR modifications.

doubled ← SignedSat(Rm << 1, 32)
result ← SignedSat(Rn - doubled, 32)
Rd ← result
if (overflow during doubling or subtraction) then Q ← 1


Summary: Hints memory system to bring data into cache.

Hints to the memory system that data at the address Rn + imm should be preloaded into the cache hierarchy. No registers are modified and no exception is raised if the address is invalid; the instruction is purely advisory. No flags are affected. A32-only instruction; generates no architectural effect but may improve performance.

address ← Rn + imm12
// Preload hint sent to memory system; no registers modified


Summary: Hints memory system to bring instructions into cache.

Hints to the memory system that instruction code at the address Rn + imm should be preloaded into the instruction cache. No registers are modified and no exception is raised if the address is invalid; the instruction is purely advisory. No flags are affected. A32-only instruction; generates no architectural effect but may improve performance by prefetching code.

address ← Rn + imm12
// Preload hint for instruction cache sent to memory system; no registers modified


Summary: Stores LR and SPSR to the stack of a specific mode.

Stores the Link Register (LR) and Saved Program Status Register (SPSR) of the current mode to the stack pointer of a specified processor mode. If write-back is enabled, the SP of the specified mode is updated. Requires privileged execution (not User mode). A32-only system instruction; no condition flags are modified and exception generation may occur if the target mode is invalid.

target_sp ← SPOfMode(mode)
if (P == 0) then address ← target_sp
else address ← target_sp - 8
if (U == 1) then address ← target_sp + offset else address ← target_sp - offset
[address] ← LR
[address + 4] ← SPSR
if (W == 1) then SPOfMode(mode) ← address + 8 else SPOfMode(mode) ← address


Summary: Loads PC and CPSR from the stack.

Restores the Program Counter and CPSR from a pair of words stored on the stack indicated by Rn. If write-back is enabled, Rn is updated to point past the loaded values. This instruction is used to return from exceptions and perform mode changes. Requires privileged execution. A32-only system instruction; the PC is restored and CPSR is updated, potentially changing processor mode and interrupt masks.

if (P == 0) then address ← Rn
else address ← Rn - 8
if (U == 1) then
  new_pc ← [address]
  new_cpsr ← [address + 4]
  if (W == 1) then Rn ← Rn + 8
else
  new_pc ← [address]
  new_cpsr ← [address + 4]
  if (W == 1) then Rn ← Rn - 8
PC ← new_pc
CPSR ← new_cpsr


Summary: Changes the processor mode or interrupt masks.

Changes the processor mode, interrupt masks (I, F, A flags in CPSR), or both based on the encoded effect (IE=enable or ID=disable) and mode field. Requires privileged execution. A32-only system instruction; modifies CPSR directly and may change interrupt masks and processor mode.

if (imod == 0) then // imod encodes IE/ID
  // No change to interrupt masks
else if (imod == 1) then // IE: enable specified interrupts
  if (m == 1) then CPSR.I ← 0
else if (imod == 2) then // ID: disable specified interrupts
  if (m == 1) then CPSR.I ← 1
if (m == 1) then // Mode change enabled
  CPSR.M ← mode


Summary: Sets the endianness for data accesses (BE/LE).

Sets the endianness mode (big-endian or little-endian) for subsequent data memory accesses in A32 execution state. This instruction modifies the E bit in the CPSR to control whether data is accessed in big-endian (BE) or little-endian (LE) format. No condition flags are affected. This is an A32-only instruction; attempting to execute it in other states may cause unpredictable behavior or generate an exception.

if endian == 'BE' then
  CPSR.E ← 1
else if endian == 'LE' then
  CPSR.E ← 0


Summary: Hints that the task is performing a spin-wait.

Provides a hint to the processor that the current task is performing a spin-wait loop and may yield to other tasks. This instruction does not change any register or memory state but allows the processor to optimize power consumption or task scheduling. No condition flags are affected. This is an A32-only hint instruction.


Summary: Enters low-power state until an event occurs.

Suspends execution and transitions the processor to a low-power state until an event occurs (signaled by another processor's SEV instruction or an external event). The processor may exit the wait state before an event actually occurs due to implementation-specific reasons. No condition flags are affected. This is an A32-only hint instruction.

Wait for event; if event is signaled or implementation permits exit, resume execution


Summary: Enters low-power state until an interrupt occurs.

Suspends execution and transitions the processor to a low-power state until an interrupt is pending. The processor will resume execution when an interrupt is taken or becomes pending, subject to interrupt masking. No condition flags are affected. This is an A32-only hint instruction and typically requires non-user privilege level.

Wait for interrupt; if interrupt is signaled and unmasked, resume execution


Summary: Sends an event to all processors.

Sends an event signal to all processors in the system, waking any processors that are in the WFE low-power state. This instruction has no effect on register or memory state but coordinates multi-processor synchronization. No condition flags are affected. This is an A32-only instruction.


Summary: Sends an event locally.

Sends an event signal locally to the current processor only, waking it if it is in the WFE low-power state. Unlike SEV, this does not affect other processors. No register or memory state is changed. No condition flags are affected. This is an A32-only instruction.


Summary: Provides a hint to the debug system.

Provides a hint to the debug system with an option value (0-15). The option field typically encodes a debug-related hint such as setting a breakpoint or specifying breakpoint type, but the exact behavior is debug-system dependent. No register state or condition flags are modified. This is an A32-only instruction.


Summary: Enters halting debug state (Thumb encoding).

Enters halting debug state (T32 encoding). The processor suspends and passes control to the debug system with a halting debug exception. The imm value is an optional 6-bit debugger-supplied breakpoint ID. This is a T32-only instruction; it generates a halting debug exception and does not resume normal execution until the debugger releases it.

GenerateException(HaltingDebugException); breakpoint_id ← imm


Summary: Software Breakpoint (Thumb encoding).

Software Breakpoint (Thumb encoding). This T32 instruction raises a Prefetch Abort exception with the encoded immediate value available to the debugger or exception handler. It is used to halt execution for debugging purposes. No condition flags are affected.


Summary: System Call (Thumb encoding).

Supervisor Call (Thumb encoding). This T32 instruction raises a Supervisor Call exception (formerly SWI), transitioning to privileged mode to perform a system service. The immediate value identifies the requested service. No condition flags are affected; execution does not return to the next instruction unless the exception handler explicitly restores context.


Summary: Permanently undefined instruction (generates Undefined Instruction exception).

Undefined Instruction (A32 encoding). This A32 instruction is permanently undefined and raises an Undefined Instruction exception when executed. The 16-bit immediate (imm12 and imm4 concatenated) is available to the exception handler but does not affect execution otherwise. No condition flags are affected.


Summary: Permanently undefined instruction (Thumb).

Undefined Instruction (Thumb encoding). This T32 instruction is permanently undefined and raises an Undefined Instruction exception when executed. The 8-bit immediate value is available to the exception handler. No condition flags are affected.


Summary: Writes to a banked register from a general-purpose register.

Writes the value of a general-purpose register to a banked system register. This instruction is available only in privileged modes (not User mode) and performs a mode-aware write to the specified banked register. No condition flags are affected by this instruction.


Summary: Reads a banked register into a general-purpose register.

Reads the value of a banked system register into a general-purpose register. This instruction is available only in privileged modes (not User mode) and performs a mode-aware read from the specified banked register. No condition flags are affected by this instruction.


Summary: Converts single-precision to half-precision (Bottom half).

Converts a single-precision floating-point value to half-precision and stores it in the bottom half of the destination single-precision register. The top half of the destination is unchanged. The instruction is conditional and sets VFP flags (FPSCR) according to the conversion result.

Sd[15:0] ← ConvertToHalf(Sm); Sd[31:16] unchanged


Summary: Converts single-precision to half-precision (Top half).

Converts a single-precision floating-point value to half-precision and stores it in the top half of the destination single-precision register. The bottom half of the destination is unchanged. The instruction is conditional and sets VFP flags (FPSCR) according to the conversion result.

Sd[31:16] ← ConvertToHalf(Sm); Sd[15:0] unchanged


Summary: Selects between two double-precision registers based on flags.

Vector Select (Double). This VFP instruction selects between two 64-bit floating-point operands (Dn and Dm) based on a condition code (cc) applied to the FPSCR condition flags, writing the selected value to Dd. The condition code determines which register's value is copied. No flags are set or cleared by this instruction.

if ConditionPassed(cc) then
  Dd ← Dn
else
  Dd ← Dm


Summary: Returns larger double-precision value, handling NaNs.

Vector Maximum Number (Double). This VFP instruction compares two 64-bit floating-point values (Dn and Dm) and writes the larger value to Dd, with special handling for NaN: if one operand is NaN, the other is returned (not NaN). FPSCR exception flags may be set according to the IEEE 754 floating-point standard.

if IsNaN(Dn) then
  Dd ← Dm
elseif IsNaN(Dm) then
  Dd ← Dn
else if Dn ≥ Dm then
  Dd ← Dn
else
  Dd ← Dm


Summary: Returns smaller double-precision value, handling NaNs.

Vector Minimum Number (Double). This VFP instruction compares two 64-bit floating-point values (Dn and Dm) and writes the smaller value to Dd, with special handling for NaN: if one operand is NaN, the other is returned (not NaN). FPSCR exception flags may be set according to the IEEE 754 floating-point standard.

if IsNaN(Dn) then
  Dd ← Dm
elseif IsNaN(Dm) then
  Dd ← Dn
else if Dn ≤ Dm then
  Dd ← Dn
else
  Dd ← Dm


Summary: Rounds float to integral float using FPSCR rounding mode.

Sd

Destination 32-bit floating-point register

Sm

Second source 32-bit floating-point register

Vector Round Floating-Point (Current). This VFP instruction rounds the 32-bit floating-point value in Sm to an integral floating-point value using the rounding mode specified in the FPSCR and writes the result to Sd. The rounding mode and exception behavior are controlled by FPSCR flags; inexact exceptions may be signaled.

rounding_mode ← FPSCR.RMode
Sd ← RoundFP(Sm, rounding_mode)


Summary: Rounds float to integral float, raising Inexact exception.

Rounds each single-precision floating-point element to the nearest integral value, with round-to-nearest-even semantics. The Inexact exception is raised if the result differs from the input. Condition flags are not affected. This is an A32/T32 VFP instruction requiring the VFP extension.

for i = 0 to 0 do
  Sd[i] ← RoundToNearest(Sm[i])
  if Sd[i] != Sm[i] then
    FPExc_IXC ← 1
  end if
end for


Summary: SHA512 hash update part 1.

Performs the first part of the SHA-512 hash computation, processing hash values and round constants. The operation combines Qn (hash) and Qm (data) values and updates Qd (state) with intermediate results. This is an A32 Advanced SIMD instruction requiring the SHA512 Cryptographic Extension. Condition flags are not affected.


Summary: SHA512 hash update part 2.

Performs the second part of the SHA-512 hash computation, completing the hash update using state (Qd), hash values (Qn), and message data (Qm). This variant differs from SHA512H in the internal transformation applied. This is an A32 Advanced SIMD instruction requiring the SHA512 Cryptographic Extension. Condition flags are not affected.


Summary: SHA512 schedule update instruction 0.

Performs the first schedule update operation for SHA-512 message scheduling, processing Qm and updating Qd with the first sigma operation. This is a unary operation used during SHA-512 preprocessing of the message schedule. This is an A32 Advanced SIMD instruction requiring the SHA512 Cryptographic Extension. Condition flags are not affected.


Summary: SHA512 schedule update instruction 1.

Performs the second schedule update operation for SHA-512 message scheduling, combining Qd and Qn with Qm to compute the next message schedule value. This operation incorporates previous schedule elements and the second sigma transformation. This is an A32 Advanced SIMD instruction requiring the SHA512 Cryptographic Extension. Condition flags are not affected.


Summary: SM3 cryptographic hash step 1.

Performs step 1 of the SM3 cryptographic hash function, combining three 128-bit operands to produce an intermediate result. The operation implements the SM3 compression function's linear transformation. This is an A32 Advanced SIMD instruction requiring the SM3 Cryptographic Extension. Condition flags are not affected.


Summary: SM3 cryptographic hash step 2A.

Performs step 2A of the SM3 cryptographic hash, updating 32-bit word elements based on the specified rotation immediate. Operates on 64-bit source registers but stores results in a 128-bit destination. This is an A32 Advanced SIMD instruction requiring the SM3 Cryptographic Extension. Condition flags are not affected.

rot ← imm * 8
Qd ← SM3_TT1A(Dn, Dm, rot)


Summary: SM3 cryptographic hash step 2B.

Performs step 2B of the SM3 cryptographic hash, updating 32-bit word elements with a different permutation than SM3TT1A, based on the specified rotation immediate. Operates on 64-bit source registers but stores results in a 128-bit destination. This is an A32 Advanced SIMD instruction requiring the SM3 Cryptographic Extension. Condition flags are not affected.

rot ← imm * 8
Qd ← SM3_TT1B(Dn, Dm, rot)


Summary: SM3 cryptographic hash step 3A.

SM3 Step 3A performs part of the SM3 cryptographic hash compression function, processing two 32-bit words from the input with a rotation parameter. This instruction operates on 64-bit source registers and writes a 128-bit result, and does not affect any condition flags. The instruction is A32-only and requires the Crypto SM3 extension; it generates an Undefined Instruction exception if executed without the extension enabled.


Summary: SM3 cryptographic hash step 3B.

SM3 Step 3B performs the second variant of SM3 compression function step 3, processing two 32-bit words with a different constant path than SM3TT2A. This instruction operates on 64-bit source registers and writes a 128-bit result, and does not affect condition flags. The instruction is A32-only and requires the Crypto SM3 extension; it generates an Undefined Instruction exception if executed without the extension enabled.


Summary: SM3 schedule update part 1.

SM3 Part Word 1 performs the first part of SM3 message schedule update, computing intermediate values from the previous message schedule words. This instruction operates on three 128-bit registers and does not affect condition flags. The instruction is A32-only and requires the Crypto SM3 extension; it generates an Undefined Instruction exception if executed without the extension enabled.


Summary: SM3 schedule update part 2.

SM3 Part Word 2 performs the second part of SM3 message schedule update, completing the computation of new message schedule words from previous values. This instruction operates on three 128-bit registers and does not affect condition flags. The instruction is A32-only and requires the Crypto SM3 extension; it generates an Undefined Instruction exception if executed without the extension enabled.


Summary: SM4 encryption step.

SM4 Encrypt performs one round of SM4 block cipher encryption, transforming a 128-bit state register using a 128-bit round key. This instruction does not affect condition flags. The instruction is A32-only and requires the Crypto SM4 extension; it generates an Undefined Instruction exception if executed without the extension enabled.


Summary: SM4 key schedule step.

SM4 Key performs one round of SM4 key schedule expansion, computing a derived key from the previous key material. This instruction does not affect condition flags. The instruction is A32-only and requires the Crypto SM4 extension; it generates an Undefined Instruction exception if executed without the extension enabled.


Summary: Loads a byte, acquires semantics, marks exclusive.

Rt

Transfer general-purpose register (load/store)

Loads a byte from memory at the address in Rn with Acquire semantics and marks the location as exclusive. The loaded byte is zero-extended and placed in Rt. Acquire semantics ensure that subsequent memory operations are not reordered before this load. No condition flags are affected.

Rt ← ZeroExtend([Rn], 8); ExclusiveLocal ← TRUE; Acquire()


Summary: Loads a halfword, acquires semantics, marks exclusive.

Loads a halfword from memory at the address in Rn with Acquire semantics and marks the location as exclusive. The loaded halfword is zero-extended and placed in Rt. Acquire semantics ensure that subsequent memory operations are not reordered before this load. No condition flags are affected.

Rt ← ZeroExtend([Rn], 16); ExclusiveLocal ← TRUE; Acquire()


Summary: Loads a doubleword, acquires semantics, marks exclusive.

Loads a doubleword (64 bits) from memory at the address in Rn with Acquire semantics and marks the location as exclusive. The lower 32 bits are placed in Rt and the upper 32 bits in Rt2. Acquire semantics ensure that subsequent memory operations are not reordered before this load. No condition flags are affected.

Rt ← [Rn]; Rt2 ← [Rn+4]; ExclusiveLocal ← TRUE; Acquire()


Summary: Stores a byte with Release semantics if exclusive.

Attempts to store a byte to memory at the address in Rn with Release semantics if the location is marked exclusive. The result of the store attempt (0 for success, 1 for failure) is written to Rd. Release semantics ensure that preceding memory operations are not reordered after this store. No condition flags are affected.

if ExclusiveLocal then [Rn] ← Rt[7:0]; Rd ← 0; Release(); ExclusiveLocal ← FALSE else Rd ← 1 endif


Summary: Stores a halfword with Release semantics if exclusive.

Stores a halfword to memory with Release semantics if the exclusive monitor is set for the address. Writes a status value (0=success, 1=failure) to Rd and the value from Rt to the memory location addressed by Rn. This is an exclusive store with memory ordering guarantees. No condition flags are affected. Execution state: A32 only; requires privilege level dependent on the accessed address.

if ExclusiveMonitorsPass(address=Rn, size=2) then
  [Rn] ← Rt[15:0]
  Rd ← 0
  ClearExclusiveMonitors()
else
  Rd ← 1


Summary: Stores a doubleword with Release semantics if exclusive.

Second transfer register (load/store pair)

Stores a doubleword (64-bit value) to memory with Release semantics if the exclusive monitor is set for the address. The value is loaded from the register pair [Rt, Rt2], and a status is written to Rd (0=success, 1=failure). This is an exclusive store with full Release memory ordering. No condition flags are affected. Execution state: A32 only; Rt must be even-numbered and Rt2=Rt+1.

if ExclusiveMonitorsPass(address=Rn, size=8) then
  [Rn] ← Rt
  [Rn+4] ← Rt2
  Rd ← 0
  ClearExclusiveMonitors()
else
  Rd ← 1


Summary: Complex integer addition with rotation (NEON).

VCADD<c>.I<size> <Qd>, <Qn>, <Qm>, #<rot>

Performs complex addition on pairs of elements within 128-bit SIMD registers, treating each pair as a complex number (real, imaginary), with rotation applied before addition. The rotation is either 90° or 270° as specified by rot. Operates on 32-bit or 64-bit element pairs. NEON extension; no condition flags affected.

rotation_angle ← if rot == 0 then 90 else 270
for i = 0 to elements_per_128bit_register/2 - 1 do
  real_n ← Qn[2*i]
  imag_n ← Qn[2*i+1]
  real_m ← Qm[2*i]
  imag_m ← Qm[2*i+1]
  rotated_real ← rotate(real_m, imag_m, rotation_angle).real
  rotated_imag ← rotate(real_m, imag_m, rotation_angle).imag
  Qd[2*i] ← real_n + rotated_real
  Qd[2*i+1] ← imag_n + rotated_imag


Vector Complex Multiply Accumulate (A32)

Summary: Complex integer multiply-accumulate with rotation.

VCMLA<c>.I<size> <Qd>, <Qn>, <Qm>, #<rot>

Vector Complex Multiply-Accumulate performs complex multiplication of two vectors with a specified rotation (0°, 90°, 180°, or 270°) and accumulates the result into the destination register, operating on 32-bit or 64-bit integer elements. This instruction does not affect condition flags. The instruction is A32-only and requires the NEON Complex extension; it generates an Undefined Instruction exception if executed without the extension enabled.

for i = 0 to (128 / esize) - 1 do
  real_part = Qn[2*i] * Qm[2*i] - Qn[2*i+1] * Qm[2*i+1]
  imag_part = Qn[2*i] * Qm[2*i+1] + Qn[2*i+1] * Qm[2*i]
  (real_part, imag_part) = RotateByRot(real_part, imag_part, rot)
  Qd[2*i] = Qd[2*i] + real_part
  Qd[2*i+1] = Qd[2*i+1] + imag_part


Summary: BFloat16 dot product to float32 accumulator.

Vector BFloat16 Dot Product computes the dot product of two vectors of BFloat16 (brain floating-point 16-bit) values and accumulates the result as a 32-bit floating-point value in the destination. This instruction does not affect condition flags. The instruction is A32-only and requires the NEON BFloat16 extension; it generates an Undefined Instruction exception if executed without the extension enabled.


Summary: BFloat16 matrix multiply-accumulate.

Multiplies two 128-bit SIMD registers containing BFloat16 (16-bit brain floating-point) elements in 2×2 matrix format and accumulates the result into the destination register. Each 2×2 matrix multiplication processes four BFloat16 values, producing single-precision results that are accumulated. Condition flags (N, Z, C, V) are unaffected. This instruction requires the NEON BFloat16 extension and executes in A32 (ARM) instruction set only.


Summary: Converts Float32 to BFloat16.

Converts 128-bit SIMD register containing single-precision floating-point elements to BFloat16 (16-bit brain floating-point) format by rounding the mantissa to 7 bits and preserving the sign and exponent. The result is stored as 64 BFloat16 elements in the destination 128-bit register. Condition flags are unaffected. This instruction requires the NEON BFloat16 extension and executes in A32 (ARM) instruction set only.


Vector Unsigned-Signed Dot Product (A32)

Summary: Dot product of unsigned (src1) and signed (src2) bytes.

Computes the dot product of unsigned 8-bit integers from Qn and signed 8-bit integers from Qm, accumulating four dot products (one per 32-bit lane) into the corresponding 32-bit signed integer elements of Qd. Each lane multiplies and sums four pairs of unsigned×signed bytes. Condition flags are unaffected. This instruction requires the NEON DotProd extension and executes in A32 (ARM) instruction set only.

for i = 0 to 3 do
  acc = Qd[i*32 + 0:31]
  for j = 0 to 3 do
    unsigned_byte = ZeroExtend(Qn[(i*4 + j)*8 + 0:7])
    signed_byte = SignExtend(Qm[(i*4 + j)*8 + 0:7])
    acc = acc + (unsigned_byte * signed_byte)
  Qd[i*32 + 0:31] = acc


Vector Signed Int8 Matrix Multiply (A32)

Summary: Matrix multiply-accumulate (Signed Int8).

Multiplies two 128-bit SIMD registers containing signed 8-bit integer elements in 4×4 matrix format and accumulates the result into the destination register as signed 32-bit integers. Processes four 4×4 matrices, each producing four 32-bit signed results that are added to Qd. Condition flags are unaffected. This instruction requires the NEON MatMul extension and executes in A32 (ARM) instruction set only.

for i = 0 to 3 do
  // Extract 4x4 S8 matrix from Qn
  for r = 0 to 3 do
    for c = 0 to 3 do
      matrix_a[r][c] = SignExtend(Qn[(i*16 + r*4 + c)*8 + 0:7])
  // Extract 4x4 S8 matrix from Qm
  for r = 0 to 3 do
    for c = 0 to 3 do
      matrix_b[r][c] = SignExtend(Qm[(i*16 + r*4 + c)*8 + 0:7])
  // Multiply and accumulate
  for r = 0 to 3 do
    result = Qd[(i*4 + r)*32 + 0:31]
    for k = 0 to 3 do
      result = result + matrix_a[r][k] * matrix_b[k][r]
    Qd[(i*4 + r)*32 + 0:31] = result


Vector Unsigned-Signed Matrix Multiply (A32)

Summary: Matrix multiply-accumulate (Unsigned x Signed Int8).

Multiplies two 128-bit SIMD registers containing unsigned 8-bit integers from Qn and signed 8-bit integers from Qm in 4×4 matrix format and accumulates the result into the destination register as signed 32-bit integers. Processes four 4×4 matrices, each producing four 32-bit signed results. Condition flags are unaffected. This instruction requires the NEON MatMul extension and executes in A32 (ARM) instruction set only.

for i = 0 to 3 do
  // Extract 4x4 U8 matrix from Qn
  for r = 0 to 3 do
    for c = 0 to 3 do
      matrix_a[r][c] = ZeroExtend(Qn[(i*16 + r*4 + c)*8 + 0:7])
  // Extract 4x4 S8 matrix from Qm
  for r = 0 to 3 do
    for c = 0 to 3 do
      matrix_b[r][c] = SignExtend(Qm[(i*16 + r*4 + c)*8 + 0:7])
  // Multiply and accumulate
  for r = 0 to 3 do
    result = Qd[(i*4 + r)*32 + 0:31]
    for k = 0 to 3 do
      result = result + matrix_a[r][k] * matrix_b[k][r]
    Qd[(i*4 + r)*32 + 0:31] = result


Summary: Matrix multiply-accumulate (Unsigned Int8).

Multiplies two 128-bit SIMD registers containing unsigned 8-bit integer elements in 4×4 matrix format and accumulates the result into the destination register as unsigned 32-bit integers. Processes four 4×4 matrices, each producing four 32-bit unsigned results that are added to Qd. Condition flags are unaffected. This instruction requires the NEON MatMul extension and executes in A32 (ARM) instruction set only.

for i = 0 to 3 do
  // Extract 4x4 U8 matrix from Qn
  for r = 0 to 3 do
    for c = 0 to 3 do
      matrix_a[r][c] = ZeroExtend(Qn[(i*16 + r*4 + c)*8 + 0:7])
  // Extract 4x4 U8 matrix from Qm
  for r = 0 to 3 do
    for c = 0 to 3 do
      matrix_b[r][c] = ZeroExtend(Qm[(i*16 + r*4 + c)*8 + 0:7])
  // Multiply and accumulate
  for r = 0 to 3 do
    result = Qd[(i*4 + r)*32 + 0:31]
    for k = 0 to 3 do
      result = result + matrix_a[r][k] * matrix_b[k][r]
    Qd[(i*4 + r)*32 + 0:31] = result


Summary: Converts double to signed 32-bit integer (JS semantics).

Converts a 64-bit double-precision floating-point value to a signed 32-bit integer using JavaScript semantics (NaN maps to 0, out-of-range values saturate). The result is stored as a single-precision floating-point value in the destination 32-bit register. Condition flags are unaffected. This instruction requires the VFP JavaScript extension and executes in A32 (ARM) instruction set only.


Summary: Hints memory system to bring data into cache for writing.

Preloads data for write by hinting the memory system to allocate cache line(s) in an exclusive state at the address computed from the base register and 12-bit immediate offset. This is a hint instruction and does not cause exceptions on address translation or access faults. Condition flags and general-purpose registers are unaffected. This instruction executes in A32 (ARM) instruction set only.

address = Rn + imm12
// Hint to memory system to preload for exclusive access (write)
PreloadDataForWrite(address)


Summary: Hints memory system to bring data into cache for writing (Thumb).

Preload Data for Write provides a hint to the memory system to bring a cache line into the cache hierarchy in preparation for a write operation. The instruction does not modify any registers or condition flags and serves only as a performance optimization hint. It is available in Thumb (T32) instruction set and has no architectural side effects if the hint is ignored.

// Hint to memory system to preload data for write at address [Rn + imm]
// No architectural effect on registers or flags
Hint_PreloadForWrite(address: Rn + imm)


Summary: Prevents speculative execution across the barrier (v8.0).

Speculation Barrier (v8.0) prevents speculative execution from crossing the barrier in either direction, creating a serialization point for instruction execution. This instruction acts as a full execution barrier that completes all prior instructions before allowing subsequent instructions to execute speculatively. Available in A32 instruction set; does not modify condition flags.

// Serialize execution; prevent speculative execution across this point
SpeculationBarrier()
// All prior instructions complete before any subsequent instruction executes speculatively


Summary: Prevents speculative loads bypassing earlier stores (v8.0).

Speculative Store Bypass Barrier (v8.0) prevents speculative loads from bypassing earlier stores, ensuring that load operations wait for all prior store operations to complete. This is a lighter-weight barrier than SB, specifically targeting store-to-load forwarding speculation. Available in A32 instruction set; does not modify condition flags.

// Prevent speculative load execution past prior stores
StoreBypassBarrier()
// All prior stores complete before subsequent loads can execute


Physical Speculative Store Bypass Barrier (A32)

Summary: Prevents speculation on physical resources (v8.0).

Physical Speculative Store Bypass Barrier (v8.0) prevents speculative load bypassing on physical memory operations, operating at a more restrictive level than SSBB by affecting physical resource speculation. This barrier is typically used in security contexts to prevent cross-VM or cross-process speculation. Available in A32 instruction set; does not modify condition flags.

// Prevent speculative load bypass on physical resources
PhysicalStoreBypassBarrier()
// All prior physical stores complete before subsequent loads can execute on physical resources


Summary: Ensures trace generation is complete (v8.2).

Trace Synchronization Barrier with CSYNC operand (v8.2) ensures that trace generation is synchronized and complete before subsequent instructions execute, used to maintain consistency in trace output. This instruction is primarily used in debug and tracing scenarios and does not modify general-purpose registers or condition flags. Available in A32 instruction set.

// Synchronize trace generation (CSYNC variant)
TraceBarrier(CSYNC)
// Trace context switches complete before proceeding


Summary: Deprecated alias for DSB.

Debug Flush Barrier (Legacy) is a deprecated alias for DSB that is retained for compatibility; it flushes the debug pipeline and ensures all debug operations complete. This instruction should not be used in new code as it is superseded by explicit DSB instructions. Available in A32 instruction set; does not modify condition flags.

// Deprecated: Flush debug pipeline (equivalent to DSB)
DebugFlushBarrier()
// All debug operations complete (legacy behavior)


Summary: Legacy instruction to enter Jazelle state (Now behaves like BX).

Legacy instruction that branches to the address in Rm with exchange (Thumb/ARM mode switching based on bit [0] of Rm). In current ARMv8 architecture, BXJ behaves identically to BX due to Jazelle being obsolete. Bit [0] of Rm determines the target state (0=ARM, 1=Thumb). No condition flags are affected. Execution state: A32 only.

next_address ← Rm
if next_address[0] == 1 then
  CPSR.T ← 1
else
  CPSR.T ← 0
PC ← next_address AND NOT(0x1)


Vector Round Floating-Point (Minus Infinity)

Summary: Rounds float towards Minus Infinity (Floor).

Rounds a 32-bit floating-point value towards minus infinity (floor) and stores the result in the destination register. This instruction does not modify the condition code flags. It is available in A32 and T32 with the VFP extension, and requires floating-point support.


Vector Round Floating-Point (Plus Infinity)

Summary: Rounds float towards Plus Infinity (Ceil).

Rounds a 32-bit floating-point value towards plus infinity (ceiling) and stores the result in the destination register. This instruction does not modify the condition code flags. It is available in A32 and T32 with the VFP extension, and requires floating-point support.


Vector Round Floating-Point Double (Minus Infinity)

Summary: Rounds double towards Minus Infinity (Floor).

Rounds a 64-bit floating-point value towards minus infinity (floor) and stores the result in the destination register. This instruction does not modify the condition code flags. It is available in A32 and T32 with the VFP extension, and requires floating-point support.


Vector Round Floating-Point Double (Plus Infinity)

Summary: Rounds double towards Plus Infinity (Ceil).

Rounds a 64-bit floating-point value towards plus infinity (ceiling) and stores the result in the destination register. This instruction does not modify the condition code flags. It is available in A32 and T32 with the VFP extension, and requires floating-point support.


Summary: Enters halting debug state (A32 encoding).

Halts execution and enters the debugger, with an optional 16-bit immediate value providing debug information. The instruction is unconditional in A32 and causes an exception to the debugger if enabled, otherwise it behaves as an unpredictable instruction. This is an A32-only instruction and is typically privileged.


Move Immediate to Special Register (A32)

Summary: Writes an immediate to a status register (A32).

Writes an immediate value to a status register (CPSR or SPSR) with mask control in A32. The immediate is expanded by a rotate amount encoded in the instruction. Only the register fields specified by the mask are updated. This is a privileged instruction if writing to SPSR or certain CPSR fields. Condition flags (N, Z, C, V) may be updated depending on mask. Execution state: A32 only.

imm_value ← rotate_right(imm8, 2 * rotate)
if spec_reg == CPSR then
  if mask[0] then CPSR[7:0] ← imm_value[7:0]
  if mask[1] then CPSR[15:8] ← imm_value[15:8]
  if mask[2] then CPSR[23:16] ← imm_value[23:16]
  if mask[3] then CPSR[31:24] ← imm_value[31:24]
else if spec_reg == SPSR then
  if mask[0] then SPSR[7:0] ← imm_value[7:0]
  if mask[1] then SPSR[15:8] ← imm_value[15:8]
  if mask[2] then SPSR[23:16] ← imm_value[23:16]
  if mask[3] then SPSR[31:24] ← imm_value[31:24]


Move Immediate to Special Register (Thumb)

Summary: Writes an immediate to a status register (Thumb).

Writes an immediate value to a status register (CPSR or SPSR) in T32/Thumb state. The immediate is zero-extended and only the lowest 8 bits are used to update certain CPSR/SPSR fields. This is a privileged instruction. Condition flags may be modified based on the target register and field selection. Execution state: T32 only.

imm_value ← ZeroExtend(imm8, 32)
if spec_reg == CPSR then
  CPSR[31:24] ← imm_value[31:24]
else if spec_reg == SPSR then
  SPSR[31:24] ← imm_value[31:24]


Summary: Returns from an exception (A32).

Returns from an exception by restoring the PC from ELR_ELx and the PSTATE from SPSR_ELx. This instruction is unconditional and is only available in A32 AArch32 execution state. It requires privilege level sufficient to execute exception-handling code (typically EL1 or higher) and is used at the end of exception handlers.


Summary: Subs PC, LR, #imm (Exception return mechanism).

Subtracts an immediate from the LR register and stores the result in PC, causing an exception return with automatic CPSR restoration from SPSR. All condition flags (N, Z, C, V) are updated from the subtraction result. This instruction is the preferred exception return mechanism in A32 and must execute in a privileged mode. Execution state: A32 only.

result ← LR - imm12
N ← result[31]
Z ← (result == 0)
C ← (LR >= imm12)
V ← OverflowFrom(LR - imm12)
PC ← result
CPSR ← SPSR


Summary: Loads a word from a label.

Loads a 32-bit word from a memory address computed as the sum of the current PC and a label offset. The offset is encoded as a 12-bit immediate, with the direction (add/subtract) controlled by the U bit. No condition flags are affected. Execution state: A32 only; label must be within ±4KB of the current instruction.

if U == 1 then
  address ← Align(PC, 4) + imm12
else
  address ← Align(PC, 4) - imm12
Rt ← [address]


Summary: Loads a word from a label (Thumb).

Loads a 32-bit word from memory at a PC-relative address into a register. The effective address is computed by adding the 8-bit immediate (shifted left by 2) to the aligned PC. No condition flags are affected. This is a Thumb 16-bit instruction available in all Thumb-capable processors.

address ← Align(PC, 4) + (imm8 << 2)
Rt ← [address]


Summary: Adds an immediate value to the PC (Thumb).

Computes a PC-relative address by adding an 8-bit immediate (shifted left by 2) to the aligned PC and writes the result to a register. No condition flags are affected. This Thumb 16-bit instruction is available in all Thumb-capable processors.


Summary: Reverse Subtract (Thumb 16-bit).

Subtracts a register from zero and writes the result to the destination register (two's complement negation). Sets the N, Z, C, and V flags based on the result. This Thumb 16-bit instruction is available in all Thumb-capable processors.

result ← 0 - Rn
Rd ← result
N ← (result[31] == 1)
Z ← (result == 0)
C ← BorrowFrom(0 - Rn)
V ← OverflowFrom(0 - Rn)


Summary: Calls the Hypervisor (EL2) from Thumb state.

Generates a hypervisor call exception, transitioning to EL2 with an optional 16-bit immediate value encoding the hypervisor service request. The instruction is unconditional and available in Thumb state. Execution requires that EL2 is implemented and enabled; the hypervisor takes control and may use the immediate as a service identifier.

ExceptionSyndromeISS ← imm16; RaiseException(HypercallException)


Summary: Calls the Secure Monitor (EL3) from Thumb state.

Generates a secure monitor call exception, transitioning to EL3 with an optional 16-bit immediate value encoding the secure service request. The instruction is unconditional and available in Thumb state. Execution requires that secure state is supported; the secure monitor takes control and may use the immediate as a service identifier.

ExceptionSyndromeISS ← imm16; RaiseException(SecureMonitorCallException)


Summary: Returns from an exception (Thumb state).

Exception Return: Returns from exception handling to the instruction following the exception. Restores the PC from ELR_ELx and PSTATE from SPSR_ELx. Execution state and privilege level are determined by the restored PSTATE. This instruction is only available in privileged modes (EL1 and above in AArch64, or with sufficient privilege in A32/T32).

PC ← ELR_ELx
PSTATE ← SPSR_ELx
ExecutionState ← PSTATE.SS
PrivilegeLevel ← PSTATE.M


Summary: Clears a bitfield in a register.

Clears a contiguous bitfield in a register by zeroing bits from lsb to lsb+width-1, leaving other bits unchanged. No condition flags are affected. This is a 32-bit Thumb instruction available in ARMv6T2 and later.

msb ← lsb + width - 1
mask ← (1 << (msb + 1)) - (1 << lsb)
Rd ← Rd AND NOT mask


Summary: Inserts a bitfield into a register.

Inserts a bitfield from a source register into a destination register, clearing bits from lsb to lsb+width-1 and inserting the corresponding bits from Rn. No condition flags are affected. This is a 32-bit Thumb instruction available in ARMv6T2 and later.

msb ← lsb + width - 1
mask ← (1 << (msb + 1)) - (1 << lsb)
Rd ← (Rd AND NOT mask) OR ((Rn << lsb) AND mask)


Summary: Extracts and sign-extends bits.

Signed Bit Field Extract: Extracts a bit field from Rn starting at bit position lsb with width width, sign-extends the result, and writes it to Rd. The condition flags are not affected. This instruction is available in Thumb state (T32) and A32.

lsb_val ← ZeroExtend(imm3:imm2, 6)
width_val ← ZeroExtend(width, 5)
msb ← lsb_val + width_val - 1
extracted ← (Rn >> lsb_val)[width_val-1:0]
if extracted[width_val-1] == 1 then
  Rd ← SignExtend(extracted, 32)
else
  Rd ← ZeroExtend(extracted, 32)


Summary: Extracts and zero-extends bits.

Unsigned Bit Field Extract: Extracts a bit field from Rn starting at bit position lsb with width width, zero-extends the result, and writes it to Rd. The condition flags are not affected. This instruction is available in Thumb state (T32) and A32.

lsb_val ← ZeroExtend(imm3:imm2, 6)
width_val ← ZeroExtend(width, 5)
extracted ← (Rn >> lsb_val)[width_val-1:0]
Rd ← ZeroExtend(extracted, 32)


Summary: Reverses bits in a 32-bit register.

Reverse Bits: Reverses all 32 bits in Rm and writes the result to Rd. Each bit position i is moved to position 31-i. The condition flags are not affected. This instruction is available in Thumb state (T32) and A32.


Summary: Reverses bytes (Endian swap).

Reverses the byte order of a 32-bit word (equivalent to endian conversion). No condition flags are affected. This is a 32-bit Thumb instruction available in ARMv6 and later.


Summary: Reverses bytes in each 16-bit halfword.

Reverses the byte order within each 16-bit halfword independently (bits [31:24] swap with [23:16] and bits [15:8] swap with [7:0]). No condition flags are affected. This is a 32-bit Thumb instruction available in ARMv6 and later.


Summary: Reverses bytes in low halfword and sign-extends.

Reverse Signed Halfword: Reverses the bytes in the low halfword of Rm, sign-extends the result to 32 bits, and writes it to Rd. The high halfword of Rm is ignored. The condition flags are not affected. This instruction is available in Thumb state (T32) and A32.

halfword ← Rm[15:0]
reversed ← (halfword[7:0] << 8) | halfword[15:8]
if reversed[15] == 1 then
  Rd ← SignExtend(reversed, 32)
else
  Rd ← ZeroExtend(reversed, 32)


Summary: Counts consecutive zeros.

Count the number of leading zero bits in the 32-bit value in Rm and place the result in Rd. The result ranges from 0 (all bits set) to 32 (all bits clear). No condition flags are affected. This instruction is available in T32 (Thumb) and executes in all privilege levels.


Summary: Signed integer division.

Perform signed integer division of Rn by Rm and place the quotient in Rd. If Rm is zero, the result is UNPREDICTABLE. If overflow occurs (e.g., INT_MIN / -1), the result is UNPREDICTABLE. No condition flags are affected. This instruction is available in T32 (Thumb) and executes in all privilege levels.

if Rm == 0 then UNPREDICTABLE else Rd ← SignedDivide(Rn, Rm)


Summary: Unsigned integer division.

Perform unsigned integer division of Rn by Rm and place the quotient in Rd. If Rm is zero, the result is UNPREDICTABLE. No condition flags are affected. This instruction is available in T32 (Thumb) and executes in all privilege levels.

if Rm == 0 then UNPREDICTABLE else Rd ← UnsignedDivide(Rn, Rm)


Summary: Rd = Rn + (Rm * Ra).

Ra

Accumulator general-purpose register (multiply-add)

Multiply Rm by Ra and accumulate the result with Rn, placing the 32-bit result in Rd. Condition flags N, Z, C, and V are not affected. This instruction is available in T32 (Thumb) and executes in all privilege levels.


Summary: Rd = Rn - (Rm * Ra).

Multiply Rm by Ra and subtract the result from Rn, placing the 32-bit result in Rd. Condition flags N, Z, C, and V are not affected. This instruction is available in T32 (Thumb) and executes in all privilege levels.


Summary: Unsigned Multiply (64-bit result).

Multiply Rn by Rm as unsigned 32-bit values and place the 64-bit result in RdHi:RdLo, where RdHi receives the upper 32 bits and RdLo receives the lower 32 bits. Condition flags N, Z, C, and V are not affected. This instruction is available in T32 (Thumb) and executes in all privilege levels.

result ← Rn × Rm; RdHi ← result[63:32]; RdLo ← result[31:0]


Unsigned Multiply Accumulate Long (Thumb)

Summary: Unsigned Multiply Accumulate (64-bit result).

Unsigned Multiply Accumulate Long: Multiplies the unsigned 32-bit values in Rn and Rm, accumulates the 64-bit result with the value in RdHi:RdLo, and writes the 64-bit result back to RdHi:RdLo. The condition flags are not affected. This instruction is available in Thumb state (T32) and A32.

product ← ZeroExtend(Rn, 64) × ZeroExtend(Rm, 64)
accumulator ← (RdHi << 32) | RdLo
result ← accumulator + product
RdLo ← result[31:0]
RdHi ← result[63:32]


Summary: Signed Multiply (64-bit result).

Multiply Rn by Rm as signed 32-bit values and place the 64-bit result in RdHi:RdLo, where RdHi receives the upper 32 bits and RdLo receives the lower 32 bits. Condition flags N, Z, C, and V are not affected. This instruction is available in T32 (Thumb) and executes in all privilege levels.

result ← SignedMultiply(Rn, Rm); RdHi ← result[63:32]; RdLo ← result[31:0]


Summary: Signed Multiply Accumulate (64-bit result).

Signed Multiply Accumulate Long: Multiplies the signed 32-bit values in Rn and Rm, accumulates the 64-bit result with the value in RdHi:RdLo, and writes the 64-bit result back to RdHi:RdLo. The condition flags are not affected. This instruction is available in Thumb state (T32) and A32.

product ← SignExtend(Rn, 64) × SignExtend(Rm, 64)
accumulator ← (RdHi << 32) | RdLo
result ← accumulator + product
RdLo ← result[31:0]
RdHi ← result[63:32]


Summary: Loads two words from memory (Thumb).

Load two consecutive 32-bit words from memory at address [Rn ± imm] and place them in Rt and Rt2. The immediate offset is scaled by 4 (range ±1020 bytes). No condition flags are affected. This instruction is available in T32 (Thumb) and executes in all privilege levels.

address ← Rn + (imm8 << 2); Rt ← [address]; Rt2 ← [address + 4]


Summary: Stores two words to memory (Thumb).

Stores two consecutive 32-bit words from registers Rt and Rt2 to memory at the address computed from base register Rn with an optional immediate offset (scaled by 4). The instruction does not modify the condition flags. Execution in Thumb-2 state only.

address ← Rn + (imm8 << 2)
[address] ← Rt
[address + 4] ← Rt2


Summary: Stores word if exclusive monitor is open (Thumb).

Attempts to store a 32-bit word from Rt to memory at the address in Rn only if the exclusive monitor is open; writes 0 to Rd if successful, or 1 if the store fails. No condition flags are modified. Execution in Thumb-2 state only; used for atomic operations and compare-and-swap patterns.

address ← Rn
if ExclusiveMonitor[address] then
  [address] ← Rt
  Rd ← 0
  ClearExclusiveMonitor()
else
  Rd ← 1


Summary: Loads word and sets exclusive monitor (Thumb).

Loads a 32-bit word from memory at the address in Rn into Rt and opens the exclusive monitor for that address. The instruction does not modify the condition flags. Execution in Thumb-2 state only; typically paired with STREX for atomic operations.

address ← Rn
Rt ← [address]
SetExclusiveMonitor(address)


Summary: Stores byte exclusively (Thumb).

Attempts to store the low byte from Rt to memory at the address in Rn only if the exclusive monitor is open; writes 0 to Rd if successful, or 1 if the store fails. No condition flags are modified. Execution in Thumb-2 state only; used for atomic byte-sized operations.

address ← Rn
if ExclusiveMonitor[address] then
  [address] ← Rt[7:0]
  Rd ← 0
  ClearExclusiveMonitor()
else
  Rd ← 1


Summary: Loads byte exclusively (Thumb).

Loads a byte from memory at the address in Rn into the low byte of Rt (zero-extending to 32 bits) and opens the exclusive monitor for that address. The instruction does not modify the condition flags. Execution in Thumb-2 state only; typically paired with STREXB for atomic byte operations.

address ← Rn
Rt ← ZeroExtend([address][7:0], 32)
SetExclusiveMonitor(address)


Store Register Exclusive Halfword (Thumb)

Summary: Stores halfword exclusively (Thumb).

Attempts to store the low halfword from Rt to memory at the address in Rn only if the exclusive monitor is open; writes 0 to Rd if successful, or 1 if the store fails. No condition flags are modified. Execution in Thumb-2 state only; used for atomic halfword-sized operations.

address ← Rn
if ExclusiveMonitor[address] then
  [address] ← Rt[15:0]
  Rd ← 0
  ClearExclusiveMonitor()
else
  Rd ← 1


Load Register Exclusive Halfword (Thumb)

Summary: Loads halfword exclusively (Thumb).

Loads a halfword from memory at the address in Rn into the low halfword of Rt (zero-extending to 32 bits) and opens the exclusive monitor for that address. The instruction does not modify the condition flags. Execution in Thumb-2 state only; typically paired with STREXH for atomic halfword operations.

address ← Rn
Rt ← ZeroExtend([address][15:0], 32)
SetExclusiveMonitor(address)


Summary: Clears exclusive monitor (Thumb).

Clear Exclusive: Clears the exclusive monitor, causing any subsequent STREX or STLEX instructions to fail. This instruction is used to release exclusive access to memory and is typically called after completion of a load-exclusive/store-exclusive sequence. The condition flags are not affected.


Summary: Memory barrier (Thumb).

Data Memory Barrier enforces completion of all explicit data memory operations before any subsequent memory operations are executed. It ensures memory ordering without requiring instruction completion. In Thumb mode, the option field (bits 3:0) specifies the barrier domain: SY (full system), ISH (inner shareable), OSH (outer shareable), or NSH (non-shareable). No condition flags are affected, and this instruction has no restrictions on execution state or privilege level.

if option == SY then
  DataMemoryBarrier(FullSystem)
else if option == ISH then
  DataMemoryBarrier(InnerShareable)
else if option == OSH then
  DataMemoryBarrier(OuterShareable)
else if option == NSH then
  DataMemoryBarrier(NonShareable)
else
  DataMemoryBarrier(FullSystem)


Summary: Sync barrier (Thumb).

Data Synchronization Barrier ensures that all explicit data memory operations before the DSB complete before any subsequent memory, prefetch, or branch operations are executed. The option field specifies the barrier domain (SY, ISH, OSH, NSH). No condition flags are affected. This instruction is available in all privilege levels and execution states.

if option == SY then
  DataSynchronizationBarrier(FullSystem)
else if option == ISH then
  DataSynchronizationBarrier(InnerShareable)
else if option == OSH then
  DataSynchronizationBarrier(OuterShareable)
else if option == NSH then
  DataSynchronizationBarrier(NonShareable)
else
  DataSynchronizationBarrier(FullSystem)


Instruction Synchronization Barrier (Thumb)

Summary: Instruction barrier (Thumb).

Instruction Synchronization Barrier flushes the processor pipeline and ensures that all instructions that follow are fetched from cache or memory after the ISB completes. The option field is typically SY (full system) and is the only valid value in most implementations. No condition flags are affected. ISB is available in all privilege levels and is essential for self-modifying code.

if option == SY then
  InstructionSynchronizationBarrier()
else
  InstructionSynchronizationBarrier()


Summary: No op (Thumb 16-bit).

Performs no operation; used for code alignment, timing adjustments, or as a placeholder instruction. No registers are modified and no condition flags are affected. Available in both A32 and Thumb-2 states.


Summary: Yield hint (Thumb).

Yield is a hint instruction that suggests the processor may improve performance by yielding to other threads or tasks. It does not perform any operation if the yield hint is not implemented. No registers, memory, or condition flags are modified. YIELD is available in all privilege levels and is used for spinlock and busy-wait optimization.


Summary: Wait for event (Thumb).

Wait For Event causes the processor to enter a low-power state and wait until an event is signaled (by WFE, SEV, or external interrupt). If the event register is already set, WFE clears it and returns immediately. No registers or condition flags are modified. This instruction may require specific privilege levels depending on implementation.

if EventRegister == 1 then
  EventRegister ← 0
else
  WaitForEvent()
  EventRegister ← 0


Summary: Wait for interrupt (Thumb).

Wait For Interrupt causes the processor to enter a low-power state and wait until an interrupt is signaled. Execution resumes when an interrupt arrives that is neither masked nor suppressed. No registers or condition flags are modified. WFI is commonly used in idle loops and power management.


Summary: Send event (Thumb).

Send Event sets the event register and wakes all processors in the same inner-shareable domain that are waiting on WFE. This is used for synchronization between multiple CPUs or threads. No registers or condition flags are modified. SEV is available in all privilege levels.

EventRegister ← 1
WakeupInnerShareableDomain()


Summary: Send local event (Thumb).

Send Event Local sets the local event monitor to signaled state, causing any subsequent WFE instruction in the same PE to wake immediately without waiting. This is a Thumb 16-bit instruction that has no effect on condition flags. It is available in ARMv6K and later, and executes in any privilege level.


Move Special Register to Register (Thumb)

Summary: Read special register (Thumb).

Move Special Register to Register reads the value of a system register specified by spec_reg and writes it to the general-purpose register Rd. In T32/Thumb, this is a 32-bit instruction that accesses APSR, IPSR, EPSR, IAPSR, EAPSR, IEPSR, MSPLIM, PSPLIM, or other banked registers depending on the spec_reg encoding. The instruction does not modify the condition flags; it simply transfers the register value.


Move Register to Special Register (Thumb)

Summary: Write special register (Thumb).

Move Register to Special Register writes the value from the general-purpose register Rn to the system register specified by spec_reg. In T32/Thumb, this is a 32-bit instruction used to modify APSR, IPSR, EPSR, or other banked registers. The instruction may update condition flags (N, Z, C, V) if the target is APSR; otherwise, flags remain unaffected based on the register written.


Summary: Change mode/state (Thumb).

Change Processor State changes interrupt masks (I, F, A flags) and optionally changes processor mode in Thumb mode. The effect field (IE/ID) specifies whether to Enable or Disable the specified interrupt flags. This instruction does not affect condition codes and requires appropriate privilege level to change mode.

if effect == 'IE' then
  if 'A' in iflags then CPSR.A ← 0
  if 'I' in iflags then CPSR.I ← 0
  if 'F' in iflags then CPSR.F ← 0
elsif effect == 'ID' then
  if 'A' in iflags then CPSR.A ← 1
  if 'I' in iflags then CPSR.I ← 1
  if 'F' in iflags then CPSR.F ← 1
if mode_specified then
  CPSR.M ← mode


Summary: Set endianness (Thumb).

Set Endianness changes the endianness state in the CPSR: BE sets big-endian, LE sets little-endian. This Thumb instruction does not affect condition codes and requires appropriate privilege level (typically User mode cannot change this). The change takes effect on the next memory access.

if endian == 'BE' then
  CPSR.E ← 1
elsif endian == 'LE' then
  CPSR.E ← 0


Summary: Debug hint (Thumb).

Debug Hint provides a hint to the debugger about the execution state, encoded in a 4-bit option field. The instruction is a no-op from an architectural perspective and does not modify registers, memory, or condition flags. It is useful for marking debug checkpoints in code.

// Debug hint - architecturally NOP
// Debugger may act on option field
PC ← PC + instruction_length


Summary: Pop registers from stack (Thumb 16-bit).

Pop Registers from Stack loads multiple registers from memory addresses specified by the SP register, incrementing SP after each load. The P bit in the encoding indicates whether the PC is included in the register list. This Thumb 16-bit instruction does not affect condition flags directly but may load into the PC, which can cause a branch.

address ← SP
for each register in register_list (in ascending order):
  register ← [address]
  address ← address + 4
SP ← address
if P == 1 then
  PC ← [SP - 4]
  address ← address (SP already updated)


Summary: Push registers to stack (Thumb 16-bit).

Push Registers to Stack stores multiple registers to memory addresses specified by the SP register, decrementing SP before each store. The M bit in the encoding indicates whether the LR is included in the register list. This Thumb 16-bit instruction does not affect condition flags.

address ← SP
for each register in register_list (in descending order):
  address ← address - 4
  [address] ← register
SP ← address
if M == 1 then
  address ← address - 4
  [address] ← LR
  SP ← address


Summary: Load multiple registers (Thumb 16-bit).

Load Multiple (Thumb 16-bit) loads multiple registers from memory at addresses formed by Rn, and optionally updates Rn to point to the next memory location. The register list is encoded in an 8-bit field. If Rn is the SP, this can function as a pop operation. Condition flags are not modified by the load itself, but if the PC is in the register list, execution continues at the loaded address.

address ← Rn
for each register in register_list (in ascending order):
  register ← [address]
  address ← address + 4
Rn ← address
if PC in register_list:
  PC ← loaded_PC_value


Summary: Store multiple registers (Thumb 16-bit).

Store Multiple (Thumb 16-bit) stores multiple registers to memory at addresses formed by Rn, and optionally updates Rn to point to the next memory location. The register list is encoded in an 8-bit field. If Rn is the SP, this can function as a push operation. Condition flags are not modified.

address ← Rn
for each register in register_list (in ascending order):
  [address] ← register
  address ← address + 4
Rn ← address


Summary: Sets elements of the predicate register to true (all active).

SVE Initialize Predicate to True sets all active elements of the destination predicate register to 1 (true) based on the specified pattern and element type. The pattern field controls which elements are considered active (e.g., VL1, VL2, all). This SVE instruction does not affect PSTATE condition flags.

num_active ← GetPatternLength(pattern, <T>)
for i = 0 to (VL / element_bits - 1):
  if i < num_active then
    Pd[i] ← 1
  else
    Pd[i] ← 0


Summary: Clears all elements of the predicate register.

SVE Initialize Predicate to False clears all elements of the destination predicate register to 0 (false). This SVE instruction is equivalent to PTRUE with pattern 'none' and does not affect PSTATE condition flags. The .B suffix is fixed for this instruction.


Summary: Loads bytes from memory into a vector under predicate control.

Loads contiguous bytes from memory into a SVE vector register under predicate control. Each active predicate element (indicated by Pg) loads one byte from the address sequence starting at [Xn|SP], zero-extending to fill the byte element. Inactive elements are zeroed (Z suffix semantics). No flags are affected.

for i = 0 to VL/8-1
  if Pg[i] == 1 then
    Zt.B[i] ← [Xn + i]
  else
    Zt.B[i] ← 0


Summary: Loads halfwords from memory into a vector under predicate control.

Loads contiguous halfwords from memory into a SVE vector register under predicate control. Each active predicate element loads one 16-bit value from the address sequence [Xn|SP + 2*i], zero-extending to fill the halfword element. Inactive elements are zeroed (Z suffix semantics). No flags are affected.

for i = 0 to VL/16-1
  if Pg[i] == 1 then
    Zt.H[i] ← [Xn + 2*i]
  else
    Zt.H[i] ← 0


Summary: Loads words from memory into a vector under predicate control.

Loads contiguous words from memory into a SVE vector register under predicate control. Each active predicate element loads one 32-bit value from the address sequence [Xn|SP + 4*i], zero-extending to fill the word element. Inactive elements are zeroed (Z suffix semantics). No flags are affected.

for i = 0 to VL/32-1
  if Pg[i] == 1 then
    Zt.S[i] ← [Xn + 4*i]
  else
    Zt.S[i] ← 0


Summary: Loads doublewords from memory into a vector under predicate control.

Loads contiguous doublewords from memory into a SVE vector register under predicate control. Each active predicate element loads one 64-bit value from the address sequence [Xn|SP + 8*i]. Inactive elements are zeroed (Z suffix semantics). No flags are affected.

for i = 0 to VL/64-1
  if Pg[i] == 1 then
    Zt.D[i] ← [Xn + 8*i]
  else
    Zt.D[i] ← 0


Summary: Stores active bytes from vector to memory.

Stores active bytes from a SVE vector register to memory under predicate control. Only elements where the corresponding predicate bit is set are written; inactive elements do not generate memory operations. No flags are affected.

for i = 0 to VL/8-1
  if Pg[i] == 1 then
    [Xn + i] ← Zt.B[i]


Summary: Stores active halfwords from vector to memory.

Stores active halfwords from a SVE vector register to memory under predicate control. Only elements where the corresponding predicate bit is set are written to addresses [Xn|SP + 2*i]; inactive elements do not generate memory operations. No flags are affected.

for i = 0 to VL/16-1
  if Pg[i] == 1 then
    [Xn + 2*i] ← Zt.H[i]


Summary: Stores active words from vector to memory.

Stores active words from a SVE vector register to memory under predicate control. Only elements where the corresponding predicate bit is set are written to addresses [Xn|SP + 4*i]; inactive elements do not generate memory operations. No flags are affected.

for i = 0 to VL/32-1
  if Pg[i] == 1 then
    [Xn + 4*i] ← Zt.S[i]


Summary: Stores active doublewords from vector to memory.

Stores active doublewords from a SVE vector register to memory under predicate control. Only elements where the corresponding predicate bit is set are written to addresses [Xn|SP + 8*i]; inactive elements do not generate memory operations. No flags are affected.

for i = 0 to VL/64-1
  if Pg[i] == 1 then
    [Xn + 8*i] ← Zt.D[i]


Summary: Generates a predicate based on a loop counter (while Xn < Xm).

Generates a predicate register by comparing a loop counter with a limit, setting each element to true if counter < limit. Operates on 64-bit signed integers and generates a predicate for elements of type T (8-bit, 16-bit, 32-bit, or 64-bit). No flags are affected. This is an AArch64-only SVE instruction.

for i = 0 to VL/esize-1
  Pd[i] ← (Xn < Xm)


Summary: Generates a predicate based on loop counter (while Xn <= Xm).

Generates a predicate register by comparing a loop counter with a limit, setting each element to true if counter ≤ limit. Operates on 64-bit signed integers and generates a predicate for elements of type T. No flags are affected. This is an AArch64-only SVE instruction.

for i = 0 to VL/esize-1
  Pd[i] ← (Xn <= Xm)


Summary: Adds two vectors under predicate control.

Zm

Second source scalable vector register (SVE)

SVE Integer Add (Predicated) adds two scalable vector registers Zdn and Zm element-wise under predicate control, storing the result back in Zdn. Elements not selected by the predicate Pg are unchanged (merge behavior). The element type T is determined by the sz encoding (8, 16, 32, or 64 bits). Condition flags are not modified.

for i in 0 to VL/element_width - 1:
  if Pg[i] == 1:
    Zdn[i] ← Zdn[i] + Zm[i]
  // else: Zdn[i] remains unchanged


Summary: Subtracts vector Zm from Zdn under predicate.

SVE Integer Subtract (Predicated) subtracts the scalable vector register Zm from Zdn element-wise under predicate control, storing the result back in Zdn. Elements not selected by the predicate Pg are unchanged (merge behavior). The element type T is determined by the sz encoding (8, 16, 32, or 64 bits). Condition flags are not modified.

for i in 0 to VL/element_width - 1:
  if Pg[i] == 1:
    Zdn[i] ← Zdn[i] - Zm[i]
  // else: Zdn[i] remains unchanged


Summary: Multiplies two vectors under predicate.

SVE Integer Multiply (Predicated) multiplies two scalable vector registers Zdn and Zm element-wise under predicate control, storing the result back in Zdn. Elements not selected by the predicate Pg are unchanged (merge behavior). The element type T is determined by the sz encoding (8, 16, 32, or 64 bits). Condition flags are not modified.

for i in 0 to VL/element_width - 1:
  if Pg[i] == 1:
    Zdn[i] ← Zdn[i] * Zm[i]
  // else: Zdn[i] remains unchanged


Summary: Selects elements from Zn or Zm based on predicate.

Zd

Destination scalable vector register (SVE)

Conditionally selects elements from two source vectors based on a predicate mask, placing results in the destination vector. For each element, if the predicate bit is set, the element from Zn is selected; otherwise, the element from Zm is selected. Operates on elements of type T and no flags are affected. This is an AArch64-only SVE instruction.

for i = 0 to VL/esize-1
  if Pg[i] then
    Zd[i] ← Zn[i]
  else
    Zd[i] ← Zm[i]


Summary: Generates a vector of indices: V[i] = Start + i * Step.

Generates an index vector where each element contains a value computed as Start + element_index × Step. The Start and Step operands may be immediate values or scalar registers. Operates on elements of type T and no flags are affected. This is an AArch64-only SVE instruction.

for i = 0 to VL/esize-1
  Zd[i] ← Start + (i * Step)


Summary: Broadcasts a scalar register or immediate to all active vector elements.

Broadcasts a scalar value from a general-purpose register to all elements of a vector. The destination register Zd is set to replicate the source scalar across all elements of type T without predication. No flags are affected. This is an AArch64-only SVE instruction.


Summary: Copies scalar value to active vector elements (Alias for DUP predicated).

Copies a scalar value from a general-purpose register to active elements of a vector under predicate control. Only elements where the predicate is true are updated; inactive elements remain unchanged. Operates on elements of type T and no flags are affected. This is an AArch64-only SVE instruction.

for i = 0 to VL/esize-1
  if Pg[i] then
    Zd[i] ← Rn


Summary: Increments a general-purpose register by the number of active bytes in the pattern.

Increments a 64-bit general-purpose register by the count of active bytes matching the specified pattern, optionally scaled by an immediate multiplier. The pattern defines which byte positions are considered active (e.g., all bytes, even bytes, etc.). No condition flags are affected. This is an AArch64-only SVE instruction.

Xdn ← Xdn + (CountActiveBytes(pattern) × (1 + imm4))


Summary: Increments a register by the number of active words.

Increments a 64-bit general-purpose register by the count of active words matching the specified pattern, optionally scaled by an immediate multiplier. The pattern defines which word positions are considered active. No condition flags are affected. This is an AArch64-only SVE instruction.

Xdn ← Xdn + (CountActiveWords(pattern) × (1 + imm4))


SVE Increment Scalar by Doubleword Count

Summary: Increments a register by the number of active doublewords.

Increments a 64-bit scalar register by the count of active doublewords in the SVE vector length, optionally multiplied by an immediate. The increment amount is calculated as VL/8 (number of 64-bit elements) times an optional multiplier (1-16). No condition flags are affected. AArch64-only instruction requiring SVE extension.

count ← CountActiveDoublewords(pattern)
multiplier ← imm4 if imm4 != 0 else 1
Xdn ← Xdn + (count * multiplier)


Summary: Decrements a register by the number of active bytes.

Decrements a 64-bit scalar register by the count of active bytes in the SVE vector length, optionally multiplied by an immediate. The decrement amount is calculated as VL/1 (number of byte elements) times an optional multiplier (1-16). No condition flags are affected. AArch64-only instruction requiring SVE extension.

count ← CountActiveBytes(pattern)
multiplier ← imm4 if imm4 != 0 else 1
Xdn ← Xdn - (count * multiplier)


Summary: Decrements a register by the number of active words.

Decrements a 64-bit scalar register by the count of active words in the SVE vector length, optionally multiplied by an immediate. The decrement amount is calculated as VL/4 (number of 32-bit elements) times an optional multiplier (1-16). No condition flags are affected. AArch64-only instruction requiring SVE extension.

count ← CountActiveWords(pattern)
multiplier ← imm4 if imm4 != 0 else 1
Xdn ← Xdn - (count * multiplier)


SVE Decrement Scalar by Doubleword Count

Summary: Decrements a register by the number of active doublewords.

Decrements a 64-bit scalar register by the count of active doublewords in the SVE vector length, optionally multiplied by an immediate. The decrement amount is calculated as VL/8 (number of 64-bit elements) times an optional multiplier (1-16). No condition flags are affected. AArch64-only instruction requiring SVE extension.

count ← CountActiveDoublewords(pattern)
multiplier ← imm4 if imm4 != 0 else 1
Xdn ← Xdn - (count * multiplier)


Summary: Bitwise AND of two vectors under predicate.

Zdn

Combined destination/source scalable vector register (SVE)

Performs element-wise bitwise AND between two SVE vector registers under predicate control. Only elements where the corresponding predicate bit is 1 are updated; others are left unchanged. No condition flags are affected. This is an AArch64-only SVE instruction requiring SVE support.

for i = 0 to VL/esize-1 do
  if Pg[i] then
    Zdn[i*esize +: esize] ← Zdn[i*esize +: esize] AND Zm[i*esize +: esize]
  else
    // element unchanged
endfor


Summary: Bitwise OR of two vectors under predicate.

Performs element-wise bitwise OR between two SVE vector registers under predicate control. Only elements where the corresponding predicate bit is 1 are updated; others are left unchanged. No condition flags are affected. This is an AArch64-only SVE instruction requiring SVE support.

for i = 0 to VL/esize-1 do
  if Pg[i] then
    Zdn[i*esize +: esize] ← Zdn[i*esize +: esize] OR Zm[i*esize +: esize]
  else
    // element unchanged
endfor


Summary: Bitwise XOR of two vectors under predicate.

Performs element-wise bitwise exclusive OR (XOR) between two SVE vector registers under predicate control. Only elements where the corresponding predicate bit is 1 are updated; others are left unchanged. No condition flags are affected. This is an AArch64-only SVE instruction requiring SVE support.

for i = 0 to VL/esize-1 do
  if Pg[i] then
    Zdn[i*esize +: esize] ← Zdn[i*esize +: esize] EOR Zm[i*esize +: esize]
  else
    // element unchanged
endfor


Summary: Bitwise AND NOT of two vectors under predicate.

Performs element-wise bitwise AND with inverted second operand (AND NOT) between two SVE vector registers under predicate control. Only elements where the corresponding predicate bit is 1 are updated; others are left unchanged. No condition flags are affected. This is an AArch64-only SVE instruction requiring SVE support.

for i = 0 to VL/esize-1 do
  if Pg[i] then
    Zdn[i*esize +: esize] ← Zdn[i*esize +: esize] AND NOT Zm[i*esize +: esize]
  else
    // element unchanged
endfor


Summary: Adds floating-point elements under predicate.

Adds corresponding floating-point elements in Zdn and Zm, writing results back to Zdn under the control of predicate Pg in merging mode. The operation is performed element-by-element on 32-bit, 64-bit, or 16-bit (half-precision) floating-point values as indicated by the type specifier. No condition flags are affected; inactive elements are preserved in Zdn. AArch64-only instruction requiring SVE extension.

for i ← 0 to VL/esize - 1
  if Pg[i] == 1 then
    Zdn[i] ← Zdn[i] + Zm[i]
  else
    Zdn[i] ← Zdn[i]  // unchanged


Summary: Subtracts floating-point elements under predicate.

Subtracts corresponding floating-point elements (Zm from Zdn), writing results back to Zdn under the control of predicate Pg in merging mode. The operation is performed element-by-element on 32-bit, 64-bit, or 16-bit (half-precision) floating-point values as indicated by the type specifier. No condition flags are affected; inactive elements are preserved in Zdn. AArch64-only instruction requiring SVE extension.

for i ← 0 to VL/esize - 1
  if Pg[i] == 1 then
    Zdn[i] ← Zdn[i] - Zm[i]
  else
    Zdn[i] ← Zdn[i]  // unchanged


Summary: Multiplies floating-point elements under predicate.

Multiplies corresponding floating-point elements in Zdn and Zm, writing results back to Zdn under the control of predicate Pg in merging mode. The operation is performed element-by-element on 32-bit, 64-bit, or 16-bit (half-precision) floating-point values as indicated by the type specifier. No condition flags are affected; inactive elements are preserved in Zdn. AArch64-only instruction requiring SVE extension.

for i ← 0 to VL/esize - 1
  if Pg[i] == 1 then
    Zdn[i] ← Zdn[i] * Zm[i]
  else
    Zdn[i] ← Zdn[i]  // unchanged


Summary: Divides floating-point elements under predicate.

Divides corresponding floating-point elements (Zdn by Zm), writing results back to Zdn under the control of predicate Pg in merging mode. The operation is performed element-by-element on 32-bit, 64-bit, or 16-bit (half-precision) floating-point values as indicated by the type specifier. No condition flags are affected; inactive elements are preserved in Zdn. Division by zero produces a signed infinity or NaN according to IEEE floating-point semantics. AArch64-only instruction requiring SVE extension.

for i ← 0 to VL/esize - 1
  if Pg[i] == 1 then
    Zdn[i] ← Zdn[i] / Zm[i]
  else
    Zdn[i] ← Zdn[i]  // unchanged


Summary: Determines maximum value of active float elements.

SVE floating-point maximum operation that computes element-wise maximum of two scalable vectors under predicate control. For each active element in the predicate mask, the larger of the two floating-point values is written to the destination. Inactive elements (where the predicate is false) are left unchanged in the destination register. NZCV flags are not affected by this instruction.

for i = 0 to VL/element_size-1:
  if Pg[i] then
    Zdn[i] ← max(Zdn[i], Zm[i])
  else
    Zdn[i] ← Zdn[i]


Summary: Determines minimum value of active float elements.

SVE floating-point minimum operation that computes element-wise minimum of two scalable vectors under predicate control. For each active element in the predicate mask, the smaller of the two floating-point values is written to the destination. Inactive elements (where the predicate is false) are left unchanged in the destination register. NZCV flags are not affected by this instruction.

for i = 0 to VL/element_size-1:
  if Pg[i] then
    Zdn[i] ← min(Zdn[i], Zm[i])
  else
    Zdn[i] ← Zdn[i]


Summary: Calculates (Zda + Zn * Zm) under predicate.

Zn

First source scalable vector register (SVE)

SVE floating-point fused multiply-add instruction that computes Zda + (Zn × Zm) for each element under predicate control, with a single rounding step at the end. Inactive elements (where the predicate is false) are left unchanged in the destination. This instruction performs true fusedoperation with only one rounding error, unlike separate multiply and add instructions. NZCV flags are not affected.

for i = 0 to VL/element_size-1:
  if Pg[i] then
    Zda[i] ← Zda[i] + (Zn[i] × Zm[i])
  else
    Zda[i] ← Zda[i]


SVE Floating-Point Fused Multiply-Subtract

Summary: Calculates (Zda - Zn * Zm) under predicate.

SVE floating-point fused multiply-subtract instruction that computes Zda - (Zn × Zm) for each element under predicate control, with a single rounding step at the end. Inactive elements (where the predicate is false) are left unchanged in the destination. This instruction performs true fused operation with only one rounding error, unlike separate multiply and subtract instructions. NZCV flags are not affected.

for i = 0 to VL/element_size-1:
  if Pg[i] then
    Zda[i] ← Zda[i] - (Zn[i] × Zm[i])
  else
    Zda[i] ← Zda[i]


Summary: Sums all active unsigned elements into a scalar result.

SVE unsigned integer addition reduction that sums all active elements in the source vector under predicate control and writes the scalar result to the destination. The destination is a general-purpose scalar register sized according to the element type. Elements where the predicate is false are excluded from the sum. NZCV flags are not affected by this reduction.

result ← 0
for i = 0 to VL/element_size-1:
  if Pg[i] then
    result ← result + Zn[i]
Vd ← result


Summary: Sums all active floating-point elements into a scalar result.

SVE floating-point addition reduction that sums all active floating-point elements in the source vector under predicate control and writes the scalar result to the destination. The destination is a floating-point scalar register sized according to the element type. Elements where the predicate is false are excluded from the sum. Reductions are performed with strict left-to-right ordering for reproducibility. NZCV flags are not affected.

result ← 0.0
for i = 0 to VL/element_size-1:
  if Pg[i] then
    result ← result + Zn[i]
Vd ← result


Summary: Finds the next active predicate bit.

SVE predicate find-next instruction that scans the source predicate register for the next active bit after the position currently set in the predicate, under control of the governing predicate. The destination predicate is updated to indicate the position of the next active element. Sets the Z flag if no further active element is found. This instruction is useful for iterating through active predicate elements.

next_pos ← -1
for i = 0 to VL-1:
  if Pg[i] ∧ Pdn[i] then
    for j = i+1 to VL-1:
      if Pg[j] ∧ Pdn[j] then
        next_pos ← j
        break
    break
if next_pos ≥ 0 then
  Pdn ← (1 << next_pos)
  Z ← 0
else
  Pdn ← 0
  Z ← 1


Summary: Sets predicates up to and including the first active element.

SVE break-after instruction that creates a new predicate containing all bits from the first active bit (inclusive) up to and including the first false bit in the input predicate, under control of the governing predicate. The destination predicate contains a contiguous sequence of true bits starting from the first true bit in the source. Sets the Z flag if no active bits are found in the input. This is useful for creating masks that break execution at the first false element.

first_true ← -1
for i = 0 to VL-1:
  if Pg[i] ∧ Pn[i] then
    first_true ← i
    break
if first_true ≥ 0 then
  Pd ← 0
  for i = first_true to VL-1:
    if Pg[i] then
      Pd[i] ← 1
      if ¬Pn[i] then
        break
  Z ← 0
else
  Pd ← 0
  Z ← 1


Summary: Sets predicates up to (but excluding) the first active element.

SVE Break Before First True sets all predicate elements up to (but excluding) the first active element in Pn (as governed by Pg) to 1, and all subsequent elements to 0. The instruction is used to isolate processing before the first true element in a predicate. No condition flags are affected. This is an AArch64-only SVE instruction requiring SVE support.

integer esize = 8;
integer elements = VL / esize;
integer g = 0;
for e = 0 to elements-1
  if Pg[e] == '1' and Pn[e] == '1' and g == 0 then
    g = 1;
  if g == 0 then
    Pd[e] = '1';
  else
    Pd[e] = '0';


Summary: Packs active elements to the bottom of the vector.

SVE Compact Vector permutes the vector Zn such that all elements for which the corresponding predicate bit in Pg is 1 are packed contiguously at the low end of Zd, in order, with remaining elements zeroed. This operation is useful for gathering active elements. No condition flags are affected. This is an AArch64-only SVE instruction requiring SVE support.

integer esize = 8 << UInt(sz);
integer elements = VL / esize;
integer dst_index = 0;
for e = 0 to elements-1
  if Pg[e] == '1' then
    Zd[dst_index * esize +: esize] = Zn[e * esize +: esize];
    dst_index = dst_index + 1;
for e = dst_index to elements-1
  Zd[e * esize +: esize] = 0;