Summary: Subtracts the contents of two vector registers and places the result in a target vector register.

For xvsubdp, each double-precision floating-point operand in the source vector registers is negated and added to the corresponding operand in the other source vector register. The results are normalized and rounded to double precision before being stored in the target vector register.

for i = {0, 1} do
    src1 <- VSR[XA][i]
    src2 <- VSR[XB][i]
    if src1 is NaN or src2 is NaN then
        v <- Q(src1) if src1 is NaN else Q(src2)
        vxsnan_flag <- 1 if either src1 or src2 is SNaN
    else if src1 is +Infinity and src2 is +Infinity then
        v <- +Infinity
        vxisi_flag <- 1
    else if src1 is -Infinity and src2 is -Infinity then
        v <- -Infinity
        vxisi_flag <- 1
    else if src1 is NZF and src2 is NZF then
        v <- S(src1, -src2)
    else if src1 is Zero and src2 is Zero then
        v <- Rezd
    else if src1 is +Zero and src2 is -Zero then
        v <- +Zero
    else if src1 is -Zero and src2 is +Zero then
        v <- -Zero
    else if src1 is NZF and src2 is Zero then
        v <- src1
    else if src1 is Zero and src2 is NZF then
        v <- -src2
    else if src1 is NZF and src2 is +Infinity then
        v <- -Infinity
    else if src1 is NZF and src2 is -Infinity then
        v <- +Infinity
    else if src1 is Zero and src2 is +Infinity then
        v <- -Infinity
    else if src1 is Zero and src2 is -Infinity then
        v <- +Infinity
    VSR[VX][i] <- v

The xvsubdp instruction performs element-wise subtraction of double-precision floating-point numbers from two source vectors, negating the operands before addition. Be cautious with NaN and infinity values as they can set flags (vxsnan_flag, vxisi_flag) and affect results. Ensure proper alignment for vector registers to avoid performance penalties.


Summary: Multiplies two double-precision floating-point numbers in vector registers and stores the result.

VSX Vector Multiply Double-Precision multiplies two double-precision floating-point elements from VSX registers XA and XB, storing the results in VSX register XT. This VSX category instruction processes two 64-bit elements in parallel and may update FPSCR with floating-point exception flags.

The xvmuldp instruction performs element-wise multiplication of double-precision floating-point values in VSX registers. Ensure that the input vectors are properly aligned to avoid alignment faults. Be cautious with NaN and infinity handling, as they follow specific rules for propagation and sign determination. This instruction operates at user privilege level.


Summary: Divides the contents of two vector registers and places the result in another vector register.

For xvdivdp, each double-precision floating-point operand in doubleword elements of VSR[XA] is divided by the corresponding operand in VSR[XB], producing a quotient that is normalized and rounded to double precision. The result is placed into doubleword elements of VSR[XT].

for i = 0 to 1 do
    src1 <- VSR[XA][i]
    src2 <- VSR[XB][i]
    if src2 is NaN then
        v <- Q(src2)
        vxsnan_flag <- 1
    else if src1 is NaN then
        v <- Q(src1)
        vxsnan_flag <- 1
    else if src1 is +Infinity and src2 is +Infinity then
        v <- +Infinity
        vxidi_flag <- 1
    else if src1 is -Infinity and src2 is -Infinity then
        v <- +Infinity
        vxidi_flag <- 1
    else if src1 is +Infinity and src2 is -Infinity then
        v <- -Infinity
        vxidi_flag <- 1
    else if src1 is -Infinity and src2 is +Infinity then
        v <- -Infinity
        vxidi_flag <- 1
    else if src1 is +Zero and src2 is +Zero then
        v <- +Zero
        zx_flag <- 1
    else if src1 is -Zero and src2 is -Zero then
        v <- +Zero
        zx_flag <- 1
    else if src1 is +Zero and src2 is -Zero then
        v <- -Zero
        zx_flag <- 1
    else if src1 is -Zero and src2 is +Zero then
        v <- -Zero
        zx_flag <- 1
    else if src1 is +Infinity or src1 is -Infinity and src2 is not zero then
        v <- Q(src2)
        vxidi_flag <- 1
    else if src2 is +Zero or src2 is -Zero and src1 is not zero then
        v <- dQNaN
        vxzdz_flag <- 1
    else
        v <- D(src1, src2)
    VSR[VRT][i] <- v

FPSCR, VXSNAN, VXIDI, VXZDZ, OX, UX, ZX, XX

The xvdivdp instruction performs element-wise division of double-precision floating-point numbers. Ensure that the input vectors are properly aligned and that the destination vector is distinct to avoid unintended data corruption. Be aware of special cases like division by zero, which sets VXZDZ flag and results in a NaN. Handle exceptions by checking the FPSCR register flags after execution.


VSX Vector Absolute Value Double-Precision

Summary: Computes the absolute value of each double-precision floating-point element in a vector.

The instruction computes the absolute value of each double-precision floating-point element in the source vector VSR[XB] and stores the result in the target vector VSR[XT].

if MSR.VSX=0 then
    VSX_Unavailable()
do i = 0 to 1
    src ←VSR[32×BX+B].dword[i]
    VSR[32×TX+T].dword[i] ←bfp64_ABSOLUTE(src)
end

This instruction is used to compute the absolute value of each double-precision floating-point element in a vector. Ensure that VSX (Vector Scalar Extensions) is enabled by checking and setting the appropriate bit in the MSR register. The operation processes two elements per vector register, so ensure proper alignment if manipulating individual elements directly.


Summary: Negates the contents of a double-precision floating-point vector register and stores the result in another vector register.

The instruction negates each doubleword element of the source vector register VSR[XB] and stores the results in the target vector register VSR[XT].

if MSR.VSX=0 then VSX_Unavailable()
do i = 0 to 3
    src ←VSR[32×BX+B].dword[i]
    VSR[32×TX+T].dword[i] ←bfp64_NEGATE(src)
end

This instruction is used to negate each double-precision floating-point element in a vector. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking and setting the appropriate bit in the MSR register. The operation processes four elements per vector register, so ensure proper alignment of data for optimal performance. This instruction operates at the user privilege level and will raise an exception if VSX is not available.


Summary: Computes the square root of each double-precision floating-point element in a vector.

For xvsqrtdp, the unbounded-precision square root of each double-precision floating-point operand in doubleword elements of VSR[XB] is computed and rounded to double-precision format. The result is placed into corresponding elements of VSR[XT].

if MSR.VSX=0 then VSX_Unavailable()
ex_flag ←0b0
do i = 0 to 1
    reset_xflags()
    src ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])
    v   ←bfp_SQUARE_ROOT(src)
    rnd ←bfp_ROUND_TO_BFP64(0b0,FPSCR.RN,v)
    vresult.dword[i] ←bfp64_CONVERT_FROM_BFP(rnd)
    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    if vxsqrt_flag=1 then SetFX(FPSCR.VXSQRT)
    if xx_flag=1 then SetFX(FPSCR.XX)
    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vxsqrt_flag) | (FPSCR.XE & xx_flag)
end
if ex_flag=0 then VSR[32×TX+T] ←vresult

The xvsqrtdp instruction computes the square root of each double-precision floating-point operand in a vector. Ensure that VSX is enabled by checking MSR.VSX. Handle exceptions by examining FPSCR flags such as VXSNAN, VXSQRT, and XX. The instruction operates on aligned data and requires supervisor privilege level.


Vector Scalar Maximum Double-Precision Floating Point

Summary: Compares two double-precision floating-point values and selects the maximum value for each element.

For xvmaxdp, the instruction compares the double-precision floating-point values in the elements of VSR[XA] and VSR[XB], and places the maximum value into the corresponding elements of VSR[XT].

for i in {0, 1} do
    src1 <- VSR[XA][i]
    src2 <- VSR[XB][i]
    if src1 is QNaN or src2 is QNaN then
        T(Q(src2))
    else if src1 is SNaN or src2 is SNaN then
        fx(VXSNAN)
    else if src1 is +Infinity and src2 is -Infinity then
        T(src1)
    else if src1 is -Infinity and src2 is +Infinity then
        T(src2)
    else if src1 is NZF and src2 is Zero then
        T(src1)
    else if src1 is Zero and src2 is NZF then
        T(src2)
    else if src1 is NZF and src2 is NZF then
        T(M(src1,src2))
    else if src1 is +Zero and src2 is +Zero then
        T(src1)
    else if src1 is -Zero and src2 is -Zero then
        T(src2)
    else if src1 is +Infinity and src2 is +Infinity then
        T(src1)
    else if src1 is -Infinity and src2 is -Infinity then
        T(src2)
    else if src1 is QNaN or SNaN then
        T(src2)
    end if
end for

This instruction compares two double-precision floating-point vectors element-wise and stores the maximum value in each corresponding element of the destination vector. Be cautious with NaN values, as they can trigger exceptions or propagate through the operation. Ensure that the input vectors are properly aligned to avoid performance penalties.


Summary: Compares two double-precision floating-point values and selects the minimum value for each element.

VSX Vector Minimum Double-Precision compares two double-precision floating-point elements from VSX registers XA and XB element-wise, selecting the minimum value for each element and storing results in VSX register XT. This VSX category instruction processes two 64-bit elements in parallel and follows IEEE 754 minimum semantics.

The xvmindp instruction is used to perform element-wise minimum comparison of double-precision floating-point values in VSX registers. Ensure that the input vectors are properly aligned and that the FPSCR register is correctly configured to handle exceptions like NaNs or infinities. This instruction operates at a privilege level that allows access to VSX registers, typically requiring supervisor or higher privileges.


VSX Vector Compare Equal Double-Precision

Summary: Compares two double-precision floating-point values in vector registers and sets the target register based on equality.

For xvcmpeqdp, each element of the source vectors VSR[XA] and VSR[XB] is compared. The result is stored in VSR[XT]. If Rc=1, CR field 6 is updated with comparison results.

if MSR.VSX=0 then VSX_Unavailable()
ex_flag ←0b0
all_false ←0b1
all_true ←0b1
do i = 0 to 1
    reset_xflags()
    src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[i])
    src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])
    vxsnan_flag ←IsSNaN(src1) | IsSNaN(src2)
    if src1 = src2 then do
        all_false ←0b0
    end
    else do
        vresult.dword[i] ←0x0000_0000_0000_0000
        all_true ←0b0
    end
    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag)
end
if Rc=1 then do
    if vex_flag=0 then
        CR[6] ←all_true || 0b0 || all_false || 0b0
    else
        CR[6] ←0bUUUU
end

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.


VSX Vector Compare Greater Than Double-Precision

Summary: Compares two double-precision floating-point values and sets the target vector register based on the comparison.

For xvcmpgtdp, each element of the source vectors VSR[XA] and VSR[XB] is compared. The result is stored in VSR[XT]. If Rc=1, CR Field 6 is updated with the results of the comparison.

if MSR.VSX=0 then VSX_Unavailable()

ex_flag ← 0b0
all_false ← 0b1
all_true ← 0b1
do i = 0 to 1
    reset_xflags()
    src1 ← bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[i])
    src2 ← bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])
    if src1.class.SNaN | src2.class.SNaN then do
        vxsnan_flag ← 0b1
        if FPSCR.VE=0 then vxvc_flag ← 0b1
    end else vxvc_flag ← IsQNaN(src1) | IsQNaN(src2)
    if src1 > src2 then do
        vresult.dword[i] ← 0xFFFF_FFFF_FFFF_FFFF
        all_false ← 0b0
    end else do
        all_true ← 0b0
        vresult.dword[i] ← 0x0000_0000_0000_0000
    end
    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    if vxvc_flag=1 then SetFX(FPSCR.VXVC)
    ex_flag ← ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vxvc_flag)
end
if ex_flag=0 then VSR[32×TX+T] ← vresult
if Rc=1 then do
    if vex_flag=0 then CR.field[6] ← all_true || 0b0 || all_false || 0b0 else CR.field[6] ← 0bUUUU
end


VSX Vector Compare Greater or Equal Double-Precision

For xvcmpgedp, each integer value i from 0 to 1, the double-precision floating-point operand in doubleword element i of VSR[XA] is compared to the double-precision floating-point operand in doubleword element i of VSR[XB]. The contents of doubleword element i of VSR[XT] are set to all 1s if src1 is greater than or equal to src2, and is set to all 0s otherwise.

if MSR.VSX=0 then VSX_Unavailable()
ex_flag ←0b0
all_false ←0b1
all_true ←0b1
do i = 0 to 1
    reset_xflags()
    src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[i])
    src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])
    if src1.class.SNaN | src2.class.SNaN then do
        vxsnan_flag ←0b1
        if FPSCR.VE=0 then vxvc_flag ←0b1
    end
    else vxvc_flag ←IsQNaN(src1) | IsQNaN(src2)
    if src1 >= src2 then do
        vresult.dword[i] ←0xFFFF_FFFF_FFFF_FFFF
        all_false ←0b0
    end
    else do
        vresult.dword[i] ←0x0000_0000_0000_0000
        all_true ←0b0
    end
    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    if vxvc_flag=1 then SetFX(FPSCR.VXVC)
    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vxvc_flag)
end
if ex_flag=0 then VSR[32×TX+T] ←vresult
if Rc=1 then do
    if vex_flag=0 then CR.field[6] ←all_true || 0b0 || all_false || 0b0
    else CR.field[6] ←0bUUUU
end


Summary: Adds the contents of two single-precision floating-point vector registers and places the result in another vector register.

For xvaddsp, each element of the source vector VSRA is added to the corresponding element of the source vector VSRC, and the results are placed into the destination vector VSRD.

if MSR.VSX=0 then VSX_Unavailable()

ex_flag ←0b0
do i = 0 to 3
    reset_xflags()
    src1 ←bfp_CONVERT_FROM_BFP32(VSR[32×AX+A].word[i])
    src2 ←bfp_CONVERT_FROM_BFP32(VSR[32×BX+B].word[i])
    v    ←bfp_ADD(src1,src2)
    rnd  ←bfp_ROUND_TO_BFP32(FPSCR.RN,v)
    vresult.word[i] ←bfp32_CONVERT_FROM_BFP(rnd)

    if vxisi_flag=1 then SetFX(FPSCR.VXISI)
    if ox_flag=1 then SetFX(FPSCR.OX)
    if ux_flag=1 then SetFX(FPSCR.UX)
    if xx_flag=1 then SetFX(FPSCR.XX)

    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vxisi_flag) | (FPSCR.OE & ox_flag) | (FPSCR.UE & ux_flag) | (FPSCR.XE & xx_flag)
end

if ex_flag=0 then VSR[32×TX+T] ←vresult

The xvaddsp instruction is used for adding single-precision floating-point numbers in vector registers. Ensure that the VSX feature is enabled by checking and setting MSR.VSX. Be aware of potential exceptions such as invalid operations (VXISI), overflow (OX), underflow (UX), or inexact results (XX). These conditions can be checked using the FPSCR flags.


Summary: Subtracts the contents of two vector registers and places the result in another vector register.

For xvsubsp, each single-precision floating-point operand in word elements of VSR[XA] is negated and added to the corresponding element in VSR[XB]. The results are normalized and rounded to single precision before being placed into VSR[XT].

for i = 0 to 3 do
    src1 <- VSR[XA][i]
    src2 <- VSR[XB][i]
    if src1 is NaN or src2 is NaN then
        v <- Q(src1) or Q(src2)
        vxsnan_flag <- 1
    else if src1 is +Infinity and src2 is +Infinity then
        v <- +Infinity
        vxisi_flag <- 1
    else if src1 is -Infinity and src2 is -Infinity then
        v <- -Infinity
        vxisi_flag <- 1
    else if src1 is NZF and src2 is NZF then
        v <- S(src1, -src2)
    else if src1 is Zero and src2 is Zero then
        v <- Rezd
    else if src1 is +Zero and src2 is -Zero then
        v <- +Zero
    else if src1 is -Zero and src2 is +Zero then
        v <- -Zero
    else if src1 is NZF and src2 is Zero then
        v <- src1
    else if src1 is Zero and src2 is NZF then
        v <- -src2
    else if src1 is +Infinity and src2 is NZF then
        v <- +Infinity
    else if src1 is NZF and src2 is +Infinity then
        v <- -Infinity
    else if src1 is -Infinity and src2 is NZF then
        v <- -Infinity
    else if src1 is NZF and src2 is -Infinity then
        v <- +Infinity
    VSR[VX][i] <- v

The xvsubsp instruction performs element-wise subtraction of single-precision floating-point numbers in VSX registers. Be cautious with NaNs, infinities, and zeros as they can trigger special flags (vxsnan_flag, vxisi_flag) and may result in unexpected outcomes. Ensure that the input vectors are properly aligned to avoid alignment faults.


Summary: Multiplies the contents of two single-precision floating-point values and places the result into a vector register.

VSX Vector Multiply Single-Precision multiplies four single-precision floating-point elements from VSX registers XA and XB, storing the results in VSX register XT. This VSX category instruction processes four 32-bit elements in parallel and may update FPSCR with floating-point exception flags.

The xvmulsp instruction performs element-wise multiplication of single-precision floating-point values in vector registers. Ensure that the input vectors are properly aligned to avoid alignment faults. Be cautious with NaN and infinity handling, as they follow specific rules for propagation and sign determination. This instruction operates at user privilege level.


For xvdivsp, each element of the source vectors VSR[XA] and VSR[XB] is divided to produce a quotient that is placed into the corresponding element of the target vector VSR[XT].

if MSR.VSX=0 then VSX_Unavailable()

ex_flag ←0b0
do i = 0 to 3
    reset_xflags()
    src1 ←bfp_CONVERT_FROM_BFP32(VSR[32×AX+A].word[i])
    src2 ←bfp_CONVERT_FROM_BFP32(VSR[32×BX+B].word[i])
    v    ←bfp_DIVIDE(src1,src2)
    rnd  ←bfp_ROUND_TO_BFP32(FPSCR.RN,v)
    vresult.word[i] ←bfp32_CONVERT_FROM_BFP(rnd)
    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    if vxidi_flag=1 then SetFX(FPSCR.VXIDI)
    if vxisi_flag=1 then SetFX(FPSCR.VXZDZ)
    if ox_flag=1 then SetFX(FPSCR.OX)
    if ux_flag=1 then SetFX(FPSCR.UX)
    if xx_flag=1 then SetFX(FPSCR.XX)
    if zx_flag=1 then SetFX(FPSCR.ZX)

    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag)
                       | (FPSCR.VE & vxidi_flag)
                       | (FPSCR.VE & vxzdz_flag)
                       | (FPSCR.OE & ox_flag)
                       | (FPSCR.UE & ux_flag)
                       | (FPSCR.ZE & zx_flag)
                       | (FPSCR.XE & xx_flag)
end

if ex_flag=0 then VSR[32×TX+T] ←vresult

The xvdivsp instruction performs element-wise division of single-precision floating-point numbers in VSX vectors. Ensure that the VSX facility is enabled (MSR.VSX=1) to avoid exceptions. Handle potential exceptions by checking the FPSCR flags, especially VXSNAN, VXIDI, VXZDZ, OX, UX, ZX, and XX. Be cautious of alignment requirements for vector registers to maintain performance.


Summary: Computes absolute value for four single-precision floats.

VSX Vector Absolute Value Single-Precision computes the absolute value of four single-precision floating-point elements from VSX register XB, storing the results in VSX register XT. This VSX category instruction clears the sign bit of each 32-bit element and does not affect floating-point status flags.

The xvabssp instruction is used to compute the absolute value of each single-precision floating-point element in a vector register. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking and setting the appropriate bit in the MSR register. This instruction processes four elements per operation, so ensure your data is appropriately aligned for optimal performance.


Summary: Negates the contents of a single-precision floating-point register.

VSX Vector Negate Single-Precision negates four single-precision floating-point elements from VSX register XB, storing the results in VSX register XT. This VSX category instruction inverts the sign bit of each 32-bit element and does not affect floating-point status flags.

Use xvnegsp to negate each single-precision float in a VSX vector. Ensure vectors are properly aligned; misalignment can cause exceptions. This instruction operates at user privilege level.


Summary: Computes the square root of each single-precision floating-point element in a vector.

For xvsqrtsp, the unbounded-precision square root of each single-precision floating-point operand in word elements i of VSR[XB] is computed. The result is rounded to single precision using the rounding mode specified by RN and placed into word element i of VSR[XT].

if MSR.VSX=0 then VSX_Unavailable()
ex_flag ←0b0
do i = 0 to 3
    reset_xflags()
    src ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].word[i])
    v   ←bfp_SQUARE_ROOT(src)
    rnd ←bfp_ROUND_TO_BFP32(FPSCR.RN,v)
    vresult.word[i] ←bfp32_CONVERT_FROM_BFP(rnd)
    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    if vxsqrt_flag=1 then SetFX(FPSCR.VXSQRT)
    if xx_flag=1     then SetFX(FPSCR.XX)
    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vxsqrt_flag) | (FPSCR.XE & xx_flag)
end
if ex_flag=0 then VSR[32×TX+T] ←vresult

The xvsqrtsp instruction computes the square root of each single-precision floating-point element in a vector. Ensure that VSX is enabled (MSR.VSX=1) to avoid exceptions. Handle potential exceptions by checking FPSCR flags such as VXSNAN, VXSQRT, and XX. The instruction operates on 4 elements per vector register.


Summary: Computes the maximum of corresponding single-precision floating-point elements in two vector registers and stores the result in a third vector register.

For xvmaxsp, the instruction compares each element of the source vectors VSR[XA] and VSR[XB] and places the larger value into the corresponding element of the target vector VSR[XT].

for i = 0 to 3 do
    src1 <- VSR[XA][i]
    src2 <- VSR[XB][i]
    if isNaN(src1) or isNaN(src2) then
        fx(VXSNAN)
        T(Q(src2))
    else if isInfinity(src1) and isInfinity(src2) and sign(src1) != sign(src2) then
        fx(VXSNAN)
        T(Q(src2))
    else if isZero(src1) and isZero(src2) and sign(src1) != sign(src2) then
        fx(VXSNAN)
        T(Q(src2))
    else
        T(M(src1, src2))
    end if
end for

The xvmaxsp instruction compares each element of two source vectors and stores the larger value in the target vector. It handles NaNs by setting VXSNAN in the FPSCR and transferring the quiet NaN to the result. Be cautious with infinities and zeros of opposite signs, as they also trigger VXSNAN. Ensure that the vectors are properly aligned for optimal performance.


Summary: Performs a minimum operation on single-precision floating-point values from two vector scalar registers and stores the result in another vector scalar register.

VSX Vector Minimum Single-Precision compares four single-precision floating-point elements from VSX registers XA and XB element-wise, selecting the minimum value for each element and storing results in VSX register XT. This VSX category instruction processes four 32-bit elements in parallel and follows IEEE 754 minimum semantics.

The xvminsp instruction is commonly used for performing element-wise minimum comparisons on single-precision floating-point values in VSX registers. Ensure that the VSX facility is enabled by checking and setting the MSR.VSX bit. Be aware of the VXSNAN flag, which indicates a quiet NaN result; this can be checked via the FPSCR register. The instruction operates at the user privilege level and does not raise exceptions unless enabled through the FPSCR's VE (Invalid Operation Enable) bit.


VSX Vector Compare Equal Single-Precision

Summary: Compares each single-precision floating-point element of two VSX registers and sets the corresponding element in the target register to all 1s if they are equal, otherwise all 0s.

For xvcmpeqsp, each integer value i from 0 to 3, the single-precision floating-point operand in word element i of VSR[XA] is compared to the single-precision floating-point operand in word element i of VSR[XB]. The contents of word element i of VSR[XT] are set to all 1s if they are equal, and all 0s otherwise.

if MSR.VSX=0 then VSX_Unavailable()
ex_flag ←0b0
all_false ←0b1
all_true ←0b1
do i = 0 to 3
    reset_xflags()
    src1 ←bfp_CONVERT_FROM_BFP32(VSR[32×AX+A].word[i])
    src2 ←bfp_CONVERT_FROM_BFP32(VSR[32×BX+B].word[i])
    vxsnan_flag ←IsSNaN(src1) | IsSNaN(src2)
    if src1 = src2 then do
        all_false ←0b0
    end
    else do
        vresult.word[i] ←0x0000_0000
        all_true ←0b0
    end
    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag)
end
if Rc=1 then do
    if vex_flag=0 then
        CR.field[6] ←all_true || 0b0 || all_false || 0b0
    else
        CR.field[6] ←0bUUUU
end


VSX Vector Compare Greater Than Single-Precision

Summary: Compares each single-precision floating-point element in two vector registers and sets the corresponding element in a target vector register to all 1s if the first element is greater than the second, otherwise all 0s.

For xvcmpgtsp, each integer value i from 0 to 3, the single-precision floating-point operand in word element i of VSR[XA] is compared to the single-precision floating-point operand in word element i of VSR[XB]. The contents of word element i of VSR[XT] are set to all 1s if the first operand is greater than the second, and all 0s otherwise.

if MSR.VSX=0 then VSX_Unavailable()

ex_flag ←0b0
all_false ←0b1
all_true ←0b1
do i = 0 to 3
    reset_xflags()
    src1 ←bfp_CONVERT_FROM_BFP32(VSR[32×AX+A].word[i])
    src2 ←bfp_CONVERT_FROM_BFP32(VSR[32×BX+B].word[i])
    if IsSNaN(src1)=1 | IsSNaN(src2)=1 then do
        vxsnan_flag ←0b1
        if FPSCR.VE=0 then vxvc_flag ←0b1
    end
    else
        vxvc_flag ←src1.class.QNaN | src2.class.QNaN
    if src1 > src2 then do
        vresult.word[i] ←0xFFFF_FFFF
        all_false ←0b0
    end
    else
        vresult.word[i] ←0x0000_0000
        all_true ←0b0
    end
    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    if vxvc_flag=1 then SetFX(FPSCR.VXVC)
    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vxvc_flag)
end
if ex_flag=0 then VSR[32×TX+T] ←vresult
if Rc=1 then do
    if vex_flag=0 then
        CR.field[6] ←all_true || 0b0 || all_false || 0b0
    else
        CR.field[6] ←0bUUUU
end


VSX Vector Compare Greater or Equal Single-Precision

Summary: Compares each element of two single-precision floating-point vectors and sets the target vector elements to all 1s if the corresponding source elements are greater than or equal, otherwise all 0s.

For xvcmpgesp, each element of the single-precision floating-point vector in VSR[XA] is compared with the corresponding element in VSR[XB]. The result is stored in VSR[XT]. If Rc=1, CR field 6 is updated based on the comparison results.

if 'xvcmpgesp' then
    for each integer value i from 0 to 3 do
        src1 ← bfp_CONVERT_FROM_BFP32(VSR[32×AX+A].word[i])
        src2 ← bfp_CONVERT_FROM_BFP32(VSR[32×BX+B].word[i])
        if src1.class.SNaN | src2.class.SNaN then
            vxsnan_flag ← 0b1
            if FPSCR.VE=0 then vxvc_flag ← 0b1
        else vxvc_flag ← IsQNaN(src1) | IsQNaN(src2)
        if src1 >= src2 then
            vresult.word[i] ← 0xFFFF_FFFF
        else
            vresult.word[i] ← 0x0000_0000
        ex_flag ← ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vxvc_flag)
    end
    if ex_flag=0 then VSR[32×TX+T] ← vresult
    if Rc=1 then do
        CR.field[6] ← all_true || 0b0 || all_false || 0b0
    end


VSX Scalar Convert Double-Precision to Signed Doubleword with Round to Zero

Summary: Converts a double-precision floating-point value to a signed doubleword integer using round towards zero.

The instruction converts the double-precision floating-point value in doubleword element 0 of VSR[XB] to a signed doubleword integer. The result is placed into doubleword element 0 of VSR[XT], and doubleword element 1 of VSR[XT] is set to 0.

if src ≤ Nmin - 1 then
    T(Nmin)
    fr(0)
    fi(0)
    fx(VXCVI)
    if error() then invoke system error handler
else if Nmin - 1 < src < Nmin then
    T(Nmin)
    fr(0)
    fi(1)
    fx(XX)
    if error() then invoke system error handler
else if src = Nmin then
    T(Nmin)
    fr(0)
    fi(0)
else if Nmin < src < Nmax then
    T(f2i(trunc(src)))
    fr(0)
    fi(1)
    fx(XX)
    if error() then invoke system error handler
else if src = Nmax then
    T(Nmax)
    fr(0)
    fi(0)
else if Nmax < src < Nmax + 1 then
    T(Nmax)
    fr(0)
    fi(1)
    fx(XX)
    if error() then invoke system error handler
else if src ≥ Nmax + 1 then
    T(Nmin)
    fr(0)
    fi(0)
    fx(VXCVI)
    if error() then invoke system error handler
else if src is a QNaN then
    T(Nmin)
    fr(0)
    fi(0)
    fx(VXCVI)
    if error() then invoke system error handler
else if src is a SNaN then
    T(Nmin)
    fr(0)
    fi(0)
    fx(VXCVI)
    fx(VXSNAN)
    if error() then invoke system error handler

xscvdpsxds rounds using Round towards Zero rounding mode. For other rounding modes, software must use a Round to Double-Precision Integer instruction that corresponds to the desired rounding mode. Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.


VSX Scalar Convert Double-Precision to Unsigned Doubleword with Round to Zero

Summary: Converts a double-precision floating-point value to an unsigned 64-bit integer using round towards zero.

The instruction converts the double-precision floating-point value in doubleword element 0 of VSR[XB] to an unsigned 64-bit integer. The result is placed into doubleword element 0 of VSR[XT], and doubleword element 1 of VSR[XT] is set to 0.

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src ← bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
rnd ← bfp_ROUND_TO_INTEGER(0b001, src)
result ← ui64_CONVERT_FROM_BFP(rnd)
vxsnan_flag ← vxsnan(src)
vxcvi_flag ← vxcvi(src)
xx_flag ← xx(src)
vx_flag ← vxsnan_flag | vxcvi_flag
vex_flag ← FPSCR.VE & vx_flag
if vex_flag=0 then
do
    VSR[32×TX+T].dword[1] ← result
    VSR[32×TX+T].dword[2] ← 0x0000_0000_0000_0000
    FPSCR.FPRF ← 0bUUUUU
    FPSCR.FR ← inc_flag
    FPSCR.FI ← xx_flag
end
else
do
    FPSCR.FR ← 0b0
    FPSCR.FI ← 0b0
end

FPSCR (undefined), VXSNAN, VXCVI, FX, XX

If src is a NaN, the result is 0x0000_0000_0000_0000 and VXCVI is set to 1. If src is an SNaN, VXSNAN is also set to 1. If the rounded value is greater than 264 -1, the result is 0xFFFF_FFFF_FFFF_FFFF and VXCVI is set to 1. Otherwise, if the rounded value is less than 0, the result is 0x0000_0000_0000_0000 and VXCVI is set to 1. Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.


Vector Scalar Convert Single-Precision to Double-Precision format Non-signalling

Summary: Converts a single-precision floating-point value in VSR[XB] to double-precision format and places the result into VSR[XT].

Converts a single-precision floating-point value in the lower 32 bits of VSR[XB] to double-precision format and places the result in VSR[XT]. This is a scalar VSX instruction that operates on element 0 of the VSR. The instruction does not signal on NaN or other exceptional floating-point conditions.

xscvspdp can be used to convert a single-precision value in single-precision format to double-precision format for use by Floating-Point scalar single-precision operations. Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.


VSX Scalar Convert Double-Precision to Single-Precision

Summary: Converts a double-precision floating-point value in VSR[XB] to single-precision format and places the result into VSR[XT].

The instruction converts the double-precision floating-point value from word element 0 of VSR[XB] to single-precision format. The result is placed into word elements 0 and 1 of VSR[XT], with word elements 2 and 3 set to zero.

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src ← bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
rnd ← bfp_ROUND_TO_BFP32(FPSCR.RN, src)
result ← bfp32_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if xx_flag=1 then SetFX(FPSCR.XX)
if ox_flag=1 then SetFX(FPSCR.OX)
if ux_flag=1 then SetFX(FPSCR.UX)
vex_flag ← FPSCR.VE & vxsnan_flag
if vex_flag=0 then do
    VSR[32×TX+T].word[0] ← result
    VSR[32×TX+T].word[1] ← result
    VSR[32×TX+T].word[2] ← 0x0000_0000
    VSR[32×TX+T].word[3] ← 0x0000_0000
    FPSCR.FPRF ← fprf_CLASS_BFP32(result)
    FPSCR.FR ← inc_flag
    FPSCR.FI ← xx_flag
end else do
    FPSCR.FI ← 0b0
end

This instruction can be used to operate on a single-precision source operand. Previous versions of the architecture allowed the contents of words 1, 2, and 3 of the result register to be undefined, however, all processors that support this instruction write the result into both words 0 and 1 of the result register, as is required by this version of the architecture. If src is a SNaN, the result is src converted to a QNaN (i.e., bit 12 of src is set to 1). VXSNAN is set to 1.


Vector Convert Double-Precision to Single-Precision

Summary: Converts double-precision floating-point values in a vector to single-precision format.

Converts two double-precision floating-point values in VSR[XB] to single-precision format and places the results in VSR[XT]. The two double-precision elements (0 and 1) are converted and packed into the single-precision elements (0 and 1) of the target. Rounding is performed according to the current rounding mode in FPSCR.

VSR[XT].element[0] ← ConvertDP_to_SP(VSR[XB].element[0])
VSR[XT].element[1] ← ConvertDP_to_SP(VSR[XB].element[1])

Previous versions of the architecture allowed the contents of bits 32:63 of each doubleword in the result register to be undefined, however, all processors that support this instruction write the result into bits 32:63 of each doubleword in the result register as well as into bits 0:31, as is required by this version of the architecture. Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.


Summary: Converts two floats to two doubles.

Converts two single-precision floating-point values in VSR[XB] to double-precision format and places the results in VSR[XT]. The single-precision elements (0 and 1) are expanded to double-precision elements (0 and 1). No rounding is required for this widening conversion.

VSR[XT].element[0] ← ConvertSP_to_DP(VSR[XB].element[0])
VSR[XT].element[1] ← ConvertSP_to_DP(VSR[XB].element[1])

The xvcvspdp instruction is used to convert a vector of single-precision floating-point values to double-precision. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register, otherwise, an exception will be raised. Handle special cases like signaling NaNs by checking and setting the appropriate flags in FPSCR.


VSX Vector Convert Double-Precision to Signed Doubleword for- mat XX2-form

Summary: Converts a double-precision floating-point value to a signed doubleword integer, rounding according to the current rounding mode.

Converts two double-precision floating-point values in VSR[XB] to signed 64-bit integer format (doubleword) and places the results in VSR[XT]. Rounding is performed according to the current rounding mode in FPSCR. On overflow or invalid operation, the result is saturated to the maximum or minimum signed 64-bit integer.

VSR[XT].element[0] ← ConvertDP_to_SXD_Round(VSR[XB].element[0], RoundMode)
VSR[XT].element[1] ← ConvertDP_to_SXD_Round(VSR[XB].element[1], RoundMode)

xvcvdpsxds rounds using Round towards Zero rounding mode. For other rounding modes, software must use a Round to Double-Precision Integer instruction that corresponds to the desired rounding mode.


Vector Convert Double-Precision to Unsigned Doubleword with Round to Zero

Summary: Converts double-precision floating-point values in a vector to unsigned doublewords using round towards zero.

This instruction converts each element of the source vector (VSR[XB]) from double-precision floating-point format to an unsigned 64-bit integer, rounding towards zero. The result is stored in the corresponding element of the target vector (VSR[XT]). If any element results in a NaN or SNaN, VXSNAN and VXCVI are set accordingly.

for i = 0 to 1 do
    src <- VSR[XB][i]
    if src is a QNaN then
        T(Nmin), fx(VXCVI)
        if FPSCR.VXCVI=0 and MSR.FE0!=ignore-exception-mode then error()
    else if src is a SNaN then
        T(Nmin), fx(VXCVI), fx(VXSNAN)
        if FPSCR.VXSNAN=0 and MSR.FE1!=ignore-exception-mode then error()
    else if src ≤ Nmin-1 then
        T(Nmin), fx(VXCVI)
        if FPSCR.VXCVI=0 and MSR.FE0!=ignore-exception-mode then error()
    else if Nmin-1 < src < Nmin then
        if FPSCR.VE=0 then
            T(Nmin), fx(XX)
            if FPSCR.XX=0 and MSR.FE1!=ignore-exception-mode then error()
        else
            fx(XX), error()
    else if src = Nmin then
        T(Nmin)
    else if Nmin < src < Nmax then
        if FPSCR.VE=0 then
            T(f2i(trunc(src))), fx(XX)
            if FPSCR.XX=0 and MSR.FE1!=ignore-exception-mode then error()
        else
            fx(XX), error()
    else if src = Nmax then
        T(Nmax)
    else if Nmax < src < Nmax+1 then
        if FPSCR.VE=0 then
            T(Nmax), fx(XX)
            if FPSCR.XX=0 and MSR.FE1!=ignore-exception-mode then error()
        else
            fx(XX), error()
    else if src ≥ Nmax+1 then
        T(Nmin), fx(VXCVI)
        if FPSCR.VXCVI=0 and MSR.FE0!=ignore-exception-mode then error()
    end if
end for

xvcvdpuxds rounds using Round towards Zero rounding mode. For other rounding modes, software must use a Round to Double-Precision Integer instruction that corresponds to the desired rounding mode.


Vector Convert with round to zero Single-Precision to Signed Doubleword format XX2-form

Summary: Converts single-precision floating-point values in a vector to signed doublewords, rounding towards zero.

Converts single-precision floating-point values in VSR[XB] to signed 64-bit integer format (doubleword) and places the results in VSR[XT], rounding towards zero (truncation). Only the first two single-precision elements are converted; results are placed in the two doubleword elements of the target.

VSR[XT].element[0] ← ConvertSP_to_SXD_Truncate(VSR[XB].element[0])
VSR[XT].element[1] ← ConvertSP_to_SXD_Truncate(VSR[XB].element[1])

xvcvspsxds rounds using Round towards Zero rounding mode. For other rounding modes, software must use a Round to Single-Precision Integer instruction that corresponds to the desired rounding mode, including xvrspic which uses the rounding mode specified by RN.


VSX Vector Convert with round Signed Word to Single-Precision format

Summary: Converts a signed integer in each word of the source vector to single-precision floating-point and rounds it.

For xvcvsxwsp, each word element of VSR[XB] is converted from a signed integer to an unbounded-precision floating-point value, rounded to single-precision using the rounding mode specified by RN, and placed into the corresponding word element of VSR[XT].

if MSR.VSX=0 then VSX_Unavailable()

ex_flag ←0b0

do i = 0 to 3
    reset_xflags()

    src ←bfp_CONVERT_FROM_SI32(VSR[32×BX+B].word[i])
    rnd ←bfp_ROUND_TO_BFP32(FPSCR.RN,src)

    vresult.word[i] ←bfp32_CONVERT_FROM_BFP(rnd)

    if xx_flag=1 then SetFX(FPSCR.XX)
    ex_flag ←ex_flag | (FPSCR.XE & xx_flag)
end

if ex_flag=0 then VSR[32×TX+T] ←vresult

This instruction is commonly used for converting signed integer values to single-precision floating-point numbers in vector operations. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking and setting MSR.VSX if necessary. Be aware of rounding modes specified by FPSCR.RN, as they can affect the precision of the conversion. Handle exceptions properly by checking FPSCR.XX and FPSCR.XE after execution.


VSX Vector Convert Unsigned Word to Single

Summary: Converts four 32-bit unsigned integers to four floats.

Converts four 32-bit unsigned integer values in VSR[XB] to four single-precision floating-point results and places them in VSR[XT]. Each unsigned word element is converted to the corresponding single-precision element. Rounding is performed according to the current rounding mode in FPSCR.

VSR[XT].element[0] ← ConvertUW_to_SP(VSR[XB].element[0])
VSR[XT].element[1] ← ConvertUW_to_SP(VSR[XB].element[1])
VSR[XT].element[2] ← ConvertUW_to_SP(VSR[XB].element[2])
VSR[XT].element[3] ← ConvertUW_to_SP(VSR[XB].element[3])

This instruction is commonly used for converting unsigned integer data to floating-point format in vector operations. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking and setting MSR.VSX before using this instruction. Be aware of potential exceptions during conversion, as no results will be written to the target register if any trap-enabled exception occurs. The rounding mode is determined by FPSCR.RN, so ensure it's set appropriately for your application.


Summary: Spatially duplicates a 32-bit immediate into all 4 words of the target.

Duplicates a 32-bit immediate value into all four 32-bit word elements of VSR[XT]. This is a VSX vector splat immediate instruction that fills the entire 128-bit register with copies of the 32-bit immediate. No floating-point status updates occur.

imm32 ← sign_extend(IMM)
VSR[XT].element[0] ← imm32
VSR[XT].element[1] ← imm32
VSR[XT].element[2] ← imm32
VSR[XT].element[3] ← imm32

The xxspltiw instruction is commonly used to initialize a VSX vector with a repeated immediate word value. Ensure that the 'imm' field is within the valid range of a 32-bit signed integer to avoid unexpected behavior. This instruction operates at user privilege level and does not generate exceptions under normal circumstances.


VSX Vector Splat Immediate Double-Precision

Summary: Spatially duplicates a 32-bit immediate (converted to double) into both double elements.

The instruction splats the double-precision value formed by concatenating imm0 and imm1 into each doubleword element of VSR[XT].

if MSR.VSX=0 then VSX_Unavailable()
IMM32 ←imm0<<16 | imm1
VSR[32×TX+T].dword[0] ←bfp64_CONVERT_FROM_BFP(IMM32)
VSR[32×TX+T].dword[1] ←bfp64_CONVERT_FROM_BFP(IMM32)

This instruction is used to replicate a double-precision floating-point value across all elements of a VSX vector register. Ensure that the VSX facility is enabled in the MSR register; otherwise, it will raise an exception. The immediate values imm0 and imm1 are concatenated to form a 32-bit integer, which is then converted to a double-precision float and replicated across the vector. Be cautious of alignment requirements for the target vector register.


Summary: Merges high doublewords from XA and XB.

Merges the two high-order doubleword elements from VSR[XA] and VSR[XB] into VSR[XT]. Element 0 of XA is placed in element 0 of XT, and element 0 of XB is placed in element 1 of XT. This is a vector permutation instruction with no floating-point status updates.

VSR[XT].element[0] ← VSR[XA].element[0]
VSR[XT].element[1] ← VSR[XB].element[0]

The xxmrghd instruction is used to merge the high doublewords from two source vector registers into a target vector register. Ensure that the VSX facility is enabled by checking and setting the appropriate bit in the MSR register. Be cautious with the DM bits, as they determine which source doubleword is merged into the target register. This instruction operates at the user privilege level and will raise an exception if the VSX facility is not available.


Summary: Merges low doublewords from XA and XB.

Merges the low (rightmost) doubleword from XA and the low doubleword from XB into the target register XT, placing XA's low doubleword in the high position and XB's low doubleword in the low position. This is a VSX instruction that operates on 128-bit vector registers and does not affect any condition or status flags.

The xxmrgld instruction is used to merge the low doublewords of two VSX registers into a target register. Ensure that the VSX facility is enabled by checking and setting the appropriate bit in the MSR register. Be cautious with the DM bits as they determine which doubleword from the source registers is placed into the target register's second doubleword position.


Summary: Swaps the two doublewords in the register.

Swaps the two doublewords within the XB register and stores the result in XT. The high doubleword becomes the low doubleword and vice versa. This is a VSX instruction that does not affect condition or status flags.

The xxswapd instruction swaps doubleword elements between two VSX registers based on the DM bit setting. Ensure that the VSX facility is enabled in the MSR register to avoid a VSX_Unavailable exception. This instruction operates at user privilege level and does not require specific alignment of data.


Summary: Selects elements from two source vectors based on a mask vector.

Selects bits from XA or XB for each bit position based on the corresponding bit in the mask register XC. Where XC has a 1 bit, the result takes the bit from XA; where XC has a 0 bit, the result takes the bit from XB. This is a VSX instruction with no effect on condition or status flags.

for i in 0 to 127 do
  if XC[i] = 1 then
    XT[i] ← XA[i]
  else
    XT[i] ← XB[i]

The xxsel instruction is commonly used for conditional vector selection based on a mask. Ensure that the VSX feature is enabled in the MSR register to avoid an exception. The source and destination vectors must be properly aligned, typically requiring 16-byte alignment for optimal performance.


Summary: Bitwise OR.

Performs a bitwise logical OR of the contents of XA and XB, storing the result in XT. This is a VSX instruction that does not affect condition or status flags.

The xxlor instruction is used to perform a bitwise OR operation on two VSX registers. Ensure that the VSX facility is enabled by checking and setting the MSR.VSX bit; otherwise, a VSX_Unavailable exception will be raised. This instruction operates on 128-bit vectors and requires proper alignment of the input and output registers.


Summary: Bitwise XOR.

Performs a bitwise logical XOR of the contents of XA and XB, storing the result in XT. This is a VSX instruction that does not affect condition or status flags.

The xxlxor instruction requires the VSX facility to be enabled; otherwise, it will raise an exception. Ensure that the VSX bit in the MSR register is set before using this instruction. The operation is performed on 128-bit vector registers, so ensure proper alignment and that the input registers contain valid data for accurate results.


Summary: Performs a bitwise AND operation on the contents of two vector registers and stores the result in another vector register.

The contents of VSR[XA] are ANDed with the contents of VSR[XB] and the result is placed into VSR[XT].

if MSR.VSX=0 then VSX_Unavailable()
VSR[32×TX+T] ← VSR[32×AX+A] & VSR[32×BX+B]

Ensure that the VSX (Vector Scalar Extensions) is enabled in the MSR register before using this instruction. The operation is performed on 128-bit vector registers, so both input and output must be properly aligned. This instruction operates at a high performance for bitwise operations on vectors.


Summary: Performs a logical NOR operation on the contents of two VSX registers and stores the result in another VSX register.

The contents of VSR[XA] are ORed with the contents of VSR[XB], then the complemented result is placed into VSR[XT].

if MSR.VSX=0 then
    VSX_Unavailable()
XT <- ¬(XA | XB)

The xxlnor instruction performs a logical NOR operation between two vector registers and stores the result in another. Ensure that the VSX (Vector Scalar Extensions) is enabled by checking and setting the MSR.VSX bit; otherwise, handle the VSX_Unavailable exception. This instruction operates on 128-bit vectors and requires proper alignment of the input and output registers.


Summary: Multiplies the 1st and 3rd words of the source vectors to produce two 64-bit results.

Multiplies the unsigned 32-bit words at positions 1 and 3 of vA by the corresponding words in vB, producing two unsigned 64-bit results stored in vD. This is a VMX (AltiVec) instruction that does not affect condition or status flags.

This instruction is useful for performing element-wise multiplication of unsigned integers stored in odd-numbered positions of two vectors. Ensure that the input vectors are properly aligned to avoid alignment faults. The result is a vector with doubleword elements, so be mindful of potential overflow if the product exceeds 64 bits.


Summary: Multiplies odd words (1,3) to 64-bit signed result.

Multiplies the signed 32-bit words at positions 1 and 3 of vA by the corresponding words in vB, producing two signed 64-bit results stored in vD. This is a VMX (AltiVec) instruction that does not affect condition or status flags.

The vmulosw instruction is used for multiplying signed integers located in the odd word elements of two vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The result is stored in doubleword elements of the destination register, and developers should handle potential overflow by checking the sign extension of the products.


Summary: Multiplies the even-numbered words of two vector registers and places the results in a destination vector register.

For vmuleuw, each pair of even-numbered words from VSR[VRA+32] and VSR[VRB+32] are multiplied, and the results are placed into VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    src1 ←EXTZ(VSR[VRA+32].word[2×i])
    src2 ←EXTZ(VSR[VRB+32].word[2×i])
    VSR[VRT+32].dword[i] ←CHOP64(src1 × src2)
end

This instruction multiplies even-numbered words from two vector registers and stores the results in another register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. Be cautious of overflow, as the multiplication result is truncated to 64 bits before storage.


Summary: Multiplies even-indexed signed words from two vector registers and stores the results in a destination vector register.

For vmulesw, each pair of even-indexed signed words from VSR[VRA+32] and VSR[VRB+32] are multiplied, and the 64-bit products are stored in VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    src1 ←EXTS(VSR[VRA+32].word[2×i])
    src2 ←EXTS(VSR[VRB+32].word[2×i])
    VSR[VRT+32].dword[i] ←CHOP64(src1 × src2)
end

This instruction multiplies even-indexed signed words from two vector registers and stores the 64-bit products in another register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. Be cautious of overflow, as the multiplication results are truncated to 64 bits.


Vector Multiply-Sum Unsigned Byte Modulo

Summary: Multiplies bytes and sums adjacent results into words.

Multiplies each unsigned byte in vA by the corresponding byte in vB, then sums the products of adjacent byte pairs to produce four unsigned 32-bit word results. The results are added to the four words in the accumulator vC and stored in vD. This is a VMX (AltiVec) instruction that does not affect condition or status flags.

This instruction is commonly used for performing efficient vectorized operations on unsigned byte data. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation processes 8 bytes per iteration, multiplying corresponding elements and adding to the third source vector's word element, storing the result in the destination vector. Be cautious of overflow as only the low-order 16 bits are stored.


Vector Multiply-Sum Signed Halfword Modulo

Summary: Multiplies halfwords and sums adjacent results into words.

Multiplies four pairs of signed halfword elements from vA and vB, then sums the adjacent pairs of products modulo 2^32 and adds the corresponding word element from vC (accumulator), storing the result in vD. This instruction operates on Classic VMX (AltiVec) and does not set any condition flags.

for i in 0 to 1 do
  prod_hi ← vA[i*2] × vB[i*2]
  prod_lo ← vA[i*2+1] × vB[i*2+1]
  vD[i] ← (prod_hi + prod_lo + vC[i]) mod 2^32
endfor

This instruction is useful for performing vectorized multiply-sum operations on signed halfwords, ensuring results are within the range of a 16-bit signed integer by applying modulo arithmetic. Ensure that input vectors and accumulator are properly aligned to avoid performance penalties. This operation does not require any special privileges but can generate exceptions if input data exceeds expected ranges.


Vector Multiply-Sum Signed Halfword Saturate

Summary: Performs a vector multiply-sum operation on signed halfwords and saturates the result.

For vmsumshs, each element in VRA and VRB is multiplied by corresponding elements in VRC. The results are summed and saturated if necessary.

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    temp ←EXTS(VSR[VRC+32].word[i])
    do j = 0 to 1
        src1 ←EXTS(VSR[VRA+32].word[i].hword[j])
        src2 ←EXTS(VSR[VRB+32].word[i].hword[j])
        temp ←temp + (src1 × src2)
    end
    VSR[VRT+32].word[i] ←si32_CLAMP(temp)
    VSCR.SAT ←sat_flag
end

vmsumshs is used for vectorized operations involving signed halfword multiplication and summation. Ensure that the Vector Status and Control Register (VSCR) is properly managed, especially when handling saturation flags. This instruction operates at the user privilege level and will raise an exception if the vector facility is not enabled in the Machine State Register (MSR).


Vector Sum-across Partial (1/4) Unsigned Byte Saturate

Summary: Sums the unsigned byte elements of two vector registers and saturates the result.

For vsum4ubs, the sum of the unsigned integer values in the four byte elements contained in each word element of VSR[VRA+32] is added to the unsigned integer value in the corresponding word element of VSR[VRB+32]. If the intermediate result exceeds 2^32 - 1, it saturates to 2^32 - 1 and sets the SAT flag.

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    temp ← EXTZ(VSR[VRB+32].word[i])
    do j = 0 to 3
        temp ← temp + EXTZ(VSR[VRA+32].word[i].byte[j])
    end
    VSR[VRT+32].word[i] ← ui32_CLAMP(temp)
    VSCR.SAT ← sat_flag
end

vsum4ubs is commonly used for accumulating sums of byte elements within vector registers, with saturation to prevent overflow. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation processes four bytes per word, and results are clamped to 32-bit unsigned integers, setting the VSCR.SAT flag if saturation occurs.


Vector Sum-across Partial (1/4) Signed Byte Saturate

Summary: Adds the contents of four signed byte elements from two vector registers and saturates the result.

For vsum4sbs, the sum of the signed integer values in the four byte elements contained in word element i of VSR[VRA+32] is added to the signed integer value in word element i of VSR[VRB+32]. If the intermediate result is greater than 2^31-1 or less than -2^31, the result saturates and SAT is set to 1.

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    temp ←EXTS(VSR[VRB+32].word[i])
    do j = 0 to 3
        temp ←temp + EXTS(VSR[VRA+32].word[i].byte[j])
    end
    VSR[VRT+32].word[i] ←si32_CLAMP(temp)
    VSCR.SAT ←sat_flag
end

vsum4sbs is useful for accumulating sums of byte elements within words, with saturation handling. Ensure vectors are properly aligned and check VSCR.SAT after execution to handle overflow cases. This instruction operates at the user privilege level.


Vector Sum-across Partial (1/4) Signed Halfword Saturate

Summary: Sums every 2 halfwords into a word.

Sums pairs of signed halfword elements from vA and accumulates into words in vB (accumulator), storing saturated results in vD. The instruction processes 2 halfword pairs per word, setting the saturation bit (VSCR[SAT]) if any result overflows. This is a Classic VMX (AltiVec) instruction.

for i in 0 to 3 do
  sum ← vA[i*2] + vA[i*2+1] + vB[i]
  vD[i] ← SATURATE_SIGNED_WORD(sum)
  if overflow then VSCR[SAT] ← 1
endfor

The vsum4shs instruction is commonly used for performing saturated addition of signed halfwords within vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. Be cautious with saturation handling as it can affect the results if intermediate sums exceed 32-bit integer limits.


Vector Sum-across Partial (1/2) Signed Word Saturate

Summary: Adds the contents of two vector registers and updates the saturation flag.

Sums pairs of signed word elements from vA and accumulates into doublewords conceptually, storing the lower 32 bits of saturated results in alternating word positions of vD. The instruction sets the saturation bit (VSCR[SAT]) if any result overflows a signed 32-bit word. This is a Classic VMX (AltiVec) instruction.

for i in 0 to 1 do
  sum ← sign_extend_64(vA[i*2]) + sign_extend_64(vA[i*2+1]) + sign_extend_64(vB[i*2])
  vD[i*2] ← SATURATE_SIGNED_WORD(sum)
  if overflow then VSCR[SAT] ← 1
endfor

This instruction is useful for performing saturated addition of word elements in vector registers. Ensure that the VSCR.SAT flag is checked after execution to handle saturation cases. The instruction operates on 32-bit signed integers and requires the vector facility to be enabled (MSR.VEC=1).


Summary: Adds the contents of four word elements of one vector register to a single word element of another vector register and saturates the result.

The sum of the signed integer values in the four word elements of VSR[VRA+32] is added to the signed integer value in the word element 3 of VSR[VRB+32]. The low-order 32 bits of the result are placed into word element 3 of VSR[VRT+32], and the high-order 96 bits are set to zero. If the intermediate result is greater than 2^31 - 1, it saturates to 2^31 - 1; if less than -2^31, it saturates to -2^31.

if MSR.VEC=0 then
    Vector_Unavailable()
temp ←EXTS(VSR[VRB+32].word[3])
do i = 0 to 3
    temp ←temp + EXTS(VSR[VRA+32].word[i])
end
VSR[VRT+32].word[0] ←0x0000_0000
VSR[VRT+32].word[1] ←0x0000_0000
VSR[VRT+32].word[2] ←0x0000_0000
VSR[VRT+32].word[3] ←si32_CLAMP(temp)
VSCR.SAT ←sat_flag

This instruction is useful for accumulating sums of signed integers with saturation, preventing overflow. Ensure that the vector registers are properly aligned and that the VEC bit in the MSR is set to 1. Be aware of the saturation behavior; if the sum exceeds the 32-bit signed integer range, it will be clamped to the maximum or minimum value. The result is stored only in the fourth word element of the destination register, with the other elements zeroed out.


Summary: Adds the contents of two vector registers and places the result in another vector register.

For vaddfp, each element of the source vectors VRA and VRB is added to produce corresponding elements in the destination vector VRT.

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ← VSR[VRA+32].word[i]
    src2 ← VSR[VRB+32].word[i]
    VSR[VRT+32].word[i] ← bfp32_ADD(src1,src2)
end

The vaddfp instruction adds corresponding elements of two source vectors and stores the results in a destination vector. Ensure that the Vector Facility is enabled by setting MSR.VEC to 1; otherwise, a Vector_Unavailable exception will be raised. This instruction operates on single-precision floating-point numbers and processes four elements per operation.


Summary: Subtracts four single-precision floats (Classic VMX).

Subtracts four single-precision floating-point elements in vB from the corresponding elements in vA, storing the IEEE 754 results in vD. No condition flags are set by this instruction. This is a Classic VMX (AltiVec) floating-point operation.

for i in 0 to 3 do
  vD[i] ← vA[i] - vB[i]  (IEEE 754 single precision)
endfor

The vsubfp instruction is used for vectorized subtraction of single-precision floating-point numbers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation processes four elements at a time, so ensure that the input vectors are properly aligned and contain valid floating-point data to avoid unexpected results.


Vector Convert to Unsigned Fixed-Point Word Saturate

Summary: Converts 4 floats to 4 unsigned 32-bit integers.

Converts four single-precision floating-point elements in vB to unsigned 32-bit fixed-point integers with UIM fractional bits, saturating to the unsigned 32-bit range and storing results in vD. Sets the saturation bit (VSCR[SAT]) if any conversion saturates. This is a Classic VMX (AltiVec) instruction.

scale ← 2^UIM
for i in 0 to 3 do
  converted ← round(vB[i] × scale)
  vD[i] ← SATURATE_UNSIGNED_WORD(converted)
  if saturated then VSCR[SAT] ← 1
endfor

The vctuxs instruction converts floating-point elements to unsigned fixed-point words with saturation. Ensure the vector facility is enabled by checking and setting MSR.VEC. Handle exceptions for invalid operations or overflow carefully. The conversion respects the rounding mode specified by UIM, so verify its configuration for accurate results.


Vector Convert to Signed Fixed-Point Word Saturate

Summary: Converts a vector of floating-point values to signed fixed-point integers with rounding towards zero and saturation.

For vctsxs, each element in the source vector VRB is converted to a signed fixed-point integer using the specified scale factor UIM. The result is saturated if it exceeds the range of a 32-bit signed integer.

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src ← VSR[VRB+32].word[i]
    VSR[VRT+32].word[i] ← si32_CONVERT_FROM_BFP32(src, UIM)
end

The vctsxs instruction converts each element of the source vector to a signed fixed-point integer using the specified scale factor. Ensure that the scale factor is appropriate for your data range to avoid saturation. This instruction operates at user privilege level and will raise an exception if the VEC bit in the MSR register is not set.


Vector Convert from Unsigned Fixed-Point Word

Summary: Converts 4 unsigned 32-bit integers to floats.

Converts four unsigned 32-bit fixed-point integers in vB (with UIM fractional bits) to single-precision floating-point elements, storing IEEE 754 results in vD. No saturation or condition flags are set. This is a Classic VMX (AltiVec) instruction.

scale ← 2^(-UIM)
for i in 0 to 3 do
  vD[i] ← unsigned_word_to_float(vB[i]) × scale  (IEEE 754)
endfor

The vcfux instruction is used for converting signed floating-point values to unsigned fixed-point integers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. Be cautious of saturation when results exceed 2^32 - 1.


Vector Convert from Signed Fixed-Point Word to Single-Precision Floating-Point

Summary: Converts signed fixed-point values in a vector register to single-precision floating-point values.

For vcfsx, each word element of the source vector register VRB is converted to a nearest single-precision floating-point value and divided by 2^UIM. The results are stored in the corresponding word elements of the target vector register VRT.

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src ← VSR[VRB+32].word[i]
    VSR[VRT+32].word[i] ← bfp32_CONVERT_FROM_SI32(src, UIM)
end

The fixed-point integers used by the Vector Convert instructions can be interpreted as consisting of 32-UIM integer bits followed by UIM fraction bits.


Vector Round to Floating-Point Integer towards Minus Infinity

Summary: Rounds each element of a vector toward negative infinity.

For vrfim, each single-precision floating-point value in the elements of VSR[VRB+32] is rounded toward negative infinity and placed into the corresponding elements of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src ← VSR[VRB+32].word[i]
    VSR[VRT+32].word[i] ← bfp32_ROUND_TO_INTEGER_FLOOR(src)
end

This instruction rounds each single-precision floating-point value in the source vector towards negative infinity. Ensure that the Vector Facility is enabled by checking and setting the appropriate bit in the MSR register. Be cautious of potential exceptions if the input values are out of range for integer representation.


Vector Round to Floating-Point Integer Nearest

Summary: Rounds 4 floats to nearest integer.

Rounds four single-precision floating-point elements in vB to the nearest integer value (using round-to-nearest-even), storing IEEE 754 results in vD. No condition flags are set. This is a Classic VMX (AltiVec) instruction.

for i in 0 to 3 do
  vD[i] ← round_nearest_even(vB[i])  (IEEE 754 single precision)
endfor

The vrfin instruction is commonly used for rounding floating-point numbers in vector operations. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. Be aware of potential precision loss when rounding to integers, especially with ties. This instruction operates on 32-bit floating-point elements and requires proper alignment for optimal performance.


Vector Round to Floating-Point Integer towards Plus Infinity

Summary: Rounds each element of a vector to the nearest integer towards positive infinity.

For vrfip, each single-precision floating-point value in VSR[VRB+32] is rounded towards positive infinity and placed into the corresponding word element of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src ← VSR[VRB+32].word[i]
    VSR[VRT+32].word[i] ← bfp32_ROUND_TO_INTEGER_CEIL(src)
end

This instruction rounds each single-precision floating-point value in the source vector towards positive infinity. Ensure that the Vector Facility is enabled by checking and setting the appropriate bit in the MSR register. Be cautious of potential overflow when rounding very large numbers.


Vector Round to Floating-Point Integer towards Zero

Summary: Rounds 4 floats to integer (trunc).

Rounds each of four 32-bit floating-point elements in vB towards zero (truncate) and stores the integer results as floating-point values in vD. This instruction operates on the VMX/AltiVec extension and does not modify condition registers or exception flags.

for i in 0 to 3:
  vD[32*i:32*i+31] ← RoundTowardZero(vB[32*i:32*i+31])

The vrfiz instruction rounds each single-precision floating-point value in the source vector towards zero. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on 32-bit words, so ensure proper alignment of the data for optimal performance.


Summary: Compares the elements of two vector registers for equality and stores the result in a third vector register.

For vcmpeqfp, each element of VSR[VRA+32] is compared to the corresponding element of VSR[VRB+32]. If they are equal, the corresponding element of VSR[VRT+32] is set to all 1s; otherwise, it is set to all 0s.

if MSR.VEC=0 then
    Vector_Unavailable()
all_true ←1
all_false ←1
do i = 0 to 3
    src1 ←VSR[VRA+32].word[i]
    src2 ←VSR[VRB+32].word[i]
    if bool_COMPARE_EQ_BFP32(src1,src2)=1 then
        VSR[VRT+32].word[i] ←0xFFFF_FFFF
        all_false ←0
    else
        VSR[VRT+32].word[i] ←0x0000_0000
        all_true ←0
end
if Rc=1 then
    CR.field[6] ←all_true || 0b0 || all_false || 0b0

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.


Vector Compare Greater Than Floating-Point

Summary: Compares the contents of two vector registers and sets the target vector register based on whether each element is greater than the corresponding element in the other vector.

For vcmpgtfp, the contents of VSR[VRA+32] are compared to the contents of VSR[VRB+32]. The result is stored in VSR[VRT+32], with each word set to all 1s if the corresponding element in VSR[VRA+32] is greater than that in VSR[VRB+32], and all 0s otherwise.

if MSR.VEC=0 then
    Vector_Unavailable()
all_true ←1
all_false ←1
do i = 0 to 3
    src1 ←VSR[VRA+32].word[i]
    src2 ←VSR[VRB+32].word[i]
    if bool_COMPARE_GT_BFP32(src1,src2)=1 then
        VSR[VRT+32].word[i] ←0xFFFF_FFFF
        all_false ←0
    else
        all_true ←0
        VSR[VRT+32].word[i] ←0x0000_0000
end
if Rc=1 then
    CR.field[6] ←all_true || 0b0 || all_false || 0b0


Vector Compare Greater Equal Floating-Point

Summary: Compares 4 floats (A >= B).

Compares each of four 32-bit floating-point elements: vA >= vB. For each element, stores all 1s (0xFFFFFFFF) if the condition is true, or all 0s if false, into the corresponding word of vD. This instruction operates on VMX/AltiVec and does not modify the condition register.

This instruction is commonly used for element-wise comparison of single-precision floating-point numbers in vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The result of each comparison is stored as 0xFFFFFFFF if true or 0x0000_0000 if false in the target VSR. If Rc=1, CR Field 6 is updated to reflect whether all comparisons were true, all were false, or a mix of both.


Summary: Compares two VSRs word element by word and sets the target VSR if Rc=1.

Performs a bounds check comparing each of four 32-bit floating-point elements in VRA against the range defined by two bounds in VRB. The result is stored in VRT as a 4-bit value per element indicating which bound(s) the value violates. When the Rc bit is set (vcmpbfp.), the CR6 field is updated based on the result.

Each single-precision floating-point value in VSR[VRB+32] should be non-negative; if it is negative, the corresponding element in VSR[VRA+32] will necessarily be out of bounds. One exception to this is when the value of an element in VSR[VRB+32] is -0.0 and the value of the corresponding element in VSR[VRA+32] is either +0.0 or -0.0. +0.0 and -0.0 compare equal to -0.0.


Summary: Packs the contents of two vector registers into a single vector register, with each source word being considered as a 32-bit pixel and each target halfword as a 16-bit pixel.

For vpkpx, the contents of VSR[VRA+32] and VSR[VRB+32] are concatenated to form a single vector. Each word element from this concatenated vector is then packed into a halfword element in VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
let vsrc be the concatenation of the contents of VSR[VRA+32] followed by the contents of VSR[VRB+32].
do i = 0 to 7
    VSR[VRT+32].hword[i].bit[0] ← vsrc.word[i].bit[7]
    VSR[VRT+32].hword[i].bit[1:5] ← vsrc.word[i].bit[8:12]
    VSR[VRT+32].hword[i].bit[6:10] ← vsrc.word[i].bit[16:20]
    VSR[VRT+32].hword[i].bit[11:15] ← vsrc.word[i].bit[24:28]

Each source word can be considered to be a 32-bit 'pixel', consisting of four 8-bit 'channels'. Each target halfword can be considered to be a 16-bit pixel, consisting of one 1-bit channel and three 5-bit channels.


Summary: Unpacks high 4 pixels to 4 words.

Unpacks the four high-order pixel values (each 8 bits) from vB into four 32-bit word elements in vD, expanding each pixel into a word with implicit format expansion. This VMX/AltiVec instruction is commonly used in graphics processing and does not affect status registers.

for i in 0 to 3:
  pixel ← vB[8*(i+4):8*(i+4)+7]
  vD[32*i:32*i+31] ← ExpandPixel(pixel)

The vupkhpx instruction is used to unpack the high halfwords of a vector register into bytes, sign-extending the most significant bit and zero-extending the remaining bits. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. This operation is useful for processing pixel data where each pixel requires byte-level manipulation.


Summary: Unpacks low 4 pixels to 4 words.

Unpacks the four low-order pixel values (each 8 bits) from vB into four 32-bit word elements in vD, expanding each pixel into a word with implicit format expansion. This VMX/AltiVec instruction is commonly used in graphics processing and does not affect status registers.

for i in 0 to 3:
  pixel ← vB[8*i:8*i+7]
  vD[32*i:32*i+31] ← ExpandPixel(pixel)

The vupklpx instruction is used to unpack the low halfwords of a vector register into bytes, sign-extending the first bit and zero-extending the remaining bits. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. This instruction operates on 128-bit vector registers and processes each halfword in the source register to produce four bytes per iteration.


Summary: Bitwise byte shuffle similar to vperm but for little-endian access optimization.

Performs a byte permutation by selecting bytes from the concatenation of vA and vB using indices from vC, optimized for little-endian access patterns. This VMX/AltiVec instruction rearranges 16 bytes across the three source registers and stores the result in vD, with no impact on condition registers.

The vpermr instruction is used to perform a right permutation on the elements of a vector register. It is commonly used in scenarios where data needs to be shifted or rotated within a vector for operations like cryptography, signal processing, or custom algorithms. Ensure that the input vector is properly aligned and that the operation does not exceed the bounds of the vector register to avoid undefined behavior. This instruction operates at user privilege level and may raise exceptions if the alignment requirements are not met.

src ← vA || vB
for i in 0 to 15:
  index ← vC[4*i:4*i+3]
  vD[8*i:8*i+7] ← src[8*index:8*index+7]


Summary: Performs GF(2) polynomial arithmetic (Carryless Multiply) on bytes.

For vpmsumb, each byte element in VSR[VRA+32] is multiplied by each byte element in VSR[VRB+32], and the results are summed. The final result is stored in VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 15
    prod[i].bit[0:14] ←0
    srcA ←VSR[VRA+32].byte[i]
    srcB ←VSR[VRB+32].byte[i]
    do j = 0 to 7
        do k = 0 to j
            gbit ←srcA.bit[k] & srcB.bit[j-k]
            prod[i].bit[j] ←prod[i].bit[j] ⊕gbit
        end
    end
    do j = 8 to 14
        do k = j-7 to 7
            gbit ←(srcA.bit[k] & srcB.bit[j-k])
            prod[i].bit[j] ←prod[i].bit[j] ⊕gbit
        end
    end
end
do i = 0 to 7
    VSR[VRT+32].hword[i] ←0b0 || (prod[2×i] ⊕prod[2×i+1])
end

The vpmsumb instruction performs a polynomial multiplication and summation on byte elements of vector registers. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on 16-byte vectors, so input and output vectors must be properly aligned. Be cautious with handling overflow as the result is truncated to fit into the destination register.


Summary: Performs GF(2) polynomial arithmetic on halfwords.

Performs GF(2) polynomial multiplication on pairs of 16-bit halfword elements from vA and vB, accumulating the results into vD. This VMX/AltiVec instruction is used in cryptographic and polynomial arithmetic operations and does not modify condition registers or exception status.

The vpmsumh instruction is commonly used for finite field arithmetic operations, particularly in cryptographic algorithms. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. Be cautious of alignment requirements; source vectors must be aligned to halfword boundaries. This instruction operates at a privilege level where vector operations are supported, typically user or supervisor mode. Exception conditions include a Vector Unavailable exception if the facility is not enabled.


Summary: Performs a polynomial multiply-sum operation on word elements of two vector registers and stores the result in another vector register.

Performs GF(2) polynomial multiplication on pairs of 32-bit word elements from vA and vB, accumulating the results into vD. This instruction is part of the Vector Crypto extension and is essential for cryptographic operations such as CRC and GHASH computation. No condition registers or exception flags are modified.

The vpmsumw instruction is used for polynomial multiplication of word elements in vector registers. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on 128-bit vectors, processing four 32-bit words each. Be cautious with alignment; input vectors must be properly aligned to avoid undefined behavior. The result is a 64-bit word for each pair of input words, XORed together and stored in the destination vector. Exception conditions include invalid use of registers or disabled Vector Facility.


Vector Polynomial Multiply-Sum Doubleword

Summary: Performs GF(2) polynomial arithmetic on doublewords.

Performs Galois Field GF(2) polynomial multiplication and summation on doubleword elements. The instruction multiplies corresponding doubleword elements from vA and vB using polynomial arithmetic over GF(2), accumulating partial products into the destination register vD. This instruction is part of the Vector Crypto extension and does not affect CR0 or condition registers.

The vpmsumd instruction is commonly used for performing polynomial multiplication and summation operations on large datasets efficiently. Ensure that the input vectors are properly aligned to doubleword boundaries to avoid alignment faults. This instruction operates at user privilege level, but care must be taken to handle potential overflow conditions in the sum results. Performance can be optimized by ensuring that the data is loaded into vector registers before executing vpmsumd.


Summary: Loads a 128-bit vector from memory (VSX aligned offset).

For lxv, the contents of the quadword in storage at address EA are placed into load_data. The order of bytes depends on the endianness (Big-Endian or Little-Endian). load_data is then placed into VSR[XT].

if 'lxv' & TX=0 & MSR.VSX=0 then VSX_Unavailable()
if 'lxv' & TX=1 & MSR.VEC=0 then Vector_Unavailable()
EA ←(RA|0) + EXTS64(DQ||0b0000)
VSR[32×TX+T] ←MEM(EA,16)

The lxv instruction loads a 16-byte vector from memory into a VSX register. Ensure the address is properly aligned to avoid alignment faults. Check that the appropriate privilege levels (MSR.VSX for VSX operations and MSR.VEC for vector operations) are enabled before executing this instruction.


Summary: Stores a 128-bit vector to memory (VSX aligned offset).

For stxv, the contents of VSR[XS] are stored into memory at the effective address (EA), which is the sum of the contents of GPR[RA] and the value DQ sign-extended to 64 bits. If RA=0, EA is set to 0.

if 'stxv' & SX=0 & MSR.VSX=0 then VSX_Unavailable()
if 'stxv' & SX=1 & MSR.VEC=0 then Vector_Unavailable()
EA ← (RA|0) + EXTS64(DQ||0b0000)
MEM(EA,16) ← VSR[32×SX+S]

The stxv instruction stores a VSX vector from the VSR register to memory. Ensure that the VSX or Vector facility is enabled in the MSR register based on the SX field value. The effective address (EA) is calculated by adding the contents of GPR[RA] and the sign-extended DQ value. If RA is 0, EA defaults to 0. This instruction operates at user privilege level unless otherwise specified.


Load VSX Vector Doubleword and Splat Indexed

Summary: Loads a doubleword from memory and splats it into two elements of a VSX vector register.

Loads a doubleword from memory at the address computed from RA+RB and splats it across two doubleword elements in the VSX vector register XT. The effective address is formed by adding the contents of RA (or 0 if RA=0) and RB. The 64-bit value is replicated into both elements of the 128-bit VSX register. This VSX extension instruction does not affect condition registers.

EA ← (RA = 0) ? RB : RA + RB
doubleword ← [EA]
XT[0:63] ← doubleword
XT[64:127] ← doubleword

The lxvdsx instruction is commonly used to load a doubleword from memory and replicate it across both elements of a VSX vector register. Ensure that the VSX facility is enabled (MSR.VSX=1) to avoid exceptions. The effective address must be aligned to an 8-byte boundary for optimal performance, although unaligned accesses are supported with potential performance penalties.


Summary: Loads four words into a vector (unaligned).

The contents of the byte in storage at address EA+4×i+3 are placed into byte element 3 of load_data. When Little-Endian byte ordering is employed, the contents of the word in storage at address EA+4×i are placed into word element i of VSR[XT] in such an order that; if MSR.VSX=0 then VSX_Unavailable(). EA ←((RA=0) ? 0 : GPR[RA]) + GPR[RB]. Let XT be the value 32×TX + T. Let EA be the sum of the contents of GPR[RA], or 0 if RA is equal to 0, and the contents of GPR[RB]. For each integer value i from 0 to 3, do the following.

if MSR.VSX=0 then
    VSX_Unavailable()
EA ←((RA=0) ? 0 : GPR[RA]) + GPR[RB]
for i from 0 to 3 do
    VSR[32×TX+T].word[i] ←MEM(EA+4×i, 4)

lxvd2x, lxvw4x, lxvh8x, lxvb16x, and lxvx exhibit identical behavior in Big-Endian mode.


Summary: Stores four words from a vector (unaligned).

Stores four 32-bit word elements from a VSX vector register XS into memory at an unaligned address computed as RA+RB. The effective address is calculated by adding RA (or 0 if RA=0) and RB, and the four words from the source register are written to consecutive memory locations. This VSX extension instruction does not affect condition registers and permits unaligned access.

stxvd2x, stxvw4x, stxvh8x, stxvb16x, and stxvx exhibit identical behavior in Big-Endian mode.


Load VSX Scalar as Integer Word Algebraic Indexed

Summary: Loads a word from memory into the left-most doubleword element of a VSR, sign-extends it to 64 bits, and aligns it.

Loads a 32-bit signed integer word from memory at address RA+RB into the left-most doubleword element of VSX register XT, with the value sign-extended to 64 bits. The effective address is computed by adding RA (or 0 if RA=0) and RB. The loaded and sign-extended value occupies bits 0-63 of the VSX register, leaving the right element undefined. This VSX extension instruction does not affect condition registers.

EA ← (RA = 0) ? RB : RA + RB
word ← [EA:EA+3]
XT[0:63] ← sign_extend(word, 64)
XT[64:127] ← undefined

The lxsiwax instruction is commonly used to load a 32-bit integer from memory into the left-most doubleword of a VSX register, with sign extension. Ensure that the VSX facility is enabled in the MSR register; otherwise, a VSX_Unavailable exception will be raised. The effective address (EA) must be properly calculated and aligned to a word boundary for optimal performance and correct data loading.


Load VSX Scalar as Integer Word Zero Indexed

Summary: Loads a word from memory and places it into the specified VSX register, zero-extending it.

Loads a 32-bit unsigned integer word from memory at address RA+RB into the left-most doubleword element of VSX register XT, with the value zero-extended to 64 bits. The effective address is computed by adding RA (or 0 if RA=0) and RB. The loaded and zero-extended value occupies bits 0-63 of the VSX register. This VSX extension instruction does not affect condition registers.

EA ← (RA = 0) ? RB : RA + RB
word ← [EA:EA+3]
XT[0:63] ← zero_extend(word, 64)
XT[64:127] ← undefined

The lxsiwzx instruction is commonly used to load a word from memory into a VSX register, ensuring zero-extension. Ensure that the VSX facility is enabled in the MSR register; otherwise, a VSX_Unavailable exception will be raised. The address calculation respects the base and offset registers, with RA being optional (use 0 if not needed). This instruction does not require any specific alignment but must be executed at a privilege level where VSX operations are permitted.


Store VSX Scalar as Integer Word Indexed

Summary: Stores a single-precision floating-point value from a VSX register into memory, indexed by another register.

Stores the low-order 32 bits from the left-most doubleword element of VSX register XS into memory at the address computed as RA+RB. The effective address is formed by adding RA (or 0 if RA=0) and RB. The 32-bit word from XS[32:63] is written to the memory location. This VSX extension instruction does not affect condition registers.

The stxsiwx instruction stores the second word of a VSX register into memory. Ensure that the VSX facility is enabled in the MSR register to avoid exceptions. The effective address is calculated from two GPRs, so ensure proper alignment and bounds checking to prevent memory access errors.


Summary: Moves the contents of a doubleword element from a Vector-Scalar Register (VSR) to a General Purpose Register (GPR).

The contents of doubleword element 0 of VSR[XS] are placed into GPR[RA]. For SX=0, mfvsrd is treated as a Floating-Point instruction in terms of resource availability. For SX=1, mfvsrd is treated as a Vector instruction in terms of resource availability.

if SX=0 & MSR.FP=0 then FP_Unavailable()
if SX=1 & MSR.VEC=0 then Vector_Unavailable()
GPR[RA] ← VSR[32×SX+S].dword[0]


Summary: Moves 64 bits from a GPR to a VSR.

Moves a 64-bit value from general-purpose register RA into the left-most doubleword element of VSX register XT. The entire 64-bit content of RA is copied to bits 0-63 of the target VSX register; the right doubleword element (bits 64-127) is left undefined. This VSX extension instruction does not affect condition registers.

The mtvsrd instruction is commonly used to transfer data from a general-purpose register to the first doubleword of a vector-scalar register. Ensure that the appropriate privilege level (FP or VEC) is enabled in the MSR register, otherwise, an exception will be raised. Note that the second doubleword of the VSR is zeroed out during this operation.


Summary: Moves the contents of a word element from a vector-scalar register to a general-purpose register, zeroing the upper bits.

The contents of word element 1 of VSR[XS] are placed into bits 32:63 of GPR[RA]. The contents of bits 0:31 of GPR[RA] are set to 0. Let XS be the value 32×SX + S.

if SX=0 & MSR.FP=0 then FP_Unavailable()
if SX=1 & MSR.VEC=0 then Vector_Unavailable()
GPR[RA] ←EXTZ64(VSR[32×SX+S].word[1])

For SX=0, mfvsrwz is treated as a Floating-Point instruction in terms of resource availability.
For SX=1, mfvsrwz is treated as a Vector instruction in terms of resource availability.


Summary: Moves the two's-complement integer in bits 32:63 of GPR[RA] to doubleword element 0 of VSR[XT], sign-extended to 64 bits.

The two’s-complement integer in bits 32:63 of GPR[RA] is sign-extended to 64 bits and placed into doubleword element 0 of VSR[XT]. The contents of doubleword element 1 of VSR[XT] are undefined.

if TX=0 & MSR.FP=0 then FP_Unavailable()
if TX=1 & MSR.VEC=0 then Vector_Unavailable()
VSR[32×TX+T].dword[0] ←EXTS64(GPR[RA].bit[32:63])
VSR[32×TX+T].dword[1] ←0xUUUU_UUUU_UUUU_UUUU

For TX=0, mtvsrwa is treated as a Floating-Point instruction in terms of resource availability.
For TX=1, mtvsrwa is treated as a Vector instruction in terms of resource availability.


Summary: Compares two registers as signed integers and records the result in the specified Condition Register Field.

Compare r3 vs r4 (32-bit signed), result in cr7.

The fixed-point Compare instructions compare the contents of register RA with either the sign-extended value of the SI field, the zero-extended value of the UI field, or the contents of register RB. The comparison is signed for cmpi and cmp, and unsigned for cmpli and cmpl. The L field determines whether the operands are treated as 32-bit or 64-bit quantities.

The cmp instruction is commonly used for signed comparisons between two registers. Ensure that the operands are correctly aligned and consider the L field to specify whether the comparison should be performed on 32-bit or 64-bit values. The result of the comparison updates the Condition Register (CR), so always check CR[BF] after executing cmp to determine the outcome.


Summary: Compares the contents of register RA with a sign-extended immediate value.

if L = 0 then a ←EXTS((RA)32:63)
else a ←(RA)
if      a < EXTS(SI) then c ←0b100
else if a > EXTS(SI) then c ←0b010
else                      c ←0b001
CR4×BF+32:4×BF+35 ←c || XERSO

The contents of register RA ((RA)32:63 sign-extended to 64 bits if L=0) are compared with the sign-extended value of the SI field, treating the operands as signed integers. The result of the comparison is placed into CR field BF.

The cmpi instruction is commonly used for signed integer comparisons where one operand is an immediate value. Be cautious with the alignment of the register RA, as incorrect alignment can lead to unexpected results. This instruction operates at user privilege level and does not generate exceptions under normal circumstances.


Summary: Compares two registers as unsigned integers.

if L = 0 then
  a ← zero_extend(RA[32:63], 64)
  b ← zero_extend(RB[32:63], 64)
else
  a ← RA
  b ← RB
if a < b then
  CR[BF] ← 0b100 || SO
elseif a > b then
  CR[BF] ← 0b010 || SO
else
  CR[BF] ← 0b001 || SO

Performs an unsigned logical comparison between RA and RB, with L determining the operand size (L=0 for 32-bit, L=1 for 64-bit). The comparison result is written to condition register field BF. The comparison sets the LT, GT, or EQ bits in the target CR field based on whether RA is less than, greater than, or equal to RB when interpreted as unsigned integers. This Base category instruction affects only the specified condition register field, not CR0.

Use cmpl for unsigned comparisons. Ensure registers RA and RB are properly aligned if they contain pointers or data structures. The instruction modifies the Condition Register (CR), so check the appropriate field after execution to determine the result of the comparison.


Summary: Compares the contents of a register with an immediate value and updates the condition register.

if L = 0 then a ←320 || (RA)32:63
else a ←(RA)
if      a <u (480 || UI) then c ←0b100
else if a >u (480 || UI) then c ←0b010
else                         c ←0b001
CR4×BF+32:4×BF+35 ←c || XERSO

The contents of register RA ((RA)32:63 zero-extended to 64 bits if L=0) are compared with 480 || UI, treating the operands as unsigned integers. The result of the comparison is placed into CR field BF.

The cmpli instruction is commonly used for unsigned integer comparisons where one operand is an immediate value. Be cautious with the zero-extension behavior when L=0, as it can lead to unexpected results if not accounted for. This instruction operates at user privilege level and does not generate exceptions under normal circumstances.


Summary: Counts the number of consecutive 0 bits starting from bit 32 (MSB of the low word).

n ← 0
while n < 32 and RS[n] = 0 do n ← n + 1
RA ← n
if Rc = 1 then CR0 ← (RA = 0, RA < 0, RA > 0, SO)

r3 = Leading Zeros in lower 32-bits of r4.

Counts the number of consecutive zero bits from the MSB (bit 0) of the 32-bit word in RS and stores the result in RA. The count ranges from 0 to 32. If Rc=1, CR0 is updated based on the result.

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.


Summary: Counts the number of consecutive 0 bits starting from bit 0 (MSB of 64-bit reg).

n ← 0
while n < 64 and RS[n] = 0 do n ← n + 1
RT ← n
if Rc = 1 then CR0 ← (RT = 0, RT < 0, RT > 0, SO)

Counts the number of consecutive zero bits from the MSB (bit 0) of the 64-bit doubleword in RS and stores the result in RT. The count ranges from 0 to 64. If Rc=1, CR0 is updated based on the result.


Summary: Performs a bitwise AND between two bits in the Condition Register.

The bit in the Condition Register specified by BA+32 is ANDed with the bit in the Condition Register specified by BB+32, and the result is placed into the bit in the Condition Register specified by BT+32.

The crand instruction performs a bitwise AND operation on specific bits of the Condition Register (CR). It's commonly used to combine condition flags from different operations. Ensure that the BA, BB, and BT fields are correctly set to avoid unintended results. This instruction operates at user privilege level.


Summary: Performs a bitwise OR between two bits in the Condition Register.

Performs a bitwise OR of CR bit BA and CR bit BB, storing the result in CR bit BT. This instruction operates only on the Condition Register and is commonly used in conditional branch sequences.

The cror instruction is commonly used to combine condition flags from different parts of the Condition Register (CR) for conditional branching or logical operations. Ensure that the BA, BB, and BT fields correctly specify the bits you intend to OR; otherwise, it may lead to incorrect results. This instruction operates at user privilege level and does not generate exceptions under normal circumstances.


Summary: Performs a bitwise XOR between two bits in the Condition Register. Used to clear CR bits (crxor x,x,x).

Performs a bitwise XOR of CR bit BA and CR bit BB, storing the result in CR bit BT. When BA and BB are the same bit, this effectively clears CR[BT]; this form is frequently used for clearing condition register fields.

The crxor instruction is used to perform a bitwise XOR operation between two condition register bits and store the result in another condition register bit. Ensure that the BA, BB, and BT fields are correctly set to avoid unintended behavior. This instruction operates at the problem state privilege level.


Summary: Unconditionally branches to a target address relative to the current instruction pointer.

LI

24-bit Signed Immediate (Displacement / 4)

if AA then
    NIA ←iea EXTS(LI || 0b00)
else
    NIA ←iea CIA + EXTS(LI || 0b00)
if LK then
    LR ←iea CIA + 4

The branch target address is the sum of LI || 0b00 sign-extended and the address of this instruction, with the high-order 32 bits of the branch target address set to 0 in 32-bit mode.

The b instruction is used for unconditional branching. The AA and LK fields control whether the address is absolute or relative and whether to link back to the current instruction.


Summary: Unconditionally branches to an absolute address.

NIA ← (LI || 0b00)
if LK = 1 then LR ← CIA + 4

Unconditionally branches to an absolute address formed by sign-extending the 24-bit immediate LI and shifting left by 2 bits. The Link Register is not modified unless LK=1. This instruction does not check any condition bits.

When LK=1, the address of the next sequential instruction is placed in LR, making this a subroutine call. Use blr to return.


Summary: Branches to a target address and saves the return address (CIA + 4) in the Link Register (LR). Used for function calls.

if AA = 0 then NIA ← CIA + (LI || 0b00) else NIA ← (LI || 0b00)
LR ← CIA + 4

Branches to a target address calculated from the 24-bit signed immediate and saves the return address (CIA + 4) in the Link Register (LR). The AA bit determines whether the address is absolute or relative. This is the standard instruction for subroutine calls.

The bl instruction is commonly used for function calls where a return to the caller is required. Ensure that the target address is correctly calculated and aligned, as misalignment can lead to exceptions. The link register (LR) must be preserved if nested subroutine calls are made to maintain correct return paths.


Summary: Branches conditionally based on the Count Register (CTR) and/or a bit in the Condition Register (CR).

ctr_ok ← (BO[2] = 1) | (CTR ≠ 0 ⊕ BO[3])
if BO[2] = 0 then CTR ← CTR - 1
cr_ok ← (BO[0] = 1) | (CR[BI] = BO[1])
if ctr_ok & cr_ok then
  if AA = 0 then NIA ← CIA + (BD || 0b00) else NIA ← (BD || 0b00)
if LK = 1 then LR ← CIA + 4

Branches conditionally based on the state of the Count Register (CTR) and/or a bit in the Condition Register (CR), as controlled by the BO field. The AA field determines absolute vs. relative addressing; LK=1 saves the return address in LR. This is the fundamental conditional branch instruction.

The bc instruction branches to a target address based on the condition bits in the Condition Register (CR). Ensure that the branch condition and target address are correctly set. The instruction operates at user privilege level, but care must be taken with conditional logic to avoid unintended execution paths.


Summary: Branches to the address in the Link Register (LR) if the condition is met. Used for function returns.

ctr_ok ← (BO[2] = 1) | (CTR ≠ 0 ⊕ BO[3])
if BO[2] = 0 then CTR ← CTR - 1
cr_ok ← (BO[0] = 1) | (CR[BI] = BO[1])
if ctr_ok & cr_ok then NIA ← LR[0:61] || 0b00
if LK = 1 then LR ← CIA + 4

Branches to the address in the Link Register (LR) if the condition specified by BO and BI is satisfied. The CTR is decremented if BO[2]=0. If LK=1, the return address (CIA + 4) is saved in LR, enabling exception-safe subroutine returns. The BH field provides a branch prediction hint to the processor.

bclr, bclrl, bcctr, and bcctrl each serve as both a basic and an extended mnemonic. The Assembler will recognize a bclr, bclrl, bcctr, or bcctrl mnemonic with three operands as the basic form, and a bclr, bclrl, bcctr, or bcctrl mnemonic with two operands as the extended form. In the extended form the BH operand is omitted and assumed to be 0b00.


Summary: Branches to the address in the Count Register (CTR) if the condition is met. Used for computed jumps and switch statements.

if (BO[0] = 0) then CTR ← CTR - 1; ctr_ok ← (BO[2] ∨ (CTR ≠ 0)); cond_ok ← (BO[4] ∨ (CR[BI] = BO[3])); if (ctr_ok ∧ cond_ok) then NIA ← CTR[0:61]; if (LK = 1) then LR ← CIA + 4;

Conditionally branches to the address in the Count Register based on the Branch Options (BO) field and the state of the condition register bit selected by BI. The link register is optionally updated if LK=1. This instruction is commonly used for computed jumps and indirect branches in switch statements and virtual function calls.

When LK=1, the address of the next sequential instruction is placed in LR, making this a subroutine call. Use blr to return.
CTR is decremented before the branch condition is tested; the branch is taken only if the combined CTR-and-condition test passes. Do not use this instruction inside a loop that also modifies CTR.