Summary: Extracts the biased exponent of a DFP operand in FRB and places it into FRT.

The biased exponent of the operand in FRB is extracted and placed into FRT in the 64-bit signed binary integer format. Special codes are returned for infinity, QNaN, or SNaN operands.

if 'dxex' then
    a <- biased exponent of FRB[p]
    if a > MBE1 then
        FRT[p] <- QNaNSNaN
    else if 0 ≤a ≤MBE then
        FRT[p] <- Finite number with biased exponent a
    else if a = -1 then
        FRT[p] <- Infinity
    else if a = -2 then
        FRT[p] <- QNaN
    else if a = -3 then
        FRT[p] <- SNaN
    else if a < -3 then
        FRT[p] <- QNaN

The exponent bias value is 101 for DFP Short, 398 for DFP Long, and 6176 for DFP Extended.


Decimal Shift Coefficient Left Immediate

Summary: Shifts the significand of a DFP operand left by a specified number of digits.

The significand of the DFP operand in FRA is shifted left SH digits. For NaN or infinity, all significand digits are in the trailing significand field. SH is a 6-bit unsigned binary integer. Digits shifted out of the leftmost digit are lost. Zeros are supplied to the vacated positions on the right. The result is placed into FRT. The sign of the result is the same as the sign of the source operand in FRA.

The dscli instruction shifts the significand of a decimal floating-point number to the left by a specified number of digits. Ensure that the shift amount (SH) is within the 0-63 range, as it's a 6-bit unsigned integer. This operation does not affect the sign or exponent of the operand. If SH is greater than the precision of the significand, leading zeros will be introduced to fill the vacated positions on the right.


Decimal Shift Coefficient Right Immediate

Summary: Shifts the coefficient of a DFP number right.

Shifts the coefficient of a 64-bit Decimal Floating-Point number right by an immediate amount (0-63 places), with zeros shifted in from the left. The exponent remains unchanged. This instruction is part of the Decimal Floating-Point extension and does not affect condition registers unless Rc=1.

coefficient ← coefficient >> SH
FRT ← DFP_construct(sign, exponent, coefficient)


Summary: Subtracts the contents of two quad-precision floating-point registers and handles special cases like NaNs.

Subtracts the quad-precision floating-point operand in VSR VRB from VSR VRA and stores the result in VSR VRT, handling infinities, NaNs, and denormalised numbers according to IEEE 754 semantics. This VSX instruction may update FPSCR exception flags and the result sign. The 'o' suffix variant enables underflow/overflow exception.

FRT ← FRA - FRB
FPSCR ← updated with exception flags (XX, ZX, UX, OX, VXISI, VXSNAN, etc.)

FPSCR FPRF FR FI FX VXSNAN VXISI OX UX XX

The xssubqp instruction is used for subtracting quad-precision floating-point numbers. Ensure that the VSX feature is enabled in the MSR register to avoid exceptions. Handle special cases like NaNs and infinities by checking the FPSCR flags after execution. The result is rounded according to the rounding mode specified in FPSCR.RN.


Summary: Divides the contents of two quad-precision floating-point registers and places the result in another register.

Divides the quad-precision floating-point operand in VSR vA by the quad-precision operand in VSR vB, placing the quotient in VSR vD, with IEEE 754 rounding and exception handling. This VSX instruction updates FPSCR flags including division-by-zero, invalid operation, and underflow/overflow conditions.

vD ← vA ÷ vB
FPSCR ← updated with exception flags (ZX, XX, UX, OX, VXSNAN, VXIDI, VXDZ, etc.)

FPSCR, VXSNAN, VXIDI, VXZDZ, OX, UX, ZX, XX

The xsdivqp instruction is used for dividing two quad-precision floating-point numbers. Be cautious of division by zero, which results in infinity or quiet NaN, and set appropriate flags. Handle infinities and zeros carefully as they can lead to special cases like zero or infinity in the result. Ensure that operands are correctly aligned and consider performance implications when using this instruction in loops.


Summary: Computes the square root of a quad-precision floating-point value with unbounded significand precision and exponent range.

The normalized square root of src is produced with unbounded significand precision and exponent range. If RO=1, the rounding mode is Round to Odd; otherwise, it is specified by RN.

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src ← bfp_CONVERT_FROM_BFP128(VSR[VRB+32])
v ← bfp_SQUARE_ROOT(src)
rnd ← bfp_ROUND_TO_BFP128(RO, FPSCR.RN, v)
result ← bfp128_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vxsqrt_flag=1 then SetFX(FPSCR.VXSQRT)
if xx_flag=1 then SetFX(FPSCR.XX)
vx_flag ← vxsnan_flag | vxsqrt_flag
vex_flag ← FPSCR.VE & vx_flag
if vex_flag=0 then do
  VSR[VRT+32] ← result
  FPSCR.FPRF ← fprf_CLASS_BFP128(result)
end
FPSCR.FR ← (vx_flag=0) & inc_flag
FPSCR.FI ← (vx_flag=0) & xx_flag

The xssqrtqp instruction computes the square root of a quad-precision floating-point number. Ensure that VSX is enabled in the MSR register to avoid exceptions. Be cautious with rounding modes; setting RO=1 enables Round to Odd, which may differ from standard rounding behaviors. This instruction handles special cases like NaNs and infinities, updating the FPSCR accordingly.


VSX Scalar Compare Unordered Quad-Precision

Summary: Compares two quad-precision floating-point values and updates the condition register.

The instruction compares the contents of VSR[VRA+32] (src1) and VSR[VRB+32] (src2) in quad-precision format. It sets bits in the CR field BF to indicate the result of the comparison.

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src1 ←bfp_CONVERT_FROM_BFP128(VSR[VRA+32])
src2 ←bfp_CONVERT_FROM_BFP128(VSR[VRB+32])
vxsnan_flag ←src1.class.SNaN | src2.class.SNaN
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
CR.bit[4×BF+32] ←FPSCR.FL ←src1 < src2
CR.bit[4×BF+33] ←FPSCR.FG ←src1 > src2
CR.bit[4×BF+34] ←FPSCR.FE ←src1 = src2
CR.bit[4×BF+35] ←FPSCR.FU ←src1.class.SNaN | src1.class.QNaN | src2.class.SNaN | src2.class.QNaN

This instruction is used for comparing two quad-precision floating-point numbers. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. Be cautious with NaN values, as they can trigger VXSNAN and FU flags in the FPSCR register. The comparison results are stored in the CR register bits corresponding to BF.


VSX Scalar Compare Ordered Quad-Precision

Summary: Compares Quad floats (Signaling on NaN).

Compares two quad-precision floating-point values in VSRs vA and vB, signaling (raising exception) if either operand is a quiet NaN, and stores the comparison result (Less Than, Greater Than, Equal, or Unordered) in condition register field BF. The FPSCR VE flag may be set on NaN detection.

if (vA is NaN) or (vB is NaN) then FPSCR[VXSNAN] ← 1
if vA < vB then CR[BF] ← 0b100
else if vA > vB then CR[BF] ← 0b010
else if vA = vB then CR[BF] ← 0b001
else CR[BF] ← 0b011 (unordered)


Summary: Negates a 128-bit Quad float.

Negates the sign bit of a 128-bit quad-precision floating-point value in VSR vB and stores the result in VSR vD. This is a simple bit-flip operation that does not affect FPSCR exception flags or condition registers.

This instruction is used to negate a quad-precision floating-point value. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking and setting the appropriate bit in the MSR register. The operation affects two consecutive doublewords, so ensure proper alignment of the source register.


Summary: Computes the absolute value of a quad-precision floating-point number.

Computes the absolute value of a 128-bit quad-precision floating-point number in VSR vB by clearing the sign bit and stores the result in VSR vD. This VSX instruction does not modify FPSCR exception flags or condition registers.

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.


Summary: Inserts a 32-bit word from a GPR into a specific element of a VSR.

Inserts a 32-bit word from GPR RB into a specified 32-bit element of VSR XT, with the element index selected by UIM[2:0]. This is a VSX instruction that operates on vector data and does not affect condition registers or status fields.

element_index ← UIM[2:0]
XT[32*element_index : 32*element_index+31] ← RB[32:63]

The xxinsertw instruction is used to insert a word from one vector register into another at a specified byte offset. Ensure that the UIM (Upper Immediate) field does not exceed 12 to avoid undefined behavior. This instruction requires VSX (Vector Scalar Extensions) to be enabled in the MSR.VSX bit; otherwise, it will raise an exception.


Summary: Extracts an unsigned word from a vector register and places it into another vector register.

The instruction extracts the contents of byte elements UIM:UIM+3 from VSR[XB] and places them into word element 1 of VSR[XT]. The remaining byte elements of VSR[XT] are not modified, and the remaining word elements of VSR[XT] are set to 0.

if MSR.VSX=0 then
    VSX_Unavailable()
src ←VSR[32×BX+B].byte[UIM:UIM+3]
VSR[32×TX+T].dword[0] ←EXTZ64(src)
VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000

This instruction is useful for extracting a specific 4-byte segment from one vector register and placing it into another, while zeroing out the rest of the destination register. Ensure that VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. Be cautious with byte alignment; UIM must be a multiple of 4 to correctly extract a word. This instruction operates at the user privilege level and does not generate any exceptions beyond those related to VSX availability.


Summary: Replicates a word element from one vector register into all elements of another vector register.

The contents of the specified word element UIM in VSR[XB] are replicated into each word element of VSR[XT].

if MSR.VSX=0 then VSX_Unavailable()

XT <- XB.word[UIM]
VSR[32×TX+T].word[0] ← XT
VSR[32×TX+T].word[1] ← XT
VSR[32×TX+T].word[2] ← XT
VSR[32×TX+T].word[3] ← XT

The xxspltw instruction is commonly used to replicate a word element from one vector register into all elements of another vector register. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register; otherwise, an exception will be raised. This instruction does not have specific alignment requirements and operates at user privilege level.


Summary: Loads words from memory into registers RT through R31 (Context Switch).

Loads a sequence of words from memory starting at address (RA + D) into GPRs RT through R31, incrementing the address by 4 bytes for each register. This instruction is part of the Base ISA and does not update condition registers; it may be used for context switching.

if RA = 0 then EA ← 0 + D else EA ← RA + D
for i ← 0 to (31 - RT) do
  GPRC[RT+i] ← MEM[EA+4*i : EA+4*i+31]
end for

This instruction is not supported in Little-Endian mode. If it is executed in Little-Endian mode, the system alignment error handler is invoked.


Summary: Stores words from registers RT through R31 to memory (Context Switch).

Stores a sequence of words from GPRs RT through R31 to memory starting at address (RA + D), incrementing the address by 4 bytes for each register. This instruction is part of the Base ISA and does not update condition registers; it is commonly used for context switching.

if RA = 0 then EA ← 0 + D else EA ← RA + D
for i ← 0 to (31 - RT) do
  MEM[EA+4*i : EA+4*i+31] ← GPRC[RT+i]
end for

Loads (or stores) a sequence of GPRs from consecutive word-aligned memory locations. Not pipelined on most implementations; for bulk data movement consider using vector or floating-point load/store multiples instead.


Summary: Loads a sequence of bytes from memory into general-purpose registers.

Loads NB bytes from memory starting at address RA into a sequence of GPRs beginning at RT, filling registers left-to-right and wrapping from R31 back to R0 if necessary. This Base ISA instruction does not affect condition registers and provides a byte-oriented string load capability.

EA ← RA
reg ← RT
byte_index ← 0
for i ← 0 to (NB - 1) do
  GPRC[reg][(32 - 8*(byte_index+1)) : (31 - 8*byte_index)] ← MEM[EA+i : EA+i+7]
  byte_index ← byte_index + 1
  if byte_index = 4 then
    byte_index ← 0
    reg ← (reg + 1) mod 32
  end if
end for


Summary: Stores a string of words from general-purpose registers to memory, starting at the address in RA and using an immediate byte count.

Stores NB bytes from a sequence of GPRs beginning at RS to memory starting at address RA, extracting bytes left-to-right and wrapping from R31 back to R0 if necessary. This Base ISA instruction does not affect condition registers and provides a byte-oriented string store capability.

EA ← RA
reg ← RS
byte_index ← 0
for i ← 0 to (NB - 1) do
  MEM[EA+i : EA+i+7] ← GPRC[reg][(32 - 8*(byte_index+1)) : (31 - 8*byte_index)]
  byte_index ← byte_index + 1
  if byte_index = 4 then
    byte_index ← 0
    reg ← (reg + 1) mod 32
  end if
end for

This instruction is not supported in Little-Endian mode. If it is executed in Little-Endian mode and NB > 0, the system alignment error handler is invoked.


Summary: Invalidates all Segment Lookaside Buffer entries (OS Management).

Invalidates all Segment Lookaside Buffer (SLB) entries, optionally using an invalidation hint. This is a privileged instruction that flushes virtual-to-real address translation caches and is typically used during context switches or address-space changes.

for each SLB entry do
  invalidate entry
end for

slbia does not affect SLBs on other threads.
If slbia is executed when instruction address translation is enabled, software can ensure that attempting to fetch the instruction following the slbia does not cause an Instruction Segment interrupt by placing the slbia and the subsequent instruction in the effective segment mapped by SLB entry 0.


Summary: Writes an SLB entry (Mapping effective to virtual address).

Writes an entry to the Segment Lookaside Buffer, mapping an effective segment address (from RB) to a virtual segment ID and protection bits (from RS). This is a privileged 64-bit instruction that modifies virtual address translation state.

The slbmte instruction is used to install temporary ESID-to-VSID translations in the SLB for a specific hardware thread. These entries are thread-specific and can be made permanent (bolted) if LPCRUPRT=1, allowing up to four bolted entries per thread. Ensure that the MSR[PR] bit is clear when executing this instruction, as it requires supervisor privilege level. Be cautious of alignment requirements for the SLB entry data.


Summary: Clears a pending doorbell interrupt (Inter-processor comms).

Clears a pending doorbell or message interrupt from another processor, based on the message type specified in RB. This is a privileged instruction used for inter-processor communication and does not affect condition registers.

Use msgclr to clear messages accepted by the current thread. If clearing a message of type 0x05, it also clears any associated Directed Ultravisor Doorbell exception. This instruction is typically used in hypervisor environments where message handling and doorbell management are required.


Summary: Sends a doorbell interrupt to another processor.

The instruction sends a message to other threads based on the contents of register RB. The message type and destination thread(s) are specified in RB.

msgtype ← GPR(RB)32:36
payload ← GPR(RB)37:63
if (msgtype = 0x05)
then
    send_msg(msgtype, payload)

If msgsnd is used to notify the receiver that updates have been made to storage, a sync should be placed between the stores and the msgsnd. See Section 6.9.2.


Summary: Stops execution and alerts the hardware debugger.

Stops execution and signals the hardware debugger, allowing entry into debug mode. This is a privileged instruction that halts the processor and alerts external debugging hardware. No condition registers or status fields are affected by the instruction itself; the processor state is frozen pending debugger intervention.


Summary: Clear Branch History Rolling Buffer. Clears all entries in the Branch History Rolling Buffer (BHRB) to zero. Used to flush branch prediction history, for example when switching execution contexts to prevent information leakage between security domains.

Sets all BHRB entries to 0s.

for n = 0 to (number_of_BHRBEs implemented - 1)
    BHRB(n) ←0

The clrbhrb instruction is used to clear the Branch History Rolling Buffer, resetting all its entries to zero. This can be useful for ensuring a predictable state before branch prediction analysis or when isolating performance tests. However, it should be used with caution as it affects speculative execution paths, potentially impacting performance if not necessary.


Summary: Aborts a transaction if the condition is met (Word comparison).

Transaction Abort Word Conditional. Aborts the current transaction if the condition formed by TO and the comparison of RA and RB is true. Records the abort cause in TEXASR.

if Transactional() then
  if TO_condition(TO, RA, RB) then
    Abort_Transaction(cause=Explicit)

Use tabortwc to conditionally abort a transaction based on a comparison between two registers. Ensure that the transaction is active when using this instruction; otherwise, it will have no effect. The TO field specifies the type of comparison (e.g., equal, less than). Be cautious with the privilege level and ensure the MSR[TS] bit is set to enable transactions.


Summary: Aborts a transaction if the condition is met (Doubleword comparison).

Transaction Abort Doubleword Conditional. Aborts the current transaction if the condition formed by TO and the 64-bit comparison of RA and RB is true. Records the abort cause in TEXASR.

if Transactional() then
  if TO_condition_64(TO, RA, RB) then
    Abort_Transaction(cause=Explicit)

Use tabortdc to conditionally abort a transaction based on a 64-bit comparison. Ensure that the transaction is active when using this instruction; otherwise, it has no effect. The TO field specifies the condition for the comparison, and RA and RB are the registers holding the values to compare. This instruction operates at the problem state privilege level.


Summary: Updates the transaction checkpoint.

Transaction Recheckpoint. Restores the transactional register state from the checkpoint saved by a prior tbegin. Used to restart a transaction after a non-transactional abort.

if Suspended() then
  Restore_Checkpoint()
  Resume_Transaction()

LR, CTR, CR, FPSCR, XER, MSR, SRR0, SRR1, TAR

The trechkpt instruction is used to restore the transactional register state from a previous checkpoint, allowing a transaction to be restarted after a non-transactional abort. It should only be used within a transactional region and requires that the transaction was previously suspended. Ensure proper ordering of instructions to maintain consistency and avoid data corruption.


Summary: Loads N bytes into a vector, where N is specified in a GPR.

Loads up to 16 bytes from memory into a VSX register, with the byte count specified by bits 0-4 of RB. Bytes from address RA|0 (or RA + RB if RA is non-zero) are loaded left-aligned into XT; unloaded bytes are zeroed. This is a VSX category instruction with no effect on condition registers.

N ← RB[0:4]
if N > 16 then N ← 16
addr ← RA + 0 (if RA != 0 else address from context)
for i ← 0 to N-1
  XT[8*i:8*i+7] ← [addr + i]
for i ← N to 15
  XT[8*i:8*i+7] ← 0

Loading less than 16 bytes of data using lxvl in BE mode results in data being loaded into the target VSR left-to-right, placing the first byte in the leftmost byte of the target VSR, and padded on the right with 0s. Loading less than 16 bytes of data using lxvl in LE mode results in data being loaded into the target VSR right-to-left, placing the first byte in the rightmost byte of the target VSR, and padded on the left with 0s.


Summary: Stores a specified number of bytes from a VSX vector register to memory.

Stores up to 16 bytes from a VSX register to memory, with the byte count specified by bits 0-4 of RB. Bytes are stored from XS starting at address RA|0 (or RA + RB if RA is non-zero). This is a VSX category instruction with no effect on condition registers.

N ← RB[0:4]
if N > 16 then N ← 16
addr ← RA + 0 (if RA != 0 else address from context)
for i ← 0 to N-1
  [addr + i] ← XS[8*i:8*i+7]

Storing N bytes of data from the source VSR using stxvl in BE mode, results in the leftmost N bytes in the source VSR being placed in storage, starting with the leftmost byte of the source VSR.

Storing N bytes of data from the source VSR using stxvl in LE mode, results in the rightmost N bytes in the source VSR being placed in storage, starting with the rightmost byte of the source VSR.


Summary: Performs a vector permute operation on the contents of three VSX registers.

Permutes bytes from two 128-bit VSX registers (XA and XB) using a control vector in XC to produce a 128-bit result in XT. Each byte in the control vector specifies which byte from the 32-byte concatenation of XA and XB is selected into the corresponding output byte. This is a VSX category instruction with no effect on condition registers.

concat ← XA || XB
for i ← 0 to 15
  control_byte ← XC[8*i:8*i+7]
  idx ← control_byte[1:4]
  XT[8*i:8*i+7] ← concat[8*idx:8*idx+7]

The xxperm instruction requires VSX (Vector Scalar Extensions) to be enabled in the MSR register. Ensure that the control vector register is correctly set up, as it defines how the source bytes are permuted. This instruction operates on 32-byte vectors and can be used for tasks like data reordering or encryption. Be cautious of alignment requirements; the VSX registers must be properly aligned to avoid exceptions.


Summary: Little-endian optimized permute.

Permutes bytes from two 128-bit VSX registers (XA and XB) using a control vector in XC, optimized for little-endian byte ordering. Each byte in the control vector specifies which byte from the concatenation of XB and XA is selected into the corresponding output byte in XT. This is a VSX category instruction with no effect on condition registers.

concat ← XB || XA
for i ← 0 to 15
  control_byte ← XC[8*i:8*i+7]
  idx ← control_byte[1:4]
  XT[8*i:8*i+7] ← concat[8*idx:8*idx+7]

The xxpermr instruction is useful for complex byte-level data manipulation, especially when merging and reordering bytes from two source vectors. Ensure that the control vector (second source) correctly specifies the desired permutation indices to avoid unexpected results. This instruction operates at a privilege level that allows it in user mode, but developers should be cautious of potential performance overhead due to its complexity.


Summary: Loads N bytes from memory (N in XER).

Loads a variable number of bytes from memory into a sequence of GPRs starting at RT, where the byte count is stored in XER[25:31]. Bytes are loaded from address RA|0 (or RA + RB if RA is non-zero) into consecutive 32-bit words. This is a Base category instruction that does not affect condition registers.

N ← XER[25:31]
addr ← (RA == 0) ? 0 : RA + RB
reg ← RT
for i ← 0 to N-1
  byte_offset ← i mod 4
  if byte_offset == 0 and i > 0 then
    reg ← (reg + 1) mod 32
  reg[8*byte_offset:8*byte_offset+7] ← [addr + i]

String instructions are not pipelined on most implementations and can be very slow for large counts. Consider using byte loops or vector instructions for performance-critical paths. NB: these instructions are optional in Power ISA 3.0+ and may trap on some implementations.


Summary: Stores N bytes to memory (N in XER).

Stores a variable number of bytes from a sequence of GPRs starting at RT to memory, where the byte count is stored in XER[25:31]. Bytes are stored from consecutive 32-bit words to address RA|0 (or RA + RB if RA is non-zero). This is a Base category instruction that does not affect condition registers.

N ← XER[25:31]
addr ← (RA == 0) ? 0 : RA + RB
reg ← RT
for i ← 0 to N-1
  byte_offset ← i mod 4
  if byte_offset == 0 and i > 0 then
    reg ← (reg + 1) mod 32
  [addr + i] ← reg[8*byte_offset:8*byte_offset+7]


Summary: Stops instruction execution and places the processor in a lower power state until an interrupt occurs.

if WC == 0 then
  WaitForInterrupt()
else if WC == 1 then
  WaitForResume()

Suspends instruction execution and places the processor in a low-power idle state until an interrupt is pending. The WC field selects the wait condition (interrupt vs. resume), and the PL field optionally specifies a programmable length timeout. This is a Base/privileged instruction with no effect on condition registers; execution resumes after the specified event.

Because the waiting begins when the instruction completes, if the waiting is ended by an exception that causes a change of control flow (interrupt, event-based branch), the SPR that is set to reflect the point in the instruction stream at which the change of control flow occurred (e.g., SRR0 for Decrementer interrupt) will contain the EA of the instruction following the wait instruction. Bits 6 and 7 of the wait instruction may be used in some implementations for an implementation-dependent field. Unless the intention is to use the implementation-dependent field, these bits must be coded zero. wait serves as both a basic and an extended mnemonic. The Assembler will recognize a wait mnemonic with two operands as the basic form and a wait mnemonic with one operand or with no operand as an extended form. In the extended form with one operand the PL operand is omitted and assumed to be 0. In the extended form with no operand the WC and PL operands are omitted and assumed to be 0. The wait instruction frees computational resources which might be allocated to another program or converted into power savings.


Summary: Zeros a cache block (implementation defined size).

Zeros a cache block of implementation-defined size (typically larger than the standard dcbz 128-byte block) specified by the address computed as RA + RB. This instruction operates on the data cache and may affect cache coherency on multiprocessor systems. No condition or status registers are modified; cache operations are weakly ordered.

EA ← (RA) + (RB)
Zero cache block at EA with implementation-defined block size


Summary: Reads the ESID part of an SLB entry.

Reads the ESID (Effective Segment ID) portion of a Segment Lookaside Buffer entry. The SLB entry is selected by the index in RB. This privileged instruction is used in 64-bit mode for TLB management. No condition or status registers are modified.

The slbmfee instruction is used to read software-loaded SLB entries, placing the ESID and V fields into register RT. If the entry is valid and LPCRUPRT is set, it also places the BO field into RT. Ensure that the index calculation respects the LPCRUPRT setting to avoid accessing invalid SLB entries.


Summary: Reads software-loaded SLB entries and places the contents of the B, VSID, Ks, Kp, N, L, C, and LP fields into register RT.

This instruction is used to read software-loaded SLB entries. When LPCRUPRT=0, the entry is specified by bits 52:63 of register RB. When LPCRUPRT=1, only the first four entries can be read, so bits 52:61 of register RB are ignored. If the specified entry is valid (V=1), the contents of the B, VSID, Ks, Kp, N, L, C, and LP fields of the entry are placed into register RT.

if 'slbmfev' then
    if LPCRUPRT=0 then
        entry_index <- (RB)[52:63]
    else
        entry_index <- (RB)[52:61] & 0xF
    end if
    if SLB[entry_index].V=1 then
        RT[0:1] <- SLB[entry_index].B
        RT[2:51] <- SLB[entry_index].VSID
        RT[52] <- SLB[entry_index].Ks
        RT[53] <- SLB[entry_index].Kp
        RT[54] <- SLB[entry_index].N
        RT[55] <- SLB[entry_index].L
        RT[56] <- SLB[entry_index].C
        RT[57] <- 0b0
        RT[58:59] <- SLB[entry_index].LP
        RT[60:63] <- 0b0000
    else
        RT <- 0
    end if

This instruction is privileged. The use of the L field is implementation specific.


Summary: Clears a privileged doorbell interrupt.

Clears a privileged doorbell interrupt message matching the type specified in RB. This privileged instruction is used for inter-processor communication and interrupt management. Clearing a message may affect pending interrupts. No explicit status registers are modified, but interrupt state is affected.

Clear privileged doorbell message of type (RB)

The msgclrp instruction is used to clear messages accepted by the current thread, specifically handling Directed Hypervisor Doorbell exceptions when the message type is 0x05. It operates at a privileged level and should be used carefully to avoid unintended side effects on exception handling.


Summary: Sends a message to other threads on the same processor or sub-processor.

The instruction sends a message to other threads based on the contents of RB. The message type and destination thread(s) are specified in RB.

msgtype ← (RB)32:36
payload ← (RB)37:63
t ← (RB)57:63
if msgtype = 5 and t ≤ maximum privileged thread number on processor or sub-processor then
    DPDES63-t ← 1
    send_msg(msgtype, payload, t)

If msgsndp is used to notify the receiver that updates have been made to storage, a lwsync or sync should be placed between the stores and the msgsndp. See Section 6.9.2.


Summary: Legacy 32-bit segment register read.

Reads a 32-bit Segment Register (legacy 32-bit PowerPC mode) and stores the value in RT. This instruction is used only in 32-bit addressing mode and is deprecated in 64-bit architecture. No condition or status registers are modified.


Summary: Legacy 32-bit segment register write.

Move the contents of GPR RS into the specified 32-bit segment register SR. This is a legacy instruction used in 32-bit PowerPC address translation and is not available in 64-bit mode. No status fields are affected.


Summary: Indirect read of segment register using RB.

Move the contents of the segment register selected by bits 0-3 of GPR RB into GPR RT. This is an indirect read of the 32-bit segment register and is not available in 64-bit mode. No status fields are affected.


Summary: Indirect write of segment register using RB.

Move the contents of GPR RS into the segment register selected by bits 0-3 of GPR RB. This is an indirect write of the 32-bit segment register and is not available in 64-bit mode. No status fields are affected.

SR_index ← RB[0:3]
SR[SR_index] ← RS[32:63]


Move From Branch History Rolling Buffer Entry

Summary: Reads a specific entry from the BHRB.

Move the contents of a Branch History Rolling Buffer (BHRB) entry, indexed by BHRBE, into GPR RT. The BHRB records branch addresses and is used for performance monitoring. This is a hypervisor-privileged or performance-monitoring register operation. No architected status fields are affected.

The mfbhrbe instruction is used to access entries in the Branch History Rolling Buffer (BHRB). Ensure that the specified entry index is within the range of implemented entries to avoid placing zero in the target register. This instruction operates at user privilege level and does not generate exceptions under normal conditions.


Summary: Suspends or resumes a transaction based on L.

Transaction Suspend or Resume. Suspends an active transaction (L=0) or resumes a suspended transaction (L=1). The transactional state is preserved across the suspend/resume boundary.

if L = 0 then
  Suspend_Transaction()
else
  Resume_Transaction()

The tsr instruction is used to either suspend or resume a transaction based on the value of the L bit. Ensure that the transactional state is properly managed to avoid data corruption. This instruction operates at the privilege level of the executing context and may raise exceptions if used incorrectly, such as attempting to resume a non-existent suspended transaction.


Summary: Aborts transaction if word condition (Immediate) is met.

Transaction Abort Word Conditional Immediate. Aborts the current transaction if the condition formed by TO and the comparison of RA with the sign-extended immediate SI is true.

if Transactional() then
  if TO_condition(TO, RA, EXTS(SI)) then
    Abort_Transaction(cause=Explicit)

Use tabortwci to conditionally abort a transaction based on the comparison of a register with an immediate value. Ensure that the transactional state is active; otherwise, the instruction has no effect. Be cautious with the TO condition and immediate sign extension to avoid unintended aborts.


Summary: Aborts transaction if doubleword condition (Immediate) is met.

Transaction Abort Doubleword Conditional Immediate. Aborts the current transaction if the condition formed by TO and the 64-bit comparison of RA with the sign-extended immediate SI is true.

if Transactional() then
  if TO_condition_64(TO, RA, EXTS(SI)) then
    Abort_Transaction(cause=Explicit)

Use tabortdci to conditionally abort a transaction based on a comparison between a register and an immediate value. Ensure the transaction is active; otherwise, the instruction has no effect. Be cautious with TO conditions to avoid unintended transaction aborts.


VSX Scalar Round to Integer Quad-Precision

Summary: Rounds Quad float to nearest Integer.

Round the quad-precision floating-point value in VSR vB to the nearest integer, using the rounding mode specified in FPSCR[RN], and store the result in VSR vD. This is a VSX instruction. FPSCR is read for rounding mode and may have status flags updated (XX, ZX, etc.) depending on the rounding operation.

vD ← round_to_integer_qp(vB, FPSCR[RN])
FPSCR[FPCC, VXCVI, XX, ZX, ...] ← updated as per rounding


Summary: Converts DFP Long (64-bit) to DFP Quad (128-bit).

Convert a DFP long (64-bit) value from FPR FRB into a DFP quad (128-bit) value and store it in VSR vD. This is a Decimal Floating-Point (DFP) instruction. FPSCR status fields may be updated to indicate conversion results.

quad_value ← convert_dfp_long_to_quad(FRB)
vD ← quad_value
FPSCR[...] ← updated as per conversion

The dctqpq instruction is used to convert a DFP number from long format to extended format. Ensure that the source register (FRAp) contains a valid DFP value in long format, and the target register (FRTp) is properly aligned for storing an extended format DFP number. This operation does not alter the FPSCR register.


Summary: Rounds DFP Quad (128-bit) to DFP Long (64-bit).

Round a DFP quad (128-bit) value from VSR vB to DFP long (64-bit) precision using the rounding mode in FPSCR[RN], and store the result in FPR FRT. This is a Decimal Floating-Point (DFP) instruction. FPSCR status fields are updated to reflect rounding or conversion results.

The drdpq instruction is used for rounding decimal floating-point numbers to quad-precision. Ensure that the input number in FRA[p] is within the valid range for quad-precision format to avoid overflow or underflow exceptions. The rounding mode is controlled by the FPSCR register, so make sure it's set according to your application's requirements before executing drdpq.

long_value ← round_dfp_quad_to_long(vB, FPSCR[RN])
FRT ← long_value
FPSCR[...] ← updated as per rounding


Summary: Performs the final round of AES encryption (SubBytes, ShiftRows, AddRoundKey). No MixColumns.

Perform the final round of AES encryption on 128-bit blocks. Applies SubBytes, ShiftRows, and AddRoundKey transformations (but not MixColumns, which is done in prior rounds). Operates on one or more 128-bit AES blocks. No status flags are affected.

vD ← AES_SubBytes(vA)
vD ← AES_ShiftRows(vD)
vD ← AES_AddRoundKey(vD, vB)

The vcipherlast instruction is used to perform the final round of AES encryption on a vector of data. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. This instruction processes each 32-bit word of the input data with the corresponding round key from the VRA register to produce the encrypted output in the VRT register.


Summary: Performs the final round of AES decryption.

Performs the final round of AES decryption on a 128-bit block, applying the inverse MixColumns and InvSubBytes operations followed by AddRoundKey with the provided round key. This instruction is part of the Vector Crypto extension and operates on 128-bit values held in vector registers. No status flags are affected.

The vncipherlast instruction is used to complete the AES inverse cipher process by applying the final transformations. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The input State and RoundKey must be correctly loaded into VSR registers VRA+32 and VRB+32, respectively, to avoid incorrect results.


Summary: Performs the SubBytes operation (S-Box lookup) on a vector.

Performs the SubBytes operation (S-Box lookup) on all 16 bytes of a 128-bit vector, applying the AES S-box transformation to each byte independently. This instruction is part of the Vector Crypto extension and is used during AES encryption and decryption. No status flags are affected.

The vsbox instruction applies the AES SubBytes transformation to a vector register, requiring the Vector Facility to be enabled (MSR.VEC=1). Ensure that the input vector is correctly aligned and that the destination register is properly set to avoid data corruption. This instruction operates at user privilege level but will raise an exception if the Vector Facility is not available.


Summary: Performs the SHA-512 σ0, σ1, Σ0, or Σ1 functions on doubleword elements of vector registers.

For vshasigmad, the instruction performs either a SHA-512 σ0, σ1, Σ0, or Σ1 function on each doubleword element of VSR[VRA+32] based on the values in ST and SIX. The result is placed into corresponding elements of VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    src ← VSR[VRA+32].dword[i]
    if ST=0 & SIX.bit[2×i]=0 then
        // SHA-512 σ0 function
        VSR[VRT+32].dword[i] ← (src >>> 1) ⊕ (src >>> 8) ⊕ (src >> 7)
    if ST=0 & SIX.bit[2×i]=1 then
        // SHA-512 σ1 function
        VSR[VRT+32].dword[i] ← (src >>> 19) ⊕ (src >>> 61) ⊕ (src >> 6)
    if ST=1 & SIX.bit[2×i]=0 then
        // SHA-512 Σ0 function
        VSR[VRT+32].dword[i] ← (src >>> 28) ⊕ (src >>> 34) ⊕ (src >>> 39)
    if ST=1 & SIX.bit[2×i]=1 then
        // SHA-512 Σ1 function
        VSR[VRT+32].dword[i] ← (src >>> 14) ⊕ (src >>> 18) ⊕ (src >>> 41)
end


Summary: Permutes bytes from vA and vB, then XORs with vC. Used for finite field arithmetic.

Permutes bytes from vA and vB according to the permutation control vector vC, then XORs the result with vC. This instruction is used for finite field arithmetic operations in cryptographic algorithms within the Vector Crypto extension. No status flags are affected.

temp ← Permute(vA || vB, vC); vD ← temp XOR vC

The vpermxor instruction requires the Vector Facility to be enabled in the MSR. Ensure that the index values in VRC do not exceed 15 to avoid undefined behavior. This instruction operates on byte-level data and is useful for complex data transformations involving permutation and bitwise operations.


Summary: Converts a national decimal value to packed decimal format and stores it in the target vector register.

The instruction checks if the source vector register contains a valid national decimal value. If valid, it converts it to packed decimal format and stores it in the target vector register. The condition register is updated based on the comparison of the source with zero.

if MSR.VEC=0 then
    Vector_Unavailable()
src_sign ←(VSR[VRB+32].hword[7] = 0x002D)
eq_flag ←1
inv_flag ←(VSR[VRB+32].hword[7] != 0x002B) & (VSR[VRB+32].hword[7] != 0x002D)
do i = 0 to 6
eq_flag  ←eq_flag & (VSR[VRB+32].hword[i] = 0x0030)
inv_flag ←inv_flag | (VSR[VRB+32].hword[i] < 0x0030) | (VSR[VRB+32].hword[i] > 0x0039)
end
lt_flag ←(eq_flag=0) & (src_sign=1)
gt_flag ←(eq_flag=0) & (src_sign=0)
do i = 0 to 23
result.nibble[i] ←0x0
end
do i = 0 to 6
result.nibble[i+24] ← VSR[VRB+32].hword[i].nibble[3]
end
result.nibble[31] ← (src_sign=0) ? ((PS=0) ? 0xC : 0xF) : 0xD
VSR[VRT+32] ←inv_flag ? undefined : result
CR.bit[56] ←inv_flag ? 0b0 : lt_flag
CR.bit[57] ←inv_flag ? 0b0 : gt_flag
CR.bit[58] ←inv_flag ? 0b0 : eq_flag
CR.bit[59] ←inv_flag

The bcdcfn. instruction is used to convert a national decimal value in a vector register to packed decimal format, updating the condition register based on comparison with zero. Ensure the source vector contains valid national decimal values; otherwise, the result is undefined and flags are set accordingly. This instruction requires the Vector Facility (MSR.VEC) enabled.


Summary: Converts a packed decimal value to national decimal format and stores it in a vector register.

The instruction converts the packed decimal value from VSR[VRB+32] into national decimal format and places it into VSR[VRT+32]. It also updates the condition register CR6 based on the validity of the input and its comparison to zero.

if MSR.VEC=0 then
    Vector_Unavailable()
end
src_sign ←(VSR[VRB+32].nibble[31] = 0xB) | (VSR[VRB+32].nibble[31] = 0xD)
eq_flag ←(VSR[VRB+32].nibble[0:30] = 0)
lt_flag ←(eq_flag=0) & (src_sign=1)
gt_flag ←(eq_flag=0) & (src_sign=0)
inv_flag ←false
ox_flag ←false
do i = 0 to 23
    ox_flag ←ox_flag | (VSR[VRB+32].nibble[i] != 0x0)
end
do i = 0 to 30
    inv_flag ←inv_flag | (VSR[VRB+32].nibble[i] > 0x9)
end
if inv_flag then
    VSR[VRT+32] ←undefined
else
    do i = 0 to 6
        result.hword[i].nibble[0:2] ←0x003
        result.hword[i].nibble[3] ←VSR[VRB+32].nibble[i+24]
    end
    result.hword[7] ←(src_sign=1) ? 0x002D : 0x002B
    VSR[VRT+32] ←result
end
CR.bit[56] ←inv_flag ? 0b0 : lt_flag
CR.bit[57] ←inv_flag ? 0b0 : gt_flag
CR.bit[58] ←inv_flag ? 0b0 : eq_flag
CR.bit[59] ←inv_flag | ox_flag

The bcdctn. instruction is used to convert packed decimal values into national decimal format, updating CR6 with flags indicating the result's validity and sign. Ensure VSR[VRB+32] contains valid packed decimal data; otherwise, VSR[VRT+32] will be undefined. This instruction requires vector mode enabled (MSR.VEC=1) and operates at user privilege level.


Summary: Converts BCD Zoned format to Signed Packed BCD.

The bcdcfz. instruction converts a zoned decimal value in VSR[VRB+32] to a packed decimal format and stores the result in VSR[VRT+32]. The conversion is based on the sign code and digit values of the source operand.

if MSR.VEC=0 then
    Vector_Unavailable()
inv_flag ← ((VSR[VRB+32].byte[15].nibble[0] < 0xA) & (PS=1)) | (VSR[VRB+32].byte[15].nibble[1] > 0x9)
MIN ← (PS=0) ? 0x30 : 0xF0
MAX ← (PS=0) ? 0x39 : 0xF9
do i = 0 to 14
    inv_flag ← inv_flag | (VSR[VRB+32].byte[i] < MIN) | (VSR[VRB+32].byte[i] > MAX)
end
if PS=0 then
    src_sign ← VSR[VRB+32].nibble[30].bit[1]
else
    src_sign ← (VSR[VRB+32].nibble[30] = 0b1011) | (VSR[VRB+32].nibble[30] = 0b1101)
eq_flag ← 1
do i = 0 to 14
    result.nibble[i] ← 0x0
end
do i = 0 to 15
    result.nibble[i+15] ← VSR[VRB+32].byte[i].nibble[1]
    eq_flag ← eq_flag & (VSR[VRB+32].byte[i].nibble[1]=0x0)
end
lt_flag ← (eq_flag=0) & (src_sign=1)
gt_flag ← (eq_flag=0) & (src_sign=0)
result.nibble[31] ← (src_sign=0) ? 0xC : 0xD
CR.bit[56] ← inv_flag ? 0b0 : lt_flag
CR.bit[57] ← inv_flag ? 0b0 : gt_flag
CR.bit[58] ← inv_flag ? 0b0 : eq_flag
CR.bit[59] ← inv_flag
VSR[VRT+32] ← inv_flag ? undefined : result

The bcdcfz. instruction is used to convert zoned decimal values to packed decimal format. Ensure that the source vector register (VRB) contains valid zoned decimal data, as invalid input can lead to undefined results and set the CR6 flags accordingly. This instruction operates at the user privilege level and requires the Vector Facility to be enabled; otherwise, a Vector_Unavailable exception is raised.


Summary: Converts Signed Packed BCD to Zoned format.

The contents of each nibble 0-30 must be a value in the range 0x0 to 0x9. Packed decimal values with sign codes of 0xA, 0xC, 0xE, or 0xF are interpreted as positive values. Packed decimal values with sign codes of 0xB or 0xD are interpreted as negative values.

if MSR.VEC=0 then
    Vector_Unavailable()
inv_flag ←(VSR[VRB+32].nibble[31] < 0xA)
do i = 0 to 30
    inv_flag ←inv_flag | (VSR[VRB+32].nibble[i] > 0x9)
ox_flag ←0
do i = 0 to 15
    ox_flag ←ox_flag | (VSR[VRB+32].nibble[i] != 0x0)
src_sign ←(VSR[VRB+32].nibble[31] = 0xB) | (VSR[VRB+32].nibble[31] = 0xD)
eq_flag ←(VSR[VRB+32].nibble[0:30] = 0)
lt_flag ←(eq_flag=0) & (src_sign=1)
gt_flag ←(eq_flag=0) & (src_sign=0)
do i = 0 to 14
    result.byte[i].nibble[0] ←(PS=0) ? 0x3 : 0xF
    result.byte[i].nibble[1] ←VSR[VRB+32].nibble[i+15]
end
if src.sign=0 then
    result.byte[15].nibble[0] ←(PS=0) ? 0x3 : 0xC
else
    result.byte[15].nibble[0] ←(PS=0) ? 0x7 : 0xD
end
result.byte[15].nibble[1] ←VSR[VRB+32].nibble[30]
VSR[VRT+32] ←inv_flag ? undefined : result
CR.bit[56] ←inv_flag ? 0b0 : lt_flag
CR.bit[57] ←inv_flag ? 0b0 : gt_flag
CR.bit[58] ←inv_flag ? 0b0 : eq_flag
CR.bit[59] ←inv_flag | ox_flag

The bcdctz. instruction converts packed decimal values to zoned format, interpreting sign codes and handling invalid nibble values. Ensure that the input data is correctly formatted with valid nibbles (0x0-0x9) and appropriate sign codes. The instruction operates on vector registers and requires the Vector Facility to be enabled; otherwise, it raises a Vector Unavailable exception. Check the condition register bits for flags indicating invalid input, less than, greater than, or equal conditions.


Summary: Converts a signed quadword integer to packed decimal format and updates the condition register.

The bcdcfsq. instruction converts a signed quadword integer from VSR[VRB+32] to packed decimal format and stores it in VSR[VRT+32]. It also updates the condition register CR6 based on the conversion result.

if MSR.VEC=0 then
    Vector_Unavailable()

ox_flag ←(EXTS(VSR[VRB+32]) > 1031-1) |
           (EXTS(VSR[VRB+32]) < -(1031-1))
lt_flag ←(EXTS(VSR[VRB+32]) < 0)
gt_flag ←(EXTS(VSR[VRB+32]) > 0)
eq_flag ←(EXTS(VSR[VRB+32]) = 0)

if ox_flag=0 then
   result ←bcd_CONVERT_FROM_SI128(EXTS(VSR[VRB+32]),PS)
else
   result ←0xUUUU_UUUU_UUUU_UUUU_UUUU_UUUU_UUUU_UUUU

VSR[VRT+32] ←ox_flag ? undefined : result

CR.bit[56] ←lt_flag
CR.bit[57] ←gt_flag
CR.bit[58] ←eq_flag
CR.bit[59] ←ox_flag

The bcdcfsq. instruction is used to convert a signed quadword integer to packed decimal format, storing the result in VSR[VRT+32]. It updates CR6 with flags indicating overflow (OX), less than (LT), greater than (GT), and equal (EQ) conditions. Ensure that the Vector Facility is enabled by checking MSR.VEC before using this instruction. Be cautious of overflow conditions, as they result in an undefined value being stored.


Binary Coded Decimal Compare and Test Sign Quadword

Summary: Compares two binary coded decimal (BCD) numbers in a quadword format and tests the sign.

The instruction converts the packed decimal value in VSR[VRB+32] to a signed integer and places it into VSR[VRT+32]. The sign code must be within the range 0xA to 0xF, with specific interpretations for positive and negative values. If the input is invalid, the result is undefined.

if MSR.VEC=0 then
    Vector_Unavailable()
inv_flag ←(VSR[VRB+32].nibble[31] < 0xA)
do i = 0 to 30
    inv_flag ←inv_flag | (VSR[VRB+32].nibble[i] > 0x9)
src_sign ←(VSR[VRB+32].nibble[31] = 0xB) | (VSR[VRB+32].nibble[31] = 0xD)
eq_flag ←(VSR[VRB+32].nibble[0:30] = 0)
lt_flag ←(eq_flag=0) & (src_sign=1)
gt_flag ←(eq_flag=0) & (src_sign=0)
result ←si128_CONVERT_FROM_BCD(VSR[VRB+32])
VSR[VRT+32] ←inv_flag ? undefined : result
CR.bit[56] ←inv_flag ? 0b0 : lt_flag
CR.bit[57] ←inv_flag ? 0b0 : gt_flag
CR.bit[58] ←inv_flag ? 0b0 : eq_flag
CR.bit[59] ←inv_flag

The bcdctsq. instruction is used to convert a packed decimal value to a signed integer, storing the result in VSR[VRT+32]. Ensure the input sign code is within 0xA to 0xF; otherwise, the result is undefined. The instruction sets condition register bits CR6 based on comparison results, but these are only valid if the input is not invalid.


Summary: Multiplies two 64-bit integers and returns the upper 64 bits of the 128-bit result (Signed).

Multiplies two 64-bit signed integers (RA and RB) and stores the upper 64 bits of the 128-bit signed result in RT. The overflow flag (OE) is not typically set by this instruction as it returns the mathematically correct upper bits. If Rc=1, CR0 is updated based on the result.

prod ← (RA) *s (RB); RT ← prod[64:127]; if Rc then CR0 ← (RT < 0, RT > 0, RT = 0, SO)

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.


Summary: Multiplies two 64-bit integers and returns the upper 64 bits of the 128-bit result (Unsigned).

Multiplies two 64-bit unsigned integers (RA and RB) and stores the upper 64 bits of the 128-bit unsigned result in RT. The overflow flag is not set as the full 128-bit product is well-defined for unsigned multiplication. If Rc=1, CR0 is updated based on the result.

prod ← (RA) *u (RB); RT ← prod[64:127]; if Rc then CR0 ← (RT < 0, RT > 0, RT = 0, SO)


Summary: Multiplies two 32-bit integers and returns the upper 32 bits (Signed).

Multiplies two 32-bit signed integers (RA[32:63] and RB[32:63]) and stores the upper 32 bits of the 64-bit signed result in RT[32:63], with RT[0:31] undefined. If Rc=1, CR0 is updated based on the result. No overflow is recorded.


Summary: Multiplies two 32-bit integers and returns the upper 32 bits (Unsigned).

Multiplies two 32-bit unsigned integers (RA[32:63] and RB[32:63]) and stores the upper 32 bits of the 64-bit unsigned result in RT[32:63], with RT[0:31] undefined. If Rc=1, CR0 is updated based on the result.


Summary: Divides a 128-bit signed integer by a 128-bit signed integer (using VSX pairs).

Divides a 128-bit signed integer dividend (vA) by a 128-bit signed integer divisor (vB) and stores the 128-bit signed quotient in vD. This instruction operates on VSX vector register pairs and is part of the Base category with extended integer support. Division by zero results in undefined behavior; no overflow exception is generated.


Summary: Divides a 128-bit unsigned integer by a 128-bit unsigned integer.

Divides a 128-bit unsigned integer (vA) by a 128-bit unsigned integer (vB), storing the 128-bit unsigned quotient in vD. This is a VSX or MMA category instruction that performs quadword division. If division by zero is attempted, the result is undefined.

vD ← vA ÷ vB (128-bit unsigned integer division)


Summary: Computes remainder of 128-bit signed division.

Computes the remainder of a 128-bit signed integer division, storing the 128-bit signed remainder in vD. This is a VSX or MMA category instruction. The operation uses the dividend (vA) and divisor (vB) to compute the modulo result, with sign following the dividend.

vD ← vA mod vB (128-bit signed integer modulo)


Summary: Computes remainder of 128-bit unsigned division.

Computes the remainder of a 128-bit unsigned integer division, storing the 128-bit unsigned remainder in vD. This is a VSX or MMA category instruction. The operation uses the dividend (vA) and divisor (vB) to compute the modulo result.

vD ← vA mod vB (128-bit unsigned integer modulo)


Load Halfword and Zero Caching Inhibited

Summary: Loads a halfword bypassing the cache.

Loads an unsigned halfword (16 bits) from memory at address (RA + RB) with caching inhibited, zero-extending the result to 64 bits in RT. This instruction bypasses the cache and is used for memory-mapped I/O. No condition registers are affected.

EA ← (RA) + (RB); RT ← 0x000000000000ZZZZ where ZZZZ = [EA]


Summary: Loads a word bypassing the cache.

Loads an unsigned word (32 bits) from memory at address (RA + RB) with caching inhibited, zero-extending the result to 64 bits in RT. This instruction bypasses the cache and is commonly used for memory-mapped I/O device access. No condition registers are affected.

EA ← (RA) + (RB); RT ← 0x00000000ZZZZZZZZ where ZZZZZZZZ = [EA]


Summary: Loads a doubleword bypassing the cache.

Loads a doubleword (64 bits) from memory at address (RA + RB) with caching inhibited, storing the result in RT. This instruction bypasses the cache hierarchy and is used for memory-mapped I/O operations in 64-bit mode. No condition registers are affected.


Summary: Stores a byte bypassing the cache.

Stores the low-order byte from RS to memory at address (RA + RB) with caching inhibited. This instruction bypasses the cache hierarchy and is typically used for memory-mapped I/O operations. No condition registers are affected.


Summary: Stores a halfword bypassing the cache.

Store a halfword from register RS to memory at address (RA + RB), with cache inhibit semantics to bypass the L1 data cache. The halfword is written directly to L2 or memory depending on cache hierarchy. This instruction requires cache-inhibited access and is typically used for memory-mapped I/O or special memory regions.

addr ← (RA) + (RB)
[(addr)] ← (RS)[48:63]
Memory write with cache inhibit attribute


Summary: Stores a word bypassing the cache.

Store a word from register RS to memory at address (RA + RB), with cache inhibit semantics to bypass the L1 data cache. The word is written directly to L2 or memory. This instruction is used for memory-mapped I/O or device registers where cache bypass is required.

addr ← (RA) + (RB)
[(addr)] ← (RS)[32:63]
Memory write with cache inhibit attribute


Summary: Stores a doubleword bypassing the cache.

Store a doubleword from register RS to memory at address (RA + RB), with cache inhibit semantics to bypass the L1 data cache. The doubleword is written directly to L2 or memory. This instruction is used for memory-mapped I/O operations requiring full 64-bit cache-bypassed writes.

addr ← (RA) + (RB)
[(addr)] ← (RS)[0:63]
Memory write with cache inhibit attribute


Summary: Aborts a hardware accelerator copy-paste sequence.

Abort an ongoing copy-paste sequence initiated by a prior COPY instruction. This privileged instruction clears the copy-paste state, terminating any in-flight hardware accelerator operation. It is typically used in exception handlers or during context switches to ensure no stale copy-paste state persists.

Copy-paste buffer state ← cleared
Any pending copy-paste operation ← aborted


Move to Condition Register from XER Extended

Summary: Copies the contents of the XER register fields OV, OV32, CA, and CA32 to the specified condition register field.

The contents of the OV, OV32, CA, and CA32 are copied to Condition Register field BF. The contents of bits 32:63 of register RS are placed into the Condition Register under control of the field mask specified by FXM.

The mcrxrx instruction is used to transfer specific bits from the XER register into the Condition Register. Ensure that the FXM field correctly specifies which bits of RS should be moved to CR, as incorrect masking can lead to unexpected results. This instruction operates at user privilege level and does not generate exceptions under normal conditions.


Summary: Performs a system call to a fixed vector address (Faster than 'sc').

Perform a system call with a vectored trap to a fixed address determined by the LEV (level) field, providing faster dispatch than the traditional sc instruction. The instruction saves SRR0 and SRR1, sets MSR[PR]=0 to enter privileged mode, and jumps to the system call vector. LEV is a 7-bit field (bits 20-26) that selects among up to 128 vector addresses.

SRR0 ← CIA + 4
SRR1 ← MSR
MSR[PR] ← 0
MSR[EE] ← 0
MSR[IR] ← 0
MSR[DR] ← 0
PC ← Interrupt Vector Base + (LEV << 7) + System Call Vectored Offset

If this instruction sets MSRPR to 1, it also sets MSREE, MSRIR, and MSRDR to 1. If this instruction results in MSRS HV PR being equal to 0b110, it also sets MSRIR and MSRDR to 0.

This instruction does not alter MSRHV, MSRS, or MSRME.


Summary: Returns from a vectored system call.

Return from a vectored system call by restoring the processor state from SRR0 and SRR1. This privileged instruction restores PC from SRR0 and MSR from SRR1, typically returning to user mode if MSR[PR] was set in the saved state. It is the inverse of scv.

The rfscv instruction is used to return from a system call vectored, restoring the program's execution context by setting the CIA to the value in SRR0 and the MSR from SRR1. Ensure that this instruction is executed at the appropriate privilege level and be aware of any potential exceptions or performance implications related to restoring the machine state.


Summary: Stops instruction execution and enters a power-saving state (replaces nap/doze on P9+).

The thread is placed into power-saving mode and execution is stopped. The power-saving level that is entered is determined by the contents of the PSSCR. The thread remains in power-saving mode until either a System Reset exception or certain other events occur.

This instruction should not be executed in ultravisor state because that scenario may not be thoroughly verified. This instruction is privileged and context synchronizing.

PSSCR ← (PSSCR & ~0x3F) | power-saving-level
stop


Ultravisor Return from Interrupt Doubleword

Summary: Returns from an ultravisor interrupt.

The 'urfid' instruction is used to return from an interrupt in the ultravisor context. It updates the Machine State Register (MSR) and sets the next instruction address based on the values in USRR0 and USRR1.

If this instruction sets MSRPR to 1, it also sets MSREE, MSRIR, and MSRDR to 1. If this instruction sets MSRS HV PR to 0b110, it also sets MSRIR and MSRDR to 0.


Summary: Sets RT to 1 if CR bit is set, else 0. (Branchless logic).

Set register RT to 1 if the condition register bit identified by BI is set, else set RT to 0. This instruction provides a branchless way to materialize a boolean value from a condition register bit, useful for conditional assignment without branching.

if CR[BI] = 1 then
  RT ← 1
else
  RT ← 0

The setbc instruction is useful for conditionally setting a register based on the state of a specific bit in the Condition Register. Ensure that the correct bit index BI is specified to avoid unintended behavior. This instruction operates at user privilege level and does not generate exceptions under normal conditions.


Summary: Sets RT to 1 if CR bit is clear, else 0.

Set register RT to 1 if the condition register bit identified by BI is clear (0), else set RT to 0. This is the logical inverse of setbc, allowing branchless negation of a condition register bit test.

if CR[BI] = 0 then
  RT ← 1
else
  RT ← 0

The setbcr instruction is useful for setting a register based on the state of a specific bit in the Condition Register. Ensure that the correct bit index BI is specified to avoid unintended behavior. This instruction operates at user privilege level and does not generate exceptions under normal conditions.


Summary: Sets RT to -1 if CR bit is set, else 0.

Sets the target GPR to -1 (all bits set) if the specified condition register bit is set, otherwise sets it to 0. This instruction operates entirely on the CR and target register, with no side effects on other status fields.

Use setnbc to conditionally set a register based on a specific bit in the Condition Register. Ensure CRBI is within valid range; otherwise, results are undefined. This instruction operates at user privilege level and does not generate exceptions under normal conditions.


Summary: Sets RT to -1 if CR bit is clear, else 0.

Sets the target GPR to -1 (all bits set) if the specified condition register bit is clear, otherwise sets it to 0. This is the logical inverse of setnbc, with no side effects on other status fields.

Use setnbcr when you need to invert a condition bit in the Condition Register into a boolean value. Ensure that the target register RT is properly aligned and accessible. This instruction operates at user privilege level, so no special permissions are required. Be cautious of potential performance impacts if used in tight loops.


VSX Scalar Compare Exponents Double-Precision

Summary: Compares the exponents of two double-precision floating-point values in VSX registers and updates the condition register.

The exponent of src1 is compared with the exponent of src2. The result of the compare is placed into FPCC and CR field BF.

if MSR.VSX=0 then VSX_Unavailable()
src1 ←VSR[32×AX+A].dword[0]
src2 ←VSR[32×BX+B].dword[0]
src1.exponent ←EXTZ(src1.bit[1:11])
src1.fraction ←EXTZ(src1.bit[12:63])
src2.exponent ←EXTZ(src2.bit[1:11])
src2.fraction ←EXTZ(src2.bit[12:63])
src1.class.NaN ←(src1.exponent = 2047) & (src1.fraction != 0)
src2.class.NaN ←(src2.exponent = 2047) & (src2.fraction != 0)
lt_flag ←(src1.exponent < src2.exponent)
gt_flag ←(src1.exponent > src2.exponent)
eq_flag ←(src1.exponent = src2.exponent)
uo_flag ←src1.class.NaN | src2.class.NaN
CR.bit[4×BF+32] ←FPSCR.FL ←!uo_flag & lt_flag
CR.bit[4×BF+33] ←FPSCR.FG ←!uo_flag & gt_flag
CR.bit[4×BF+34] ←FPSCR.FE ←!uo_flag & eq_flag
CR.bit[4×BF+35] ←FPSCR.FU ←uo_flag

This instruction can be used to operate on single-precision source operands.


VSX Scalar Insert Exponent Double-Precision

Summary: Inserts exponent from one double into another.

Inserts the exponent bits from XB (bits 0-10) into the exponent field of the significand in XA, placing the result in XT. This operation constructs a double-precision floating-point value by combining a significand with a new exponent. Requires VSX support.

This instruction can be used to produce a single-precision result. Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.


VSX Scalar Extract Exponent Double-Precision

Summary: Extracts the exponent from a double-precision floating-point value in VSR and places it into GPR.

The instruction extracts the exponent field of a double-precision floating-point value located in the specified VSX register and stores it in a general-purpose register.

if MSR.VSX=0 then VSX_Unavailable()
src ←VSR[32×BX+B].dword[0]
GPR[RT] ←EXTZ64(src.bit[1:11])

This instruction can be used to operate on a single-precision source operand.


VSX Scalar Extract Significand Double-Precision

Summary: Extracts the significand of a double-precision floating-point value from a VSX register and places it into a general-purpose register.

Extracts the significand (mantissa) from a double-precision floating-point value in XB and places it as a 52-bit value into the lower half of XT, sign-extended. This instruction isolates the fractional part of the floating-point representation. Requires VSX support.


VSX Scalar Test Data Class Double-Precision

Summary: Tests the data class of a double-precision floating-point value in VSR[XB] and sets bits in CR field BF and FPCC accordingly.

The instruction tests the data class of the double-precision floating-point value in VSR[XB].dword[0] and sets bits in CR field BF and FPCC based on the result.

if MSR.VSX=0 then
    VSX_Unavailable()
src ← VSR[32×BX+B].dword[0]
exponent ← src.bit[1:11]
fraction ← src.bit[12:63]
class.NaN ← (exponent = 0x7FF) & (fraction != 0)
class.Infinity ← (exponent = 0x7FF) & (fraction = 0)
class.Zero ← (exponent = 0x000) & (fraction = 0)
class.Denormal ← (exponent = 0x000) & (fraction != 0)
match ←
    (DCMX.bit[0] & class.NaN) |
    (DCMX.bit[2] & class.Infinity & sign) |
    (DCMX.bit[3] & class.Zero & !sign) |
    (DCMX.bit[4] & class.Zero & sign) |
    (DCMX.bit[5] & class.Denormal & !sign) |
    (DCMX.bit[6] & class.Denormal & sign)
CR.bit[4×BF+32] ← FPSCR.FL ← src.sign
CR.bit[4×BF+33] ← FPSCR.FG ← 0b0
CR.bit[4×BF+34] ← FPSCR.FE ← match
CR.bit[4×BF+35] ← FPSCR.FU ← 0b0

This instruction is used to test the data class of a double-precision floating-point value. Ensure that VSX (Vector Scalar Extensions) is enabled in the MSR register, otherwise, an exception will be raised. The result updates both the CR and FPSCR registers, so check these for further processing. Be cautious with alignment; the source vector register must be properly aligned to avoid undefined behavior.


Summary: Loads a double quadword from memory into two VSX registers.

Loads a 256-bit (32-byte) aligned vector pair from memory at the effective address (RA + DQ), storing the first 128 bits into XT and the second 128 bits into XT+1. DQ is a 4-bit field that specifies the offset in units of 16 bytes, requiring 16-byte alignment. Requires VSX support.

For best performance, EA should be word-aligned.


Summary: Stores a pair of VSX vector registers to memory.

For stxvp, the effective address (EA) is the sum of the integer value in GPR[RA] or 0 if RA=0 and the value DQ||0b0000, sign-extended to 64 bits. The contents of VSR[XSp] concatenated with VSR[XSp+1] are stored into memory at address EA.

if MSR.VSX=0 then VSX_Unavailable()
EAbase ←(RA=0) ? 0 : GPR[RA]
EAdisp ←EXTS64(DQ || 0b0000)
EA ←EAbase + EAdisp
store_data.bit[128:255] ←VSR[32×SX+2×Sp+1]
MEM(EA,32) ←store_data


Summary: Loads a 256-bit vector pair with 34-bit offset.

Loads a 256-bit (32-byte) vector pair from memory using a 34-bit signed offset encoded as a 8-byte prefix + suffix. When R=0, the offset is relative to RA; when R=1, the offset is relative to the current instruction address. Requires VSX and Prefixed instruction support.

The plxvp instruction is used to load a pair of VSX vectors from memory into the VSRs. Ensure that the number of bytes specified in GPR[RB] does not exceed 16, as it will be clamped if it does. This instruction requires the VSX or Vector facility to be enabled in the MSR register, depending on the SX bit setting.


Summary: Stores a 256-bit vector pair with 34-bit offset.

Stores a 256-bit (32-byte) vector pair from XS and XS+1 to memory using a 34-bit signed offset encoded as a 8-byte prefix + suffix. When R=0, the offset is relative to RA; when R=1, the offset is relative to the current instruction address. Requires VSX and Prefixed instruction support.

The pstxvp instruction is used to store a VSX vector pair from the VSR registers to memory. It supports both prefixed and non-prefixed addressing modes. Ensure that the destination address is properly aligned for optimal performance. This instruction operates at privilege level 0.


VSX Scalar Convert Half-Precision to Double-Precision format XX2-form

Summary: Converts a half-precision floating-point value to a double-precision floating-point value.

The instruction converts the half-precision floating-point value in the rightmost halfword of doubleword element 0 of VSR[XB] to a double-precision floating-point value and places it into doubleword element 0 of VSR[XT]. Doubleword element 1 of VSR[XT] is set to 0.

if MSR.VSX=0 then VSX_Unavailable()
reset_flags()
src ←bfp_CONVERT_FROM_BFP16(VSR[BX×32+B].hword[3])
if src.class.SNaN=1 then
    result ←bfp64_CONVERT_FROM_BFP(bfp_QUIET(src))
else
    result ←bfp64_CONVERT_FROM_BFP(src)
vxsnan_flag ←src.class.SNaN
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
vex_flag ←FPSCR.VE & vxsnan_flag
if vex_flag=0 then do
    VSR[TX×32+T].dword[0] ←result
    VSR[TX×32+T].dword[1] ←0x0000_0000_0000_0000
    FPSCR.FPRF ←fprf_CLASS_BFP64(result)
end
FPSCR.FR ←0
FPSCR.FI ←0

Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.


VSX Scalar Convert Double to Half-Precision

Summary: Converts a double-precision floating-point value to a half-precision floating-point value with rounding.

Converts the double-precision floating-point value in XB to a half-precision floating-point value, placing the result in the lower half of XT. The conversion applies rounding according to the current floating-point rounding mode in FPSCR. Requires VSX support.

XT ← convert_to_half_precision(XB, round_mode=FPSCR[RN])

This instruction can be used to operate on a single-precision source operand. Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.


VSX Vector Convert Half-Precision to Single

Summary: Converts half-precision floating-point values in a vector register to single-precision floating-point values.

For xvcvhpsp, each half-precision floating-point value in the rightmost halfword of word element i of VSR[XB] is converted to a single-precision floating-point value and placed into word element i of VSR[XT].

if MSR.VSX=0 then VSX_Unavailable()
reset_flags()
ex_flag ← 0
for i from 0 to 3 do
    src ← bfp_CONVERT_FROM_BFP16(VSR[BX×32+B].word[i].hword[1])
    if src.class.SNaN = 1 then
        vresult.word[i] ← bfp32_CONVERT_FROM_BFP(bfp_QUIET(src))
        vxsnan_flag ← src.class.SNaN
        if vxsnan_flag = 1 then SetFX(FPSCR.VXSNAN)
        ex_flag ← ex_flag | (FPSCR.VE & vxsnan_flag)
    else
        vresult.word[i] ← bfp32_CONVERT_FROM_BFP(src)
    end
end
if ex_flag = 0 then VSR[32×TX+T] ← vresult

This instruction is used to convert half-precision floating-point values to single-precision. Ensure that the VSX feature is enabled in the MSR register. Handle exceptions by checking the FPSCR for VXSNAN and VE flags. The conversion respects NaN handling, converting signaling NaNs to quiet NaNs.


Vector Convert Single-Precision to Half-Precision format XX2-form

Summary: Converts each single-precision floating-point value in a vector register to half-precision and stores the result in another vector register.

For xvcvsphp, each integer value i from 0 to 3, do the following. Let src be the single-precision floating-point value in word element i of VSR[XB]. If src is an SNaN, the result is the half-precision representation of that SNaN converted to a QNaN. Otherwise, if src is a QNaN, the result is the half-precision representation of that QNaN. Otherwise, if src is an Infinity, the result is the half-precision representation of Infinity with the same sign as src. Otherwise, if src is a Zero, the result is the half-precision representation of Zero with the same sign as src. Otherwise, the result is the half-precision representation of src rounded to half-precision using the rounding mode specified by RN. The result is zero-extended and placed into word element i of VSR[XT]. If a trap-enabled exception occurs, VSR[XT] is not modified.

if MSR.VSX=0 then VSX_Unavailable()
reset_flags()
do i = 0 to 3
    src ←bfp_CONVERT_FROM_BFP32(VSR[BX×32+B].word[i])
    rnd ←bfp_ROUND_TO_BFP16(FPSCR.RN,src)
    vresult.word[i].hword[0] ←0x0000
    vresult.word[i].hword[1] ← bfp16_CONVERT_FROM_BFP(rnd)
    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    if ox_flag=1 then SetFX(FPSCR.OX)
    if ux_flag=1 then SetFX(FPSCR.UX)
    if xx_flag=1 then SetFX(FPSCR.XX)
ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.OE & ox_flag) | (FPSCR.UE & ux_flag) | (FPSCR.XE & xx_flag)
end
Let XT be the value 32×TX + T.
Let XB be the value 32×BX + B.

This instruction converts single-precision floating-point values to half-precision format, handling special cases like NaNs and infinities. Ensure VSX is enabled; otherwise, a VSX_Unavailable exception occurs. The result is zero-extended into the destination vector register. Be cautious of rounding modes specified by FPSCR.RN and exceptions that may set flags in FPSCR.


Summary: Ensures that all instructions preceding the sync instruction have completed before the sync instruction completes, and no subsequent instructions are initiated until after the sync instruction completes.

Synchronize memory operations as specified by L and SC fields; ensure prior instructions complete before this instruction completes; ensure subsequent instructions do not begin until this instruction completes.

Synchronizes memory operations by ensuring all instructions preceding the sync complete before the sync completes, and no subsequent instructions are initiated until after sync completes. The L field specifies the synchronization scope: L=0 (hwsync) enforces a heavy-weight synchronization across all storage types, while L=1 (lwsync) provides a lighter-weight barrier suitable for most memory ordering. The SC field (bits 9-10) controls store-caching-inhibited synchronization for specific storage classes. No condition or status registers are affected.

sync serves as both a basic and an extended mnemonic. The Assembler will recognize a sync mnemonic with two operands as the basic form, and a sync mnemonic with one operand or with no operand as an extended form.


Summary: Orders loads with loads, stores with stores, and loads with stores. Does NOT order stores with loads. (Encoded as sync 1).

Lightweight Sync. Extended mnemonic for SYNC (sync 1). Provides a lightweight memory synchronization barrier for ordering loads and stores without full heavyweight sync semantics.

Lightweight sync. Orders loads and stores before the barrier against loads and stores after it, but does not guarantee store-to-load ordering. Sufficient for producer-consumer patterns without data-dependent stores.


Summary: Returns from an interrupt handler. Restores PC from SRR0 and MSR from SRR1.

CIA ← SRR0; MSR ← SRR1; context is fully restored

Returns from an interrupt handler by restoring the Program Counter from SRR0 and the Machine State Register from SRR1. This is a privileged instruction that must be executed in Hypervisor or privileged state. Execution continues at the address loaded from SRR0 with the MSR value from SRR1, enabling recovery from exceptions and context restoration. No condition or status registers are affected; the entire processor state is restored from the saved registers.

If this instruction sets MSRPR to 1, it also sets MSREE, MSRIR, and MSRDR to 1. If this instruction results in MSRS HV PR being equal to 0b110, it also sets MSRIR and MSRDR to 0.


Translation Lookaside Buffer Invalidate Entry

Summary: Invalidates a TLB entry corresponding to the address in RB.

R

Effective R bit indicating whether to use the effective address or segment/page size information.

Invalidate TLB entry(ies) corresponding to address in RB, process ID in RS, controlled by RIC, PRS, and R fields; synchronization semantics depend on the radix MMU configuration.

Invalidates a translation lookaside buffer (TLB) entry corresponding to the effective address in RB. This privileged instruction allows selective invalidation controlled by the RIC (Radix Invalidation Control), PRS (Process Scoped), and R fields. The RS operand may contain a Process ID for process-scoped invalidations in radix MMU implementations. This instruction affects only the TLB state and does not modify condition or status registers.

The use of eﬀR in the RTL and verbal descriptions of tlbie[l] beginning in Version 3.1B of the architecture is a clarification of earlier architecture, not a functional change.


Segment Lookaside Buffer Invalidate Entry

Summary: Invalidates an SLB entry. Critical for memory management on Power systems.

if 'slbie' then
    RB0:35 ← (RB)0:35
    if, for SLB entry that translates or most recently translated ea,
        entry_class = (RB)36 and entry_seg_size = size specified in (RB)37:38,
        then for SLB entry (if any) that translates ea
            SLBEV ←0
            all other fields of SLBE ←undefined
    else
        s ←log_base_2(entry_seg_size)
        esid ←(RB)0:63-s
        u ←undefined 1-bit value
        if u then
            if an SLB entry translates esid
                SLBEV ←0
                all other fields of SLBE ←undefined

The instruction terminates any Segment Table walks being performed on behalf of the thread that executes it. The hardware ignores the contents of RB listed below, and software must set them to 0s.

slbie does not affect SLBs on other threads.
The class value specified by slbie must be the same as the Class value that is or was in the relevant SLB entry. The reason for this is that the hardware may use these values to optimize invalidation of implementation-specific lookaside information used in address translation. If the value specified by slbie differs from the value that is or was in the relevant SLB entry, these optimizations may produce incorrect results.
When switching tasks in certain cases, it may be advantageous to preserve some implementation-specific lookaside entries while invalidating others. The slbia instruction specifying IH value 0b001 or 0b011 can be used for this purpose if SLB class values are appropriately assigned.


Summary: Initiates a hardware transaction. If the transaction fails, execution rolls back to this point. Sets CR0 based on success/failure.

Rollback Handler (0=External, 1=Internal)

if transaction initiated successfully then CR0[EQ] ← 1 else CR0[EQ] ← 0; CR0[LT,GT,SO] set based on abort cause; transaction state is active

Initiates a hardware transaction, setting the transaction active state and recording checkpoint information. If execution completes successfully within the transaction, tbegin. sets CR0[EQ] = 1; if the transaction is aborted, execution rolls back to this instruction and CR0[EQ] = 0, with CR0[SO] indicating the abort cause. The R field determines whether a transaction failure causes an external rollback (R=0) or an internal retry (R=1). Requires Transactional Memory (TM) facility support.

In synthetic TM mode, transactions initiated by tbegin will fail immediately, invoking the failure handler. Ensure that your application logic correctly handles transaction failures to maintain data integrity.


Summary: Commits the current hardware transaction. If successful, memory changes become visible atomically.

Transaction End. Ends the current transaction. If A=1 (All), ends all nested transactions. On success the memory updates made in the transaction become visible. On failure a non-transactional abort occurs.

Use `tend` to end a transaction, making its changes permanent if successful. If an error occurs, it triggers a non-transactional abort. Ensure all nested transactions are properly managed when using the A=1 option.


Summary: Forces a transaction failure and rollback.

Abort transaction; rollback to most recent tbegin.; CR0[EQ] ← 0; CR0[SO] ← 1; TEXASR abort code ← RA

Forces an abort of the current hardware transaction, rolling back all transactional state and returning control to the point of the most recent tbegin. The RA operand contains the abort code (or a register holding the code) that is reflected in TEXASR. CR0 is set to indicate transaction failure, with CR0[SO] holding abort status. This instruction requires Transactional Memory facility support and can only be executed within a transaction.

Use tabort to explicitly abort a transaction and discard all changes. Ensure this is called within a transactional region; otherwise, it will raise an exception. Check CR0 for transaction status before or after calling tabort.


Summary: Performs one round of AES encryption (SubBytes, ShiftRows, MixColumns, AddRoundKey).

VRA

Source Vector Register containing the intermediate state array

VRB

Source Vector Register containing the round key

if MSR.VEC=0 then
    Vector_Unavailable()
State ←VSR[VRA+32]
RoundKey ←VSR[VRB+32]
vtemp1 ←SubBytes(State)
vtemp2 ←ShiftRows(vtemp1)
vtemp3 ←MixColumns(vtemp2)
VSR[VRT+32] ←vtemp3 ⊕ RoundKey

The instruction performs one round of the AES cipher operation on the intermediate State array, sequentially applying the transforms SubBytes(), ShiftRows(), MixColumns(), and AddRoundKey() as defined in FIPS-197. The result is placed into VSR[VRT+32], representing the new intermediate state of the cipher operation.

The vcipher instruction performs a single AES cipher round, requiring the Vector Facility to be enabled. Ensure that the VRA and VRB registers point to the correct intermediate state and round key in vector storage registers. The result is stored in VSR[VRT+32]. This instruction operates at the user privilege level and will raise an exception if the Vector Facility is not available.


Summary: Performs one round of an AES inverse cipher operation on the intermediate state array.

if MSR.VEC=0 then
    Vector_Unavailable()
State ← VSR[VRA+32]
RoundKey ← VSR[VRB+32]
vtemp1 ← InvShiftRows(State)
vtemp2 ← InvSubBytes(vtemp1)
vtemp3 ← vtemp2 ⊕ RoundKey
VSR[VRT+32] ← InvMixColumns(vtemp3)

The instruction performs one round of an AES inverse cipher operation, sequentially applying the transforms InvShiftRows(), InvSubBytes(), AddRoundKey(), and InvMixColumns() to the intermediate State array.

This instruction is used to perform a single round of the AES inverse cipher, which includes operations like InvShiftRows, InvSubBytes, AddRoundKey, and InvMixColumns. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The input state and round key must be correctly loaded into the appropriate vector registers (VRA+32 and VRB+32), respectively, and the result will be stored in VRT+32. This operation is typically used in cryptographic algorithms that require AES decryption.


Summary: Performs the Sigma0/Sigma1/sigma0/sigma1 functions for SHA-256.

Performs one of the four SHA-256 sigma functions (Sigma0, Sigma1, sigma0, or sigma1) on each 32-bit word in the source vector and stores the result in the destination vector. The ST field selects between Sigma-type and sigma-type operations, and SIX selects the specific operation. This is a Vector Crypto instruction that operates on four 32-bit elements in parallel within a 128-bit vector register. No condition or status registers are affected.

The vshasigmaw instruction is used to perform SHA-256 sigma or sigma-like functions on vector register elements. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. The instruction operates on each 32-bit word of the source vector, applying different bitwise rotations and XORs based on the ST and SIX fields. This instruction requires supervisor privilege level to execute.


Summary: Loads a byte from memory into a register, zeroing the upper bits of the target register, and updates the base address register.

The effective address (EA) is calculated as the sum of the contents of register RA and the sign-extended displacement D. The byte at EA is loaded into RT56:63, with RT0:55 set to zero. The EA is then stored back into RA.

EA ← (RA) + EXTS(D)
RT ← 560 || MEM(EA, 1)
RA ← EA

The base register (RA) is updated with the effective address after the memory access. RA must not be 0 and must differ from the destination register; violating this constraint produces undefined results.


Load Halfword and Zero with Update D-form

Summary: Loads a halfword from memory into a register, zero-extends it to 64 bits, and updates the base address.

The effective address (EA) is calculated as the sum of the contents of register RA and the sign-extended displacement D. The halfword at EA is loaded into RT48:63, with RT0:47 set to zero. The EA is then placed back into RA.

EA ← (RA) + EXTS(D)
RT ← 480 || MEM(EA, 2)
RA ← EA


Summary: Stores a doubleword from a register to memory and updates the base address register.

Stores a 64-bit doubleword from register RS to memory at the address computed from RA plus the sign-extended displacement, then updates RA with the effective address. The displacement is a 14-bit signed value (DS field), scaled by 8 to form a byte offset. This instruction is commonly used in prologue/epilogue code to allocate/deallocate stack space while storing values. No condition or status registers are affected.

EA ← (RA) + EXTS(DS || 0b00); M[EA:EA+7] ← (RS); RA ← EA


Summary: Multiplies the contents of a register by an immediate value and places the low-order 32 bits of the product into another register.

The 64-bit first operand is (RA). The 64-bit second operand is the sign-extended value of the SI field. The low-order 32 bits of the 128-bit product of the operands are placed into register RT.

prod0:127 ← (RA) × EXTS(SI)
RT ← prod64:127

For mulli and mullw, the low-order 32 bits of the product are the correct 32-bit product for 32-bit mode.


Summary: Adds the contents of two registers and generates sixes based on carry bits.

Adds the values in registers RA and RB, then replaces each nibble (4-bit group) of the result with 0x6 if a carry was generated from that nibble, otherwise the low 4 bits of the sum are preserved. This instruction is used in decimal arithmetic for BCD (Binary Coded Decimal) addition to generate correction factors. No condition or status registers are affected, and the Rc bit is not available (non-dot form only).

sum ← (RA) + (RB); for i = 0 to 15: if carry_from_nibble(i) then RT[4i:4i+3] ← 0x6 else RT[4i:4i+3] ← sum[4i:4i+3]

addg6s can be used to add or subtract two BCD operands. In these examples it is assumed that r0 contains 0x666...666. (BCD data formats are described in Section 5.3.)


Summary: Loads a single-precision floating-point value from memory into a floating-point register and converts it to double precision.

Loads a single-precision floating-point value from memory at address RA+D, converts it to double precision, and stores the result in FRT. This instruction is part of the Floating-Point category and does not affect condition registers or the XER.

EA ← (RA = 0 ? 0 : GPR(RA)) + EXTS(D)
FPR(FRT) ← ConvertSingleToDouble([EA])

The lfs extended mnemonic permits computing an effective address as a Load or Store instruction would, but loads the address itself into a GPR rather than loading the value that is in storage at that address.


Load Floating-Point Single with Update Indexed

Summary: Loads a floating-point single-precision operand from memory into a register and updates the base address.

The word in storage addressed by EA is interpreted as a floating-point single-precision operand. This word is converted to floating-point double format (see page 149) and placed into register FRT. The effective address (EA) is the sum of RA and D, and EA is placed into register RA.

EA ← (RA) + EXTS(D)
FRT ← DOUBLE(MEM(EA, 4))
RA ← EA
if RA=0 then
    the instruction form is invalid


Summary: Loads a doubleword from memory into a floating-point register and updates the base address register.

The doubleword in storage addressed by EA is loaded into register FRT. The effective address (EA) is the sum of the contents of register RA, or the value 0 if RA=0, and the value D, sign-extended to 64 bits. If RA=0, the instruction form is invalid.

if RA = 0 then
    b ← 0
else
    b ← (RA)
EA ← b + EXTS(D)
FRT ← MEM(EA, 8)
RA ← EA


Store Floating-Point Single Indexed X-form

Summary: Stores a single-precision floating-point value from a register to memory using an indexed address.

The contents of register FRS are converted to single format and stored into the word in storage addressed by EA, which is the sum of RA (or RA|0) and RB. If RA is not zero, it is used directly; otherwise, b is set to zero.

if RA = 0 then
    b ← 0
else
    b ← (RA)
EA ← b + (RB)
MEM(EA, 4) ← SINGLE((FRS))

The stfsx instruction stores a single-precision floating-point value from register FRS to memory. Ensure that the base address (RA or RA|0) and offset (RB) are correctly aligned for optimal performance. If RA is zero, the effective address is solely determined by RB; otherwise, it's the sum of RA and RB. This instruction operates at user privilege level.


Store Floating-Point Double with Update Indexed

Summary: Stores the contents of a floating-point register into memory and updates the base address register.

The contents of register FRS are stored into the double-word in storage addressed by EA. The effective address (EA) is the sum of the contents of registers RA and RB. If RA=0, the instruction form is invalid. EA is placed back into register RA.

if RA = 0 then
    b ← 0
else
    b ← (RA)
EA ← b + (RB)
MEM(EA, 8) ← (FRS)
RA ← EA


Summary: Stores the contents of two floating-point registers into memory as a doubleword pair.

The instruction stores the contents of the even-numbered register of FRSp into the doubleword in storage addressed by EA, and the contents of the odd-numbered register of FRSp into the doubleword in storage addressed by EA+8.

if RA = 0 then
    b ← 0
else
    b ← (RA)
EA ← b + EXTS(DS || 0b00)
MEM(EA, 8) ← FRSpeven
MEM(EA+8, 8) ← FRSpodd

The stfdp instruction is commonly used to store two consecutive double-precision floating-point numbers from the FPSCR into memory. Ensure that the base address (EA) is properly aligned to an 8-byte boundary to avoid alignment exceptions. This instruction operates at user privilege level and will raise a program interrupt if attempting to access protected memory.


Summary: Merges the even words from two floating-point registers into a third.

The contents of word element 0 of FPR[FRA] are placed into word element 0 of FPR[FRT], and the contents of word element 0 of FPR[FRB] are placed into word element 1 of FPR[FRT].

if MSR.FP=0 then
    FP_Unavailable()
FPR[FRT].word[0] ← FPR[FRA].word[0]
FPR[FRT].word[1] ← FPR[FRB].word[0]

fmrgew and fmrgow are provided to support direct move operations in 32-bit mode.


Summary: Rounds the floating-point operand in register FRB to an integral value using the rounding mode round to nearest.

The floating-point operand in register FRB is rounded to an integral value as follows, with the result placed into register FRT. If the sign of the operand is positive, (FRB) + 0.5 is truncated to an integral value, otherwise (FRB) - 0.5 is truncated to an integral value.

if 'frin' then
    if (FRB) >= 0 then
        FRT <- truncate((FRB) + 0.5)
    else
        FRT <- truncate((FRB) - 0.5)

FPSCR, (FPRF, FX, VXSNAN), FPSCR, (FR, FI), CR1, (if, Rc=1), CR0

These instructions set FR and FI to 0b00 regardless of whether the result is inexact or rounded because there is a desire to preserve the value of XX.


Summary: Moves control bits from FPSCR to a register and sets the DRN field.

The contents of the control bits in the FPSCR, that is, bits 29:31 (DRN) and bits 56:63 (VE, OE, UE, ZE, XE, NI, RN), are placed into the corresponding bits in register FRT. All other bits in register FRT are set to 0. The contents of bits 29:31 of the FPSCR (DRN) are set to the value of FRB.

mffscdrn permits software to simultaneously read control bits in the FPSCR and set the DRN field without the higher latency typically associated with accessing the status bits.


Summary: Compares the exponent values of two DFP operands and updates CR field BF and FPCC.

The exponent value (Ea) of the DFP operand in FRA is compared to the exponent value (Eb) of the DFP operand in FRB. The result of the compare is placed into CR field BF and the FPCC.

FRA

First Source DFP Floating-Point Register

FRB

Second Source DFP Floating-Point Register

Ea ← exponent of DFP operand in FRA
Eb ← exponent of DFP operand in FRB
if (FRA is F) and (FRB is F) then
    if Ea < Eb then CR_BF || FPCC ← 0b1000
    else if Ea > Eb then CR_BF || FPCC ← 0b0100
    else CR_BF || FPCC ← 0b0010
else if (FRA is ∞) and (FRB is ∞) then CR_BF || FPCC ← 0b0010
else if (FRA is QNaN or SNaN) and (FRB is QNaN or SNaN) then CR_BF || FPCC ← 0b0010
else CR_BF || FPCC ← 0b0001

The dtstex instruction compares the exponents of two DFP operands and sets the condition register field BF and floating-point status and control register (FPSCR) FPCC based on the comparison. Ensure that both operands are properly aligned and valid; otherwise, the instruction may raise exceptions. This instruction is useful for sorting or filtering operations where exponent values need to be compared.


Summary: Rounds a decimal floating-point value to the specified number of significant digits.

Rounds a decimal floating-point value in FRB to the number of significant digits specified in FRA, using the rounding mode in RMC, and stores the result in FRT. This instruction is part of the Decimal Floating-Point category. The Rc bit controls whether the condition register CR1 is updated with FPCC and exception flags.

FRA

Source Floating-Point Register containing the reference significance

FRB

Source Floating-Point Register containing the value to be rounded

k ← DecimalSignificance(FRA)
FPR(FRT) ← RoundDecimal(FRB, k, RMC)
if Rc = 1 then CR1 ← FPCC || FPSCR[OX,UX,ZX,XX]

FPSCR, (FPRF, FR, FI, FX, XX), VXSNAN, VXCVI, CR0

DFP Reround can be used to adjust a DFP value to have no more than a specified number of significant digits. The result is right-justified and rounded as specified by RMC.


Decimal Floating-Point Round To FP Integer With Inexact

Summary: Rounds a decimal floating-point number to the nearest integer and places it into a floating-point register.

The DFP operand in FRB is rounded to a floating-point integer and placed into FRT. The sign of the result is the same as the sign of the operand in FRB. The ideal exponent is the larger value of zero and the exponent of the operand in FRB. The rounding mode used is specified by RMC.

if 'drintx' then
    FRT <- round(FRB, RMC)
    if result differs from FRB then
        raise inexact exception

FPSCR, (FPRF, FR, FI, FX, XX), VXSNAN, CR1, (if, Rc=1), CR0

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.


Decimal Floating-Point Round To FP Integer Without Inexact

Summary: Rounds a decimal floating-point number to an integer without recognizing an inexact exception.

This operation rounds the value in FRB to an integer using the specified rounding mode (RMC) and places the result in FRT. It does not recognize an inexact exception.

if 'drintn' then
    FRT <- Round(FRB, RMC)
    FI <- 0
    FR <- 0
    VXSNAN <- 0
    if Rc=1 then
        CR1 <- ClassAndSign(FRT)
else if 'drintn.' then
    FRT <- Round(FRB, RMC)
    FI <- 0
    FR <- 0
    VXSNAN <- 0
    CR1 <- ClassAndSign(FRT)

FPSCR, (FPRF, FX, VXSNAN), FPSCR, (FR, FI), CR1, CR0

The DFP Round To FP Integer Without Inexact and DFP Round To FP Integer Without Inexact Quad instructions can be used to implement decimal equivalents of several C99 rounding functions by specifying the appropriate R and RMC field values.


Summary: Loads a byte from memory into a vector register element.

Loads a single byte from memory at address RA+RB and stores it in the rightmost byte of a vector register element in VRT, with zero padding in remaining bytes. This instruction is part of the VMX (AltiVec) category and does not update condition registers.

EA ← (RA = 0 ? 0 : GPR(RA)) + GPR(RB)
byte_index ← EA[28:31]
VRT ← (0x00000000000000 || [EA & ~0x3])
VRT[byte_index] ← [EA]

The Load Vector Element instructions load the specified element into the same location in the target register as the location into which it would be loaded using the Load Vector instruction.


Summary: Loads a word from memory into a vector register element.

Loads a word (32 bits) from memory at address RA+RB (aligned to 4-byte boundary) and stores it in a vector register element in VRT, with zero padding in remaining doublewords. This instruction is part of the VMX (AltiVec) category and does not update condition registers.

The lvewx instruction loads a word from memory into a vector register element. Ensure the effective address is aligned to a 4-byte boundary by ANDing with 0xFFFF_FFFF_FFFF_FFFC. This instruction requires the VEC bit in the MSR to be set; otherwise, it raises a Vector_Unavailable exception. Be aware of endianness when placing the byte into the vector register.


Summary: Stores a byte element from a vector register into memory.

Stores the byte element from vector register VRS at the position determined by the effective address RA+RB into memory. This instruction is part of the VMX (AltiVec) category and does not update condition registers.

EA ← (RA = 0 ? 0 : GPR(RA)) + GPR(RB)
byte_index ← EA[28:31]
[EA] ← VRS[byte_index]

Unless bits 60:63 of the address are known to match the byte offset of the subject byte element in VSR[VRS+32], software should use Vector Splat to splat the subject byte element before performing the store.


Summary: Loads a vector pattern suitable for shifting left indexed.

Creates a shift-left permutation pattern based on the effective address (RA+RB) modulo 16 and loads it into VRT. This instruction is part of the VMX (AltiVec) category and is typically used to set up permutation vectors for unaligned vector loads. It does not update condition registers.

EA ← (RA = 0 ? 0 : GPR(RA)) + GPR(RB)
shift_amount ← EA[28:31]
VRT ← PermutationPattern(shift_amount, "shift_left")

The lvsl instruction can be used to create a permute control vector for vperm instructions. It is useful for loading and storing unaligned data, as well as rotating or shifting the contents of a VSR.


Vector Pack Signed Doubleword Signed Saturate

Summary: Packs signed doublewords from two vector registers into a single vector register with signed saturation.

The instruction packs the contents of VSR[VRA+32] and VSR[VRB+32] into VSR[VRT+32], saturating signed values if they exceed the range of a 32-bit integer.

if MSR.VEC=0 then
    Vector_Unavailable()
for i from 0 to 3 do
    VSR[VRT+32].word[i] ← si32_CLAMP(EXTS(VSR[VRA+32].dword[i]))
    if value > 2^31 - 1 then
        SAT is set to 1
    else if value < -(2^31) then
        SAT is set to 1

This instruction is useful for packing two 64-bit signed integers into a single 128-bit vector, with saturation applied to handle overflow. Ensure that the input vectors are correctly aligned and that the VSCR.SAT flag is checked after execution to determine if any values were saturated. This operation requires vector processing privileges.


Summary: Unpacks the high signed words from a vector register into a doubleword format.

Unpacks the two high-order signed 32-bit words from vector register VRB into two signed 64-bit doublewords in VRT, sign-extending each word. This instruction is part of the VMX (AltiVec) category and does not update condition registers.

This instruction is used to extract the high signed word from each vector element of VRB and store it in the corresponding doubleword element of VRT. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector Unavailable exception will be raised. The operation is performed on 32-bit elements, so alignment requirements are based on these boundaries.


Vector Shift Left Double by Bit Immediate

Summary: Shifts the contents of two vector registers left by a specified number of bits and places the result into another vector register.

The contents of VSR[VRA+32] concatenated with the contents of VSR[VRB+32] are shifted left by SH bits. The result is placed into VSR[VRT+32].

if MSR.VEC=0 then
    Vector_Unavailable()
vsrc.qword[0] ← VSR[VRA+32]
vsrc.qword[1] ← VSR[VRB+32]
VSR[VRT+32] ← vsrc.bit[SH:SH+127]

This instruction is used to perform a left shift on the concatenated contents of two vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The shift amount (SH) must be within the range of 0 to 127 bits. Be cautious with alignment as the operation involves concatenating and shifting double quadword values.