{ "architecture": "PTX", "instructions": [ { "id": "ptx.abs", "mnemonic": "abs", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Absolute Value", "category": "Arithmetic", "summary": "Compute the absolute value of a signed or floating-point operand.", "syntax": "abs.type d, a;", "syntax_forms": [ { "syntax": "abs.type d, a;", "description": "Absolute value.", "dataTypes": [ "s16", "s32", "s64", "f32", "f64" ], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [ "f32", "f64", "s16", "s32", "s64" ], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" } ], "semantics": "d = |a|.", "examples": "abs.s32 r0,a;\n\nabs.ftz.f32 x,f0;\n\nabs.ftz.f16 x,f0;\nabs.bf16 x,b0;\nabs.bf16x2 x1,b1;", "description": "Take absolute value of a and store the result in d.\nFor.f16x2 and.bf16x2 instruction type, forms input vector by extracting half word values\nfrom the source operand. Absolute values of half-word operands are then computed in parallel to\nproduce.f16x2 or.bf16x2 result in destination.\nFor.f16 instruction type, operands d and a have.f16 or.b16 type. For.f16x2 instruction type, operands d and a have.f16x2 or.b32 type. For.bf16 instruction type, operands d and a have.b16 type. For.bf16x2 instruction\ntype, operands d and a have.b32 type.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#half-precision-floating-point-instructions-abs", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.activemask", "mnemonic": "activemask", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Active Mask", "category": "Parallel Synchronization and Communication Instructions", "summary": "Query the bitmask of currently active (converged) lanes in the executing warp.", "syntax": "activemask.b32 d;", "syntax_forms": [ { "syntax": "activemask.b32 d;", "description": "Reads the current active-lane mask with no side effects and no synchronization.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_30" ], "introducedIn": "PTX ISA 6.2" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register receiving the active-lane bitmask" } ], "semantics": "d = bitmask of lanes currently active/converged at this point in the warp.", "examples": "activemask.b32 %r1;", "description": "activemask queries predicated-on active threads from the executing warp and sets the destination d with 32-bit integer mask where bit position in the mask corresponds to the thread’s laneid.\nDestination d is a 32-bit destination register.\nAn active thread will contribute 1 for its entry in the result and exited or inactive or\npredicated-off thread will contribute 0 for its entry in the result.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-activemask", "introducedIn": "PTX ISA 6.2", "requiredTargets": [ "sm_30" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.add", "mnemonic": "add", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Add", "category": "Arithmetic", "summary": "Add two operands of the same type, with optional saturation for signed 32-bit integers.", "syntax": "add.type d, a, b;", "syntax_forms": [ { "syntax": "add.type d, a, b;", "description": "Generic add across integer and floating-point types.", "dataTypes": [ "s16", "s32", "s64", "u16", "u32", "u64", "f32", "f64", "f16", "f16x2", "bf16", "bf16x2" ], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" }, { "syntax": "add.sat.s32 d, a, b;", "description": "Signed 32-bit add with saturation on overflow instead of wraparound.", "dataTypes": [ "s32" ], "stateSpaces": [], "scopes": [], "modifiers": [ "sat" ], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [ "bf16", "bf16x2", "f16", "f16x2", "f32", "f64", "s16", "s32", "s64", "u16", "u32", "u64" ], "stateSpaces": [], "scopes": [], "modifiers": [ "sat" ], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "First source operand" }, { "name": "b", "desc": "Second source operand" } ], "semantics": "d = a + b, evaluated at the selected type's width.", "examples": "@p add.u32 x,y,z;\n add.sat.s32 c,c,1;\n add.u16x2 u,v,w;\n add.s8x4.sat p, q, r;\n\n@p add.rz.ftz.f32 f1,f2,f3;\nadd.rp.ftz.f32x2 d, a, b;\n\n// scalar f16 additions\nadd.f16 d0, a0, b0;\nadd.rn.f16 d1, a1, b1;\nadd.bf16 bd0, ba0, bb0;\nadd.rn.bf16 bd1, ba1, bb1;\n// (truncated - see the official PTX ISA docs for the full example)\n\n.reg .f32 fc, fd;\n.reg .b16 ba;\nadd.rz.f32.bf16.sat fd, fa, fc;", "description": "Performs addition and writes the resulting value into a destination register.\nFor.u16x2,.s16x2 instruction types, forms input vectors by half word values from source\noperands. Half-word operands are then added in parallel to produce.u16x2,.s16x2 result in\ndestination.\nFor.u8x4,.s8x4 instruction types, forms input vectors by quarter word values from source\noperands. Quarter-word operands are then added in parallel to produce.u8x4,.s8x4 result\nin destination.\nOperands d, a and b have the same type as the instruction type. For instruction types.u16x2,.s16x2,.u8x4,.s8x4, operands d, a and b have type.b32.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#integer-arithmetic-instructions-add", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.add.cc", "mnemonic": "add.cc", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "add.cc", "category": "Extended-Precision Integer Arithmetic Instructions", "summary": "Performs integer addition and writes the carry-out value into the condition code register.", "syntax": "add.cc.type d, a, b;", "syntax_forms": [ { "syntax": "add.cc.type d, a, b;", "description": "Performs integer addition and writes the carry-out value into the condition code register.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 1.2" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" }, { "name": "b", "desc": "Source operand" } ], "semantics": "d = a + b;", "examples": "@p add.cc.u32 x1,y1,z1; // extended-precision addition of\n@p addc.cc.u32 x2,y2,z2; // two 128-bit values\n@p addc.cc.u32 x3,y3,z3;\n@p addc.u32 x4,y4,z4;", "description": "Performs integer addition and writes the carry-out value into the condition code register.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#extended-precision-arithmetic-instructions-add-cc", "introducedIn": "PTX ISA 1.2", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.addc", "mnemonic": "addc", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "addc", "category": "Extended-Precision Integer Arithmetic Instructions", "summary": "Performs integer addition with carry-in and optionally writes the carry-out value into the condition\ncode register.", "syntax": "addc{.cc}.type d, a, b;", "syntax_forms": [ { "syntax": "addc{.cc}.type d, a, b;", "description": "Performs integer addition with carry-in and optionally writes the carry-out value into the condition\ncode register.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 1.2" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" }, { "name": "b", "desc": "Source operand" } ], "semantics": "d = a + b + CC.CF;", "examples": "@p add.cc.u32 x1,y1,z1; // extended-precision addition of\n@p addc.cc.u32 x2,y2,z2; // two 128-bit values\n@p addc.cc.u32 x3,y3,z3;\n@p addc.u32 x4,y4,z4;", "description": "Performs integer addition with carry-in and optionally writes the carry-out value into the condition\ncode register.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#extended-precision-arithmetic-instructions-addc", "introducedIn": "PTX ISA 1.2", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.alloca", "mnemonic": "alloca", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "alloca", "category": "Stack Manipulation Instructions", "summary": "The alloca instruction dynamically allocates memory on the stack frame of the current function and updates the stack pointer accordingly.", "syntax": "alloca.type ptr, size{, immAlign};", "syntax_forms": [ { "syntax": "alloca.type ptr, size{, immAlign};", "description": "The alloca instruction dynamically allocates memory on the stack frame of the current function\nand updates the stack pointer accordingly. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_52" ], "introducedIn": "PTX ISA 7.3" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": "alloca.type ptr, size, immAlign:\n\na = max(immAlign, frame_align); // frame_align is the minimum guaranteed alignment\n\n// Allocate size bytes of stack memory with alignment a and update the stack pointer.\n// Since the stack grows down, the updated stack pointer contains a lower address.\nstackptr = alloc_stack_mem(size, a);\n\n// Return the new value of stack pointer as ptr. Since ptr is the lowest address of the memory\n// allocated by alloca, the memory can be accessed using ptr up to (ptr + size of allocated memory).\nstacksave ptr;", "examples": ".reg .u32 ra, stackptr, ptr, size;\n\nstacksave.u32 stackptr; // Save the current stack pointer\nalloca ptr, size, 8; // Allocate stack memory\nst.local.u32 [ptr], ra; // Use the allocated stack memory\nstackrestore.u32 stackptr; // Deallocate memory by restoring the stack pointer", "description": "The alloca instruction dynamically allocates memory on the stack frame of the current function\nand updates the stack pointer accordingly. The returned pointer ptr points to local memory and\ncan be used in the address operand of ld.local and st.local instructions.\nIf sufficient memory is unavailable for allocation on the stack, then execution of alloca may\nresult in stack overflow. In such cases, attempting to access the allocated memory with ptr will\nresult in undefined program behavior.\nThe memory allocated by alloca is deallocated in the following ways:\nIt is automatically deallocated when the function exits. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#stack-manipulation-instructions-alloca", "introducedIn": "PTX ISA 7.3", "requiredTargets": [ "sm_52" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.and", "mnemonic": "and", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Bitwise AND", "category": "Logic and Shift Instructions", "summary": "Bitwise AND of two operands.", "syntax": "and.type d, a, b;", "syntax_forms": [ { "syntax": "and.type d, a, b;", "description": "Bitwise AND, including a predicate form.", "dataTypes": [ "b16", "b32", "b64", "pred" ], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [ "b16", "b32", "b64", "pred" ], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "First operand" }, { "name": "b", "desc": "Second operand" } ], "semantics": "d = a & b (bitwise).", "examples": "and.b32 x,q,r;\nand.b32 sign,fpvalue,0x80000000;", "description": "Compute the bit-wise and operation for the bits in a and b.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#logic-and-shift-instructions-and", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.applypriority", "mnemonic": "applypriority", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "applypriority", "category": "Data Movement and Conversion Instructions", "summary": "The applypriority instruction applies the cache eviction priority specified by the.level::eviction_priority qualifier to the address range [a..a+size)", "syntax": "applypriority{.global}.level::eviction_priority [a], size;", "syntax_forms": [ { "syntax": "applypriority{.global}.level::eviction_priority [a], size;", "description": "The applypriority instruction applies the cache eviction priority specified by the.level::eviction_priority qualifier to the address range [a..a+size) in the specified cache\nlevel. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_80" ], "introducedIn": "PTX ISA 7.4" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "applypriority.global.L2::evict_normal [ptr], 128;", "description": "The applypriority instruction applies the cache eviction priority specified by the.level::eviction_priority qualifier to the address range [a..a+size) in the specified cache\nlevel.\nIf no state space is specified then Generic Addressing is\nused. If the specified address does not fall within the address window of.global state space\nthen the behavior is undefined.\nThe operand size is an integer constant that specifies the amount of data, in bytes, in the\nspecified cache level on which the priority is to be applied. The only supported value for the size operand is 128.\nSupported addressing modes for operand a are described in Addresses as Operands. a must be aligned to 128 bytes.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-applypriority", "introducedIn": "PTX ISA 7.4", "requiredTargets": [ "sm_80" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.atom", "mnemonic": "atom", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Atomic Read-Modify-Write", "category": "Parallel Synchronization and Communication Instructions", "summary": "Atomically read-modify-write a memory location and return the prior value.", "syntax": "atom.space.op.type d, [a], b;", "syntax_forms": [ { "syntax": "atom.space.op.type d, [a], b;", "description": "Atomic operation; op selects the read-modify-write function.", "dataTypes": [ "b32", "b64", "s32", "u32", "u64", "f32", "f64" ], "stateSpaces": [ "global", "shared" ], "scopes": [], "modifiers": [ "add", "min", "max", "and", "or", "xor", "exch", "cas", "inc", "dec" ], "requiredTargets": [ "sm_11" ], "introducedIn": "PTX ISA 1.1" } ], "dataTypes": [ "b32", "b64", "f32", "f64", "s32", "u32", "u64" ], "stateSpaces": [ "global", "shared" ], "scopes": [], "modifiers": [ "add", "and", "cas", "dec", "exch", "inc", "max", "min", "or", "xor" ], "operands": [ { "name": "d", "desc": "Destination register (receives the pre-operation value)" }, { "name": "a", "desc": "Memory address" }, { "name": "b", "desc": "Operand value" } ], "semantics": "d = *a; *a = op(*a, b); indivisible with respect to other threads targeting the same address.", "examples": "atom.global.add.s32 d,[a],1;\natom.shared::cta.max.u32 d,[x+4],0;\n@p atom.global.cas.b32 d,[p],my_val,my_new_val;\natom.global.sys.add.u32 d, [a], 1;\natom.global.acquire.sys.inc.u32 ans, [gbl], %r0;\natom.add.noftz.f16x2 d, [a], b;\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Atomically loads the original value at location a into destination register d, performs a\nreduction operation with operand b and the value in location a, and stores the result of the\nspecified operation at location a, overwriting the original value. For the.cas (compare-and-swap)\noperation, operand b is the compare value and operand c is the swap value. The operation\ncompares the value at location a with operand b; if they are equal, it stores operand c at location a, otherwise it leaves the value at location a unchanged. Operand a specifies a\nlocation in the specified state space. If no state space is given, perform the memory accesses using Generic Addressing. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-atom", "introducedIn": "PTX ISA 1.1", "requiredTargets": [ "sm_11" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.bar.cta", "mnemonic": "bar.cta", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "bar.cta", "category": "Parallel Synchronization and Communication Instructions", "summary": "Performs barrier synchronization and communication within a CTA.", "syntax": "bar.cta.sync a{, b};", "syntax_forms": [ { "syntax": "bar.cta.sync a{, b};", "description": "Performs barrier synchronization and communication within a CTA. Each CTA instance has sixteen\nbarriers numbered 0..15.\nbarrier{. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "// Use bar.sync to arrive at a pre-computed barrier number and\n// wait for all threads in CTA to also arrive:\n st.shared [r0],r1; // write my result to shared memory\n bar.cta.sync 1; // arrive, wait for others to arrive\n ld.shared r2,[r3]; // use shared results from other threads\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Performs barrier synchronization and communication within a CTA. Each CTA instance has sixteen\nbarriers numbered 0..15.\nbarrier{.cta} instructions can be used by the threads within the CTA for synchronization and\ncommunication.\nOperands a, b, and d have type.u32; operands p and c are predicates. Source\noperand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15. Operand b specifies the number of threads participating in the barrier. If\nno thread count is specified, all threads in the CTA participate in the barrier. When specifying a\nthread count, the value must be a multiple of the warp size. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-bar", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.bar.warp.sync", "mnemonic": "bar.warp.sync", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "bar.warp.sync", "category": "Parallel Synchronization and Communication Instructions", "summary": "bar.warp.sync will cause executing thread to wait until all threads corresponding to membermask have executed a bar.warp.sync with the same membermask value before resuming execution.", "syntax": "bar.warp.sync membermask;", "syntax_forms": [ { "syntax": "bar.warp.sync membermask;", "description": "bar.warp.sync will cause executing thread to wait until all threads corresponding to membermask have executed a bar.warp.sync with the same membermask value before resuming\nexecution. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_30" ], "introducedIn": "PTX ISA 6.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "membermask", "desc": "Operand" } ], "semantics": null, "examples": "st.shared.u32 [r0],r1; // write my result to shared memory\nbar.warp.sync 0xffffffff; // arrive, wait for others to arrive\nld.shared.u32 r2,[r3]; // read results written by other threads", "description": "bar.warp.sync will cause executing thread to wait until all threads corresponding to membermask have executed a bar.warp.sync with the same membermask value before resuming\nexecution.\nOperand membermask specifies a 32-bit integer which is a mask indicating threads participating\nin barrier where the bit position corresponds to thread’s laneid.\nThe behavior of bar.warp.sync is undefined if the executing thread is not in the membermask.\nbar.warp.sync also guarantee memory ordering among threads participating in barrier. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-bar-warp-sync", "introducedIn": "PTX ISA 6.0", "requiredTargets": [ "sm_30" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.barrier", "mnemonic": "barrier", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Barrier Synchronization", "category": "Parallel Synchronization and Communication Instructions", "summary": "Block threads in a CTA at a named barrier until the expected number of threads has arrived.", "syntax": "barrier{.cta}.sync{.aligned} a{, b};", "syntax_forms": [ { "syntax": "barrier{.cta}.sync{.aligned} a{, b};", "description": "Wait at barrier resource a for all (or b) threads of the CTA.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 6.0" }, { "syntax": "bar.sync a{, b};", "description": "Legacy short-form alias of barrier.sync with the same semantics.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "a", "desc": "Barrier resource identifier" }, { "name": "b", "desc": "Optional thread count participating in the barrier" } ], "semantics": "Every participating thread blocks until all have executed the barrier; also orders shared-memory visibility across the participating threads.", "examples": "// Use bar.sync to arrive at a pre-computed barrier number and\n// wait for all threads in CTA to also arrive:\n st.shared [r0],r1; // write my result to shared memory\n bar.cta.sync 1; // arrive, wait for others to arrive\n ld.shared r2,[r3]; // use shared results from other threads\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Performs barrier synchronization and communication within a CTA. Each CTA instance has sixteen\nbarriers numbered 0..15.\nbarrier{.cta} instructions can be used by the threads within the CTA for synchronization and\ncommunication.\nOperands a, b, and d have type.u32; operands p and c are predicates. Source\noperand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15. Operand b specifies the number of threads participating in the barrier. If\nno thread count is specified, all threads in the CTA participate in the barrier. When specifying a\nthread count, the value must be a multiple of the warp size. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-bar", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.barrier.cluster", "mnemonic": "barrier.cluster", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "barrier.cluster", "category": "Parallel Synchronization and Communication Instructions", "summary": "Performs barrier synchronization and communication within a cluster.", "syntax": "barrier.cluster.arrive{.sem}{.aligned};", "syntax_forms": [ { "syntax": "barrier.cluster.arrive{.sem}{.aligned};", "description": "Performs barrier synchronization and communication within a cluster.\nbarrier.cluster instructions can be used by the threads within the cluster for synchronization\nand communication.\nbarrier.cluster. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_90" ], "introducedIn": "PTX ISA 7.8" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "// use of arrive followed by wait\nld.shared::cluster.u32 r0, [addr];\nbarrier.cluster.arrive.aligned;\n...\nbarrier.cluster.wait.aligned;\nst.shared::cluster.u32 [addr], r1;\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Performs barrier synchronization and communication within a cluster.\nbarrier.cluster instructions can be used by the threads within the cluster for synchronization\nand communication.\nbarrier.cluster.arrive instruction marks warps’ arrival at barrier without causing executing\nthread to wait for threads of other participating warps.\nbarrier.cluster.wait instruction causes the executing thread to wait for all non-exited threads\nof the cluster to perform barrier.cluster.arrive.\nIn addition, barrier.cluster instructions cause the executing thread to wait for all non-exited\nthreads from its warp.\nWhen all non-exited threads in the cluster have executed barrier.cluster. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-barrier-cluster", "introducedIn": "PTX ISA 7.8", "requiredTargets": [ "sm_90" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.barrier.cta", "mnemonic": "barrier.cta", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "barrier.cta", "category": "Parallel Synchronization and Communication Instructions", "summary": "Performs barrier synchronization and communication within a CTA.", "syntax": "barrier.cta.sync{.aligned} a{, b};", "syntax_forms": [ { "syntax": "barrier.cta.sync{.aligned} a{, b};", "description": "Performs barrier synchronization and communication within a CTA. Each CTA instance has sixteen\nbarriers numbered 0..15.\nbarrier{. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "// Use bar.sync to arrive at a pre-computed barrier number and\n// wait for all threads in CTA to also arrive:\n st.shared [r0],r1; // write my result to shared memory\n bar.cta.sync 1; // arrive, wait for others to arrive\n ld.shared r2,[r3]; // use shared results from other threads\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Performs barrier synchronization and communication within a CTA. Each CTA instance has sixteen\nbarriers numbered 0..15.\nbarrier{.cta} instructions can be used by the threads within the CTA for synchronization and\ncommunication.\nOperands a, b, and d have type.u32; operands p and c are predicates. Source\noperand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15. Operand b specifies the number of threads participating in the barrier. If\nno thread count is specified, all threads in the CTA participate in the barrier. When specifying a\nthread count, the value must be a multiple of the warp size. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-bar", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.bfe", "mnemonic": "bfe", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "bfe", "category": "Integer Arithmetic Instructions", "summary": "Extract bit field from a and place the zero or sign-extended result in d.", "syntax": "bfe.type d, a, b, c;", "syntax_forms": [ { "syntax": "bfe.type d, a, b, c;", "description": "Extract bit field from a and place the zero or sign-extended result in d. Source b gives\nthe bit field starting bit position, and source c gives the bit field length in bits. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 2.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" }, { "name": "b", "desc": "Source operand" }, { "name": "c", "desc": "Source operand" } ], "semantics": "msb = (.type==.u32 || .type==.s32) ? 31 : 63;\npos = b & 0xff; // pos restricted to 0..255 range\nlen = c & 0xff; // len restricted to 0..255 range\n\nif (.type==.u32 || .type==.u64 || len==0)\n sbit = 0;\nelse\n sbit = a[min(pos+len-1,msb)];\n\nd = 0;\nfor (i=0; i<=msb; i++) {\n d[i] = (i=0; i--) {\n if (a & (1<= 32 ? true : false;\nbit-position-overflow = false;\nbit-width-overflow = false;\n\nif (.mode == .clamp) {\n if (a >= 32) {\n bit-position-overflow = true;\n mask0 = 0;\n }\n if (b >= 32) {\n bit-width-overflow = true;\n }\n}\n\nif (sum-overflow || bit-position-overflow || bit-width-overflow) {\n mask1 = 0;\n} else if (b1 == 0) {\n mask1 = ~0;\n}\nd = mask0 & ~mask1;", "examples": "bmsk.clamp.b32 rd, ra, rb;\nbmsk.wrap.b32 rd, 1, 2; // Creates a bitmask of 0x00000006.", "description": "Generates a 32-bit mask starting from the bit position specified in operand a, and of the width\nspecified in operand b. The generated bitmask is stored in the destination operand d.\nThe resulting bitmask is 0 in the following cases:\nWhen the value of a is 32 or higher and.mode is.clamp. When either the specified value of b or the wrapped value of b (when.mode is\nspecified as.wrap ) is 0.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#integer-arithmetic-instructions-bmsk", "introducedIn": "PTX ISA 7.6", "requiredTargets": [ "sm_70" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.bra", "mnemonic": "bra", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "bra", "category": "Control Flow Instructions", "summary": "Continue execution at the target.", "syntax": "@p bra{.uni} tgt; // tgt is a label", "syntax_forms": [ { "syntax": "@p bra{.uni} tgt; // tgt is a label", "description": "Continue execution at the target. Conditional branches are specified by using a guard predicate. The\nbranch target must be a label.\nbra.uni is guaranteed to be non-divergent, i.e. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": "if (p) {\n pc = tgt;\n}", "examples": "bra.uni L_exit; // uniform unconditional jump\n@q bra L23; // conditional branch", "description": "Continue execution at the target. Conditional branches are specified by using a guard predicate. The\nbranch target must be a label.\nbra.uni is guaranteed to be non-divergent, i.e. all active threads in a warp that are currently\nexecuting this instruction have identical values for the guard predicate and branch target.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#control-flow-instructions-bra", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.brev", "mnemonic": "brev", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "brev", "category": "Integer Arithmetic Instructions", "summary": "Perform bitwise reversal of input.", "syntax": "brev.type d, a;", "syntax_forms": [ { "syntax": "brev.type d, a;", "description": "Perform bitwise reversal of input.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 2.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" } ], "semantics": "msb = (.type==.b32) ? 31 : 63;\n\nfor (i=0; i<=msb; i++) {\n d[i] = a[msb-i];\n}", "examples": "brev.b32 d, a;", "description": "Perform bitwise reversal of input.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#integer-arithmetic-instructions-brev", "introducedIn": "PTX ISA 2.0", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.brkpt", "mnemonic": "brkpt", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "brkpt", "category": "Miscellaneous Instructions", "summary": "Suspends execution.", "syntax": "brkpt;", "syntax_forms": [ { "syntax": "brkpt;", "description": "Suspends execution.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_11" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "brkpt;\n@p brkpt;", "description": "Suspends execution.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#miscellaneous-instructions-brkpt", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_11" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.brx.idx", "mnemonic": "brx.idx", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "brx.idx", "category": "Control Flow Instructions", "summary": "Index into a list of possible destination labels, and continue execution from the chosen label.", "syntax": "@p brx.idx{.uni} index, tlist;", "syntax_forms": [ { "syntax": "@p brx.idx{.uni} index, tlist;", "description": "Index into a list of possible destination labels, and continue execution from the chosen\nlabel. Conditional branches are specified by using a guard predicate.\nbrx.idx. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_30" ], "introducedIn": "PTX ISA 6.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": "if (p) {\n if (index < length(tlist)) {\n pc = tlist[index];\n } else {\n pc = undefined;\n }\n}", "examples": ".function foo () {\n .reg .u32 %r0;\n ...\n L1:\n ...\n L2:\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Index into a list of possible destination labels, and continue execution from the chosen\nlabel. Conditional branches are specified by using a guard predicate.\nbrx.idx.uni guarantees that the branch is non-divergent, i.e. all active threads in a warp that\nare currently executing this instruction have identical values for the guard predicate and the index argument.\nThe index operand is a.u32 register. The tlist operand must be the label of a.branchtargets directive. It is accessed as a zero-based sequence using index. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#control-flow-instructions-brx-idx", "introducedIn": "PTX ISA 6.0", "requiredTargets": [ "sm_30" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.call", "mnemonic": "call", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "call", "category": "Control Flow Instructions", "summary": "The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction.", "syntax": "// direct call to named function, func is a symbol\ncall{.uni} (ret-param), func, (param-list);", "syntax_forms": [ { "syntax": "// direct call to named function, func is a symbol\ncall{.uni} (ret-param), func, (param-list);", "description": "The call instruction stores the address of the next instruction, so execution can resume at that\npoint after executing a ret instruction. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "// examples of direct call\n call init; // call function 'init'\n call.uni g, (a); // call function 'g' with parameter 'a'\n@p call (d), h, (a, b); // return value into register d\n\n// call-via-pointer using jump table\n// (truncated - see the official PTX ISA docs for the full example)", "description": "The call instruction stores the address of the next instruction, so execution can resume at that\npoint after executing a ret instruction. A call is assumed to be divergent unless the.uni suffix is present. The.uni suffix indicates that the call is guaranteed to be\nnon-divergent, i.e. all active threads in a warp that are currently executing this instruction have\nidentical values for the guard predicate and call target.\nFor direct calls, the called location func must be a symbolic function name; for indirect calls,\nthe called location fptr must be an address of a function held in a register. Input arguments\nand return values are optional. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#control-flow-instructions-call", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.clmad", "mnemonic": "clmad", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "clmad", "category": "Integer Arithmetic Instructions", "summary": "Performs a carryless multiplication of a and b, followed by a carryless addition of c, and writes the result into destination register d.", "syntax": "clmad.mode.u64 d, a, b, c;", "syntax_forms": [ { "syntax": "clmad.mode.u64 d, a, b, c;", "description": "Performs a carryless multiplication of a and b, followed by a carryless\naddition of c, and writes the result into destination register d.\nAll operands of clmad are unsigned 64-bit values. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_80" ], "introducedIn": "PTX ISA 9.3" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" }, { "name": "b", "desc": "Source operand" }, { "name": "c", "desc": "Source operand" } ], "semantics": "tmp[127:0] = 0; // 128-bit result of carryless multiplication.\n\nfor (i = 0; i < 64; i++) {\n if ((a & (1 << i)) != 0) {\n tmp ^= b << i;\n }\n}\n\n// Select upper or lower 64 bits depending on the value of .mode.\nif (.mode == .lo) {\n d = tmp[63..0];\n} else {\n d = tmp[127..64];\n}\n\nd ^= c; // carryless accumulation.", "examples": ".reg .u64 Rd, Ra, Rb, Rc;\n\n// Carryless multiply-add producing lower 64 bits of result.\nclmad.lo.u64 Rd, Ra, Rb, Rc;\n\n// Carryless multiply-add producing higher 64 bits of result.\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Performs a carryless multiplication of a and b, followed by a carryless\naddition of c, and writes the result into destination register d.\nAll operands of clmad are unsigned 64-bit values.\nThe modifier.mode specifies which part of the carryless product is stored in\nthe destination register:.lo Produces lower 64 bits of the product, with addition of c..hi Produces higher 64 bits of the product, with addition of c.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#integer-arithmetic-instructions-clmad", "introducedIn": "PTX ISA 9.3", "requiredTargets": [ "sm_80" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.clusterlaunchcontrol.query_cancel", "mnemonic": "clusterlaunchcontrol.query_cancel", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "clusterlaunchcontrol.query_cancel", "category": "Parallel Synchronization and Communication Instructions", "summary": "Instruction clusterlaunchcontrol.query_cancel can be used to decode opaque response written by instruction clusterlaunchcontrol.try_cancel.", "syntax": "clusterlaunchcontrol.query_cancel.is_canceled.pred.b128 pred, try_cancel_response;", "syntax_forms": [ { "syntax": "clusterlaunchcontrol.query_cancel.is_canceled.pred.b128 pred, try_cancel_response;", "description": "Instruction clusterlaunchcontrol.query_cancel can be used to decode opaque response\nwritten by instruction clusterlaunchcontrol.try_cancel.\nAfter loading response from clusterlaunchcontrol. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_100" ], "introducedIn": "PTX ISA 8.6" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "pred", "desc": "Operand" }, { "name": "try_cancel_response", "desc": "Operand" } ], "semantics": null, "examples": "clusterlaunchcontrol.query_cancel.is_canceled pred.b128 p, handle;\n\n@p clusterlaunchcontrol.query_cancel.get_first_ctaid.v4.b32.b128 {xdim, ydim, zdim, ignr} handle;\n\nclusterlaunchcontrol.query_cancel.get_first_ctaid::x.b32.b128 reg0, handle;\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Instruction clusterlaunchcontrol.query_cancel can be used to decode opaque response\nwritten by instruction clusterlaunchcontrol.try_cancel.\nAfter loading response from clusterlaunchcontrol.try_cancel instruction into 16-byte\nregister it can be further queried using clusterlaunchcontrol.query_cancel instruction\nas follows:\nclusterlaunchcontrol.query_cancel.is_canceled.pred.b128: If the cluster is canceled\nsuccessfully, predicate p is set to true; otherwise, it is set to false.\nIf the request succeeded, the instruction clusterlaunchcontrol.query_cancel.get_first_ctaid extracts the CTA id of the first CTA in the canceled cluster. (see the official PTX ISA docs for the full description)", "sourceUrl": null, "introducedIn": "PTX ISA 8.6", "requiredTargets": [ "sm_100" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.clusterlaunchcontrol.try_cancel", "mnemonic": "clusterlaunchcontrol.try_cancel", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "clusterlaunchcontrol.try_cancel", "category": "Parallel Synchronization and Communication Instructions", "summary": "The clusterlaunchcontrol.try_cancel instruction requests atomically cancelling the launch of a cluster that has not started running yet.", "syntax": "clusterlaunchcontrol.try_cancel.async{.space}.completion_mechanism{.multicast::cluster::all}.b128 [addr], [mbar];", "syntax_forms": [ { "syntax": "clusterlaunchcontrol.try_cancel.async{.space}.completion_mechanism{.multicast::cluster::all}.b128 [addr], [mbar];", "description": "The clusterlaunchcontrol.try_cancel instruction requests atomically cancelling the launch of\na cluster that has not started running yet. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_100" ], "introducedIn": "PTX ISA 8.6" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "// Assumption: 1D cluster (cluster_ctaid.y/.z == 1) with 1 thread per CTA.\n\n// Current Cluster to be processed: initially the launched cluster:\nmov.b32 xctaid, %ctaid.x;\n\n// Establish full synchronization across all CTAs of the cluster for the first iteration.\n// (truncated - see the official PTX ISA docs for the full example)", "description": "The clusterlaunchcontrol.try_cancel instruction requests atomically cancelling the launch of\na cluster that has not started running yet. It asynchronously writes an opaque response to shared\nmemory indicating whether the operation succeeded or failed. The completion of the asynchronous\noperation is tracked using the mbarrier completion mechanism at.cluster scope.\nThis instruction accesses its mbarrier operand using generic-proxy.\nOn success, the opaque response contains the ctaid of the first CTA of the canceled cluster; no\nother successful response from other clusterlaunchcontrol.try_cancel operations from the same\ngrid will contain that id.\nThe mandatory. (see the official PTX ISA docs for the full description)", "sourceUrl": null, "introducedIn": "PTX ISA 8.6", "requiredTargets": [ "sm_100" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.clz", "mnemonic": "clz", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Count Leading Zeros", "category": "Integer Arithmetic Instructions", "summary": "Count the number of leading zero bits in an integer operand.", "syntax": "clz.type d, a;", "syntax_forms": [ { "syntax": "clz.type d, a;", "description": "Count leading zeros.", "dataTypes": [ "b32", "b64" ], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 2.0" } ], "dataTypes": [ "b32", "b64" ], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register (u32)" }, { "name": "a", "desc": "Source operand" } ], "semantics": "d = number of leading 0-bits in a, counted from the most-significant bit.", "examples": "clz.b32 d, a;\nclz.b64 cnt, X; // cnt is .u32", "description": "Count the number of leading zeros in a starting with the most-significant bit and place the\nresult in 32-bit destination register d. Operand a has the instruction type, and destination d has type.u32. For.b32 type, the number of leading zeros is between 0 and 32,\ninclusively. For.b64 type, the number of leading zeros is between 0 and 64, inclusively.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#integer-arithmetic-instructions-clz", "introducedIn": "PTX ISA 2.0", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.cnot", "mnemonic": "cnot", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "cnot", "category": "Logic and Shift Instructions", "summary": "Compute the logical negation using C/C++ semantics.", "syntax": "cnot.type d, a;", "syntax_forms": [ { "syntax": "cnot.type d, a;", "description": "Compute the logical negation using C/C++ semantics.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" } ], "semantics": "d = (a==0) ? 1 : 0;", "examples": "cnot.b32 d,a;", "description": "Compute the logical negation using C/C++ semantics.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#logic-and-shift-instructions-cnot", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.copysign", "mnemonic": "copysign", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "copysign", "category": "Floating-Point Instructions", "summary": "Copy sign bit of a into value of b, and return the result as d.", "syntax": "copysign.type d, a, b;", "syntax_forms": [ { "syntax": "copysign.type d, a, b;", "description": "Copy sign bit of a into value of b, and return the result as d.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 2.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" }, { "name": "b", "desc": "Source operand" } ], "semantics": null, "examples": "copysign.f32 x, y, z;\ncopysign.f64 A, B, C;", "description": "Copy sign bit of a into value of b, and return the result as d.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#floating-point-instructions-copysign", "introducedIn": "PTX ISA 2.0", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.cos", "mnemonic": "cos", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "cos", "category": "Floating-Point Instructions", "summary": "Find the cosine of the angle a (in radians).", "syntax": "cos.approx{.ftz}.f32 d, a;", "syntax_forms": [ { "syntax": "cos.approx{.ftz}.f32 d, a;", "description": "Find the cosine of the angle a (in radians).", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" } ], "semantics": "d = cos(a);", "examples": "cos.approx.ftz.f32 ca, a;", "description": "Find the cosine of the angle a (in radians).", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#floating-point-instructions-cos", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.cp.async", "mnemonic": "cp.async", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "cp.async", "category": "Data Movement and Conversion Instructions", "summary": "cp.async is a non-blocking instruction which initiates an asynchronous copy operation of data from the location specified by source address operand src to the location specified by destination address operand dst.", "syntax": "cp.async.ca.shared{::cta}.global{.level::cache_hint}{.level::prefetch_size}", "syntax_forms": [ { "syntax": "cp.async.ca.shared{::cta}.global{.level::cache_hint}{.level::prefetch_size}", "description": "cp.async is a non-blocking instruction which initiates an asynchronous copy operation of data from the location specified by source address operand src to the location specified by destination address… (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_80" ], "introducedIn": "PTX ISA 7.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "cp.async.ca.shared.global [shrd], [gbl + 4], 4;\ncp.async.ca.shared::cta.global [%r0 + 8], [%r1], 8;\ncp.async.cg.shared.global [%r2], [%r3], 16;\n\ncp.async.cg.shared.global.L2::64B [%r2], [%r3], 16;\ncp.async.cg.shared.global.L2::128B [%r0 + 16], [%r1], 16;\n// (truncated - see the official PTX ISA docs for the full example)", "description": "cp.async is a non-blocking instruction which initiates an asynchronous copy operation of data\nfrom the location specified by source address operand src to the location specified by\ndestination address operand dst. Operand src specifies a location\nin the global state space and dst specifies a location in the shared state space.\nOperand cp-size is an integer constant which specifies the size of data in bytes to be copied to\nthe destination dst. cp-size can only be 4, 8 and 16.\nInstruction cp.async allows optionally specifying a 32-bit integer operand src-size. Operand src-size represents the size of the data in bytes to be copied from src to dst and must\nbe less than cp-size. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async", "introducedIn": "PTX ISA 7.0", "requiredTargets": [ "sm_80" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.cp.async.bulk", "mnemonic": "cp.async.bulk", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "cp.async.bulk", "category": "Data Movement and Conversion Instructions", "summary": "cp.async.bulk is a non-blocking instruction which initiates an asynchronous bulk-copy operation from the location specified by source address operand srcMem to the location specified by destination address operand dstMem.", "syntax": "// global -> shared::cta\ncp.async.bulk{.sem}.dst.src.completion_mechanism{.level::cache_hint}{.ignore_oob}\n[dstMem], [srcMem], size{, ignoreBytesLeft, ignoreBytesRight}, [mbar] {, cache_policy};", "syntax_forms": [ { "syntax": "// global -> shared::cta\ncp.async.bulk{.sem}.dst.src.completion_mechanism{.level::cache_hint}{.ignore_oob}\n[dstMem], [srcMem], size{, ignoreBytesLeft, ignoreBytesRight}, [mbar] {, cache_policy};", "description": "cp.async.bulk is a non-blocking instruction which initiates an asynchronous bulk-copy operation from the location specified by source address operand srcMem to the location specified by destination ad… (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_90" ], "introducedIn": "PTX ISA 8.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "// .global -> .shared::cta (strictly non-remote):\ncp.async.bulk.shared::cta.global.mbarrier::complete_tx::bytes [dstMem], [srcMem], size, [mbar];\n\ncp.async.bulk.shared::cta.global.mbarrier::complete_tx::bytes.L2::cache_hint\n [dstMem], [srcMem], size, [mbar], cache_policy;\n// (truncated - see the official PTX ISA docs for the full example)", "description": "cp.async.bulk is a non-blocking instruction which initiates an asynchronous bulk-copy operation\nfrom the location specified by source address operand srcMem to the location specified by\ndestination address operand dstMem.\nThe direction of bulk-copy is from the state space specified by the.src modifier to the state\nspace specified by the.dst modifiers.\nThe 32-bit operand size specifies the amount of memory to be copied, in terms of number of\nbytes. size must be a multiple of 16. If the value is not a multiple of 16, then the behavior is\nundefined. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk", "introducedIn": "PTX ISA 8.0", "requiredTargets": [ "sm_90" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.cp.async.bulk.commit_group", "mnemonic": "cp.async.bulk.commit_group", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "cp.async.bulk.commit_group", "category": "Data Movement and Conversion Instructions", "summary": "cp.async.bulk.commit_group instruction creates a new per-thread bulk async-group and batches all prior cp{.reduce}.async.bulk{.prefetch}{.tensor} instructions satisfying the following conditions into…", "syntax": "cp.async.bulk.commit_group;", "syntax_forms": [ { "syntax": "cp.async.bulk.commit_group;", "description": "cp.async.bulk.commit_group instruction creates a new per-thread bulk async-group and batches\nall prior cp{.reduce}.async.bulk{.prefetch}{. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_90" ], "introducedIn": "PTX ISA 8.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "cp.async.bulk.commit_group;", "description": "cp.async.bulk.commit_group instruction creates a new per-thread bulk async-group and batches\nall prior cp{.reduce}.async.bulk{.prefetch}{.tensor} instructions satisfying the following\nconditions into the new bulk async-group:\nThe prior cp{.reduce}.async.bulk{.prefetch}{.tensor} instructions use bulk_group based\ncompletion mechanism, and They are initiated by the executing thread but not committed to any bulk async-group.\nIf there are no uncommitted cp{.reduce}.async.bulk{.prefetch}{.tensor} instructions then cp.async.bulk.commit_group results in an empty bulk async-group.\nAn executing thread can wait for the completion of all cp{.reduce}.async.bulk{.prefetch}{. (see the official PTX ISA docs for the full description)", "sourceUrl": null, "introducedIn": "PTX ISA 8.0", "requiredTargets": [ "sm_90" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.cp.async.bulk.prefetch", "mnemonic": "cp.async.bulk.prefetch", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "cp.async.bulk.prefetch", "category": "Data Movement and Conversion Instructions", "summary": "cp.async.bulk.prefetch is a non-blocking instruction which may initiate an asynchronous prefetch of data from the location specified by source address operand srcMem, in.src statespace, to the L2 cache.", "syntax": "cp.async.bulk.prefetch.L2.src{.level::cache_hint} [srcMem], size {, cache_policy};", "syntax_forms": [ { "syntax": "cp.async.bulk.prefetch.L2.src{.level::cache_hint} [srcMem], size {, cache_policy};", "description": "cp.async.bulk.prefetch is a non-blocking instruction which may initiate an asynchronous prefetch\nof data from the location specified by source address operand srcMem, in. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_90" ], "introducedIn": "PTX ISA 8.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "cp.async.bulk.prefetch.L2.global [srcMem], size;\n\ncp.async.bulk.prefetch.L2.global.L2::cache_hint [srcMem], size, policy;", "description": "cp.async.bulk.prefetch is a non-blocking instruction which may initiate an asynchronous prefetch\nof data from the location specified by source address operand srcMem, in.src statespace, to\nthe L2 cache.\nThe 32-bit operand size specifies the amount of memory to be prefetched in terms of number of\nbytes. size must be a multiple of 16. If the value is not a multiple of 16, then the behavior is\nundefined. The address srcMem must be aligned to 16 bytes.\nWhen the optional argument cache_policy is specified, the qualifier.level::cache_hint is\nrequired. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-prefetch", "introducedIn": "PTX ISA 8.0", "requiredTargets": [ "sm_90" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.cp.async.bulk.prefetch.tensor", "mnemonic": "cp.async.bulk.prefetch.tensor", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "cp.async.bulk.prefetch.tensor", "category": "Data Movement and Conversion Instructions", "summary": "cp.async.bulk.prefetch.tensor is a non-blocking instruction which may initiate an asynchronous prefetch of tensor data from the location in.src statespace to the L2 cache.", "syntax": "// global -> L2:\ncp.async.bulk.prefetch.tensor.dim.L2.src{.load_mode}{.level::cache_hint} [tensorMap, tensorCoords]\n{, im2colInfo } {, cache_policy}", "syntax_forms": [ { "syntax": "// global -> L2:\ncp.async.bulk.prefetch.tensor.dim.L2.src{.load_mode}{.level::cache_hint} [tensorMap, tensorCoords]\n{, im2colInfo } {, cache_policy}", "description": "cp.async.bulk.prefetch.tensor is a non-blocking instruction which may initiate an asynchronous\nprefetch of tensor data from the location in.src statespace to the L2 cache. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_90" ], "introducedIn": "PTX ISA 8.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "global -> L2:", "desc": "Operand" } ], "semantics": null, "examples": ".reg .b16 ctaMask, im2colwHalo, im2colOff;\n.reg .u16 i2cOffW, i2cOffH, i2cOffD;\n.reg .b64 l2CachePolicy;\n\ncp.async.bulk.prefetch.tensor.1d.L2.global.tile [tensorMap0, {tc0}];\n// (truncated - see the official PTX ISA docs for the full example)", "description": "cp.async.bulk.prefetch.tensor is a non-blocking instruction which may initiate an asynchronous\nprefetch of tensor data from the location in.src statespace to the L2 cache.\nThe operand tensorMap is the generic address of the opaque tensor-map object which resides\nin.param space or.const space or.global space. The operand tensorMap specifies\nthe properties of the tensor copy operation, as described in Tensor-map.\nThe tensorMap is accessed in tensormap proxy. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-prefetch-tensor", "introducedIn": "PTX ISA 8.0", "requiredTargets": [ "sm_90" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.cp.async.bulk.tensor", "mnemonic": "cp.async.bulk.tensor", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "cp.async.bulk.tensor", "category": "Data Movement and Conversion Instructions", "summary": "cp.async.bulk.tensor is a non-blocking instruction which initiates an asynchronous copy operation of tensor data from the location in.src state space to the location in the.dst state space.", "syntax": "// global -> shared::cta\ncp.async.bulk.tensor.dim.dst.src{.load_mode}.completion_mechanism{.cta_group}{.level::cache_hint}\n[dstMem], [tensorMap, tensorCoords], [mbar]{, im2colInfo} {, cache_policy}", "syntax_forms": [ { "syntax": "// global -> shared::cta\ncp.async.bulk.tensor.dim.dst.src{.load_mode}.completion_mechanism{.cta_group}{.level::cache_hint}\n[dstMem], [tensorMap, tensorCoords], [mbar]{, im2colInfo} {, cache_policy}", "description": "cp.async.bulk.tensor is a non-blocking instruction which initiates an asynchronous copy\noperation of tensor data from the location in.src state space to the location in the.dst state space. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_90" ], "introducedIn": "PTX ISA 8.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": ".reg .b16 ctaMask;\n.reg .u16 i2cOffW, i2cOffH, i2cOffD;\n.reg .b64 l2CachePolicy;\n\ncp.async.bulk.tensor.1d.shared::cta.global.mbarrier::complete_tx::bytes.tile [sMem0], [tensorMap0, {tc0}], [mbar0];\n// (truncated - see the official PTX ISA docs for the full example)", "description": "cp.async.bulk.tensor is a non-blocking instruction which initiates an asynchronous copy\noperation of tensor data from the location in.src state space to the location in the.dst state space.\nThe operand dstMem specifies the location in the.dst state space into which the tensor data\nhas to be copied and srcMem specifies the location in the.src state space from which the\ntensor data has to be copied.\nWhen.dst is specified as.shared::cta, the address dstMem must be in the shared memory\nof the executing CTA within the cluster, otherwise the behavior is undefined. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-tensor", "introducedIn": "PTX ISA 8.0", "requiredTargets": [ "sm_90" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.cp.async.bulk.wait_group", "mnemonic": "cp.async.bulk.wait_group", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "cp.async.bulk.wait_group", "category": "Data Movement and Conversion Instructions", "summary": "cp.async.bulk.wait_group instruction will cause the executing thread to wait until only N or fewer of the most recent bulk async-groups are pending and all the prior bulk async-groups committed by the executing threads are complete.", "syntax": "cp.async.bulk.wait_group{.read} N;", "syntax_forms": [ { "syntax": "cp.async.bulk.wait_group{.read} N;", "description": "cp.async.bulk.wait_group instruction will cause the executing thread to wait until only N or fewer of the most recent bulk async-groups are pending and all the prior bulk async-groups committed by the… (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_90" ], "introducedIn": "PTX ISA 8.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "N", "desc": "Operand" } ], "semantics": null, "examples": "cp.async.bulk.wait_group.read 0;\ncp.async.bulk.wait_group 2;", "description": "cp.async.bulk.wait_group instruction will cause the executing thread to wait until only N or\nfewer of the most recent bulk async-groups are pending and all the prior bulk async-groups committed by the executing threads are complete. For example, when N is 0, the executing thread\nwaits on all the prior bulk async-groups to complete. Operand N is an integer constant.\nBy default, cp.async.bulk.wait_group instruction will cause the executing thread to wait until\ncompletion of all the bulk async operations in the specified bulk async-group. A bulk async\noperation includes the following:\nOptionally, reading from the tensormap. Reading from the source locations. (see the official PTX ISA docs for the full description)", "sourceUrl": null, "introducedIn": "PTX ISA 8.0", "requiredTargets": [ "sm_90" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.cp.async.commit_group", "mnemonic": "cp.async.commit_group", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "cp.async.commit_group", "category": "Data Movement and Conversion Instructions", "summary": "cp.async.commit_group instruction creates a new cp.async-group per thread and batches all prior cp.async instructions initiated by the executing thread but not committed to any cp.async-group into the new cp.async-group.", "syntax": "cp.async.commit_group ;", "syntax_forms": [ { "syntax": "cp.async.commit_group ;", "description": "cp.async.commit_group instruction creates a new cp.async-group per thread and batches all\nprior cp.async instructions initiated by the executing thread but not committed to any cp. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_80" ], "introducedIn": "PTX ISA 7.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "// Example 1:\ncp.async.ca.shared.global [shrd], [gbl], 4;\ncp.async.commit_group ; // Marks the end of a cp.async group\n\n// Example 2:\ncp.async.ca.shared.global [shrd1], [gbl1], 8;\n// (truncated - see the official PTX ISA docs for the full example)", "description": "cp.async.commit_group instruction creates a new cp.async-group per thread and batches all\nprior cp.async instructions initiated by the executing thread but not committed to any cp.async-group into the new cp.async-group. If there are no uncommitted cp.async instructions then cp.async.commit_group results in an empty cp.async-group.\nAn executing thread can wait for the completion of all cp.async operations in a cp.async-group using cp.async.wait_group.\nThere is no memory ordering guarantee provided between any two cp.async operations within the\nsame cp.async-group. So two or more cp.async operations within a cp.async-group copying data\nto the same location results in undefined behavior.", "sourceUrl": null, "introducedIn": "PTX ISA 7.0", "requiredTargets": [ "sm_80" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.cp.async.mbarrier.arrive", "mnemonic": "cp.async.mbarrier.arrive", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "cp.async.mbarrier.arrive", "category": "Parallel Synchronization and Communication Instructions", "summary": "Causes an arrive-on operation to be triggered by the system on the mbarrier object upon the completion of all prior cp.async operations initiated by the executing thread.", "syntax": "cp.async.mbarrier.arrive{.noinc}{.shared{::cta}}.b64 [addr];", "syntax_forms": [ { "syntax": "cp.async.mbarrier.arrive{.noinc}{.shared{::cta}}.b64 [addr];", "description": "Causes an arrive-on operation to be\ntriggered by the system on the mbarrier object upon the completion of all prior cp.async operations initiated by the\nexecuting thread. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_80" ], "introducedIn": "PTX ISA 7.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "// Example 1: no .noinc\nmbarrier.init.shared.b64 [shMem], threadCount;\n....\ncp.async.ca.shared.global [shard1], [gbl1], 4;\ncp.async.cg.shared.global [shard2], [gbl2], 16;\n....\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Causes an arrive-on operation to be\ntriggered by the system on the mbarrier object upon the completion of all prior cp.async operations initiated by the\nexecuting thread. The mbarrier object is at the location specified by the operand addr. The arrive-on operation is\nasynchronous to execution of cp.async.mbarrier.arrive.\nWhen.noinc modifier is not specified, the pending count of the mbarrier object is incremented\nby 1 prior to the asynchronous arrive-on operation. This\nresults in a zero-net change for the pending count from the asynchronous arrive-on operation\nduring the current phase. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-cp-async-mbarrier-arrive", "introducedIn": "PTX ISA 7.0", "requiredTargets": [ "sm_80" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.cp.async.wait_all", "mnemonic": "cp.async.wait_all", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "cp.async.wait_all", "category": "Data Movement and Conversion Instructions", "summary": "cp.async.wait_all instruction will cause the executing thread to wait until all the prior cp.async operations are complete. It is equivalent to cp.async.commit_group immediately followed by cp.async.wait_group 0.", "syntax": "cp.async.wait_all;", "syntax_forms": [ { "syntax": "cp.async.wait_all;", "description": "cp.async.wait_all instruction will cause the executing thread to wait until all the prior cp.async operations are complete. It is equivalent to cp.async.commit_group immediately followed by cp.async.wait_group 0.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_80" ], "introducedIn": "PTX ISA 7.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "// Example of .wait_all:\ncp.async.ca.shared.global [shrd1], [gbl1], 4;\ncp.async.cg.shared.global [shrd2], [gbl2], 16;\ncp.async.wait_all; // waits for all prior cp.async to complete\n\n// Example of .wait_group :\n// (truncated - see the official PTX ISA docs for the full example)", "description": "cp.async.wait_all instruction will cause the executing thread to wait until all the prior cp.async operations are complete. It is equivalent to cp.async.commit_group immediately followed by cp.async.wait_group 0.", "sourceUrl": null, "introducedIn": "PTX ISA 7.0", "requiredTargets": [ "sm_80" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.cp.async.wait_group", "mnemonic": "cp.async.wait_group", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "cp.async.wait_group", "category": "Data Movement and Conversion Instructions", "summary": "cp.async.wait_group instruction will cause executing thread to wait till only N or fewer of the most recent cp.async-group s are pending and all the prior cp.async-group s committed by the executing threads are complete.", "syntax": "cp.async.wait_group N;", "syntax_forms": [ { "syntax": "cp.async.wait_group N;", "description": "cp.async.wait_group instruction will cause executing thread to wait till only N or fewer of\nthe most recent cp.async-group s are pending and all the prior cp. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_80" ], "introducedIn": "PTX ISA 7.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "N", "desc": "Operand" } ], "semantics": null, "examples": "// Example of .wait_all:\ncp.async.ca.shared.global [shrd1], [gbl1], 4;\ncp.async.cg.shared.global [shrd2], [gbl2], 16;\ncp.async.wait_all; // waits for all prior cp.async to complete\n\n// Example of .wait_group :\n// (truncated - see the official PTX ISA docs for the full example)", "description": "cp.async.wait_group instruction will cause executing thread to wait till only N or fewer of\nthe most recent cp.async-group s are pending and all the prior cp.async-group s committed by\nthe executing threads are complete. For example, when N is 0, the executing thread waits on all\nthe prior cp.async-group s to complete. Operand N is an integer constant.\ncp.async.wait_all is equivalent to:\ncp.async.commit_group;\ncp.async.wait_group 0;\nAn empty cp.async-group is considered to be trivially complete.\nWrites performed by cp.async operations are made visible to the executing thread only after:\nThe completion of cp.async.wait_all or The completion of cp.async.wait_group on the cp. (see the official PTX ISA docs for the full description)", "sourceUrl": null, "introducedIn": "PTX ISA 7.0", "requiredTargets": [ "sm_80" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.cp.reduce.async.bulk", "mnemonic": "cp.reduce.async.bulk", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "cp.reduce.async.bulk", "category": "Data Movement and Conversion Instructions", "summary": "cp.reduce.async.bulk is a non-blocking instruction which initiates an asynchronous reduction operation on an array of memory locations specified by the destination address operand dstMem with the source array whose location is specified by the source address operand srcMem.", "syntax": "cp.reduce.async.bulk{.sem.scope}.dst.src.completion_mechanism.redOp.type", "syntax_forms": [ { "syntax": "cp.reduce.async.bulk{.sem.scope}.dst.src.completion_mechanism.redOp.type", "description": "cp.reduce.async.bulk is a non-blocking instruction which initiates an asynchronous reduction operation on an array of memory locations specified by the destination address operand dstMem with the sour… (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_90" ], "introducedIn": "PTX ISA 8.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.add.u64\n [dstMem], [srcMem], size, [mbar];\n\ncp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.min.s32\n [dstMem], [srcMem], size, [mbar];\n// (truncated - see the official PTX ISA docs for the full example)", "description": "cp.reduce.async.bulk is a non-blocking instruction which initiates an asynchronous reduction\noperation on an array of memory locations specified by the destination address operand dstMem with the source array whose location is specified by the source address operand srcMem. The size\nof the source and the destination array must be the same and is specified by the operand size.\nEach data element in the destination array is reduced inline with the corresponding data element in\nthe source array with the reduction operation specified by the modifier.redOp. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-reduce-async-bulk", "introducedIn": "PTX ISA 8.0", "requiredTargets": [ "sm_90" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.cp.reduce.async.bulk.tensor", "mnemonic": "cp.reduce.async.bulk.tensor", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "cp.reduce.async.bulk.tensor", "category": "Data Movement and Conversion Instructions", "summary": "cp.reduce.async.bulk.tensor is a non-blocking instruction which initiates an asynchronous reduction operation of tensor data in the.dst state space with tensor data in the.src state space.", "syntax": "// shared::cta -> global:\ncp.reduce.async.bulk.tensor.dim.dst.src.redOp{.load_mode}.completion_mechanism{.level::cache_hint}\n[tensorMap, tensorCoords], [srcMem] {,cache_policy}", "syntax_forms": [ { "syntax": "// shared::cta -> global:\ncp.reduce.async.bulk.tensor.dim.dst.src.redOp{.load_mode}.completion_mechanism{.level::cache_hint}\n[tensorMap, tensorCoords], [srcMem] {,cache_policy}", "description": "cp.reduce.async.bulk.tensor is a non-blocking instruction which initiates an asynchronous\nreduction operation of tensor data in the.dst state space with tensor data in the.src state space. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_90" ], "introducedIn": "PTX ISA 8.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "cp.reduce.async.bulk.tensor.1d.global.shared::cta.add.tile.bulk_group\n [tensorMap0, {tc0}], [sMem0];\n\ncp.reduce.async.bulk.tensor.2d.global.shared::cta.and.bulk_group.L2::cache_hint\n [tensorMap1, {tc0, tc1}], [sMem1] , policy;\n// (truncated - see the official PTX ISA docs for the full example)", "description": "cp.reduce.async.bulk.tensor is a non-blocking instruction which initiates an asynchronous\nreduction operation of tensor data in the.dst state space with tensor data in the.src state space.\nThe operand srcMem specifies the location of the tensor data in the.src state space using\nwhich the reduction operation has to be performed.\nThe operand tensorMap is the generic address of the opaque tensor-map object which resides\nin.param space or.const space or.global space. The operand tensorMap specifies\nthe properties of the tensor copy operation, as described in Tensor-map.\nThe tensorMap is accessed in tensormap proxy. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-reduce-async-bulk-tensor", "introducedIn": "PTX ISA 8.0", "requiredTargets": [ "sm_90" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.createpolicy", "mnemonic": "createpolicy", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "createpolicy", "category": "Data Movement and Conversion Instructions", "summary": "The createpolicy instruction creates a cache eviction policy for the specified cache level in an opaque 64-bit register specified by the destination operand cache_policy.", "syntax": "// Range-based policy\ncreatepolicy.range{.global}.level::primary_priority{.level::secondary_priority}.b64\ncache_policy, [a], primary-size, total-size;", "syntax_forms": [ { "syntax": "// Range-based policy\ncreatepolicy.range{.global}.level::primary_priority{.level::secondary_priority}.b64\ncache_policy, [a], primary-size, total-size;", "description": "The createpolicy instruction creates a cache eviction policy for the specified cache level in an\nopaque 64-bit register specified by the destination operand cache_policy. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_80" ], "introducedIn": "PTX ISA 7.4" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "Range-based policy", "desc": "Operand" } ], "semantics": null, "examples": "createpolicy.fractional.L2::evict_last.b64 policy, 1.0;\ncreatepolicy.fractional.L2::evict_last.L2::evict_unchanged.b64 policy, 0.5;\n\ncreatepolicy.range.L2::evict_last.L2::evict_first.b64\n policy, [ptr], 0x100000, 0x200000;\n// (truncated - see the official PTX ISA docs for the full example)", "description": "The createpolicy instruction creates a cache eviction policy for the specified cache level in an\nopaque 64-bit register specified by the destination operand cache_policy. The cache eviction\npolicy specifies how cache eviction priorities are applied to global memory addresses used in memory\noperations with.level::cache_hint qualifier.\nThere are two types of cache eviction policies:\nRange-based policy The cache eviction policy created using createpolicy.range specifies the cache eviction\nbehaviors for the following three address ranges: [a.. a + (primary-size - 1)] referred to as primary range. [a + primary-size.. a + (total-size - 1)] referred to as trailing secondary range. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-createpolicy", "introducedIn": "PTX ISA 7.4", "requiredTargets": [ "sm_80" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.cvt", "mnemonic": "cvt", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Convert", "category": "Data Movement and Conversion Instructions", "summary": "Convert a value between integer and/or floating-point types with an explicit rounding mode.", "syntax": "cvt.dtype.atype d, a;", "syntax_forms": [ { "syntax": "cvt.dtype.atype d, a;", "description": "Type conversion between the source (atype) and destination (dtype) types.", "dataTypes": [ "s8", "s16", "s32", "s64", "u8", "u16", "u32", "u64", "f16", "f32", "f64" ], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" }, { "syntax": "cvt.rn.f32.f64 d, a;", "description": "Floating-point narrowing/widening conversion with explicit IEEE rounding mode.", "dataTypes": [ "f32", "f64" ], "stateSpaces": [], "scopes": [], "modifiers": [ "rn", "rz", "rm", "rp" ], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [ "f16", "f32", "f64", "s16", "s32", "s64", "s8", "u16", "u32", "u64", "u8" ], "stateSpaces": [], "scopes": [], "modifiers": [ "rm", "rn", "rp", "rz" ], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" } ], "semantics": "d = convert(a, atype -> dtype) using the specified rounding mode; saturating forms clamp on overflow.", "examples": "cvt.f32.s32 f,i;\ncvt.s32.f64 j,r; // float-to-int saturates by default\ncvt.rni.f32.f32 x,y; // round to nearest int, result is fp\ncvt.f32.f32 x,y; // note .ftz behavior for sm_1x targets\ncvt.rn.relu.f16.f32 b, f; // result is saturated with .relu saturation mode\ncvt.rz.f16x2.f32 b1, f, f1; // convert two fp32 values to packed fp16 outputs\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Convert between different types and sizes.\nFor.f16x2 and.bf16x2 instruction type, two inputs a and b of.f32 type are\nconverted into.f16 or.bf16 type and the converted values are packed in the destination\nregister d, such that the value converted from input a is stored in the upper half of d and the value converted from input b is stored in the lower half of d\nFor.f16x2 instruction type, destination operand d has.f16x2 or.b32 type. For.bf16 instruction type, operand d has.b16 type. For.bf16x2 instruction type,\noperand d has.b32 type. For.tf32 instruction type, operand d has.b32 type.\nWhen converting to.e4m3x2 /.e5m2x2 data formats, the destination operand d has.b16 type. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cvt", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.cvt.pack", "mnemonic": "cvt.pack", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "cvt.pack", "category": "Data Movement and Conversion Instructions", "summary": "Convert two 32-bit integers a and b into specified type and pack the results into d.", "syntax": "cvt.pack.sat.convertType.abType d, a, b;", "syntax_forms": [ { "syntax": "cvt.pack.sat.convertType.abType d, a, b;", "description": "Convert two 32-bit integers a and b into specified type and pack the results into d.\nDestination d is an unsigned 32-bit integer. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_72" ], "introducedIn": "PTX ISA 6.5" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" }, { "name": "b", "desc": "Source operand" } ], "semantics": "ta = a < MIN(convertType) ? MIN(convertType) : a;\nta = a > MAX(convertType) ? MAX(convertType) : a;\ntb = b < MIN(convertType) ? MIN(convertType) : b;\ntb = b > MAX(convertType) ? MAX(convertType) : b;\n\nsize = sizeInBits(convertType);\ntd = tb ;\nfor (i = size; i <= 2 * size - 1; i++) {\n td[i] = ta[i - size];\n}\n\nif (isU16(convertType) || isS16(convertType)) {\n d = td;\n} else {\n for (i = 0; i < 2 * size; i++) {\n d[i] = td[i];\n }\n for (i = 2 * size; i <= 31; i++) {\n d[i] = c[i - 2 * size];\n }\n}", "examples": "cvt.pack.sat.s16.s32 %r1, %r2, %r3; // 32-bit to 16-bit conversion\ncvt.pack.sat.u8.s32.b32 %r4, %r5, %r6, 0; // 32-bit to 8-bit conversion\ncvt.pack.sat.u8.s32.b32 %r7, %r8, %r9, %r4; // %r7 = { %r5, %r6, %r8, %r9 }\ncvt.pack.sat.u4.s32.b32 %r10, %r12, %r13, %r14; // 32-bit to 4-bit conversion\ncvt.pack.sat.s2.s32.b32 %r15, %r16, %r17, %r18; // 32-bits to 2-bit conversion", "description": "Convert two 32-bit integers a and b into specified type and pack the results into d.\nDestination d is an unsigned 32-bit integer. Source operands a and b are integers of\ntype.abType and the source operand c is an integer of type.cType.\nThe inputs a and b are converted to values of type specified by.convertType with\nsaturation and the results after conversion are packed into lower bits of d.\nIf operand c is specified then remaining bits of d are copied from lower bits of c.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cvt-pack", "introducedIn": "PTX ISA 6.5", "requiredTargets": [ "sm_72" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.cvta", "mnemonic": "cvta", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "cvta", "category": "Data Movement and Conversion Instructions", "summary": "Convert a const, Kernel Function Parameters (.param ), global, local, or shared address to a generic address, or vice-versa.", "syntax": "// convert const, global, local, or shared address to generic address\ncvta.space.size p, a; // source address in register a", "syntax_forms": [ { "syntax": "// convert const, global, local, or shared address to generic address\ncvta.space.size p, a; // source address in register a", "description": "Convert a const, Kernel Function Parameters (.param ), global, local, or shared address to a generic address, or vice-versa. The\nsource and destination addresses must be the same size. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 2.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "cvta.const.u32 ptr,cvar;\ncvta.local.u32 ptr,lptr;\ncvta.shared::cta.u32 p,As+4;\ncvta.shared::cluster.u32 ptr, As;\ncvta.to.global.u32 p,gptr;\ncvta.param.u64 ptr,pvar;\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Convert a const, Kernel Function Parameters (.param ), global, local, or shared address to a generic address, or vice-versa. The\nsource and destination addresses must be the same size. Use cvt.u32.u64 or cvt.u64.u32 to\ntruncate or zero-extend addresses.\nFor variables declared in.const, Kernel Function Parameters (.param ),.global,.local, or.shared state space, the generic address of the variable may be taken using cvta. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cvta", "introducedIn": "PTX ISA 2.0", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.discard", "mnemonic": "discard", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "discard", "category": "Data Movement and Conversion Instructions", "summary": "Semantically, this behaves like a weak write of an unstable indeterminate value: reads of memory locations with unstable indeterminate values may return different bit patterns each time until the memory is overwritten.", "syntax": "discard{.global}.level [a], size;", "syntax_forms": [ { "syntax": "discard{.global}.level [a], size;", "description": "Semantically, this behaves like a weak write of an unstable indeterminate value: reads of memory locations with unstable indeterminate values may return different bit patterns each time until the memo… (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_80" ], "introducedIn": "PTX ISA 7.4" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "discard.global.L2 [ptr], 128;\nld.weak.u32 r0, [ptr];\nld.weak.u32 r1, [ptr];\n// The values in r0 and r1 may differ!", "description": "Semantically, this behaves like a weak write of an unstable indeterminate value:\nreads of memory locations with unstable indeterminate values may return different\nbit patterns each time until the memory is overwritten.\nThis operation hints to the implementation that data in the specified cache.level can be destructively discarded without writing it back to memory.\nThe operand size is an integer constant that specifies the length in bytes of the\naddress range [a, a + size) to write unstable indeterminate values into.\nThe only supported value for the size operand is 128.\nIf no state space is specified then Generic Addressing is used. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-discard", "introducedIn": "PTX ISA 7.4", "requiredTargets": [ "sm_80" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.div", "mnemonic": "div", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Divide", "category": "Arithmetic", "summary": "Divide the first operand by the second.", "syntax": "div.stype d, a, b;", "syntax_forms": [ { "syntax": "div.stype d, a, b;", "description": "Integer division.", "dataTypes": [ "s32", "s64", "u32", "u64" ], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" }, { "syntax": "div.approx.f32 d, a, b;", "description": "Fast approximate single-precision division.", "dataTypes": [ "f32" ], "stateSpaces": [], "scopes": [], "modifiers": [ "approx" ], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" }, { "syntax": "div.rn.f64 d, a, b;", "description": "IEEE-754 round-to-nearest double-precision division.", "dataTypes": [ "f64" ], "stateSpaces": [], "scopes": [], "modifiers": [ "rn" ], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [ "f32", "f64", "s32", "s64", "u32", "u64" ], "stateSpaces": [], "scopes": [], "modifiers": [ "approx", "rn" ], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Dividend" }, { "name": "b", "desc": "Divisor" } ], "semantics": "d = a / b.", "examples": "div.s32 b,n,i;\n\ndiv.approx.ftz.f32 diam,circum,3.14159;\ndiv.full.ftz.f32 x, y, z;\ndiv.rn.f64 xd, yd, zd;", "description": "Divides a by b, stores result in d.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#integer-arithmetic-instructions-div", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.dp2a", "mnemonic": "dp2a", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "dp2a", "category": "Integer Arithmetic Instructions", "summary": "Two-way 16-bit to 8-bit dot product which is accumulated in 32-bit result.", "syntax": "dp2a.mode.atype.btype d, a, b, c;", "syntax_forms": [ { "syntax": "dp2a.mode.atype.btype d, a, b, c;", "description": "Two-way 16-bit to 8-bit dot product which is accumulated in 32-bit result.\nOperand a and b are 32-bit inputs. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_61" ], "introducedIn": "PTX ISA 5.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" }, { "name": "b", "desc": "Source operand" }, { "name": "c", "desc": "Source operand" } ], "semantics": "d = c;\n// Extract two 16-bit values from a 32-bit input and sign or zero extend\n// based on input type.\nVa = extractAndSignOrZeroExt_2(a, .atype);\n\n// Extract four 8-bit values from a 32-bit input and sign or zer extend\n// based on input type.\nVb = extractAndSignOrZeroExt_4(b, .btype);\n\nb_select = (.mode == .lo) ? 0 : 2;\n\nfor (i = 0; i < 2; ++i) {\n d += Va[i] * Vb[b_select + i];\n}", "examples": "dp2a.lo.u32.u32 d0, a0, b0, c0;\ndp2a.hi.u32.s32 d1, a1, b1, c1;", "description": "Two-way 16-bit to 8-bit dot product which is accumulated in 32-bit result.\nOperand a and b are 32-bit inputs. Operand a holds two 16-bits inputs in packed form and\noperand b holds 4 byte inputs in packed form for dot product.\nDepending on the.mode specified, either lower half or upper half of operand b will be used\nfor dot product.\nOperand c has type.u32 if both.atype and.btype are.u32 else operand c has type.s32.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#integer-arithmetic-instructions-dp2a", "introducedIn": "PTX ISA 5.0", "requiredTargets": [ "sm_61" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.dp4a", "mnemonic": "dp4a", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "dp4a", "category": "Integer Arithmetic Instructions", "summary": "Four-way byte dot product which is accumulated in 32-bit result.", "syntax": "dp4a.atype.btype d, a, b, c;", "syntax_forms": [ { "syntax": "dp4a.atype.btype d, a, b, c;", "description": "Four-way byte dot product which is accumulated in 32-bit result.\nOperand a and b are 32-bit inputs which hold 4 byte inputs in packed form for dot product.\nOperand c has type.u32 if both.atype and. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_61" ], "introducedIn": "PTX ISA 5.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" }, { "name": "b", "desc": "Source operand" }, { "name": "c", "desc": "Source operand" } ], "semantics": "d = c;\n\n// Extract 4 bytes from a 32bit input and sign or zero extend\n// based on input type.\nVa = extractAndSignOrZeroExt_4(a, .atype);\nVb = extractAndSignOrZeroExt_4(b, .btype);\n\nfor (i = 0; i < 4; ++i) {\n d += Va[i] * Vb[i];\n}", "examples": "dp4a.u32.u32 d0, a0, b0, c0;\ndp4a.u32.s32 d1, a1, b1, c1;", "description": "Four-way byte dot product which is accumulated in 32-bit result.\nOperand a and b are 32-bit inputs which hold 4 byte inputs in packed form for dot product.\nOperand c has type.u32 if both.atype and.btype are.u32 else operand c has type.s32.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#integer-arithmetic-instructions-dp4a", "introducedIn": "PTX ISA 5.0", "requiredTargets": [ "sm_61" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.elect.sync", "mnemonic": "elect.sync", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "elect.sync", "category": "Parallel Synchronization and Communication Instructions", "summary": "elect.sync elects one predicated active leader thread from among a set of threads specified by membermask.", "syntax": "elect.sync d|p, membermask;", "syntax_forms": [ { "syntax": "elect.sync d|p, membermask;", "description": "elect.sync elects one predicated active leader thread from among a set of threads specified by membermask. laneid of the elected thread is returned in the 32-bit destination operand d. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_90" ], "introducedIn": "PTX ISA 8.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d|p", "desc": "Operand" }, { "name": "membermask", "desc": "Operand" } ], "semantics": null, "examples": "elect.sync %r0|%p0, 0xffffffff;", "description": "elect.sync elects one predicated active leader thread from among a set of threads specified by membermask. laneid of the elected thread is returned in the 32-bit destination operand d. The sink symbol ‘_’ can be used for destination operand d. The predicate destination p is set to True for the leader thread, and False for all other threads.\nOperand membermask specifies a 32-bit integer indicating the set of threads from which a leader\nis to be elected. The behavior is undefined if the executing thread is not in membermask.\nElection of a leader thread happens deterministically, i.e. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-elect-sync", "introducedIn": "PTX ISA 8.0", "requiredTargets": [ "sm_90" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.ex2", "mnemonic": "ex2", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "ex2", "category": "Half Precision Floating-Point Instructions", "summary": "Raise 2 to the power a.", "syntax": "ex2.approx{.ftz}.f32 d, a;", "syntax_forms": [ { "syntax": "ex2.approx{.ftz}.f32 d, a;", "description": "Raise 2 to the power a.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_75" ], "introducedIn": "PTX ISA 1.0" }, { "syntax": "ex2.approx.atype d, a;", "description": "Raise 2 to the power a.\nThe type of operands d and a are as specified by.type.\nFor.f16x2 or. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_75" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" } ], "semantics": "if (.type == .f16 || .type == .bf16) {\n d = 2 ^ a\n} else if (.type == .f16x2 || .type == .bf16x2) {\n fA[0] = a[0:15];\n fA[1] = a[16:31];\n d[0] = 2 ^ fA[0]\n d[1] = 2 ^ fA[1]\n}", "examples": "ex2.approx.ftz.f32 xa, a;\n\nex2.approx.f16 h1, h0;\nex2.approx.f16x2 hd1, hd0;\nex2.approx.ftz.bf16 b1, b2;\nex2.approx.ftz.bf16x2 hb1, hb2;", "description": "Raise 2 to the power a.\nThe type of operands d and a are as specified by.type.\nFor.f16x2 or.bf16x2 instruction type, each of the half-word operands are operated in\nparallel and the results are packed appropriately into a.f16x2 or.bf16x2.\nFor.f16 instruction type, operands d and a have.f16 or.b16 type.\nFor.f16x2 instruction type, operands d and a have.f16x2 or.b32 type.\nFor.bf16 instruction type, operands d and a have.b16 type.\nFor.bf16x2 instruction type, operands d and a have.b32 type.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#half-precision-floating-point-instructions-ex2", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_75" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.exit", "mnemonic": "exit", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "exit", "category": "Control Flow Instructions", "summary": "Ends execution of a thread.\nBarriers exclusively waiting on arrivals from exited threads are always released.", "syntax": "exit;", "syntax_forms": [ { "syntax": "exit;", "description": "Ends execution of a thread.\nBarriers exclusively waiting on arrivals from exited threads are always released.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "exit;\n@p exit;", "description": "Ends execution of a thread.\nBarriers exclusively waiting on arrivals from exited threads are always released.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#control-flow-instructions-exit", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.fabric.submit", "mnemonic": "fabric.submit", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "fabric.submit", "category": "Fabric Instructions", "summary": "Submits prior fabric operations issued by the current thread.", "syntax": "fabric.submit{.submitop};", "syntax_forms": [ { "syntax": "fabric.submit{.submitop};", "description": "Submits prior fabric operations issued by the current thread. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_100" ], "introducedIn": "PTX ISA 9.3" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "fabric.submit.op_restrict::fetching;\n\nfabric.submit;", "description": "Submits prior fabric operations issued by the current thread. For any thread to observe completion\nof fabric operations via an mbarrier object, the issuing thread is required to submit those\noperations before the barrier phase tracking these operations advances. Otherwise, the behavior is\nundefined. See Life of a Fabric Operation.\nIf.op_restrict::fetching is specified, then only prior fabric.try_get and fabric.try_pullred operations issued by the current thread are submitted. Otherwise, all prior\nfabric operations issued by the current thread are submitted.\nThis operation has no effect on fabric operations that have already been submitted.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#fabric-instructions-submit", "introducedIn": "PTX ISA 9.3", "requiredTargets": [ "sm_100" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.fabric.try_get", "mnemonic": "fabric.try_get", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "fabric.try_get", "category": "Fabric Instructions", "summary": "Asynchronously copies size bytes from fabric handle [srcLeId, srcDataOff] to destination memory [dst], where srcLeId is a 32-bit unsigned value denoting the logical endpoint identifier, and…", "syntax": "fabric.try_get.async.dst.completion_mechanism.sem.scope.b128 [dst], [srcLeId, srcDataOff], size, [bar];", "syntax_forms": [ { "syntax": "fabric.try_get.async.dst.completion_mechanism.sem.scope.b128 [dst], [srcLeId, srcDataOff], size, [bar];", "description": "Asynchronously copies size bytes from fabric handle [srcLeId, srcDataOff] to destination memory [dst], where srcLeId is a 32-bit unsigned value denoting the logical endpoint identifier, and srcDataOff… (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_100" ], "introducedIn": "PTX ISA 9.3" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "fabric.try_get.async.shared::cta.mbarrier::complete_tx::bytes.mbarrier::report::fabric.relaxed.sys.b128 [dstSmem], [srcLeId, srcLeOff], 0x100, [mbar];\n\nfabric.try_get.async.shared::cta.relaxed.sys.mbarrier::complete_tx::bytes.mbarrier::report::fabric.b128 [dstSmem], [srcLeId, srcLeOff], sizeBytes, [mbar];", "description": "Asynchronously copies size bytes from fabric handle [srcLeId, srcDataOff] to destination\nmemory [dst], where srcLeId is a 32-bit unsigned value denoting the logical endpoint\nidentifier, and srcDataOff is a 64-bit unsigned value denoting the base offset of the\nresource to access within the logical endpoint associated with srcLeId.\nThe logical endpoint associated with srcLeId must be a unicast logical endpoint.\nThe size operand is 32 bits and specifies the number of bytes to be copied. It must be a\nmultiple of 16; otherwise, the behavior is undefined. The range [dst, dst + size - 1] must be\nin bounds of the destination memory space. (see the official PTX ISA docs for the full description)", "sourceUrl": null, "introducedIn": "PTX ISA 9.3", "requiredTargets": [ "sm_100" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.fabric.try_pullred", "mnemonic": "fabric.try_pullred", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "fabric.try_pullred", "category": "Fabric Instructions", "summary": "Initiates asynchronous loads from multiple resources pointed to by multicast fabric handle [srcLeId, srcDataOff], of size bytes, and performs element-", "syntax": "fabric.try_pullred.async.multimem.dst.completion_mechanism.sem.scope.redOpBit.typeBit.sync [dst], [srcLeId, srcDataOff], size, [bar], imm-membermask;", "syntax_forms": [ { "syntax": "fabric.try_pullred.async.multimem.dst.completion_mechanism.sem.scope.redOpBit.typeBit.sync [dst], [srcLeId, srcDataOff], size, [bar], imm-membermask;", "description": "Initiates asynchronous loads from multiple resources pointed to by multicast fabric handle [srcLeId, srcDataOff], of size bytes, and performs element-wise reduction on data across\neach of the loads. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_100" ], "introducedIn": "PTX ISA 9.3" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "fabric.try_pullred.async.multimem.mbarrier::complete_tx::bytes.mbarrier::report::fabric.shared::cta.f32.add.sync.relaxed.sys [dst], [leId, offset], size, [mbar], imm-membermask;", "description": "Initiates asynchronous loads from multiple resources pointed to by multicast fabric handle [srcLeId, srcDataOff], of size bytes, and performs element-wise reduction on data across\neach of the loads. The result is stored in [dst, dst + size - 1]. srcLeId is a 32-bit\nunsigned value denoting the logical endpoint identifier, and srcDataOff is a 64-bit unsigned\nvalue denoting the base offset of the resources to access within the multicast logical endpoint\nassociated with srcLeId.\nThe size operand is 32 bits and specifies the number of bytes to be copied. It must be a\nmultiple of 16; otherwise, the behavior is undefined. (see the official PTX ISA docs for the full description)", "sourceUrl": null, "introducedIn": "PTX ISA 9.3", "requiredTargets": [ "sm_100" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.fabric.try_put", "mnemonic": "fabric.try_put", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "fabric.try_put", "category": "Fabric Instructions", "summary": "Asynchronously copies size bytes from [src] to destination fabric handle [dstLeId, dstDataOff], where dstLeId is a 32-bit unsigned value denoting the logical endpoint identifier, and dstDataOff is a…", "syntax": "fabric.try_put.async{.multimem}.src.completion_mechanism0.sem.scope.b128 [dstLeId, dstDataOff], [src], size, [bar];", "syntax_forms": [ { "syntax": "fabric.try_put.async{.multimem}.src.completion_mechanism0.sem.scope.b128 [dstLeId, dstDataOff], [src], size, [bar];", "description": "Asynchronously copies size bytes from [src] to destination fabric handle [dstLeId, dstDataOff], where dstLeId is a 32-bit unsigned value denoting the logical\nendpoint identifier, and dstDataOff is a 6 (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_100" ], "introducedIn": "PTX ISA 9.3" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "fabric.try_put.async.shared::cta.mbarrier::complete_tx::16B.mbarrier::report::fabric.relaxed.sys.b128 [dstLeId, dstLeOffData], [srcSmem], 0x100, [mbar];\n\nfabric.try_put.async.counted::bytes.shared::cta.mbarrier::complete_tx::16B.mbarrier::report::fabric.relaxed.sys.b128 [dstLeId, dstLeOffData, dstLeOffCntr], [srcSmem], size, [mbar];", "description": "Asynchronously copies size bytes from [src] to destination fabric handle [dstLeId, dstDataOff], where dstLeId is a 32-bit unsigned value denoting the logical\nendpoint identifier, and dstDataOff is a 64-bit unsigned value denoting the base offset of\nthe resource to access within the logical endpoint associated with dstLeId.\nThe size operand is 32 bits and specifies the number of bytes to be copied. It must be a\nmultiple of 16; otherwise, the behavior is undefined. The range [src, src + size - 1] must\nbe in bounds of the source memory space. (see the official PTX ISA docs for the full description)", "sourceUrl": null, "introducedIn": "PTX ISA 9.3", "requiredTargets": [ "sm_100" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.fabric.try_red", "mnemonic": "fabric.try_red", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "fabric.try_red", "category": "Fabric Instructions", "summary": "Asynchronously copies size bytes from [src] to destination fabric handle [dstLeId, dstDataOff] with element-wise reduction, where dstLeId is a 32-bit unsigned value denoting the logical endpoint…", "syntax": "fabric.try_red.async{.multimem}.src.completion_mechanism0.sem.scope.redOpBit.typeBit [dstLeId, dstDataOff], [src], size, [bar];", "syntax_forms": [ { "syntax": "fabric.try_red.async{.multimem}.src.completion_mechanism0.sem.scope.redOpBit.typeBit [dstLeId, dstDataOff], [src], size, [bar];", "description": "Asynchronously copies size bytes from [src] to destination fabric handle [dstLeId, dstDataOff] with element-wise reduction, where dstLeId is a 32-bit unsigned value denoting the logical endpoint ident… (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_100" ], "introducedIn": "PTX ISA 9.3" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "fabric.try_red.async.shared::cta.mbarrier::complete_tx::16B.mbarrier::report::fabric.relaxed.sys.add.u32 [dstLeId, dstLeOffData], [srcSmem], size, [mbar];\n\nfabric.try_red.async.counted::bytes.shared::cta.mbarrier::complete_tx::16B.mbarrier::report::fabric.add.u32 [dstLeId, dstLeOffData, dstLeOffCntr], [srcSmem], size, [mbar];", "description": "Asynchronously copies size bytes from [src] to destination fabric handle [dstLeId, dstDataOff] with element-wise reduction, where dstLeId is a 32-bit unsigned\nvalue denoting the logical endpoint identifier, and dstDataOff is a 64-bit unsigned value\ndenoting the base offset of the resource to access within the logical endpoint associated with dstLeId.\nThe size operand is 32 bits and specifies the number of bytes to be copied. It must be a\nmultiple of 16; otherwise, the behavior is undefined. The source range [src, src + size - 1] must be in bounds of the source memory space. (see the official PTX ISA docs for the full description)", "sourceUrl": null, "introducedIn": "PTX ISA 9.3", "requiredTargets": [ "sm_100" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.fabric.wait", "mnemonic": "fabric.wait", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "fabric.wait", "category": "Fabric Instructions", "summary": "Fabric-read completion mechanism instruction fabric.wait waits on the local shared memory (.shared::cta ) reads of submitted fabric operations.", "syntax": "fabric.wait.sync_restrict::reads;", "syntax_forms": [ { "syntax": "fabric.wait.sync_restrict::reads;", "description": "Fabric-read completion mechanism instruction fabric.wait waits on the local\nshared memory (.shared::cta ) reads of submitted fabric operations. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_100" ], "introducedIn": "PTX ISA 9.3" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "fabric.wait.sync_restrict::reads;", "description": "Fabric-read completion mechanism instruction fabric.wait waits on the local\nshared memory (.shared::cta ) reads of submitted fabric operations. This enables\noverwriting the shared memory read by these operations before they complete.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#fabric-instructions-wait", "introducedIn": "PTX ISA 9.3", "requiredTargets": [ "sm_100" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.fence", "mnemonic": "fence", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "fence", "category": "Parallel Synchronization and Communication Instructions", "summary": "The fence instruction establishes an ordering between memory accesses requested by this thread, as described by the memory consistency model.", "syntax": "// Thread fence:\nfence{.sem}.scope;", "syntax_forms": [ { "syntax": "// Thread fence:\nfence{.sem}.scope;", "description": "The fence instruction establishes an ordering between memory accesses requested by this thread, as described by the memory consistency model.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 1.4" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "Thread fence:", "desc": "Operand" } ], "semantics": null, "examples": "membar.gl;\nmembar.cta;\nmembar.sys;\nfence.sc.cta;\nfence.sc.cluster;\nfence.proxy.alias;\n// (truncated - see the official PTX ISA docs for the full example)", "description": "The fence instruction establishes an ordering between memory accesses requested by this thread (ld, st, atom and red instructions), as described by the memory consistency model. fence.acq_rel is a light-weight fence sufficient for memory synchronization in most programs, while fence.sc is a slower fence that can restore sequential consistency when used in sufficient places, at the cost of performance. The legacy membar instruction covers the thread-scope membar.level forms.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-membar", "introducedIn": "PTX ISA 1.4", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.fma", "mnemonic": "fma", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Fused Multiply-Add", "category": "Arithmetic", "summary": "Compute (a * b) + c with a single rounding step for improved precision over mad.", "syntax": "fma.rn.f64 d, a, b, c;", "syntax_forms": [ { "syntax": "fma.rn.f64 d, a, b, c;", "description": "Double-precision fused multiply-add.", "dataTypes": [ "f64" ], "stateSpaces": [], "scopes": [], "modifiers": [ "rn" ], "requiredTargets": [ "sm_13" ], "introducedIn": "PTX ISA 1.4" }, { "syntax": "fma.rn.f32 d, a, b, c;", "description": "Single-precision fused multiply-add.", "dataTypes": [ "f32" ], "stateSpaces": [], "scopes": [], "modifiers": [ "rn" ], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 2.0" } ], "dataTypes": [ "f32", "f64" ], "stateSpaces": [], "scopes": [], "modifiers": [ "rn" ], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Multiplicand" }, { "name": "b", "desc": "Multiplier" }, { "name": "c", "desc": "Addend" } ], "semantics": "d = round_once(a * b + c), the product is not rounded before the addition.", "examples": "fma.rn.ftz.f32 w,x,y,z;\n@p fma.rn.f64 d,a,b,c;\n fma.rp.ftz.f32x2 p,q,r,s;\n\n// scalar f16 fused multiply-add\nfma.rn.f16 d0, a0, b0, c0;\nfma.rn.f16 d1, a1, b1, c1;\nfma.rn.relu.f16 d1, a1, b1, c1;\nfma.rn.oob.f16 d1, a1, b1, c1;\nfma.rn.oob.relu.f16 d1, a1, b1, c1;\n// (truncated - see the official PTX ISA docs for the full example)\n\n.reg .f32 fc, fd;\n.reg .f16 ha, hb;\nfma.rz.sat.f32.f16.sat fd, ha, hb, fc;", "description": "Performs a fused multiply-add with no loss of precision in the intermediate product and addition.\nFor.f16x2 and.bf16x2 instruction type, forms input vectors by half word values from source\noperands. Half-word operands are then operated in parallel to produce.f16x2 or.bf16x2 result in destination.\nFor.f16 instruction type, operands d, a, b and c have.f16 or.b16 type. For.f16x2 instruction type, operands d, a, b and c have.b32 type. For.bf16 instruction type, operands d, a, b and c have.b16 type. For.bf16x2 instruction type, operands d, a, b and c have.b32 type.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#half-precision-floating-point-instructions-fma", "introducedIn": "PTX ISA 1.4", "requiredTargets": [ "sm_13" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.fns", "mnemonic": "fns", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "fns", "category": "Integer Arithmetic Instructions", "summary": "Given a 32-bit value mask and an integer value base (between 0 and 31), find the n-th (given by offset) set bit in mask from the base bit, and store the bit position in d.", "syntax": "fns.b32 d, mask, base, offset;", "syntax_forms": [ { "syntax": "fns.b32 d, mask, base, offset;", "description": "Given a 32-bit value mask and an integer value base (between 0 and 31), find the n-th (given\nby offset) set bit in mask from the base bit, and store the bit position in d. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_30" ], "introducedIn": "PTX ISA 6.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "mask", "desc": "Operand" }, { "name": "base", "desc": "Operand" }, { "name": "offset", "desc": "Operand" } ], "semantics": "d = 0xffffffff;\nif (offset == 0) {\n if (mask[base] == 1) {\n d = base;\n }\n} else {\n pos = base;\n count = |offset| - 1;\n inc = (offset > 0) ? 1 : -1;\n\n while ((pos >= 0) && (pos < 32)) {\n if (mask[pos] == 1) {\n if (count == 0) {\n d = pos;\n break;\n } else {\n count = count - 1;\n }\n }\n pos = pos + inc;\n }\n}", "examples": "fns.b32 d, 0xaaaaaaaa, 3, 1; // d = 3\nfns.b32 d, 0xaaaaaaaa, 3, -1; // d = 3\nfns.b32 d, 0xaaaaaaaa, 2, 1; // d = 3\nfns.b32 d, 0xaaaaaaaa, 2, -1; // d = 1", "description": "Given a 32-bit value mask and an integer value base (between 0 and 31), find the n-th (given\nby offset) set bit in mask from the base bit, and store the bit position in d. If not\nfound, store 0xffffffff in d.\nOperand mask has a 32-bit type. Operand base has.b32,.u32 or.s32 type. Operand offset has.s32 type. Destination d has type.b32.\nOperand base must be <= 31, otherwise behavior is undefined.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#integer-arithmetic-instructions-fns", "introducedIn": "PTX ISA 6.0", "requiredTargets": [ "sm_30" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.getctarank", "mnemonic": "getctarank", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "getctarank", "category": "Data Movement and Conversion Instructions", "summary": "Write the destination register d with the rank of the CTA which contains the address specified in operand a.", "syntax": "getctarank{.space}.type d, a;", "syntax_forms": [ { "syntax": "getctarank{.space}.type d, a;", "description": "Write the destination register d with the rank of the CTA which contains the address specified\nin operand a.\nInstruction type.type indicates the type of source operand a.\nWhen space is. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_90" ], "introducedIn": "PTX ISA 7.8" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" } ], "semantics": null, "examples": "getctarank.shared::cluster.u32 d1, addr;\ngetctarank.shared::cluster.u64 d2, sh + 4;\ngetctarank.u64 d3, src;", "description": "Write the destination register d with the rank of the CTA which contains the address specified\nin operand a.\nInstruction type.type indicates the type of source operand a.\nWhen space is.shared::cluster, source a is either a shared memory variable or a register\ncontaining a valid shared memory address. When the optional qualifier.space is not specified, a is a register containing a generic addresses pointing to shared memory. Destination d is\nalways a 32-bit register which holds the rank of the CTA.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-getctarank", "introducedIn": "PTX ISA 7.8", "requiredTargets": [ "sm_90" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.griddepcontrol", "mnemonic": "griddepcontrol", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "griddepcontrol", "category": "Parallel Synchronization and Communication Instructions", "summary": "The griddepcontrol instruction allows the dependent grids and prerequisite grids as defined by\nthe runtime, to control execution in the following way:", "syntax": "griddepcontrol.action;", "syntax_forms": [ { "syntax": "griddepcontrol.action;", "description": "The griddepcontrol instruction allows the dependent grids and prerequisite grids as defined by\nthe runtime, to control execution in the following way:. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_90" ], "introducedIn": "PTX ISA 7.8" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "griddepcontrol.launch_dependents;\ngriddepcontrol.wait;", "description": "The griddepcontrol instruction allows the dependent grids and prerequisite grids as defined by\nthe runtime, to control execution in the following way:.launch_dependents modifier signals that specific dependents the runtime system designated to\nreact to this instruction can be scheduled as soon as all other CTAs in the grid issue the same\ninstruction or have completed. The dependent may launch before the completion of the current\ngrid. There is no guarantee that the dependent will launch before the completion of the current\ngrid. Repeated invocations of this instruction by threads in the current CTA will have no additional\nside effects past that of the first invocation. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-griddepcontrol", "introducedIn": "PTX ISA 7.8", "requiredTargets": [ "sm_90" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.isspacep", "mnemonic": "isspacep", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "isspacep", "category": "Data Movement and Conversion Instructions", "summary": "Write predicate register p with 1 if generic address a falls within the specified state space window and with 0 otherwise.", "syntax": "isspacep.space p, a; // result is .pred", "syntax_forms": [ { "syntax": "isspacep.space p, a; // result is .pred", "description": "Write predicate register p with 1 if generic address a falls within the specified state\nspace window and with 0 otherwise. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 2.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "isspacep.const iscnst, cptr;\nisspacep.global isglbl, gptr;\nisspacep.local islcl, lptr;\nisspacep.shared isshrd, sptr;\nisspacep.param::entry isparam, pptr;\nisspacep.shared::cta isshrdcta, sptr;\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Write predicate register p with 1 if generic address a falls within the specified state\nspace window and with 0 otherwise. Destination p has type.pred; the source address\noperand must be of type.u32 or.u64.\nisspacep.param{::entry} returns 1 if the generic address falls within the window of Kernel Function Parameters, otherwise returns 0. If.param is specified without any sub-qualifiers then it defaults to.param::entry.\nisspacep.global returns 1 for Kernel Function Parameters as.param window is contained within the.global window.\nIf no sub-qualifier is specified with.shared state space, then::cta is assumed by default.\nNote ispacep. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-isspacep", "introducedIn": "PTX ISA 2.0", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.istypep", "mnemonic": "istypep", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "istypep", "category": "Texture Instructions", "summary": "Write predicate register p with 1 if register a points to an opaque variable of the\nspecified type, and with 0 otherwise. Destination p has type.pred;", "syntax": "istypep.type p, a; // result is .pred", "syntax_forms": [ { "syntax": "istypep.type p, a; // result is .pred", "description": "Write predicate register p with 1 if register a points to an opaque variable of the\nspecified type, and with 0 otherwise. Destination p has type.pred; the source address\noperand must be of type.u64.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_30" ], "introducedIn": "PTX ISA 4.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "istypep.texref istex, tptr;\nistypep.samplerref issampler, sptr;\nistypep.surfref issurface, surfptr;", "description": "Write predicate register p with 1 if register a points to an opaque variable of the\nspecified type, and with 0 otherwise. Destination p has type.pred; the source address\noperand must be of type.u64.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#texture-instructions-istypep", "introducedIn": "PTX ISA 4.0", "requiredTargets": [ "sm_30" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.ld", "mnemonic": "ld", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Load", "category": "Data Movement and Conversion Instructions", "summary": "Load a value from the specified state space into a register.", "syntax": "ld.space.type d, [a];", "syntax_forms": [ { "syntax": "ld.space.type d, [a];", "description": "Load from an explicit state space.", "dataTypes": [ "b8", "b16", "b32", "b64", "s8", "s16", "s32", "s64", "u8", "u16", "u32", "u64", "f16", "f32", "f64" ], "stateSpaces": [ "global", "local", "shared", "param", "const" ], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" }, { "syntax": "ld.global.nc.type d, [a];", "description": "Load through the read-only (non-coherent) data cache.", "dataTypes": [], "stateSpaces": [ "global" ], "scopes": [], "modifiers": [ "nc" ], "requiredTargets": [ "sm_35" ], "introducedIn": "PTX ISA 4.0" } ], "dataTypes": [ "b16", "b32", "b64", "b8", "f16", "f32", "f64", "s16", "s32", "s64", "s8", "u16", "u32", "u64", "u8" ], "stateSpaces": [ "const", "global", "local", "param", "shared" ], "scopes": [], "modifiers": [ "nc" ], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source address" } ], "semantics": "d = *a, from the given state space.", "examples": "ld.global.f32 d,[a];\nld.shared.v4.b32 Q,[p];\nld.const.s32 d,[p+4];\nld.local.b32 x,[p+-8]; // negative offset\nld.local.b64 x,[240]; // immediate address\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Load register variable d from the location specified by the source address operand a in\nspecified state space. If no state space is given, perform the load using Generic Addressing.\nIf no sub-qualifier is specified with.shared state space, then::cta is assumed by default.\nSupported addressing modes for operand a and alignment requirements are described in Addresses as Operands\nIf no sub-qualifier is specified with.param state space, then:::func is assumed when access is inside a device function.::entry is assumed when accessing kernel function parameters from entry function. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-ld", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.ld.global.nc", "mnemonic": "ld.global.nc", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "ld.global.nc", "category": "Data Movement and Conversion Instructions", "summary": "Load register variable d from the location specified by the source address operand a in the global state space, and optionally cache in non-coherent read-only cache.", "syntax": "ld.global{.cop}.nc{.level::cache_hint}{.level::prefetch_size}.type d, [a]{, cache_policy};", "syntax_forms": [ { "syntax": "ld.global{.cop}.nc{.level::cache_hint}{.level::prefetch_size}.type d, [a]{, cache_policy};", "description": "Load register variable d from the location specified by the source address operand a in the\nglobal state space, and optionally cache in non-coherent read-only cache. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_32" ], "introducedIn": "PTX ISA 3.1" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": "d = a; // named variable a\nd = *(&a+immOff) // variable-plus-offset\nd = *a; // register\nd = *(a+immOff); // register-plus-offset\nd = *(immAddr); // immediate address", "examples": "ld.global.nc.f32 d, [a];\nld.gloal.nc.L1::evict_last.u32 d, [a];\n\ncreatepolicy.fractional.L2::evict_last.b64 cache_policy, 0.5;\nld.global.nc.L2::cache_hint.f32 d, [a], cache_policy;\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Load register variable d from the location specified by the source address operand a in the\nglobal state space, and optionally cache in non-coherent read-only cache.\nNote On some architectures, the texture cache is larger, has higher bandwidth, and longer latency than\nthe global memory cache. For applications with sufficient parallelism to cover the longer\nlatency, ld.global.nc should offer better performance than ld.global on such\narchitectures.\nThe address operand a shall contain a global address.\nSupported addressing modes for operand a and alignment requirements are\ndescribed in Addresses as Operands.\nThe.v8 (.vec ) qualifier is supported if:.type is.b32,.s32,.u32, or. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-ld-global-nc", "introducedIn": "PTX ISA 3.1", "requiredTargets": [ "sm_32" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.ldmatrix", "mnemonic": "ldmatrix", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "ldmatrix", "category": "Warp Level Matrix Multiply-Accumulate Instructions", "summary": "Collectively load one or more matrices across all threads in a warp from the location indicated by the address operand p, from.shared state space into destination register r.", "syntax": "ldmatrix.sync.aligned.shape.num{.trans}{.ss}.type r, [p];", "syntax_forms": [ { "syntax": "ldmatrix.sync.aligned.shape.num{.trans}{.ss}.type r, [p];", "description": "Collectively load one or more matrices across all threads in a warp from the location indicated by\nthe address operand p, from.shared state space into destination register r. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_75" ], "introducedIn": "PTX ISA 6.5" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "// Load a single 8x8 matrix using 64-bit addressing\n.reg .b64 addr;\n.reg .b32 d;\nldmatrix.sync.aligned.m8n8.x1.shared::cta.b16 {d}, [addr];\n\n// Load two 8x8 matrices in column-major format\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Collectively load one or more matrices across all threads in a warp from the location indicated by\nthe address operand p, from.shared state space into destination register r. If no state\nspace is provided, generic addressing is used, such that the address in p points into.shared space. If the generic address doesn’t fall in.shared state space, then the behavior\nis undefined.\nThe.shape qualifier indicates the dimensions of the matrices being loaded. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#warp-level-matrix-instructions-ldmatrix", "introducedIn": "PTX ISA 6.5", "requiredTargets": [ "sm_75" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.ldu", "mnemonic": "ldu", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "ldu", "category": "Data Movement and Conversion Instructions", "summary": "Load read-only data into register variable d from the location specified by the source address operand a in the global state space, where the address is guaranteed to be the same across all threads in the warp.", "syntax": "ldu{.ss}.type d, [a]; // load from address", "syntax_forms": [ { "syntax": "ldu{.ss}.type d, [a]; // load from address", "description": "Load read-only data into register variable d from the location specified by the source address operand a in the global state space, where the address is guaranteed to be the same across all threads in… (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_13" ], "introducedIn": "PTX ISA 2.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": "d = a; // named variable a\nd = *(&a+immOff) // variable-plus-offset\nd = *a; // register\nd = *(a+immOff); // register-plus-offset\nd = *(immAddr); // immediate address", "examples": "ldu.global.f32 d,[a];\nldu.global.b32 d,[p+4];\nldu.global.v4.f32 Q,[p];\nldu.global.b128 d,[a];", "description": "Load read-only data into register variable d from the location specified by the source address\noperand a in the global state space, where the address is guaranteed to be the same across all\nthreads in the warp. If no state space is given, perform the load using Generic Addressing.\nSupported addressing modes for operand a and alignment requirements are described in Addresses as Operands.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-ldu", "introducedIn": "PTX ISA 2.0", "requiredTargets": [ "sm_13" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.lg2", "mnemonic": "lg2", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Base-2 Logarithm (Approximate)", "category": "Arithmetic", "summary": "Fast hardware approximation of log2(x).", "syntax": "lg2.approx.f32 d, a;", "syntax_forms": [ { "syntax": "lg2.approx.f32 d, a;", "description": "Reduced-precision base-2 logarithm.", "dataTypes": [ "f32" ], "stateSpaces": [], "scopes": [], "modifiers": [ "approx" ], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [ "f32" ], "stateSpaces": [], "scopes": [], "modifiers": [ "approx" ], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" } ], "semantics": "d ≈ log2(a).", "examples": "lg2.approx.ftz.f32 la, a;", "description": "Determine the log 2 of a.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#floating-point-instructions-lg2", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.lop3", "mnemonic": "lop3", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "lop3", "category": "Logic and Shift Instructions", "summary": "Compute bitwise logical operation on inputs a, b, c and store the result in destination d.", "syntax": "lop3.b32 d, a, b, c, immLut;", "syntax_forms": [ { "syntax": "lop3.b32 d, a, b, c, immLut;", "description": "Compute bitwise logical operation on inputs a, b, c and store the result in destination d.\nOptionally,. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_50" ], "introducedIn": "PTX ISA 4.3" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" }, { "name": "b", "desc": "Source operand" }, { "name": "c", "desc": "Source operand" }, { "name": "immLut", "desc": "Operand" } ], "semantics": "F = GetFunctionFromTable(immLut); // returns the function corresponding to immLut value\nd = F(a, b, c);\nif (BoolOp specified) {\n p = (d != 0) BoolOp q;\n}", "examples": "lop3.b32 d, a, b, c, 0x40;\nlop3.or.b32 d|p, a, b, c, 0x3f, q;\nlop3.and.b32 _|p, a, b, c, 0x3f, q;", "description": "Compute bitwise logical operation on inputs a, b, c and store the result in destination d.\nOptionally,.BoolOp can be specified to compute the predicate result p by performing a\nBoolean operation on the destination operand d with the predicate q in the following manner:\np = (d != 0) BoolOp q;\nThe sink symbol ‘_’ may be used in place of the destination operand d when.BoolOp qualifier\nis specified.\nThe logical operation is defined by a look-up table which, for 3 inputs, can be represented as an\n8-bit value specified by operand immLut as described below. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#logic-and-shift-instructions-lop3", "introducedIn": "PTX ISA 4.3", "requiredTargets": [ "sm_50" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.mad", "mnemonic": "mad", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Multiply-Add", "category": "Arithmetic", "summary": "Compute (a * b) + c as two rounding steps (unlike fma, which fuses them into one).", "syntax": "mad.mode.stype d, a, b, c;", "syntax_forms": [ { "syntax": "mad.mode.stype d, a, b, c;", "description": "Integer multiply-add.", "dataTypes": [ "s16", "s32", "s64", "u16", "u32", "u64" ], "stateSpaces": [], "scopes": [], "modifiers": [ "lo", "hi", "wide" ], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" }, { "syntax": "mad.f32 d, a, b, c;", "description": "Single-precision floating-point multiply-add (not fused).", "dataTypes": [ "f32" ], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [ "f32", "s16", "s32", "s64", "u16", "u32", "u64" ], "stateSpaces": [], "scopes": [], "modifiers": [ "hi", "lo", "wide" ], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Multiplicand" }, { "name": "b", "desc": "Multiplier" }, { "name": "c", "desc": "Addend" } ], "semantics": "d = (a * b) + c.", "examples": "@p mad.lo.s32 d,a,b,c;\n mad.lo.s32 r,p,q,r;\n\n@p mad.f32 d,a,b,c;", "description": "Multiplies two values, optionally extracts the high or low half of the intermediate result, and adds\na third value. Writes the result into a destination register.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#integer-arithmetic-instructions-mad", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.mad.cc", "mnemonic": "mad.cc", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "mad.cc", "category": "Extended-Precision Integer Arithmetic Instructions", "summary": "Multiplies two values, extracts either the high or low part of the result, and adds a third value.", "syntax": "mad{.hi,.lo}.cc.type d, a, b, c;", "syntax_forms": [ { "syntax": "mad{.hi,.lo}.cc.type d, a, b, c;", "description": "Multiplies two values, extracts either the high or low part of the result, and adds a third\nvalue. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 3.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" }, { "name": "b", "desc": "Source operand" }, { "name": "c", "desc": "Source operand" } ], "semantics": "t = a * b;\nd = t<63..32> + c; // for .hi variant\nd = t<31..0> + c; // for .lo variant", "examples": "@p mad.lo.cc.u32 d,a,b,c;\n mad.lo.cc.u32 r,p,q,r;", "description": "Multiplies two values, extracts either the high or low part of the result, and adds a third\nvalue. Writes the result to the destination register and the carry-out from the addition into the\ncondition code register.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#extended-precision-arithmetic-instructions-mad-cc", "introducedIn": "PTX ISA 3.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.mad24", "mnemonic": "mad24", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "mad24", "category": "Integer Arithmetic Instructions", "summary": "Compute the product of two 24-bit integer values held in 32-bit source registers, and add a third, 32-bit value to either the high or low 32-bits of the 48-bit result.", "syntax": "mad24.mode.type d, a, b, c;", "syntax_forms": [ { "syntax": "mad24.mode.type d, a, b, c;", "description": "Compute the product of two 24-bit integer values held in 32-bit source registers, and add a third,\n32-bit value to either the high or low 32-bits of the 48-bit result. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" }, { "name": "b", "desc": "Source operand" }, { "name": "c", "desc": "Source operand" } ], "semantics": "t = a * b;\nd = t<47..16> + c; // for .hi variant\nd = t<31..0> + c; // for .lo variant", "examples": "mad24.lo.s32 d,a,b,c; // low 32-bits of 24x24-bit signed multiply.", "description": "Compute the product of two 24-bit integer values held in 32-bit source registers, and add a third,\n32-bit value to either the high or low 32-bits of the 48-bit result. Return either the high or low\n32-bits of the 48-bit result.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#integer-arithmetic-instructions-mad24", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.madc", "mnemonic": "madc", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "madc", "category": "Extended-Precision Integer Arithmetic Instructions", "summary": "Multiplies two values, extracts either the high or low part of the result, and adds a third value along with carry-in.", "syntax": "madc{.hi,.lo}{.cc}.type d, a, b, c;", "syntax_forms": [ { "syntax": "madc{.hi,.lo}{.cc}.type d, a, b, c;", "description": "Multiplies two values, extracts either the high or low part of the result, and adds a third value\nalong with carry-in. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 3.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" }, { "name": "b", "desc": "Source operand" }, { "name": "c", "desc": "Source operand" } ], "semantics": "t = a * b;\nd = t<63..32> + c + CC.CF; // for .hi variant\nd = t<31..0> + c + CC.CF; // for .lo variant", "examples": "// extended-precision multiply: [r3,r2,r1,r0] = [r5,r4] * [r7,r6]\nmul.lo.u32 r0,r4,r6; // r0=(r4*r6).[31:0], no carry-out\nmul.hi.u32 r1,r4,r6; // r1=(r4*r6).[63:32], no carry-out\nmad.lo.cc.u32 r1,r5,r6,r1; // r1+=(r5*r6).[31:0], may carry-out\nmadc.hi.u32 r2,r5,r6,0; // r2 =(r5*r6).[63:32]+carry-in,\n // no carry-out\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Multiplies two values, extracts either the high or low part of the result, and adds a third value\nalong with carry-in. Writes the result to the destination register and optionally writes the\ncarry-out from the addition into the condition code register.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#extended-precision-arithmetic-instructions-madc", "introducedIn": "PTX ISA 3.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.mapa", "mnemonic": "mapa", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "mapa", "category": "Data Movement and Conversion Instructions", "summary": "Get address in the CTA specified by operand b which corresponds to the address specified by operand a.", "syntax": "mapa{.space}.type d, a, b;", "syntax_forms": [ { "syntax": "mapa{.space}.type d, a, b;", "description": "Get address in the CTA specified by operand b which corresponds to the address specified by\noperand a.\nInstruction type.type indicates the type of the destination operand d and the source\noperand a.\nW (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_90" ], "introducedIn": "PTX ISA 7.8" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" }, { "name": "b", "desc": "Source operand" } ], "semantics": null, "examples": "mapa.shared::cluster.u64 d1, %reg1, cta;\nmapa.shared::cluster.u32 d2, sh, 3;\nmapa.u64 d3, %reg2, cta;", "description": "Get address in the CTA specified by operand b which corresponds to the address specified by\noperand a.\nInstruction type.type indicates the type of the destination operand d and the source\noperand a.\nWhen space is.shared::cluster, source a is either a shared memory variable or a register\ncontaining a valid shared memory address and register d contains a shared memory address. When\nthe optional qualifier.space is not specified, both a and d are registers containing\ngeneric addresses pointing to shared memory.\nb is a 32-bit integer operand representing the rank of the target CTA.\nDestination register d will hold an address in CTA b corresponding to operand a.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-mapa", "introducedIn": "PTX ISA 7.8", "requiredTargets": [ "sm_90" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.match.sync", "mnemonic": "match.sync", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "match.sync", "category": "Parallel Synchronization and Communication Instructions", "summary": "match.sync will cause executing thread to wait until all non-exited threads from membermask have executed match.sync with the same qualifiers and same membermask value before resuming execution.", "syntax": "match.any.sync.type d, a, membermask;", "syntax_forms": [ { "syntax": "match.any.sync.type d, a, membermask;", "description": "match.sync will cause executing thread to wait until all non-exited threads from membermask have executed match.sync with the same qualifiers and same membermask value before resuming\nexecution. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_70" ], "introducedIn": "PTX ISA 6.0" }, { "syntax": "match.all.sync.type d[|p], a, membermask;", "description": "match.all returns the mask only if all non-exited threads in membermask share the same value of operand a; the optional predicate p is set accordingly.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_70" ], "introducedIn": "PTX ISA 6.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" }, { "name": "membermask", "desc": "Operand" } ], "semantics": null, "examples": "match.any.sync.b32 d, a, 0xffffffff;\nmatch.all.sync.b64 d|p, a, mask;", "description": "match.sync will cause executing thread to wait until all non-exited threads from membermask have executed match.sync with the same qualifiers and same membermask value before resuming\nexecution.\nOperand membermask specifies a 32-bit integer which is a mask indicating threads participating\nin this instruction where the bit position corresponds to thread’s laneid.\nmatch.sync performs broadcast and compare of operand a across all non-exited threads in membermask and sets destination d and optional predicate p based on mode.\nOperand a has instruction type and d has.b32 type.\nDestination d is a 32-bit mask where bit position in mask corresponds to thread’s laneid. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-match-sync", "introducedIn": "PTX ISA 6.0", "requiredTargets": [ "sm_70" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.max", "mnemonic": "max", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Maximum", "category": "Arithmetic", "summary": "Select the larger of two operands.", "syntax": "max.type d, a, b;", "syntax_forms": [ { "syntax": "max.type d, a, b;", "description": "Integer or floating-point maximum.", "dataTypes": [ "s16", "s32", "s64", "u16", "u32", "u64", "f32", "f64" ], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [ "f32", "f64", "s16", "s32", "s64", "u16", "u32", "u64" ], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "First operand" }, { "name": "b", "desc": "Second operand" } ], "semantics": "d = (a > b) ? a : b, with type-specific NaN-handling rules for floating-point forms.", "examples": "max.u32 d,a,b;\nmax.s32 q,q,0;\nmax.relu.s16x2 t,t,u;\nmax.u8x4 p, q, r;\n\nmax.ftz.f32 f0,f1,f2;\nmax.f64 a,b,c;\n// fp32 max with .NaN\nmax.NaN.f32 f0,f1,f2;\n// fp32 max with .xorsign.abs\nmax.xorsign.abs.f32 Rd, Ra, Rb;\n\nmax.ftz.f16 h0,h1,h2;\nmax.f16x2 b0,b1,b2;\n// SIMD fp16 max with NaN\nmax.NaN.f16x2 b0,b1,b2;\n// scalar f16 max with xorsign.abs\nmax.xorsign.abs.f16 Rd, Ra, Rb;\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Store the maximum of a and b in d.\nFor.f16x2 and.bf16x2 instruction types, input vectors are formed with half-word values\nfrom source operands. Half-word operands are then processed in parallel to store.f16x2 or.bf16x2 result in destination.\nFor.f16 instruction type, operands d and a have.f16 or.b16 type. For.f16x2 instruction type, operands d and a have.f16x2 or.b32 type. For.bf16 instruction type, operands d and a have.b16 type. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#half-precision-floating-point-instructions-max", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.mbarrier.arrive", "mnemonic": "mbarrier.arrive", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "mbarrier.arrive", "category": "Parallel Synchronization and Communication Instructions", "summary": "A thread executing mbarrier.arrive performs an arrive-on operation\non the mbarrier object at the location specified by the address operand addr. The 3", "syntax": "mbarrier.arrive{.sem.scope}{.shared{::cta}}.b64 state, [addr]{, count};", "syntax_forms": [ { "syntax": "mbarrier.arrive{.sem.scope}{.shared{::cta}}.b64 state, [addr]{, count};", "description": "A thread executing mbarrier.arrive performs an arrive-on operation\non the mbarrier object at the location specified by the address operand addr. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_80" ], "introducedIn": "PTX ISA 7.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": ".reg .b32 cnt, remoteAddr32, remoteCTAId, addr32;\n.reg .b64 %r<5>, addr, remoteAddr64;\n.shared .b64 shMem, shMem2;\n\ncvta.shared.u64 addr, shMem2;\nmov.b32 addr32, shMem2;\n// (truncated - see the official PTX ISA docs for the full example)", "description": "A thread executing mbarrier.arrive performs an arrive-on operation\non the mbarrier object at the location specified by the address operand addr. The 32-bit\nunsigned integer operand count specifies the count argument to the arrive-on operation.\nIf no state space is specified then Generic Addressing is\nused. If the address specified by addr does not fall within the address window of.shared::cta state space then the behavior is undefined.\nSupported addressing modes for operand addr is as described in Addresses as Operands.\nAlignment for operand addr is as described in the Size and alignment of mbarrier object.\nThe optional qualifier. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier-arrive", "introducedIn": "PTX ISA 7.0", "requiredTargets": [ "sm_80" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.mbarrier.arrive_drop", "mnemonic": "mbarrier.arrive_drop", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "mbarrier.arrive_drop", "category": "Parallel Synchronization and Communication Instructions", "summary": "A thread executing mbarrier.arrive_drop on the mbarrier object at the location specified by the address operand addr performs the following steps: Decrements the expected arrival count of the mbarrier object by the value specified by the 32-bit integer operand count.", "syntax": "mbarrier.arrive_drop{.sem.scope}{.shared{::cta}}.b64 state, [addr] {, count};", "syntax_forms": [ { "syntax": "mbarrier.arrive_drop{.sem.scope}{.shared{::cta}}.b64 state, [addr] {, count};", "description": "A thread executing mbarrier.arrive_drop on the mbarrier object at the location specified by the address operand addr performs the following steps: Decrements the expected arrival count of the mbarrier… (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_80" ], "introducedIn": "PTX ISA 7.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": ".reg .b32 cnt;\n.reg .b64 %r1;\n.shared .b64 shMem;\n\n// Example 1\n@p mbarrier.arrive_drop.shared.b64 _, [shMem];\n// (truncated - see the official PTX ISA docs for the full example)", "description": "A thread executing mbarrier.arrive_drop on the mbarrier object at the location specified by\nthe address operand addr performs the following steps:\nDecrements the expected arrival count of the mbarrier object by the value specified by the\n32-bit integer operand count. If count operand is not specified, it defaults to 1. Performs an arrive-on operation on the mbarrier object. The operand count specifies the count argument to the arrive-on operation.\nThe decrement done in the expected arrivals count of the mbarrier object will be for all the\nsubsequent phases of the mbarrier object.\nIf no state space is specified then Generic Addressing is\nused. (see the official PTX ISA docs for the full description)", "sourceUrl": null, "introducedIn": "PTX ISA 7.0", "requiredTargets": [ "sm_80" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.mbarrier.check_layout", "mnemonic": "mbarrier.check_layout", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "mbarrier.check_layout", "category": "Parallel Synchronization and Communication Instructions", "summary": "The layout of the opaque mbarrier object can be queried using mbarrier.check_layout.", "syntax": "mbarrier.check_layout.layout{.ss}.b64 p, [addr];", "syntax_forms": [ { "syntax": "mbarrier.check_layout.layout{.ss}.b64 p, [addr];", "description": "The layout of the opaque mbarrier object can be queried using mbarrier.check_layout.\nThe address operand addr specifies the memory location of the mbarrier object whose\nlayout is being inspected. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_90" ], "introducedIn": "PTX ISA 9.3" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": ".reg .pred p;\n.shared .b64 shMem;\n\nmbarrier.check_layout.layout::v1.shared::cta.b64 p, [shMem];\n@!p bra exit\n// ... mbarrier operations on shMem\n// (truncated - see the official PTX ISA docs for the full example)", "description": "The layout of the opaque mbarrier object can be queried using mbarrier.check_layout.\nThe address operand addr specifies the memory location of the mbarrier object whose\nlayout is being inspected. The instruction sets the predicate operand p to True if the\nlayout of the mbarrier object exactly matches the.layout qualifier. Refer Layouts of the mbarrier object for\nmore details.\nIf no state space is specified then Generic Addressing is used. If the address specified\nby addr does not fall within the address window of.shared::cta state space then the\nbehavior is undefined.", "sourceUrl": null, "introducedIn": "PTX ISA 9.3", "requiredTargets": [ "sm_90" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.mbarrier.complete_tx", "mnemonic": "mbarrier.complete_tx", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "mbarrier.complete_tx", "category": "Parallel Synchronization and Communication Instructions", "summary": "A thread executing mbarrier.complete_tx performs a complete-tx operation on the mbarrier object at the location specified by the address operand addr.", "syntax": "mbarrier.complete_tx{.sem.scope}{.space}.b64 [addr], txCount;", "syntax_forms": [ { "syntax": "mbarrier.complete_tx{.sem.scope}{.space}.b64 [addr], txCount;", "description": "A thread executing mbarrier.complete_tx performs a complete-tx operation on the mbarrier object at the location specified by the address operand addr. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_90" ], "introducedIn": "PTX ISA 8.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "mbarrier.complete_tx.b64 [addr], 32;\nmbarrier.complete_tx.shared.b64 [mbarObj1], 512;\nmbarrier.complete_tx.relaxed.cta.b64 [addr2], 32;", "description": "A thread executing mbarrier.complete_tx performs a complete-tx operation on the mbarrier object at the location specified by the address operand addr. The\n32-bit unsigned integer operand txCount specifies the completeCount argument to the complete-tx operation.\nmbarrier.complete_tx does not involve any asynchronous memory operations and only simulates the\ncompletion of an asynchronous memory operation and its side effect of signaling to the mbarrier\nobject.\nIf no state space is specified then Generic Addressing is\nused. (see the official PTX ISA docs for the full description)", "sourceUrl": null, "introducedIn": "PTX ISA 8.0", "requiredTargets": [ "sm_90" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.mbarrier.expect_tx", "mnemonic": "mbarrier.expect_tx", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "mbarrier.expect_tx", "category": "Parallel Synchronization and Communication Instructions", "summary": "A thread executing mbarrier.expect_tx performs an expect-tx operation on the mbarrier object at the location specified by the address operand addr.", "syntax": "mbarrier.expect_tx{.sem.scope}{.space}.b64 [addr], txCount;", "syntax_forms": [ { "syntax": "mbarrier.expect_tx{.sem.scope}{.space}.b64 [addr], txCount;", "description": "A thread executing mbarrier.expect_tx performs an expect-tx operation on the mbarrier object at the location specified by the address operand addr. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_90" ], "introducedIn": "PTX ISA 8.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "mbarrier.expect_tx.b64 [addr], 32;\nmbarrier.expect_tx.relaxed.cta.shared.b64 [mbarObj1], 512;\nmbarrier.expect_tx.relaxed.cta.shared.b64 [mbarObj2], 512;", "description": "A thread executing mbarrier.expect_tx performs an expect-tx operation on the mbarrier object at the location specified by the address operand addr. The\n32-bit unsigned integer operand txCount specifies the expectCount argument to the expect-tx operation.\nIf no state space is specified then Generic Addressing is\nused. If the address specified by addr does not fall within the address window of.shared::cta or.shared::cluster state space then the behavior is undefined.\nSupported addressing modes for operand addr are as described in Addresses as Operands.\nAlignment for operand addr is as described in the Size and alignment of mbarrier object.\nThe optional. (see the official PTX ISA docs for the full description)", "sourceUrl": null, "introducedIn": "PTX ISA 8.0", "requiredTargets": [ "sm_90" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.mbarrier.init", "mnemonic": "mbarrier.init", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "mbarrier.init", "category": "Parallel Synchronization and Communication Instructions", "summary": "mbarrier.init initializes the mbarrier object at the location specified by the address operand addr with the unsigned 32-bit integer count.", "syntax": "mbarrier.init{.layout}{.shared{::cta}}.b64 [addr], count;", "syntax_forms": [ { "syntax": "mbarrier.init{.layout}{.shared{::cta}}.b64 [addr], count;", "description": "mbarrier.init initializes the mbarrier object at the location specified by the address operand addr with the unsigned 32-bit integer count.\nThe. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_80" ], "introducedIn": "PTX ISA 7.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": ".shared .b64 shMem, shMem2, shMem3;\n.reg .b64 addr;\n.reg .b32 %r1;\n\ncvta.shared.u64 addr, shMem2;\nmbarrier.init.b64 [addr], %r1;\n// (truncated - see the official PTX ISA docs for the full example)", "description": "mbarrier.init initializes the mbarrier object at the location specified by the address operand addr with the unsigned 32-bit integer count.\nThe.layout qualifier specifies the layout that is used to initialize the mbarrier object.\nIf not specified explicitly, a.layout::v0 mbarrier is initialized.\nRefer Layouts of the mbarrier object for more details.\nThe valid range of values for the operand count varies depending upon.layout as\nspecified below:\n[1, …, 2 20 - 1] for mbarrier with.layout::v0 [1, …, 2 9 - 1] for mbarrier with.layout::v1\nThe constituents of the mbarrier object are initialized as follows:\nThe primary and conditional phases are initialized to zero. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier-init", "introducedIn": "PTX ISA 7.0", "requiredTargets": [ "sm_80" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.mbarrier.inval", "mnemonic": "mbarrier.inval", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "mbarrier.inval", "category": "Parallel Synchronization and Communication Instructions", "summary": "mbarrier.inval invalidates the mbarrier object at the location specified by the address operand addr.", "syntax": "mbarrier.inval{.shared{::cta}}.b64 [addr];", "syntax_forms": [ { "syntax": "mbarrier.inval{.shared{::cta}}.b64 [addr];", "description": "mbarrier.inval invalidates the mbarrier object at the location specified by the address\noperand addr.\nThe invalidation is supported for all layouts described in Layouts of the mbarrier object. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_80" ], "introducedIn": "PTX ISA 7.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": ".shared .b64 shmem;\n.reg .b64 addr;\n.reg .b32 %r1;\n.reg .pred t0;\n\n// Example 1 :\n// (truncated - see the official PTX ISA docs for the full example)", "description": "mbarrier.inval invalidates the mbarrier object at the location specified by the address\noperand addr.\nThe invalidation is supported for all layouts described in Layouts of the mbarrier object.\nAn mbarrier object must be invalidated before using its memory location for any other purpose.\nPerforming any mbarrier operation except mbarrier.init on a memory location that does not\ncontain a valid mbarrier object, results in undefined behaviour.\nIf no state space is specified then Generic Addressing is\nused. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier-inval", "introducedIn": "PTX ISA 7.0", "requiredTargets": [ "sm_80" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.mbarrier.pending_count", "mnemonic": "mbarrier.pending_count", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "mbarrier.pending_count", "category": "Parallel Synchronization and Communication Instructions", "summary": "The pending count can be queried from the opaque mbarrier state using mbarrier.pending_count.", "syntax": "mbarrier.pending_count{.layout}.b64 count, state;", "syntax_forms": [ { "syntax": "mbarrier.pending_count{.layout}.b64 count, state;", "description": "The pending count can be queried from the opaque mbarrier state using mbarrier.pending_count.\nThe state operand is a 64-bit register that must be the result of a prior mbarrier.arrive. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_80" ], "introducedIn": "PTX ISA 7.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "count", "desc": "Operand" }, { "name": "state", "desc": "Operand" } ], "semantics": null, "examples": ".reg .b32 %r1;\n.reg .b64 state;\n.shared .b64 shMem;\n\nmbarrier.arrive.noComplete.b64 state, [shMem], 1;\nmbarrier.pending_count.layout::v0.b64 %r1, state;", "description": "The pending count can be queried from the opaque mbarrier state using mbarrier.pending_count.\nThe state operand is a 64-bit register that must be the result of a prior mbarrier.arrive.noComplete or mbarrier.arrive_drop.noComplete instruction. Otherwise, the\nbehavior is undefined.\nThe destination register count is a 32-bit unsigned integer representing the pending count of\nthe mbarrier object prior to the arrive-on operation from\nwhich the state register was obtained.\nThe optional qualifier.layout::v0 denotes the layout of the corresponding mbarrier object as\ndescribed in the section Layouts of the mbarrier object.", "sourceUrl": null, "introducedIn": "PTX ISA 7.0", "requiredTargets": [ "sm_80" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.mbarrier.test_wait", "mnemonic": "mbarrier.test_wait", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "mbarrier.test_wait", "category": "Parallel Synchronization and Communication Instructions", "summary": "The test_wait and try_wait operations test for the completion of the current or the immediately preceding phase of an mbarrier object at the location specified by the operand addr.", "syntax": "// without parity\nmbarrier.test_wait{.phase_type::primary}{.sem.scope}{.ss}.b64 waitComplete, [addr], state;", "syntax_forms": [ { "syntax": "// without parity\nmbarrier.test_wait{.phase_type::primary}{.sem.scope}{.ss}.b64 waitComplete, [addr], state;", "description": "The test_wait and try_wait operations test for the completion of the current or the immediately\npreceding phase of an mbarrier object at the location specified by the operand addr.\nmbarrier. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_80" ], "introducedIn": "PTX ISA 7.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "without parity", "desc": "Operand" } ], "semantics": null, "examples": "// Example 1a, thread synchronization with test_wait:\n\n.reg .b64 %r1;\n.shared .b64 shMem;\n\nmbarrier.init.shared.b64 [shMem], N; // N threads participating in the mbarrier.\n// (truncated - see the official PTX ISA docs for the full example)", "description": "The test_wait and try_wait operations test for the completion of the current or the immediately\npreceding phase of an mbarrier object at the location specified by the operand addr.\nmbarrier.test_wait is a non-blocking instruction which tests for the completion of the phase.\nmbarrier.try_wait is a potentially blocking instruction which tests for the completion of the\nphase. If the phase is not complete, the executing thread may be suspended. Suspended thread resumes\nexecution when the specified phase completes OR before the phase completes following a\nsystem-dependent time limit. (see the official PTX ISA docs for the full description)", "sourceUrl": null, "introducedIn": "PTX ISA 7.0", "requiredTargets": [ "sm_80" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.mbarrier.try_wait", "mnemonic": "mbarrier.try_wait", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "mbarrier.try_wait", "category": "Parallel Synchronization and Communication Instructions", "summary": "The test_wait and try_wait operations test for the completion of the current or the immediately preceding phase of an mbarrier object at the location specified by the operand addr.", "syntax": "// without parity\nmbarrier.try_wait{.phase_type::primary}{.sem.scope}{.ss}.b64 waitComplete, [addr], state {, timeHint};", "syntax_forms": [ { "syntax": "// without parity\nmbarrier.try_wait{.phase_type::primary}{.sem.scope}{.ss}.b64 waitComplete, [addr], state {, timeHint};", "description": "The test_wait and try_wait operations test for the completion of the current or the immediately\npreceding phase of an mbarrier object at the location specified by the operand addr.\nmbarrier. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_80" ], "introducedIn": "PTX ISA 7.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "without parity", "desc": "Operand" } ], "semantics": null, "examples": "// Example 1a, thread synchronization with test_wait:\n\n.reg .b64 %r1;\n.shared .b64 shMem;\n\nmbarrier.init.shared.b64 [shMem], N; // N threads participating in the mbarrier.\n// (truncated - see the official PTX ISA docs for the full example)", "description": "The test_wait and try_wait operations test for the completion of the current or the immediately\npreceding phase of an mbarrier object at the location specified by the operand addr.\nmbarrier.test_wait is a non-blocking instruction which tests for the completion of the phase.\nmbarrier.try_wait is a potentially blocking instruction which tests for the completion of the\nphase. If the phase is not complete, the executing thread may be suspended. Suspended thread resumes\nexecution when the specified phase completes OR before the phase completes following a\nsystem-dependent time limit. (see the official PTX ISA docs for the full description)", "sourceUrl": null, "introducedIn": "PTX ISA 7.0", "requiredTargets": [ "sm_80" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.membar", "mnemonic": "membar", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Memory Barrier / Fence", "category": "Parallel Synchronization and Communication Instructions", "summary": "Order this thread's prior memory accesses relative to later ones, visible to a given scope.", "syntax": "membar.level;", "syntax_forms": [ { "syntax": "membar.level;", "description": "level selects the visibility scope: CTA, whole GPU, or system (including other GPUs/host).", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [ "cta", "gl", "sys" ], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 1.4" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [ "cta", "gl", "sys" ], "operands": [], "semantics": "All memory operations issued by this thread before the fence become visible, in order, to other threads within the given scope before any operation issued after the fence.", "examples": "membar.gl;\nmembar.cta;\nmembar.sys;\nfence.sc.cta;\nfence.sc.cluster;\nfence.proxy.alias;\n// (truncated - see the official PTX ISA docs for the full example)", "description": "The membar instruction guarantees that prior memory accesses requested by this thread ( ld, st, atom and red instructions) are performed at the specified level, before later\nmemory operations requested by this thread following the membar instruction. The level qualifier specifies the set of threads that may observe the ordering effect of this operation.\nA memory read (e.g., by ld or atom ) has been performed when the value read has been\ntransmitted from memory and cannot be modified by another thread at the indicated level. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-membar", "introducedIn": "PTX ISA 1.4", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.min", "mnemonic": "min", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Minimum", "category": "Arithmetic", "summary": "Select the smaller of two operands.", "syntax": "min.type d, a, b;", "syntax_forms": [ { "syntax": "min.type d, a, b;", "description": "Integer or floating-point minimum.", "dataTypes": [ "s16", "s32", "s64", "u16", "u32", "u64", "f32", "f64" ], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [ "f32", "f64", "s16", "s32", "s64", "u16", "u32", "u64" ], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "First operand" }, { "name": "b", "desc": "Second operand" } ], "semantics": "d = (a < b) ? a : b, with type-specific NaN-handling rules for floating-point forms.", "examples": "min.s32 r0,a,b;\n@p min.u16 h,i,j;\n min.s16x2.relu u,v,w;\n min.u8x4 p, q, r;\n\n@p min.ftz.f32 z,z,x;\n min.f64 a,b,c;\n // fp32 min with .NaN\n min.NaN.f32 f0,f1,f2;\n // fp32 min with .xorsign.abs\n min.xorsign.abs.f32 Rd, Ra, Rb;\n\nmin.ftz.f16 h0,h1,h2;\nmin.f16x2 b0,b1,b2;\n// SIMD fp16 min with .NaN\nmin.NaN.f16x2 b0,b1,b2;\nmin.bf16 h0, h1, h2;\n// SIMD bf16 min with NaN\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Store the minimum of a and b in d.\nFor.f16x2 and.bf16x2 instruction types, input vectors are formed with half-word values\nfrom source operands. Half-word operands are then processed in parallel to store.f16x2 or.bf16x2 result in destination.\nFor.f16 instruction type, operands d and a have.f16 or.b16 type. For.f16x2 instruction type, operands d and a have.f16x2 or.b32 type. For.bf16 instruction type, operands d and a have.b16 type. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#half-precision-floating-point-instructions-min", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.mma", "mnemonic": "mma", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Matrix Multiply-Accumulate (Tensor Core)", "category": "Warp Level Matrix Multiply-Accumulate Instructions", "summary": "Cooperative, warp-wide matrix-multiply-accumulate executed on tensor-core hardware.", "syntax": "mma.sync.aligned.shape.row.col.dtype.atype.btype.ctype d, a, b, c;", "syntax_forms": [ { "syntax": "mma.sync.aligned.shape.row.col.dtype.atype.btype.ctype d, a, b, c;", "description": "Synchronizing warp-wide MMA for a fixed tile shape (e.g. m16n8k16); operand fragments are distributed across the warp's lanes per a hardware-defined layout.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_70" ], "introducedIn": "PTX ISA 6.4" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Accumulator fragment (destination)" }, { "name": "a", "desc": "Matrix A fragment" }, { "name": "b", "desc": "Matrix B fragment" }, { "name": "c", "desc": "Accumulator fragment (input)" } ], "semantics": "D = A * B + C for the fixed tile shape, computed cooperatively across all 32 lanes of the warp.", "examples": null, "description": "Perform a MxNxK matrix multiply and accumulate operation, D = A*B+C, where the A matrix is MxK, the B matrix is KxN, and the C and D matrices are MxN.\nQualifier.block_scale specifies that the matrices A and B are scaled with scale_A and scale_B matrices respectively before performing the matrix multiply and accumulate operation\nas specified in the section Block Scaling for mma.sync. The data type\ncorresponding to each of the element within scale_A and Scale_B matrices is specified\nby.stype. Qualifier.scale_vec_size specifies the number of columns of scale_A matrix\nand number of rows in the matrix scale_B.\nThe valid combinations of.kind,.stype and.scale_vec_size are described in Table 39. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#warp-level-matrix-instructions-mma", "introducedIn": "PTX ISA 6.4", "requiredTargets": [ "sm_70" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.mov", "mnemonic": "mov", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Move", "category": "Data Movement and Conversion Instructions", "summary": "Copy a value into a register, or materialize an address/immediate.", "syntax": "mov.type d, a;", "syntax_forms": [ { "syntax": "mov.type d, a;", "description": "Register-to-register move, or load of an immediate/address.", "dataTypes": [ "b16", "b32", "b64", "s16", "s32", "s64", "u16", "u32", "u64", "f32", "f64", "pred" ], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [ "b16", "b32", "b64", "f32", "f64", "pred", "s16", "s32", "s64", "u16", "u32", "u64" ], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source (register, immediate, or address expression)" } ], "semantics": "d = a, no type conversion is performed.", "examples": "mov.f32 d,a;\nmov.u16 u,v;\nmov.f32 k,0.1;\nmov.u32 ptr, A; // move address of A into ptr\nmov.u32 ptr, A[5]; // move address of A[5] into ptr\nmov.u32 ptr, A+20; // move address with offset into ptr\n// (truncated - see the official PTX ISA docs for the full example)\n\nmov.b32 %r1,{a,b}; // a,b have type .u16\nmov.b64 {lo,hi}, %x; // %x is a double; lo,hi are .u32\nmov.b32 %r1,{x,y,z,w}; // x,y,z,w have type .b8\nmov.b32 {r,g,b,a},%r1; // r,g,b,a have type .u8\nmov.b64 {%r1, _}, %x; // %x is.b64, %r1 is .b32\nmov.b128 {%b1, %b2}, %y; // %y is.b128, %b1 and % b2 are .b64\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Write register d with the value of a.\nOperand a may be a register, special register, variable with optional offset in an addressable\nmemory space, or function name.\nFor variables declared in.const,.global,.local, and.shared state spaces, mov places the non-generic address of the variable (i.e., the address of the variable in its state\nspace) into the destination register. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-mov", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.movmatrix", "mnemonic": "movmatrix", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "movmatrix", "category": "Warp Level Matrix Multiply-Accumulate Instructions", "summary": "Move a row-major matrix across all threads in a warp, reading elements from source a, and writing the transposed elements to destination d.", "syntax": "movmatrix.sync.aligned.shape.trans.type d, a;", "syntax_forms": [ { "syntax": "movmatrix.sync.aligned.shape.trans.type d, a;", "description": "Move a row-major matrix across all threads in a warp, reading elements from source a, and\nwriting the transposed elements to destination d.\nThe. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_75" ], "introducedIn": "PTX ISA 7.8" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" } ], "semantics": null, "examples": ".reg .b32 d, a;\nmovmatrix.sync.aligned.m8n8.trans.b16 d, a;", "description": "Move a row-major matrix across all threads in a warp, reading elements from source a, and\nwriting the transposed elements to destination d.\nThe.shape qualifier indicates the dimensions of the matrix being transposed. Each matrix\nelement holds 16-bit data as indicated by the.type qualifier.\nThe mandatory.sync qualifier indicates that movmatrix causes the executing thread to wait\nuntil all threads in the warp execute the same movmatrix instruction before resuming execution.\nThe mandatory.aligned qualifier indicates that all threads in the warp must execute the same movmatrix instruction. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#warp-level-matrix-instructions-movmatrix", "introducedIn": "PTX ISA 7.8", "requiredTargets": [ "sm_75" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.mul", "mnemonic": "mul", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Multiply", "category": "Arithmetic", "summary": "Multiply two operands, selecting the low, high, or widened part of an integer product.", "syntax": "mul.mode.stype d, a, b;", "syntax_forms": [ { "syntax": "mul.mode.stype d, a, b;", "description": "Integer multiply; mode selects which part of the full product is written to d.", "dataTypes": [ "s16", "s32", "s64", "u16", "u32", "u64" ], "stateSpaces": [], "scopes": [], "modifiers": [ "lo", "hi", "wide" ], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" }, { "syntax": "mul.f32 d, a, b;", "description": "Single-precision floating-point multiply.", "dataTypes": [ "f32" ], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" }, { "syntax": "mul.rn.f64 d, a, b;", "description": "Double-precision floating-point multiply with explicit round-to-nearest-even.", "dataTypes": [ "f64" ], "stateSpaces": [], "scopes": [], "modifiers": [ "rn" ], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [ "f32", "f64", "s16", "s32", "s64", "u16", "u32", "u64" ], "stateSpaces": [], "scopes": [], "modifiers": [ "hi", "lo", "rn", "wide" ], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "First source operand" }, { "name": "b", "desc": "Second source operand" } ], "semantics": "d = a * b, truncated to the selected result slice for integer forms.", "examples": "mul.wide.s16 fa,fxs,fys; // 16*16 bits yields 32 bits\nmul.lo.s16 fa,fxs,fys; // 16*16 bits, save only the low 16 bits\nmul.wide.s32 z,x,y; // 32*32 bits, creates 64 bit result\n\nmul.ftz.f32 circumf,radius,pi // a single-precision multiply\n\n// scalar f16 multiplications\nmul.f16 d0, a0, b0;\nmul.rn.f16 d1, a1, b1;\nmul.bf16 bd0, ba0, bb0;\nmul.rn.bf16 bd1, ba1, bb1;\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Performs multiplication and writes the resulting value into a destination register.\nFor.f16x2 and.bf16x2 instruction type, forms input vectors by half word values from source\noperands. Half-word operands are then multiplied in parallel to produce.f16x2 or.bf16x2 result in destination.\nFor.f16 instruction type, operands d, a and b have.f16 or.b16 type. For.f16x2 instruction type, operands d, a and b have.b32 type. For.bf16 instruction type, operands d, a, b have.b16 type. For.bf16x2 instruction type,\noperands d, a, b have.b32 type.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#half-precision-floating-point-instructions-mul", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.mul24", "mnemonic": "mul24", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "mul24", "category": "Integer Arithmetic Instructions", "summary": "Compute the product of two 24-bit integer values held in 32-bit source registers, and return either\nthe high or low 32-bits of the 48-bit result.", "syntax": "mul24.mode.type d, a, b;", "syntax_forms": [ { "syntax": "mul24.mode.type d, a, b;", "description": "Compute the product of two 24-bit integer values held in 32-bit source registers, and return either\nthe high or low 32-bits of the 48-bit result.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" }, { "name": "b", "desc": "Source operand" } ], "semantics": "t = a * b;\nd = t<47..16>; // for .hi variant\nd = t<31..0>; // for .lo variant", "examples": "mul24.lo.s32 d,a,b; // low 32-bits of 24x24-bit signed multiply.", "description": "Compute the product of two 24-bit integer values held in 32-bit source registers, and return either\nthe high or low 32-bits of the 48-bit result.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#integer-arithmetic-instructions-mul24", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.multimem.cp.async.bulk", "mnemonic": "multimem.cp.async.bulk", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "multimem.cp.async.bulk", "category": "Data Movement and Conversion Instructions", "summary": "Instruction multimem.cp.async.bulk initiates an asynchronous bulk-copy operation from source address range [srcMem, srcMem + size) to memory locations residing on each GPU’s memory referred to by the destination multimem address range [dstMem, dstMem + size).", "syntax": "multimem.cp.async.bulk{.sem}.dst.src.completion_mechanism{.cp_mask}", "syntax_forms": [ { "syntax": "multimem.cp.async.bulk{.sem}.dst.src.completion_mechanism{.cp_mask}", "description": "Instruction multimem.cp.async.bulk initiates an asynchronous bulk-copy operation from source address range [srcMem, srcMem + size) to memory locations residing on each GPU’s memory referred to by the… (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_90" ], "introducedIn": "PTX ISA 9.1" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "multimem.cp.async.bulk.global.shared::cta.bulk_group [dstMem], [srcMem], size;\n\nmultimem.cp.async.bulk.global.shared::cta.bulk_group [dstMem], [srcMem], 512;\n\nmultimem.cp.async.bulk.global.shared::cta.bulk_group.cp_mask [dstMem], [srcMem], size, byteMask;\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Instruction multimem.cp.async.bulk initiates an asynchronous bulk-copy operation from source\naddress range [srcMem, srcMem + size) to memory locations residing on each GPU’s memory referred\nto by the destination multimem address range [dstMem, dstMem + size). The direction of\nbulk-copy is from the state space specified by the.src modifier to the state space specified\nby the.dst modifiers.\nThe 32-bit operand size specifies the amount of memory to be copied, in terms of number of\nbytes. Operand size must be a multiple of 16. The memory range [dstMem, dstMem + size) must not overflow the destination multimem memory space. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-multimem-cp-async-bulk", "introducedIn": "PTX ISA 9.1", "requiredTargets": [ "sm_90" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.multimem.cp.reduce.async.bulk", "mnemonic": "multimem.cp.reduce.async.bulk", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "multimem.cp.reduce.async.bulk", "category": "Data Movement and Conversion Instructions", "summary": "Instruction multimem.cp.reduce.async.bulk initiates an element-wise asynchronous reduction operation with elements from source memory address range [srcMem, srcMem + size) to memory locations residing on each GPU’s memory referred to by the multimem destination address range [dstMem, dstMem + size).", "syntax": "multimem.cp.reduce.async.bulk{.sem.scope}.dst.src.completion_mechanism.redOp.type [dstMem], [srcMem], size;", "syntax_forms": [ { "syntax": "multimem.cp.reduce.async.bulk{.sem.scope}.dst.src.completion_mechanism.redOp.type [dstMem], [srcMem], size;", "description": "Instruction multimem.cp.reduce.async.bulk initiates an element-wise asynchronous reduction operation with elements from source memory address range [srcMem, srcMem + size) to memory locations residing… (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_90" ], "introducedIn": "PTX ISA 9.1" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "multimem.cp.reduce.async.bulk.global.shared::cta.bulk_group.add.u32 [dstMem], [srcMem], size;\n\nmultimem.cp.reduce.async.bulk.global.shared::cta.bulk_group.xor.b64 [dstMem], [srcMem], size;\n\nmultimem.cp.reduce.async.bulk.global.shared::cta.bulk_group.inc.u32 [dstMem], [srcMem], size;\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Instruction multimem.cp.reduce.async.bulk initiates an element-wise asynchronous reduction\noperation with elements from source memory address range [srcMem, srcMem + size) to memory\nlocations residing on each GPU’s memory referred to by the multimem destination address range [dstMem, dstMem + size).\nEach data element in the destination array is reduced inline with the corresponding data element in\nthe source array with the reduction operation specified by the modifier.redOp. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-multimem-cp-reduce-async-bulk", "introducedIn": "PTX ISA 9.1", "requiredTargets": [ "sm_90" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.multimem.ld_reduce", "mnemonic": "multimem.ld_reduce", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "multimem.ld_reduce", "category": "Data Movement and Conversion Instructions", "summary": "The multimem.* operations operate on multimem addresses and accesses all of the multiple memory\nlocations which the multimem address points to.\nMultimem addresses can be accessed only by multimem.* operations. Accessing a multimem address\nwith ld, st or any other memory operations results in undefined behavior.\nRefer to CUDA programming guide for creation and management of the multimem addresses.", "syntax": "// Integer type:\nmultimem.ld_reduce{.ldsem}{.scope}{.ss}.op.type d, [a];", "syntax_forms": [ { "syntax": "// Integer type:\nmultimem.ld_reduce{.ldsem}{.scope}{.ss}.op.type d, [a];", "description": "Instruction multimem.ld_reduce performs the following operations: load operation on the multimem address a, which involves loading of data from all of the multiple memory locations pointed to by the m… (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_90" ], "introducedIn": "PTX ISA 8.1" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "Integer type:", "desc": "Operand" } ], "semantics": null, "examples": "multimem.ld_reduce.and.b32 val1_b32, [addr1];\nmultimem.ld_reduce.acquire.gpu.global.add.u32 val2_u32, [addr2];\n\nmultimem.st.relaxed.gpu.b32 [addr3], val3_b32;\nmultimem.st.release.cta.global.u32 [addr4], val4_u32;\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Instruction multimem.ld_reduce performs the following operations:\nload operation on the multimem address a, which involves loading of data from all of the\nmultiple memory locations pointed to by the multimem address a, reduction operation specified by.op on the multiple data loaded from the multimem address a.\nThe result of the reduction operation in returned in register d.\nInstruction multimem.st performs a store operation of the input operand b to all the memory\nlocations pointed to by the multimem address a.\nInstruction multimem.red performs a reduction operation on all the memory locations pointed to\nby the multimem address a, with operand b.\nInstruction multimem. (see the official PTX ISA docs for the full description)", "sourceUrl": null, "introducedIn": "PTX ISA 8.1", "requiredTargets": [ "sm_90" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.multimem.red", "mnemonic": "multimem.red", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "multimem.red", "category": "Data Movement and Conversion Instructions", "summary": "The multimem.* operations operate on multimem addresses and accesses all of the multiple memory\nlocations which the multimem address points to.\nMultimem addresses can be accessed only by multimem.* operations. Accessing a multimem address\nwith ld, st or any other memory operations results in undefined behavior.\nRefer to CUDA programming guide for creation and management of the multimem addresses.", "syntax": "// Integer type:\nmultimem.red{.redsem}{.scope}{.ss}.op.type [a], b;", "syntax_forms": [ { "syntax": "// Integer type:\nmultimem.red{.redsem}{.scope}{.ss}.op.type [a], b;", "description": "Instruction multimem.ld_reduce performs the following operations: load operation on the multimem address a, which involves loading of data from all of the multiple memory locations pointed to by the m… (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_90" ], "introducedIn": "PTX ISA 8.1" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "Integer type:", "desc": "Operand" } ], "semantics": null, "examples": "multimem.ld_reduce.and.b32 val1_b32, [addr1];\nmultimem.ld_reduce.acquire.gpu.global.add.u32 val2_u32, [addr2];\n\nmultimem.st.relaxed.gpu.b32 [addr3], val3_b32;\nmultimem.st.release.cta.global.u32 [addr4], val4_u32;\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Instruction multimem.ld_reduce performs the following operations:\nload operation on the multimem address a, which involves loading of data from all of the\nmultiple memory locations pointed to by the multimem address a, reduction operation specified by.op on the multiple data loaded from the multimem address a.\nThe result of the reduction operation in returned in register d.\nInstruction multimem.st performs a store operation of the input operand b to all the memory\nlocations pointed to by the multimem address a.\nInstruction multimem.red performs a reduction operation on all the memory locations pointed to\nby the multimem address a, with operand b.\nInstruction multimem. (see the official PTX ISA docs for the full description)", "sourceUrl": null, "introducedIn": "PTX ISA 8.1", "requiredTargets": [ "sm_90" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.multimem.red.async", "mnemonic": "multimem.red.async", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "multimem.red.async", "category": "Parallel Synchronization and Communication Instructions", "summary": "multimem.red.async is a non-blocking instruction which initiates an asynchronous reduction operation specified by.op, with operand b and the value at memory locations residing on each GPU’s memory referred to by the destination multimem address operand a.", "syntax": "multimem.red.async.sem.scope{.ss}.op.type [a], b;", "syntax_forms": [ { "syntax": "multimem.red.async.sem.scope{.ss}.op.type [a], b;", "description": "multimem.red.async is a non-blocking instruction which initiates an asynchronous\nreduction operation specified by. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_90" ], "introducedIn": "PTX ISA 9.3" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "// Asynchronous add reduction, GPU scope, explicit .global, 32-bit unsigned.\nmultimem.red.async.release.gpu.global.add.u32 [mm_addr], src_u32;\n\n// System scope, generic addressing.\nmultimem.red.async.release.sys.add.s32 [mm_addr], src_s32;\n// (truncated - see the official PTX ISA docs for the full example)", "description": "multimem.red.async is a non-blocking instruction which initiates an asynchronous\nreduction operation specified by.op, with operand b and the value at memory\nlocations residing on each GPU’s memory referred to by the destination multimem address\noperand a.\nAddress operand a must be a multimem address. Otherwise, the behavior is undefined.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-multimem-red-async", "introducedIn": "PTX ISA 9.3", "requiredTargets": [ "sm_90" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.multimem.st", "mnemonic": "multimem.st", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "multimem.st", "category": "Data Movement and Conversion Instructions", "summary": "The multimem.* operations operate on multimem addresses and accesses all of the multiple memory\nlocations which the multimem address points to.\nMultimem addresses can be accessed only by multimem.* operations. Accessing a multimem address\nwith ld, st or any other memory operations results in undefined behavior.\nRefer to CUDA programming guide for creation and management of the multimem addresses.", "syntax": "// Integer type:\nmultimem.st{.stsem}{.scope}{.ss}.type [a], b;", "syntax_forms": [ { "syntax": "// Integer type:\nmultimem.st{.stsem}{.scope}{.ss}.type [a], b;", "description": "Instruction multimem.ld_reduce performs the following operations: load operation on the multimem address a, which involves loading of data from all of the multiple memory locations pointed to by the m… (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_90" ], "introducedIn": "PTX ISA 8.1" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "Integer type:", "desc": "Operand" } ], "semantics": null, "examples": "multimem.ld_reduce.and.b32 val1_b32, [addr1];\nmultimem.ld_reduce.acquire.gpu.global.add.u32 val2_u32, [addr2];\n\nmultimem.st.relaxed.gpu.b32 [addr3], val3_b32;\nmultimem.st.release.cta.global.u32 [addr4], val4_u32;\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Instruction multimem.ld_reduce performs the following operations:\nload operation on the multimem address a, which involves loading of data from all of the\nmultiple memory locations pointed to by the multimem address a, reduction operation specified by.op on the multiple data loaded from the multimem address a.\nThe result of the reduction operation in returned in register d.\nInstruction multimem.st performs a store operation of the input operand b to all the memory\nlocations pointed to by the multimem address a.\nInstruction multimem.red performs a reduction operation on all the memory locations pointed to\nby the multimem address a, with operand b.\nInstruction multimem. (see the official PTX ISA docs for the full description)", "sourceUrl": null, "introducedIn": "PTX ISA 8.1", "requiredTargets": [ "sm_90" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.multimem.st.async", "mnemonic": "multimem.st.async", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "multimem.st.async", "category": "Data Movement and Conversion Instructions", "summary": "multimem.st.async is a non-blocking instruction which initiates an asynchronous store operation that stores the value specified by source operand b to the memory locations residing on each GPU’s memory referred to by the destination multimem address operand a.", "syntax": "multimem.st.async.sem.scope{.ss}.type [a], b;", "syntax_forms": [ { "syntax": "multimem.st.async.sem.scope{.ss}.type [a], b;", "description": "multimem.st.async is a non-blocking instruction which initiates an asynchronous store operation that stores the value specified by source operand b to the memory locations residing on each GPU’s memor… (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_90" ], "introducedIn": "PTX ISA 9.3" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "// Release store to multimem address, GPU scope, explicit .global state space.\nmultimem.st.async.release.gpu.global.u32 [mm_addr], src_u32;\n\n// Release store, system scope, generic addressing for multimem operand.\nmultimem.st.async.release.sys.f64 [mm_addr], src_f64;", "description": "multimem.st.async is a non-blocking instruction which initiates an asynchronous store\noperation that stores the value specified by source operand b to the memory locations\nresiding on each GPU’s memory referred to by the destination multimem address operand a.\nAddress operand a must be a multimem address. Otherwise, the behavior is undefined.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-multimem-st-async", "introducedIn": "PTX ISA 9.3", "requiredTargets": [ "sm_90" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.nanosleep", "mnemonic": "nanosleep", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "nanosleep", "category": "Miscellaneous Instructions", "summary": "Suspends the thread for a sleep duration approximately close to the delay t, specified in nanoseconds.", "syntax": "nanosleep.u32 t;", "syntax_forms": [ { "syntax": "nanosleep.u32 t;", "description": "Suspends the thread for a sleep duration approximately close to the delay t, specified in\nnanoseconds. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_70" ], "introducedIn": "PTX ISA 6.3" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "t", "desc": "Operand" } ], "semantics": null, "examples": ".reg .b32 r;\n.reg .pred p;\n\nnanosleep.u32 r;\nnanosleep.u32 42;\n@p nanosleep.u32 r;", "description": "Suspends the thread for a sleep duration approximately close to the delay t, specified in\nnanoseconds. t may be a register or an immediate value.\nThe sleep duration is approximated, but guaranteed to be in the interval [0, 2*t]. The maximum\nsleep duration is 1 millisecond. The implementation may reduce the sleep duration for individual\nthreads within a warp such that all sleeping threads in the warp wake up together.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#miscellaneous-instructions-nanosleep", "introducedIn": "PTX ISA 6.3", "requiredTargets": [ "sm_70" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.neg", "mnemonic": "neg", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Negate", "category": "Arithmetic", "summary": "Negate a signed or floating-point operand.", "syntax": "neg.type d, a;", "syntax_forms": [ { "syntax": "neg.type d, a;", "description": "Arithmetic negation.", "dataTypes": [ "s16", "s32", "s64", "f32", "f64" ], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [ "f32", "f64", "s16", "s32", "s64" ], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" } ], "semantics": "d = -a.", "examples": "neg.s32 r0,a;\nneg.s8x4 p, q, r;\n\nneg.ftz.f32 x,f0;\n\nneg.ftz.f16 x,f0;\nneg.bf16 x,b0;\nneg.bf16x2 x1,b1;", "description": "Negate the sign of a and store the result in d.\nFor.f16x2 and.bf16x2 instruction type, forms input vector by extracting half word values\nfrom the source operand. Half-word operands are then negated in parallel to produce.f16x2 or.bf16x2 result in destination.\nFor.f16 instruction type, operands d and a have.f16 or.b16 type. For.f16x2 instruction type, operands d and a have.b32 type. For.bf16 instruction\ntype, operands d and a have.b16 type. For.bf16x2 instruction type, operands d and a have.b32 type.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#half-precision-floating-point-instructions-neg", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.not", "mnemonic": "not", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Bitwise NOT", "category": "Logic and Shift Instructions", "summary": "Bitwise complement of an operand.", "syntax": "not.type d, a;", "syntax_forms": [ { "syntax": "not.type d, a;", "description": "Bitwise complement, including a predicate form.", "dataTypes": [ "b16", "b32", "b64", "pred" ], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [ "b16", "b32", "b64", "pred" ], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" } ], "semantics": "d = ~a (bitwise).", "examples": "not.b32 mask,mask;\nnot.pred p,q;", "description": "Invert the bits in a.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#logic-and-shift-instructions-not", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.or", "mnemonic": "or", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Bitwise OR", "category": "Logic and Shift Instructions", "summary": "Bitwise OR of two operands.", "syntax": "or.type d, a, b;", "syntax_forms": [ { "syntax": "or.type d, a, b;", "description": "Bitwise OR, including a predicate form.", "dataTypes": [ "b16", "b32", "b64", "pred" ], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [ "b16", "b32", "b64", "pred" ], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "First operand" }, { "name": "b", "desc": "Second operand" } ], "semantics": "d = a | b (bitwise).", "examples": "or.b32 mask mask,0x00010001\nor.pred p,q,r;", "description": "Compute the bit-wise or operation for the bits in a and b.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#logic-and-shift-instructions-or", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.pmevent", "mnemonic": "pmevent", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "pmevent", "category": "Miscellaneous Instructions", "summary": "Triggers one or more of a fixed number of performance monitor events, with event index or mask specified by immediate operand a.", "syntax": "pmevent a; // trigger a single performance monitor event", "syntax_forms": [ { "syntax": "pmevent a; // trigger a single performance monitor event", "description": "Triggers one or more of a fixed number of performance monitor events, with event index or mask\nspecified by immediate operand a.\npmevent (without modifier. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 1.4" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "pmevent 1;\n@p pmevent 7;\n@q pmevent.mask 0xff;", "description": "Triggers one or more of a fixed number of performance monitor events, with event index or mask\nspecified by immediate operand a.\npmevent (without modifier.mask ) triggers a single performance monitor event indexed by\nimmediate operand a, in the range 0..15.\npmevent.mask triggers one or more of the performance monitor events. Each bit in the 16-bit\nimmediate operand a controls an event.\nProgrammatic performance moniter events may be combined with other hardware events using Boolean\nfunctions to increment one of the four performance counters. The relationship between events and\ncounters is programmed via API calls from the host.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#miscellaneous-instructions-pmevent", "introducedIn": "PTX ISA 1.4", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.popc", "mnemonic": "popc", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Population Count", "category": "Integer Arithmetic Instructions", "summary": "Count the number of set bits in an integer operand.", "syntax": "popc.type d, a;", "syntax_forms": [ { "syntax": "popc.type d, a;", "description": "Population count.", "dataTypes": [ "b32", "b64" ], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 2.0" } ], "dataTypes": [ "b32", "b64" ], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register (u32)" }, { "name": "a", "desc": "Source operand" } ], "semantics": "d = number of 1-bits in a.", "examples": "popc.b32 d, a;\npopc.b64 cnt, X; // cnt is .u32", "description": "Count the number of one bits in a and place the resulting population count in 32-bit\ndestination register d. Operand a has the instruction type and destination d has type.u32.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#integer-arithmetic-instructions-popc", "introducedIn": "PTX ISA 2.0", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.prefetch", "mnemonic": "prefetch", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "prefetch", "category": "Data Movement and Conversion Instructions", "summary": "The prefetch instruction brings the cache line containing the specified address in global or\nlocal memory state space into the specified cache level.", "syntax": "prefetch{.space}.level [a]; // prefetch to data cache", "syntax_forms": [ { "syntax": "prefetch{.space}.level [a]; // prefetch to data cache", "description": "The prefetch instruction brings the cache line containing the specified address in global or\nlocal memory state space into the specified cache level.\nIf the. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 2.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "prefetch.global.L1 [ptr];\nprefetch.global.L2::evict_last [ptr];\nprefetchu.L1 [addr];\nprefetch.const.tensormap [ptr];", "description": "The prefetch instruction brings the cache line containing the specified address in global or\nlocal memory state space into the specified cache level.\nIf the.tensormap qualifier is specified then the prefetch instruction brings the cache line\ncontaining the specified address in the.const or.param memory state space for subsequent\nuse by the cp.async.bulk.tensor instruction.\nIf no state space is given, the prefetch uses Generic Addressing.\nOptionally, the eviction priority to be applied on the prefetched cache line can be specified by the\nmodifier.level::eviction_priority. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-prefetch-prefetchu", "introducedIn": "PTX ISA 2.0", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.prefetchu", "mnemonic": "prefetchu", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "prefetchu", "category": "Data Movement and Conversion Instructions", "summary": "The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. A prefetch to a shared memory location performs no operation.", "syntax": "prefetchu.L1 [a]; // prefetch to uniform cache", "syntax_forms": [ { "syntax": "prefetchu.L1 [a]; // prefetch to uniform cache", "description": "The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. A prefetch to a shared memory location performs no operation.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 2.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "prefetch.global.L1 [ptr];\nprefetch.global.L2::evict_last [ptr];\nprefetchu.L1 [addr];\nprefetch.const.tensormap [ptr];", "description": "The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. A prefetch to a shared memory location performs no operation.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-prefetch-prefetchu", "introducedIn": "PTX ISA 2.0", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.prmt", "mnemonic": "prmt", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "prmt", "category": "Data Movement and Conversion Instructions", "summary": "Pick four arbitrary bytes from two 32-bit registers, and reassemble them into a 32-bit destination register.", "syntax": "prmt.b32{.mode} d, a, b, c;", "syntax_forms": [ { "syntax": "prmt.b32{.mode} d, a, b, c;", "description": "Pick four arbitrary bytes from two 32-bit registers, and reassemble them into a 32-bit destination\nregister. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 2.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" }, { "name": "b", "desc": "Source operand" }, { "name": "c", "desc": "Source operand" } ], "semantics": "tmp64 = (b<<32) | a; // create 8 byte source\n\nif ( ! mode ) {\n ctl[0] = (c >> 0) & 0xf;\n ctl[1] = (c >> 4) & 0xf;\n ctl[2] = (c >> 8) & 0xf;\n ctl[3] = (c >> 12) & 0xf;\n} else {\n ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3;\n}\n\ntmp[07:00] = ReadByte( mode, ctl[0], tmp64 );\ntmp[15:08] = ReadByte( mode, ctl[1], tmp64 );\ntmp[23:16] = ReadByte( mode, ctl[2], tmp64 );\ntmp[31:24] = ReadByte( mode, ctl[3], tmp64 );", "examples": "prmt.b32 r1, r2, r3, r4;\nprmt.b32.f4e r1, r2, r3, r4;", "description": "Pick four arbitrary bytes from two 32-bit registers, and reassemble them into a 32-bit destination\nregister.\nIn the generic form (no mode specified), the permute control consists of four 4-bit selection\nvalues. The bytes in the two source registers are numbered from 0 to 7: {b, a} = {{b7, b6, b5, b4}, {b3, b2, b1, b0}}. For each byte in the target register, a 4-bit selection value is defined.\nThe 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the\ntarget position. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-prmt", "introducedIn": "PTX ISA 2.0", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.rcp", "mnemonic": "rcp", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "rcp", "category": "Floating-Point Instructions", "summary": "Compute 1/a, store result in d.", "syntax": "rcp.approx{.ftz}.f32 d, a; // fast, approximate reciprocal", "syntax_forms": [ { "syntax": "rcp.approx{.ftz}.f32 d, a; // fast, approximate reciprocal", "description": "Compute 1/a, store result in d.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": "d = 1 / a;", "examples": "rcp.approx.ftz.f32 ri,r;\nrcp.rn.ftz.f32 xi,x;\nrcp.rn.f64 xi,x;", "description": "Compute 1/a, store result in d.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#floating-point-instructions-rcp", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.rcp.approx.ftz.f64", "mnemonic": "rcp.approx.ftz.f64", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "rcp.approx.ftz.f64", "category": "Floating-Point Instructions", "summary": "Compute a fast, gross approximation to the reciprocal as follows: extract the most-significant 32 bits of.f64 operand a in 1.11.20 IEEE floating-point format (i.e., ignore the least-significant 32…", "syntax": "rcp.approx.ftz.f64 d, a;", "syntax_forms": [ { "syntax": "rcp.approx.ftz.f64 d, a;", "description": "Compute a fast, gross approximation to the reciprocal as follows:\nextract the most-significant 32 bits of.f64 operand a in 1.11.20 IEEE floating-point\nformat (i.e. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 2.1" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" } ], "semantics": "tmp = a[63:32]; // upper word of a, 1.11.20 format\nd[63:32] = 1.0 / tmp;\nd[31:0] = 0x00000000;", "examples": "rcp.approx.ftz.f64 xi,x;", "description": "Compute a fast, gross approximation to the reciprocal as follows:\nextract the most-significant 32 bits of.f64 operand a in 1.11.20 IEEE floating-point\nformat (i.e., ignore the least-significant 32 bits of a ), compute an approximate.f64 reciprocal of this value using the most-significant 20 bits of\nthe mantissa of operand a, place the resulting 32-bits in 1.11.20 IEEE floating-point format in the most-significant 32-bits\nof destination d,and zero the least significant 32 mantissa bits of.f64 destination d.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#floating-point-instructions-rcp-approx-ftz-f64", "introducedIn": "PTX ISA 2.1", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.red", "mnemonic": "red", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Reduction", "category": "Parallel Synchronization and Communication Instructions", "summary": "Atomically read-modify-write a memory location without returning the prior value.", "syntax": "red.space.op.type [a], b;", "syntax_forms": [ { "syntax": "red.space.op.type [a], b;", "description": "Same read-modify-write as atom, but discards the prior value - cheaper when the old value isn't needed.", "dataTypes": [ "b32", "b64", "s32", "u32", "u64", "f32", "f64" ], "stateSpaces": [ "global", "shared" ], "scopes": [], "modifiers": [ "add", "min", "max", "and", "or", "xor", "inc", "dec" ], "requiredTargets": [ "sm_11" ], "introducedIn": "PTX ISA 1.2" } ], "dataTypes": [ "b32", "b64", "f32", "f64", "s32", "u32", "u64" ], "stateSpaces": [ "global", "shared" ], "scopes": [], "modifiers": [ "add", "and", "dec", "inc", "max", "min", "or", "xor" ], "operands": [ { "name": "a", "desc": "Memory address" }, { "name": "b", "desc": "Operand value" } ], "semantics": "*a = op(*a, b).", "examples": "red.global.add.s32 [a],1;\nred.shared::cluster.max.u32 [x+4],0;\n@p red.global.and.b32 [p],my_val;\nred.global.sys.add.u32 [a], 1;\nred.global.acquire.sys.add.u32 [gbl], 1;\nred.add.noftz.f16x2 [a], b;\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Performs a reduction operation with operand b and the value in location a, and stores the\nresult of the specified operation at location a, overwriting the original value. Operand a specifies a location in the specified state space. If no state space is given, perform the memory\naccesses using Generic Addressing. red with scalar type may\nbe used only with.global and.shared spaces and with generic addressing, where the address\npoints to.global or.shared space. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-red", "introducedIn": "PTX ISA 1.2", "requiredTargets": [ "sm_11" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.red.async", "mnemonic": "red.async", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "red.async", "category": "Parallel Synchronization and Communication Instructions", "summary": "red.async is a non-blocking instruction which initiates an asynchronous reduction operation specified by.op, with the operand b and the value at destination shared memory location specified by operand a.", "syntax": "// Increment and Decrement reductions\nred.async.sem.scope{.ss}.completion_mechanism.op.type [a], b, [mbar];", "syntax_forms": [ { "syntax": "// Increment and Decrement reductions\nred.async.sem.scope{.ss}.completion_mechanism.op.type [a], b, [mbar];", "description": "red.async is a non-blocking instruction which initiates an asynchronous reduction operation\nspecified by. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_90" ], "introducedIn": "PTX ISA 8.1" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.min.u32 [addr], b, [mbar_addr];\n\nred.async.release.sys.global.add.u32 [addr], b;", "description": "red.async is a non-blocking instruction which initiates an asynchronous reduction operation\nspecified by.op, with the operand b and the value at destination shared memory location\nspecified by operand a.\nred.async is performed in the generic proxy.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-red-async", "introducedIn": "PTX ISA 8.1", "requiredTargets": [ "sm_90" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.redux.sync", "mnemonic": "redux.sync", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "redux.sync", "category": "Parallel Synchronization and Communication Instructions", "summary": "redux.sync will cause the executing thread to wait until all non-exited threads corresponding to membermask have executed redux.sync with the same qualifiers and same membermask value before resuming execution.", "syntax": "redux.sync.op.type dst, src, membermask;", "syntax_forms": [ { "syntax": "redux.sync.op.type dst, src, membermask;", "description": "redux.sync will cause the executing thread to wait until all non-exited threads corresponding to membermask have executed redux. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_80" ], "introducedIn": "PTX ISA 7.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "dst", "desc": "Operand" }, { "name": "src", "desc": "Operand" }, { "name": "membermask", "desc": "Operand" } ], "semantics": null, "examples": ".reg .b32 dst, src, init, mask;\nredux.sync.add.s32 dst, src, 0xff;\nredux.sync.xor.b32 dst, src, mask;\n\nredux.sync.min.abs.NaN.f32 dst, src, mask;", "description": "redux.sync will cause the executing thread to wait until all non-exited threads corresponding to membermask have executed redux.sync with the same qualifiers and same membermask value\nbefore resuming execution.\nOperand membermask specifies a 32-bit integer which is a mask indicating threads participating\nin this instruction where the bit position corresponds to thread’s laneid.\nredux.sync performs a reduction operation.op of the 32 bit source register src across\nall non-exited threads in the membermask. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-redux-sync", "introducedIn": "PTX ISA 7.0", "requiredTargets": [ "sm_80" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.rem", "mnemonic": "rem", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Remainder", "category": "Arithmetic", "summary": "Compute the integer remainder of division.", "syntax": "rem.stype d, a, b;", "syntax_forms": [ { "syntax": "rem.stype d, a, b;", "description": "Integer remainder.", "dataTypes": [ "s16", "s32", "s64", "u16", "u32", "u64" ], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [ "s16", "s32", "s64", "u16", "u32", "u64" ], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Dividend" }, { "name": "b", "desc": "Divisor" } ], "semantics": "d = a - b * trunc(a / b).", "examples": "rem.s32 x,x,8; // x = x%8;", "description": "Divides a by b, store the remainder in d.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#integer-arithmetic-instructions-rem", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.ret", "mnemonic": "ret", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "ret", "category": "Control Flow Instructions", "summary": "Return execution to caller’s environment.", "syntax": "ret{.uni};", "syntax_forms": [ { "syntax": "ret{.uni};", "description": "Return execution to caller’s environment. A divergent return suspends threads until all threads are\nready to return to the caller. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "ret;\n@p ret;", "description": "Return execution to caller’s environment. A divergent return suspends threads until all threads are\nready to return to the caller. This allows multiple divergent ret instructions.\nA ret is assumed to be divergent unless the.uni suffix is present, indicating that the\nreturn is guaranteed to be non-divergent.\nAny values returned from a function should be moved into the return parameter variables prior to\nexecuting the ret instruction.\nA return instruction executed in a top-level entry routine will terminate thread execution.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#control-flow-instructions-ret", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.rsqrt", "mnemonic": "rsqrt", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Reciprocal Square Root (Approximate)", "category": "Arithmetic", "summary": "Fast hardware approximation of 1/sqrt(x).", "syntax": "rsqrt.approx.f32 d, a;", "syntax_forms": [ { "syntax": "rsqrt.approx.f32 d, a;", "description": "Reduced-precision reciprocal square root.", "dataTypes": [ "f32" ], "stateSpaces": [], "scopes": [], "modifiers": [ "approx" ], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [ "f32" ], "stateSpaces": [], "scopes": [], "modifiers": [ "approx" ], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" } ], "semantics": "d ≈ 1 / sqrt(a), with a hardware-specific ULP error bound rather than a fully IEEE-rounded result.", "examples": "rsqrt.approx.ftz.f32 isr, x;\nrsqrt.approx.f64 ISR, X;", "description": "Compute 1/sqrt(a) and store the result in d.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#floating-point-instructions-rsqrt", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.rsqrt.approx.ftz.f64", "mnemonic": "rsqrt.approx.ftz.f64", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "rsqrt.approx.ftz.f64", "category": "Floating-Point Instructions", "summary": "Compute a double-precision (.f64 ) approximation of the square root reciprocal of a value. The\nleast significant 32 bits of the double-precision (.f64", "syntax": "rsqrt.approx.ftz.f64 d, a;", "syntax_forms": [ { "syntax": "rsqrt.approx.ftz.f64 d, a;", "description": "Compute a double-precision (.f64 ) approximation of the square root reciprocal of a value. The\nleast significant 32 bits of the double-precision (.f64 ) destination d are all zeros.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 4.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" } ], "semantics": "tmp = a[63:32]; // upper word of a, 1.11.20 format\nd[63:32] = 1.0 / sqrt(tmp);\nd[31:0] = 0x00000000;", "examples": "rsqrt.approx.ftz.f64 xi,x;", "description": "Compute a double-precision (.f64 ) approximation of the square root reciprocal of a value. The\nleast significant 32 bits of the double-precision (.f64 ) destination d are all zeros.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#floating-point-instructions-rsqrt-approx-ftz-f64", "introducedIn": "PTX ISA 4.0", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.sad", "mnemonic": "sad", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "sad", "category": "Integer Arithmetic Instructions", "summary": "Adds the absolute value of a-b to c and writes the resulting value into d.", "syntax": "sad.type d, a, b, c;", "syntax_forms": [ { "syntax": "sad.type d, a, b, c;", "description": "Adds the absolute value of a-b to c and writes the resulting value into d.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" }, { "name": "b", "desc": "Source operand" }, { "name": "c", "desc": "Source operand" } ], "semantics": "d = c + ((a> (32-n));\n case shf.r: // extract 32 lsbs\n u32 d = (b << (32-n)) | (a >> n);\n}", "examples": null, "description": "Shift the 64-bit value formed by concatenating operands a and b left or right by the amount\nspecified by the unsigned 32-bit value in c. Operand b holds bits 63:32 and operand a\nholds bits 31:0 of the 64-bit source value. The source is shifted left or right by the clamped\nor wrapped value in c. For shf.l, the most-significant 32-bits of the result are written\ninto d; for shf.r, the least-significant 32-bits of the result are written into d.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#logic-and-shift-instructions-shf", "introducedIn": "PTX ISA 3.1", "requiredTargets": [ "sm_32" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.shfl", "mnemonic": "shfl", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Shuffle", "category": "Data Movement and Conversion Instructions", "summary": "Exchange a value directly between lanes of the same warp.", "syntax": "shfl.mode.b32 d[|p], a, b, c;", "syntax_forms": [ { "syntax": "shfl.mode.b32 d[|p], a, b, c;", "description": "Legacy (unsynchronized) warp shuffle; deprecated since PTX ISA 6.0 in favor of shfl.sync.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [ "up", "down", "bfly", "idx" ], "requiredTargets": [ "sm_30" ], "introducedIn": "PTX ISA 6.0" }, { "syntax": "shfl.sync.mode.b32 d[|p], a, b, c, membermask;", "description": "Warp shuffle that also synchronizes the specified member lanes before exchanging data.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [ "up", "down", "bfly", "idx" ], "requiredTargets": [ "sm_30" ], "introducedIn": "PTX ISA 6.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [ "bfly", "down", "idx", "up" ], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Value to shuffle" }, { "name": "b", "desc": "Source-lane selector" }, { "name": "c", "desc": "Clamp/width control" }, { "name": "membermask", "desc": "Mask of participating lanes (sync form only)" } ], "semantics": "d = value of operand a as seen by another lane in the warp, selected by mode/b; optional predicate p reports whether the source lane was valid.", "examples": "shfl.sync.up.b32 Ry|p, Rx, 0x1, 0x0, 0xffffffff;", "description": "Exchange register data between threads of a warp.\nshfl.sync will cause executing thread to wait until all non-exited threads corresponding to membermask have executed shfl.sync with the same qualifiers and same membermask value\nbefore resuming execution.\nOperand membermask specifies a 32-bit integer which is a mask indicating threads participating\nin barrier where the bit position corresponds to thread’s laneid.\nshfl.sync exchanges register data between threads in membermask.\nEach thread in the currently executing warp will compute a source lane index j based on input\noperands b and c and the mode. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-shfl-sync", "introducedIn": "PTX ISA 6.0", "requiredTargets": [ "sm_30" ], "deprecatedIn": "PTX ISA 6.0 (legacy non-sync form only)", "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.shl", "mnemonic": "shl", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Shift Left", "category": "Logic and Shift Instructions", "summary": "Shift bits left, filling with zero.", "syntax": "shl.type d, a, b;", "syntax_forms": [ { "syntax": "shl.type d, a, b;", "description": "Logical left shift by an unsigned shift amount b.", "dataTypes": [ "b16", "b32", "b64" ], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [ "b16", "b32", "b64" ], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Value to shift" }, { "name": "b", "desc": "Shift amount (u32)" } ], "semantics": "d = a << b.", "examples": null, "description": "Shift a left by the amount specified by unsigned 32-bit value in b.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#logic-and-shift-instructions-shl", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.shr", "mnemonic": "shr", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Shift Right", "category": "Logic and Shift Instructions", "summary": "Shift bits right, arithmetic or logical depending on the operand's signedness.", "syntax": "shr.type d, a, b;", "syntax_forms": [ { "syntax": "shr.type d, a, b;", "description": "Right shift: arithmetic (sign-extending) for signed types, logical for unsigned types.", "dataTypes": [ "s16", "s32", "s64", "u16", "u32", "u64" ], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [ "s16", "s32", "s64", "u16", "u32", "u64" ], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Value to shift" }, { "name": "b", "desc": "Shift amount (u32)" } ], "semantics": "d = a >> b.", "examples": null, "description": "Shift a right by the amount specified by unsigned 32-bit value in b. Signed shifts fill with\nthe sign bit, unsigned and untyped shifts fill with 0.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#logic-and-shift-instructions-shr", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.sin", "mnemonic": "sin", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Sine (Approximate)", "category": "Arithmetic", "summary": "Fast hardware approximation of sin(x).", "syntax": "sin.approx.f32 d, a;", "syntax_forms": [ { "syntax": "sin.approx.f32 d, a;", "description": "Reduced-precision sine, valid over a hardware-defined input range.", "dataTypes": [ "f32" ], "stateSpaces": [], "scopes": [], "modifiers": [ "approx" ], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [ "f32" ], "stateSpaces": [], "scopes": [], "modifiers": [ "approx" ], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand (radians)" } ], "semantics": "d ≈ sin(a).", "examples": "sin.approx.ftz.f32 sa, a;", "description": "Find the sine of the angle a (in radians).", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#floating-point-instructions-sin", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.slct", "mnemonic": "slct", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "slct", "category": "Comparison and Selection Instructions", "summary": "Conditional selection.", "syntax": "slct.dtype.s32 d, a, b, c;", "syntax_forms": [ { "syntax": "slct.dtype.s32 d, a, b, c;", "description": "Conditional selection. If c >= 0, a is stored in d, otherwise b is stored in d. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_13" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" }, { "name": "b", "desc": "Source operand" }, { "name": "c", "desc": "Source operand" } ], "semantics": "d = (c >= 0) ? a : b;", "examples": "slct.u32.s32 x, y, z, val;\nslct.ftz.u64.f32 A, B, C, fval;", "description": "Conditional selection. If c >= 0, a is stored in d, otherwise b is stored in d. Operands d, a, and b are treated as a bitsize type of the same width as the first\ninstruction type; operand c must match the second instruction type (.s32 or.f32 ). The\nselected input is copied to the output without modification.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#comparison-and-selection-instructions-slct", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_13" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.sqrt", "mnemonic": "sqrt", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "sqrt", "category": "Floating-Point Instructions", "summary": "Compute sqrt( a ) and store the result in d.", "syntax": "sqrt.approx{.ftz}.f32 d, a; // fast, approximate square root", "syntax_forms": [ { "syntax": "sqrt.approx{.ftz}.f32 d, a; // fast, approximate square root", "description": "Compute sqrt( a ) and store the result in d.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": "d = sqrt(a);", "examples": "sqrt.approx.ftz.f32 r,x;\nsqrt.rn.ftz.f32 r,x;\nsqrt.rn.f64 r,x;", "description": "Compute sqrt( a ) and store the result in d.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#floating-point-instructions-sqrt", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.st", "mnemonic": "st", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Store", "category": "Data Movement and Conversion Instructions", "summary": "Store a register value into the specified state space.", "syntax": "st.space.type [a], b;", "syntax_forms": [ { "syntax": "st.space.type [a], b;", "description": "Store to an explicit state space.", "dataTypes": [ "b8", "b16", "b32", "b64", "s8", "s16", "s32", "s64", "u8", "u16", "u32", "u64", "f16", "f32", "f64" ], "stateSpaces": [ "global", "local", "shared", "param" ], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [ "b16", "b32", "b64", "b8", "f16", "f32", "f64", "s16", "s32", "s64", "s8", "u16", "u32", "u64", "u8" ], "stateSpaces": [ "global", "local", "param", "shared" ], "scopes": [], "modifiers": [], "operands": [ { "name": "a", "desc": "Destination address" }, { "name": "b", "desc": "Value to store" } ], "semantics": "*a = b, in the given state space.", "examples": "st.global.f32 [a],b;\nst.local.b32 [q+4],a;\nst.global.v4.s32 [p],Q;\nst.local.b32 [q+-8],a; // negative offset\nst.local.s32 [100],r7; // immediate address\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Store the value of operand b in the location specified by the destination address\noperand a in specified state space. If no state space is given, perform the store using Generic Addressing. Stores to const memory are illegal.\nIf no sub-qualifier is specified with.shared state space, then::cta is assumed by default.\nSupported addressing modes for operand a and alignment requirements are described in Addresses as Operands.\nIf.param is specified without any sub-qualifiers then it defaults to.param::func.\nInstruction st.param{::func} used for passing arguments to device function cannot be predicated. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-st", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.st.async", "mnemonic": "st.async", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "st.async", "category": "Data Movement and Conversion Instructions", "summary": "st.async is a non-blocking instruction which initiates an asynchronous store operation that stores the value specified by source operand b to the destination memory location specified by operand a.", "syntax": "st.async{.weak}{.ss}.completion_mechanism{.vec}.type [a], b, [mbar];", "syntax_forms": [ { "syntax": "st.async{.weak}{.ss}.completion_mechanism{.vec}.type [a], b, [mbar];", "description": "st.async is a non-blocking instruction which initiates an asynchronous store operation that\nstores the value specified by source operand b to the destination memory location\nspecified by operand a. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_90" ], "introducedIn": "PTX ISA 8.1" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "st.async.shared::cluster.mbarrier::complete_tx::bytes.u32 [addr], b, [mbar_addr];\n\nst.async.sys.release.global.u32 [addr], b;\n\nst.async.mbarrier::complete_tx::bytes.b128 [addr], b, [mbar_addr];\n// (truncated - see the official PTX ISA docs for the full example)", "description": "st.async is a non-blocking instruction which initiates an asynchronous store operation that\nstores the value specified by source operand b to the destination memory location\nspecified by operand a.\nst.async is performed in the generic proxy.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-st-async", "introducedIn": "PTX ISA 8.1", "requiredTargets": [ "sm_90" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.st.bulk", "mnemonic": "st.bulk", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "st.bulk", "category": "Data Movement and Conversion Instructions", "summary": "st.bulk instruction initializes a region of shared memory starting from the location specified by destination address operand a.", "syntax": "st.bulk{.weak}{.shared::cta} [a], size, initval; // initval must be zero", "syntax_forms": [ { "syntax": "st.bulk{.weak}{.shared::cta} [a], size, initval; // initval must be zero", "description": "st.bulk instruction initializes a region of shared memory starting from the location specified\nby destination address operand a. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_100" ], "introducedIn": "PTX ISA 8.6" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "st.bulk.weak.shared::cta [dst], n, 0;\n\nst.bulk [gdst], 4096, 0;", "description": "st.bulk instruction initializes a region of shared memory starting from the location specified\nby destination address operand a.\nThe 32-bit or 64-bit integer operand size specifies the amount of memory to be initialized in terms of\nnumber of bytes. size must be a multiple of 8. If the value is not a multiple of 8, then the\nbehavior is undefined. The maximum value of size operand can be 16777216.\nThe integer immediate operand initval specifies the initialization value for the memory\nlocations. The only numeric value allowed for operand initval is 0.\nIf no state space is specified then Generic Addressing is used. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-st-bulk", "introducedIn": "PTX ISA 8.6", "requiredTargets": [ "sm_100" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.stackrestore", "mnemonic": "stackrestore", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "stackrestore", "category": "Stack Manipulation Instructions", "summary": "Sets the current stack pointer to source register a.", "syntax": "stackrestore.type a;", "syntax_forms": [ { "syntax": "stackrestore.type a;", "description": "Sets the current stack pointer to source register a. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_52" ], "introducedIn": "PTX ISA 7.3" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "a", "desc": "Source operand" } ], "semantics": "stackptr = a;", "examples": ".reg .u32 ra;\nstacksave.u32 ra;\n// Code that may modify stack pointer\n...\nstackrestore.u32 ra;", "description": "Sets the current stack pointer to source register a.\nWhen stackrestore is used with operand a written by a prior stacksave instruction, it\nwill effectively restore the state of stack as it was before stacksave was executed. Note that\nif stackrestore is used with an arbitrary value of a, it may cause corruption of stack\npointer. This implies that the correct use of this feature requires that stackrestore.type a is\nused after stacksave.type a without redefining the value of a between them.\nOperand a has the same type as the instruction type.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#stack-manipulation-instructions-stackrestore", "introducedIn": "PTX ISA 7.3", "requiredTargets": [ "sm_52" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.stacksave", "mnemonic": "stacksave", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "stacksave", "category": "Stack Manipulation Instructions", "summary": "Copies the current value of stack pointer into the destination register d.", "syntax": "stacksave.type d;", "syntax_forms": [ { "syntax": "stacksave.type d;", "description": "Copies the current value of stack pointer into the destination register d. Pointer returned by stacksave can be used in a subsequent stackrestore instruction to restore the stack\npointer. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_52" ], "introducedIn": "PTX ISA 7.3" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" } ], "semantics": "d = stackptr;", "examples": ".reg .u32 rd;\nstacksave.u32 rd;\n\n.reg .u64 rd1;\nstacksave.u64 rd1;", "description": "Copies the current value of stack pointer into the destination register d. Pointer returned by stacksave can be used in a subsequent stackrestore instruction to restore the stack\npointer. If d is modified prior to use in stackrestore instruction, it may corrupt data in\nthe stack.\nDestination operand d has the same type as the instruction type.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#stack-manipulation-instructions-stacksave", "introducedIn": "PTX ISA 7.3", "requiredTargets": [ "sm_52" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.stmatrix", "mnemonic": "stmatrix", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "stmatrix", "category": "Warp Level Matrix Multiply-Accumulate Instructions", "summary": "Collectively store one or more matrices across all threads in a warp to the location indicated by the address operand p, in.shared state space.", "syntax": "stmatrix.sync.aligned.shape.num{.trans}{.ss}.type [p], r;", "syntax_forms": [ { "syntax": "stmatrix.sync.aligned.shape.num{.trans}{.ss}.type [p], r;", "description": "Collectively store one or more matrices across all threads in a warp to the location indicated by\nthe address operand p, in.shared state space. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_90" ], "introducedIn": "PTX ISA 7.8" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "// Store a single 8x8 matrix using 64-bit addressing\n.reg .b64 addr;\n.reg .b32 r;\nstmatrix.sync.aligned.m8n8.x1.shared.b16 [addr], {r};\n\n// Store two 8x8 matrices in column-major format\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Collectively store one or more matrices across all threads in a warp to the location indicated by\nthe address operand p, in.shared state space. If no state space is provided, generic\naddressing is used, such that the address in p points into.shared space. If the generic\naddress doesn’t fall in.shared state space, then the behavior is undefined.\nThe.shape qualifier indicates the dimensions of the matrices being loaded. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#warp-level-matrix-instructions-stmatrix", "introducedIn": "PTX ISA 7.8", "requiredTargets": [ "sm_90" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.sub", "mnemonic": "sub", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Subtract", "category": "Arithmetic", "summary": "Subtract the second operand from the first, with optional saturation for signed 32-bit integers.", "syntax": "sub.type d, a, b;", "syntax_forms": [ { "syntax": "sub.type d, a, b;", "description": "Generic subtract across integer and floating-point types.", "dataTypes": [ "s16", "s32", "s64", "u16", "u32", "u64", "f32", "f64" ], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" }, { "syntax": "sub.sat.s32 d, a, b;", "description": "Signed 32-bit subtract with saturation.", "dataTypes": [ "s32" ], "stateSpaces": [], "scopes": [], "modifiers": [ "sat" ], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [ "f32", "f64", "s16", "s32", "s64", "u16", "u32", "u64" ], "stateSpaces": [], "scopes": [], "modifiers": [ "sat" ], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Minuend" }, { "name": "b", "desc": "Subtrahend" } ], "semantics": "d = a - b.", "examples": "sub.s32 c,a,b;\nsub.u8x4 p, q, r;\n\nsub.f32 c,a,b;\nsub.rn.ftz.f32 f1,f2,f3;\n\n// scalar f16 subtractions\nsub.f16 d0, a0, b0;\nsub.rn.f16 d1, a1, b1;\nsub.bf16 bd0, ba0, bb0;\nsub.rn.bf16 bd1, ba1, bb1;\n// (truncated - see the official PTX ISA docs for the full example)\n\n.reg .f32 fc, fd;\n.reg .f16 ha;\nsub.rz.f32.f16.sat fd, ha, fc;", "description": "Performs subtraction and writes the resulting value into a destination register.\nFor.f16x2 and.bf16x2 instruction type, forms input vectors by half word values from source\noperands. Half-word operands are then subtracted in parallel to produce.f16x2 or.bf16x2 result in destination.\nFor.f16 instruction type, operands d, a and b have.f16 or.b16 type. For.f16x2 instruction type, operands d, a and b have.b32 type. For.bf16 instruction type, operands d, a, b have.b16 type. For.bf16x2 instruction type,\noperands d, a, b have.b32 type.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#half-precision-floating-point-instructions-sub", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.sub.cc", "mnemonic": "sub.cc", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "sub.cc", "category": "Extended-Precision Integer Arithmetic Instructions", "summary": "Performs integer subtraction and writes the borrow-out value into the condition code register.", "syntax": "sub.cc.type d, a, b;", "syntax_forms": [ { "syntax": "sub.cc.type d, a, b;", "description": "Performs integer subtraction and writes the borrow-out value into the condition code register.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 1.2" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" }, { "name": "b", "desc": "Source operand" } ], "semantics": "d = a - b;", "examples": "@p sub.cc.u32 x1,y1,z1; // extended-precision subtraction\n@p subc.cc.u32 x2,y2,z2; // of two 128-bit values\n@p subc.cc.u32 x3,y3,z3;\n@p subc.u32 x4,y4,z4;", "description": "Performs integer subtraction and writes the borrow-out value into the condition code register.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#extended-precision-arithmetic-instructions-sub-cc", "introducedIn": "PTX ISA 1.2", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.subc", "mnemonic": "subc", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "subc", "category": "Extended-Precision Integer Arithmetic Instructions", "summary": "Performs integer subtraction with borrow-in and optionally writes the borrow-out value into the\ncondition code register.", "syntax": "subc{.cc}.type d, a, b;", "syntax_forms": [ { "syntax": "subc{.cc}.type d, a, b;", "description": "Performs integer subtraction with borrow-in and optionally writes the borrow-out value into the\ncondition code register.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 1.2" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" }, { "name": "b", "desc": "Source operand" } ], "semantics": "d = a - (b + CC.CF);", "examples": "@p sub.cc.u32 x1,y1,z1; // extended-precision subtraction\n@p subc.cc.u32 x2,y2,z2; // of two 128-bit values\n@p subc.cc.u32 x3,y3,z3;\n@p subc.u32 x4,y4,z4;", "description": "Performs integer subtraction with borrow-in and optionally writes the borrow-out value into the\ncondition code register.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#extended-precision-arithmetic-instructions-subc", "introducedIn": "PTX ISA 1.2", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.suld", "mnemonic": "suld", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "suld", "category": "Surface Instructions", "summary": "suld.b.{1d,2d,3d} Load from surface memory using a surface coordinate vector.", "syntax": "suld.b.geom{.cop}.vec.dtype.clamp d, [a, b]; // unformatted", "syntax_forms": [ { "syntax": "suld.b.geom{.cop}.vec.dtype.clamp d, [a, b]; // unformatted", "description": "suld.b.{1d,2d,3d}\nLoad from surface memory using a surface coordinate vector. The instruction loads data from the\nsurface named by operand a at coordinates given by operand b into destination d. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 1.5" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "suld.b.1d.v4.b32.trap {s1,s2,s3,s4}, [surf_B, {x}];\nsuld.b.3d.v2.b64.trap {r1,r2}, [surf_A, {x,y,z,w}];\nsuld.b.a1d.v2.b32 {r0,r1}, [surf_C, {idx,x}];\nsuld.b.a2d.b32 r0, [surf_D, {idx,x,y,z}]; // z ignored", "description": "suld.b.{1d,2d,3d}\nLoad from surface memory using a surface coordinate vector. The instruction loads data from the\nsurface named by operand a at coordinates given by operand b into destination d. Operand a is a.surfref variable or.u64 register. Operand b is a scalar or singleton tuple\nfor 1d surfaces; is a two-element vector for 2d surfaces; and is a four-element vector for 3d\nsurfaces, where the fourth element is ignored. Coordinate elements are of type.s32.\nsuld.b performs an unformatted load of binary data. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#surface-instructions-suld", "introducedIn": "PTX ISA 1.5", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.suq", "mnemonic": "suq", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "suq", "category": "Surface Instructions", "summary": "Query an attribute of a surface.", "syntax": "suq.query.b32 d, [a];", "syntax_forms": [ { "syntax": "suq.query.b32 d, [a];", "description": "Query an attribute of a surface. Operand a is a.surfref variable or a.u64 register.\nQuery Returns.width.height.depth value in elements. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 1.5" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "suq.width.b32 %r1, [surf_A];", "description": "Query an attribute of a surface. Operand a is a.surfref variable or a.u64 register.\nQuery Returns.width.height.depth value in elements.channel_data_type Unsigned integer corresponding to source language’s channel data\ntype enumeration. If the source language combines channel data\ntype and channel order into a single enumeration type, that value\nis returned for both channel_data_type and channel_order queries..channel_order Unsigned integer corresponding to source language’s channel order\nenumeration. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#surface-instructions-suq", "introducedIn": "PTX ISA 1.5", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.sured", "mnemonic": "sured", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "sured", "category": "Surface Instructions", "summary": "Reduction to surface memory using a surface coordinate vector.", "syntax": "sured.b.op.geom.ctype.clamp [a,b],c; // byte addressing", "syntax_forms": [ { "syntax": "sured.b.op.geom.ctype.clamp [a,b],c; // byte addressing", "description": "Reduction to surface memory using a surface coordinate vector. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 2.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "sured.b.add.2d.u32.trap [surf_A, {x,y}], r1;\nsured.p.min.1d.u32.trap [surf_B, {x}], r1;\nsured.b.max.1d.u64.trap [surf_C, {x}], r1;\nsured.p.min.1d.b64.trap [surf_D, {x}], r1;", "description": "Reduction to surface memory using a surface coordinate vector. The instruction performs a reduction\noperation with data from operand c to the surface named by operand a at coordinates given by\noperand b. Operand a is a.surfref variable or.u64 register. Operand b is a\nscalar or singleton tuple for 1d surfaces; is a two-element vector for 2d surfaces; and is a\nfour-element vector for 3d surfaces, where the fourth element is ignored. Coordinate elements are of\ntype.s32.\nsured.b performs an unformatted reduction on.u32,.s32,.b32,.u64, or.s64 data. The lowest dimension coordinate represents a byte offset into the surface and is not\nscaled. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#surface-instructions-sured", "introducedIn": "PTX ISA 2.0", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.sust", "mnemonic": "sust", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "sust", "category": "Surface Instructions", "summary": "sust.{1d,2d,3d} Store to surface memory using a surface coordinate vector.", "syntax": "sust.b.{1d,2d,3d}{.cop}.vec.ctype.clamp [a, b], c; // unformatted", "syntax_forms": [ { "syntax": "sust.b.{1d,2d,3d}{.cop}.vec.ctype.clamp [a, b], c; // unformatted", "description": "sust.{1d,2d,3d}\nStore to surface memory using a surface coordinate vector. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 1.5" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "sust.p.1d.v4.b32.trap [surf_B, {x}], {f1,f2,f3,f4};\nsust.b.3d.v2.b64.trap [surf_A, {x,y,z,w}], {r1,r2};\nsust.b.a1d.v2.b64 [surf_C, {idx,x}], {r1,r2};\nsust.b.a2d.b32 [surf_D, {idx,x,y,z}], r0; // z ignored", "description": "sust.{1d,2d,3d}\nStore to surface memory using a surface coordinate vector. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b. Operand a is\na.surfref variable or.u64 register. Operand b is a scalar or singleton tuple for 1d\nsurfaces; is a two-element vector for 2d surfaces; and is a four-element vector for 3d surfaces,\nwhere the fourth element is ignored. Coordinate elements are of type.s32.\nsust.b performs an unformatted store of binary data. The lowest dimension coordinate represents\na byte offset into the surface and is not scaled. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#surface-instructions-sust", "introducedIn": "PTX ISA 1.5", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.szext", "mnemonic": "szext", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "szext", "category": "Integer Arithmetic Instructions", "summary": "Sign-extends or zero-extends an N-bit value from operand a where N is specified in operand b.", "syntax": "szext.mode.type d, a, b;", "syntax_forms": [ { "syntax": "szext.mode.type d, a, b;", "description": "Sign-extends or zero-extends an N-bit value from operand a where N is specified in operand b. The resulting value is stored in the destination operand d.\nFor the. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_70" ], "introducedIn": "PTX ISA 7.6" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" }, { "name": "b", "desc": "Source operand" } ], "semantics": "b1 = b & 0x1f;\ntoo_large = (b >= 32 && .mode == .clamp) ? true : false;\nmask = too_large ? 0 : (~0) << b1;\nsign_pos = (b1 - 1) & 0x1f;\n\nif (b1 == 0 || too_large || .type != .s32) {\n sign_bit = false;\n} else {\n sign_bit = (a >> sign_pos) & 1;\n}\nd = (a & ~mask) | (sign_bit ? mask | 0);", "examples": "szext.clamp.s32 rd, ra, rb;\nszext.wrap.u32 rd, 0xffffffff, 0; // Result is 0.", "description": "Sign-extends or zero-extends an N-bit value from operand a where N is specified in operand b. The resulting value is stored in the destination operand d.\nFor the.s32 instruction type, the value in a is treated as an N-bit signed value and the\nmost significant bit of this N-bit value is replicated up to bit 31. For the.u32 instruction\ntype, the value in a is treated as an N-bit unsigned number and is zero-extended to 32\nbits. Operand b is an unsigned 32-bit value.\nIf the value of N is 0, then the result of szext is 0. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#integer-arithmetic-instructions-szext", "introducedIn": "PTX ISA 7.6", "requiredTargets": [ "sm_70" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.tanh", "mnemonic": "tanh", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "tanh", "category": "Half Precision Floating-Point Instructions", "summary": "Take hyperbolic tangent value of a.", "syntax": "tanh.approx.f32 d, a;", "syntax_forms": [ { "syntax": "tanh.approx.f32 d, a;", "description": "Take hyperbolic tangent value of a.\nThe operands d and a are of type.f32.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_75" ], "introducedIn": "PTX ISA 7.0" }, { "syntax": "tanh.approx.type d, a;", "description": "Take hyperbolic tangent value of a.\nThe type of operands d and a are as specified by.type.\nFor.f16x2 or. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_75" ], "introducedIn": "PTX ISA 7.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "Source operand" } ], "semantics": "if (.type == .f16 || .type == .bf16) {\n d = tanh(a)\n} else if (.type == .f16x2 || .type == .bf16x2) {\n fA[0] = a[0:15];\n fA[1] = a[16:31];\n d[0] = tanh(fA[0])\n d[1] = tanh(fA[1])\n}", "examples": "tanh.approx.f32 ta, a;\n\ntanh.approx.f16 h1, h0;\ntanh.approx.f16x2 hd1, hd0;\ntanh.approx.bf16 b1, b0;\ntanh.approx.bf16x2 hb1, hb0;", "description": "Take hyperbolic tangent value of a.\nThe type of operands d and a are as specified by.type.\nFor.f16x2 or.bf16x2 instruction type, each of the half-word operands are operated in\nparallel and the results are packed appropriately into a.f16x2 or.bf16x2.\nFor.f16 instruction type, operands d and a have.f16 or.b16 type.\nFor.f16x2 instruction type, operands d and a have.f16x2 or.b32 type.\nFor.bf16 instruction type, operands d and a have.b16 type.\nFor.bf16x2 instruction type, operands d and a have.b32 type.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#half-precision-floating-point-instructions-tanh", "introducedIn": "PTX ISA 7.0", "requiredTargets": [ "sm_75" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.tcgen05.alloc", "mnemonic": "tcgen05.alloc", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "tcgen05.alloc", "category": "Tensor Memory Allocation and Management Instructions", "summary": "tcgen05.alloc is a blocking instruction which dynamically allocates the specified number of columns in the Tensor Memory and writes the address of the allocated Tensor Memory into shared memory at the location specified by address operand dst.", "syntax": "tcgen05.alloc.cta_group.sync.aligned{.shared::cta}.b32 [dst], nCols;", "syntax_forms": [ { "syntax": "tcgen05.alloc.cta_group.sync.aligned{.shared::cta}.b32 [dst], nCols;", "description": "tcgen05.alloc is a blocking instruction which dynamically allocates the specified number of columns in the Tensor Memory and writes the address of the allocated Tensor Memory into shared memory at the… (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_100a" ], "introducedIn": "PTX ISA 8.6" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "// Example 1:\n\ntcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [sMemAddr1], 32;\nld.shared.b32 taddr, [sMemAddr1];\n// use taddr ...\n// more allocations and its usages ...\n// (truncated - see the official PTX ISA docs for the full example)", "description": "tcgen05.alloc is a blocking instruction which dynamically allocates\nthe specified number of columns in the Tensor Memory and writes\nthe address of the allocated Tensor Memory into shared memory\nat the location specified by address operand dst. The tcgen05.alloc blocks if the\nrequested amount of Tensor Memory is not available and unblocks\nas soon as the requested amount of Tensor Memory becomes\navailable for allocation.\ntcgen05.dealloc is a potentially blocking instruction which deallocates the Tensor Memory specified by the Tensor Memory address taddr. (see the official PTX ISA docs for the full description)", "sourceUrl": null, "introducedIn": "PTX ISA 8.6", "requiredTargets": [ "sm_100a" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.tcgen05.commit", "mnemonic": "tcgen05.commit", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "tcgen05.commit", "category": "TensorCore 5th Generation Family Instructions", "summary": "The instruction tcgen05.commit is an asynchronous instruction which makes the mbarrier object, specified by the address operand mbar, track the completion of all the prior asynchronous tcgen05 operations, as listed in mbarrier based completion mechanism, initiated by the executing thread.", "syntax": "tcgen05.commit.cta_group.completion_mechanism{.shared::cluster}{.multicast}.b64", "syntax_forms": [ { "syntax": "tcgen05.commit.cta_group.completion_mechanism{.shared::cluster}{.multicast}.b64", "description": "The instruction tcgen05.commit is an asynchronous instruction which makes the mbarrier object, specified by the address operand mbar, track the completion of all the prior asynchronous tcgen05 operati… (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_100a" ], "introducedIn": "PTX ISA 8.6" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "Example 1:\ntcgen05.cp.cta_group::1.128x256b [taddr0], sdesc0;\ntcgen05.commit.cta_group::1.mbarrier::arrive::one.b64 [mbarObj1];\n\nloop:\nmbarrier.try_wait.parity.b64 p, [mbarObj1], 0;\n// (truncated - see the official PTX ISA docs for the full example)", "description": "The instruction tcgen05.commit is an asynchronous instruction which makes the mbarrier object,\nspecified by the address operand mbar, track the completion of all the prior asynchronous tcgen05 operations, as listed in mbarrier based completion mechanism,\ninitiated by the executing thread. Upon the completion of the tracked asynchronous tcgen05 operations, the signal specified by the.completion_mechanism is triggered by the system\non the mbarrier object.\nThis instruction accesses its mbarrier operand using generic-proxy.\nThe instruction tcgen05.commit.cta_group::1 tracks for the completion of all prior\nasynchronous tcgen05 operations with.cta_group::1 issued by the current thread. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#tcgen-async-sync-operations-commit", "introducedIn": "PTX ISA 8.6", "requiredTargets": [ "sm_100a" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.tcgen05.cp", "mnemonic": "tcgen05.cp", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "tcgen05.cp", "category": "Tensor Memory Data Movement Instructions", "summary": "Instruction tcgen05.cp initiates an asynchronous copy operation from shared memory to the location specified by the address operand taddr in the Tensor Memory.", "syntax": "tcgen05.cp.cta_group.shape{.multicast}{.dst_fmt.src_fmt} [taddr], s-desc;", "syntax_forms": [ { "syntax": "tcgen05.cp.cta_group.shape{.multicast}{.dst_fmt.src_fmt} [taddr], s-desc;", "description": "Instruction tcgen05.cp initiates an asynchronous copy operation from shared memory to the\nlocation specified by the address operand taddr in the Tensor Memory. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_100a" ], "introducedIn": "PTX ISA 8.6" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "tcgen05.cp.cta_group::1.128x256b [taddr0], sdesc0;\ntcgen05.cp.cta_group::2.128x128b.b8x16.b6x16_p32 [taddr1], sdesc1;\ntcgen05.cp.cta_group::1.64x128b.warpx2::02_13 [taddr2], sdesc2;", "description": "Instruction tcgen05.cp initiates an asynchronous copy operation from shared memory to the\nlocation specified by the address operand taddr in the Tensor Memory.\nThe 64-bit register operand s-desc is the matrix descriptor which represents the source\nmatrix in the shared memory that needs to be copied. The format of the matrix descriptor is\ndescribed in Matrix Descriptors.\nThe.shape qualifier indicates the dimension of data to be copied as described in the Data Movement Shape.\nQualifier.cta_group specifies the number of CTAs whose Tensor Memory is\naccessed when a single thread of a single CTA executes the tcgen05.cp instruction.\nWhen. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-cp", "introducedIn": "PTX ISA 8.6", "requiredTargets": [ "sm_100a" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.tcgen05.dealloc", "mnemonic": "tcgen05.dealloc", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "tcgen05.dealloc", "category": "Tensor Memory Allocation and Management Instructions", "summary": "tcgen05.dealloc is a blocking instruction which de-allocates the Tensor Memory specified by the Tensor Memory address taddr. The operand nCols specifies the number of columns to be de-allocated.", "syntax": "tcgen05.dealloc.cta_group.sync.aligned.b32 taddr, nCols;", "syntax_forms": [ { "syntax": "tcgen05.dealloc.cta_group.sync.aligned.b32 taddr, nCols;", "description": "tcgen05.dealloc is a blocking instruction which de-allocates the Tensor Memory specified by the Tensor Memory address taddr. The operand nCols specifies the number of columns to be de-allocated.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_100a" ], "introducedIn": "PTX ISA 8.6" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "// de-allocate the columns previously allocated at taddr:\ntcgen05.dealloc.cta_group::1.sync.aligned.b32 taddr, 32;", "description": "tcgen05.dealloc is a blocking instruction which de-allocates the Tensor Memory specified by the Tensor Memory address taddr. The operand nCols specifies the number of columns to be de-allocated.", "sourceUrl": null, "introducedIn": "PTX ISA 8.6", "requiredTargets": [ "sm_100a" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.tcgen05.fence", "mnemonic": "tcgen05.fence", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "tcgen05.fence", "category": "TensorCore 5th Generation Family Instructions", "summary": "The instruction tcgen05.fence::before_thread_sync orders all the prior asynchronous tcgen05 operations with respect to the subsequent tcgen05 and the execution ordering operations.", "syntax": "tcgen05.fence::before_thread_sync ;", "syntax_forms": [ { "syntax": "tcgen05.fence::before_thread_sync ;", "description": "The instruction tcgen05.fence::before_thread_sync orders all the prior asynchronous tcgen05 operations with respect to the subsequent tcgen05 and the execution\nordering operations. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_100a" ], "introducedIn": "PTX ISA 8.6" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "// Producer thread:\n\ntcgen05.cp.cta_group::1.128x256b [taddr0], sdesc0;\n\ntcgen05.fence::before_thread_sync;\nst.relaxed.b32 [flag], 1;\n// (truncated - see the official PTX ISA docs for the full example)", "description": "The instruction tcgen05.fence::before_thread_sync orders all the prior asynchronous tcgen05 operations with respect to the subsequent tcgen05 and the execution\nordering operations.\nThe instruction tcgen05.fence::after_thread_sync orders all the subsequent asynchronous tcgen05 operations with respect to the prior tcgen05 and the execution ordering\noperations.\nThe tcgen05.fence::* instructions compose with execution ordering instructions across\na thread scope and provide ordering between tcgen05 instructions across the same scope.\nThe tcgen05.fence::before_thread_sync instructions behave as code motion fence for prior tcgen05 instructions as they cannot be hoisted across. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#tcgen05-special-sync-operations-fence", "introducedIn": "PTX ISA 8.6", "requiredTargets": [ "sm_100a" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.tcgen05.ld", "mnemonic": "tcgen05.ld", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "tcgen05.ld", "category": "Tensor Memory and Register Load/Store Instructions", "summary": "Instruction tcgen05.ld asynchronously loads data from the Tensor Memory at the location specified by the 32-bit address operand taddr into the destination register r, collectively across all threads of the warps.", "syntax": "// Base load instruction:\ntcgen05.ld.sync.aligned.shape1.num{.pack}.b32 r, [taddr];", "syntax_forms": [ { "syntax": "// Base load instruction:\ntcgen05.ld.sync.aligned.shape1.num{.pack}.b32 r, [taddr];", "description": "Instruction tcgen05.ld asynchronously loads data from the Tensor Memory at the location specified by the 32-bit address operand taddr into the destination register r, collectively across all threads o… (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_100a" ], "introducedIn": "PTX ISA 8.6" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "tcgen05.ld.sync.aligned.32x32b.x2.b32 {r0, r1}, [taddr1];\n\ntcgen05.ld.sync.aligned.16x128b.x4.b32 {r0, r1, r2, r3, r4, r5, r6, r7}, [taddr2];\n\ntcgen05.ld.red.sync.aligned.16x32bx2.x8.u32.max {r0, r1, r2, r3, r4, r5, r6, r7},\n redVal, [taddr3], 16;", "description": "Instruction tcgen05.ld asynchronously loads data from the Tensor Memory at the location specified by the 32-bit address operand taddr into the destination\nregister r, collectively across all threads of the warps.\nAll the threads in the warp must specify the same value of taddr, which must be the\nbase address of the collective load operation. Otherwise, the behavior is undefined.\nThe.shape qualifier and the.num qualifier together determines the total\ndimension of the data which is loaded from the Tensor Memory. The.shape qualifier indicates the base dimension of data to be accessed as described in the Data Movement Shape. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-ld", "introducedIn": "PTX ISA 8.6", "requiredTargets": [ "sm_100a" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.tcgen05.mma", "mnemonic": "tcgen05.mma", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "tcgen05.mma", "category": "TensorCore 5th Generation of MMA Instructions", "summary": "Instruction tcgen05.mma is an asynchronous instruction which initiates an MxNxK matrix multiply and accumulate operation, D = A*B+D where the A matrix is MxK, the B matrix is KxN, and the D matrix is MxN.", "syntax": "// 1. Floating-point type without block scaling:\ntcgen05.mma.cta_group.kind [d-tmem], a-desc, b-desc, idesc,\n{ disable-output-lane }, enable-input-d {, scale-input-d};", "syntax_forms": [ { "syntax": "// 1. Floating-point type without block scaling:\ntcgen05.mma.cta_group.kind [d-tmem], a-desc, b-desc, idesc,\n{ disable-output-lane }, enable-input-d {, scale-input-d};", "description": "Instruction tcgen05.mma is an asynchronous instruction which initiates an MxNxK matrix multiply and accumulate operation, D = A*B+D where the A matrix is MxK, the B matrix is KxN, and the D matrix is… (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_100a" ], "introducedIn": "PTX ISA 8.6" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "tcgen05.mma.cta_group::1.kind::tf32 [taddr0], adesc, bdesc, idesc, {m0, m1, m2, m3}, p;\ntcgen05.mma.cta_group::1.kind::mxf8f6f4 [taddr2], [taddr1], bdesc, idesc,\n [tmem_scaleA], [tmem_scaleB], p;\n\ntcgen05.commit.cta_group::1.mbarrier::arrive::one.b64 [mbarObj0];\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Instruction tcgen05.mma is an asynchronous instruction which initiates an MxNxK matrix\nmultiply and accumulate operation, D = A*B+D where the A matrix is MxK, the B matrix is KxN, and the D matrix is MxN.\nThe operation of the form D = A*B is issued when the input predicate argument enable-input-d is false.\nThe optional immediate argument scale-input-d can be specified to scale the input\nmatrix D as follows: D = A*B+D * (2 ^ - scale-input-d)\nThe valid range of values for argument scale-input-d is [0, 15]. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma", "introducedIn": "PTX ISA 8.6", "requiredTargets": [ "sm_100a" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.tcgen05.mma.sp", "mnemonic": "tcgen05.mma.sp", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "tcgen05.mma.sp", "category": "TensorCore 5th Generation of MMA Instructions", "summary": "Instruction tcgen05.mma.sp is an asynchronous instruction which initiates an MxNxK matrix multiply and accumulate operation of the form D = A*B+D where the A matrix is Mx(K/2), the B matrix is KxN, and the D matrix is MxN.", "syntax": "// 1. Floating-point type without block scaling:\ntcgen05.mma.sp.cta_group.kind [d-tmem], a-desc, b-desc, [sp-meta-tmem] , idesc,\n{ disable-output-lane }, enable-input-d{, scale-input-d};", "syntax_forms": [ { "syntax": "// 1. Floating-point type without block scaling:\ntcgen05.mma.sp.cta_group.kind [d-tmem], a-desc, b-desc, [sp-meta-tmem] , idesc,\n{ disable-output-lane }, enable-input-d{, scale-input-d};", "description": "Instruction tcgen05.mma.sp is an asynchronous instruction which initiates an MxNxK matrix multiply and accumulate operation of the form D = A*B+D where the A matrix is Mx(K/2), the B matrix is KxN, an… (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_100a" ], "introducedIn": "PTX ISA 8.6" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "tcgen05.mma.sp.cta_group::1.kind::f16 [taddr0], adesc, bdesc, [tmem_spmeta0], idesc, p;\n\ntcgen05.mma.sp.cta_group::1.kind::mxf8f6f4.collector::a:fill\n [taddr2], [taddr1], bdesc, [tmem_spmeta1], idesc,\n [tmem_scaleA], [tmem_scaleB], p;\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Instruction tcgen05.mma.sp is an asynchronous instruction which initiates an MxNxK matrix multiply and accumulate operation of the form D = A*B+D where the A matrix is Mx(K/2), the B matrix is KxN, and the D matrix is MxN. Sparse Matrices describes the details of the sparsity.\nThe operation of the form D = A*B is issued when the input predicate argument enable-input-d is false.\nThe optional immediate argument scale-input-d can be specified to scale the\ninput matrix D as follows: D = A*B+D * (2 ^ - scale-input-d)\nThe valid range of values for argument scale-input-d is [0, 15]. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma-sp", "introducedIn": "PTX ISA 8.6", "requiredTargets": [ "sm_100a" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.tcgen05.mma.ws", "mnemonic": "tcgen05.mma.ws", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "tcgen05.mma.ws", "category": "TensorCore 5th Generation of MMA Instructions", "summary": "Instruction tcgen05.mma.ws is an asynchronous instruction which initiates an MxNxK matrix multiply and accumulate operation, D = A*B+D where the A matrix is MxK, the B matrix is KxN, and the D matrix is MxN.", "syntax": "// 1. Floating-point type without block scaling:\ntcgen05.mma.ws.cta_group::1.kind{.collector_usage} [d-tmem], a-desc, b-desc, idesc,\nenable-input-d {, zero-column-mask-desc };", "syntax_forms": [ { "syntax": "// 1. Floating-point type without block scaling:\ntcgen05.mma.ws.cta_group::1.kind{.collector_usage} [d-tmem], a-desc, b-desc, idesc,\nenable-input-d {, zero-column-mask-desc };", "description": "Instruction tcgen05.mma.ws is an asynchronous instruction which initiates an MxNxK matrix multiply and accumulate operation, D = A*B+D where the A matrix is MxK, the B matrix is KxN, and the D matrix… (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_100a" ], "introducedIn": "PTX ISA 8.6" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2:use [taddr2], [taddr1], bdesc, idesc, p;\ntcgen05.commit.cta_group::1.mbarrier::arrive::one.b64 [mbarObj0];\n\nloop:\nmbarrier.try_wait.parity.b64 p, [mbarObj0], 0;\n@!p bra loop;", "description": "Instruction tcgen05.mma.ws is an asynchronous instruction which initiates an MxNxK matrix multiply and accumulate operation, D = A*B+D where the A matrix is MxK, the B matrix is KxN, and the D matrix is MxN.\nThe operation of the form D = A*B is issued when the input predicate argument enable-input-d is false.\nThe 32-bit register operand idesc is the instruction descriptor as described in Instruction descriptor, specifies the shapes, exact\ntypes, sparsity and other details of the input matrices, output matrix and the matrix\nmultiply and accumulate operation.\nThe qualifier. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma-ws", "introducedIn": "PTX ISA 8.6", "requiredTargets": [ "sm_100a" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.tcgen05.mma.ws.sp", "mnemonic": "tcgen05.mma.ws.sp", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "tcgen05.mma.ws.sp", "category": "TensorCore 5th Generation of MMA Instructions", "summary": "Instruction tcgen05.mma.ws.sp is an asynchronous instruction which initiates\nan MxNxK matrix multiply and accumulate operation, D = A*B+D where the A", "syntax": "// 1. Floating-point type without block scaling:\ntcgen05.mma.ws.sp.cta_group::1.kind{.collector_usage} [d-tmem], a-desc, b-desc,\n[sp-meta-tmem] , idesc,\nenable-input-d {, zero-column-mask-desc};", "syntax_forms": [ { "syntax": "// 1. Floating-point type without block scaling:\ntcgen05.mma.ws.sp.cta_group::1.kind{.collector_usage} [d-tmem], a-desc, b-desc,\n[sp-meta-tmem] , idesc,\nenable-input-d {, zero-column-mask-desc};", "description": "Instruction tcgen05.mma.ws.sp is an asynchronous instruction which initiates\nan MxNxK matrix multiply and accumulate operation, D = A*B+D where the A matrix is Mx(K/2), the B matrix is KxN, and the D (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_100a" ], "introducedIn": "PTX ISA 8.6" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "tcgen05.mma.ws.sp.cta_group::1.kind::tf32.collector::b1::fill [taddr1], [taddr0], bdesc,\n [tmem_spmeta0], idesc, p;\n\ntcgen05.commit.cta_group::1.mbarrier::arrive::one.b64 [mbarObj0];\n\nloop:\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Instruction tcgen05.mma.ws.sp is an asynchronous instruction which initiates\nan MxNxK matrix multiply and accumulate operation, D = A*B+D where the A matrix is Mx(K/2), the B matrix is KxN, and the D matrix\nis MxN. Sparse Matrices describes the details of the\nsparsity.\nThe operation of the form D = A*B is issued when the input predicate argument enable-input-d is false.\nThe 32-bit register operand idesc is the instruction descriptor as described in Instruction descriptor, specifies the shapes, exact\ntypes, sparsity and other details of the input matrices, output matrix and the matrix\nmultiply and accumulate operation.\nThe qualifier. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma-ws-sp", "introducedIn": "PTX ISA 8.6", "requiredTargets": [ "sm_100a" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.tcgen05.relinquish_alloc_permit", "mnemonic": "tcgen05.relinquish_alloc_permit", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "tcgen05.relinquish_alloc_permit", "category": "Tensor Memory Allocation and Management Instructions", "summary": "tcgen05.relinquish_alloc_permit specifies that the CTA of the executing thread is relinquishing the right to allocate Tensor Memory.", "syntax": "tcgen05.relinquish_alloc_permit.cta_group.sync.aligned;", "syntax_forms": [ { "syntax": "tcgen05.relinquish_alloc_permit.cta_group.sync.aligned;", "description": "tcgen05.relinquish_alloc_permit specifies that the CTA of the executing thread is relinquishing the right to allocate Tensor Memory.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_100a" ], "introducedIn": "PTX ISA 8.6" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;", "description": "tcgen05.relinquish_alloc_permit specifies that the CTA of the executing thread is relinquishing the right to allocate Tensor Memory.", "sourceUrl": null, "introducedIn": "PTX ISA 8.6", "requiredTargets": [ "sm_100a" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.tcgen05.shift", "mnemonic": "tcgen05.shift", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "tcgen05.shift", "category": "Tensor Memory Data Movement Instructions", "summary": "Instruction tcgen05.shift is an asynchronous instruction which initiates the shifting of 32-byte elements downwards across all the rows, except the last, by one row.", "syntax": "tcgen05.shift.cta_group.down [taddr];", "syntax_forms": [ { "syntax": "tcgen05.shift.cta_group.down [taddr];", "description": "Instruction tcgen05.shift is an asynchronous instruction which initiates the shifting of 32-byte\nelements downwards across all the rows, except the last, by one row. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_100a" ], "introducedIn": "PTX ISA 8.6" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "tcgen05.shift.down.cta_group::1 [taddr0];\ntcgen05.shift.down.cta_group::2 [taddr1];", "description": "Instruction tcgen05.shift is an asynchronous instruction which initiates the shifting of 32-byte\nelements downwards across all the rows, except the last, by one row. The address operand taddr specifies the base address of the matrix in the Tensor Memory whose rows must\nbe down shifted.\nThe lane of the address operand taddr must be aligned to 32.\nQualifier.cta_group specifies the number of CTAs whose Tensor Memory is touched when a single thread of a single CTA executes the tcgen05.shift instruction.\nWhen.cta_group::1 is specified, the shift operation is performed in the Tensor Memory of the current CTA. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-shift", "introducedIn": "PTX ISA 8.6", "requiredTargets": [ "sm_100a" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.tcgen05.st", "mnemonic": "tcgen05.st", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "tcgen05.st", "category": "Tensor Memory and Register Load/Store Instructions", "summary": "Instruction tcgen05.st asynchronously stores data from the source register r into the Tensor Memory at the location specified by the 32-bit address operand taddr, collectively across all threads of the warps.", "syntax": "tcgen05.st.sync.aligned.shape1.num{.unpack}.b32 [taddr], r;", "syntax_forms": [ { "syntax": "tcgen05.st.sync.aligned.shape1.num{.unpack}.b32 [taddr], r;", "description": "Instruction tcgen05.st asynchronously stores data from the source register r into the Tensor Memory at the location specified by the 32-bit address operand taddr, collectively across all threads of th… (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_100a" ], "introducedIn": "PTX ISA 8.6" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "tcgen05.st.sync.aligned.16x64b.x4.b32 [taddr0], {r0, r1, r2, r3};\n\ntcgen05.st.sync.aligned.16x128b.x1.unpack::16b.b32 [taddr1], {r0, r1};", "description": "Instruction tcgen05.st asynchronously stores data from the source register r into\nthe Tensor Memory at the location specified by the 32-bit address operand taddr,\ncollectively across all threads of the warps.\nAll the threads in the warp must specify the same value of taddr, which must be the base\naddress of the collective store operation. Otherwise, the behavior is undefined.\nThe.shape qualifier and the.num qualifier together determines the total dimension\nof the data which is stored to the Tensor Memory. The.shape qualifier indicates the base\ndimension of data to be accessed as described in the Data Movement Shape. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-st", "introducedIn": "PTX ISA 8.6", "requiredTargets": [ "sm_100a" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.tcgen05.wait", "mnemonic": "tcgen05.wait", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "tcgen05.wait", "category": "Tensor Memory and Register Load/Store Instructions", "summary": "Instruction tcgen05.wait::st causes the executing thread to block until all prior tcgen05.st operations issued by the executing thread have completed.", "syntax": "tcgen05.wait_operation.sync.aligned;", "syntax_forms": [ { "syntax": "tcgen05.wait_operation.sync.aligned;", "description": "Instruction tcgen05.wait::st causes the executing thread to block until all prior tcgen05.st operations issued by the executing thread have completed.\nInstruction tcgen05. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_100a" ], "introducedIn": "PTX ISA 8.6" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "Example 1:\n\ntcgen05.ld.sync.aligned.32x32b.x2.b32 {r0, r1}, [taddr0];\n\n// Prevents subsequent tcgen05.mma from racing ahead of the tcgen05.ld\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Instruction tcgen05.wait::st causes the executing thread to block until all prior tcgen05.st operations issued by the executing thread have completed.\nInstruction tcgen05.wait::ld causes the executing thread to block until all prior tcgen05.ld operations issued by the executing thread have completed.\nThe mandatory.sync qualifier indicates that tcgen05.wait_operation causes the\nexecuting thread to wait until all threads in the warp execute the same tcgen05.wait_operation instruction before resuming execution.\nThe mandatory.aligned qualifier indicates that all threads in the warp must execute the\nsame tcgen05.wait_operation instruction.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-wait", "introducedIn": "PTX ISA 8.6", "requiredTargets": [ "sm_100a" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.tensormap.cp_fenceproxy", "mnemonic": "tensormap.cp_fenceproxy", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "tensormap.cp_fenceproxy", "category": "Parallel Synchronization and Communication Instructions", "summary": "The tensormap.cp_fenceproxy instructions perform the following operations in order: Copies data of size specified by the size argument, in bytes, from the location specified by the address operand…", "syntax": "tensormap.cp_fenceproxy.cp_qualifiers.fence_qualifiers.sync.aligned [dst], [src], size;", "syntax_forms": [ { "syntax": "tensormap.cp_fenceproxy.cp_qualifiers.fence_qualifiers.sync.aligned [dst], [src], size;", "description": "The tensormap.cp_fenceproxy instructions perform the following operations in order: Copies data of size specified by the size argument, in bytes, from the location specified by the address operand src… (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_90" ], "introducedIn": "PTX ISA 8.3" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "// Example: manipulate a tensor-map object and then consume it in cp.async.bulk.tensor\n\n.reg .b64 new_addr;\n.global .align 128 .b8 gbl[128];\n.shared .align 128 .b8 sMem[128];\n// (truncated - see the official PTX ISA docs for the full example)", "description": "The tensormap.cp_fenceproxy instructions perform the following operations in order:\nCopies data of size specified by the size argument, in bytes, from the location specified\nby the address operand src in shared memory to the location specified by the address operand dst in the global memory, in the generic proxy. Establishes a uni-directional proxy release pattern on the ordering from the copy operation\nto the subsequent access performed in the tensormap proxy on the address dst.\nThe valid value of immediate operand size is 128.\nThe operands src and dst specify non-generic addresses in shared::cta and global state space respectively.\nThe. (see the official PTX ISA docs for the full description)", "sourceUrl": null, "introducedIn": "PTX ISA 8.3", "requiredTargets": [ "sm_90" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.tensormap.replace", "mnemonic": "tensormap.replace", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "tensormap.replace", "category": "Data Movement and Conversion Instructions", "summary": "The tensormap.replace instruction replaces the field, specified by.field qualifier, of the tensor-map object at the location specified by the address operand addr with a new value.", "syntax": "tensormap.replace.mode.field1{.ss}.b1024.type [addr], new_val;", "syntax_forms": [ { "syntax": "tensormap.replace.mode.field1{.ss}.b1024.type [addr], new_val;", "description": "The tensormap.replace instruction replaces the field, specified by.field qualifier,\nof the tensor-map object at the location specified by the address operand addr with a\nnew value. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_90a" ], "introducedIn": "PTX ISA 8.3" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "tensormap.replace.tile.global_address.shared::cta.b1024.b64 [sMem], new_val;", "description": "The tensormap.replace instruction replaces the field, specified by.field qualifier,\nof the tensor-map object at the location specified by the address operand addr with a\nnew value. The new value is specified by the argument new_val.\nQualifier.mode specifies the mode of the tensor-map object\nlocated at the address operand addr.\nInstruction type.b1024 indicates the size of the tensor-map object, which is 1024 bits.\nOperand new_val has the type.type. When.field is specified as.global_address or.global_stride,.type must be.b64. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-tensormap-replace", "introducedIn": "PTX ISA 8.3", "requiredTargets": [ "sm_90a" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.testp", "mnemonic": "testp", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "testp", "category": "Floating-Point Instructions", "summary": "testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False.", "syntax": "testp.op.type p, a; // result is .pred", "syntax_forms": [ { "syntax": "testp.op.type p, a; // result is .pred", "description": "testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False.\ntestp.finite True if the input is not infinite or NaN testp. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 2.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "testp.notanumber.f32 isnan, f0;\ntestp.infinite.f64 p, X;", "description": "testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False.\ntestp.finite True if the input is not infinite or NaN testp.infinite True if the input is positive or negative infinity testp.number True if the input is not NaN testp.notanumber True if the input is NaN testp.normal True if the input is a normal number (not NaN, not infinity) testp.subnormal True if the input is a subnormal number (not NaN, not infinity)\nAs a special case, positive and negative zero are considered normal numbers.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#floating-point-instructions-testp", "introducedIn": "PTX ISA 2.0", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.tex", "mnemonic": "tex", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "tex", "category": "Texture Instructions", "summary": "tex.{1d,2d,3d} Texture lookup using a texture coordinate vector.", "syntax": "tex.geom.v4.dtype.ctype d, [a, c] {, e} {, f};", "syntax_forms": [ { "syntax": "tex.geom.v4.dtype.ctype d, [a, c] {, e} {, f};", "description": "tex.{1d,2d,3d}\nTexture lookup using a texture coordinate vector. The instruction loads data from the texture named\nby operand a at coordinates given by operand c into destination d. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "// Example of unified mode texturing\n // - f4 is required to pad four-element tuple and is ignored\n tex.3d.v4.s32.s32 {r1,r2,r3,r4}, [tex_a,{f1,f2,f3,f4}];\n\n // Example of independent mode texturing\n tex.1d.v4.s32.f32 {r1,r2,r3,r4}, [tex_a,smpl_x,{f1}];\n// (truncated - see the official PTX ISA docs for the full example)", "description": "tex.{1d,2d,3d}\nTexture lookup using a texture coordinate vector. The instruction loads data from the texture named\nby operand a at coordinates given by operand c into destination d. Operand c is a\nscalar or singleton tuple for 1d textures; is a two-element vector for 2d textures; and is a\nfour-element vector for 3d textures, where the fourth element is ignored. An optional texture\nsampler b may be specified. If no sampler is specified, the sampler behavior is a property of\nthe named texture. The optional destination predicate p is set to True if data from texture\nat specified coordinates is resident in memory, False otherwise. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#texture-instructions-tex", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.tld4", "mnemonic": "tld4", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "tld4", "category": "Texture Instructions", "summary": "Texture fetch of the 4-texel bilerp footprint using a texture coordinate vector.", "syntax": "tld4.comp.2d.v4.dtype.f32 d[|p], [a, c] {, e} {, f};", "syntax_forms": [ { "syntax": "tld4.comp.2d.v4.dtype.f32 d[|p], [a, c] {, e} {, f};", "description": "Texture fetch of the 4-texel bilerp footprint using a texture coordinate vector. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 2.2" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "//Example of unified mode texturing\ntld4.r.2d.v4.s32.f32 {r1,r2,r3,r4}, [tex_a,{f1,f2}];\n\n// Example of independent mode texturing\ntld4.r.2d.v4.u32.f32 {u1,u2,u3,u4}, [tex_a,smpl_x,{f1,f2}];\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Texture fetch of the 4-texel bilerp footprint using a texture coordinate vector. The instruction\nloads the bilerp footprint from the texture named by operand a at coordinates given by operand c into vector destination d. The texture component fetched for each texel sample is\nspecified by.comp. The four texel samples are placed into destination vector d in\ncounter-clockwise order starting at lower left.\nAn optional texture sampler b may be specified. If no sampler is specified, the sampler behavior\nis a property of the named texture.\nThe optional destination predicate p is set to True if data from texture at specified\ncoordinates is resident in memory, False otherwise. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#texture-instructions-tld4", "introducedIn": "PTX ISA 2.2", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.trap", "mnemonic": "trap", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "trap", "category": "Miscellaneous Instructions", "summary": "Abort execution and generate an interrupt to the host CPU.", "syntax": "trap;", "syntax_forms": [ { "syntax": "trap;", "description": "Abort execution and generate an interrupt to the host CPU.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "trap;\n@p trap;", "description": "Abort execution and generate an interrupt to the host CPU.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#miscellaneous-instructions-trap", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.txq", "mnemonic": "txq", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "txq", "category": "Texture Instructions", "summary": "Query an attribute of a texture or sampler.", "syntax": "txq.tquery.b32 d, [a]; // texture attributes", "syntax_forms": [ { "syntax": "txq.tquery.b32 d, [a]; // texture attributes", "description": "Query an attribute of a texture or sampler. Operand a is either a.texref or.samplerref variable, or a.u64 register.\nQuery Returns.width.height.depth value in elements. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 1.5" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "txq.width.b32 %r1, [tex_A];\ntxq.filter_mode.b32 %r1, [tex_A]; // unified mode\ntxq.addr_mode_0.b32 %r1, [smpl_B]; // independent mode\ntxq.level.width.b32 %r1, [tex_A], %r_lod;", "description": "Query an attribute of a texture or sampler. Operand a is either a.texref or.samplerref variable, or a.u64 register.\nQuery Returns.width.height.depth value in elements.channel_data_type Unsigned integer corresponding to source language’s channel data type\nenumeration. If the source language combines channel data type and channel\norder into a single enumeration type, that value is returned for both channel_data_type and channel_order queries..channel_order Unsigned integer corresponding to source language’s channel order\nenumeration. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#texture-instructions-txq", "introducedIn": "PTX ISA 1.5", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.vadd", "mnemonic": "vadd", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "vadd", "category": "Scalar Video Instructions", "summary": "Perform scalar arithmetic operation with optional saturate, and optional secondary arithmetic operation or subword data merge.", "syntax": "// 32-bit scalar operation, with optional secondary operation\nvadd.dtype.atype.btype{.sat} d, a{.asel}, b{.bsel};", "syntax_forms": [ { "syntax": "// 32-bit scalar operation, with optional secondary operation\nvadd.dtype.atype.btype{.sat} d, a{.asel}, b{.bsel};", "description": "Perform scalar arithmetic operation with optional saturate, and optional secondary arithmetic operation or subword data merge.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 2.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": "// extract byte/half-word/word and sign- or zero-extend\n// based on source operand type\nta = partSelectSignExtend( a, atype, asel );\ntb = partSelectSignExtend( b, btype, bsel );\n\nswitch ( vop ) {\n case vadd: tmp = ta + tb;\n case vsub: tmp = ta - tb;\n case vabsdiff: tmp = | ta - tb |;\n case vmin: tmp = MIN( ta, tb );\n case vmax: tmp = MAX( ta, tb );\n}\n// saturate, taking into account destination type and merge operations\ntmp = optSaturate( tmp, sat, isSigned(dtype), dsel );\nd = optSecondaryOp( op2, tmp, c ); // optional secondary operation\nd = optMerge( dsel, tmp, c ); // optional merge with c operand", "examples": "vadd.s32.u32.s32.sat r1, r2.b0, r3.h0;\nvsub.s32.s32.u32.sat r1, r2.h1, r3.h1;\nvabsdiff.s32.s32.s32.sat r1.h0, r2.b0, r3.b2, c;\nvmin.s32.s32.s32.sat.add r1, r2, r3, c;", "description": "Perform scalar arithmetic operation with optional saturate, and optional secondary arithmetic operation or subword data merge.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#scalar-video-instructions-vadd-vsub-vabsdiff-vmin-vmax", "introducedIn": "PTX ISA 2.0", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.vadd2", "mnemonic": "vadd2", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "vadd2", "category": "SIMD Video Instructions", "summary": "Two-way SIMD parallel arithmetic operation with secondary operation.", "syntax": "// SIMD instruction with secondary SIMD merge operation\nvadd2.dtype.atype.btype{.sat} d{.mask}, a{.asel}, b{.bsel}, c;", "syntax_forms": [ { "syntax": "// SIMD instruction with secondary SIMD merge operation\nvadd2.dtype.atype.btype{.sat} d{.mask}, a{.asel}, b{.bsel}, c;", "description": "Two-way SIMD parallel arithmetic operation with secondary operation. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_30" ], "introducedIn": "PTX ISA 3.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": "// extract pairs of half-words and sign- or zero-extend\n// based on operand type\nVa = extractAndSignExt_2( a, b, .asel, .atype );\nVb = extractAndSignExt_2( a, b, .bsel, .btype );\nVc = extractAndSignExt_2( c );\n\nfor (i=0; i<2; i++) {\n switch ( vop2 ) {\n case vadd2: t[i] = Va[i] + Vb[i];\n case vsub2: t[i] = Va[i] - Vb[i];\n case vavrg2: if ( ( Va[i] + Vb[i] ) >= 0 ) {\n t[i] = ( Va[i] + Vb[i] + 1 ) >> 1;\n } else {\n t[i] = ( Va[i] + Vb[i] ) >> 1;\n }\n case vabsdiff2: t[i] = | Va[i] - Vb[i] |;\n case vmin2: t[i] = MIN( Va[i], Vb[i] );\n case vmax2: t[i] = MAX( Va[i], Vb[i] );\n }\n if (.sat) {\n if ( .dtype == .s32 ) t[i] = CLAMP( t[i], S16_MAX, S16_MIN ); (see the official PTX ISA docs for the full semantics)", "examples": "vadd2.s32.s32.u32.sat r1, r2, r3, r1;\nvsub2.s32.s32.s32.sat r1.h0, r2.h10, r3.h32, r1;\nvmin2.s32.u32.u32.add r1.h10, r2.h00, r3.h22, r1;", "description": "Two-way SIMD parallel arithmetic operation with secondary operation.\nElements of each dual half-word source to the operation are selected from any of the four half-words\nin the two source operands a and b using the asel and bsel modifiers.\nThe selected half-words are then operated on in parallel.\nThe results are optionally clamped to the appropriate range determined by the destination type\n(signed or unsigned). Saturation cannot be used with the secondary accumulate operation.\nFor instructions with a secondary SIMD merge operation:\nFor half-word positions indicated in mask, the selected half-word results are copied into\ndestination d. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#simd-video-instructions-vadd2-vsub2-vavrg2-vabsdiff2-vmin2-vmax2", "introducedIn": "PTX ISA 3.0", "requiredTargets": [ "sm_30" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.vadd4", "mnemonic": "vadd4", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "vadd4", "category": "SIMD Video Instructions", "summary": "Four-way SIMD parallel arithmetic operation with secondary operation.", "syntax": "// SIMD instruction with secondary SIMD merge operation\nvadd4.dtype.atype.btype{.sat} d{.mask}, a{.asel}, b{.bsel}, c;", "syntax_forms": [ { "syntax": "// SIMD instruction with secondary SIMD merge operation\nvadd4.dtype.atype.btype{.sat} d{.mask}, a{.asel}, b{.bsel}, c;", "description": "Four-way SIMD parallel arithmetic operation with secondary operation. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_30" ], "introducedIn": "PTX ISA 3.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": "// extract quads of bytes and sign- or zero-extend\n// based on operand type\nVa = extractAndSignExt_4( a, b, .asel, .atype );\nVb = extractAndSignExt_4( a, b, .bsel, .btype );\nVc = extractAndSignExt_4( c );\nfor (i=0; i<4; i++) {\n switch ( vop4 ) {\n case vadd4: t[i] = Va[i] + Vb[i];\n case vsub4: t[i] = Va[i] - Vb[i];\n case vavrg4: if ( ( Va[i] + Vb[i] ) >= 0 ) {\n t[i] = ( Va[i] + Vb[i] + 1 ) >> 1;\n } else {\n t[i] = ( Va[i] + Vb[i] ) >> 1;\n }\n case vabsdiff4: t[i] = | Va[i] - Vb[i] |;\n case vmin4: t[i] = MIN( Va[i], Vb[i] );\n case vmax4: t[i] = MAX( Va[i], Vb[i] );\n }\n if (.sat) {\n if ( .dtype == .s32 ) t[i] = CLAMP( t[i], S8_MAX, S8_MIN ); (see the official PTX ISA docs for the full semantics)", "examples": "vadd4.s32.s32.u32.sat r1, r2, r3, r1;\nvsub4.s32.s32.s32.sat r1.b0, r2.b3210, r3.b7654, r1;\nvmin4.s32.u32.u32.add r1.b00, r2.b0000, r3.b2222, r1;", "description": "Four-way SIMD parallel arithmetic operation with secondary operation.\nElements of each quad byte source to the operation are selected from any of the eight bytes in the\ntwo source operands a and b using the asel and bsel modifiers.\nThe selected bytes are then operated on in parallel.\nThe results are optionally clamped to the appropriate range determined by the destination type\n(signed or unsigned). Saturation cannot be used with the secondary accumulate operation.\nFor instructions with a secondary SIMD merge operation:\nFor byte positions indicated in mask, the selected byte results are copied into destination d. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#simd-video-instructions-vadd4-vsub4-vavrg4-vabsdiff4-vmin4-vmax4", "introducedIn": "PTX ISA 3.0", "requiredTargets": [ "sm_30" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.vmad", "mnemonic": "vmad", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "vmad", "category": "Scalar Video Instructions", "summary": "Calculate (a*b) + c, with optional operand negates, plus one mode, and scaling.\nThe source operands support optional negation with some restrictions.", "syntax": "// 32-bit scalar operation\nvmad.dtype.atype.btype{.sat}{.scale} d, {-}a{.asel}, {-}b{.bsel},\n{-}c;", "syntax_forms": [ { "syntax": "// 32-bit scalar operation\nvmad.dtype.atype.btype{.sat}{.scale} d, {-}a{.asel}, {-}b{.bsel},\n{-}c;", "description": "Calculate (a*b) + c, with optional operand negates, plus one mode, and scaling.\nThe source operands support optional negation with some restrictions. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 2.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": "// extract byte/half-word/word and sign- or zero-extend\n// based on source operand type\nta = partSelectSignExtend( a, atype, asel );\ntb = partSelectSignExtend( b, btype, bsel );\nsignedFinal = isSigned(atype) || isSigned(btype) ||\n (a.negate ^ b.negate) || c.negate;\ntmp[127:0] = ta * tb;\n\nlsb = 0;\nif ( .po ) { lsb = 1; } else\nif ( a.negate ^ b.negate ) { tmp = ~tmp; lsb = 1; } else\nif ( c.negate ) { c = ~c; lsb = 1; }\n\nc128[127:0] = (signedFinal) sext32( c ) : zext ( c );\ntmp = tmp + c128 + lsb;\nswitch( scale ) {\n case .shr7: result = (tmp >> 7) & 0xffffffffffffffff;\n case .shr15: result = (tmp >> 15) & 0xffffffffffffffff;\n}\nif ( .sat ) {\n if (signedFinal) result = CLAMP(result, S32_MAX, S32_MIN);\n else result = CLAMP(result, U32_MAX, U32_MIN);\n}", "examples": "vmad.s32.s32.u32.sat r0, r1, r2, -r3;\nvmad.u32.u32.u32.shr15 r0, r1.h0, r2.h0, r3;", "description": "Calculate (a*b) + c, with optional operand negates, plus one mode, and scaling.\nThe source operands support optional negation with some restrictions. Although PTX syntax allows\nseparate negation of the a and b operands, internally this is represented as negation of the\nproduct (a*b). That is, (a*b) is negated if and only if exactly one of a or b is\nnegated. PTX allows negation of either (a*b) or c.\nThe plus one mode (.po ) computes (a*b) + c + 1, which is used in computing averages. Source\noperands may not be negated in.po mode.\nThe intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated; otherwise, the intermediate result is signed. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#scalar-video-instructions-vmad", "introducedIn": "PTX ISA 2.0", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.vote", "mnemonic": "vote", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Vote", "category": "Parallel Synchronization and Communication Instructions", "summary": "Combine a per-lane predicate across the warp using any/all/ballot reduction.", "syntax": "vote.mode.pred d, {!}a;", "syntax_forms": [ { "syntax": "vote.mode.pred d, {!}a;", "description": "Reduce predicate a across the warp: any true, all true, or all-lanes-agree.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [ "any", "all", "uni" ], "requiredTargets": [ "sm_12" ], "introducedIn": "PTX ISA 6.0" }, { "syntax": "vote.ballot.b32 d, {!}a;", "description": "Collect per-lane predicate a into a 32-bit bitmask, one bit per lane.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [ "ballot" ], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 2.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [ "all", "any", "ballot", "uni" ], "operands": [ { "name": "d", "desc": "Destination register or predicate" }, { "name": "a", "desc": "Per-lane predicate operand" } ], "semantics": "d = reduction of predicate a across the active lanes of the warp, per the selected mode.", "examples": "vote.sync.all.pred p,q,0xffffffff;\nvote.sync.ballot.b32 r1,p,0xffffffff; // get 'ballot' across warp", "description": "vote.sync will cause executing thread to wait until all non-exited threads corresponding to membermask have executed vote.sync with the same qualifiers and same membermask value\nbefore resuming execution.\nOperand membermask specifies a 32-bit integer which is a mask indicating threads participating\nin this instruction where the bit position corresponds to thread’s laneid. Operand a is a\npredicate register.\nIn the mode form, vote.sync performs a reduction of the source predicate across all non-exited\nthreads in membermask. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-vote-sync", "introducedIn": "PTX ISA 6.0", "requiredTargets": [ "sm_12" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.vset", "mnemonic": "vset", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "vset", "category": "Scalar Video Instructions", "summary": "Compare input values using specified comparison, with optional secondary arithmetic operation or subword data merge.", "syntax": "// 32-bit scalar operation, with optional secondary operation\nvset.atype.btype.cmp d, a{.asel}, b{.bsel};", "syntax_forms": [ { "syntax": "// 32-bit scalar operation, with optional secondary operation\nvset.atype.btype.cmp d, a{.asel}, b{.bsel};", "description": "Compare input values using specified comparison, with optional secondary arithmetic operation or\nsubword data merge. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 2.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": "// extract byte/half-word/word and sign- or zero-extend\n// based on source operand type\nta = partSelectSignExtend( a, atype, asel );\ntb = partSelectSignExtend( b, btype, bsel );\ntmp = compare( ta, tb, cmp ) ? 1 : 0;\nd = optSecondaryOp( op2, tmp, c ); // optional secondary operation\nd = optMerge( dsel, tmp, c ); // optional merge with c operand", "examples": "vset.s32.u32.lt r1, r2, r3;\nvset.u32.u32.ne r1, r2, r3.h1;", "description": "Compare input values using specified comparison, with optional secondary arithmetic operation or\nsubword data merge.\nThe intermediate result of the comparison is always unsigned, and therefore destination d and\noperand c are also unsigned.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#scalar-video-instructions-vset", "introducedIn": "PTX ISA 2.0", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.vset2", "mnemonic": "vset2", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "vset2", "category": "SIMD Video Instructions", "summary": "Two-way SIMD parallel comparison with secondary operation.", "syntax": "// SIMD instruction with secondary SIMD merge operation\nvset2.atype.btype.cmp d{.mask}, a{.asel}, b{.bsel}, c;", "syntax_forms": [ { "syntax": "// SIMD instruction with secondary SIMD merge operation\nvset2.atype.btype.cmp d{.mask}, a{.asel}, b{.bsel}, c;", "description": "Two-way SIMD parallel comparison with secondary operation. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_30" ], "introducedIn": "PTX ISA 3.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": "// extract pairs of half-words and sign- or zero-extend\n// based on operand type\nVa = extractAndSignExt_2( a, b, .asel, .atype );\nVb = extractAndSignExt_2( a, b, .bsel, .btype );\nVc = extractAndSignExt_2( c );\nfor (i=0; i<2; i++) {\n t[i] = compare( Va[i], Vb[i], .cmp ) ? 1 : 0;\n}\n// secondary accumulate or SIMD merge\nmask = extractMaskBits( .mask );\nif (.add) {\n d = c;\n for (i=0; i<2; i++) { d += mask[i] ? t[i] : 0; }\n} else {\n d = 0;\n for (i=0; i<2; i++) { d |= mask[i] ? t[i] : Vc[i]; }\n}", "examples": "vset2.s32.u32.lt r1, r2, r3, r0;\nvset2.u32.u32.ne.add r1, r2, r3, r0;", "description": "Two-way SIMD parallel comparison with secondary operation.\nElements of each dual half-word source to the operation are selected from any of the four half-words\nin the two source operands a and b using the asel and bsel modifiers.\nThe selected half-words are then compared in parallel.\nThe intermediate result of the comparison is always unsigned, and therefore the half-words of\ndestination d and operand c are also unsigned.\nFor instructions with a secondary SIMD merge operation:\nFor half-word positions indicated in mask, the selected half-word results are copied into\ndestination d. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#simd-video-instructions-vset2", "introducedIn": "PTX ISA 3.0", "requiredTargets": [ "sm_30" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.vset4", "mnemonic": "vset4", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "vset4", "category": "SIMD Video Instructions", "summary": "Four-way SIMD parallel comparison with secondary operation.", "syntax": "// SIMD instruction with secondary SIMD merge operation\nvset4.atype.btype.cmp d{.mask}, a{.asel}, b{.bsel}, c;", "syntax_forms": [ { "syntax": "// SIMD instruction with secondary SIMD merge operation\nvset4.atype.btype.cmp d{.mask}, a{.asel}, b{.bsel}, c;", "description": "Four-way SIMD parallel comparison with secondary operation. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_30" ], "introducedIn": "PTX ISA 3.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": "// extract quads of bytes and sign- or zero-extend\n// based on operand type\nVa = extractAndSignExt_4( a, b, .asel, .atype );\nVb = extractAndSignExt_4( a, b, .bsel, .btype );\nVc = extractAndSignExt_4( c );\nfor (i=0; i<4; i++) {\n t[i] = compare( Va[i], Vb[i], cmp ) ? 1 : 0;\n}\n// secondary accumulate or SIMD merge\nmask = extractMaskBits( .mask );\nif (.add) {\n d = c;\n for (i=0; i<4; i++) { d += mask[i] ? t[i] : 0; }\n} else {\n d = 0;\n for (i=0; i<4; i++) { d |= mask[i] ? t[i] : Vc[i]; }\n}", "examples": "vset4.s32.u32.lt r1, r2, r3, r0;\nvset4.u32.u32.ne.max r1, r2, r3, r0;", "description": "Four-way SIMD parallel comparison with secondary operation.\nElements of each quad byte source to the operation are selected from any of the eight bytes in the\ntwo source operands a and b using the asel and bsel modifiers.\nThe selected bytes are then compared in parallel.\nThe intermediate result of the comparison is always unsigned, and therefore the bytes of destination d and operand c are also unsigned.\nFor instructions with a secondary SIMD merge operation:\nFor byte positions indicated in mask, the selected byte results are copied into destination d. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#simd-video-instructions-vset4", "introducedIn": "PTX ISA 3.0", "requiredTargets": [ "sm_30" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.vshl", "mnemonic": "vshl", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "vshl", "category": "Scalar Video Instructions", "summary": "vshl Shift a left by unsigned amount in b with optional saturate, and optional secondary arithmetic operation or subword data merge.", "syntax": "// 32-bit scalar operation, with optional secondary operation\nvshl.dtype.atype.u32{.sat}.mode d, a{.asel}, b{.bsel};", "syntax_forms": [ { "syntax": "// 32-bit scalar operation, with optional secondary operation\nvshl.dtype.atype.u32{.sat}.mode d, a{.asel}, b{.bsel};", "description": "vshl Shift a left by unsigned amount in b with optional saturate, and optional secondary\narithmetic operation or subword data merge. Left shift fills with zero. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 2.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": "// extract byte/half-word/word and sign- or zero-extend\n// based on source operand type\nta = partSelectSignExtend( a,atype, asel );\ntb = partSelectSignExtend( b, .u32, bsel );\nif ( mode == .clamp && tb > 32 ) tb = 32;\nif ( mode == .wrap ) tb = tb & 0x1f;\nswitch ( vop ){\n case vshl: tmp = ta << tb;\n case vshr: tmp = ta >> tb;\n}\n// saturate, taking into account destination type and merge operations\ntmp = optSaturate( tmp, sat, isSigned(dtype), dsel );\nd = optSecondaryOp( op2, tmp, c ); // optional secondary operation\nd = optMerge( dsel, tmp, c ); // optional merge with c operand", "examples": "vshl.s32.u32.u32.clamp r1, r2, r3;\nvshr.u32.u32.u32.wrap r1, r2, r3.h1;", "description": "vshl Shift a left by unsigned amount in b with optional saturate, and optional secondary\narithmetic operation or subword data merge. Left shift fills with zero. vshr Shift a right by unsigned amount in b with optional saturate, and optional secondary\narithmetic operation or subword data merge. Signed shift fills with the sign bit, unsigned shift\nfills with zero.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#scalar-video-instructions-vshl-vshr", "introducedIn": "PTX ISA 2.0", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.vshr", "mnemonic": "vshr", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "vshr", "category": "Scalar Video Instructions", "summary": "vshl Shift a left by unsigned amount in b with optional saturate, and optional secondary arithmetic operation or subword data merge.", "syntax": "// 32-bit scalar operation, with optional secondary operation\nvshr.dtype.atype.u32{.sat}.mode d, a{.asel}, b{.bsel};", "syntax_forms": [ { "syntax": "// 32-bit scalar operation, with optional secondary operation\nvshr.dtype.atype.u32{.sat}.mode d, a{.asel}, b{.bsel};", "description": "vshl Shift a left by unsigned amount in b with optional saturate, and optional secondary\narithmetic operation or subword data merge. Left shift fills with zero. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 2.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": "// extract byte/half-word/word and sign- or zero-extend\n// based on source operand type\nta = partSelectSignExtend( a,atype, asel );\ntb = partSelectSignExtend( b, .u32, bsel );\nif ( mode == .clamp && tb > 32 ) tb = 32;\nif ( mode == .wrap ) tb = tb & 0x1f;\nswitch ( vop ){\n case vshl: tmp = ta << tb;\n case vshr: tmp = ta >> tb;\n}\n// saturate, taking into account destination type and merge operations\ntmp = optSaturate( tmp, sat, isSigned(dtype), dsel );\nd = optSecondaryOp( op2, tmp, c ); // optional secondary operation\nd = optMerge( dsel, tmp, c ); // optional merge with c operand", "examples": "vshl.s32.u32.u32.clamp r1, r2, r3;\nvshr.u32.u32.u32.wrap r1, r2, r3.h1;", "description": "vshl Shift a left by unsigned amount in b with optional saturate, and optional secondary\narithmetic operation or subword data merge. Left shift fills with zero. vshr Shift a right by unsigned amount in b with optional saturate, and optional secondary\narithmetic operation or subword data merge. Signed shift fills with the sign bit, unsigned shift\nfills with zero.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#scalar-video-instructions-vshl-vshr", "introducedIn": "PTX ISA 2.0", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.vsub", "mnemonic": "vsub", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "vsub", "category": "Scalar Video Instructions", "summary": "Perform scalar arithmetic operation with optional saturate, and optional secondary arithmetic operation or subword data merge.", "syntax": "// 32-bit scalar operation, with optional secondary operation\nvsub.dtype.atype.btype{.sat} d, a{.asel}, b{.bsel};", "syntax_forms": [ { "syntax": "// 32-bit scalar operation, with optional secondary operation\nvsub.dtype.atype.btype{.sat} d, a{.asel}, b{.bsel};", "description": "Perform scalar arithmetic operation with optional saturate, and optional secondary arithmetic operation or subword data merge.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_20" ], "introducedIn": "PTX ISA 2.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": "// extract byte/half-word/word and sign- or zero-extend\n// based on source operand type\nta = partSelectSignExtend( a, atype, asel );\ntb = partSelectSignExtend( b, btype, bsel );\n\nswitch ( vop ) {\n case vadd: tmp = ta + tb;\n case vsub: tmp = ta - tb;\n case vabsdiff: tmp = | ta - tb |;\n case vmin: tmp = MIN( ta, tb );\n case vmax: tmp = MAX( ta, tb );\n}\n// saturate, taking into account destination type and merge operations\ntmp = optSaturate( tmp, sat, isSigned(dtype), dsel );\nd = optSecondaryOp( op2, tmp, c ); // optional secondary operation\nd = optMerge( dsel, tmp, c ); // optional merge with c operand", "examples": "vadd.s32.u32.s32.sat r1, r2.b0, r3.h0;\nvsub.s32.s32.u32.sat r1, r2.h1, r3.h1;\nvabsdiff.s32.s32.s32.sat r1.h0, r2.b0, r3.b2, c;\nvmin.s32.s32.s32.sat.add r1, r2, r3, c;", "description": "Perform scalar arithmetic operation with optional saturate, and optional secondary arithmetic operation or subword data merge.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#scalar-video-instructions-vadd-vsub-vabsdiff-vmin-vmax", "introducedIn": "PTX ISA 2.0", "requiredTargets": [ "sm_20" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.vsub2", "mnemonic": "vsub2", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "vsub2", "category": "SIMD Video Instructions", "summary": "Two-way SIMD parallel arithmetic operation with secondary operation.", "syntax": "// SIMD instruction with secondary SIMD merge operation\nvsub2.dtype.atype.btype{.sat} d{.mask}, a{.asel}, b{.bsel}, c;", "syntax_forms": [ { "syntax": "// SIMD instruction with secondary SIMD merge operation\nvsub2.dtype.atype.btype{.sat} d{.mask}, a{.asel}, b{.bsel}, c;", "description": "Two-way SIMD parallel arithmetic operation with secondary operation. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_30" ], "introducedIn": "PTX ISA 3.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": "// extract pairs of half-words and sign- or zero-extend\n// based on operand type\nVa = extractAndSignExt_2( a, b, .asel, .atype );\nVb = extractAndSignExt_2( a, b, .bsel, .btype );\nVc = extractAndSignExt_2( c );\n\nfor (i=0; i<2; i++) {\n switch ( vop2 ) {\n case vadd2: t[i] = Va[i] + Vb[i];\n case vsub2: t[i] = Va[i] - Vb[i];\n case vavrg2: if ( ( Va[i] + Vb[i] ) >= 0 ) {\n t[i] = ( Va[i] + Vb[i] + 1 ) >> 1;\n } else {\n t[i] = ( Va[i] + Vb[i] ) >> 1;\n }\n case vabsdiff2: t[i] = | Va[i] - Vb[i] |;\n case vmin2: t[i] = MIN( Va[i], Vb[i] );\n case vmax2: t[i] = MAX( Va[i], Vb[i] );\n }\n if (.sat) {\n if ( .dtype == .s32 ) t[i] = CLAMP( t[i], S16_MAX, S16_MIN ); (see the official PTX ISA docs for the full semantics)", "examples": "vadd2.s32.s32.u32.sat r1, r2, r3, r1;\nvsub2.s32.s32.s32.sat r1.h0, r2.h10, r3.h32, r1;\nvmin2.s32.u32.u32.add r1.h10, r2.h00, r3.h22, r1;", "description": "Two-way SIMD parallel arithmetic operation with secondary operation.\nElements of each dual half-word source to the operation are selected from any of the four half-words\nin the two source operands a and b using the asel and bsel modifiers.\nThe selected half-words are then operated on in parallel.\nThe results are optionally clamped to the appropriate range determined by the destination type\n(signed or unsigned). Saturation cannot be used with the secondary accumulate operation.\nFor instructions with a secondary SIMD merge operation:\nFor half-word positions indicated in mask, the selected half-word results are copied into\ndestination d. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#simd-video-instructions-vadd2-vsub2-vavrg2-vabsdiff2-vmin2-vmax2", "introducedIn": "PTX ISA 3.0", "requiredTargets": [ "sm_30" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.vsub4", "mnemonic": "vsub4", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "vsub4", "category": "SIMD Video Instructions", "summary": "Four-way SIMD parallel arithmetic operation with secondary operation.", "syntax": "// SIMD instruction with secondary SIMD merge operation\nvsub4.dtype.atype.btype{.sat} d{.mask}, a{.asel}, b{.bsel}, c;", "syntax_forms": [ { "syntax": "// SIMD instruction with secondary SIMD merge operation\nvsub4.dtype.atype.btype{.sat} d{.mask}, a{.asel}, b{.bsel}, c;", "description": "Four-way SIMD parallel arithmetic operation with secondary operation. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_30" ], "introducedIn": "PTX ISA 3.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": "// extract quads of bytes and sign- or zero-extend\n// based on operand type\nVa = extractAndSignExt_4( a, b, .asel, .atype );\nVb = extractAndSignExt_4( a, b, .bsel, .btype );\nVc = extractAndSignExt_4( c );\nfor (i=0; i<4; i++) {\n switch ( vop4 ) {\n case vadd4: t[i] = Va[i] + Vb[i];\n case vsub4: t[i] = Va[i] - Vb[i];\n case vavrg4: if ( ( Va[i] + Vb[i] ) >= 0 ) {\n t[i] = ( Va[i] + Vb[i] + 1 ) >> 1;\n } else {\n t[i] = ( Va[i] + Vb[i] ) >> 1;\n }\n case vabsdiff4: t[i] = | Va[i] - Vb[i] |;\n case vmin4: t[i] = MIN( Va[i], Vb[i] );\n case vmax4: t[i] = MAX( Va[i], Vb[i] );\n }\n if (.sat) {\n if ( .dtype == .s32 ) t[i] = CLAMP( t[i], S8_MAX, S8_MIN ); (see the official PTX ISA docs for the full semantics)", "examples": "vadd4.s32.s32.u32.sat r1, r2, r3, r1;\nvsub4.s32.s32.s32.sat r1.b0, r2.b3210, r3.b7654, r1;\nvmin4.s32.u32.u32.add r1.b00, r2.b0000, r3.b2222, r1;", "description": "Four-way SIMD parallel arithmetic operation with secondary operation.\nElements of each quad byte source to the operation are selected from any of the eight bytes in the\ntwo source operands a and b using the asel and bsel modifiers.\nThe selected bytes are then operated on in parallel.\nThe results are optionally clamped to the appropriate range determined by the destination type\n(signed or unsigned). Saturation cannot be used with the secondary accumulate operation.\nFor instructions with a secondary SIMD merge operation:\nFor byte positions indicated in mask, the selected byte results are copied into destination d. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#simd-video-instructions-vadd4-vsub4-vavrg4-vabsdiff4-vmin4-vmax4", "introducedIn": "PTX ISA 3.0", "requiredTargets": [ "sm_30" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.wgmma.commit_group", "mnemonic": "wgmma.commit_group", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "wgmma.commit_group", "category": "Asynchronous Warpgroup Level Matrix Multiply-Accumulate Instructions", "summary": "wgmma.commit_group instruction creates a new wgmma-group per warpgroup and batches all prior wgmma.mma_async instructions initiated by the executing warp but not committed to any wgmma-group into the new wgmma-group.", "syntax": "wgmma.commit_group.sync.aligned;", "syntax_forms": [ { "syntax": "wgmma.commit_group.sync.aligned;", "description": "wgmma.commit_group instruction creates a new wgmma-group per warpgroup and batches all prior wgmma. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_90a" ], "introducedIn": "PTX ISA 8.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "wgmma.commit_group.sync.aligned;", "description": "wgmma.commit_group instruction creates a new wgmma-group per warpgroup and batches all prior wgmma.mma_async instructions initiated by the executing warp but not committed to any\nwgmma-group into the new wgmma-group. If there are no uncommitted wgmma.mma_async instructions\nthen wgmma.commit_group results in an empty wgmma-group.\nAn executing thread can wait for the completion of all wgmma.mma_async operations in a\nwgmma-group by using wgmma.wait_group.\nThe mandatory.sync qualifier indicates that wgmma.commit_group instruction causes the\nexecuting thread to wait until all threads in the warp execute the same wgmma.commit_group instruction before resuming execution.\nThe mandatory. (see the official PTX ISA docs for the full description)", "sourceUrl": null, "introducedIn": "PTX ISA 8.0", "requiredTargets": [ "sm_90a" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.wgmma.fence", "mnemonic": "wgmma.fence", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "wgmma.fence", "category": "Asynchronous Warpgroup Level Matrix Multiply-Accumulate Instructions", "summary": "wgmma.fence instruction establishes an ordering between prior accesses to any warpgroup registers and subsequent accesses to the same registers by a wgmma.mma_async instruction.", "syntax": "wgmma.fence.sync.aligned;", "syntax_forms": [ { "syntax": "wgmma.fence.sync.aligned;", "description": "wgmma.fence instruction establishes an ordering between prior accesses to any warpgroup\nregisters and subsequent accesses to the same registers by a wgmma.mma_async instruction. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_90a" ], "introducedIn": "PTX ISA 8.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [], "semantics": null, "examples": "// Example 1, first use example:\nwgmma.fence.sync.aligned; // Establishes an ordering w.r.t. prior accesses to the registers s32d<0-3>\nwgmma.mma_async.sync.aligned.m64n8k32.s32.u8.u8 {s32d0, s32d1, s32d2, s32d3},\n descA, descB, scaleD;\nwgmma.commit_group.sync.aligned;\nwgmma.wait_group.sync.aligned 0;\n// (truncated - see the official PTX ISA docs for the full example)", "description": "wgmma.fence instruction establishes an ordering between prior accesses to any warpgroup\nregisters and subsequent accesses to the same registers by a wgmma.mma_async instruction. Only\nthe accumulator register and the input registers containing the fragments of matrix A require this\nordering.\nThe wgmma.fence instruction must be issued by all warps of the warpgroup at the following\nlocations:\nBefore the first wgmma.mma_async operation in a warpgroup. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#asynchronous-warpgroup-level-matrix-instructions-wgmma-fence", "introducedIn": "PTX ISA 8.0", "requiredTargets": [ "sm_90a" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.wgmma.mma_async", "mnemonic": "wgmma.mma_async", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "wgmma.mma_async", "category": "Asynchronous Warpgroup Level Matrix Multiply-Accumulate Instructions", "summary": "Instruction wgmma.mma_async issues a MxNxK matrix multiply and accumulate operation, D = A*B+D, where the A matrix is MxK, the B matrix is KxN, and the D matrix is MxN.", "syntax": "wgmma.mma_async.sync.aligned.shape.dtype.f16.f16 d, a-desc, b-desc, scale-d, imm-scale-a, imm-scale-b, imm-trans-a, imm-trans-b;", "syntax_forms": [ { "syntax": "wgmma.mma_async.sync.aligned.shape.dtype.f16.f16 d, a-desc, b-desc, scale-d, imm-scale-a, imm-scale-b, imm-trans-a, imm-trans-b;", "description": "Instruction wgmma.mma_async issues a MxNxK matrix multiply and accumulate operation, D = A*B+D, where the A matrix is MxK, the B matrix is KxN, and the D matrix is MxN.\nThe operation of the form D = A (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_90a" ], "introducedIn": "PTX ISA 8.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a-desc", "desc": "Operand" }, { "name": "b-desc", "desc": "Operand" }, { "name": "scale-d", "desc": "Operand" }, { "name": "imm-scale-a", "desc": "Operand" }, { "name": "imm-scale-b", "desc": "Operand" }, { "name": "imm-trans-a", "desc": "Operand" }, { "name": "imm-trans-b", "desc": "Operand" } ], "semantics": null, "examples": null, "description": "Instruction wgmma.mma_async issues a MxNxK matrix multiply and accumulate operation, D = A*B+D, where the A matrix is MxK, the B matrix is KxN, and the D matrix is MxN.\nThe operation of the form D = A*B is issued when the input predicate argument scale-d is\nfalse.\nwgmma.fence instruction must be used to fence the register accesses of wgmma.mma_async instruction from their prior accesses. (see the official PTX ISA docs for the full description)", "sourceUrl": null, "introducedIn": "PTX ISA 8.0", "requiredTargets": [ "sm_90a" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.wgmma.mma_async.sp", "mnemonic": "wgmma.mma_async.sp", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "wgmma.mma_async.sp", "category": "Asynchronous Warpgroup Level Matrix Multiply-Accumulate Instructions", "summary": "Instruction wgmma.mma_async issues a MxNxK matrix multiply and accumulate operation, D = A*B+D, where the A matrix is MxK, the B matrix is KxN, and the D matrix is MxN.", "syntax": "wgmma.mma_async.sp.sync.aligned.shape.dtype.f16.f16 d, a-desc, b-desc, sp-meta, sp-sel, scale-d, imm-scale-a, imm-scale-b, imm-trans-a, imm-trans-b;", "syntax_forms": [ { "syntax": "wgmma.mma_async.sp.sync.aligned.shape.dtype.f16.f16 d, a-desc, b-desc, sp-meta, sp-sel, scale-d, imm-scale-a, imm-scale-b, imm-trans-a, imm-trans-b;", "description": "Instruction wgmma.mma_async issues a MxNxK matrix multiply and accumulate operation, D = A*B+D, where the A matrix is MxK, the B matrix is KxN, and the D matrix is MxN. (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_90a" ], "introducedIn": "PTX ISA 8.2" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a-desc", "desc": "Operand" }, { "name": "b-desc", "desc": "Operand" }, { "name": "sp-meta", "desc": "Operand" }, { "name": "sp-sel", "desc": "Operand" }, { "name": "scale-d", "desc": "Operand" }, { "name": "imm-scale-a", "desc": "Operand" }, { "name": "imm-scale-b", "desc": "Operand" }, { "name": "imm-trans-a", "desc": "Operand" }, { "name": "imm-trans-b", "desc": "Operand" } ], "semantics": null, "examples": null, "description": "Instruction wgmma.mma_async issues a MxNxK matrix multiply and accumulate operation, D = A*B+D, where the A matrix is MxK, the B matrix is KxN, and the D matrix is MxN.\nThe matrix A is stored in the packed format Mx(K/2) as described in Sparse matrix storage.\nThe operation of the form D = A*B is issued when the input predicate argument scale-d is\nfalse.\nwgmma.fence instruction must be used to fence the register accesses of wgmma.mma_async instruction from their prior accesses. (see the official PTX ISA docs for the full description)", "sourceUrl": null, "introducedIn": "PTX ISA 8.2", "requiredTargets": [ "sm_90a" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.wgmma.wait_group", "mnemonic": "wgmma.wait_group", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "wgmma.wait_group", "category": "Asynchronous Warpgroup Level Matrix Multiply-Accumulate Instructions", "summary": "wgmma.wait_group instruction will cause the executing thread to wait until only N or fewer of the most recent wgmma-groups are pending and all the prior wgmma-groups committed by the executing threads are complete.", "syntax": "wgmma.wait_group.sync.aligned N;", "syntax_forms": [ { "syntax": "wgmma.wait_group.sync.aligned N;", "description": "wgmma.wait_group instruction will cause the executing thread to wait until only N or fewer of the most recent wgmma-groups are pending and all the prior wgmma-groups committed by the executing threads… (see the official PTX ISA docs for the full description)", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_90a" ], "introducedIn": "PTX ISA 8.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "N", "desc": "Operand" } ], "semantics": null, "examples": "wgmma.fence.sync.aligned;\n\nwgmma.mma_async.sync.aligned.m64n8k32.s32.u8.u8 {s32d0, s32d1, s32d2, s32d3},\n descA, descB, scaleD;\nwgmma.commit_group.sync.aligned;\n// (truncated - see the official PTX ISA docs for the full example)", "description": "wgmma.wait_group instruction will cause the executing thread to wait until only N or fewer of\nthe most recent wgmma-groups are pending and all the prior wgmma-groups committed by the executing\nthreads are complete. For example, when N is 0, the executing thread waits on all the prior\nwgmma-groups to complete. Operand N is an integer constant.\nAccessing the accumulator register or the input register containing the fragments of matrix A of a wgmma.mma_async instruction without first performing a wgmma.wait_group instruction that\nwaits on a wgmma-group including that wgmma.mma_async instruction is undefined behavior.\nThe mandatory.sync qualifier indicates that wgmma. (see the official PTX ISA docs for the full description)", "sourceUrl": null, "introducedIn": "PTX ISA 8.0", "requiredTargets": [ "sm_90a" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.wmma", "mnemonic": "wmma", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Warp Matrix Multiply-Accumulate", "category": "Warp Level Matrix Multiply-Accumulate Instructions", "summary": "Higher-level warp matrix-multiply-accumulate built from explicit load/mma/store steps.", "syntax": "wmma.load.a.sync.aligned.layout.shape.type r, [p];", "syntax_forms": [ { "syntax": "wmma.load.a.sync.aligned.layout.shape.type r, [p];", "description": "Load a matrix fragment cooperatively across the warp.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_70" ], "introducedIn": "PTX ISA 6.0" }, { "syntax": "wmma.mma.sync.aligned.layout.shape.dtype.ctype d, a, b, c;", "description": "Perform the accumulate step on already-loaded fragments.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_70" ], "introducedIn": "PTX ISA 6.0" }, { "syntax": "wmma.store.d.sync.aligned.layout.shape.type [p], r;", "description": "Store an accumulator fragment cooperatively across the warp.", "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_70" ], "introducedIn": "PTX ISA 6.0" } ], "dataTypes": [], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "r/d", "desc": "Fragment register(s)" }, { "name": "a", "desc": "Matrix A fragment" }, { "name": "b", "desc": "Matrix B fragment" }, { "name": "c", "desc": "Accumulator fragment (input)" }, { "name": "p", "desc": "Memory address for load/store forms" } ], "semantics": "Together, the load/mma/store triplet compute D = A * B + C for a fixed tile shape, cooperatively across the warp.", "examples": "// Load elements from f16 row-major matrix B\n.reg .b32 x<8>;\n\nwmma.load.b.sync.aligned.m16n16k16.row.f16 {x0,x1,x2,x3,x4,x5,x,x7}, [ptr];\n// Now use {x0, ..., x7} for the actual wmma.mma\n// (truncated - see the official PTX ISA docs for the full example)\n\n.global .align 32 .f16 A[256], B[256];\n.global .align 32 .f32 C[256], D[256];\n.reg .b32 a<8> b<8> c<8> d<8>;\n\nwmma.load.a.sync.aligned.m16n16k16.global.row.f16\n {a0, a1, a2, a3, a4, a5, a6, a7}, [A];\n// (truncated - see the official PTX ISA docs for the full example)\n\n// Storing f32 elements computed by a wmma.mma\n.reg .b32 x<8>;\n\nwmma.mma.sync.m16n16k16.row.col.f32.f32\n {d0, d1, d2, d3, d4, d5, d6, d7}, ...;\nwmma.store.d.sync.m16n16k16.row.f32\n// (truncated - see the official PTX ISA docs for the full example)", "description": "Perform a warp-level matrix multiply-and-accumulate computation D = A * B + C using matrices A,\nB and C loaded in registers a, b and c respectively, and store the result matrix in\nregister d. The register arguments a, b, c and d hold unspecified fragments of\nthe corresponding matrices as described in Matrix Fragments for WMMA\nThe qualifiers.dtype,.atype,.btype and.ctype indicate the data-type of the\nelements in the matrices D, A, B and C respectively.\nFor wmma.mma without explicit.atype and.btype:.atype and.btype are\nimplicitly set to.f16.\nFor integer wmma,.ctype and.dtype must be specified as.s32. (see the official PTX ISA docs for the full description)", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#warp-level-matrix-instructions-wmma-mma", "introducedIn": "PTX ISA 6.0", "requiredTargets": [ "sm_70" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] }, { "id": "ptx.xor", "mnemonic": "xor", "architecture": "PTX", "vendor": "NVIDIA", "processorClass": "gpu", "isaLayer": "virtual", "executionModel": "SIMT", "full_name": "Bitwise Exclusive OR", "category": "Logic and Shift Instructions", "summary": "Bitwise XOR of two operands.", "syntax": "xor.type d, a, b;", "syntax_forms": [ { "syntax": "xor.type d, a, b;", "description": "Bitwise XOR, including a predicate form.", "dataTypes": [ "b16", "b32", "b64", "pred" ], "stateSpaces": [], "scopes": [], "modifiers": [], "requiredTargets": [ "sm_10" ], "introducedIn": "PTX ISA 1.0" } ], "dataTypes": [ "b16", "b32", "b64", "pred" ], "stateSpaces": [], "scopes": [], "modifiers": [], "operands": [ { "name": "d", "desc": "Destination register" }, { "name": "a", "desc": "First operand" }, { "name": "b", "desc": "Second operand" } ], "semantics": "d = a ^ b (bitwise).", "examples": "xor.b32 d,q,r;\nxor.b16 d,x,0x0001;", "description": "Compute the bit-wise exclusive-or operation for the bits in a and b.", "sourceUrl": "https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#logic-and-shift-instructions-xor", "introducedIn": "PTX ISA 1.0", "requiredTargets": [ "sm_10" ], "deprecatedIn": null, "encoding": { "format": "Virtual (PTX)" }, "sourceIds": [ "nvidia-ptx-isa" ] } ] }