{
  "name": "InstructionSets instruction dataset",
  "generated": "2026-09-02",
  "records": 5986,
  "architectures": {
    "x86": 957,
    "ARM": 1145,
    "PowerISA": 1187,
    "RISC-V": 547,
    "PTX": 190,
    "AMDGPU": 1960
  },
  "excluded_fields": {
    "vendor_reproduced": [
      "sdm"
    ],
    "render_time": [
      "family_anchor",
      "family_is_primary",
      "family_key",
      "legacy_slug",
      "linked_pseudocode",
      "linked_summary",
      "other_forms",
      "pseudocode_html",
      "rel_url",
      "related_concept",
      "show_description",
      "show_example",
      "sibling_ids",
      "slug",
      "syntax_html",
      "title_qualifier",
      "visual_parts"
    ]
  },
  "vendor_bytes_removed": 8779825,
  "licence": "CC0-1.0",
  "licence_url": "https://creativecommons.org/publicdomain/zero/1.0/",
  "attribution": "Not required. Credit is welcome but not a condition of use: https://instructionsets.com. Vendor trademarks and the upstream specifications remain with their owners, see NOTICE.",
  "notes": "The sdm field is excluded because it reproduces Intel manual text verbatim. Every record retains its summary, description, pseudocode, operands and encoding.",
  "sha256": {
    "x86.json": "57b377d379cb6b4c7a2500a4c6aceaf923dbb3e9d712b3ec558f1da7e9fb4e8a",
    "arm.json": "e6375acbaf80fb711f575b4f87879893dc028d299c51f7e4157802906d3df5c9",
    "powerisa.json": "205369c0f06250f842fea6ba9095901ed49b5eff0d783c81bc353af4a7681d46",
    "riscv.json": "41e8c7e31f79c396cbc729d171eda8fa5404ce34770ab075df9b4f9f7899b8f4",
    "ptx.json": "66a7f6002c357f5550dffa4051db5f6da91746f992c5613637cf90afcdea7f10",
    "amdgpu.json": "7cc1386d676231fcaec63a58725846edba77dc76761e6f03bda9738390a10ac8",
    "instructions.jsonl": "1c343739a35a02e6255c6bab3731b74e755291a3d62c3aca9af136ed003e68b7"
  }
}