{ "architecture": "ARM", "instructions": [ { "mnemonic": "at", "architecture": "ARMv8-A", "full_name": "Address Translate (Stage 1 Current)", "summary": "Performs stage 1 address translation for current EL.", "syntax": "AT S1E1R, ", "encoding": { "format": "System", "binary_pattern": "1101010100 | 0 | 01 | op1 | 0111 | CRm | op2 | Rt", "hex_opcode": "0xD5087800", "visual_parts": [ { "raw": "1101010100", "clean": "1101010100" }, { "raw": "0", "clean": "0" }, { "raw": "01", "clean": "01" }, { "raw": "op1", "clean": "op1" }, { "raw": "0111", "clean": "0111" }, { "raw": "CRm", "clean": "CRm" }, { "raw": "op2", "clean": "op2" }, { "raw": "Rt", "clean": "Rt" } ], "bit_positions": "31:22 | 21 | 20:19 | 18:16 | 15:12 | 11:8 | 7:5 | 4:0" }, "operands": [ { "name": "Xt", "desc": "Virt Addr" } ], "extension": "Base (System)", "description": "Performs stage 1 address translation for a virtual address in the current execution level, treating the access as a read. The translation result (physical address and attributes) is written to the PAR_EL1 register. No condition flags are affected. This is an AArch64-only instruction that requires appropriate privilege level to access the address translation system registers.", "example": "AT S1E1R, x3", "pseudocode": "address ← Xt\ntranslation_result ← TranslateAddress(address, S1E1R, current_EL)\nPAR_EL1 ← translation_result" }, { "mnemonic": "at", "architecture": "ARMv8-A", "full_name": "Address Translate (Stage 1 Write)", "summary": "Performs stage 1 address translation for write permission.", "syntax": "AT S1E1W, ", "encoding": { "format": "System", "binary_pattern": "1101010100 | 0 | 01 | op1 | 0111 | CRm | op2 | Rt", "hex_opcode": "0xD5087800", "visual_parts": [ { "raw": "1101010100", "clean": "1101010100" }, { "raw": "0", "clean": "0" }, { "raw": "01", "clean": "01" }, { "raw": "op1", "clean": "op1" }, { "raw": "0111", "clean": "0111" }, { "raw": "CRm", "clean": "CRm" }, { "raw": "op2", "clean": "op2" }, { "raw": "Rt", "clean": "Rt" } ], "bit_positions": "31:22 | 21 | 20:19 | 18:16 | 15:12 | 11:8 | 7:5 | 4:0" }, "operands": [ { "name": "Xt", "desc": "Virt Addr" } ], "extension": "Base (System)", "description": "Performs stage 1 address translation for a virtual address in the current execution level, treating the access as a write. The translation result (physical address and attributes) is written to the PAR_EL1 register. No condition flags are affected. This is an AArch64-only instruction that requires appropriate privilege level to access the address translation system registers.", "example": "AT S1E1W, x3", "pseudocode": "address ← Xt\ntranslation_result ← TranslateAddress(address, S1E1W, current_EL)\nPAR_EL1 ← translation_result" }, { "mnemonic": "tlbi", "architecture": "ARMv8-A", "full_name": "TLB Invalidate (All)", "summary": "Invalidates all TLB entries in the inner shareable domain.", "syntax": "TLBI VMALLE1IS", "encoding": { "format": "System", "binary_pattern": "1101010100 | 0 | 01 | op1 | CRn | CRm | op2 | Rt", "hex_opcode": "0xD5088000", "visual_parts": [ { "raw": "1101010100", "clean": "1101010100" }, { "raw": "0", "clean": "0" }, { "raw": "01", "clean": "01" }, { "raw": "op1", "clean": "op1" }, { "raw": "CRn", "clean": "CRn" }, { "raw": "CRm", "clean": "CRm" }, { "raw": "op2", "clean": "op2" }, { "raw": "Rt", "clean": "Rt" } ], "bit_positions": "31:22 | 21 | 20:19 | 18:16 | 15:12 | 11:8 | 7:5 | 4:0" }, "operands": [], "extension": "Base (System)", "description": "Invalidates all TLB entries in the inner shareable domain, affecting all PEs in the shareable domain. This is an AArch64-only instruction requiring EL1 or higher privilege. No condition flags are affected; the instruction generates an exception if executed at EL0.", "example": "TLBI VMALLE1IS", "pseudocode": "TLBInvalidateAll(InnerShareable); DSB(SY); ISB()" }, { "mnemonic": "tlbi", "architecture": "ARMv8-A", "full_name": "TLB Invalidate (VA)", "summary": "Invalidates TLB entries by Virtual Address.", "syntax": "TLBI VAE1, ", "encoding": { "format": "System", "binary_pattern": "1101010100 | 0 | 01 | op1 | CRn | CRm | op2 | Rt", "hex_opcode": "0xD5088000", "visual_parts": [ { "raw": "1101010100", "clean": "1101010100" }, { "raw": "0", "clean": "0" }, { "raw": "01", "clean": "01" }, { "raw": "op1", "clean": "op1" }, { "raw": "CRn", "clean": "CRn" }, { "raw": "CRm", "clean": "CRm" }, { "raw": "op2", "clean": "op2" }, { "raw": "Rt", "clean": "Rt" } ], "bit_positions": "31:22 | 21 | 20:19 | 18:16 | 15:12 | 11:8 | 7:5 | 4:0" }, "operands": [ { "name": "Xt", "desc": "VA" } ], "extension": "Base (System)", "description": "Invalidates TLB entries matching the virtual address supplied in the register operand, at the current exception level. This is an AArch64-only instruction requiring EL1 or higher privilege. No condition flags are affected; the instruction generates an exception if executed at EL0.", "example": "TLBI VAE1, x3", "pseudocode": "TLBInvalidateByVA(Xt, EL1); DSB(SY); ISB()" }, { "mnemonic": "mcr", "architecture": "ARMv8-A", "full_name": "Move to Coprocessor from Register (A32)", "summary": "Writes a general-purpose register to a coprocessor register (e.g., CP15).", "syntax": "MCR , , , , {, }", "encoding": { "format": "Coprocessor", "binary_pattern": "cond | 1110 | opc1 | 0 | CRn | Rt | 111 | coproc<0> | opc2 | 1 | CRm", "hex_opcode": "0x0E000E10", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "1110", "clean": "1110" }, { "raw": "opc1", "clean": "opc1" }, { "raw": "0", "clean": "0" }, { "raw": "CRn", "clean": "CRn" }, { "raw": "Rt", "clean": "Rt" }, { "raw": "111", "clean": "111" }, { "raw": "coproc<0>", "clean": "coproc<0>" }, { "raw": "opc2", "clean": "opc2" }, { "raw": "1", "clean": "1" }, { "raw": "CRm", "clean": "CRm" } ], "bit_positions": "31:28 | 27:24 | 23:21 | 20 | 19:16 | 15:12 | 11:9 | 8 | 7:5 | 4 | 3:0" }, "operands": [ { "name": "coproc", "desc": "CP Num" }, { "name": "Rt", "desc": "Transfer general-purpose register (load/store)" }, { "name": "CRn", "desc": "Dest CP Reg" } ], "extension": "A32 (System)", "description": "Moves data from a general-purpose register into a coprocessor register (typically CP15 for system control). The instruction is conditional and executes only if the condition code is satisfied. No ARM condition flags (N, Z, C, V) are modified by this instruction. This is an A32-only instruction with implementation-specific side effects depending on the target coprocessor register.", "example": "MCR p15, 0, r3, c1, c2", "pseudocode": "if ConditionPassed(cond) then\n CP[coproc, opc1, CRn, CRm, opc2] ← Rt" }, { "mnemonic": "mrc", "architecture": "ARMv8-A", "full_name": "Move to Register from Coprocessor (A32)", "summary": "Reads a coprocessor register into a general-purpose register.", "syntax": "MRC , , , , {, }", "encoding": { "format": "Coprocessor", "binary_pattern": "cond | 1110 | opc1 | 1 | CRn | Rt | 111 | coproc<0> | opc2 | 1 | CRm", "hex_opcode": "0x0E100E10", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "1110", "clean": "1110" }, { "raw": "opc1", "clean": "opc1" }, { "raw": "1", "clean": "1" }, { "raw": "CRn", "clean": "CRn" }, { "raw": "Rt", "clean": "Rt" }, { "raw": "111", "clean": "111" }, { "raw": "coproc<0>", "clean": "coproc<0>" }, { "raw": "opc2", "clean": "opc2" }, { "raw": "1", "clean": "1" }, { "raw": "CRm", "clean": "CRm" } ], "bit_positions": "31:28 | 27:24 | 23:21 | 20 | 19:16 | 15:12 | 11:9 | 8 | 7:5 | 4 | 3:0" }, "operands": [ { "name": "coproc", "desc": "CP Num" }, { "name": "Rt", "desc": "Transfer general-purpose register (load/store)" }, { "name": "CRn", "desc": "Src CP Reg" } ], "extension": "A32 (System)", "description": "Moves data from a coprocessor register (typically CP15 for system control) into a general-purpose register. The instruction is conditional and executes only if the condition code is satisfied. The N, Z, C, V flags may be modified depending on the coprocessor register being read. This is an A32-only instruction with implementation-specific behavior depending on the source coprocessor register.", "example": "MRC p15, 0, r3, c1, c2", "pseudocode": "if ConditionPassed(cond) then\n Rt ← CP[coproc, opc1, CRn, CRm, opc2]\n condition_flags may be updated by coprocessor" }, { "mnemonic": "mcrr", "architecture": "ARMv8-A", "full_name": "Move to Coprocessor from Two Registers (A32)", "summary": "Writes two general-purpose registers to a coprocessor (64-bit transfer).", "syntax": "MCRR , , , , ", "encoding": { "format": "Coprocessor", "binary_pattern": "cond | 11000 | 1 | 0 | 0 | Rt2 | Rt | 111 | coproc<0> | opc1 | CRm", "hex_opcode": "0x0C400E00", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "11000", "clean": "11000" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "Rt2", "clean": "Rt2" }, { "raw": "Rt", "clean": "Rt" }, { "raw": "111", "clean": "111" }, { "raw": "coproc<0>", "clean": "coproc<0>" }, { "raw": "opc1", "clean": "opc1" }, { "raw": "CRm", "clean": "CRm" } ], "bit_positions": "31:28 | 27:23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "coproc", "desc": "CP Num" }, { "name": "Rt", "desc": "Transfer general-purpose register (load/store)" }, { "name": "Rt2", "desc": "Second transfer register (load/store pair)" } ], "extension": "A32 (System)", "description": "Moves data from two consecutive general-purpose registers into a coprocessor (64-bit data transfer). The instruction is conditional and executes only if the condition code is satisfied. No ARM condition flags are modified. This is an A32-only instruction; the two source registers are treated as a 64-bit value with Rt containing the lower 32 bits.", "example": "MCRR p15, 0, r3, r4, c2", "pseudocode": "if ConditionPassed(cond) then\n CP64[coproc, opc1, CRm] ← (Rt2:Rt)\n // Rt holds bits [31:0], Rt2 holds bits [63:32]" }, { "mnemonic": "mrrc", "architecture": "ARMv8-A", "full_name": "Move to Two Registers from Coprocessor (A32)", "summary": "Reads a coprocessor register into two general-purpose registers.", "syntax": "MRRC , , , , ", "encoding": { "format": "Coprocessor", "binary_pattern": "cond | 11000 | 1 | 0 | 1 | Rt2 | Rt | 111 | coproc<0> | opc1 | CRm", "hex_opcode": "0x0C500E00", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "11000", "clean": "11000" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "Rt2", "clean": "Rt2" }, { "raw": "Rt", "clean": "Rt" }, { "raw": "111", "clean": "111" }, { "raw": "coproc<0>", "clean": "coproc<0>" }, { "raw": "opc1", "clean": "opc1" }, { "raw": "CRm", "clean": "CRm" } ], "bit_positions": "31:28 | 27:23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "coproc", "desc": "CP Num" }, { "name": "Rt", "desc": "Dest 1" }, { "name": "Rt2", "desc": "Dest 2" } ], "extension": "A32 (System)", "description": "Moves data from a coprocessor into two consecutive general-purpose registers (64-bit data transfer). The instruction is conditional and executes only if the condition code is satisfied. No ARM condition flags are modified by this instruction itself, though the coprocessor may affect them. This is an A32-only instruction; the 64-bit result is split with Rt receiving the lower 32 bits and Rt2 the upper 32 bits.", "example": "MRRC p15, 0, r3, r4, c2", "pseudocode": "if ConditionPassed(cond) then\n data64 ← CP64[coproc, opc1, CRm]\n Rt ← data64[31:0]\n Rt2 ← data64[63:32]" }, { "mnemonic": "ldc", "architecture": "ARMv8-A", "full_name": "Load Coprocessor (A32)", "summary": "Loads memory into a coprocessor.", "syntax": "LDC{L} , , [, #+/-]{!}", "encoding": { "format": "Coprocessor", "binary_pattern": "cond | 110 | 1 | U | 0 | 1 | 1 | Rn | 0101 | 111 | 0 | imm8", "hex_opcode": "0x0D305E00", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "110", "clean": "110" }, { "raw": "1", "clean": "1" }, { "raw": "U", "clean": "U" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "0101", "clean": "0101" }, { "raw": "111", "clean": "111" }, { "raw": "0", "clean": "0" }, { "raw": "imm8", "clean": "imm8" } ], "bit_positions": "31:28 | 27:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:9 | 8 | 7:0" }, "operands": [ { "name": "coproc", "desc": "CP Num" }, { "name": "CRd", "desc": "Destination coprocessor register" }, { "name": "Rn", "desc": "First source / base general-purpose register" } ], "extension": "A32 (System)", "description": "Loads data from memory into a coprocessor register, with pre/post-indexed addressing. This is an A32-only instruction that executes conditionally based on the condition field. The base register Rn is updated if the write-back bit W is set; no condition flags are affected by this instruction.", "example": "LDC p15, c0, [r1, #+/-#16]!", "pseudocode": "if ConditionPassed(cond) then\n address ← if P then (Rn + (imm8 << 2)) else Rn\n if U then address ← Rn + (imm8 << 2) else address ← Rn - (imm8 << 2)\n Coproc_load(address, CRd)\n if W then Rn ← address" }, { "mnemonic": "stc", "architecture": "ARMv8-A", "full_name": "Store Coprocessor (A32)", "summary": "Stores coprocessor contents to memory.", "syntax": "STC{L} , , [, #+/-]{!}", "encoding": { "format": "Coprocessor", "binary_pattern": "cond | 110 | 1 | U | 0 | 1 | 0 | Rn | 0101 | 111 | 0 | imm8", "hex_opcode": "0x0D205E00", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "110", "clean": "110" }, { "raw": "1", "clean": "1" }, { "raw": "U", "clean": "U" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "0101", "clean": "0101" }, { "raw": "111", "clean": "111" }, { "raw": "0", "clean": "0" }, { "raw": "imm8", "clean": "imm8" } ], "bit_positions": "31:28 | 27:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:9 | 8 | 7:0" }, "operands": [ { "name": "coproc", "desc": "CP Num" }, { "name": "CRd", "desc": "Destination coprocessor register" }, { "name": "Rn", "desc": "First source / base general-purpose register" } ], "extension": "A32 (System)", "description": "Stores coprocessor register contents to memory, with pre/post-indexed addressing. This is an A32-only instruction that executes conditionally based on the condition field. The base register Rn is updated if the write-back bit W is set; no condition flags are affected by this instruction.", "example": "STC p15, c0, [r1, #+/-#16]!", "pseudocode": "if ConditionPassed(cond) then\n address ← if P then (Rn + (imm8 << 2)) else Rn\n if U then address ← Rn + (imm8 << 2) else address ← Rn - (imm8 << 2)\n [address] ← Coproc_store(CRd)\n if W then Rn ← address" }, { "mnemonic": "vmrs", "architecture": "ARMv8-A", "full_name": "Move VFP System Register to Register", "summary": "Reads a VFP system register (like FPSCR).", "syntax": "VMRS , ", "encoding": { "format": "VFP System", "binary_pattern": "cond | 1110111 | 1 | reg | Rt | 1010 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0", "hex_opcode": "0x0EF00A10", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "1110111", "clean": "1110111" }, { "raw": "1", "clean": "1" }, { "raw": "reg", "clean": "reg" }, { "raw": "Rt", "clean": "Rt" }, { "raw": "1010", "clean": "1010" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" } ], "bit_positions": "31:28 | 27:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0" }, "operands": [ { "name": "Rt", "desc": "Dest (or APSR_nzcv)" }, { "name": "spec_reg", "desc": "FPSCR" } ], "extension": "VFP (System)", "description": "Reads a VFP system register (typically FPSCR) and transfers its value to a general-purpose register or the APSR condition flags. This is an A32/T32 instruction that executes conditionally. If Rt is R15, the N, Z, C, V flags are updated from FPSCR bits; otherwise no flags are modified.", "example": "VMRS r3, nzcv", "pseudocode": "if ConditionPassed(cond) then\n if Rt == 15 then\n APSR_nzcv ← FPSCR[31:28]\n else\n Rt ← FPSCR" }, { "mnemonic": "vmsr", "architecture": "ARMv8-A", "full_name": "Move Register to VFP System Register", "summary": "Writes to a VFP system register.", "syntax": "VMSR , ", "encoding": { "format": "VFP System", "binary_pattern": "cond | 1110111 | 0 | reg | Rt | 1010 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0", "hex_opcode": "0x0EE00A10", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "1110111", "clean": "1110111" }, { "raw": "0", "clean": "0" }, { "raw": "reg", "clean": "reg" }, { "raw": "Rt", "clean": "Rt" }, { "raw": "1010", "clean": "1010" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" } ], "bit_positions": "31:28 | 27:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0" }, "operands": [ { "name": "spec_reg", "desc": "FPSCR" }, { "name": "Rt", "desc": "Transfer general-purpose register (load/store)" } ], "extension": "VFP (System)", "description": "Writes a general-purpose register value to a VFP system register (typically FPSCR). This is an A32/T32 instruction that executes conditionally. If Rt is R15, the APSR condition flags are written to FPSCR; the instruction may modify exception flags and rounding modes in FPSCR.", "example": "VMSR nzcv, r3", "pseudocode": "if ConditionPassed(cond) then\n if Rt == 15 then\n FPSCR[31:28] ← APSR_nzcv\n else\n FPSCR ← Rt" }, { "mnemonic": "ldrexb", "architecture": "ARMv8-A", "full_name": "Load Register Exclusive Byte (A32)", "summary": "Loads a byte and marks address as exclusive.", "syntax": "LDREXB , []", "encoding": { "format": "Load/Store Excl", "binary_pattern": "cond | 00011 | 10 | 1 | Rn | Rt | 1 | 1 | 1 | 1 | 1001 | 1111", "hex_opcode": "0x01D00F9F", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00011", "clean": "00011" }, { "raw": "10", "clean": "10" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rt", "clean": "Rt" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1001", "clean": "1001" }, { "raw": "1111", "clean": "1111" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rt", "desc": "Transfer general-purpose register (load/store)" }, { "name": "Rn", "desc": "First source / base general-purpose register" } ], "extension": "A32 (Atomic)", "description": "Loads a byte from memory into a register and marks the address as exclusive for synchronization. The byte is zero-extended to 32 bits in the destination register. No condition flags are modified. This is an A32-only instruction that atomically acquires an exclusive lock on the target byte address; the lock is released by a matching STREXB or other exclusive store.", "example": "LDREXB r3, [r1]", "pseudocode": "if ConditionPassed(cond) then\n address ← Rn\n Rt ← ZeroExtend([address], 8)\n SetExclusiveMonitor(address, 1)" }, { "mnemonic": "strexb", "architecture": "ARMv8-A", "full_name": "Store Register Exclusive Byte (A32)", "summary": "Stores a byte if address is still exclusive.", "syntax": "STREXB , , []", "encoding": { "format": "Load/Store Excl", "binary_pattern": "cond | 00011 | 10 | 0 | Rn | Rd | 1 | 1 | 1 | 1 | 1001 | Rt", "hex_opcode": "0x01C00F90", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00011", "clean": "00011" }, { "raw": "10", "clean": "10" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1001", "clean": "1001" }, { "raw": "Rt", "clean": "Rt" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Status" }, { "name": "Rt", "desc": "Transfer general-purpose register (load/store)" }, { "name": "Rn", "desc": "First source / base general-purpose register" } ], "extension": "A32 (Atomic)", "description": "Conditionally stores a byte to memory if the address is still marked as exclusive, returning a status in Rd (0=success, 1=failure). No condition flags are modified by the store result; success/failure is reported only in Rd. This is an A32-only instruction that atomically releases the exclusive lock and performs the write only if the lock is still held from a prior LDREXB.", "example": "STREXB r0, r3, [r1]", "pseudocode": "if ConditionPassed(cond) then\n address ← Rn\n byte_value ← Rt[7:0]\n if ExclusiveMonitorSet(address, 1) then\n [address] ← byte_value\n Rd ← 0\n ClearExclusiveMonitor(address, 1)\n else\n Rd ← 1" }, { "mnemonic": "ldrexh", "architecture": "ARMv8-A", "full_name": "Load Register Exclusive Halfword (A32)", "summary": "Loads a halfword and marks address as exclusive.", "syntax": "LDREXH , []", "encoding": { "format": "Load/Store Excl", "binary_pattern": "cond | 00011 | 11 | 1 | Rn | Rt | 1 | 1 | 1 | 1 | 1001 | 1111", "hex_opcode": "0x01F00F9F", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00011", "clean": "00011" }, { "raw": "11", "clean": "11" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rt", "clean": "Rt" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1001", "clean": "1001" }, { "raw": "1111", "clean": "1111" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rt", "desc": "Transfer general-purpose register (load/store)" }, { "name": "Rn", "desc": "First source / base general-purpose register" } ], "extension": "A32 (Atomic)", "description": "Loads a 16-bit value from memory at the address in Rn and marks that address as exclusive for the current processor. The loaded halfword is zero-extended and placed in Rt. No condition flags are affected. This A32 instruction requires a matching STREXH to conditionally store; if the exclusive monitor is cleared, a subsequent STREXH will fail.", "example": "LDREXH r3, [r1]", "pseudocode": "address ← Rn; Rt ← ZeroExtend(MemU[address, 2]); ExclusiveMonitorsMarkExclusive(address, ProcessorID(), 2);" }, { "mnemonic": "strexh", "architecture": "ARMv8-A", "full_name": "Store Register Exclusive Halfword (A32)", "summary": "Stores a halfword if address is still exclusive.", "syntax": "STREXH , , []", "encoding": { "format": "Load/Store Excl", "binary_pattern": "cond | 00011 | 11 | 0 | Rn | Rd | 1 | 1 | 1 | 1 | 1001 | Rt", "hex_opcode": "0x01E00F90", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00011", "clean": "00011" }, { "raw": "11", "clean": "11" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1001", "clean": "1001" }, { "raw": "Rt", "clean": "Rt" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Status" }, { "name": "Rt", "desc": "Transfer general-purpose register (load/store)" }, { "name": "Rn", "desc": "First source / base general-purpose register" } ], "extension": "A32 (Atomic)", "description": "Conditionally stores a 16-bit value from Rt to memory at the address in Rn if that address is still marked exclusive by the current processor. Writes 0 to Rd if the store succeeds, or 1 if it fails due to loss of exclusivity. No condition flags are affected by the instruction result itself; the exclusive monitor behavior determines success/failure.", "example": "STREXH r0, r3, [r1]", "pseudocode": "address ← Rn; if ExclusiveMonitorsCheckExclusive(address, ProcessorID(), 2) then MemU[address, 2] ← Rt[15:0]; Rd ← 0; ExclusiveMonitorsClearExclusive(ProcessorID()); else Rd ← 1;" }, { "mnemonic": "ldrexd", "architecture": "ARMv8-A", "full_name": "Load Register Exclusive Double (A32)", "summary": "Loads a doubleword and marks address as exclusive.", "syntax": "LDREXD , , []", "encoding": { "format": "Load/Store Excl", "binary_pattern": "cond | 00011 | 01 | 1 | Rn | Rt | 1 | 1 | 1 | 1 | 1001 | 1111", "hex_opcode": "0x01B00F9F", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00011", "clean": "00011" }, { "raw": "01", "clean": "01" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rt", "clean": "Rt" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1001", "clean": "1001" }, { "raw": "1111", "clean": "1111" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rt", "desc": "Dest 1" }, { "name": "Rt2", "desc": "Dest 2" }, { "name": "Rn", "desc": "First source / base general-purpose register" } ], "extension": "A32 (Atomic)", "description": "Loads a 64-bit doubleword from memory at the address in Rn and marks that address as exclusive for the current processor. The loaded value is split across Rt (lower 32 bits) and Rt2 (upper 32 bits). No condition flags are affected. This A32 instruction requires matching STREXD for conditional storage; Rt and Rt2 must be consecutive registers.", "example": "LDREXD r3, r4, [r1]", "pseudocode": "address ← Rn; value ← MemU[address, 8]; Rt ← value[31:0]; Rt2 ← value[63:32]; ExclusiveMonitorsMarkExclusive(address, ProcessorID(), 8);" }, { "mnemonic": "strexd", "architecture": "ARMv8-A", "full_name": "Store Register Exclusive Double (A32)", "summary": "Stores a doubleword if address is still exclusive.", "syntax": "STREXD , , , []", "encoding": { "format": "Load/Store Excl", "binary_pattern": "cond | 00011 | 01 | 0 | Rn | Rd | 1 | 1 | 1 | 1 | 1001 | Rt", "hex_opcode": "0x01A00F90", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00011", "clean": "00011" }, { "raw": "01", "clean": "01" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1001", "clean": "1001" }, { "raw": "Rt", "clean": "Rt" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Status" }, { "name": "Rt", "desc": "Transfer general-purpose register (load/store)" }, { "name": "Rt2", "desc": "Second transfer register (load/store pair)" }, { "name": "Rn", "desc": "First source / base general-purpose register" } ], "extension": "A32 (Atomic)", "description": "Conditionally stores a 64-bit doubleword from Rt and Rt2 to memory at the address in Rn if that address is still marked exclusive by the current processor. Writes 0 to Rd on success or 1 on failure. No condition flags are affected; exclusive monitor state determines the outcome.", "example": "STREXD r0, r3, r4, [r1]", "pseudocode": "address ← Rn; if ExclusiveMonitorsCheckExclusive(address, ProcessorID(), 8) then MemU[address, 8] ← Rt || Rt2; Rd ← 0; ExclusiveMonitorsClearExclusive(ProcessorID()); else Rd ← 1;" }, { "mnemonic": "dcps1", "architecture": "ARMv8-A", "full_name": "Debug Change PE State to EL1 (A32)", "summary": "Switches execution to EL1 (Debug).", "syntax": "DCPS1", "encoding": { "format": "System", "binary_pattern": "111101111000 | 1111 | 1000 | 0000000000 | 01", "hex_opcode": "0xF78F8001", "visual_parts": [ { "raw": "111101111000", "clean": "111101111000" }, { "raw": "1111", "clean": "1111" }, { "raw": "1000", "clean": "1000" }, { "raw": "0000000000", "clean": "0000000000" }, { "raw": "01", "clean": "01" } ], "bit_positions": "31:20 | 19:16 | 15:12 | 11:2 | 1:0" }, "operands": [], "extension": "A32 (System)", "description": "Changes PE execution state to EL1 for debugging purposes. This is an A32-only instruction that immediately changes exception level and may update execution state; it does not return (implicit branch to debug handler). Condition flags are not affected by the instruction itself but are context-switched at the target exception level.", "example": "DCPS1", "pseudocode": "DebugChangeEL(EL1); // Changes exception level and branches to debug handler" }, { "mnemonic": "dcps2", "architecture": "ARMv8-A", "full_name": "Debug Change PE State to EL2 (A32)", "summary": "Switches execution to EL2 (Debug).", "syntax": "DCPS2", "encoding": { "format": "System", "binary_pattern": "111101111000 | 1111 | 1000 | 0000000000 | 10", "hex_opcode": "0xF78F8002", "visual_parts": [ { "raw": "111101111000", "clean": "111101111000" }, { "raw": "1111", "clean": "1111" }, { "raw": "1000", "clean": "1000" }, { "raw": "0000000000", "clean": "0000000000" }, { "raw": "10", "clean": "10" } ], "bit_positions": "31:20 | 19:16 | 15:12 | 11:2 | 1:0" }, "operands": [], "extension": "A32 (System)", "description": "Changes PE execution state to EL2 for debugging purposes. This is an A32-only instruction that immediately changes exception level and may update execution state; it does not return (implicit branch to debug handler). Condition flags are not affected by the instruction itself but are context-switched at the target exception level.", "example": "DCPS2", "pseudocode": "DebugChangeEL(EL2); // Changes exception level and branches to debug handler" }, { "mnemonic": "dcps3", "architecture": "ARMv8-A", "full_name": "Debug Change PE State to EL3 (A32)", "summary": "Switches execution to EL3 (Debug).", "syntax": "DCPS3", "encoding": { "format": "System", "binary_pattern": "111101111000 | 1111 | 1000 | 0000000000 | 11", "hex_opcode": "0xF78F8003", "visual_parts": [ { "raw": "111101111000", "clean": "111101111000" }, { "raw": "1111", "clean": "1111" }, { "raw": "1000", "clean": "1000" }, { "raw": "0000000000", "clean": "0000000000" }, { "raw": "11", "clean": "11" } ], "bit_positions": "31:20 | 19:16 | 15:12 | 11:2 | 1:0" }, "operands": [], "extension": "A32 (System)", "description": "Debug Change PE State to EL3 switches the processor to Exception Level 3 (EL3) in debug state without saving the current processor state. This instruction is used by debuggers to enter the highest privilege level. It is available only in A32 instruction set and requires debug authentication. No condition flags are modified.", "example": "DCPS3", "pseudocode": "CurrentEL ← EL3; PSTATE.EL ← '11'; PSTATE.SS ← '0';" }, { "mnemonic": "setpan", "architecture": "ARMv8-A", "full_name": "Set Privileged Access Never (A32)", "summary": "Enables/Disables PAN (Prevents kernel accessing user memory).", "syntax": "SETPAN #", "encoding": { "format": "System", "binary_pattern": "111100010001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | imm1 | 0 | 0000 | 0 | 0 | 0 | 0", "hex_opcode": "0xF1100000", "visual_parts": [ { "raw": "111100010001", "clean": "111100010001" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "imm1", "clean": "imm1" }, { "raw": "0", "clean": "0" }, { "raw": "0000", "clean": "0000" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" } ], "bit_positions": "31:20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7:4 | 3 | 2 | 1 | 0" }, "operands": [ { "name": "imm", "desc": "0/1" } ], "extension": "A32 (System)", "description": "Set Privileged Access Never enables or disables the PAN (Privileged Access Never) control bit, which prevents privileged software from accessing user-mode memory. When PAN is enabled (imm=1), privileged accesses to user memory are trapped; when disabled (imm=0), such accesses are permitted. This instruction is available in A32 and requires appropriate privilege level. No condition flags are modified.", "example": "SETPAN #16", "pseudocode": "PSTATE.PAN ← imm;" }, { "mnemonic": "esb", "architecture": "ARMv8-A", "full_name": "Error Synchronization Barrier (A32)", "summary": "Synchronizes system errors (v8.2).", "syntax": "ESB", "encoding": { "format": "System Hint", "binary_pattern": "cond | 00110 | 0 | 10 | 0000 | 1 | 1 | 1 | 1 | 000000010000", "hex_opcode": "0x0320F010", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00110", "clean": "00110" }, { "raw": "0", "clean": "0" }, { "raw": "10", "clean": "10" }, { "raw": "0000", "clean": "0000" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "000000010000", "clean": "000000010000" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15 | 14 | 13 | 12 | 11:0" }, "operands": [], "extension": "A32 (RAS)", "description": "Error Synchronization Barrier (v8.2) for RAS (Reliability, Availability, and Serviceability) synchronizes system error handling, ensuring that error detection and processing operations complete in order. This instruction is essential in fault-tolerance and error recovery scenarios and does not modify general-purpose registers or condition flags. Available in A32 instruction set.", "example": "ESB", "pseudocode": "// Synchronize error handling\nErrorSynchronizationBarrier()\n// All pending error detection and processing operations complete" }, { "mnemonic": "csdb", "architecture": "ARMv8-A", "full_name": "Consumption of Speculative Data Barrier (A32)", "summary": "Prevents speculative data consumption (v8.0).", "syntax": "CSDB", "encoding": { "format": "System Hint", "binary_pattern": "cond | 00110 | 0 | 10 | 0000 | 1 | 1 | 1 | 1 | 000000010100", "hex_opcode": "0x0320F014", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00110", "clean": "00110" }, { "raw": "0", "clean": "0" }, { "raw": "10", "clean": "10" }, { "raw": "0000", "clean": "0000" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "000000010100", "clean": "000000010100" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15 | 14 | 13 | 12 | 11:0" }, "operands": [], "extension": "A32 (v8.0)", "description": "Consumption of Speculative Data Barrier (v8.0) prevents the CPU from using speculatively-loaded data in subsequent operations, protecting against attacks that exploit speculative data consumption side channels. Instructions following CSDB cannot use data speculatively loaded before this barrier. Available in A32 instruction set; does not modify condition flags.", "example": "CSDB", "pseudocode": "// Prevent consumption of speculatively-loaded data\nConsumptionBarrier()\n// Subsequent instructions cannot use data obtained through speculative execution prior to this barrier" }, { "mnemonic": "vldm", "architecture": "ARMv8-A", "full_name": "Vector Load Multiple (VFP)", "summary": "Loads multiple VFP registers from memory.", "syntax": "VLDM {!}, ", "encoding": { "format": "VFP Load Multiple", "binary_pattern": "cond | 110 | 0 | 1 | D | W | 1 | Rn | Vd | 10 | 10 | imm8", "hex_opcode": "0x0C900A00", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "110", "clean": "110" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "W", "clean": "W" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "imm8", "clean": "imm8" } ], "bit_positions": "31:28 | 27:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:10 | 9:8 | 7:0" }, "operands": [ { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "list", "desc": "Registers" } ], "extension": "VFP (Float)", "description": "Vector Load Multiple loads multiple consecutive double-precision or single-precision floating-point registers from memory using the address in a general-purpose base register. The base register can be optionally auto-incremented by the total bytes loaded. Condition flags (N, Z, C, V) are unaffected unless an exception occurs.", "example": "VLDMia r1!, {r0-r3", "pseudocode": "address ← Rn; for i = 0 to (list_count - 1) do; Driestlist[i] ← [address]; address ← address + (register_size / 8); end; if !(!) then Rn ← address;" }, { "mnemonic": "vstm", "architecture": "ARMv8-A", "full_name": "Vector Store Multiple (VFP)", "summary": "Stores multiple VFP registers to memory.", "syntax": "VSTM {!}, ", "encoding": { "format": "VFP Store Multiple", "binary_pattern": "cond | 110 | 0 | 1 | D | W | 0 | Rn | Vd | 10 | 10 | imm8", "hex_opcode": "0x0C800A00", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "110", "clean": "110" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "W", "clean": "W" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "imm8", "clean": "imm8" } ], "bit_positions": "31:28 | 27:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:10 | 9:8 | 7:0" }, "operands": [ { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "list", "desc": "Registers" } ], "extension": "VFP (Float)", "description": "Vector Store Multiple stores multiple consecutive double-precision or single-precision floating-point registers to memory using the address in a general-purpose base register. The base register can be optionally auto-incremented by the total bytes stored. Condition flags (N, Z, C, V) are unaffected unless an exception occurs.", "example": "VSTMia r1!, {r0-r3", "pseudocode": "address ← Rn; for i = 0 to (list_count - 1) do; [address] ← Vriestlist[i]; address ← address + (register_size / 8); end; if !(!) then Rn ← address;" }, { "mnemonic": "vcmp", "architecture": "ARMv8-A", "full_name": "Vector Compare Zero (VFP)", "summary": "Compares a floating-point value with #0.0.", "syntax": "VCMP.F32 , #0.0", "encoding": { "format": "VFP Compare", "binary_pattern": "cond | 11101 | D | 11 | 0 | 101 | Vd | 10 | 10 | 0 | 1 | 0 | 0 | 0000", "hex_opcode": "0x0EB50A40", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "11101", "clean": "11101" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "0", "clean": "0" }, { "raw": "101", "clean": "101" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0000", "clean": "0000" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" } ], "extension": "VFP (Float)", "description": "Vector Compare Zero compares a single-precision floating-point value against zero and updates the VFP condition flags (FPSCR bits 28-31) based on the result. The comparison sets flags for signed magnitude comparison: N, Z, C, V flags in FPSCR are updated; FPSCR.E bit may be set if an exception occurs. Available in A32 VFP extension.", "example": "VCMP.F32 s0, #0.0", "pseudocode": "result ← Sd - 0.0; UpdateFPSCRConditionFlags(result); if exception then SetFPSCRException();" }, { "mnemonic": "vdiv", "architecture": "ARMv8-A", "full_name": "Vector Divide (Double)", "summary": "Divides two double-precision registers.", "syntax": "VDIV.F64
, , ", "encoding": { "format": "VFP Arith", "binary_pattern": "cond | 1110 | 1 | D | 00 | Vn | Vd | 10 | 11 | N | 0 | M | 0 | Vm", "hex_opcode": "0x0E800B00", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "1110", "clean": "1110" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "00", "clean": "00" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "11", "clean": "11" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:28 | 27:24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Dd", "desc": "Destination 64-bit SIMD/FP register" }, { "name": "Dn", "desc": "Dividend" }, { "name": "Dm", "desc": "Divisor" } ], "extension": "VFP (Float)", "description": "Divides the 64-bit double-precision value in Dn by the value in Dm and places the floating-point result in Dd. The operation follows IEEE 754 semantics for rounding and exception handling. FPSCR condition flags (N, Z, C, V) may be set based on the result and any exceptions; this instruction is available only in A32 and T32 with VFP support.", "example": "VDIV.F64 d0, d1, d2", "pseudocode": "Dd ← FPDiv(Dn, Dm); FPSCR.N ← Dd[63]; FPSCR.Z ← (Dd == 0.0); FPSCR.C ← FPExceptionRaised(); FPSCR.V ← FPInvalidOp();" }, { "mnemonic": "vabs", "architecture": "ARMv8-A", "full_name": "Vector Absolute Value (Double)", "summary": "Absolute value of double-precision register.", "syntax": "VABS.F64
, ", "encoding": { "format": "VFP Unary", "binary_pattern": "cond | 11101 | D | 11 | 0 | 000 | Vd | 10 | 11 | 1 | 1 | M | 0 | Vm", "hex_opcode": "0x0EB00BC0", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "11101", "clean": "11101" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "0", "clean": "0" }, { "raw": "000", "clean": "000" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "11", "clean": "11" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Dd", "desc": "Destination 64-bit SIMD/FP register" }, { "name": "Dm", "desc": "Second source 64-bit SIMD/FP register" } ], "extension": "VFP (Float)", "description": "Vector Absolute Value computes the absolute value of a 64-bit double-precision floating-point register and stores the result in the destination register. The sign bit is cleared while the exponent and significand are preserved. Condition flags are unaffected unless an exception occurs. Available in A32 VFP extension.", "example": "VABS.F64 d0, d2", "pseudocode": "Dd.sign ← 0; Dd.exponent ← Dm.exponent; Dd.fraction ← Dm.fraction;" }, { "mnemonic": "vneg", "architecture": "ARMv8-A", "full_name": "Vector Negate (Double)", "summary": "Negates double-precision register.", "syntax": "VNEG.F64
, ", "encoding": { "format": "VFP Unary", "binary_pattern": "cond | 11101 | D | 11 | 0 | 001 | Vd | 10 | 11 | 0 | 1 | M | 0 | Vm", "hex_opcode": "0x0EB10B40", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "11101", "clean": "11101" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "0", "clean": "0" }, { "raw": "001", "clean": "001" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "11", "clean": "11" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Dd", "desc": "Destination 64-bit SIMD/FP register" }, { "name": "Dm", "desc": "Second source 64-bit SIMD/FP register" } ], "extension": "VFP (Float)", "description": "Negates a double-precision floating-point value in the source register and stores the result in the destination register. This is a unary VFP operation that inverts the sign bit of the IEEE 754 double-precision number. No condition flags are affected. Requires VFP extension and executes only in A32 instruction set.", "example": "VNEG.F64 d0, d2", "pseudocode": "Dd ← -Dm\nFPSCR.NZCV unchanged" }, { "mnemonic": "vsqrt", "architecture": "ARMv8-A", "full_name": "Vector Square Root (Double)", "summary": "Square root of double-precision register.", "syntax": "VSQRT.F64
, ", "encoding": { "format": "VFP Unary", "binary_pattern": "cond | 11101 | D | 11 | 0 | 001 | Vd | 10 | 11 | 1 | 1 | M | 0 | Vm", "hex_opcode": "0x0EB10BC0", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "11101", "clean": "11101" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "0", "clean": "0" }, { "raw": "001", "clean": "001" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "11", "clean": "11" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Dd", "desc": "Destination 64-bit SIMD/FP register" }, { "name": "Dm", "desc": "Second source 64-bit SIMD/FP register" } ], "extension": "VFP (Float)", "description": "Computes the square root of a double-precision floating-point value and stores the result in the destination register. This is a unary VFP operation that performs IEEE 754 compliant square-root computation; if the source is negative (excluding -0), the result is NaN. FPSCR exception flags may be set based on input and result. Requires VFP extension and executes only in A32 instruction set.", "example": "VSQRT.F64 d0, d2", "pseudocode": "Dd ← sqrt(Dm)\nFPSCR.IOC ← 1 if Dm < 0.0 and Dm ≠ -0.0 (invalid operation)\nFPSCR.UFC ← 1 if result is subnormal (underflow)\nFPSCR.OFC ← 1 if result overflows\nFPSCR.IXC ← 1 if result is inexact" }, { "mnemonic": "vfma", "architecture": "ARMv8-A", "full_name": "Vector Fused Multiply Accumulate (Double)", "summary": "Fused multiply-add (Double).", "syntax": "VFMA.F64 , , ", "encoding": { "format": "VFP Arith", "binary_pattern": "cond | 1110 | 1 | D | 10 | Vn | Vd | 10 | 11 | N | 0 | M | 0 | Vm", "hex_opcode": "0x0EA00B00", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "1110", "clean": "1110" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "10", "clean": "10" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "11", "clean": "11" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:28 | 27:24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "VFPv4 (Float)", "description": "Performs a fused multiply-accumulate operation on two double-precision values with a third double-precision accumulator value: Qd ← Qd + (Qn × Qm). The operation is a single fused operation with one rounding step, providing higher precision than separate multiply and add instructions. FPSCR exception flags may be set. Requires VFPv4 extension and executes only in A32 instruction set.", "example": "VFMA.F64 q0, q1, q2", "pseudocode": "Qd ← Qd + (Qn × Qm)\nFPSCR.IOC ← 1 if invalid operand\nFPSCR.UFC ← 1 if result underflows\nFPSCR.OFC ← 1 if result overflows\nFPSCR.IXC ← 1 if result is inexact" }, { "mnemonic": "vfms", "architecture": "ARMv8-A", "full_name": "Vector Fused Multiply Subtract (Double)", "summary": "Fused multiply-subtract (Double).", "syntax": "VFMS.F64 , , ", "encoding": { "format": "VFP Arith", "binary_pattern": "cond | 1110 | 1 | D | 10 | Vn | Vd | 10 | 11 | N | 1 | M | 0 | Vm", "hex_opcode": "0x0EA00B40", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "1110", "clean": "1110" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "10", "clean": "10" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "11", "clean": "11" }, { "raw": "N", "clean": "N" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:28 | 27:24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "VFPv4 (Float)", "description": "Performs a fused multiply-subtract on 128-bit NEON registers: computes Qd = Qd - (Qn × Qm) for double-precision (F64) elements with a single rounding step. This VFPv4 instruction is more accurate than separate multiply and subtract operations. Floating-point exception flags in FPSCR may be set; condition codes N, Z, C, V are not directly modified.", "example": "VFMS.F64 q0, q1, q2", "pseudocode": "Qd ← FPMulSubFused(Qd, Qn, Qm);" }, { "mnemonic": "vcmp", "architecture": "ARMv8-A", "full_name": "Vector Compare (Double)", "summary": "Compares two double-precision values.", "syntax": "VCMP.F64
, ", "encoding": { "format": "VFP Compare", "binary_pattern": "cond | 11101 | D | 11 | 0 | 100 | Vd | 10 | 11 | 0 | 1 | M | 0 | Vm", "hex_opcode": "0x0EB40B40", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "11101", "clean": "11101" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "0", "clean": "0" }, { "raw": "100", "clean": "100" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "11", "clean": "11" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Dd", "desc": "Destination 64-bit SIMD/FP register" }, { "name": "Dm", "desc": "Second source 64-bit SIMD/FP register" } ], "extension": "VFP (Float)", "description": "Compares two double-precision floating-point values and sets the FPSCR condition flags based on the comparison result (equal, less than, greater than, or unordered). The instruction does not produce a destination register value; it only updates FPSCR flags (N, Z, C, V). Requires VFP extension and executes only in A32 instruction set.", "example": "VCMP.F64 d0, d2", "pseudocode": "result ← Dd - Dm\nFPSCR.N ← sign bit of result\nFPSCR.Z ← 1 if values equal\nFPSCR.C ← 1 if Dd ≥ Dm\nFPSCR.V ← 1 if either operand is NaN (unordered)" }, { "mnemonic": "vmov", "architecture": "ARMv8-A", "full_name": "Vector Move (Double)", "summary": "Moves data between Double registers.", "syntax": "VMOV.F64
, ", "encoding": { "format": "VFP Move", "binary_pattern": "cond | 11101 | D | 11 | 0 | 000 | Vd | 10 | size | 0 | 1 | M | 0 | Vm", "hex_opcode": "0x0EB00B40", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "11101", "clean": "11101" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "0", "clean": "0" }, { "raw": "000", "clean": "000" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "size", "clean": "size" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Dd", "desc": "Destination 64-bit SIMD/FP register" }, { "name": "Dm", "desc": "Second source 64-bit SIMD/FP register" } ], "extension": "VFP (Float)", "description": "Copies a 64-bit double-precision floating-point value from Dm to Dd with no arithmetic or rounding. This is a register-to-register move within the VFP register file. No condition flags are affected, and this instruction executes unconditionally (though it respects the condition code in A32/T32).", "example": "VMOV.F64 d0, d2", "pseudocode": "Dd ← Dm;" }, { "mnemonic": "vmov", "architecture": "ARMv8-A", "full_name": "Vector Move (Double <-> 2xGPR)", "summary": "Moves a Double register to/from two Core registers.", "syntax": "VMOV , , ", "encoding": { "format": "VFP Transfer", "binary_pattern": "cond | 11000 | 1 | 0 | 0 | Rt2 | Rt | 10 | 11 | 00 | M | 1 | Vm", "hex_opcode": "0x0C400B10", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "11000", "clean": "11000" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "Rt2", "clean": "Rt2" }, { "raw": "Rt", "clean": "Rt" }, { "raw": "10", "clean": "10" }, { "raw": "11", "clean": "11" }, { "raw": "00", "clean": "00" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:28 | 27:23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:10 | 9:8 | 7:6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Rt", "desc": "Low" }, { "name": "Rt2", "desc": "High" }, { "name": "Dm", "desc": "VFP" } ], "extension": "VFP (Float)", "description": "Transfers a 64-bit value between a VFP double-precision register (Dm) and two consecutive ARM core registers (Rt for bits [31:0], Rt2 for bits [63:32]). Direction is determined by the opcode bit pattern: from core to VFP or VFP to core. No condition flags are affected.", "example": "VMOV r3, r4, d2", "pseudocode": "if direction == 'core_to_vfp' then Dm ← Rt2 || Rt; else Rt ← Dm[31:0]; Rt2 ← Dm[63:32];" }, { "mnemonic": "vcvta", "architecture": "ARMv8-A", "full_name": "Vector Convert to Integer (Nearest, Double)", "summary": "Converts double to integer, rounding to nearest.", "syntax": "VCVTA.
.F64 , ", "encoding": { "format": "VFP Convert", "binary_pattern": "111111101 | D | 111 | 1 | 00 | Vd | 10 | 11 | op | 1 | M | 0 | Vm", "hex_opcode": "0xFEBC0B40", "visual_parts": [ { "raw": "111111101", "clean": "111111101" }, { "raw": "D", "clean": "D" }, { "raw": "111", "clean": "111" }, { "raw": "1", "clean": "1" }, { "raw": "00", "clean": "00" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "11", "clean": "11" }, { "raw": "op", "clean": "op" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:19 | 18 | 17:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" }, { "name": "Dm", "desc": "Second source 64-bit SIMD/FP register" } ], "extension": "VFP (Float)", "description": "Converts a 64-bit double-precision floating-point value to a 32-bit integer, rounding to nearest (away from zero on tie). Executes conditionally in A32 and writes the integer result to a 32-bit floating-point register. No condition flags are affected by this instruction.", "example": "VCVTA.dt.F64 s0, d2", "pseudocode": "if ConditionPassed() then\n Sd = ConvertToInt(Dm, RoundingMode=RoundToNearest)" }, { "mnemonic": "vcvtn", "architecture": "ARMv8-A", "full_name": "Vector Convert to Integer (Nearest Even, Double)", "summary": "Converts double to integer, rounding to nearest even.", "syntax": "VCVTN.
.F64 , ", "encoding": { "format": "VFP Convert", "binary_pattern": "111111101 | D | 111 | 1 | 01 | Vd | 10 | 11 | op | 1 | M | 0 | Vm", "hex_opcode": "0xFEBD0B40", "visual_parts": [ { "raw": "111111101", "clean": "111111101" }, { "raw": "D", "clean": "D" }, { "raw": "111", "clean": "111" }, { "raw": "1", "clean": "1" }, { "raw": "01", "clean": "01" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "11", "clean": "11" }, { "raw": "op", "clean": "op" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:19 | 18 | 17:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" }, { "name": "Dm", "desc": "Second source 64-bit SIMD/FP register" } ], "extension": "VFP (Float)", "description": "Converts a 64-bit double-precision floating-point value to a 32-bit integer, rounding to nearest even (banker's rounding). Executes conditionally in A32 and writes the integer result to a 32-bit floating-point register. No condition flags are affected by this instruction.", "example": "VCVTN.dt.F64 s0, d2", "pseudocode": "if ConditionPassed() then\n Sd = ConvertToInt(Dm, RoundingMode=RoundToNearestEven)" }, { "mnemonic": "vcvt", "architecture": "ARMv8-A", "full_name": "Vector Convert (Fixed Point)", "summary": "Converts between floating-point and fixed-point.", "syntax": "VCVT.. , , #", "encoding": { "format": "VFP Convert", "binary_pattern": "cond | 11101 | D | 11 | 1 | 1 | 1 | U | Vd | 10 | 10 | sx | 1 | i | 0 | imm4", "hex_opcode": "0x0EBE0A40", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "11101", "clean": "11101" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "U", "clean": "U" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "sx", "clean": "sx" }, { "raw": "1", "clean": "1" }, { "raw": "i", "clean": "i" }, { "raw": "0", "clean": "0" }, { "raw": "imm4", "clean": "imm4" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18 | 17 | 16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" }, { "name": "fbits", "desc": "Number of fractional bits" } ], "extension": "VFP (Float)", "description": "Converts between floating-point and fixed-point formats in 128-bit SIMD registers with a specified number of fractional bits. This is a NEON instruction that operates element-wise on the vector operands. No condition flags are affected.", "example": "VCVT.Td.Tm q0, q2, #8", "pseudocode": "if ConditionPassed() then\n for i = 0 to elements-1\n if Tm == F32 then\n Qd[i] = FixedPointConvert(Qm[i], fbits)\n else\n Qd[i] = FloatingPointConvert(Qm[i], fbits)" }, { "mnemonic": "addg", "architecture": "ARMv8-A", "full_name": "Add with Tag", "summary": "Adds an immediate to an address, modifying the Allocation Tag (MTE).", "syntax": "ADDG , , #, #", "encoding": { "format": "Data Processing", "binary_pattern": "1 | 0 | 0 | 1000110 | uimm6 | 00 | uimm4 | Xn | Xd", "hex_opcode": "0x91800000", "visual_parts": [ { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "1000110", "clean": "1000110" }, { "raw": "uimm6", "clean": "uimm6" }, { "raw": "00", "clean": "00" }, { "raw": "uimm4", "clean": "uimm4" }, { "raw": "Xn", "clean": "Xn" }, { "raw": "Xd", "clean": "Xd" } ], "bit_positions": "31 | 30 | 29 | 28:22 | 21:16 | 15:14 | 13:10 | 9:5 | 4:0" }, "operands": [ { "name": "Xd", "desc": "Destination 64-bit integer register" }, { "name": "Xn", "desc": "First source / base 64-bit integer register" }, { "name": "uimm6", "desc": "Address Offset" }, { "name": "uimm4", "desc": "Tag Offset" } ], "extension": "MTE (Memory Tagging)", "description": "Adds a scaled immediate offset (uimm6 × 16) to an address in the source register and simultaneously updates the Memory Tagging Extension (MTE) Allocation Tag in bits [59:56] by adding uimm4. The result is stored in the destination register. This is an AArch64-only instruction that modifies both address and tag atomically. No condition flags are affected.", "example": "ADDG x0, x1, #8, #3", "pseudocode": "address_offset ← uimm6 × 16\ntag_offset ← uimm4\nif Xn == SP then\n Xd ← (Xn + address_offset)[63:0]\n Xd[59:56] ← (Xn[59:56] + tag_offset) AND 0xF\nelse\n Xd ← (Xn + address_offset)[63:0]\n Xd[59:56] ← (Xn[59:56] + tag_offset) AND 0xF" }, { "mnemonic": "subg", "architecture": "ARMv8-A", "full_name": "Subtract with Tag", "summary": "Subtracts an immediate from an address, modifying the Allocation Tag (MTE).", "syntax": "SUBG , , #, #", "encoding": { "format": "Data Processing", "binary_pattern": "1 | 1 | 0 | 1000110 | uimm6 | 00 | uimm4 | Xn | Xd", "hex_opcode": "0xD1800000", "visual_parts": [ { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "1000110", "clean": "1000110" }, { "raw": "uimm6", "clean": "uimm6" }, { "raw": "00", "clean": "00" }, { "raw": "uimm4", "clean": "uimm4" }, { "raw": "Xn", "clean": "Xn" }, { "raw": "Xd", "clean": "Xd" } ], "bit_positions": "31 | 30 | 29 | 28:22 | 21:16 | 15:14 | 13:10 | 9:5 | 4:0" }, "operands": [ { "name": "Xd", "desc": "Destination 64-bit integer register" }, { "name": "Xn", "desc": "First source / base 64-bit integer register" }, { "name": "uimm6", "desc": "Address Offset" }, { "name": "uimm4", "desc": "Tag Offset" } ], "extension": "MTE (Memory Tagging)", "description": "Subtracts a scaled immediate offset (uimm6 × 16) from an address in the source register and simultaneously updates the Memory Tagging Extension (MTE) Allocation Tag in bits [59:56] by adding uimm4. The result is stored in the destination register. This is an AArch64-only instruction that modifies both address and tag atomically. No condition flags are affected.", "example": "SUBG x0, x1, #8, #3", "pseudocode": "address_offset ← uimm6 × 16\ntag_offset ← uimm4\nif Xn == SP then\n Xd ← (Xn - address_offset)[63:0]\n Xd[59:56] ← (Xn[59:56] + tag_offset) AND 0xF\nelse\n Xd ← (Xn - address_offset)[63:0]\n Xd[59:56] ← (Xn[59:56] + tag_offset) AND 0xF" }, { "mnemonic": "cosp", "architecture": "ARMv8-A", "full_name": "Call Out Speculation", "summary": "Prevents speculation from determining that the instruction is executed.", "syntax": "COSP ", "encoding": { "format": "System", "binary_pattern": "1101010100 | 0 | 01 | 011 | 0111 | 0011 | 110 | Rt", "hex_opcode": "0xD50B73C0", "visual_parts": [ { "raw": "1101010100", "clean": "1101010100" }, { "raw": "0", "clean": "0" }, { "raw": "01", "clean": "01" }, { "raw": "011", "clean": "011" }, { "raw": "0111", "clean": "0111" }, { "raw": "0011", "clean": "0011" }, { "raw": "110", "clean": "110" }, { "raw": "Rt", "clean": "Rt" } ], "bit_positions": "31:22 | 21 | 20:19 | 18:16 | 15:12 | 11:8 | 7:5 | 4:0" }, "operands": [ { "name": "Xt", "desc": "Reg" } ], "extension": "FEAT_CSV3 (Speculation)", "description": "Call Out Speculation: prevents speculation from reaching instructions beyond this point until the operand register is committed. This instruction is part of the CSV3 speculation control feature and executes in AArch64 state only. It does not affect any condition flags and requires the source register value to be resolved before execution can proceed speculatively.", "example": "COSP x3", "pseudocode": "if FEAT_CSV3 == '0' then\n UNDEFINED\nelse\n CommitSpeculation(X[t])" }, { "mnemonic": "cpp", "architecture": "ARMv8-A", "full_name": "Cache Prefetch Prediction Pruning", "summary": "Prevents cache prefetch prediction past this instruction.", "syntax": "CPPP ", "encoding": { "format": "System", "binary_pattern": "1101010100 | 0 | 01 | 011 | 0111 | 0011 | 111 | Rt", "hex_opcode": "0xD50B73E0", "visual_parts": [ { "raw": "1101010100", "clean": "1101010100" }, { "raw": "0", "clean": "0" }, { "raw": "01", "clean": "01" }, { "raw": "011", "clean": "011" }, { "raw": "0111", "clean": "0111" }, { "raw": "0011", "clean": "0011" }, { "raw": "111", "clean": "111" }, { "raw": "Rt", "clean": "Rt" } ], "bit_positions": "31:22 | 21 | 20:19 | 18:16 | 15:12 | 11:8 | 7:5 | 4:0" }, "operands": [ { "name": "Xt", "desc": "Reg" } ], "extension": "FEAT_CPP", "description": "Prevents cache prefetch prediction from reordering beyond this instruction, allowing precise control over cache prefetch behavior. This is an AArch64-only instruction requiring FEAT_CPP (Cache Prefetch Prediction). The source register Xt is ignored; the instruction acts as a prefetch prediction barrier. No condition flags are affected.", "example": "CPPP x3", "pseudocode": "Cache_Prefetch_Prediction_Barrier()" }, { "mnemonic": "rcwswpp", "architecture": "ARMv8-A", "full_name": "Read Check Write Swap Pair", "summary": "Atomically swaps a 128-bit register pair with a checked descriptor in memory (Translation Hardening).", "syntax": "RCWSWPP , , []", "encoding": { "format": "Atomic", "binary_pattern": "0 | 0 | 011001 | 0 | 0 | 1 | Rt2 | 1 | 010 | 00 | Rn | Rt", "hex_opcode": "0x1920A000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "011001", "clean": "011001" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "Rt2", "clean": "Rt2" }, { "raw": "1", "clean": "1" }, { "raw": "010", "clean": "010" }, { "raw": "00", "clean": "00" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rt", "clean": "Rt" } ], "bit_positions": "31 | 30 | 29:24 | 23 | 22 | 21 | 20:16 | 15 | 14:12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Xt", "desc": "Data/Status" }, { "name": "Xt+1", "desc": "Second register of the data pair" }, { "name": "Xn", "desc": "Address" } ], "extension": "FEAT_THE (Hardening)", "description": "Atomically reads a 128-bit translation table descriptor from memory, checks its validity, and conditionally writes it back with hardening constraints (FEAT_THE). The instruction requires 128-bit alignment and is available only in AArch64. Acquire-Release semantics are not applied; results are returned in a pair of 64-bit registers with status flags.", "example": "RCWSWPP x2, x3, [x1]", "pseudocode": "address ← Xn; data ← Mem[address, 16]; ValidateAndProcess(data); if validated then Mem[address, 16] ← data; Xt ← data[63:0]; Xt+1 ← data[127:64];" }, { "mnemonic": "ldff1b", "architecture": "ARMv8-A", "full_name": "SVE Load First-Fault Contiguous Bytes", "summary": "Loads bytes speculatively; suppresses faults after the first active element.", "syntax": "LDFF1B { .B }, /Z, []", "encoding": { "format": "SVE Load", "binary_pattern": "1010010 | 000 | 0 | Rm | 011 | Pg | Rn | Zt", "hex_opcode": "0xA4006000", "visual_parts": [ { "raw": "1010010", "clean": "1010010" }, { "raw": "000", "clean": "000" }, { "raw": "0", "clean": "0" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "011", "clean": "011" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Zt", "clean": "Zt" } ], "bit_positions": "31:25 | 24:22 | 21 | 20:16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zt", "desc": "Transfer scalable vector register (SVE load/store)" }, { "name": "Pg", "desc": "Predicate" }, { "name": "Xn", "desc": "First source / base 64-bit integer register" } ], "extension": "SVE", "description": "Loads bytes from memory into a scalable vector register with first-fault semantics; subsequent faults are suppressed if any active element has already been loaded. Only elements where the predicate is true are loaded. This instruction is AArch64-only and requires SVE. No condition flags are set.", "example": "LDFF1B p0/m/Z, [x1]", "pseudocode": "for i ← 0 to (VL/8 - 1) do if Pg[i] then Zt[i*8+7:i*8] ← [Xn + i]; faulted ← false; end if; if fault_occurs and faulted then suppress_fault; faulted ← true; end if; end for" }, { "mnemonic": "ldff1h", "architecture": "ARMv8-A", "full_name": "SVE Load First-Fault Contiguous Halfwords", "summary": "Loads halfwords speculatively; suppresses faults after the first active element.", "syntax": "LDFF1H { .H }, /Z, []", "encoding": { "format": "SVE Load", "binary_pattern": "1010010 | 010 | 1 | Rm | 011 | Pg | Rn | Zt", "hex_opcode": "0xA4A06000", "visual_parts": [ { "raw": "1010010", "clean": "1010010" }, { "raw": "010", "clean": "010" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "011", "clean": "011" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Zt", "clean": "Zt" } ], "bit_positions": "31:25 | 24:22 | 21 | 20:16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zt", "desc": "Transfer scalable vector register (SVE load/store)" }, { "name": "Pg", "desc": "Predicate" }, { "name": "Xn", "desc": "First source / base 64-bit integer register" } ], "extension": "SVE", "description": "Loads halfwords from memory into a scalable vector register with first-fault semantics; subsequent faults are suppressed if any active element has already been loaded. Only elements where the predicate is true are loaded. This instruction is AArch64-only and requires SVE. No condition flags are set.", "example": "LDFF1H p0/m/Z, [x1]", "pseudocode": "for i ← 0 to (VL/16 - 1) do if Pg[i] then Zt[i*16+15:i*16] ← [Xn + i*2]; faulted ← false; end if; if fault_occurs and faulted then suppress_fault; faulted ← true; end if; end for" }, { "mnemonic": "ldff1w", "architecture": "ARMv8-A", "full_name": "SVE Load First-Fault Contiguous Words", "summary": "Loads words speculatively; suppresses faults after the first active element.", "syntax": "LDFF1W { .S }, /Z, []", "encoding": { "format": "SVE Load", "binary_pattern": "1000010 | 1 | 0 | xs | 0 | Zm | 0 | 1 | 1 | Pg | Rn | Zt", "hex_opcode": "0x85006000", "visual_parts": [ { "raw": "1000010", "clean": "1000010" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "xs", "clean": "xs" }, { "raw": "0", "clean": "0" }, { "raw": "Zm", "clean": "Zm" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Zt", "clean": "Zt" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21 | 20:16 | 15 | 14 | 13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zt", "desc": "Transfer scalable vector register (SVE load/store)" }, { "name": "Pg", "desc": "Predicate" }, { "name": "Xn", "desc": "First source / base 64-bit integer register" } ], "extension": "SVE", "description": "Loads words from memory into a scalable vector register with first-fault semantics; subsequent faults are suppressed if any active element has already been loaded. Only elements where the predicate is true are loaded. This instruction is AArch64-only and requires SVE. No condition flags are set.", "example": "LDFF1W p0/m/Z, [x1]", "pseudocode": "for i ← 0 to (VL/32 - 1) do if Pg[i] then Zt[i*32+31:i*32] ← [Xn + i*4]; faulted ← false; end if; if fault_occurs and faulted then suppress_fault; faulted ← true; end if; end for" }, { "mnemonic": "ldff1d", "architecture": "ARMv8-A", "full_name": "SVE Load First-Fault Contiguous Doublewords", "summary": "Loads doublewords speculatively; suppresses faults after the first active element.", "syntax": "LDFF1D { .D }, /Z, []", "encoding": { "format": "SVE Load", "binary_pattern": "1100010 | 1 | 1 | 10 | Zm | 1 | 1 | 1 | Pg | Rn | Zt", "hex_opcode": "0xC5C0E000", "visual_parts": [ { "raw": "1100010", "clean": "1100010" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "10", "clean": "10" }, { "raw": "Zm", "clean": "Zm" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Zt", "clean": "Zt" } ], "bit_positions": "31:25 | 24 | 23 | 22:21 | 20:16 | 15 | 14 | 13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zt", "desc": "Transfer scalable vector register (SVE load/store)" }, { "name": "Pg", "desc": "Predicate" }, { "name": "Xn", "desc": "First source / base 64-bit integer register" } ], "extension": "SVE", "description": "Loads doublewords from memory into a scalable vector register with first-fault semantics; subsequent faults are suppressed if any active element has already been loaded. Only elements where the predicate is true are loaded. This instruction is AArch64-only and requires SVE. No condition flags are set.", "example": "LDFF1D p0/m/Z, [x1]", "pseudocode": "for i ← 0 to (VL/64 - 1) do if Pg[i] then Zt[i*64+63:i*64] ← [Xn + i*8]; faulted ← false; end if; if fault_occurs and faulted then suppress_fault; faulted ← true; end if; end for" }, { "mnemonic": "ldnf1b", "architecture": "ARMv8-A", "full_name": "SVE Load Non-Fault Contiguous Bytes", "summary": "Loads bytes without faulting; returns 0 if fault occurs.", "syntax": "LDNF1B { .B }, /Z, []", "encoding": { "format": "SVE Load", "binary_pattern": "1010010 | 000 | 0 | 1 | imm4 | 101 | Pg | Rn | Zt", "hex_opcode": "0xA410A000", "visual_parts": [ { "raw": "1010010", "clean": "1010010" }, { "raw": "000", "clean": "000" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "imm4", "clean": "imm4" }, { "raw": "101", "clean": "101" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Zt", "clean": "Zt" } ], "bit_positions": "31:25 | 24:22 | 21 | 20 | 19:16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zt", "desc": "Transfer scalable vector register (SVE load/store)" }, { "name": "Pg", "desc": "Predicate" }, { "name": "Xn", "desc": "First source / base 64-bit integer register" } ], "extension": "SVE", "description": "Loads bytes from memory into a scalable vector register without raising faults; elements that would fault are loaded as zero. Only elements where the predicate is true are accessed. This instruction is AArch64-only and requires SVE. No condition flags are set.", "example": "LDNF1B p0/m/Z, [x1]", "pseudocode": "for i ← 0 to (VL/8 - 1) do if Pg[i] then if fault_would_occur then Zt[i*8+7:i*8] ← 0; else Zt[i*8+7:i*8] ← [Xn + i]; end if; end if; end for" }, { "mnemonic": "ldnf1h", "architecture": "ARMv8-A", "full_name": "SVE Load Non-Fault Contiguous Halfwords", "summary": "Loads halfwords without faulting.", "syntax": "LDNF1H { .H }, /Z, []", "encoding": { "format": "SVE Load", "binary_pattern": "1010010 | 010 | 1 | 1 | imm4 | 101 | Pg | Rn | Zt", "hex_opcode": "0xA4B0A000", "visual_parts": [ { "raw": "1010010", "clean": "1010010" }, { "raw": "010", "clean": "010" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "imm4", "clean": "imm4" }, { "raw": "101", "clean": "101" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Zt", "clean": "Zt" } ], "bit_positions": "31:25 | 24:22 | 21 | 20 | 19:16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zt", "desc": "Transfer scalable vector register (SVE load/store)" }, { "name": "Pg", "desc": "Predicate" }, { "name": "Xn", "desc": "First source / base 64-bit integer register" } ], "extension": "SVE", "description": "Loads halfwords from memory into a scalable vector register without raising faults; elements that would fault are loaded as zero. Only elements where the predicate is true are accessed. This instruction is AArch64-only and requires SVE. No condition flags are set.", "example": "LDNF1H p0/m/Z, [x1]", "pseudocode": "for i ← 0 to (VL/16 - 1) do if Pg[i] then if fault_would_occur then Zt[i*16+15:i*16] ← 0; else Zt[i*16+15:i*16] ← [Xn + i*2]; end if; end if; end for" }, { "mnemonic": "ldnf1w", "architecture": "ARMv8-A", "full_name": "SVE Load Non-Fault Contiguous Words", "summary": "Loads words without faulting.", "syntax": "LDNF1W { .S }, /Z, []", "encoding": { "format": "SVE Load", "binary_pattern": "1010010 | 101 | 0 | 1 | imm4 | 101 | Pg | Rn | Zt", "hex_opcode": "0xA550A000", "visual_parts": [ { "raw": "1010010", "clean": "1010010" }, { "raw": "101", "clean": "101" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "imm4", "clean": "imm4" }, { "raw": "101", "clean": "101" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Zt", "clean": "Zt" } ], "bit_positions": "31:25 | 24:22 | 21 | 20 | 19:16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zt", "desc": "Transfer scalable vector register (SVE load/store)" }, { "name": "Pg", "desc": "Predicate" }, { "name": "Xn", "desc": "First source / base 64-bit integer register" } ], "extension": "SVE", "description": "Loads words from memory into a scalable vector register without raising faults; elements that would fault are loaded as zero. Only elements where the predicate is true are accessed. This instruction is AArch64-only and requires SVE. No condition flags are set.", "example": "LDNF1W p0/m/Z, [x1]", "pseudocode": "for i ← 0 to (VL/32 - 1) do if Pg[i] then if fault_would_occur then Zt[i*32+31:i*32] ← 0; else Zt[i*32+31:i*32] ← [Xn + i*4]; end if; end if; end for" }, { "mnemonic": "ldnf1d", "architecture": "ARMv8-A", "full_name": "SVE Load Non-Fault Contiguous Doublewords", "summary": "Loads doublewords without faulting.", "syntax": "LDNF1D { .D }, /Z, []", "encoding": { "format": "SVE Load", "binary_pattern": "1010010 | 111 | 1 | 1 | imm4 | 101 | Pg | Rn | Zt", "hex_opcode": "0xA5F0A000", "visual_parts": [ { "raw": "1010010", "clean": "1010010" }, { "raw": "111", "clean": "111" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "imm4", "clean": "imm4" }, { "raw": "101", "clean": "101" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Zt", "clean": "Zt" } ], "bit_positions": "31:25 | 24:22 | 21 | 20 | 19:16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zt", "desc": "Transfer scalable vector register (SVE load/store)" }, { "name": "Pg", "desc": "Predicate" }, { "name": "Xn", "desc": "First source / base 64-bit integer register" } ], "extension": "SVE", "description": "Loads contiguous doublewords (64-bit elements) from memory into a scalable vector register without generating a fault if a load would be out-of-bounds or inaccessible. Only elements where the corresponding predicate bit in Pg is true are loaded; others are zeroed in the destination Zt. This instruction is AArch64-only, requires SVE support, and does not affect condition flags.", "example": "LDNF1D p0/m/Z, [x1]", "pseudocode": "for i = 0 to VL/64-1\n if Pg[i] == 1 then\n Zt.D[i] ← [Xn + (i × 8)]\n else\n Zt.D[i] ← 0\n endif\nendfor" }, { "mnemonic": "whilelo", "architecture": "ARMv8-A", "full_name": "SVE While Lower (Unsigned)", "summary": "Generates predicate for unsigned loop (while Xn < Xm).", "syntax": "WHILELO ., , ", "encoding": { "format": "SVE Compare", "binary_pattern": "00100101 | size | 1 | Rm | 000 | sf | 1 | 1 | Rn | 0 | Pd", "hex_opcode": "0x25200C00", "visual_parts": [ { "raw": "00100101", "clean": "00100101" }, { "raw": "size", "clean": "size" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "000", "clean": "000" }, { "raw": "sf", "clean": "sf" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "0", "clean": "0" }, { "raw": "Pd", "clean": "Pd" } ], "bit_positions": "31:24 | 23:22 | 21 | 20:16 | 15:13 | 12 | 11 | 10 | 9:5 | 4 | 3:0" }, "operands": [ { "name": "Pd", "desc": "Destination predicate register (SVE)" }, { "name": "Xn", "desc": "Start" }, { "name": "Xm", "desc": "Limit" } ], "extension": "SVE", "description": "Generates a predicate where each element is true if the corresponding loop counter (Xn + element_index) is less than Xm (unsigned comparison). The output predicate Pd has element width determined by (byte, halfword, word, or doubleword). This is an AArch64-only SVE instruction; all condition flags are unaffected.", "example": "WHILELO p0.T, x1, x2", "pseudocode": "element_size ← size_in_bytes()\nfor i = 0 to VL/element_size-1\n if (Xn + i) < Xm then\n Pd[i] ← 1\n else\n Pd[i] ← 0\n endif\nendfor" }, { "mnemonic": "whilels", "architecture": "ARMv8-A", "full_name": "SVE While Lower or Same (Unsigned)", "summary": "Generates predicate for unsigned loop (while Xn <= Xm).", "syntax": "WHILELS ., , ", "encoding": { "format": "SVE Compare", "binary_pattern": "00100101 | size | 1 | Rm | 000 | sf | 1 | 1 | Rn | 1 | Pd", "hex_opcode": "0x25200C10", "visual_parts": [ { "raw": "00100101", "clean": "00100101" }, { "raw": "size", "clean": "size" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "000", "clean": "000" }, { "raw": "sf", "clean": "sf" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "1", "clean": "1" }, { "raw": "Pd", "clean": "Pd" } ], "bit_positions": "31:24 | 23:22 | 21 | 20:16 | 15:13 | 12 | 11 | 10 | 9:5 | 4 | 3:0" }, "operands": [ { "name": "Pd", "desc": "Destination predicate register (SVE)" }, { "name": "Xn", "desc": "Start" }, { "name": "Xm", "desc": "Limit" } ], "extension": "SVE", "description": "Generates a predicate where each element is true if the corresponding loop counter (Xn + element_index) is less than or equal to Xm (unsigned comparison). The output predicate Pd has element width determined by . This is an AArch64-only SVE instruction; all condition flags are unaffected.", "example": "WHILELS p0.T, x1, x2", "pseudocode": "element_size ← size_in_bytes()\nfor i = 0 to VL/element_size-1\n if (Xn + i) <= Xm then\n Pd[i] ← 1\n else\n Pd[i] ← 0\n endif\nendfor" }, { "mnemonic": "whilehi", "architecture": "ARMv8-A", "full_name": "SVE While Higher (Unsigned)", "summary": "Generates predicate for unsigned loop (while Xn > Xm).", "syntax": "WHILEHI ., , ", "encoding": { "format": "SVE Compare", "binary_pattern": "00100101 | size | 1 | Rm | 000 | sf | 1 | 0 | Rn | 1 | Pd", "hex_opcode": "0x25200810", "visual_parts": [ { "raw": "00100101", "clean": "00100101" }, { "raw": "size", "clean": "size" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "000", "clean": "000" }, { "raw": "sf", "clean": "sf" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "1", "clean": "1" }, { "raw": "Pd", "clean": "Pd" } ], "bit_positions": "31:24 | 23:22 | 21 | 20:16 | 15:13 | 12 | 11 | 10 | 9:5 | 4 | 3:0" }, "operands": [ { "name": "Pd", "desc": "Destination predicate register (SVE)" }, { "name": "Xn", "desc": "Start" }, { "name": "Xm", "desc": "Limit" } ], "extension": "SVE", "description": "Generates a predicate where each element is true if the corresponding loop counter (Xn + element_index) is greater than Xm (unsigned comparison). The output predicate Pd has element width determined by . This is an AArch64-only SVE instruction; all condition flags are unaffected.", "example": "WHILEHI p0.T, x1, x2", "pseudocode": "element_size ← size_in_bytes()\nfor i = 0 to VL/element_size-1\n if (Xn + i) > Xm then\n Pd[i] ← 1\n else\n Pd[i] ← 0\n endif\nendfor" }, { "mnemonic": "whilehs", "architecture": "ARMv8-A", "full_name": "SVE While Higher or Same (Unsigned)", "summary": "Generates predicate for unsigned loop (while Xn >= Xm).", "syntax": "WHILEHS ., , ", "encoding": { "format": "SVE Compare", "binary_pattern": "00100101 | size | 1 | Rm | 000 | sf | 1 | 0 | Rn | 0 | Pd", "hex_opcode": "0x25200800", "visual_parts": [ { "raw": "00100101", "clean": "00100101" }, { "raw": "size", "clean": "size" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "000", "clean": "000" }, { "raw": "sf", "clean": "sf" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "0", "clean": "0" }, { "raw": "Pd", "clean": "Pd" } ], "bit_positions": "31:24 | 23:22 | 21 | 20:16 | 15:13 | 12 | 11 | 10 | 9:5 | 4 | 3:0" }, "operands": [ { "name": "Pd", "desc": "Destination predicate register (SVE)" }, { "name": "Xn", "desc": "Start" }, { "name": "Xm", "desc": "Limit" } ], "extension": "SVE", "description": "Generates a predicate where each element is true if the corresponding loop counter (Xn + element_index) is greater than or equal to Xm (unsigned comparison). The output predicate Pd has element width determined by . This is an AArch64-only SVE instruction; all condition flags are unaffected.", "example": "WHILEHS p0.T, x1, x2", "pseudocode": "element_size ← size_in_bytes()\nfor i = 0 to VL/element_size-1\n if (Xn + i) >= Xm then\n Pd[i] ← 1\n else\n Pd[i] ← 0\n endif\nendfor" }, { "mnemonic": "cntp", "architecture": "ARMv8-A", "full_name": "SVE Count Active Predicates", "summary": "Counts the number of true elements in a predicate.", "syntax": "CNTP , , .", "encoding": { "format": "SVE Count", "binary_pattern": "00100101 | size | 100 | 00 | 0 | 10 | Pg | 0 | Pn | Rd", "hex_opcode": "0x25208000", "visual_parts": [ { "raw": "00100101", "clean": "00100101" }, { "raw": "size", "clean": "size" }, { "raw": "100", "clean": "100" }, { "raw": "00", "clean": "00" }, { "raw": "0", "clean": "0" }, { "raw": "10", "clean": "10" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "0", "clean": "0" }, { "raw": "Pn", "clean": "Pn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31:24 | 23:22 | 21:19 | 18:17 | 16 | 15:14 | 13:10 | 9 | 8:5 | 4:0" }, "operands": [ { "name": "Xn", "desc": "Dest GPR" }, { "name": "Pg", "desc": "Mask" }, { "name": "Pn", "desc": "First source predicate register (SVE)" } ], "extension": "SVE", "description": "Counts the number of true bits in Pn.T (where the element size determines the predicate width) that are also true in the governing predicate Pg, and writes the 64-bit count to the general-purpose register Xn. This is an AArch64-only SVE instruction; all condition flags are unaffected.", "example": "CNTP x1, p0/m, p1.T", "pseudocode": "count ← 0\nelement_size ← size_in_bytes()\nfor i = 0 to VL/element_size-1\n if Pg[i] == 1 and Pn[i] == 1 then\n count ← count + 1\n endif\nendfor\nXn ← count" }, { "mnemonic": "ptest", "architecture": "ARMv8-A", "full_name": "SVE Predicate Test", "summary": "Updates processor flags (NZCV) based on predicate state.", "syntax": "PTEST , .B", "encoding": { "format": "SVE Predicate", "binary_pattern": "00 | 100101 | 0 | 1 | 01 | 000011 | Pg | 0 | Pn | 0 | 0 | 0 | 0 | 0", "hex_opcode": "0x2550C000", "visual_parts": [ { "raw": "00", "clean": "00" }, { "raw": "100101", "clean": "100101" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "01", "clean": "01" }, { "raw": "000011", "clean": "000011" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "0", "clean": "0" }, { "raw": "Pn", "clean": "Pn" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" } ], "bit_positions": "31:30 | 29:24 | 23 | 22 | 21:20 | 19:14 | 13:10 | 9 | 8:5 | 4 | 3 | 2 | 1 | 0" }, "operands": [ { "name": "Pg", "desc": "Mask" }, { "name": "Pn", "desc": "First source predicate register (SVE)" } ], "extension": "SVE", "description": "Tests the predicate Pn.B (byte-wide elements) under the control of governing predicate Pg and updates the condition flags (N, Z, C, V) to indicate the result. Sets Z=1 if all tested elements are false, C=1 if any tested element is true, N and V are set according to the logical AND and OR of tested bits. This is an AArch64-only SVE instruction.", "example": "PTEST p0/m, p1.B", "pseudocode": "result_any ← 0\nresult_all ← 1\nfor i = 0 to VL/8-1\n if Pg[i] == 1 then\n if Pn[i] == 1 then\n result_any ← 1\n result_all ← result_all AND 1\n else\n result_all ← 0\n endif\n endif\nendfor\nZ ← (result_any == 0)\nC ← result_any\nN ← result_all\nV ← 0" }, { "mnemonic": "pfirst", "architecture": "ARMv8-A", "full_name": "SVE Predicate First Active", "summary": "Sets destination predicate to true only at the first active element.", "syntax": "PFIRST .B, , .B", "encoding": { "format": "SVE Predicate", "binary_pattern": "00100101 | 0 | 1 | 011000110000 | 0 | Pg | 0 | Pdn", "hex_opcode": "0x2558C000", "visual_parts": [ { "raw": "00100101", "clean": "00100101" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "011000110000", "clean": "011000110000" }, { "raw": "0", "clean": "0" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "0", "clean": "0" }, { "raw": "Pdn", "clean": "Pdn" } ], "bit_positions": "31:24 | 23 | 22 | 21:10 | 9 | 8:5 | 4 | 3:0" }, "operands": [ { "name": "Pd", "desc": "Dest Pred" }, { "name": "Pg", "desc": "Mask" }, { "name": "Pn", "desc": "First source predicate register (SVE)" } ], "extension": "SVE", "description": "Sets the destination predicate Pd.B such that only the first element (in vector order) where both Pg and Pn are true is set to true; all other elements are set to false. This is useful for scalar tail-processing in loops. This is an AArch64-only SVE instruction; all condition flags are unaffected.", "example": "PFIRST p0.B, p0/m, p1.B", "pseudocode": "for i = 0 to VL/8-1\n if Pg[i] == 1 and Pn[i] == 1 then\n Pd[i] ← 1\n break\n else\n Pd[i] ← 0\n endif\nendfor\nfor j = i+1 to VL/8-1\n Pd[j] ← 0\nendfor" }, { "mnemonic": "clasta", "architecture": "ARMv8-A", "full_name": "SVE Conditional Last Element After", "summary": "Extracts element after the last active element.", "syntax": "CLASTA , , , .", "encoding": { "format": "SVE Extract", "binary_pattern": "00000101 | size | 11000 | 0 | 101 | Pg | Zm | Rdn", "hex_opcode": "0x0530A000", "visual_parts": [ { "raw": "00000101", "clean": "00000101" }, { "raw": "size", "clean": "size" }, { "raw": "11000", "clean": "11000" }, { "raw": "0", "clean": "0" }, { "raw": "101", "clean": "101" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zm", "clean": "Zm" }, { "raw": "Rdn", "clean": "Rdn" } ], "bit_positions": "31:24 | 23:22 | 21:17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Rdn", "desc": "Dest/Fallback" }, { "name": "Pg", "desc": "Predicate" }, { "name": "Zm", "desc": "Vector" } ], "extension": "SVE", "description": "Extracts the element immediately after the last active element (as determined by the predicate) from a SVE vector and writes it to a scalar register; if no active elements exist, the destination register is unchanged. This instruction operates only in AArch64 state and does not modify the condition flags.", "example": "CLASTA r0, p0/m, r0, z2.s.T", "pseudocode": "activecount ← CountActiveLanes(Pg, esize)\nif activecount == VL/esize then\n Rdn ← Zm[0]\nelse if activecount > 0 then\n Rdn ← Zm[activecount]\nelse\n Rdn ← Rdn" }, { "mnemonic": "clastb", "architecture": "ARMv8-A", "full_name": "SVE Conditional Last Element Before", "summary": "Extracts the last active element.", "syntax": "CLASTB , , , .", "encoding": { "format": "SVE Extract", "binary_pattern": "00000101 | size | 11000 | 1 | 101 | Pg | Zm | Rdn", "hex_opcode": "0x0531A000", "visual_parts": [ { "raw": "00000101", "clean": "00000101" }, { "raw": "size", "clean": "size" }, { "raw": "11000", "clean": "11000" }, { "raw": "1", "clean": "1" }, { "raw": "101", "clean": "101" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zm", "clean": "Zm" }, { "raw": "Rdn", "clean": "Rdn" } ], "bit_positions": "31:24 | 23:22 | 21:17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Rdn", "desc": "Dest/Fallback" }, { "name": "Pg", "desc": "Predicate" }, { "name": "Zm", "desc": "Vector" } ], "extension": "SVE", "description": "Extracts the last active element (as determined by the predicate) from a SVE vector and writes it to a scalar register; if no active elements exist, the destination register is unchanged. This instruction operates only in AArch64 state and does not modify the condition flags.", "example": "CLASTB r0, p0/m, r0, z2.s.T", "pseudocode": "activecount ← CountActiveLanes(Pg, esize)\nif activecount > 0 then\n Rdn ← Zm[activecount - 1]\nelse\n Rdn ← Rdn" }, { "mnemonic": "lasta", "architecture": "ARMv8-A", "full_name": "SVE Extract Last Element After", "summary": "Extracts element after last active (SIMD scalar destination).", "syntax": "LASTA ., , .", "encoding": { "format": "SVE Extract", "binary_pattern": "00000101 | size | 10001 | 0 | 100 | Pg | Zn | Vd", "hex_opcode": "0x05228000", "visual_parts": [ { "raw": "00000101", "clean": "00000101" }, { "raw": "size", "clean": "size" }, { "raw": "10001", "clean": "10001" }, { "raw": "0", "clean": "0" }, { "raw": "100", "clean": "100" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Vd", "clean": "Vd" } ], "bit_positions": "31:24 | 23:22 | 21:17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Vd", "desc": "Dest Scalar" }, { "name": "Pg", "desc": "Predicate" }, { "name": "Zn", "desc": "Vector" } ], "extension": "SVE", "description": "Extracts the element immediately after the last active element (as determined by the predicate) from a SVE vector and writes it to a SIMD scalar register; if no active elements exist, the destination register is unchanged. This instruction operates only in AArch64 state and does not modify the condition flags.", "example": "LASTA v0.4s.T, p0/m, z1.s.T", "pseudocode": "activecount ← CountActiveLanes(Pg, esize)\nif activecount == VL/esize then\n Vd ← Zn[0]\nelse if activecount > 0 then\n Vd ← Zn[activecount]\nelse\n Vd ← Vd" }, { "mnemonic": "lastb", "architecture": "ARMv8-A", "full_name": "SVE Extract Last Element Before", "summary": "Extracts last active element (SIMD scalar destination).", "syntax": "LASTB ., , .", "encoding": { "format": "SVE Extract", "binary_pattern": "00000101 | size | 10001 | 1 | 100 | Pg | Zn | Vd", "hex_opcode": "0x05238000", "visual_parts": [ { "raw": "00000101", "clean": "00000101" }, { "raw": "size", "clean": "size" }, { "raw": "10001", "clean": "10001" }, { "raw": "1", "clean": "1" }, { "raw": "100", "clean": "100" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Vd", "clean": "Vd" } ], "bit_positions": "31:24 | 23:22 | 21:17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Vd", "desc": "Dest Scalar" }, { "name": "Pg", "desc": "Predicate" }, { "name": "Zn", "desc": "Vector" } ], "extension": "SVE", "description": "Extracts the last active element (as determined by the predicate) from a SVE vector and writes it to a SIMD scalar register; if no active elements exist, the destination register is unchanged. This instruction operates only in AArch64 state and does not modify the condition flags.", "example": "LASTB v0.4s.T, p0/m, z1.s.T", "pseudocode": "activecount ← CountActiveLanes(Pg, esize)\nif activecount > 0 then\n Vd ← Zn[activecount - 1]\nelse\n Vd ← Vd" }, { "mnemonic": "insr", "architecture": "ARMv8-A", "full_name": "SVE Insert Scalar", "summary": "Inserts scalar into bottom of vector, shifting other elements up.", "syntax": "INSR ., ", "encoding": { "format": "SVE Move", "binary_pattern": "00000101 | size | 100100001110 | Rm | Zdn", "hex_opcode": "0x05243800", "visual_parts": [ { "raw": "00000101", "clean": "00000101" }, { "raw": "size", "clean": "size" }, { "raw": "100100001110", "clean": "100100001110" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "Zdn", "clean": "Zdn" } ], "bit_positions": "31:24 | 23:22 | 21:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zdn", "desc": "Combined destination/source scalable vector register (SVE)" }, { "name": "Rm", "desc": "Scalar Src" } ], "extension": "SVE", "description": "Inserts a scalar register value into the bottom element of a SVE vector, shifting all other elements upward (toward higher element indices), with the top element discarded. This instruction operates only in AArch64 state and does not modify the condition flags.", "example": "INSR z0.s.T, Rm", "pseudocode": "elements ← VL / esize\nfor i = elements - 1 downto 1\n Zdn[i] ← Zdn[i-1]\nZdn[0] ← Rm" }, { "mnemonic": "ext", "architecture": "ARMv8-A", "full_name": "SVE Extract Vector", "summary": "Extracts a vector from a pair (sliding window) using immediate byte index.", "syntax": "EXT ., ., ., #", "encoding": { "format": "SVE Permute", "binary_pattern": "00000101001 | imm8h | 000 | imm8l | Zm | Zdn", "hex_opcode": "0x05200000", "visual_parts": [ { "raw": "00000101001", "clean": "00000101001" }, { "raw": "imm8h", "clean": "imm8h" }, { "raw": "000", "clean": "000" }, { "raw": "imm8l", "clean": "imm8l" }, { "raw": "Zm", "clean": "Zm" }, { "raw": "Zdn", "clean": "Zdn" } ], "bit_positions": "31:21 | 20:16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zdn", "desc": "Dest/Low" }, { "name": "Zm", "desc": "High" }, { "name": "imm", "desc": "Index" } ], "extension": "SVE", "description": "Extracts a contiguous sequence of bytes from the concatenation of two SVE vectors (the low vector followed by the high vector) starting at a byte offset, and places the result in the destination vector. This instruction operates only in AArch64 state and does not modify the condition flags.", "example": "EXT z0.s.T, z0.s.T, z2.s.T, #16", "pseudocode": "offset ← imm\nresult ← Concatenate(Zdn, Zm)[offset:offset + (VL/8) - 1]\nZdn ← result" }, { "mnemonic": "rev", "architecture": "ARMv8-A", "full_name": "SVE Reverse Vector", "summary": "Reverses the order of elements in the vector.", "syntax": "REV ., .", "encoding": { "format": "SVE Permute", "binary_pattern": "00000101 | size | 111000001110 | Zn | Zd", "hex_opcode": "0x05383800", "visual_parts": [ { "raw": "00000101", "clean": "00000101" }, { "raw": "size", "clean": "size" }, { "raw": "111000001110", "clean": "111000001110" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Zd", "clean": "Zd" } ], "bit_positions": "31:24 | 23:22 | 21:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zd", "desc": "Destination scalable vector register (SVE)" }, { "name": "Zn", "desc": "First source scalable vector register (SVE)" } ], "extension": "SVE", "description": "Reverses the order of elements within a SVE vector; the element at index 0 is moved to the last position, and the last element is moved to index 0. This instruction operates only in AArch64 state and does not modify the condition flags.", "example": "REV z0.s.T, z1.s.T", "pseudocode": "elements ← VL / esize\nfor i = 0 to elements - 1\n Zd[i] ← Zn[elements - 1 - i]" }, { "mnemonic": "revb", "architecture": "ARMv8-A", "full_name": "SVE Reverse Bytes in Elements", "summary": "Reverses bytes within 16/32/64-bit elements.", "syntax": "REVB ., /M, .", "encoding": { "format": "SVE Permute", "binary_pattern": "00000101 | size | 1001 | 0 | 0 | 100 | Pg | Zn | Zd", "hex_opcode": "0x05248000", "visual_parts": [ { "raw": "00000101", "clean": "00000101" }, { "raw": "size", "clean": "size" }, { "raw": "1001", "clean": "1001" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "100", "clean": "100" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Zd", "clean": "Zd" } ], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zd", "desc": "Destination scalable vector register (SVE)" }, { "name": "Pg", "desc": "Mask" }, { "name": "Zn", "desc": "First source scalable vector register (SVE)" } ], "extension": "SVE", "description": "Reverses the byte order within each element of a SVE vector under predicate control; for 16-bit elements 2 bytes are reversed, for 32-bit elements 4 bytes, and for 64-bit elements 8 bytes. This instruction operates only in AArch64 state and does not modify the condition flags.", "example": "REVB z0.s.T, p0/m/M, z1.s.T", "pseudocode": "elements ← VL / esize\nfor i = 0 to elements - 1\n if Pg[i] then\n Zd[i] ← ReverseBytes(Zn[i], esize)\n else\n Zd[i] ← Zd[i]" }, { "mnemonic": "revh", "architecture": "ARMv8-A", "full_name": "SVE Reverse Halfwords in Elements", "summary": "Reverses halfwords within 32/64-bit elements.", "syntax": "REVH ., /M, .", "encoding": { "format": "SVE Permute", "binary_pattern": "00000101 | size | 1001 | 0 | 1 | 100 | Pg | Zn | Zd", "hex_opcode": "0x05258000", "visual_parts": [ { "raw": "00000101", "clean": "00000101" }, { "raw": "size", "clean": "size" }, { "raw": "1001", "clean": "1001" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "100", "clean": "100" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Zd", "clean": "Zd" } ], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zd", "desc": "Destination scalable vector register (SVE)" }, { "name": "Pg", "desc": "Mask" }, { "name": "Zn", "desc": "First source scalable vector register (SVE)" } ], "extension": "SVE", "description": "Reverses the byte order of halfwords (16-bit elements) within 32-bit or 64-bit SVE vector elements, operating under predicate control. No condition flags are affected. This instruction is AArch64-only and available with the SVE extension; it performs element-wise reversals where each 32-bit or 64-bit element has its constituent halfwords byte-reversed in place.", "example": "REVH z0.s.T, p0/m/M, z1.s.T", "pseudocode": "for i = 0 to VL/esize-1\n if Pg[i] then\n case esize of\n 32: Zd[i+1:i] ← reverse_halfwords_in_32bit(Zn[i+1:i])\n 64: Zd[i+1:i] ← reverse_halfwords_in_64bit(Zn[i+1:i])\n else\n Zd[i+1:i] ← Zd[i+1:i]" }, { "mnemonic": "revw", "architecture": "ARMv8-A", "full_name": "SVE Reverse Words in Elements", "summary": "Reverses words within 64-bit elements.", "syntax": "REVW .D, /M, .D", "encoding": { "format": "SVE Permute", "binary_pattern": "00000101 | size | 1001 | 1 | 0 | 100 | Pg | Zn | Zd", "hex_opcode": "0x05268000", "visual_parts": [ { "raw": "00000101", "clean": "00000101" }, { "raw": "size", "clean": "size" }, { "raw": "1001", "clean": "1001" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "100", "clean": "100" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Zd", "clean": "Zd" } ], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zd", "desc": "Destination scalable vector register (SVE)" }, { "name": "Pg", "desc": "Mask" }, { "name": "Zn", "desc": "First source scalable vector register (SVE)" } ], "extension": "SVE", "description": "Reverses the byte order of words (32-bit elements) within 64-bit SVE vector elements, operating under predicate control. No condition flags are affected. This instruction is AArch64-only and available with the SVE extension; it swaps the two 32-bit words in each 64-bit element.", "example": "REVW z0.s.D, p0/m/M, z1.s.D", "pseudocode": "for i = 0 to VL/64-1\n if Pg[i] then\n Zd[i+1:i] ← {Zn[i+31:i], Zn[i+63:i+32]}\n else\n Zd[i+1:i] ← Zd[i+1:i]" }, { "mnemonic": "rbit", "architecture": "ARMv8-A", "full_name": "SVE Reverse Bits", "summary": "Reverses bits in each element.", "syntax": "RBIT ., /M, .", "encoding": { "format": "SVE Permute", "binary_pattern": "00000101 | size | 1001 | 1 | 1 | 100 | Pg | Zn | Zd", "hex_opcode": "0x05278000", "visual_parts": [ { "raw": "00000101", "clean": "00000101" }, { "raw": "size", "clean": "size" }, { "raw": "1001", "clean": "1001" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "100", "clean": "100" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Zd", "clean": "Zd" } ], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zd", "desc": "Destination scalable vector register (SVE)" }, { "name": "Pg", "desc": "Mask" }, { "name": "Zn", "desc": "First source scalable vector register (SVE)" } ], "extension": "SVE", "description": "Reverses the bit order within each SVE vector element, operating under predicate control. No condition flags are affected. This instruction is AArch64-only and available with the SVE extension; each element's bits are reversed such that bit 0 becomes the MSB and the MSB becomes bit 0.", "example": "RBIT z0.s.T, p0/m/M, z1.s.T", "pseudocode": "for i = 0 to VL/esize-1\n if Pg[i] then\n Zd[i+1:i] ← reverse_bits(Zn[i+1:i], esize)\n else\n Zd[i+1:i] ← Zd[i+1:i]" }, { "mnemonic": "sunpklo", "architecture": "ARMv8-A", "full_name": "SVE Signed Unpack Low", "summary": "Unpacks and sign-extends lower half of vector elements.", "syntax": "SUNPKLO ., .", "encoding": { "format": "SVE Permute", "binary_pattern": "00000101 | size | 1100 | 0 | 0 | 001110 | Zn | Zd", "hex_opcode": "0x05303800", "visual_parts": [ { "raw": "00000101", "clean": "00000101" }, { "raw": "size", "clean": "size" }, { "raw": "1100", "clean": "1100" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "001110", "clean": "001110" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Zd", "clean": "Zd" } ], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zd", "desc": "Destination scalable vector register (SVE)" }, { "name": "Zn", "desc": "First source scalable vector register (SVE)" } ], "extension": "SVE", "description": "Unpacks the lower half of each source element and sign-extends it to the destination element size in SVE vectors. No condition flags are affected. This instruction is AArch64-only and available with the SVE extension; destination elements are twice the width of source elements, with sign extension applied to the lower elements.", "example": "SUNPKLO z0.s.T, z1.s.Tb", "pseudocode": "for i = 0 to VL/esize_dst-1\n Zd[i+1:i] ← sign_extend(Zn[i+esize_src/2-1:i], esize_dst)" }, { "mnemonic": "sunpkhi", "architecture": "ARMv8-A", "full_name": "SVE Signed Unpack High", "summary": "Unpacks and sign-extends upper half of vector elements.", "syntax": "SUNPKHI ., .", "encoding": { "format": "SVE Permute", "binary_pattern": "00000101 | size | 1100 | 0 | 1 | 001110 | Zn | Zd", "hex_opcode": "0x05313800", "visual_parts": [ { "raw": "00000101", "clean": "00000101" }, { "raw": "size", "clean": "size" }, { "raw": "1100", "clean": "1100" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "001110", "clean": "001110" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Zd", "clean": "Zd" } ], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zd", "desc": "Destination scalable vector register (SVE)" }, { "name": "Zn", "desc": "First source scalable vector register (SVE)" } ], "extension": "SVE", "description": "Unpacks the upper half of each source element and sign-extends it to the destination element size in SVE vectors. No condition flags are affected. This instruction is AArch64-only and available with the SVE extension; destination elements are twice the width of source elements, with sign extension applied to the upper elements.", "example": "SUNPKHI z0.s.T, z1.s.Tb", "pseudocode": "for i = 0 to VL/esize_dst-1\n Zd[i+1:i] ← sign_extend(Zn[i+esize_src-1:i+esize_src/2], esize_dst)" }, { "mnemonic": "uunpklo", "architecture": "ARMv8-A", "full_name": "SVE Unsigned Unpack Low", "summary": "Unpacks and zero-extends lower half of vector elements.", "syntax": "UUNPKLO ., .", "encoding": { "format": "SVE Permute", "binary_pattern": "00000101 | size | 1100 | 1 | 0 | 001110 | Zn | Zd", "hex_opcode": "0x05323800", "visual_parts": [ { "raw": "00000101", "clean": "00000101" }, { "raw": "size", "clean": "size" }, { "raw": "1100", "clean": "1100" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "001110", "clean": "001110" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Zd", "clean": "Zd" } ], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zd", "desc": "Destination scalable vector register (SVE)" }, { "name": "Zn", "desc": "First source scalable vector register (SVE)" } ], "extension": "SVE", "description": "Unpacks the lower half of each source element and zero-extends it to the destination element size in SVE vectors. No condition flags are affected. This instruction is AArch64-only and available with the SVE extension; destination elements are twice the width of source elements, with zero extension applied to the lower elements.", "example": "UUNPKLO z0.s.T, z1.s.Tb", "pseudocode": "for i = 0 to VL/esize_dst-1\n Zd[i+1:i] ← zero_extend(Zn[i+esize_src/2-1:i], esize_dst)" }, { "mnemonic": "uunpkhi", "architecture": "ARMv8-A", "full_name": "SVE Unsigned Unpack High", "summary": "Unpacks and zero-extends upper half of vector elements.", "syntax": "UUNPKHI ., .", "encoding": { "format": "SVE Permute", "binary_pattern": "00000101 | size | 1100 | 1 | 1 | 001110 | Zn | Zd", "hex_opcode": "0x05333800", "visual_parts": [ { "raw": "00000101", "clean": "00000101" }, { "raw": "size", "clean": "size" }, { "raw": "1100", "clean": "1100" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "001110", "clean": "001110" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Zd", "clean": "Zd" } ], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zd", "desc": "Destination scalable vector register (SVE)" }, { "name": "Zn", "desc": "First source scalable vector register (SVE)" } ], "extension": "SVE", "description": "Unpacks the upper half of each source element and zero-extends it to the destination element size in SVE vectors. No condition flags are affected. This instruction is AArch64-only and available with the SVE extension; destination elements are twice the width of source elements, with zero extension applied to the upper elements.", "example": "UUNPKHI z0.s.T, z1.s.Tb", "pseudocode": "for i = 0 to VL/esize_dst-1\n Zd[i+1:i] ← zero_extend(Zn[i+esize_src-1:i+esize_src/2], esize_dst)" }, { "mnemonic": "sdot", "architecture": "ARMv8-A", "full_name": "SVE Signed Dot Product", "summary": "Computes dot product of signed integers (AI Acceleration).", "syntax": "SDOT ., ., .", "encoding": { "format": "SVE Dot Product", "binary_pattern": "01000100 | size | 0 | Zm | 00000 | 0 | Zn | Zda", "hex_opcode": "0x44000000", "visual_parts": [ { "raw": "01000100", "clean": "01000100" }, { "raw": "size", "clean": "size" }, { "raw": "0", "clean": "0" }, { "raw": "Zm", "clean": "Zm" }, { "raw": "00000", "clean": "00000" }, { "raw": "0", "clean": "0" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Zda", "clean": "Zda" } ], "bit_positions": "31:24 | 23:22 | 21 | 20:16 | 15:11 | 10 | 9:5 | 4:0" }, "operands": [ { "name": "Zda", "desc": "Accumulator" }, { "name": "Zn", "desc": "First source scalable vector register (SVE)" }, { "name": "Zm", "desc": "Second source scalable vector register (SVE)" } ], "extension": "SVE", "description": "Computes the dot product of signed integer vectors and accumulates the result into the destination register, supporting AI acceleration. No condition flags are affected. This instruction is AArch64-only and available with the SVE extension; the destination is widened relative to the sources, and the accumulation is added to existing values in Zda.", "example": "SDOT z0.s.T, z1.s.Tb, z2.s.Tb", "pseudocode": "for i = 0 to VL/esize_dst-1\n product ← 0\n for j = 0 to (esize_dst / esize_src) - 1\n product ← product + sign_extend(Zn[i*esize_dst + (j+1)*esize_src - 1 : i*esize_dst + j*esize_src], esize_dst) * sign_extend(Zm[i*esize_dst + (j+1)*esize_src - 1 : i*esize_dst + j*esize_src], esize_dst)\n Zda[i+1:i] ← Zda[i+1:i] + product" }, { "mnemonic": "udot", "architecture": "ARMv8-A", "full_name": "SVE Unsigned Dot Product", "summary": "Computes dot product of unsigned integers.", "syntax": "UDOT ., ., .", "encoding": { "format": "SVE Dot Product", "binary_pattern": "01000100 | size | 0 | Zm | 00000 | 1 | Zn | Zda", "hex_opcode": "0x44000400", "visual_parts": [ { "raw": "01000100", "clean": "01000100" }, { "raw": "size", "clean": "size" }, { "raw": "0", "clean": "0" }, { "raw": "Zm", "clean": "Zm" }, { "raw": "00000", "clean": "00000" }, { "raw": "1", "clean": "1" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Zda", "clean": "Zda" } ], "bit_positions": "31:24 | 23:22 | 21 | 20:16 | 15:11 | 10 | 9:5 | 4:0" }, "operands": [ { "name": "Zda", "desc": "Accumulator" }, { "name": "Zn", "desc": "First source scalable vector register (SVE)" }, { "name": "Zm", "desc": "Second source scalable vector register (SVE)" } ], "extension": "SVE", "description": "SVE unsigned dot product: accumulates the sum of element-wise products of unsigned integers from Zn and Zm into Zda. The element size of Zn and Zm (Tb) is half that of Zda (T), allowing 2, 4, or 8 products to be summed per destination element depending on the vector length. No condition flags are affected. This is an AArch64-only instruction requiring SVE support.", "example": "UDOT z0.s.T, z1.s.Tb, z2.s.Tb", "pseudocode": "for e = 0 to VL/getElementSize(T)-1\n element_pairs = getElements(Zn[e], Tb) × getElements(Zm[e], Tb)\n Zda[e] ← Zda[e] + sum(element_pairs)\nend for" }, { "mnemonic": "smax", "architecture": "ARMv8-A", "full_name": "SVE Signed Maximum", "summary": "Determines maximum signed value per element.", "syntax": "SMAX ., /M, ., .", "encoding": { "format": "SVE Integer Binary", "binary_pattern": "00000100 | size | 001 | 0 | 0 | 0 | 000 | Pg | Zm | Zdn", "hex_opcode": "0x04080000", "visual_parts": [ { "raw": "00000100", "clean": "00000100" }, { "raw": "size", "clean": "size" }, { "raw": "001", "clean": "001" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "000", "clean": "000" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zm", "clean": "Zm" }, { "raw": "Zdn", "clean": "Zdn" } ], "bit_positions": "31:24 | 23:22 | 21:19 | 18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zdn", "desc": "Combined destination/source scalable vector register (SVE)" }, { "name": "Pg", "desc": "Mask" }, { "name": "Zm", "desc": "Second source scalable vector register (SVE)" } ], "extension": "SVE", "description": "SVE signed maximum: computes the element-wise maximum of two signed integer vectors (Zdn and Zm), writing results to Zdn under predicate mask control (Pg). Only elements where the predicate is active are updated; inactive elements retain their original values in Zdn. No condition flags are affected. This is an AArch64-only instruction requiring SVE support.", "example": "SMAX z0.s.T, p0/m/M, z0.s.T, z2.s.T", "pseudocode": "for e = 0 to VL/getElementSize(T)-1\n if Pg[e] == 1 then\n Zdn[e] ← max_signed(Zdn[e], Zm[e])\n end if\nend for" }, { "mnemonic": "smin", "architecture": "ARMv8-A", "full_name": "SVE Signed Minimum", "summary": "Determines minimum signed value per element.", "syntax": "SMIN ., /M, ., .", "encoding": { "format": "SVE Integer Binary", "binary_pattern": "00000100 | size | 001 | 0 | 1 | 0 | 000 | Pg | Zm | Zdn", "hex_opcode": "0x040A0000", "visual_parts": [ { "raw": "00000100", "clean": "00000100" }, { "raw": "size", "clean": "size" }, { "raw": "001", "clean": "001" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "000", "clean": "000" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zm", "clean": "Zm" }, { "raw": "Zdn", "clean": "Zdn" } ], "bit_positions": "31:24 | 23:22 | 21:19 | 18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zdn", "desc": "Combined destination/source scalable vector register (SVE)" }, { "name": "Pg", "desc": "Mask" }, { "name": "Zm", "desc": "Second source scalable vector register (SVE)" } ], "extension": "SVE", "description": "SVE signed minimum: computes the element-wise minimum of two signed integer vectors (Zdn and Zm), writing results to Zdn under predicate mask control (Pg). Only elements where the predicate is active are updated; inactive elements retain their original values in Zdn. No condition flags are affected. This is an AArch64-only instruction requiring SVE support.", "example": "SMIN z0.s.T, p0/m/M, z0.s.T, z2.s.T", "pseudocode": "for e = 0 to VL/getElementSize(T)-1\n if Pg[e] == 1 then\n Zdn[e] ← min_signed(Zdn[e], Zm[e])\n end if\nend for" }, { "mnemonic": "umax", "architecture": "ARMv8-A", "full_name": "SVE Unsigned Maximum", "summary": "Determines maximum unsigned value per element.", "syntax": "UMAX ., /M, ., .", "encoding": { "format": "SVE Integer Binary", "binary_pattern": "00000100 | size | 001 | 0 | 0 | 1 | 000 | Pg | Zm | Zdn", "hex_opcode": "0x04090000", "visual_parts": [ { "raw": "00000100", "clean": "00000100" }, { "raw": "size", "clean": "size" }, { "raw": "001", "clean": "001" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "000", "clean": "000" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zm", "clean": "Zm" }, { "raw": "Zdn", "clean": "Zdn" } ], "bit_positions": "31:24 | 23:22 | 21:19 | 18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zdn", "desc": "Combined destination/source scalable vector register (SVE)" }, { "name": "Pg", "desc": "Mask" }, { "name": "Zm", "desc": "Second source scalable vector register (SVE)" } ], "extension": "SVE", "description": "SVE unsigned maximum: computes the element-wise maximum of two unsigned integer vectors (Zdn and Zm), writing results to Zdn under predicate mask control (Pg). Only elements where the predicate is active are updated; inactive elements retain their original values in Zdn. No condition flags are affected. This is an AArch64-only instruction requiring SVE support.", "example": "UMAX z0.s.T, p0/m/M, z0.s.T, z2.s.T", "pseudocode": "for e = 0 to VL/getElementSize(T)-1\n if Pg[e] == 1 then\n Zdn[e] ← max_unsigned(Zdn[e], Zm[e])\n end if\nend for" }, { "mnemonic": "umin", "architecture": "ARMv8-A", "full_name": "SVE Unsigned Minimum", "summary": "Determines minimum unsigned value per element.", "syntax": "UMIN ., /M, ., .", "encoding": { "format": "SVE Integer Binary", "binary_pattern": "00000100 | size | 001 | 0 | 1 | 1 | 000 | Pg | Zm | Zdn", "hex_opcode": "0x040B0000", "visual_parts": [ { "raw": "00000100", "clean": "00000100" }, { "raw": "size", "clean": "size" }, { "raw": "001", "clean": "001" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "000", "clean": "000" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zm", "clean": "Zm" }, { "raw": "Zdn", "clean": "Zdn" } ], "bit_positions": "31:24 | 23:22 | 21:19 | 18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zdn", "desc": "Combined destination/source scalable vector register (SVE)" }, { "name": "Pg", "desc": "Mask" }, { "name": "Zm", "desc": "Second source scalable vector register (SVE)" } ], "extension": "SVE", "description": "SVE unsigned minimum: computes the element-wise minimum of two unsigned integer vectors (Zdn and Zm), writing results to Zdn under predicate mask control (Pg). Only elements where the predicate is active are updated; inactive elements retain their original values in Zdn. No condition flags are affected. This is an AArch64-only instruction requiring SVE support.", "example": "UMIN z0.s.T, p0/m/M, z0.s.T, z2.s.T", "pseudocode": "for e = 0 to VL/getElementSize(T)-1\n if Pg[e] == 1 then\n Zdn[e] ← min_unsigned(Zdn[e], Zm[e])\n end if\nend for" }, { "mnemonic": "abs", "architecture": "ARMv8-A", "full_name": "SVE Absolute Value", "summary": "Calculates absolute value of integers.", "syntax": "ABS ., /M, .", "encoding": { "format": "SVE Integer Unary", "binary_pattern": "00000100 | size | 010 | 11 | 0 | 101 | Pg | Zn | Zd", "hex_opcode": "0x0416A000", "visual_parts": [ { "raw": "00000100", "clean": "00000100" }, { "raw": "size", "clean": "size" }, { "raw": "010", "clean": "010" }, { "raw": "11", "clean": "11" }, { "raw": "0", "clean": "0" }, { "raw": "101", "clean": "101" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Zd", "clean": "Zd" } ], "bit_positions": "31:24 | 23:22 | 21:19 | 18:17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zdn", "desc": "Dest/Src" }, { "name": "Pg", "desc": "Mask" } ], "extension": "SVE", "description": "SVE absolute value: computes the element-wise absolute value of signed integers in Zdn, writing results back to Zdn under predicate mask control (Pg). Only elements where the predicate is active are updated; inactive elements retain their original values. No condition flags are affected. This is an AArch64-only instruction requiring SVE support.", "example": "ABS z0.s.T, p0/m/M, z0.s.T", "pseudocode": "for e = 0 to VL/getElementSize(T)-1\n if Pg[e] == 1 then\n Zdn[e] ← abs_signed(Zdn[e])\n end if\nend for" }, { "mnemonic": "neg", "architecture": "ARMv8-A", "full_name": "SVE Negate", "summary": "Negates integers.", "syntax": "NEG ., /M, .", "encoding": { "format": "SVE Integer Unary", "binary_pattern": "00000100 | size | 010 | 11 | 1 | 101 | Pg | Zn | Zd", "hex_opcode": "0x0417A000", "visual_parts": [ { "raw": "00000100", "clean": "00000100" }, { "raw": "size", "clean": "size" }, { "raw": "010", "clean": "010" }, { "raw": "11", "clean": "11" }, { "raw": "1", "clean": "1" }, { "raw": "101", "clean": "101" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Zd", "clean": "Zd" } ], "bit_positions": "31:24 | 23:22 | 21:19 | 18:17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zdn", "desc": "Dest/Src" }, { "name": "Pg", "desc": "Mask" } ], "extension": "SVE", "description": "SVE negate: computes the element-wise negation (two's complement) of integers in Zdn, writing results back to Zdn under predicate mask control (Pg). Only elements where the predicate is active are updated; inactive elements retain their original values. No condition flags are affected. This is an AArch64-only instruction requiring SVE support.", "example": "NEG z0.s.T, p0/m/M, z0.s.T", "pseudocode": "for e = 0 to VL/getElementSize(T)-1\n if Pg[e] == 1 then\n Zdn[e] ← -Zdn[e]\n end if\nend for" }, { "mnemonic": "not", "architecture": "ARMv8-A", "full_name": "SVE Bitwise NOT", "summary": "Inverts bits.", "syntax": "NOT ., /M, .", "encoding": { "format": "SVE Integer Unary", "binary_pattern": "00000100 | size | 011 | 11 | 0 | 101 | Pg | Zn | Zd", "hex_opcode": "0x041EA000", "visual_parts": [ { "raw": "00000100", "clean": "00000100" }, { "raw": "size", "clean": "size" }, { "raw": "011", "clean": "011" }, { "raw": "11", "clean": "11" }, { "raw": "0", "clean": "0" }, { "raw": "101", "clean": "101" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Zd", "clean": "Zd" } ], "bit_positions": "31:24 | 23:22 | 21:19 | 18:17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zdn", "desc": "Dest/Src" }, { "name": "Pg", "desc": "Mask" } ], "extension": "SVE", "description": "SVE bitwise NOT: inverts all bits in each element of Zdn under predicate mask control (Pg), writing the results back to Zdn. Only elements where the predicate is active are updated; inactive elements retain their original values. No condition flags are affected. This is an AArch64-only instruction requiring SVE support.", "example": "NOT z0.s.T, p0/m/M, z0.s.T", "pseudocode": "for e = 0 to VL/getElementSize(T)-1\n if Pg[e] == 1 then\n Zdn[e] ← ~Zdn[e]\n end if\nend for" }, { "mnemonic": "sdiv", "architecture": "ARMv8-A", "full_name": "SVE Signed Divide", "summary": "Divides signed integers.", "syntax": "SDIV ., /M, ., .", "encoding": { "format": "SVE Integer Binary", "binary_pattern": "00000100 | size | 0101 | 0 | 0 | 000 | Pg | Zm | Zdn", "hex_opcode": "0x04140000", "visual_parts": [ { "raw": "00000100", "clean": "00000100" }, { "raw": "size", "clean": "size" }, { "raw": "0101", "clean": "0101" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "000", "clean": "000" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zm", "clean": "Zm" }, { "raw": "Zdn", "clean": "Zdn" } ], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zdn", "desc": "Dest/Dividend" }, { "name": "Pg", "desc": "Mask" }, { "name": "Zm", "desc": "Divisor" } ], "extension": "SVE", "description": "SVE signed integer divide: divides each active element of Zdn (dividend) by the corresponding element of Zm (divisor), storing the quotient back in Zdn. Elements where the predicate is false are left unchanged. No condition flags are affected. This is an SVE-only instruction and does not raise exceptions on division by zero; instead, undefined results are written to inactive elements.", "example": "SDIV z0.s.T, p0/m/M, z0.s.T, z2.s.T", "pseudocode": "for i = 0 to VL-1\n if Pg[i] == '1' then\n Zdn[i] ← Zdn[i] / Zm[i]\n // else Zdn[i] unchanged" }, { "mnemonic": "udiv", "architecture": "ARMv8-A", "full_name": "SVE Unsigned Divide", "summary": "Divides unsigned integers.", "syntax": "UDIV ., /M, ., .", "encoding": { "format": "SVE Integer Binary", "binary_pattern": "00000100 | size | 0101 | 0 | 1 | 000 | Pg | Zm | Zdn", "hex_opcode": "0x04150000", "visual_parts": [ { "raw": "00000100", "clean": "00000100" }, { "raw": "size", "clean": "size" }, { "raw": "0101", "clean": "0101" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "000", "clean": "000" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zm", "clean": "Zm" }, { "raw": "Zdn", "clean": "Zdn" } ], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zdn", "desc": "Dest/Dividend" }, { "name": "Pg", "desc": "Mask" }, { "name": "Zm", "desc": "Divisor" } ], "extension": "SVE", "description": "SVE unsigned integer divide: divides each active element of Zdn (dividend) by the corresponding element of Zm (divisor) as unsigned values, storing the quotient back in Zdn. Elements where the predicate is false are left unchanged. No condition flags are affected. This is an SVE-only instruction and does not raise exceptions on division by zero.", "example": "UDIV z0.s.T, p0/m/M, z0.s.T, z2.s.T", "pseudocode": "for i = 0 to VL-1\n if Pg[i] == '1' then\n Zdn[i] ← UnsignedDivide(Zdn[i], Zm[i])\n // else Zdn[i] unchanged" }, { "mnemonic": "fsqrt", "architecture": "ARMv8-A", "full_name": "SVE Floating-Point Square Root", "summary": "Calculates square root of floats.", "syntax": "FSQRT ., /M, .", "encoding": { "format": "SVE FP Unary", "binary_pattern": "01100101 | size | 0011 | 0 | 1 | 101 | Pg | Zn | Zd", "hex_opcode": "0x650DA000", "visual_parts": [ { "raw": "01100101", "clean": "01100101" }, { "raw": "size", "clean": "size" }, { "raw": "0011", "clean": "0011" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "101", "clean": "101" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Zd", "clean": "Zd" } ], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zdn", "desc": "Combined destination/source scalable vector register (SVE)" }, { "name": "Pg", "desc": "Mask" } ], "extension": "SVE", "description": "SVE floating-point square root: computes the square root of each active element in Zdn and stores the result back in Zdn. Elements where the predicate is false are left unchanged. Floating-point exception flags (IOC, DZC, OFC, UFC, IXC) are updated according to the IEEE 754 standard; no integer condition flags are affected. This is an SVE-only instruction.", "example": "FSQRT z0.s.T, p0/m/M, z0.s.T", "pseudocode": "for i = 0 to VL-1\n if Pg[i] == '1' then\n Zdn[i] ← FPSquareRoot(Zdn[i])\n // else Zdn[i] unchanged\n// FP exception flags updated per IEEE 754" }, { "mnemonic": "fabs", "architecture": "ARMv8-A", "full_name": "SVE Floating-Point Absolute Value", "summary": "Calculates absolute value of floats.", "syntax": "FABS ., /M, .", "encoding": { "format": "SVE FP Unary", "binary_pattern": "00000100 | size | 011 | 10 | 0 | 101 | Pg | Zn | Zd", "hex_opcode": "0x041CA000", "visual_parts": [ { "raw": "00000100", "clean": "00000100" }, { "raw": "size", "clean": "size" }, { "raw": "011", "clean": "011" }, { "raw": "10", "clean": "10" }, { "raw": "0", "clean": "0" }, { "raw": "101", "clean": "101" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Zd", "clean": "Zd" } ], "bit_positions": "31:24 | 23:22 | 21:19 | 18:17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zdn", "desc": "Combined destination/source scalable vector register (SVE)" }, { "name": "Pg", "desc": "Mask" } ], "extension": "SVE", "description": "SVE floating-point absolute value: computes the absolute value of each active element in Zdn and stores the result back in Zdn, clearing the sign bit. Elements where the predicate is false are left unchanged. No condition flags or floating-point exceptions are affected. This is an SVE-only instruction.", "example": "FABS z0.s.T, p0/m/M, z0.s.T", "pseudocode": "for i = 0 to VL-1\n if Pg[i] == '1' then\n Zdn[i] ← FPAbs(Zdn[i])\n // else Zdn[i] unchanged" }, { "mnemonic": "fneg", "architecture": "ARMv8-A", "full_name": "SVE Floating-Point Negate", "summary": "Negates floats.", "syntax": "FNEG ., /M, .", "encoding": { "format": "SVE FP Unary", "binary_pattern": "00000100 | size | 011 | 10 | 1 | 101 | Pg | Zn | Zd", "hex_opcode": "0x041DA000", "visual_parts": [ { "raw": "00000100", "clean": "00000100" }, { "raw": "size", "clean": "size" }, { "raw": "011", "clean": "011" }, { "raw": "10", "clean": "10" }, { "raw": "1", "clean": "1" }, { "raw": "101", "clean": "101" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Zd", "clean": "Zd" } ], "bit_positions": "31:24 | 23:22 | 21:19 | 18:17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zdn", "desc": "Combined destination/source scalable vector register (SVE)" }, { "name": "Pg", "desc": "Mask" } ], "extension": "SVE", "description": "SVE floating-point negate: flips the sign bit of each active element in Zdn and stores the result back in Zdn. Elements where the predicate is false are left unchanged. No condition flags or floating-point exceptions are affected. This is an SVE-only instruction.", "example": "FNEG z0.s.T, p0/m/M, z0.s.T", "pseudocode": "for i = 0 to VL-1\n if Pg[i] == '1' then\n Zdn[i] ← FPNegate(Zdn[i])\n // else Zdn[i] unchanged" }, { "mnemonic": "fcadd", "architecture": "ARMv8-A", "full_name": "SVE Floating-Point Complex Add", "summary": "Performs complex addition with rotation.", "syntax": "FCADD ., /M, ., ., #", "encoding": { "format": "SVE FP Complex", "binary_pattern": "01100100 | size | 00000 | rot | 100 | Pg | Zm | Zdn", "hex_opcode": "0x64008000", "visual_parts": [ { "raw": "01100100", "clean": "01100100" }, { "raw": "size", "clean": "size" }, { "raw": "00000", "clean": "00000" }, { "raw": "rot", "clean": "rot" }, { "raw": "100", "clean": "100" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zm", "clean": "Zm" }, { "raw": "Zdn", "clean": "Zdn" } ], "bit_positions": "31:24 | 23:22 | 21:17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zdn", "desc": "Combined destination/source scalable vector register (SVE)" }, { "name": "Pg", "desc": "Mask" }, { "name": "Zm", "desc": "Second source scalable vector register (SVE)" }, { "name": "rot", "desc": "Rotation (90, 270)" } ], "extension": "SVE", "description": "SVE floating-point complex add: performs a predicate-masked complex addition of Zdn and Zm with a 90° or 270° rotation applied to Zm before addition. For rot=90, computes Zdn + i*Zm; for rot=270, computes Zdn - i*Zm. Elements where the predicate is false are left unchanged. Floating-point exceptions are signaled per IEEE 754. This is an SVE-only instruction.", "example": "FCADD z0.s.T, p0/m/M, z0.s.T, z2.s.T, #rot", "pseudocode": "for i = 0 to VL-1\n if Pg[i] == '1' then\n rotated ← RotateComplex(Zm[i], rot)\n Zdn[i] ← FPAdd(Zdn[i], rotated)\n // else Zdn[i] unchanged" }, { "mnemonic": "fcmla", "architecture": "ARMv8-A", "full_name": "SVE Floating-Point Complex Multiply-Add", "summary": "Performs complex multiply-accumulate.", "syntax": "FCMLA ., /M, ., ., #", "encoding": { "format": "SVE FP Complex", "binary_pattern": "01100100 | size | 0 | Zm | 0 | rot | Pg | Zn | Zda", "hex_opcode": "0x64000000", "visual_parts": [ { "raw": "01100100", "clean": "01100100" }, { "raw": "size", "clean": "size" }, { "raw": "0", "clean": "0" }, { "raw": "Zm", "clean": "Zm" }, { "raw": "0", "clean": "0" }, { "raw": "rot", "clean": "rot" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Zda", "clean": "Zda" } ], "bit_positions": "31:24 | 23:22 | 21 | 20:16 | 15 | 14:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zda", "desc": "Accumulator scalable vector register (SVE)" }, { "name": "Pg", "desc": "Mask" }, { "name": "Zn", "desc": "First source scalable vector register (SVE)" }, { "name": "Zm", "desc": "Second source scalable vector register (SVE)" }, { "name": "rot", "desc": "Rot" } ], "extension": "SVE", "description": "SVE floating-point complex multiply-add: performs a predicate-masked complex multiply-accumulate operation where Zn and Zm are multiplied with rotation, and the result is added to Zda. For each rotation value (0°, 90°, 180°, 270°), a different complex multiplication result is accumulated. Elements where the predicate is false leave Zda unchanged. Floating-point exceptions are signaled per IEEE 754. This is an SVE-only instruction.", "example": "FCMLA z0.s.T, p0/m/M, z1.s.T, z2.s.T, #rot", "pseudocode": "for i = 0 to VL-1\n if Pg[i] == '1' then\n product ← FPComplexMultiply(Zn[i], Zm[i], rot)\n Zda[i] ← FPAdd(Zda[i], product)\n // else Zda[i] unchanged" }, { "mnemonic": "saddv", "architecture": "ARMv8-A", "full_name": "SVE Signed Integer Add Reduction", "summary": "Sums all active signed elements into a scalar result.", "syntax": "SADDV , , .", "encoding": { "format": "SVE Reduction", "binary_pattern": "00000100 | size | 0000 | 0 | 0 | 001 | Pg | Zn | Vd", "hex_opcode": "0x04002000", "visual_parts": [ { "raw": "00000100", "clean": "00000100" }, { "raw": "size", "clean": "size" }, { "raw": "0000", "clean": "0000" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "001", "clean": "001" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Vd", "clean": "Vd" } ], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Vd", "desc": "Dest Scalar" }, { "name": "Pg", "desc": "Mask" }, { "name": "Zn", "desc": "Vector" } ], "extension": "SVE", "description": "SVE signed integer add reduction: sums all active signed elements of the SVE vector Zn across the vector length and accumulates the result into the scalar destination Vd, sign-extending to the element width. Only elements where the corresponding predicate bit is set participate in the reduction. No condition flags are affected. This is an SVE-only instruction.", "example": "SADDV v0.4s, p0/m, z1.s.T", "pseudocode": "result ← 0\nfor i = 0 to VL-1\n if Pg[i] == '1' then\n result ← result + SignExtend(Zn[i])\nVd ← result" }, { "mnemonic": "smaxv", "architecture": "ARMv8-A", "full_name": "SVE Signed Maximum Reduction", "summary": "Finds max signed element in vector.", "syntax": "SMAXV , , .", "encoding": { "format": "SVE Reduction", "binary_pattern": "00000100 | size | 0010 | 0 | 0 | 001 | Pg | Zn | Vd", "hex_opcode": "0x04082000", "visual_parts": [ { "raw": "00000100", "clean": "00000100" }, { "raw": "size", "clean": "size" }, { "raw": "0010", "clean": "0010" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "001", "clean": "001" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Vd", "clean": "Vd" } ], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Vd", "desc": "Dest Scalar" }, { "name": "Pg", "desc": "Mask" }, { "name": "Zn", "desc": "Vector" } ], "extension": "SVE", "description": "SVE signed maximum reduction: finds the maximum signed element in vector Zn according to predicate mask Pg, and stores the result as a scalar in Vd. The operation reads all active elements from Zn, compares them as signed integers (element size determined by sz), and reduces to a single scalar value. No NZCV flags are affected by this instruction.", "example": "SMAXV v0.4s, p0/m, z1.s.T", "pseudocode": "bits(esize) result = MIN_INT(esize);\nfor i = 0 to VL/esize - 1\n if Pg[i] == '1' then\n element = Zn[i*esize +: esize];\n if element > result (signed) then result = element;\nVd[0 +: esize] ← result;" }, { "mnemonic": "umaxv", "architecture": "ARMv8-A", "full_name": "SVE Unsigned Maximum Reduction", "summary": "Finds max unsigned element in vector.", "syntax": "UMAXV , , .", "encoding": { "format": "SVE Reduction", "binary_pattern": "00000100 | size | 0010 | 0 | 1 | 001 | Pg | Zn | Vd", "hex_opcode": "0x04092000", "visual_parts": [ { "raw": "00000100", "clean": "00000100" }, { "raw": "size", "clean": "size" }, { "raw": "0010", "clean": "0010" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "001", "clean": "001" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Vd", "clean": "Vd" } ], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Vd", "desc": "Dest Scalar" }, { "name": "Pg", "desc": "Mask" }, { "name": "Zn", "desc": "Vector" } ], "extension": "SVE", "description": "SVE unsigned maximum reduction: finds the maximum unsigned element in vector Zn according to predicate mask Pg, and stores the result as a scalar in Vd. The operation compares all active elements as unsigned integers (element size determined by sz) and reduces to a single scalar. No NZCV flags are affected by this instruction.", "example": "UMAXV v0.4s, p0/m, z1.s.T", "pseudocode": "bits(esize) result = 0;\nfor i = 0 to VL/esize - 1\n if Pg[i] == '1' then\n element = Zn[i*esize +: esize];\n if element > result (unsigned) then result = element;\nVd[0 +: esize] ← result;" }, { "mnemonic": "sminv", "architecture": "ARMv8-A", "full_name": "SVE Signed Minimum Reduction", "summary": "Finds min signed element in vector.", "syntax": "SMINV , , .", "encoding": { "format": "SVE Reduction", "binary_pattern": "00000100 | size | 0010 | 1 | 0 | 001 | Pg | Zn | Vd", "hex_opcode": "0x040A2000", "visual_parts": [ { "raw": "00000100", "clean": "00000100" }, { "raw": "size", "clean": "size" }, { "raw": "0010", "clean": "0010" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "001", "clean": "001" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Vd", "clean": "Vd" } ], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Vd", "desc": "Dest Scalar" }, { "name": "Pg", "desc": "Mask" }, { "name": "Zn", "desc": "Vector" } ], "extension": "SVE", "description": "SVE signed minimum reduction: finds the minimum signed element in vector Zn according to predicate mask Pg, and stores the result as a scalar in Vd. The operation reads all active elements from Zn, compares them as signed integers (element size determined by sz), and reduces to a single scalar value. No NZCV flags are affected by this instruction.", "example": "SMINV v0.4s, p0/m, z1.s.T", "pseudocode": "bits(esize) result = MAX_INT(esize);\nfor i = 0 to VL/esize - 1\n if Pg[i] == '1' then\n element = Zn[i*esize +: esize];\n if element < result (signed) then result = element;\nVd[0 +: esize] ← result;" }, { "mnemonic": "uminv", "architecture": "ARMv8-A", "full_name": "SVE Unsigned Minimum Reduction", "summary": "Finds min unsigned element in vector.", "syntax": "UMINV , , .", "encoding": { "format": "SVE Reduction", "binary_pattern": "00000100 | size | 0010 | 1 | 1 | 001 | Pg | Zn | Vd", "hex_opcode": "0x040B2000", "visual_parts": [ { "raw": "00000100", "clean": "00000100" }, { "raw": "size", "clean": "size" }, { "raw": "0010", "clean": "0010" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "001", "clean": "001" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Vd", "clean": "Vd" } ], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Vd", "desc": "Dest Scalar" }, { "name": "Pg", "desc": "Mask" }, { "name": "Zn", "desc": "Vector" } ], "extension": "SVE", "description": "SVE unsigned minimum reduction: finds the minimum unsigned element in vector Zn according to predicate mask Pg, and stores the result as a scalar in Vd. The operation compares all active elements as unsigned integers (element size determined by sz) and reduces to a single scalar. No NZCV flags are affected by this instruction.", "example": "UMINV v0.4s, p0/m, z1.s.T", "pseudocode": "bits(esize) result = ALL_ONES(esize);\nfor i = 0 to VL/esize - 1\n if Pg[i] == '1' then\n element = Zn[i*esize +: esize];\n if element < result (unsigned) then result = element;\nVd[0 +: esize] ← result;" }, { "mnemonic": "fmaxv", "architecture": "ARMv8-A", "full_name": "SVE Floating-Point Maximum Reduction", "summary": "Finds max float in vector.", "syntax": "FMAXV , , .", "encoding": { "format": "SVE Reduction", "binary_pattern": "01100101 | size | 000 | 11 | 0 | 001 | Pg | Zn | Vd", "hex_opcode": "0x65062000", "visual_parts": [ { "raw": "01100101", "clean": "01100101" }, { "raw": "size", "clean": "size" }, { "raw": "000", "clean": "000" }, { "raw": "11", "clean": "11" }, { "raw": "0", "clean": "0" }, { "raw": "001", "clean": "001" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Vd", "clean": "Vd" } ], "bit_positions": "31:24 | 23:22 | 21:19 | 18:17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Vd", "desc": "Dest Scalar" }, { "name": "Pg", "desc": "Mask" }, { "name": "Zn", "desc": "Vector" } ], "extension": "SVE", "description": "SVE floating-point maximum reduction: finds the maximum floating-point element in vector Zn according to predicate mask Pg, and stores the result as a scalar in Vd. The operation compares all active elements as IEEE 754 floats (precision determined by sz: 0=half, 1=single or double) using quiet comparison semantics, and reduces to a single scalar. No NZCV flags are affected; SNaNs propagate as the maximum.", "example": "FMAXV v0.4s, p0/m, z1.s.T", "pseudocode": "bits(esize) result = NegInfinity(esize);\nfor i = 0 to VL/esize - 1\n if Pg[i] == '1' then\n element = Zn[i*esize +: esize];\n if element > result (FP) || IsNaN(result) then result = element;\nVd[0 +: esize] ← result;" }, { "mnemonic": "fminv", "architecture": "ARMv8-A", "full_name": "SVE Floating-Point Minimum Reduction", "summary": "Finds min float in vector.", "syntax": "FMINV , , .", "encoding": { "format": "SVE Reduction", "binary_pattern": "01100101 | size | 000 | 11 | 1 | 001 | Pg | Zn | Vd", "hex_opcode": "0x65072000", "visual_parts": [ { "raw": "01100101", "clean": "01100101" }, { "raw": "size", "clean": "size" }, { "raw": "000", "clean": "000" }, { "raw": "11", "clean": "11" }, { "raw": "1", "clean": "1" }, { "raw": "001", "clean": "001" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Vd", "clean": "Vd" } ], "bit_positions": "31:24 | 23:22 | 21:19 | 18:17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Vd", "desc": "Dest Scalar" }, { "name": "Pg", "desc": "Mask" }, { "name": "Zn", "desc": "Vector" } ], "extension": "SVE", "description": "SVE floating-point minimum reduction: finds the minimum floating-point element in vector Zn according to predicate mask Pg, and stores the result as a scalar in Vd. The operation compares all active elements as IEEE 754 floats (precision determined by sz: 0=half, 1=single or double) using quiet comparison semantics, and reduces to a single scalar. No NZCV flags are affected; SNaNs propagate as the minimum.", "example": "FMINV v0.4s, p0/m, z1.s.T", "pseudocode": "bits(esize) result = PosInfinity(esize);\nfor i = 0 to VL/esize - 1\n if Pg[i] == '1' then\n element = Zn[i*esize +: esize];\n if element < result (FP) || IsNaN(result) then result = element;\nVd[0 +: esize] ← result;" }, { "mnemonic": "andv", "architecture": "ARMv8-A", "full_name": "SVE Bitwise AND Reduction", "summary": "ANDs all active elements into a scalar.", "syntax": "ANDV , , .", "encoding": { "format": "SVE Reduction", "binary_pattern": "00000100 | size | 0110 | 1 | 0 | 001 | Pg | Zn | Vd", "hex_opcode": "0x041A2000", "visual_parts": [ { "raw": "00000100", "clean": "00000100" }, { "raw": "size", "clean": "size" }, { "raw": "0110", "clean": "0110" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "001", "clean": "001" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Vd", "clean": "Vd" } ], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Vd", "desc": "Dest Scalar" }, { "name": "Pg", "desc": "Mask" }, { "name": "Zn", "desc": "Vector" } ], "extension": "SVE", "description": "SVE bitwise AND reduction: performs a bitwise AND of all active elements in vector Zn according to predicate mask Pg, and stores the result as a scalar in Vd. The operation reduces a vector of integers to a single scalar by bitwise AND across all selected elements (element size determined by sz). No NZCV flags are affected by this instruction.", "example": "ANDV v0.4s, p0/m, z1.s.T", "pseudocode": "bits(esize) result = ALL_ONES(esize);\nfor i = 0 to VL/esize - 1\n if Pg[i] == '1' then\n element = Zn[i*esize +: esize];\n result = result AND element;\nVd[0 +: esize] ← result;" }, { "mnemonic": "orv", "architecture": "ARMv8-A", "full_name": "SVE Bitwise OR Reduction", "summary": "ORs all active elements into a scalar.", "syntax": "ORV , , .", "encoding": { "format": "SVE Reduction", "binary_pattern": "00000100 | size | 0110 | 0 | 0 | 001 | Pg | Zn | Vd", "hex_opcode": "0x04182000", "visual_parts": [ { "raw": "00000100", "clean": "00000100" }, { "raw": "size", "clean": "size" }, { "raw": "0110", "clean": "0110" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "001", "clean": "001" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Vd", "clean": "Vd" } ], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Vd", "desc": "Dest Scalar" }, { "name": "Pg", "desc": "Mask" }, { "name": "Zn", "desc": "Vector" } ], "extension": "SVE", "description": "SVE bitwise OR reduction: performs a bitwise OR of all active elements in vector Zn according to predicate mask Pg, and stores the result as a scalar in Vd. The operation reduces a vector of integers to a single scalar by bitwise OR across all selected elements (element size determined by sz). No NZCV flags are affected by this instruction.", "example": "ORV v0.4s, p0/m, z1.s.T", "pseudocode": "bits(esize) result = 0;\nfor i = 0 to VL/esize - 1\n if Pg[i] == '1' then\n element = Zn[i*esize +: esize];\n result = result OR element;\nVd[0 +: esize] ← result;" }, { "mnemonic": "eorv", "architecture": "ARMv8-A", "full_name": "SVE Bitwise EOR Reduction", "summary": "XORs all active elements into a scalar.", "syntax": "EORV , , .", "encoding": { "format": "SVE Reduction", "binary_pattern": "00000100 | size | 0110 | 0 | 1 | 001 | Pg | Zn | Vd", "hex_opcode": "0x04192000", "visual_parts": [ { "raw": "00000100", "clean": "00000100" }, { "raw": "size", "clean": "size" }, { "raw": "0110", "clean": "0110" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "001", "clean": "001" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Vd", "clean": "Vd" } ], "bit_positions": "31:24 | 23:22 | 21:18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Vd", "desc": "Dest Scalar" }, { "name": "Pg", "desc": "Mask" }, { "name": "Zn", "desc": "Vector" } ], "extension": "SVE", "description": "SVE bitwise XOR reduction that combines all active predicated elements of a scalable vector into a scalar result. The operation iteratively XORs each active element into the destination scalar register. No condition flags are affected by this instruction. This is an AArch64-only SVE instruction.", "example": "EORV v0.4s, p0/m, z1.s.T", "pseudocode": "bits(smax(8*datasize,32)) result = Vd;\nfor i = 0 to (VL/esize)-1\n if Pg[i]\n result = result XOR Zn[i*esize+esize-1:i*esize]\nVd = result;" }, { "mnemonic": "scvtf", "architecture": "ARMv8-A", "full_name": "SVE Signed Integer Convert to Floating-Point", "summary": "Converts signed integers to floats.", "syntax": "SCVTF ., /M, .", "encoding": { "format": "SVE Conversion", "binary_pattern": "01100101 | 0 | 1 | 010 | 0 | 1 | 0 | 101 | Pg | Zn | Zd", "hex_opcode": "0x6552A000", "visual_parts": [ { "raw": "01100101", "clean": "01100101" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "010", "clean": "010" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "101", "clean": "101" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Zd", "clean": "Zd" } ], "bit_positions": "31:24 | 23 | 22 | 21:19 | 18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zdn", "desc": "Combined destination/source scalable vector register (SVE)" }, { "name": "Pg", "desc": "Mask" } ], "extension": "SVE", "description": "SVE instruction that converts signed integer elements in a scalable vector to floating-point representation. Only active predicated elements are converted; inactive elements are zeroed. The instruction operates under predicate control with zeroing (/Z) semantics. This is an AArch64-only SVE instruction with no NZCV flag effects.", "example": "SCVTF z0.s.T, p0/m/M, z0.s.T", "pseudocode": "for i = 0 to (VL/esize)-1\n if Pg[i]\n Zdn[i*esize+esize-1:i*esize] = ConvertSignedIntegerToFP(Zdn[i*esize+esize-1:i*esize])\n else\n Zdn[i*esize+esize-1:i*esize] = 0" }, { "mnemonic": "ucvtf", "architecture": "ARMv8-A", "full_name": "SVE Unsigned Integer Convert to Floating-Point", "summary": "Converts unsigned integers to floats.", "syntax": "UCVTF ., /M, .", "encoding": { "format": "SVE Conversion", "binary_pattern": "01100101 | 0 | 1 | 010 | 0 | 1 | 1 | 101 | Pg | Zn | Zd", "hex_opcode": "0x6553A000", "visual_parts": [ { "raw": "01100101", "clean": "01100101" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "010", "clean": "010" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "101", "clean": "101" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Zd", "clean": "Zd" } ], "bit_positions": "31:24 | 23 | 22 | 21:19 | 18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zdn", "desc": "Combined destination/source scalable vector register (SVE)" }, { "name": "Pg", "desc": "Mask" } ], "extension": "SVE", "description": "SVE instruction that converts unsigned integer elements in a scalable vector to floating-point representation. Only active predicated elements are converted; inactive elements are zeroed. The instruction operates under predicate control with zeroing (/Z) semantics. This is an AArch64-only SVE instruction with no NZCV flag effects.", "example": "UCVTF z0.s.T, p0/m/M, z0.s.T", "pseudocode": "for i = 0 to (VL/esize)-1\n if Pg[i]\n Zdn[i*esize+esize-1:i*esize] = ConvertUnsignedIntegerToFP(Zdn[i*esize+esize-1:i*esize])\n else\n Zdn[i*esize+esize-1:i*esize] = 0" }, { "mnemonic": "fcvtzs", "architecture": "ARMv8-A", "full_name": "SVE Floating-Point Convert to Signed Integer", "summary": "Converts floats to signed integers (Truncate).", "syntax": "FCVTZS ., /M, .", "encoding": { "format": "SVE Conversion", "binary_pattern": "01100101 | 0 | 1 | 011 | 0 | 1 | 0 | 101 | Pg | Zn | Zd", "hex_opcode": "0x655AA000", "visual_parts": [ { "raw": "01100101", "clean": "01100101" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "011", "clean": "011" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "101", "clean": "101" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Zd", "clean": "Zd" } ], "bit_positions": "31:24 | 23 | 22 | 21:19 | 18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zdn", "desc": "Combined destination/source scalable vector register (SVE)" }, { "name": "Pg", "desc": "Mask" } ], "extension": "SVE", "description": "SVE instruction that converts floating-point elements in a scalable vector to signed integer representation by truncation toward zero. Only active predicated elements are converted; inactive elements are zeroed. The instruction operates under predicate control with zeroing (/Z) semantics. This is an AArch64-only SVE instruction with no NZCV flag effects.", "example": "FCVTZS z0.s.T, p0/m/M, z0.s.T", "pseudocode": "for i = 0 to (VL/esize)-1\n if Pg[i]\n Zdn[i*esize+esize-1:i*esize] = ConvertFPToSignedIntegerTruncate(Zdn[i*esize+esize-1:i*esize])\n else\n Zdn[i*esize+esize-1:i*esize] = 0" }, { "mnemonic": "fcvtzu", "architecture": "ARMv8-A", "full_name": "SVE Floating-Point Convert to Unsigned Integer", "summary": "Converts floats to unsigned integers (Truncate).", "syntax": "FCVTZU ., /M, .", "encoding": { "format": "SVE Conversion", "binary_pattern": "01100101 | 0 | 1 | 011 | 0 | 1 | 1 | 101 | Pg | Zn | Zd", "hex_opcode": "0x655BA000", "visual_parts": [ { "raw": "01100101", "clean": "01100101" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "011", "clean": "011" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "101", "clean": "101" }, { "raw": "Pg", "clean": "Pg" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Zd", "clean": "Zd" } ], "bit_positions": "31:24 | 23 | 22 | 21:19 | 18 | 17 | 16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Zdn", "desc": "Combined destination/source scalable vector register (SVE)" }, { "name": "Pg", "desc": "Mask" } ], "extension": "SVE", "description": "SVE instruction that converts floating-point elements in a scalable vector to unsigned integer representation by truncation toward zero. Only active predicated elements are converted; inactive elements are zeroed. The instruction operates under predicate control with zeroing (/Z) semantics. This is an AArch64-only SVE instruction with no NZCV flag effects.", "example": "FCVTZU z0.s.T, p0/m/M, z0.s.T", "pseudocode": "for i = 0 to (VL/esize)-1\n if Pg[i]\n Zdn[i*esize+esize-1:i*esize] = ConvertFPToUnsignedIntegerTruncate(Zdn[i*esize+esize-1:i*esize])\n else\n Zdn[i*esize+esize-1:i*esize] = 0" }, { "mnemonic": "smulbb", "architecture": "ARMv8-A", "full_name": "Signed Multiply (Bottom x Bottom)", "summary": "Multiplies bottom 16 bits of Rn and Rm.", "syntax": "SMULBB , , ", "encoding": { "format": "Multiply", "binary_pattern": "cond | 00010 | 11 | 0 | Rd | 0000 | Rm | 1 | 0 | 0 | 0 | Rn", "hex_opcode": "0x01600080", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00010", "clean": "00010" }, { "raw": "11", "clean": "11" }, { "raw": "0", "clean": "0" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "0000", "clean": "0000" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "Src 1 (Bot)" }, { "name": "Rm", "desc": "Src 2 (Bot)" } ], "extension": "A32 (DSP)", "description": "Multiplies the bottom 16 bits (bits [15:0]) of Rn by the bottom 16 bits of Rm as signed integers, producing a 32-bit signed result in Rd. This is an A32 DSP instruction that does not update condition flags.", "example": "SMULBB r0, r1, r2", "pseudocode": "if ConditionPassed() then\n operand1 = SignExtend(Rn[15:0], 32)\n operand2 = SignExtend(Rm[15:0], 32)\n Rd = operand1 * operand2" }, { "mnemonic": "smulbt", "architecture": "ARMv8-A", "full_name": "Signed Multiply (Bottom x Top)", "summary": "Multiplies bottom 16 bits of Rn and top 16 bits of Rm.", "syntax": "SMULBT , , ", "encoding": { "format": "Multiply", "binary_pattern": "cond | 00010 | 11 | 0 | Rd | 0000 | Rm | 1 | 1 | 0 | 0 | Rn", "hex_opcode": "0x016000C0", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00010", "clean": "00010" }, { "raw": "11", "clean": "11" }, { "raw": "0", "clean": "0" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "0000", "clean": "0000" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "Src 1 (Bot)" }, { "name": "Rm", "desc": "Src 2 (Top)" } ], "extension": "A32 (DSP)", "description": "A32 DSP multiply instruction that multiplies the bottom 16 bits (signed) of Rn by the top 16 bits (signed) of Rm and stores the 32-bit result in Rd. The instruction is conditional and does not affect the NZCV condition flags. Q flag behavior is not documented for this instruction in standard architectures.", "example": "SMULBT r0, r1, r2", "pseudocode": "operand1 = SignExtend(Rn<15:0>, 32)\noperand2 = SignExtend(Rm<31:16>, 32)\nRd = (operand1 * operand2)<31:0>" }, { "mnemonic": "smultb", "architecture": "ARMv8-A", "full_name": "Signed Multiply (Top x Bottom)", "summary": "Multiplies top 16 bits of Rn and bottom 16 bits of Rm.", "syntax": "SMULTB , , ", "encoding": { "format": "Multiply", "binary_pattern": "cond | 00010 | 11 | 0 | Rd | 0000 | Rm | 1 | 0 | 1 | 0 | Rn", "hex_opcode": "0x016000A0", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00010", "clean": "00010" }, { "raw": "11", "clean": "11" }, { "raw": "0", "clean": "0" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "0000", "clean": "0000" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "Src 1 (Top)" }, { "name": "Rm", "desc": "Src 2 (Bot)" } ], "extension": "A32 (DSP)", "description": "A32 DSP multiply instruction that multiplies the top 16 bits (signed) of Rn by the bottom 16 bits (signed) of Rm and stores the 32-bit result in Rd. The instruction is conditional and does not affect the NZCV condition flags. Q flag behavior is not documented for this instruction in standard architectures.", "example": "SMULTB r0, r1, r2", "pseudocode": "operand1 = SignExtend(Rn<31:16>, 32)\noperand2 = SignExtend(Rm<15:0>, 32)\nRd = (operand1 * operand2)<31:0>" }, { "mnemonic": "smultt", "architecture": "ARMv8-A", "full_name": "Signed Multiply (Top x Top)", "summary": "Multiplies top 16 bits of Rn and top 16 bits of Rm.", "syntax": "SMULTT , , ", "encoding": { "format": "Multiply", "binary_pattern": "cond | 00010 | 11 | 0 | Rd | 0000 | Rm | 1 | 1 | 1 | 0 | Rn", "hex_opcode": "0x016000E0", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00010", "clean": "00010" }, { "raw": "11", "clean": "11" }, { "raw": "0", "clean": "0" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "0000", "clean": "0000" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "Src 1 (Top)" }, { "name": "Rm", "desc": "Src 2 (Top)" } ], "extension": "A32 (DSP)", "description": "A32 DSP multiply instruction that multiplies the top 16 bits (signed) of Rn by the top 16 bits (signed) of Rm and stores the 32-bit result in Rd. The instruction is conditional and does not affect the NZCV condition flags. Q flag behavior is not documented for this instruction in standard architectures.", "example": "SMULTT r0, r1, r2", "pseudocode": "operand1 = SignExtend(Rn<31:16>, 32)\noperand2 = SignExtend(Rm<31:16>, 32)\nRd = (operand1 * operand2)<31:0>" }, { "mnemonic": "smlabb", "architecture": "ARMv8-A", "full_name": "Signed Multiply Accumulate (Bottom x Bottom)", "summary": "Accumulates (Rn.B * Rm.B) into Ra.", "syntax": "SMLABB , , , ", "encoding": { "format": "Multiply", "binary_pattern": "cond | 00010 | 00 | 0 | Rd | Ra | Rm | 1 | 0 | 0 | 0 | Rn", "hex_opcode": "0x01000080", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00010", "clean": "00010" }, { "raw": "00", "clean": "00" }, { "raw": "0", "clean": "0" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "Ra", "clean": "Ra" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" }, { "name": "Ra", "desc": "Acc" } ], "extension": "A32 (DSP)", "description": "Signed multiply-accumulate of the bottom 16-bit halfwords of Rn and Rm, with the 32-bit product added to Ra and stored in Rd. This is an A32 DSP instruction that operates on 16-bit subregisters. The Q flag may be set if overflow occurs during accumulation, but N, Z, C, V flags are unchanged.", "example": "SMLABB r0, r1, r2, r5", "pseudocode": "temp ← SignExtend(Rn[15:0], 32) * SignExtend(Rm[15:0], 32);\nresult ← temp + Ra;\nif OverflowFrom_Addition(temp, Ra) then Q ← 1; end if;\nRd ← result;" }, { "mnemonic": "smlabt", "architecture": "ARMv8-A", "full_name": "Signed Multiply Accumulate (Bottom x Top)", "summary": "Accumulates (Rn.B * Rm.T) into Ra.", "syntax": "SMLABT , , , ", "encoding": { "format": "Multiply", "binary_pattern": "cond | 00010 | 00 | 0 | Rd | Ra | Rm | 1 | 1 | 0 | 0 | Rn", "hex_opcode": "0x010000C0", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00010", "clean": "00010" }, { "raw": "00", "clean": "00" }, { "raw": "0", "clean": "0" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "Ra", "clean": "Ra" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" }, { "name": "Ra", "desc": "Acc" } ], "extension": "A32 (DSP)", "description": "Signed multiply-accumulate of the bottom 16-bit halfword of Rn and the top 16-bit halfword of Rm, with the 32-bit product added to Ra and stored in Rd. This is an A32 DSP instruction that operates on 16-bit subregisters. The Q flag may be set if overflow occurs during accumulation, but N, Z, C, V flags are unchanged.", "example": "SMLABT r0, r1, r2, r5", "pseudocode": "temp ← SignExtend(Rn[15:0], 32) * SignExtend(Rm[31:16], 32);\nresult ← temp + Ra;\nif OverflowFrom_Addition(temp, Ra) then Q ← 1; end if;\nRd ← result;" }, { "mnemonic": "smlatb", "architecture": "ARMv8-A", "full_name": "Signed Multiply Accumulate (Top x Bottom)", "summary": "Accumulates (Rn.T * Rm.B) into Ra.", "syntax": "SMLATB , , , ", "encoding": { "format": "Multiply", "binary_pattern": "cond | 00010 | 00 | 0 | Rd | Ra | Rm | 1 | 0 | 1 | 0 | Rn", "hex_opcode": "0x010000A0", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00010", "clean": "00010" }, { "raw": "00", "clean": "00" }, { "raw": "0", "clean": "0" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "Ra", "clean": "Ra" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" }, { "name": "Ra", "desc": "Acc" } ], "extension": "A32 (DSP)", "description": "Signed multiply-accumulate of the top 16-bit halfword of Rn and the bottom 16-bit halfword of Rm, with the 32-bit product added to Ra and stored in Rd. This is an A32 DSP instruction that operates on 16-bit subregisters. The Q flag may be set if overflow occurs during accumulation, but N, Z, C, V flags are unchanged.", "example": "SMLATB r0, r1, r2, r5", "pseudocode": "temp ← SignExtend(Rn[31:16], 32) * SignExtend(Rm[15:0], 32);\nresult ← temp + Ra;\nif OverflowFrom_Addition(temp, Ra) then Q ← 1; end if;\nRd ← result;" }, { "mnemonic": "smlatt", "architecture": "ARMv8-A", "full_name": "Signed Multiply Accumulate (Top x Top)", "summary": "Accumulates (Rn.T * Rm.T) into Ra.", "syntax": "SMLATT , , , ", "encoding": { "format": "Multiply", "binary_pattern": "cond | 00010 | 00 | 0 | Rd | Ra | Rm | 1 | 1 | 1 | 0 | Rn", "hex_opcode": "0x010000E0", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00010", "clean": "00010" }, { "raw": "00", "clean": "00" }, { "raw": "0", "clean": "0" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "Ra", "clean": "Ra" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" }, { "name": "Ra", "desc": "Acc" } ], "extension": "A32 (DSP)", "description": "Signed multiply-accumulate of the top 16-bit halfwords of Rn and Rm, with the 32-bit product added to Ra and stored in Rd. This is an A32 DSP instruction that operates on 16-bit subregisters. The Q flag may be set if overflow occurs during accumulation, but N, Z, C, V flags are unchanged.", "example": "SMLATT r0, r1, r2, r5", "pseudocode": "temp ← SignExtend(Rn[31:16], 32) * SignExtend(Rm[31:16], 32);\nresult ← temp + Ra;\nif OverflowFrom_Addition(temp, Ra) then Q ← 1; end if;\nRd ← result;" }, { "mnemonic": "smulwb", "architecture": "ARMv8-A", "full_name": "Signed Multiply (Word x Bottom)", "summary": "Multiplies 32-bit Rn by bottom 16-bits of Rm, takes top 32-bits of result.", "syntax": "SMULWB , , ", "encoding": { "format": "Multiply", "binary_pattern": "cond | 00010 | 01 | 0 | Rd | 0000 | Rm | 1 | 0 | 1 | 0 | Rn", "hex_opcode": "0x012000A0", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00010", "clean": "00010" }, { "raw": "01", "clean": "01" }, { "raw": "0", "clean": "0" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "0000", "clean": "0000" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "Word Src" }, { "name": "Rm", "desc": "Half Src" } ], "extension": "A32 (DSP)", "description": "Signed multiply of the 32-bit Rn by the bottom 16-bit halfword of Rm, extracting the top 32 bits of the 48-bit product into Rd. This is an A32 DSP instruction that produces no flag changes; overflow is not indicated.", "example": "SMULWB r0, r1, r2", "pseudocode": "product ← SignExtend(Rn[31:0], 48) * SignExtend(Rm[15:0], 48);\nRd ← product[47:16];" }, { "mnemonic": "smulwt", "architecture": "ARMv8-A", "full_name": "Signed Multiply (Word x Top)", "summary": "Multiplies 32-bit Rn by top 16-bits of Rm, takes top 32-bits of result.", "syntax": "SMULWT , , ", "encoding": { "format": "Multiply", "binary_pattern": "cond | 00010 | 01 | 0 | Rd | 0000 | Rm | 1 | 1 | 1 | 0 | Rn", "hex_opcode": "0x012000E0", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00010", "clean": "00010" }, { "raw": "01", "clean": "01" }, { "raw": "0", "clean": "0" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "0000", "clean": "0000" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "Word Src" }, { "name": "Rm", "desc": "Half Src" } ], "extension": "A32 (DSP)", "description": "Signed multiply of the 32-bit Rn by the top 16-bit halfword of Rm, extracting the top 32 bits of the 48-bit product into Rd. This is an A32 DSP instruction that produces no flag changes; overflow is not indicated.", "example": "SMULWT r0, r1, r2", "pseudocode": "product ← SignExtend(Rn[31:0], 48) * SignExtend(Rm[31:16], 48);\nRd ← product[47:16];" }, { "mnemonic": "smlawb", "architecture": "ARMv8-A", "full_name": "Signed Multiply Accumulate (Word x Bottom)", "summary": "Performs SMULWB and adds to accumulator.", "syntax": "SMLAWB , , , ", "encoding": { "format": "Multiply", "binary_pattern": "cond | 00010 | 01 | 0 | Rd | Ra | Rm | 1 | 0 | 0 | 0 | Rn", "hex_opcode": "0x01200080", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00010", "clean": "00010" }, { "raw": "01", "clean": "01" }, { "raw": "0", "clean": "0" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "Ra", "clean": "Ra" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "Word" }, { "name": "Rm", "desc": "Half" }, { "name": "Ra", "desc": "Acc" } ], "extension": "A32 (DSP)", "description": "Signed multiply-accumulate combining SMULWB with addition of Ra; multiplies 32-bit Rn by the bottom 16-bit halfword of Rm, takes the top 32 bits of the product, adds Ra, and stores in Rd. This is an A32 DSP instruction. The Q flag may be set if overflow occurs during accumulation, but N, Z, C, V flags are unchanged.", "example": "SMLAWB r0, r1, r2, r5", "pseudocode": "product ← SignExtend(Rn[31:0], 48) * SignExtend(Rm[15:0], 48);\ntemp ← product[47:16];\nresult ← temp + Ra;\nif OverflowFrom_Addition(temp, Ra) then Q ← 1; end if;\nRd ← result;" }, { "mnemonic": "smlawt", "architecture": "ARMv8-A", "full_name": "Signed Multiply Accumulate (Word x Top)", "summary": "Performs SMULWT and adds to accumulator.", "syntax": "SMLAWT , , , ", "encoding": { "format": "Multiply", "binary_pattern": "cond | 00010 | 01 | 0 | Rd | Ra | Rm | 1 | 1 | 0 | 0 | Rn", "hex_opcode": "0x012000C0", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00010", "clean": "00010" }, { "raw": "01", "clean": "01" }, { "raw": "0", "clean": "0" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "Ra", "clean": "Ra" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "Word" }, { "name": "Rm", "desc": "Half" }, { "name": "Ra", "desc": "Acc" } ], "extension": "A32 (DSP)", "description": "Signed multiply-accumulate combining SMULWT with addition of Ra; multiplies 32-bit Rn by the top 16-bit halfword of Rm, takes the top 32 bits of the product, adds Ra, and stores in Rd. This is an A32 DSP instruction. The Q flag may be set if overflow occurs during accumulation, but N, Z, C, V flags are unchanged.", "example": "SMLAWT r0, r1, r2, r5", "pseudocode": "product ← SignExtend(Rn[31:0], 48) * SignExtend(Rm[31:16], 48);\ntemp ← product[47:16];\nresult ← temp + Ra;\nif OverflowFrom_Addition(temp, Ra) then Q ← 1; end if;\nRd ← result;" }, { "mnemonic": "smlalbb", "architecture": "ARMv8-A", "full_name": "Signed Multiply Accumulate Long (Bottom x Bottom)", "summary": "Accumulates (Rn.B * Rm.B) into 64-bit pair.", "syntax": "SMLALBB , , , ", "encoding": { "format": "Multiply", "binary_pattern": "cond | 00010 | 10 | 0 | RdHi | RdLo | Rm | 1 | 0 | 0 | 0 | Rn", "hex_opcode": "0x01400080", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00010", "clean": "00010" }, { "raw": "10", "clean": "10" }, { "raw": "0", "clean": "0" }, { "raw": "RdHi", "clean": "RdHi" }, { "raw": "RdLo", "clean": "RdLo" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "RdLo", "desc": "Lo" }, { "name": "RdHi", "desc": "Hi" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Signed Multiply Accumulate Long (Bottom × Bottom) multiplies the bottom 16 bits of Rn by the bottom 16 bits of Rm, treating both as signed, and accumulates the 32-bit result into the 64-bit value formed by RdHi:RdLo. This A32 DSP extension instruction does not update condition flags and is not available in AArch64.", "example": "SMLALBB r1, r0, r1, r2", "pseudocode": "operand1 ← SignExtend(Rn[15:0], 32);\noperand2 ← SignExtend(Rm[15:0], 32);\nresult ← operand1 * operand2;\nRdHi:RdLo ← RdHi:RdLo + result;" }, { "mnemonic": "smlalbt", "architecture": "ARMv8-A", "full_name": "Signed Multiply Accumulate Long (Bottom x Top)", "summary": "Accumulates (Rn.B * Rm.T) into 64-bit pair.", "syntax": "SMLALBT , , , ", "encoding": { "format": "Multiply", "binary_pattern": "cond | 00010 | 10 | 0 | RdHi | RdLo | Rm | 1 | 1 | 0 | 0 | Rn", "hex_opcode": "0x014000C0", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00010", "clean": "00010" }, { "raw": "10", "clean": "10" }, { "raw": "0", "clean": "0" }, { "raw": "RdHi", "clean": "RdHi" }, { "raw": "RdLo", "clean": "RdLo" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "RdLo", "desc": "Lo" }, { "name": "RdHi", "desc": "Hi" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Signed Multiply Accumulate Long (Bottom × Top) multiplies the bottom 16 bits of Rn by the top 16 bits of Rm, treating both as signed, and accumulates the 32-bit result into the 64-bit value formed by RdHi:RdLo. This A32 DSP extension instruction does not update condition flags and is not available in AArch64.", "example": "SMLALBT r1, r0, r1, r2", "pseudocode": "operand1 ← SignExtend(Rn[15:0], 32);\noperand2 ← SignExtend(Rm[31:16], 32);\nresult ← operand1 * operand2;\nRdHi:RdLo ← RdHi:RdLo + result;" }, { "mnemonic": "smlaltb", "architecture": "ARMv8-A", "full_name": "Signed Multiply Accumulate Long (Top x Bottom)", "summary": "Accumulates (Rn.T * Rm.B) into 64-bit pair.", "syntax": "SMLALTB , , , ", "encoding": { "format": "Multiply", "binary_pattern": "cond | 00010 | 10 | 0 | RdHi | RdLo | Rm | 1 | 0 | 1 | 0 | Rn", "hex_opcode": "0x014000A0", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00010", "clean": "00010" }, { "raw": "10", "clean": "10" }, { "raw": "0", "clean": "0" }, { "raw": "RdHi", "clean": "RdHi" }, { "raw": "RdLo", "clean": "RdLo" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "RdLo", "desc": "Lo" }, { "name": "RdHi", "desc": "Hi" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Signed Multiply Accumulate Long (Top × Bottom) multiplies the top 16 bits of Rn by the bottom 16 bits of Rm, treating both as signed, and accumulates the 32-bit result into the 64-bit value formed by RdHi:RdLo. This A32 DSP extension instruction does not update condition flags and is not available in AArch64.", "example": "SMLALTB r1, r0, r1, r2", "pseudocode": "operand1 ← SignExtend(Rn[31:16], 32);\noperand2 ← SignExtend(Rm[15:0], 32);\nresult ← operand1 * operand2;\nRdHi:RdLo ← RdHi:RdLo + result;" }, { "mnemonic": "smlaltt", "architecture": "ARMv8-A", "full_name": "Signed Multiply Accumulate Long (Top x Top)", "summary": "Accumulates (Rn.T * Rm.T) into 64-bit pair.", "syntax": "SMLALTT , , , ", "encoding": { "format": "Multiply", "binary_pattern": "cond | 00010 | 10 | 0 | RdHi | RdLo | Rm | 1 | 1 | 1 | 0 | Rn", "hex_opcode": "0x014000E0", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00010", "clean": "00010" }, { "raw": "10", "clean": "10" }, { "raw": "0", "clean": "0" }, { "raw": "RdHi", "clean": "RdHi" }, { "raw": "RdLo", "clean": "RdLo" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "RdLo", "desc": "Lo" }, { "name": "RdHi", "desc": "Hi" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Signed Multiply Accumulate Long (Top × Top) multiplies the top 16 bits of Rn by the top 16 bits of Rm, treating both as signed, and accumulates the 32-bit result into the 64-bit value formed by RdHi:RdLo. This A32 DSP extension instruction does not update condition flags and is not available in AArch64.", "example": "SMLALTT r1, r0, r1, r2", "pseudocode": "operand1 ← SignExtend(Rn[31:16], 32);\noperand2 ← SignExtend(Rm[31:16], 32);\nresult ← operand1 * operand2;\nRdHi:RdLo ← RdHi:RdLo + result;" }, { "mnemonic": "mia", "architecture": "ARMv8-A", "full_name": "Multiply with Internal Accumulate", "summary": "Multiplies two 32-bit values and adds to 40-bit internal acc (XScale Legacy).", "syntax": "MIA , , ", "encoding": { "format": "Coprocessor", "binary_pattern": "cond | 11100010 | 0000 | Rn | Acc | 0000 | 0001 | Rm", "hex_opcode": "0x0E200010", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "11100010", "clean": "11100010" }, { "raw": "0000", "clean": "0000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Acc", "clean": "Acc" }, { "raw": "0000", "clean": "0000" }, { "raw": "0001", "clean": "0001" }, { "raw": "Rm", "clean": "Rm" } ] }, "operands": [ { "name": "Acc", "desc": "Accumulator" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (XScale)", "description": "Multiply with Internal Accumulate multiplies two 32-bit values (Rn and Rm) and adds the 64-bit result to a 40-bit internal accumulator indexed by Acc. This XScale legacy A32 instruction is encoded as a coprocessor operation; condition flags are not updated, and this instruction is deprecated in modern ARM implementations.", "example": "MIA Acc, r1, r2", "pseudocode": "operand1 ← SignExtend(Rn, 64);\noperand2 ← SignExtend(Rm, 64);\nproduct ← operand1 * operand2;\ninternalAccumulator[Acc] ← internalAccumulator[Acc] + product;" }, { "mnemonic": "miaph", "architecture": "ARMv8-A", "full_name": "Multiply with Internal Accumulate Packed Halfwords", "summary": "SIMD multiply of packed halfwords to internal acc (XScale Legacy).", "syntax": "MIAPH , , ", "encoding": { "format": "Coprocessor", "binary_pattern": "cond | 11100010 | 1000 | Rn | Acc | 0000 | 0001 | Rm", "hex_opcode": "0x0E280010", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "11100010", "clean": "11100010" }, { "raw": "1000", "clean": "1000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Acc", "clean": "Acc" }, { "raw": "0000", "clean": "0000" }, { "raw": "0001", "clean": "0001" }, { "raw": "Rm", "clean": "Rm" } ] }, "operands": [ { "name": "Acc", "desc": "Accumulator" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (XScale)", "description": "Multiply with Internal Accumulate Packed Halfwords performs SIMD multiplication of two packed 16-bit signed halfwords from Rn and Rm, accumulating each product into corresponding 40-bit internal accumulators. This XScale legacy A32 instruction is encoded as a coprocessor operation; condition flags are not updated, and this instruction is deprecated in modern ARM implementations.", "example": "MIAPH Acc, r1, r2", "pseudocode": "operand1_low ← SignExtend(Rn[15:0], 32);\noperand1_high ← SignExtend(Rn[31:16], 32);\noperand2_low ← SignExtend(Rm[15:0], 32);\noperand2_high ← SignExtend(Rm[31:16], 32);\nproduct_low ← operand1_low * operand2_low;\nproduct_high ← operand1_high * operand2_high;\ninternalAccumulator[Acc] ← internalAccumulator[Acc] + product_low;\ninternalAccumulator[Acc+1] ← internalAccumulator[Acc+1] + product_high;" }, { "mnemonic": "sha256h", "architecture": "ARMv8-A", "full_name": "SHA256 Hash Part 1 (A32)", "summary": "SHA256 hash update (part 1).", "syntax": "SHA256H.32 , , ", "encoding": { "format": "Crypto 3-Reg", "binary_pattern": "11110011 | 0 | 0 | 0 | Vn | Vd | 1100 | N | Q | M | 0 | Vm", "hex_opcode": "0xF3000C00", "visual_parts": [ { "raw": "11110011", "clean": "11110011" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1100", "clean": "1100" }, { "raw": "N", "clean": "N" }, { "raw": "Q", "clean": "Q" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ] }, "operands": [ { "name": "Qd", "desc": "State" }, { "name": "Qn", "desc": "Hash" }, { "name": "Qm", "desc": "Data" } ], "extension": "Crypto", "description": "SHA256 Hash Part 1 performs the first half of a SHA256 hash update operation on 128-bit NEON registers, processing the W array intermediate values. Qd receives updated hash state W[t] and W[t+1]; Qn provides the previous hash state; Qm provides the input data block words. This A32 Crypto extension instruction does not update condition flags and requires NEON support.", "example": "SHA256H.32 q0, q1, q2", "pseudocode": "hash_state ← Qd;\nw_data ← Qn;\ndata_words ← Qm;\ntemp ← SHA256_CH(hash_state.word[1], hash_state.word[2], hash_state.word[3]);\ntemp ← temp + SHA256_SUM1(hash_state.word[1]);\ntemp ← temp + data_words;\nQd.word[0] ← Qd.word[0] + temp;\nQd.word[1] ← hash_state.word[0];" }, { "mnemonic": "sha256h2", "architecture": "ARMv8-A", "full_name": "SHA256 Hash Part 2 (A32)", "summary": "SHA256 hash update (part 2).", "syntax": "SHA256H2.32 , , ", "encoding": { "format": "Crypto 3-Reg", "binary_pattern": "11110011 | 0 | 0 | 0 | Vn | Vd | 1100 | N | Q | M | 1 | Vm", "hex_opcode": "0xF3100C00", "visual_parts": [ { "raw": "11110011", "clean": "11110011" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1100", "clean": "1100" }, { "raw": "N", "clean": "N" }, { "raw": "Q", "clean": "Q" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ] }, "operands": [ { "name": "Qd", "desc": "State" }, { "name": "Qn", "desc": "Hash" }, { "name": "Qm", "desc": "Data" } ], "extension": "Crypto", "description": "SHA256 Hash Part 2 performs the second half of a SHA256 hash update operation on 128-bit NEON registers, processing the W array and final hash update. Qd receives the final hash state; Qn provides the hash value from the previous SHA256H instruction; Qm provides the input data block words. This A32 Crypto extension instruction does not update condition flags and requires NEON support.", "example": "SHA256H2.32 q0, q1, q2", "pseudocode": "hash_state ← Qd;\nw_data ← Qn;\ndata_words ← Qm;\ntemp ← SHA256_CH(hash_state.word[0], hash_state.word[1], hash_state.word[2]);\ntemp ← temp + SHA256_SUM1(hash_state.word[0]);\ntemp ← temp + data_words;\nQd.word[1] ← Qd.word[1] + temp;\nQd.word[0] ← hash_state.word[3];" }, { "mnemonic": "sha256su0", "architecture": "ARMv8-A", "full_name": "SHA256 Schedule Update 0 (A32)", "summary": "SHA256 schedule update instruction 0.", "syntax": "SHA256SU0.32 , ", "encoding": { "format": "Crypto 2-Reg", "binary_pattern": "11110011 | 1 | D | 11 | 10 | 10 | Vd | 00100 | Q | M | 0 | Vm", "hex_opcode": "0xF3B203C0", "visual_parts": [ { "raw": "11110011", "clean": "11110011" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "00100", "clean": "00100" }, { "raw": "Q", "clean": "Q" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:24 | 23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11:7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "Crypto", "description": "SHA256 Schedule Update 0 performs the first part of SHA256 message schedule expansion on four 32-bit words held in a 128-bit SIMD register. It processes the sigma_0 function as part of the SHA256 cryptographic algorithm. No condition flags are modified. This instruction requires the ARM Cryptography Extensions and executes only in A32 (ARM) state.", "example": "SHA256SU0.32 q0, q2", "pseudocode": "W[t] ← (W[t] >>> 7) XOR (W[t] >>> 18) XOR (W[t] >> 3); Qd ← result of applying this transformation to each 32-bit element of Qm" }, { "mnemonic": "sha256su1", "architecture": "ARMv8-A", "full_name": "SHA256 Schedule Update 1 (A32)", "summary": "SHA256 schedule update instruction 1.", "syntax": "SHA256SU1.32 , , ", "encoding": { "format": "Crypto 3-Reg", "binary_pattern": "11110011 | 0 | 0 | 0 | Vn | Vd | 1101 | N | Q | M | 0 | Vm", "hex_opcode": "0xF3200C00", "visual_parts": [ { "raw": "11110011", "clean": "11110011" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1101", "clean": "1101" }, { "raw": "N", "clean": "N" }, { "raw": "Q", "clean": "Q" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ] }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "Crypto", "description": "SHA256 Schedule Update 1 performs the second part of SHA256 message schedule expansion, combining three 128-bit registers to compute new message schedule words. It implements the full sigma_0(W[t-15]) + W[t-7] + sigma_1(W[t-2]) + W[t-16] operation. No condition flags are modified. This instruction requires the ARM Cryptography Extensions and executes only in A32 (ARM) state.", "example": "SHA256SU1.32 q0, q1, q2", "pseudocode": "Qd ← Qd + (Qn >>> 17) XOR (Qn >>> 19) XOR (Qn >> 10) + (Qm <<< 25) XOR (Qm <<< 14) XOR (Qm >> 6); (applied element-wise to 32-bit values)" }, { "mnemonic": "sdot", "architecture": "ARMv8-A", "full_name": "Signed Dot Product (A32)", "summary": "Signed Dot Product (vector by vector).", "syntax": "SDOT.S8 , , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "01000100000 | Zm | 11001 | 0 | Zn | Zda", "hex_opcode": "0x4400C800", "visual_parts": [ { "raw": "01000100000", "clean": "01000100000" }, { "raw": "Zm", "clean": "Zm" }, { "raw": "11001", "clean": "11001" }, { "raw": "0", "clean": "0" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Zda", "clean": "Zda" } ], "bit_positions": "31:21 | 20:16 | 15:11 | 10 | 9:5 | 4:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (DotProd)", "description": "Signed Dot Product computes the dot product of four signed 8-bit integer elements from Qn and Qm, accumulating the result into the corresponding 32-bit element of Qd. Four separate dot products are computed in parallel across the 128-bit vectors. No condition flags are modified. This instruction requires the NEON Dot Product extension and executes in A32 (ARM) state.", "example": "SDOT.S8 q0, q1, q2", "pseudocode": "for i in [0, 1, 2, 3]:\n Qd[i*32+31:i*32] ← Qd[i*32+31:i*32] + SignedDotProduct(Qn[i*32+31:i*32], Qm[i*32+31:i*32])" }, { "mnemonic": "udot", "architecture": "ARMv8-A", "full_name": "Unsigned Dot Product (A32)", "summary": "Unsigned Dot Product (vector by vector).", "syntax": "UDOT.U8 , , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "01000100000 | Zm | 11001 | 1 | Zn | Zda", "hex_opcode": "0x4400CC00", "visual_parts": [ { "raw": "01000100000", "clean": "01000100000" }, { "raw": "Zm", "clean": "Zm" }, { "raw": "11001", "clean": "11001" }, { "raw": "1", "clean": "1" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Zda", "clean": "Zda" } ], "bit_positions": "31:21 | 20:16 | 15:11 | 10 | 9:5 | 4:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (DotProd)", "description": "Unsigned Dot Product computes the dot product of four unsigned 8-bit integer elements from Qn and Qm, accumulating the result into the corresponding 32-bit element of Qd. Four separate dot products are computed in parallel across the 128-bit vectors. No condition flags are modified. This instruction requires the NEON Dot Product extension and executes in A32 (ARM) state.", "example": "UDOT.U8 q0, q1, q2", "pseudocode": "for i in [0, 1, 2, 3]:\n Qd[i*32+31:i*32] ← Qd[i*32+31:i*32] + UnsignedDotProduct(Qn[i*32+31:i*32], Qm[i*32+31:i*32])" }, { "mnemonic": "vmmla", "architecture": "ARMv8-A", "full_name": "Matrix Multiply Accumulate (A32)", "summary": "Matrix multiply-accumulate (BFloat16/Int8).", "syntax": "VMMLA.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111110 | 00 | D | 0 | 0 | Vn | Vd | 1 | 1 | 0 | 0 | N | 1 | M | 0 | Vm", "hex_opcode": "0xFC000C40", "visual_parts": [ { "raw": "1111110", "clean": "1111110" }, { "raw": "00", "clean": "00" }, { "raw": "D", "clean": "D" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "N", "clean": "N" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24:23 | 22 | 21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (MatMul)", "description": "Vector Matrix Multiply-Accumulate performs a 4×4 matrix multiply-accumulate operation on either 8-bit integers or BFloat16 values, with results accumulated into Qd. When sz=0, operates on signed/unsigned 8-bit elements; when sz=1, operates on BFloat16 elements. No condition flags are modified. This instruction requires the NEON Matrix Multiply extension and executes in A32 (ARM) state.", "example": "VMMLA.dt q0, q1, q2", "pseudocode": "if sz == 0:\n Qd ← Qd + MatMul_Int8(Qn, Qm) (4x4 matrix multiply of int8 elements)\nelse:\n Qd ← Qd + MatMul_BF16(Qn, Qm) (4x4 matrix multiply of bfloat16 elements)" }, { "mnemonic": "usdot", "architecture": "ARMv8-A", "full_name": "Unsigned Signed Dot Product (A32)", "summary": "Dot product of unsigned and signed integers.", "syntax": "USDOT.S8 , , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "01000100 | 1 | 0 | 0 | Zm | 011110 | Zn | Zda", "hex_opcode": "0x44807800", "visual_parts": [ { "raw": "01000100", "clean": "01000100" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "Zm", "clean": "Zm" }, { "raw": "011110", "clean": "011110" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Zda", "clean": "Zda" } ], "bit_positions": "31:24 | 23 | 22 | 21 | 20:16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "Unsigned" }, { "name": "Qm", "desc": "Signed" } ], "extension": "NEON (DotProd)", "description": "Unsigned-Signed Dot Product computes the dot product of unsigned 8-bit integers from Qn and signed 8-bit integers from Qm, accumulating into the corresponding 32-bit element of Qd. Four separate dot products are computed in parallel. No condition flags are modified. This instruction requires the NEON Dot Product extension and executes in A32 (ARM) state.", "example": "USDOT.S8 q0, q1, q2", "pseudocode": "for i in [0, 1, 2, 3]:\n Qd[i*32+31:i*32] ← Qd[i*32+31:i*32] + USSignedDotProduct(UnsignedQn[i*32+31:i*32], SignedQm[i*32+31:i*32])" }, { "mnemonic": "sxtb", "architecture": "ARMv8-A", "full_name": "Signed Extend Byte (Thumb)", "summary": "Sign-extends byte to word (Thumb).", "syntax": "SXTB , ", "encoding": { "format": "Thumb Data Proc", "binary_pattern": "10110010 | 0 | 1 | Rm | Rd", "hex_opcode": "0xB240", "visual_parts": [ { "raw": "10110010", "clean": "10110010" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "15:8 | 7 | 6 | 5:3 | 2:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "T32 (Thumb)", "description": "Sign-extends an 8-bit byte value to a 32-bit word in the T32 (Thumb) instruction set. The least-significant byte of Rm is sign-extended and written to Rd. No condition flags are affected.", "example": "SXTB r0, r2", "pseudocode": "Rd = SignExtend(Rm[7:0], 32)" }, { "mnemonic": "sxth", "architecture": "ARMv8-A", "full_name": "Signed Extend Halfword (Thumb)", "summary": "Sign-extends halfword to word (Thumb).", "syntax": "SXTH , ", "encoding": { "format": "Thumb Data Proc", "binary_pattern": "10110010 | 0 | 0 | Rm | Rd", "hex_opcode": "0xB200", "visual_parts": [ { "raw": "10110010", "clean": "10110010" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "15:8 | 7 | 6 | 5:3 | 2:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "T32 (Thumb)", "description": "Sign-extends a 16-bit halfword value to a 32-bit word in the T32 (Thumb) instruction set. The least-significant halfword of Rm is sign-extended and written to Rd. No condition flags are affected.", "example": "SXTH r0, r2", "pseudocode": "Rd = SignExtend(Rm[15:0], 32)" }, { "mnemonic": "uxtb", "architecture": "ARMv8-A", "full_name": "Unsigned Extend Byte (Thumb)", "summary": "Zero-extends byte to word (Thumb).", "syntax": "UXTB , ", "encoding": { "format": "Thumb Data Proc", "binary_pattern": "10110010 | 1 | 1 | Rm | Rd", "hex_opcode": "0xB2C0", "visual_parts": [ { "raw": "10110010", "clean": "10110010" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "15:8 | 7 | 6 | 5:3 | 2:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "T32 (Thumb)", "description": "Zero-extends an 8-bit byte value to a 32-bit word in the T32 (Thumb) instruction set. The least-significant byte of Rm is zero-extended and written to Rd. No condition flags are affected.", "example": "UXTB r0, r2", "pseudocode": "Rd = ZeroExtend(Rm[7:0], 32)" }, { "mnemonic": "uxth", "architecture": "ARMv8-A", "full_name": "Unsigned Extend Halfword (Thumb)", "summary": "Zero-extends halfword to word (Thumb).", "syntax": "UXTH , ", "encoding": { "format": "Thumb Data Proc", "binary_pattern": "10110010 | 1 | 0 | Rm | Rd", "hex_opcode": "0xB280", "visual_parts": [ { "raw": "10110010", "clean": "10110010" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "15:8 | 7 | 6 | 5:3 | 2:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "T32 (Thumb)", "description": "Zero-extends a 16-bit halfword value to a 32-bit word in the T32 (Thumb) instruction set. The least-significant halfword of Rm is zero-extended and written to Rd. No condition flags are affected.", "example": "UXTH r0, r2", "pseudocode": "Rd = ZeroExtend(Rm[15:0], 32)" }, { "mnemonic": "rev", "architecture": "ARMv8-A", "full_name": "Reverse Bytes (Thumb)", "summary": "Endian swap (Thumb).", "syntax": "REV , ", "encoding": { "format": "Thumb Data Proc", "binary_pattern": "10111010 | 00 | Rm | Rd", "hex_opcode": "0xBA00", "visual_parts": [ { "raw": "10111010", "clean": "10111010" }, { "raw": "00", "clean": "00" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "15:8 | 7:6 | 5:3 | 2:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "T32 (Thumb)", "description": "Reverses the byte order of a 32-bit value in a general-purpose register. The four bytes of the source register are swapped to convert between big-endian and little-endian representations. This instruction does not affect the condition flags. Execution is restricted to T32 (Thumb) instruction set.", "example": "REV r0, r2", "pseudocode": "Rd ← (Rm[7:0] << 24) | (Rm[15:8] << 16) | (Rm[23:16] << 8) | Rm[31:24]" }, { "mnemonic": "rev16", "architecture": "ARMv8-A", "full_name": "Reverse Bytes Halfword (Thumb)", "summary": "Reverse bytes in halfwords (Thumb).", "syntax": "REV16 , ", "encoding": { "format": "Thumb Data Proc", "binary_pattern": "10111010 | 01 | Rm | Rd", "hex_opcode": "0xBA40", "visual_parts": [ { "raw": "10111010", "clean": "10111010" }, { "raw": "01", "clean": "01" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "15:8 | 7:6 | 5:3 | 2:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "T32 (Thumb)", "description": "Reverses the byte order within each 16-bit halfword of a 32-bit register independently. Bytes [7:0] and [15:8] are swapped, and bytes [23:16] and [31:24] are swapped. This instruction does not affect the condition flags. Execution is restricted to T32 (Thumb) instruction set.", "example": "REV16 r0, r2", "pseudocode": "Rd ← (Rm[7:0] << 8) | Rm[15:8] | (Rm[23:16] << 8) | Rm[31:24]" }, { "mnemonic": "revsh", "architecture": "ARMv8-A", "full_name": "Reverse Signed Halfword (Thumb)", "summary": "Reverse bytes in low halfword, sign extend (Thumb).", "syntax": "REVSH , ", "encoding": { "format": "Thumb Data Proc", "binary_pattern": "10111010 | 11 | Rm | Rd", "hex_opcode": "0xBAC0", "visual_parts": [ { "raw": "10111010", "clean": "10111010" }, { "raw": "11", "clean": "11" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "15:8 | 7:6 | 5:3 | 2:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "T32 (Thumb)", "description": "Reverse Signed Halfword reverses the byte order of the low 16 bits of Rm, then sign-extends the result to 32 bits and writes it to Rd. This is commonly used to perform endian conversion on signed 16-bit values. No condition flags are modified. This instruction executes only in T32 (Thumb) state.", "example": "REVSH r0, r2", "pseudocode": "halfword ← Rm[15:0];\nreversed ← (halfword[7:0] << 8) | halfword[15:8];\nRd ← SignExtend(reversed, 16)" }, { "mnemonic": "fabs", "architecture": "ARMv8-A", "full_name": "Floating-Point Absolute Value (Scalar)", "summary": "Calculates the absolute value of a float.", "syntax": "FABS , ", "encoding": { "format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 10000 | 01 | 10000 | Rn | Rd", "hex_opcode": "0x1E20C000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "10000", "clean": "10000" }, { "raw": "01", "clean": "01" }, { "raw": "10000", "clean": "10000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:17 | 16:15 | 14:10 | 9:5 | 4:0" }, "operands": [ { "name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" } ], "extension": "Floating Point", "description": "Computes the absolute value of a scalar floating-point operand, clearing the sign bit while preserving all other bits. Floating-point exception conditions (invalid operation, etc.) are not generated. The instruction operates on Half-precision (16-bit), Single-precision (32-bit), or Double-precision (64-bit) formats, determined by the type field. This is an AArch64-only instruction.", "example": "FABS Dd, Dn", "pseudocode": "Rd ← abs(Rn)\nif (type == 00) then Rd is H-register (16-bit)\nelse if (type == 01) then Rd is S-register (32-bit)\nelse if (type == 10) then Rd is D-register (64-bit)" }, { "mnemonic": "fadd", "architecture": "ARMv8-A", "full_name": "Floating-Point Add (Scalar)", "summary": "Adds two floating-point values.", "syntax": "FADD , , ", "encoding": { "format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | 001 | 0 | 10 | Rn | Rd", "hex_opcode": "0x1E202800", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "001", "clean": "001" }, { "raw": "0", "clean": "0" }, { "raw": "10", "clean": "10" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:13 | 12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" }, { "name": "Hm|Sm|Dm", "desc": "Second source SIMD&FP register (half, single or double-precision)" } ], "extension": "Floating Point", "description": "Adds two scalar floating-point operands and writes the result to the destination register. The operation respects IEEE 754 rounding modes and may generate floating-point exception conditions (invalid, overflow, underflow, inexact). The instruction operates on Half-precision (16-bit), Single-precision (32-bit), or Double-precision (64-bit) formats, determined by the type field. This is an AArch64-only instruction.", "example": "FADD Dd, Dn, Dm", "pseudocode": "Rd ← FP_Add(Rn, Rm)\nif (type == 00) then operands are H-registers (16-bit)\nelse if (type == 01) then operands are S-registers (32-bit)\nelse if (type == 10) then operands are D-registers (64-bit)" }, { "mnemonic": "fsub", "architecture": "ARMv8-A", "full_name": "Floating-Point Subtract (Scalar)", "summary": "Subtracts two floating-point values.", "syntax": "FSUB , , ", "encoding": { "format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | 001 | 1 | 10 | Rn | Rd", "hex_opcode": "0x1E203800", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "001", "clean": "001" }, { "raw": "1", "clean": "1" }, { "raw": "10", "clean": "10" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:13 | 12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" }, { "name": "Hm|Sm|Dm", "desc": "Second source SIMD&FP register (half, single or double-precision)" } ], "extension": "Floating Point", "description": "Subtracts one scalar floating-point operand from another and writes the result to the destination register. The operation respects IEEE 754 rounding modes and may generate floating-point exception conditions (invalid, overflow, underflow, inexact). The instruction operates on Half-precision (16-bit), Single-precision (32-bit), or Double-precision (64-bit) formats, determined by the type field. This is an AArch64-only instruction.", "example": "FSUB Dd, Dn, Dm", "pseudocode": "Rd ← FP_Subtract(Rn, Rm)\nif (type == 00) then operands are H-registers (16-bit)\nelse if (type == 01) then operands are S-registers (32-bit)\nelse if (type == 10) then operands are D-registers (64-bit)" }, { "mnemonic": "fmul", "architecture": "ARMv8-A", "full_name": "Floating-Point Multiply (Scalar)", "summary": "Multiplies two floating-point values.", "syntax": "FMUL , , ", "encoding": { "format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | 0 | 00010 | Rn | Rd", "hex_opcode": "0x1E200800", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "0", "clean": "0" }, { "raw": "00010", "clean": "00010" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15 | 14:10 | 9:5 | 4:0" }, "operands": [ { "name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" }, { "name": "Hm|Sm|Dm", "desc": "Second source SIMD&FP register (half, single or double-precision)" } ], "extension": "Floating Point", "description": "Multiplies two scalar floating-point operands and writes the result to the destination register. The operation respects IEEE 754 rounding modes and may generate floating-point exception conditions (invalid, overflow, underflow, inexact). The instruction operates on Half-precision (16-bit), Single-precision (32-bit), or Double-precision (64-bit) formats, determined by the type field. This is an AArch64-only instruction.", "example": "FMUL Dd, Dn, Dm", "pseudocode": "Rd ← FP_Multiply(Rn, Rm)\nif (type == 00) then operands are H-registers (16-bit)\nelse if (type == 01) then operands are S-registers (32-bit)\nelse if (type == 10) then operands are D-registers (64-bit)" }, { "mnemonic": "fdiv", "architecture": "ARMv8-A", "full_name": "Floating-Point Divide (Scalar)", "summary": "Divides two floating-point values.", "syntax": "FDIV , , ", "encoding": { "format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | 0001 | 10 | Rn | Rd", "hex_opcode": "0x1E201800", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "0001", "clean": "0001" }, { "raw": "10", "clean": "10" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" }, { "name": "Hm|Sm|Dm", "desc": "Second source SIMD&FP register (half, single or double-precision)" } ], "extension": "Floating Point", "description": "Divides one scalar floating-point operand by another and writes the result to the destination register. The operation respects IEEE 754 rounding modes and may generate floating-point exception conditions (invalid, overflow, underflow, inexact, divide-by-zero). The instruction operates on Half-precision (16-bit), Single-precision (32-bit), or Double-precision (64-bit) formats, determined by the type field. This is an AArch64-only instruction.", "example": "FDIV Dd, Dn, Dm", "pseudocode": "Rd ← FP_Divide(Rn, Rm)\nif (type == 00) then operands are H-registers (16-bit)\nelse if (type == 01) then operands are S-registers (32-bit)\nelse if (type == 10) then operands are D-registers (64-bit)" }, { "mnemonic": "fmadd", "architecture": "ARMv8-A", "full_name": "Floating-Point Fused Multiply-Add (Scalar)", "summary": "Calculates (Vn * Vm) + Va without intermediate rounding.", "syntax": "FMADD , , , ", "encoding": { "format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11111 | 00 | 0 | Rm | 0 | Ra | Rn | Rd", "hex_opcode": "0x1F000000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11111", "clean": "11111" }, { "raw": "00", "clean": "00" }, { "raw": "0", "clean": "0" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "0", "clean": "0" }, { "raw": "Ra", "clean": "Ra" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15 | 14:10 | 9:5 | 4:0" }, "operands": [ { "name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" }, { "name": "Hm|Sm|Dm", "desc": "Second source SIMD&FP register (half, single or double-precision)" }, { "name": "Ha|Sa|Da", "desc": "Third source (accumulator) SIMD&FP register (half, single or double-precision)" } ], "extension": "Floating Point", "description": "Computes a fused multiply-add operation: (Rn × Rm) + Ra, with a single rounding step applied to the final result. This guarantees higher precision than separate multiply and add instructions. Floating-point exception conditions (invalid, overflow, underflow, inexact) may be generated. The instruction operates on Half-precision (16-bit), Single-precision (32-bit), or Double-precision (64-bit) formats, determined by the type field. This is an AArch64-only instruction.", "example": "FMADD Dd, Dn, Dm, Da", "pseudocode": "Rd ← FP_FusedMultiplyAdd(Rn, Rm, Ra)\nif (type == 00) then operands are H-registers (16-bit)\nelse if (type == 01) then operands are S-registers (32-bit)\nelse if (type == 10) then operands are D-registers (64-bit)" }, { "mnemonic": "fmsub", "architecture": "ARMv8-A", "full_name": "Floating-Point Fused Multiply-Subtract (Scalar)", "summary": "Calculates (Vn * Vm) - Va.", "syntax": "FMSUB , , , ", "encoding": { "format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11111 | 00 | 0 | Rm | 1 | Ra | Rn | Rd", "hex_opcode": "0x1F008000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11111", "clean": "11111" }, { "raw": "00", "clean": "00" }, { "raw": "0", "clean": "0" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "1", "clean": "1" }, { "raw": "Ra", "clean": "Ra" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15 | 14:10 | 9:5 | 4:0" }, "operands": [ { "name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" }, { "name": "Hm|Sm|Dm", "desc": "Second source SIMD&FP register (half, single or double-precision)" }, { "name": "Ha|Sa|Da", "desc": "Third source (accumulator) SIMD&FP register (half, single or double-precision)" } ], "extension": "Floating Point", "description": "Floating-point fused multiply-subtract: computes (Vn × Vm) - Va and stores the result in Vd as a single fused operation with a single rounding step. Supports half-precision (H), single-precision (S), and double-precision (D) floating-point formats. No condition flags are affected; exceptions may be generated for invalid operations, overflow, underflow, inexact results, or input denormals depending on FPCR settings. AArch64 only.", "example": "FMSUB Dd, Dn, Dm, Da", "pseudocode": "if HaveFPExt() then\n Vd ← FPMulSub(Vn, Vm, Va)\nelse\n UNDEFINED" }, { "mnemonic": "fnmadd", "architecture": "ARMv8-A", "full_name": "Floating-Point Fused Negated Multiply-Add (Scalar)", "summary": "Calculates -((Vn * Vm) + Va).", "syntax": "FNMADD , , , ", "encoding": { "format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11111 | 00 | 1 | Rm | 0 | Ra | Rn | Rd", "hex_opcode": "0x1F200000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11111", "clean": "11111" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "0", "clean": "0" }, { "raw": "Ra", "clean": "Ra" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15 | 14:10 | 9:5 | 4:0" }, "operands": [ { "name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" }, { "name": "Hm|Sm|Dm", "desc": "Second source SIMD&FP register (half, single or double-precision)" }, { "name": "Ha|Sa|Da", "desc": "Third source (accumulator) SIMD&FP register (half, single or double-precision)" } ], "extension": "Floating Point", "description": "Floating-point fused negated multiply-add: computes -((Vn × Vm) + Va) and stores the result in Vd as a single fused operation with a single rounding step. Supports half-precision (H), single-precision (S), and double-precision (D) floating-point formats. No condition flags are affected; exceptions may be generated for invalid operations, overflow, underflow, inexact results, or input denormals depending on FPCR settings. AArch64 only.", "example": "FNMADD Dd, Dn, Dm, Da", "pseudocode": "if HaveFPExt() then\n Vd ← FPNegMulAdd(Vn, Vm, Va)\nelse\n UNDEFINED" }, { "mnemonic": "fnmsub", "architecture": "ARMv8-A", "full_name": "Floating-Point Fused Negated Multiply-Subtract (Scalar)", "summary": "Calculates -((Vn * Vm) - Va).", "syntax": "FNMSUB , , , ", "encoding": { "format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11111 | 00 | 1 | Rm | 1 | Ra | Rn | Rd", "hex_opcode": "0x1F208000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11111", "clean": "11111" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "1", "clean": "1" }, { "raw": "Ra", "clean": "Ra" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15 | 14:10 | 9:5 | 4:0" }, "operands": [ { "name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" }, { "name": "Hm|Sm|Dm", "desc": "Second source SIMD&FP register (half, single or double-precision)" }, { "name": "Ha|Sa|Da", "desc": "Third source (accumulator) SIMD&FP register (half, single or double-precision)" } ], "extension": "Floating Point", "description": "Floating-point fused negated multiply-subtract: computes -((Vn × Vm) - Va) and stores the result in Vd as a single fused operation with a single rounding step. Supports half-precision (H), single-precision (S), and double-precision (D) floating-point formats. No condition flags are affected; exceptions may be generated for invalid operations, overflow, underflow, inexact results, or input denormals depending on FPCR settings. AArch64 only.", "example": "FNMSUB Dd, Dn, Dm, Da", "pseudocode": "if HaveFPExt() then\n Vd ← FPNegMulSub(Vn, Vm, Va)\nelse\n UNDEFINED" }, { "mnemonic": "fnmul", "architecture": "ARMv8-A", "full_name": "Floating-Point Negated Multiply (Scalar)", "summary": "Calculates -(Vn * Vm).", "syntax": "FNMUL , , ", "encoding": { "format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | 1 | 00010 | Rn | Rd", "hex_opcode": "0x1E208800", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "1", "clean": "1" }, { "raw": "00010", "clean": "00010" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15 | 14:10 | 9:5 | 4:0" }, "operands": [ { "name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" }, { "name": "Hm|Sm|Dm", "desc": "Second source SIMD&FP register (half, single or double-precision)" } ], "extension": "Floating Point", "description": "Floating-Point Negated Multiply computes the negation of the product of two floating-point values: -(Vn × Vm), writing the result to Vd. Supports half-precision (type=0, 16-bit), single-precision (type=1, 32-bit), and double-precision (type=2, 64-bit) operands. FPSR exception flags may be set based on invalid, inexact, or overflow conditions. This instruction executes only in AArch64 state.", "example": "FNMUL Dd, Dn, Dm", "pseudocode": "if type == 0:\n Vd ← -(Vn_float16 × Vm_float16)\nelse if type == 1:\n Vd ← -(Vn_float32 × Vm_float32)\nelse if type == 2:\n Vd ← -(Vn_float64 × Vm_float64)" }, { "mnemonic": "fsqrt", "architecture": "ARMv8-A", "full_name": "Floating-Point Square Root (Scalar)", "summary": "Calculates square root.", "syntax": "FSQRT , ", "encoding": { "format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 10000 | 11 | 10000 | Rn | Rd", "hex_opcode": "0x1E21C000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "10000", "clean": "10000" }, { "raw": "11", "clean": "11" }, { "raw": "10000", "clean": "10000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:17 | 16:15 | 14:10 | 9:5 | 4:0" }, "operands": [ { "name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" } ], "extension": "Floating Point", "description": "Floating-point square root: computes the square root of Vn and stores the result in Vd. Supports half-precision (H), single-precision (S), and double-precision (D) floating-point formats. No condition flags are affected; exceptions may be generated for invalid operations (negative non-zero inputs), underflow, inexact results, or input denormals depending on FPCR settings. AArch64 only.", "example": "FSQRT Dd, Dn", "pseudocode": "if HaveFPExt() then\n Vd ← FPSqrt(Vn)\nelse\n UNDEFINED" }, { "mnemonic": "fneg", "architecture": "ARMv8-A", "full_name": "Floating-Point Negate (Scalar)", "summary": "Negates the value (flips sign bit).", "syntax": "FNEG , ", "encoding": { "format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 11 | 10000 | 10 | 10000 | Rn | Rd", "hex_opcode": "0x1EE14000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "11", "clean": "11" }, { "raw": "10000", "clean": "10000" }, { "raw": "10", "clean": "10" }, { "raw": "10000", "clean": "10000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:17 | 16:15 | 14:10 | 9:5 | 4:0" }, "operands": [ { "name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" } ], "extension": "Floating Point", "description": "Floating-point negate: flips the sign bit of Vn and stores the result in Vd, converting positive to negative and vice versa (including sign of zero). Supports half-precision (H), single-precision (S), and double-precision (D) floating-point formats. No condition flags are affected; no floating-point exceptions are generated. AArch64 only.", "example": "FNEG Dd, Dn", "pseudocode": "if HaveFPExt() then\n Vd ← FPNeg(Vn)\nelse\n UNDEFINED" }, { "mnemonic": "fmax", "architecture": "ARMv8-A", "full_name": "Floating-Point Maximum (Scalar)", "summary": "Returns the larger of two values.", "syntax": "FMAX , , ", "encoding": { "format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | 01 | 00 | 10 | Rn | Rd", "hex_opcode": "0x1E204800", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "01", "clean": "01" }, { "raw": "00", "clean": "00" }, { "raw": "10", "clean": "10" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:14 | 13:12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" }, { "name": "Hm|Sm|Dm", "desc": "Second source SIMD&FP register (half, single or double-precision)" } ], "extension": "Floating Point", "description": "Floating-point maximum: returns the larger of Vn and Vm and stores it in Vd. Supports half-precision (H), single-precision (S), and double-precision (D) floating-point formats. Follows IEEE 754 rules where if either operand is NaN, NaN is returned; if one operand is zero and the other is -0, returns +0. No condition flags are affected; exceptions may be generated for invalid operations or input denormals depending on FPCR settings. AArch64 only.", "example": "FMAX Dd, Dn, Dm", "pseudocode": "if HaveFPExt() then\n Vd ← FPMax(Vn, Vm)\nelse\n UNDEFINED" }, { "mnemonic": "fmin", "architecture": "ARMv8-A", "full_name": "Floating-Point Minimum (Scalar)", "summary": "Returns the smaller of two values.", "syntax": "FMIN , , ", "encoding": { "format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | 01 | 01 | 10 | Rn | Rd", "hex_opcode": "0x1E205800", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "01", "clean": "01" }, { "raw": "01", "clean": "01" }, { "raw": "10", "clean": "10" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:14 | 13:12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" }, { "name": "Hm|Sm|Dm", "desc": "Second source SIMD&FP register (half, single or double-precision)" } ], "extension": "Floating Point", "description": "Floating-point minimum: returns the smaller of Vn and Vm and stores it in Vd. Supports half-precision (H), single-precision (S), and double-precision (D) floating-point formats. Follows IEEE 754 rules where if either operand is NaN, NaN is returned; if one operand is zero and the other is -0, returns -0. No condition flags are affected; exceptions may be generated for invalid operations or input denormals depending on FPCR settings. AArch64 only.", "example": "FMIN Dd, Dn, Dm", "pseudocode": "if HaveFPExt() then\n Vd ← FPMin(Vn, Vm)\nelse\n UNDEFINED" }, { "mnemonic": "fmaxnm", "architecture": "ARMv8-A", "full_name": "Floating-Point Max Number (Scalar)", "summary": "Returns larger value, handling NaNs according to IEEE 754-2008 'maxNum'.", "syntax": "FMAXNM , , ", "encoding": { "format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | 01 | 10 | 10 | Rn | Rd", "hex_opcode": "0x1E206800", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "01", "clean": "01" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:14 | 13:12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" }, { "name": "Hm|Sm|Dm", "desc": "Second source SIMD&FP register (half, single or double-precision)" } ], "extension": "Floating Point", "description": "Floating-point maximum number: returns the larger of two floating-point numbers Vn and Vm according to IEEE 754-2008 'maxNum' semantics, where if one operand is NaN and the other is a number, the number is returned. Supports half-precision (H), single-precision (S), and double-precision (D) floating-point formats. No condition flags are affected; exceptions may be generated for invalid operations or input denormals depending on FPCR settings. AArch64 only.", "example": "FMAXNM Dd, Dn, Dm", "pseudocode": "if HaveFPExt() then\n Vd ← FPMaxNum(Vn, Vm)\nelse\n UNDEFINED" }, { "mnemonic": "fminnm", "architecture": "ARMv8-A", "full_name": "Floating-Point Min Number (Scalar)", "summary": "Returns smaller value, handling NaNs according to IEEE 754-2008 'minNum'.", "syntax": "FMINNM , , ", "encoding": { "format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | 01 | 11 | 10 | Rn | Rd", "hex_opcode": "0x1E207800", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "01", "clean": "01" }, { "raw": "11", "clean": "11" }, { "raw": "10", "clean": "10" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:14 | 13:12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" }, { "name": "Hm|Sm|Dm", "desc": "Second source SIMD&FP register (half, single or double-precision)" } ], "extension": "Floating Point", "description": "Floating-point minimum of two scalar values, returning the number (non-NaN) operand when one operand is NaN, per IEEE 754-2008 minNum semantics. Condition flags (N, Z, C, V) are not affected. AArch64-only instruction.", "example": "FMINNM Dd, Dn, Dm", "pseudocode": "if IsNaN(Vn) then\n result ← Vm\nelsif IsNaN(Vm) then\n result ← Vn\nelse\n result ← min(Vn, Vm)\nVd ← result" }, { "mnemonic": "fcmp", "architecture": "ARMv8-A", "full_name": "Floating-Point Compare (Scalar)", "summary": "Compares two floating-point values and updates process flags (NZCV).", "syntax": "FCMP , ", "encoding": { "format": "FP Compare", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | 00 | 1000 | Rn | 00 | 000", "hex_opcode": "0x1E202000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "00", "clean": "00" }, { "raw": "1000", "clean": "1000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "00", "clean": "00" }, { "raw": "000", "clean": "000" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:14 | 13:10 | 9:5 | 4:3 | 2:0" }, "operands": [ { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" }, { "name": "Hm|Sm|Dm|0.0", "desc": "Second source SIMD/FP vector register" } ], "extension": "Floating Point", "description": "Compares two floating-point scalar values and updates the NZCV condition flags based on the result. The comparison is performed on the values in the two source registers, and flags are set to reflect whether the first operand is less than, equal to, greater than, or unordered with respect to the second. This is an AArch64-only instruction that does not modify any registers, only the NZCV flags.", "example": "FCMP Dn, Dm|#0.0", "pseudocode": "result ← FPCompare(Vn, Vm)\nN ← result.N\nZ ← result.Z\nC ← result.C\nV ← result.V" }, { "mnemonic": "fccmp", "architecture": "ARMv8-A", "full_name": "Floating-Point Conditional Compare (Scalar)", "summary": "Compares floats only if condition is met, else sets flags to immediate.", "syntax": "FCCMP , , #, ", "encoding": { "format": "FP Compare", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | cond | 01 | Rn | 0 | nzcv", "hex_opcode": "0x1E200400", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "cond", "clean": "cond" }, { "raw": "01", "clean": "01" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "0", "clean": "0" }, { "raw": "nzcv", "clean": "nzcv" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:12 | 11:10 | 9:5 | 4 | 3:0" }, "operands": [ { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" }, { "name": "Hm|Sm|Dm", "desc": "Second source SIMD&FP register (half, single or double-precision)" }, { "name": "nzcv", "desc": "Def Flags" }, { "name": "cond", "desc": "Condition" } ], "extension": "Floating Point", "description": "Conditionally compares two floating-point scalar values if the specified condition is true, updating NZCV flags with the comparison result; if the condition is false, sets NZCV to the immediate value provided. This is an AArch64-only instruction that allows conditional flag updates without branching, useful for implementing conditional chains and complex control flow.", "example": "FCCMP Dn, Dm, #nzcv, cond", "pseudocode": "if ConditionHolds(cond) then\n result ← FPCompare(Vn, Vm)\n N ← result.N\n Z ← result.Z\n C ← result.C\n V ← result.V\nelse\n N ← nzcv[3]\n Z ← nzcv[2]\n C ← nzcv[1]\n V ← nzcv[0]" }, { "mnemonic": "fcsel", "architecture": "ARMv8-A", "full_name": "Floating-Point Conditional Select (Scalar)", "summary": "Selects one of two floats based on condition flags.", "syntax": "FCSEL , , , ", "encoding": { "format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | cond | 11 | Rn | Rd", "hex_opcode": "0x1E200C00", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "cond", "clean": "cond" }, { "raw": "11", "clean": "11" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" }, { "name": "Hm|Sm|Dm", "desc": "Second source SIMD&FP register (half, single or double-precision)" }, { "name": "cond", "desc": "Condition" } ], "extension": "Floating Point", "description": "Selects between two floating-point scalar values based on the current condition flags, writing the selected value to the destination register. If the condition is true, Vn is selected; otherwise, Vm is selected. This is an AArch64-only instruction that does not modify condition flags or any register other than the destination.", "example": "FCSEL Dd, Dn, Dm, cond", "pseudocode": "if ConditionHolds(cond) then\n Vd ← Vn\nelse\n Vd ← Vm" }, { "mnemonic": "fcvt", "architecture": "ARMv8-A", "full_name": "Floating-Point Convert (Scalar)", "summary": "Converts between float precisions (e.g., Half <-> Single <-> Double).", "syntax": "FCVT , ", "encoding": { "format": "FP Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 11 | 10001 | 00 | 10000 | Rn | Rd", "hex_opcode": "0x1EE24000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "11", "clean": "11" }, { "raw": "10001", "clean": "10001" }, { "raw": "00", "clean": "00" }, { "raw": "10000", "clean": "10000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:17 | 16:15 | 14:10 | 9:5 | 4:0" }, "operands": [ { "name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" } ], "extension": "Floating Point", "description": "Converts a scalar floating-point value between precision formats (e.g., Half ↔ Single ↔ Double). The rounding mode is determined by FPCR.RMode. Condition flags are not affected. AArch64-only instruction.", "example": "FCVT Dd, Dn", "pseudocode": "operand ← Vn\nresult ← ConvertFP(operand, source_precision, destination_precision, FPCR.RMode)\nVd ← result" }, { "mnemonic": "fcvtas", "architecture": "ARMv8-A", "full_name": "Floating-Point Convert to Signed Integer (Nearest)", "summary": "Converts float to signed integer, rounding to nearest.", "syntax": "FCVTAS , ", "encoding": { "format": "FP Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 11 | 1 | 00 | 100 | 000000 | Rn | Rd", "hex_opcode": "0x1EE40000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "11", "clean": "11" }, { "raw": "1", "clean": "1" }, { "raw": "00", "clean": "00" }, { "raw": "100", "clean": "100" }, { "raw": "000000", "clean": "000000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Wd|Xd", "desc": "Destination general-purpose register (32-bit/64-bit)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" } ], "extension": "Floating Point", "description": "Converts a scalar floating-point value to a signed integer, rounding to nearest with ties away from zero. Sets condition flags based on the integer result. Raises Invalid Operation exception on overflow or invalid input. AArch64-only instruction.", "example": "FCVTAS Wd, Dn", "pseudocode": "operand ← Vn\nintval ← RoundTowardNearestAwayFromZero(operand)\nif intval > MaxInt(destination_width) or intval < MinInt(destination_width) then\n GenerateException(InvalidOperation)\nelse\n Rd ← SignExtend(intval)\n UpdateFlags(intval)\nend" }, { "mnemonic": "fcvtau", "architecture": "ARMv8-A", "full_name": "Floating-Point Convert to Unsigned Integer (Nearest)", "summary": "Converts float to unsigned integer, rounding to nearest.", "syntax": "FCVTAU , ", "encoding": { "format": "FP Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 11 | 1 | 00 | 101 | 000000 | Rn | Rd", "hex_opcode": "0x1EE50000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "11", "clean": "11" }, { "raw": "1", "clean": "1" }, { "raw": "00", "clean": "00" }, { "raw": "101", "clean": "101" }, { "raw": "000000", "clean": "000000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Wd|Xd", "desc": "Destination general-purpose register (32-bit/64-bit)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" } ], "extension": "Floating Point", "description": "Converts a scalar floating-point value to an unsigned integer, rounding to nearest with ties away from zero. Sets condition flags based on the integer result. Raises Invalid Operation exception on overflow or invalid input. AArch64-only instruction.", "example": "FCVTAU Wd, Dn", "pseudocode": "operand ← Vn\nintval ← RoundTowardNearestAwayFromZero(operand)\nif intval > MaxUInt(destination_width) or intval < 0 then\n GenerateException(InvalidOperation)\nelse\n Rd ← ZeroExtend(intval)\n UpdateFlags(intval)\nend" }, { "mnemonic": "fcvtms", "architecture": "ARMv8-A", "full_name": "Floating-Point Convert to Signed Integer (Minus Infinity)", "summary": "Converts float to signed integer, rounding towards minus infinity (Floor).", "syntax": "FCVTMS , ", "encoding": { "format": "FP Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | 10 | 000 | 000000 | Rn | Rd", "hex_opcode": "0x1E300000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "10", "clean": "10" }, { "raw": "000", "clean": "000" }, { "raw": "000000", "clean": "000000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Wd|Xd", "desc": "Destination general-purpose register (32-bit/64-bit)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" } ], "extension": "Floating Point", "description": "Converts a scalar floating-point value to a signed integer, rounding towards negative infinity (floor). Sets condition flags based on the integer result. Raises Invalid Operation exception on overflow or invalid input. AArch64-only instruction.", "example": "FCVTMS Wd, Dn", "pseudocode": "operand ← Vn\nintval ← Floor(operand)\nif intval > MaxInt(destination_width) or intval < MinInt(destination_width) then\n GenerateException(InvalidOperation)\nelse\n Rd ← SignExtend(intval)\n UpdateFlags(intval)\nend" }, { "mnemonic": "fcvtmu", "architecture": "ARMv8-A", "full_name": "Floating-Point Convert to Unsigned Integer (Minus Infinity)", "summary": "Converts float to unsigned integer, rounding towards minus infinity.", "syntax": "FCVTMU , ", "encoding": { "format": "FP Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | 10 | 001 | 000000 | Rn | Rd", "hex_opcode": "0x1E310000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "10", "clean": "10" }, { "raw": "001", "clean": "001" }, { "raw": "000000", "clean": "000000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Wd|Xd", "desc": "Destination general-purpose register (32-bit/64-bit)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" } ], "extension": "Floating Point", "description": "Converts a scalar floating-point value to an unsigned integer, rounding towards negative infinity (floor). Sets condition flags based on the integer result. Raises Invalid Operation exception on overflow or invalid input. AArch64-only instruction.", "example": "FCVTMU Wd, Dn", "pseudocode": "operand ← Vn\nintval ← Floor(operand)\nif intval > MaxUInt(destination_width) or intval < 0 then\n GenerateException(InvalidOperation)\nelse\n Rd ← ZeroExtend(intval)\n UpdateFlags(intval)\nend" }, { "mnemonic": "fcvtns", "architecture": "ARMv8-A", "full_name": "Floating-Point Convert to Signed Integer (Nearest, ties to Even)", "summary": "Converts float to signed integer, rounding to nearest (bankers' round).", "syntax": "FCVTNS , ", "encoding": { "format": "FP Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | 00 | 000 | 000000 | Rn | Rd", "hex_opcode": "0x1E200000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "00", "clean": "00" }, { "raw": "000", "clean": "000" }, { "raw": "000000", "clean": "000000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Wd|Xd", "desc": "Destination general-purpose register (32-bit/64-bit)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" } ], "extension": "Floating Point", "description": "Converts a scalar floating-point value to a signed integer, rounding to nearest with ties to even (bankers' round). Sets condition flags based on the integer result. Raises Invalid Operation exception on overflow or invalid input. AArch64-only instruction.", "example": "FCVTNS Wd, Dn", "pseudocode": "operand ← Vn\nintval ← RoundTowardNearestEven(operand)\nif intval > MaxInt(destination_width) or intval < MinInt(destination_width) then\n GenerateException(InvalidOperation)\nelse\n Rd ← SignExtend(intval)\n UpdateFlags(intval)\nend" }, { "mnemonic": "fcvtnu", "architecture": "ARMv8-A", "full_name": "Floating-Point Convert to Unsigned Integer (Nearest, ties to Even)", "summary": "Converts float to unsigned integer, rounding to nearest (bankers' round).", "syntax": "FCVTNU , ", "encoding": { "format": "FP Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | 00 | 001 | 000000 | Rn | Rd", "hex_opcode": "0x1E210000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "00", "clean": "00" }, { "raw": "001", "clean": "001" }, { "raw": "000000", "clean": "000000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Wd|Xd", "desc": "Destination general-purpose register (32-bit/64-bit)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" } ], "extension": "Floating Point", "description": "Converts a scalar floating-point value to an unsigned integer, rounding to nearest with ties to even (bankers' round). Sets condition flags based on the integer result. Raises Invalid Operation exception on overflow or invalid input. AArch64-only instruction.", "example": "FCVTNU Wd, Dn", "pseudocode": "operand ← Vn\nintval ← RoundTowardNearestEven(operand)\nif intval > MaxUInt(destination_width) or intval < 0 then\n GenerateException(InvalidOperation)\nelse\n Rd ← ZeroExtend(intval)\n UpdateFlags(intval)\nend" }, { "mnemonic": "fcvtps", "architecture": "ARMv8-A", "full_name": "Floating-Point Convert to Signed Integer (Plus Infinity)", "summary": "Converts float to signed integer, rounding towards plus infinity (Ceil).", "syntax": "FCVTPS , ", "encoding": { "format": "FP Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | 01 | 000 | 000000 | Rn | Rd", "hex_opcode": "0x1E280000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "01", "clean": "01" }, { "raw": "000", "clean": "000" }, { "raw": "000000", "clean": "000000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Wd|Xd", "desc": "Destination general-purpose register (32-bit/64-bit)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" } ], "extension": "Floating Point", "description": "Converts a floating-point value to a signed integer, rounding towards plus infinity (ceiling). The source is read from a half-precision (H), single-precision (S), or double-precision (D) FP register, and the result is written to a 32-bit (W) or 64-bit (X) general-purpose register. NZCV flags are not affected by this instruction. This is an AArch64-only instruction that executes at any privilege level.", "example": "FCVTPS Wd, Dn", "pseudocode": "if source_is_nan then\n result ← 0\nelse\n result ← round_to_plus_infinity(FP_to_signed_integer(Vn))\nRd ← result" }, { "mnemonic": "fcvtpu", "architecture": "ARMv8-A", "full_name": "Floating-Point Convert to Unsigned Integer (Plus Infinity)", "summary": "Converts float to unsigned integer, rounding towards plus infinity.", "syntax": "FCVTPU , ", "encoding": { "format": "FP Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | 01 | 001 | 000000 | Rn | Rd", "hex_opcode": "0x1E290000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "01", "clean": "01" }, { "raw": "001", "clean": "001" }, { "raw": "000000", "clean": "000000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Wd|Xd", "desc": "Destination general-purpose register (32-bit/64-bit)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" } ], "extension": "Floating Point", "description": "Converts a floating-point value to an unsigned integer, rounding towards plus infinity (ceiling). The source is read from a half-precision (H), single-precision (S), or double-precision (D) FP register, and the result is written to a 32-bit (W) or 64-bit (X) general-purpose register. NZCV flags are not affected by this instruction. This is an AArch64-only instruction that executes at any privilege level.", "example": "FCVTPU Wd, Dn", "pseudocode": "if source_is_nan then\n result ← 0\nelse\n result ← round_to_plus_infinity(FP_to_unsigned_integer(Vn))\nRd ← result" }, { "mnemonic": "fcvtzs", "architecture": "ARMv8-A", "full_name": "Floating-Point Convert to Signed Integer (Zero)", "summary": "Converts float to signed integer, rounding towards zero (Truncate).", "syntax": "FCVTZS , {, #}", "encoding": { "format": "FP Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | 11 | 000 | 000000 | Rn | Rd", "hex_opcode": "0x1E380000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "11", "clean": "11" }, { "raw": "000", "clean": "000" }, { "raw": "000000", "clean": "000000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Wd|Xd", "desc": "Destination general-purpose register (32-bit/64-bit)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" }, { "name": "fbits", "desc": "Number of fractional bits" } ], "extension": "Floating Point", "description": "Converts a floating-point value to a signed integer, rounding towards zero (truncation). The source is read from a half-precision (H), single-precision (S), or double-precision (D) FP register, and the result is written to a 32-bit (W) or 64-bit (X) general-purpose register. An optional fixed-point shift parameter (fbits) can scale the result by 2^fbits. NZCV flags are not affected by this instruction. This is an AArch64-only instruction that executes at any privilege level.", "example": "FCVTZS Wd, Dn", "pseudocode": "if source_is_nan then\n result ← 0\nelse\n if fbits_present then\n result ← round_towards_zero(FP_to_signed_integer(Vn) × 2^fbits)\n else\n result ← round_towards_zero(FP_to_signed_integer(Vn))\nRd ← result" }, { "mnemonic": "fcvtzu", "architecture": "ARMv8-A", "full_name": "Floating-Point Convert to Unsigned Integer (Zero)", "summary": "Converts float to unsigned integer, rounding towards zero (Truncate).", "syntax": "FCVTZU , {, #}", "encoding": { "format": "FP Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | 11 | 001 | 000000 | Rn | Rd", "hex_opcode": "0x1E390000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "11", "clean": "11" }, { "raw": "001", "clean": "001" }, { "raw": "000000", "clean": "000000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Wd|Xd", "desc": "Destination general-purpose register (32-bit/64-bit)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" }, { "name": "fbits", "desc": "Number of fractional bits" } ], "extension": "Floating Point", "description": "Converts a floating-point value to an unsigned integer, rounding towards zero (truncation). The source is read from a half-precision (H), single-precision (S), or double-precision (D) FP register, and the result is written to a 32-bit (W) or 64-bit (X) general-purpose register. An optional fixed-point shift parameter (fbits) can scale the result by 2^fbits. NZCV flags are not affected by this instruction. This is an AArch64-only instruction that executes at any privilege level.", "example": "FCVTZU Wd, Dn", "pseudocode": "if source_is_nan then\n result ← 0\nelse\n if fbits_present then\n result ← round_towards_zero(FP_to_unsigned_integer(Vn) × 2^fbits)\n else\n result ← round_towards_zero(FP_to_unsigned_integer(Vn))\nRd ← result" }, { "mnemonic": "scvtf", "architecture": "ARMv8-A", "full_name": "Signed Integer Convert to Floating-Point", "summary": "Converts signed integer (GPR) to floating-point.", "syntax": "SCVTF , {, #}", "encoding": { "format": "FP Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | 00 | 010 | 000000 | Rn | Rd", "hex_opcode": "0x1E220000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "00", "clean": "00" }, { "raw": "010", "clean": "010" }, { "raw": "000000", "clean": "000000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)" }, { "name": "Wn|Xn", "desc": "First source general-purpose register (32-bit/64-bit)" } ], "extension": "Floating Point", "description": "Converts a signed integer value from a GPR to floating-point format and writes the result to an FP scalar register. The conversion respects an optional fixed-point scaling factor (fbits) if provided, effectively dividing the result by 2^fbits. This is an AArch64-only instruction that does not modify condition flags.", "example": "SCVTF Dd, Wn", "pseudocode": "int_val ← SignExtend(Rn)\nif fbits != 0 then\n fp_val ← ConvertToFP(int_val / 2^fbits)\nelse\n fp_val ← ConvertToFP(int_val)\nVd ← fp_val" }, { "mnemonic": "ucvtf", "architecture": "ARMv8-A", "full_name": "Unsigned Integer Convert to Floating-Point", "summary": "Converts unsigned integer (GPR) to floating-point.", "syntax": "UCVTF , {, #}", "encoding": { "format": "FP Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | 00 | 011 | 000000 | Rn | Rd", "hex_opcode": "0x1E230000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "00", "clean": "00" }, { "raw": "011", "clean": "011" }, { "raw": "000000", "clean": "000000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)" }, { "name": "Wn|Xn", "desc": "First source general-purpose register (32-bit/64-bit)" } ], "extension": "Floating Point", "description": "Converts an unsigned integer value from a GPR to floating-point format and writes the result to an FP scalar register. The conversion respects an optional fixed-point scaling factor (fbits) if provided, effectively dividing the result by 2^fbits. This is an AArch64-only instruction that does not modify condition flags.", "example": "UCVTF Dd, Wn", "pseudocode": "uint_val ← ZeroExtend(Rn)\nif fbits != 0 then\n fp_val ← ConvertToFP(uint_val / 2^fbits)\nelse\n fp_val ← ConvertToFP(uint_val)\nVd ← fp_val" }, { "mnemonic": "frinta", "architecture": "ARMv8-A", "full_name": "Floating-Point Round to Integral (Nearest)", "summary": "Rounds float to nearest integral value (ties away from zero).", "syntax": "FRINTA , ", "encoding": { "format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1001 | 100 | 10000 | Rn | Rd", "hex_opcode": "0x1E264000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1001", "clean": "1001" }, { "raw": "100", "clean": "100" }, { "raw": "10000", "clean": "10000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:18 | 17:15 | 14:10 | 9:5 | 4:0" }, "operands": [ { "name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" } ], "extension": "Floating Point", "description": "Rounds a floating-point scalar value to the nearest integral value, with ties rounded away from zero. The rounding mode is always \"round to nearest, ties away from zero\" regardless of the FPCR rounding mode setting. This is an AArch64-only instruction that does not modify condition flags.", "example": "FRINTA Dd, Dn", "pseudocode": "rounded_val ← RoundToIntegral_TiesAwayFromZero(Vn)\nVd ← rounded_val" }, { "mnemonic": "frinti", "architecture": "ARMv8-A", "full_name": "Floating-Point Round to Integral (Current)", "summary": "Rounds float to integral value using current FPCR rounding mode.", "syntax": "FRINTI , ", "encoding": { "format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1001 | 111 | 10000 | Rn | Rd", "hex_opcode": "0x1E27C000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1001", "clean": "1001" }, { "raw": "111", "clean": "111" }, { "raw": "10000", "clean": "10000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:18 | 17:15 | 14:10 | 9:5 | 4:0" }, "operands": [ { "name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" } ], "extension": "Floating Point", "description": "Rounds a floating-point scalar value to an integral value using the current rounding mode specified in the FPCR (Floating-Point Control Register). The rounding behavior depends on the RMode field in FPCR. This is an AArch64-only instruction that does not modify condition flags.", "example": "FRINTI Dd, Dn", "pseudocode": "rounded_val ← RoundToIntegral_CurrentMode(Vn) \nVd ← rounded_val" }, { "mnemonic": "frintm", "architecture": "ARMv8-A", "full_name": "Floating-Point Round to Integral (Minus Infinity)", "summary": "Rounds float to integral value towards minus infinity (Floor).", "syntax": "FRINTM , ", "encoding": { "format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1001 | 010 | 10000 | Rn | Rd", "hex_opcode": "0x1E254000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1001", "clean": "1001" }, { "raw": "010", "clean": "010" }, { "raw": "10000", "clean": "10000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:18 | 17:15 | 14:10 | 9:5 | 4:0" }, "operands": [ { "name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" } ], "extension": "Floating Point", "description": "Rounds a floating-point scalar value towards negative infinity (floor). The rounding mode is always \"round towards minus infinity\" regardless of the FPCR rounding mode setting. This is an AArch64-only instruction that does not modify condition flags.", "example": "FRINTM Dd, Dn", "pseudocode": "rounded_val ← RoundToIntegral_MinusInfinity(Vn)\nVd ← rounded_val" }, { "mnemonic": "frintn", "architecture": "ARMv8-A", "full_name": "Floating-Point Round to Integral (Nearest Even)", "summary": "Rounds float to integral value nearest, ties to even.", "syntax": "FRINTN , ", "encoding": { "format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1001 | 000 | 10000 | Rn | Rd", "hex_opcode": "0x1E244000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1001", "clean": "1001" }, { "raw": "000", "clean": "000" }, { "raw": "10000", "clean": "10000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:18 | 17:15 | 14:10 | 9:5 | 4:0" }, "operands": [ { "name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" } ], "extension": "Floating Point", "description": "Rounds the floating-point value in the source register to the nearest integer using round-to-nearest-ties-to-even mode, and writes the result to the destination register. The instruction does not set any condition flags (N, Z, C, V remain unaffected). Execution is AArch64-only and may generate floating-point exceptions based on the source operand and enabled exception controls.", "example": "FRINTN Dd, Dn", "pseudocode": "Vd ← RoundToNearestEven(Vn)" }, { "mnemonic": "frintp", "architecture": "ARMv8-A", "full_name": "Floating-Point Round to Integral (Plus Infinity)", "summary": "Rounds float to integral value towards plus infinity (Ceil).", "syntax": "FRINTP , ", "encoding": { "format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1001 | 001 | 10000 | Rn | Rd", "hex_opcode": "0x1E24C000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1001", "clean": "1001" }, { "raw": "001", "clean": "001" }, { "raw": "10000", "clean": "10000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:18 | 17:15 | 14:10 | 9:5 | 4:0" }, "operands": [ { "name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" } ], "extension": "Floating Point", "description": "Rounds the floating-point value in the source register to the nearest integer towards positive infinity (ceiling), and writes the result to the destination register. The instruction does not set any condition flags (N, Z, C, V remain unaffected). Execution is AArch64-only and may generate floating-point exceptions based on the source operand and enabled exception controls.", "example": "FRINTP Dd, Dn", "pseudocode": "Vd ← RoundTowardsPlusInfinity(Vn)" }, { "mnemonic": "frintx", "architecture": "ARMv8-A", "full_name": "Floating-Point Round to Integral (Exact)", "summary": "Rounds float to integral value using current mode, raising Inexact exception.", "syntax": "FRINTX , ", "encoding": { "format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1001 | 110 | 10000 | Rn | Rd", "hex_opcode": "0x1E274000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1001", "clean": "1001" }, { "raw": "110", "clean": "110" }, { "raw": "10000", "clean": "10000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:18 | 17:15 | 14:10 | 9:5 | 4:0" }, "operands": [ { "name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" } ], "extension": "Floating Point", "description": "Rounds the floating-point value in the source register to the nearest integer using the current rounding mode and raises an Inexact floating-point exception if the result differs from the input. The instruction does not set condition flags (N, Z, C, V remain unaffected). Execution is AArch64-only and always signals the Inexact exception condition when rounding occurs.", "example": "FRINTX Dd, Dn", "pseudocode": "Vd ← RoundToIntegral(Vn); if Vd ≠ Vn then RaiseInexactException()" }, { "mnemonic": "frintz", "architecture": "ARMv8-A", "full_name": "Floating-Point Round to Integral (Zero)", "summary": "Rounds float to integral value towards zero (Truncate).", "syntax": "FRINTZ , ", "encoding": { "format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1001 | 011 | 10000 | Rn | Rd", "hex_opcode": "0x1E25C000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1001", "clean": "1001" }, { "raw": "011", "clean": "011" }, { "raw": "10000", "clean": "10000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:18 | 17:15 | 14:10 | 9:5 | 4:0" }, "operands": [ { "name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" } ], "extension": "Floating Point", "description": "Rounds the floating-point value in the source register to the nearest integer towards zero (truncation), and writes the result to the destination register. The instruction does not set any condition flags (N, Z, C, V remain unaffected). Execution is AArch64-only and may generate floating-point exceptions based on the source operand and enabled exception controls.", "example": "FRINTZ Dd, Dn", "pseudocode": "Vd ← RoundTowardsZero(Vn)" }, { "mnemonic": "fmov", "architecture": "ARMv8-A", "full_name": "Floating-Point Move (Immediate)", "summary": "Moves a floating-point immediate into a scalar register.", "syntax": "FMOV , #", "encoding": { "format": "FP Immediate", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | imm8 | 100 | 00000 | Rd", "hex_opcode": "0x1E201000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "imm8", "clean": "imm8" }, { "raw": "100", "clean": "100" }, { "raw": "00000", "clean": "00000" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)" }, { "name": "fimm", "desc": "Floating-point immediate value" } ], "extension": "Floating Point", "description": "Moves a floating-point immediate constant into a half-precision (H), single-precision (S), or double-precision (D) scalar FP register. The immediate is encoded as an 8-bit value and expanded to full precision according to the IEEE 754 floating-point format. NZCV flags are not affected. This is an AArch64-only instruction that executes at any privilege level.", "example": "FMOV Dd, #1.0", "pseudocode": "Vd ← decode_fp_immediate(imm8, type)" }, { "mnemonic": "fmov", "architecture": "ARMv8-A", "full_name": "Floating-Point Move (Register)", "summary": "Copies a value from one scalar FP register to another.", "syntax": "FMOV , ", "encoding": { "format": "FP Data Processing", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 10000 | 00 | 10000 | Rn | Rd", "hex_opcode": "0x1E204000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "10000", "clean": "10000" }, { "raw": "00", "clean": "00" }, { "raw": "10000", "clean": "10000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:17 | 16:15 | 14:10 | 9:5 | 4:0" }, "operands": [ { "name": "Hd|Sd|Dd", "desc": "Destination SIMD&FP register (half, single or double-precision)" }, { "name": "Hn|Sn|Dn", "desc": "First source SIMD&FP register (half, single or double-precision)" } ], "extension": "Floating Point", "description": "Copies a floating-point value from one scalar FP register to another, preserving the value and precision. Both source and destination must be the same type (half-precision, single-precision, or double-precision). NZCV flags are not affected. This is an AArch64-only instruction that executes at any privilege level.", "example": "FMOV Dd, Dn", "pseudocode": "Vd ← Vn" }, { "mnemonic": "fmov", "architecture": "ARMv8-A", "full_name": "Floating-Point Move (General)", "summary": "Copies bits between a General-Purpose Register (W/X) and FP Register (S/D).", "syntax": "FMOV , ", "encoding": { "format": "FP Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | 00 | 110 | 000000 | Rn | Rd", "hex_opcode": "0x1E260000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "00", "clean": "00" }, { "raw": "110", "clean": "110" }, { "raw": "000000", "clean": "000000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Wd|Xd", "desc": "Destination general-purpose register (32-bit/64-bit)" }, { "name": "Sn|Dn", "desc": "First source SIMD&FP register (single or double-precision)" } ], "extension": "Floating Point", "description": "Copies the bit pattern from a floating-point register (single-precision or double-precision) to a general-purpose register (32-bit or 64-bit), treating the value as an opaque bit sequence without any floating-point interpretation. NZCV flags are not affected. This is an AArch64-only instruction that executes at any privilege level.", "example": "FMOV Wd, Sn", "pseudocode": "Rd ← bits(Vn)" }, { "mnemonic": "fmov", "architecture": "ARMv8-A", "full_name": "Floating-Point Move (General to FP)", "summary": "Copies bits from a General-Purpose Register (W/X) to FP Register (S/D).", "syntax": "FMOV , ", "encoding": { "format": "FP Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | 00 | 111 | 000000 | Rn | Rd", "hex_opcode": "0x1E270000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "00", "clean": "00" }, { "raw": "111", "clean": "111" }, { "raw": "000000", "clean": "000000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Sd|Dd", "desc": "Destination SIMD&FP register (single or double-precision)" }, { "name": "Wn|Xn", "desc": "First source general-purpose register (32-bit/64-bit)" } ], "extension": "Floating Point", "description": "Copies the bit pattern from a general-purpose register (32-bit or 64-bit) to a floating-point register (single-precision or double-precision), treating the value as an opaque bit sequence without any floating-point interpretation. NZCV flags are not affected. This is an AArch64-only instruction that executes at any privilege level.", "example": "FMOV Sd, Wn", "pseudocode": "Vd ← bits(Rn)" }, { "mnemonic": "ldr", "architecture": "ARMv8-A", "full_name": "Load SIMD&FP Register (Immediate)", "summary": "Loads a floating-point/SIMD register from memory.", "syntax": "LDR , [, #]", "encoding": { "format": "Load/Store", "binary_pattern": "10 | 111 | 1 | 01 | 01 | imm12 | Rn | Rt", "hex_opcode": "0xBD400000", "visual_parts": [ { "raw": "10", "clean": "10" }, { "raw": "111", "clean": "111" }, { "raw": "1", "clean": "1" }, { "raw": "01", "clean": "01" }, { "raw": "01", "clean": "01" }, { "raw": "imm12", "clean": "imm12" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rt", "clean": "Rt" } ], "bit_positions": "31:30 | 29:27 | 26 | 25:24 | 23:22 | 21:10 | 9:5 | 4:0" }, "operands": [ { "name": "Bt|Ht|St|Dt|Qt", "desc": "Transfer SIMD&FP register (byte, half, single, double or quad-precision)" }, { "name": "Xn|SP", "desc": "First source / base 64-bit integer register" }, { "name": "pimm", "desc": "Positive immediate offset" } ], "extension": "Floating Point", "description": "The Load SIMD&FP Register instruction loads a floating-point/SIMD register from memory.", "example": "LDR Qt, [x1, #16]", "pseudocode": "Vt ← Memory[address]" }, { "mnemonic": "str", "architecture": "ARMv8-A", "full_name": "Store SIMD&FP Register (Immediate)", "summary": "Stores a floating-point/SIMD register to memory.", "syntax": "STR , [, #]", "encoding": { "format": "Load/Store", "binary_pattern": "10 | 111 | 1 | 01 | 00 | imm12 | Rn | Rt", "hex_opcode": "0xBD000000", "visual_parts": [ { "raw": "10", "clean": "10" }, { "raw": "111", "clean": "111" }, { "raw": "1", "clean": "1" }, { "raw": "01", "clean": "01" }, { "raw": "00", "clean": "00" }, { "raw": "imm12", "clean": "imm12" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rt", "clean": "Rt" } ], "bit_positions": "31:30 | 29:27 | 26 | 25:24 | 23:22 | 21:10 | 9:5 | 4:0" }, "operands": [ { "name": "Bt|Ht|St|Dt|Qt", "desc": "Transfer SIMD&FP register (byte, half, single, double or quad-precision)" }, { "name": "Xn|SP", "desc": "First source / base 64-bit integer register" }, { "name": "pimm", "desc": "Positive immediate offset" } ], "extension": "Floating Point", "description": "The Store SIMD&FP Register instruction stores a floating-point/SIMD register to memory.", "example": "STR Qt, [x1, #16]", "pseudocode": "Memory[address] ← Xn" }, { "mnemonic": "ldp", "architecture": "ARMv8-A", "full_name": "Load Pair SIMD&FP Registers", "summary": "Loads two floating-point/SIMD registers.", "syntax": "LDP , , [, #]", "encoding": { "format": "Load/Store Pair", "binary_pattern": "00 | 101 | 1 | 010 | 1 | imm7 | Rt2 | Rn | Rt", "hex_opcode": "0x2D400000", "visual_parts": [ { "raw": "00", "clean": "00" }, { "raw": "101", "clean": "101" }, { "raw": "1", "clean": "1" }, { "raw": "010", "clean": "010" }, { "raw": "1", "clean": "1" }, { "raw": "imm7", "clean": "imm7" }, { "raw": "Rt2", "clean": "Rt2" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rt", "clean": "Rt" } ], "bit_positions": "31:30 | 29:27 | 26 | 25:23 | 22 | 21:15 | 14:10 | 9:5 | 4:0" }, "operands": [ { "name": "St1|Dt1|Qt1", "desc": "First transfer SIMD&FP register (single, double or quad-precision)" }, { "name": "St2|Dt2|Qt2", "desc": "Second transfer SIMD&FP register (single, double or quad-precision)" }, { "name": "Xn|SP", "desc": "First source / base 64-bit integer register" }, { "name": "imm", "desc": "Signed immediate value" } ], "extension": "Floating Point", "description": "Loads two consecutive floating-point or SIMD vector registers from memory at an address calculated from a base register and a scaled signed immediate offset. The two values are loaded atomically as a pair, and no condition flags are affected. Execution is AArch64-only; the immediate is scaled by the operand size (4 bytes for 32-bit, 8 bytes for 64-bit, 16 bytes for 128-bit).", "example": "LDP Qt1, Qt2, [x1, #16]", "pseudocode": "address ← (Xn | SP) + (imm7 << scale); Vt1 ← [address]; Vt2 ← [address + operand_size]" }, { "mnemonic": "stp", "architecture": "ARMv8-A", "full_name": "Store Pair SIMD&FP Registers", "summary": "Stores two floating-point/SIMD registers.", "syntax": "STP , , [, #]", "encoding": { "format": "Load/Store Pair", "binary_pattern": "00 | 101 | 1 | 010 | 0 | imm7 | Rt2 | Rn | Rt", "hex_opcode": "0x2D000000", "visual_parts": [ { "raw": "00", "clean": "00" }, { "raw": "101", "clean": "101" }, { "raw": "1", "clean": "1" }, { "raw": "010", "clean": "010" }, { "raw": "0", "clean": "0" }, { "raw": "imm7", "clean": "imm7" }, { "raw": "Rt2", "clean": "Rt2" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rt", "clean": "Rt" } ], "bit_positions": "31:30 | 29:27 | 26 | 25:23 | 22 | 21:15 | 14:10 | 9:5 | 4:0" }, "operands": [ { "name": "St1|Dt1|Qt1", "desc": "First transfer SIMD&FP register (single, double or quad-precision)" }, { "name": "St2|Dt2|Qt2", "desc": "Second transfer SIMD&FP register (single, double or quad-precision)" }, { "name": "Xn|SP", "desc": "First source / base 64-bit integer register" }, { "name": "imm", "desc": "Signed immediate value" } ], "extension": "Floating Point", "description": "Stores two consecutive floating-point or SIMD vector registers to memory at an address calculated from a base register and a scaled signed immediate offset. The two values are stored atomically as a pair, and no condition flags are affected. Execution is AArch64-only; the immediate is scaled by the operand size (4 bytes for 32-bit, 8 bytes for 64-bit, 16 bytes for 128-bit).", "example": "STP Qt1, Qt2, [x1, #16]", "pseudocode": "address ← (Xn | SP) + (imm7 << scale); [address] ← Vt1; [address + operand_size] ← Vt2" }, { "mnemonic": "ldrb", "architecture": "ARMv8-A", "full_name": "Load Register Byte (Immediate)", "summary": "Loads a byte from memory (zero-extended) using immediate offset.", "syntax": "LDRB , [, #]", "encoding": { "format": "Load/Store", "binary_pattern": "00 | 111 | 0 | 01 | 01 | imm12 | Rn | Rt", "hex_opcode": "0x39400000", "visual_parts": [ { "raw": "00", "clean": "00" }, { "raw": "111", "clean": "111" }, { "raw": "0", "clean": "0" }, { "raw": "01", "clean": "01" }, { "raw": "01", "clean": "01" }, { "raw": "imm12", "clean": "imm12" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rt", "clean": "Rt" } ], "bit_positions": "31:30 | 29:27 | 26 | 25:24 | 23:22 | 21:10 | 9:5 | 4:0" }, "operands": [ { "name": "Wt", "desc": "Transfer 32-bit integer register (load/store)" }, { "name": "Xn", "desc": "First source / base 64-bit integer register" }, { "name": "pimm", "desc": "Positive immediate offset" } ], "extension": "Base", "description": "Loads an unsigned byte from memory using immediate offset and zero-extends it to 32 bits, writing the result to a 32-bit register. No condition flags are affected. This is an AArch64 Base instruction that executes in all privilege levels.", "example": "LDRB w3, [x1, #16]", "pseudocode": "address ← Xn + (pimm << 0);\nWt ← ZeroExtend(Mem[address, 1], 32);" }, { "mnemonic": "ldrb", "architecture": "ARMv8-A", "full_name": "Load Register Byte (Register)", "summary": "Loads a byte from memory (zero-extended) using register offset.", "syntax": "LDRB , [, {, }]", "encoding": { "format": "Load/Store", "binary_pattern": "00 | 111 | 0 | 00 | 01 | 1 | Rm | option | S | 10 | Rn | Rt", "hex_opcode": "0x38600800", "visual_parts": [ { "raw": "00", "clean": "00" }, { "raw": "111", "clean": "111" }, { "raw": "0", "clean": "0" }, { "raw": "00", "clean": "00" }, { "raw": "01", "clean": "01" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "option", "clean": "option" }, { "raw": "S", "clean": "S" }, { "raw": "10", "clean": "10" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rt", "clean": "Rt" } ], "bit_positions": "31:30 | 29:27 | 26 | 25:24 | 23:22 | 21 | 20:16 | 15:13 | 12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Wt", "desc": "Transfer 32-bit integer register (load/store)" }, { "name": "Xn", "desc": "First source / base 64-bit integer register" }, { "name": "Rm", "desc": "Offset Reg" } ], "extension": "Base", "description": "Loads an unsigned byte from memory using register offset with optional shift/extension and zero-extends it to 32 bits. No condition flags are affected. This is an AArch64 Base instruction that executes in all privilege levels.", "example": "LDRB w3, [x1, Rm ]", "pseudocode": "offset ← ExtendReg(Rm, extend_type, shift_amount);\naddress ← Xn + offset;\nWt ← ZeroExtend(Mem[address, 1], 32);" }, { "mnemonic": "ldrh", "architecture": "ARMv8-A", "full_name": "Load Register Halfword (Immediate)", "summary": "Loads a halfword from memory (zero-extended).", "syntax": "LDRH , [, #]", "encoding": { "format": "Load/Store", "binary_pattern": "01 | 111 | 0 | 01 | 01 | imm12 | Rn | Rt", "hex_opcode": "0x79400000", "visual_parts": [ { "raw": "01", "clean": "01" }, { "raw": "111", "clean": "111" }, { "raw": "0", "clean": "0" }, { "raw": "01", "clean": "01" }, { "raw": "01", "clean": "01" }, { "raw": "imm12", "clean": "imm12" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rt", "clean": "Rt" } ], "bit_positions": "31:30 | 29:27 | 26 | 25:24 | 23:22 | 21:10 | 9:5 | 4:0" }, "operands": [ { "name": "Wt", "desc": "Transfer 32-bit integer register (load/store)" }, { "name": "Xn", "desc": "First source / base 64-bit integer register" }, { "name": "pimm", "desc": "Positive immediate offset" } ], "extension": "Base", "description": "Loads an unsigned halfword from memory using immediate offset and zero-extends it to 32 bits. No condition flags are affected. This is an AArch64 Base instruction that executes in all privilege levels.", "example": "LDRH w3, [x1, #16]", "pseudocode": "address ← Xn + (pimm << 1);\nWt ← ZeroExtend(Mem[address, 2], 32);" }, { "mnemonic": "ldrh", "architecture": "ARMv8-A", "full_name": "Load Register Halfword (Register)", "summary": "Loads a halfword from memory (zero-extended) using register offset.", "syntax": "LDRH , [, {, }]", "encoding": { "format": "Load/Store", "binary_pattern": "01 | 111 | 0 | 00 | 01 | 1 | Rm | option | S | 10 | Rn | Rt", "hex_opcode": "0x78600800", "visual_parts": [ { "raw": "01", "clean": "01" }, { "raw": "111", "clean": "111" }, { "raw": "0", "clean": "0" }, { "raw": "00", "clean": "00" }, { "raw": "01", "clean": "01" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "option", "clean": "option" }, { "raw": "S", "clean": "S" }, { "raw": "10", "clean": "10" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rt", "clean": "Rt" } ], "bit_positions": "31:30 | 29:27 | 26 | 25:24 | 23:22 | 21 | 20:16 | 15:13 | 12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Wt", "desc": "Transfer 32-bit integer register (load/store)" }, { "name": "Xn", "desc": "First source / base 64-bit integer register" }, { "name": "Rm", "desc": "Offset Reg" } ], "extension": "Base", "description": "Loads an unsigned halfword from memory using register offset with optional extension and zero-extends it to 32 bits. No condition flags are affected. This is an AArch64 Base instruction that executes in all privilege levels.", "example": "LDRH w3, [x1, Rm ]", "pseudocode": "offset ← ExtendReg(Rm, extend_type, shift_amount);\naddress ← Xn + offset;\nWt ← ZeroExtend(Mem[address, 2], 32);" }, { "mnemonic": "ldrsb", "architecture": "ARMv8-A", "full_name": "Load Register Signed Byte (Immediate)", "summary": "Loads a byte and sign-extends it to 32-bits.", "syntax": "LDRSB , [, #]", "encoding": { "format": "Load/Store", "binary_pattern": "00 | 111 | 0 | 01 | 11 | imm12 | Rn | Rt", "hex_opcode": "0x39C00000", "visual_parts": [ { "raw": "00", "clean": "00" }, { "raw": "111", "clean": "111" }, { "raw": "0", "clean": "0" }, { "raw": "01", "clean": "01" }, { "raw": "11", "clean": "11" }, { "raw": "imm12", "clean": "imm12" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rt", "clean": "Rt" } ], "bit_positions": "31:30 | 29:27 | 26 | 25:24 | 23:22 | 21:10 | 9:5 | 4:0" }, "operands": [ { "name": "Wt", "desc": "Transfer 32-bit integer register (load/store)" }, { "name": "Xn", "desc": "First source / base 64-bit integer register" }, { "name": "pimm", "desc": "Positive immediate offset" } ], "extension": "Base", "description": "Loads a signed byte from memory using immediate offset and sign-extends it to 32 bits. No condition flags are affected. This is an AArch64 Base instruction that executes in all privilege levels.", "example": "LDRSB w3, [x1, #16]", "pseudocode": "address ← Xn + (pimm << 0);\nWt ← SignExtend(Mem[address, 1], 32);" }, { "mnemonic": "ldrsb", "architecture": "ARMv8-A", "full_name": "Load Register Signed Byte (64-bit Immediate)", "summary": "Loads a byte and sign-extends it to 64-bits.", "syntax": "LDRSB , [, #]", "encoding": { "format": "Load/Store", "binary_pattern": "00 | 111 | 0 | 01 | 10 | imm12 | Rn | Rt", "hex_opcode": "0x39800000", "visual_parts": [ { "raw": "00", "clean": "00" }, { "raw": "111", "clean": "111" }, { "raw": "0", "clean": "0" }, { "raw": "01", "clean": "01" }, { "raw": "10", "clean": "10" }, { "raw": "imm12", "clean": "imm12" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rt", "clean": "Rt" } ], "bit_positions": "31:30 | 29:27 | 26 | 25:24 | 23:22 | 21:10 | 9:5 | 4:0" }, "operands": [ { "name": "Xt", "desc": "Transfer 64-bit integer register (load/store)" }, { "name": "Xn", "desc": "First source / base 64-bit integer register" }, { "name": "pimm", "desc": "Positive immediate offset" } ], "extension": "Base", "description": "Loads a signed byte from memory using immediate offset and sign-extends it to 64 bits. No condition flags are affected. This is an AArch64 Base instruction that executes in all privilege levels.", "example": "LDRSB x3, [x1, #16]", "pseudocode": "address ← Xn + (pimm << 0);\nXt ← SignExtend(Mem[address, 1], 64);" }, { "mnemonic": "ldrsw", "architecture": "ARMv8-A", "full_name": "Load Register Signed Word (Immediate)", "summary": "Loads a word and sign-extends it to 64-bits.", "syntax": "LDRSW , [, #]", "encoding": { "format": "Load/Store", "binary_pattern": "10 | 111 | 0 | 01 | 10 | imm12 | Rn | Rt", "hex_opcode": "0xB9800000", "visual_parts": [ { "raw": "10", "clean": "10" }, { "raw": "111", "clean": "111" }, { "raw": "0", "clean": "0" }, { "raw": "01", "clean": "01" }, { "raw": "10", "clean": "10" }, { "raw": "imm12", "clean": "imm12" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rt", "clean": "Rt" } ], "bit_positions": "31:30 | 29:27 | 26 | 25:24 | 23:22 | 21:10 | 9:5 | 4:0" }, "operands": [ { "name": "Xt", "desc": "Transfer 64-bit integer register (load/store)" }, { "name": "Xn", "desc": "First source / base 64-bit integer register" }, { "name": "pimm", "desc": "Positive immediate offset" } ], "extension": "Base", "description": "Loads a signed word from memory using immediate offset and sign-extends it to 64 bits. No condition flags are affected. This is an AArch64 Base instruction that executes in all privilege levels.", "example": "LDRSW x3, [x1, #16]", "pseudocode": "address ← Xn + (pimm << 2);\nXt ← SignExtend(Mem[address, 4], 64);" }, { "mnemonic": "ldrsw", "architecture": "ARMv8-A", "full_name": "Load Register Signed Word (Literal)", "summary": "Loads a word from PC-relative address and sign-extends to 64-bits.", "syntax": "LDRSW ,
, , ", "encoding": { "format": "NEON Table", "binary_pattern": "111100111 | D | 11 | Vn | Vd | 10 | len | N | 1 | M | 0 | Vm", "hex_opcode": "0xF3B00840", "visual_parts": [ { "raw": "111100111", "clean": "111100111" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "len", "clean": "len" }, { "raw": "N", "clean": "N" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Dd", "desc": "Dest/Base" }, { "name": "list", "desc": "Table" }, { "name": "Dm", "desc": "Indices" } ], "extension": "NEON (SIMD)", "description": "Performs a table lookup and extension: for each byte index in Dm, looks up the corresponding byte in the table (1-4 registers starting at Vn) and inserts it into the corresponding position in Dd, leaving unmapped indices unchanged in Dd. Condition flags (N, Z, C, V) are unaffected. Execution is restricted to A32/T32 with NEON extension; out-of-range indices preserve the original element in Dd.", "example": "VTBX.8 d0, {r0-r3}, d2", "pseudocode": "for i = 0 to 15 do\n index ← Dm.byte[i]\n if (index < (len + 1) * 16) then\n table_reg ← Vn + (index / 16)\n element_offset ← index mod 16\n Dd.byte[i] ← [table_reg].byte[element_offset]\n else\n Dd.byte[i] ← Dd.byte[i]" }, { "mnemonic": "vfma", "architecture": "ARMv8-A", "full_name": "Vector Fused Multiply Accumulate", "summary": "Computes Vd = Vd + (Vn * Vm) with single rounding.", "syntax": "VFMA.F32 , , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 0 | D | 0 | sz | Vn | Vd | 1100 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2000C10", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "0", "clean": "0" }, { "raw": "sz", "clean": "sz" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1100", "clean": "1100" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Dest/Acc" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "VFPv4 (SIMD)", "description": "Fused multiply-accumulate: computes Qd = Qd + (Qn × Qm) on 32-bit floating-point elements with a single rounding operation, improving precision over separate multiply and add. Condition flags (N, Z, C, V) are unaffected. Execution is restricted to A32/T32 with VFPv4 (NEON) extension; operates on 128-bit quad registers.", "example": "VFMA.F32 q0, q1, q2", "pseudocode": "for i = 0 to 3 do\n Qd[i] ← round_to_nearest(Qd[i] + (Qn[i] × Qm[i]))" }, { "mnemonic": "vfms", "architecture": "ARMv8-A", "full_name": "Vector Fused Multiply Subtract", "summary": "Computes Vd = Vd - (Vn * Vm) with single rounding.", "syntax": "VFMS.F32 , , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 0 | D | 1 | sz | Vn | Vd | 1100 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2200C10", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "1", "clean": "1" }, { "raw": "sz", "clean": "sz" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1100", "clean": "1100" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Dest/Acc" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "VFPv4 (SIMD)", "description": "Fused multiply-subtract: computes Qd = Qd - (Qn × Qm) on 32-bit floating-point elements with a single rounding operation, improving precision over separate multiply and subtract. Condition flags (N, Z, C, V) are unaffected. Execution is restricted to A32/T32 with VFPv4 (NEON) extension; operates on 128-bit quad registers.", "example": "VFMS.F32 q0, q1, q2", "pseudocode": "for i = 0 to 3 do\n Qd[i] ← round_to_nearest(Qd[i] - (Qn[i] × Qm[i]))" }, { "mnemonic": "vfnma", "architecture": "ARMv8-A", "full_name": "Vector Fused Negated Multiply Accumulate", "summary": "Computes Vd = Vd - (Vn * Vm).", "syntax": "VFNMA.F32 , , ", "encoding": { "format": "VFP Arith", "binary_pattern": "cond | 1110 | 1 | D | 01 | Vn | Vd | 10 | 10 | N | 1 | M | 0 | Vm", "hex_opcode": "0x0E900A40", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "1110", "clean": "1110" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "01", "clean": "01" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "N", "clean": "N" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:28 | 27:24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" }, { "name": "Sn", "desc": "First source 32-bit floating-point register" }, { "name": "Sm", "desc": "Second source 32-bit floating-point register" } ], "extension": "VFPv4 (Float)", "description": "Fused negated multiply-accumulate: computes Sd = Sd - (Sn × Sm) on 32-bit floating-point values with a single rounding operation. Condition flags (N, Z, C, V) are unaffected. Execution is restricted to A32/T32 with VFPv4 (scalar floating-point) extension; operates on 32-bit single-precision registers.", "example": "VFNMA.F32 s0, s1, s2", "pseudocode": "Sd ← round_to_nearest(Sd - (Sn × Sm))" }, { "mnemonic": "vfnms", "architecture": "ARMv8-A", "full_name": "Vector Fused Negated Multiply Subtract", "summary": "Computes Vd = -Vd + (Vn * Vm).", "syntax": "VFNMS.F32 , , ", "encoding": { "format": "VFP Arith", "binary_pattern": "cond | 1110 | 1 | D | 01 | Vn | Vd | 10 | 10 | N | 0 | M | 0 | Vm", "hex_opcode": "0x0E900A00", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "1110", "clean": "1110" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "01", "clean": "01" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:28 | 27:24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" }, { "name": "Sn", "desc": "First source 32-bit floating-point register" }, { "name": "Sm", "desc": "Second source 32-bit floating-point register" } ], "extension": "VFPv4 (Float)", "description": "Vector Fused Negated Multiply Subtract computes the negation of the destination plus the product of two operands: Sd = -Sd + (Sn * Sm). This is a single fused operation that performs multiplication and subtraction with only one rounding step, improving precision over separate operations. The instruction is available in VFPv4 and operates on 32-bit single-precision floating-point values. Condition flags (N, Z, C, V) are not affected; floating-point exception flags may be set based on the result.", "example": "VFNMS.F32 s0, s1, s2", "pseudocode": "Sd ← -Sd + (Sn * Sm)" }, { "mnemonic": "vrecps", "architecture": "ARMv8-A", "full_name": "Vector Reciprocal Step", "summary": "Newton-Raphson step for reciprocal refinement: (2 - Vn * Vm).", "syntax": "VRECPS.F32 , , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 0 | D | 0 | sz | Vn | Vd | 1111 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2000F10", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "0", "clean": "0" }, { "raw": "sz", "clean": "sz" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1111", "clean": "1111" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Vector Reciprocal Step performs a Newton-Raphson step for reciprocal refinement on 32-bit floating-point SIMD elements: Qd = 2.0 - (Qn * Qm). This operation is typically used iteratively to refine reciprocal approximations. The instruction operates on 128-bit SIMD registers, processing multiple 32-bit float elements in parallel. No integer flags are affected; floating-point exception flags may be set based on the results.", "example": "VRECPS.F32 q0, q1, q2", "pseudocode": "for i = 0 to 3\n Qd[i] ← 2.0 - (Qn[i] * Qm[i])" }, { "mnemonic": "vrsqrts", "architecture": "ARMv8-A", "full_name": "Vector Reciprocal Square Root Step", "summary": "Newton-Raphson step for reciprocal sqrt refinement: (3 - Vn * Vm) / 2.", "syntax": "VRSQRTS.F32 , , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 0 | D | 1 | sz | Vn | Vd | 1111 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2200F10", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "1", "clean": "1" }, { "raw": "sz", "clean": "sz" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1111", "clean": "1111" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Vector Reciprocal Square Root Step performs a Newton-Raphson step for reciprocal square root refinement on 32-bit floating-point SIMD elements: Qd = (3.0 - (Qn * Qm)) / 2.0. This operation is typically used iteratively to refine reciprocal square root approximations. The instruction operates on 128-bit SIMD registers, processing multiple 32-bit float elements in parallel. No integer flags are affected; floating-point exception flags may be set based on the results.", "example": "VRSQRTS.F32 q0, q1, q2", "pseudocode": "for i = 0 to 3\n Qd[i] ← (3.0 - (Qn[i] * Qm[i])) / 2.0" }, { "mnemonic": "vpadal", "architecture": "ARMv8-A", "full_name": "Vector Pairwise Add and Accumulate Long", "summary": "Adds adjacent pairs and accumulates into wide destination.", "syntax": "VPADAL.
, ", "encoding": { "format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 00 | Vd | 0 | 110 | op | 0 | M | 0 | Vm", "hex_opcode": "0xF3B00600", "visual_parts": [ { "raw": "111100111", "clean": "111100111" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "size", "clean": "size" }, { "raw": "00", "clean": "00" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0", "clean": "0" }, { "raw": "110", "clean": "110" }, { "raw": "op", "clean": "op" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Vector Pairwise Add and Accumulate Long adds adjacent pairs of elements from the source register and accumulates the results into the destination register, which is widened. The data type and element size are specified by the size field; both signed and unsigned variants exist. No condition flags are affected. The destination elements are wider than the source elements to accommodate the accumulated sums.", "example": "VPADAL.dt q0, q2", "pseudocode": "for i = 0 to (pairs_in_Qm - 1)\n Qd[i] ← Qd[i] + (Qm[2*i] + Qm[2*i+1])" }, { "mnemonic": "vpaddl", "architecture": "ARMv8-A", "full_name": "Vector Pairwise Add Long", "summary": "Adds adjacent pairs and produces wide result.", "syntax": "VPADDL.
, ", "encoding": { "format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 00 | Vd | 0 | 010 | op | 0 | M | 0 | Vm", "hex_opcode": "0xF3B00200", "visual_parts": [ { "raw": "111100111", "clean": "111100111" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "size", "clean": "size" }, { "raw": "00", "clean": "00" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0", "clean": "0" }, { "raw": "010", "clean": "010" }, { "raw": "op", "clean": "op" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Vector Pairwise Add Long adds adjacent pairs of elements from the source register and produces a widened result in the destination register. The data type and element size are specified by the size field; both signed and unsigned variants exist. No condition flags are affected. The destination elements are wider than the source elements to accommodate the pair sums.", "example": "VPADDL.dt q0, q2", "pseudocode": "for i = 0 to (pairs_in_Qm - 1)\n Qd[i] ← Qm[2*i] + Qm[2*i+1]" }, { "mnemonic": "vswp", "architecture": "ARMv8-A", "full_name": "Vector Swap", "summary": "Swaps the contents of two vectors.", "syntax": "VSWP , ", "encoding": { "format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | 00 | 10 | Vd | 0 | 0000 | 0 | M | 0 | Vm", "hex_opcode": "0xF3B20000", "visual_parts": [ { "raw": "111100111", "clean": "111100111" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "00", "clean": "00" }, { "raw": "10", "clean": "10" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0", "clean": "0" }, { "raw": "0000", "clean": "0000" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Reg 1" }, { "name": "Qm", "desc": "Reg 2" } ], "extension": "NEON (SIMD)", "description": "Vector Swap exchanges the entire contents of two SIMD registers. The register sizes (64-bit or 128-bit) are determined by the Q bit in the encoding. This is a data movement operation with no arithmetic or comparison; no condition flags are affected.", "example": "VSWP q0, q2", "pseudocode": "temp ← Qd\nQd ← Qm\nQm ← temp" }, { "mnemonic": "vmaxnm", "architecture": "ARMv8-A", "full_name": "Vector Maximum Number", "summary": "Returns larger value, handling NaNs per IEEE 754-2008.", "syntax": "VMAXNM.F32 , , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "111111101 | D | 00 | Vn | Vd | 10 | 10 | N | 0 | M | 0 | Vm", "hex_opcode": "0xFE800A00", "visual_parts": [ { "raw": "111111101", "clean": "111111101" }, { "raw": "D", "clean": "D" }, { "raw": "00", "clean": "00" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Vector Maximum Number returns the larger of two 32-bit floating-point values for each lane, handling NaN operands according to IEEE 754-2008 semantics (if one operand is NaN, the non-NaN value is returned). The instruction operates on 128-bit SIMD registers, processing multiple 32-bit float elements in parallel. No integer flags are affected; floating-point exception flags may be set based on the results.", "example": "VMAXNM.F32 q0, q1, q2", "pseudocode": "for i = 0 to 3\n if isNaN(Qn[i]) and not isNaN(Qm[i])\n Qd[i] ← Qm[i]\n else if isNaN(Qm[i]) and not isNaN(Qn[i])\n Qd[i] ← Qn[i]\n else\n Qd[i] ← max(Qn[i], Qm[i])" }, { "mnemonic": "vminnm", "architecture": "ARMv8-A", "full_name": "Vector Minimum Number", "summary": "Returns smaller value, handling NaNs per IEEE 754-2008.", "syntax": "VMINNM.F32 , , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "111111101 | D | 00 | Vn | Vd | 10 | 10 | N | 1 | M | 0 | Vm", "hex_opcode": "0xFE800A40", "visual_parts": [ { "raw": "111111101", "clean": "111111101" }, { "raw": "D", "clean": "D" }, { "raw": "00", "clean": "00" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "N", "clean": "N" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Vector Minimum Number returns the smaller of two 32-bit floating-point values for each lane, handling NaN operands according to IEEE 754-2008 semantics (if one operand is NaN, the non-NaN value is returned). The instruction operates on 128-bit SIMD registers, processing multiple 32-bit float elements in parallel. No integer flags are affected; floating-point exception flags may be set based on the results.", "example": "VMINNM.F32 q0, q1, q2", "pseudocode": "for i = 0 to 3\n if isNaN(Qn[i]) and not isNaN(Qm[i])\n Qd[i] ← Qm[i]\n else if isNaN(Qm[i]) and not isNaN(Qn[i])\n Qd[i] ← Qn[i]\n else\n Qd[i] ← min(Qn[i], Qm[i])" }, { "mnemonic": "vcvta", "architecture": "ARMv8-A", "full_name": "Vector Convert to Integer (Nearest)", "summary": "Converts float to integer, rounding to nearest.", "syntax": "VCVTA.
.F32 , ", "encoding": { "format": "NEON 2-Reg", "binary_pattern": "111111101 | D | 111 | 1 | 00 | Vd | 10 | 10 | op | 1 | M | 0 | Vm", "hex_opcode": "0xFEBC0A40", "visual_parts": [ { "raw": "111111101", "clean": "111111101" }, { "raw": "D", "clean": "D" }, { "raw": "111", "clean": "111" }, { "raw": "1", "clean": "1" }, { "raw": "00", "clean": "00" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "op", "clean": "op" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:19 | 18 | 17:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Converts each floating-point element in the source Q register to a signed or unsigned integer, rounding towards positive infinity (towards +∞), and writes the results to the destination Q register. This is a vector operation where each lane is independently converted. No NEON flags are modified; results follow IEEE 754 rounding semantics. This instruction requires NEON support and executes in AArch32 state (T32/A32).", "example": "VCVTA.dt.F32 q0, q2", "pseudocode": "for i ← 0 to (128 / element_width) - 1 do; element ← Qm[i]; integer_result ← ConvertToInteger(element, RoundTowardsPlusInfinity, unsigned); Qd[i] ← integer_result; end" }, { "mnemonic": "vcvtn", "architecture": "ARMv8-A", "full_name": "Vector Convert to Integer (Nearest Even)", "summary": "Converts float to integer, rounding to nearest even.", "syntax": "VCVTN.
.F32 , ", "encoding": { "format": "NEON 2-Reg", "binary_pattern": "111111101 | D | 111 | 1 | 01 | Vd | 10 | 10 | op | 1 | M | 0 | Vm", "hex_opcode": "0xFEBD0A40", "visual_parts": [ { "raw": "111111101", "clean": "111111101" }, { "raw": "D", "clean": "D" }, { "raw": "111", "clean": "111" }, { "raw": "1", "clean": "1" }, { "raw": "01", "clean": "01" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "op", "clean": "op" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:19 | 18 | 17:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Converts each floating-point element in the source Q register to a signed or unsigned integer, rounding to nearest even (banker's rounding), and writes the results to the destination Q register. This is a vector operation where each lane is independently converted. No NEON flags are modified; results follow IEEE 754 rounding semantics. This instruction requires NEON support and executes in AArch32 state (T32/A32).", "example": "VCVTN.dt.F32 q0, q2", "pseudocode": "for i ← 0 to (128 / element_width) - 1 do; element ← Qm[i]; integer_result ← ConvertToInteger(element, RoundToNearestEven, unsigned); Qd[i] ← integer_result; end" }, { "mnemonic": "vcvtp", "architecture": "ARMv8-A", "full_name": "Vector Convert to Integer (Plus Infinity)", "summary": "Converts float to integer, rounding towards +Inf (Ceil).", "syntax": "VCVTP.
.F32 , ", "encoding": { "format": "NEON 2-Reg", "binary_pattern": "111111101 | D | 111 | 1 | 10 | Vd | 10 | 10 | op | 1 | M | 0 | Vm", "hex_opcode": "0xFEBE0A40", "visual_parts": [ { "raw": "111111101", "clean": "111111101" }, { "raw": "D", "clean": "D" }, { "raw": "111", "clean": "111" }, { "raw": "1", "clean": "1" }, { "raw": "10", "clean": "10" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "op", "clean": "op" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:19 | 18 | 17:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Converts each floating-point element in the source Q register to a signed or unsigned integer, rounding towards positive infinity (ceiling), and writes the results to the destination Q register. This is a vector operation where each lane is independently converted. No NEON flags are modified; results follow IEEE 754 rounding semantics. This instruction requires NEON support and executes in AArch32 state (T32/A32).", "example": "VCVTP.dt.F32 q0, q2", "pseudocode": "for i ← 0 to (128 / element_width) - 1 do; element ← Qm[i]; integer_result ← ConvertToInteger(element, RoundTowardsPlusInfinity, unsigned); Qd[i] ← integer_result; end" }, { "mnemonic": "vcvtm", "architecture": "ARMv8-A", "full_name": "Vector Convert to Integer (Minus Infinity)", "summary": "Converts float to integer, rounding towards -Inf (Floor).", "syntax": "VCVTM.
.F32 , ", "encoding": { "format": "NEON 2-Reg", "binary_pattern": "111111101 | D | 111 | 1 | 11 | Vd | 10 | 10 | op | 1 | M | 0 | Vm", "hex_opcode": "0xFEBF0A40", "visual_parts": [ { "raw": "111111101", "clean": "111111101" }, { "raw": "D", "clean": "D" }, { "raw": "111", "clean": "111" }, { "raw": "1", "clean": "1" }, { "raw": "11", "clean": "11" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "op", "clean": "op" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:19 | 18 | 17:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Converts floating-point values in a NEON vector to signed integers, rounding towards negative infinity (floor). This is a NEON SIMD instruction that operates on 32-bit floating-point elements and produces integer results. No condition flags are affected by this instruction.", "example": "VCVTM.dt.F32 q0, q2", "pseudocode": "for i = 0 to elements-1\n Qd[i] ← RoundTowardsMinusInfinity(Qm[i])" }, { "mnemonic": "vrinta", "architecture": "ARMv8-A", "full_name": "Vector Round Floating-Point (Nearest)", "summary": "Rounds float to integral float (Nearest).", "syntax": "VRINTA.F32 , ", "encoding": { "format": "NEON 2-Reg", "binary_pattern": "111111101 | D | 111 | 0 | 00 | Vd | 10 | 10 | 0 | 1 | M | 0 | Vm", "hex_opcode": "0xFEB80A40", "visual_parts": [ { "raw": "111111101", "clean": "111111101" }, { "raw": "D", "clean": "D" }, { "raw": "111", "clean": "111" }, { "raw": "0", "clean": "0" }, { "raw": "00", "clean": "00" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:19 | 18 | 17:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Rounds each 32-bit floating-point element in the source vector to the nearest integer value, using round-to-nearest (ties away from zero) rounding mode, and writes the result as a floating-point value to the destination vector. This instruction does not modify the condition flags. Available in A32/T32 with NEON extension.", "example": "VRINTA.F32 q0, q2", "pseudocode": "for i = 0 to 3\n Qd[i] ← RoundToNearest(Qm[i])\nend for" }, { "mnemonic": "vrintn", "architecture": "ARMv8-A", "full_name": "Vector Round Floating-Point (Nearest Even)", "summary": "Rounds float to integral float (Nearest Even).", "syntax": "VRINTN.F32 , ", "encoding": { "format": "NEON 2-Reg", "binary_pattern": "111111101 | D | 111 | 0 | 01 | Vd | 10 | 10 | 0 | 1 | M | 0 | Vm", "hex_opcode": "0xFEB90A40", "visual_parts": [ { "raw": "111111101", "clean": "111111101" }, { "raw": "D", "clean": "D" }, { "raw": "111", "clean": "111" }, { "raw": "0", "clean": "0" }, { "raw": "01", "clean": "01" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:19 | 18 | 17:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Rounds each 32-bit floating-point element in the source vector to the nearest integer value, using round-to-nearest-even (banker's rounding) rounding mode, and writes the result as a floating-point value to the destination vector. This instruction does not modify the condition flags. Available in A32/T32 with NEON extension.", "example": "VRINTN.F32 q0, q2", "pseudocode": "for i = 0 to 3\n Qd[i] ← RoundToNearestEven(Qm[i])\nend for" }, { "mnemonic": "vrintz", "architecture": "ARMv8-A", "full_name": "Vector Round Floating-Point (Zero)", "summary": "Rounds float to integral float (Towards Zero).", "syntax": "VRINTZ.F32 , ", "encoding": { "format": "NEON 2-Reg", "binary_pattern": "cond | 11101 | D | 11 | 0 | 110 | Vd | 10 | 10 | 1 | 1 | M | 0 | Vm", "hex_opcode": "0x0EB60AC0", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "11101", "clean": "11101" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "0", "clean": "0" }, { "raw": "110", "clean": "110" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Rounds each 32-bit floating-point element in the source vector towards zero to an integer value, and writes the result as a floating-point value to the destination vector. This instruction does not modify the condition flags. Available in A32/T32 with NEON extension.", "example": "VRINTZ.F32 q0, q2", "pseudocode": "for i = 0 to 3\n Qd[i] ← RoundTowardsZero(Qm[i])\nend for" }, { "mnemonic": "vsel", "architecture": "ARMv8-A", "full_name": "Vector Select", "summary": "Selects elements from Dn or Dm based on condition flags (predicated VFP).", "syntax": "VSEL.F32 , , ", "encoding": { "format": "VFP Misc", "binary_pattern": "11111110 | 0 | D | cc | Vn | Vd | 1010 | N | 0 | M | Vm", "hex_opcode": "0xFE000A00", "visual_parts": [ { "raw": "11111110", "clean": "11111110" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "cc", "clean": "cc" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1010", "clean": "1010" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "Vm", "clean": "Vm" } ] }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" }, { "name": "Sn", "desc": "First source 32-bit floating-point register" }, { "name": "Sm", "desc": "Second source 32-bit floating-point register" } ], "extension": "VFP (Float)", "description": "Conditionally selects the 32-bit floating-point value from either Sn or Sm based on the current state of the condition flags and writes it to Sd. The condition code (cc) embedded in the instruction determines which flag combination is tested. This instruction does not modify condition flags. Available in A32/T32 with VFP extension.", "example": "VSELcond.F32 s0, s1, s2", "pseudocode": "if ConditionHolds(cc) then\n Sd ← Sn\nelse\n Sd ← Sm\nend if" }, { "mnemonic": "aese", "architecture": "ARMv8-A", "full_name": "AES Encrypt (A32)", "summary": "Performs one round of AES encryption (AArch32).", "syntax": "AESE.8 , ", "encoding": { "format": "Crypto 2-Reg", "binary_pattern": "11110011 | 1 | D | 11 | 00 | 00 | Vd | 00110 | Q | M | 0 | Vm", "hex_opcode": "0xF3B00300", "visual_parts": [ { "raw": "11110011", "clean": "11110011" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "00", "clean": "00" }, { "raw": "00", "clean": "00" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "00110", "clean": "00110" }, { "raw": "Q", "clean": "Q" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:24 | 23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11:7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Data" }, { "name": "Qm", "desc": "Key" } ], "extension": "Crypto", "description": "Performs a single round of AES encryption (SubBytes, ShiftRows, MixColumns, and AddRoundKey stages) on the 128-bit data block in Qd using the 128-bit round key in Qm. The result is written back to Qd. This instruction does not modify the condition flags. Available in A32/T32 with Crypto extension and requires AES feature.", "example": "AESE.8 q0, q2", "pseudocode": "state ← Qd\nround_key ← Qm\nstate ← SubBytes(state)\nstate ← ShiftRows(state)\nstate ← MixColumns(state)\nstate ← AddRoundKey(state, round_key)\nQd ← state" }, { "mnemonic": "aesd", "architecture": "ARMv8-A", "full_name": "AES Decrypt (A32)", "summary": "Performs one round of AES decryption (AArch32).", "syntax": "AESD.8 , ", "encoding": { "format": "Crypto 2-Reg", "binary_pattern": "11110011 | 1 | D | 11 | 00 | 00 | Vd | 00111 | Q | M | 0 | Vm", "hex_opcode": "0xF3B00340", "visual_parts": [ { "raw": "11110011", "clean": "11110011" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "00", "clean": "00" }, { "raw": "00", "clean": "00" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "00111", "clean": "00111" }, { "raw": "Q", "clean": "Q" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:24 | 23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11:7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Data" }, { "name": "Qm", "desc": "Key" } ], "extension": "Crypto", "description": "Performs a single round of AES decryption (InvShiftRows, InvSubBytes, AddRoundKey, and InvMixColumns stages) on the 128-bit data block in Qd using the 128-bit round key in Qm. The result is written back to Qd. This instruction does not modify the condition flags. Available in A32/T32 with Crypto extension and requires AES feature.", "example": "AESD.8 q0, q2", "pseudocode": "state ← Qd\nround_key ← Qm\nstate ← InvShiftRows(state)\nstate ← InvSubBytes(state)\nstate ← AddRoundKey(state, round_key)\nstate ← InvMixColumns(state)\nQd ← state" }, { "mnemonic": "aesmc", "architecture": "ARMv8-A", "full_name": "AES Mix Columns (A32)", "summary": "AES Mix Columns transformation.", "syntax": "AESMC.8 , ", "encoding": { "format": "Crypto 2-Reg", "binary_pattern": "11110011 | 1 | D | 11 | 00 | 10 | Vd | 00110 | Q | M | 0 | Vm", "hex_opcode": "0xF3B00380", "visual_parts": [ { "raw": "11110011", "clean": "11110011" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "00", "clean": "00" }, { "raw": "10", "clean": "10" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "00110", "clean": "00110" }, { "raw": "Q", "clean": "Q" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:24 | 23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11:7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "Crypto", "description": "Applies the AES MixColumns (forward) transformation to each column of the 128-bit state in Qm and writes the result to Qd. This transformation is equivalent to one round's MixColumns operation and is used in key expansion during AES encryption. This instruction does not modify the condition flags. Available in A32/T32 with Crypto extension and requires AES feature.", "example": "AESMC.8 q0, q2", "pseudocode": "Qd ← AESMixColumns(Qm)" }, { "mnemonic": "aesimc", "architecture": "ARMv8-A", "full_name": "AES Inverse Mix Columns (A32)", "summary": "AES Inverse Mix Columns transformation.", "syntax": "AESIMC.8 , ", "encoding": { "format": "Crypto 2-Reg", "binary_pattern": "11110011 | 1 | D | 11 | 00 | 10 | Vd | 00111 | Q | M | 0 | Vm", "hex_opcode": "0xF3B003C0", "visual_parts": [ { "raw": "11110011", "clean": "11110011" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "00", "clean": "00" }, { "raw": "10", "clean": "10" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "00111", "clean": "00111" }, { "raw": "Q", "clean": "Q" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:24 | 23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11:7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "Crypto", "description": "Applies the AES Inverse MixColumns (inverse) transformation to each column of the 128-bit state in Qm and writes the result to Qd. This transformation reverses the forward MixColumns operation and is used in equivalent inverse cipher key expansion during AES decryption. This instruction does not modify the condition flags. Available in A32/T32 with Crypto extension and requires AES feature.", "example": "AESIMC.8 q0, q2", "pseudocode": "Qd ← AESInverseMixColumns(Qm)" }, { "mnemonic": "sha1c", "architecture": "ARMv8-A", "full_name": "SHA1 Choose (A32)", "summary": "SHA1 hash update (Choose).", "syntax": "SHA1C.32 , , ", "encoding": { "format": "Crypto 3-Reg", "binary_pattern": "11110010 | 0 | 0 | 0 | Vn | Vd | 0011 | N | Q | M | 0 | Vm", "hex_opcode": "0xF2000C00", "visual_parts": [ { "raw": "11110010", "clean": "11110010" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0011", "clean": "0011" }, { "raw": "N", "clean": "N" }, { "raw": "Q", "clean": "Q" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ] }, "operands": [ { "name": "Qd", "desc": "State" }, { "name": "Qn", "desc": "Hash" }, { "name": "Qm", "desc": "Data" } ], "extension": "Crypto", "description": "SHA1 Choose function: updates SHA1 hash state by computing the Choose operation on 32-bit elements. This instruction performs a cryptographic hash round step specific to SHA1 and is part of the ARM Cryptographic Extension. No condition flags are affected. Available in A32 and T32 with Crypto extension support.", "example": "SHA1C.32 q0, q1, q2", "pseudocode": "Qd[127:96] ← SHA1_CHOOSE(Qd[127:96], Qn[127:96], Qm[127:96])\nQd[95:64] ← SHA1_CHOOSE(Qd[95:64], Qn[95:64], Qm[95:64])\nQd[63:32] ← SHA1_CHOOSE(Qd[63:32], Qn[63:32], Qm[63:32])\nQd[31:0] ← SHA1_CHOOSE(Qd[31:0], Qn[31:0], Qm[31:0])" }, { "mnemonic": "sha1h", "architecture": "ARMv8-A", "full_name": "SHA1 Hash Update (A32)", "summary": "Updates SHA1 hash state.", "syntax": "SHA1H.32 , ", "encoding": { "format": "Crypto 2-Reg", "binary_pattern": "11110011 | 1 | D | 11 | 10 | 10 | Vd | 00000 | Q | M | 1 | Vm", "hex_opcode": "0xF3B102C0", "visual_parts": [ { "raw": "11110011", "clean": "11110011" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "00000", "clean": "00000" }, { "raw": "Q", "clean": "Q" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:24 | 23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11:7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "Crypto", "description": "SHA1 Hash Update: performs the final hash update step in the SHA1 algorithm by processing the hash state. This instruction computes the SHA1 hash finalization on four 32-bit words in parallel. No condition flags are affected. Available in A32 and T32 with Crypto extension support.", "example": "SHA1H.32 q0, q2", "pseudocode": "Qd[127:96] ← ROTATE_LEFT(Qm[127:96], 30)\nQd[95:64] ← ROTATE_LEFT(Qm[95:64], 30)\nQd[63:32] ← ROTATE_LEFT(Qm[63:32], 30)\nQd[31:0] ← ROTATE_LEFT(Qm[31:0], 30)" }, { "mnemonic": "sha1m", "architecture": "ARMv8-A", "full_name": "SHA1 Majority (A32)", "summary": "SHA1 hash update (Majority).", "syntax": "SHA1M.32 , , ", "encoding": { "format": "Crypto 3-Reg", "binary_pattern": "11110010 | 0 | 0 | 10 | Vn | Vd | 0011 | N | Q | M | 0 | Vm", "hex_opcode": "0xF2200C00", "visual_parts": [ { "raw": "11110010", "clean": "11110010" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "10", "clean": "10" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0011", "clean": "0011" }, { "raw": "N", "clean": "N" }, { "raw": "Q", "clean": "Q" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "State" }, { "name": "Qn", "desc": "Hash" }, { "name": "Qm", "desc": "Data" } ], "extension": "Crypto", "description": "SHA1 Majority function: updates SHA1 hash state by computing the Majority operation on 32-bit elements. This instruction performs a cryptographic hash round step specific to SHA1 and is part of the ARM Cryptographic Extension. No condition flags are affected. Available in A32 and T32 with Crypto extension support.", "example": "SHA1M.32 q0, q1, q2", "pseudocode": "Qd[127:96] ← SHA1_MAJORITY(Qd[127:96], Qn[127:96], Qm[127:96])\nQd[95:64] ← SHA1_MAJORITY(Qd[95:64], Qn[95:64], Qm[95:64])\nQd[63:32] ← SHA1_MAJORITY(Qd[63:32], Qn[63:32], Qm[63:32])\nQd[31:0] ← SHA1_MAJORITY(Qd[31:0], Qn[31:0], Qm[31:0])" }, { "mnemonic": "sha1p", "architecture": "ARMv8-A", "full_name": "SHA1 Parity (A32)", "summary": "SHA1 hash update (Parity).", "syntax": "SHA1P.32 , , ", "encoding": { "format": "Crypto 3-Reg", "binary_pattern": "11110010 | 0 | 0 | 01 | Vn | Vd | 0011 | N | Q | M | 0 | Vm", "hex_opcode": "0xF2100C00", "visual_parts": [ { "raw": "11110010", "clean": "11110010" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "01", "clean": "01" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0011", "clean": "0011" }, { "raw": "N", "clean": "N" }, { "raw": "Q", "clean": "Q" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "State" }, { "name": "Qn", "desc": "Hash" }, { "name": "Qm", "desc": "Data" } ], "extension": "Crypto", "description": "SHA1 Parity function: updates SHA1 hash state by computing the Parity operation on 32-bit elements. This instruction performs a cryptographic hash round step specific to SHA1 and is part of the ARM Cryptographic Extension. No condition flags are affected. Available in A32 and T32 with Crypto extension support.", "example": "SHA1P.32 q0, q1, q2", "pseudocode": "Qd[127:96] ← SHA1_PARITY(Qd[127:96], Qn[127:96], Qm[127:96])\nQd[95:64] ← SHA1_PARITY(Qd[95:64], Qn[95:64], Qm[95:64])\nQd[63:32] ← SHA1_PARITY(Qd[63:32], Qn[63:32], Qm[63:32])\nQd[31:0] ← SHA1_PARITY(Qd[31:0], Qn[31:0], Qm[31:0])" }, { "mnemonic": "crc32b", "architecture": "ARMv8-A", "full_name": "CRC32 Byte (A32)", "summary": "CRC32 checksum update (Byte).", "syntax": "CRC32B , , ", "encoding": { "format": "Data Proc", "binary_pattern": "cond | 00010 | 00 | 0 | Rn | Rd | 0 | 0 | 0 | 0 | 0100 | Rm", "hex_opcode": "0x01000040", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00010", "clean": "00010" }, { "raw": "00", "clean": "00" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0100", "clean": "0100" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "Acc" }, { "name": "Rm", "desc": "Data" } ], "extension": "CRC", "description": "CRC32 Checksum Update (Byte): accumulates a 32-bit CRC checksum by processing a single byte from the input. Rd is updated with CRC32(Rn, Rm[7:0]) using the standard CRC32 polynomial. No condition flags are affected. Subject to condition code in A32; available in A32 only with CRC extension.", "example": "CRC32B r0, r1, r2", "pseudocode": "Rd ← CRC32_POLYNOMIAL(Rn, Rm[7:0])" }, { "mnemonic": "crc32w", "architecture": "ARMv8-A", "full_name": "CRC32 Word (A32)", "summary": "CRC32 checksum update (Word).", "syntax": "CRC32W , , ", "encoding": { "format": "Data Proc", "binary_pattern": "cond | 00010 | 10 | 0 | Rn | Rd | 0 | 0 | 0 | 0 | 0100 | Rm", "hex_opcode": "0x01400040", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00010", "clean": "00010" }, { "raw": "10", "clean": "10" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0100", "clean": "0100" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "Acc" }, { "name": "Rm", "desc": "Data" } ], "extension": "CRC", "description": "CRC32 Checksum Update (Word): accumulates a 32-bit CRC checksum by processing a full 32-bit word from the input. Rd is updated with CRC32(Rn, Rm[31:0]) using the standard CRC32 polynomial. No condition flags are affected. Subject to condition code in A32; available in A32 only with CRC extension.", "example": "CRC32W r0, r1, r2", "pseudocode": "Rd ← CRC32_POLYNOMIAL(Rn, Rm[31:0])" }, { "mnemonic": "smc", "architecture": "ARMv8-A", "full_name": "Secure Monitor Call (A32)", "summary": "Calls the Secure Monitor (EL3).", "syntax": "SMC #", "encoding": { "format": "System", "binary_pattern": "cond | 00010 | 11 | 0 | 000000000000 | 0111 | imm4", "hex_opcode": "0x01600070", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00010", "clean": "00010" }, { "raw": "11", "clean": "11" }, { "raw": "0", "clean": "0" }, { "raw": "000000000000", "clean": "000000000000" }, { "raw": "0111", "clean": "0111" }, { "raw": "imm4", "clean": "imm4" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:8 | 7:4 | 3:0" }, "operands": [ { "name": "imm", "desc": "ID" } ], "extension": "A32 (System)", "description": "Secure Monitor Call: a synchronous exception that transitions execution to the Secure Monitor at EL3 to handle a secure service request. The immediate value encodes the SMC ID for the handler. This instruction requires Secure state; execution in Non-secure state is subject to the SMCNC trap. Subject to condition code in A32.", "example": "SMC #16", "pseudocode": "exception_taken ← 'SMC'\nELR_EL3 ← PC + 4\nSPSR_EL3 ← CPSR\nCPSR.M ← '10110' (Monitor mode)\nPC ← VECTOR_SMC" }, { "mnemonic": "lda", "architecture": "ARMv8-A", "full_name": "Load Acquire (A32)", "summary": "Loads a word with Acquire semantics.", "syntax": "LDA , []", "encoding": { "format": "Load/Store", "binary_pattern": "cond | 00011 | 00 | 1 | Rn | Rt | 1 | 1 | 0 | 0 | 1001 | 1111", "hex_opcode": "0x01900C9F", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00011", "clean": "00011" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rt", "clean": "Rt" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "1001", "clean": "1001" }, { "raw": "1111", "clean": "1111" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rt", "desc": "Transfer general-purpose register (load/store)" }, { "name": "Rn", "desc": "First source / base general-purpose register" } ], "extension": "A32 (Atomic)", "description": "Load Acquire: loads a 32-bit word from memory with Acquire semantics, ensuring memory synchronization and preventing subsequent memory operations from being reordered before this load. The address is computed from Rn (no offset). No condition flags are affected. Subject to condition code in A32; available in A32 with Atomic extension.", "example": "LDA r3, [r1]", "pseudocode": "Rt ← [Rn]\nAcquire_Semantics()" }, { "mnemonic": "stl", "architecture": "ARMv8-A", "full_name": "Store Release (A32)", "summary": "Stores a word with Release semantics.", "syntax": "STL , []", "encoding": { "format": "Load/Store", "binary_pattern": "cond | 00011 | 00 | 0 | Rn | 1111 | 1 | 1 | 0 | 0 | 1001 | Rt", "hex_opcode": "0x0180FC90", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00011", "clean": "00011" }, { "raw": "00", "clean": "00" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "1111", "clean": "1111" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "1001", "clean": "1001" }, { "raw": "Rt", "clean": "Rt" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rt", "desc": "Transfer general-purpose register (load/store)" }, { "name": "Rn", "desc": "First source / base general-purpose register" } ], "extension": "A32 (Atomic)", "description": "Stores a 32-bit word to memory with Release semantics, ensuring all prior memory operations are visible to other observers before the store completes. No condition flags are affected. This is an A32-only instruction that provides atomic release semantics for synchronization.", "example": "STL r3, [r1]", "pseudocode": "address ← Rn\nMemoryOrder ← Release\n[address] ← Rt[31:0]\nDRAIN_RELEASE_BARRIER()" }, { "mnemonic": "ldaex", "architecture": "ARMv8-A", "full_name": "Load Acquire Exclusive (A32)", "summary": "Loads a word with Acquire Exclusive semantics.", "syntax": "LDAEX , []", "encoding": { "format": "Load/Store", "binary_pattern": "cond | 00011 | 00 | 1 | Rn | Rt | 1 | 1 | 1 | 0 | 1001 | 1111", "hex_opcode": "0x01900E9F", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00011", "clean": "00011" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rt", "clean": "Rt" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "1001", "clean": "1001" }, { "raw": "1111", "clean": "1111" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rt", "desc": "Transfer general-purpose register (load/store)" }, { "name": "Rn", "desc": "First source / base general-purpose register" } ], "extension": "A32 (Atomic)", "description": "Loads a 32-bit word from memory with Acquire Exclusive semantics, allowing subsequent memory operations to observe earlier loads and stores. The processor acquires exclusive access to the address for potential paired store-exclusive. No condition flags are affected. This is an A32-only instruction.", "example": "LDAEX r3, [r1]", "pseudocode": "address ← Rn\nMemoryOrder ← Acquire\nRt ← [address]\nSET_EXCLUSIVE_MONITOR(address)\nDRAIN_ACQUIRE_BARRIER()" }, { "mnemonic": "stlex", "architecture": "ARMv8-A", "full_name": "Store Release Exclusive (A32)", "summary": "Stores a word with Release Exclusive semantics.", "syntax": "STLEX , , []", "encoding": { "format": "Load/Store", "binary_pattern": "cond | 00011 | 00 | 0 | Rn | Rd | 1 | 1 | 1 | 0 | 1001 | Rt", "hex_opcode": "0x01800E90", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00011", "clean": "00011" }, { "raw": "00", "clean": "00" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "1001", "clean": "1001" }, { "raw": "Rt", "clean": "Rt" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Status" }, { "name": "Rt", "desc": "Transfer general-purpose register (load/store)" }, { "name": "Rn", "desc": "First source / base general-purpose register" } ], "extension": "A32 (Atomic)", "description": "Atomically stores a 32-bit word to memory with Release semantics and exclusive access, writing status to Rd. This A32 instruction is used for inter-processor synchronization and memory ordering. The status register Rd is written with 0 on success or 1 on failure; no condition flags are affected.", "example": "STLEX r0, r3, [r1]", "pseudocode": "if ExclusiveAccess[Rn] then\n [Rn] ← Rt\n Rd ← 0\n ClearExclusiveAccess()\nelse\n Rd ← 1" }, { "mnemonic": "bfdot", "architecture": "ARMv8-A", "full_name": "BFloat16 Dot Product (NEON)", "summary": "Computes dot product of BFloat16 elements, accumulating to Float32 (NEON).", "syntax": "BFDOT ., ., .", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "0 | Q | 1 | 01110 | 01 | 0 | Rm | 1 | 1111 | 1 | Rn | Rd", "hex_opcode": "0x2E40FC00", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "Q", "clean": "Q" }, { "raw": "1", "clean": "1" }, { "raw": "01110", "clean": "01110" }, { "raw": "01", "clean": "01" }, { "raw": "0", "clean": "0" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "1", "clean": "1" }, { "raw": "1111", "clean": "1111" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15 | 14:11 | 10 | 9:5 | 4:0" }, "operands": [ { "name": "Vd", "desc": "Dest (F32)" }, { "name": "Vn", "desc": "Src1 (BF16)" }, { "name": "Vm", "desc": "Src2 (BF16)" } ], "extension": "FEAT_BF16 (AI)", "description": "Computes the dot product of BFloat16 pairs from two NEON vectors and accumulates the Float32 result into the destination vector. Requires FEAT_BF16. No flags are affected. Operates on 128-bit NEON vectors with BFloat16 source elements.", "example": "BFDOT v0.4s.T, v1.4s.T, v2.4s.T", "pseudocode": "for i = 0 to elements-1 do\n product ← BF16_to_F32(Vn[2*i]) × BF16_to_F32(Vm[2*i]) +\n BF16_to_F32(Vn[2*i+1]) × BF16_to_F32(Vm[2*i+1])\n Vd[i] ← Vd[i] + product\nend for" }, { "mnemonic": "bfmmla", "architecture": "ARMv8-A", "full_name": "BFloat16 Matrix Multiply-Accumulate (NEON)", "summary": "Performs 2x2 matrix multiplication on BFloat16 tiles (NEON).", "syntax": "BFMMLA ., ., .", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "0 | 1 | 1 | 01110 | 01 | 0 | Rm | 1 | 1101 | 1 | Rn | Rd", "hex_opcode": "0x6E40EC00", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "01110", "clean": "01110" }, { "raw": "01", "clean": "01" }, { "raw": "0", "clean": "0" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "1", "clean": "1" }, { "raw": "1101", "clean": "1101" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15 | 14:11 | 10 | 9:5 | 4:0" }, "operands": [ { "name": "Vd", "desc": "Destination SIMD/FP vector register" }, { "name": "Vn", "desc": "First source SIMD/FP vector register" }, { "name": "Vm", "desc": "Second source SIMD/FP vector register" } ], "extension": "FEAT_BF16 (AI)", "description": "Performs a 2×2 matrix multiply-accumulate operation on BFloat16 tiles, accumulating the result into Float32 elements of the destination vector. Requires FEAT_BF16. No flags are affected. Operates on 128-bit NEON vectors.", "example": "BFMMLA v0.4s.T, v1.4s.T, v2.4s.T", "pseudocode": "for i = 0 to 1 do\n for j = 0 to 1 do\n sum ← Vd[i*2+j]\n for k = 0 to 1 do\n sum ← sum + (BF16_to_F32(Vn[i*2+k]) × BF16_to_F32(Vm[k*2+j]))\n end for\n Vd[i*2+j] ← sum\n end for\nend for" }, { "mnemonic": "bfcvtn", "architecture": "ARMv8-A", "full_name": "BFloat16 Convert Narrow (NEON)", "summary": "Converts Float32 to BFloat16 (Lower Half).", "syntax": "BFCVTN ., .", "encoding": { "format": "NEON 2-Reg", "binary_pattern": "0 | Q | 0 | 01110 | 10 | 10000 | 10110 | 10 | Rn | Rd", "hex_opcode": "0x0EA16800", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "Q", "clean": "Q" }, { "raw": "0", "clean": "0" }, { "raw": "01110", "clean": "01110" }, { "raw": "10", "clean": "10" }, { "raw": "10000", "clean": "10000" }, { "raw": "10110", "clean": "10110" }, { "raw": "10", "clean": "10" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:17 | 16:12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Vd", "desc": "Dest (BF16)" }, { "name": "Vn", "desc": "Src (F32)" } ], "extension": "FEAT_BF16 (AI)", "description": "Converts Float32 values from the first half of the source vector to BFloat16 format and stores them in the lower half of the destination vector, leaving the upper half unchanged. Requires FEAT_BF16. No flags are affected. Operates on NEON vectors.", "example": "BFCVTN v0.4s.Tb, v1.4s.Ta", "pseudocode": "for i = 0 to 3 do\n Vd[i] ← F32_to_BF16(Vn[i])\nend for\nVd[8:4] ← Vd[8:4] // Upper half unchanged" }, { "mnemonic": "bfcvtn2", "architecture": "ARMv8-A", "full_name": "BFloat16 Convert Narrow High (NEON)", "summary": "Converts Float32 to BFloat16 (Upper Half).", "syntax": "BFCVTN2 ., .", "encoding": { "format": "NEON 2-Reg", "binary_pattern": "0 | Q | 0 | 01110 | 10 | 10000 | 10110 | 10 | Rn | Rd", "hex_opcode": "0x0EA16800", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "Q", "clean": "Q" }, { "raw": "0", "clean": "0" }, { "raw": "01110", "clean": "01110" }, { "raw": "10", "clean": "10" }, { "raw": "10000", "clean": "10000" }, { "raw": "10110", "clean": "10110" }, { "raw": "10", "clean": "10" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:17 | 16:12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Vd", "desc": "Dest (BF16)" }, { "name": "Vn", "desc": "Src (F32)" } ], "extension": "FEAT_BF16 (AI)", "description": "Converts Float32 values from the source vector to BFloat16 format and stores them in the upper half of the destination vector, leaving the lower half unchanged. Requires FEAT_BF16. No flags are affected. Operates on NEON vectors.", "example": "BFCVTN2 v0.4s.Tb, v1.4s.Ta", "pseudocode": "for i = 0 to 3 do\n Vd[i+4] ← F32_to_BF16(Vn[i])\nend for\nVd[3:0] ← Vd[3:0] // Lower half unchanged" }, { "mnemonic": "smmla", "architecture": "ARMv8-A", "full_name": "Signed Integer Matrix Multiply-Accumulate (NEON)", "summary": "Performs 2x2 matrix multiplication on Signed Int8 tiles.", "syntax": "SMMLA ., ., .", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "0 | 1 | 0 | 01110 | 10 | 0 | Rm | 1010 | 0 | 1 | Rn | Rd", "hex_opcode": "0x4E80A400", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "01110", "clean": "01110" }, { "raw": "10", "clean": "10" }, { "raw": "0", "clean": "0" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "1010", "clean": "1010" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:12 | 11 | 10 | 9:5 | 4:0" }, "operands": [ { "name": "Vd", "desc": "Destination SIMD/FP vector register" }, { "name": "Vn", "desc": "First source SIMD/FP vector register" }, { "name": "Vm", "desc": "Second source SIMD/FP vector register" } ], "extension": "FEAT_I8MM (AI)", "description": "Performs a 2×2 signed integer matrix multiply-accumulate operation on Int8 tiles, accumulating the result into Int32 elements of the destination vector. Requires FEAT_I8MM. No flags are affected. Operates on 128-bit NEON vectors.", "example": "SMMLA v0.4s.T, v1.4s.T, v2.4s.T", "pseudocode": "for i = 0 to 1 do\n for j = 0 to 1 do\n sum ← Vd[i*4+j*4 : i*4+j*4+31]\n for k = 0 to 1 do\n sum ← sum + (SignExtend(Vn[i*4+k*4 : i*4+k*4+7]) × SignExtend(Vm[k*4+j*4 : k*4+j*4+7]))\n end for\n Vd[i*4+j*4 : i*4+j*4+31] ← sum\n end for\nend for" }, { "mnemonic": "ummla", "architecture": "ARMv8-A", "full_name": "Unsigned Integer Matrix Multiply-Accumulate (NEON)", "summary": "Performs 2x2 matrix multiplication on Unsigned Int8 tiles.", "syntax": "UMMLA ., ., .", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "0 | 1 | 1 | 01110 | 10 | 0 | Rm | 1010 | 0 | 1 | Rn | Rd", "hex_opcode": "0x6E80A400", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "01110", "clean": "01110" }, { "raw": "10", "clean": "10" }, { "raw": "0", "clean": "0" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "1010", "clean": "1010" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:12 | 11 | 10 | 9:5 | 4:0" }, "operands": [ { "name": "Vd", "desc": "Destination SIMD/FP vector register" }, { "name": "Vn", "desc": "First source SIMD/FP vector register" }, { "name": "Vm", "desc": "Second source SIMD/FP vector register" } ], "extension": "FEAT_I8MM (AI)", "description": "Performs a 2×2 unsigned integer matrix multiply-accumulate operation on Int8 tiles, accumulating the result into Int32 elements of the destination vector. Requires FEAT_I8MM. No flags are affected. Operates on 128-bit NEON vectors.", "example": "UMMLA v0.4s.T, v1.4s.T, v2.4s.T", "pseudocode": "for i = 0 to 1 do\n for j = 0 to 1 do\n sum ← Vd[i*4+j*4 : i*4+j*4+31]\n for k = 0 to 1 do\n sum ← sum + (ZeroExtend(Vn[i*4+k*4 : i*4+k*4+7]) × ZeroExtend(Vm[k*4+j*4 : k*4+j*4+7]))\n end for\n Vd[i*4+j*4 : i*4+j*4+31] ← sum\n end for\nend for" }, { "mnemonic": "usmmla", "architecture": "ARMv8-A", "full_name": "Unsigned-Signed Matrix Multiply-Accumulate (NEON)", "summary": "Matrix multiply Unsigned Int8 with Signed Int8.", "syntax": "USMMLA ., ., .", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "0 | 1 | 0 | 01110 | 10 | 0 | Rm | 1010 | 1 | 1 | Rn | Rd", "hex_opcode": "0x4E80AC00", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "01110", "clean": "01110" }, { "raw": "10", "clean": "10" }, { "raw": "0", "clean": "0" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "1010", "clean": "1010" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:12 | 11 | 10 | 9:5 | 4:0" }, "operands": [ { "name": "Vd", "desc": "Destination SIMD/FP vector register" }, { "name": "Vn", "desc": "Unsigned" }, { "name": "Vm", "desc": "Signed" } ], "extension": "FEAT_I8MM (AI)", "description": "Performs an unsigned-signed 8-bit integer matrix multiply-accumulate operation, multiplying unsigned Int8 elements from Vn with signed Int8 elements from Vm and accumulating the results into Vd. This instruction operates on 128-bit NEON vectors and requires the FEAT_I8MM (Advanced SIMD and Floating-point Extension 2) architectural feature. No condition flags are affected; this is an AArch64-only instruction.", "example": "USMMLA v0.4s.T, v1.4s.T, v2.4s.T", "pseudocode": "for e = 0 to (128 / 32) - 1\n Vd[e] ← Vd[e] + (Vn[4×e:4×e+3] × Vm[4×e:4×e+3])\n // Each element is 32-bit int32, products of 4×uint8 × 4×sint8" }, { "mnemonic": "usdot", "architecture": "ARMv8-A", "full_name": "Unsigned-Signed Dot Product (NEON)", "summary": "Dot product of Unsigned Int8 and Signed Int8.", "syntax": "USDOT ., ., .", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "0 | Q | 0 | 01110 | 10 | 0 | Rm | 1 | 0011 | 1 | Rn | Rd", "hex_opcode": "0x0E809C00", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "Q", "clean": "Q" }, { "raw": "0", "clean": "0" }, { "raw": "01110", "clean": "01110" }, { "raw": "10", "clean": "10" }, { "raw": "0", "clean": "0" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "1", "clean": "1" }, { "raw": "0011", "clean": "0011" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15 | 14:11 | 10 | 9:5 | 4:0" }, "operands": [ { "name": "Vd", "desc": "Destination SIMD/FP vector register" }, { "name": "Vn", "desc": "Unsigned" }, { "name": "Vm", "desc": "Signed" } ], "extension": "FEAT_I8MM (AI)", "description": "Performs an unsigned-signed 8-bit integer dot product, multiplying unsigned Int8 elements from Vn with signed Int8 elements from Vm and accumulating into 32-bit integer lanes of Vd. This instruction operates on 128-bit NEON vectors and requires the FEAT_I8MM architectural feature. No condition flags are affected; this is an AArch64-only instruction.", "example": "USDOT v0.4s.T, v1.4s.T, v2.4s.T", "pseudocode": "for e = 0 to (128 / 32) - 1\n Vd[e] ← Vd[e] + (uint(Vn[4×e]) × sint(Vm[4×e]) +\n uint(Vn[4×e+1]) × sint(Vm[4×e+1]) +\n uint(Vn[4×e+2]) × sint(Vm[4×e+2]) +\n uint(Vn[4×e+3]) × sint(Vm[4×e+3]))\n // Each Vd[e] is a 32-bit signed result" }, { "mnemonic": "sudot", "architecture": "ARMv8-A", "full_name": "Signed-Unsigned Dot Product (NEON)", "summary": "Dot product of Signed Int8 and Unsigned Int8 (Indexed).", "syntax": "SUDOT ., ., .[]", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "0 | Q | 0 | 01111 | 0 | 0 | L | M | Rm | 1111 | H | 0 | Rn | Rd", "hex_opcode": "0x0F00F000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "Q", "clean": "Q" }, { "raw": "0", "clean": "0" }, { "raw": "01111", "clean": "01111" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "L", "clean": "L" }, { "raw": "M", "clean": "M" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "1111", "clean": "1111" }, { "raw": "H", "clean": "H" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11 | 10 | 9:5 | 4:0" }, "operands": [ { "name": "Vd", "desc": "Destination SIMD/FP vector register" }, { "name": "Vn", "desc": "Signed" }, { "name": "Vm", "desc": "Unsigned" } ], "extension": "FEAT_I8MM (AI)", "description": "Performs a signed-unsigned 8-bit integer dot product with an indexed operand, multiplying signed Int8 elements from Vn with unsigned Int8 elements from a specific 32-bit lane of Vm and accumulating into 32-bit integer lanes of Vd. This instruction operates on 128-bit NEON vectors and requires the FEAT_I8MM architectural feature. No condition flags are affected; this is an AArch64-only instruction.", "example": "SUDOT v0.4s.T, v1.4s.T, v2.4s.T[index]", "pseudocode": "// Vm is indexed; extract the 32-bit lane containing 4 unsigned Int8 values\nfor e = 0 to (128 / 32) - 1\n lane_data ← Vm[32×index + 0 : 32×index + 31]\n Vd[e] ← Vd[e] + (sint(Vn[4×e]) × uint(lane_data[7:0]) +\n sint(Vn[4×e+1]) × uint(lane_data[15:8]) +\n sint(Vn[4×e+2]) × uint(lane_data[23:16]) +\n sint(Vn[4×e+3]) × uint(lane_data[31:24]))\n // Each Vd[e] is a 32-bit signed result" }, { "mnemonic": "mrrs", "architecture": "ARMv8-A", "full_name": "Move to Two Registers from System Register (128-bit)", "summary": "Reads a 128-bit system register into two general-purpose registers.", "syntax": "MRRS , , ", "encoding": { "format": "System", "binary_pattern": "1101010101 | 1 | 1 | o0 | op1 | CRn | CRm | op2 | Rt", "hex_opcode": "0xD5700000", "visual_parts": [ { "raw": "1101010101", "clean": "1101010101" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "o0", "clean": "o0" }, { "raw": "op1", "clean": "op1" }, { "raw": "CRn", "clean": "CRn" }, { "raw": "CRm", "clean": "CRm" }, { "raw": "op2", "clean": "op2" }, { "raw": "Rt", "clean": "Rt" } ], "bit_positions": "31:22 | 21 | 20 | 19 | 18:16 | 15:12 | 11:8 | 7:5 | 4:0" }, "operands": [ { "name": "Xt", "desc": "Lo" }, { "name": "Xt+1", "desc": "Hi" }, { "name": "sysreg", "desc": "Reg" } ], "extension": "FEAT_SYSREG128", "description": "Reads a 128-bit system register into two consecutive 64-bit general-purpose registers (Xt and Xt+1). This is an AArch64-only instruction requiring FEAT_SYSREG128 and may require elevated privilege depending on the system register being accessed. No condition flags are affected.", "example": "MRRS x3, Xt+1, sysreg", "pseudocode": "Xt ← SYSREG[sysreg][63:0]\nXt+1 ← SYSREG[sysreg][127:64]" }, { "mnemonic": "msrr", "architecture": "ARMv8-A", "full_name": "Move Two Registers to System Register (128-bit)", "summary": "Writes two general-purpose registers into a 128-bit system register.", "syntax": "MSRR , , ", "encoding": { "format": "System", "binary_pattern": "1101010101 | 0 | 1 | o0 | op1 | CRn | CRm | op2 | Rt", "hex_opcode": "0xD5500000", "visual_parts": [ { "raw": "1101010101", "clean": "1101010101" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "o0", "clean": "o0" }, { "raw": "op1", "clean": "op1" }, { "raw": "CRn", "clean": "CRn" }, { "raw": "CRm", "clean": "CRm" }, { "raw": "op2", "clean": "op2" }, { "raw": "Rt", "clean": "Rt" } ], "bit_positions": "31:22 | 21 | 20 | 19 | 18:16 | 15:12 | 11:8 | 7:5 | 4:0" }, "operands": [ { "name": "sysreg", "desc": "Reg" }, { "name": "Xt", "desc": "Lo" }, { "name": "Xt+1", "desc": "Hi" } ], "extension": "FEAT_SYSREG128", "description": "Writes two consecutive 64-bit general-purpose registers (Xt and Xt+1) into a 128-bit system register. This is an AArch64-only instruction requiring FEAT_SYSREG128 and may require elevated privilege depending on the system register being accessed. No condition flags are affected.", "example": "MSRR sysreg, x3, Xt+1", "pseudocode": "SYSREG[sysreg][63:0] ← Xt\nSYSREG[sysreg][127:64] ← Xt+1" }, { "mnemonic": "irg", "architecture": "ARMv8-A", "full_name": "Insert Random Tag", "summary": "Inserts a random Allocation Tag into a pointer (MTE).", "syntax": "IRG , {, }", "encoding": { "format": "Data Processing", "binary_pattern": "1 | 0 | 0 | 11010110 | Xm | 000100 | Xn | Xd", "hex_opcode": "0x9AC01000", "visual_parts": [ { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11010110", "clean": "11010110" }, { "raw": "Xm", "clean": "Xm" }, { "raw": "000100", "clean": "000100" }, { "raw": "Xn", "clean": "Xn" }, { "raw": "Xd", "clean": "Xd" } ], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Xd", "desc": "Dest Ptr" }, { "name": "Xn", "desc": "Src Ptr" }, { "name": "Xm", "desc": "Exclude Mask" } ], "extension": "MTE (Memory Tagging)", "description": "Inserts a randomly selected Allocation Tag into a pointer held in Xn or SP, optionally excluding tags specified by a mask in Xm, and stores the result in Xd or SP. This instruction is only available in AArch64 and requires the MTE (Memory Tagging Extension) feature. The random tag selection is unpredictable from software perspective; no condition flags are affected.", "example": "IRG x0, x1", "pseudocode": "if Xm is not present then\n exclude_mask ← 0x0000000000000000\nelse\n exclude_mask ← Xm\ntag ← random_tag_not_in(exclude_mask)\nXd ← (Xn & ~0xF000000000000000) | (tag << 56)" }, { "mnemonic": "gmi", "architecture": "ARMv8-A", "full_name": "Get Memory Tag Intersection", "summary": "Calculates a mask of excluded tags (MTE).", "syntax": "GMI , , ", "encoding": { "format": "Data Processing", "binary_pattern": "1 | 0 | 0 | 11010110 | Xm | 000101 | Xn | Xd", "hex_opcode": "0x9AC01400", "visual_parts": [ { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11010110", "clean": "11010110" }, { "raw": "Xm", "clean": "Xm" }, { "raw": "000101", "clean": "000101" }, { "raw": "Xn", "clean": "Xn" }, { "raw": "Xd", "clean": "Xd" } ], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Xd", "desc": "Dest Mask" }, { "name": "Xn", "desc": "Ptr" }, { "name": "Xm", "desc": "Excluded" } ], "extension": "MTE (Memory Tagging)", "description": "Calculates the intersection of an Allocation Tag mask (tags excluded from Xm) with tags that are NOT present in the pointer Xn, returning a 16-bit mask of valid alternative tags in Xd. This instruction is only available in AArch64 and requires the MTE feature. No condition flags are affected.", "example": "GMI x0, x1, x2", "pseudocode": "ptr_tag ← (Xn >> 56) & 0xF\nexclude_mask ← Xm & 0xFFFF\nvalid_tags ← ~exclude_mask & 0xFFFF\n// Return mask of tags that are both valid (not excluded) and different from current tag\nXd ← valid_tags & ~(1 << ptr_tag)" }, { "mnemonic": "ldg", "architecture": "ARMv8-A", "full_name": "Load Allocation Tag", "summary": "Loads the Allocation Tag from memory.", "syntax": "LDG , [, #]", "encoding": { "format": "Load/Store", "binary_pattern": "11011001 | 01 | 1 | imm9 | 00 | Xn | Xt", "hex_opcode": "0xD9600000", "visual_parts": [ { "raw": "11011001", "clean": "11011001" }, { "raw": "01", "clean": "01" }, { "raw": "1", "clean": "1" }, { "raw": "imm9", "clean": "imm9" }, { "raw": "00", "clean": "00" }, { "raw": "Xn", "clean": "Xn" }, { "raw": "Xt", "clean": "Xt" } ], "bit_positions": "31:24 | 23:22 | 21 | 20:12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Xt", "desc": "Transfer 64-bit integer register (load/store)" }, { "name": "Xn", "desc": "First source / base 64-bit integer register" }, { "name": "simm", "desc": "Signed immediate offset" } ], "extension": "MTE (Memory Tagging)", "description": "Loads the Allocation Tag from a 16-byte granule in memory at address [Xn + simm] and places it into the tag field (bits [59:56]) of Xt, with the lower 56 bits zeroed. This instruction is only available in AArch64 and requires the MTE feature. The simm9 immediate is scaled by 16 (granule size). No condition flags are affected.", "example": "LDG x3, [x1, #-8]", "pseudocode": "address ← Xn + (simm << 4) // simm is a signed 9-bit value, scaled by 16\nmemory_tag ← load_tag_from_memory(address)\nXt ← (memory_tag << 56) & 0xF000000000000000" }, { "mnemonic": "stg", "architecture": "ARMv8-A", "full_name": "Store Allocation Tag", "summary": "Stores the Allocation Tag to memory.", "syntax": "STG , [, #]", "encoding": { "format": "Load/Store", "binary_pattern": "11011001 | 00 | 1 | imm9 | 01 | Xn | Xt", "hex_opcode": "0xD9200400", "visual_parts": [ { "raw": "11011001", "clean": "11011001" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "imm9", "clean": "imm9" }, { "raw": "01", "clean": "01" }, { "raw": "Xn", "clean": "Xn" }, { "raw": "Xt", "clean": "Xt" } ], "bit_positions": "31:24 | 23:22 | 21 | 20:12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Xt", "desc": "Tag Src" }, { "name": "Xn", "desc": "First source / base 64-bit integer register" }, { "name": "simm", "desc": "Signed immediate offset" } ], "extension": "MTE (Memory Tagging)", "description": "Stores the Allocation Tag from Xt (bits [59:56]) into the tag storage of a 16-byte granule at address [Xn + simm]. This instruction is only available in AArch64 and requires the MTE feature. The simm9 immediate is scaled by 16. Data in the granule is not modified. No condition flags are affected.", "example": "STG Xt, [x1, #-8]", "pseudocode": "address ← Xn + (simm << 4) // simm is a signed 9-bit value, scaled by 16\ntag_to_store ← (Xt >> 56) & 0xF\nstore_tag_to_memory(address, tag_to_store)" }, { "mnemonic": "stzg", "architecture": "ARMv8-A", "full_name": "Store Allocation Tag and Zero", "summary": "Stores the Allocation Tag and zeros the data granule.", "syntax": "STZG , [, #]", "encoding": { "format": "Load/Store", "binary_pattern": "11011001 | 01 | 1 | imm9 | 10 | Xn | Xt", "hex_opcode": "0xD9600800", "visual_parts": [ { "raw": "11011001", "clean": "11011001" }, { "raw": "01", "clean": "01" }, { "raw": "1", "clean": "1" }, { "raw": "imm9", "clean": "imm9" }, { "raw": "10", "clean": "10" }, { "raw": "Xn", "clean": "Xn" }, { "raw": "Xt", "clean": "Xt" } ], "bit_positions": "31:24 | 23:22 | 21 | 20:12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Xt", "desc": "Tag Src" }, { "name": "Xn", "desc": "First source / base 64-bit integer register" }, { "name": "simm", "desc": "Signed immediate offset" } ], "extension": "MTE (Memory Tagging)", "description": "Stores the Allocation Tag from Xt (bits [59:56]) into tag storage at address [Xn + simm] and simultaneously zeros all 16 bytes of the data granule at that address. This instruction is only available in AArch64 and requires the MTE feature. The simm9 immediate is scaled by 16. No condition flags are affected; this is a combined tag-write and memory-zero operation.", "example": "STZG Xt, [x1, #-8]", "pseudocode": "address ← Xn + (simm << 4) // simm is a signed 9-bit value, scaled by 16\ntag_to_store ← (Xt >> 56) & 0xF\nstore_tag_to_memory(address, tag_to_store)\nfor i = 0 to 15\n memory[address + i] ← 0" }, { "mnemonic": "st2g", "architecture": "ARMv8-A", "full_name": "Store Allocation Tag (Two Granules)", "summary": "Stores the Allocation Tag to two memory granules.", "syntax": "ST2G , [, #]", "encoding": { "format": "Load/Store", "binary_pattern": "11011001 | 10 | 1 | imm9 | 10 | Xn | Xt", "hex_opcode": "0xD9A00800", "visual_parts": [ { "raw": "11011001", "clean": "11011001" }, { "raw": "10", "clean": "10" }, { "raw": "1", "clean": "1" }, { "raw": "imm9", "clean": "imm9" }, { "raw": "10", "clean": "10" }, { "raw": "Xn", "clean": "Xn" }, { "raw": "Xt", "clean": "Xt" } ], "bit_positions": "31:24 | 23:22 | 21 | 20:12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Xt", "desc": "Source Tag" }, { "name": "Xn", "desc": "First source / base 64-bit integer register" }, { "name": "simm", "desc": "Signed immediate offset" } ], "extension": "MTE (Memory Tagging)", "description": "Stores the Allocation Tag from Xt to two consecutive 16-byte memory granules at [Xn + offset]. The offset is scaled by 16. Both granules receive the same tag. No condition flags are affected. AArch64-only; requires MTE extension.", "example": "ST2G Xt, [x1, #-8]", "pseudocode": "address ← Xn + (SignExtend(imm9, 9) << 4)\ntag ← GetAllocationTag(Xt)\nmemory[address] ← memory[address] with tag set to tag\nmemory[address + 16] ← memory[address + 16] with tag set to tag" }, { "mnemonic": "stgp", "architecture": "ARMv8-A", "full_name": "Store Allocation Tag and Pair", "summary": "Stores Tag and two 64-bit data values.", "syntax": "STGP , , [, #]", "encoding": { "format": "Load/Store", "binary_pattern": "01 | 101 | 0 | 010 | 0 | simm7 | Xt2 | Xn | Xt", "hex_opcode": "0x69000000", "visual_parts": [ { "raw": "01", "clean": "01" }, { "raw": "101", "clean": "101" }, { "raw": "0", "clean": "0" }, { "raw": "010", "clean": "010" }, { "raw": "0", "clean": "0" }, { "raw": "simm7", "clean": "simm7" }, { "raw": "Xt2", "clean": "Xt2" }, { "raw": "Xn", "clean": "Xn" }, { "raw": "Xt", "clean": "Xt" } ], "bit_positions": "31:30 | 29:27 | 26 | 25:23 | 22 | 21:15 | 14:10 | 9:5 | 4:0" }, "operands": [ { "name": "Xt", "desc": "Data 1" }, { "name": "Xt2", "desc": "Data 2" }, { "name": "Xn", "desc": "First source / base 64-bit integer register" } ], "extension": "MTE (Memory Tagging)", "description": "Stores the Allocation Tag to a 16-byte memory address and simultaneously stores two 64-bit values from Xt and Xt2 (the pair register following Xt). The tag is derived from Xt, and the offset is scaled by 16. This instruction requires MTE support, does not modify the condition flags, and operates only in AArch64 execution state.", "example": "STGP x3, x4, [x1, #-8]", "pseudocode": "address ← (Xn | SP) + (simm7 << 4)\ntag ← Xt[3:0]\nmemory[address:address+7] ← Xt[63:0]\nmemory[address+8:address+15] ← Xt2[63:0]\nmemory[address][3:0] ← tag" }, { "mnemonic": "subp", "architecture": "ARMv8-A", "full_name": "Subtract Pointers", "summary": "Subtracts pointers ignoring Tags.", "syntax": "SUBP , , ", "encoding": { "format": "Data Processing", "binary_pattern": "1 | 0 | 0 | 11010110 | Xm | 000000 | Xn | Xd", "hex_opcode": "0x9AC00000", "visual_parts": [ { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11010110", "clean": "11010110" }, { "raw": "Xm", "clean": "Xm" }, { "raw": "000000", "clean": "000000" }, { "raw": "Xn", "clean": "Xn" }, { "raw": "Xd", "clean": "Xd" } ], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Xd", "desc": "Destination 64-bit integer register" }, { "name": "Xn", "desc": "Ptr 1" }, { "name": "Xm", "desc": "Ptr 2" } ], "extension": "MTE (Memory Tagging)", "description": "Subtracts the pointer in Xm from the pointer in Xn, removing any Allocation Tags from both operands before performing the subtraction. The result is stored in Xd. This instruction does not modify the condition flags and operates only in AArch64 execution state with MTE support.", "example": "SUBP x0, x1, x2", "pseudocode": "Xd ← (Xn | SP)[55:0] - (Xm | SP)[55:0]" }, { "mnemonic": "pacia", "architecture": "ARMv8-A", "full_name": "Pointer Authentication Code (Inst A)", "summary": "Signs a pointer in Xd using Key A and modifier Xm (or SP).", "syntax": "PACIA , ", "encoding": { "format": "Data Processing", "binary_pattern": "1 | 1 | 0 | 11010110 | 00001 | 00 | 0 | 000 | Rn | Rd", "hex_opcode": "0xDAC10000", "visual_parts": [ { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "11010110", "clean": "11010110" }, { "raw": "00001", "clean": "00001" }, { "raw": "00", "clean": "00" }, { "raw": "0", "clean": "0" }, { "raw": "000", "clean": "000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:14 | 13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Xd", "desc": "Ptr" }, { "name": "Xn", "desc": "Modifier" } ], "extension": "PAC (Security)", "description": "Signs the pointer in Xd using the Instruction key A and a modifier from Xn or SP, storing the Pointer Authentication Code (PAC) in the high bits of Xd. The instruction does not modify the condition flags and operates only in AArch64 execution state with PAC support. The operation is implementation-defined; a PACIA PACIASP variant uses SP as the modifier when Xn is omitted.", "example": "PACIA x0, x1", "pseudocode": "modifier ← Xn | SP\nXd ← AddPAC(Xd, modifier, key_a, instruction_key)" }, { "mnemonic": "pacib", "architecture": "ARMv8-A", "full_name": "Pointer Authentication Code (Inst B)", "summary": "Signs a pointer in Xd using Key B.", "syntax": "PACIB , ", "encoding": { "format": "Data Processing", "binary_pattern": "1 | 1 | 0 | 11010110 | 00001 | 00 | 0 | 001 | Rn | Rd", "hex_opcode": "0xDAC10400", "visual_parts": [ { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "11010110", "clean": "11010110" }, { "raw": "00001", "clean": "00001" }, { "raw": "00", "clean": "00" }, { "raw": "0", "clean": "0" }, { "raw": "001", "clean": "001" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:14 | 13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Xd", "desc": "Ptr" }, { "name": "Xn", "desc": "Modifier" } ], "extension": "PAC (Security)", "description": "Signs the pointer in Xd using the Instruction key B and a modifier from Xn or SP, storing the Pointer Authentication Code (PAC) in the high bits of Xd. The instruction does not modify the condition flags and operates only in AArch64 execution state with PAC support. The operation is implementation-defined; a PACIB PACIBSP variant uses SP as the modifier when Xn is omitted.", "example": "PACIB x0, x1", "pseudocode": "modifier ← Xn | SP\nXd ← AddPAC(Xd, modifier, key_b, instruction_key)" }, { "mnemonic": "pacda", "architecture": "ARMv8-A", "full_name": "Pointer Authentication Code (Data A)", "summary": "Signs a data pointer using Key A.", "syntax": "PACDA , ", "encoding": { "format": "Data Processing", "binary_pattern": "1 | 1 | 0 | 11010110 | 00001 | 00 | 0 | 010 | Rn | Rd", "hex_opcode": "0xDAC10800", "visual_parts": [ { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "11010110", "clean": "11010110" }, { "raw": "00001", "clean": "00001" }, { "raw": "00", "clean": "00" }, { "raw": "0", "clean": "0" }, { "raw": "010", "clean": "010" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:14 | 13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Xd", "desc": "Ptr" }, { "name": "Xn", "desc": "Modifier" } ], "extension": "PAC (Security)", "description": "Signs the data pointer in Xd using the Data key A and a modifier from Xn or SP, storing the Pointer Authentication Code (PAC) in the high bits of Xd. The instruction does not modify the condition flags and operates only in AArch64 execution state with PAC support. The operation is implementation-defined and typically used for signing data pointers rather than instruction pointers.", "example": "PACDA x0, x1", "pseudocode": "modifier ← Xn | SP\nXd ← AddPAC(Xd, modifier, key_a, data_key)" }, { "mnemonic": "pacdb", "architecture": "ARMv8-A", "full_name": "Pointer Authentication Code (Data B)", "summary": "Signs a data pointer using Key B.", "syntax": "PACDB , ", "encoding": { "format": "Data Processing", "binary_pattern": "1 | 1 | 0 | 11010110 | 00001 | 00 | 0 | 011 | Rn | Rd", "hex_opcode": "0xDAC10C00", "visual_parts": [ { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "11010110", "clean": "11010110" }, { "raw": "00001", "clean": "00001" }, { "raw": "00", "clean": "00" }, { "raw": "0", "clean": "0" }, { "raw": "011", "clean": "011" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:14 | 13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Xd", "desc": "Ptr" }, { "name": "Xn", "desc": "Modifier" } ], "extension": "PAC (Security)", "description": "Signs the data pointer in Xd using the Data key B and a modifier from Xn or SP, storing the Pointer Authentication Code (PAC) in the high bits of Xd. The instruction does not modify the condition flags and operates only in AArch64 execution state with PAC support. The operation is implementation-defined and typically used for signing data pointers rather than instruction pointers.", "example": "PACDB x0, x1", "pseudocode": "modifier ← Xn | SP\nXd ← AddPAC(Xd, modifier, key_b, data_key)" }, { "mnemonic": "autia", "architecture": "ARMv8-A", "full_name": "Authenticate Code (Inst A)", "summary": "Authenticates a pointer signed with Key A. Corrupts pointer if failed.", "syntax": "AUTIA , ", "encoding": { "format": "Data Processing", "binary_pattern": "1 | 1 | 0 | 11010110 | 00001 | 00 | 0 | 100 | Rn | Rd", "hex_opcode": "0xDAC11000", "visual_parts": [ { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "11010110", "clean": "11010110" }, { "raw": "00001", "clean": "00001" }, { "raw": "00", "clean": "00" }, { "raw": "0", "clean": "0" }, { "raw": "100", "clean": "100" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:14 | 13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Xd", "desc": "Ptr" }, { "name": "Xn", "desc": "Modifier" } ], "extension": "PAC (Security)", "description": "Authenticates a 64-bit pointer in Xd using Key A and a modifier from Xn or SP. If authentication fails, the pointer is corrupted with a known bit pattern. This instruction is AArch64-only and requires the PAC (Pointer Authentication Code) extension. It does not affect the condition flags (N, Z, C, V) but may generate an exception if executed in an inappropriate context.", "example": "AUTIA x0, x1", "pseudocode": "authenticated_pointer ← AuthenticatePointer(Xd, Xn, KeyA)\nif authentication_fails then\n Xd ← corrupted_value\nelse\n Xd ← authenticated_pointer\nend if" }, { "mnemonic": "autib", "architecture": "ARMv8-A", "full_name": "Authenticate Code (Inst B)", "summary": "Authenticates a pointer signed with Key B.", "syntax": "AUTIB , ", "encoding": { "format": "Data Processing", "binary_pattern": "1 | 1 | 0 | 11010110 | 00001 | 00 | 0 | 101 | Rn | Rd", "hex_opcode": "0xDAC11400", "visual_parts": [ { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "11010110", "clean": "11010110" }, { "raw": "00001", "clean": "00001" }, { "raw": "00", "clean": "00" }, { "raw": "0", "clean": "0" }, { "raw": "101", "clean": "101" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:14 | 13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Xd", "desc": "Ptr" }, { "name": "Xn", "desc": "Modifier" } ], "extension": "PAC (Security)", "description": "Authenticates a 64-bit pointer in Xd using Key B and a modifier from Xn or SP. If authentication fails, the pointer is corrupted with a known bit pattern. This instruction is AArch64-only and requires the PAC (Pointer Authentication Code) extension. It does not affect the condition flags (N, Z, C, V) but may generate an exception if executed in an inappropriate context.", "example": "AUTIB x0, x1", "pseudocode": "authenticated_pointer ← AuthenticatePointer(Xd, Xn, KeyB)\nif authentication_fails then\n Xd ← corrupted_value\nelse\n Xd ← authenticated_pointer\nend if" }, { "mnemonic": "xpaci", "architecture": "ARMv8-A", "full_name": "Strip Pointer Authentication Code (Inst)", "summary": "Removes the PAC signature from an instruction pointer.", "syntax": "XPACI ", "encoding": { "format": "Data Processing", "binary_pattern": "1 | 1 | 0 | 11010110 | 00001 | 01000 | 0 | 11111 | Rd", "hex_opcode": "0xDAC143E0", "visual_parts": [ { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "11010110", "clean": "11010110" }, { "raw": "00001", "clean": "00001" }, { "raw": "01000", "clean": "01000" }, { "raw": "0", "clean": "0" }, { "raw": "11111", "clean": "11111" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:11 | 10 | 9:5 | 4:0" }, "operands": [ { "name": "Xd", "desc": "Ptr" } ], "extension": "PAC (Security)", "description": "Strips the Pointer Authentication Code from a 64-bit instruction pointer in Xd without verifying the signature. This instruction is AArch64-only and requires the PAC extension. The condition flags (N, Z, C, V) are not affected, and the operation is not privileged.", "example": "XPACI x0", "pseudocode": "Xd ← StripPAC(Xd, InstructionPointer)" }, { "mnemonic": "xpacd", "architecture": "ARMv8-A", "full_name": "Strip Pointer Authentication Code (Data)", "summary": "Removes the PAC signature from a data pointer.", "syntax": "XPACD ", "encoding": { "format": "Data Processing", "binary_pattern": "1 | 1 | 0 | 11010110 | 00001 | 01000 | 1 | 11111 | Rd", "hex_opcode": "0xDAC147E0", "visual_parts": [ { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "11010110", "clean": "11010110" }, { "raw": "00001", "clean": "00001" }, { "raw": "01000", "clean": "01000" }, { "raw": "1", "clean": "1" }, { "raw": "11111", "clean": "11111" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:11 | 10 | 9:5 | 4:0" }, "operands": [ { "name": "Xd", "desc": "Ptr" } ], "extension": "PAC (Security)", "description": "Strips the Pointer Authentication Code from a 64-bit data pointer in Xd without verifying the signature. This instruction is AArch64-only and requires the PAC extension. The condition flags (N, Z, C, V) are not affected, and the operation is not privileged.", "example": "XPACD x0", "pseudocode": "Xd ← StripPAC(Xd, DataPointer)" }, { "mnemonic": "ldraa", "architecture": "ARMv8-A", "full_name": "Load Register Authenticate (Key A)", "summary": "Loads a value, authenticating the address with Key A.", "syntax": "LDRAA , [, #]", "encoding": { "format": "Load/Store", "binary_pattern": "11 | 111 | 0 | 00 | 0 | S | 1 | imm9 | 0 | 1 | Rn | Rt", "hex_opcode": "0xF8200400", "visual_parts": [ { "raw": "11", "clean": "11" }, { "raw": "111", "clean": "111" }, { "raw": "0", "clean": "0" }, { "raw": "00", "clean": "00" }, { "raw": "0", "clean": "0" }, { "raw": "S", "clean": "S" }, { "raw": "1", "clean": "1" }, { "raw": "imm9", "clean": "imm9" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rt", "clean": "Rt" } ], "bit_positions": "31:30 | 29:27 | 26 | 25:24 | 23 | 22 | 21 | 20:12 | 11 | 10 | 9:5 | 4:0" }, "operands": [ { "name": "Xt", "desc": "Transfer 64-bit integer register (load/store)" }, { "name": "Xn", "desc": "First source / base 64-bit integer register" }, { "name": "simm", "desc": "Signed immediate offset" } ], "extension": "PAC (Security)", "description": "Loads a 64-bit value from memory using an address authenticated with Pointer Authentication Code (PAC) using Key A. The address is computed from a base register and a signed 9-bit immediate offset. This AArch64-only instruction requires PAC support and will generate an Authentication Failure exception if authentication fails; no condition flags are affected.", "example": "LDRAA x3, [x1, #-8]", "pseudocode": "address ← Xn|SP + (simm9 << 3)\nauthenticated_address ← AuthenticateAddressA(address)\nXt ← [authenticated_address]" }, { "mnemonic": "ldrab", "architecture": "ARMv8-A", "full_name": "Load Register Authenticate (Key B)", "summary": "Loads a value, authenticating the address with Key B.", "syntax": "LDRAB , [, #]", "encoding": { "format": "Load/Store", "binary_pattern": "11 | 111 | 0 | 00 | 1 | S | 1 | imm9 | 0 | 1 | Rn | Rt", "hex_opcode": "0xF8A00400", "visual_parts": [ { "raw": "11", "clean": "11" }, { "raw": "111", "clean": "111" }, { "raw": "0", "clean": "0" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "S", "clean": "S" }, { "raw": "1", "clean": "1" }, { "raw": "imm9", "clean": "imm9" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rt", "clean": "Rt" } ], "bit_positions": "31:30 | 29:27 | 26 | 25:24 | 23 | 22 | 21 | 20:12 | 11 | 10 | 9:5 | 4:0" }, "operands": [ { "name": "Xt", "desc": "Transfer 64-bit integer register (load/store)" }, { "name": "Xn", "desc": "First source / base 64-bit integer register" }, { "name": "simm", "desc": "Signed immediate offset" } ], "extension": "PAC (Security)", "description": "Loads a 64-bit value from memory using an address authenticated with Pointer Authentication Code (PAC) using Key B. The address is computed from a base register and a signed 9-bit immediate offset. This AArch64-only instruction requires PAC support and will generate an Authentication Failure exception if authentication fails; no condition flags are affected.", "example": "LDRAB x3, [x1, #-8]", "pseudocode": "address ← Xn|SP + (simm9 << 3)\nauthenticated_address ← AuthenticateAddressB(address)\nXt ← [authenticated_address]" }, { "mnemonic": "bti", "architecture": "ARMv8-A", "full_name": "Branch Target Identification", "summary": "Marks a valid target for indirect branches (Guard against JOP/ROP).", "syntax": "BTI ", "encoding": { "format": "System Hint", "binary_pattern": "11010101000000110010 | 0100 | op2 | 11111", "hex_opcode": "0xD503241F", "visual_parts": [ { "raw": "11010101000000110010", "clean": "11010101000000110010" }, { "raw": "0100", "clean": "0100" }, { "raw": "op2", "clean": "op2" }, { "raw": "11111", "clean": "11111" } ], "bit_positions": "31:12 | 11:8 | 7:5 | 4:0" }, "operands": [ { "name": "target", "desc": "J/C/JC" } ], "extension": "BTI (Security)", "description": "Marks a valid branch target for indirect branch instructions, providing defense against Jump-Oriented Programming (JOP) and Return-Oriented Programming (ROP) attacks. This instruction is AArch64-only and requires the BTI (Branch Target Identification) extension. It does not affect condition flags and acts as a hint; execution continues to the next instruction.", "example": "BTI target", "pseudocode": "if not_valid_branch_target and branch_target_enforcement_enabled then\n GenerateException(BTYPE_mismatch)\nelse\n NOP\nend if" }, { "mnemonic": "rndr", "architecture": "ARMv8-A", "full_name": "Random Number", "summary": "Reads a random number from hardware entropy source.", "syntax": "RNDR ", "encoding": { "format": "System", "binary_pattern": "11010101001 | 00011 | 0011 | 0010 | 010 | Rt", "hex_opcode": "0xD53B2400", "visual_parts": [ { "raw": "11010101001", "clean": "11010101001" }, { "raw": "00011", "clean": "00011" }, { "raw": "0011", "clean": "0011" }, { "raw": "0010", "clean": "0010" }, { "raw": "010", "clean": "010" }, { "raw": "Rt", "clean": "Rt" } ] }, "operands": [ { "name": "Xt", "desc": "Transfer 64-bit integer register (load/store)" } ], "extension": "FEAT_RNG", "description": "Reads a 64-bit random number from the system's hardware entropy source and writes it to Xt. This instruction is AArch64-only and requires the FEAT_RNG extension. It does not modify condition flags and may set the C flag to indicate failure (entropy unavailable), depending on implementation.", "example": "RNDR x3", "pseudocode": "Xt ← HardwareRandomNumber()\nif entropy_available then\n C ← 0\nelse\n C ← 1\nend if" }, { "mnemonic": "rndrrs", "architecture": "ARMv8-A", "full_name": "Random Number Reseed", "summary": "Reads a random number and requests reseed.", "syntax": "RNDRRS ", "encoding": { "format": "System", "binary_pattern": "11010101001 | 00011 | 0011 | 0010 | 011 | Rt", "hex_opcode": "0xD53B2600", "visual_parts": [ { "raw": "11010101001", "clean": "11010101001" }, { "raw": "00011", "clean": "00011" }, { "raw": "0011", "clean": "0011" }, { "raw": "0010", "clean": "0010" }, { "raw": "011", "clean": "011" }, { "raw": "Rt", "clean": "Rt" } ] }, "operands": [ { "name": "Xt", "desc": "Transfer 64-bit integer register (load/store)" } ], "extension": "FEAT_RNG", "description": "Reads a 64-bit random number from the hardware entropy source, writes it to Xt, and requests a reseed of the entropy generator. This instruction is AArch64-only and requires the FEAT_RNG extension. It may set the C flag to indicate entropy availability, similar to RNDR.", "example": "RNDRRS x3", "pseudocode": "Xt ← HardwareRandomNumber()\nRequestReseed(entropy_generator)\nif entropy_available then\n C ← 0\nelse\n C ← 1\nend if" }, { "mnemonic": "cfinv", "architecture": "ARMv8-A", "full_name": "Condition Flag Invert", "summary": "Inverts the C (Carry) flag.", "syntax": "CFINV", "encoding": { "format": "System", "binary_pattern": "1101010100000 | 000 | 0100 | 0000 | 000 | 11111", "hex_opcode": "0xD500401F", "visual_parts": [ { "raw": "1101010100000", "clean": "1101010100000" }, { "raw": "000", "clean": "000" }, { "raw": "0100", "clean": "0100" }, { "raw": "0000", "clean": "0000" }, { "raw": "000", "clean": "000" }, { "raw": "11111", "clean": "11111" } ], "bit_positions": "31:19 | 18:16 | 15:12 | 11:8 | 7:5 | 4:0" }, "operands": [], "extension": "FEAT_FlagM", "description": "Inverts the Carry flag (C) in the condition flags register. This instruction is AArch64-only and requires the FEAT_FlagM extension. All other condition flags (N, Z, V) remain unchanged. The operation is not privileged.", "example": "CFINV", "pseudocode": "C ← NOT C" }, { "mnemonic": "rmif", "architecture": "ARMv8-A", "full_name": "Rotate Mask Insert Flags", "summary": "Rotates a register and inserts bits into the Process State flags.", "syntax": "RMIF , #, #", "encoding": { "format": "Data Processing", "binary_pattern": "1 | 0 | 1 | 11010000 | imm6 | 00001 | Rn | 0 | mask", "hex_opcode": "0xBA000400", "visual_parts": [ { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "11010000", "clean": "11010000" }, { "raw": "imm6", "clean": "imm6" }, { "raw": "00001", "clean": "00001" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "0", "clean": "0" }, { "raw": "mask", "clean": "mask" } ], "bit_positions": "31 | 30 | 29 | 28:21 | 20:15 | 14:10 | 9:5 | 4 | 3:0" }, "operands": [ { "name": "Xn", "desc": "First source / base 64-bit integer register" }, { "name": "shift", "desc": "Rot" }, { "name": "mask", "desc": "Flags" } ], "extension": "FEAT_FlagM", "description": "Rotates the 64-bit value in Xn right by shift bits, then uses the mask to selectively update PSTATE condition flags (N, Z, C, V). Each bit set in mask causes the corresponding rotated bit to update the corresponding flag. AArch64-only; requires FEAT_FlagM. Does not update any other registers.", "example": "RMIF x1, #LSL, #mask", "pseudocode": "rotated ← ROR(Xn, shift); if mask<3> then N ← rotated<63>; if mask<2> then Z ← (rotated == 0); if mask<1> then C ← rotated<0>; if mask<0> then V ← rotated<1>;" }, { "mnemonic": "setf8", "architecture": "ARMv8-A", "full_name": "Set Flags 8-bit", "summary": "Sets PSTATE flags based on 8-bit operand.", "syntax": "SETF8 ", "encoding": { "format": "System", "binary_pattern": "0 | 0 | 1 | 11010000 | 000000 | 0 | 0010 | Rn | 0 | 1101", "hex_opcode": "0x3A00080D", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "11010000", "clean": "11010000" }, { "raw": "000000", "clean": "000000" }, { "raw": "0", "clean": "0" }, { "raw": "0010", "clean": "0010" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "0", "clean": "0" }, { "raw": "1101", "clean": "1101" } ], "bit_positions": "31 | 30 | 29 | 28:21 | 20:15 | 14 | 13:10 | 9:5 | 4 | 3:0" }, "operands": [ { "name": "Wn", "desc": "First source / base 32-bit integer register" } ], "extension": "FEAT_FlagM", "description": "Sets PSTATE condition flags (N, Z, C, V) based on the lower 8 bits of the 32-bit source register Wn, interpreting them as a signed 8-bit value. AArch64-only; requires FEAT_FlagM. N is set if bit 7 of Wn is set; Z is set if the lower 8 bits are zero; C and V are cleared.", "example": "SETF8 w1", "pseudocode": "val8 ← Wn<7:0>; N ← val8<7>; Z ← (val8 == 0); C ← 0; V ← 0;" }, { "mnemonic": "setf16", "architecture": "ARMv8-A", "full_name": "Set Flags 16-bit", "summary": "Sets PSTATE flags based on 16-bit operand.", "syntax": "SETF16 ", "encoding": { "format": "System", "binary_pattern": "0 | 0 | 1 | 11010000 | 000000 | 1 | 0010 | Rn | 0 | 1101", "hex_opcode": "0x3A00480D", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "11010000", "clean": "11010000" }, { "raw": "000000", "clean": "000000" }, { "raw": "1", "clean": "1" }, { "raw": "0010", "clean": "0010" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "0", "clean": "0" }, { "raw": "1101", "clean": "1101" } ], "bit_positions": "31 | 30 | 29 | 28:21 | 20:15 | 14 | 13:10 | 9:5 | 4 | 3:0" }, "operands": [ { "name": "Wn", "desc": "First source / base 32-bit integer register" } ], "extension": "FEAT_FlagM", "description": "Sets PSTATE condition flags (N, Z, C, V) based on the lower 16 bits of the 32-bit source register Wn, interpreting them as a signed 16-bit value. AArch64-only; requires FEAT_FlagM. N is set if bit 15 of Wn is set; Z is set if the lower 16 bits are zero; C and V are cleared.", "example": "SETF16 w1", "pseudocode": "val16 ← Wn<15:0>; N ← val16<15>; Z ← (val16 == 0); C ← 0; V ← 0;" }, { "mnemonic": "fjcvtzs", "architecture": "ARMv8-A", "full_name": "Floating-Point Javascript Convert", "summary": "Converts double to signed 32-bit integer with JS rounding semantics.", "syntax": "FJCVTZS , ", "encoding": { "format": "Float Convert", "binary_pattern": "0 | 0 | 0 | 11110 | 01 | 1 | 11 | 110 | 000000 | Rn | Rd", "hex_opcode": "0x1E7E0000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "01", "clean": "01" }, { "raw": "1", "clean": "1" }, { "raw": "11", "clean": "11" }, { "raw": "110", "clean": "110" }, { "raw": "000000", "clean": "000000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Wd", "desc": "Destination 32-bit integer register" }, { "name": "Dn", "desc": "First source 64-bit SIMD/FP register" } ], "extension": "FEAT_JSCVT", "description": "Converts the 64-bit floating-point value in Dn to a signed 32-bit integer in Wd using JavaScript rounding semantics (round toward zero, with special handling for NaN and out-of-range values). AArch64-only; requires FEAT_JSCVT. Sets the C flag to 1 if the input is out of range or NaN, otherwise clears it. Other flags are not affected.", "example": "FJCVTZS w0, d1", "pseudocode": "if IsNaN(Dn) or (Dn > 2^31 - 1) or (Dn < -2^31) then Wd ← 0; C ← 1; else Wd ← SignedSaturate(RoundTowardZero(Dn), 32); C ← 0;" }, { "mnemonic": "sbfx", "architecture": "ARMv8-A", "full_name": "Signed Bit Field Extract (A32)", "summary": "Extracts bits from a register and sign-extends them.", "syntax": "SBFX , , #, #", "encoding": { "format": "Data Proc", "binary_pattern": "cond | 01111 | 0 | 1 | widthm1 | Rd | lsb | 101 | Rn", "hex_opcode": "0x07A00050", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01111", "clean": "01111" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "widthm1", "clean": "widthm1" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "lsb", "clean": "lsb" }, { "raw": "101", "clean": "101" }, { "raw": "Rn", "clean": "Rn" } ], "bit_positions": "31:28 | 27:23 | 22 | 21 | 20:16 | 15:12 | 11:7 | 6:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "lsb", "desc": "Start Bit" }, { "name": "width", "desc": "Width" } ], "extension": "A32 (Base)", "description": "Extracts a bitfield of width bits starting at position lsb from Rn, sign-extends the extracted value, and writes it to Rd. A32 instruction; available in all A32 processor modes. Does not affect PSTATE flags. The condition code suffix controls execution.", "example": "SBFX r0, r1, #0, #width", "pseudocode": "extracted ← Rn<(lsb + width - 1):lsb>; if extracted<(width - 1)> == 1 then Rd ← SignExtend(extracted, width) else Rd ← ZeroExtend(extracted, width);" }, { "mnemonic": "ubfx", "architecture": "ARMv8-A", "full_name": "Unsigned Bit Field Extract (A32)", "summary": "Extracts bits from a register and zero-extends them.", "syntax": "UBFX , , #, #", "encoding": { "format": "Data Proc", "binary_pattern": "cond | 01111 | 1 | 1 | widthm1 | Rd | lsb | 101 | Rn", "hex_opcode": "0x07E00050", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01111", "clean": "01111" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "widthm1", "clean": "widthm1" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "lsb", "clean": "lsb" }, { "raw": "101", "clean": "101" }, { "raw": "Rn", "clean": "Rn" } ], "bit_positions": "31:28 | 27:23 | 22 | 21 | 20:16 | 15:12 | 11:7 | 6:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "lsb", "desc": "Start Bit" }, { "name": "width", "desc": "Width" } ], "extension": "A32 (Base)", "description": "Extracts a bitfield of width bits starting at position lsb from Rn, zero-extends the extracted value, and writes it to Rd. A32 instruction; available in all A32 processor modes. Does not affect PSTATE flags. The condition code suffix controls execution.", "example": "UBFX r0, r1, #0, #width", "pseudocode": "extracted ← Rn<(lsb + width - 1):lsb>; Rd ← ZeroExtend(extracted, width);" }, { "mnemonic": "sxtb", "architecture": "ARMv8-A", "full_name": "Signed Extend Byte (A32)", "summary": "Sign-extends the low byte (8-bits) to 32-bits.", "syntax": "SXTB , {, }", "encoding": { "format": "Data Proc", "binary_pattern": "cond | 01101 | 0 | 10 | 1111 | Rd | rotate | 0 | 0 | 0111 | Rm", "hex_opcode": "0x06AF0070", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01101", "clean": "01101" }, { "raw": "0", "clean": "0" }, { "raw": "10", "clean": "10" }, { "raw": "1111", "clean": "1111" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "rotate", "clean": "rotate" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0111", "clean": "0111" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (Base)", "description": "Sign-extends the low byte of Rm into the full 32-bit word in Rd, with optional pre-rotation of Rm by 0, 8, 16, or 24 bits. This is an A32 instruction that does not affect any condition flags. The rotation is applied before the sign extension.", "example": "SXTB r0, r2", "pseudocode": "rotated ← ROR(Rm, rotation)\nRd ← SignExtend(rotated[7:0], 32)" }, { "mnemonic": "sxth", "architecture": "ARMv8-A", "full_name": "Signed Extend Halfword (A32)", "summary": "Sign-extends the low halfword (16-bits) to 32-bits.", "syntax": "SXTH , {, }", "encoding": { "format": "Data Proc", "binary_pattern": "cond | 01101 | 0 | 11 | 1111 | Rd | rotate | 0 | 0 | 0111 | Rm", "hex_opcode": "0x06BF0070", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01101", "clean": "01101" }, { "raw": "0", "clean": "0" }, { "raw": "11", "clean": "11" }, { "raw": "1111", "clean": "1111" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "rotate", "clean": "rotate" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0111", "clean": "0111" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (Base)", "description": "Sign-extends the low halfword of Rm into the full 32-bit word in Rd, with optional pre-rotation of Rm by 0, 8, 16, or 24 bits. This is an A32 instruction that does not affect any condition flags. The rotation is applied before the sign extension.", "example": "SXTH r0, r2", "pseudocode": "rotated ← ROR(Rm, rotation)\nRd ← SignExtend(rotated[15:0], 32)" }, { "mnemonic": "sxtb16", "architecture": "ARMv8-A", "full_name": "Signed Extend Byte 16 (A32)", "summary": "Sign-extends two bytes to two halfwords.", "syntax": "SXTB16 , {, }", "encoding": { "format": "Data Proc", "binary_pattern": "cond | 01101 | 0 | 00 | 1111 | Rd | rotate | 0 | 0 | 0111 | Rm", "hex_opcode": "0x068F0070", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01101", "clean": "01101" }, { "raw": "0", "clean": "0" }, { "raw": "00", "clean": "00" }, { "raw": "1111", "clean": "1111" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "rotate", "clean": "rotate" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0111", "clean": "0111" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Sign-extends the two low bytes (bits 7:0 and 15:8) of Rm to two 16-bit halfwords in Rd, with an optional rotation applied to Rm before extraction. A32 instruction; requires DSP extension. Does not affect PSTATE flags. The condition code suffix controls execution.", "example": "SXTB16 r0, r2", "pseudocode": "rotated ← ROR(Rm, rotation); Rd<15:0> ← SignExtend(rotated<7:0>, 16); Rd<31:16> ← SignExtend(rotated<15:8>, 16);" }, { "mnemonic": "uxtb", "architecture": "ARMv8-A", "full_name": "Unsigned Extend Byte (A32)", "summary": "Zero-extends the low byte to 32-bits.", "syntax": "UXTB , {, }", "encoding": { "format": "Data Proc", "binary_pattern": "cond | 01101 | 1 | 10 | 1111 | Rd | rotate | 0 | 0 | 0111 | Rm", "hex_opcode": "0x06EF0070", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01101", "clean": "01101" }, { "raw": "1", "clean": "1" }, { "raw": "10", "clean": "10" }, { "raw": "1111", "clean": "1111" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "rotate", "clean": "rotate" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0111", "clean": "0111" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (Base)", "description": "Zero-extends the low byte (bits [7:0]) of Rm to the full 32-bit width and stores the result in Rd. An optional rotation (0°, 90°, 180°, or 270°) can be applied to Rm before the extension. No condition flags are affected by this instruction. A32 only; executes in User and Privileged modes.", "example": "UXTB r0, r2", "pseudocode": "rotated ← ROR(Rm, rotation * 8)\nRd ← ZeroExtend(rotated[7:0], 32)" }, { "mnemonic": "uxth", "architecture": "ARMv8-A", "full_name": "Unsigned Extend Halfword (A32)", "summary": "Zero-extends the low halfword to 32-bits.", "syntax": "UXTH , {, }", "encoding": { "format": "Data Proc", "binary_pattern": "cond | 01101 | 1 | 11 | 1111 | Rd | rotate | 0 | 0 | 0111 | Rm", "hex_opcode": "0x06FF0070", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01101", "clean": "01101" }, { "raw": "1", "clean": "1" }, { "raw": "11", "clean": "11" }, { "raw": "1111", "clean": "1111" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "rotate", "clean": "rotate" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0111", "clean": "0111" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (Base)", "description": "Zero-extends the low halfword (bits [15:0]) of Rm to the full 32-bit width and stores the result in Rd. An optional rotation (0°, 90°, 180°, or 270°) can be applied to Rm before the extension. No condition flags are affected by this instruction. A32 only; executes in User and Privileged modes.", "example": "UXTH r0, r2", "pseudocode": "rotated ← ROR(Rm, rotation * 8)\nRd ← ZeroExtend(rotated[15:0], 32)" }, { "mnemonic": "uxtb16", "architecture": "ARMv8-A", "full_name": "Unsigned Extend Byte 16 (A32)", "summary": "Zero-extends two bytes to two halfwords.", "syntax": "UXTB16 , {, }", "encoding": { "format": "Data Proc", "binary_pattern": "cond | 01101 | 1 | 00 | 1111 | Rd | rotate | 0 | 0 | 0111 | Rm", "hex_opcode": "0x06CF0070", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01101", "clean": "01101" }, { "raw": "1", "clean": "1" }, { "raw": "00", "clean": "00" }, { "raw": "1111", "clean": "1111" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "rotate", "clean": "rotate" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0111", "clean": "0111" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Zero-extends the two low bytes (bits 7:0 and 15:8) of Rm to two 16-bit halfwords in Rd, with an optional rotation applied to Rm before extraction. A32 instruction; requires DSP extension. Does not affect PSTATE flags. The condition code suffix controls execution.", "example": "UXTB16 r0, r2", "pseudocode": "rotated ← ROR(Rm, rotation); Rd<15:0> ← ZeroExtend(rotated<7:0>, 16); Rd<31:16> ← ZeroExtend(rotated<15:8>, 16);" }, { "mnemonic": "ssat", "architecture": "ARMv8-A", "full_name": "Signed Saturate (A32)", "summary": "Saturates a signed value to a specified bit width.", "syntax": "SSAT , #, {, }", "encoding": { "format": "Data Proc", "binary_pattern": "cond | 01101 | 0 | 1 | sat_imm | Rd | imm5 | 0 | 01 | Rn", "hex_opcode": "0x06A00010", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01101", "clean": "01101" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "sat_imm", "clean": "sat_imm" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "imm5", "clean": "imm5" }, { "raw": "0", "clean": "0" }, { "raw": "01", "clean": "01" }, { "raw": "Rn", "clean": "Rn" } ], "bit_positions": "31:28 | 27:23 | 22 | 21 | 20:16 | 15:12 | 11:7 | 6 | 5:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "imm", "desc": "Bit Position" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Saturates a signed integer to a specified bit width. The instruction shifts the source value by an optional amount, then saturates the result to a signed range defined by the saturation position. Sets the Q flag if saturation occurs; N, Z, C, V flags are unaffected. A32-only instruction requiring DSP extension.", "example": "SSAT r0, #16, r2", "pseudocode": "shifted ← Rm << shift_amount\nsat_range ← 2^(imm-1) - 1\nif shifted > sat_range then\n Rd ← sat_range\n Q ← 1\nelse if shifted < -(2^(imm-1)) then\n Rd ← -(2^(imm-1))\n Q ← 1\nelse\n Rd ← shifted" }, { "mnemonic": "usat", "architecture": "ARMv8-A", "full_name": "Unsigned Saturate (A32)", "summary": "Saturates an unsigned value to a specified bit width.", "syntax": "USAT , #, {, }", "encoding": { "format": "Data Proc", "binary_pattern": "cond | 01101 | 1 | 1 | sat_imm | Rd | imm5 | 0 | 01 | Rn", "hex_opcode": "0x06E00010", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01101", "clean": "01101" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "sat_imm", "clean": "sat_imm" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "imm5", "clean": "imm5" }, { "raw": "0", "clean": "0" }, { "raw": "01", "clean": "01" }, { "raw": "Rn", "clean": "Rn" } ], "bit_positions": "31:28 | 27:23 | 22 | 21 | 20:16 | 15:12 | 11:7 | 6 | 5:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "imm", "desc": "Bit Position" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Saturates an unsigned integer to a specified bit width. The instruction shifts the source value by an optional amount, then saturates the result to an unsigned range [0, 2^imm-1]. Sets the Q flag if saturation occurs; N, Z, C, V flags are unaffected. A32-only instruction requiring DSP extension.", "example": "USAT r0, #16, r2", "pseudocode": "shifted ← Rm << shift_amount\nsat_max ← 2^imm - 1\nif shifted > sat_max then\n Rd ← sat_max\n Q ← 1\nelse if shifted < 0 then\n Rd ← 0\n Q ← 1\nelse\n Rd ← shifted" }, { "mnemonic": "ssat16", "architecture": "ARMv8-A", "full_name": "Signed Saturate 16 (A32)", "summary": "Saturates two signed 16-bit values.", "syntax": "SSAT16 , #, ", "encoding": { "format": "Data Proc", "binary_pattern": "cond | 01101 | 0 | 10 | sat_imm | Rd | 1 | 1 | 1 | 1 | 0011 | Rn", "hex_opcode": "0x06A00F30", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01101", "clean": "01101" }, { "raw": "0", "clean": "0" }, { "raw": "10", "clean": "10" }, { "raw": "sat_imm", "clean": "sat_imm" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0011", "clean": "0011" }, { "raw": "Rn", "clean": "Rn" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "imm", "desc": "Bit Position" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Saturates two signed 16-bit halfword values packed in a register to a specified bit width. The upper and lower 16-bit values are independently saturated to the range [-(2^(imm-1)), 2^(imm-1)-1]. Sets the Q flag if either halfword saturates; N, Z, C, V flags are unaffected. A32-only instruction requiring DSP extension.", "example": "SSAT16 r0, #16, r2", "pseudocode": "lower_hw ← Rm[15:0] (signed)\nupper_hw ← Rm[31:16] (signed)\nsat_range ← 2^(imm-1) - 1\nsat_min ← -(2^(imm-1))\nif lower_hw > sat_range or lower_hw < sat_min then\n Rd[15:0] ← Clamp(lower_hw, sat_min, sat_range)\n Q ← 1\nelse\n Rd[15:0] ← lower_hw\nif upper_hw > sat_range or upper_hw < sat_min then\n Rd[31:16] ← Clamp(upper_hw, sat_min, sat_range)\n Q ← 1\nelse\n Rd[31:16] ← upper_hw" }, { "mnemonic": "usat16", "architecture": "ARMv8-A", "full_name": "Unsigned Saturate 16 (A32)", "summary": "Saturates two unsigned 16-bit values.", "syntax": "USAT16 , #, ", "encoding": { "format": "Data Proc", "binary_pattern": "cond | 01101 | 1 | 10 | sat_imm | Rd | 1 | 1 | 1 | 1 | 0011 | Rn", "hex_opcode": "0x06E00F30", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01101", "clean": "01101" }, { "raw": "1", "clean": "1" }, { "raw": "10", "clean": "10" }, { "raw": "sat_imm", "clean": "sat_imm" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0011", "clean": "0011" }, { "raw": "Rn", "clean": "Rn" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "imm", "desc": "Bit Position" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Saturates two unsigned 16-bit halfword values packed in a register to a specified bit width. The upper and lower 16-bit values are independently saturated to the range [0, 2^imm-1]. Sets the Q flag if either halfword saturates; N, Z, C, V flags are unaffected. A32-only instruction requiring DSP extension.", "example": "USAT16 r0, #16, r2", "pseudocode": "lower_hw ← Rm[15:0] (unsigned)\nupper_hw ← Rm[31:16] (unsigned)\nsat_max ← 2^imm - 1\nif lower_hw > sat_max then\n Rd[15:0] ← sat_max\n Q ← 1\nelse\n Rd[15:0] ← lower_hw\nif upper_hw > sat_max then\n Rd[31:16] ← sat_max\n Q ← 1\nelse\n Rd[31:16] ← upper_hw" }, { "mnemonic": "pkhbt", "architecture": "ARMv8-A", "full_name": "Pack Halfword Bottom Top", "summary": "Combines bottom half of Rn with top half of shifted Rm.", "syntax": "PKHBT , , {, LSL #}", "encoding": { "format": "Data Proc", "binary_pattern": "cond | 01101000 | Rn | Rd | imm5 | 0 | 01 | Rm", "hex_opcode": "0x06800010", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01101000", "clean": "01101000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "imm5", "clean": "imm5" }, { "raw": "0", "clean": "0" }, { "raw": "01", "clean": "01" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:20 | 19:16 | 15:12 | 11:7 | 6 | 5:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "Bottom Src" }, { "name": "Rm", "desc": "Top Src" } ], "extension": "A32 (DSP)", "description": "Packs the bottom halfword of Rn with the top halfword of (Rm shifted left). Assembles a 32-bit result by taking bits [15:0] from Rn and bits [31:16] from the shifted Rm. Condition flags N, Z, C, V are unaffected. A32-only instruction requiring DSP extension.", "example": "PKHBT r0, r1, r2", "pseudocode": "Rd[15:0] ← Rn[15:0]\nshifted_rm ← Rm << shift_imm\nRd[31:16] ← shifted_rm[31:16]" }, { "mnemonic": "pkhtb", "architecture": "ARMv8-A", "full_name": "Pack Halfword Top Bottom", "summary": "Combines top half of Rn with bottom half of shifted Rm.", "syntax": "PKHTB , , {, ASR #}", "encoding": { "format": "Data Proc", "binary_pattern": "cond | 01101000 | Rn | Rd | imm5 | 1 | 01 | Rm", "hex_opcode": "0x06800050", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01101000", "clean": "01101000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "imm5", "clean": "imm5" }, { "raw": "1", "clean": "1" }, { "raw": "01", "clean": "01" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:20 | 19:16 | 15:12 | 11:7 | 6 | 5:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "Top Src" }, { "name": "Rm", "desc": "Bottom Src" } ], "extension": "A32 (DSP)", "description": "Packs the top halfword of Rn with the bottom halfword of (Rm shifted right). Assembles a 32-bit result by taking bits [31:16] from Rn and bits [15:0] from the shifted Rm. Condition flags N, Z, C, V are unaffected. A32-only instruction requiring DSP extension.", "example": "PKHTB r0, r1, r2", "pseudocode": "shifted_rm ← Rm >> shift_imm\nRd[15:0] ← shifted_rm[15:0]\nRd[31:16] ← Rn[31:16]" }, { "mnemonic": "sadd16", "architecture": "ARMv8-A", "full_name": "Signed Add 16 (A32)", "summary": "Parallel add of two signed 16-bit halfwords.", "syntax": "SADD16 , , ", "encoding": { "format": "SIMD Integer", "binary_pattern": "cond | 01100 | 001 | Rn | Rd | 1 | 1 | 1 | 1 | 0 | 00 | 1 | Rm", "hex_opcode": "0x06100F10", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01100", "clean": "01100" }, { "raw": "001", "clean": "001" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Performs two independent parallel signed 16-bit additions: the high halfword of Rn is added to the high halfword of Rm, and the low halfword of Rn is added to the low halfword of Rm; results are stored in the corresponding halfwords of Rd. The CPSR GE[3:0] flags are updated to reflect signed overflow in each halfword; N, Z, C, V are unaffected. A32 only; requires DSP extension; executes in User and Privileged modes.", "example": "SADD16 r0, r1, r2", "pseudocode": "Rd[31:16] ← Rn[31:16] + Rm[31:16]\nRd[15:0] ← Rn[15:0] + Rm[15:0]\nGE[3] ← (Rd[31:16] >= 0) ? 1 : 0\nGE[2] ← (Rd[31:16] < 0) ? 0 : 1\nGE[1] ← (Rd[15:0] >= 0) ? 1 : 0\nGE[0] ← (Rd[15:0] < 0) ? 0 : 1" }, { "mnemonic": "uadd16", "architecture": "ARMv8-A", "full_name": "Unsigned Add 16 (A32)", "summary": "Parallel add of two unsigned 16-bit halfwords.", "syntax": "UADD16 , , ", "encoding": { "format": "SIMD Integer", "binary_pattern": "cond | 01100 | 101 | Rn | Rd | 1 | 1 | 1 | 1 | 0 | 00 | 1 | Rm", "hex_opcode": "0x06500F10", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01100", "clean": "01100" }, { "raw": "101", "clean": "101" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Performs two independent parallel unsigned 16-bit additions: the high halfword of Rn is added to the high halfword of Rm, and the low halfword of Rn is added to the low halfword of Rm; results are stored in the corresponding halfwords of Rd. The CPSR GE[3:0] flags are updated to reflect unsigned overflow (carry-out) in each halfword; N, Z, C, V are unaffected. A32 only; requires DSP extension; executes in User and Privileged modes.", "example": "UADD16 r0, r1, r2", "pseudocode": "Rd[31:16] ← Rn[31:16] + Rm[31:16]\nRd[15:0] ← Rn[15:0] + Rm[15:0]\nGE[3] ← (Rn[31:16] + Rm[31:16] < 2^16) ? 0 : 1\nGE[2] ← (Rn[31:16] + Rm[31:16] < 2^16) ? 1 : 0\nGE[1] ← (Rn[15:0] + Rm[15:0] < 2^16) ? 0 : 1\nGE[0] ← (Rn[15:0] + Rm[15:0] < 2^16) ? 1 : 0" }, { "mnemonic": "sadd8", "architecture": "ARMv8-A", "full_name": "Signed Add 8 (A32)", "summary": "Parallel add of four signed 8-bit bytes.", "syntax": "SADD8 , , ", "encoding": { "format": "SIMD Integer", "binary_pattern": "cond | 01100 | 001 | Rn | Rd | 1 | 1 | 1 | 1 | 1 | 00 | 1 | Rm", "hex_opcode": "0x06100F90", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01100", "clean": "01100" }, { "raw": "001", "clean": "001" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Performs four independent parallel signed 8-bit additions, one for each byte of Rn and Rm; results are stored in the corresponding bytes of Rd. The CPSR GE[3:0] flags are updated to reflect signed overflow in each byte; N, Z, C, V are unaffected. A32 only; requires DSP extension; executes in User and Privileged modes.", "example": "SADD8 r0, r1, r2", "pseudocode": "Rd[31:24] ← Rn[31:24] + Rm[31:24]\nRd[23:16] ← Rn[23:16] + Rm[23:16]\nRd[15:8] ← Rn[15:8] + Rm[15:8]\nRd[7:0] ← Rn[7:0] + Rm[7:0]\nfor i = 0 to 3:\n GE[i] ← (Rd[i*8+7:i*8] >= 0) ? 1 : 0" }, { "mnemonic": "uadd8", "architecture": "ARMv8-A", "full_name": "Unsigned Add 8 (A32)", "summary": "Parallel add of four unsigned 8-bit bytes.", "syntax": "UADD8 , , ", "encoding": { "format": "SIMD Integer", "binary_pattern": "cond | 01100 | 101 | Rn | Rd | 1 | 1 | 1 | 1 | 1 | 00 | 1 | Rm", "hex_opcode": "0x06500F90", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01100", "clean": "01100" }, { "raw": "101", "clean": "101" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Performs four independent parallel unsigned 8-bit additions, one for each byte of Rn and Rm; results are stored in the corresponding bytes of Rd. The CPSR GE[3:0] flags are updated to reflect unsigned overflow (carry-out) in each byte; N, Z, C, V are unaffected. A32 only; requires DSP extension; executes in User and Privileged modes.", "example": "UADD8 r0, r1, r2", "pseudocode": "Rd[31:24] ← Rn[31:24] + Rm[31:24]\nRd[23:16] ← Rn[23:16] + Rm[23:16]\nRd[15:8] ← Rn[15:8] + Rm[15:8]\nRd[7:0] ← Rn[7:0] + Rm[7:0]\nfor i = 0 to 3:\n GE[i] ← (Rn[i*8+7:i*8] + Rm[i*8+7:i*8] < 2^8) ? 0 : 1" }, { "mnemonic": "ssub16", "architecture": "ARMv8-A", "full_name": "Signed Subtract 16 (A32)", "summary": "Parallel sub of two signed 16-bit halfwords.", "syntax": "SSUB16 , , ", "encoding": { "format": "SIMD Integer", "binary_pattern": "cond | 01100 | 001 | Rn | Rd | 1 | 1 | 1 | 1 | 0 | 11 | 1 | Rm", "hex_opcode": "0x06100F70", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01100", "clean": "01100" }, { "raw": "001", "clean": "001" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "11", "clean": "11" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Performs two independent parallel signed 16-bit subtractions: the high halfword of Rm is subtracted from the high halfword of Rn, and the low halfword of Rm is subtracted from the low halfword of Rn; results are stored in the corresponding halfwords of Rd. The CPSR GE[3:0] flags are updated to reflect signed borrow in each halfword; N, Z, C, V are unaffected. A32 only; requires DSP extension; executes in User and Privileged modes.", "example": "SSUB16 r0, r1, r2", "pseudocode": "Rd[31:16] ← Rn[31:16] - Rm[31:16]\nRd[15:0] ← Rn[15:0] - Rm[15:0]\nGE[3] ← (Rd[31:16] >= 0) ? 1 : 0\nGE[2] ← (Rd[31:16] < 0) ? 0 : 1\nGE[1] ← (Rd[15:0] >= 0) ? 1 : 0\nGE[0] ← (Rd[15:0] < 0) ? 0 : 1" }, { "mnemonic": "usub16", "architecture": "ARMv8-A", "full_name": "Unsigned Subtract 16 (A32)", "summary": "Parallel sub of two unsigned 16-bit halfwords.", "syntax": "USUB16 , , ", "encoding": { "format": "SIMD Integer", "binary_pattern": "cond | 01100 | 101 | Rn | Rd | 1 | 1 | 1 | 1 | 0 | 11 | 1 | Rm", "hex_opcode": "0x06500F70", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01100", "clean": "01100" }, { "raw": "101", "clean": "101" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "11", "clean": "11" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Performs two independent parallel unsigned 16-bit subtractions: the high halfword of Rm is subtracted from the high halfword of Rn, and the low halfword of Rm is subtracted from the low halfword of Rn; results are stored in the corresponding halfwords of Rd. The CPSR GE[3:0] flags are updated to reflect unsigned borrow (no carry-out) in each halfword; N, Z, C, V are unaffected. A32 only; requires DSP extension; executes in User and Privileged modes.", "example": "USUB16 r0, r1, r2", "pseudocode": "Rd[31:16] ← Rn[31:16] - Rm[31:16]\nRd[15:0] ← Rn[15:0] - Rm[15:0]\nGE[3] ← (Rn[31:16] >= Rm[31:16]) ? 1 : 0\nGE[2] ← (Rn[31:16] >= Rm[31:16]) ? 0 : 1\nGE[1] ← (Rn[15:0] >= Rm[15:0]) ? 1 : 0\nGE[0] ← (Rn[15:0] >= Rm[15:0]) ? 0 : 1" }, { "mnemonic": "usad8", "architecture": "ARMv8-A", "full_name": "Unsigned Sum of Absolute Differences", "summary": "Computes sum of absolute differences of bytes (Video Codec).", "syntax": "USAD8 , , ", "encoding": { "format": "SIMD Integer", "binary_pattern": "cond | 01111000 | Rd | 1111 | Rm | 0001 | Rn", "hex_opcode": "0x0780F010", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01111000", "clean": "01111000" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1111", "clean": "1111" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "0001", "clean": "0001" }, { "raw": "Rn", "clean": "Rn" } ], "bit_positions": "31:28 | 27:20 | 19:16 | 15:12 | 11:8 | 7:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Computes the unsigned sum of absolute differences of four byte-wide values. Treats Rn and Rm as four unsigned bytes each, computes the absolute difference for each byte pair, sums them, and stores the result in Rd. Condition flags N, Z, C, V are unaffected. A32-only instruction requiring DSP extension; commonly used in video codec applications.", "example": "USAD8 r0, r1, r2", "pseudocode": "diff0 ← |Rn[7:0] - Rm[7:0]|\ndiff1 ← |Rn[15:8] - Rm[15:8]|\ndiff2 ← |Rn[23:16] - Rm[23:16]|\ndiff3 ← |Rn[31:24] - Rm[31:24]|\nRd ← diff0 + diff1 + diff2 + diff3" }, { "mnemonic": "usada8", "architecture": "ARMv8-A", "full_name": "Unsigned Sum of Absolute Differences Accumulate", "summary": "USAD8 plus accumulator.", "syntax": "USADA8 , , , ", "encoding": { "format": "SIMD Integer", "binary_pattern": "cond | 01111000 | Rd | Ra | Rm | 0001 | Rn", "hex_opcode": "0x07800010", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01111000", "clean": "01111000" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "Ra", "clean": "Ra" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "0001", "clean": "0001" }, { "raw": "Rn", "clean": "Rn" } ], "bit_positions": "31:28 | 27:20 | 19:16 | 15:12 | 11:8 | 7:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" }, { "name": "Ra", "desc": "Acc" } ], "extension": "A32 (DSP)", "description": "Computes the unsigned sum of absolute differences of four byte-wide values and adds an accumulator. Treats Rn and Rm as four unsigned bytes each, computes absolute differences for each byte pair, sums them, and adds the value in Ra to produce the result stored in Rd. Condition flags N, Z, C, V are unaffected. A32-only instruction requiring DSP extension.", "example": "USADA8 r0, r1, r2, r5", "pseudocode": "diff0 ← |Rn[7:0] - Rm[7:0]|\ndiff1 ← |Rn[15:8] - Rm[15:8]|\ndiff2 ← |Rn[23:16] - Rm[23:16]|\ndiff3 ← |Rn[31:24] - Rm[31:24]|\nRd ← (diff0 + diff1 + diff2 + diff3) + Ra" }, { "mnemonic": "smmul", "architecture": "ARMv8-A", "full_name": "Signed Most Significant Word Multiply", "summary": "Multiplies and returns the top 32-bits of the 64-bit result.", "syntax": "SMMUL{R} , , ", "encoding": { "format": "Multiply", "binary_pattern": "cond | 01110 | 101 | Rd | 1111 | Rm | 00 | 0 | 1 | Rn", "hex_opcode": "0x0750F010", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01110", "clean": "01110" }, { "raw": "101", "clean": "101" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1111", "clean": "1111" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "00", "clean": "00" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" } ], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11:8 | 7:6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Signed Most Significant Word Multiply performs a signed 32×32-bit multiply and returns the upper 32 bits of the 64-bit result in Rd. This is commonly used for fixed-point arithmetic and fast DSP operations. No condition flags are affected. Available in A32 instruction set with DSP extension; the optional R suffix rounds the result by adding 0x80000000 before truncation.", "example": "SMMUL r0, r1, r2", "pseudocode": "product ← SignedMul(Rn, Rm)\nRd ← (product[63:32])" }, { "mnemonic": "smmla", "architecture": "ARMv8-A", "full_name": "Signed Most Significant Word Multiply Accumulate", "summary": "SMMUL + Accumulate.", "syntax": "SMMLA{R} , , , ", "encoding": { "format": "Multiply", "binary_pattern": "cond | 01110 | 101 | Rd | Ra | Rm | 00 | 0 | 1 | Rn", "hex_opcode": "0x07500010", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01110", "clean": "01110" }, { "raw": "101", "clean": "101" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "Ra", "clean": "Ra" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "00", "clean": "00" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" } ], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11:8 | 7:6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" }, { "name": "Ra", "desc": "Acc" } ], "extension": "A32 (DSP)", "description": "Signed Most Significant Word Multiply Accumulate computes the signed product of Rn and Rm, extracts the upper 32 bits, and adds the accumulator register Ra to produce the final result stored in Rd. This combines multiplication and accumulation in a single instruction, useful for DSP and filtering operations. No condition flags are affected. Available in A32 instruction set with DSP extension; the optional R suffix applies rounding.", "example": "SMMLA r0, r1, r2, r5", "pseudocode": "product ← SignedMul(Rn, Rm)\nRd ← Ra + (product[63:32])" }, { "mnemonic": "vadd", "architecture": "ARMv8-A", "full_name": "Vector Add (VFP)", "summary": "Adds two floating-point values.", "syntax": "VADD.F32 , , ", "encoding": { "format": "VFP Arith", "binary_pattern": "cond | 1110 | 0 | D | 11 | Vn | Vd | 10 | 10 | N | 0 | M | 0 | Vm", "hex_opcode": "0x0E300A00", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "1110", "clean": "1110" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:28 | 27:24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" }, { "name": "Sn", "desc": "First source 32-bit floating-point register" }, { "name": "Sm", "desc": "Second source 32-bit floating-point register" } ], "extension": "VFP (Float)", "description": "Adds two single-precision floating-point values (Sn + Sm) and stores the result in Sd. This VFP instruction operates on 32-bit IEEE 754 single-precision operands. The condition flags (N, Z, C, V) are updated based on the floating-point result according to the FPSCR. Execution is conditional based on the condition code and requires VFP extension support in A32/T32 modes.", "example": "VADD.F32 s0, s1, s2", "pseudocode": "Sd ← Sn + Sm\nFPSCR.NZCV ← FP_CC(result)" }, { "mnemonic": "vadd", "architecture": "ARMv8-A", "full_name": "Vector Add Double (VFP)", "summary": "Adds two double-precision floating-point values.", "syntax": "VADD.F64
, , ", "encoding": { "format": "VFP Arith", "binary_pattern": "cond | 1110 | 0 | D | 11 | Vn | Vd | 10 | 11 | N | 0 | M | 0 | Vm", "hex_opcode": "0x0E300B00", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "1110", "clean": "1110" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "11", "clean": "11" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:28 | 27:24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Dd", "desc": "Destination 64-bit SIMD/FP register" }, { "name": "Dn", "desc": "First source 64-bit SIMD/FP register" }, { "name": "Dm", "desc": "Second source 64-bit SIMD/FP register" } ], "extension": "VFP (Float)", "description": "Adds two double-precision floating-point values (Dn + Dm) and stores the result in Dd. This VFP instruction operates on 64-bit IEEE 754 double-precision operands. The condition flags (N, Z, C, V) are updated based on the floating-point result according to the FPSCR. Execution is conditional based on the condition code and requires VFP extension support in A32/T32 modes.", "example": "VADD.F64 d0, d1, d2", "pseudocode": "Dd ← Dn + Dm\nFPSCR.NZCV ← FP_CC(result)" }, { "mnemonic": "vsub", "architecture": "ARMv8-A", "full_name": "Vector Subtract (VFP)", "summary": "Subtracts two floating-point values.", "syntax": "VSUB.F32 , , ", "encoding": { "format": "VFP Arith", "binary_pattern": "cond | 1110 | 0 | D | 11 | Vn | Vd | 10 | 10 | N | 1 | M | 0 | Vm", "hex_opcode": "0x0E300A40", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "1110", "clean": "1110" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "N", "clean": "N" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:28 | 27:24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" }, { "name": "Sn", "desc": "First source 32-bit floating-point register" }, { "name": "Sm", "desc": "Second source 32-bit floating-point register" } ], "extension": "VFP (Float)", "description": "Subtracts two single-precision floating-point values (Sn - Sm) and stores the result in Sd. This VFP instruction operates on 32-bit IEEE 754 single-precision operands. The condition flags (N, Z, C, V) are updated based on the floating-point result according to the FPSCR. Execution is conditional based on the condition code and requires VFP extension support in A32/T32 modes.", "example": "VSUB.F32 s0, s1, s2", "pseudocode": "Sd ← Sn - Sm\nFPSCR.NZCV ← FP_CC(result)" }, { "mnemonic": "vmul", "architecture": "ARMv8-A", "full_name": "Vector Multiply (VFP)", "summary": "Multiplies two floating-point values.", "syntax": "VMUL.F32 , , ", "encoding": { "format": "VFP Arith", "binary_pattern": "cond | 1110 | 0 | D | 10 | Vn | Vd | 10 | 10 | N | 0 | M | 0 | Vm", "hex_opcode": "0x0E200A00", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "1110", "clean": "1110" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "10", "clean": "10" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:28 | 27:24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" }, { "name": "Sn", "desc": "First source 32-bit floating-point register" }, { "name": "Sm", "desc": "Second source 32-bit floating-point register" } ], "extension": "VFP (Float)", "description": "Vector Multiply (VFP) performs single-precision floating-point multiplication of Sn and Sm, storing the result in Sd. The operation follows IEEE 754 semantics, updating the FPSCR exception flags (IXC, OFC, UFC, IOC, DZC) based on the result but not affecting the ARM condition flags N, Z, C, V. Available in A32/T32 with VFP extension; execution is conditional based on the condition code suffix.", "example": "VMUL.F32 s0, s1, s2", "pseudocode": "Sd ← FP_Multiply(Sn, Sm)\nFPSCR ← updated with floating-point exception flags" }, { "mnemonic": "vdiv", "architecture": "ARMv8-A", "full_name": "Vector Divide (VFP)", "summary": "Divides two floating-point values.", "syntax": "VDIV.F32 , , ", "encoding": { "format": "VFP Arith", "binary_pattern": "cond | 1110 | 1 | D | 00 | Vn | Vd | 10 | 10 | N | 0 | M | 0 | Vm", "hex_opcode": "0x0E800A00", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "1110", "clean": "1110" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "00", "clean": "00" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:28 | 27:24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" }, { "name": "Sn", "desc": "Dividend" }, { "name": "Sm", "desc": "Divisor" } ], "extension": "VFP (Float)", "description": "Divides two single-precision floating-point values (Sn / Sm) and stores the result in Sd. This VFP instruction performs floating-point division on 32-bit IEEE 754 single-precision operands. The condition flags (N, Z, C, V) are updated based on the floating-point result according to the FPSCR; division by zero generates a floating-point exception or returns infinity depending on exception settings. Execution is conditional based on the condition code and requires VFP extension support in A32/T32 modes.", "example": "VDIV.F32 s0, s1, s2", "pseudocode": "Sd ← Sn / Sm\nFPSCR.NZCV ← FP_CC(result)\nif (Sm == 0.0) then FP_Exception(DivideByZero)" }, { "mnemonic": "vmla", "architecture": "ARMv8-A", "full_name": "Vector Multiply Accumulate (VFP)", "summary": "Sd = Sd + (Sn * Sm).", "syntax": "VMLA.F32 , , ", "encoding": { "format": "VFP Arith", "binary_pattern": "cond | 1110 | 0 | D | 00 | Vn | Vd | 10 | 10 | N | 0 | M | 0 | Vm", "hex_opcode": "0x0E000A00", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "1110", "clean": "1110" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "00", "clean": "00" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:28 | 27:24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Sd", "desc": "Dest/Acc" }, { "name": "Sn", "desc": "First source 32-bit floating-point register" }, { "name": "Sm", "desc": "Second source 32-bit floating-point register" } ], "extension": "VFP (Float)", "description": "Vector Multiply Accumulate (VFP) computes Sn × Sm and adds the result to Sd, storing the final value back in Sd. The operation follows IEEE 754 semantics with rounding and exception handling controlled by FPSCR, updating floating-point exception flags but not ARM condition flags. Available in A32/T32 with VFP extension; execution is conditional based on the condition code suffix.", "example": "VMLA.F32 s0, s1, s2", "pseudocode": "product ← FP_Multiply(Sn, Sm)\nSd ← FP_Add(Sd, product)\nFPSCR ← updated with floating-point exception flags" }, { "mnemonic": "vmls", "architecture": "ARMv8-A", "full_name": "Vector Multiply Subtract (VFP)", "summary": "Sd = Sd - (Sn * Sm).", "syntax": "VMLS.F32 , , ", "encoding": { "format": "VFP Arith", "binary_pattern": "cond | 1110 | 0 | D | 00 | Vn | Vd | 10 | 10 | N | 1 | M | 0 | Vm", "hex_opcode": "0x0E000A40", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "1110", "clean": "1110" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "00", "clean": "00" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "N", "clean": "N" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:28 | 27:24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Sd", "desc": "Dest/Acc" }, { "name": "Sn", "desc": "First source 32-bit floating-point register" }, { "name": "Sm", "desc": "Second source 32-bit floating-point register" } ], "extension": "VFP (Float)", "description": "Multiplies two single-precision floating-point values and subtracts the result from the destination (Sd ← Sd - (Sn × Sm)). This VFP instruction performs a fused multiply-subtract operation on 32-bit IEEE 754 single-precision operands, with Sd serving as both accumulator and destination. The condition flags (N, Z, C, V) are updated based on the final floating-point result according to the FPSCR. Execution is conditional based on the condition code and requires VFP extension support in A32/T32 modes.", "example": "VMLS.F32 s0, s1, s2", "pseudocode": "Sd ← Sd - (Sn × Sm)\nFPSCR.NZCV ← FP_CC(result)" }, { "mnemonic": "vnmul", "architecture": "ARMv8-A", "full_name": "Vector Negated Multiply (VFP)", "summary": "Sd = -(Sn * Sm).", "syntax": "VNMUL.F32 , , ", "encoding": { "format": "VFP Arith", "binary_pattern": "cond | 1110 | 0 | D | 10 | Vn | Vd | 10 | 10 | N | 1 | M | 0 | Vm", "hex_opcode": "0x0E200A40", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "1110", "clean": "1110" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "10", "clean": "10" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "N", "clean": "N" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:28 | 27:24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" }, { "name": "Sn", "desc": "First source 32-bit floating-point register" }, { "name": "Sm", "desc": "Second source 32-bit floating-point register" } ], "extension": "VFP (Float)", "description": "Vector Negated Multiply (VFP) computes the negation of Sn × Sm and stores the result in Sd. This is equivalent to multiplying then negating, and follows IEEE 754 semantics for the intermediate product, with sign negation applied afterward. FPSCR exception flags are updated but ARM condition flags N, Z, C, V are not affected. Available in A32/T32 with VFP extension; execution is conditional based on the condition code suffix.", "example": "VNMUL.F32 s0, s1, s2", "pseudocode": "product ← FP_Multiply(Sn, Sm)\nSd ← FP_Negate(product)\nFPSCR ← updated with floating-point exception flags" }, { "mnemonic": "vabs", "architecture": "ARMv8-A", "full_name": "Vector Absolute Value (VFP)", "summary": "Calculates absolute value.", "syntax": "VABS.F32 , ", "encoding": { "format": "VFP Unary", "binary_pattern": "cond | 11101 | D | 11 | 0 | 000 | Vd | 10 | 10 | 1 | 1 | M | 0 | Vm", "hex_opcode": "0x0EB00AC0", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "11101", "clean": "11101" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "0", "clean": "0" }, { "raw": "000", "clean": "000" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" }, { "name": "Sm", "desc": "Second source 32-bit floating-point register" } ], "extension": "VFP (Float)", "description": "Vector Absolute Value (VFP) computes the absolute value of Sm by clearing the sign bit and storing the result in Sd. This is a unary floating-point operation that follows IEEE 754 semantics, updating FPSCR exception flags but not affecting ARM condition flags. Available in A32/T32 with VFP extension; execution is conditional based on the condition code suffix.", "example": "VABS.F32 s0, s2", "pseudocode": "Sd ← FP_AbsoluteValue(Sm)\nFPSCR ← updated with floating-point exception flags" }, { "mnemonic": "vneg", "architecture": "ARMv8-A", "full_name": "Vector Negate (VFP)", "summary": "Negates the value.", "syntax": "VNEG.F32 , ", "encoding": { "format": "VFP Unary", "binary_pattern": "cond | 11101 | D | 11 | 0 | 001 | Vd | 10 | 10 | 0 | 1 | M | 0 | Vm", "hex_opcode": "0x0EB10A40", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "11101", "clean": "11101" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "0", "clean": "0" }, { "raw": "001", "clean": "001" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" }, { "name": "Sm", "desc": "Second source 32-bit floating-point register" } ], "extension": "VFP (Float)", "description": "Vector Negate (VFP) negates the value in Sm by inverting the sign bit and stores the result in Sd. This is a unary floating-point operation that follows IEEE 754 semantics, affecting only the sign bit and updating FPSCR exception flags but not ARM condition flags. Available in A32/T32 with VFP extension; execution is conditional based on the condition code suffix.", "example": "VNEG.F32 s0, s2", "pseudocode": "Sd ← FP_Negate(Sm)\nFPSCR ← updated with floating-point exception flags" }, { "mnemonic": "vsqrt", "architecture": "ARMv8-A", "full_name": "Vector Square Root (VFP)", "summary": "Calculates square root.", "syntax": "VSQRT.F32 , ", "encoding": { "format": "VFP Unary", "binary_pattern": "cond | 11101 | D | 11 | 0 | 001 | Vd | 10 | 10 | 1 | 1 | M | 0 | Vm", "hex_opcode": "0x0EB10AC0", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "11101", "clean": "11101" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "0", "clean": "0" }, { "raw": "001", "clean": "001" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" }, { "name": "Sm", "desc": "Second source 32-bit floating-point register" } ], "extension": "VFP (Float)", "description": "Vector Square Root (VFP) computes the square root of Sm using IEEE 754 semantics and stores the result in Sd. This unary floating-point operation may raise exceptions for invalid operands (negative inputs) or precision issues, updating FPSCR exception flags but not affecting ARM condition flags. Available in A32/T32 with VFP extension; execution is conditional based on the condition code suffix.", "example": "VSQRT.F32 s0, s2", "pseudocode": "Sd ← FP_SquareRoot(Sm)\nFPSCR ← updated with floating-point exception flags" }, { "mnemonic": "vcmp", "architecture": "ARMv8-A", "full_name": "Vector Compare (VFP)", "summary": "Compares two floating-point values.", "syntax": "VCMP.F32 , ", "encoding": { "format": "VFP Compare", "binary_pattern": "cond | 11101 | D | 11 | 0 | 100 | Vd | 10 | 10 | 0 | 1 | M | 0 | Vm", "hex_opcode": "0x0EB40A40", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "11101", "clean": "11101" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "0", "clean": "0" }, { "raw": "100", "clean": "100" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" }, { "name": "Sm", "desc": "Second source 32-bit floating-point register" } ], "extension": "VFP (Float)", "description": "Compares two single-precision floating-point values in VFP registers and sets the FPSCR condition flags (N, Z, C, V) based on the comparison result. The comparison is quiet (does not raise exceptions for NaN operands). Executed in A32/T32 with VFP extension; condition flags are updated in the floating-point status and control register (FPSCR), not the general-purpose condition flags.", "example": "VCMP.F32 s0, s2", "pseudocode": "result ← compare(Sd, Sm)\nFPSCR.N ← result.N\nFPSCR.Z ← result.Z\nFPSCR.C ← result.C\nFPSCR.V ← result.V" }, { "mnemonic": "vcmpe", "architecture": "ARMv8-A", "full_name": "Vector Compare Exception (VFP)", "summary": "Compares values and raises exception on NaN.", "syntax": "VCMPE.F32 , ", "encoding": { "format": "VFP Compare", "binary_pattern": "cond | 11101 | D | 11 | 0 | 100 | Vd | 10 | 10 | 1 | 1 | M | 0 | Vm", "hex_opcode": "0x0EB40AC0", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "11101", "clean": "11101" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "0", "clean": "0" }, { "raw": "100", "clean": "100" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" }, { "name": "Sm", "desc": "Second source 32-bit floating-point register" } ], "extension": "VFP (Float)", "description": "Compares two single-precision floating-point values in VFP registers and sets the FPSCR condition flags (N, Z, C, V) based on the comparison result. Unlike VCMP, this variant raises an Invalid Operation exception if either operand is NaN (signaling comparison). Executed in A32/T32 with VFP extension; exception behavior depends on FPSCR exception-enable bits.", "example": "VCMPE.F32 s0, s2", "pseudocode": "if Sd is NaN or Sm is NaN then\n if FPSCR.IXE then raise InvalidOperationException\nresult ← compare(Sd, Sm)\nFPSCR.N ← result.N\nFPSCR.Z ← result.Z\nFPSCR.C ← result.C\nFPSCR.V ← result.V" }, { "mnemonic": "vcvt", "architecture": "ARMv8-A", "full_name": "Vector Convert (Float to Integer)", "summary": "Converts float to signed/unsigned integer.", "syntax": "VCVT.. , ", "encoding": { "format": "VFP Convert", "binary_pattern": "cond | 11101 | D | 11 | 1 | 000 | Vd | 10 | 01 | op | 1 | M | 0 | Vm", "hex_opcode": "0x0EB80940", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "11101", "clean": "11101" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "1", "clean": "1" }, { "raw": "000", "clean": "000" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "01", "clean": "01" }, { "raw": "op", "clean": "op" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" }, { "name": "Sm", "desc": "Second source 32-bit floating-point register" } ], "extension": "VFP (Float)", "description": "Converts a single-precision floating-point value to a signed or unsigned 32-bit integer and stores the result in Sd. This VFP instruction performs floating-point-to-integer conversion with rounding behavior controlled by the FPSCR rounding mode. The condition flags are not updated; conversion errors (overflow, invalid operand) may set exception bits in the FPSCR depending on exception configuration. Execution is conditional based on the condition code and requires VFP extension support in A32/T32 modes.", "example": "VCVT.Td.Tm s0, s2", "pseudocode": "result ← Convert_F32_to_Int32(Sm, signed/unsigned, rounding_mode)\nSd ← result\nif (overflow or invalid) then FP_Exception_or_Saturate()" }, { "mnemonic": "vmov", "architecture": "ARMv8-A", "full_name": "Vector Move (Register)", "summary": "Moves data between VFP registers.", "syntax": "VMOV.F32 , ", "encoding": { "format": "VFP Move", "binary_pattern": "cond | 11101 | D | 11 | 0 | 000 | Vd | 10 | size | 0 | 1 | M | 0 | Vm", "hex_opcode": "0x0EB00A40", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "11101", "clean": "11101" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "0", "clean": "0" }, { "raw": "000", "clean": "000" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "size", "clean": "size" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" }, { "name": "Sm", "desc": "Second source 32-bit floating-point register" } ], "extension": "VFP (Float)", "description": "Moves (copies) a single-precision floating-point value from one VFP register to another (Sd ← Sm). This is a pure register-to-register transfer with no arithmetic; it preserves the bit pattern including NaN payloads and sign. Condition flags are not affected. Execution is conditional based on the condition code and requires VFP extension support in A32/T32 modes.", "example": "VMOV.F32 s0, s2", "pseudocode": "Sd ← Sm" }, { "mnemonic": "vmov", "architecture": "ARMv8-A", "full_name": "Vector Move (Core <-> VFP)", "summary": "Moves data between Core registers (R) and VFP registers (S).", "syntax": "VMOV , ", "encoding": { "format": "VFP Transfer", "binary_pattern": "cond | 1110000 | 0 | Vn | Rt | 1010 | N | 0 | 0 | 1 | 0 | 0 | 0 | 0", "hex_opcode": "0x0E000A10", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "1110000", "clean": "1110000" }, { "raw": "0", "clean": "0" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Rt", "clean": "Rt" }, { "raw": "1010", "clean": "1010" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" } ], "bit_positions": "31:28 | 27:21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0" }, "operands": [ { "name": "Sn", "desc": "VFP Reg" }, { "name": "Rt", "desc": "Core Reg" } ], "extension": "VFP (Float)", "description": "Moves a 32-bit value between a core integer register (Rt) and a VFP single-precision register (Sn). The instruction transfers the bit pattern without interpretation; a floating-point value moved to a core register is treated as raw bits. Condition flags are not affected. Execution is conditional based on the condition code and requires VFP extension support in A32/T32 modes.", "example": "VMOV s1, r3", "pseudocode": "Sn ← Rt (bit-exact transfer)" }, { "mnemonic": "vldr", "architecture": "ARMv8-A", "full_name": "Vector Load Register (VFP)", "summary": "Loads a floating-point register from memory.", "syntax": "VLDR , [, #+/-]", "encoding": { "format": "VFP Load", "binary_pattern": "cond | 110 | 1 | U | D | 0 | 1 | Rn | Vd | 10 | 10 | imm8", "hex_opcode": "0x0D100A00", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "110", "clean": "110" }, { "raw": "1", "clean": "1" }, { "raw": "U", "clean": "U" }, { "raw": "D", "clean": "D" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "imm8", "clean": "imm8" } ], "bit_positions": "31:28 | 27:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:10 | 9:8 | 7:0" }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "imm", "desc": "Signed immediate value" } ], "extension": "VFP (Float)", "description": "Loads a single-precision floating-point value from memory into a VFP register using a PC-relative or register-relative address with an optional offset. The memory access uses the address [Rn ± (imm8 << 2)]. Executed in A32/T32 with VFP extension; no condition flags are affected.", "example": "VLDR s0, [r1, #+/-#16]", "pseudocode": "offset ← ZeroExtend(imm8) << 2\nif U == 1 then\n address ← Rn + offset\nelse\n address ← Rn - offset\nSd ← [address]" }, { "mnemonic": "vstr", "architecture": "ARMv8-A", "full_name": "Vector Store Register (VFP)", "summary": "Stores a floating-point register to memory.", "syntax": "VSTR , [, #+/-]", "encoding": { "format": "VFP Store", "binary_pattern": "cond | 110 | 1 | U | D | 0 | 0 | Rn | Vd | 10 | 10 | imm8", "hex_opcode": "0x0D000A00", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "110", "clean": "110" }, { "raw": "1", "clean": "1" }, { "raw": "U", "clean": "U" }, { "raw": "D", "clean": "D" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "imm8", "clean": "imm8" } ], "bit_positions": "31:28 | 27:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:10 | 9:8 | 7:0" }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "imm", "desc": "Signed immediate value" } ], "extension": "VFP (Float)", "description": "Stores a single-precision floating-point value from a VFP register to memory using a register-relative address with an optional offset. The memory access uses the address [Rn ± (imm8 << 2)]. Executed in A32/T32 with VFP extension; no condition flags are affected.", "example": "VSTR s0, [r1, #+/-#16]", "pseudocode": "offset ← ZeroExtend(imm8) << 2\nif U == 1 then\n address ← Rn + offset\nelse\n address ← Rn - offset\n[address] ← Sd" }, { "mnemonic": "vpop", "architecture": "ARMv8-A", "full_name": "Vector Pop (VFP)", "summary": "Pops VFP registers from the stack (Alias for VLDMIA SP!).", "syntax": "VPOP ", "encoding": { "format": "VFP Load Multiple", "binary_pattern": "cond | 110 | 0 | 1 | D | 1 | 1 | 1101 | Vd | 10 | 10 | imm8", "hex_opcode": "0x0CBD0A00", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "110", "clean": "110" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1101", "clean": "1101" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "imm8", "clean": "imm8" } ], "bit_positions": "31:28 | 27:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:10 | 9:8 | 7:0" }, "operands": [ { "name": "list", "desc": "Register List" } ], "extension": "VFP (Float)", "description": "Pops VFP floating-point registers from the stack by loading them from memory at the address in SP, then post-incrementing SP. This is an alias for VLDMIA SP! (VFP Load Multiple with post-index). The condition flags (N, Z, C, V) are unaffected by this instruction. Execution is restricted to A32 and T32 instruction sets with VFP extension enabled.", "example": "VPOP {r0-r3", "pseudocode": "address ← SP; for each register in list (in ascending order): register ← [address]; address ← address + 4 or 8 (depending on register width); SP ← address;" }, { "mnemonic": "vpush", "architecture": "ARMv8-A", "full_name": "Vector Push (VFP)", "summary": "Pushes VFP registers to the stack (Alias for VSTMDB SP!).", "syntax": "VPUSH ", "encoding": { "format": "VFP Store Multiple", "binary_pattern": "cond | 110 | 1 | 0 | D | 1 | 0 | 1101 | Vd | 10 | 10 | imm8", "hex_opcode": "0x0D2D0A00", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "110", "clean": "110" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "1101", "clean": "1101" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "imm8", "clean": "imm8" } ], "bit_positions": "31:28 | 27:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:10 | 9:8 | 7:0" }, "operands": [ { "name": "list", "desc": "Register List" } ], "extension": "VFP (Float)", "description": "Pushes VFP floating-point registers onto the stack by decrementing SP and storing them to memory. This is an alias for VSTMDB SP! (VFP Store Multiple with pre-decrement). The condition flags (N, Z, C, V) are unaffected by this instruction. Execution is restricted to A32 and T32 instruction sets with VFP extension enabled.", "example": "VPUSH {r0-r3", "pseudocode": "address ← SP; for each register in list (in descending order): address ← address - 4 or 8 (depending on register width); [address] ← register; SP ← address;" }, { "mnemonic": "adc.w", "architecture": "ARMv8-A", "full_name": "Add with Carry (Wide)", "summary": "Thumb-2 32-bit add with carry (Access high registers/large constants).", "syntax": "ADC.W , , ", "encoding": { "format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 1010 | 0 | Rn | 0 | imm3 | Rd | imm2 | stype | Rm", "hex_opcode": "0xEB400000", "visual_parts": [ { "raw": "1110101", "clean": "1110101" }, { "raw": "1010", "clean": "1010" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "0", "clean": "0" }, { "raw": "imm3", "clean": "imm3" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "imm2", "clean": "imm2" }, { "raw": "stype", "clean": "stype" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Operand2", "desc": "Flexible second operand (register or shifted register)" } ], "extension": "T32 (Thumb2)", "description": "Adds Rn and Operand2 plus the Carry flag value, storing the result in Rd. If S=1, the N, Z, C, V flags are updated based on the result; otherwise flags are unaffected. This is a Thumb-2 32-bit instruction that allows use of high registers (R8-R15) and larger constant operands than 16-bit Thumb ADC.", "example": "ADC.W r0, r1, r2", "pseudocode": "result ← Rn + Operand2 + C; Rd ← result; if S == 1 then: N ← result[31]; Z ← (result == 0); C ← CarryOut(Rn, Operand2, C); V ← OverflowFrom(Rn, Operand2, C);" }, { "mnemonic": "add.w", "architecture": "ARMv8-A", "full_name": "Add (Wide)", "summary": "Thumb-2 32-bit add.", "syntax": "ADD.W , , ", "encoding": { "format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 1000 | 0 | Rn | 0 | imm3 | Rd | imm2 | stype | Rm", "hex_opcode": "0xEB000000", "visual_parts": [ { "raw": "1110101", "clean": "1110101" }, { "raw": "1000", "clean": "1000" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "0", "clean": "0" }, { "raw": "imm3", "clean": "imm3" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "imm2", "clean": "imm2" }, { "raw": "stype", "clean": "stype" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Operand2", "desc": "Flexible second operand (register or shifted register)" } ], "extension": "T32 (Thumb2)", "description": "Adds Rn and Operand2, storing the result in Rd. If S=1, the N, Z, C, V flags are updated based on the result; otherwise flags are unaffected. This is a Thumb-2 32-bit instruction that allows use of high registers (R8-R15) and larger constant operands than 16-bit Thumb ADD.", "example": "ADD.W r0, r1, r2", "pseudocode": "result ← Rn + Operand2; Rd ← result; if S == 1 then: N ← result[31]; Z ← (result == 0); C ← CarryOut(Rn, Operand2); V ← OverflowFrom(Rn, Operand2);" }, { "mnemonic": "sub.w", "architecture": "ARMv8-A", "full_name": "Subtract (Wide)", "summary": "Thumb-2 32-bit subtract.", "syntax": "SUB.W , , ", "encoding": { "format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 1101 | 0 | Rn | 0 | imm3 | Rd | imm2 | stype | Rm", "hex_opcode": "0xEBA00000", "visual_parts": [ { "raw": "1110101", "clean": "1110101" }, { "raw": "1101", "clean": "1101" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "0", "clean": "0" }, { "raw": "imm3", "clean": "imm3" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "imm2", "clean": "imm2" }, { "raw": "stype", "clean": "stype" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Operand2", "desc": "Flexible second operand (register or shifted register)" } ], "extension": "T32 (Thumb2)", "description": "Subtracts Operand2 from Rn, storing the result in Rd. If S=1, the N, Z, C, V flags are updated based on the result; otherwise flags are unaffected. This is a Thumb-2 32-bit instruction that allows use of high registers (R8-R15) and larger constant operands than 16-bit Thumb SUB.", "example": "SUB.W r0, r1, r2", "pseudocode": "result ← Rn - Operand2; Rd ← result; if S == 1 then: N ← result[31]; Z ← (result == 0); C ← NOT BorrowFrom(Rn, Operand2); V ← OverflowFrom(Rn, -Operand2);" }, { "mnemonic": "sbc.w", "architecture": "ARMv8-A", "full_name": "Subtract with Carry (Wide)", "summary": "Thumb-2 32-bit subtract with carry.", "syntax": "SBC.W , , ", "encoding": { "format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 1011 | 0 | Rn | 0 | imm3 | Rd | imm2 | stype | Rm", "hex_opcode": "0xEB600000", "visual_parts": [ { "raw": "1110101", "clean": "1110101" }, { "raw": "1011", "clean": "1011" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "0", "clean": "0" }, { "raw": "imm3", "clean": "imm3" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "imm2", "clean": "imm2" }, { "raw": "stype", "clean": "stype" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Operand2", "desc": "Flexible second operand (register or shifted register)" } ], "extension": "T32 (Thumb2)", "description": "Subtracts Operand2 and the inverted Carry flag from Rn, storing the result in Rd. If S=1, the N, Z, C, V flags are updated based on the result; otherwise flags are unaffected. This is a Thumb-2 32-bit instruction used for multi-word arithmetic with carry propagation.", "example": "SBC.W r0, r1, r2", "pseudocode": "result ← Rn - Operand2 - (NOT C); Rd ← result; if S == 1 then: N ← result[31]; Z ← (result == 0); C ← NOT BorrowFrom(Rn, Operand2, NOT C); V ← OverflowFrom(Rn, -Operand2, NOT C);" }, { "mnemonic": "rsb.w", "architecture": "ARMv8-A", "full_name": "Reverse Subtract (Wide)", "summary": "Thumb-2 32-bit reverse subtract.", "syntax": "RSB.W , , ", "encoding": { "format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 1110 | 0 | Rn | 0 | imm3 | Rd | imm2 | stype | Rm", "hex_opcode": "0xEBC00000", "visual_parts": [ { "raw": "1110101", "clean": "1110101" }, { "raw": "1110", "clean": "1110" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "0", "clean": "0" }, { "raw": "imm3", "clean": "imm3" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "imm2", "clean": "imm2" }, { "raw": "stype", "clean": "stype" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Operand2", "desc": "Flexible second operand (register or shifted register)" } ], "extension": "T32 (Thumb2)", "description": "Reverse-subtracts Rn from Operand2, storing the result in Rd (computes Operand2 - Rn). If S=1, the N, Z, C, V flags are updated based on the result; otherwise flags are unaffected. This is a Thumb-2 32-bit instruction allowing negation and complex arithmetic patterns.", "example": "RSB.W r0, r1, r2", "pseudocode": "result ← Operand2 - Rn; Rd ← result; if S == 1 then: N ← result[31]; Z ← (result == 0); C ← NOT BorrowFrom(Operand2, Rn); V ← OverflowFrom(Operand2, -Rn);" }, { "mnemonic": "and.w", "architecture": "ARMv8-A", "full_name": "Bitwise AND (Wide)", "summary": "Thumb-2 32-bit AND.", "syntax": "AND.W , , ", "encoding": { "format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 0000 | 0 | Rn | 0 | imm3 | Rd | imm2 | stype | Rm", "hex_opcode": "0xEA000000", "visual_parts": [ { "raw": "1110101", "clean": "1110101" }, { "raw": "0000", "clean": "0000" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "0", "clean": "0" }, { "raw": "imm3", "clean": "imm3" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "imm2", "clean": "imm2" }, { "raw": "stype", "clean": "stype" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Operand2", "desc": "Flexible second operand (register or shifted register)" } ], "extension": "T32 (Thumb2)", "description": "Performs a bitwise AND of Rn and the shifted Operand2, storing the result in Rd. In Thumb-2, this is a 32-bit instruction that can update the condition flags (N, Z, C) when the S bit is set; V is unaffected. The operand2 can be a register with optional shift or an immediate value.", "example": "AND.W r0, r1, r2", "pseudocode": "result ← Rn AND Operand2\nRd ← result\nif S == 1 then\n CPSR.N ← result[31]\n CPSR.Z ← (result == 0)\n CPSR.C ← CarryOut(Operand2)\nelse\n CPSR.C ← CPSR.C" }, { "mnemonic": "orr.w", "architecture": "ARMv8-A", "full_name": "Bitwise OR (Wide)", "summary": "Thumb-2 32-bit OR.", "syntax": "ORR.W , , ", "encoding": { "format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 0010 | 0 | Rn | 0 | imm3 | Rd | imm2 | stype | Rm", "hex_opcode": "0xEA400000", "visual_parts": [ { "raw": "1110101", "clean": "1110101" }, { "raw": "0010", "clean": "0010" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "0", "clean": "0" }, { "raw": "imm3", "clean": "imm3" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "imm2", "clean": "imm2" }, { "raw": "stype", "clean": "stype" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Operand2", "desc": "Flexible second operand (register or shifted register)" } ], "extension": "T32 (Thumb2)", "description": "Performs a bitwise OR of Rn and the shifted Operand2, storing the result in Rd. In Thumb-2, this is a 32-bit instruction that can update the condition flags (N, Z, C) when the S bit is set; V is unaffected. The operand2 can be a register with optional shift or an immediate value.", "example": "ORR.W r0, r1, r2", "pseudocode": "result ← Rn OR Operand2\nRd ← result\nif S == 1 then\n CPSR.N ← result[31]\n CPSR.Z ← (result == 0)\n CPSR.C ← CarryOut(Operand2)\nelse\n CPSR.C ← CPSR.C" }, { "mnemonic": "eor.w", "architecture": "ARMv8-A", "full_name": "Bitwise Exclusive OR (Wide)", "summary": "Thumb-2 32-bit XOR.", "syntax": "EOR.W , , ", "encoding": { "format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 0100 | 0 | Rn | 0 | imm3 | Rd | imm2 | stype | Rm", "hex_opcode": "0xEA800000", "visual_parts": [ { "raw": "1110101", "clean": "1110101" }, { "raw": "0100", "clean": "0100" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "0", "clean": "0" }, { "raw": "imm3", "clean": "imm3" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "imm2", "clean": "imm2" }, { "raw": "stype", "clean": "stype" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Operand2", "desc": "Flexible second operand (register or shifted register)" } ], "extension": "T32 (Thumb2)", "description": "Performs a bitwise exclusive-OR (XOR) of Rn and the shifted Operand2, storing the result in Rd. In Thumb-2, this is a 32-bit instruction that can update the condition flags (N, Z, C) when the S bit is set; V is unaffected. The operand2 can be a register with optional shift or an immediate value.", "example": "EOR.W r0, r1, r2", "pseudocode": "result ← Rn XOR Operand2\nRd ← result\nif S == 1 then\n CPSR.N ← result[31]\n CPSR.Z ← (result == 0)\n CPSR.C ← CarryOut(Operand2)\nelse\n CPSR.C ← CPSR.C" }, { "mnemonic": "bic.w", "architecture": "ARMv8-A", "full_name": "Bitwise Bit Clear (Wide)", "summary": "Thumb-2 32-bit AND NOT.", "syntax": "BIC.W , , ", "encoding": { "format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 0001 | 0 | Rn | 0 | imm3 | Rd | imm2 | stype | Rm", "hex_opcode": "0xEA200000", "visual_parts": [ { "raw": "1110101", "clean": "1110101" }, { "raw": "0001", "clean": "0001" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "0", "clean": "0" }, { "raw": "imm3", "clean": "imm3" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "imm2", "clean": "imm2" }, { "raw": "stype", "clean": "stype" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Operand2", "desc": "Flexible second operand (register or shifted register)" } ], "extension": "T32 (Thumb2)", "description": "Performs a bitwise AND of Rn with the bitwise NOT of the shifted Operand2, effectively clearing bits in Rn where Operand2 has set bits. In Thumb-2, this is a 32-bit instruction that can update the condition flags (N, Z, C) when the S bit is set; V is unaffected. The operand2 can be a register with optional shift or an immediate value.", "example": "BIC.W r0, r1, r2", "pseudocode": "result ← Rn AND NOT Operand2\nRd ← result\nif S == 1 then\n CPSR.N ← result[31]\n CPSR.Z ← (result == 0)\n CPSR.C ← CarryOut(Operand2)\nelse\n CPSR.C ← CPSR.C" }, { "mnemonic": "orn.w", "architecture": "ARMv8-A", "full_name": "Bitwise OR NOT (Wide)", "summary": "Thumb-2 32-bit OR NOT.", "syntax": "ORN.W , , ", "encoding": { "format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 0011 | 0 | Rn | 0 | imm3 | Rd | imm2 | stype | Rm", "hex_opcode": "0xEA600000", "visual_parts": [ { "raw": "1110101", "clean": "1110101" }, { "raw": "0011", "clean": "0011" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "0", "clean": "0" }, { "raw": "imm3", "clean": "imm3" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "imm2", "clean": "imm2" }, { "raw": "stype", "clean": "stype" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Operand2", "desc": "Flexible second operand (register or shifted register)" } ], "extension": "T32 (Thumb2)", "description": "Bitwise OR NOT: computes Rd = Rn | ~Operand2, performing a logical OR between Rn and the bitwise NOT of Operand2. The N and Z flags are updated based on the result; C is updated by the shifter; V is unaffected. This is a Thumb-2 (32-bit) instruction available in T32 execution state.", "example": "ORN.W r0, r1, r2", "pseudocode": "result ← Rn | (NOT Operand2)\nRd ← result\nN ← result[31]\nZ ← (result == 0)\nC ← CarryOut(NOT Operand2)\nV ← unchanged" }, { "mnemonic": "mov.w", "architecture": "ARMv8-A", "full_name": "Move (Wide)", "summary": "Thumb-2 32-bit Move.", "syntax": "MOV.W , ", "encoding": { "format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 0010 | 0 | 1111 | 0 | imm3 | Rd | imm2 | stype | Rm", "hex_opcode": "0xEA4F0000", "visual_parts": [ { "raw": "1110101", "clean": "1110101" }, { "raw": "0010", "clean": "0010" }, { "raw": "0", "clean": "0" }, { "raw": "1111", "clean": "1111" }, { "raw": "0", "clean": "0" }, { "raw": "imm3", "clean": "imm3" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "imm2", "clean": "imm2" }, { "raw": "stype", "clean": "stype" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Operand2", "desc": "Flexible second operand (register or shifted register)" } ], "extension": "T32 (Thumb2)", "description": "Moves Operand2 into Rd without affecting any flags (the S bit is fixed to 0 in this variant). This is a Thumb-2 32-bit instruction that allows encoding of larger immediates (via modified immediate) and access to high registers (R8-R15), providing greater flexibility than 16-bit Thumb MOV.", "example": "MOV.W r0, r2", "pseudocode": "Rd ← Operand2;" }, { "mnemonic": "mvn.w", "architecture": "ARMv8-A", "full_name": "Move NOT (Wide)", "summary": "Thumb-2 32-bit Move Inverse.", "syntax": "MVN.W , ", "encoding": { "format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 0011 | 0 | 1111 | 0 | imm3 | Rd | imm2 | stype | Rm", "hex_opcode": "0xEA6F0000", "visual_parts": [ { "raw": "1110101", "clean": "1110101" }, { "raw": "0011", "clean": "0011" }, { "raw": "0", "clean": "0" }, { "raw": "1111", "clean": "1111" }, { "raw": "0", "clean": "0" }, { "raw": "imm3", "clean": "imm3" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "imm2", "clean": "imm2" }, { "raw": "stype", "clean": "stype" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Operand2", "desc": "Flexible second operand (register or shifted register)" } ], "extension": "T32 (Thumb2)", "description": "Thumb-2 32-bit bitwise NOT: Rd ← NOT(Operand2). The second operand can be a register or a shifted register. If the S suffix is present, the condition flags N and Z are updated based on the result, and C is updated from the shifter carry-out; V is unaffected. Execution state: T32 only.", "example": "MVN.W r0, r2", "pseudocode": "result ← NOT(Operand2)\nRd ← result\nif S then\n N ← result[31]\n Z ← (result == 0)\n C ← shifter_carry_out" }, { "mnemonic": "tst.w", "architecture": "ARMv8-A", "full_name": "Test (Wide)", "summary": "Thumb-2 32-bit Test (AND and update flags).", "syntax": "TST.W , ", "encoding": { "format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 0000 | 1 | Rn | 0 | imm3 | 1111 | imm2 | stype | Rm", "hex_opcode": "0xEA100F00", "visual_parts": [ { "raw": "1110101", "clean": "1110101" }, { "raw": "0000", "clean": "0000" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "0", "clean": "0" }, { "raw": "imm3", "clean": "imm3" }, { "raw": "1111", "clean": "1111" }, { "raw": "imm2", "clean": "imm2" }, { "raw": "stype", "clean": "stype" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0" }, "operands": [ { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Operand2", "desc": "Flexible second operand (register or shifted register)" } ], "extension": "T32 (Thumb2)", "description": "Test (AND and update flags): computes the bitwise AND of Rn and Operand2, updating the N and Z flags based on the result without writing to a destination register. C is updated by the shifter; V is unaffected. This is a Thumb-2 (32-bit) instruction available in T32 execution state.", "example": "TST.W r1, r2", "pseudocode": "result ← Rn AND Operand2\nN ← result[31]\nZ ← (result == 0)\nC ← CarryOut(Operand2)\nV ← unchanged" }, { "mnemonic": "teq.w", "architecture": "ARMv8-A", "full_name": "Test Equivalence (Wide)", "summary": "Thumb-2 32-bit Test Equivalence (XOR and update flags).", "syntax": "TEQ.W , ", "encoding": { "format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 0100 | 1 | Rn | 0 | imm3 | 1111 | imm2 | stype | Rm", "hex_opcode": "0xEA900F00", "visual_parts": [ { "raw": "1110101", "clean": "1110101" }, { "raw": "0100", "clean": "0100" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "0", "clean": "0" }, { "raw": "imm3", "clean": "imm3" }, { "raw": "1111", "clean": "1111" }, { "raw": "imm2", "clean": "imm2" }, { "raw": "stype", "clean": "stype" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0" }, "operands": [ { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Operand2", "desc": "Flexible second operand (register or shifted register)" } ], "extension": "T32 (Thumb2)", "description": "Test Equivalence (XOR and update flags): computes the bitwise XOR of Rn and Operand2, updating the N and Z flags based on the result without writing to a destination register. C is updated by the shifter; V is unaffected. This is a Thumb-2 (32-bit) instruction available in T32 execution state.", "example": "TEQ.W r1, r2", "pseudocode": "result ← Rn XOR Operand2\nN ← result[31]\nZ ← (result == 0)\nC ← CarryOut(Operand2)\nV ← unchanged" }, { "mnemonic": "cmp.w", "architecture": "ARMv8-A", "full_name": "Compare (Wide)", "summary": "Thumb-2 32-bit Compare (Subtract and update flags).", "syntax": "CMP.W , ", "encoding": { "format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 1101 | 1 | Rn | 0 | imm3 | 1111 | imm2 | stype | Rm", "hex_opcode": "0xEBB00F00", "visual_parts": [ { "raw": "1110101", "clean": "1110101" }, { "raw": "1101", "clean": "1101" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "0", "clean": "0" }, { "raw": "imm3", "clean": "imm3" }, { "raw": "1111", "clean": "1111" }, { "raw": "imm2", "clean": "imm2" }, { "raw": "stype", "clean": "stype" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0" }, "operands": [ { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Operand2", "desc": "Flexible second operand (register or shifted register)" } ], "extension": "T32 (Thumb2)", "description": "Compare (Subtract and update flags): computes Rn - Operand2, updating the N, Z, C, and V flags based on the result without writing to a destination register. This is a Thumb-2 (32-bit) instruction available in T32 execution state and is commonly used to set condition flags for subsequent conditional branches.", "example": "CMP.W r1, r2", "pseudocode": "result ← Rn - Operand2\nN ← result[31]\nZ ← (result == 0)\nC ← NOT BorrowFrom(Rn - Operand2)\nV ← OverflowFrom(Rn - Operand2)" }, { "mnemonic": "cmn.w", "architecture": "ARMv8-A", "full_name": "Compare Negative (Wide)", "summary": "Thumb-2 32-bit Compare Negative (Add and update flags).", "syntax": "CMN.W , ", "encoding": { "format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 1000 | 1 | Rn | 0 | imm3 | 1111 | imm2 | stype | Rm", "hex_opcode": "0xEB100F00", "visual_parts": [ { "raw": "1110101", "clean": "1110101" }, { "raw": "1000", "clean": "1000" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "0", "clean": "0" }, { "raw": "imm3", "clean": "imm3" }, { "raw": "1111", "clean": "1111" }, { "raw": "imm2", "clean": "imm2" }, { "raw": "stype", "clean": "stype" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0" }, "operands": [ { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Operand2", "desc": "Flexible second operand (register or shifted register)" } ], "extension": "T32 (Thumb2)", "description": "Compare Negative (Add and update flags): computes Rn + Operand2, updating the N, Z, C, and V flags based on the result without writing to a destination register. This is a Thumb-2 (32-bit) instruction available in T32 execution state and is commonly used to compare a register against the negation of a value.", "example": "CMN.W r1, r2", "pseudocode": "result ← Rn + Operand2\nN ← result[31]\nZ ← (result == 0)\nC ← CarryOut(Rn + Operand2)\nV ← OverflowFrom(Rn + Operand2)" }, { "mnemonic": "cdp", "architecture": "ARMv8-A", "full_name": "Coprocessor Data Processing (A32)", "summary": "Initiates a coprocessor data processing operation.", "syntax": "CDP , , , , , ", "encoding": { "format": "Coprocessor", "binary_pattern": "cond | 1110 | opc1 | CRn | CRd | coproc | opc2 | 0 | CRm", "hex_opcode": "0x0E000000", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "1110", "clean": "1110" }, { "raw": "opc1", "clean": "opc1" }, { "raw": "CRn", "clean": "CRn" }, { "raw": "CRd", "clean": "CRd" }, { "raw": "coproc", "clean": "coproc" }, { "raw": "opc2", "clean": "opc2" }, { "raw": "0", "clean": "0" }, { "raw": "CRm", "clean": "CRm" } ] }, "operands": [ { "name": "coproc", "desc": "CP Num" }, { "name": "CRd", "desc": "Destination coprocessor register" }, { "name": "CRn", "desc": "First source coprocessor register" }, { "name": "CRm", "desc": "Second source coprocessor register" } ], "extension": "A32 (System)", "description": "Coprocessor Data Processing: initiates a data processing operation in the specified coprocessor using three coprocessor registers and two operation codes. The instruction is conditional based on the condition field and does not modify processor flags. This is an A32 instruction restricted to privileged execution states in systems with a coprocessor.", "example": "CDP p15, 0, c0, c1, c2, 0", "pseudocode": "if ConditionPassed() then\n Coprocessor[coproc].DataProcessing(opc1, CRd, CRn, CRm, opc2)" }, { "mnemonic": "cdp2", "architecture": "ARMv8-A", "full_name": "Coprocessor Data Processing 2 (A32)", "summary": "Initiates a coprocessor operation (Extension encoding).", "syntax": "CDP2 , , , , , ", "encoding": { "format": "Coprocessor", "binary_pattern": "11111110 | opc1 | CRn | CRd | coproc | opc2 | 0 | CRm", "hex_opcode": "0xFE000000", "visual_parts": [ { "raw": "11111110", "clean": "11111110" }, { "raw": "opc1", "clean": "opc1" }, { "raw": "CRn", "clean": "CRn" }, { "raw": "CRd", "clean": "CRd" }, { "raw": "coproc", "clean": "coproc" }, { "raw": "opc2", "clean": "opc2" }, { "raw": "0", "clean": "0" }, { "raw": "CRm", "clean": "CRm" } ] }, "operands": [ { "name": "coproc", "desc": "CP Num" }, { "name": "CRd", "desc": "Destination coprocessor register" }, { "name": "CRn", "desc": "First source coprocessor register" }, { "name": "CRm", "desc": "Second source coprocessor register" } ], "extension": "A32 (System)", "description": "Coprocessor Data Processing 2 (unconditional extension): initiates a data processing operation in the specified coprocessor using three coprocessor registers and two operation codes. Unlike CDP, this instruction is unconditional and uses the extension encoding (always executes). Restricted to privileged execution states in systems with a coprocessor.", "example": "CDP2 p15, 0, c0, c1, c2, 0", "pseudocode": "Coprocessor[coproc].DataProcessing(opc1, CRd, CRn, CRm, opc2)" }, { "mnemonic": "mcr2", "architecture": "ARMv8-A", "full_name": "Move to Coprocessor from Register 2 (A32)", "summary": "Writes a general-purpose register to a coprocessor (Extension encoding).", "syntax": "MCR2 , , , , {, }", "encoding": { "format": "Coprocessor", "binary_pattern": "11111110 | opc1 | 0 | CRn | Rt | coproc | opc2 | 1 | CRm", "hex_opcode": "0xFE000010", "visual_parts": [ { "raw": "11111110", "clean": "11111110" }, { "raw": "opc1", "clean": "opc1" }, { "raw": "0", "clean": "0" }, { "raw": "CRn", "clean": "CRn" }, { "raw": "Rt", "clean": "Rt" }, { "raw": "coproc", "clean": "coproc" }, { "raw": "opc2", "clean": "opc2" }, { "raw": "1", "clean": "1" }, { "raw": "CRm", "clean": "CRm" } ] }, "operands": [ { "name": "coproc", "desc": "CP Num" }, { "name": "Rt", "desc": "Transfer general-purpose register (load/store)" }, { "name": "CRn", "desc": "Dest CP Reg" } ], "extension": "A32 (System)", "description": "A32 coprocessor data transfer (extension encoding): writes the general-purpose register Rt to the coprocessor coproc, register CRm, with operation codes opc1 and opc2. Does not modify condition flags. Execution state: A32 only; requires coprocessor support. May cause an Undefined Instruction exception if the coprocessor does not exist.", "example": "MCR2 p15, 0, r3, c1, c2", "pseudocode": "Coprocessor[coproc].CRm[opc2] ← Rt" }, { "mnemonic": "mrc2", "architecture": "ARMv8-A", "full_name": "Move to Register from Coprocessor 2 (A32)", "summary": "Reads a coprocessor register into a general-purpose register (Extension encoding).", "syntax": "MRC2 , , , , {, }", "encoding": { "format": "Coprocessor", "binary_pattern": "11111110 | opc1 | 1 | CRn | Rt | coproc | opc2 | 1 | CRm", "hex_opcode": "0xFE100010", "visual_parts": [ { "raw": "11111110", "clean": "11111110" }, { "raw": "opc1", "clean": "opc1" }, { "raw": "1", "clean": "1" }, { "raw": "CRn", "clean": "CRn" }, { "raw": "Rt", "clean": "Rt" }, { "raw": "coproc", "clean": "coproc" }, { "raw": "opc2", "clean": "opc2" }, { "raw": "1", "clean": "1" }, { "raw": "CRm", "clean": "CRm" } ] }, "operands": [ { "name": "coproc", "desc": "CP Num" }, { "name": "Rt", "desc": "Transfer general-purpose register (load/store)" }, { "name": "CRn", "desc": "Src CP Reg" } ], "extension": "A32 (System)", "description": "A32 coprocessor data transfer (extension encoding): reads a coprocessor register (CRn, CRm) from coproc into the general-purpose register Rt. The opc1 and opc2 fields specify the operation. Does not modify condition flags. Execution state: A32 only; requires coprocessor support. May cause an Undefined Instruction exception if the coprocessor does not exist.", "example": "MRC2 p15, 0, r3, c1, c2", "pseudocode": "Rt ← Coprocessor[coproc].CRn[opc1] or Coprocessor[coproc].CRm[opc2]" }, { "mnemonic": "mcrr2", "architecture": "ARMv8-A", "full_name": "Move to Coprocessor from Two Registers 2 (A32)", "summary": "Writes two registers to a coprocessor (Extension encoding).", "syntax": "MCRR2 , , , , ", "encoding": { "format": "Coprocessor", "binary_pattern": "111111000100 | Rt2 | Rt | coproc | opc1 | CRm", "hex_opcode": "0xFC400000", "visual_parts": [ { "raw": "111111000100", "clean": "111111000100" }, { "raw": "Rt2", "clean": "Rt2" }, { "raw": "Rt", "clean": "Rt" }, { "raw": "coproc", "clean": "coproc" }, { "raw": "opc1", "clean": "opc1" }, { "raw": "CRm", "clean": "CRm" } ] }, "operands": [ { "name": "coproc", "desc": "CP Num" }, { "name": "Rt", "desc": "Transfer general-purpose register (load/store)" }, { "name": "Rt2", "desc": "Second transfer register (load/store pair)" } ], "extension": "A32 (System)", "description": "A32 coprocessor data transfer (extension encoding): writes two general-purpose registers (Rt, Rt2) to the coprocessor coproc, coprocessor register CRm, with operation code opc1. Does not modify condition flags. Execution state: A32 only; requires coprocessor support. May cause an Undefined Instruction exception if the coprocessor does not exist.", "example": "MCRR2 p15, 0, r3, r4, c2", "pseudocode": "Coprocessor[coproc].CRm ← (Rt2 : Rt)" }, { "mnemonic": "mrrc2", "architecture": "ARMv8-A", "full_name": "Move to Two Registers from Coprocessor 2 (A32)", "summary": "Reads a coprocessor register into two registers (Extension encoding).", "syntax": "MRRC2 , , , , ", "encoding": { "format": "Coprocessor", "binary_pattern": "111111000101 | Rt2 | Rt | coproc | opc1 | CRm", "hex_opcode": "0xFC500000", "visual_parts": [ { "raw": "111111000101", "clean": "111111000101" }, { "raw": "Rt2", "clean": "Rt2" }, { "raw": "Rt", "clean": "Rt" }, { "raw": "coproc", "clean": "coproc" }, { "raw": "opc1", "clean": "opc1" }, { "raw": "CRm", "clean": "CRm" } ] }, "operands": [ { "name": "coproc", "desc": "CP Num" }, { "name": "Rt", "desc": "Dest 1" }, { "name": "Rt2", "desc": "Dest 2" } ], "extension": "A32 (System)", "description": "A32 coprocessor data transfer (extension encoding): reads a 64-bit value from coprocessor coproc register CRm into two general-purpose registers (Rt, Rt2), with operation code opc1. Does not modify condition flags. Execution state: A32 only; requires coprocessor support. May cause an Undefined Instruction exception if the coprocessor does not exist.", "example": "MRRC2 p15, 0, r3, r4, c2", "pseudocode": "(Rt2 : Rt) ← Coprocessor[coproc].CRm" }, { "mnemonic": "ldc2", "architecture": "ARMv8-A", "full_name": "Load Coprocessor 2 (A32)", "summary": "Loads memory into a coprocessor (Extension encoding).", "syntax": "LDC2{L} , , [, #+/-]{!}", "encoding": { "format": "Coprocessor", "binary_pattern": "1111110 | P | U | N | W | 1 | Rn | CRd | coproc | imm8", "hex_opcode": "0xFD100000", "visual_parts": [ { "raw": "1111110", "clean": "1111110" }, { "raw": "P", "clean": "P" }, { "raw": "U", "clean": "U" }, { "raw": "N", "clean": "N" }, { "raw": "W", "clean": "W" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "CRd", "clean": "CRd" }, { "raw": "coproc", "clean": "coproc" }, { "raw": "imm8", "clean": "imm8" } ] }, "operands": [ { "name": "coproc", "desc": "CP Num" }, { "name": "CRd", "desc": "Destination coprocessor register" }, { "name": "Rn", "desc": "First source / base general-purpose register" } ], "extension": "A32 (System)", "description": "Load Coprocessor 2 (unconditional extension): loads a word or multiple words from memory into a coprocessor register, with the memory address computed from Rn plus an optional offset. The P, U, W bits control pre/post-indexing and writeback; the instruction is unconditional and uses the extension encoding. Restricted to privileged execution states and requires a coprocessor.", "example": "LDC2 p15, c0, [r1, #+/-#16]!", "pseudocode": "if P == 0 and W == 1 then\n address ← Rn\n Rn ← Rn + (if U then imm8 << 2 else -(imm8 << 2))\nelse if P == 1 then\n address ← Rn + (if U then imm8 << 2 else -(imm8 << 2))\n if W == 1 then Rn ← address\nCoprocessor[coproc].LoadFromMemory(CRd, address)" }, { "mnemonic": "stc2", "architecture": "ARMv8-A", "full_name": "Store Coprocessor 2 (A32)", "summary": "Stores coprocessor contents to memory (Extension encoding).", "syntax": "STC2{L} , , [, #+/-]{!}", "encoding": { "format": "Coprocessor", "binary_pattern": "1111110 | P | U | N | W | 0 | Rn | CRd | coproc | imm8", "hex_opcode": "0xFD000000", "visual_parts": [ { "raw": "1111110", "clean": "1111110" }, { "raw": "P", "clean": "P" }, { "raw": "U", "clean": "U" }, { "raw": "N", "clean": "N" }, { "raw": "W", "clean": "W" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "CRd", "clean": "CRd" }, { "raw": "coproc", "clean": "coproc" }, { "raw": "imm8", "clean": "imm8" } ] }, "operands": [ { "name": "coproc", "desc": "CP Num" }, { "name": "CRd", "desc": "Destination coprocessor register" }, { "name": "Rn", "desc": "First source / base general-purpose register" } ], "extension": "A32 (System)", "description": "Stores coprocessor data to memory using an extension encoding (STC2 variant). The instruction computes an address from base register Rn and an offset (imm8 scaled by 4), and writes coprocessor register CRd to that memory location. The P, U, N, W bits control pre/post-indexing, up/down offset direction, narrow/wide transfer, and write-back. Condition flags are not affected.", "example": "STC2 p15, c0, [r1, #+/-#16]!", "pseudocode": "if ConditionPassed() then\n address ← ComputeAddress(Rn, imm8, P, U, W)\n memory[address] ← CP[coproc, CRd]\n if W == 1 then Rn ← address" }, { "mnemonic": "rrx", "architecture": "ARMv8-A", "full_name": "Rotate Right with Extend (A32)", "summary": "Shifts register right by 1, inserting Carry flag into MSB.", "syntax": "RRX{S} , ", "encoding": { "format": "Data Proc", "binary_pattern": "cond | 00011 | 01 | 0 | 0000 | Rd | 00000 | 11 | 0 | Rm", "hex_opcode": "0x01A00060", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00011", "clean": "00011" }, { "raw": "01", "clean": "01" }, { "raw": "0", "clean": "0" }, { "raw": "0000", "clean": "0000" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "00000", "clean": "00000" }, { "raw": "11", "clean": "11" }, { "raw": "0", "clean": "0" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11:7 | 6:5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (Base)", "description": "A32 Rotate Right with Extend by 1: Rd ← (C : Rm)[32:1], where the Carry flag is shifted into the MSB and the LSB is shifted out to C. If the S suffix is present, N and Z are updated from the result, and C is updated from the shifted-out bit; V is unaffected. Execution state: A32 only.", "example": "RRX r0, r2", "pseudocode": "shifted_result ← (C : Rm)[32:1]\nRd ← shifted_result\nif S then\n N ← shifted_result[31]\n Z ← (shifted_result == 0)\n C ← Rm[0]" }, { "mnemonic": "rrx", "architecture": "ARMv8-A", "full_name": "Rotate Right with Extend (Thumb)", "summary": "Thumb-2 32-bit Rotate Right with Extend.", "syntax": "RRX{S}.W , ", "encoding": { "format": "Thumb2 Data Proc", "binary_pattern": "1110101 | 0010 | 0 | 1111 | 0 | 000 | Rd | 00 | 11 | Rm", "hex_opcode": "0xEA4F0030", "visual_parts": [ { "raw": "1110101", "clean": "1110101" }, { "raw": "0010", "clean": "0010" }, { "raw": "0", "clean": "0" }, { "raw": "1111", "clean": "1111" }, { "raw": "0", "clean": "0" }, { "raw": "000", "clean": "000" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "00", "clean": "00" }, { "raw": "11", "clean": "11" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:25 | 24:21 | 20 | 19:16 | 15 | 14:12 | 11:8 | 7:6 | 5:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "T32 (Thumb2)", "description": "Thumb-2 32-bit Rotate Right with Extend by 1: Rd ← (C : Rm)[32:1], where the Carry flag is rotated into the MSB and the LSB is shifted out to C. If the S suffix is present, N and Z are updated from the result, and C is updated from the shifted-out bit; V is unaffected. Execution state: T32 only.", "example": "RRX.W r0, r2", "pseudocode": "shifted_result ← (C : Rm)[32:1]\nRd ← shifted_result\nif S then\n N ← shifted_result[31]\n Z ← (shifted_result == 0)\n C ← Rm[0]" }, { "mnemonic": "b.w", "architecture": "ARMv8-A", "full_name": "Branch (Wide)", "summary": "Thumb-2 32-bit Unconditional Branch (large range).", "syntax": "B.W
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 0111 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2000710", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "U", "clean": "U" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0111", "clean": "0111" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Dest/Acc" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "NEON Vector Absolute Difference and Accumulate: computes the absolute difference between corresponding elements in Qn and Qm, then adds the results to the corresponding elements in Qd (accumulation). The data type (dt) determined by sz (8, 16, 32 bits) specifies element width. NEON flags (FPSCR) are not modified; no general condition flags are affected.", "example": "VABA.dt q0, q1, q2", "pseudocode": "for i = 0 to num_elements(Qd, dt) - 1\n diff ← abs(Qn[i] - Qm[i])\n Qd[i] ← Qd[i] + diff" }, { "mnemonic": "vabd", "architecture": "ARMv8-A", "full_name": "Vector Absolute Difference", "summary": "Computes absolute difference between elements.", "syntax": "VABD.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 0111 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2000700", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "U", "clean": "U" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0111", "clean": "0111" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "NEON Vector Absolute Difference: computes the absolute difference between corresponding elements in Qn and Qm and stores results in Qd. The data type (dt) determined by sz specifies element width (8, 16, or 32 bits). NEON flags are not modified; no general condition flags are affected.", "example": "VABD.dt q0, q1, q2", "pseudocode": "for i = 0 to num_elements(Qd, dt) - 1\n Qd[i] ← abs(Qn[i] - Qm[i])" }, { "mnemonic": "vabs", "architecture": "ARMv8-A", "full_name": "Vector Absolute Value", "summary": "Calculates absolute value of integer/float elements.", "syntax": "VABS.
, ", "encoding": { "format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 01 | Vd | 0 | F | 110 | 0 | M | 0 | Vm", "hex_opcode": "0xF3B10300", "visual_parts": [ { "raw": "111100111", "clean": "111100111" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "size", "clean": "size" }, { "raw": "01", "clean": "01" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0", "clean": "0" }, { "raw": "F", "clean": "F" }, { "raw": "110", "clean": "110" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10 | 9:7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "NEON Vector Absolute Value: computes the absolute value of each element in Qm and stores the result in Qd. Supports integer (8, 16, 32 bits) and floating-point (32 bits) data types as specified by sz. NEON flags are not modified; no general condition flags are affected.", "example": "VABS.dt q0, q2", "pseudocode": "for i = 0 to num_elements(Qd, dt) - 1\n Qd[i] ← abs(Qm[i])" }, { "mnemonic": "vadd", "architecture": "ARMv8-A", "full_name": "Vector Add (Integer)", "summary": "Adds integer elements of two vectors.", "syntax": "VADD.I , , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 0 | D | size | Vn | Vd | 1000 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2000800", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1000", "clean": "1000" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Vector Add (Integer) performs element-wise addition of two NEON 128-bit registers, adding corresponding integer elements of size 8, 16, 32, or 64 bits. The instruction executes in Q-register (128-bit) mode and wraps on overflow without setting flags. This is a NEON SIMD instruction available in both A32 and T32 states when NEON is supported.", "example": "VADD.Isize q0, q1, q2", "pseudocode": "for each element i in Qd:\n Qd[i] ← Qn[i] + Qm[i]" }, { "mnemonic": "vaddhn", "architecture": "ARMv8-A", "full_name": "Vector Add High Narrow", "summary": "Adds 2N-bit elements, selects high N-bits for result.", "syntax": "VADDHN.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 1 | D | size | Vn | Vd | 0100 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2800400", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0100", "clean": "0100" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Dd", "desc": "Dest Narrow" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Adds corresponding 2N-bit elements from two 128-bit NEON registers, then selects the high N bits of each result and stores them as N-bit elements in the destination 64-bit register. This instruction performs unsigned or signed addition at 2× the element width, then narrows the result. No flags are affected.", "example": "VADDHN.dt d0, q1, q2", "pseudocode": "for i = 0 to pairs-1\n Dd[i] ← (Qn[i] + Qm[i])[2*N-1:N]" }, { "mnemonic": "vaddl", "architecture": "ARMv8-A", "full_name": "Vector Add Long", "summary": "Adds N-bit elements, producing 2N-bit results.", "syntax": "VADDL.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 1 | D | size | Vn | Vd | 000 | 0 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2800000", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "U", "clean": "U" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "000", "clean": "000" }, { "raw": "0", "clean": "0" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:9 | 8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Dest Wide" }, { "name": "Dn", "desc": "First source 64-bit SIMD/FP register" }, { "name": "Dm", "desc": "Second source 64-bit SIMD/FP register" } ], "extension": "NEON (SIMD)", "description": "Adds corresponding N-bit elements from two 64-bit NEON registers and produces 2N-bit results stored in a 128-bit register. This instruction performs widening addition, doubling the element width and producing twice as many result bits. No flags are affected.", "example": "VADDL.dt q0, d1, d2", "pseudocode": "for i = 0 to pairs-1\n Qd[i] ← Dn[i] + Dm[i]" }, { "mnemonic": "vaddw", "architecture": "ARMv8-A", "full_name": "Vector Add Wide", "summary": "Adds N-bit vector to 2N-bit vector.", "syntax": "VADDW.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 1 | D | size | Vn | Vd | 000 | 1 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2800100", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "U", "clean": "U" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "000", "clean": "000" }, { "raw": "1", "clean": "1" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:9 | 8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Dest Wide" }, { "name": "Qn", "desc": "Src Wide" }, { "name": "Dm", "desc": "Src Narrow" } ], "extension": "NEON (SIMD)", "description": "Adds a 64-bit vector of N-bit elements to a 128-bit vector of 2N-bit elements, with the narrow operand implicitly widened before addition. The result is stored in the 128-bit destination. This instruction combines widening and addition in a single operation. No flags are affected.", "example": "VADDW.dt q0, q1, d2", "pseudocode": "for i = 0 to pairs-1\n Qd[i] ← Qn[i] + widen(Dm[i])" }, { "mnemonic": "vand", "architecture": "ARMv8-A", "full_name": "Vector Bitwise AND", "summary": "Bitwise AND of two vectors.", "syntax": "VAND , , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 0 | D | 00 | Vn | Vd | 0001 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2000110", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "00", "clean": "00" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0001", "clean": "0001" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Performs bitwise AND on corresponding bits of two 128-bit NEON registers and stores the result in the destination register. This instruction is data-type agnostic and operates on the bit patterns directly. No flags are affected.", "example": "VAND q0, q1, q2", "pseudocode": "Qd ← Qn AND Qm" }, { "mnemonic": "vbic", "architecture": "ARMv8-A", "full_name": "Vector Bitwise Bit Clear", "summary": "ANDs Vd with NOT of Vm (Vd & ~Vm).", "syntax": "VBIC , , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 0 | D | 01 | Vn | Vd | 0001 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2100110", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "01", "clean": "01" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0001", "clean": "0001" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Performs bitwise AND of the first operand with the bitwise NOT of the second operand (Qd ← Qn AND NOT Qm), storing the result in the destination register. This clears bits in Qn where the corresponding bits in Qm are set. No flags are affected.", "example": "VBIC q0, q1, q2", "pseudocode": "Qd ← Qn AND (NOT Qm)" }, { "mnemonic": "vbif", "architecture": "ARMv8-A", "full_name": "Vector Bit Insert False", "summary": "Inserts bits from Vm into Vd where Vn (mask) is 0.", "syntax": "VBIF , , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | 1 | 0 | D | 11 | Vn | Vd | 0001 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF3300110", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0001", "clean": "0001" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" }, { "name": "Qn", "desc": "Mask" } ], "extension": "NEON (SIMD)", "description": "Selectively inserts bits from Qm into Qd where the corresponding bits in Qn (the mask) are 0. Where mask bits are 1, the original Qd bits are retained. This is a masked insert operation. No flags are affected.", "example": "VBIF q0, q2, q1", "pseudocode": "for i = 0 to 127\n if Qn[i] == 0 then Qd[i] ← Qm[i]" }, { "mnemonic": "vbit", "architecture": "ARMv8-A", "full_name": "Vector Bit Insert True", "summary": "Inserts bits from Vm into Vd where Vn (mask) is 1.", "syntax": "VBIT , , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | 1 | 0 | D | 10 | Vn | Vd | 0001 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF3200110", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "10", "clean": "10" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0001", "clean": "0001" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" }, { "name": "Qn", "desc": "Mask" } ], "extension": "NEON (SIMD)", "description": "Selectively inserts bits from Qm into Qd where the corresponding bits in Qn (the mask) are 1. Where mask bits are 0, the original Qd bits are retained. This is the complement of VBIF. No flags are affected.", "example": "VBIT q0, q2, q1", "pseudocode": "for i = 0 to 127\n if Qn[i] == 1 then Qd[i] ← Qm[i]" }, { "mnemonic": "vbsl", "architecture": "ARMv8-A", "full_name": "Vector Bit Select", "summary": "Selects bits from Vn or Vm based on Vd (mask).", "syntax": "VBSL , , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | 1 | 0 | D | 01 | Vn | Vd | 0001 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF3100110", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "01", "clean": "01" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0001", "clean": "0001" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Dest/Mask" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Performs a bit-select operation using Qd as the mask: selects bits from Qn where Qd bits are 1 and from Qm where Qd bits are 0. The result is stored in Qd. This implements the operation Qd ← (Qd AND Qn) OR (NOT Qd AND Qm). No flags are affected.", "example": "VBSL q0, q1, q2", "pseudocode": "for i = 0 to 127\n if Qd[i] == 1 then Qd[i] ← Qn[i] else Qd[i] ← Qm[i]" }, { "mnemonic": "vceq", "architecture": "ARMv8-A", "full_name": "Vector Compare Equal", "summary": "Sets destination bits to all 1s if elements equal, else 0s.", "syntax": "VCEQ.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | 1 | 0 | D | size | Vn | Vd | 1000 | N | 1 | M | 1 | Vm", "hex_opcode": "0xF3000850", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1000", "clean": "1000" }, { "raw": "N", "clean": "N" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Vector Compare Equal performs element-wise equality comparison on 128-bit SIMD registers. For each element in Qn and Qm, if they are equal, the corresponding element in Qd is set to all 1s; otherwise, it is set to all 0s. No condition flags are affected. This is a NEON instruction available in both A32 and T32 states.", "example": "VCEQ.dt q0, q1, q2", "pseudocode": "for i = 0 to (128 / element_size) - 1 do\n if Qn[i] == Qm[i] then\n Qd[i] ← all_ones\n else\n Qd[i] ← all_zeros\n end if\nend for" }, { "mnemonic": "vcge", "architecture": "ARMv8-A", "full_name": "Vector Compare Greater Than or Equal", "summary": "Compares elements (>=) and sets result mask.", "syntax": "VCGE.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 0011 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2000310", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "U", "clean": "U" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0011", "clean": "0011" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Vector Compare Greater Than or Equal performs signed element-wise comparison on 128-bit SIMD registers. For each element in Qn, if it is greater than or equal to the corresponding element in Qm, the result element in Qd is set to all 1s; otherwise, it is set to all 0s. No condition flags are affected. This is a NEON instruction available in both A32 and T32 states.", "example": "VCGE.dt q0, q1, q2", "pseudocode": "for i = 0 to (128 / element_size) - 1 do\n if Qn[i] >= Qm[i] then\n Qd[i] ← all_ones\n else\n Qd[i] ← all_zeros\n end if\nend for" }, { "mnemonic": "vcgt", "architecture": "ARMv8-A", "full_name": "Vector Compare Greater Than", "summary": "Compares elements (>) and sets result mask.", "syntax": "VCGT.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 0011 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2000300", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "U", "clean": "U" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0011", "clean": "0011" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Vector Compare Greater Than performs signed element-wise comparison on 128-bit SIMD registers. For each element in Qn, if it is strictly greater than the corresponding element in Qm, the result element in Qd is set to all 1s; otherwise, it is set to all 0s. No condition flags are affected. This is a NEON instruction available in both A32 and T32 states.", "example": "VCGT.dt q0, q1, q2", "pseudocode": "for i = 0 to (128 / element_size) - 1 do\n if Qn[i] > Qm[i] then\n Qd[i] ← all_ones\n else\n Qd[i] ← all_zeros\n end if\nend for" }, { "mnemonic": "vcle", "architecture": "ARMv8-A", "full_name": "Vector Compare Less Than or Equal", "summary": "Compares elements (<=). Alias for VCGE with swapped operands.", "syntax": "VCLE.
, , ", "encoding": { "format": "NEON Alias", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 0011 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2000310", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "U", "clean": "U" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0011", "clean": "0011" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Vector Compare Less Than or Equal is an alias that performs signed element-wise comparison on 128-bit SIMD registers with operands swapped relative to VCGE. For each element in Qn, if it is less than or equal to the corresponding element in Qm, the result element in Qd is set to all 1s; otherwise, it is set to all 0s. No condition flags are affected. This is a NEON instruction available in both A32 and T32 states.", "example": "VCLE.dt q0, q1, q2", "pseudocode": "for i = 0 to (128 / element_size) - 1 do\n if Qn[i] <= Qm[i] then\n Qd[i] ← all_ones\n else\n Qd[i] ← all_zeros\n end if\nend for" }, { "mnemonic": "vclt", "architecture": "ARMv8-A", "full_name": "Vector Compare Less Than", "summary": "Compares elements (<). Alias for VCGT with swapped operands.", "syntax": "VCLT.
, , ", "encoding": { "format": "NEON Alias", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 0011 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2000300", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "U", "clean": "U" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0011", "clean": "0011" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Vector Compare Less Than is an alias that performs signed element-wise comparison on 128-bit SIMD registers with operands swapped relative to VCGT. For each element in Qn, if it is strictly less than the corresponding element in Qm, the result element in Qd is set to all 1s; otherwise, it is set to all 0s. No condition flags are affected. This is a NEON instruction available in both A32 and T32 states.", "example": "VCLT.dt q0, q1, q2", "pseudocode": "for i = 0 to (128 / element_size) - 1 do\n if Qn[i] < Qm[i] then\n Qd[i] ← all_ones\n else\n Qd[i] ← all_zeros\n end if\nend for" }, { "mnemonic": "vcls", "architecture": "ARMv8-A", "full_name": "Vector Count Leading Sign Bits", "summary": "Counts number of consecutive sign bits.", "syntax": "VCLS.
, ", "encoding": { "format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 00 | Vd | 0 | 1000 | 1 | M | 0 | Vm", "hex_opcode": "0xF3B00440", "visual_parts": [ { "raw": "111100111", "clean": "111100111" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "size", "clean": "size" }, { "raw": "00", "clean": "00" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0", "clean": "0" }, { "raw": "1000", "clean": "1000" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Vector Count Leading Sign Bits counts the number of consecutive sign bits (bits matching the sign bit) in each element of the source register. For each integer element in Qm, the result in Qd is the count of leading sign bits. The data type determines element size (8, 16, or 32 bits). No condition flags are affected. This is a NEON instruction available in both A32 and T32 states.", "example": "VCLS.dt q0, q2", "pseudocode": "for i = 0 to (128 / element_size) - 1 do\n sign_bit ← Qm[i] >> (element_size - 1)\n count ← 0\n for j = element_size - 2 downto 0 do\n if (Qm[i] >> j) & 1 == sign_bit then\n count ← count + 1\n else\n break\n end if\n end for\n Qd[i] ← count\nend for" }, { "mnemonic": "vclz", "architecture": "ARMv8-A", "full_name": "Vector Count Leading Zeros", "summary": "Counts number of consecutive zeros.", "syntax": "VCLZ.
, ", "encoding": { "format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 00 | Vd | 0 | 1001 | 1 | M | 0 | Vm", "hex_opcode": "0xF3B004C0", "visual_parts": [ { "raw": "111100111", "clean": "111100111" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "size", "clean": "size" }, { "raw": "00", "clean": "00" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0", "clean": "0" }, { "raw": "1001", "clean": "1001" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Vector Count Leading Zeros counts the number of consecutive zero bits from the most significant bit in each element of the source register. For each integer element in Qm, the result in Qd is the count of leading zeros. The data type determines element size (8, 16, or 32 bits). No condition flags are affected. This is a NEON instruction available in both A32 and T32 states.", "example": "VCLZ.dt q0, q2", "pseudocode": "for i = 0 to (128 / element_size) - 1 do\n count ← 0\n for j = element_size - 1 downto 0 do\n if (Qm[i] >> j) & 1 == 0 then\n count ← count + 1\n else\n break\n end if\n end for\n Qd[i] ← count\nend for" }, { "mnemonic": "vcnt", "architecture": "ARMv8-A", "full_name": "Vector Count Set Bits", "summary": "Population count (number of 1s) per byte.", "syntax": "VCNT.8 , ", "encoding": { "format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 00 | Vd | 0 | 1010 | 0 | M | 0 | Vm", "hex_opcode": "0xF3B00500", "visual_parts": [ { "raw": "111100111", "clean": "111100111" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "size", "clean": "size" }, { "raw": "00", "clean": "00" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0", "clean": "0" }, { "raw": "1010", "clean": "1010" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Vector Count Set Bits (population count) counts the number of set (1) bits in each 8-bit element of the source register. For each byte element in Qm, the result in Qd is the count of set bits within that byte. The data type is always .8 (8-bit elements). No condition flags are affected. This is a NEON instruction available in both A32 and T32 states.", "example": "VCNT.8 q0, q2", "pseudocode": "for i = 0 to 15 do\n count ← 0\n for j = 0 to 7 do\n if (Qm[8*i + j] & (1 << j)) != 0 then\n count ← count + 1\n end if\n end for\n Qd[8*i..8*i+7] ← count\nend for" }, { "mnemonic": "vdup", "architecture": "ARMv8-A", "full_name": "Vector Duplicate (Scalar)", "summary": "Duplicates a scalar value to all lanes of a vector.", "syntax": "VDUP.
, ", "encoding": { "format": "NEON Scalar", "binary_pattern": "111100111 | D | 11 | imm4 | Vd | 11 | 000 | 0 | M | 0 | Vm", "hex_opcode": "0xF3B00C00", "visual_parts": [ { "raw": "111100111", "clean": "111100111" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "imm4", "clean": "imm4" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "11", "clean": "11" }, { "raw": "000", "clean": "000" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Dm[x]", "desc": "Scalar" } ], "extension": "NEON (SIMD)", "description": "Duplicates a scalar value from a lane of a NEON register to all lanes of a destination vector. The scalar is extracted from the indexed lane of Dm based on the element size, then broadcast to fill all lanes of Qd. No condition flags are affected. This is an ARMv7 Advanced SIMD (NEON) instruction, executable in both A32 and T32 states.", "example": "VDUP.dt q0, Dm[x]", "pseudocode": "lane_index ← imm4\nelement_size ← dt_in_bits\nscalar_value ← Dm[lane_index]\nfor i = 0 to (128 / element_size - 1)\n Qd[i] ← scalar_value" }, { "mnemonic": "veor", "architecture": "ARMv8-A", "full_name": "Vector Exclusive OR", "summary": "Bitwise XOR of two vectors.", "syntax": "VEOR , , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | 1 | 0 | D | 00 | Vn | Vd | 0001 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF3000110", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "00", "clean": "00" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0001", "clean": "0001" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Performs a bitwise exclusive OR (XOR) of corresponding lanes in two 128-bit NEON vectors and stores the result in the destination. Each lane of Qn is XORed with the corresponding lane of Qm, producing Qd. No condition flags are affected. This is an ARMv7 Advanced SIMD instruction, executable in both A32 and T32 states.", "example": "VEOR q0, q1, q2", "pseudocode": "for i = 0 to 127\n Qd[i] ← Qn[i] XOR Qm[i]" }, { "mnemonic": "vext", "architecture": "ARMv8-A", "full_name": "Vector Extract", "summary": "Extracts a new vector from a pair of vectors (Sliding window).", "syntax": "VEXT.8 , , , #", "encoding": { "format": "NEON Extract", "binary_pattern": "111100101 | D | 11 | Vn | Vd | imm4 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2B00000", "visual_parts": [ { "raw": "111100101", "clean": "111100101" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "imm4", "clean": "imm4" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "Low Src" }, { "name": "Qm", "desc": "High Src" }, { "name": "imm", "desc": "Byte Offset" } ], "extension": "NEON (SIMD)", "description": "Extracts a contiguous sequence of bytes from the concatenation of two 128-bit NEON vectors and stores the result in the destination. The vectors Qn and Qm are logically concatenated, then bytes [imm:imm+15] are extracted to form Qd. All operations are on 8-bit granularity. No condition flags are affected. This is an ARMv7 Advanced SIMD instruction, executable in both A32 and T32 states.", "example": "VEXT.8 q0, q1, q2, #16", "pseudocode": "combined ← (Qn << (imm * 8)) | (Qm >> ((16 - imm) * 8))\nQd ← combined[127:0]\nfor i = 0 to 15\n Qd[8*i+7:8*i] ← (Qn || Qm)[8*(imm+i)+7:8*(imm+i)]" }, { "mnemonic": "vhadd", "architecture": "ARMv8-A", "full_name": "Vector Halving Add", "summary": "Add elements and shift right by 1 (Average).", "syntax": "VHADD.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 00 | 0 | 0 | N | 1 | M | 0 | Vm", "hex_opcode": "0xF2000040", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "U", "clean": "U" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "00", "clean": "00" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "N", "clean": "N" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Adds corresponding elements of two 128-bit NEON vectors and right-shifts the result by 1 bit (rounded toward zero), effectively computing the average. The operation is performed element-wise according to the data type. No condition flags are affected. This is an ARMv7 Advanced SIMD instruction, executable in both A32 and T32 states.", "example": "VHADD.dt q0, q1, q2", "pseudocode": "for each lane i of size specified by dt\n sum ← Qn[i] + Qm[i]\n Qd[i] ← sum >> 1" }, { "mnemonic": "vhsub", "architecture": "ARMv8-A", "full_name": "Vector Halving Subtract", "summary": "Subtract elements and shift right by 1.", "syntax": "VHSUB.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 00 | 1 | 0 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2000200", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "U", "clean": "U" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Subtracts corresponding elements of two 128-bit NEON vectors and right-shifts the result by 1 bit (rounded toward zero). The operation is performed element-wise according to the data type. No condition flags are affected. This is an ARMv7 Advanced SIMD instruction, executable in both A32 and T32 states.", "example": "VHSUB.dt q0, q1, q2", "pseudocode": "for each lane i of size specified by dt\n diff ← Qn[i] - Qm[i]\n Qd[i] ← diff >> 1" }, { "mnemonic": "vld1", "architecture": "ARMv8-A", "full_name": "Vector Load Multiple (Single Element)", "summary": "Loads vector data from memory (interleaved or sequential).", "syntax": "VLD1. , []{!}", "encoding": { "format": "NEON Load", "binary_pattern": "111101001 | D | 1 | 0 | Rn | Vd | 00 | 00 | index_align | 1101", "hex_opcode": "0xF4A0000D", "visual_parts": [ { "raw": "111101001", "clean": "111101001" }, { "raw": "D", "clean": "D" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "00", "clean": "00" }, { "raw": "00", "clean": "00" }, { "raw": "index_align", "clean": "index_align" }, { "raw": "1101", "clean": "1101" } ], "bit_positions": "31:23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:10 | 9:8 | 7:4 | 3:0" }, "operands": [ { "name": "list", "desc": "Dest Registers" }, { "name": "Rn", "desc": "First source / base general-purpose register" } ], "extension": "NEON (SIMD)", "description": "Loads one or more NEON vectors from memory at an address specified by a general-purpose register, with optional post-index update. The instruction supports contiguous or strided loading patterns depending on the type field. No condition flags are affected. This is an ARMv7 Advanced SIMD memory instruction, executable in both A32 and T32 states.", "example": "VLD1.size {r0-r3}, [r1]!", "pseudocode": "address ← Rn\nfor each register in list\n load vector from address\n address ← address + stride\nif writeback\n Rn ← Rn + total_bytes_loaded" }, { "mnemonic": "vld2", "architecture": "ARMv8-A", "full_name": "Vector Load Multiple (2-Element Structure)", "summary": "De-interleaves 2 streams of data while loading.", "syntax": "VLD2. , []{!}", "encoding": { "format": "NEON Load", "binary_pattern": "111101001 | D | 1 | 0 | Rn | Vd | 00 | 01 | index_align | 1101", "hex_opcode": "0xF4A0010D", "visual_parts": [ { "raw": "111101001", "clean": "111101001" }, { "raw": "D", "clean": "D" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "00", "clean": "00" }, { "raw": "01", "clean": "01" }, { "raw": "index_align", "clean": "index_align" }, { "raw": "1101", "clean": "1101" } ], "bit_positions": "31:23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:10 | 9:8 | 7:4 | 3:0" }, "operands": [ { "name": "list", "desc": "Dest Registers" }, { "name": "Rn", "desc": "First source / base general-purpose register" } ], "extension": "NEON (SIMD)", "description": "Loads two streams of interleaved data from memory and de-interleaves them into separate 128-bit NEON vectors. The instruction handles 2-element structures, reading from memory and distributing elements to the destination registers in a de-interleaved pattern. No condition flags are affected. This is an ARMv7 Advanced SIMD memory instruction, executable in both A32 and T32 states.", "example": "VLD2.size {r0-r3}, [r1]!", "pseudocode": "address ← Rn\nfor each 2-element structure at address\n element0 ← memory[address]\n element1 ← memory[address + size_bytes]\n store element0 in first destination register\n store element1 in second destination register\n address ← address + 2 * size_bytes\nif writeback\n Rn ← Rn + total_bytes_loaded" }, { "mnemonic": "vmax", "architecture": "ARMv8-A", "full_name": "Vector Maximum", "summary": "Selects maximum value from elements.", "syntax": "VMAX.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 0110 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2000600", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "U", "clean": "U" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0110", "clean": "0110" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Compares corresponding lanes of two 128-bit NEON vectors and stores the maximum value in each lane of the destination. The comparison is performed element-wise according to the data type (signed or unsigned integer). No condition flags are affected. This is an ARMv7 Advanced SIMD instruction, executable in both A32 and T32 states.", "example": "VMAX.dt q0, q1, q2", "pseudocode": "for each lane i of size specified by dt\n if Qn[i] > Qm[i]\n Qd[i] ← Qn[i]\n else\n Qd[i] ← Qm[i]" }, { "mnemonic": "vmin", "architecture": "ARMv8-A", "full_name": "Vector Minimum", "summary": "Selects minimum value from elements.", "syntax": "VMIN.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 0110 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2000610", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "U", "clean": "U" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0110", "clean": "0110" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Performs element-wise minimum operation on two 128-bit SIMD registers, selecting the smaller value from each corresponding pair of elements. The data type (sz field) determines whether elements are 32-bit or 16-bit integers. Condition flags N, Z, C, V are unaffected. This is an A32/T32 NEON instruction with no privilege restrictions.", "example": "VMIN.dt q0, q1, q2", "pseudocode": "for i = 0 to (128 / element_width) - 1:\n Qd[i] ← min(Qn[i], Qm[i])" }, { "mnemonic": "vmla", "architecture": "ARMv8-A", "full_name": "Vector Multiply Accumulate", "summary": "Multiplies and adds to accumulator.", "syntax": "VMLA.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 0 | D | size | Vn | Vd | 1001 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2000900", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1001", "clean": "1001" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Dest/Acc" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Multiplies corresponding elements from two source registers and accumulates (adds) the products into the destination register. Performs Qd ← Qd + (Qn × Qm) for each element. The sz field specifies 16-bit or 32-bit element width. Condition flags are unaffected. This is an A32/T32 NEON instruction with no privilege restrictions.", "example": "VMLA.dt q0, q1, q2", "pseudocode": "for i = 0 to (128 / element_width) - 1:\n product ← Qn[i] × Qm[i]\n Qd[i] ← Qd[i] + product" }, { "mnemonic": "vmls", "architecture": "ARMv8-A", "full_name": "Vector Multiply Subtract", "summary": "Multiplies and subtracts from accumulator.", "syntax": "VMLS.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 0 | D | 1 | sz | Vn | Vd | 1101 | N | 1 | M | 1 | Vm", "hex_opcode": "0xF2200D50", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "1", "clean": "1" }, { "raw": "sz", "clean": "sz" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1101", "clean": "1101" }, { "raw": "N", "clean": "N" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Dest/Acc" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Multiplies corresponding elements from two source registers and subtracts the products from the accumulator. Performs Qd ← Qd - (Qn × Qm) for each element. The sz field specifies 16-bit or 32-bit element width. Condition flags are unaffected. This is an A32/T32 NEON instruction with no privilege restrictions.", "example": "VMLS.dt q0, q1, q2", "pseudocode": "for i = 0 to (128 / element_width) - 1:\n product ← Qn[i] × Qm[i]\n Qd[i] ← Qd[i] - product" }, { "mnemonic": "vmov", "architecture": "ARMv8-A", "full_name": "Vector Move (Immediate)", "summary": "Moves immediate value into vector.", "syntax": "VMOV.
, #", "encoding": { "format": "NEON Imm", "binary_pattern": "1111001 | i | 1 | D | 000 | imm3 | Vd | cmode | 0 | 0 | 0 | 1 | imm4", "hex_opcode": "0xF2800010", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "i", "clean": "i" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "000", "clean": "000" }, { "raw": "imm3", "clean": "imm3" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "cmode", "clean": "cmode" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "imm4", "clean": "imm4" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:19 | 18:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "imm", "desc": "Value" } ], "extension": "NEON (SIMD)", "description": "Vector Move (Immediate) moves an immediate value into all elements of a 128-bit NEON register. The immediate is replicated across elements according to the data type (8, 16, 32, or 64 bits) and element expansion mode (cmode). No flags are affected. This is a NEON instruction available in both A32 and T32 states when NEON is supported.", "example": "VMOV.dt q0, #16", "pseudocode": "imm_expanded ← ExpandImmediate(imm, cmode)\nfor each element i in Qd:\n Qd[i] ← imm_expanded" }, { "mnemonic": "vmovl", "architecture": "ARMv8-A", "full_name": "Vector Move Long", "summary": "Copies N-bit elements to 2N-bit elements (Widening).", "syntax": "VMOVL.
, ", "encoding": { "format": "NEON 2-Reg", "binary_pattern": "1111001 | U | 1 | D | imm3H | 000 | Vd | 1010 | 0 | 0 | M | 1 | Vm", "hex_opcode": "0xF2800A10", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "U", "clean": "U" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "imm3H", "clean": "imm3H" }, { "raw": "000", "clean": "000" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1010", "clean": "1010" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:19 | 18:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Dest Wide" }, { "name": "Dm", "desc": "Src Narrow" } ], "extension": "NEON (SIMD)", "description": "Widens N-bit elements from a 64-bit source register to 2N-bit elements in a 128-bit destination register, with zero or sign extension based on the data type. The Q field and element size encoding determine which half of the source to use and the widening operation. Condition flags are unaffected. This is an A32/T32 NEON instruction with no privilege restrictions.", "example": "VMOVL.dt q0, d2", "pseudocode": "for i = 0 to (64 / source_element_width) - 1:\n Qd[i] ← ZeroExtend(Dm[i]) or SignExtend(Dm[i])" }, { "mnemonic": "vmovn", "architecture": "ARMv8-A", "full_name": "Vector Move Narrow", "summary": "Copies 2N-bit elements to N-bit elements (Narrowing).", "syntax": "VMOVN.
, ", "encoding": { "format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 10 | Vd | 0 | 0100 | 0 | M | 0 | Vm", "hex_opcode": "0xF3B20200", "visual_parts": [ { "raw": "111100111", "clean": "111100111" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "size", "clean": "size" }, { "raw": "10", "clean": "10" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0", "clean": "0" }, { "raw": "0100", "clean": "0100" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Dd", "desc": "Dest Narrow" }, { "name": "Qm", "desc": "Src Wide" } ], "extension": "NEON (SIMD)", "description": "Narrows 2N-bit elements from a 128-bit source register to N-bit elements in a 64-bit destination register, discarding the upper bits. The sz field determines the source element size (16, 32, or 64 bits) and corresponding destination size. Condition flags are unaffected. This is an A32/T32 NEON instruction with no privilege restrictions.", "example": "VMOVN.dt d0, q2", "pseudocode": "for i = 0 to (128 / source_element_width) - 1:\n Dd[i] ← Qm[i][destination_element_width-1:0]" }, { "mnemonic": "vmul", "architecture": "ARMv8-A", "full_name": "Vector Multiply", "summary": "Multiplies elements.", "syntax": "VMUL.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | op | 0 | D | size | Vn | Vd | 1001 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2000910", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "op", "clean": "op" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1001", "clean": "1001" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Performs element-wise multiplication of two 128-bit SIMD registers, storing results in the destination. The sz field determines 16-bit or 32-bit element width. Condition flags N, Z, C, V are unaffected. This is an A32/T32 NEON instruction with no privilege restrictions.", "example": "VMUL.dt q0, q1, q2", "pseudocode": "for i = 0 to (128 / element_width) - 1:\n Qd[i] ← Qn[i] × Qm[i]" }, { "mnemonic": "vmull", "architecture": "ARMv8-A", "full_name": "Vector Multiply Long", "summary": "Multiplies N-bit elements producing 2N-bit results.", "syntax": "VMULL.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 1 | D | size | Vn | Vd | 11 | op | 0 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2800C00", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "U", "clean": "U" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "11", "clean": "11" }, { "raw": "op", "clean": "op" }, { "raw": "0", "clean": "0" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Dest Wide" }, { "name": "Dn", "desc": "First source 64-bit SIMD/FP register" }, { "name": "Dm", "desc": "Second source 64-bit SIMD/FP register" } ], "extension": "NEON (SIMD)", "description": "Multiplies N-bit elements from two 64-bit source registers to produce 2N-bit results in a 128-bit destination register. The sz field specifies 8, 16, or 32-bit source element width. Condition flags are unaffected. This is an A32/T32 NEON instruction with no privilege restrictions.", "example": "VMULL.dt q0, d1, d2", "pseudocode": "for i = 0 to (64 / source_element_width) - 1:\n Qd[i] ← Dn[i] × Dm[i]" }, { "mnemonic": "vmvn", "architecture": "ARMv8-A", "full_name": "Vector Move NOT", "summary": "Moves bitwise inverse of immediate/register.", "syntax": "VMVN , ", "encoding": { "format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 00 | Vd | 0 | 1011 | 0 | M | 0 | Vm", "hex_opcode": "0xF3B00580", "visual_parts": [ { "raw": "111100111", "clean": "111100111" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "size", "clean": "size" }, { "raw": "00", "clean": "00" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0", "clean": "0" }, { "raw": "1011", "clean": "1011" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Performs bitwise NOT (inversion) of all bits in a 128-bit SIMD register, storing the result in the destination. This is a data-type-independent operation that works on all bit patterns equally. Condition flags are unaffected. This is an A32/T32 NEON instruction with no privilege restrictions.", "example": "VMVN q0, q2", "pseudocode": "Qd ← ~Qm" }, { "mnemonic": "vneg", "architecture": "ARMv8-A", "full_name": "Vector Negate", "summary": "Negates integer/float elements.", "syntax": "VNEG.
, ", "encoding": { "format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 01 | Vd | 0 | F | 111 | 0 | M | 0 | Vm", "hex_opcode": "0xF3B10380", "visual_parts": [ { "raw": "111100111", "clean": "111100111" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "size", "clean": "size" }, { "raw": "01", "clean": "01" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0", "clean": "0" }, { "raw": "F", "clean": "F" }, { "raw": "111", "clean": "111" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10 | 9:7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Negates each element in the source vector and places the result in the destination register. For integer elements, the result is two's complement negation; for floating-point elements, only the sign bit is inverted. No condition flags are affected. Execution is available in both A32 and T32 instruction sets via NEON.", "example": "VNEG.dt q0, q2", "pseudocode": "for i = 0 to elements-1\n Qd[i] ← -Qm[i]" }, { "mnemonic": "vorn", "architecture": "ARMv8-A", "full_name": "Vector OR NOT", "summary": "Bitwise OR with NOT (Vd = Vn | ~Vm).", "syntax": "VORN , , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 0 | D | 11 | Vn | Vd | 0001 | N | 1 | M | 1 | Vm", "hex_opcode": "0xF2300150", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0001", "clean": "0001" }, { "raw": "N", "clean": "N" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Performs bitwise OR of the first operand with the bitwise NOT of the second operand (Qd = Qn | ~Qm), element-wise. No condition flags are affected. Execution is available in both A32 and T32 instruction sets via NEON.", "example": "VORN q0, q1, q2", "pseudocode": "for i = 0 to 127\n Qd[i] ← Qn[i] | ~Qm[i]" }, { "mnemonic": "vorr", "architecture": "ARMv8-A", "full_name": "Vector Logical OR", "summary": "Bitwise OR of two vectors.", "syntax": "VORR , , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 0 | D | 10 | Vn | Vd | 0001 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2200110", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "10", "clean": "10" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0001", "clean": "0001" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Performs bitwise OR of two vectors element-wise (Qd = Qn | Qm). No condition flags are affected. Execution is available in both A32 and T32 instruction sets via NEON.", "example": "VORR q0, q1, q2", "pseudocode": "for i = 0 to 127\n Qd[i] ← Qn[i] | Qm[i]" }, { "mnemonic": "vpadd", "architecture": "ARMv8-A", "full_name": "Vector Pairwise Add", "summary": "Adds adjacent pairs of elements.", "syntax": "VPADD.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 0 | D | size | Vn | Vd | 1011 | N | Q | M | 1 | Vm", "hex_opcode": "0xF2000B10", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1011", "clean": "1011" }, { "raw": "N", "clean": "N" }, { "raw": "Q", "clean": "Q" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Dd", "desc": "Destination 64-bit SIMD/FP register" }, { "name": "Dn", "desc": "First source 64-bit SIMD/FP register" }, { "name": "Dm", "desc": "Second source 64-bit SIMD/FP register" } ], "extension": "NEON (SIMD)", "description": "Adds adjacent pairs of elements from the source operands and places the results in the destination register, reducing dimensionality by half. For example, in 32-bit mode, pairs of adjacent 32-bit elements are summed to produce 4 results in the 64-bit destination. No condition flags are affected. Execution is available in both A32 and T32 instruction sets via NEON.", "example": "VPADD.dt d0, d1, d2", "pseudocode": "case dt of\n when I8: for i = 0 to 3: Dd[i] ← Dn[2*i] + Dn[2*i+1] + Dm[2*i] + Dm[2*i+1]\n when I16: for i = 0 to 1: Dd[i] ← Dn[2*i] + Dn[2*i+1] + Dm[2*i] + Dm[2*i+1]\n when I32: Dd[0] ← Dn[0] + Dn[1]; Dd[1] ← Dm[0] + Dm[1]\n when F32: Dd[0] ← Dn[0] + Dn[1]; Dd[1] ← Dm[0] + Dm[1]" }, { "mnemonic": "vpmin", "architecture": "ARMv8-A", "full_name": "Vector Pairwise Minimum", "summary": "Minimum of adjacent pairs.", "syntax": "VPMIN.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 1010 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2000A10", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "U", "clean": "U" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1010", "clean": "1010" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Dd", "desc": "Destination 64-bit SIMD/FP register" }, { "name": "Dn", "desc": "First source 64-bit SIMD/FP register" }, { "name": "Dm", "desc": "Second source 64-bit SIMD/FP register" } ], "extension": "NEON (SIMD)", "description": "Computes the minimum of adjacent pairs of elements from the source operands and places the results in the destination register, reducing dimensionality by half. For each pair, the smaller element is selected. No condition flags are affected. Execution is available in both A32 and T32 instruction sets via NEON.", "example": "VPMIN.dt d0, d1, d2", "pseudocode": "case dt of\n when I8: for i = 0 to 3: Dd[i] ← min(Dn[2*i], Dn[2*i+1], Dm[2*i], Dm[2*i+1])\n when I16: for i = 0 to 1: Dd[i] ← min(Dn[2*i], Dn[2*i+1], Dm[2*i], Dm[2*i+1])\n when I32: Dd[0] ← min(Dn[0], Dn[1]); Dd[1] ← min(Dm[0], Dm[1])\n when F32: Dd[0] ← min(Dn[0], Dn[1]); Dd[1] ← min(Dm[0], Dm[1])" }, { "mnemonic": "vpmax", "architecture": "ARMv8-A", "full_name": "Vector Pairwise Maximum", "summary": "Maximum of adjacent pairs.", "syntax": "VPMAX.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 1010 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2000A00", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "U", "clean": "U" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1010", "clean": "1010" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Dd", "desc": "Destination 64-bit SIMD/FP register" }, { "name": "Dn", "desc": "First source 64-bit SIMD/FP register" }, { "name": "Dm", "desc": "Second source 64-bit SIMD/FP register" } ], "extension": "NEON (SIMD)", "description": "Computes the maximum of adjacent pairs of elements from the source operands and places the results in the destination register, reducing dimensionality by half. For each pair, the larger element is selected. No condition flags are affected. Execution is available in both A32 and T32 instruction sets via NEON.", "example": "VPMAX.dt d0, d1, d2", "pseudocode": "case dt of\n when I8: for i = 0 to 3: Dd[i] ← max(Dn[2*i], Dn[2*i+1], Dm[2*i], Dm[2*i+1])\n when I16: for i = 0 to 1: Dd[i] ← max(Dn[2*i], Dn[2*i+1], Dm[2*i], Dm[2*i+1])\n when I32: Dd[0] ← max(Dn[0], Dn[1]); Dd[1] ← max(Dm[0], Dm[1])\n when F32: Dd[0] ← max(Dn[0], Dn[1]); Dd[1] ← max(Dm[0], Dm[1])" }, { "mnemonic": "vqadd", "architecture": "ARMv8-A", "full_name": "Vector Saturating Add", "summary": "Adds elements with saturation.", "syntax": "VQADD.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 0000 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2000010", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "U", "clean": "U" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0000", "clean": "0000" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Adds corresponding elements from two vectors with saturation. If the result overflows or underflows, it is saturated to the data type's maximum or minimum representable value. No condition flags are affected; saturation status is not reflected in APSR. Execution is available in both A32 and T32 instruction sets via NEON.", "example": "VQADD.dt q0, q1, q2", "pseudocode": "for i = 0 to elements-1\n Qd[i] ← SatQ(Qn[i] + Qm[i], dt)" }, { "mnemonic": "vqsub", "architecture": "ARMv8-A", "full_name": "Vector Saturating Subtract", "summary": "Subtracts elements with saturation.", "syntax": "VQSUB.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 0010 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2000210", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "U", "clean": "U" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0010", "clean": "0010" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Subtracts the second operand from the first with saturation. If the result overflows or underflows, it is saturated to the data type's maximum or minimum representable value. No condition flags are affected; saturation status is not reflected in APSR. Execution is available in both A32 and T32 instruction sets via NEON.", "example": "VQSUB.dt q0, q1, q2", "pseudocode": "for i = 0 to elements-1\n Qd[i] ← SatQ(Qn[i] - Qm[i], dt)" }, { "mnemonic": "vrecpe", "architecture": "ARMv8-A", "full_name": "Vector Reciprocal Estimate", "summary": "Estimates reciprocal (1/x).", "syntax": "VRECPE.
, ", "encoding": { "format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 11 | Vd | 0 | 10 | F | 0 | 1 | M | 0 | Vm", "hex_opcode": "0xF3B30440", "visual_parts": [ { "raw": "111100111", "clean": "111100111" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "size", "clean": "size" }, { "raw": "11", "clean": "11" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0", "clean": "0" }, { "raw": "10", "clean": "10" }, { "raw": "F", "clean": "F" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:9 | 8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Computes a vector reciprocal estimate (1/x) for each element in the source register and stores the result in the destination register. This is a Newton-Raphson reciprocal estimate; the result is not fully accurate and is intended as a starting point for iterative refinement. Condition flags (N, Z, C, V) are not affected. Executes in A32/T32 with NEON extension; requires FPEXC.EN = 1 for floating-point operation.", "example": "VRECPE.dt q0, q2", "pseudocode": "for i = 0 to 127 by element_size:\n element ← Vm[i+element_size-1:i]\n Qd[i+element_size-1:i] ← RecipEstimate(element)" }, { "mnemonic": "vrsqrte", "architecture": "ARMv8-A", "full_name": "Vector Reciprocal Square Root Estimate", "summary": "Estimates reciprocal square root (1/sqrt(x)).", "syntax": "VRSQRTE.
, ", "encoding": { "format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 11 | Vd | 0 | 10 | F | 1 | 1 | M | 0 | Vm", "hex_opcode": "0xF3B304C0", "visual_parts": [ { "raw": "111100111", "clean": "111100111" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "size", "clean": "size" }, { "raw": "11", "clean": "11" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0", "clean": "0" }, { "raw": "10", "clean": "10" }, { "raw": "F", "clean": "F" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:9 | 8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Computes a vector reciprocal square root estimate (1/√x) for each element in the source register and stores the result in the destination register. This is a Newton-Raphson reciprocal square root estimate; the result serves as a starting point for iterative refinement. Condition flags (N, Z, C, V) are not affected. Executes in A32/T32 with NEON extension; requires FPEXC.EN = 1 for floating-point operation.", "example": "VRSQRTE.dt q0, q2", "pseudocode": "for i = 0 to 127 by element_size:\n element ← Qm[i+element_size-1:i]\n Qd[i+element_size-1:i] ← RecipSqrtEstimate(element)" }, { "mnemonic": "vrev16", "architecture": "ARMv8-A", "full_name": "Vector Reverse 16", "summary": "Reverses bytes within 16-bit halfwords.", "syntax": "VREV16.
, ", "encoding": { "format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 00 | Vd | 0 | 00 | 10 | 0 | M | 0 | Vm", "hex_opcode": "0xF3B00100", "visual_parts": [ { "raw": "111100111", "clean": "111100111" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "size", "clean": "size" }, { "raw": "00", "clean": "00" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0", "clean": "0" }, { "raw": "00", "clean": "00" }, { "raw": "10", "clean": "10" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:9 | 8:7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Reverses the byte order within each 16-bit halfword element in the source register. For example, bytes [1,0] become [0,1] within each 16-bit element. Condition flags (N, Z, C, V) are not affected. Executes in A32/T32 with NEON extension; operates on integer data types.", "example": "VREV16.dt q0, q2", "pseudocode": "for i = 0 to 127 by 16:\n for j = 0 to 15 by 8:\n Qd[i+j+7:i+j] ← Qm[i+15-j:i+8-j]" }, { "mnemonic": "vrev32", "architecture": "ARMv8-A", "full_name": "Vector Reverse 32", "summary": "Reverses elements within 32-bit words.", "syntax": "VREV32.
, ", "encoding": { "format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 00 | Vd | 0 | 00 | 01 | 0 | M | 0 | Vm", "hex_opcode": "0xF3B00080", "visual_parts": [ { "raw": "111100111", "clean": "111100111" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "size", "clean": "size" }, { "raw": "00", "clean": "00" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0", "clean": "0" }, { "raw": "00", "clean": "00" }, { "raw": "01", "clean": "01" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:9 | 8:7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Reverses the byte or halfword order within each 32-bit word element in the source register, depending on element size. For 8-bit elements, reverses bytes within words; for 16-bit elements, reverses halfwords within words. Condition flags (N, Z, C, V) are not affected. Executes in A32/T32 with NEON extension; operates on integer data types.", "example": "VREV32.dt q0, q2", "pseudocode": "if element_size == 8:\n for i = 0 to 127 by 32:\n for j = 0 to 31 by 8:\n Qd[i+j+7:i+j] ← Qm[i+31-j:i+24-j]\nelse if element_size == 16:\n for i = 0 to 127 by 32:\n Qd[i+31:i+16] ← Qm[i+15:i+0]\n Qd[i+15:i+0] ← Qm[i+31:i+16]" }, { "mnemonic": "vrev64", "architecture": "ARMv8-A", "full_name": "Vector Reverse 64", "summary": "Reverses elements within 64-bit doublewords.", "syntax": "VREV64.
, ", "encoding": { "format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 00 | Vd | 0 | 00 | 00 | 0 | M | 0 | Vm", "hex_opcode": "0xF3B00000", "visual_parts": [ { "raw": "111100111", "clean": "111100111" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "size", "clean": "size" }, { "raw": "00", "clean": "00" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0", "clean": "0" }, { "raw": "00", "clean": "00" }, { "raw": "00", "clean": "00" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:9 | 8:7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Reverses the order of elements within each 64-bit doubleword in the source register. The granularity of reversal depends on element size: 8-bit elements are reversed within 64-bit units, 16-bit elements are reversed within 64-bit units, and 32-bit elements are reversed within 64-bit units. Condition flags (N, Z, C, V) are not affected. Executes in A32/T32 with NEON extension; operates on integer data types.", "example": "VREV64.dt q0, q2", "pseudocode": "if element_size == 8:\n for i = 0 to 127 by 64:\n for j = 0 to 63 by 8:\n Qd[i+j+7:i+j] ← Qm[i+63-j:i+56-j]\nelse if element_size == 16:\n for i = 0 to 127 by 64:\n for j = 0 to 48 by 16:\n Qd[i+j+15:i+j] ← Qm[i+63-j:i+48-j]\nelse if element_size == 32:\n for i = 0 to 127 by 64:\n Qd[i+63:i+32] ← Qm[i+31:i+0]\n Qd[i+31:i+0] ← Qm[i+63:i+32]" }, { "mnemonic": "vshl", "architecture": "ARMv8-A", "full_name": "Vector Shift Left (Immediate)", "summary": "Shifts elements left.", "syntax": "VSHL.
, , #", "encoding": { "format": "NEON Shift", "binary_pattern": "1111001 | 0 | 1 | D | imm6 | Vd | 0101 | L | 0 | M | 1 | Vm", "hex_opcode": "0xF2800510", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "imm6", "clean": "imm6" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0101", "clean": "0101" }, { "raw": "L", "clean": "L" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" }, { "name": "imm", "desc": "Signed immediate value" } ], "extension": "NEON (SIMD)", "description": "Shifts each element in the source register left by an immediate number of bits and stores the result in the destination register. Bits shifted out of the left end are lost, and zeros are shifted in from the right. The shift amount is applied uniformly to all elements and is encoded in the imm6 field, with the interpretation dependent on element size (sz). Condition flags (N, Z, C, V) are not affected. Executes in A32/T32 with NEON extension.", "example": "VSHL.dt q0, q2, #16", "pseudocode": "shift_amount ← DecodeImmShift(imm6, sz) // Decodes imm6 based on element size\nfor i = 0 to 127 by element_size:\n element ← Qm[i+element_size-1:i]\n Qd[i+element_size-1:i] ← element << shift_amount" }, { "mnemonic": "vshr", "architecture": "ARMv8-A", "full_name": "Vector Shift Right (Immediate)", "summary": "Shifts elements right.", "syntax": "VSHR.
, , #", "encoding": { "format": "NEON Shift", "binary_pattern": "1111001 | U | 1 | D | imm6 | Vd | 0000 | L | 0 | M | 1 | Vm", "hex_opcode": "0xF2800010", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "U", "clean": "U" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "imm6", "clean": "imm6" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0000", "clean": "0000" }, { "raw": "L", "clean": "L" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" }, { "name": "imm", "desc": "Signed immediate value" } ], "extension": "NEON (SIMD)", "description": "Shifts each element in the source register right by an immediate number of bits, performing a logical (unsigned) or arithmetic (signed) shift depending on the data type, and stores the result in the destination register. For unsigned types, zeros are shifted in from the left; for signed types, the sign bit is extended. Condition flags (N, Z, C, V) are not affected. Executes in A32/T32 with NEON extension.", "example": "VSHR.dt q0, q2, #16", "pseudocode": "shift_amount ← DecodeImmShift(imm6, sz) // Decodes imm6 based on element size\nfor i = 0 to 127 by element_size:\n element ← Qm[i+element_size-1:i]\n if is_signed_type:\n Qd[i+element_size-1:i] ← arithmetic_shift_right(element, shift_amount)\n else:\n Qd[i+element_size-1:i] ← element >> shift_amount" }, { "mnemonic": "vshrn", "architecture": "ARMv8-A", "full_name": "Vector Shift Right Narrow", "summary": "Shifts right and narrows result.", "syntax": "VSHRN.
, , #", "encoding": { "format": "NEON Shift", "binary_pattern": "1111001 | 0 | 1 | D | imm6 | Vd | 1000 | 0 | 0 | M | 1 | Vm", "hex_opcode": "0xF2800810", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "imm6", "clean": "imm6" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1000", "clean": "1000" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Dd", "desc": "Dest Narrow" }, { "name": "Qm", "desc": "Src Wide" }, { "name": "imm", "desc": "Signed immediate value" } ], "extension": "NEON (SIMD)", "description": "Shifts each element in the 128-bit source register right by an immediate number of bits, narrows the result to half-width, and stores the narrowed values in the 64-bit destination register. For example, 16-bit results from 32-bit elements are stored in a 64-bit destination. Condition flags (N, Z, C, V) are not affected. Executes in A32/T32 with NEON extension.", "example": "VSHRN.dt d0, q2, #16", "pseudocode": "shift_amount ← DecodeImmShift(imm6, input_element_size)\noutput_element_size ← input_element_size / 2\nfor i = 0 to 63 by output_element_size:\n element ← Qm[i*2+input_element_size*2-1:i*2]\n shifted ← element >> shift_amount\n Dd[i+output_element_size-1:i] ← shifted[output_element_size-1:0]" }, { "mnemonic": "vst1", "architecture": "ARMv8-A", "full_name": "Vector Store Multiple (Single Element)", "summary": "Stores vector data to memory.", "syntax": "VST1. , []{!}", "encoding": { "format": "NEON Store", "binary_pattern": "111101001 | D | 0 | 0 | Rn | Vd | 00 | 00 | index_align | 1101", "hex_opcode": "0xF480000D", "visual_parts": [ { "raw": "111101001", "clean": "111101001" }, { "raw": "D", "clean": "D" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "00", "clean": "00" }, { "raw": "00", "clean": "00" }, { "raw": "index_align", "clean": "index_align" }, { "raw": "1101", "clean": "1101" } ], "bit_positions": "31:23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:10 | 9:8 | 7:4 | 3:0" }, "operands": [ { "name": "list", "desc": "Src Registers" }, { "name": "Rn", "desc": "First source / base general-purpose register" } ], "extension": "NEON (SIMD)", "description": "Stores one or more NEON vectors to memory at the address held in Rn. The specifies the vector registers to store (1-4 registers), and determines the element width (8, 16, 32, or 64 bits). If ! is present, Rn is post-indexed by the number of bytes stored. No flags are affected. Execution is restricted to A32/T32 with NEON support; privilege level is determined by the memory access.", "example": "VST1.size {r0-r3}, [r1]!", "pseudocode": "address ← Rn\nfor each register in list:\n [address] ← register value (element size as specified)\n address ← address + (register_width_in_bytes)\nif postindex:\n Rn ← Rn + (total_bytes_stored)" }, { "mnemonic": "vsub", "architecture": "ARMv8-A", "full_name": "Vector Subtract (Integer)", "summary": "Subtracts integer elements.", "syntax": "VSUB.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 0 | D | 1 | sz | Vn | Vd | 1101 | N | 1 | M | 0 | Vm", "hex_opcode": "0xF2200D40", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "1", "clean": "1" }, { "raw": "sz", "clean": "sz" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1101", "clean": "1101" }, { "raw": "N", "clean": "N" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Vector Subtract (Integer) performs element-wise subtraction of two NEON 128-bit registers, subtracting corresponding integer elements of size 8, 16, 32, or 64 bits. The instruction executes in Q-register (128-bit) mode and wraps on underflow without setting flags. This is a NEON SIMD instruction available in both A32 and T32 states when NEON is supported.", "example": "VSUB.dt q0, q1, q2", "pseudocode": "for each element i in Qd:\n Qd[i] ← Qn[i] - Qm[i]" }, { "mnemonic": "vtbl", "architecture": "ARMv8-A", "full_name": "Vector Table Lookup", "summary": "Look up elements in a vector table.", "syntax": "VTBL.8
, , ", "encoding": { "format": "NEON Table", "binary_pattern": "111100111 | D | 11 | Vn | Vd | 10 | len | N | 0 | M | 0 | Vm", "hex_opcode": "0xF3B00800", "visual_parts": [ { "raw": "111100111", "clean": "111100111" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "len", "clean": "len" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Dd", "desc": "Destination 64-bit SIMD/FP register" }, { "name": "list", "desc": "Table" }, { "name": "Dm", "desc": "Indices" } ], "extension": "NEON (SIMD)", "description": "Performs a table lookup where each element of Dm is used as an index into the table formed by one or more consecutive NEON registers in , and the corresponding table element is written to Dd. Out-of-range indices produce a zero result. No flags are affected. Execution is restricted to A32/T32 with NEON support; the table may span 1-4 consecutive registers, controlled by the encoding field.", "example": "VTBL.8 d0, {r0-r3}, d2", "pseudocode": "for i ← 0 to (size_of_Dd / 8) - 1:\n index ← Dm[i*8 +: 8]\n if index < (len + 1) * 16:\n Dd[i*8 +: 8] ← table[index]\n else:\n Dd[i*8 +: 8] ← 0" }, { "mnemonic": "vtrn", "architecture": "ARMv8-A", "full_name": "Vector Transpose", "summary": "Transposes elements of two vectors.", "syntax": "VTRN.
, ", "encoding": { "format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 10 | Vd | 0 | 0001 | 1 | M | 0 | Vm", "hex_opcode": "0xF3B200C0", "visual_parts": [ { "raw": "111100111", "clean": "111100111" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "size", "clean": "size" }, { "raw": "10", "clean": "10" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0", "clean": "0" }, { "raw": "0001", "clean": "0001" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Dest/Src1" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Transposes elements of two 128-bit NEON vectors Qd and Qm, swapping odd and even elements. The element size is determined by
(8, 16, or 32 bits). After execution, Qd and Qm contain interleaved even/odd elements from the original vectors. No flags are affected. Execution is restricted to A32/T32 with NEON support.", "example": "VTRN.dt q0, q2", "pseudocode": "temp_d ← Qd\ntemp_m ← Qm\nfor i ← 0 to (128 / element_width) - 1:\n if i is even:\n Qd[i * element_width +: element_width] ← temp_d[i * element_width +: element_width]\n Qm[i * element_width +: element_width] ← temp_m[i * element_width +: element_width]\n else:\n Qd[i * element_width +: element_width] ← temp_m[(i - 1) * element_width +: element_width]\n Qm[i * element_width +: element_width] ← temp_d[(i - 1) * element_width +: element_width]" }, { "mnemonic": "vtst", "architecture": "ARMv8-A", "full_name": "Vector Test Bits", "summary": "Tests if any bits match (Vd = (Vn & Vm) != 0).", "syntax": "VTST.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 0 | D | size | Vn | Vd | 1000 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2000810", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1000", "clean": "1000" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Tests if any bits match by computing (Qn AND Qm) per element and writing all 1s (matching element size) to Qd if the result is nonzero, else all 0s. Element size is determined by
. No arithmetic flags are modified. Execution is restricted to A32/T32 with NEON support.", "example": "VTST.dt q0, q1, q2", "pseudocode": "for i ← 0 to (128 / element_width) - 1:\n result ← Qn[i * element_width +: element_width] AND Qm[i * element_width +: element_width]\n if result != 0:\n Qd[i * element_width +: element_width] ← (element_width bits of 1s)\n else:\n Qd[i * element_width +: element_width] ← 0" }, { "mnemonic": "vuzp", "architecture": "ARMv8-A", "full_name": "Vector Unzip", "summary": "De-interleaves vectors.", "syntax": "VUZP.
, ", "encoding": { "format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 10 | Vd | 0 | 0010 | 1 | M | 0 | Vm", "hex_opcode": "0xF3B20140", "visual_parts": [ { "raw": "111100111", "clean": "111100111" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "size", "clean": "size" }, { "raw": "10", "clean": "10" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0", "clean": "0" }, { "raw": "0010", "clean": "0010" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Dest/Src1" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "De-interleaves elements from two 128-bit NEON vectors by extracting all even-indexed or all odd-indexed elements and placing them into Qd and Qm respectively. Element size is determined by
. No flags are affected. Execution is restricted to A32/T32 with NEON support.", "example": "VUZP.dt q0, q2", "pseudocode": "temp_d ← Qd\ntemp_m ← Qm\nfor i ← 0 to (128 / (2 * element_width)) - 1:\n Qd[i * element_width +: element_width] ← temp_d[(2 * i) * element_width +: element_width]\n Qd[(64 + i) * element_width +: element_width] ← temp_m[(2 * i) * element_width +: element_width]\n Qm[i * element_width +: element_width] ← temp_d[(2 * i + 1) * element_width +: element_width]\n Qm[(64 + i) * element_width +: element_width] ← temp_m[(2 * i + 1) * element_width +: element_width]" }, { "mnemonic": "vzip", "architecture": "ARMv8-A", "full_name": "Vector Zip", "summary": "Interleaves vectors.", "syntax": "VZIP.
, ", "encoding": { "format": "NEON 2-Reg", "binary_pattern": "111100111 | D | 11 | size | 10 | Vd | 0 | 0011 | 1 | M | 0 | Vm", "hex_opcode": "0xF3B201C0", "visual_parts": [ { "raw": "111100111", "clean": "111100111" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "size", "clean": "size" }, { "raw": "10", "clean": "10" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0", "clean": "0" }, { "raw": "0011", "clean": "0011" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Dest/Src1" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Interleaves elements from two 128-bit NEON vectors by mixing even-indexed elements from Qd with odd-indexed elements from Qm and vice versa. Element size is determined by
. No flags are affected. Execution is restricted to A32/T32 with NEON support.", "example": "VZIP.dt q0, q2", "pseudocode": "temp_d ← Qd\ntemp_m ← Qm\nfor i ← 0 to (128 / (2 * element_width)) - 1:\n Qd[2 * i * element_width +: element_width] ← temp_d[i * element_width +: element_width]\n Qd[(2 * i + 1) * element_width +: element_width] ← temp_m[i * element_width +: element_width]\n Qm[2 * i * element_width +: element_width] ← temp_d[(64 + i) * element_width +: element_width]\n Qm[(2 * i + 1) * element_width +: element_width] ← temp_m[(64 + i) * element_width +: element_width]" }, { "mnemonic": "adc", "architecture": "ARMv8-A", "full_name": "Add with Carry", "summary": "Adds two register values and the Carry flag.", "syntax": "ADC , , ", "encoding": { "format": "Data Processing (3-source)", "binary_pattern": "0 | 0 | 0 | 11010000 | Rm | 000000 | Rn | Rd", "hex_opcode": "0x1A000000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11010000", "clean": "11010000" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "000000", "clean": "000000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Wd", "desc": "Dest (32-bit)" }, { "name": "Wn", "desc": "First source / base 32-bit integer register" }, { "name": "Wm", "desc": "Second source / offset 32-bit integer register" } ], "extension": "Base", "description": "Adds Wn and Wm plus the Carry flag (C), placing the 32-bit result in Wd. The C flag is read but not modified by this instruction; use ADCS to update flags. Execution is available in AArch64 only.", "example": "ADC w0, w1, w2", "pseudocode": "result ← Wn + Wm + C\nWd ← result[0:31]" }, { "mnemonic": "adc", "architecture": "ARMv8-A", "full_name": "Add with Carry (64-bit)", "summary": "Adds two 64-bit register values and the Carry flag.", "syntax": "ADC , , ", "encoding": { "format": "Data Processing (3-source)", "binary_pattern": "1 | 0 | 0 | 11010000 | Rm | 000000 | Rn | Rd", "hex_opcode": "0x9A000000", "visual_parts": [ { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11010000", "clean": "11010000" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "000000", "clean": "000000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Xd", "desc": "Dest (64-bit)" }, { "name": "Xn", "desc": "First source / base 64-bit integer register" }, { "name": "Xm", "desc": "Second source / offset 64-bit integer register" } ], "extension": "Base", "description": "Add with Carry adds two 64-bit register values and the Carry flag, storing the result in a 64-bit register. The N, Z, C, and V flags are not modified; use ADCS to update flags. This instruction is AArch64-only and executes at any privilege level.", "example": "ADC x0, x1, x2", "pseudocode": "Xd ← Xn + Xm + C" }, { "mnemonic": "adcs", "architecture": "ARMv8-A", "full_name": "Add with Carry and Set Flags", "summary": "Adds two register values and Carry, updating NZCV flags.", "syntax": "ADCS , , ", "encoding": { "format": "Data Processing (3-source)", "binary_pattern": "0 | 0 | 1 | 11010000 | Rm | 000000 | Rn | Rd", "hex_opcode": "0x3A000000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "11010000", "clean": "11010000" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "000000", "clean": "000000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Wd", "desc": "Destination 32-bit integer register" }, { "name": "Wn", "desc": "First source / base 32-bit integer register" }, { "name": "Wm", "desc": "Second source / offset 32-bit integer register" } ], "extension": "Base", "description": "Adds Wn and Wm plus the Carry flag (C), placing the 32-bit result in Wd and updating the NZCV condition flags. The N, Z, C, and V flags are set based on the result: N if bit 31 is set, Z if the result is zero, C if an unsigned overflow occurs, V if a signed overflow occurs. Execution is available in AArch64 only.", "example": "ADCS w0, w1, w2", "pseudocode": "result ← Wn + Wm + C\nWd ← result[0:31]\nN ← result[31]\nZ ← (result[0:31] == 0)\nC ← result[32] (unsigned overflow)\nV ← (overflow from signed addition)" }, { "mnemonic": "adcs", "architecture": "ARMv8-A", "full_name": "Add with Carry and Set Flags (64-bit)", "summary": "Adds two 64-bit register values and Carry, updating NZCV flags.", "syntax": "ADCS , , ", "encoding": { "format": "Data Processing (3-source)", "binary_pattern": "1 | 0 | 1 | 11010000 | Rm | 000000 | Rn | Rd", "hex_opcode": "0xBA000000", "visual_parts": [ { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "11010000", "clean": "11010000" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "000000", "clean": "000000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Xd", "desc": "Destination 64-bit integer register" }, { "name": "Xn", "desc": "First source / base 64-bit integer register" }, { "name": "Xm", "desc": "Second source / offset 64-bit integer register" } ], "extension": "Base", "description": "Add with Carry and Set Flags adds two 64-bit register values and the Carry flag, updating the NZCV condition flags based on the result. The N flag reflects the sign of the result, Z is set if the result is zero, C is set on unsigned carry, and V is set on signed overflow. This instruction is AArch64-only and executes at any privilege level.", "example": "ADCS x0, x1, x2", "pseudocode": "result ← Xn + Xm + C\nXd ← result\nN ← result[63]\nZ ← (result == 0)\nC ← UnsignedOverflow(Xn, Xm, C)\nV ← SignedOverflow(Xn, Xm, C)" }, { "mnemonic": "add", "architecture": "ARMv8-A", "full_name": "Add (Extended Register)", "summary": "Adds a register value and a sign/zero-extended register value.", "syntax": "ADD , , {, {#}}", "encoding": { "format": "Data Processing (Register)", "binary_pattern": "0 | 0 | 0 | 01011 | 00 | 1 | Rm | option | imm3 | Rn | Rd", "hex_opcode": "0x0B200000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "01011", "clean": "01011" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "option", "clean": "option" }, { "raw": "imm3", "clean": "imm3" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Wd", "desc": "Destination 32-bit integer register" }, { "name": "Wn", "desc": "First source / base 32-bit integer register" }, { "name": "Wm", "desc": "Second source / offset 32-bit integer register" }, { "name": "extend", "desc": "Extension type" } ], "extension": "Base", "description": "Adds a sign/zero-extended 32-bit register value to another 32-bit register and stores the result in the destination register. The extension type and optional shift amount are specified via the extend operand. Condition flags (N, Z, C, V) are not affected by this instruction.", "example": "ADD Wd, Wn, w2", "pseudocode": "Wd ← Wn + ExtendValue(Wm, extend, amount)" }, { "mnemonic": "add", "architecture": "ARMv8-A", "full_name": "Add (Extended Register 64-bit)", "summary": "Adds a 64-bit register and an extended register value.", "syntax": "ADD , , {, {#}}", "encoding": { "format": "Data Processing (Register)", "binary_pattern": "1 | 0 | 0 | 01011 | 00 | 1 | Rm | option | imm3 | Rn | Rd", "hex_opcode": "0x8B200000", "visual_parts": [ { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "01011", "clean": "01011" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "option", "clean": "option" }, { "raw": "imm3", "clean": "imm3" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Xd", "desc": "Destination 64-bit integer register" }, { "name": "Xn", "desc": "First source / base 64-bit integer register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "Base", "description": "Adds a sign/zero-extended 64-bit register value to another 64-bit register and stores the result in the destination register. The extension type and optional shift amount determine how Rm is extended. Condition flags (N, Z, C, V) are not affected by this instruction.", "example": "ADD x0, x1, Rm", "pseudocode": "Xd ← Xn + ExtendValue(Rm, extend, amount)" }, { "mnemonic": "add", "architecture": "ARMv8-A", "full_name": "Add (Immediate)", "summary": "Adds a register value and an immediate value.", "syntax": "ADD , , # {, lsl #}", "encoding": { "format": "Data Processing (Immediate)", "binary_pattern": "0 | 0 | 0 | 100010 | sh | imm12 | Rn | Rd", "hex_opcode": "0x11000000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "100010", "clean": "100010" }, { "raw": "sh", "clean": "sh" }, { "raw": "imm12", "clean": "imm12" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:23 | 22 | 21:10 | 9:5 | 4:0" }, "operands": [ { "name": "Wd", "desc": "Destination 32-bit integer register" }, { "name": "Wn", "desc": "First source / base 32-bit integer register" }, { "name": "imm", "desc": "Immediate (12-bit)" } ], "extension": "Base", "description": "Adds a 12-bit immediate value (optionally shifted left by 0 or 12 bits) to a 32-bit register and stores the result in the destination register. Condition flags (N, Z, C, V) are not affected by this instruction. SP may be used as source or destination.", "example": "ADD Wd, Wn, #16", "pseudocode": "Wd ← Wn + (imm << (sh * 12))" }, { "mnemonic": "add", "architecture": "ARMv8-A", "full_name": "Add (Immediate 64-bit)", "summary": "Adds a 64-bit register value and an immediate value.", "syntax": "ADD , , # {, lsl #}", "encoding": { "format": "Data Processing (Immediate)", "binary_pattern": "1 | 0 | 0 | 100010 | sh | imm12 | Rn | Rd", "hex_opcode": "0x91000000", "visual_parts": [ { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "100010", "clean": "100010" }, { "raw": "sh", "clean": "sh" }, { "raw": "imm12", "clean": "imm12" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:23 | 22 | 21:10 | 9:5 | 4:0" }, "operands": [ { "name": "Xd", "desc": "Destination 64-bit integer register" }, { "name": "Xn", "desc": "First source / base 64-bit integer register" }, { "name": "imm", "desc": "Signed immediate value" } ], "extension": "Base", "description": "Adds a 12-bit immediate value (optionally shifted left by 0 or 12 bits) to a 64-bit register and stores the result in the destination register. Condition flags (N, Z, C, V) are not affected by this instruction. SP may be used as source or destination.", "example": "ADD x0, x1, #16", "pseudocode": "Xd ← Xn + (imm << (sh * 12))" }, { "mnemonic": "add", "architecture": "ARMv8-A", "full_name": "Add (Shifted Register)", "summary": "Adds a register value and a shifted register value.", "syntax": "ADD , , {, #}", "encoding": { "format": "Data Processing (Register)", "binary_pattern": "0 | 0 | 0 | 01011 | shift | 0 | Rm | imm6 | Rn | Rd", "hex_opcode": "0x0B000000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "01011", "clean": "01011" }, { "raw": "shift", "clean": "shift" }, { "raw": "0", "clean": "0" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "imm6", "clean": "imm6" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Wd", "desc": "Destination 32-bit integer register" }, { "name": "Wn", "desc": "First source / base 32-bit integer register" }, { "name": "Wm", "desc": "Second source / offset 32-bit integer register" } ], "extension": "Base", "description": "Adds a shifted 32-bit register value to another 32-bit register and stores the result in the destination register. The shift type and amount are encoded in the imm6 field. Condition flags (N, Z, C, V) are not affected by this instruction.", "example": "ADD w0, w1, w2", "pseudocode": "Wd ← Wn + ShiftReg(Wm, shift_type, shift_amount)" }, { "mnemonic": "add", "architecture": "ARMv8-A", "full_name": "Add (Shifted Register 64-bit)", "summary": "Adds a 64-bit register value and a shifted register value.", "syntax": "ADD , , {, #}", "encoding": { "format": "Data Processing (Register)", "binary_pattern": "1 | 0 | 0 | 01011 | shift | 0 | Rm | imm6 | Rn | Rd", "hex_opcode": "0x8B000000", "visual_parts": [ { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "01011", "clean": "01011" }, { "raw": "shift", "clean": "shift" }, { "raw": "0", "clean": "0" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "imm6", "clean": "imm6" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Xd", "desc": "Destination 64-bit integer register" }, { "name": "Xn", "desc": "First source / base 64-bit integer register" }, { "name": "Xm", "desc": "Second source / offset 64-bit integer register" } ], "extension": "Base", "description": "Adds a shifted 64-bit register value to another 64-bit register and stores the result in the destination register. The shift type and amount are encoded in the imm6 field. Condition flags (N, Z, C, V) are not affected by this instruction.", "example": "ADD x0, x1, x2", "pseudocode": "Xd ← Xn + ShiftReg(Xm, shift_type, shift_amount)" }, { "mnemonic": "adds", "architecture": "ARMv8-A", "full_name": "Add and Set Flags (Extended Register)", "summary": "Adds and updates flags (Extended Register).", "syntax": "ADDS , , {, {#}}", "encoding": { "format": "Data Processing (Register)", "binary_pattern": "0 | 0 | 1 | 01011 | 00 | 1 | Rm | option | imm3 | Rn | Rd", "hex_opcode": "0x2B200000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "01011", "clean": "01011" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "option", "clean": "option" }, { "raw": "imm3", "clean": "imm3" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Wd", "desc": "Destination 32-bit integer register" }, { "name": "Wn", "desc": "First source / base 32-bit integer register" }, { "name": "Wm", "desc": "Second source / offset 32-bit integer register" } ], "extension": "Base", "description": "Add and Set Flags adds a 32-bit register value (optionally extended or shifted) to a 32-bit register or stack pointer, updating the NZCV condition flags. The N flag reflects the sign of the result, Z is set if result is zero, C is set on unsigned carry, and V is set on signed overflow. This instruction is AArch64-only and executes at any privilege level.", "example": "ADDS w0, Wn, w2", "pseudocode": "shifted ← ExtendAndShift(Wm, option, imm3)\nresult ← Wn + shifted\nWd ← result\nN ← result[31]\nZ ← (result == 0)\nC ← UnsignedOverflow(Wn, shifted)\nV ← SignedOverflow(Wn, shifted)" }, { "mnemonic": "adds", "architecture": "ARMv8-A", "full_name": "Add and Set Flags (Extended Register 64-bit)", "summary": "Adds and updates flags (Extended Register 64-bit).", "syntax": "ADDS , , {, {#}}", "encoding": { "format": "Data Processing (Register)", "binary_pattern": "1 | 0 | 1 | 01011 | 00 | 1 | Rm | option | imm3 | Rn | Rd", "hex_opcode": "0xAB200000", "visual_parts": [ { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "01011", "clean": "01011" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "option", "clean": "option" }, { "raw": "imm3", "clean": "imm3" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Xd", "desc": "Destination 64-bit integer register" }, { "name": "Xn", "desc": "First source / base 64-bit integer register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "Base", "description": "Add with extended register operand and set condition flags. Adds the sign-extended or zero-extended value of Rm to Xn, stores the result in Xd, and updates the N, Z, C, and V flags based on the result. AArch64-only instruction executing at any privilege level.", "example": "ADDS x0, x1, Rm", "pseudocode": "result ← Xn + ExtendValue(Rm, extend, amount)\nXd ← result\nN ← result[63]\nZ ← (result == 0)\nC ← CarryOut(Xn, ExtendValue(Rm, extend, amount))\nV ← OverflowFrom(Xn, ExtendValue(Rm, extend, amount))" }, { "mnemonic": "adds", "architecture": "ARMv8-A", "full_name": "Add and Set Flags (Immediate)", "summary": "Adds immediate and updates flags.", "syntax": "ADDS , , # {, lsl #}", "encoding": { "format": "Data Processing (Immediate)", "binary_pattern": "0 | 0 | 1 | 100010 | sh | imm12 | Rn | Rd", "hex_opcode": "0x31000000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "100010", "clean": "100010" }, { "raw": "sh", "clean": "sh" }, { "raw": "imm12", "clean": "imm12" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:23 | 22 | 21:10 | 9:5 | 4:0" }, "operands": [ { "name": "Wd", "desc": "Destination 32-bit integer register" }, { "name": "Wn", "desc": "First source / base 32-bit integer register" }, { "name": "imm", "desc": "Imm" } ], "extension": "Base", "description": "Add immediate value to 32-bit register and set condition flags. Adds a 12-bit immediate (optionally left-shifted by 0 or 12 bits) to Wn, stores the result in Wd, and updates the N, Z, C, and V flags based on the result. AArch64-only instruction executing at any privilege level.", "example": "ADDS w0, Wn, #16", "pseudocode": "imm_val ← imm12 << (sh * 12)\nresult ← Wn + imm_val\nWd ← result\nN ← result[31]\nZ ← (result == 0)\nC ← CarryOut(Wn, imm_val)\nV ← OverflowFrom(Wn, imm_val)" }, { "mnemonic": "adds", "architecture": "ARMv8-A", "full_name": "Add and Set Flags (Immediate 64-bit)", "summary": "Adds immediate and updates flags (64-bit).", "syntax": "ADDS , , # {, lsl #}", "encoding": { "format": "Data Processing (Immediate)", "binary_pattern": "1 | 0 | 1 | 100010 | sh | imm12 | Rn | Rd", "hex_opcode": "0xB1000000", "visual_parts": [ { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "100010", "clean": "100010" }, { "raw": "sh", "clean": "sh" }, { "raw": "imm12", "clean": "imm12" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:23 | 22 | 21:10 | 9:5 | 4:0" }, "operands": [ { "name": "Xd", "desc": "Destination 64-bit integer register" }, { "name": "Xn", "desc": "First source / base 64-bit integer register" }, { "name": "imm", "desc": "Imm" } ], "extension": "Base", "description": "Add immediate value to 64-bit register and set condition flags. Adds a 12-bit immediate (optionally left-shifted by 0 or 12 bits) to Xn, stores the result in Xd, and updates the N, Z, C, and V flags based on the result. AArch64-only instruction executing at any privilege level.", "example": "ADDS x0, x1, #16", "pseudocode": "imm_val ← imm12 << (sh * 12)\nresult ← Xn + imm_val\nXd ← result\nN ← result[63]\nZ ← (result == 0)\nC ← CarryOut(Xn, imm_val)\nV ← OverflowFrom(Xn, imm_val)" }, { "mnemonic": "adds", "architecture": "ARMv8-A", "full_name": "Add and Set Flags (Shifted Register)", "summary": "Adds shifted register and updates flags.", "syntax": "ADDS , , {, #}", "encoding": { "format": "Data Processing (Register)", "binary_pattern": "0 | 0 | 1 | 01011 | shift | 0 | Rm | imm6 | Rn | Rd", "hex_opcode": "0x2B000000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "01011", "clean": "01011" }, { "raw": "shift", "clean": "shift" }, { "raw": "0", "clean": "0" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "imm6", "clean": "imm6" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Wd", "desc": "Destination 32-bit integer register" }, { "name": "Wn", "desc": "First source / base 32-bit integer register" }, { "name": "Wm", "desc": "Second source / offset 32-bit integer register" } ], "extension": "Base", "description": "Add shifted 32-bit register to another and set condition flags. Adds the optionally shifted value of Wm to Wn, stores the result in Wd, and updates the N, Z, C, and V flags based on the result. AArch64-only instruction executing at any privilege level.", "example": "ADDS w0, w1, w2", "pseudocode": "shifted_val ← Wm << amount\nresult ← Wn + shifted_val\nWd ← result\nN ← result[31]\nZ ← (result == 0)\nC ← CarryOut(Wn, shifted_val)\nV ← OverflowFrom(Wn, shifted_val)" }, { "mnemonic": "adds", "architecture": "ARMv8-A", "full_name": "Add and Set Flags (Shifted Register 64-bit)", "summary": "Adds shifted register and updates flags (64-bit).", "syntax": "ADDS , , {, #}", "encoding": { "format": "Data Processing (Register)", "binary_pattern": "1 | 0 | 1 | 01011 | shift | 0 | Rm | imm6 | Rn | Rd", "hex_opcode": "0xAB000000", "visual_parts": [ { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "01011", "clean": "01011" }, { "raw": "shift", "clean": "shift" }, { "raw": "0", "clean": "0" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "imm6", "clean": "imm6" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Xd", "desc": "Destination 64-bit integer register" }, { "name": "Xn", "desc": "First source / base 64-bit integer register" }, { "name": "Xm", "desc": "Second source / offset 64-bit integer register" } ], "extension": "Base", "description": "Add shifted 64-bit register to another and set condition flags. Adds the optionally shifted value of Xm to Xn, stores the result in Xd, and updates the N, Z, C, and V flags based on the result. AArch64-only instruction executing at any privilege level.", "example": "ADDS x0, x1, x2", "pseudocode": "shifted_val ← Xm << amount\nresult ← Xn + shifted_val\nXd ← result\nN ← result[63]\nZ ← (result == 0)\nC ← CarryOut(Xn, shifted_val)\nV ← OverflowFrom(Xn, shifted_val)" }, { "mnemonic": "adr", "architecture": "ARMv8-A", "full_name": "Form PC-relative Address", "summary": "Calculates the address of a label (PC +/- 1MB range).", "syntax": "ADR ,
, , ", "encoding": { "format": "VFP Misc", "binary_pattern": "11111110 | 0 | D | cc | Vn | Vd | 1011 | N | 0 | M | Vm", "hex_opcode": "0xFE000B00", "visual_parts": [ { "raw": "11111110", "clean": "11111110" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "cc", "clean": "cc" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1011", "clean": "1011" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "Vm", "clean": "Vm" } ] }, "operands": [ { "name": "Dd", "desc": "Destination 64-bit SIMD/FP register" }, { "name": "Dn", "desc": "First source 64-bit SIMD/FP register" }, { "name": "Dm", "desc": "Second source 64-bit SIMD/FP register" } ], "extension": "VFP (Float)", "description": "Vector Select (Double). This VFP instruction selects between two 64-bit floating-point operands (Dn and Dm) based on a condition code (cc) applied to the FPSCR condition flags, writing the selected value to Dd. The condition code determines which register's value is copied. No flags are set or cleared by this instruction.", "example": "VSELcond.F64 d0, d1, d2", "pseudocode": "if ConditionPassed(cc) then\n Dd ← Dn\nelse\n Dd ← Dm" }, { "mnemonic": "vmaxnm", "architecture": "ARMv8-A", "full_name": "Vector Maximum Number (Double)", "summary": "Returns larger double-precision value, handling NaNs.", "syntax": "VMAXNM.F64
, , ", "encoding": { "format": "VFP Misc", "binary_pattern": "111111101 | D | 00 | Vn | Vd | 10 | 11 | N | 0 | M | 0 | Vm", "hex_opcode": "0xFE800B00", "visual_parts": [ { "raw": "111111101", "clean": "111111101" }, { "raw": "D", "clean": "D" }, { "raw": "00", "clean": "00" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "11", "clean": "11" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Dd", "desc": "Destination 64-bit SIMD/FP register" }, { "name": "Dn", "desc": "First source 64-bit SIMD/FP register" }, { "name": "Dm", "desc": "Second source 64-bit SIMD/FP register" } ], "extension": "VFP (Float)", "description": "Vector Maximum Number (Double). This VFP instruction compares two 64-bit floating-point values (Dn and Dm) and writes the larger value to Dd, with special handling for NaN: if one operand is NaN, the other is returned (not NaN). FPSCR exception flags may be set according to the IEEE 754 floating-point standard.", "example": "VMAXNM.F64 d0, d1, d2", "pseudocode": "if IsNaN(Dn) then\n Dd ← Dm\nelseif IsNaN(Dm) then\n Dd ← Dn\nelse if Dn ≥ Dm then\n Dd ← Dn\nelse\n Dd ← Dm" }, { "mnemonic": "vminnm", "architecture": "ARMv8-A", "full_name": "Vector Minimum Number (Double)", "summary": "Returns smaller double-precision value, handling NaNs.", "syntax": "VMINNM.F64
, , ", "encoding": { "format": "VFP Misc", "binary_pattern": "111111101 | D | 00 | Vn | Vd | 10 | 11 | N | 1 | M | 0 | Vm", "hex_opcode": "0xFE800B40", "visual_parts": [ { "raw": "111111101", "clean": "111111101" }, { "raw": "D", "clean": "D" }, { "raw": "00", "clean": "00" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "11", "clean": "11" }, { "raw": "N", "clean": "N" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Dd", "desc": "Destination 64-bit SIMD/FP register" }, { "name": "Dn", "desc": "First source 64-bit SIMD/FP register" }, { "name": "Dm", "desc": "Second source 64-bit SIMD/FP register" } ], "extension": "VFP (Float)", "description": "Vector Minimum Number (Double). This VFP instruction compares two 64-bit floating-point values (Dn and Dm) and writes the smaller value to Dd, with special handling for NaN: if one operand is NaN, the other is returned (not NaN). FPSCR exception flags may be set according to the IEEE 754 floating-point standard.", "example": "VMINNM.F64 d0, d1, d2", "pseudocode": "if IsNaN(Dn) then\n Dd ← Dm\nelseif IsNaN(Dm) then\n Dd ← Dn\nelse if Dn ≤ Dm then\n Dd ← Dn\nelse\n Dd ← Dm" }, { "mnemonic": "vrintr", "architecture": "ARMv8-A", "full_name": "Vector Round Floating-Point (Current)", "summary": "Rounds float to integral float using FPSCR rounding mode.", "syntax": "VRINTR.F32 , ", "encoding": { "format": "VFP Unary", "binary_pattern": "cond | 11101 | D | 11 | 0 | 110 | Vd | 10 | 10 | 0 | 1 | M | 0 | Vm", "hex_opcode": "0x0EB60A40", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "11101", "clean": "11101" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "0", "clean": "0" }, { "raw": "110", "clean": "110" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" }, { "name": "Sm", "desc": "Second source 32-bit floating-point register" } ], "extension": "VFP (Float)", "description": "Vector Round Floating-Point (Current). This VFP instruction rounds the 32-bit floating-point value in Sm to an integral floating-point value using the rounding mode specified in the FPSCR and writes the result to Sd. The rounding mode and exception behavior are controlled by FPSCR flags; inexact exceptions may be signaled.", "example": "VRINTR.F32 s0, s2", "pseudocode": "rounding_mode ← FPSCR.RMode\nSd ← RoundFP(Sm, rounding_mode)" }, { "mnemonic": "vrintx", "architecture": "ARMv8-A", "full_name": "Vector Round Floating-Point (Exact)", "summary": "Rounds float to integral float, raising Inexact exception.", "syntax": "VRINTX.F32 , ", "encoding": { "format": "VFP Unary", "binary_pattern": "cond | 11101 | D | 11 | 0 | 111 | Vd | 10 | 10 | 0 | 1 | M | 0 | Vm", "hex_opcode": "0x0EB70A40", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "11101", "clean": "11101" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "0", "clean": "0" }, { "raw": "111", "clean": "111" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" }, { "name": "Sm", "desc": "Second source 32-bit floating-point register" } ], "extension": "VFP (Float)", "description": "Rounds each single-precision floating-point element to the nearest integral value, with round-to-nearest-even semantics. The Inexact exception is raised if the result differs from the input. Condition flags are not affected. This is an A32/T32 VFP instruction requiring the VFP extension.", "example": "VRINTX.F32 s0, s2", "pseudocode": "for i = 0 to 0 do\n Sd[i] ← RoundToNearest(Sm[i])\n if Sd[i] != Sm[i] then\n FPExc_IXC ← 1\n end if\nend for" }, { "mnemonic": "sha512h", "architecture": "ARMv8-A", "full_name": "SHA512 Hash Part 1 (A32)", "summary": "SHA512 hash update part 1.", "syntax": "SHA512H.64 , , ", "encoding": { "format": "Crypto 3-Reg", "binary_pattern": "11001110011 | Rm | 1 | 0 | 00 | 00 | Rn | Rd", "hex_opcode": "0xCE608000", "visual_parts": [ { "raw": "11001110011", "clean": "11001110011" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "00", "clean": "00" }, { "raw": "00", "clean": "00" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31:21 | 20:16 | 15 | 14 | 13:12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Qd", "desc": "State" }, { "name": "Qn", "desc": "Hash" }, { "name": "Qm", "desc": "Data" } ], "extension": "Crypto (SHA512)", "description": "Performs the first part of the SHA-512 hash computation, processing hash values and round constants. The operation combines Qn (hash) and Qm (data) values and updates Qd (state) with intermediate results. This is an A32 Advanced SIMD instruction requiring the SHA512 Cryptographic Extension. Condition flags are not affected.", "example": "SHA512H.64 q0, q1, q2", "pseudocode": "Qd ← SHA512_H_Part1(Qd, Qn, Qm)" }, { "mnemonic": "sha512h2", "architecture": "ARMv8-A", "full_name": "SHA512 Hash Part 2 (A32)", "summary": "SHA512 hash update part 2.", "syntax": "SHA512H2.64 , , ", "encoding": { "format": "Crypto 3-Reg", "binary_pattern": "11001110011 | Rm | 1 | 0 | 00 | 01 | Rn | Rd", "hex_opcode": "0xCE608400", "visual_parts": [ { "raw": "11001110011", "clean": "11001110011" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "00", "clean": "00" }, { "raw": "01", "clean": "01" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31:21 | 20:16 | 15 | 14 | 13:12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Qd", "desc": "State" }, { "name": "Qn", "desc": "Hash" }, { "name": "Qm", "desc": "Data" } ], "extension": "Crypto (SHA512)", "description": "Performs the second part of the SHA-512 hash computation, completing the hash update using state (Qd), hash values (Qn), and message data (Qm). This variant differs from SHA512H in the internal transformation applied. This is an A32 Advanced SIMD instruction requiring the SHA512 Cryptographic Extension. Condition flags are not affected.", "example": "SHA512H2.64 q0, q1, q2", "pseudocode": "Qd ← SHA512_H_Part2(Qd, Qn, Qm)" }, { "mnemonic": "sha512su0", "architecture": "ARMv8-A", "full_name": "SHA512 Schedule Update 0 (A32)", "summary": "SHA512 schedule update instruction 0.", "syntax": "SHA512SU0.64 , ", "encoding": { "format": "Crypto 2-Reg", "binary_pattern": "11001110110000001000 | 00 | Rn | Rd", "hex_opcode": "0xCEC08000", "visual_parts": [ { "raw": "11001110110000001000", "clean": "11001110110000001000" }, { "raw": "00", "clean": "00" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31:12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "Crypto (SHA512)", "description": "Performs the first schedule update operation for SHA-512 message scheduling, processing Qm and updating Qd with the first sigma operation. This is a unary operation used during SHA-512 preprocessing of the message schedule. This is an A32 Advanced SIMD instruction requiring the SHA512 Cryptographic Extension. Condition flags are not affected.", "example": "SHA512SU0.64 q0, q2", "pseudocode": "Qd ← SHA512_SU_0(Qm)" }, { "mnemonic": "sha512su1", "architecture": "ARMv8-A", "full_name": "SHA512 Schedule Update 1 (A32)", "summary": "SHA512 schedule update instruction 1.", "syntax": "SHA512SU1.64 , , ", "encoding": { "format": "Crypto 3-Reg", "binary_pattern": "11001110011 | Rm | 1 | 0 | 00 | 10 | Rn | Rd", "hex_opcode": "0xCE608800", "visual_parts": [ { "raw": "11001110011", "clean": "11001110011" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "00", "clean": "00" }, { "raw": "10", "clean": "10" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31:21 | 20:16 | 15 | 14 | 13:12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "Crypto (SHA512)", "description": "Performs the second schedule update operation for SHA-512 message scheduling, combining Qd and Qn with Qm to compute the next message schedule value. This operation incorporates previous schedule elements and the second sigma transformation. This is an A32 Advanced SIMD instruction requiring the SHA512 Cryptographic Extension. Condition flags are not affected.", "example": "SHA512SU1.64 q0, q1, q2", "pseudocode": "Qd ← SHA512_SU_1(Qd, Qn, Qm)" }, { "mnemonic": "sm3ss1", "architecture": "ARMv8-A", "full_name": "SM3 Step 1 (A32)", "summary": "SM3 cryptographic hash step 1.", "syntax": "SM3SS1.32 , , ", "encoding": { "format": "Crypto 3-Reg", "binary_pattern": "110011100 | 10 | Rm | 0 | Ra | Rn | Rd", "hex_opcode": "0xCE400000", "visual_parts": [ { "raw": "110011100", "clean": "110011100" }, { "raw": "10", "clean": "10" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "0", "clean": "0" }, { "raw": "Ra", "clean": "Ra" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31:23 | 22:21 | 20:16 | 15 | 14:10 | 9:5 | 4:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "Crypto (SM3)", "description": "Performs step 1 of the SM3 cryptographic hash function, combining three 128-bit operands to produce an intermediate result. The operation implements the SM3 compression function's linear transformation. This is an A32 Advanced SIMD instruction requiring the SM3 Cryptographic Extension. Condition flags are not affected.", "example": "SM3SS1.32 q0, q1, q2", "pseudocode": "Qd ← SM3_StepSS1(Qn, Qm)" }, { "mnemonic": "sm3tt1a", "architecture": "ARMv8-A", "full_name": "SM3 Step 2A (A32)", "summary": "SM3 cryptographic hash step 2A.", "syntax": "SM3TT1A.32 , , , #", "encoding": { "format": "Crypto Imm", "binary_pattern": "11001110010 | Rm | 10 | imm2 | 00 | Rn | Rd", "hex_opcode": "0xCE408000", "visual_parts": [ { "raw": "11001110010", "clean": "11001110010" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "10", "clean": "10" }, { "raw": "imm2", "clean": "imm2" }, { "raw": "00", "clean": "00" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31:21 | 20:16 | 15:14 | 13:12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Dn", "desc": "First source 64-bit SIMD/FP register" }, { "name": "Dm", "desc": "Second source 64-bit SIMD/FP register" }, { "name": "imm", "desc": "Rot" } ], "extension": "Crypto (SM3)", "description": "Performs step 2A of the SM3 cryptographic hash, updating 32-bit word elements based on the specified rotation immediate. Operates on 64-bit source registers but stores results in a 128-bit destination. This is an A32 Advanced SIMD instruction requiring the SM3 Cryptographic Extension. Condition flags are not affected.", "example": "SM3TT1A.32 q0, d1, d2, #16", "pseudocode": "rot ← imm * 8\nQd ← SM3_TT1A(Dn, Dm, rot)" }, { "mnemonic": "sm3tt1b", "architecture": "ARMv8-A", "full_name": "SM3 Step 2B (A32)", "summary": "SM3 cryptographic hash step 2B.", "syntax": "SM3TT1B.32 , , , #", "encoding": { "format": "Crypto Imm", "binary_pattern": "11001110010 | Rm | 10 | imm2 | 01 | Rn | Rd", "hex_opcode": "0xCE408400", "visual_parts": [ { "raw": "11001110010", "clean": "11001110010" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "10", "clean": "10" }, { "raw": "imm2", "clean": "imm2" }, { "raw": "01", "clean": "01" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31:21 | 20:16 | 15:14 | 13:12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Dn", "desc": "First source 64-bit SIMD/FP register" }, { "name": "Dm", "desc": "Second source 64-bit SIMD/FP register" }, { "name": "imm", "desc": "Rot" } ], "extension": "Crypto (SM3)", "description": "Performs step 2B of the SM3 cryptographic hash, updating 32-bit word elements with a different permutation than SM3TT1A, based on the specified rotation immediate. Operates on 64-bit source registers but stores results in a 128-bit destination. This is an A32 Advanced SIMD instruction requiring the SM3 Cryptographic Extension. Condition flags are not affected.", "example": "SM3TT1B.32 q0, d1, d2, #16", "pseudocode": "rot ← imm * 8\nQd ← SM3_TT1B(Dn, Dm, rot)" }, { "mnemonic": "sm3tt2a", "architecture": "ARMv8-A", "full_name": "SM3 Step 3A (A32)", "summary": "SM3 cryptographic hash step 3A.", "syntax": "SM3TT2A.32 , , , #", "encoding": { "format": "Crypto Imm", "binary_pattern": "11001110010 | Rm | 10 | imm2 | 10 | Rn | Rd", "hex_opcode": "0xCE408800", "visual_parts": [ { "raw": "11001110010", "clean": "11001110010" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "10", "clean": "10" }, { "raw": "imm2", "clean": "imm2" }, { "raw": "10", "clean": "10" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31:21 | 20:16 | 15:14 | 13:12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Dn", "desc": "First source 64-bit SIMD/FP register" }, { "name": "Dm", "desc": "Second source 64-bit SIMD/FP register" }, { "name": "imm", "desc": "Rot" } ], "extension": "Crypto (SM3)", "description": "SM3 Step 3A performs part of the SM3 cryptographic hash compression function, processing two 32-bit words from the input with a rotation parameter. This instruction operates on 64-bit source registers and writes a 128-bit result, and does not affect any condition flags. The instruction is A32-only and requires the Crypto SM3 extension; it generates an Undefined Instruction exception if executed without the extension enabled.", "example": "SM3TT2A.32 q0, d1, d2, #16", "pseudocode": "Qd ← SM3_TT2A(Dn, Dm, imm2)" }, { "mnemonic": "sm3tt2b", "architecture": "ARMv8-A", "full_name": "SM3 Step 3B (A32)", "summary": "SM3 cryptographic hash step 3B.", "syntax": "SM3TT2B.32 , , , #", "encoding": { "format": "Crypto Imm", "binary_pattern": "11001110010 | Rm | 10 | imm2 | 11 | Rn | Rd", "hex_opcode": "0xCE408C00", "visual_parts": [ { "raw": "11001110010", "clean": "11001110010" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "10", "clean": "10" }, { "raw": "imm2", "clean": "imm2" }, { "raw": "11", "clean": "11" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31:21 | 20:16 | 15:14 | 13:12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Dn", "desc": "First source 64-bit SIMD/FP register" }, { "name": "Dm", "desc": "Second source 64-bit SIMD/FP register" }, { "name": "imm", "desc": "Rot" } ], "extension": "Crypto (SM3)", "description": "SM3 Step 3B performs the second variant of SM3 compression function step 3, processing two 32-bit words with a different constant path than SM3TT2A. This instruction operates on 64-bit source registers and writes a 128-bit result, and does not affect condition flags. The instruction is A32-only and requires the Crypto SM3 extension; it generates an Undefined Instruction exception if executed without the extension enabled.", "example": "SM3TT2B.32 q0, d1, d2, #16", "pseudocode": "Qd ← SM3_TT2B(Dn, Dm, imm2)" }, { "mnemonic": "sm3partw1", "architecture": "ARMv8-A", "full_name": "SM3 Part Word 1 (A32)", "summary": "SM3 schedule update part 1.", "syntax": "SM3PARTW1.32 , , ", "encoding": { "format": "Crypto 3-Reg", "binary_pattern": "11001110011 | Rm | 1 | 1 | 00 | 00 | Rn | Rd", "hex_opcode": "0xCE60C000", "visual_parts": [ { "raw": "11001110011", "clean": "11001110011" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "00", "clean": "00" }, { "raw": "00", "clean": "00" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31:21 | 20:16 | 15 | 14 | 13:12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "Crypto (SM3)", "description": "SM3 Part Word 1 performs the first part of SM3 message schedule update, computing intermediate values from the previous message schedule words. This instruction operates on three 128-bit registers and does not affect condition flags. The instruction is A32-only and requires the Crypto SM3 extension; it generates an Undefined Instruction exception if executed without the extension enabled.", "example": "SM3PARTW1.32 q0, q1, q2", "pseudocode": "Qd ← SM3_PARTW1(Qn, Qm)" }, { "mnemonic": "sm3partw2", "architecture": "ARMv8-A", "full_name": "SM3 Part Word 2 (A32)", "summary": "SM3 schedule update part 2.", "syntax": "SM3PARTW2.32 , , ", "encoding": { "format": "Crypto 3-Reg", "binary_pattern": "11001110011 | Rm | 1 | 1 | 00 | 01 | Rn | Rd", "hex_opcode": "0xCE60C400", "visual_parts": [ { "raw": "11001110011", "clean": "11001110011" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "00", "clean": "00" }, { "raw": "01", "clean": "01" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31:21 | 20:16 | 15 | 14 | 13:12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "Crypto (SM3)", "description": "SM3 Part Word 2 performs the second part of SM3 message schedule update, completing the computation of new message schedule words from previous values. This instruction operates on three 128-bit registers and does not affect condition flags. The instruction is A32-only and requires the Crypto SM3 extension; it generates an Undefined Instruction exception if executed without the extension enabled.", "example": "SM3PARTW2.32 q0, q1, q2", "pseudocode": "Qd ← SM3_PARTW2(Qn, Qm)" }, { "mnemonic": "sm4e", "architecture": "ARMv8-A", "full_name": "SM4 Encrypt (A32)", "summary": "SM4 encryption step.", "syntax": "SM4E.32 , ", "encoding": { "format": "Crypto 2-Reg", "binary_pattern": "11001110110000001000 | 01 | Rn | Rd", "hex_opcode": "0xCEC08400", "visual_parts": [ { "raw": "11001110110000001000", "clean": "11001110110000001000" }, { "raw": "01", "clean": "01" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31:12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Key" } ], "extension": "Crypto (SM4)", "description": "SM4 Encrypt performs one round of SM4 block cipher encryption, transforming a 128-bit state register using a 128-bit round key. This instruction does not affect condition flags. The instruction is A32-only and requires the Crypto SM4 extension; it generates an Undefined Instruction exception if executed without the extension enabled.", "example": "SM4E.32 q0, q2", "pseudocode": "Qd ← SM4_Encrypt(Qd, Qm)" }, { "mnemonic": "sm4ekey", "architecture": "ARMv8-A", "full_name": "SM4 Key (A32)", "summary": "SM4 key schedule step.", "syntax": "SM4EKEY.32 , ", "encoding": { "format": "Crypto 2-Reg", "binary_pattern": "01000101 | 0 | 0 | 1 | Zm | 11110 | 0 | Zn | Zd", "hex_opcode": "0x4520F000", "visual_parts": [ { "raw": "01000101", "clean": "01000101" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "Zm", "clean": "Zm" }, { "raw": "11110", "clean": "11110" }, { "raw": "0", "clean": "0" }, { "raw": "Zn", "clean": "Zn" }, { "raw": "Zd", "clean": "Zd" } ], "bit_positions": "31:24 | 23 | 22 | 21 | 20:16 | 15:11 | 10 | 9:5 | 4:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Key" } ], "extension": "Crypto (SM4)", "description": "SM4 Key performs one round of SM4 key schedule expansion, computing a derived key from the previous key material. This instruction does not affect condition flags. The instruction is A32-only and requires the Crypto SM4 extension; it generates an Undefined Instruction exception if executed without the extension enabled.", "example": "SM4EKEY.32 q0, q2", "pseudocode": "Qd ← SM4_KeySchedule(Qd, Qm)" }, { "mnemonic": "ldaexb", "architecture": "ARMv8-A", "full_name": "Load Acquire Exclusive Byte (A32)", "summary": "Loads a byte, acquires semantics, marks exclusive.", "syntax": "LDAEXB , []", "encoding": { "format": "Load Excl", "binary_pattern": "cond | 00011 | 10 | 1 | Rn | Rt | 1 | 1 | 1 | 0 | 1001 | 1111", "hex_opcode": "0x01D00E9F", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00011", "clean": "00011" }, { "raw": "10", "clean": "10" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rt", "clean": "Rt" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "1001", "clean": "1001" }, { "raw": "1111", "clean": "1111" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rt", "desc": "Transfer general-purpose register (load/store)" }, { "name": "Rn", "desc": "First source / base general-purpose register" } ], "extension": "A32 (Atomic)", "description": "Loads a byte from memory at the address in Rn with Acquire semantics and marks the location as exclusive. The loaded byte is zero-extended and placed in Rt. Acquire semantics ensure that subsequent memory operations are not reordered before this load. No condition flags are affected.", "example": "LDAEXB r3, [r1]", "pseudocode": "Rt ← ZeroExtend([Rn], 8); ExclusiveLocal ← TRUE; Acquire()" }, { "mnemonic": "ldaexh", "architecture": "ARMv8-A", "full_name": "Load Acquire Exclusive Halfword (A32)", "summary": "Loads a halfword, acquires semantics, marks exclusive.", "syntax": "LDAEXH , []", "encoding": { "format": "Load Excl", "binary_pattern": "cond | 00011 | 11 | 1 | Rn | Rt | 1 | 1 | 1 | 0 | 1001 | 1111", "hex_opcode": "0x01F00E9F", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00011", "clean": "00011" }, { "raw": "11", "clean": "11" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rt", "clean": "Rt" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "1001", "clean": "1001" }, { "raw": "1111", "clean": "1111" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rt", "desc": "Transfer general-purpose register (load/store)" }, { "name": "Rn", "desc": "First source / base general-purpose register" } ], "extension": "A32 (Atomic)", "description": "Loads a halfword from memory at the address in Rn with Acquire semantics and marks the location as exclusive. The loaded halfword is zero-extended and placed in Rt. Acquire semantics ensure that subsequent memory operations are not reordered before this load. No condition flags are affected.", "example": "LDAEXH r3, [r1]", "pseudocode": "Rt ← ZeroExtend([Rn], 16); ExclusiveLocal ← TRUE; Acquire()" }, { "mnemonic": "ldaexd", "architecture": "ARMv8-A", "full_name": "Load Acquire Exclusive Double (A32)", "summary": "Loads a doubleword, acquires semantics, marks exclusive.", "syntax": "LDAEXD , , []", "encoding": { "format": "Load Excl", "binary_pattern": "cond | 00011 | 01 | 1 | Rn | Rt | 1 | 1 | 1 | 0 | 1001 | 1111", "hex_opcode": "0x01B00E9F", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00011", "clean": "00011" }, { "raw": "01", "clean": "01" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rt", "clean": "Rt" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "1001", "clean": "1001" }, { "raw": "1111", "clean": "1111" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rt", "desc": "Dest 1" }, { "name": "Rt2", "desc": "Dest 2" }, { "name": "Rn", "desc": "First source / base general-purpose register" } ], "extension": "A32 (Atomic)", "description": "Loads a doubleword (64 bits) from memory at the address in Rn with Acquire semantics and marks the location as exclusive. The lower 32 bits are placed in Rt and the upper 32 bits in Rt2. Acquire semantics ensure that subsequent memory operations are not reordered before this load. No condition flags are affected.", "example": "LDAEXD r3, r4, [r1]", "pseudocode": "Rt ← [Rn]; Rt2 ← [Rn+4]; ExclusiveLocal ← TRUE; Acquire()" }, { "mnemonic": "stlexb", "architecture": "ARMv8-A", "full_name": "Store Release Exclusive Byte (A32)", "summary": "Stores a byte with Release semantics if exclusive.", "syntax": "STLEXB , , []", "encoding": { "format": "Store Excl", "binary_pattern": "cond | 00011 | 10 | 0 | Rn | Rd | 1 | 1 | 1 | 0 | 1001 | Rt", "hex_opcode": "0x01C00E90", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00011", "clean": "00011" }, { "raw": "10", "clean": "10" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "1001", "clean": "1001" }, { "raw": "Rt", "clean": "Rt" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Status" }, { "name": "Rt", "desc": "Transfer general-purpose register (load/store)" }, { "name": "Rn", "desc": "First source / base general-purpose register" } ], "extension": "A32 (Atomic)", "description": "Attempts to store a byte to memory at the address in Rn with Release semantics if the location is marked exclusive. The result of the store attempt (0 for success, 1 for failure) is written to Rd. Release semantics ensure that preceding memory operations are not reordered after this store. No condition flags are affected.", "example": "STLEXB r0, r3, [r1]", "pseudocode": "if ExclusiveLocal then [Rn] ← Rt[7:0]; Rd ← 0; Release(); ExclusiveLocal ← FALSE else Rd ← 1 endif" }, { "mnemonic": "stlexh", "architecture": "ARMv8-A", "full_name": "Store Release Exclusive Halfword (A32)", "summary": "Stores a halfword with Release semantics if exclusive.", "syntax": "STLEXH , , []", "encoding": { "format": "Store Excl", "binary_pattern": "cond | 00011 | 11 | 0 | Rn | Rd | 1 | 1 | 1 | 0 | 1001 | Rt", "hex_opcode": "0x01E00E90", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00011", "clean": "00011" }, { "raw": "11", "clean": "11" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "1001", "clean": "1001" }, { "raw": "Rt", "clean": "Rt" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Status" }, { "name": "Rt", "desc": "Transfer general-purpose register (load/store)" }, { "name": "Rn", "desc": "First source / base general-purpose register" } ], "extension": "A32 (Atomic)", "description": "Stores a halfword to memory with Release semantics if the exclusive monitor is set for the address. Writes a status value (0=success, 1=failure) to Rd and the value from Rt to the memory location addressed by Rn. This is an exclusive store with memory ordering guarantees. No condition flags are affected. Execution state: A32 only; requires privilege level dependent on the accessed address.", "example": "STLEXH r0, r3, [r1]", "pseudocode": "if ExclusiveMonitorsPass(address=Rn, size=2) then\n [Rn] ← Rt[15:0]\n Rd ← 0\n ClearExclusiveMonitors()\nelse\n Rd ← 1" }, { "mnemonic": "stlexd", "architecture": "ARMv8-A", "full_name": "Store Release Exclusive Double (A32)", "summary": "Stores a doubleword with Release semantics if exclusive.", "syntax": "STLEXD , , , []", "encoding": { "format": "Store Excl", "binary_pattern": "cond | 00011 | 01 | 0 | Rn | Rd | 1 | 1 | 1 | 0 | 1001 | Rt", "hex_opcode": "0x01A00E90", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00011", "clean": "00011" }, { "raw": "01", "clean": "01" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "1001", "clean": "1001" }, { "raw": "Rt", "clean": "Rt" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Status" }, { "name": "Rt", "desc": "Transfer general-purpose register (load/store)" }, { "name": "Rt2", "desc": "Second transfer register (load/store pair)" }, { "name": "Rn", "desc": "First source / base general-purpose register" } ], "extension": "A32 (Atomic)", "description": "Stores a doubleword (64-bit value) to memory with Release semantics if the exclusive monitor is set for the address. The value is loaded from the register pair [Rt, Rt2], and a status is written to Rd (0=success, 1=failure). This is an exclusive store with full Release memory ordering. No condition flags are affected. Execution state: A32 only; Rt must be even-numbered and Rt2=Rt+1.", "example": "STLEXD r0, r3, r4, [r1]", "pseudocode": "if ExclusiveMonitorsPass(address=Rn, size=8) then\n [Rn] ← Rt\n [Rn+4] ← Rt2\n Rd ← 0\n ClearExclusiveMonitors()\nelse\n Rd ← 1" }, { "mnemonic": "vcadd", "architecture": "ARMv8-A", "full_name": "Vector Complex Add (A32)", "summary": "Complex integer addition with rotation (NEON).", "syntax": "VCADD.I , , , #", "encoding": { "format": "NEON Complex", "binary_pattern": "1111110 | rot | 1 | D | 0 | S | Vn | Vd | 1 | 0 | 0 | 0 | N | 1 | M | 0 | Vm", "hex_opcode": "0xFC800840", "visual_parts": [ { "raw": "1111110", "clean": "1111110" }, { "raw": "rot", "clean": "rot" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "0", "clean": "0" }, { "raw": "S", "clean": "S" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "N", "clean": "N" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" }, { "name": "rot", "desc": "Rot" } ], "extension": "NEON (Complex)", "description": "Performs complex addition on pairs of elements within 128-bit SIMD registers, treating each pair as a complex number (real, imaginary), with rotation applied before addition. The rotation is either 90° or 270° as specified by rot. Operates on 32-bit or 64-bit element pairs. NEON extension; no condition flags affected.", "example": "VCADD.Isize q0, q1, q2, #rot", "pseudocode": "rotation_angle ← if rot == 0 then 90 else 270\nfor i = 0 to elements_per_128bit_register/2 - 1 do\n real_n ← Qn[2*i]\n imag_n ← Qn[2*i+1]\n real_m ← Qm[2*i]\n imag_m ← Qm[2*i+1]\n rotated_real ← rotate(real_m, imag_m, rotation_angle).real\n rotated_imag ← rotate(real_m, imag_m, rotation_angle).imag\n Qd[2*i] ← real_n + rotated_real\n Qd[2*i+1] ← imag_n + rotated_imag" }, { "mnemonic": "vcmla", "architecture": "ARMv8-A", "full_name": "Vector Complex Multiply Accumulate (A32)", "summary": "Complex integer multiply-accumulate with rotation.", "syntax": "VCMLA.I , , , #", "encoding": { "format": "NEON Complex", "binary_pattern": "1111110 | rot | D | 1 | S | Vn | Vd | 1 | 0 | 0 | 0 | N | 1 | M | 0 | Vm", "hex_opcode": "0xFC200840", "visual_parts": [ { "raw": "1111110", "clean": "1111110" }, { "raw": "rot", "clean": "rot" }, { "raw": "D", "clean": "D" }, { "raw": "1", "clean": "1" }, { "raw": "S", "clean": "S" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "N", "clean": "N" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24:23 | 22 | 21 | 20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" }, { "name": "rot", "desc": "Rot" } ], "extension": "NEON (Complex)", "description": "Vector Complex Multiply-Accumulate performs complex multiplication of two vectors with a specified rotation (0°, 90°, 180°, or 270°) and accumulates the result into the destination register, operating on 32-bit or 64-bit integer elements. This instruction does not affect condition flags. The instruction is A32-only and requires the NEON Complex extension; it generates an Undefined Instruction exception if executed without the extension enabled.", "example": "VCMLA.Isize q0, q1, q2, #rot", "pseudocode": "for i = 0 to (128 / esize) - 1 do\n real_part = Qn[2*i] * Qm[2*i] - Qn[2*i+1] * Qm[2*i+1]\n imag_part = Qn[2*i] * Qm[2*i+1] + Qn[2*i+1] * Qm[2*i]\n (real_part, imag_part) = RotateByRot(real_part, imag_part, rot)\n Qd[2*i] = Qd[2*i] + real_part\n Qd[2*i+1] = Qd[2*i+1] + imag_part" }, { "mnemonic": "vdot", "architecture": "ARMv8-A", "full_name": "Vector BFloat16 Dot Product (A32)", "summary": "BFloat16 dot product to float32 accumulator.", "syntax": "VDOT.BF16 , , ", "encoding": { "format": "NEON BFloat16", "binary_pattern": "1111110 | 00 | D | 00 | Vn | Vd | 1 | 1 | 0 | 1 | N | 1 | M | 0 | Vm", "hex_opcode": "0xFC000D40", "visual_parts": [ { "raw": "1111110", "clean": "1111110" }, { "raw": "00", "clean": "00" }, { "raw": "D", "clean": "D" }, { "raw": "00", "clean": "00" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "N", "clean": "N" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24:23 | 22 | 21:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (BFloat16)", "description": "Vector BFloat16 Dot Product computes the dot product of two vectors of BFloat16 (brain floating-point 16-bit) values and accumulates the result as a 32-bit floating-point value in the destination. This instruction does not affect condition flags. The instruction is A32-only and requires the NEON BFloat16 extension; it generates an Undefined Instruction exception if executed without the extension enabled.", "example": "VDOT.BF16 q0, q1, q2", "pseudocode": "for i = 0 to 3 do\n acc = 0.0\n for j = 0 to 1 do\n bf16_a = Qn[4*i + 2*j : 4*i + 2*j + 1]\n bf16_b = Qm[4*i + 2*j : 4*i + 2*j + 1]\n acc = acc + BF16_to_FP32(bf16_a) * BF16_to_FP32(bf16_b)\n Qd[i] = Qd[i] + acc" }, { "mnemonic": "vbfmmla", "architecture": "ARMv8-A", "full_name": "Vector BFloat16 Matrix Multiply (A32)", "summary": "BFloat16 matrix multiply-accumulate.", "syntax": "VBFMMLA.BF16 , , ", "encoding": { "format": "NEON BFloat16", "binary_pattern": "11111100 | 0 | 0 | 11 | Vn | Vd | 1100 | N | Q | M | 1 | Vm", "hex_opcode": "0xFC000C40", "visual_parts": [ { "raw": "11111100", "clean": "11111100" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11", "clean": "11" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1100", "clean": "1100" }, { "raw": "N", "clean": "N" }, { "raw": "Q", "clean": "Q" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ] }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (BFloat16)", "description": "Multiplies two 128-bit SIMD registers containing BFloat16 (16-bit brain floating-point) elements in 2×2 matrix format and accumulates the result into the destination register. Each 2×2 matrix multiplication processes four BFloat16 values, producing single-precision results that are accumulated. Condition flags (N, Z, C, V) are unaffected. This instruction requires the NEON BFloat16 extension and executes in A32 (ARM) instruction set only.", "example": "VBFMMLA.BF16 q0, q1, q2", "pseudocode": "for i = 0 to 3 do\n // Extract 2x2 BF16 matrix from Qn\n matrix_a[0] = BF16_to_F32(Qn[i*2*16 + 0:15])\n matrix_a[1] = BF16_to_F32(Qn[i*2*16 + 16:31])\n matrix_a[2] = BF16_to_F32(Qn[i*2*16 + 32:47])\n matrix_a[3] = BF16_to_F32(Qn[i*2*16 + 48:63])\n // Extract 2x2 BF16 matrix from Qm\n matrix_b[0] = BF16_to_F32(Qm[i*2*16 + 0:15])\n matrix_b[1] = BF16_to_F32(Qm[i*2*16 + 16:31])\n matrix_b[2] = BF16_to_F32(Qm[i*2*16 + 32:47])\n matrix_b[3] = BF16_to_F32(Qm[i*2*16 + 48:63])\n // Multiply and accumulate\n Qd[i*32 + 0:31] = Qd[i*32 + 0:31] + matrix_a[0] * matrix_b[0] + matrix_a[1] * matrix_b[2]\n Qd[i*32 + 32:63] = Qd[i*32 + 32:63] + matrix_a[2] * matrix_b[0] + matrix_a[3] * matrix_b[2]" }, { "mnemonic": "vbfcvt", "architecture": "ARMv8-A", "full_name": "Vector Convert BFloat16 (A32)", "summary": "Converts Float32 to BFloat16.", "syntax": "VBFCVT.BF16.F32 , ", "encoding": { "format": "NEON BFloat16", "binary_pattern": "11110011 | 1 | D | 11 | 01 | 10 | Vd | 00110 | Q | M | 0 | Vm", "hex_opcode": "0xF3B60640", "visual_parts": [ { "raw": "11110011", "clean": "11110011" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "01", "clean": "01" }, { "raw": "10", "clean": "10" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "00110", "clean": "00110" }, { "raw": "Q", "clean": "Q" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ] }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (BFloat16)", "description": "Converts 128-bit SIMD register containing single-precision floating-point elements to BFloat16 (16-bit brain floating-point) format by rounding the mantissa to 7 bits and preserving the sign and exponent. The result is stored as 64 BFloat16 elements in the destination 128-bit register. Condition flags are unaffected. This instruction requires the NEON BFloat16 extension and executes in A32 (ARM) instruction set only.", "example": "VBFCVT.BF16.F32 q0, q2", "pseudocode": "for i = 0 to 3 do\n f32_val = Qm[i*32 + 0:31]\n bf16_val = F32_to_BF16(f32_val)\n Qd[i*16 + 0:15] = bf16_val" }, { "mnemonic": "vusdot", "architecture": "ARMv8-A", "full_name": "Vector Unsigned-Signed Dot Product (A32)", "summary": "Dot product of unsigned (src1) and signed (src2) bytes.", "syntax": "VUSDOT.S8 , , ", "encoding": { "format": "NEON DotProd", "binary_pattern": "1111110 | 01 | D | 10 | Vn | Vd | 1 | 1 | 0 | 1 | N | 1 | M | 0 | Vm", "hex_opcode": "0xFCA00D40", "visual_parts": [ { "raw": "1111110", "clean": "1111110" }, { "raw": "01", "clean": "01" }, { "raw": "D", "clean": "D" }, { "raw": "10", "clean": "10" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "N", "clean": "N" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24:23 | 22 | 21:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "Unsigned" }, { "name": "Qm", "desc": "Signed" } ], "extension": "NEON (DotProd)", "description": "Computes the dot product of unsigned 8-bit integers from Qn and signed 8-bit integers from Qm, accumulating four dot products (one per 32-bit lane) into the corresponding 32-bit signed integer elements of Qd. Each lane multiplies and sums four pairs of unsigned×signed bytes. Condition flags are unaffected. This instruction requires the NEON DotProd extension and executes in A32 (ARM) instruction set only.", "example": "VUSDOT.S8 q0, q1, q2", "pseudocode": "for i = 0 to 3 do\n acc = Qd[i*32 + 0:31]\n for j = 0 to 3 do\n unsigned_byte = ZeroExtend(Qn[(i*4 + j)*8 + 0:7])\n signed_byte = SignExtend(Qm[(i*4 + j)*8 + 0:7])\n acc = acc + (unsigned_byte * signed_byte)\n Qd[i*32 + 0:31] = acc" }, { "mnemonic": "vsmmla", "architecture": "ARMv8-A", "full_name": "Vector Signed Int8 Matrix Multiply (A32)", "summary": "Matrix multiply-accumulate (Signed Int8).", "syntax": "VSMMLA.S8 , , ", "encoding": { "format": "NEON MatMul", "binary_pattern": "1111110 | 0 | 0 | D | 10 | Vn | Vd | 1 | 1 | 0 | 0 | N | 1 | M | 0 | Vm", "hex_opcode": "0xFC200C40", "visual_parts": [ { "raw": "1111110", "clean": "1111110" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "10", "clean": "10" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "N", "clean": "N" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (MatMul)", "description": "Multiplies two 128-bit SIMD registers containing signed 8-bit integer elements in 4×4 matrix format and accumulates the result into the destination register as signed 32-bit integers. Processes four 4×4 matrices, each producing four 32-bit signed results that are added to Qd. Condition flags are unaffected. This instruction requires the NEON MatMul extension and executes in A32 (ARM) instruction set only.", "example": "VSMMLA.S8 q0, q1, q2", "pseudocode": "for i = 0 to 3 do\n // Extract 4x4 S8 matrix from Qn\n for r = 0 to 3 do\n for c = 0 to 3 do\n matrix_a[r][c] = SignExtend(Qn[(i*16 + r*4 + c)*8 + 0:7])\n // Extract 4x4 S8 matrix from Qm\n for r = 0 to 3 do\n for c = 0 to 3 do\n matrix_b[r][c] = SignExtend(Qm[(i*16 + r*4 + c)*8 + 0:7])\n // Multiply and accumulate\n for r = 0 to 3 do\n result = Qd[(i*4 + r)*32 + 0:31]\n for k = 0 to 3 do\n result = result + matrix_a[r][k] * matrix_b[k][r]\n Qd[(i*4 + r)*32 + 0:31] = result" }, { "mnemonic": "vusmmla", "architecture": "ARMv8-A", "full_name": "Vector Unsigned-Signed Matrix Multiply (A32)", "summary": "Matrix multiply-accumulate (Unsigned x Signed Int8).", "syntax": "VUSMMLA.S8 , , ", "encoding": { "format": "NEON MatMul", "binary_pattern": "1111110 | 0 | 1 | D | 10 | Vn | Vd | 1 | 1 | 0 | 0 | N | 1 | M | 0 | Vm", "hex_opcode": "0xFCA00C40", "visual_parts": [ { "raw": "1111110", "clean": "1111110" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "10", "clean": "10" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "N", "clean": "N" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "Unsigned" }, { "name": "Qm", "desc": "Signed" } ], "extension": "NEON (MatMul)", "description": "Multiplies two 128-bit SIMD registers containing unsigned 8-bit integers from Qn and signed 8-bit integers from Qm in 4×4 matrix format and accumulates the result into the destination register as signed 32-bit integers. Processes four 4×4 matrices, each producing four 32-bit signed results. Condition flags are unaffected. This instruction requires the NEON MatMul extension and executes in A32 (ARM) instruction set only.", "example": "VUSMMLA.S8 q0, q1, q2", "pseudocode": "for i = 0 to 3 do\n // Extract 4x4 U8 matrix from Qn\n for r = 0 to 3 do\n for c = 0 to 3 do\n matrix_a[r][c] = ZeroExtend(Qn[(i*16 + r*4 + c)*8 + 0:7])\n // Extract 4x4 S8 matrix from Qm\n for r = 0 to 3 do\n for c = 0 to 3 do\n matrix_b[r][c] = SignExtend(Qm[(i*16 + r*4 + c)*8 + 0:7])\n // Multiply and accumulate\n for r = 0 to 3 do\n result = Qd[(i*4 + r)*32 + 0:31]\n for k = 0 to 3 do\n result = result + matrix_a[r][k] * matrix_b[k][r]\n Qd[(i*4 + r)*32 + 0:31] = result" }, { "mnemonic": "vummla", "architecture": "ARMv8-A", "full_name": "Vector Unsigned Matrix Multiply (A32)", "summary": "Matrix multiply-accumulate (Unsigned Int8).", "syntax": "VUMMLA.U8 , , ", "encoding": { "format": "NEON MatMul", "binary_pattern": "1111110 | 0 | 0 | D | 10 | Vn | Vd | 1 | 1 | 0 | 0 | N | 1 | M | 1 | Vm", "hex_opcode": "0xFC200C50", "visual_parts": [ { "raw": "1111110", "clean": "1111110" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "10", "clean": "10" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "N", "clean": "N" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (MatMul)", "description": "Multiplies two 128-bit SIMD registers containing unsigned 8-bit integer elements in 4×4 matrix format and accumulates the result into the destination register as unsigned 32-bit integers. Processes four 4×4 matrices, each producing four 32-bit unsigned results that are added to Qd. Condition flags are unaffected. This instruction requires the NEON MatMul extension and executes in A32 (ARM) instruction set only.", "example": "VUMMLA.U8 q0, q1, q2", "pseudocode": "for i = 0 to 3 do\n // Extract 4x4 U8 matrix from Qn\n for r = 0 to 3 do\n for c = 0 to 3 do\n matrix_a[r][c] = ZeroExtend(Qn[(i*16 + r*4 + c)*8 + 0:7])\n // Extract 4x4 U8 matrix from Qm\n for r = 0 to 3 do\n for c = 0 to 3 do\n matrix_b[r][c] = ZeroExtend(Qm[(i*16 + r*4 + c)*8 + 0:7])\n // Multiply and accumulate\n for r = 0 to 3 do\n result = Qd[(i*4 + r)*32 + 0:31]\n for k = 0 to 3 do\n result = result + matrix_a[r][k] * matrix_b[k][r]\n Qd[(i*4 + r)*32 + 0:31] = result" }, { "mnemonic": "vjcvt", "architecture": "ARMv8-A", "full_name": "Vector Javascript Convert (A32)", "summary": "Converts double to signed 32-bit integer (JS semantics).", "syntax": "VJCVT.S32.F64 , ", "encoding": { "format": "VFP Convert", "binary_pattern": "cond | 11101 | D | 11 | 1 | 001 | Vd | 10 | 11 | 1 | 1 | M | 0 | Vm", "hex_opcode": "0x0EB90BC0", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "11101", "clean": "11101" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "1", "clean": "1" }, { "raw": "001", "clean": "001" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "11", "clean": "11" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19 | 18:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" }, { "name": "Dm", "desc": "Second source 64-bit SIMD/FP register" } ], "extension": "VFP (JS)", "description": "Converts a 64-bit double-precision floating-point value to a signed 32-bit integer using JavaScript semantics (NaN maps to 0, out-of-range values saturate). The result is stored as a single-precision floating-point value in the destination 32-bit register. Condition flags are unaffected. This instruction requires the VFP JavaScript extension and executes in A32 (ARM) instruction set only.", "example": "VJCVT.S32.F64 s0, d2", "pseudocode": "f64_val = Dm[0:63]\nif IsNaN(f64_val) then\n s32_val = 0\nelse if f64_val > 2147483647.0 then\n s32_val = 2147483647\nelse if f64_val < -2147483648.0 then\n s32_val = -2147483648\nelse\n s32_val = RoundTowardsZero(f64_val)\nSd[0:31] = F32(s32_val)" }, { "mnemonic": "pldw", "architecture": "ARMv8-A", "full_name": "Preload Data for Write (A32)", "summary": "Hints memory system to bring data into cache for writing.", "syntax": "PLDW [, #]", "encoding": { "format": "Load/Store", "binary_pattern": "1111010 | 1 | U | 0 | 01 | Rn | 1 | 1 | 1 | 1 | imm12", "hex_opcode": "0xF510F000", "visual_parts": [ { "raw": "1111010", "clean": "1111010" }, { "raw": "1", "clean": "1" }, { "raw": "U", "clean": "U" }, { "raw": "0", "clean": "0" }, { "raw": "01", "clean": "01" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "imm12", "clean": "imm12" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15 | 14 | 13 | 12 | 11:0" }, "operands": [ { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "imm", "desc": "Signed immediate value" } ], "extension": "A32 (Base)", "description": "Preloads data for write by hinting the memory system to allocate cache line(s) in an exclusive state at the address computed from the base register and 12-bit immediate offset. This is a hint instruction and does not cause exceptions on address translation or access faults. Condition flags and general-purpose registers are unaffected. This instruction executes in A32 (ARM) instruction set only.", "example": "PLDW [r1, #16]", "pseudocode": "address = Rn + imm12\n// Hint to memory system to preload for exclusive access (write)\nPreloadDataForWrite(address)" }, { "mnemonic": "pldw", "architecture": "ARMv8-A", "full_name": "Preload Data for Write (Thumb)", "summary": "Hints memory system to bring data into cache for writing (Thumb).", "syntax": "PLDW [, #]", "encoding": { "format": "Thumb Load/Store", "binary_pattern": "111110001 | 0 | 1 | 1 | Rn | 1111 | imm12", "hex_opcode": "0xF8B0F000", "visual_parts": [ { "raw": "111110001", "clean": "111110001" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "1111", "clean": "1111" }, { "raw": "imm12", "clean": "imm12" } ], "bit_positions": "31:23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:0" }, "operands": [ { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "imm", "desc": "Signed immediate value" } ], "extension": "T32 (Thumb2)", "description": "Preload Data for Write provides a hint to the memory system to bring a cache line into the cache hierarchy in preparation for a write operation. The instruction does not modify any registers or condition flags and serves only as a performance optimization hint. It is available in Thumb (T32) instruction set and has no architectural side effects if the hint is ignored.", "example": "PLDW [r1, #16]", "pseudocode": "// Hint to memory system to preload data for write at address [Rn + imm]\n// No architectural effect on registers or flags\nHint_PreloadForWrite(address: Rn + imm)" }, { "mnemonic": "sb", "architecture": "ARMv8-A", "full_name": "Speculation Barrier (A32)", "summary": "Prevents speculative execution across the barrier (v8.0).", "syntax": "SB", "encoding": { "format": "System Hint", "binary_pattern": "111101010111 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0111 | 0000", "hex_opcode": "0xF57FF070", "visual_parts": [ { "raw": "111101010111", "clean": "111101010111" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0111", "clean": "0111" }, { "raw": "0000", "clean": "0000" } ], "bit_positions": "31:20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7:4 | 3:0" }, "operands": [], "extension": "A32 (v8.0)", "description": "Speculation Barrier (v8.0) prevents speculative execution from crossing the barrier in either direction, creating a serialization point for instruction execution. This instruction acts as a full execution barrier that completes all prior instructions before allowing subsequent instructions to execute speculatively. Available in A32 instruction set; does not modify condition flags.", "example": "SB", "pseudocode": "// Serialize execution; prevent speculative execution across this point\nSpeculationBarrier()\n// All prior instructions complete before any subsequent instruction executes speculatively" }, { "mnemonic": "ssbb", "architecture": "ARMv8-A", "full_name": "Speculative Store Bypass Barrier (A32)", "summary": "Prevents speculative loads bypassing earlier stores (v8.0).", "syntax": "SSBB", "encoding": { "format": "System Hint", "binary_pattern": "111101010111 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0100 | 0000", "hex_opcode": "0xF57FF040", "visual_parts": [ { "raw": "111101010111", "clean": "111101010111" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0100", "clean": "0100" }, { "raw": "0000", "clean": "0000" } ], "bit_positions": "31:20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7:4 | 3:0" }, "operands": [], "extension": "A32 (v8.0)", "description": "Speculative Store Bypass Barrier (v8.0) prevents speculative loads from bypassing earlier stores, ensuring that load operations wait for all prior store operations to complete. This is a lighter-weight barrier than SB, specifically targeting store-to-load forwarding speculation. Available in A32 instruction set; does not modify condition flags.", "example": "SSBB", "pseudocode": "// Prevent speculative load execution past prior stores\nStoreBypassBarrier()\n// All prior stores complete before subsequent loads can execute" }, { "mnemonic": "pssbb", "architecture": "ARMv8-A", "full_name": "Physical Speculative Store Bypass Barrier (A32)", "summary": "Prevents speculation on physical resources (v8.0).", "syntax": "PSSBB", "encoding": { "format": "System Hint", "binary_pattern": "111101010111 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0100 | 0100", "hex_opcode": "0xF57FF044", "visual_parts": [ { "raw": "111101010111", "clean": "111101010111" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0100", "clean": "0100" }, { "raw": "0100", "clean": "0100" } ], "bit_positions": "31:20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7:4 | 3:0" }, "operands": [], "extension": "A32 (v8.0)", "description": "Physical Speculative Store Bypass Barrier (v8.0) prevents speculative load bypassing on physical memory operations, operating at a more restrictive level than SSBB by affecting physical resource speculation. This barrier is typically used in security contexts to prevent cross-VM or cross-process speculation. Available in A32 instruction set; does not modify condition flags.", "example": "PSSBB", "pseudocode": "// Prevent speculative load bypass on physical resources\nPhysicalStoreBypassBarrier()\n// All prior physical stores complete before subsequent loads can execute on physical resources" }, { "mnemonic": "tsb", "architecture": "ARMv8-A", "full_name": "Trace Synchronization Barrier (A32)", "summary": "Ensures trace generation is complete (v8.2).", "syntax": "TSB CSYNC", "encoding": { "format": "System Hint", "binary_pattern": "cond | 00110 | 0 | 10 | 0000 | 1 | 1 | 1 | 1 | 000000010010", "hex_opcode": "0x0320F012", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00110", "clean": "00110" }, { "raw": "0", "clean": "0" }, { "raw": "10", "clean": "10" }, { "raw": "0000", "clean": "0000" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "000000010010", "clean": "000000010010" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15 | 14 | 13 | 12 | 11:0" }, "operands": [], "extension": "A32 (Trace)", "description": "Trace Synchronization Barrier with CSYNC operand (v8.2) ensures that trace generation is synchronized and complete before subsequent instructions execute, used to maintain consistency in trace output. This instruction is primarily used in debug and tracing scenarios and does not modify general-purpose registers or condition flags. Available in A32 instruction set.", "example": "TSB CSYNC", "pseudocode": "// Synchronize trace generation (CSYNC variant)\nTraceBarrier(CSYNC)\n// Trace context switches complete before proceeding" }, { "mnemonic": "dfb", "architecture": "ARMv8-A", "full_name": "Debug Flush Barrier (A32)", "summary": "Deprecated alias for DSB.", "syntax": "DFB", "encoding": { "format": "System Hint", "binary_pattern": "11110101011111111111000001001100", "hex_opcode": "0xF57FF04C", "visual_parts": [ { "raw": "11110101011111111111000001001100", "clean": "11110101011111111111000001001100" } ] }, "operands": [], "extension": "A32 (Legacy)", "description": "Debug Flush Barrier (Legacy) is a deprecated alias for DSB that is retained for compatibility; it flushes the debug pipeline and ensures all debug operations complete. This instruction should not be used in new code as it is superseded by explicit DSB instructions. Available in A32 instruction set; does not modify condition flags.", "example": "DFB", "pseudocode": "// Deprecated: Flush debug pipeline (equivalent to DSB)\nDebugFlushBarrier()\n// All debug operations complete (legacy behavior)" }, { "mnemonic": "bxj", "architecture": "ARMv8-A", "full_name": "Branch and Exchange Jazelle (A32)", "summary": "Legacy instruction to enter Jazelle state (Now behaves like BX).", "syntax": "BXJ ", "encoding": { "format": "Branch", "binary_pattern": "cond | 00010010 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0010 | Rm", "hex_opcode": "0x012FFF20", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00010010", "clean": "00010010" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0010", "clean": "0010" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (Legacy)", "description": "Legacy instruction that branches to the address in Rm with exchange (Thumb/ARM mode switching based on bit [0] of Rm). In current ARMv8 architecture, BXJ behaves identically to BX due to Jazelle being obsolete. Bit [0] of Rm determines the target state (0=ARM, 1=Thumb). No condition flags are affected. Execution state: A32 only.", "example": "BXJ r2", "pseudocode": "next_address ← Rm\nif next_address[0] == 1 then\n CPSR.T ← 1\nelse\n CPSR.T ← 0\nPC ← next_address AND NOT(0x1)" }, { "mnemonic": "vrintm", "architecture": "ARMv8-A", "full_name": "Vector Round Floating-Point (Minus Infinity)", "summary": "Rounds float towards Minus Infinity (Floor).", "syntax": "VRINTM.F32 , ", "encoding": { "format": "VFP Unary", "binary_pattern": "111111101 | D | 111 | 0 | 11 | Vd | 10 | 10 | 0 | 1 | M | 0 | Vm", "hex_opcode": "0xFEBB0A40", "visual_parts": [ { "raw": "111111101", "clean": "111111101" }, { "raw": "D", "clean": "D" }, { "raw": "111", "clean": "111" }, { "raw": "0", "clean": "0" }, { "raw": "11", "clean": "11" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:19 | 18 | 17:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" }, { "name": "Sm", "desc": "Second source 32-bit floating-point register" } ], "extension": "VFP (Float)", "description": "Rounds a 32-bit floating-point value towards minus infinity (floor) and stores the result in the destination register. This instruction does not modify the condition code flags. It is available in A32 and T32 with the VFP extension, and requires floating-point support.", "example": "VRINTM.F32 s0, s2", "pseudocode": "Sd ← RoundTowardMinusInfinity(Sm)" }, { "mnemonic": "vrintp", "architecture": "ARMv8-A", "full_name": "Vector Round Floating-Point (Plus Infinity)", "summary": "Rounds float towards Plus Infinity (Ceil).", "syntax": "VRINTP.F32 , ", "encoding": { "format": "VFP Unary", "binary_pattern": "111111101 | D | 111 | 0 | 10 | Vd | 10 | 10 | 0 | 1 | M | 0 | Vm", "hex_opcode": "0xFEBA0A40", "visual_parts": [ { "raw": "111111101", "clean": "111111101" }, { "raw": "D", "clean": "D" }, { "raw": "111", "clean": "111" }, { "raw": "0", "clean": "0" }, { "raw": "10", "clean": "10" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "10", "clean": "10" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:19 | 18 | 17:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" }, { "name": "Sm", "desc": "Second source 32-bit floating-point register" } ], "extension": "VFP (Float)", "description": "Rounds a 32-bit floating-point value towards plus infinity (ceiling) and stores the result in the destination register. This instruction does not modify the condition code flags. It is available in A32 and T32 with the VFP extension, and requires floating-point support.", "example": "VRINTP.F32 s0, s2", "pseudocode": "Sd ← RoundTowardPlusInfinity(Sm)" }, { "mnemonic": "vrintm", "architecture": "ARMv8-A", "full_name": "Vector Round Floating-Point Double (Minus Infinity)", "summary": "Rounds double towards Minus Infinity (Floor).", "syntax": "VRINTM.F64
, ", "encoding": { "format": "VFP Unary", "binary_pattern": "111111101 | D | 111 | 0 | 11 | Vd | 10 | 11 | 0 | 1 | M | 0 | Vm", "hex_opcode": "0xFEBB0B40", "visual_parts": [ { "raw": "111111101", "clean": "111111101" }, { "raw": "D", "clean": "D" }, { "raw": "111", "clean": "111" }, { "raw": "0", "clean": "0" }, { "raw": "11", "clean": "11" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "11", "clean": "11" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:19 | 18 | 17:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Dd", "desc": "Destination 64-bit SIMD/FP register" }, { "name": "Dm", "desc": "Second source 64-bit SIMD/FP register" } ], "extension": "VFP (Float)", "description": "Rounds a 64-bit floating-point value towards minus infinity (floor) and stores the result in the destination register. This instruction does not modify the condition code flags. It is available in A32 and T32 with the VFP extension, and requires floating-point support.", "example": "VRINTM.F64 d0, d2", "pseudocode": "Dd ← RoundTowardMinusInfinity(Dm)" }, { "mnemonic": "vrintp", "architecture": "ARMv8-A", "full_name": "Vector Round Floating-Point Double (Plus Infinity)", "summary": "Rounds double towards Plus Infinity (Ceil).", "syntax": "VRINTP.F64
, ", "encoding": { "format": "VFP Unary", "binary_pattern": "111111101 | D | 111 | 0 | 10 | Vd | 10 | 11 | 0 | 1 | M | 0 | Vm", "hex_opcode": "0xFEBA0B40", "visual_parts": [ { "raw": "111111101", "clean": "111111101" }, { "raw": "D", "clean": "D" }, { "raw": "111", "clean": "111" }, { "raw": "0", "clean": "0" }, { "raw": "10", "clean": "10" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "11", "clean": "11" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:19 | 18 | 17:16 | 15:12 | 11:10 | 9:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Dd", "desc": "Destination 64-bit SIMD/FP register" }, { "name": "Dm", "desc": "Second source 64-bit SIMD/FP register" } ], "extension": "VFP (Float)", "description": "Rounds a 64-bit floating-point value towards plus infinity (ceiling) and stores the result in the destination register. This instruction does not modify the condition code flags. It is available in A32 and T32 with the VFP extension, and requires floating-point support.", "example": "VRINTP.F64 d0, d2", "pseudocode": "Dd ← RoundTowardPlusInfinity(Dm)" }, { "mnemonic": "hlt", "architecture": "ARMv8-A", "full_name": "Halting Debug (A32)", "summary": "Enters halting debug state (A32 encoding).", "syntax": "HLT #", "encoding": { "format": "System", "binary_pattern": "cond | 00010 | 00 | 0 | imm12 | 0111 | imm4", "hex_opcode": "0x01000070", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00010", "clean": "00010" }, { "raw": "00", "clean": "00" }, { "raw": "0", "clean": "0" }, { "raw": "imm12", "clean": "imm12" }, { "raw": "0111", "clean": "0111" }, { "raw": "imm4", "clean": "imm4" } ], "bit_positions": "31:28 | 27:23 | 22:21 | 20 | 19:8 | 7:4 | 3:0" }, "operands": [ { "name": "imm", "desc": "ID" } ], "extension": "A32 (Base)", "description": "Halts execution and enters the debugger, with an optional 16-bit immediate value providing debug information. The instruction is unconditional in A32 and causes an exception to the debugger if enabled, otherwise it behaves as an unpredictable instruction. This is an A32-only instruction and is typically privileged.", "example": "HLT #16", "pseudocode": "DebugState ← Halted; DebugID ← imm16" }, { "mnemonic": "msr", "architecture": "ARMv8-A", "full_name": "Move Immediate to Special Register (A32)", "summary": "Writes an immediate to a status register (A32).", "syntax": "MSR , #", "encoding": { "format": "System", "binary_pattern": "cond | 00110 | R | 10 | mask | 1 | 1 | 1 | 1 | imm12", "hex_opcode": "0x0320F000", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00110", "clean": "00110" }, { "raw": "R", "clean": "R" }, { "raw": "10", "clean": "10" }, { "raw": "mask", "clean": "mask" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "imm12", "clean": "imm12" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15 | 14 | 13 | 12 | 11:0" }, "operands": [ { "name": "spec_reg", "desc": "CPSR/SPSR" }, { "name": "imm", "desc": "Value" } ], "extension": "A32 (System)", "description": "Writes an immediate value to a status register (CPSR or SPSR) with mask control in A32. The immediate is expanded by a rotate amount encoded in the instruction. Only the register fields specified by the mask are updated. This is a privileged instruction if writing to SPSR or certain CPSR fields. Condition flags (N, Z, C, V) may be updated depending on mask. Execution state: A32 only.", "example": "MSR nzcv, #16", "pseudocode": "imm_value ← rotate_right(imm8, 2 * rotate)\nif spec_reg == CPSR then\n if mask[0] then CPSR[7:0] ← imm_value[7:0]\n if mask[1] then CPSR[15:8] ← imm_value[15:8]\n if mask[2] then CPSR[23:16] ← imm_value[23:16]\n if mask[3] then CPSR[31:24] ← imm_value[31:24]\nelse if spec_reg == SPSR then\n if mask[0] then SPSR[7:0] ← imm_value[7:0]\n if mask[1] then SPSR[15:8] ← imm_value[15:8]\n if mask[2] then SPSR[23:16] ← imm_value[23:16]\n if mask[3] then SPSR[31:24] ← imm_value[31:24]" }, { "mnemonic": "msr", "architecture": "ARMv8-A", "full_name": "Move Immediate to Special Register (Thumb)", "summary": "Writes an immediate to a status register (Thumb).", "syntax": "MSR , #", "encoding": { "format": "Thumb System", "binary_pattern": "11110011100 | R | Rn | 10 | 0 | 0 | mask | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0", "hex_opcode": "0xF3808000", "visual_parts": [ { "raw": "11110011100", "clean": "11110011100" }, { "raw": "R", "clean": "R" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "10", "clean": "10" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "mask", "clean": "mask" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" } ], "bit_positions": "31:21 | 20 | 19:16 | 15:14 | 13 | 12 | 11:8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0" }, "operands": [ { "name": "spec_reg", "desc": "CPSR/SPSR" }, { "name": "imm", "desc": "Value" } ], "extension": "T32 (System)", "description": "Writes an immediate value to a status register (CPSR or SPSR) in T32/Thumb state. The immediate is zero-extended and only the lowest 8 bits are used to update certain CPSR/SPSR fields. This is a privileged instruction. Condition flags may be modified based on the target register and field selection. Execution state: T32 only.", "example": "MSR nzcv, #16", "pseudocode": "imm_value ← ZeroExtend(imm8, 32)\nif spec_reg == CPSR then\n CPSR[31:24] ← imm_value[31:24]\nelse if spec_reg == SPSR then\n SPSR[31:24] ← imm_value[31:24]" }, { "mnemonic": "eret", "architecture": "ARMv8-A", "full_name": "Exception Return (A32)", "summary": "Returns from an exception (A32).", "syntax": "ERET", "encoding": { "format": "System", "binary_pattern": "cond | 00010110 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0110 | 1 | 1 | 1 | 0", "hex_opcode": "0x0160006E", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "00010110", "clean": "00010110" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0110", "clean": "0110" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" } ], "bit_positions": "31:28 | 27:20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7:4 | 3 | 2 | 1 | 0" }, "operands": [], "extension": "A32 (System)", "description": "Returns from an exception by restoring the PC from ELR_ELx and the PSTATE from SPSR_ELx. This instruction is unconditional and is only available in A32 AArch32 execution state. It requires privilege level sufficient to execute exception-handling code (typically EL1 or higher) and is used at the end of exception handlers.", "example": "ERET", "pseudocode": "PC ← ELR_ELx; PSTATE ← SPSR_ELx" }, { "mnemonic": "subs", "architecture": "ARMv8-A", "full_name": "Subtract and Return (A32)", "summary": "Subs PC, LR, #imm (Exception return mechanism).", "syntax": "SUBS PC, LR, #", "encoding": { "format": "Data Proc", "binary_pattern": "cond | 0010 | 010 | 1 | Rn | Rd | imm12", "hex_opcode": "0x02500000", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "0010", "clean": "0010" }, { "raw": "010", "clean": "010" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "imm12", "clean": "imm12" } ], "bit_positions": "31:28 | 27:24 | 23:21 | 20 | 19:16 | 15:12 | 11:0" }, "operands": [ { "name": "imm", "desc": "Signed immediate value" } ], "extension": "A32 (Base)", "description": "Subtracts an immediate from the LR register and stores the result in PC, causing an exception return with automatic CPSR restoration from SPSR. All condition flags (N, Z, C, V) are updated from the subtraction result. This instruction is the preferred exception return mechanism in A32 and must execute in a privileged mode. Execution state: A32 only.", "example": "SUBS PC, LR, #16", "pseudocode": "result ← LR - imm12\nN ← result[31]\nZ ← (result == 0)\nC ← (LR >= imm12) \nV ← OverflowFrom(LR - imm12)\nPC ← result\nCPSR ← SPSR" }, { "mnemonic": "ldr", "architecture": "ARMv8-A", "full_name": "Load Register PC-Relative (A32)", "summary": "Loads a word from a label.", "syntax": "LDR ,
, .", "encoding": { "format": "NEON Scalar", "binary_pattern": "01011110 | 11110001 | 101110 | Rn | Rd", "hex_opcode": "0x5E31B800", "visual_parts": [ { "raw": "01011110", "clean": "01011110" }, { "raw": "11110001", "clean": "11110001" }, { "raw": "101110", "clean": "101110" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ] }, "operands": [ { "name": "Dd", "desc": "Destination 64-bit SIMD/FP register" }, { "name": "Vn", "desc": "First source SIMD/FP vector register" } ], "extension": "NEON (Scalar)", "description": "Adds the two 64-bit elements of a NEON vector register pairwise and stores the scalar 64-bit result in a destination register. Condition flags (N, Z, C, V) are set according to the result. AArch64 only with NEON extension.", "example": "ADDP d0, v1.4s.T", "pseudocode": "result ← (Vn[0] as i64) + (Vn[1] as i64)\nDd ← result\nN ← result[63]\nZ ← (result == 0)\nC ← Carry_Out(Vn[0], Vn[1])\nV ← Overflow_From_Add(Vn[0], Vn[1])" }, { "mnemonic": "fmaxv", "architecture": "ARMv8-A", "full_name": "Floating-Point Maximum Reduction (NEON)", "summary": "Finds max float in a vector.", "syntax": "FMAXV , .", "encoding": { "format": "NEON Reduction", "binary_pattern": "0 | Q | 0 | 01110 | 0 | 011000 | 01111 | 10 | Rn | Rd", "hex_opcode": "0x0E30F800", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "Q", "clean": "Q" }, { "raw": "0", "clean": "0" }, { "raw": "01110", "clean": "01110" }, { "raw": "0", "clean": "0" }, { "raw": "011000", "clean": "011000" }, { "raw": "01111", "clean": "01111" }, { "raw": "10", "clean": "10" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23 | 22:17 | 16:12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" }, { "name": "Vn", "desc": "First source SIMD/FP vector register" } ], "extension": "NEON (v8.0)", "description": "Floating-point maximum reduction across vector elements. Scans all floating-point elements in the source vector and writes the maximum value to the destination scalar register. FPSR is updated with cumulative exception flags from all comparisons; condition flags (N, Z, C, V) are unaffected. AArch64-only instruction requiring NEON support.", "example": "FMAXV s0, v1.4s.T", "pseudocode": "elements ← VecReduction(Vn, 'max')\nSd ← FPMaxReduction(elements)\nFPSR.IOC ← FPSRAccum from comparisons" }, { "mnemonic": "fminv", "architecture": "ARMv8-A", "full_name": "Floating-Point Minimum Reduction (NEON)", "summary": "Finds min float in a vector.", "syntax": "FMINV , .", "encoding": { "format": "NEON Reduction", "binary_pattern": "0 | Q | 0 | 01110 | 1 | 011000 | 01111 | 10 | Rn | Rd", "hex_opcode": "0x0EB0F800", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "Q", "clean": "Q" }, { "raw": "0", "clean": "0" }, { "raw": "01110", "clean": "01110" }, { "raw": "1", "clean": "1" }, { "raw": "011000", "clean": "011000" }, { "raw": "01111", "clean": "01111" }, { "raw": "10", "clean": "10" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23 | 22:17 | 16:12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" }, { "name": "Vn", "desc": "First source SIMD/FP vector register" } ], "extension": "NEON (v8.0)", "description": "Floating-point minimum reduction across vector elements. Scans all floating-point elements in the source vector and writes the minimum value to the destination scalar register. FPSR is updated with cumulative exception flags from all comparisons; condition flags (N, Z, C, V) are unaffected. AArch64-only instruction requiring NEON support.", "example": "FMINV s0, v1.4s.T", "pseudocode": "elements ← VecReduction(Vn, 'min')\nSd ← FPMinReduction(elements)\nFPSR.IOC ← FPSRAccum from comparisons" }, { "mnemonic": "frint32x", "architecture": "ARMv8-A", "full_name": "Floating-Point Round to 32-bit Integer (Exact)", "summary": "Rounds to 32-bit integer, exact exception.", "syntax": "FRINT32X , ", "encoding": { "format": "Float Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 10100 | 01 | 10000 | Rn | Rd", "hex_opcode": "0x1E28C000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "10100", "clean": "10100" }, { "raw": "01", "clean": "01" }, { "raw": "10000", "clean": "10000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:17 | 16:15 | 14:10 | 9:5 | 4:0" }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" }, { "name": "Sn", "desc": "First source 32-bit floating-point register" } ], "extension": "FEAT_FRINTTS", "description": "Rounds a 32-bit floating-point value to the nearest 32-bit integer value using the current rounding mode, signaling an inexact exception. Condition flags are unaffected. Requires FEAT_FRINTTS; AArch64 only.", "example": "FRINT32X s0, s1", "pseudocode": "result ← FP_RoundToInt(Sn, RMode_FromFPCR, exact=true)\nif result != Sn\n FP_InexactException()\nSd ← result" }, { "mnemonic": "frint32z", "architecture": "ARMv8-A", "full_name": "Floating-Point Round to 32-bit Integer (Zero)", "summary": "Rounds to 32-bit integer towards zero.", "syntax": "FRINT32Z , ", "encoding": { "format": "Float Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 10100 | 00 | 10000 | Rn | Rd", "hex_opcode": "0x1E284000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "10100", "clean": "10100" }, { "raw": "00", "clean": "00" }, { "raw": "10000", "clean": "10000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:17 | 16:15 | 14:10 | 9:5 | 4:0" }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" }, { "name": "Sn", "desc": "First source 32-bit floating-point register" } ], "extension": "FEAT_FRINTTS", "description": "Rounds the source single-precision floating-point value to a 32-bit signed integer using round towards zero (truncate) rounding mode, and writes the result as a single-precision floating-point value to the destination. Does not update the NZCV condition flags. Requires FEAT_FRINTTS extension; AArch64 only.", "example": "FRINT32Z s0, s1", "pseudocode": "Xn_bits ← Sn\nint32_val ← RoundTowardsZero(FPUnpack(Xn_bits), 32)\nSd ← FPPack(int32_val as single-precision floating-point)" }, { "mnemonic": "frint64x", "architecture": "ARMv8-A", "full_name": "Floating-Point Round to 64-bit Integer (Exact)", "summary": "Rounds to 64-bit integer, exact exception.", "syntax": "FRINT64X , ", "encoding": { "format": "Float Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 10100 | 11 | 10000 | Rn | Rd", "hex_opcode": "0x1E29C000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "10100", "clean": "10100" }, { "raw": "11", "clean": "11" }, { "raw": "10000", "clean": "10000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:17 | 16:15 | 14:10 | 9:5 | 4:0" }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" }, { "name": "Sn", "desc": "First source 32-bit floating-point register" } ], "extension": "FEAT_FRINTTS", "description": "Rounds the source single-precision floating-point value to a 64-bit signed integer using the current rounding mode, and writes the result as a single-precision floating-point value to the destination. Signals an inexact exception if the input was not exactly representable as a 64-bit integer. Does not update the NZCV condition flags. Requires FEAT_FRINTTS extension; AArch64 only.", "example": "FRINT64X s0, s1", "pseudocode": "Xn_bits ← Sn\nint64_val ← RoundUsingCurrentMode(FPUnpack(Xn_bits), 64)\nif int64_val is inexact then signal_inexact_exception()\nSd ← FPPack(int64_val as single-precision floating-point)" }, { "mnemonic": "frint64z", "architecture": "ARMv8-A", "full_name": "Floating-Point Round to 64-bit Integer (Zero)", "summary": "Rounds to 64-bit integer towards zero.", "syntax": "FRINT64Z , ", "encoding": { "format": "Float Conversion", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 10100 | 10 | 10000 | Rn | Rd", "hex_opcode": "0x1E294000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "10100", "clean": "10100" }, { "raw": "10", "clean": "10" }, { "raw": "10000", "clean": "10000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:17 | 16:15 | 14:10 | 9:5 | 4:0" }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" }, { "name": "Sn", "desc": "First source 32-bit floating-point register" } ], "extension": "FEAT_FRINTTS", "description": "Rounds the source single-precision floating-point value to a 64-bit signed integer using round towards zero (truncate) rounding mode, and writes the result as a single-precision floating-point value to the destination. Does not update the NZCV condition flags. Requires FEAT_FRINTTS extension; AArch64 only.", "example": "FRINT64Z s0, s1", "pseudocode": "Xn_bits ← Sn\nint64_val ← RoundTowardsZero(FPUnpack(Xn_bits), 64)\nSd ← FPPack(int64_val as single-precision floating-point)" }, { "mnemonic": "chkfeat", "architecture": "ARMv8-A", "full_name": "Check", "summary": "Check feature status (FEAT_CHK).", "syntax": "CHK <#imm>", "encoding": { "format": "System", "binary_pattern": "11010101000000110010 | 0101 | 000 | 11111", "hex_opcode": "0xD503251F", "visual_parts": [ { "raw": "11010101000000110010", "clean": "11010101000000110010" }, { "raw": "0101", "clean": "0101" }, { "raw": "000", "clean": "000" }, { "raw": "11111", "clean": "11111" } ], "bit_positions": "31:12 | 11:8 | 7:5 | 4:0" }, "operands": [ { "name": "imm", "desc": "Feature ID" } ], "extension": "FEAT_CHK", "description": "Checks the status of a system feature identified by the immediate operand and raises a CHK exception if the feature is not available or in the expected state. The specific behavior depends on the feature ID encoded in the immediate. Requires FEAT_CHK extension; AArch64 only; may only execute at EL0 and EL1 (subject to CHKFEATURE_EL0 register control).", "example": "CHK #imm", "pseudocode": "feature_id ← imm\nif not CheckFeature(feature_id) then raise_exception(CHK_EXCEPTION)" }, { "mnemonic": "clrex", "architecture": "ARMv8-A", "full_name": "Clear Exclusive (System)", "summary": "Clears the local monitor state (AArch64 variant).", "syntax": "CLREX {#}", "encoding": { "format": "System", "binary_pattern": "11010101000000110011 | CRm | 010 | 11111", "hex_opcode": "0xD503305F", "visual_parts": [ { "raw": "11010101000000110011", "clean": "11010101000000110011" }, { "raw": "CRm", "clean": "CRm" }, { "raw": "010", "clean": "010" }, { "raw": "11111", "clean": "11111" } ], "bit_positions": "31:12 | 11:8 | 7:5 | 4:0" }, "operands": [ { "name": "imm", "desc": "Optional" } ], "extension": "Base (Atomic)", "description": "Clears the local monitor state associated with the current PE, removing any exclusive accesses held by this processor. Subsequent LDEX/STEX instructions will treat the exclusive monitor as clear. Does not update condition flags. AArch64 only; optional immediate operand is typically 0xF (ignored).", "example": "CLREX", "pseudocode": "local_monitor_state ← CLEAR" }, { "mnemonic": "fadd", "architecture": "ARMv8-A", "full_name": "Floating-point Add (Single)", "summary": "Adds two single-precision floating-point registers.", "syntax": "FADD , , ", "encoding": { "format": "Float Data Proc", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | 001 | 0 | 10 | Rn | Rd", "hex_opcode": "0x1E202800", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "001", "clean": "001" }, { "raw": "0", "clean": "0" }, { "raw": "10", "clean": "10" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:13 | 12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Sd", "desc": "Dest (32-bit)" }, { "name": "Sn", "desc": "First source 32-bit floating-point register" }, { "name": "Sm", "desc": "Second source 32-bit floating-point register" } ], "extension": "F.P.", "description": "Floating-point addition of two single-precision (32-bit) values. Adds operand Sn and operand Sm and writes the result to Sd. FPSR exception flags are updated; condition flags (N, Z, C, V) are unaffected. AArch64-only instruction; uses IEEE 754 rounding mode from FPCR.", "example": "FADD s0, s1, s2", "pseudocode": "operand1 ← Sn (32-bit float)\noperand2 ← Sm (32-bit float)\nresult ← FPAdd(operand1, operand2)\nSd ← result\nUpdateFPSR(exception_flags)" }, { "mnemonic": "fadd", "architecture": "ARMv8-A", "full_name": "Floating-point Add (Double)", "summary": "Adds two double-precision floating-point registers.", "syntax": "FADD
, , ", "encoding": { "format": "Float Data Proc", "binary_pattern": "0 | 0 | 0 | 11110 | 01 | 1 | Rm | 001 | 0 | 10 | Rn | Rd", "hex_opcode": "0x1E602800", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "01", "clean": "01" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "001", "clean": "001" }, { "raw": "0", "clean": "0" }, { "raw": "10", "clean": "10" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:13 | 12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Dd", "desc": "Dest (64-bit)" }, { "name": "Dn", "desc": "First source 64-bit SIMD/FP register" }, { "name": "Dm", "desc": "Second source 64-bit SIMD/FP register" } ], "extension": "F.P.", "description": "Floating-point addition of two double-precision (64-bit) values. Adds operand Dn and operand Dm and writes the result to Dd. FPSR exception flags are updated; condition flags (N, Z, C, V) are unaffected. AArch64-only instruction; uses IEEE 754 rounding mode from FPCR.", "example": "FADD d0, d1, d2", "pseudocode": "operand1 ← Dn (64-bit float)\noperand2 ← Dm (64-bit float)\nresult ← FPAdd(operand1, operand2)\nDd ← result\nUpdateFPSR(exception_flags)" }, { "mnemonic": "fsub", "architecture": "ARMv8-A", "full_name": "Floating-point Subtract (Single)", "summary": "Subtracts two single-precision floating-point registers.", "syntax": "FSUB , , ", "encoding": { "format": "Float Data Proc", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | 001 | 1 | 10 | Rn | Rd", "hex_opcode": "0x1E203800", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "001", "clean": "001" }, { "raw": "1", "clean": "1" }, { "raw": "10", "clean": "10" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:13 | 12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" }, { "name": "Sn", "desc": "First source 32-bit floating-point register" }, { "name": "Sm", "desc": "Second source 32-bit floating-point register" } ], "extension": "F.P.", "description": "Floating-point subtraction of two single-precision (32-bit) values. Subtracts operand Sm from operand Sn and writes the result to Sd. FPSR exception flags are updated; condition flags (N, Z, C, V) are unaffected. AArch64-only instruction; uses IEEE 754 rounding mode from FPCR.", "example": "FSUB s0, s1, s2", "pseudocode": "operand1 ← Sn (32-bit float)\noperand2 ← Sm (32-bit float)\nresult ← FPSub(operand1, operand2)\nSd ← result\nUpdateFPSR(exception_flags)" }, { "mnemonic": "fsub", "architecture": "ARMv8-A", "full_name": "Floating-point Subtract (Double)", "summary": "Subtracts two double-precision floating-point registers.", "syntax": "FSUB
, , ", "encoding": { "format": "Float Data Proc", "binary_pattern": "0 | 0 | 0 | 11110 | 01 | 1 | Rm | 001 | 1 | 10 | Rn | Rd", "hex_opcode": "0x1E603800", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "01", "clean": "01" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "001", "clean": "001" }, { "raw": "1", "clean": "1" }, { "raw": "10", "clean": "10" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:13 | 12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Dd", "desc": "Destination 64-bit SIMD/FP register" }, { "name": "Dn", "desc": "First source 64-bit SIMD/FP register" }, { "name": "Dm", "desc": "Second source 64-bit SIMD/FP register" } ], "extension": "F.P.", "description": "Floating-point subtraction of two double-precision (64-bit) values. Subtracts operand Dm from operand Dn and writes the result to Dd. FPSR exception flags are updated; condition flags (N, Z, C, V) are unaffected. AArch64-only instruction; uses IEEE 754 rounding mode from FPCR.", "example": "FSUB d0, d1, d2", "pseudocode": "operand1 ← Dn (64-bit float)\noperand2 ← Dm (64-bit float)\nresult ← FPSub(operand1, operand2)\nDd ← result\nUpdateFPSR(exception_flags)" }, { "mnemonic": "fmul", "architecture": "ARMv8-A", "full_name": "Floating-point Multiply (Single)", "summary": "Multiplies two single-precision floating-point registers.", "syntax": "FMUL , , ", "encoding": { "format": "Float Data Proc", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | 0 | 00010 | Rn | Rd", "hex_opcode": "0x1E200800", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "0", "clean": "0" }, { "raw": "00010", "clean": "00010" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15 | 14:10 | 9:5 | 4:0" }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" }, { "name": "Sn", "desc": "First source 32-bit floating-point register" }, { "name": "Sm", "desc": "Second source 32-bit floating-point register" } ], "extension": "F.P.", "description": "Floating-point multiplication of two single-precision (32-bit) values. Multiplies operand Sn by operand Sm and writes the result to Sd. FPSR exception flags are updated; condition flags (N, Z, C, V) are unaffected. AArch64-only instruction; uses IEEE 754 rounding mode from FPCR.", "example": "FMUL s0, s1, s2", "pseudocode": "operand1 ← Sn (32-bit float)\noperand2 ← Sm (32-bit float)\nresult ← FPMul(operand1, operand2)\nSd ← result\nUpdateFPSR(exception_flags)" }, { "mnemonic": "fmul", "architecture": "ARMv8-A", "full_name": "Floating-point Multiply (Double)", "summary": "Multiplies two double-precision floating-point registers.", "syntax": "FMUL
, , ", "encoding": { "format": "Float Data Proc", "binary_pattern": "0 | 0 | 0 | 11110 | 01 | 1 | Rm | 0 | 00010 | Rn | Rd", "hex_opcode": "0x1E600800", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "01", "clean": "01" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "0", "clean": "0" }, { "raw": "00010", "clean": "00010" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15 | 14:10 | 9:5 | 4:0" }, "operands": [ { "name": "Dd", "desc": "Destination 64-bit SIMD/FP register" }, { "name": "Dn", "desc": "First source 64-bit SIMD/FP register" }, { "name": "Dm", "desc": "Second source 64-bit SIMD/FP register" } ], "extension": "F.P.", "description": "Floating-point multiplication of two double-precision (64-bit) values. Multiplies operand Dn by operand Dm and writes the result to Dd. FPSR exception flags are updated; condition flags (N, Z, C, V) are unaffected. AArch64-only instruction; uses IEEE 754 rounding mode from FPCR.", "example": "FMUL d0, d1, d2", "pseudocode": "operand1 ← Dn (64-bit float)\noperand2 ← Dm (64-bit float)\nresult ← FPMul(operand1, operand2)\nDd ← result\nUpdateFPSR(exception_flags)" }, { "mnemonic": "fdiv", "architecture": "ARMv8-A", "full_name": "Floating-point Divide (Single)", "summary": "Divides two single-precision floating-point registers.", "syntax": "FDIV , , ", "encoding": { "format": "Float Data Proc", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | 0001 | 10 | Rn | Rd", "hex_opcode": "0x1E201800", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "0001", "clean": "0001" }, { "raw": "10", "clean": "10" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Sd", "desc": "Destination 32-bit floating-point register" }, { "name": "Sn", "desc": "Dividend" }, { "name": "Sm", "desc": "Divisor" } ], "extension": "F.P.", "description": "Divides the single-precision floating-point value in Sn by the value in Sm and stores the result in Sd. This instruction operates on 32-bit IEEE 754 floating-point values. The NZCV flags are updated based on the result: N is set if the result is negative, Z if zero, C and V are set according to IEEE 754 semantics. This is an AArch64-only instruction requiring the Floating-Point extension.", "example": "FDIV s0, s1, s2", "pseudocode": "Sd ← Sn ÷ Sm\nN ← Sd[31]\nZ ← (Sd == 0.0)\nC ← (overflow or underflow)\nV ← (invalid operation or overflow)" }, { "mnemonic": "fdiv", "architecture": "ARMv8-A", "full_name": "Floating-point Divide (Double)", "summary": "Divides two double-precision floating-point registers.", "syntax": "FDIV
, , ", "encoding": { "format": "Float Data Proc", "binary_pattern": "0 | 0 | 0 | 11110 | 01 | 1 | Rm | 0001 | 10 | Rn | Rd", "hex_opcode": "0x1E601800", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "01", "clean": "01" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "0001", "clean": "0001" }, { "raw": "10", "clean": "10" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Dd", "desc": "Destination 64-bit SIMD/FP register" }, { "name": "Dn", "desc": "Dividend" }, { "name": "Dm", "desc": "Divisor" } ], "extension": "F.P.", "description": "Divides the double-precision floating-point value in Dn by the value in Dm and stores the result in Dd. This instruction operates on 64-bit IEEE 754 floating-point values. The NZCV flags are updated based on the result: N is set if the result is negative, Z if zero, C and V are set according to IEEE 754 semantics. This is an AArch64-only instruction requiring the Floating-Point extension.", "example": "FDIV d0, d1, d2", "pseudocode": "Dd ← Dn ÷ Dm\nN ← Dd[63]\nZ ← (Dd == 0.0)\nC ← (overflow or underflow)\nV ← (invalid operation or overflow)" }, { "mnemonic": "fcmp", "architecture": "ARMv8-A", "full_name": "Floating-point Compare (Single)", "summary": "Compares two single-precision registers and updates NZCV flags.", "syntax": "FCMP , ", "encoding": { "format": "Float Compare", "binary_pattern": "0 | 0 | 0 | 11110 | 00 | 1 | Rm | 00 | 1000 | Rn | 00 | 000", "hex_opcode": "0x1E202000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "00", "clean": "00" }, { "raw": "1000", "clean": "1000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "00", "clean": "00" }, { "raw": "000", "clean": "000" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:14 | 13:10 | 9:5 | 4:3 | 2:0" }, "operands": [ { "name": "Sn", "desc": "First source 32-bit floating-point register" }, { "name": "Sm", "desc": "Second source 32-bit floating-point register" } ], "extension": "F.P.", "description": "Compares two single-precision floating-point registers (Sn and Sm) and updates the NZCV condition flags based on the result. Handles NaN operands by setting both N and V flags; neither operand being NaN results in N, Z, C, V being set according to the comparison outcome. AArch64 only.", "example": "FCMP s1, s2", "pseudocode": "op1 ← FPUnpack(Sn)\nop2 ← FPUnpack(Sm)\nresult ← FPCompare(op1, op2)\nif isNaN(op1) or isNaN(op2) then\n N ← 1; Z ← 0; C ← 1; V ← 1\nelse if op1 == op2 then\n N ← 0; Z ← 1; C ← 1; V ← 0\nelse if op1 < op2 then\n N ← 1; Z ← 0; C ← 0; V ← 0\nelse\n N ← 0; Z ← 0; C ← 1; V ← 0" }, { "mnemonic": "fcmp", "architecture": "ARMv8-A", "full_name": "Floating-point Compare (Double)", "summary": "Compares two double-precision registers and updates NZCV flags.", "syntax": "FCMP , ", "encoding": { "format": "Float Compare", "binary_pattern": "0 | 0 | 0 | 11110 | 01 | 1 | Rm | 00 | 1000 | Rn | 00 | 000", "hex_opcode": "0x1E602000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "01", "clean": "01" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "00", "clean": "00" }, { "raw": "1000", "clean": "1000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "00", "clean": "00" }, { "raw": "000", "clean": "000" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:16 | 15:14 | 13:10 | 9:5 | 4:3 | 2:0" }, "operands": [ { "name": "Dn", "desc": "First source 64-bit SIMD/FP register" }, { "name": "Dm", "desc": "Second source 64-bit SIMD/FP register" } ], "extension": "F.P.", "description": "Compares two double-precision floating-point registers (Dn and Dm) and updates the NZCV condition flags based on the result. Handles NaN operands by setting both N and V flags; neither operand being NaN results in N, Z, C, V being set according to the comparison outcome. AArch64 only.", "example": "FCMP d1, d2", "pseudocode": "op1 ← FPUnpack(Dn)\nop2 ← FPUnpack(Dm)\nresult ← FPCompare(op1, op2)\nif isNaN(op1) or isNaN(op2) then\n N ← 1; Z ← 0; C ← 1; V ← 1\nelse if op1 == op2 then\n N ← 0; Z ← 1; C ← 1; V ← 0\nelse if op1 < op2 then\n N ← 1; Z ← 0; C ← 0; V ← 0\nelse\n N ← 0; Z ← 0; C ← 1; V ← 0" }, { "mnemonic": "fmov", "architecture": "ARMv8-A", "full_name": "Floating-point Move (Register)", "summary": "Copies value between floating-point registers.", "syntax": "FMOV
, ", "encoding": { "format": "Float Data Proc", "binary_pattern": "0 | 0 | 0 | 11110 | 01 | 10000 | 00 | 10000 | Rn | Rd", "hex_opcode": "0x1E604000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "01", "clean": "01" }, { "raw": "10000", "clean": "10000" }, { "raw": "00", "clean": "00" }, { "raw": "10000", "clean": "10000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21:17 | 16:15 | 14:10 | 9:5 | 4:0" }, "operands": [ { "name": "Dd", "desc": "Destination 64-bit SIMD/FP register" }, { "name": "Dn", "desc": "First source 64-bit SIMD/FP register" } ], "extension": "F.P.", "description": "Copies a 64-bit double-precision floating-point value from Dn to Dd without any conversion or modification. The condition flags NZCV are not affected. This is an AArch64-only instruction requiring the Floating-Point extension.", "example": "FMOV d0, d1", "pseudocode": "Dd ← Dn" }, { "mnemonic": "fmov", "architecture": "ARMv8-A", "full_name": "Floating-point Move (Immediate)", "summary": "Moves immediate value into floating-point register.", "syntax": "FMOV
, #", "encoding": { "format": "Float Imm", "binary_pattern": "0 | 0 | 0 | 11110 | 01 | 1 | imm8 | 100 | 00000 | Rd", "hex_opcode": "0x1E601000", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "01", "clean": "01" }, { "raw": "1", "clean": "1" }, { "raw": "imm8", "clean": "imm8" }, { "raw": "100", "clean": "100" }, { "raw": "00000", "clean": "00000" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:13 | 12:10 | 9:5 | 4:0" }, "operands": [ { "name": "Dd", "desc": "Destination 64-bit SIMD/FP register" }, { "name": "imm", "desc": "Signed immediate value" } ], "extension": "F.P.", "description": "Moves an 8-bit encoded immediate value into a 64-bit double-precision floating-point register Dd. The immediate is expanded to a full 64-bit floating-point value according to the VFPv3 expanded-immediate encoding scheme. The condition flags NZCV are not affected. This is an AArch64-only instruction requiring the Floating-Point extension.", "example": "FMOV d0, #16", "pseudocode": "Dd ← ExpandImmediate(imm8)" }, { "mnemonic": "scvtf", "architecture": "ARMv8-A", "full_name": "Signed Integer Convert to Floating-point", "summary": "Converts signed integer (scalar) to floating-point.", "syntax": "SCVTF
, ", "encoding": { "format": "Float Conversion", "binary_pattern": "1 | 0 | 0 | 11110 | 00 | 1 | 00 | 010 | 000000 | Rn | Rd", "hex_opcode": "0x9E220000", "visual_parts": [ { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "00", "clean": "00" }, { "raw": "010", "clean": "010" }, { "raw": "000000", "clean": "000000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Dd", "desc": "Dest (Double)" }, { "name": "Xn", "desc": "Src (Int64)" } ], "extension": "F.P.", "description": "Converts a 64-bit signed integer value from Xn to a double-precision floating-point value using the current rounding mode, and writes the result to Dd. Does not update the NZCV condition flags. AArch64 only.", "example": "SCVTF d0, x1", "pseudocode": "int_val ← X[n]\nfp_result ← ConvertSignedIntegerToFP(int_val, double-precision, current_rounding_mode)\nD[d] ← FPPack(fp_result)" }, { "mnemonic": "fcvtzs", "architecture": "ARMv8-A", "full_name": "Floating-point Convert to Signed Integer (Round towards Zero)", "summary": "Converts floating-point to signed integer.", "syntax": "FCVTZS , ", "encoding": { "format": "Float Conversion", "binary_pattern": "1 | 0 | 0 | 11110 | 00 | 1 | 11 | 000 | 000000 | Rn | Rd", "hex_opcode": "0x9E380000", "visual_parts": [ { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "11110", "clean": "11110" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "11", "clean": "11" }, { "raw": "000", "clean": "000" }, { "raw": "000000", "clean": "000000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:24 | 23:22 | 21 | 20:19 | 18:16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Xd", "desc": "Dest (Int64)" }, { "name": "Dn", "desc": "Src (Double)" } ], "extension": "F.P.", "description": "Converts a 64-bit double-precision floating-point value in Dn to a signed 64-bit integer, rounding towards zero, and stores the result in Xd. If the result overflows the signed 64-bit range, the result is the most negative or most positive 64-bit integer depending on the input sign. The condition flags NZCV are not affected. This is an AArch64-only instruction requiring the Floating-Point extension.", "example": "FCVTZS x0, d1", "pseudocode": "Xd ← ConvertToSignedInteger(Dn, RoundTowardZero)\nif (overflow) then\n Xd ← (Dn < 0) ? INT64_MIN : INT64_MAX" }, { "mnemonic": "rev", "architecture": "ARMv8-A", "full_name": "Reverse Bytes (32-bit)", "summary": "Reverses the byte order in a 32-bit register (Endianness swap).", "syntax": "REV , ", "encoding": { "format": "Data Processing", "binary_pattern": "0 | 1 | 0 | 11010110 | 00000 | 0000 | 10 | Rn | Rd", "hex_opcode": "0x5AC00800", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "11010110", "clean": "11010110" }, { "raw": "00000", "clean": "00000" }, { "raw": "0000", "clean": "0000" }, { "raw": "10", "clean": "10" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:12 | 11:10 | 9:5 | 4:0" }, "operands": [ { "name": "Wd", "desc": "Destination 32-bit integer register" }, { "name": "Wn", "desc": "First source / base 32-bit integer register" } ], "extension": "Base", "description": "Reverses the byte order of a 32-bit value in Wn and stores the result in Wd, performing endianness conversion. The upper 32 bits of the destination register are zeroed. The condition flags NZCV are not affected. This is an AArch64-only instruction available in the Base instruction set.", "example": "REV w0, w1", "pseudocode": "Wd ← ReverseBytes(Wn)\nXd[63:32] ← 0" }, { "mnemonic": "rbit", "architecture": "ARMv8-A", "full_name": "Reverse Bits (64-bit)", "summary": "Reverses the bit order in a 64-bit register.", "syntax": "RBIT , ", "encoding": { "format": "Data Processing", "binary_pattern": "1 | 1 | 0 | 11010110 | 00000 | 000000 | Rn | Rd", "hex_opcode": "0xDAC00000", "visual_parts": [ { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "11010110", "clean": "11010110" }, { "raw": "00000", "clean": "00000" }, { "raw": "000000", "clean": "000000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30 | 29 | 28:21 | 20:16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Xd", "desc": "Destination 64-bit integer register" }, { "name": "Xn", "desc": "First source / base 64-bit integer register" } ], "extension": "Base", "description": "Reverses the bit order in a 64-bit register, placing the least significant bit at the most significant position. No condition flags are affected. This is an AArch64 instruction with no privilege requirements.", "example": "RBIT x0, x1", "pseudocode": "Xd ← BitReverse(Xn)" }, { "mnemonic": "sxtb", "architecture": "ARMv8-A", "full_name": "Sign Extend Byte", "summary": "Extracts the lowest 8 bits and sign-extends to 32 bits (Alias for SBFM).", "syntax": "SXTB , ", "encoding": { "format": "Bitfield", "binary_pattern": "0 | 00 | 100110 | 0 | 000000 | 000111 | Rn | Rd", "hex_opcode": "0x13001C00", "visual_parts": [ { "raw": "0", "clean": "0" }, { "raw": "00", "clean": "00" }, { "raw": "100110", "clean": "100110" }, { "raw": "0", "clean": "0" }, { "raw": "000000", "clean": "000000" }, { "raw": "000111", "clean": "000111" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30:29 | 28:23 | 22 | 21:16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Wd", "desc": "Destination 32-bit integer register" }, { "name": "Wn", "desc": "First source / base 32-bit integer register" } ], "extension": "Base", "description": "Extracts the lowest 8 bits of a 32-bit register and sign-extends the result to fill all 32 bits. No condition flags are affected. This is an AArch64 alias for SBFM (Signed Bitfield Move) with bit positions 0 and 7.", "example": "SXTB w0, w1", "pseudocode": "Wd ← SignExtend(Wn[7:0], 32)" }, { "mnemonic": "sxtw", "architecture": "ARMv8-A", "full_name": "Sign Extend Word", "summary": "Sign-extends a 32-bit register to 64 bits (Alias for SBFM).", "syntax": "SXTW , ", "encoding": { "format": "Bitfield", "binary_pattern": "1 | 00 | 100110 | 1 | 000000 | 011111 | Rn | Rd", "hex_opcode": "0x93407C00", "visual_parts": [ { "raw": "1", "clean": "1" }, { "raw": "00", "clean": "00" }, { "raw": "100110", "clean": "100110" }, { "raw": "1", "clean": "1" }, { "raw": "000000", "clean": "000000" }, { "raw": "011111", "clean": "011111" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" } ], "bit_positions": "31 | 30:29 | 28:23 | 22 | 21:16 | 15:10 | 9:5 | 4:0" }, "operands": [ { "name": "Xd", "desc": "Dest (64)" }, { "name": "Wn", "desc": "Source (32)" } ], "extension": "Base", "description": "Sign-extends a 32-bit value to fill 64 bits, replicating bit 31 into all upper bits. No condition flags are affected. This is an AArch64 alias for SBFM with bit positions 0 and 31.", "example": "SXTW x0, w1", "pseudocode": "Xd ← SignExtend(Wn, 64)" }, { "mnemonic": "adc", "architecture": "ARMv8-A", "full_name": "Add with Carry (A32)", "summary": "Adds two 32-bit values and the Carry flag.", "syntax": "ADC{S} , , {, }", "encoding": { "format": "Data Proc", "binary_pattern": "cond | 0000 | 101 | 0 | Rn | Rd | imm5 | stype | 0 | Rm", "hex_opcode": "0x00A00000", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "0000", "clean": "0000" }, { "raw": "101", "clean": "101" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "imm5", "clean": "imm5" }, { "raw": "stype", "clean": "stype" }, { "raw": "0", "clean": "0" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:24 | 23:21 | 20 | 19:16 | 15:12 | 11:7 | 6:5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (Base)", "description": "Adds two 32-bit values from Rn and Rm along with the Carry flag (C) and stores the result in Rd. If the S bit is set, the condition flags are updated: N and Z reflect the result, C is set on unsigned overflow, V is set on signed overflow. The shift operand is optional and applies a shift to Rm before the addition. This is an A32 instruction with conditional execution.", "example": "ADC r0, r1, r2", "pseudocode": "shifted_Rm ← ApplyShift(Rm, shift)\nresult ← Rn + shifted_Rm + C\nRd ← result\nif S then\n N ← result[31]\n Z ← (result == 0)\n C ← CarryOut(Rn + shifted_Rm + C)\n V ← OverflowFrom(Rn + shifted_Rm + C)" }, { "mnemonic": "add", "architecture": "ARMv8-A", "full_name": "Add (A32)", "summary": "Adds two 32-bit values.", "syntax": "ADD{S} , , {, }", "encoding": { "format": "Data Proc", "binary_pattern": "cond | 0000 | 100 | 0 | Rn | Rd | imm5 | stype | 0 | Rm", "hex_opcode": "0x00800000", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "0000", "clean": "0000" }, { "raw": "100", "clean": "100" }, { "raw": "0", "clean": "0" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "imm5", "clean": "imm5" }, { "raw": "stype", "clean": "stype" }, { "raw": "0", "clean": "0" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:24 | 23:21 | 20 | 19:16 | 15:12 | 11:7 | 6:5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (Base)", "description": "Adds two 32-bit operands and stores the result in the destination register. If the S bit is set, the condition flags (N, Z, C, V) are updated based on the result; otherwise they are unaffected. This is an A32 instruction where the condition code (cond) field determines execution based on the current condition flags.", "example": "ADD r0, r1, r2", "pseudocode": "result ← Rn + (Rm << shift_amount)\nRd ← result[31:0]\nif S then\n N ← result[31]\n Z ← (result == 0)\n C ← CarryOut(Rn, Rm << shift_amount)\n V ← OverflowFrom(Rn, Rm << shift_amount)" }, { "mnemonic": "adr", "architecture": "ARMv8-A", "full_name": "Form PC-relative Address (A32)", "summary": "Adds an immediate value to the PC register.", "syntax": "ADR ,
, , #", "encoding": { "format": "NEON Shift", "binary_pattern": "1111001 | U | 1 | D | imm6 | Vd | 0001 | L | 0 | M | 1 | Vm", "hex_opcode": "0xF2800110", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "U", "clean": "U" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "imm6", "clean": "imm6" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0001", "clean": "0001" }, { "raw": "L", "clean": "L" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Dest/Acc" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" }, { "name": "imm", "desc": "Signed immediate value" } ], "extension": "NEON (SIMD)", "description": "Shifts each element in the source register right by the immediate shift amount and accumulates (adds) the shifted result into the corresponding element of the destination register. The shift amount is treated as unsigned. No condition flags are modified. This is a NEON instruction available in both A32 and T32 instruction sets.", "example": "VSRA.dt q0, q2, #16", "pseudocode": "for i = 0 to elements_in_Qd - 1\n shift_amount ← imm6\n shifted ← Qm[i] >> shift_amount\n Qd[i] ← Qd[i] + shifted\nendfor" }, { "mnemonic": "vrsra", "architecture": "ARMv8-A", "full_name": "Vector Rounding Shift Right and Accumulate", "summary": "Shifts right with rounding and adds to accumulator.", "syntax": "VRSRA.
, , #", "encoding": { "format": "NEON Shift", "binary_pattern": "1111001 | U | 1 | D | imm6 | Vd | 0011 | L | 0 | M | 1 | Vm", "hex_opcode": "0xF2800310", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "U", "clean": "U" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "imm6", "clean": "imm6" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0011", "clean": "0011" }, { "raw": "L", "clean": "L" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Dest/Acc" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" }, { "name": "imm", "desc": "Signed immediate value" } ], "extension": "NEON (SIMD)", "description": "Shifts each element in the source register right by the immediate shift amount with rounding (adding 1 to bit position before the round point), then accumulates the rounded result into the destination register. The shift amount is unsigned. No condition flags are modified. This is a NEON instruction available in both A32 and T32 instruction sets.", "example": "VRSRA.dt q0, q2, #16", "pseudocode": "for i = 0 to elements_in_Qd - 1\n shift_amount ← imm6\n if shift_amount > 0 then\n rounded ← (Qm[i] + (1 << (shift_amount - 1))) >> shift_amount\n else\n rounded ← Qm[i]\n endif\n Qd[i] ← Qd[i] + rounded\nendfor" }, { "mnemonic": "vsli", "architecture": "ARMv8-A", "full_name": "Vector Shift Left and Insert", "summary": "Shifts bits left and inserts into destination (merging).", "syntax": "VSLI. , , #", "encoding": { "format": "NEON Shift", "binary_pattern": "1111001 | 1 | 1 | D | imm6 | Vd | 0101 | L | 1 | M | 1 | Vm", "hex_opcode": "0xF3800550", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "imm6", "clean": "imm6" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0101", "clean": "0101" }, { "raw": "L", "clean": "L" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" }, { "name": "imm", "desc": "Signed immediate value" } ], "extension": "NEON (SIMD)", "description": "Shifts each element in the source register left by the immediate shift amount and inserts the shifted bits into the low bits of the destination element, leaving the high bits of the destination unchanged (merging operation). The shift amount is unsigned. No condition flags are modified. This is a NEON instruction available in both A32 and T32 instruction sets.", "example": "VSLI.size q0, q2, #16", "pseudocode": "for i = 0 to elements_in_Qd - 1\n shift_amount ← imm6\n shifted ← Qm[i] << shift_amount\n mask ← (1 << shift_amount) - 1\n Qd[i] ← (Qd[i] & ~mask) | (shifted & mask)\nendfor" }, { "mnemonic": "vsri", "architecture": "ARMv8-A", "full_name": "Vector Shift Right and Insert", "summary": "Shifts bits right and inserts into destination.", "syntax": "VSRI. , , #", "encoding": { "format": "NEON Shift", "binary_pattern": "1111001 | 1 | 1 | D | imm6 | Vd | 0100 | L | 1 | M | 1 | Vm", "hex_opcode": "0xF3800450", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "imm6", "clean": "imm6" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0100", "clean": "0100" }, { "raw": "L", "clean": "L" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" }, { "name": "imm", "desc": "Signed immediate value" } ], "extension": "NEON (SIMD)", "description": "Shifts each element in the source register right by the immediate shift amount and inserts the shifted bits into the high bits of the destination element, leaving the low bits of the destination unchanged (merging operation). The shift amount is unsigned. No condition flags are modified. This is a NEON instruction available in both A32 and T32 instruction sets.", "example": "VSRI.size q0, q2, #16", "pseudocode": "for i = 0 to elements_in_Qd - 1\n shift_amount ← imm6\n shifted ← Qm[i] >> shift_amount\n mask ← ((1 << (element_size - shift_amount)) - 1) << shift_amount\n Qd[i] ← (Qd[i] & ~mask) | (shifted & mask)\nendfor" }, { "mnemonic": "vrshl", "architecture": "ARMv8-A", "full_name": "Vector Rounding Shift Left", "summary": "Shifts left with rounding based on a register value.", "syntax": "VRSHL.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 0101 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2000500", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "U", "clean": "U" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0101", "clean": "0101" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" }, { "name": "Qn", "desc": "Shift Reg" } ], "extension": "NEON (SIMD)", "description": "Shifts each element in Qm left or right by the amount specified in the corresponding element of Qn with rounding applied when shifting right. Positive shift amounts shift left; negative amounts shift right with rounding. Results are stored in Qd. No condition flags are modified. This is a NEON instruction available in both A32 and T32 instruction sets.", "example": "VRSHL.dt q0, q2, q1", "pseudocode": "for i = 0 to elements_in_Qd - 1\n shift_amount ← signed(Qn[i])\n if shift_amount >= 0 then\n Qd[i] ← Qm[i] << shift_amount\n else\n if shift_amount <= -element_size then\n Qd[i] ← 0\n else\n rounded ← Qm[i] + (1 << (-shift_amount - 1))\n Qd[i] ← rounded >> (-shift_amount)\n endif\n endif\nendfor" }, { "mnemonic": "vrshr", "architecture": "ARMv8-A", "full_name": "Vector Rounding Shift Right", "summary": "Shifts right with rounding based on immediate.", "syntax": "VRSHR.
, , #", "encoding": { "format": "NEON Shift", "binary_pattern": "1111001 | U | 1 | D | imm6 | Vd | 0010 | L | 0 | M | 1 | Vm", "hex_opcode": "0xF2800210", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "U", "clean": "U" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "imm6", "clean": "imm6" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0010", "clean": "0010" }, { "raw": "L", "clean": "L" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" }, { "name": "imm", "desc": "Signed immediate value" } ], "extension": "NEON (SIMD)", "description": "Shifts each element in the source register right by the immediate shift amount with rounding (the bit at the shift position and all bits to the right are rounded according to ARM rounding rules). Results are stored in the destination register. No condition flags are modified. This is a NEON instruction available in both A32 and T32 instruction sets.", "example": "VRSHR.dt q0, q2, #16", "pseudocode": "for i = 0 to elements_in_Qd - 1\n shift_amount ← imm6\n if shift_amount >= element_size then\n Qd[i] ← 0\n else\n rounding_bit ← (Qm[i] >> (shift_amount - 1)) & 1\n Qd[i] ← (Qm[i] >> shift_amount) + rounding_bit\n endif\nendfor" }, { "mnemonic": "vrshrn", "architecture": "ARMv8-A", "full_name": "Vector Rounding Shift Right Narrow", "summary": "Shifts right, rounds, and narrows (2N -> N bits).", "syntax": "VRSHRN.
, , #", "encoding": { "format": "NEON Shift", "binary_pattern": "111100111 | D | 11 | size | 10 | Vd | 0 | 0100 | 0 | M | 0 | Vm", "hex_opcode": "0xF3B20200", "visual_parts": [ { "raw": "111100111", "clean": "111100111" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "size", "clean": "size" }, { "raw": "10", "clean": "10" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0", "clean": "0" }, { "raw": "0100", "clean": "0100" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Dd", "desc": "Dest Narrow" }, { "name": "Qm", "desc": "Src Wide" }, { "name": "imm", "desc": "Signed immediate value" } ], "extension": "NEON (SIMD)", "description": "Shifts each element of the 128-bit source register right by the immediate shift amount with rounding, then narrows the result from 2N bits to N bits (halving the element width), and stores into the 64-bit destination register. The high half of the shift result is kept. No condition flags are modified. This is a NEON instruction available in both A32 and T32 instruction sets.", "example": "VRSHRN.dt d0, q2, #16", "pseudocode": "for i = 0 to elements_in_Dd - 1\n shift_amount ← imm6\n if shift_amount > 2 × element_size then\n Dd[i] ← 0\n else\n value ← Qm[i]\n rounding_correction ← (1 << (shift_amount - 1))\n rounded ← (value + rounding_correction) >> shift_amount\n Dd[i] ← saturate(rounded, element_size / 2)\n endif\nendfor" }, { "mnemonic": "vqshl", "architecture": "ARMv8-A", "full_name": "Vector Saturating Shift Left (Register)", "summary": "Shifts left with saturation based on register.", "syntax": "VQSHL.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 0100 | N | 1 | M | 1 | Vm", "hex_opcode": "0xF2000450", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "U", "clean": "U" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0100", "clean": "0100" }, { "raw": "N", "clean": "N" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" }, { "name": "Qn", "desc": "Shift Reg" } ], "extension": "NEON (SIMD)", "description": "Vector Saturating Shift Left (Register) shifts each element in Qm left by the amount specified by the corresponding element in Qn, saturating the result to the range of the operand data type. The shift amount is interpreted as a signed value; negative amounts perform a right shift. All condition flags (N, Z, C, V) remain unaffected. This is an A32/T32 NEON instruction that operates on 128-bit quad registers.", "example": "VQSHL.dt q0, q2, q1", "pseudocode": "for i = 0 to elements-1 do\n shift_amount ← SignExtend(Qn[i])\n if shift_amount >= 0 then\n result ← SatQ(Qm[i] << shift_amount, esize)\n else\n result ← SatQ(Qm[i] >> (-shift_amount), esize)\n Qd[i] ← result" }, { "mnemonic": "vqshl", "architecture": "ARMv8-A", "full_name": "Vector Saturating Shift Left (Immediate)", "summary": "Shifts left with saturation based on immediate.", "syntax": "VQSHL.
, , #", "encoding": { "format": "NEON Shift", "binary_pattern": "1111001 | U | 1 | D | imm6 | Vd | 011 | 1 | L | 0 | M | 1 | Vm", "hex_opcode": "0xF2800710", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "U", "clean": "U" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "imm6", "clean": "imm6" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "011", "clean": "011" }, { "raw": "1", "clean": "1" }, { "raw": "L", "clean": "L" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:16 | 15:12 | 11:9 | 8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" }, { "name": "imm", "desc": "Signed immediate value" } ], "extension": "NEON (SIMD)", "description": "Vector Saturating Shift Left (Immediate) shifts each element in Qm left by an immediate value, saturating the result to the range of the operand data type. The immediate is a signed value encoded in imm6; positive values shift left, negative values (when sign-extended) would shift right. All condition flags (N, Z, C, V) remain unaffected. This is an A32/T32 NEON instruction.", "example": "VQSHL.dt q0, q2, #16", "pseudocode": "shift_amount ← SignExtend(imm6, 6)\nfor i = 0 to elements-1 do\n result ← SatQ(Qm[i] << shift_amount, esize)\n Qd[i] ← result" }, { "mnemonic": "vqshr", "architecture": "ARMv8-A", "full_name": "Vector Saturating Shift Right (Unsigned)", "summary": "Shifts right with saturation (Unsigned).", "syntax": "VQSHR.U , , #", "encoding": { "format": "NEON Shift", "binary_pattern": "11110010 | 1 | D | imm6 | Vd | 1101 | L | Q | M | 1 | Vm", "hex_opcode": "0xF2800910", "visual_parts": [ { "raw": "11110010", "clean": "11110010" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "imm6", "clean": "imm6" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1101", "clean": "1101" }, { "raw": "L", "clean": "L" }, { "raw": "Q", "clean": "Q" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ] }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" }, { "name": "imm", "desc": "Signed immediate value" } ], "extension": "NEON (SIMD)", "description": "Vector Saturating Shift Right (Unsigned) shifts each unsigned element in Qm right by an immediate value, saturating underflow to zero. The immediate specifies the right shift count. All condition flags (N, Z, C, V) remain unaffected. This is an A32/T32 NEON instruction for unsigned data types.", "example": "VQSHR.Usize q0, q2, #16", "pseudocode": "shift_amount ← imm6\nfor i = 0 to elements-1 do\n if shift_amount > 0 then\n result ← SatQ(Qm[i] >> shift_amount, 0, max_unsigned_value)\n else\n result ← Qm[i]\n Qd[i] ← result" }, { "mnemonic": "vqshrn", "architecture": "ARMv8-A", "full_name": "Vector Saturating Shift Right Narrow", "summary": "Shifts right, saturates, and narrows.", "syntax": "VQSHRN.
, , #", "encoding": { "format": "NEON Shift", "binary_pattern": "1111001 | U | 1 | D | imm6 | Vd | 100 | 1 | 0 | 0 | M | 1 | Vm", "hex_opcode": "0xF2800910", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "U", "clean": "U" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "imm6", "clean": "imm6" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "100", "clean": "100" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:16 | 15:12 | 11:9 | 8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Dd", "desc": "Dest Narrow" }, { "name": "Qm", "desc": "Src Wide" }, { "name": "imm", "desc": "Signed immediate value" } ], "extension": "NEON (SIMD)", "description": "Vector Saturating Shift Right Narrow shifts each element in Qm right by an immediate value, saturates to the range of the narrower result type, then packs the narrowed results into the destination Dd. This operation reduces element size by half and narrows the register from 128-bit to 64-bit. All condition flags (N, Z, C, V) remain unaffected. This is an A32/T32 NEON instruction.", "example": "VQSHRN.dt d0, q2, #16", "pseudocode": "shift_amount ← imm6\nfor i = 0 to narrow_elements-1 do\n wide_value ← Qm[i]\n shifted ← wide_value >> shift_amount\n result ← SatQ(shifted, narrow_esize)\n Dd[i] ← result" }, { "mnemonic": "vqshlu", "architecture": "ARMv8-A", "full_name": "Vector Saturating Shift Left Unsigned", "summary": "Shifts signed elements left, saturating to unsigned result.", "syntax": "VQSHLU.
, , #", "encoding": { "format": "NEON Shift", "binary_pattern": "1111001 | 1 | 1 | D | imm6 | Vd | 011 | 0 | L | 1 | M | 1 | Vm", "hex_opcode": "0xF3800650", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "imm6", "clean": "imm6" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "011", "clean": "011" }, { "raw": "0", "clean": "0" }, { "raw": "L", "clean": "L" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:16 | 15:12 | 11:9 | 8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" }, { "name": "imm", "desc": "Signed immediate value" } ], "extension": "NEON (SIMD)", "description": "Vector Saturating Shift Left Unsigned shifts each signed element in Qm left by an immediate value and saturates the result to an unsigned range. Elements that overflow are clamped to the maximum unsigned value of the result type. All condition flags (N, Z, C, V) remain unaffected. This is an A32/T32 NEON instruction.", "example": "VQSHLU.dt q0, q2, #16", "pseudocode": "shift_amount ← imm6\nfor i = 0 to elements-1 do\n result ← SatQ(Qm[i] << shift_amount, 0, max_unsigned_value)\n Qd[i] ← result" }, { "mnemonic": "vqrshl", "architecture": "ARMv8-A", "full_name": "Vector Saturating Rounding Shift Left", "summary": "Shifts left with saturation and rounding.", "syntax": "VQRSHL.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 0 | D | size | Vn | Vd | 0101 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF2000510", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "U", "clean": "U" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0101", "clean": "0101" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" }, { "name": "Qn", "desc": "Shift Reg" } ], "extension": "NEON (SIMD)", "description": "Vector Saturating Rounding Shift Left shifts each element in Qm left by the amount specified in the corresponding element of Qn, with saturation and rounding applied. When the shift amount is negative, a right shift with rounding is performed. All condition flags (N, Z, C, V) remain unaffected. This is an A32/T32 NEON instruction.", "example": "VQRSHL.dt q0, q2, q1", "pseudocode": "for i = 0 to elements-1 do\n shift_amount ← SignExtend(Qn[i])\n if shift_amount >= 0 then\n result ← SatQ(Qm[i] << shift_amount, esize)\n else\n rounding_bit ← Qm[i][(-shift_amount-1)]\n shifted ← Qm[i] >> (-shift_amount)\n result ← SatQ(shifted + rounding_bit, esize)\n Qd[i] ← result" }, { "mnemonic": "vqrshrn", "architecture": "ARMv8-A", "full_name": "Vector Saturating Rounding Shift Right Narrow", "summary": "Shifts right, saturates, rounds, and narrows.", "syntax": "VQRSHRN.
, , #", "encoding": { "format": "NEON Shift", "binary_pattern": "111100111 | D | 11 | size | 10 | Vd | 0 | 010 | op | M | 0 | Vm", "hex_opcode": "0xF3B20280", "visual_parts": [ { "raw": "111100111", "clean": "111100111" }, { "raw": "D", "clean": "D" }, { "raw": "11", "clean": "11" }, { "raw": "size", "clean": "size" }, { "raw": "10", "clean": "10" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0", "clean": "0" }, { "raw": "010", "clean": "010" }, { "raw": "op", "clean": "op" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:23 | 22 | 21:20 | 19:18 | 17:16 | 15:12 | 11 | 10:8 | 7:6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Dd", "desc": "Dest Narrow" }, { "name": "Qm", "desc": "Src Wide" }, { "name": "imm", "desc": "Signed immediate value" } ], "extension": "NEON (SIMD)", "description": "Vector Saturating Rounding Shift Right Narrow shifts each element in Qm right by an immediate value with rounding, saturates to the narrower result type, and packs the narrowed results into Dd. Rounding is applied before truncation and narrowing. This reduces element size by half and narrows the register from 128-bit to 64-bit. All condition flags (N, Z, C, V) remain unaffected. This is an A32/T32 NEON instruction.", "example": "VQRSHRN.dt d0, q2, #16", "pseudocode": "shift_amount ← imm6\nfor i = 0 to narrow_elements-1 do\n wide_value ← Qm[i]\n rounding_bit ← wide_value[shift_amount-1]\n shifted ← wide_value >> shift_amount\n rounded ← shifted + rounding_bit\n result ← SatQ(rounded, narrow_esize)\n Dd[i] ← result" }, { "mnemonic": "vacge", "architecture": "ARMv8-A", "full_name": "Vector Absolute Compare Greater or Equal", "summary": "Compares absolute values (|Vn| >= |Vm|).", "syntax": "VACGE.F32 , , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | 1 | 0 | D | 0 | sz | Vn | Vd | 1110 | N | 0 | M | 1 | Vm", "hex_opcode": "0xF3000E10", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "0", "clean": "0" }, { "raw": "sz", "clean": "sz" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1110", "clean": "1110" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Dest Mask" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Vector Absolute Compare Greater or Equal compares the absolute values of corresponding floating-point elements in Qn and Qm, setting each element in Qd to all 1s (true) if |Qn[i]| >= |Qm[i]|, or all 0s (false) otherwise. The comparison is per-element on 32-bit floating-point values. All condition flags (N, Z, C, V) remain unaffected. This is an A32/T32 NEON floating-point instruction.", "example": "VACGE.F32 q0, q1, q2", "pseudocode": "for i = 0 to elements-1 do\n if FPAbs(Qn[i]) >= FPAbs(Qm[i]) then\n Qd[i] ← 0xFFFFFFFF\n else\n Qd[i] ← 0x00000000" }, { "mnemonic": "vacgt", "architecture": "ARMv8-A", "full_name": "Vector Absolute Compare Greater Than", "summary": "Compares absolute values (|Vn| > |Vm|).", "syntax": "VACGT.F32 , , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | 1 | 0 | D | 1 | sz | Vn | Vd | 1110 | N | 1 | M | 1 | Vm", "hex_opcode": "0xF3200E50", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "1", "clean": "1" }, { "raw": "sz", "clean": "sz" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1110", "clean": "1110" }, { "raw": "N", "clean": "N" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "1", "clean": "1" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21 | 20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Dest Mask" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Performs a vector absolute comparison of floating-point elements, setting each element of the destination to all 1s if |Vn| > |Vm|, otherwise 0s. This is a NEON floating-point comparison that operates on F32 elements in 128-bit registers. No condition flags are modified; the result is a per-element mask stored in the destination register.", "example": "VACGT.F32 q0, q1, q2", "pseudocode": "for i = 0 to 3\n if abs(Qn[i]) > abs(Qm[i]) then\n Qd[i] ← 0xFFFFFFFF\n else\n Qd[i] ← 0x00000000" }, { "mnemonic": "vabal", "architecture": "ARMv8-A", "full_name": "Vector Absolute Difference and Accumulate Long", "summary": "Computes absolute difference of narrow elements and adds to wide acc.", "syntax": "VABAL.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 1 | D | size | Vn | Vd | 0101 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2800500", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "U", "clean": "U" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0101", "clean": "0101" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Dest Wide" }, { "name": "Dn", "desc": "First source 64-bit SIMD/FP register" }, { "name": "Dm", "desc": "Second source 64-bit SIMD/FP register" } ], "extension": "NEON (SIMD)", "description": "Computes the absolute difference of narrow elements from two double-width registers and accumulates (adds) the widened result to a quad-width accumulator register. The operand size is determined by the data type specifier (sz field controls .I8, .I16, or .I32 variants). No condition flags are affected; saturation may occur and set the QC flag if enabled.", "example": "VABAL.dt q0, d1, d2", "pseudocode": "for i = 0 to (64 / esize - 1)\n diff ← abs(Dn[i] - Dm[i])\n Qd[i] ← Qd[i] + diff_widened" }, { "mnemonic": "vabdl", "architecture": "ARMv8-A", "full_name": "Vector Absolute Difference Long", "summary": "Computes absolute difference of narrow elements to wide result.", "syntax": "VABDL.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | U | 1 | D | size | Vn | Vd | 0111 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2800700", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "U", "clean": "U" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0111", "clean": "0111" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Dest Wide" }, { "name": "Dn", "desc": "First source 64-bit SIMD/FP register" }, { "name": "Dm", "desc": "Second source 64-bit SIMD/FP register" } ], "extension": "NEON (SIMD)", "description": "Computes the absolute difference of narrow elements from two double-width registers and widens the result to quad-width. The operand size is determined by the data type specifier (sz field controls .I8, .I16, or .I32 variants). No condition flags are affected; the result is written to the destination without saturation.", "example": "VABDL.dt q0, d1, d2", "pseudocode": "for i = 0 to (64 / esize - 1)\n diff ← abs(Dn[i] - Dm[i])\n Qd[i] ← diff_widened" }, { "mnemonic": "vraddhn", "architecture": "ARMv8-A", "full_name": "Vector Rounding Add High Narrow", "summary": "Adds wide elements, rounds, and returns high narrow half.", "syntax": "VRADDHN.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | 1 | 1 | D | size | Vn | Vd | 0100 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF3800400", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0100", "clean": "0100" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Dd", "desc": "Dest Narrow" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Adds corresponding wide elements from two quad-width registers, applies rounding (round to nearest, ties to even), and returns the high half of each widened result as narrow elements in a double-width destination. The operand size is determined by the data type specifier (sz field controls .I16, .I32, or .I64 variants). No condition flags are affected.", "example": "VRADDHN.dt d0, q1, q2", "pseudocode": "for i = 0 to (128 / (esize * 2) - 1)\n sum ← Qn[i] + Qm[i]\n rounded ← sum + (1 << (esize - 1))\n Dd[i] ← (rounded >> esize)[esize - 1:0]" }, { "mnemonic": "vsubhn", "architecture": "ARMv8-A", "full_name": "Vector Subtract High Narrow", "summary": "Subtracts wide elements and returns high narrow half.", "syntax": "VSUBHN.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 1 | D | size | Vn | Vd | 0110 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2800600", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0110", "clean": "0110" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Dd", "desc": "Dest Narrow" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Subtracts wide elements of the second quad-width register from the first, and returns the high half of the result as narrow elements in a double-width destination. The operand size is determined by the data type specifier (sz field controls .I16, .I32, or .I64 variants). No condition flags are affected; no rounding is applied.", "example": "VSUBHN.dt d0, q1, q2", "pseudocode": "for i = 0 to (128 / (esize * 2) - 1)\n diff ← Qn[i] - Qm[i]\n Dd[i] ← (diff >> esize)[esize - 1:0]" }, { "mnemonic": "vrsubhn", "architecture": "ARMv8-A", "full_name": "Vector Rounding Subtract High Narrow", "summary": "Subtracts wide elements, rounds, and returns high narrow half.", "syntax": "VRSUBHN.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | 1 | 1 | D | size | Vn | Vd | 0110 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF3800600", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "0110", "clean": "0110" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Dd", "desc": "Dest Narrow" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Subtracts wide elements of the second quad-width register from the first, applies rounding (round to nearest), and returns the high half of the result as narrow elements in a double-width destination. The operand size is determined by the data type specifier (sz field controls .I16, .I32, or .I64 variants). No condition flags are affected.", "example": "VRSUBHN.dt d0, q1, q2", "pseudocode": "for i = 0 to (128 / (esize * 2) - 1)\n diff ← Qn[i] - Qm[i]\n rounded ← diff + (1 << (esize - 1))\n Dd[i] ← (rounded >> esize)[esize - 1:0]" }, { "mnemonic": "vqdmlal", "architecture": "ARMv8-A", "full_name": "Vector Saturating Doubling Multiply Accumulate Long", "summary": "Multiplies, doubles, saturates, and adds to accumulator (High precision DSP).", "syntax": "VQDMLAL.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 1 | D | size | Vn | Vd | 10 | 0 | 1 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2800900", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Dest Wide" }, { "name": "Dn", "desc": "First source 64-bit SIMD/FP register" }, { "name": "Dm", "desc": "Second source 64-bit SIMD/FP register" } ], "extension": "NEON (SIMD)", "description": "Performs a saturating doubling multiply of corresponding narrow elements, then accumulates (adds) the doubled products to a quad-width destination register. The multiplication is doubled with saturation; the operand size is determined by the data type specifier (sz field controls .S16 or .S32 variants). The QC (saturation) flag may be set if overflow occurs during doubling or accumulation.", "example": "VQDMLAL.dt q0, d1, d2", "pseudocode": "for i = 0 to (64 / esize - 1)\n product ← Dn[i] * Dm[i]\n doubled ← SatMul(product, 2) ; saturating double\n Qd[i] ← SatAdd(Qd[i], doubled)" }, { "mnemonic": "vqdmlsl", "architecture": "ARMv8-A", "full_name": "Vector Saturating Doubling Multiply Subtract Long", "summary": "Multiplies, doubles, saturates, and subtracts from accumulator.", "syntax": "VQDMLSL.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 1 | D | size | Vn | Vd | 10 | 1 | 1 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2800B00", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "10", "clean": "10" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Dest Wide" }, { "name": "Dn", "desc": "First source 64-bit SIMD/FP register" }, { "name": "Dm", "desc": "Second source 64-bit SIMD/FP register" } ], "extension": "NEON (SIMD)", "description": "Performs a saturating doubling multiply of corresponding narrow elements, then subtracts the doubled products from a quad-width destination register. The multiplication is doubled with saturation; the operand size is determined by the data type specifier (sz field controls .S16 or .S32 variants). The QC (saturation) flag may be set if overflow occurs during doubling or subtraction.", "example": "VQDMLSL.dt q0, d1, d2", "pseudocode": "for i = 0 to (64 / esize - 1)\n product ← Dn[i] * Dm[i]\n doubled ← SatMul(product, 2) ; saturating double\n Qd[i] ← SatSub(Qd[i], doubled)" }, { "mnemonic": "vqdmulh", "architecture": "ARMv8-A", "full_name": "Vector Saturating Doubling Multiply High", "summary": "Multiplies, doubles, saturates, and keeps high half.", "syntax": "VQDMULH.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 0 | D | size | Vn | Vd | 1011 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2000B00", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1011", "clean": "1011" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Performs signed fixed-point saturating doubling multiply on NEON vector elements, returning the high half of the doubled result. Each element in Qn is multiplied by the corresponding element in Qm, the result is doubled, saturated to the data type range, and the high half is written to Qd. The NEON condition flags are not affected; saturation is indicated via the FPSCR QC bit if the result overflows.", "example": "VQDMULH.dt q0, q1, q2", "pseudocode": "for i = 0 to elements_in_128bit(dt) - 1 do\n product ← (Qn[i] * Qm[i]) * 2\n Qd[i] ← SignedSaturate(product, dt)\nFPSCR.QC ← FPSCR.QC OR (product overflowed)" }, { "mnemonic": "vqrdmulh", "architecture": "ARMv8-A", "full_name": "Vector Saturating Rounding Doubling Multiply High", "summary": "Fixed-point multiply with rounding and saturation.", "syntax": "VQRDMULH.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | 1 | 0 | D | size | Vn | Vd | 1011 | N | 1 | M | 0 | Vm", "hex_opcode": "0xF3000B40", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1011", "clean": "1011" }, { "raw": "N", "clean": "N" }, { "raw": "1", "clean": "1" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Destination 128-bit SIMD register" }, { "name": "Qn", "desc": "First source 128-bit SIMD register" }, { "name": "Qm", "desc": "Second source 128-bit SIMD register" } ], "extension": "NEON (SIMD)", "description": "Performs signed fixed-point saturating rounding doubling multiply on NEON vector elements, returning the high half with rounding. Each element in Qn is multiplied by the corresponding element in Qm, the result is doubled with rounding applied (via addition of 0x80000000 for 32-bit or 0x8000 for 16-bit before right-shift), saturated to the data type range, and the high half is written to Qd. The NEON condition flags are not affected; saturation is indicated via the FPSCR QC bit.", "example": "VQRDMULH.dt q0, q1, q2", "pseudocode": "for i = 0 to elements_in_128bit(dt) - 1 do\n product ← (Qn[i] * Qm[i]) * 2\n if dt == S32 then\n product ← (product + 0x80000000) >> 32\n else\n product ← (product + 0x8000) >> 16\n Qd[i] ← SignedSaturate(product, dt)\nFPSCR.QC ← FPSCR.QC OR (saturation occurred)" }, { "mnemonic": "vqdmull", "architecture": "ARMv8-A", "full_name": "Vector Saturating Doubling Multiply Long", "summary": "Multiplies narrow elements, doubles, and saturates into wide elements.", "syntax": "VQDMULL.
, , ", "encoding": { "format": "NEON 3-Reg", "binary_pattern": "1111001 | 0 | 1 | D | size | Vn | Vd | 1101 | N | 0 | M | 0 | Vm", "hex_opcode": "0xF2800D00", "visual_parts": [ { "raw": "1111001", "clean": "1111001" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "D", "clean": "D" }, { "raw": "size", "clean": "size" }, { "raw": "Vn", "clean": "Vn" }, { "raw": "Vd", "clean": "Vd" }, { "raw": "1101", "clean": "1101" }, { "raw": "N", "clean": "N" }, { "raw": "0", "clean": "0" }, { "raw": "M", "clean": "M" }, { "raw": "0", "clean": "0" }, { "raw": "Vm", "clean": "Vm" } ], "bit_positions": "31:25 | 24 | 23 | 22 | 21:20 | 19:16 | 15:12 | 11:8 | 7 | 6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Qd", "desc": "Dest Wide" }, { "name": "Dn", "desc": "First source 64-bit SIMD/FP register" }, { "name": "Dm", "desc": "Second source 64-bit SIMD/FP register" } ], "extension": "NEON (SIMD)", "description": "Performs signed fixed-point saturating doubling multiply long on NEON vectors, widening narrow elements to double-width results. Each element in Dn is multiplied by the corresponding element in Dm, the result is doubled, saturated to the wider data type range, and written to the corresponding location in Qd. The NEON condition flags are not affected; saturation is indicated via the FPSCR QC bit.", "example": "VQDMULL.dt q0, d1, d2", "pseudocode": "for i = 0 to elements_in_64bit(dt) - 1 do\n product ← (Dn[i] * Dm[i]) * 2\n Qd[i] ← SignedSaturate(product, widen(dt))\nFPSCR.QC ← FPSCR.QC OR (saturation occurred)" }, { "mnemonic": "sxtab", "architecture": "ARMv8-A", "full_name": "Signed Extend and Add Byte", "summary": "Sign-extends a byte from Rm and adds to Rn.", "syntax": "SXTAB , , {, }", "encoding": { "format": "Data Proc", "binary_pattern": "cond | 01101 | 0 | 10 | Rn | Rd | rotate | 0 | 0 | 0111 | Rm", "hex_opcode": "0x06A00070", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01101", "clean": "01101" }, { "raw": "0", "clean": "0" }, { "raw": "10", "clean": "10" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "rotate", "clean": "rotate" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0111", "clean": "0111" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "Accumulator" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Sign-extends the least significant byte of Rm (optionally rotated), adds it to Rn, and writes the result to Rd. This is an A32 instruction that operates on general-purpose registers and does not affect the condition flags. The rotation parameter is optional (ROR by 0, 8, 16, or 24 bits before sign-extension).", "example": "SXTAB r0, r1, r2", "pseudocode": "rotated ← ROR(Rm, rotation)\nbyte_value ← rotated[7:0]\nsign_extended ← SignExtend(byte_value, 32)\nRd ← Rn + sign_extended" }, { "mnemonic": "sxtab16", "architecture": "ARMv8-A", "full_name": "Signed Extend and Add Byte 16", "summary": "Sign-extends two bytes and adds to two halfwords.", "syntax": "SXTAB16 , , {, }", "encoding": { "format": "Data Proc", "binary_pattern": "cond | 01101 | 0 | 00 | Rn | Rd | rotate | 0 | 0 | 0111 | Rm", "hex_opcode": "0x06800070", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01101", "clean": "01101" }, { "raw": "0", "clean": "0" }, { "raw": "00", "clean": "00" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "rotate", "clean": "rotate" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0111", "clean": "0111" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "Accumulator" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Sign-extends the least significant byte and the most significant byte of the low halfword from Rm (optionally rotated), adds them separately to the two halfwords of Rn, and writes the results to Rd. This is an A32 instruction that operates on general-purpose registers and does not affect the condition flags. Useful for parallel byte-to-halfword sign-extension and accumulation.", "example": "SXTAB16 r0, r1, r2", "pseudocode": "rotated ← ROR(Rm, rotation)\nbyte0 ← rotated[7:0]\nbyte1 ← rotated[15:8]\nsign_ext0 ← SignExtend(byte0, 16)\nsign_ext1 ← SignExtend(byte1, 16)\nRd[15:0] ← Rn[15:0] + sign_ext0\nRd[31:16] ← Rn[31:16] + sign_ext1" }, { "mnemonic": "sxtah", "architecture": "ARMv8-A", "full_name": "Signed Extend and Add Halfword", "summary": "Sign-extends a halfword and adds to Rn.", "syntax": "SXTAH , , {, }", "encoding": { "format": "Data Proc", "binary_pattern": "cond | 01101 | 0 | 11 | Rn | Rd | rotate | 0 | 0 | 0111 | Rm", "hex_opcode": "0x06B00070", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01101", "clean": "01101" }, { "raw": "0", "clean": "0" }, { "raw": "11", "clean": "11" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "rotate", "clean": "rotate" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0111", "clean": "0111" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "Accumulator" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Sign-extends the least significant halfword of Rm (optionally rotated), adds it to Rn, and writes the result to Rd. This is an A32 instruction that operates on general-purpose registers and does not affect the condition flags. The rotation parameter is optional (ROR by 0, 8, 16, or 24 bits before sign-extension).", "example": "SXTAH r0, r1, r2", "pseudocode": "rotated ← ROR(Rm, rotation)\nhalfword_value ← rotated[15:0]\nsign_extended ← SignExtend(halfword_value, 32)\nRd ← Rn + sign_extended" }, { "mnemonic": "uxtab", "architecture": "ARMv8-A", "full_name": "Unsigned Extend and Add Byte", "summary": "Zero-extends a byte and adds to Rn.", "syntax": "UXTAB , , {, }", "encoding": { "format": "Data Proc", "binary_pattern": "cond | 01101 | 1 | 10 | Rn | Rd | rotate | 0 | 0 | 0111 | Rm", "hex_opcode": "0x06E00070", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01101", "clean": "01101" }, { "raw": "1", "clean": "1" }, { "raw": "10", "clean": "10" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "rotate", "clean": "rotate" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0111", "clean": "0111" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "Accumulator" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Zero-extends the least significant byte of Rm (optionally rotated), adds it to Rn, and writes the result to Rd. This is an A32 instruction that operates on general-purpose registers and does not affect the condition flags. The rotation parameter is optional (ROR by 0, 8, 16, or 24 bits before zero-extension).", "example": "UXTAB r0, r1, r2", "pseudocode": "rotated ← ROR(Rm, rotation)\nbyte_value ← rotated[7:0]\nzero_extended ← ZeroExtend(byte_value, 32)\nRd ← Rn + zero_extended" }, { "mnemonic": "uxtab16", "architecture": "ARMv8-A", "full_name": "Unsigned Extend and Add Byte 16", "summary": "Zero-extends two bytes and adds to two halfwords.", "syntax": "UXTAB16 , , {, }", "encoding": { "format": "Data Proc", "binary_pattern": "cond | 01101 | 1 | 00 | Rn | Rd | rotate | 0 | 0 | 0111 | Rm", "hex_opcode": "0x06C00070", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01101", "clean": "01101" }, { "raw": "1", "clean": "1" }, { "raw": "00", "clean": "00" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "rotate", "clean": "rotate" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0111", "clean": "0111" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "Accumulator" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Zero-extends the least significant byte and the most significant byte of the low halfword from Rm (optionally rotated), adds them separately to the two halfwords of Rn, and writes the results to Rd. This is an A32 instruction that operates on general-purpose registers and does not affect the condition flags. Useful for parallel byte-to-halfword zero-extension and accumulation.", "example": "UXTAB16 r0, r1, r2", "pseudocode": "rotated ← ROR(Rm, rotation)\nbyte0 ← rotated[7:0]\nbyte1 ← rotated[15:8]\nzero_ext0 ← ZeroExtend(byte0, 16)\nzero_ext1 ← ZeroExtend(byte1, 16)\nRd[15:0] ← Rn[15:0] + zero_ext0\nRd[31:16] ← Rn[31:16] + zero_ext1" }, { "mnemonic": "uxtah", "architecture": "ARMv8-A", "full_name": "Unsigned Extend and Add Halfword", "summary": "Zero-extends a halfword and adds to Rn.", "syntax": "UXTAH , , {, }", "encoding": { "format": "Data Proc", "binary_pattern": "cond | 01101 | 1 | 11 | Rn | Rd | rotate | 0 | 0 | 0111 | Rm", "hex_opcode": "0x06F00070", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01101", "clean": "01101" }, { "raw": "1", "clean": "1" }, { "raw": "11", "clean": "11" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "rotate", "clean": "rotate" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0111", "clean": "0111" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22 | 21:20 | 19:16 | 15:12 | 11:10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "Accumulator" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Zero-extends a halfword (16-bit) from Rm, optionally rotates it by 0, 8, 16, or 24 bits, and adds the result to Rn, storing the sum in Rd. The instruction executes conditionally based on the condition code and does not update the condition flags. This is an A32 DSP extension instruction.", "example": "UXTAH r0, r1, r2", "pseudocode": "rotated ← ROR(Rm, rotation)\nextended ← ZeroExtend(rotated[15:0], 32)\nRd ← Rn + extended" }, { "mnemonic": "smuad", "architecture": "ARMv8-A", "full_name": "Signed Multiply Add Dual", "summary": "Performs two 16x16 multiplies and adds results (Top*Top + Bot*Bot).", "syntax": "SMUAD{X} , , ", "encoding": { "format": "Multiply", "binary_pattern": "cond | 01110 | 000 | Rd | 1111 | Rm | 00 | 0 | 1 | Rn", "hex_opcode": "0x0700F010", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01110", "clean": "01110" }, { "raw": "000", "clean": "000" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1111", "clean": "1111" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "00", "clean": "00" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" } ], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11:8 | 7:6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Multiplies two pairs of signed 16-bit values: (Rn[31:16] × Rm[31:16]) + (Rn[15:0] × Rm[15:0]), storing the 32-bit signed result in Rd. The {X} variant swaps the operands of one multiply. The instruction does not update condition flags. A32 DSP extension only.", "example": "SMUAD r0, r1, r2", "pseudocode": "if X then\n prod1 ← SignExtend(Rn[31:16], 32) × SignExtend(Rm[15:0], 32)\n prod2 ← SignExtend(Rn[15:0], 32) × SignExtend(Rm[31:16], 32)\nelse\n prod1 ← SignExtend(Rn[31:16], 32) × SignExtend(Rm[31:16], 32)\n prod2 ← SignExtend(Rn[15:0], 32) × SignExtend(Rm[15:0], 32)\nRd ← prod1 + prod2" }, { "mnemonic": "smusd", "architecture": "ARMv8-A", "full_name": "Signed Multiply Subtract Dual", "summary": "Performs two 16x16 multiplies and subtracts results.", "syntax": "SMUSD{X} , , ", "encoding": { "format": "Multiply", "binary_pattern": "cond | 01110 | 000 | Rd | 1111 | Rm | 01 | 0 | 1 | Rn", "hex_opcode": "0x0700F050", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01110", "clean": "01110" }, { "raw": "000", "clean": "000" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1111", "clean": "1111" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "01", "clean": "01" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" } ], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11:8 | 7:6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Multiplies two pairs of signed 16-bit values and subtracts: (Rn[31:16] × Rm[31:16]) - (Rn[15:0] × Rm[15:0]), storing the 32-bit signed result in Rd. The {X} variant swaps the operands of one multiply. The instruction does not update condition flags. A32 DSP extension only.", "example": "SMUSD r0, r1, r2", "pseudocode": "if X then\n prod1 ← SignExtend(Rn[31:16], 32) × SignExtend(Rm[15:0], 32)\n prod2 ← SignExtend(Rn[15:0], 32) × SignExtend(Rm[31:16], 32)\nelse\n prod1 ← SignExtend(Rn[31:16], 32) × SignExtend(Rm[31:16], 32)\n prod2 ← SignExtend(Rn[15:0], 32) × SignExtend(Rm[15:0], 32)\nRd ← prod1 - prod2" }, { "mnemonic": "smlad", "architecture": "ARMv8-A", "full_name": "Signed Multiply Accumulate Dual", "summary": "Dual multiply add + accumulate.", "syntax": "SMLAD{X} , , , ", "encoding": { "format": "Multiply", "binary_pattern": "cond | 01110 | 000 | Rd | Ra | Rm | 00 | 0 | 1 | Rn", "hex_opcode": "0x07000010", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01110", "clean": "01110" }, { "raw": "000", "clean": "000" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "Ra", "clean": "Ra" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "00", "clean": "00" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" } ], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11:8 | 7:6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" }, { "name": "Ra", "desc": "Acc" } ], "extension": "A32 (DSP)", "description": "Multiplies two pairs of signed 16-bit values and adds the products, then adds the accumulator Ra: (Rn[31:16] × Rm[31:16]) + (Rn[15:0] × Rm[15:0]) + Ra, storing the 32-bit signed result in Rd. The {X} variant swaps operands of one multiply. Does not update condition flags. A32 DSP extension only.", "example": "SMLAD r0, r1, r2, r5", "pseudocode": "if X then\n prod1 ← SignExtend(Rn[31:16], 32) × SignExtend(Rm[15:0], 32)\n prod2 ← SignExtend(Rn[15:0], 32) × SignExtend(Rm[31:16], 32)\nelse\n prod1 ← SignExtend(Rn[31:16], 32) × SignExtend(Rm[31:16], 32)\n prod2 ← SignExtend(Rn[15:0], 32) × SignExtend(Rm[15:0], 32)\nRd ← prod1 + prod2 + Ra" }, { "mnemonic": "smlsd", "architecture": "ARMv8-A", "full_name": "Signed Multiply Subtract Dual", "summary": "Dual multiply subtract + accumulate.", "syntax": "SMLSD{X} , , , ", "encoding": { "format": "Multiply", "binary_pattern": "cond | 01110 | 000 | Rd | Ra | Rm | 01 | 0 | 1 | Rn", "hex_opcode": "0x07000050", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01110", "clean": "01110" }, { "raw": "000", "clean": "000" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "Ra", "clean": "Ra" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "01", "clean": "01" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" } ], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11:8 | 7:6 | 5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" }, { "name": "Ra", "desc": "Acc" } ], "extension": "A32 (DSP)", "description": "Multiplies two pairs of signed 16-bit values, subtracts the products, then adds accumulator Ra: (Rn[31:16] × Rm[31:16]) - (Rn[15:0] × Rm[15:0]) + Ra, storing the 32-bit signed result in Rd. The {X} variant swaps operands of one multiply. Does not update condition flags. A32 DSP extension only.", "example": "SMLSD r0, r1, r2, r5", "pseudocode": "if X then\n prod1 ← SignExtend(Rn[31:16], 32) × SignExtend(Rm[15:0], 32)\n prod2 ← SignExtend(Rn[15:0], 32) × SignExtend(Rm[31:16], 32)\nelse\n prod1 ← SignExtend(Rn[31:16], 32) × SignExtend(Rm[31:16], 32)\n prod2 ← SignExtend(Rn[15:0], 32) × SignExtend(Rm[15:0], 32)\nRd ← prod1 - prod2 + Ra" }, { "mnemonic": "smlald", "architecture": "ARMv8-A", "full_name": "Signed Multiply Accumulate Long Dual", "summary": "Dual multiply add + 64-bit accumulate.", "syntax": "SMLALD{X} , , , ", "encoding": { "format": "Multiply", "binary_pattern": "cond | 01110 | 100 | RdHi | RdLo | Rm | 00 | 0 | 1 | Rn", "hex_opcode": "0x07400010", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01110", "clean": "01110" }, { "raw": "100", "clean": "100" }, { "raw": "RdHi", "clean": "RdHi" }, { "raw": "RdLo", "clean": "RdLo" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "00", "clean": "00" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" } ], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11:8 | 7:6 | 5 | 4 | 3:0" }, "operands": [ { "name": "RdLo", "desc": "Dest Lo" }, { "name": "RdHi", "desc": "Dest Hi" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Multiplies two pairs of signed 16-bit values and adds the products to a 64-bit accumulator: (Rn[31:16] × Rm[31:16]) + (Rn[15:0] × Rm[15:0]) + (RdHi:RdLo), storing the 64-bit signed result in RdHi:RdLo. The {X} variant swaps operands of one multiply. Does not update condition flags. A32 DSP extension only.", "example": "SMLALD r1, r0, r1, r2", "pseudocode": "if X then\n prod1 ← SignExtend(Rn[31:16], 64) × SignExtend(Rm[15:0], 64)\n prod2 ← SignExtend(Rn[15:0], 64) × SignExtend(Rm[31:16], 64)\nelse\n prod1 ← SignExtend(Rn[31:16], 64) × SignExtend(Rm[31:16], 64)\n prod2 ← SignExtend(Rn[15:0], 64) × SignExtend(Rm[15:0], 64)\naccum ← (RdHi << 32) | RdLo\nresult ← prod1 + prod2 + accum\nRdHi ← result[63:32]\nRdLo ← result[31:0]" }, { "mnemonic": "smlsld", "architecture": "ARMv8-A", "full_name": "Signed Multiply Subtract Long Dual", "summary": "Dual multiply subtract + 64-bit accumulate.", "syntax": "SMLSLD{X} , , , ", "encoding": { "format": "Multiply", "binary_pattern": "cond | 01110 | 100 | RdHi | RdLo | Rm | 01 | 0 | 1 | Rn", "hex_opcode": "0x07400050", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01110", "clean": "01110" }, { "raw": "100", "clean": "100" }, { "raw": "RdHi", "clean": "RdHi" }, { "raw": "RdLo", "clean": "RdLo" }, { "raw": "Rm", "clean": "Rm" }, { "raw": "01", "clean": "01" }, { "raw": "0", "clean": "0" }, { "raw": "1", "clean": "1" }, { "raw": "Rn", "clean": "Rn" } ], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11:8 | 7:6 | 5 | 4 | 3:0" }, "operands": [ { "name": "RdLo", "desc": "Dest Lo" }, { "name": "RdHi", "desc": "Dest Hi" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Multiplies two pairs of signed 16-bit values, subtracts the products, and adds to a 64-bit accumulator: (Rn[31:16] × Rm[31:16]) - (Rn[15:0] × Rm[15:0]) + (RdHi:RdLo), storing the 64-bit signed result in RdHi:RdLo. The {X} variant swaps operands of one multiply. Does not update condition flags. A32 DSP extension only.", "example": "SMLSLD r1, r0, r1, r2", "pseudocode": "if X then\n prod1 ← SignExtend(Rn[31:16], 64) × SignExtend(Rm[15:0], 64)\n prod2 ← SignExtend(Rn[15:0], 64) × SignExtend(Rm[31:16], 64)\nelse\n prod1 ← SignExtend(Rn[31:16], 64) × SignExtend(Rm[31:16], 64)\n prod2 ← SignExtend(Rn[15:0], 64) × SignExtend(Rm[15:0], 64)\naccum ← (RdHi << 32) | RdLo\nresult ← prod1 - prod2 + accum\nRdHi ← result[63:32]\nRdLo ← result[31:0]" }, { "mnemonic": "qadd8", "architecture": "ARMv8-A", "full_name": "Saturating Add 8", "summary": "Parallel saturating add of 4 signed bytes.", "syntax": "QADD8 , , ", "encoding": { "format": "SIMD Integer", "binary_pattern": "cond | 01100 | 010 | Rn | Rd | 1 | 1 | 1 | 1 | 1 | 00 | 1 | Rm", "hex_opcode": "0x06200F90", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01100", "clean": "01100" }, { "raw": "010", "clean": "010" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Performs four parallel saturating additions on signed bytes: each byte of Rn is added to the corresponding byte of Rm with signed saturation, and the four 8-bit saturated results are packed into Rd. The GE[3:0] condition flags are updated to indicate which byte operations did not saturate. A32 DSP extension only.", "example": "QADD8 r0, r1, r2", "pseudocode": "for i = 0 to 3\n byte_index ← i × 8\n a ← SignExtend(Rn[byte_index + 7 : byte_index], 9)\n b ← SignExtend(Rm[byte_index + 7 : byte_index], 9)\n sum ← a + b\n if sum > 127 then\n result_byte ← 127\n GE[i] ← 0\n elsif sum < -128 then\n result_byte ← -128\n GE[i] ← 0\n else\n result_byte ← sum[7:0]\n GE[i] ← 1\n Rd[byte_index + 7 : byte_index] ← result_byte" }, { "mnemonic": "qadd16", "architecture": "ARMv8-A", "full_name": "Saturating Add 16", "summary": "Parallel saturating add of 2 signed halfwords.", "syntax": "QADD16 , , ", "encoding": { "format": "SIMD Integer", "binary_pattern": "cond | 01100 | 010 | Rn | Rd | 1 | 1 | 1 | 1 | 0 | 00 | 1 | Rm", "hex_opcode": "0x06200F10", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01100", "clean": "01100" }, { "raw": "010", "clean": "010" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Performs parallel saturating addition of two signed 16-bit halfwords in Rn and Rm, storing results in Rd. Each halfword is independently saturated to the signed 16-bit range [-32768, 32767] if overflow occurs. No condition flags are affected. Execution restricted to A32 with DSP extension; requires ARMv6 or later.", "example": "QADD16 r0, r1, r2", "pseudocode": "Rd[31:16] ← SignedSat(Rn[31:16] + Rm[31:16], 16)\nRd[15:0] ← SignedSat(Rn[15:0] + Rm[15:0], 16)" }, { "mnemonic": "qsub8", "architecture": "ARMv8-A", "full_name": "Saturating Subtract 8", "summary": "Parallel saturating subtract of 4 signed bytes.", "syntax": "QSUB8 , , ", "encoding": { "format": "SIMD Integer", "binary_pattern": "cond | 01100 | 010 | Rn | Rd | 1 | 1 | 1 | 1 | 1 | 11 | 1 | Rm", "hex_opcode": "0x06200FF0", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01100", "clean": "01100" }, { "raw": "010", "clean": "010" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "11", "clean": "11" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Performs parallel saturating subtraction of four signed 8-bit bytes in Rm from Rn, storing results in Rd. Each byte is independently saturated to the signed 8-bit range [-128, 127] if underflow occurs. No condition flags are affected. Execution restricted to A32 with DSP extension; requires ARMv6 or later.", "example": "QSUB8 r0, r1, r2", "pseudocode": "Rd[31:24] ← SignedSat(Rn[31:24] - Rm[31:24], 8)\nRd[23:16] ← SignedSat(Rn[23:16] - Rm[23:16], 8)\nRd[15:8] ← SignedSat(Rn[15:8] - Rm[15:8], 8)\nRd[7:0] ← SignedSat(Rn[7:0] - Rm[7:0], 8)" }, { "mnemonic": "qsub16", "architecture": "ARMv8-A", "full_name": "Saturating Subtract 16", "summary": "Parallel saturating subtract of 2 signed halfwords.", "syntax": "QSUB16 , , ", "encoding": { "format": "SIMD Integer", "binary_pattern": "cond | 01100 | 010 | Rn | Rd | 1 | 1 | 1 | 1 | 0 | 11 | 1 | Rm", "hex_opcode": "0x06200F70", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01100", "clean": "01100" }, { "raw": "010", "clean": "010" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "11", "clean": "11" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Performs parallel saturating subtraction of two signed 16-bit halfwords in Rm from Rn, storing results in Rd. Each halfword is independently saturated to the signed 16-bit range [-32768, 32767] if underflow occurs. No condition flags are affected. Execution restricted to A32 with DSP extension; requires ARMv6 or later.", "example": "QSUB16 r0, r1, r2", "pseudocode": "Rd[31:16] ← SignedSat(Rn[31:16] - Rm[31:16], 16)\nRd[15:0] ← SignedSat(Rn[15:0] - Rm[15:0], 16)" }, { "mnemonic": "shadd8", "architecture": "ARMv8-A", "full_name": "Signed Halving Add 8", "summary": "Signed add and halving (average) of 4 bytes.", "syntax": "SHADD8 , , ", "encoding": { "format": "SIMD Integer", "binary_pattern": "cond | 01100 | 011 | Rn | Rd | 1 | 1 | 1 | 1 | 1 | 00 | 1 | Rm", "hex_opcode": "0x06300F90", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01100", "clean": "01100" }, { "raw": "011", "clean": "011" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Performs parallel addition of four signed 8-bit bytes from Rn and Rm, then arithmetically shifts each result right by 1 bit (halving), storing in Rd. No saturation occurs; results are always in the range [-128, 127]. No condition flags are affected. Execution restricted to A32 with DSP extension; requires ARMv6 or later.", "example": "SHADD8 r0, r1, r2", "pseudocode": "Rd[31:24] ← (SignExtend(Rn[31:24]) + SignExtend(Rm[31:24])) >> 1\nRd[23:16] ← (SignExtend(Rn[23:16]) + SignExtend(Rm[23:16])) >> 1\nRd[15:8] ← (SignExtend(Rn[15:8]) + SignExtend(Rm[15:8])) >> 1\nRd[7:0] ← (SignExtend(Rn[7:0]) + SignExtend(Rm[7:0])) >> 1" }, { "mnemonic": "shadd16", "architecture": "ARMv8-A", "full_name": "Signed Halving Add 16", "summary": "Signed add and halving (average) of 2 halfwords.", "syntax": "SHADD16 , , ", "encoding": { "format": "SIMD Integer", "binary_pattern": "cond | 01100 | 011 | Rn | Rd | 1 | 1 | 1 | 1 | 0 | 00 | 1 | Rm", "hex_opcode": "0x06300F10", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01100", "clean": "01100" }, { "raw": "011", "clean": "011" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Performs parallel addition of two signed 16-bit halfwords from Rn and Rm, then arithmetically shifts each result right by 1 bit (halving), storing in Rd. No saturation occurs; results are always in the range [-32768, 32767]. No condition flags are affected. Execution restricted to A32 with DSP extension; requires ARMv6 or later.", "example": "SHADD16 r0, r1, r2", "pseudocode": "Rd[31:16] ← (SignExtend(Rn[31:16]) + SignExtend(Rm[31:16])) >> 1\nRd[15:0] ← (SignExtend(Rn[15:0]) + SignExtend(Rm[15:0])) >> 1" }, { "mnemonic": "shsub8", "architecture": "ARMv8-A", "full_name": "Signed Halving Subtract 8", "summary": "Signed subtract and halving of 4 bytes.", "syntax": "SHSUB8 , , ", "encoding": { "format": "SIMD Integer", "binary_pattern": "cond | 01100 | 011 | Rn | Rd | 1 | 1 | 1 | 1 | 1 | 11 | 1 | Rm", "hex_opcode": "0x06300FF0", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01100", "clean": "01100" }, { "raw": "011", "clean": "011" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "11", "clean": "11" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Performs parallel subtraction of four signed 8-bit bytes in Rm from Rn, then arithmetically shifts each result right by 1 bit (halving), storing in Rd. No saturation occurs; results are always in the range [-128, 127]. No condition flags are affected. Execution restricted to A32 with DSP extension; requires ARMv6 or later.", "example": "SHSUB8 r0, r1, r2", "pseudocode": "Rd[31:24] ← (SignExtend(Rn[31:24]) - SignExtend(Rm[31:24])) >> 1\nRd[23:16] ← (SignExtend(Rn[23:16]) - SignExtend(Rm[23:16])) >> 1\nRd[15:8] ← (SignExtend(Rn[15:8]) - SignExtend(Rm[15:8])) >> 1\nRd[7:0] ← (SignExtend(Rn[7:0]) - SignExtend(Rm[7:0])) >> 1" }, { "mnemonic": "shsub16", "architecture": "ARMv8-A", "full_name": "Signed Halving Subtract 16", "summary": "Signed subtract and halving of 2 halfwords.", "syntax": "SHSUB16 , , ", "encoding": { "format": "SIMD Integer", "binary_pattern": "cond | 01100 | 011 | Rn | Rd | 1 | 1 | 1 | 1 | 0 | 11 | 1 | Rm", "hex_opcode": "0x06300F70", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01100", "clean": "01100" }, { "raw": "011", "clean": "011" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "11", "clean": "11" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Performs parallel subtraction of two signed 16-bit halfwords in Rm from Rn, then arithmetically shifts each result right by 1 bit (halving), storing in Rd. No saturation occurs; results are always in the range [-32768, 32767]. No condition flags are affected. Execution restricted to A32 with DSP extension; requires ARMv6 or later.", "example": "SHSUB16 r0, r1, r2", "pseudocode": "Rd[31:16] ← (SignExtend(Rn[31:16]) - SignExtend(Rm[31:16])) >> 1\nRd[15:0] ← (SignExtend(Rn[15:0]) - SignExtend(Rm[15:0])) >> 1" }, { "mnemonic": "uqadd8", "architecture": "ARMv8-A", "full_name": "Unsigned Saturating Add 8", "summary": "Unsigned saturating add of 4 bytes.", "syntax": "UQADD8 , , ", "encoding": { "format": "SIMD Integer", "binary_pattern": "cond | 01100 | 110 | Rn | Rd | 1 | 1 | 1 | 1 | 1 | 00 | 1 | Rm", "hex_opcode": "0x06600F90", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01100", "clean": "01100" }, { "raw": "110", "clean": "110" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Performs parallel saturating addition of four unsigned 8-bit bytes from Rn and Rm, storing results in Rd. Each byte is independently saturated to the unsigned 8-bit range [0, 255] if overflow occurs. No condition flags are affected. Execution restricted to A32 with DSP extension; requires ARMv6 or later.", "example": "UQADD8 r0, r1, r2", "pseudocode": "Rd[31:24] ← UnsignedSat(Rn[31:24] + Rm[31:24], 8)\nRd[23:16] ← UnsignedSat(Rn[23:16] + Rm[23:16], 8)\nRd[15:8] ← UnsignedSat(Rn[15:8] + Rm[15:8], 8)\nRd[7:0] ← UnsignedSat(Rn[7:0] + Rm[7:0], 8)" }, { "mnemonic": "uqadd16", "architecture": "ARMv8-A", "full_name": "Unsigned Saturating Add 16", "summary": "Unsigned saturating add of 2 halfwords.", "syntax": "UQADD16 , , ", "encoding": { "format": "SIMD Integer", "binary_pattern": "cond | 01100 | 110 | Rn | Rd | 1 | 1 | 1 | 1 | 0 | 00 | 1 | Rm", "hex_opcode": "0x06600F10", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01100", "clean": "01100" }, { "raw": "110", "clean": "110" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Performs unsigned saturating addition of two 16-bit halfwords in parallel. Each halfword of Rn is added to the corresponding halfword of Rm; if the result exceeds the unsigned 16-bit range (0-65535), it saturates to 65535. No condition flags are affected; saturation status is not recorded.", "example": "UQADD16 r0, r1, r2", "pseudocode": "half1_rn ← Rn[15:0]; half2_rn ← Rn[31:16]\nhalf1_rm ← Rm[15:0]; half2_rm ← Rm[31:16]\nsum1 ← half1_rn + half1_rm; sum2 ← half2_rn + half2_rm\nRd[15:0] ← (sum1 > 0xFFFF) ? 0xFFFF : sum1\nRd[31:16] ← (sum2 > 0xFFFF) ? 0xFFFF : sum2" }, { "mnemonic": "uqsub8", "architecture": "ARMv8-A", "full_name": "Unsigned Saturating Subtract 8", "summary": "Unsigned saturating subtract of 4 bytes.", "syntax": "UQSUB8 , , ", "encoding": { "format": "SIMD Integer", "binary_pattern": "cond | 01100 | 110 | Rn | Rd | 1 | 1 | 1 | 1 | 1 | 11 | 1 | Rm", "hex_opcode": "0x06600FF0", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01100", "clean": "01100" }, { "raw": "110", "clean": "110" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "11", "clean": "11" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Performs unsigned saturating subtraction of four 8-bit bytes in parallel. Each byte of Rm is subtracted from the corresponding byte of Rn; if the result would be negative, it saturates to 0. No condition flags are affected; saturation status is not recorded.", "example": "UQSUB8 r0, r1, r2", "pseudocode": "for i = 0 to 3 do\n byte_rn ← Rn[8*i+7:8*i]; byte_rm ← Rm[8*i+7:8*i]\n diff ← byte_rn - byte_rm\n Rd[8*i+7:8*i] ← (diff < 0) ? 0 : diff" }, { "mnemonic": "uqsub16", "architecture": "ARMv8-A", "full_name": "Unsigned Saturating Subtract 16", "summary": "Unsigned saturating subtract of 2 halfwords.", "syntax": "UQSUB16 , , ", "encoding": { "format": "SIMD Integer", "binary_pattern": "cond | 01100 | 110 | Rn | Rd | 1 | 1 | 1 | 1 | 0 | 11 | 1 | Rm", "hex_opcode": "0x06600F70", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01100", "clean": "01100" }, { "raw": "110", "clean": "110" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "11", "clean": "11" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Performs unsigned saturating subtraction of two 16-bit halfwords in parallel. Each halfword of Rm is subtracted from the corresponding halfword of Rn; if the result would be negative, it saturates to 0. No condition flags are affected; saturation status is not recorded.", "example": "UQSUB16 r0, r1, r2", "pseudocode": "half1_rn ← Rn[15:0]; half2_rn ← Rn[31:16]\nhalf1_rm ← Rm[15:0]; half2_rm ← Rm[31:16]\ndiff1 ← half1_rn - half1_rm; diff2 ← half2_rn - half2_rm\nRd[15:0] ← (diff1 < 0) ? 0 : diff1\nRd[31:16] ← (diff2 < 0) ? 0 : diff2" }, { "mnemonic": "uhadd8", "architecture": "ARMv8-A", "full_name": "Unsigned Halving Add 8", "summary": "Unsigned average of 4 bytes.", "syntax": "UHADD8 , , ", "encoding": { "format": "SIMD Integer", "binary_pattern": "cond | 01100 | 111 | Rn | Rd | 1 | 1 | 1 | 1 | 1 | 00 | 1 | Rm", "hex_opcode": "0x06700F90", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01100", "clean": "01100" }, { "raw": "111", "clean": "111" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Performs unsigned halving addition of four 8-bit bytes in parallel, effectively computing the average. Each byte of Rn is added to the corresponding byte of Rm and the result is divided by 2 (rounded down). No condition flags are affected.", "example": "UHADD8 r0, r1, r2", "pseudocode": "for i = 0 to 3 do\n byte_rn ← Rn[8*i+7:8*i]; byte_rm ← Rm[8*i+7:8*i]\n sum ← byte_rn + byte_rm\n Rd[8*i+7:8*i] ← sum >> 1" }, { "mnemonic": "uhadd16", "architecture": "ARMv8-A", "full_name": "Unsigned Halving Add 16", "summary": "Unsigned average of 2 halfwords.", "syntax": "UHADD16 , , ", "encoding": { "format": "SIMD Integer", "binary_pattern": "cond | 01100 | 111 | Rn | Rd | 1 | 1 | 1 | 1 | 0 | 00 | 1 | Rm", "hex_opcode": "0x06700F10", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01100", "clean": "01100" }, { "raw": "111", "clean": "111" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "00", "clean": "00" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Performs unsigned halving addition of two 16-bit halfwords in parallel, computing the average of each pair. Each halfword of Rn is added to the corresponding halfword of Rm and the result is divided by 2 (rounded down). No condition flags are affected.", "example": "UHADD16 r0, r1, r2", "pseudocode": "half1_rn ← Rn[15:0]; half2_rn ← Rn[31:16]\nhalf1_rm ← Rm[15:0]; half2_rm ← Rm[31:16]\nsum1 ← half1_rn + half1_rm; sum2 ← half2_rn + half2_rm\nRd[15:0] ← sum1 >> 1\nRd[31:16] ← sum2 >> 1" }, { "mnemonic": "uhsub8", "architecture": "ARMv8-A", "full_name": "Unsigned Halving Subtract 8", "summary": "Unsigned halving subtract of 4 bytes.", "syntax": "UHSUB8 , , ", "encoding": { "format": "SIMD Integer", "binary_pattern": "cond | 01100 | 111 | Rn | Rd | 1 | 1 | 1 | 1 | 1 | 11 | 1 | Rm", "hex_opcode": "0x06700FF0", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01100", "clean": "01100" }, { "raw": "111", "clean": "111" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "11", "clean": "11" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Performs unsigned halving subtraction of four 8-bit bytes in parallel. Each byte of Rm is subtracted from the corresponding byte of Rn and the result is divided by 2 (rounded down). No condition flags are affected.", "example": "UHSUB8 r0, r1, r2", "pseudocode": "for i = 0 to 3 do\n byte_rn ← Rn[8*i+7:8*i]; byte_rm ← Rm[8*i+7:8*i]\n diff ← byte_rn - byte_rm\n Rd[8*i+7:8*i] ← diff >> 1" }, { "mnemonic": "uhsub16", "architecture": "ARMv8-A", "full_name": "Unsigned Halving Subtract 16", "summary": "Unsigned halving subtract of 2 halfwords.", "syntax": "UHSUB16 , , ", "encoding": { "format": "SIMD Integer", "binary_pattern": "cond | 01100 | 111 | Rn | Rd | 1 | 1 | 1 | 1 | 0 | 11 | 1 | Rm", "hex_opcode": "0x06700F70", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01100", "clean": "01100" }, { "raw": "111", "clean": "111" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "11", "clean": "11" }, { "raw": "1", "clean": "1" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:23 | 22:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7 | 6:5 | 4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Performs unsigned halving subtraction of two 16-bit halfwords in parallel. Each halfword of Rm is subtracted from the corresponding halfword of Rn and the result is divided by 2 (rounded down). No condition flags are affected.", "example": "UHSUB16 r0, r1, r2", "pseudocode": "half1_rn ← Rn[15:0]; half2_rn ← Rn[31:16]\nhalf1_rm ← Rm[15:0]; half2_rm ← Rm[31:16]\ndiff1 ← half1_rn - half1_rm; diff2 ← half2_rn - half2_rm\nRd[15:0] ← diff1 >> 1\nRd[31:16] ← diff2 >> 1" }, { "mnemonic": "sel", "architecture": "ARMv8-A", "full_name": "Select Bytes", "summary": "Selects bytes from Rn or Rm based on GE flags.", "syntax": "SEL , , ", "encoding": { "format": "Data Proc", "binary_pattern": "cond | 01101000 | Rn | Rd | 1 | 1 | 1 | 1 | 1011 | Rm", "hex_opcode": "0x06800FB0", "visual_parts": [ { "raw": "cond", "clean": "cond" }, { "raw": "01101000", "clean": "01101000" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rd", "clean": "Rd" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1", "clean": "1" }, { "raw": "1011", "clean": "1011" }, { "raw": "Rm", "clean": "Rm" } ], "bit_positions": "31:28 | 27:20 | 19:16 | 15:12 | 11 | 10 | 9 | 8 | 7:4 | 3:0" }, "operands": [ { "name": "Rd", "desc": "Destination general-purpose register" }, { "name": "Rn", "desc": "First source / base general-purpose register" }, { "name": "Rm", "desc": "Second source / offset general-purpose register" } ], "extension": "A32 (DSP)", "description": "Selects bytes from Rn or Rm based on the GE (Greater-than-or-Equal) condition flags, placing the selected bytes into Rd. For each byte position i, if GE[i] is set, the byte from Rn[8*i+7:8*i] is selected; otherwise, the byte from Rm[8*i+7:8*i] is selected. Condition flags are not affected by this instruction.", "example": "SEL r0, r1, r2", "pseudocode": "for i = 0 to 3 do\n if GE[i] == 1 then\n Rd[8*i+7:8*i] ← Rn[8*i+7:8*i]\n else\n Rd[8*i+7:8*i] ← Rm[8*i+7:8*i]" }, { "mnemonic": "prfm", "architecture": "ARMv8-A", "full_name": "Prefetch Memory (Immediate)", "summary": "Signals the memory system to prefetch data into cache.", "syntax": "PRFM , [, #]", "encoding": { "format": "Load/Store Imm", "binary_pattern": "11 | 111 | 0 | 01 | 10 | imm12 | Rn | Rt", "hex_opcode": "0xF9800000", "visual_parts": [ { "raw": "11", "clean": "11" }, { "raw": "111", "clean": "111" }, { "raw": "0", "clean": "0" }, { "raw": "01", "clean": "01" }, { "raw": "10", "clean": "10" }, { "raw": "imm12", "clean": "imm12" }, { "raw": "Rn", "clean": "Rn" }, { "raw": "Rt", "clean": "Rt" } ], "bit_positions": "31:30 | 29:27 | 26 | 25:24 | 23:22 | 21:10 | 9:5 | 4:0" }, "operands": [ { "name": "prfop", "desc": "Type (PLDL1KEEP, etc)" }, { "name": "Xn", "desc": "Base Addr" }, { "name": "pimm", "desc": "Positive immediate offset" } ], "extension": "Base", "description": "Prefetch Memory (Immediate) signals the memory system to prefetch data from an address calculated by adding a scaled 12-bit immediate offset to a base register. This is a hint instruction that does not architecturally affect register state or condition flags. Execution is AArch64-only and no exceptions are generated for invalid addresses.", "example": "PRFM prfop, [x1, #16]", "pseudocode": "address ← Xn|SP + (imm12 << 3); Prefetch(address, prfop);" }, { "mnemonic": "prfm", "architecture": "ARMv8-A", "full_name": "Prefetch Memory (Literal)", "summary": "Prefetches data from a PC-relative address.", "syntax": "PRFM ,