# InstructionSets instruction dataset

5,986 CPU and GPU instruction records across six architectures, released
into the public domain under CC0 1.0. Use it for anything, no permission and no
attribution required.

| Architecture | Records |
|---|---|
| x86 | 957 |
| ARM | 1,145 |
| PowerISA | 1,187 |
| RISC-V | 547 |
| PTX | 190 |
| AMDGPU | 1,960 |

## Files

- `instructions.jsonl` - every record, one JSON object per line
- `<arch>.json` - the same records split per architecture
- `manifest.json` - counts, excluded fields and SHA-256 checksums
- `LICENSE` - the CC0 dedication and what it does not cover

## Fields

Each record carries `mnemonic`, `architecture`, `summary`, `description`,
`syntax`, `operands`, `encoding` (format, bit pattern, hex opcode),
`pseudocode`, `extension` and, where known, an example.

## Provenance and accuracy

Extracted from vendor specifications by a language model, then repaired over
many passes. That makes measurement mandatory rather than optional, so
`ACCURACY.md`, included in this download, reports corroboration against the
vendor specifications themselves: mnemonics at 94-98% across the four
architectures
that can be checked, with RISC-V encodings at 406/406 after 18 defects were
found and fixed. Roughly a third of the corpus (PTX and AMDGPU) is not yet
audited, and semantic correctness of prose and pseudocode is not measured at
all. Treat the figures as a lower bound and the unaudited part as unverified.

8.37 MB of verbatim vendor manual text was removed before
release, because it was not ours to publish. Every record keeps its own
summary, description, pseudocode, operands and encoding.

- `ACCURACY.md` - how accuracy was measured, and what was not measured

Home, and every record as a browsable page: https://instructionsets.com