{ "architecture": "PowerISA", "instructions": [ { "mnemonic": "xvi4ger8", "architecture": "PowerISA", "full_name": "VSX Vector Integer 4-bit GER (Rank-8 Update)", "summary": "Performs an accumulation of eight outer products (rank 8 update) using signed 4-bit integers from two vector scalar registers.", "syntax": "xvi4ger8 AT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "60 | AT | XA | XB | 34", "hex_opcode": "0xEC000118", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "AT", "clean": "AT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "34", "clean": "34" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "AT", "desc": "Accumulator" }, { "name": "XA", "desc": "Src A (4-bit)" }, { "name": "XB", "desc": "Src B (4-bit)" } ], "extension": "MMA", "description": "The instruction multiplies corresponding elements of the matrices X and Y, accumulates the results, and stores them in the accumulator ACC[AT]. The result is chopped to a 32-bit signed integer.", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\n\nPMSK ←0b11111111\nXMSK ←0b1111\nYMSK ←0b1111\n\ndo i = 0 to 3\ndo j = 0 to 3\n if XMSK.bit[i] & YMSK.bit[j] then do\n prod0 ←(PMSK.bit[0]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].nibble[0]) * EXTS(VSR[32×BX+B].word[j].nibble[0])\n prod1 ←(PMSK.bit[1]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].nibble[1]) * EXTS(VSR[32×BX+B].word[j].nibble[1])\n prod2 ←(PMSK.bit[2]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].nibble[2]) * EXTS(VSR[32×BX+B].word[j].nibble[2])\n prod3 ←(PMSK.bit[3]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].nibble[3]) * EXTS(VSR[32×BX+B].word[j].nibble[3])\n prod4 ←(PMSK.bit[4]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].nibble[4]) * EXTS(VSR[32×BX+B].word[j].nibble[4])\n prod5 ←(PMSK.bit[5]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].nibble[5]) * EXTS(VSR[32×BX+B].word[j].nibble[5])\n prod6 ←(PMSK.bit[6]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].nibble[6]) * EXTS(VSR[32×BX+B].word[j].nibble[6])\n prod7 ←(PMSK.bit[7]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].nibble[7]) * EXTS(VSR[32×BX+B].word[j].nibble[7])\n\n psum ←prod0 + prod1 + prod2 + prod3 + prod4 + prod5 + prod6 + prod7\n\n ACC[AT][i].word[j] ←CHOP32( psum )\n end\n else\n ACC[AT][i].word[j] ←0x0000_0000\nend\nend", "page_found": "Page 917 - 918", "programming_notes": "Let X be the 8×4 matrix of 4-bit signed integer values contained in VSR[XA] in row-major format.\nLet Y be the 8×4 matrix of 4-bit signed integer values contained in VSR[XB] in row-major format.\nLet ACC[AT] be the Accumulator containing a 4×4 matrix of 32-bit signed-integer values.", "special_registers": "MSR", "example": "xvi4ger8 acc0, vs2, vs3" }, { "mnemonic": "xvi4ger8pp", "architecture": "PowerISA", "full_name": "VSX Vector Integer 4-bit GER (Rank-8 Update) Plus/Plus", "summary": "Unsigned 4-bit integer matrix multiply accumulate.", "syntax": "xvi4ger8pp AT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "60 | AT | XA | XB | 35", "hex_opcode": "0xEC000110", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "AT", "clean": "AT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "35", "clean": "35" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "AT", "desc": "Accumulator" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "MMA", "description": "Performs an unsigned 4-bit integer matrix multiplication with rank-8 accumulation, accumulating the result with plus-signed saturation. This MMA instruction multiplies 4-bit elements from two VSX registers and adds the partial products to an MMA accumulator, treating both input and output as unsigned values. The plus/plus variant saturates on overflow using unsigned saturation semantics.", "pseudocode": "AT ← ACC[AT] + (XA × XB)", "page_found": "Page 918", "special_registers": "FPSCR, XER", "programming_notes": "This instruction is commonly used for matrix multiplication and accumulation operations on VSX registers with saturation handling. Ensure that the input matrices are correctly aligned and masked as per requirements. The instruction operates at a privilege level that allows access to FPSCR and XER, and it may raise exceptions if there are issues with operand alignment or access rights. Performance can be optimized by ensuring that the masks (XMSK and YMSK) are efficiently set to minimize unnecessary computations.", "example": "xvi4ger8pp acc0, vs2, vs3" }, { "mnemonic": "pmxvi4ger8", "architecture": "PowerISA", "full_name": "Prefixed Masked VSX Vector Integer 4-bit GER", "summary": "Masked 4-bit integer matrix multiply.", "syntax": "pmxvi4ger8 AT, XA, XB, XMSK, YMSK", "encoding": { "format": "MMIRR-form", "binary_pattern": "1 | 3 | PMSK | XMSK | YMSK | 0 | 59 | AT | / | XA | XB | 3 | AX | BX | /", "hex_opcode": "0x07900000EC000118", "visual_parts": [ { "raw": "000001", "clean": "000001" }, { "raw": "11", "clean": "11" }, { "raw": "...", "clean": "..." } ], "length": "64", "bit_positions": "0 | 6 | 8 | 9 | 14 | 32 | 38 | 41 | 43 | 48 | 53 | 56 | 57 | 58 | " }, "operands": [ { "name": "AT", "desc": "Accumulator" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" }, { "name": "XMSK", "desc": "Mask A" }, { "name": "YMSK", "desc": "Mask B" } ], "extension": "Prefixed", "description": "Performs a masked unsigned 4-bit integer matrix multiplication with rank-8 accumulation using separate row and column masks. This prefixed MMA instruction multiplies 4-bit elements from two VSX registers and adds the partial products to an MMA accumulator, with XMSK controlling which rows and YMSK controlling which columns participate. The result is treated as unsigned.", "pseudocode": "AT ← ACC[AT] + ((XA & XMSK) × (XB & YMSK))", "page_found": "Page 918", "programming_notes": "The pmxvi4ger8 instruction is useful for performing masked vector integer operations, multiplying and accumulating products of signed integers from two vectors based on a mask. Ensure that the mask registers (XMSK, YMSK) are correctly set to control which elements are processed. The operation requires proper alignment of VSX registers, and results are clamped to 32-bit signed integers to prevent overflow. This instruction operates at privilege level 0.", "example": "pmxvi4ger8 acc0, vs2, vs3, 15, 15" }, { "mnemonic": "pmxvi4ger8pp", "architecture": "PowerISA", "full_name": "Prefixed Masked VSX Vector Integer 4-bit GER Plus/Plus", "summary": "Masked unsigned 4-bit integer matrix multiply.", "syntax": "pmxvi4ger8pp AT, XA, XB, XMSK, YMSK", "encoding": { "format": "MMIRR-form", "binary_pattern": "1 | 3 | PMSK | XMSK | YMSK | 0 | 59 | AT | / | XA | XB | 3 | AX | BX | /", "hex_opcode": "0x07900000EC000110", "visual_parts": [ { "raw": "000001", "clean": "000001" }, { "raw": "11", "clean": "11" }, { "raw": "...", "clean": "..." } ], "length": "64", "bit_positions": "0 | 6 | 8 | 9 | 14 | 32 | 38 | 41 | 43 | 48 | 53 | 56 | 57 | 58 | " }, "operands": [ { "name": "AT", "desc": "Accumulator" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" }, { "name": "XMSK", "desc": "Mask A" }, { "name": "YMSK", "desc": "Mask B" } ], "extension": "Prefixed", "description": "Performs a masked unsigned 4-bit integer matrix multiplication with rank-8 accumulation and plus-signed saturation using separate row and column masks. This prefixed MMA instruction multiplies masked 4-bit elements from two VSX registers and accumulates the partial products into an MMA accumulator with unsigned saturation on overflow. XMSK controls row participation and YMSK controls column participation.", "pseudocode": "AT ← ACC[AT] + sat_u((XA & XMSK) × (XB & YMSK))", "page_found": "Page 918", "special_registers": "FPSCR", "programming_notes": "This instruction is useful for performing masked vectorized integer operations with saturation, ideal for applications requiring precise control over overflow conditions. Ensure that the mask registers (XMSK and YMSK) are correctly set to avoid unintended computations. The operation is performed at the user privilege level, but care must be taken to handle potential exceptions related to invalid register access or alignment issues. Performance may vary based on the specific data patterns and the effectiveness of the masking applied.", "example": "pmxvi4ger8pp acc0, vs2, vs3, 15, 15" }, { "mnemonic": "dst", "architecture": "PowerISA", "full_name": "Data Stream Touch", "summary": "Initiates a hardware data stream prefetch (AltiVec Legacy).", "syntax": "dst RA, RB, STRM", "encoding": { "format": "X-form", "binary_pattern": "31 | STRM | RA | RB | 342 | /", "hex_opcode": "0x7C0002AC", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "STRM", "clean": "STRM" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "342", "clean": "342" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" }, { "name": "STRM", "desc": "Stream ID" } ], "extension": "Base", "description": "Initiates a hardware prefetch stream for data that is likely to be loaded in the near future. The instruction computes an effective address from RA and RB and hints to the memory subsystem to begin streaming data into the cache with the temporal locality specified by STRM. This is an advisory instruction with no architectural side effects if the hardware does not support data streaming.", "pseudocode": "EA ← (RA | 0) + RB; InitiateDataStream(EA, STRM, isStore=0, isTransient=0)", "example": "dst r4, r5, 0" }, { "mnemonic": "dstt", "architecture": "PowerISA", "full_name": "Data Stream Touch Transient", "summary": "Initiates a transient (non-temporal) data stream prefetch.", "syntax": "dstt RA, RB, STRM", "encoding": { "format": "X-form", "binary_pattern": "31 | STRM | RA | RB | 342 | /", "hex_opcode": "0x7C0002AC", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "STRM", "clean": "STRM" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "342", "clean": "342" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" }, { "name": "STRM", "desc": "Stream ID" } ], "extension": "Base", "description": "Initiates a hardware prefetch stream for transient (non-temporal) data that is likely to be loaded in the near future and not reused. The instruction computes an effective address from RA and RB and hints to the memory subsystem to begin streaming data with transient semantics specified by STRM. This is an advisory instruction that may reduce cache pollution for one-time accesses.", "pseudocode": "EA ← (RA | 0) + RB; InitiateDataStream(EA, STRM, isStore=0, isTransient=1)", "example": "dstt r4, r5, 0" }, { "mnemonic": "dstst", "architecture": "PowerISA", "full_name": "Data Stream Touch for Store", "summary": "Initiates a prefetch for writing.", "syntax": "dstst RA, RB, STRM", "encoding": { "format": "X-form", "binary_pattern": "31 | STRM | RA | RB | 374 | /", "hex_opcode": "0x7C0002EC", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "STRM", "clean": "STRM" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "374", "clean": "374" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" }, { "name": "STRM", "desc": "Stream ID" } ], "extension": "Base", "description": "Initiates a hardware prefetch stream for data that is likely to be written in the near future. The instruction computes an effective address from RA and RB and hints to the memory subsystem to begin preparing the cache line for write-back operations with the temporal locality specified by STRM. This is an advisory instruction supporting store-stream prefetching.", "pseudocode": "EA ← (RA | 0) + RB; InitiateDataStream(EA, STRM, isStore=1, isTransient=0)", "example": "dstst r4, r5, 0" }, { "mnemonic": "dststt", "architecture": "PowerISA", "full_name": "Data Stream Touch for Store Transient", "summary": "Initiates a transient prefetch for writing.", "syntax": "dststt RA, RB, STRM", "encoding": { "format": "X-form", "binary_pattern": "31 | STRM | RA | RB | 374 | /", "hex_opcode": "0x7C0002EC", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "STRM", "clean": "STRM" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "374", "clean": "374" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" }, { "name": "STRM", "desc": "Stream ID" } ], "extension": "Base", "description": "Initiates a hardware prefetch stream for transient (non-temporal) data that is likely to be written in the near future and not reused. The instruction computes an effective address from RA and RB and hints to the memory subsystem to prepare the cache line for write operations with transient semantics. This advisory instruction supports transient store-stream prefetching to reduce cache pollution.", "pseudocode": "EA ← (RA | 0) + RB; InitiateDataStream(EA, STRM, isStore=1, isTransient=1)", "example": "dststt r4, r5, 0" }, { "mnemonic": "dss", "architecture": "PowerISA", "full_name": "Data Stream Stop", "summary": "Stops a data stream prefetch operation.", "syntax": "dss STRM", "encoding": { "format": "X-form", "binary_pattern": "31 | STRM | 0 | 0 | 822 | /", "hex_opcode": "0x7C000666", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "STRM", "clean": "STRM" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "822", "clean": "822" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "STRM", "desc": "Stream ID" } ], "extension": "Base", "description": "Stops the hardware prefetch stream identified by STRM. This instruction terminates data stream prefetching for a specific stream, allowing the hardware to cease streaming operations and free associated resources. It is an advisory instruction with no architectural side effects if data streaming is not supported.", "pseudocode": "StopDataStream(STRM)", "example": "dss 0" }, { "mnemonic": "dssall", "architecture": "PowerISA", "full_name": "Data Stream Stop All", "summary": "Stops all active data stream prefetch operations.", "syntax": "dssall", "encoding": { "format": "X-form", "binary_pattern": "31 | 0 | 0 | 0 | 822 | /", "hex_opcode": "0x7C000666", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "822", "clean": "822" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [], "extension": "Base", "description": "Stops all active data stream prefetch operations initiated by DSS instructions. This is a privileged instruction that terminates data prefetching without affecting general processor state or condition registers. Used to optimize cache behavior by halting speculative data stream operations.", "programming_notes": "Use dssall to halt all data stream operations, preventing any further processing or transfer of data. This instruction is typically used in scenarios where you need to ensure complete cessation of data flow, such as during system shutdowns or critical error handling. Ensure that this instruction is executed at a privilege level sufficient to control data streams, and be aware that it may trigger exceptions if not properly managed.", "pseudocode": "All data stream prefetch operations are terminated.", "example": "dssall" }, { "mnemonic": "dcba", "architecture": "PowerISA", "full_name": "Data Cache Block Allocate", "summary": "Allocates a cache block without loading from memory (optimization for overwrite).", "syntax": "dcba RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | / | RA | RB | 758 | /", "hex_opcode": "0x7C0005EC", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "758", "clean": "758" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Base", "description": "Allocates a cache block at the effective address (RA + RB) into the data cache without loading data from memory. This instruction is used as an optimization hint when the application will overwrite the entire cache block, avoiding unnecessary memory traffic. No condition registers or status fields are modified.", "pseudocode": "EA ← (RA) + (RB)\nAllocate cache block at EA without loading from memory", "example": "dcba r4, r5" }, { "mnemonic": "dcbi", "architecture": "PowerISA", "full_name": "Data Cache Block Invalidate", "summary": "Invalidates a cache block (Privileged).", "syntax": "dcbi RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | / | RA | RB | 470 | /", "hex_opcode": "0x7C0003AC", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "470", "clean": "470" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Privileged", "programming_notes": "Privileged. Invalidates a cache block without writeback. Use only when you know the block is clean or its contents can be discarded.", "description": "Invalidates the data cache block at effective address (RA + RB), removing it from the cache. This is a privileged instruction used for cache management. The instruction does not modify condition registers and may trigger cache coherency operations on multiprocessor systems.", "pseudocode": "EA ← (RA) + (RB)\nInvalidate cache block at EA", "example": "dcbi r4, r5" }, { "mnemonic": "eciwx", "architecture": "PowerISA", "full_name": "External Control In Word Indexed", "summary": "Loads a word from an external device using the EAR register.", "syntax": "eciwx RT, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | RA | RB | 310 | /", "hex_opcode": "0x7C00026C", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "310", "clean": "310" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Base", "description": "Loads a 32-bit word from an external control device into RT, using address formation from RA + RB and device selection from the External Address Register (EAR). This instruction requires special external interface hardware support and does not affect condition registers. It is typically used in embedded or specialized processor configurations.", "pseudocode": "EA ← (RA) + (RB)\nRT ← ExternalLoad32(EA, EAR)", "example": "eciwx r3, r4, r5" }, { "mnemonic": "ecowx", "architecture": "PowerISA", "full_name": "External Control Out Word Indexed", "summary": "Stores a word to an external device using the EAR register.", "syntax": "ecowx RS, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 438 | /", "hex_opcode": "0x7C00036C", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "438", "clean": "438" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RS", "desc": "Source" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Base", "description": "Stores a 32-bit word from RS to an external control device, using address formation from RA + RB and device selection from the External Address Register (EAR). This instruction requires special external interface hardware support and does not affect condition registers. It is typically used in embedded or specialized processor configurations.", "pseudocode": "EA ← (RA) + (RB)\nExternalStore32(EA, EAR, (RS))", "example": "ecowx r3, r4, r5" }, { "mnemonic": "mcrfs", "architecture": "PowerISA", "full_name": "Move to Condition Register from FPSCR", "summary": "Moves a field from the Floating-Point Status and Control Register (FPSCR) to the Condition Register.", "syntax": "mcrfs BF, BFA", "encoding": { "format": "X-form", "binary_pattern": "63 | BF | / | BFA | / | 64 | /", "hex_opcode": "0xFC000080", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "BF", "clean": "BF" }, { "raw": "/", "clean": "/" }, { "raw": "BFA", "clean": "BFA" }, { "raw": "/", "clean": "/" }, { "raw": "64", "clean": "64" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:8 | 9:10 | 11:13 | 14:20 | 21:30 | 31" }, "operands": [ { "name": "BF", "desc": "Target CR" }, { "name": "BFA", "desc": "Src FPSCR" }, { "name": "CRf", "desc": "Condition Register Field" }, { "name": "FPSCRf", "desc": "Floating-Point Status and Control Register Field" } ], "extension": "Floating-Point", "pseudocode": "CR[4*BF:4*BF+3] ← FPSCR[4*BFA:4*BFA+3]\nFPSCR[4*BFA:4*BFA+3] ← 0", "special_registers": "CR0, FPSCR", "page_found": "Page 1468 - 1469", "description": "Moves a 4-bit field from the Floating-Point Status and Control Register (FPSCR) into a 4-bit field of the Condition Register (CR). The source field is specified by BFA and the destination field by BF. The corresponding FPSCR field is cleared after the move, and no other status fields are affected.", "programming_notes": "The mcrfs instruction is commonly used to transfer floating-point status and control information from the FPSCR to a general-purpose register. Ensure that the destination register (FRT) is properly aligned for optimal performance. This instruction operates at user privilege level, but accessing certain bits may require higher privileges depending on system configuration. Be cautious of potential exceptions if the FPSCR contains invalid or unexpected values.", "example": "mcrfs cr0, cr1" }, { "mnemonic": "mfmsr", "architecture": "PowerISA", "full_name": "Move From Machine State Register", "summary": "Moves the contents of the Machine State Register (MSR) into a general-purpose register.", "syntax": "mfmsr RT", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | / | / | 83 | /", "hex_opcode": "0x7C0000A6", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "83", "clean": "83" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RT", "desc": "Target" } ], "extension": "Privileged", "description": "Moves the entire Machine State Register (MSR) into the general-purpose register RT. This is a privileged instruction that allows reading of system state including interrupt enable, privilege level, and other control bits. No condition registers or status fields are modified by this instruction.", "pseudocode": "RT ← MSR", "programming_notes": "This instruction is privileged.", "page_found": "Page 1145 - 1146", "special_registers": "MSR", "example": "mfmsr r3" }, { "mnemonic": "mtmsr", "architecture": "PowerISA", "full_name": "Move To Machine State Register", "summary": "Sets the Machine State Register (MSR) based on the contents of a source register and a control bit.", "syntax": "mtmsr RS,L", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | / | L | 146 | /", "hex_opcode": "0x7C000124", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "/", "clean": "/" }, { "raw": "L", "clean": "L" }, { "raw": "146", "clean": "146" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RS", "desc": "Source" }, { "name": "L", "desc": "Load (32/64)" } ], "extension": "Privileged", "description": "The MSR is set based on the contents of register RS and the L field. If L=0, specific bits are modified based on logical operations involving RS and the current state of the MSR. If L=1, only certain bits (48 and 62) from RS are placed into the corresponding bits of the MSR.", "pseudocode": "if L = 0 then\n MSR48 ← (RS)48 | (RS)49 & ¬(MSR41 & MSR3 & (¬(RS)49))\n MSR58 ← ((RS)58 | (RS)49) & ¬(MSR41 & MSR3 & (¬(RS)49))\n MSR32:40 42:47 49:50 52:57 60:62 ← (RS)32:40 42:47 49:50 52:57 60:62\nelse\n MSR48 62 ← (RS)48 62", "special_registers": "MSR", "programming_notes": "If this instruction sets MSRPR to 1, it also sets MSREE, MSRIR, and MSRDR to 1. If this instruction results in MSRS HV PR being equal to 0b110, it also sets MSRIR and MSRDR to 0. This instruction does not alter MSRS, MSRME, or MSRLE. If the only MSR bits to be altered are MSREE RI, to obtain the best performance L=1 should be used. mtmsr serves as both a basic and an extended mnemonic. The Assembler will recognize an mtmsr mnemonic with two operands as the basic form, and an mtmsr mnemonic with one operand as the extended form. In the extended form the L operand is omitted and assumed to be 0.", "extended_mnemonics": [ { "mnemonic": "mtmsr", "equivalent_to": "mtmsr RS,0" } ], "page_found": "Page 1143 - 1144", "example": "mtmsr r3, 0" }, { "mnemonic": "mtmsrd", "architecture": "PowerISA", "full_name": "Move To Machine State Register Doubleword", "summary": "Sets the Machine State Register (MSR) based on the contents of a source register and an L field.", "syntax": "mtmsrd RS,L", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | / | L | 178 | /", "hex_opcode": "0x7C000164", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "/", "clean": "/" }, { "raw": "L", "clean": "L" }, { "raw": "178", "clean": "178" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RS", "desc": "Source" }, { "name": "L", "desc": "Load" } ], "extension": "Privileged", "description": "The MSR is set based on the contents of register RS and the value of the L field. If L=0, specific bits are updated based on logical operations involving the contents of RS and the current state of the MSR. If L=1, only certain bits (48 and 62) from RS are placed into the corresponding bits of the MSR.", "pseudocode": "if L = 0 then\n MSR48 ← (RS)48 | (RS)49\n if MSRPR = 1 then\n MSREE, MSRIR, MSRDR ← 1\n if MSRS HV PR = 0b110 then\n MSRIR, MSRDR ← 0\nelse\n MSR48 62 ← (RS)48 62", "special_registers": "MSR", "programming_notes": "If this instruction sets MSRPR to 1, it also sets MSREE, MSRIR, and MSRDR to 1. If this instruction results in MSRS HV PR being equal to 0b110, it also sets MSRIR and MSRDR to 0.\n\nIf the only MSR bits to be altered are MSREE RI, to obtain the best performance L=1 should be used.\n\nmtmsrd serves as both a basic and an extended mnemonic. The Assembler will recognize an mtmsrd mnemonic with two operands as the basic form, and an mtmsrd mnemonic with one operand as the extended form. In the extended form the L operand is omitted and assumed to be 0.", "extended_mnemonics": [ { "mnemonic": "mtmsrd", "equivalent_to": "mtmsrd RS,0" } ], "page_found": "Page 1144 - 1145", "example": "mtmsrd r3, 0" }, { "mnemonic": "tlbia", "architecture": "PowerISA", "full_name": "TLB Invalidate All", "summary": "Invalidates the entire Translation Lookaside Buffer.", "syntax": "tlbia", "encoding": { "format": "X-form", "binary_pattern": "31 | / | / | / | 370 | /", "hex_opcode": "0x7C0002E4", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "370", "clean": "370" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [], "extension": "Privileged", "description": "Invalidates all entries in the Translation Lookaside Buffer (TLB), flushing all virtual-to-physical address translations. This is a privileged instruction used for memory management and typically follows changes to page tables. No condition registers are modified; the instruction may have latency on some implementations.", "pseudocode": "for each TLB entry: InvalidateEntry()", "example": "tlbia" }, { "mnemonic": "tlbsync", "architecture": "PowerISA", "full_name": "TLB Synchronize", "summary": "Provides an ordering function for the effects of all tlbie instructions executed by the thread executing the tlbsync instruction.", "syntax": "tlbsync", "encoding": { "format": "X-form", "binary_pattern": "31 | / | / | / | 566 | /", "hex_opcode": "0x7C00046C", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "566", "clean": "566" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [], "extension": "Privileged", "description": "Provides a memory ordering function that ensures all tlbie instructions executed by the thread before this instruction have completed before any instruction after tlbsync begins execution. This is a privileged instruction used to synchronize TLB invalidation operations. No condition registers or status fields are affected; this is purely an ordering barrier for memory management operations.", "programming_notes": "tlbsync should not be used to synchronize the completion of tlbiel.", "page_found": "Page 1221 - 1222", "pseudocode": "Synchronize effects of all preceding tlbie instructions", "example": "tlbsync" }, { "mnemonic": "dcbtst", "architecture": "PowerISA", "full_name": "Data Cache Block Touch for Store", "summary": "Provides a hint that describes a block or data stream to which the program may perform a store access.", "syntax": "dcbtst TH, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | TH | RA | RB | 246 | /", "hex_opcode": "0x7C0001EC", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "TH", "clean": "TH" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "246", "clean": "246" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "TH", "desc": "Hint" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Base", "description": "Issues a cache hint indicating that a data block or stream will be accessed for storage (write). The instruction takes a hint field (TH) and an effective address (RA + RB) but does not load data into cache; it merely communicates intent to the cache hierarchy. No registers are modified and no condition codes are affected.", "programming_notes": "See the Programming Notes at the beginning of this section.", "extended_mnemonics": [ { "mnemonic": "dcbtstds RA,RB,TH", "equivalent_to": "dcbtst RA,RB,TH" }, { "mnemonic": "dcbtstt RA,RB", "equivalent_to": "dcbtst RA,RB,0b10000" } ], "page_found": "Page 1035 - 1036", "pseudocode": "EA ← (RA) + (RB)\n// Hint to cache management that block at EA will be stored to\n// No actual load or register modification occurs", "example": "dcbtst 0, r4, r5" }, { "mnemonic": "icbt", "architecture": "PowerISA", "full_name": "Instruction Cache Block Touch", "summary": "Provides a hint that the program will soon execute code from the block containing the byte addressed by EA, and that the block should be loaded into the cache specified by the CT field.", "syntax": "icbt RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | / | RA | RB | 22 | /", "hex_opcode": "0x7C00002C", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "22", "clean": "22" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" }, { "name": "CT", "desc": "Cache Type Field" } ], "extension": "Base", "description": "Issues a hint that the program will soon execute code from a block and requests that the block be preloaded into the instruction cache. The effective address is computed from RA + RB, and an optional cache-type field (CT, encoded in bits 21-25 of the instruction) specifies which cache level. This is a hint only and does not guarantee a load; no registers are modified.", "pseudocode": "EA ← (RA) + (RB)\n// Hint to instruction cache that block at EA should be preloaded\n// CT field (from instruction bits 21-25) specifies cache type\n// No register modification", "programming_notes": "The hint is ignored if the block is Caching Inhibited. This instruction treated as a Load (see Section 4.3), except that the system data storage error handler is not invoked, and reference and change recording need not be done.", "page_found": "Page 1026 - 1027", "example": "icbt r4, r5" }, { "mnemonic": "mfpvr", "architecture": "PowerISA", "full_name": "Move From Processor Version Register", "summary": "Reads the PVR (Processor ID).", "syntax": "mfpvr RT", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | 287 | 339 | /", "hex_opcode": "0x7C1F42A6", "visual_parts": [ { "raw": "mfspr RT, 287", "clean": "mfspr RT, 287" } ], "bit_positions": "0:5 | 6:10 | 11:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" } ], "extension": "Privileged", "description": "Move From Processor Version Register. Extended mnemonic for MFSPR (mfspr RT,287). Copies the Processor Version Register (PVR) into register RT. The PVR contains the processor version and revision numbers.", "pseudocode": "RT ← PVR", "special_registers": "PVR", "programming_notes": "The mfpvr instruction is used to retrieve the Processor Version Register (PVR), which contains information about the processor's version and revision. This instruction is commonly used for software that needs to detect or adapt to specific processor features or versions. It operates at user privilege level, so no special privileges are required. There are no alignment requirements for this instruction.", "example": "mfpvr r3" }, { "mnemonic": "mftb", "architecture": "PowerISA", "full_name": "Move From Timebase", "summary": "Moves the contents of the Time Base Register (TBR) into a general-purpose register.", "syntax": "mftb RT,268", "encoding": { "format": "XFX-form", "binary_pattern": "31 | RT | 268 | 371 | /", "hex_opcode": "0x7C0002E6", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "268", "clean": "268" }, { "raw": "371", "clean": "371" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:20 | 21:30 | 31" }, "operands": [ { "name": "RT", "desc": "Target" } ], "extension": "Base", "description": "This instruction behaves as if it were an mfspr instruction. The TBR operand is omitted and assumed to be 268 (the value that corresponds to TB).", "pseudocode": "if 'mftb' then\n RT <- TBR[268]", "programming_notes": "This instruction behaves as if it were an mfspr instruction; see the mfspr instruction description in Section 3.3.19 of Book I.\nNew programs should use mfspr instead of mftb to access the Time Base.", "extended_mnemonics": [ "mftb RT", "mfspr RT,268" ], "page_found": "Page 1067 - 1068", "special_registers": "TBR", "example": "mftb r3, 268" }, { "mnemonic": "mftbu", "architecture": "PowerISA", "full_name": "Move From Timebase Upper", "summary": "Reads the upper 32 bits of the Timebase (32-bit implementations).", "syntax": "mftbu RT", "encoding": { "format": "XFX-form", "binary_pattern": "31 | RT | 269 | 371 | /", "hex_opcode": "0x7C0002E7", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "269", "clean": "269" }, { "raw": "371", "clean": "371" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" } ], "extension": "Base", "description": "Reads the upper 32 bits of the Timebase register and places the value into the target GPR. This instruction is primarily used in 32-bit implementations to obtain the high word of the 64-bit Timebase. It does not modify condition registers or status fields.", "pseudocode": "RT ← TBU\n// TBU is the upper 32 bits of the 64-bit Timebase counter", "page_found": "Page 1068", "special_registers": "TBU", "programming_notes": "Use mftbu to capture the high-order bits of the timebase for timestamping or performance measurement. Ensure that your application accounts for potential discrepancies between the upper and lower 32-bit reads due to timebase overflow.", "example": "mftbu r3" }, { "mnemonic": "lbz", "architecture": "PowerISA", "full_name": "Load Byte and Zero", "summary": "Loads a byte from memory into the low 8 bits of a register and clears the upper 56 bits.", "syntax": "lbz RT, D(RA)", "encoding": { "format": "D-form", "binary_pattern": "34 | RT | RA | D", "hex_opcode": "0x88000000", "visual_parts": [ { "raw": "34", "clean": "34" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "D", "clean": "D" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "D", "desc": "Displacement (16-bit Signed)" }, { "name": "RA", "desc": "Base Register" } ], "pseudocode": "if 'lbz' then\n EA ← (RA|0) + EXTS64(D)\n RT ← EXTZ(MEM(EA, 1))", "example": "lbz r3, 0(r4)", "example_note": "Load byte from address in r4.", "extension": "Base", "description": "The effective address (EA) is computed as the sum of the contents of register RA and the sign-extended immediate value D. The byte at EA is loaded into RT, with the upper 56 bits set to zero.", "page_found": "Page 82 - 84", "programming_notes": "The lbz instruction is commonly used for loading a single byte from memory into a register while zeroing out the upper bits. Ensure that the address is properly aligned to avoid potential performance penalties or exceptions. This instruction operates at user privilege level and will raise an exception if the EA is outside the valid address space." }, { "mnemonic": "lhz", "architecture": "PowerISA", "full_name": "Load Halfword and Zero", "summary": "Loads a halfword (16 bits) from memory and clears the upper 48 bits.", "syntax": "lhz RT, D(RA)", "encoding": { "format": "D-form", "binary_pattern": "40 | RT | RA | D", "hex_opcode": "0xA0000000", "visual_parts": [ { "raw": "40", "clean": "40" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "D", "clean": "D" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "D", "desc": "Displacement" }, { "name": "RA", "desc": "Base Register" } ], "pseudocode": "if RA = 0 then\n EA ← sign_extend(D)\nelse\n EA ← (RA) + sign_extend(D)\nRT ← (0 || [EA+1:EA])\n// Load halfword at EA, zero-extend to 64 bits", "example": "lhz r3, 0(r4)", "example_note": "Load unsigned 16-bit value.", "extension": "Base", "description": "Loads a 16-bit halfword from memory at address (RA + sign_extend(D)) and places it into RT with the upper 48 bits cleared to zero. The base register may be R0 if RA is zero in the instruction, in which case the displacement is used as an absolute address. No condition or status registers are affected.", "page_found": "Page 85 - 86", "programming_notes": "The lhz instruction is commonly used for loading halfword values from memory into a register while ensuring the upper 16 bits are zeroed. Ensure that the effective address (EA) is properly aligned to avoid unaligned access exceptions. This instruction operates at user privilege level and will raise an exception if the EA is invalid or if there's a protection fault." }, { "mnemonic": "lha", "architecture": "PowerISA", "full_name": "Load Halfword Algebraic", "summary": "Loads a halfword (16 bits) from memory and sign-extends it to 64 bits.", "syntax": "lha RT, D(RA)", "encoding": { "format": "D-form", "binary_pattern": "42 | RT | RA | D", "hex_opcode": "0xA8000000", "visual_parts": [ { "raw": "42", "clean": "42" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "D", "clean": "D" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "D", "desc": "Displacement" }, { "name": "RA", "desc": "Base Register" } ], "pseudocode": "if RA = 0 then\n EA ← sign_extend(D)\nelse\n EA ← (RA) + sign_extend(D)\nRT ← sign_extend([EA+1:EA])\n// Load halfword at EA and sign-extend to 64 bits", "example": "lha r3, 0(r4)", "example_note": "Load signed 16-bit value.", "extension": "Base", "description": "Loads a 16-bit halfword from memory at address (RA + sign_extend(D)) and places it into RT with sign extension to the full 64-bit width. The base register may be R0 if RA is zero in the instruction. No condition or status registers are affected.", "page_found": "Page 87", "programming_notes": "The lha instruction is commonly used for loading signed halfword values from memory into a register, ensuring proper sign extension. Ensure that the effective address (EA) is properly aligned to avoid alignment faults. This instruction operates at user privilege level and will raise an exception if the EA is invalid or if there are insufficient privileges." }, { "mnemonic": "lwz", "architecture": "PowerISA", "full_name": "Load Word and Zero", "summary": "Loads a word (32 bits) from memory and clears the upper 32 bits.", "syntax": "lwz RT, D(RA)", "encoding": { "format": "D-form", "binary_pattern": "32 | RT | RA | D", "hex_opcode": "0x80000000", "visual_parts": [ { "raw": "32", "clean": "32" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "D", "clean": "D" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "D", "desc": "Displacement" }, { "name": "RA", "desc": "Base Register" } ], "pseudocode": "EA ← (RA|0) + EXTS64(D)\nRT ← 320 || MEM(EA, 4)", "example": "lwz r3, 8(r4)", "example_note": "Load 32-bit int from r4+8.", "extension": "Base", "description": "The effective address (EA) is calculated as (RA|0) + EXTS64(D). The word in storage addressed by EA is loaded into RT32:63. RT0:31 are set to 0.", "page_found": "Page 88 - 90", "programming_notes": "The lwz instruction is commonly used for loading a word from memory into a register while zeroing the upper half of the target register. Ensure that the address is properly aligned to avoid alignment exceptions. This instruction operates at user privilege level and does not generate any exceptions under normal circumstances." }, { "mnemonic": "lwa", "architecture": "PowerISA", "full_name": "Load Word Algebraic", "summary": "Loads a word (32 bits) from memory and sign-extends it to 64 bits.", "syntax": "lwa RT, DS(RA)", "encoding": { "format": "DS-form", "binary_pattern": "58 | RT | RA | DS | 2", "hex_opcode": "0xE8000002", "visual_parts": [ { "raw": "58", "clean": "58" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "DS", "clean": "DS" }, { "raw": "2", "clean": "2" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:29 | 30:31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "DS", "desc": "Displacement (Aligned)" }, { "name": "RA", "desc": "Base Register" } ], "pseudocode": "if RA = 0 then\n EA ← (DS || 0b00)\nelse\n EA ← (RA) + (DS || 0b00)\nRT ← sign_extend([EA+3:EA])\n// Load word at aligned EA and sign-extend to 64 bits", "example": "lwa r3, 8(r4)", "example_note": "Load signed 32-bit int.", "extension": "Base", "description": "Loads a 32-bit word from memory at address (RA + (DS || 0b00)), where DS is a 14-bit signed displacement (making the effective address 4-byte aligned), and places it into RT with sign extension to 64 bits. This is a 64-bit instruction available only in 64-bit implementations. No condition or status registers are affected.", "page_found": "Page 90", "programming_notes": "The lwa instruction is commonly used for loading a 32-bit word from memory into a target register while zeroing out the upper 32 bits. Ensure that the base address in RA and displacement D are correctly aligned to avoid alignment faults. This instruction operates at user privilege level and will raise an exception if the effective address is invalid or if there is a protection fault." }, { "mnemonic": "ld", "architecture": "PowerISA", "full_name": "Load Doubleword", "summary": "Loads a doubleword (64 bits) from memory.", "syntax": "ld RT, DS(RA)", "encoding": { "format": "DS-form", "binary_pattern": "0 | RT | RA | DS | 0 | 31", "hex_opcode": "0xE8000000", "visual_parts": [ { "raw": "58", "clean": "58" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "DS", "clean": "DS" }, { "raw": "0", "clean": "0" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "DS", "desc": "Displacement (14-bit Signed, Multiple of 4)" }, { "name": "RA", "desc": "Base Register" }, { "name": "disp", "desc": "Displacement value" } ], "pseudocode": "if 'ld' then\n EA ← (RA|0) + EXTS64(DS||0b00)\n RT ← MEM(EA, 8)", "example": "ld r3, 16(r4)", "example_note": "Load 64-bit value.", "extension": "Base", "description": "The doubleword in storage addressed by EA is loaded into RT. The effective address (EA) is the sum of RA and disp, sign-extended to 64 bits.", "page_found": "Page 90 - 92", "programming_notes": "The ld instruction loads a doubleword from memory into a register. Ensure the address is properly aligned to avoid alignment faults. This instruction operates at user privilege level and will raise an exception if the EA is out of bounds or access permissions are violated." }, { "mnemonic": "lwarx", "architecture": "PowerISA", "full_name": "Load Word and Reserve Indexed", "summary": "Loads a word and creates a reservation for use with 'stwcx.'. Critical for implementing atomic primitives (mutexes).", "syntax": "lwarx EH=0 RT,RA,D", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | RA | RB | 20 | EH", "hex_opcode": "0x7C000028", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "20", "clean": "20" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "RA", "desc": "Base Register" }, { "name": "RB", "desc": "Index Register" }, { "name": "D", "desc": "Immediate Displacement" }, { "name": "EH", "desc": "Hint for subsequent store operation" } ], "pseudocode": "EA ← (RA) + (RB)\nRT ← sign_extend([EA+3:EA])\nRESERVATION_VALID ← 1\nRESERVATION_ADDR ← page_address(EA)\n// EH field (bit 31) is a hint for subsequent stwcx.", "example": "lwarx r3, 0, r4", "example_note": "Start atomic read-modify-write.", "extension": "Base", "description": "Loads a 32-bit word from memory at address (RA + RB) and places it into RT, and creates a reservation on that cache line for atomic updates with stwcx. The optional EH field (bit 31) provides a hint about the expected success of a subsequent conditional store. This instruction is critical for implementing atomic operations and locks. No condition or status registers are modified by this instruction itself.", "special_registers": "XER, LR", "programming_notes": "EH = 0 should be used when all accesses to a mutex variable are performed using an instruction sequence with Load And Reserve followed by Store Conditional. EH = 1 should be used when the program is obtaining a lock variable which it will subsequently release before another program attempts to perform a store to it.", "page_found": "Page 1050 - 1051", "extended_mnemonics": [ { "mnemonic": "lwarx", "equivalent_to": "lwarx RT,RA,RB,0" } ] }, { "mnemonic": "ldarx", "architecture": "PowerISA", "full_name": "Load Doubleword and Reserve Indexed", "summary": "Loads a doubleword and creates a reservation. 64-bit version of lwarx.", "syntax": "ldarx RT,RA,RB,EH", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | RA | RB | 84 | /", "hex_opcode": "0x7C0000A8", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "84", "clean": "84" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "RA", "desc": "Base Register" }, { "name": "RB", "desc": "Index Register" }, { "name": "EH", "desc": "Hint for subsequent store operation" } ], "pseudocode": "EA ← (RA) + (RB)\nRT ← MEM(EA, 8)\nReserve(EA, 8)", "example": "ldarx r3, 0, r4", "example_note": "Atomic 64-bit load.", "extension": "Base", "description": "Loads a doubleword from memory at address RA+RB and creates a reservation on that memory location for use with subsequent stdcx. instructions. The EH field provides a hint to the processor about the expected outcome of the following store-conditional. This is the 64-bit variant of lwarx and is essential for atomic operations and synchronization primitives.", "programming_notes": "Load Doubleword And Reserve Indexed X-form serves as both a basic and an extended mnemonic. The Assembler will recognize a ldarx mnemonic with four operands as the basic form, and a ldarx mnemonic with three operands as the extended form.", "extended_mnemonics": [ { "mnemonic": "ldarx", "equivalent_to": "ldarx RT,RA,RB,0" } ], "page_found": "Page 1056 - 1057", "special_registers": "RESERVE, RESERVE_LENGTH, RESERVE_ADDR" }, { "mnemonic": "mtspr", "architecture": "PowerISA", "full_name": "Move To Special Purpose Register", "summary": "Copies a value from a general-purpose register to a system SPR (e.g., CTR, LR, XER).", "syntax": "mtspr SPR, RS", "encoding": { "format": "XFX-form", "binary_pattern": "31 | RS | SPR | 467 | /", "hex_opcode": "0x7C0003A6", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "SPR", "clean": "SPR" }, { "raw": "467", "clean": "467" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:20 | 21:30 | 31" }, "operands": [ { "name": "SPR", "desc": "Special Purpose Register ID (Reordered bits)" }, { "name": "RS", "desc": "Source Register" } ], "pseudocode": "SPR_index ← (SPR[5:0] || SPR[10:5])\nSPR[SPR_index] ← RS", "example": "mtspr 9, r3", "example_note": "Move r3 to Count Register (CTR).", "extension": "Base", "description": "Moves the contents of a general-purpose register to a special-purpose register (such as CTR, LR, XER, FPSCR, or others). The SPR field is reordered from its 10-bit encoding in the instruction. Privilege level and results depend on which SPR is targeted; some SPRs are supervisor-only. No condition register flags are set by this instruction itself.", "special_registers": "AMR, IAMR, UAMOR, BESCR, BESCRU, HMER, TBL, TBU, SPR", "programming_notes": "spr0=1 if and only if writing the register is privileged. Execution of this instruction specifying an SPR number with spr0=1 when the privilege state of the thread does not permit the access causes one of the following: MSRPR=1: Privileged Instruction type Program interrupt, MSRHV PR=0b00 or MSRS HV PR=0b010 and the SPR is always an ultravisor resource (independent of the contents of SMFCTRL): Privileged Instruction type Program interrupt, LPCREVIRT=0: Privileged Instruction type Program interrupt, LPCREVIRT=1: Hypervisor Emulation Assistance interrupt, MSRS HV PR=0b010 and the SPR is PTCR, DAWRn, DAWRXn, or CIABR when they are ultravisor privileged for the operation: Hypervisor Emulation Assistance interrupt.", "extended_mnemonics": [ { "mnemonic": "mtxer", "equivalent_to": "mtspr 1,RS" }, { "mnemonic": "mtlr", "equivalent_to": "mtspr 8,RS" }, { "mnemonic": "mtctr", "equivalent_to": "mtspr 9,RS" }, { "mnemonic": "mtppr", "equivalent_to": "mtspr 896,RS" }, { "mnemonic": "mtppr32", "equivalent_to": "mtspr 898,RS" } ], "page_found": "Page 161 - 162" }, { "mnemonic": "mfspr", "architecture": "PowerISA", "full_name": "Move From Special Purpose Register", "summary": "Moves the contents of a special purpose register into a general-purpose register.", "syntax": "mfspr RT, SPR", "encoding": { "format": "XFX-form", "binary_pattern": "10 | RT | SPR[5:0] | SPR[10:5]", "hex_opcode": "0x7C0002A6", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "SPR", "clean": "SPR" }, { "raw": "339", "clean": "339" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "SPR", "desc": "Special Purpose Register ID" } ], "pseudocode": "SPR_index ← (SPR[5:0] || SPR[10:5])\nRT ← SPR[SPR_index]", "example": "mfspr r3, 8", "example_note": "Move Link Register (LR) to r3.", "extension": "Base", "description": "Moves the contents of a special-purpose register into a general-purpose register. The SPR field is reordered from its 10-bit encoding. Privilege level and results depend on which SPR is read; some SPRs are supervisor-only or hypervisor-only. No condition register flags are modified.", "programming_notes": "The SPR field denotes a Special Purpose Register, encoded as shown in the table below. If the SPR field contains a value from 808 through 811, the instruction specifies a reserved SPR, and is treated as a no-op; see Section 1.3.3, “Reserved Fields, Reserved Values, and Reserved SPRs”. Otherwise, the contents of the designated Special Purpose Register are placed into register RT. For Special Purpose Registers that are 32 bits long, the low-order 32 bits of RT receive the contents of the Special Purpose Register and the high-order 32 bits of RT are set to zero.", "extended_mnemonics": [ { "mnemonic": "mfxer", "equivalent_to": "mfspr RT,1" }, { "mnemonic": "mflr", "equivalent_to": "mfspr RT,8" }, { "mnemonic": "mfctr", "equivalent_to": "mfspr RT,9" } ], "page_found": "Page 162 - 164", "special_registers": "SPR" }, { "mnemonic": "mullw", "architecture": "PowerISA", "full_name": "Multiply Low Word", "summary": "Multiplies two 32-bit integers and stores the lower 32 bits of the 64-bit result.", "syntax": "mullw RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "31 | RT | RA | RB | OE | 235 | Rc", "hex_opcode": "0x7C0001D6", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "OE", "clean": "OE" }, { "raw": "235", "clean": "235" }, { "raw": "Rc", "clean": "Rc" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21 | 22:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RA", "desc": "Src 1" }, { "name": "RB", "desc": "Src 2" } ], "pseudocode": "product ← (RA) ×signed (RB)\nRT ← product[32:63]\nif OE = 1 then\n OV ← (product[0:31] ≠ sign_extend(product[32:63]))\n SO ← SO | OV\nif Rc = 1 then\n CR0 ← (RT < 0) || (RT > 0) || (RT = 0) || SO", "example": "mullw r3, r4, r5", "example_note": "32-bit multiply.", "extension": "Base", "description": "Multiplies the contents of RA and RB as signed 32-bit integers and stores the lower 32 bits of the 64-bit result in RT. If OE=1, sets OV and SO in XER if the result overflows (i.e., if the upper 32 bits of the 64-bit product differ from the sign extension of bits 0-31). If Rc=1, updates CR0 based on the result.", "page_found": "Page 116", "special_registers": "CR0", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER." }, { "mnemonic": "mulld", "architecture": "PowerISA", "full_name": "Multiply Low Doubleword", "summary": "Multiplies the contents of two registers and places the low-order 64 bits of the product into a target register.", "syntax": "mulld RT,RA,RB", "encoding": { "format": "XO-form", "binary_pattern": "31 | RT | RA | RB | OE | 233 | Rc", "hex_opcode": "0x7C0001D2", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "OE", "clean": "OE" }, { "raw": "233", "clean": "233" }, { "raw": "Rc", "clean": "Rc" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21 | 22:30 | 31" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RA", "desc": "Src 1" }, { "name": "RB", "desc": "Src 2" } ], "pseudocode": "prod0:127 ← (RA) × (RB)\nRT ← prod0:63\nif OE=1 then\n OV and OV32 are set to 1 if the product cannot be represented in 64 bits.", "example": "mulld r3, r4, r5", "example_note": "64-bit multiply.", "extension": "Base", "description": "The 64-bit operands are (RA) and (RB). The low-order 64 bits of the 128-bit product of the operands are placed into register RT. Both operands and the product are interpreted as signed integers.", "special_registers": "CR0, XER", "programming_notes": "The XO-form Multiply instructions may execute faster on some implementations if RB contains the operand having the smaller absolute value.", "page_found": "Page 120 - 122" }, { "mnemonic": "mr", "architecture": "PowerISA", "full_name": "Move Register", "summary": "Copies contents of RS to RA. (Alias for 'or RA, RS, RS').", "syntax": "mr RA, RS", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RS | 444 | /", "hex_opcode": "0x7C000378", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RS", "clean": "RS" }, { "raw": "444", "clean": "444" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "RS", "desc": "Source" } ], "extension": "Base", "description": "Move Register. Extended mnemonic for OR (or RA,RS,RS). Copies the contents of register RS into register RA.", "pseudocode": "RA ← RS", "programming_notes": "The `mr` instruction is commonly used to copy values between general-purpose registers. It does not require any special alignment or privilege level. However, be cautious when using this instruction in performance-critical sections as it may introduce pipeline stalls if the destination register is already in use.", "example": "mr r4, r3" }, { "mnemonic": "sc", "architecture": "PowerISA", "full_name": "System Call", "summary": "Provides the means by which a program can call upon the system to perform a service.", "syntax": "sc LEV", "encoding": { "format": "SC-form", "binary_pattern": "17 | / | / | / | LEV | / | 1", "hex_opcode": "0x44000002", "visual_parts": [ { "raw": "17", "clean": "17" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "LEV", "clean": "LEV" }, { "raw": "/", "clean": "/" }, { "raw": "1", "clean": "1" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:19 | 20:26 | 27:30 | 31" }, "operands": [ { "name": "LEV", "desc": "Level (0=OS, 1=Hypervisor)" } ], "extension": "Base", "description": "Triggers a system call, transferring control to the operating system (LEV=0) or hypervisor (LEV=1). The instruction is privileged; attempting to execute it in user mode or with an invalid LEV value may cause an exception. The LEV field indicates the target privilege level for the service request.", "pseudocode": "if LEV = 0 then\n SyscallOS()\nelse if LEV = 1 then\n SyscallHypervisor()\nelse\n raise exception", "special_registers": "SRR0, SRR1, MSR", "programming_notes": "Executing this instruction with LEV=1 or LEV=2 is the only way that executing an instruction can cause a transition from non-hypervisor state to hypervisor state on the thread that executed the instruction. Executing this instruction with LEV=2 when SMFCTRLE=1 is the only way that executing an instruction can cause a transition from non-ultravisor state to ultravisor state on the thread that executed the instruction. In correct use, this instruction is used to 'call up' one privilege level (application program calls operating system, operating system calls hypervisor, hypervisor calls ultravisor). However, it is possible for a program to call up more than one level (e.g., for an application program to call the hypervisor). An attempt to call up more than one level should be considered a programming error.", "extended_mnemonics": [ "sc" ], "page_found": "Page 1119 - 1120", "example": "sc 0" }, { "mnemonic": "nop", "architecture": "PowerISA", "full_name": "No Operation", "summary": "Does nothing. (Alias for 'ori 0, 0, 0').", "syntax": "nop", "encoding": { "format": "D-form", "binary_pattern": "24 | 0 | 0 | 0", "hex_opcode": "0x60000000", "visual_parts": [ { "raw": "24", "clean": "24" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:31", "length": "32" }, "operands": [], "extension": "Base", "description": "A no-operation instruction that performs no action and modifies no registers or status flags. It is commonly used for instruction alignment, timing, or as a placeholder. This is implemented as an alias for 'ori 0, 0, 0' in the base ISA.", "pseudocode": "(no operation)", "page_found": "Page 134", "programming_notes": "The nop instruction is useful for optimizing code by reducing unnecessary operations, but it has no effect on program state or execution flow.", "example": "nop" }, { "mnemonic": "li", "architecture": "PowerISA", "full_name": "Load Immediate", "summary": "Loads a 16-bit signed immediate into a register. (Alias for 'addi RT, 0, SIM').", "syntax": "li RT, SIM", "encoding": { "format": "D-form", "binary_pattern": "14 | RT | 0 | SIM", "hex_opcode": "0x38000000", "visual_parts": [ { "raw": "14", "clean": "14" }, { "raw": "RT", "clean": "RT" }, { "raw": "0", "clean": "0" }, { "raw": "SIM", "clean": "SIM" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "SIM", "desc": "Immediate" } ], "extension": "Base", "description": "Loads a 16-bit signed immediate value into the target register. This is an assembly-language alias for 'addi RT, 0, SIM' that simplifies loading small constants. No condition register flags are affected.", "pseudocode": "RT ← sign_extend(SIM, 16)", "page_found": "Page 55", "programming_notes": "The `li` instruction is commonly used for initializing or resetting registers to specific values. Ensure the immediate value fits within the 32-bit signed integer range to avoid unexpected behavior. This instruction operates at user privilege level and does not generate exceptions unless there are issues with the instruction encoding.", "example": "li r3, 4" }, { "mnemonic": "lis", "architecture": "PowerISA", "full_name": "Load Immediate Shifted", "summary": "Loads a 16-bit immediate into the upper half of a 32-bit word. (Alias for 'addis RT, 0, SIM').", "syntax": "lis RT, SIM", "encoding": { "format": "D-form", "binary_pattern": "15 | RT | 0 | SIM", "hex_opcode": "0x3C000000", "visual_parts": [ { "raw": "15", "clean": "15" }, { "raw": "RT", "clean": "RT" }, { "raw": "0", "clean": "0" }, { "raw": "SIM", "clean": "SIM" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "SIM", "desc": "Immediate" } ], "extension": "Base", "description": "The 'lis' instruction loads an immediate value shifted left by 16 bits into a register. If the source register (RA) is zero, it uses the value 0; otherwise, it adds the contents of RA to the sign-extended immediate value.", "pseudocode": "if RA = 0 then\n RT ← EXTS(SI || 160)\nelse\n RT ← (RA) + EXTS(SI || 160)", "page_found": "Page 110", "programming_notes": "The 'lis' instruction is commonly used to load large constants into a register by shifting the immediate value left by 16 bits. If the source register (RA) is not zero, its contents are added to the sign-extended immediate value. Be cautious with alignment as this can affect performance and correctness. This instruction operates at user privilege level.", "example": "lis r3, 4" }, { "mnemonic": "not", "architecture": "PowerISA", "full_name": "Complement Register", "summary": "Complements the contents of one register and places the result into another register.", "syntax": "not Rx,Ry", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RS | 124 | /", "hex_opcode": "0x7C0000F8", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RS", "clean": "RS" }, { "raw": "124", "clean": "124" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "RS", "desc": "Source" }, { "name": "Rx", "desc": "Target General Purpose Register" }, { "name": "Ry", "desc": "Source General Purpose Register" } ], "extension": "Base", "description": "The 'not' instruction complements the contents of register Ry and places the result into register Rx. This mnemonic can be coded with a final '.' to cause the Rc bit to be set in the underlying instruction.", "pseudocode": "if 'not' then\n Rx <- ~Ry\nif 'not.' then\n Rx <- ~Ry\n Rc = 1", "special_registers": "CR0, XER", "page_found": "Page 1001 - 1002", "programming_notes": "The 'not' instruction is commonly used for bitwise negation of a register's contents. Be cautious with the '.' suffix as it affects the condition register (CR0) by setting the Rc bit, which can impact subsequent conditional branches. Ensure that the registers are properly aligned and accessible at the privilege level required for execution.", "example": "not r3, r4" }, { "mnemonic": "mtctr", "architecture": "PowerISA", "full_name": "Move To Count Register", "summary": "Moves GPR to CTR. (Alias for 'mtspr 9, RS').", "syntax": "mtctr RS", "encoding": { "format": "XFX-form", "binary_pattern": "31 | RS | 9 | 467 | /", "hex_opcode": "0x7C0903A6", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "9", "clean": "9" }, { "raw": "467", "clean": "467" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RS", "desc": "Source" } ], "extension": "Base", "description": "Moves a value from a general-purpose register into the Count register (CTR), typically used to set up loop counts or branch targets for branch-to-CTR instructions. This is an alias for 'mtspr 9, RS' where SPR 9 designates CTR. No condition register flags are modified.", "page_found": "Page 162", "pseudocode": "CTR ← RS", "special_registers": "CTR", "programming_notes": "The mtctr instruction is commonly used to set up loop counters by moving values from a general-purpose register into the Count Register (CTR). Ensure that the source register contains the correct value for the desired loop iterations. This instruction operates at user privilege level and does not generate exceptions under normal conditions, but incorrect usage can lead to infinite loops if not managed properly.", "example": "mtctr r3" }, { "mnemonic": "mfctr", "architecture": "PowerISA", "full_name": "Move From Count Register", "summary": "Moves CTR to GPR. (Alias for 'mfspr RT, 9').", "syntax": "mfctr RT", "encoding": { "format": "XFX-form", "binary_pattern": "31 | RT | 9 | 339 | /", "hex_opcode": "0x7C0902A6", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "9", "clean": "9" }, { "raw": "339", "clean": "339" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" } ], "extension": "Base", "description": "Moves the Count Register (CTR) to a general-purpose register. This is an alias for mfspr RT, 9 and is commonly used to save the loop counter or retrieve branching information. No status registers are affected.", "pseudocode": "RT ← CTR", "page_found": "Page 164", "special_registers": "CTR", "programming_notes": "The mfctr instruction is commonly used to retrieve the current count value from the Count Register, which is often utilized in loop control. Ensure that the destination register (RT) is properly aligned and accessible at the privilege level where this instruction is executed. This instruction does not raise exceptions under normal circumstances but should be used with caution in critical loops to avoid unintended behavior.", "example": "mfctr r3" }, { "mnemonic": "mtlr", "architecture": "PowerISA", "full_name": "Move To Link Register", "summary": "Moves GPR to LR. (Alias for 'mtspr 8, RS').", "syntax": "mtlr RS", "encoding": { "format": "XFX-form", "binary_pattern": "31 | RS | 8 | 467 | /", "hex_opcode": "0x7C0803A6", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "8", "clean": "8" }, { "raw": "467", "clean": "467" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RS", "desc": "Source" } ], "extension": "Base", "description": "Move To Link Register. Extended mnemonic for MTSPR (mtspr 8,RS). Copies the contents of register RS into the Link Register (LR).", "pseudocode": "LR ← RS", "special_registers": "LR", "programming_notes": "The mtlr instruction is commonly used to update the Link Register with a new value, often during function calls or branch operations. Ensure that the source register contains the correct address or value before executing this instruction. This operation does not require any special privileges and will not generate exceptions under normal circumstances.", "example": "mtlr r3" }, { "mnemonic": "mflr", "architecture": "PowerISA", "full_name": "Move From Link Register", "summary": "Moves LR to GPR. (Alias for 'mfspr RT, 8').", "syntax": "mflr RT", "encoding": { "format": "XFX-form", "binary_pattern": "31 | RT | 8 | 339 | /", "hex_opcode": "0x7C0802A6", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "8", "clean": "8" }, { "raw": "339", "clean": "339" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" } ], "extension": "Base", "description": "Moves the Link Register (LR) to a general-purpose register. This is an alias for mfspr RT, 8 and is commonly used to save the return address before modifying LR. No status registers are affected.", "pseudocode": "RT ← LR", "page_found": "Page 164", "special_registers": "LR", "programming_notes": "Use mflr to save the return address before making a function call, ensuring you can return correctly afterward. Ensure the target register (RT) is not reserved and is properly aligned for your architecture.", "example": "mflr r3" }, { "mnemonic": "rlwinm", "architecture": "PowerISA", "full_name": "Rotate Left Word Immediate Then AND with Mask", "summary": "Rotates the low-order 32 bits of a register left by a specified number of bit positions, generates a mask, and performs an AND operation.", "syntax": "rlwinm RA,RS,SH,MB,ME", "encoding": { "format": "M-form", "binary_pattern": "21 | RS | RA | SH | MB | ME | Rc", "hex_opcode": "0x54000000", "visual_parts": [ { "raw": "21", "clean": "21" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "SH", "clean": "SH" }, { "raw": "MB", "clean": "MB" }, { "raw": "ME", "clean": "ME" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:30 | 31" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "RS", "desc": "Source" }, { "name": "SH", "desc": "Shift" }, { "name": "MB", "desc": "Mask Begin" }, { "name": "ME", "desc": "Mask End" } ], "extension": "Base", "description": "The contents of register RS are rotated32 left SH bits. A mask is generated having 1-bits from bit MB+32 through bit ME+32 and 0-bits elsewhere. The rotated data are ANDed with the generated mask and the result is placed into register RA.", "pseudocode": "if 'rlwinm' then\n n ← SH\n r ← ROTL32((RS)32:63, n)\n m ← MASK(MB+32, ME+32)\n RA ← r & m", "special_registers": "CR0", "programming_notes": "Let RSL represent the low-order 32 bits of register RS, with the bits numbered from 0 through 31. rlwinm can be used to extract an n-bit field that starts at bit position b in RSL, right-justified into the low-order 32 bits of register RA (clearing the remaining 32-n bits of the low-order 32 bits of RA), by setting SH=b+n, MB=32-n, and ME=31. It can be used to extract an n-bit field that starts at bit position b in RSL, left-justified into the low-order 32 bits of register RA (clearing the remaining 32-n bits of the low-order 32 bits of RA), by setting SH=b, MB = 0, and ME=n-1. It can be used to rotate the contents of the low-order 32 bits of a register left (right) by n bits, by setting SH=n (32-n), MB=0, and ME=31. It can be used to shift the contents of the low-order 32 bits of a register right by n bits, by setting SH=32-n, MB=n, and ME=31. It can be used to clear the high-order b bits of the low-order 32 bits of the contents of a register and then shift the result left by n bits, by setting SH=n, MB=b-n, and ME=31-n. It can be used to clear the low-order n bits of the low-order 32 bits of a register, by setting SH=0, MB=0, and ME=31-n.", "extended_mnemonics": [ { "mnemonic": "extlwi", "equivalent_to": "rlwinm RA,RS,b,0,n-1" }, { "mnemonic": "srwi", "equivalent_to": "rlwinm RA,RS,32-n,n,31" }, { "mnemonic": "clrrwi", "equivalent_to": "rlwinm RA,RS,0,0,31-n" }, { "name": "extlwi", "equivalent_to": "rlwinm RA,RS,b,0,n-1" }, { "name": "srwi", "equivalent_to": "rlwinm RA,RS,32-n,n,31" }, { "name": "clrrwi", "equivalent_to": "rlwinm RA,RS,0,0,31-n" } ], "page_found": "Page 142 - 144", "example": "rlwinm r4, r3, 3, 0, 31" }, { "mnemonic": "rlwimi", "architecture": "PowerISA", "full_name": "Rotate Left Word Immediate Then Mask Insert", "summary": "Rotates a word left, then inserts bits into the target under a mask. Used for inserting bitfields.", "syntax": "rlwimi RA, RS, SH, MB, ME", "encoding": { "format": "M-form", "binary_pattern": "20 | RS | RA | SH | MB | ME", "hex_opcode": "0x50000000", "visual_parts": [ { "raw": "20", "clean": "20" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "SH", "clean": "SH" }, { "raw": "MB", "clean": "MB" }, { "raw": "ME", "clean": "ME" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target/Dest" }, { "name": "RS", "desc": "Source" }, { "name": "SH", "desc": "Shift" }, { "name": "MB", "desc": "Mask Begin" }, { "name": "ME", "desc": "Mask End" } ], "extension": "Base", "description": "Rotates the contents of RS left by SH bit positions, creates a mask from bits MB through ME, and inserts the rotated value into RA under that mask, leaving other bits in RA unchanged. The condition register CR0 is updated if Rc=1.", "pseudocode": "n ← SH\nmask ← MASK(MB, ME)\nrotated ← ROTL32(RS, n)\nRA ← (RA & ¬mask) | (rotated & mask)\nif Rc = 1 then CR0 ← (RA < 0, RA > 0, RA = 0, SO)", "page_found": "Page 145", "programming_notes": "The rlwimi instruction is commonly used for bit manipulation tasks such as rotating bits and selectively inserting them into a register. Be cautious with the shift amount (SH), mask bits (MB and ME), and ensure they are within valid ranges to avoid unexpected results. This instruction operates at user privilege level and does not generate exceptions under normal conditions, but improper use can lead to data corruption.", "example": "rlwimi r4, r3, 3, 0, 31" }, { "mnemonic": "rlwnm", "architecture": "PowerISA", "full_name": "Rotate Left Word Then AND with Mask", "summary": "Rotates the contents of register RS left by the number of bits specified by (RB)59:63, and then performs a bitwise AND operation with a mask.", "syntax": "rlwnm RT,RS,RB,MB,ME", "encoding": { "format": "M-form", "binary_pattern": "23 | RS | RA | RB | MB | ME | Rc", "hex_opcode": "0x5C000000", "visual_parts": [ { "raw": "23", "clean": "23" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "MB", "clean": "MB" }, { "raw": "ME", "clean": "ME" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:30 | 31" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "RS", "desc": "Source" }, { "name": "RB", "desc": "Shift Reg" }, { "name": "MB", "desc": "Mask Begin" }, { "name": "ME", "desc": "Mask End" }, { "name": "RT", "desc": "Target General Purpose Register" } ], "extension": "Base", "description": "The contents of register RS are rotated 32 left the number of bits specified by (RB)59:63. A mask is generated having 1-bits from bit MB+32 through bit ME+32 and 0-bits elsewhere. The rotated data are ANDed with the generated mask and the result is placed into register RA.", "pseudocode": "if 'rlwnm' then\n n ← (RB)59:63\n r ← ROTL32((RS)32:63, n)\n m ← MASK(MB+32, ME+32)\n RA ← r & m\nelse if 'rlwnm.' then\n n ← (RB)59:63\n r ← ROTL32((RS)32:63, n)\n m ← MASK(MB+32, ME+32)\n RA ← r & m", "special_registers": "CR0", "programming_notes": "RS, with the bits numbered from 0 through 31. rlwnm can be used to extract an n-bit field that starts at variable bit position b in RSL, right-justified into the low-order 32 bits of register RA (clearing the remaining 32-n bits of the low-order 32 bits of RA), by setting RB59:63=b+n, MB=32-n, and ME=31. It can be used to extract an n-bit field that starts at variable bit position b in RSL, left-justified into the low-order 32 bits of register RA (clearing the remaining 32-n bits of the low-order 32 bits of RA), by setting RB59:63=b, MB = 0, and ME=n-1. It can be used to rotate the contents of the low-order 32 bits of a register left (right) by variable n bits, by setting RB59:63=n (32-n), MB=0, and ME=31.", "extended_mnemonics": [ { "mnemonic": "rotlw", "equivalent_to": "rlwnm RA,RS,RB,0,31" }, { "mnemonic": "rotlw.", "equivalent_to": "rlwnm. RA,RS,RB,0,31" } ], "page_found": "Page 144 - 146", "example": "rlwnm r3, r3, r5, 0, 31" }, { "mnemonic": "rldic", "architecture": "PowerISA", "full_name": "Rotate Left Doubleword Immediate Clear", "summary": "Rotates a 64-bit register left, then clears bits based on a mask. 64-bit equivalent of rlwinm.", "syntax": "rldic RT,RA,RB,MB", "encoding": { "format": "MD-form", "binary_pattern": "30 | RS | RA | SH | MB | 2 | sh Rc", "hex_opcode": "0x78000008", "visual_parts": [ { "raw": "30", "clean": "30" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "SH", "clean": "SH" }, { "raw": "MB", "clean": "MB" }, { "raw": "00", "clean": "00" }, { "raw": "Rc", "clean": "Rc" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "RS", "desc": "Source" }, { "name": "SH", "desc": "Shift Amount" }, { "name": "MB", "desc": "Mask Begin" }, { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RB", "desc": "Immediate Value for SH (Shift Amount)" } ], "pseudocode": "if 'rldic' then\n SH ← sh5 || sh0:4\n r ← ROTL64((RS), SH)\n MB ← mb5 || mb0:4\n m ← MASK(MB, 63-SH)\n RA ← r & m", "example": "rldic r3, r4, 4, 10", "example_note": "Rotate left 4, clear bits 0-9.", "extension": "Base", "description": "The contents of register RS are rotated64 left SH bits. A mask is generated having 1-bits from bit MB through bit 63-SH and 0-bits elsewhere. The rotated data are ANDed with the generated mask and the result is placed into register RA.", "special_registers": "CR0", "programming_notes": "rldic can be used to clear the high-order b bits of the contents of a register and then shift the result left by n bits, by setting SH=n and MB=b-n. It can be used to clear the high-order n bits of a register, by setting SH=0 and MB=n.", "extended_mnemonics": [ { "mnemonic": "clrlsldi", "equivalent_to": "rldic RA,RS,n,b-n" }, { "mnemonic": "clrlsldi.RA,RS,b,n", "equivalent_to": "rldic. RA,RS,n,b-n" } ], "page_found": "Page 146 - 148" }, { "mnemonic": "rldicl", "architecture": "PowerISA", "full_name": "Rotate Left Doubleword Immediate Clear Left", "summary": "Rotates the contents of a register left by a specified number of bits and clears higher-order bits.", "syntax": "rldicl RA, RS, SH, MB", "encoding": { "format": "MD-form", "binary_pattern": "30 | RS | RA | SH | MB | 0 | sh | Rc", "hex_opcode": "0x78000000", "visual_parts": [ { "raw": "30", "clean": "30" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "SH", "clean": "SH" }, { "raw": "MB", "clean": "MB" }, { "raw": "0", "clean": "0" }, { "raw": "SH", "clean": "SH" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:29 | 30 | 31" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "RS", "desc": "Source" }, { "name": "SH", "desc": "Shift" }, { "name": "MB", "desc": "Mask Begin" } ], "extension": "Base", "description": "The contents of register RS are rotated 64 left SH bits. A mask is generated having 1-bits from bit MB through bit 63 and 0-bits elsewhere. The rotated data are ANDed with the generated mask and the result is placed into register RA.", "pseudocode": "SH ← SH5 || SH0:4\nr ← ROTL64((RS), SH)\nMB ← MB5 || MB0:4\nm ← MASK(MB, 63)\nRA ← r & m", "programming_notes": "rldicl can be used to extract an n-bit field that starts at bit position b in register RS, right-justified into register RA (clearing the remaining 64-n bits of RA), by setting SH=b+n and MB=64-n. It can be used to rotate the contents of a register left by n bits, by setting SH=n and MB=0. It can be used to shift the contents of a register right by n bits, by setting SH=64-n and MB=n. It can be used to clear the high-order n bits of a register, by setting SH=0 and MB=n.", "extended_mnemonics": [ { "mnemonic": "extrdi", "equivalent_to": "rldicl RA,RS,b+n,64-n" }, { "mnemonic": "srdi", "equivalent_to": "rldicl RA,RS,64-n,n" }, { "mnemonic": "clrldi", "equivalent_to": "rldicl RA,RS,0,n" } ], "page_found": "Page 145 - 146", "special_registers": "CR0", "example": "rldicl r4, r3, 3, 0" }, { "mnemonic": "rldicr", "architecture": "PowerISA", "full_name": "Rotate Left Doubleword Immediate Clear Right", "summary": "Rotates 64-bit RS left by SH, then clears the low-order bits (ME+1 to 63).", "syntax": "rldicr RA, RS, SH, ME", "encoding": { "format": "MD-form", "binary_pattern": "30 | RS | RA | SH | ME | 01 | Rc", "hex_opcode": "0x78000004", "visual_parts": [ { "raw": "30", "clean": "30" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "SH", "clean": "SH" }, { "raw": "ME", "clean": "ME" }, { "raw": "01", "clean": "01" }, { "raw": "Rc", "clean": "Rc" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:26 | 27:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "RS", "desc": "Source" }, { "name": "SH", "desc": "Shift Amount" }, { "name": "ME", "desc": "Mask End" } ], "pseudocode": "n ← SH\nmask ← MASK(0, ME)\nrotated ← ROTL64(RS, n)\nRA ← rotated & mask\nif Rc = 1 then CR0 ← (RA < 0, RA > 0, RA = 0, SO)", "example": "rldicr r3, r4, 2, 60", "example_note": "Align address to 8 bytes.", "extension": "Base", "description": "Rotates the 64-bit contents of RS left by SH positions, then clears bits (ME+1) through 63, effectively creating a mask from bit 0 through ME. The condition register CR0 is updated if Rc=1.", "page_found": "Page 146", "special_registers": "CR0", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER." }, { "mnemonic": "rldimi", "architecture": "PowerISA", "full_name": "Rotate Left Doubleword Immediate Mask Insert", "summary": "Rotates 64-bit value and inserts into target under mask.", "syntax": "rldimi RA, RS, SH, MB", "encoding": { "format": "MD-form", "binary_pattern": "30 | RS | RA | SH | MB | 3 | SH", "hex_opcode": "0x7800000C", "visual_parts": [ { "raw": "30", "clean": "30" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "SH", "clean": "SH" }, { "raw": "MB", "clean": "MB" }, { "raw": "3", "clean": "3" }, { "raw": "SH", "clean": "SH" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:26 | 27:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "RS", "desc": "Source" }, { "name": "SH", "desc": "Shift" }, { "name": "MB", "desc": "Mask Begin" } ], "extension": "Base", "description": "Rotates the 64-bit contents of RS left by SH positions and inserts the result into RA under a mask defined by MB and (63-SH), leaving other bits in RA unchanged. The condition register CR0 is updated if Rc=1.", "pseudocode": "n ← SH\nmask ← MASK(MB, 63 - n)\nrotated ← ROTL64(RS, n)\nRA ← (RA & ¬mask) | (rotated & mask)\nif Rc = 1 then CR0 ← (RA < 0, RA > 0, RA = 0, SO)", "page_found": "Page 148", "programming_notes": "The rldimi instruction is useful for performing masked left rotations on 64-bit values. Ensure that the shift amount (SH) and mask bits (MB) are within valid ranges to avoid undefined behavior. This instruction operates at user privilege level and does not generate exceptions under normal conditions, but incorrect usage can lead to unexpected results.", "example": "rldimi r4, r3, 3, 0" }, { "mnemonic": "sld", "architecture": "PowerISA", "full_name": "Shift Left Doubleword", "summary": "Shifts a 64-bit register left by the amount specified in RB.", "syntax": "sld RA, RS, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 27 | Rc", "hex_opcode": "0x7C000036", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "27", "clean": "27" }, { "raw": "Rc", "clean": "Rc" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RA", "desc": "Target Register" }, { "name": "RS", "desc": "Source Register" }, { "name": "RB", "desc": "Shift Amount Register" }, { "name": "RT", "desc": "Target General Purpose Register" } ], "pseudocode": "if (RB)57 = 0 then\n n ←(RB)58:63\n r ←ROTL64((RS), n)\n m ←MASK(0, 63-n)\nelse\n m ←640\nRA ←r & m", "example": "sld r3, r4, r5", "example_note": "r3 = r4 << r5 (64-bit).", "extension": "Base", "description": "The contents of register RS are shifted left the number of bits specified by (RB)57:63. Bits shifted out of position 0 are lost. Zeros are supplied to the vacated positions on the right. The result is placed into register RA. Shift amounts from 64 to 127 give a zero result.", "special_registers": "CR0", "page_found": "Page 150 - 152", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER." }, { "mnemonic": "srd", "architecture": "PowerISA", "full_name": "Shift Right Doubleword", "summary": "Logical right shift of 64-bit value.", "syntax": "srd RA, RS, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 539", "hex_opcode": "0x7C000436", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "539", "clean": "539" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "RS", "desc": "Source" }, { "name": "RB", "desc": "Shift Reg" } ], "extension": "Base", "description": "Logically shifts RS right by the number of bit positions specified in RB (bits 57-63), inserting zeros at the left. If RB ≥ 64, the result is zero. No status registers are affected.", "pseudocode": "n ← RB[57:63]\nif n < 64 then RA ← RS >> n\nelse RA ← 0", "page_found": "Page 1145", "special_registers": "MSR", "programming_notes": "The srd instruction is used to update the Machine State Register (MSR) based on the contents of a source register and the L field. When L=0, specific bits in the MSR are updated using logical operations involving bits from the source register and the current MSR state. When L=1, only bits 48 and 62 of the MSR are set to match those in the source register, while other bits remain unchanged. This instruction requires supervisor privilege level and can trigger exceptions if not executed properly.", "example": "srd r4, r3, r5" }, { "mnemonic": "srad", "architecture": "PowerISA", "full_name": "Shift Right Algebraic Doubleword", "summary": "Arithmetic right shift of 64-bit value (preserves sign).", "syntax": "srad RA, RS, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 794", "hex_opcode": "0x7C000634", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "794", "clean": "794" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "RS", "desc": "Source" }, { "name": "RB", "desc": "Shift Reg" } ], "extension": "Base", "description": "Arithmetically shifts RS right by the number of bit positions specified in RB (bits 57-63), preserving the sign bit (bit 0) and shifting in sign-extended bits. If RB ≥ 64, the result is all 0s or all 1s depending on sign. The XER[CA] carry bit is set if any 1-bits are shifted out from a negative number.", "pseudocode": "n ← RB[57:63]\nif n < 64 then\n RA ← RS >>a n\n XER[CA] ← 1 if (RS < 0 & (RS & MASK(64-n, 63)) ≠ 0) else 0\nelse\n if RS < 0 then RA ← -1; XER[CA] ← 1\n else RA ← 0; XER[CA] ← 0", "page_found": "Page 151", "programming_notes": "The srad instruction is commonly used for right-shifting signed integers while preserving the sign bit. Be cautious with shift amounts of 32 or more, as they result in a full sign extension and clear the carry bits. Ensure that the input register RS contains valid data and that RB's upper 8 bits specify a valid shift amount (0-63).", "example": "srad r4, r3, r5" }, { "mnemonic": "sradi", "architecture": "PowerISA", "full_name": "Shift Right Algebraic Doubleword Immediate", "summary": "Performs an arithmetic right shift on a 64-bit doubleword by a constant amount.", "syntax": "sradi RA, RS, SH", "encoding": { "format": "XS-form", "binary_pattern": "31 | RS | RA | SH | 413 | Rc", "hex_opcode": "0x7C000674", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "SH", "clean": "SH" }, { "raw": "413", "clean": "413" }, { "raw": "Rc", "clean": "Rc" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target Register" }, { "name": "RS", "desc": "Source Register" }, { "name": "SH", "desc": "Shift Amount (0-63, Split field)" } ], "pseudocode": "n ← SH\nRA ← RS >>a n\nif RS < 0 & (RS & MASK(64-n, 63)) ≠ 0 then XER[CA] ← 1\nelse XER[CA] ← 0\nif Rc = 1 then CR0 ← (RA < 0, RA > 0, RA = 0, SO)", "example": "sradi r3, r4, 10", "example_note": "r3 = r4 >> 10 (Signed 64-bit).", "extension": "Base", "description": "Arithmetically shifts RS right by SH bit positions (0-63), preserving the sign bit and shifting in sign-extended bits. Sets XER[CA] if any 1-bits are shifted out from a negative number. The condition register CR0 is updated if Rc=1.", "page_found": "Page 151", "special_registers": "CR0", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER." }, { "mnemonic": "lhbrx", "architecture": "PowerISA", "full_name": "Load Halfword Byte-Reverse Indexed", "summary": "Loads a halfword from memory, byte-reverses it, and stores it in a register.", "syntax": "lhbrx RT, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | RA | RB | 790 | /", "hex_opcode": "0x7C00062C", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "790", "clean": "790" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Base", "description": "Loads a halfword from memory at address (RA|0) + RB, byte-reverses it, and stores the result in RT. No status flags are affected. This is part of the Base category and is commonly used for endianness conversion when reading network or file data.", "pseudocode": "EA ← (RA|0) + RB\nRT ← byte_reverse_16([EA])", "programming_notes": "These instructions have the effect of loading and storing data in the opposite byte ordering from that which would be used by other Load and Store instructions.", "page_found": "Page 100 - 102", "example": "lhbrx r3, r4, r5" }, { "mnemonic": "lwbrx", "architecture": "PowerISA", "full_name": "Load Word Byte-Reverse Indexed", "summary": "Loads a word and swaps bytes.", "syntax": "lwbrx RT, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | RA | RB | 534 | /", "hex_opcode": "0x7C00042C", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "534", "clean": "534" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Base", "description": "Loads a word (32-bit value) from memory at address (RA|0) + RB, byte-reverses it, and stores the result in RT. No status flags are affected. This instruction is used for converting word-sized data between big-endian and little-endian formats.", "pseudocode": "EA ← (RA|0) + RB\nRT ← byte_reverse_32([EA])", "page_found": "Page 102", "programming_notes": "The lwbrx instruction is commonly used to load a word from memory and reverse its byte order, which can be useful for handling data in big-endian or little-endian formats. Ensure that the base address (RA) and index (RB) registers are correctly set to avoid incorrect memory access. This instruction operates at user privilege level and will raise an exception if it accesses invalid memory addresses.", "example": "lwbrx r3, r4, r5" }, { "mnemonic": "sthbrx", "architecture": "PowerISA", "full_name": "Store Halfword Byte-Reverse Indexed", "summary": "Swaps bytes and stores a halfword.", "syntax": "sthbrx RS, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 918 | /", "hex_opcode": "0x7C00072C", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "918", "clean": "918" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RS", "desc": "Source" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Base", "description": "Byte-reverses the low 16 bits of RS and stores the result as a halfword in memory at address (RA|0) + RB. No status flags are affected. This is used to write halfword data in reversed byte order to memory.", "pseudocode": "EA ← (RA|0) + RB\n[EA] ← byte_reverse_16(RS[48:63])", "page_found": "Page 102", "programming_notes": "The sthbrx instruction is useful for storing a halfword in memory with byte-reversed order. Ensure that the base address register (RA) and index register (RB) are correctly set to avoid incorrect memory addresses. This instruction operates at user privilege level and will raise an exception if the effective address is out of bounds or if there is a protection fault.", "example": "sthbrx r3, r4, r5" }, { "mnemonic": "stwbrx", "architecture": "PowerISA", "full_name": "Store Word Byte-Reverse Indexed", "summary": "Swaps bytes and stores a word.", "syntax": "stwbrx RS, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 662 | /", "hex_opcode": "0x7C00052C", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "662", "clean": "662" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RS", "desc": "Source" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Base", "description": "Byte-reverses the low 32 bits of RS and stores the result as a word in memory at address (RA|0) + RB. No status flags are affected. This instruction is used for writing word-sized data in reversed byte order.", "pseudocode": "EA ← (RA|0) + RB\n[EA] ← byte_reverse_32(RS[32:63])", "page_found": "Page 102", "programming_notes": "The stwbrx instruction is useful for storing a word in memory with its byte order reversed, which can be necessary for compatibility with systems that use different endianness. Ensure that the effective address (EA) calculated from registers RA and RB is properly aligned to avoid alignment exceptions. This instruction operates at user privilege level but will raise an exception if the EA is out of bounds or if there are insufficient permissions.", "example": "stwbrx r3, r4, r5" }, { "mnemonic": "ldbrx", "architecture": "PowerISA", "full_name": "Load Doubleword Byte-Reverse Indexed", "summary": "Loads a doubleword from memory, byte-reversing it before storing in the target register.", "syntax": "ldbrx RT, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | RA | RB | 532 | /", "hex_opcode": "0x7C000428", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "532", "clean": "532" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Base", "description": "Loads a doubleword (64-bit value) from memory at address (RA|0) + RB, byte-reverses it, and stores the result in RT. No status flags are affected. This is used for converting doubleword data between big-endian and little-endian byte orders.", "pseudocode": "EA ← (RA|0) + RB\nRT ← byte_reverse_64([EA])", "page_found": "Page 102 - 104", "programming_notes": "The ldbrx instruction is commonly used for loading and reversing the byte order of a doubleword from memory into a register. Ensure that the base address in RA (or 0 if using an absolute address) and the offset in RB are correctly set to avoid accessing invalid memory locations. This instruction operates at user privilege level, but care must be taken to handle potential exceptions such as alignment errors or access violations. Performance may vary depending on memory alignment; optimal performance is achieved when the effective address is 8-byte aligned.", "example": "ldbrx r3, r4, r5" }, { "mnemonic": "stdbrx", "architecture": "PowerISA", "full_name": "Store Doubleword Byte-Reverse Indexed", "summary": "Swaps bytes and stores 64 bits.", "syntax": "stdbrx RS, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 660 | /", "hex_opcode": "0x7C000528", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "660", "clean": "660" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RS", "desc": "Source" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Base", "description": "Byte-reverses all 64 bits of RS and stores the result as a doubleword in memory at address (RA|0) + RB. No status flags are affected. This instruction is used to write doubleword data in reversed byte order to memory.", "pseudocode": "EA ← (RA|0) + RB\n[EA] ← byte_reverse_64(RS)", "page_found": "Page 103", "programming_notes": "The stdbrx instruction is useful for storing a doubleword in memory with byte-reversed order. Ensure that the source register RS contains the data to be stored, and registers RA and RB are correctly set to calculate the effective address. This instruction operates at user privilege level and may raise an exception if there's a memory access violation.", "example": "stdbrx r3, r4, r5" }, { "mnemonic": "stwcx.", "architecture": "PowerISA", "full_name": "Store Word Conditional Indexed", "summary": "Stores a word from a register to memory if the reservation is valid and matches the address used in the corresponding lwarx instruction.", "syntax": "stwcx. RS, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 150 | 1", "hex_opcode": "0x7C00012D", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "150", "clean": "150" }, { "raw": "1", "clean": "1" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RS", "desc": "Source" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Base", "description": "The stwcx. instruction stores the upper half of the contents of register RS into memory at the effective address (EA) formed by adding the contents of registers RA and RB, provided that a reservation exists for this EA and the reservation length is 4 bytes. If the reservation does not exist or the conditions are not met, no store is performed.", "pseudocode": "if RA = 0 then\n b ← 0\nelse\n b ← (RA)\nEA ← b + (RB)\nif RESERVE then\n if RESERVE_LENGTH = 4 &\n RESERVE_ADDR = real_addr(EA) then\n MEM(EA, 4) ← (RS)32:63\n undefined_case ← 0\n store_performed ← 1\n else\n z ← smallest real page size supported by implementation\n if RESERVE_ADDR ÷ z = real_addr(EA) ÷ z then\n undefined_case ← 1\n else\n undefined_case ← 0\n store_performed ← 0\nelse\n undefined_case ← 0\n store_performed ← 0\nif undefined_case then\n u1 ← undefined 1-bit value\n if u1 then\n MEM(EA, 4) ← (RS)32:63\n u2 ← undefined 1-bit value\n CR0 ← 0b00 || u2 || XERSO\nelse\n CR0 ← 0b00 || store_performed || XERSO\nRESERVE ← 0", "special_registers": "CR0, XER", "page_found": "Page 1055 - 1056", "programming_notes": "Succeeds only if a valid reservation exists on the target address. Sets CR0[EQ] to 1 on success, 0 on failure. Must always be used in a retry loop that re-executes the load-reserve instruction on failure.", "example": "stwcx. r3, r4, r5" }, { "mnemonic": "stdcx.", "architecture": "PowerISA", "full_name": "Store Doubleword Conditional Indexed", "summary": "Stores a doubleword from a register to memory if the reservation is valid and matches the address used for the reservation.", "syntax": "stdcx. RS, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 214 | 1", "hex_opcode": "0x7C0001AD", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "214", "clean": "214" }, { "raw": "1", "clean": "1" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RS", "desc": "Source" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Base", "description": "The stdcx. instruction stores the contents of register RS into memory at the effective address (EA) calculated as the sum of registers RA and RB, but only if there is a valid reservation that matches this EA and has a length of 8 bytes. The reservation is cleared after the operation.", "pseudocode": "if RA = 0 then\n b ← 0\nelse\n b ← (RA)\nEA ← b + (RB)\nif RESERVE then\n if RESERVE_LENGTH = 8 &\n RESERVE_ADDR = real_addr(EA) then\n MEM(EA, 8) ← (RS)\n undefined_case ← 0\n store_performed ← 1\n else\n z ← smallest real page size supported by implementation\n if RESERVE_ADDR ÷ z = real_addr(EA) ÷ z then\n undefined_case ← 1\n else\n undefined_case ← 0\n store_performed ← 0\nelse\n undefined_case ← 0\n store_performed ← 0\nif undefined_case then\n u1 ← undefined 1-bit value\n if u1 then\n MEM(EA, 8) ← (RS)\n u2 ← undefined 1-bit value\n CR0 ← 0b00 || u2 || XERSO\nelse\n CR0 ← 0b00 || store_performed || XERSO\nRESERVE ← 0", "special_registers": "CR0, XER", "page_found": "Page 1057 - 1058", "programming_notes": "Succeeds only if a valid reservation exists on the target address. Sets CR0[EQ] to 1 on success, 0 on failure. Must always be used in a retry loop that re-executes the load-reserve instruction on failure.", "example": "stdcx. r3, r4, r5" }, { "mnemonic": "tw", "architecture": "PowerISA", "full_name": "Trap Word", "summary": "Traps if condition (comparison of words) is met.", "syntax": "tw TO, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | TO | RA | RB | 4", "hex_opcode": "0x7C000008", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "TO", "clean": "TO" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "4", "clean": "4" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "TO", "desc": "Options" }, { "name": "RA", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Base", "description": "Compares the 32-bit signed values in RA and RB according to the trap condition bits in TO. If the condition is true, a program interrupt (trap) is generated; otherwise execution continues. The TO field encodes up to five independent comparison conditions (less-than, greater-than, equal, unsigned less-than, unsigned greater-than).", "pseudocode": "if (TO[0] & (RA s RB)) | (TO[2] & (RA = RB)) | (TO[3] & (RA u RB)) then\n Trap_Exception ← 1\nelse\n Trap_Exception ← 0", "page_found": "Page 130", "special_registers": "CR0, CR1, CR6", "programming_notes": "Generates a program exception (System Call or Trap type) when the trap condition is true. The condition codes in TO select which comparisons trigger the trap: bit 0 = LT, bit 1 = GT, bit 2 = EQ, bit 3 = LU (unsigned), bit 4 = GU (unsigned). TO=31 (all bits set) always traps.", "example": "tw 4, r4, r5" }, { "mnemonic": "twi", "architecture": "PowerISA", "full_name": "Trap Word Immediate", "summary": "Compares the contents of register RA with an immediate value and invokes the system trap handler if any specified condition is met.", "syntax": "twi TO, RA, SIM", "encoding": { "format": "D-form", "binary_pattern": "3 | TO | RA | SI", "hex_opcode": "0x0C000000", "visual_parts": [ { "raw": "3", "clean": "3" }, { "raw": "TO", "clean": "TO" }, { "raw": "RA", "clean": "RA" }, { "raw": "SIM", "clean": "SIM" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "operands": [ { "name": "TO", "desc": "Options" }, { "name": "RA", "desc": "Src" }, { "name": "SIM", "desc": "Imm" }, { "name": "SI", "desc": "Sign-Extended Immediate Value" }, { "name": "CRb", "desc": "Condition Register Field" }, { "name": "L", "desc": "Link Bit" }, { "name": "Ra", "desc": "Source General Purpose Register" }, { "name": "SIm", "desc": "Immediate Value" }, { "name": "LK", "desc": "Link Bit" } ], "extension": "Base", "description": "The contents of register RA are compared with the sign-extended value of the SI field. If any bit in the TO field is set to 1 and its corresponding condition is met by the result of the comparison, the system trap handler is invoked.", "pseudocode": "a ← EXTS((RA)32:63)\nif (a < EXTS(SI)) & TO0 then TRAP\nif (a > EXTS(SI)) & TO1 then TRAP\nif (a = EXTS(SI)) & TO2 then TRAP\nif (a u EXTS(SI)) & TO4 then TRAP", "extended_mnemonics": [ { "mnemonic": "tweq", "equivalent_to": "twi 4,RA,RB" }, { "mnemonic": "twgti", "equivalent_to": "twi 8,RA,SI" }, { "mnemonic": "twllei", "equivalent_to": "twi 6,RA,SI" } ], "page_found": "Page 129 - 130", "special_registers": "CR0, XER", "programming_notes": "Generates a program exception (System Call or Trap type) when the trap condition is true. The condition codes in TO select which comparisons trigger the trap: bit 0 = LT, bit 1 = GT, bit 2 = EQ, bit 3 = LU (unsigned), bit 4 = GU (unsigned). TO=31 (all bits set) always traps.", "example": "twi 4, r4, 4" }, { "mnemonic": "td", "architecture": "PowerISA", "full_name": "Trap Doubleword", "summary": "Traps if condition (comparison of doublewords) is met.", "syntax": "td TO, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | TO | RA | RB | 68", "hex_opcode": "0x7C000088", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "TO", "clean": "TO" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "68", "clean": "68" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "TO", "desc": "Options" }, { "name": "RA", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Base", "description": "Compares the 64-bit signed values in RA and RB according to the trap condition bits in TO. If the condition is true, a program interrupt (trap) is generated; otherwise execution continues. The TO field encodes five independent doubleword comparison conditions (less-than, greater-than, equal, unsigned less-than, unsigned greater-than).", "pseudocode": "if (TO[0] & (RA s RB)) | (TO[2] & (RA = RB)) | (TO[3] & (RA u RB)) then\n Trap_Exception ← 1\nelse\n Trap_Exception ← 0", "programming_notes": "Generates a program exception (System Call or Trap type) when the trap condition is true. The condition codes in TO select which comparisons trigger the trap: bit 0 = LT, bit 1 = GT, bit 2 = EQ, bit 3 = LU (unsigned), bit 4 = GU (unsigned). TO=31 (all bits set) always traps.", "example": "td 4, r4, r5" }, { "mnemonic": "tdi", "architecture": "PowerISA", "full_name": "Trap Doubleword Immediate", "summary": "Compares the contents of a register with an immediate value and invokes a trap handler if specified conditions are met.", "syntax": "tdi TO, RA, SIM", "encoding": { "format": "D-form", "binary_pattern": "000010 | CRb | RA | SIMM", "hex_opcode": "0x08000000", "visual_parts": [ { "raw": "2", "clean": "2" }, { "raw": "TO", "clean": "TO" }, { "raw": "RA", "clean": "RA" }, { "raw": "SIM", "clean": "SIM" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "TO", "desc": "Options" }, { "name": "RA", "desc": "Src" }, { "name": "SIM", "desc": "Imm" }, { "name": "SI", "desc": "Sign-Extended Immediate Value" }, { "name": "CRb", "desc": "Condition Register Field" }, { "name": "SIMM", "desc": "Signed Immediate Value" } ], "extension": "Base", "description": "The contents of register RA are compared with the sign-extended value of the SI field. If any bit in the TO field is set to 1 and its corresponding condition is met by the result of the comparison, the system trap handler is invoked.", "pseudocode": "a ← (RA)\nb ← EXTS(SI)\nif (a < b) & TO0 then TRAP\nif (a > b) & TO1 then TRAP\nif (a = b) & TO2 then TRAP\nif (a u b) & TO4 then TRAP", "extended_mnemonics": [ { "mnemonic": "tdge", "equivalent_to": "td 12,RA,RB" }, { "mnemonic": "tdlnl", "equivalent_to": "td 5,RA,RB tdlti RA,SI" }, { "mnemonic": "tdnei", "equivalent_to": "tdi 24,RA,SI" } ], "page_found": "Page 130 - 132", "special_registers": "CRb, XER", "programming_notes": "Generates a program exception (System Call or Trap type) when the trap condition is true. The condition codes in TO select which comparisons trigger the trap: bit 0 = LT, bit 1 = GT, bit 2 = EQ, bit 3 = LU (unsigned), bit 4 = GU (unsigned). TO=31 (all bits set) always traps.", "example": "tdi 4, r4, 4" }, { "mnemonic": "extsb", "architecture": "PowerISA", "full_name": "Extend Sign Byte", "summary": "Sign extends the low byte of a register to the full width.", "syntax": "extsb RT,RS", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | 954 | /", "hex_opcode": "0x7C000774", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "954", "clean": "954" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "RS", "desc": "Source" }, { "name": "RT", "desc": "Target General Purpose Register" } ], "extension": "Base", "description": "The contents of the specified byte (RS)56 are placed into RA56:63, and RA0:55 are filled with a copy of (RS)56.", "pseudocode": "if 'extsb' then\n s ← (RS)56\n RA56:63 ← (RS)56:63\n RA0:55 ← 56s\nelse if 'extsb.' then\n s ← (RS)56\n RA56:63 ← (RS)56:63\n RA0:55 ← 56s", "special_registers": "CR0, XER", "page_found": "Page 136 - 138", "programming_notes": "The extsb instruction is commonly used to sign-extend a byte value into a full word. Ensure the source register contains the correct byte to avoid unexpected results. This instruction operates at user privilege level and does not generate exceptions under normal conditions.", "example": "extsb r3, r3" }, { "mnemonic": "extsh", "architecture": "PowerISA", "full_name": "Extend Sign Halfword", "summary": "Sign extends the low halfword.", "syntax": "extsh RA, RS", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | 922 | /", "hex_opcode": "0x7C000734", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "922", "clean": "922" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "RS", "desc": "Source" } ], "extension": "Base", "description": "Sign-extends the low 16 bits (halfword) of the source register to fill all 64 bits of the destination register. The instruction replicates bit 15 of RS to all higher-order bits. No condition registers or status fields are affected unless an extended form with a recorded bit is used (extsH.).", "pseudocode": "RA ← EXTS(RS[48:63], 64)", "page_found": "Page 137", "programming_notes": "The extsh instruction is commonly used to sign-extend a halfword value from the source register into the destination register. Ensure that the source register contains a valid halfword value, and be aware that this operation affects the entire 64-bit destination register. This instruction operates at user privilege level and does not generate exceptions under normal circumstances.", "example": "extsh r4, r3" }, { "mnemonic": "extsw", "architecture": "PowerISA", "full_name": "Extend Sign Word", "summary": "Sign extends the low word (32-bit) to 64 bits.", "syntax": "extsw RT,RS", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | 986 | /", "hex_opcode": "0x7C0007B4", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "986", "clean": "986" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "RS", "desc": "Source" }, { "name": "RT", "desc": "Target General Purpose Register" } ], "extension": "Base", "description": "The contents of register RS are extended to fill the upper 32 bits of register RA, and the lower 32 bits of RA are filled with a copy of the upper 32 bits of RS.", "pseudocode": "if 'extsw' then\n s ← (RS)32\n RA32:63 ← (RS)32:63\n RA0:31 ← 32s\nelse if 'extsw.' then\n s ← (RS)32\n RA32:63 ← (RS)32:63\n RA0:31 ← 32s", "special_registers": "CR0, XER", "page_found": "Page 138 - 140", "programming_notes": "The extsw instruction is commonly used to sign-extend a 32-bit value in RS to a 64-bit value in RA. Ensure that the source register RS contains the correct 32-bit signed integer to avoid unexpected results. This instruction operates at user privilege level and does not generate exceptions under normal circumstances.", "example": "extsw r3, r3" }, { "mnemonic": "eqv", "architecture": "PowerISA", "full_name": "Equivalent", "summary": "Bitwise Equivalence (XNOR). RA = ~(RS ^ RB).", "syntax": "eqv RA, RS, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 284 | /", "hex_opcode": "0x7C000238", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "284", "clean": "284" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "RS", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Base", "description": "Performs a bitwise equivalence (XNOR) operation: RA ← ~(RS XOR RB). Each bit position in RA is set to 1 if the corresponding bits in RS and RB are equal, 0 otherwise. No condition registers or status fields are affected unless an extended form with a recorded bit is used (eqv.).", "pseudocode": "RA ← ~(RS ^ RB)", "page_found": "Page 136", "programming_notes": "The eqv instruction is useful for performing bitwise equivalence operations, which can be applied in various logic and data manipulation tasks. Ensure that the input registers RS and RB are correctly aligned and contain the expected data to avoid unexpected results. This instruction operates at user privilege level and does not generate exceptions under normal conditions.", "example": "eqv r4, r3, r5" }, { "mnemonic": "nand", "architecture": "PowerISA", "full_name": "NAND", "summary": "Bitwise NAND. RA = ~(RS & RB).", "syntax": "nand RA, RS, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 476 | /", "hex_opcode": "0x7C0003B8", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "476", "clean": "476" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "RS", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Base", "description": "Performs a bitwise NAND operation: RA ← ~(RS AND RB). Each bit position in RA is set to 1 if the corresponding bits in RS and RB are not both 1, 0 otherwise. No condition registers or status fields are affected unless an extended form with a recorded bit is used (nand.).", "pseudocode": "RA ← ~(RS & RB)", "page_found": "Page 79", "special_registers": "CR", "programming_notes": "The crnand instruction is useful for performing bitwise NAND operations on specific bits within the Condition Register. Ensure that the bit positions specified by BA, BB, and BT are valid to avoid undefined behavior. This instruction operates at user privilege level and does not generate exceptions under normal conditions.", "example": "nand r4, r3, r5" }, { "mnemonic": "nor", "architecture": "PowerISA", "full_name": "NOR", "summary": "Bitwise NOR. RA = ~(RS | RB).", "syntax": "nor RA, RS, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 124 | /", "hex_opcode": "0x7C0000F8", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "124", "clean": "124" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "RS", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Base", "description": "Performs a bitwise NOR operation: RA ← ~(RS OR RB). Each bit position in RA is set to 1 if the corresponding bits in RS and RB are both 0, 0 otherwise. No condition registers or status fields are affected unless an extended form with a recorded bit is used (nor.).", "pseudocode": "RA ← ~(RS | RB)", "page_found": "Page 1037", "programming_notes": "The nor instruction performs a bitwise NOR of registers RS and RB and places the result in RA. Coding RB the same as RS forms the extended mnemonic not RA,RS, the standard way to complement a register. This instruction operates at user privilege level.", "example": "nor r4, r3, r5" }, { "mnemonic": "orc", "architecture": "PowerISA", "full_name": "OR with Complement", "summary": "Performs a bitwise OR operation between the contents of two registers and the complement of the third register.", "syntax": "orc RA,RS,RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 412 | /", "hex_opcode": "0x7C000338", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "412", "clean": "412" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "RS", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Base", "description": "The contents of register RS are ORed with the complement of the contents of register RB, and the result is placed into register RA.", "pseudocode": "if 'orc' then\n RA <- (RS) | ¬(RB)\nelse if 'orc.' then\n RA <- (RS) | ¬(RB)\n CR0 <- result of OR operation", "special_registers": "CR0", "page_found": "Page 135 - 136", "programming_notes": "The orc instruction is useful for setting bits in a register based on the complement of another register. Be cautious with bit manipulation as incorrect usage can lead to unexpected results. The instruction operates at user privilege level and does not generate exceptions under normal conditions. Performance may vary depending on the specific implementation and architecture.", "example": "orc r4, r3, r5" }, { "mnemonic": "macchw", "architecture": "PowerISA", "full_name": "Multiply Accumulate Cross Halfword", "summary": "Multiply bottom half of RA by top half of RB, add to RT.", "syntax": "macchw RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "4 | RT | RA | RB | 172 | 0", "hex_opcode": "0x10000158", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "172", "clean": "172" }, { "raw": "0", "clean": "0" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Acc/Dest" }, { "name": "RA", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Embedded", "description": "Multiplies the low halfword (bits 48-63) of RA by the high halfword (bits 0-15) of RB and adds the signed 32-bit product to the low 32 bits of RT, placing the result back in the low 32 bits of RT. This is part of the embedded (e200/e500) category. The instruction does not affect condition registers or XER unless an extended variant is used.", "pseudocode": "prod ← EXTS(RA[48:63], 32) * EXTS(RB[0:15], 32); RT[32:63] ← RT[32:63] + prod[0:31]", "example": "macchw r3, r4, r5" }, { "mnemonic": "macchws", "architecture": "PowerISA", "full_name": "Multiply Accumulate Cross Halfword Signed", "summary": "Signed Multiply Accumulate Cross Halfword with Saturation.", "syntax": "macchws RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "4 | RT | RA | RB | 236 | 0", "hex_opcode": "0x100001D8", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "236", "clean": "236" }, { "raw": "0", "clean": "0" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Acc/Dest" }, { "name": "RA", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Embedded", "description": "Signed multiply-accumulate of the low halfword of RA by the high halfword of RB, added to RT with saturation. The signed 32-bit product is added to the low 32 bits of RT; if overflow occurs, the result is saturated to the signed 32-bit range. This is an embedded (e200/e500) instruction. The SAT bit in XER is set if saturation occurs; other condition registers are not affected.", "pseudocode": "prod ← EXTS(RA[48:63], 32) * EXTS(RB[0:15], 32); sum ← EXTS(RT[32:63], 33) + EXTS(prod, 33); if (sum > 2^31 - 1) then { RT[32:63] ← 2^31 - 1; XER[SAT] ← 1 } else if (sum < -2^31) then { RT[32:63] ← -2^31; XER[SAT] ← 1 } else { RT[32:63] ← sum[0:31] }", "example": "macchws r3, r4, r5" }, { "mnemonic": "macchwu", "architecture": "PowerISA", "full_name": "Multiply Accumulate Cross Halfword Unsigned", "summary": "Unsigned Multiply Accumulate Cross Halfword.", "syntax": "macchwu RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "4 | RT | RA | RB | 12 | 0", "hex_opcode": "0x10000118", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "12", "clean": "12" }, { "raw": "0", "clean": "0" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Acc/Dest" }, { "name": "RA", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Embedded", "description": "Unsigned multiply-accumulate of the low halfword of RA by the high halfword of RB, added to RT. The unsigned 32-bit product is added to the low 32 bits of RT, with wraparound on overflow. This is an embedded (e200/e500) instruction. No condition registers or XER fields are affected.", "pseudocode": "prod ← EXTZ(RA[48:63], 32) * EXTZ(RB[0:15], 32); RT[32:63] ← (RT[32:63] + prod[0:31]) mod 2^32", "example": "macchwu r3, r4, r5" }, { "mnemonic": "macchwsu", "architecture": "PowerISA", "full_name": "Multiply Accumulate Cross Halfword Signed Unsigned", "summary": "Mixed Sign Multiply Accumulate Cross Halfword with Saturation.", "syntax": "macchwsu RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "4 | RT | RA | RB | 204 | 0", "hex_opcode": "0x10000198", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "204", "clean": "204" }, { "raw": "0", "clean": "0" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Acc/Dest" }, { "name": "RA", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Embedded", "description": "Mixed-sign multiply-accumulate of the signed low halfword of RA by the unsigned high halfword of RB, added to RT with saturation. The signed 32-bit product is added to the low 32 bits of RT; if overflow occurs, the result is saturated to the signed 32-bit range. This is an embedded (e200/e500) instruction. The SAT bit in XER is set if saturation occurs.", "pseudocode": "prod ← EXTS(RA[48:63], 32) * EXTZ(RB[0:15], 32); sum ← EXTS(RT[32:63], 33) + EXTS(prod, 33); if (sum > 2^31 - 1) then { RT[32:63] ← 2^31 - 1; XER[SAT] ← 1 } else if (sum < -2^31) then { RT[32:63] ← -2^31; XER[SAT] ← 1 } else { RT[32:63] ← sum[0:31] }", "example": "macchwsu r3, r4, r5" }, { "mnemonic": "machhw", "architecture": "PowerISA", "full_name": "Multiply Accumulate High Halfword", "summary": "Multiply top half of RA by top half of RB, add to RT.", "syntax": "machhw RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "4 | RT | RA | RB | 44 | 0", "hex_opcode": "0x10000058", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "44", "clean": "44" }, { "raw": "0", "clean": "0" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Acc/Dest" }, { "name": "RA", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Embedded", "description": "Multiplies the high halfword (bits 0-15) of RA by the high halfword of RB as signed integers, then adds the 32-bit product to RT and stores the result in RT. This is part of the Embedded (SPE) category and does not affect any condition or status registers.", "pseudocode": "product ← EXTS(RA[0:15]) × EXTS(RB[0:15])\nRT ← RT + product", "example": "machhw r3, r4, r5" }, { "mnemonic": "machhws", "architecture": "PowerISA", "full_name": "Multiply Accumulate High Halfword Signed", "summary": "Signed Multiply Accumulate High Halfword with Saturation.", "syntax": "machhws RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "4 | RT | RA | RB | 108 | 0", "hex_opcode": "0x100000D8", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "108", "clean": "108" }, { "raw": "0", "clean": "0" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Acc/Dest" }, { "name": "RA", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Embedded", "description": "Multiplies the high halfword (bits 0-15) of RA by the high halfword of RB as signed integers, adds the 32-bit product to RT, and saturates the result to the signed 32-bit range if overflow occurs. This is part of the Embedded (SPE) category and sets the SAT bit in the SPEFSCR if saturation occurs.", "pseudocode": "product ← EXTS(RA[0:15]) × EXTS(RB[0:15])\nresult ← RT + product\nif result > 2147483647 then\n RT ← 2147483647\n SPEFSCR[SAT] ← 1\nelif result < -2147483648 then\n RT ← -2147483648\n SPEFSCR[SAT] ← 1\nelse\n RT ← result", "example": "machhws r3, r4, r5" }, { "mnemonic": "machhwu", "architecture": "PowerISA", "full_name": "Multiply Accumulate High Halfword Unsigned", "summary": "Unsigned Multiply Accumulate High Halfword.", "syntax": "machhwu RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "4 | RT | RA | RB | 12 | 0", "hex_opcode": "0x10000018", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "12", "clean": "12" }, { "raw": "0", "clean": "0" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Acc/Dest" }, { "name": "RA", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Embedded", "description": "Multiplies the high halfword (bits 0-15) of RA by the high halfword of RB as unsigned integers, then adds the 32-bit product to RT and stores the result in RT. This is part of the Embedded (SPE) category and does not affect any condition or status registers.", "pseudocode": "product ← EXTZ(RA[0:15]) × EXTZ(RB[0:15])\nRT ← RT + product", "example": "machhwu r3, r4, r5" }, { "mnemonic": "machhwsu", "architecture": "PowerISA", "full_name": "Multiply Accumulate High Halfword Signed Unsigned", "summary": "Mixed Sign Multiply Accumulate High Halfword with Saturation.", "syntax": "machhwsu RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "4 | RT | RA | RB | 76 | 0", "hex_opcode": "0x10000098", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "76", "clean": "76" }, { "raw": "0", "clean": "0" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Acc/Dest" }, { "name": "RA", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Embedded", "description": "Multiplies the high halfword (bits 0-15) of RA (signed) by the high halfword of RB (unsigned), adds the 32-bit product to RT, and saturates the result to the signed 32-bit range if overflow occurs. This is part of the Embedded (SPE) category and sets the SAT bit in SPEFSCR if saturation occurs.", "pseudocode": "product ← EXTS(RA[0:15]) × EXTZ(RB[0:15])\nresult ← RT + product\nif result > 2147483647 then\n RT ← 2147483647\n SPEFSCR[SAT] ← 1\nelif result < -2147483648 then\n RT ← -2147483648\n SPEFSCR[SAT] ← 1\nelse\n RT ← result", "example": "machhwsu r3, r4, r5" }, { "mnemonic": "maclhw", "architecture": "PowerISA", "full_name": "Multiply Accumulate Low Halfword", "summary": "Multiply bottom half of RA by bottom half of RB, add to RT.", "syntax": "maclhw RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "4 | RT | RA | RB | 428 | 0", "hex_opcode": "0x10000358", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "428", "clean": "428" }, { "raw": "0", "clean": "0" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Acc/Dest" }, { "name": "RA", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Embedded", "description": "Multiplies the low halfword (bits 16-31) of RA by the low halfword of RB as signed integers, then adds the 32-bit product to RT and stores the result in RT. This is part of the Embedded (SPE) category and does not affect any condition or status registers.", "pseudocode": "product ← EXTS(RA[16:31]) × EXTS(RB[16:31])\nRT ← RT + product", "example": "maclhw r3, r4, r5" }, { "mnemonic": "maclhws", "architecture": "PowerISA", "full_name": "Multiply Accumulate Low Halfword Signed", "summary": "Signed Multiply Accumulate Low Halfword with Saturation.", "syntax": "maclhws RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "4 | RT | RA | RB | 492 | 0", "hex_opcode": "0x100003D8", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "492", "clean": "492" }, { "raw": "0", "clean": "0" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Acc/Dest" }, { "name": "RA", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Embedded", "description": "Multiplies the low halfword (bits 16-31) of RA by the low halfword of RB as signed integers, adds the 32-bit product to RT, and saturates the result to the signed 32-bit range if overflow occurs. This is part of the Embedded (SPE) category and sets the SAT bit in SPEFSCR if saturation occurs.", "pseudocode": "product ← EXTS(RA[16:31]) × EXTS(RB[16:31])\nresult ← RT + product\nif result > 2147483647 then\n RT ← 2147483647\n SPEFSCR[SAT] ← 1\nelif result < -2147483648 then\n RT ← -2147483648\n SPEFSCR[SAT] ← 1\nelse\n RT ← result", "example": "maclhws r3, r4, r5" }, { "mnemonic": "maclhwu", "architecture": "PowerISA", "full_name": "Multiply Accumulate Low Halfword Unsigned", "summary": "Unsigned Multiply Accumulate Low Halfword.", "syntax": "maclhwu RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "4 | RT | RA | RB | 396 | 0", "hex_opcode": "0x10000318", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "396", "clean": "396" }, { "raw": "0", "clean": "0" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Acc/Dest" }, { "name": "RA", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Embedded", "description": "Multiplies the low halfword (bits 16-31) of RA by the low halfword of RB as unsigned integers, then adds the 32-bit product to RT and stores the result in RT. This is part of the Embedded (SPE) category and does not affect any condition or status registers.", "pseudocode": "product ← EXTZ(RA[16:31]) × EXTZ(RB[16:31])\nRT ← RT + product", "example": "maclhwu r3, r4, r5" }, { "mnemonic": "maclhwsu", "architecture": "PowerISA", "full_name": "Multiply Accumulate Low Halfword Signed Unsigned", "summary": "Mixed Sign Multiply Accumulate Low Halfword with Saturation.", "syntax": "maclhwsu RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "4 | RT | RA | RB | 460 | 0", "hex_opcode": "0x10000398", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "460", "clean": "460" }, { "raw": "0", "clean": "0" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Acc/Dest" }, { "name": "RA", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Embedded", "description": "Multiplies the low halfword (bits 16-31) of RA (signed) by the low halfword of RB (unsigned), adds the 32-bit product to RT, and saturates the result to the signed 32-bit range if overflow occurs. This is part of the Embedded (SPE) category and sets the SAT bit in SPEFSCR if saturation occurs.", "pseudocode": "product ← EXTS(RA[16:31]) × EXTZ(RB[16:31])\nresult ← RT + product\nif result > 2147483647 then\n RT ← 2147483647\n SPEFSCR[SAT] ← 1\nelif result < -2147483648 then\n RT ← -2147483648\n SPEFSCR[SAT] ← 1\nelse\n RT ← result", "example": "maclhwsu r3, r4, r5" }, { "mnemonic": "mulchw", "architecture": "PowerISA", "full_name": "Multiply Cross Halfword", "summary": "Multiply bottom half of RA by top half of RB.", "syntax": "mulchw RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "4 | RT | RA | RB | 168 | 0", "hex_opcode": "0x10000150", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "168", "clean": "168" }, { "raw": "0", "clean": "0" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RA", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Embedded", "description": "Multiplies the sign-extended bottom halfword of RA by the sign-extended top halfword of RB, storing the low 32 bits of the product in RT. This is a signed 16×16→32 multiply operation. No condition register or status flags are affected.", "pseudocode": "a ← EXTS(RA[16:31])\nb ← EXTS(RB[0:15])\nRT ← (a × b)[32:63]", "example": "mulchw r3, r4, r5" }, { "mnemonic": "mulchwu", "architecture": "PowerISA", "full_name": "Multiply Cross Halfword Unsigned", "summary": "Unsigned Multiply Cross Halfword.", "syntax": "mulchwu RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "4 | RT | RA | RB | 136 | 0", "hex_opcode": "0x10000110", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "136", "clean": "136" }, { "raw": "0", "clean": "0" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RA", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Embedded", "description": "Multiplies the zero-extended bottom halfword of RA by the zero-extended top halfword of RB, storing the low 32 bits of the product in RT. This is an unsigned 16×16→32 multiply operation. No condition register or status flags are affected.", "pseudocode": "a ← (RA[16:31])\nb ← (RB[0:15])\nRT ← (a × b)[32:63]", "example": "mulchwu r3, r4, r5" }, { "mnemonic": "mulhhw", "architecture": "PowerISA", "full_name": "Multiply High Halfword", "summary": "Multiply top half of RA by top half of RB.", "syntax": "mulhhw RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "4 | RT | RA | RB | 40 | 0", "hex_opcode": "0x10000050", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "40", "clean": "40" }, { "raw": "0", "clean": "0" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RA", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Embedded", "description": "Multiplies the sign-extended top halfword of RA by the sign-extended top halfword of RB, storing the low 32 bits of the product in RT. This is a signed 16×16→32 multiply operation on the upper halves. No condition register or status flags are affected.", "pseudocode": "a ← EXTS(RA[0:15])\nb ← EXTS(RB[0:15])\nRT ← (a × b)[32:63]", "example": "mulhhw r3, r4, r5" }, { "mnemonic": "mulhhwu", "architecture": "PowerISA", "full_name": "Multiply High Halfword Unsigned", "summary": "Unsigned Multiply High Halfword.", "syntax": "mulhhwu RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "4 | RT | RA | RB | 8 | 0", "hex_opcode": "0x10000010", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "8", "clean": "8" }, { "raw": "0", "clean": "0" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RA", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Embedded", "description": "Multiplies the zero-extended top halfword of RA by the zero-extended top halfword of RB, storing the low 32 bits of the product in RT. This is an unsigned 16×16→32 multiply operation on the upper halves. No condition register or status flags are affected.", "pseudocode": "a ← (RA[0:15])\nb ← (RB[0:15])\nRT ← (a × b)[32:63]", "example": "mulhhwu r3, r4, r5" }, { "mnemonic": "mullhw", "architecture": "PowerISA", "full_name": "Multiply Low Halfword", "summary": "Multiply bottom half of RA by bottom half of RB.", "syntax": "mullhw RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "4 | RT | RA | RB | 424 | 0", "hex_opcode": "0x10000350", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "424", "clean": "424" }, { "raw": "0", "clean": "0" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RA", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Embedded", "description": "Multiplies the sign-extended bottom halfword of RA by the sign-extended bottom halfword of RB, storing the low 32 bits of the product in RT. This is a signed 16×16→32 multiply operation on the lower halves. No condition register or status flags are affected.", "pseudocode": "a ← EXTS(RA[16:31])\nb ← EXTS(RB[16:31])\nRT ← (a × b)[32:63]", "example": "mullhw r3, r4, r5" }, { "mnemonic": "mullhwu", "architecture": "PowerISA", "full_name": "Multiply Low Halfword Unsigned", "summary": "Unsigned Multiply Low Halfword.", "syntax": "mullhwu RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "4 | RT | RA | RB | 392 | 0", "hex_opcode": "0x10000310", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "392", "clean": "392" }, { "raw": "0", "clean": "0" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RA", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Embedded", "description": "Multiplies the zero-extended bottom halfword of RA by the zero-extended bottom halfword of RB, storing the low 32 bits of the product in RT. This is an unsigned 16×16→32 multiply operation on the lower halves. No condition register or status flags are affected.", "pseudocode": "a ← (RA[16:31])\nb ← (RB[16:31])\nRT ← (a × b)[32:63]", "example": "mullhwu r3, r4, r5" }, { "mnemonic": "nmacchw", "architecture": "PowerISA", "full_name": "Negative Multiply Accumulate Cross Halfword", "summary": "Negate product of cross halfwords and add to accumulator.", "syntax": "nmacchw RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "4 | RT | RA | RB | 174 | 0", "hex_opcode": "0x1000015C", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "174", "clean": "174" }, { "raw": "0", "clean": "0" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Acc/Dest" }, { "name": "RA", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Embedded", "description": "Multiplies the sign-extended bottom halfword of RA by the sign-extended top halfword of RB, negates the product, and adds it to the current value of RT (treating RT as a 32-bit accumulator). The result is stored back in RT. No condition register or status flags are affected.", "pseudocode": "a ← EXTS(RA[16:31])\nb ← EXTS(RB[0:15])\nproduct ← (a × b)[32:63]\nRT ← RT + (¬product + 1)", "example": "nmacchw r3, r4, r5" }, { "mnemonic": "nmacchws", "architecture": "PowerISA", "full_name": "Negative Multiply Accumulate Cross Halfword Signed", "summary": "Negate product of cross halfwords and add to accumulator (Signed Saturation).", "syntax": "nmacchws RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "4 | RT | RA | RB | 238 | 0", "hex_opcode": "0x100001DC", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "238", "clean": "238" }, { "raw": "0", "clean": "0" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Acc/Dest" }, { "name": "RA", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Embedded", "description": "Multiplies the sign-extended bottom halfword of RA by the sign-extended top halfword of RB, negates the product, and adds it to RT with signed saturation to 32 bits. The saturated result is stored in RT, and the SAT bit in the SPEFSCR is set if saturation occurred. This instruction requires the SPE category.", "pseudocode": "a ← EXTS(RA[16:31])\nb ← EXTS(RB[0:15])\nproduct ← (a × b)[32:63]\nresult ← RT + (¬product + 1)\nif result > 2147483647 then\n RT ← 2147483647\n SPEFSCR[SAT] ← 1\nelif result < -2147483648 then\n RT ← -2147483648\n SPEFSCR[SAT] ← 1\nelse\n RT ← result", "example": "nmacchws r3, r4, r5" }, { "mnemonic": "nmachhw", "architecture": "PowerISA", "full_name": "Negative Multiply Accumulate High Halfword", "summary": "Negate product of high halfwords and add to accumulator.", "syntax": "nmachhw RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "4 | RT | RA | RB | 46 | 0", "hex_opcode": "0x1000005C", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "46", "clean": "46" }, { "raw": "0", "clean": "0" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Acc/Dest" }, { "name": "RA", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Embedded", "description": "Multiplies the high halfwords (bits 0-15) of RA and RB as signed 16-bit integers, negates the 32-bit product, and adds it to RT, storing the result in RT. This is an embedded SPE instruction that performs signed halfword multiply-accumulate with negation. The overflow bit (XER[OV]) is set if the result overflows a 32-bit signed integer.", "pseudocode": "prod ← EXTS((RA[0:15]) * (RB[0:15]))\nRT ← RT + (-prod)\nif overflow then XER[OV] ← 1 else XER[OV] ← 0\nXER[SO] ← XER[SO] | XER[OV]", "example": "nmachhw r3, r4, r5" }, { "mnemonic": "nmachhws", "architecture": "PowerISA", "full_name": "Negative Multiply Accumulate High Halfword Signed", "summary": "Negate product of high halfwords and add to accumulator (Signed Saturation).", "syntax": "nmachhws RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "4 | RT | RA | RB | 110 | 0", "hex_opcode": "0x100000DC", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "110", "clean": "110" }, { "raw": "0", "clean": "0" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Acc/Dest" }, { "name": "RA", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Embedded", "description": "Multiplies the high halfwords (bits 0-15) of RA and RB as signed 16-bit integers, negates the 32-bit product, and adds it to RT with signed saturation, storing the result in RT. This is an embedded SPE instruction that performs signed halfword multiply-accumulate with negation and saturation. The overflow and saturation bits (XER[OV] and XER[SAT]) are set appropriately.", "pseudocode": "prod ← EXTS((RA[0:15]) * (RB[0:15]))\nresult ← RT + (-prod)\nif result > 2147483647 then\n RT ← 2147483647\n XER[SAT] ← 1\nelse if result < -2147483648 then\n RT ← -2147483648\n XER[SAT] ← 1\nelse\n RT ← result\nXER[OV] ← XER[SAT]", "example": "nmachhws r3, r4, r5" }, { "mnemonic": "nmaclhw", "architecture": "PowerISA", "full_name": "Negative Multiply Accumulate Low Halfword", "summary": "Negate product of low halfwords and add to accumulator.", "syntax": "nmaclhw RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "4 | RT | RA | RB | 430 | 0", "hex_opcode": "0x1000035C", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "430", "clean": "430" }, { "raw": "0", "clean": "0" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Acc/Dest" }, { "name": "RA", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Embedded", "description": "Multiplies the low halfwords (bits 16-31) of RA and RB as signed 16-bit integers, negates the 32-bit product, and adds it to RT, storing the result in RT. This is an embedded SPE instruction that performs signed halfword multiply-accumulate with negation. The overflow bit (XER[OV]) is set if the result overflows a 32-bit signed integer.", "pseudocode": "prod ← EXTS((RA[16:31]) * (RB[16:31]))\nRT ← RT + (-prod)\nif overflow then XER[OV] ← 1 else XER[OV] ← 0\nXER[SO] ← XER[SO] | XER[OV]", "example": "nmaclhw r3, r4, r5" }, { "mnemonic": "nmaclhws", "architecture": "PowerISA", "full_name": "Negative Multiply Accumulate Low Halfword Signed", "summary": "Negate product of low halfwords and add to accumulator (Signed Saturation).", "syntax": "nmaclhws RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "4 | RT | RA | RB | 494 | 0", "hex_opcode": "0x100003DC", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "494", "clean": "494" }, { "raw": "0", "clean": "0" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Acc/Dest" }, { "name": "RA", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Embedded", "description": "Multiplies the low halfwords (bits 16-31) of RA and RB as signed 16-bit integers, negates the 32-bit product, and adds it to RT with signed saturation, storing the result in RT. This is an embedded SPE instruction that performs signed halfword multiply-accumulate with negation and saturation. The overflow and saturation bits (XER[OV] and XER[SAT]) are set appropriately.", "pseudocode": "prod ← EXTS((RA[16:31]) * (RB[16:31]))\nresult ← RT + (-prod)\nif result > 2147483647 then\n RT ← 2147483647\n XER[SAT] ← 1\nelse if result < -2147483648 then\n RT ← -2147483648\n XER[SAT] ← 1\nelse\n RT ← result\nXER[OV] ← XER[SAT]", "example": "nmaclhws r3, r4, r5" }, { "mnemonic": "dccci", "architecture": "PowerISA", "full_name": "Data Cache Congruence Class Invalidate", "summary": "Invalidates a congruence class in the data cache (Embedded).", "syntax": "dccci RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | / | RA | RB | 454 | /", "hex_opcode": "0x7C00038E", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "454", "clean": "454" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Embedded", "description": "Invalidates a congruence class in the data cache at the address formed by RA + RB. This is an embedded cache-management instruction with no guaranteed semantics on all implementations; behavior is implementation-dependent and may require supervisor privilege. The instruction has no effect on data in higher-level caches or main memory.", "pseudocode": "addr ← (RA) + (RB)\nInvalidate data cache congruence class at addr", "example": "dccci r4, r5" }, { "mnemonic": "dcread", "architecture": "PowerISA", "full_name": "Data Cache Read", "summary": "Reads a data cache tag or data (Debug).", "syntax": "dcread RT, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | RA | RB | 486 | /", "hex_opcode": "0x7C0003CC", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "486", "clean": "486" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Embedded", "description": "Reads and returns a data cache tag or data value from the address RA + RB into register RT. This is an embedded debug/diagnostic instruction used to inspect data cache contents; exact behavior (tag vs. data read, selection mechanism) is implementation-dependent. The instruction requires supervisor privilege and may not be available on all embedded PowerPC implementations.", "pseudocode": "addr ← (RA) + (RB)\nRT ← Read data cache entry at addr", "example": "dcread r3, r4, r5" }, { "mnemonic": "iccci", "architecture": "PowerISA", "full_name": "Instruction Cache Congruence Class Invalidate", "summary": "Invalidates a congruence class in the instruction cache (Embedded).", "syntax": "iccci RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | / | RA | RB | 966 | /", "hex_opcode": "0x7C00078E", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "966", "clean": "966" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Embedded", "description": "Invalidates a congruence class in the instruction cache at the address formed by RA + RB. This is an embedded cache-management instruction with no guaranteed semantics on all implementations; behavior is implementation-dependent and may require supervisor privilege. The instruction has no effect on instruction cache entries in higher-level caches or main memory.", "pseudocode": "addr ← (RA) + (RB)\nInvalidate instruction cache congruence class at addr", "example": "iccci r4, r5" }, { "mnemonic": "icread", "architecture": "PowerISA", "full_name": "Instruction Cache Read", "summary": "Reads an instruction cache tag or data (Debug).", "syntax": "icread RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | / | RA | RB | 998 | /", "hex_opcode": "0x7C0007CE", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "998", "clean": "998" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Embedded", "description": "Reads and returns an instruction cache tag or data value from the address RA + RB into a read port. This is an embedded debug/diagnostic instruction used to inspect instruction cache contents; exact behavior (tag vs. instruction read, selection mechanism) is implementation-dependent. The instruction requires supervisor privilege and may not be available on all embedded PowerPC implementations.", "pseudocode": "addr ← (RA) + (RB)\nRead instruction cache entry at addr", "example": "icread r4, r5" }, { "mnemonic": "tlbre", "architecture": "PowerISA", "full_name": "TLB Read Entry", "summary": "Reads a TLB entry into MAS registers.", "syntax": "tlbre", "encoding": { "format": "X-form", "binary_pattern": "31 | / | / | / | 946 | /", "hex_opcode": "0x7C000762", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "946", "clean": "946" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [], "extension": "Embedded", "description": "Reads a TLB entry specified by MAS0 into the MAS1-MAS3 registers. This instruction is privileged and requires hypervisor mode on some implementations. The TLB entry index and way are determined by the MAS0 register; the instruction populates MAS1-MAS3 with the corresponding entry data.", "pseudocode": "MAS1 ← TLB[MAS0.ESEL, MAS0.TLBSEL].MAS1\nMAS2 ← TLB[MAS0.ESEL, MAS0.TLBSEL].MAS2\nMAS3 ← TLB[MAS0.ESEL, MAS0.TLBSEL].MAS3", "example": "tlbre" }, { "mnemonic": "tlbwe", "architecture": "PowerISA", "full_name": "TLB Write Entry", "summary": "Writes a TLB entry from MAS registers.", "syntax": "tlbwe", "encoding": { "format": "X-form", "binary_pattern": "31 | / | / | / | 978 | /", "hex_opcode": "0x7C0007A2", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "978", "clean": "978" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [], "extension": "Embedded", "description": "Writes a TLB entry from MAS1-MAS3 registers into the TLB at the location specified by MAS0. This instruction is privileged and requires hypervisor mode on some implementations. The entry index and way are determined by MAS0; the instruction updates the corresponding TLB entry with data from MAS1-MAS3.", "pseudocode": "TLB[MAS0.ESEL, MAS0.TLBSEL].MAS1 ← MAS1\nTLB[MAS0.ESEL, MAS0.TLBSEL].MAS2 ← MAS2\nTLB[MAS0.ESEL, MAS0.TLBSEL].MAS3 ← MAS3", "example": "tlbwe" }, { "mnemonic": "tlbsx", "architecture": "PowerISA", "full_name": "TLB Search Indexed", "summary": "Searches the TLB for an address.", "syntax": "tlbsx RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | / | RA | RB | 914 | /", "hex_opcode": "0x7C000722", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "914", "clean": "914" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Embedded", "description": "Searches the TLB for an entry matching the virtual address formed by combining RA and RB, and loads matching entry data into MAS0-MAS3 registers. If a match is found, MAS0.ESEL contains the entry index and MAS1-MAS3 contain the matching entry data. This instruction is privileged and affects MAS registers but not the general condition register.", "pseudocode": "EA ← (RA) + (RB)\nif TLB.lookup(EA) then\n MAS0 ← TLB.index(EA)\n MAS1 ← TLB[index].MAS1\n MAS2 ← TLB[index].MAS2\n MAS3 ← TLB[index].MAS3\nelse\n MAS0.NOMPLT ← 1\nend if", "example": "tlbsx r4, r5" }, { "mnemonic": "tlbivax", "architecture": "PowerISA", "full_name": "TLB Invalidate Virtual Address Indexed", "summary": "Invalidates a TLB entry by virtual address.", "syntax": "tlbivax RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | / | RA | RB | 786 | /", "hex_opcode": "0x7C000622", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "786", "clean": "786" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Embedded", "description": "Invalidates a TLB entry matching the virtual address formed by RA and RB. This instruction is privileged and causes any TLB entry with a matching virtual address to be marked invalid. The exact behavior depends on the MMU implementation and may invalidate one or multiple entries.", "pseudocode": "EA ← (RA) + (RB)\nfor each TLB entry matching EA do\n TLB[entry].V ← 0\nend for", "example": "tlbivax r4, r5" }, { "mnemonic": "wrtee", "architecture": "PowerISA", "full_name": "Write MSR External Enable", "summary": "Updates the EE bit of the MSR from a GPR.", "syntax": "wrtee RS", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | / | / | 131 | /", "hex_opcode": "0x7C000106", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "131", "clean": "131" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RS", "desc": "Source" } ], "extension": "Embedded", "description": "Updates the Machine State Register (MSR) External Enable (EE) bit from the least significant bit of RS. This instruction is privileged and allows software to enable or disable external interrupts. The EE bit controls whether external interrupts are recognized by the processor.", "pseudocode": "MSR.EE ← RS[63]", "example": "wrtee r3" }, { "mnemonic": "wrteei", "architecture": "PowerISA", "full_name": "Write MSR External Enable Immediate", "summary": "Updates the EE bit of the MSR from an immediate.", "syntax": "wrteei E", "encoding": { "format": "X-form", "binary_pattern": "31 | / | / | E | 163 | /", "hex_opcode": "0x7C000146", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "E", "clean": "E" }, { "raw": "163", "clean": "163" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "E", "desc": "Enable (0/1)" } ], "extension": "Embedded", "description": "Updates the Machine State Register (MSR) External Enable (EE) bit from the immediate value E (0 or 1). This instruction is privileged and provides a quick way to enable or disable external interrupts. The EE bit controls whether external interrupts are recognized by the processor.", "pseudocode": "MSR.EE ← E", "example": "wrteei 0" }, { "mnemonic": "mfdcr", "architecture": "PowerISA", "full_name": "Move From Device Control Register", "summary": "Reads an on-chip peripheral register (DCR).", "syntax": "mfdcr RT, DCRN", "encoding": { "format": "XFX-form", "binary_pattern": "31 | RT | DCRN | 323 | /", "hex_opcode": "0x7C000286", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "DCRN", "clean": "DCRN" }, { "raw": "323", "clean": "323" } ], "bit_positions": "0:5 | 6:10 | 11:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "DCRN", "desc": "DCR Number" } ], "extension": "Embedded", "description": "Reads a Device Control Register (DCR) and writes the value to general-purpose register RT. This instruction is privileged and device-specific; the DCR address is specified by DCRN. Access to DCR is implementation-dependent and may not be available on all processors.", "pseudocode": "RT ← DCR[DCRN]", "example": "mfdcr r3, 0" }, { "mnemonic": "mtdcr", "architecture": "PowerISA", "full_name": "Move To Device Control Register", "summary": "Writes an on-chip peripheral register (DCR).", "syntax": "mtdcr DCRN, RS", "encoding": { "format": "XFX-form", "binary_pattern": "31 | RS | DCRN | 451 | /", "hex_opcode": "0x7C000386", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "DCRN", "clean": "DCRN" }, { "raw": "451", "clean": "451" } ], "bit_positions": "0:5 | 6:10 | 11:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "DCRN", "desc": "DCR Number" }, { "name": "RS", "desc": "Source" } ], "extension": "Embedded", "description": "Writes the value from general-purpose register RS to a Device Control Register (DCR) specified by DCRN. This instruction is privileged and device-specific. Access to DCR is implementation-dependent and may not be available on all processors; the effects depend on the target DCR.", "pseudocode": "DCR[DCRN] ← RS", "example": "mtdcr 0, r3" }, { "mnemonic": "darn", "architecture": "PowerISA", "full_name": "Deliver A Random Number", "summary": "Returns a random number from the hardware RNG. (L=3: Raw, L=1: Conditioned, L=0: 32-bit).", "syntax": "darn RT, L", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | / | L | 755 | /", "hex_opcode": "0x7C0005E6", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "/", "clean": "/" }, { "raw": "L", "clean": "L" }, { "raw": "755", "clean": "755" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:13 | 14:15 | 16:20 | 21:31" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "L", "desc": "Mode" } ], "extension": "Base", "description": "Delivers a random number from the hardware random number generator into GPR RT. The L field controls the output mode: L=3 returns raw entropy, L=1 returns conditioned/whitened entropy, and L=0 returns a 32-bit conditioned value. This instruction requires the darn facility to be enabled and does not affect any condition or status registers.", "pseudocode": "if L = 3 then\n RT ← raw_random_64()\nelif L = 1 then\n RT ← conditioned_random_64()\nelif L = 0 then\n RT ← (0 || conditioned_random_32())\nelse\n UNDEFINED", "programming_notes": "The random number generator provides a minimum of 0.5 bits of entropy per bit. For L=0, the random number range is 0:0xFFFFFFFF. For L=1 and L=2, the random number range is 0:0xFFFFFFFF_FFFFFFFE. L=3 is reserved. A raw random number is unconditioned noise source output. A conditioned random number has been processed by hardware to reduce bias. 32-bit software running in an environment that does not preserve the high-order 32 bits of GPRs across invocations of the system error handler, signal handlers, event-based branch handlers, etc., may use the L=0 variant of darn and interpret the value 0xFFFFFFFF to indicate an error condition. When the error value is obtained, software is expected to repeat the operation. If a non-error value has not been obtained after several attempts, a software random number generation method should be used.", "page_found": "Page 119 - 120", "example": "darn r3, 0" }, { "mnemonic": "mffs", "architecture": "PowerISA", "full_name": "Move From FPSCR", "summary": "Moves the contents of the Floating-Point Status and Control Register (FPSCR) into a floating-point register.", "syntax": "mffs FRT", "encoding": { "format": "X-form", "binary_pattern": "63 | FRT | / | / | 583 | Rc", "hex_opcode": "0xFC00048E", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "583", "clean": "583" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" } ], "extension": "Floating-Point", "description": "Moves the contents of the Floating-Point Status and Control Register (FPSCR) into floating-point register FRT. If Rc=1 (mffs.), the instruction updates CR1 based on the moved FPSCR value. This is a privileged instruction that does not alter FPSCR itself.", "pseudocode": "FRT ← FPSCR\nif Rc = 1 then\n CR1 ← (FRT[0:3])", "special_registers": "FPSCR, CR1, (if, Rc=1), CR0", "extended_mnemonics": [ "mffs.", "mffs" ], "page_found": "Page 216 - 218", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "mffs f1" }, { "mnemonic": "mtfsf", "architecture": "PowerISA", "full_name": "Move To FPSCR Fields", "summary": "Moves the contents of a floating-point register into specified fields of the FPSCR.", "syntax": "mtfsf FLM,FRB,L,W", "encoding": { "format": "XFL-form", "binary_pattern": "63 | L | FLM | W | FRB | 711 | /", "hex_opcode": "0xFC00058E", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "L", "clean": "L" }, { "raw": "FLM", "clean": "FLM" }, { "raw": "W", "clean": "W" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "711", "clean": "711" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "FLM", "desc": "Field Mask" }, { "name": "FRB", "desc": "Source" }, { "name": "L", "desc": "Load Control Bit" }, { "name": "W", "desc": "Word Select Bit" } ], "extension": "Floating-Point", "description": "The FPSCR is modified as specified by the FLM, L, and W fields. If L=0, the contents of register FRB are placed into the FPSCR under control of the W field and the field mask specified by FLM. If L=1, the contents of register FRB are placed into the FPSCR.", "pseudocode": "if 'mtfsf' then\n if L=0 then\n for i from 0 to 7 do\n if FLMi=1 then\n FPSCR[k] <- FRB[i+8*(1-W)]\n end if\n end for\n else if L=1 then\n FPSCR <- FRB\n end if\nend if", "special_registers": "FPSCR, CR1", "programming_notes": "Bits 33 and 34 (FEX and VX) cannot be explicitly reset.\nIf L=1 or if L=0 and FPSCR32:35 is specified, bits 32 (FX) and 35 (OX) are set to the values of (FRB)32 and (FRB)35.", "extended_mnemonics": [ "mtfsf FLM,FRB" ], "page_found": "Page 220 - 222", "example": "mtfsf 0xFF, f3, 0, 0" }, { "mnemonic": "mtfsfi", "architecture": "PowerISA", "full_name": "Move To FPSCR Field Immediate", "summary": "Writes a 4-bit immediate to a specific FPSCR field.", "syntax": "mtfsfi BF, U", "encoding": { "format": "X-form", "binary_pattern": "63 | BF | / | U | 134 | /", "hex_opcode": "0xFC00010C", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "BF", "clean": "BF" }, { "raw": "/", "clean": "/" }, { "raw": "U", "clean": "U" }, { "raw": "134", "clean": "134" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "BF", "desc": "Field Index" }, { "name": "U", "desc": "Immediate" } ], "extension": "Floating-Point", "description": "Writes a 4-bit immediate value U into a 4-bit field of the FPSCR selected by BF. The target FPSCR field is at bits [4×BF : 4×BF+3]. This instruction directly modifies FPSCR state and may affect subsequent floating-point operations.", "special_registers": "FPSCR", "programming_notes": "Use mtfsfi to directly manipulate specific fields in the FPSCR, such as enabling or disabling exceptions. Ensure the immediate value fits within the specified field size to avoid undefined behavior. This instruction operates at user privilege level and does not generate exceptions for valid immediate values.", "pseudocode": "FPSCR[4*BF : 4*BF+3] ← U", "example": "mtfsfi cr0, 0" }, { "mnemonic": "mtfsb0", "architecture": "PowerISA", "full_name": "Move To FPSCR Bit 0", "summary": "Clears a specific bit in the FPSCR.", "syntax": "mtfsb0 BT", "encoding": { "format": "X-form", "binary_pattern": "63 | BT | / | / | 70 | /", "hex_opcode": "0xFC00008C", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "BT", "clean": "BT" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "70", "clean": "70" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "BT", "desc": "Bit Index" } ], "extension": "Floating-Point", "description": "Clears (sets to 0) the FPSCR bit specified by BT. The FPSCR bits are numbered 0-31. Clearing certain FPSCR bits (e.g., exception bits or mode flags) can alter the behavior of subsequent floating-point operations.", "pseudocode": "FPSCR[BT] ← 0", "page_found": "Page 221", "special_registers": "FPSCR", "programming_notes": "The mtfsb0 instruction sets a specific bit in the FPSCR register to the value of the U field. It's commonly used for controlling floating-point exceptions and status flags. Be cautious when altering the FX bit, as it affects exception handling. This instruction operates at user privilege level.", "example": "mtfsb0 0" }, { "mnemonic": "mtfsb1", "architecture": "PowerISA", "full_name": "Move To FPSCR Bit 1", "summary": "Sets a specific bit in the FPSCR.", "syntax": "mtfsb1 BT", "encoding": { "format": "X-form", "binary_pattern": "63 | BT | / | / | 38 | /", "hex_opcode": "0xFC00004C", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "BT", "clean": "BT" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "38", "clean": "38" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "BT", "desc": "Bit Index" } ], "extension": "Floating-Point", "description": "Sets (sets to 1) the FPSCR bit specified by BT. The FPSCR bits are numbered 0-31. Setting certain FPSCR bits (e.g., rounding mode or enable flags) can alter the behavior of subsequent floating-point operations.", "pseudocode": "FPSCR[BT] ← 1", "special_registers": "FPSCR", "programming_notes": "This instruction is used to enable a specific floating-point exception. Ensure that the FPSCR register is properly managed to avoid unintended exceptions. This operation requires supervisor privilege level.", "example": "mtfsb1 0" }, { "mnemonic": "hrfid", "architecture": "PowerISA", "full_name": "Hypervisor Return From Interrupt Doubleword", "summary": "Returns from a hypervisor interrupt.", "syntax": "hrfid", "encoding": { "format": "XL-form", "binary_pattern": "19 | / | / | / | 274 | /", "hex_opcode": "0x4C000224", "visual_parts": [ { "raw": "19", "clean": "19" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "274", "clean": "274" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [], "extension": "Privileged", "description": "Returns from a hypervisor interrupt by restoring the program counter from HSRR0 and machine state from HSRR1, then resuming execution at the restored address. This is a hypervisor-privileged instruction and only valid when the processor is in hypervisor state. It acts as a serializing instruction.", "pseudocode": "NIA ← HSRR0\nRestore MSR from HSRR1\nReturn", "special_registers": "SRR0, SRR1, MSR", "programming_notes": "The hrfid instruction is crucial for hypervisors to manage interrupt returns, updating the MSR and setting the NIA based on values from HSRR. Ensure that HSRR registers are correctly populated before executing hrfid to avoid undefined behavior. This instruction operates at supervisor level and may trigger exceptions if executed in an inappropriate context.", "example": "hrfid" }, { "mnemonic": "copy", "architecture": "PowerISA", "full_name": "Copy", "summary": "Initiates a hardware copy (accelerator) operation.", "syntax": "copy RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | / | RA | RB | 706 | /", "hex_opcode": "0x7C20060C", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "706", "clean": "706" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RA", "desc": "Dest/Control" }, { "name": "RB", "desc": "Source" } ], "extension": "Privileged", "description": "The 'copy' instruction loads a 128-byte block of data and associated metadata from memory into the copy buffer. The effective address (EA) is calculated as the sum of RA and RB. If EA is not aligned to 128 bytes or if the storage is Caching Inhibited, appropriate error handlers are invoked.", "pseudocode": "if RA = 0 then\n b ← 0\nelse\n b ← (RA)\nEA ← b + (RB)\ncopy_buffer ← memory(EA, 128) || MEMmetadata(EA, 128)", "programming_notes": "This instruction is treated as a Load, except that the data transfer ordering is described in Section 1.7.1.1.", "page_found": "Page 1042 - 1043", "example": "copy r4, r5" }, { "mnemonic": "paste", "architecture": "PowerISA", "full_name": "Paste", "summary": "Transfers data from the copy buffer to a specified memory location.", "syntax": "paste RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | / | RA | RB | 770 | /", "hex_opcode": "0x7C00070C", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "770", "clean": "770" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RA", "desc": "Dest" }, { "name": "RB", "desc": "Control" }, { "name": "L", "desc": "Logical flag (0 or 1)" } ], "extension": "Privileged", "description": "Transfers data from the processor's copy buffer to a memory location specified by the effective address formed from RA and RB. This instruction is part of the Copy/Paste facility and requires special kernel/hypervisor support. The L operand controls paste behavior (0=non-atomic, 1=atomic).", "pseudocode": "EA ← (RA) + (RB)\nif L = 1 then\n Paste_Atomic(EA, Copy_Buffer)\nelse\n Paste_NonAtomic(EA, Copy_Buffer)", "special_registers": "CR0, XERSO", "extended_mnemonics": [ "paste. RA,RB", "paste. RA,RB,1" ], "page_found": "Page 1043 - 1044", "programming_notes": "The paste instruction is commonly used to transfer data from the copy buffer to memory. Ensure that the effective address (EA) calculated from RA and RB is correctly aligned for optimal performance. If L=1, be aware that metadata bits in the copy buffer are cleared before the transfer, which might affect subsequent operations relying on these bits.", "example": "paste r4, r5" }, { "mnemonic": "vclzb", "architecture": "PowerISA", "full_name": "Vector Count Leading Zeros Byte", "summary": "Counts the number of leading zero bits in each byte element of a vector register.", "syntax": "vclzb vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "0 | VRT | VRB | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0", "hex_opcode": "0x10000702", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1794", "clean": "1794" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vclzb, the number of consecutive zero bits starting at bit 0 of each byte element in VSR[VRB+32] is placed into the corresponding byte element in VSR[VRT+32]. The count ranges from 0 to 8, inclusive.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 15\n n ←0\n do while n < 8\n if VSR[VRB+32].byte[i].bit[n] = 0b1 then\n leave\n n ←n + 1\n end\n VSR[VRT+32].byte[i] ←n\nend", "page_found": "Page 470 - 471", "special_registers": "MSR", "programming_notes": "The vclzb instruction counts leading zeros in each byte of the input vector. Ensure that the Vector Facility is enabled by checking and setting the appropriate bit in the MSR register. This instruction operates on 16-byte vectors, processing each byte individually. Be cautious with alignment; while not strictly required, proper alignment can optimize performance. The result is a vector where each element contains the count of leading zeros from the corresponding input byte.", "example": "vclzb vd, vb" }, { "mnemonic": "vclzh", "architecture": "PowerISA", "full_name": "Vector Count Leading Zeros Halfword", "summary": "Counts leading zeros in each halfword.", "syntax": "vclzh vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 0 | vB | 1858", "hex_opcode": "0x10000742", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1858", "clean": "1858" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" } ], "extension": "VMX (AltiVec)", "description": "Counts the number of leading zero bits in each of the four 16-bit halfwords of register VB and writes the count (0-16) into the corresponding halfword of register VD. Does not affect CR or FPSCR.", "pseudocode": "for i in 0 to 3 do\n halfword ← VB[16*i : 16*i+15]\n VD[16*i : 16*i+15] ← ctz(halfword) // count leading zeros in 16-bit value", "page_found": "Page 471", "special_registers": "MSR", "programming_notes": "The vclzh instruction is useful for counting leading zeros in each halfword of a vector, which can be helpful in various bit manipulation tasks. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The instruction processes 8 halfwords per vector register, and results are stored directly in the destination vector register.", "example": "vclzh vd, vb" }, { "mnemonic": "vclzw", "architecture": "PowerISA", "full_name": "Vector Count Leading Zeros Word", "summary": "Counts the number of leading zero bits in each word element of a vector register.", "syntax": "vclzw vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 0 | vB | 1922", "hex_opcode": "0x10000782", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1922", "clean": "1922" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vclzw, the number of consecutive zero bits starting at bit 0 of each word element in VSR[VRB+32] is counted and placed into the corresponding word element in VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n n ←0\ndo while n < 32\n if VSR[VRB+32].word[i].bit[n] = 0b1 then\n leave\n n ←n + 1\nend\nVSR[VRT+32].word[i] ←n\nend", "page_found": "Page 471 - 472", "special_registers": "MSR", "programming_notes": "vclzw counts leading zeros in each word of the input vector. Ensure VSR[VRB+32] is properly aligned and accessible. This instruction operates at user privilege level unless MSR.VEC is set, in which case it raises an exception.", "example": "vclzw vd, vb" }, { "mnemonic": "vclzd", "architecture": "PowerISA", "full_name": "Vector Count Leading Zeros Doubleword", "summary": "Counts the number of leading zero bits in each doubleword element of a vector register.", "syntax": "vclzd vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 0 | vB | 1986", "hex_opcode": "0x100007C2", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1986", "clean": "1986" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vclzd, for each integer value i from 0 to 1, counts the number of consecutive zero bits starting at bit 0 of doubleword element i of VSR[VRB+32] and places this count into doubleword element i of VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 1\n n ←0\n do while (n<64) & (VSR[VRB+32].dword[i].bit[n]=0b0)\n n ←n + 1\n end\n VSR[VRT+32].dword[i] ←n\nend", "page_found": "Page 472 - 473", "special_registers": "MSR", "programming_notes": "The vclzd instruction counts leading zeros in each doubleword of the input vector. Ensure that the Vector Facility is enabled by checking and setting the MSR.VEC bit. This instruction operates on 64-bit elements, so input vectors must be aligned accordingly. The result is stored in the destination vector register.", "example": "vclzd vd, vb" }, { "mnemonic": "vctzb", "architecture": "PowerISA", "full_name": "Vector Count Trailing Zeros Byte", "summary": "Counts the number of trailing zero bits in each byte element of a vector register.", "syntax": "vctzb vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | VRT | 28 | VRB | 1538", "hex_opcode": "0x101C0602", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1794", "clean": "1794" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vctzb, the number of consecutive zero bits starting at bit 7 of each byte element in VSR[VRB+32] is placed into the corresponding byte element in VSR[VRT+32]. The count ranges from 0 to 8, inclusive.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 15\n n ←0\n do while n < 8\n if VSR[VRB+32].byte[i].bit[7-n] = 0b1 then\n leave\n n ←n + 1\n end\n VSR[VRT+32].byte[i] ←CHOP8(EXTZ(n))\nend", "page_found": "Page 473 - 474", "special_registers": "MSR", "programming_notes": "The vctzb instruction counts the number of trailing zero bits in each byte of the source vector, storing the result in the destination vector. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on 16-byte vectors and processes each byte independently. Be cautious with alignment; while not strictly required, proper alignment can improve performance.", "example": "vctzb vd, vb" }, { "mnemonic": "vctzh", "architecture": "PowerISA", "full_name": "Vector Count Trailing Zeros Halfword", "summary": "Counts trailing zeros in each halfword.", "syntax": "vctzh vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 0 | vB | 1858", "hex_opcode": "0x101D0602", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1858", "clean": "1858" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" } ], "extension": "VMX (AltiVec)", "description": "Counts the number of trailing zero bits in each of the 8 halfword elements in vB and stores the result in the corresponding halfword of vD. Each result is an unsigned integer in the range 0-16. No status flags are affected. This instruction is part of the VMX (AltiVec) extension.", "pseudocode": "for i in 0 to 7 do\n count ← 0\n halfword ← vB[i*16 : i*16+15]\n if halfword = 0 then\n count ← 16\n else\n for j in 0 to 15 do\n if halfword[j] = 1 then\n break\n count ← count + 1\n vD[i*16 : i*16+15] ← count", "page_found": "Page 474", "special_registers": "MSR", "programming_notes": "The vctzh instruction is useful for counting trailing zeros in each halfword of a vector, which can be helpful in bit manipulation and data compression tasks. Ensure that the Vector Facility (VEC) is enabled in the MSR register to avoid a Vector_Unavailable exception. The instruction processes 8 halfwords per vector register, so ensure your data is properly aligned and structured for optimal performance.", "example": "vctzh vd, vb" }, { "mnemonic": "vctzw", "architecture": "PowerISA", "full_name": "Vector Count Trailing Zeros Word", "summary": "Counts the number of trailing zero bits in each word element of a vector register.", "syntax": "vctzw vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 0 | vB | 1922", "hex_opcode": "0x101E0602", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1922", "clean": "1922" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vctzw, the number of consecutive zero bits starting at bit 31 of each word element in VSR[VRB+32] is counted and placed into the corresponding word element in VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n n ←0\ndo while n < 32\n if VSR[VRB+32].word[i].bit[31-n] = 0b1 then\n leave\n n ←n + 1\nend\nVSR[VRT+32].word[i] ←CHOP32(EXTZ(n))\nend", "page_found": "Page 474 - 475", "special_registers": "MSR", "programming_notes": "The vctzw instruction counts the number of trailing zeros in each word element of a vector register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on 32-bit words, so input data must be aligned accordingly. The result is stored in another vector register, preserving the original data unless explicitly overwritten.", "example": "vctzw vd, vb" }, { "mnemonic": "vctzd", "architecture": "PowerISA", "full_name": "Vector Count Trailing Zeros Doubleword", "summary": "Counts the number of consecutive zero bits starting at bit 63 of each doubleword element in VSR[VRB+32] and places the result into VSR[VRT+32].", "syntax": "vctzd vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 0 | vB | 1986", "hex_opcode": "0x101F0602", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1986", "clean": "1986" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vctzd, for each integer value i from 0 to 1, a count of the number of consecutive zero bits starting at bit 63 of doubleword element i of VSR[VRB+32] is placed into doubleword element i of VSR[VRT+32]. This number ranges from 0 to 64, inclusive.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 1\n n ←0\n do while n < 64\n if VSR[VRB+32].dword[i].bit[63-n] = 0b1 then\n leave\n n ←n + 1\n end\n VSR[VRT+32].dword[i] ←CHOP64(EXTZ(n))\nend", "page_found": "Page 475 - 476", "special_registers": "MSR", "programming_notes": "The vctzd instruction counts trailing zeros in each doubleword of the input vector. Ensure that the Vector Facility is enabled by checking and setting the MSR.VEC bit. This instruction operates on 64-bit elements, so input vectors must be aligned accordingly. The result is a count from 0 to 64 for each element, indicating the number of trailing zeros.", "example": "vctzd vd, vb" }, { "mnemonic": "vpopcntb", "architecture": "PowerISA", "full_name": "Vector Population Count Byte", "summary": "Counts the number of bits set to 1 in each byte of a vector register.", "syntax": "vpopcntb vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 0 | vB | 1795", "hex_opcode": "0x10000703", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1795", "clean": "1795" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vpopcntb, the number of bits set to 1 in each byte element of VSR[VRB+32] is counted and placed into the corresponding byte element of VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 15\n n ←0\n do j = 0 to 7\n n ←n + VSR[VRB+32].byte[i].bit[j]\n end\n VSR[VRT+32].byte[i] ←n\nend", "page_found": "Page 480 - 481", "special_registers": "MSR", "programming_notes": "This instruction is used to count the number of set bits (1s) in each byte of a vector register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. The operation processes 16 bytes, and the result is stored in another vector register. This instruction is available at user privilege level.", "example": "vpopcntb vd, vb" }, { "mnemonic": "vpopcnth", "architecture": "PowerISA", "full_name": "Vector Population Count Halfword", "summary": "Counts set bits in each halfword.", "syntax": "vpopcnth vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 0 | vB | 1859", "hex_opcode": "0x10000743", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1859", "clean": "1859" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" } ], "extension": "VMX (AltiVec)", "description": "Counts the number of set bits (population count) in each of the 8 halfword elements in vB and stores the result in the corresponding halfword of vD. Each result is an unsigned integer in the range 0-16. No status flags are affected. This instruction is part of the VMX (AltiVec) extension.", "pseudocode": "for i in 0 to 7 do\n count ← 0\n halfword ← vB[i*16 : i*16+15]\n for j in 0 to 15 do\n if halfword[j] = 1 then\n count ← count + 1\n vD[i*16 : i*16+15] ← count", "page_found": "Page 481", "special_registers": "MSR", "programming_notes": "This instruction is useful for counting the number of set bits in each halfword of a vector, which can be helpful in various bit manipulation tasks. Ensure that the Vector Facility (VEC) is enabled in the Machine State Register (MSR) before using this instruction; otherwise, it will raise an exception. The operation is performed on 8 halfwords per vector register, and there are no specific alignment requirements for the data being processed.", "example": "vpopcnth vd, vb" }, { "mnemonic": "vpopcntw", "architecture": "PowerISA", "full_name": "Vector Population Count Word", "summary": "Counts the number of bits set to 1 in each word element of a vector register.", "syntax": "vpopcntw vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 0 | vB | 1923", "hex_opcode": "0x10000783", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1923", "clean": "1923" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vpopcntw, the number of bits set to 1 in each word element of VSR[VRB+32] is counted and placed into the corresponding word element of VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n n ←0\n do j = 0 to 31\n n ←n + VSR[VRB+32].word[i].bit[j]\n end\n VSR[VRT+32].word[i] ←n\nend", "page_found": "Page 481 - 482", "special_registers": "MSR", "programming_notes": "This instruction counts the number of set bits (1s) in each 32-bit word of the source vector and stores the result in the destination vector. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on 128-bit vectors, processing four 32-bit words per operation.", "example": "vpopcntw vd, vb" }, { "mnemonic": "vpopcntd", "architecture": "PowerISA", "full_name": "Vector Population Count Doubleword", "summary": "Counts set bits in each doubleword.", "syntax": "vpopcntd vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 0 | vB | 1987", "hex_opcode": "0x100007C3", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1987", "clean": "1987" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" } ], "extension": "VMX (AltiVec)", "description": "Counts the number of set bits (population count) in each of the 2 doubleword elements in vB and stores the result in the corresponding doubleword of vD. Each result is an unsigned integer in the range 0-64. No status flags are affected. This instruction is part of the VMX (AltiVec) extension.", "pseudocode": "for i in 0 to 1 do\n count ← 0\n doubleword ← vB[i*64 : i*64+63]\n for j in 0 to 63 do\n if doubleword[j] = 1 then\n count ← count + 1\n vD[i*64 : i*64+63] ← count", "page_found": "Page 482", "special_registers": "MSR", "programming_notes": "The vpopcntd instruction is useful for counting the number of set bits in each 64-bit element of a vector. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. This instruction operates on two doublewords per vector register, and results are stored in the corresponding positions of the destination vector.", "example": "vpopcntd vd, vb" }, { "mnemonic": "vextractub", "architecture": "PowerISA", "full_name": "Vector Extract Unsigned Byte to VSR using Immediate-specified Index VX-form", "summary": "Extracts an unsigned byte from a vector register and places it into the upper byte of another vector register.", "syntax": "vextractub RA, vB, UIM", "encoding": { "format": "VX-form", "binary_pattern": "4 | RA | UIM | vB | 525", "hex_opcode": "0x1000020D", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "RA", "clean": "RA" }, { "raw": "UIM", "clean": "UIM" }, { "raw": "vB", "clean": "vB" }, { "raw": "525", "clean": "525" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "RA", "desc": "Target GPR" }, { "name": "vB", "desc": "Source Vector" }, { "name": "UIM", "desc": "Index" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "The contents of byte element UIM of VSR[VRB+32] are placed into bits 56:63 of VSR[VRT+32]. The contents of the remaining byte elements of VSR[VRT+32] are set to 0.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nsrc ←VSR[VRB+32].byte[UIM]\nVSR[VRT+32].dword[0] ←EXTZ64(src)\nVSR[VRT+32].dword[1] ←0x0000_0000_0000_0000", "page_found": "Page 328 - 330", "programming_notes": "If the value of UIM is greater than 14, the results are undefined.", "special_registers": "MSR", "example": "vextractub r4, vb, uim" }, { "mnemonic": "vextractuh", "architecture": "PowerISA", "full_name": "Vector Extract Unsigned Halfword", "summary": "Extracts a halfword from a vector into a GPR.", "syntax": "vextractuh RA, vB, UIM", "encoding": { "format": "VX-form", "binary_pattern": "4 | RA | UIM | vB | 589", "hex_opcode": "0x1000024D", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "RA", "clean": "RA" }, { "raw": "UIM", "clean": "UIM" }, { "raw": "vB", "clean": "vB" }, { "raw": "589", "clean": "589" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target GPR" }, { "name": "vB", "desc": "Source Vector" }, { "name": "UIM", "desc": "Index" } ], "extension": "VMX (AltiVec)", "description": "Extracts an unsigned halfword element from vB at the position specified by UIM and stores the zero-extended 16-bit value into general-purpose register RA. The halfword index (0-7) is provided by the 3-bit immediate UIM. No status flags are affected. This instruction is part of the VMX (AltiVec) extension.", "page_found": "Page 330", "programming_notes": "The vextractuh instruction extracts an unsigned halfword from a vector register at a specified index. Ensure the index is within bounds to avoid undefined behavior. This instruction operates in user privilege level and does not generate exceptions for valid indices.", "pseudocode": "index ← UIM[1:3]\nRA ← (0x0000) || vB[index*16 : index*16+15]", "example": "vextractuh r4, vb, uim" }, { "mnemonic": "vextractuw", "architecture": "PowerISA", "full_name": "Vector Extract Unsigned Word to VSR using Immediate-specified Index VX-form", "summary": "Extracts an unsigned word from a vector register and places it into another vector register using an immediate-specified index.", "syntax": "vextractuw RA, vB, UIM", "encoding": { "format": "VX-form", "binary_pattern": "4 | RA | UIM | vB | 653", "hex_opcode": "0x1000028D", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "RA", "clean": "RA" }, { "raw": "UIM", "clean": "UIM" }, { "raw": "vB", "clean": "vB" }, { "raw": "653", "clean": "653" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "RA", "desc": "Target GPR" }, { "name": "vB", "desc": "Source Vector" }, { "name": "UIM", "desc": "Index" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "VX", "desc": "Target Vector Register" }, { "name": "VS", "desc": "Source Vector Register" }, { "name": "UI", "desc": "Immediate-specified index" } ], "extension": "VMX (AltiVec)", "description": "The contents of byte elements UIM:UIM+3 of VSR[VRB+32] are placed into word element 1 of VSR[VRT+32]. The contents of the remaining word elements of VSR[VRT+32] are set to 0.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nsrc ←VSR[VRB+32].byte[UIM:UIM+3]\nVSR[VRT+32].dword[0] ←EXTZ64(src)\nVSR[VRT+32].dword[1] ←0x0000_0000_0000_0000", "page_found": "Page 330 - 332", "special_registers": "MSR", "programming_notes": "This instruction is used to extract a 4-byte unsigned word from a vector register and place it into another vector register. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. The source byte elements must be correctly specified by UIM, and the destination register will have its first dword set to the extracted value while the second dword is zeroed out.", "example": "vextractuw r4, vb, uim" }, { "mnemonic": "vextractd", "architecture": "PowerISA", "full_name": "Vector Extract Doubleword", "summary": "Extracts a doubleword from a vector into a GPR.", "syntax": "vextractd RA, vB, UIM", "encoding": { "format": "VX-form", "binary_pattern": "4 | RA | UIM | vB | 717", "hex_opcode": "0x100002CD", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "RA", "clean": "RA" }, { "raw": "UIM", "clean": "UIM" }, { "raw": "vB", "clean": "vB" }, { "raw": "717", "clean": "717" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target GPR" }, { "name": "vB", "desc": "Source Vector" }, { "name": "UIM", "desc": "Index" } ], "extension": "VMX (AltiVec)", "description": "Extracts an unsigned doubleword element from vB at the position specified by UIM and stores the 64-bit value into general-purpose register RA. The doubleword index (0-1) is provided by the 1-bit immediate UIM. No status flags are affected. This instruction is part of the VMX (AltiVec) extension.", "pseudocode": "index ← UIM[0:1]\nRA ← vB[index*64 : index*64+63]", "page_found": "Page 331", "special_registers": "MSR", "programming_notes": "The vextractd instruction is used to extract an 8-byte doubleword from a source vector register into the destination vector register, starting at a specified byte index. Ensure that the MSR.VEC bit is set to enable vector operations; otherwise, a Vector_Unavailable exception will be raised. Be cautious with the UIM index; if it exceeds 8, the results are undefined. The destination register's second doubleword is zeroed out.", "example": "vextractd r4, vb, uim" }, { "mnemonic": "vinsertb", "architecture": "PowerISA", "full_name": "Vector Insert Byte from VSR using Immediate-specified Index", "summary": "Inserts a byte element from one vector register into another at an immediate-specified index.", "syntax": "vinsertb vD, vB, UIM", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | UIM | vB | 781", "hex_opcode": "0x1000030D", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "UIM", "clean": "UIM" }, { "raw": "vB", "clean": "vB" }, { "raw": "781", "clean": "781" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target Vector" }, { "name": "vB", "desc": "Source GPR" }, { "name": "UIM", "desc": "Index" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "VX", "desc": "Target Vector Register" }, { "name": "VS", "desc": "Source Vector Register" }, { "name": "VI", "desc": "Immediate Value" }, { "name": "IMM8", "desc": "8-bit Immediate Index" } ], "extension": "VMX (AltiVec)", "description": "The contents of byte element 7 of VSR[VRB+32] are placed into byte element UIM of VSR[VRT+32]. The remaining byte elements of VSR[VRT+32] are not modified.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nVRT[32].byte[UIM] ← VRB[32].byte[7]", "page_found": "Page 338 - 339", "special_registers": "MSR", "programming_notes": "This instruction is used to insert a byte from one vector register into another at a specified index. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector Unavailable exception will be raised. The destination and source registers must be in the range of 32-63. Be cautious with alignment as it affects performance and correctness.", "example": "vinsertb vd, vb, uim" }, { "mnemonic": "vinserth", "architecture": "PowerISA", "full_name": "Vector Insert Halfword", "summary": "Inserts a halfword from a GPR into a vector.", "syntax": "vinserth vD, vB, UIM", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | UIM | vB | 845", "hex_opcode": "0x1000034D", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "UIM", "clean": "UIM" }, { "raw": "vB", "clean": "vB" }, { "raw": "845", "clean": "845" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target Vector" }, { "name": "vB", "desc": "Source GPR" }, { "name": "UIM", "desc": "Index" } ], "extension": "VMX (AltiVec)", "description": "Inserts the low-order 16 bits of general-purpose register vB into vD at the halfword position specified by UIM, leaving other halfword elements of vD unchanged. The halfword index (0-7) is provided by the 3-bit immediate UIM. No status flags are affected. This instruction is part of the VMX (AltiVec) extension.", "pseudocode": "index ← UIM[1:3]\nvD[index*16 : index*16+15] ← vB[48:63]", "page_found": "Page 339", "special_registers": "MSR", "programming_notes": "The vinserth instruction is used to insert a halfword from one vector register into another at a specified index. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. The destination vector's remaining byte elements remain unchanged after the insertion.", "example": "vinserth vd, vb, uim" }, { "mnemonic": "vinsertw", "architecture": "PowerISA", "full_name": "Vector Insert Word from VSR using Immediate-specified Index", "summary": "Inserts a word element from one vector register into another vector register at an immediate-specified index.", "syntax": "vinsertw vD, vB, UIM", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | UIM | vB | 909", "hex_opcode": "0x1000038D", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "UIM", "clean": "UIM" }, { "raw": "vB", "clean": "vB" }, { "raw": "909", "clean": "909" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target Vector" }, { "name": "vB", "desc": "Source GPR" }, { "name": "UIM", "desc": "Index" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "The contents of word element 1 of VSR[VRB+32] are placed into byte elements UIM:UIM+3 of VSR[VRT+32]. The contents of the remaining byte elements of VSR[VRT+32] are not modified. If the value of UIM is greater than 12, the results are undefined.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nVSR[VRT+32].byte[UIM:UIM+3] ← VSR[VRB+32].word[1]", "page_found": "Page 339 - 340", "special_registers": "MSR", "programming_notes": "This instruction is used to insert a word from one vector register into another, with the destination index specified by an immediate value. Ensure that the immediate index (UIM) does not exceed 12 to avoid undefined behavior. This operation requires the Vector Facility to be enabled in the Machine State Register (MSR).", "example": "vinsertw vd, vb, uim" }, { "mnemonic": "vinsertd", "architecture": "PowerISA", "full_name": "Vector Insert Doubleword", "summary": "Inserts a doubleword from a GPR into a vector.", "syntax": "vinsertd vD, vB, UIM", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | UIM | vB | 973", "hex_opcode": "0x100003CD", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "UIM", "clean": "UIM" }, { "raw": "vB", "clean": "vB" }, { "raw": "973", "clean": "973" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target Vector" }, { "name": "vB", "desc": "Source GPR" }, { "name": "UIM", "desc": "Index" } ], "extension": "VMX (AltiVec)", "description": "Inserts the contents of general-purpose register vB into vD at the doubleword position specified by UIM, leaving the other doubleword element of vD unchanged. The doubleword index (0-1) is provided by the 1-bit immediate UIM. No status flags are affected. This instruction is part of the VMX (AltiVec) extension.", "pseudocode": "index ← UIM[0:1]\nvD[index*64 : index*64+63] ← vB[0:63]", "page_found": "Page 340", "special_registers": "MSR", "programming_notes": "The vinsertd instruction is used to insert a doubleword from one vector register into another, with specific byte alignment. Ensure that the UIM value does not exceed 8 to avoid undefined behavior. This instruction requires the VEC bit in the MSR (Machine State Register) to be set; otherwise, it will raise an exception.", "example": "vinsertd vd, vb, uim" }, { "mnemonic": "vaddcuw", "architecture": "PowerISA", "full_name": "Vector Add Carryout Unsigned Word", "summary": "Adds the contents of two vector registers and writes the carry-out to another vector register.", "syntax": "vaddcuw vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 384", "hex_opcode": "0x10000180", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "384", "clean": "384" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vaddcuw, the sum of the unsigned integer values in word elements of VSR[VRA+32] and VSR[VRB+32] is placed into word elements of VSR[VRT+32]. The carry out of the 32-bit sum is zero-extended to 32 bits and placed into word element i of VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n src1 ←EXTZ(VSR[VRA+32].word[i])\n src2 ←EXTZ(VSR[VRB+32].word[i])\n VSR[VRT+32].word[i] ←CHOP32((src1 + src2) >> 32)\nend", "page_found": "Page 348 - 349", "special_registers": "MSR", "programming_notes": "This instruction is used for adding unsigned integers in vector registers, with the carry out being zero-extended and stored alongside the result. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation processes each word element independently, so alignment of data within the vectors is not strictly required.", "example": "vaddcuw vd, va, vb" }, { "mnemonic": "vaddcuq", "architecture": "PowerISA", "full_name": "Vector Add Carryout Unsigned Quadword", "summary": "Adds the contents of two vector registers and writes the carry-out to another register.", "syntax": "vaddcuq vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 1280", "hex_opcode": "0x10000140", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1280", "clean": "1280" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "The instruction adds the unsigned integer values in VSR[VRA+32] and VSR[VRB+32], placing the result in VSR[VRT+32]. The carry-out is also written into VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nsrc1 ←EXTZ(VSR[VRA+32])\nsrc2 ←EXTZ(VSR[VRB+32])\nsum ←EXTZ(src1) + EXTZ(src2)\nVSR[VRT+32] ←EXTZ128((src1 + src2) >> 128)", "programming_notes": "The Vector Add Unsigned Quadword instructions support efficient wide-integer addition.", "page_found": "Page 355 - 356", "special_registers": "MSR", "example": "vaddcuq vd, va, vb" }, { "mnemonic": "vsubcuw", "architecture": "PowerISA", "full_name": "Vector Subtract Carryout Unsigned Word", "summary": "Subtracts the unsigned integer values in word elements of two vector registers and writes the result to another vector register, along with the carry-out.", "syntax": "vsubcuw vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 1408", "hex_opcode": "0x10000580", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1408", "clean": "1408" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vsubcuw, the unsigned integer value in word element i of VSR[VRB+32] is subtracted from the unsigned integer value in word element i of VSR[VRA+32]. The complement of the borrow out of bit 0 of the 32-bit difference is zero-extended to 32 bits and placed into word element i of VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n src1 ←EXTZ(VSR[VRA+32].word[i])\n src2 ←EXTZ(¬VSR[VRB+32].word[i])\n VSR[VRT+32].word[i] ←EXTZ32((src1+src2+1) >> 32)\nend", "page_found": "Page 356 - 357", "special_registers": "MSR", "programming_notes": "The vsubcuw instruction performs an unsigned subtraction with carryout on each word element of the input vectors. It is useful for operations requiring precise control over overflow handling. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation does not require any specific alignment, but inputs must be correctly aligned to 128-bit boundaries as per standard vector register usage.", "example": "vsubcuw vd, va, vb" }, { "mnemonic": "vsubcuq", "architecture": "PowerISA", "full_name": "Vector Subtract Carryout Unsigned Quadword", "summary": "Subtracts the contents of two vector registers, adds one, and writes the carry-out to another register.", "syntax": "vsubcuq vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "0 | VRT | VRA | VRB | 1344", "hex_opcode": "0x10000540", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1280", "clean": "1280" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vsubcuq, the difference between the contents of VSR[VRA+32] and the one's complement of VSR[VRB+32], plus one, is placed into VSR[VRT+32]. The carry out is also written to VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nsrc1 ←EXTZ(VSR[VRA+32])\nsrc2 ←EXTZ(¬VSR[VRB+32])\nVSR[VRT+32] ←CHOP128((src1 + src2 + 1) >> 128)", "programming_notes": "The Vector Subtract Unsigned Quadword instructions support efficient wide-integer subtraction.", "page_found": "Page 363 - 364", "special_registers": "MSR", "example": "vsubcuq vd, va, vb" }, { "mnemonic": "vprtybw", "architecture": "PowerISA", "full_name": "Vector Parity Byte Word", "summary": "Calculates the parity of each byte in a vector word and stores the result.", "syntax": "vprtybw vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | VRT | 8 | VRB | 1538", "hex_opcode": "0x10080602", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1540", "clean": "1540" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vprtybw, the parity of each byte in the source vector register VRB is calculated and stored in the corresponding position in the target vector register VRT.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n s ←0\n do j = 0 to 3\n s ←s ⊕VSR[VRB+32].word[i].byte[j].bit[7]\n end\n VSR[VRT+32].word[i] ←CHOP32(EXTZ(s))\nend", "page_found": "Page 482 - 483", "special_registers": "MSR", "programming_notes": "The vprtybw instruction calculates the parity of each byte in the source vector register and stores the result in the target vector register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on 128-bit vectors, processing four 32-bit words per iteration. Be cautious with alignment; both source and target registers must be properly aligned to avoid exceptions.", "example": "vprtybw vd, vb" }, { "mnemonic": "vprtybd", "architecture": "PowerISA", "full_name": "Vector Parity Byte Doubleword", "summary": "Computes parity of bytes within doublewords.", "syntax": "vprtybd vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 0 | vB | 1604", "hex_opcode": "0x10090602", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1604", "clean": "1604" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" } ], "extension": "VMX (AltiVec)", "description": "Computes the parity (XOR of all bits) of each byte within the 2 doubleword elements of vB and stores a single parity bit (0 or 1) into the corresponding byte position of vD, with each doubleword's 8 bytes reduced to their individual parities. No status flags are affected. This instruction is part of the VMX (AltiVec) extension.", "pseudocode": "for i in 0 to 1 do\n for j in 0 to 7 do\n byte_index ← i*8 + j\n byte_val ← vB[byte_index*8 : byte_index*8+7]\n parity ← XOR(byte_val[0], byte_val[1], ..., byte_val[7])\n vD[byte_index*8 : byte_index*8+7] ← (0x00) || parity", "page_found": "Page 483", "special_registers": "MSR", "programming_notes": "This instruction is useful for calculating the parity of the least significant bit in each byte of a doubleword element. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The operation is performed on 64-bit elements, and the result is stored in the corresponding output vector register. There are no specific alignment requirements for the input data.", "example": "vprtybd vd, vb" }, { "mnemonic": "vprtybq", "architecture": "PowerISA", "full_name": "Vector Parity Byte Quadword", "summary": "Calculates the parity of each byte in a vector register and stores the result in another vector register.", "syntax": "vprtybq vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 0 | vB | 1668", "hex_opcode": "0x100A0602", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1668", "clean": "1668" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "Computes the parity bit for each byte in the 128-bit source vector and stores the result in the destination vector. The parity of each byte is XORed across all 8 bits, producing a single bit (0 or 1) for each byte. This is a VMX/AltiVec extension instruction and does not affect condition registers or status fields.", "pseudocode": "for i in 0 to 15 do\n parity_bit ← 0\n for j in 0 to 7 do\n parity_bit ← parity_bit XOR vB[i*8 + j]\n vD[i*8:i*8+7] ← (0b0000000 || parity_bit)\nend", "page_found": "Page 483 - 484", "special_registers": "MSR", "programming_notes": "The vprtybq instruction calculates the parity of each byte in the source vector register VRB and stores the result in the target vector register VRT. Ensure that the Vector Facility is enabled by checking and setting the MSR.VEC bit. The instruction processes 16 bytes from VRB, and the result is a single bit indicating the parity for each byte, which is then replicated across all 128 bits of VRT.", "example": "vprtybq vd, vb" }, { "mnemonic": "vbcdadd", "architecture": "PowerISA", "full_name": "Vector BCD Add", "summary": "Adds two BCD (Binary Coded Decimal) vectors.", "syntax": "vbcdadd vD, vA, vB, PS", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 1", "hex_opcode": "0x10000001", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1", "clean": "1" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "PS", "desc": "Sign" } ], "extension": "Vector Crypto", "description": "Adds two Binary Coded Decimal (BCD) vectors element-wise and stores the result in the destination vector. The PS field specifies the preferred sign convention for the result. This instruction requires the Vector Crypto extension and does not directly affect condition registers.", "pseudocode": "for i in 0 to 15 do\n BCD_digit_A ← vA[i*4:i*4+3]\n BCD_digit_B ← vB[i*4:i*4+3]\n sum ← BCD_digit_A + BCD_digit_B\n if sum > 9 then\n sum ← sum + 6\n vD[i*4:i*4+3] ← sum[3:0]\nend\nif PS then\n apply_sign_to_vD()\nend", "example": "vbcdadd vd, va, vb, 0" }, { "mnemonic": "dtstsfi", "architecture": "PowerISA", "full_name": "Decimal Test Significance Immediate", "summary": "Tests the significance of a decimal floating-point value in FPR[FRB] against an immediate value UIM.", "syntax": "dtstsfi BF, U, FRB", "encoding": { "format": "X-form", "binary_pattern": "59 | BF | / | U | FRB | 675", "hex_opcode": "0xEC000546", "visual_parts": [ { "raw": "59", "clean": "59" }, { "raw": "BF", "clean": "BF" }, { "raw": "/", "clean": "/" }, { "raw": "U", "clean": "U" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "675", "clean": "675" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "BF", "desc": "CR Field" }, { "name": "U", "desc": "Imm" }, { "name": "FRB", "desc": "Source" }, { "name": "UIM", "desc": "Immediate Reference Significance" } ], "extension": "Decimal Floating-Point", "description": "The instruction compares the number of significant digits (NSDb) of the DFP value in FPR[FRB] with the reference significance specified by UIM. The result is placed into CR field BF and FPCC.", "pseudocode": "NSDb <- number of significant digits in FPR[FRB]\nif UIM != 0 and UIM < NSDb then\n CR[BF] <- 0b0010\n FPCC <- 0b0010\nelse if UIM != 0 and UIM > NSDb or UIM = 0 then\n CR[BF] <- 0b0100\n FPCC <- 0b0100\nelse if UIM != 0 and UIM = NSDb then\n CR[BF] <- 0b1000\n FPCC <- 0b1000\nelse\n CR[BF] <- 0b0001\n FPCC <- 0b0001", "special_registers": "CR, FPSCR", "page_found": "Page 248 - 250", "programming_notes": "The dtstsfi instruction is used to compare the number of significant digits in a DFP value with a specified reference significance. Ensure that the UIM (Upper Immediate) is correctly set according to the desired comparison. This instruction operates at the problem state and may raise exceptions if the FPR[FRB] contains an invalid DFP value. Performance can be optimized by minimizing the use of this instruction in critical loops due to its dependency on floating-point operations.", "example": "dtstsfi cr0, 0, f3" }, { "mnemonic": "dtstsfiq", "architecture": "PowerISA", "full_name": "Decimal Test Significance Immediate Quad", "summary": "Tests DFP Quad significance.", "syntax": "dtstsfiq BF, U, FRB", "encoding": { "format": "X-form", "binary_pattern": "63 | BF | / | U | FRB | 675", "hex_opcode": "0xFC000546", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "BF", "clean": "BF" }, { "raw": "/", "clean": "/" }, { "raw": "U", "clean": "U" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "675", "clean": "675" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "BF", "desc": "CR Field" }, { "name": "U", "desc": "Imm" }, { "name": "FRB", "desc": "Source" } ], "extension": "Decimal Floating-Point", "description": "Tests the significance of a Decimal Floating-Point Quad-precision operand based on the immediate value U and updates the specified condition register field. The result indicates whether the value is zero, subnormal, normal, or special (infinity/NaN). Requires the Decimal Floating-Point facility and updates the target CR field.", "pseudocode": "if isSpecial(FRB[0:127]) then\n CR[BF*4:BF*4+3] ← test_special(FRB[0:127], U)\nelif isZero(FRB[0:127]) then\n CR[BF*4:BF*4+3] ← 0b0100\nelif isSubnormal(FRB[0:127]) then\n CR[BF*4:BF*4+3] ← 0b0010\nelse\n CR[BF*4:BF*4+3] ← 0b0001\nend", "page_found": "Page 249", "special_registers": "FPSCR", "programming_notes": "The dtstsfiq instruction is used to compare the number of significant digits in a DFP value with an immediate reference significance. Ensure that the UIM (immediate reference significance) is correctly set according to your comparison needs. The result is stored in both the condition register field BF and the FPSCR's FPCC field, allowing for easy conditional branching based on the comparison outcome.", "example": "dtstsfiq cr0, 0, f3" }, { "mnemonic": "cmpeqb", "architecture": "PowerISA", "full_name": "Compare Equal Byte", "summary": "Compares the contents of bits 56:63 of register RA with each byte in register RB and sets the condition register field BF.", "syntax": "cmpeqb RA, RS, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 224 | /", "hex_opcode": "0x7C0001C0", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "224", "clean": "224" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RA", "desc": "Target GPR" }, { "name": "RS", "desc": "Src A" }, { "name": "RB", "desc": "Src B" }, { "name": "BF", "desc": "Condition Register Field" } ], "extension": "Base", "description": "Compares the least significant byte of register RS (bits 56:63) against each of the eight bytes in register RB, setting a byte in register RA to 0xFF where a match occurs and 0x00 where no match occurs. The instruction does not update condition registers directly but produces a byte-mask result in RA.", "pseudocode": "search_byte ← RS[56:63]\nfor i in 0 to 7 do\n if RB[i*8:i*8+7] = search_byte then\n RA[i*8:i*8+7] ← 0xFF\n else\n RA[i*8:i*8+7] ← 0x00\n end\nend", "special_registers": "CR", "programming_notes": "cmpeqb is useful for implementing character typing functions such as isspace() that are implemented by comparing the character to 1 or more values. A function such as isspace() can be implemented by loading the 6 byte codes corresponding to characters considered as whitespace (HT, LF, VT, FF, CR, and SP) and using the cmpeqb to compare the subject character to those 6 values to determine if any match occurs.", "page_found": "Page 128 - 130", "example": "cmpeqb r4, r3, r5" }, { "mnemonic": "cmpb", "architecture": "PowerISA", "full_name": "Compare Bytes", "summary": "Compares bytes in two GPRs, result is byte mask.", "syntax": "cmpb RA, RS, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 508 | /", "hex_opcode": "0x7C0003F8", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "508", "clean": "508" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target GPR" }, { "name": "RS", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Base", "description": "Compares each byte of register RS with the corresponding byte in register RB and stores a byte-mask result in register RA. For each byte, 0xFF is written to RA if the bytes are equal, and 0x00 is written if they differ. No condition register fields are updated.", "pseudocode": "for i in 0 to 7 do\n if RS[i*8:i*8+7] = RB[i*8:i*8+7] then\n RA[i*8:i*8+7] ← 0xFF\n else\n RA[i*8:i*8+7] ← 0x00\n end\nend", "programming_notes": "The cmpb instruction is useful for performing byte-wise comparisons between two registers. Ensure that the input registers (RS and RB) are properly aligned to avoid unexpected results. The output register (RA) will contain 0xFF in bytes where the comparison was equal, and 0x00 elsewhere. This instruction operates at user privilege level.", "example": "cmpb r4, r3, r5" }, { "mnemonic": "prtyw", "architecture": "PowerISA", "full_name": "Parity Word", "summary": "Calculates parity of a word (Scalar).", "syntax": "prtyw RA, RS", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | / | 154 | /", "hex_opcode": "0x7C000134", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "/", "clean": "/" }, { "raw": "154", "clean": "154" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "RS", "desc": "Source" } ], "extension": "Base", "description": "Computes the parity of the entire 32-bit word in register RS by XORing all 32 bits and stores the result (a single bit) in the low bit of register RA. All other bits of RA are cleared to zero. No condition registers or status fields are affected.", "pseudocode": "parity_bit ← 0\nfor i in 0 to 31 do\n parity_bit ← parity_bit XOR RS[i]\nend\nRA ← (0 || parity_bit)", "programming_notes": "The prtyw instruction is useful for calculating the parity of each byte in a doubleword, which can be helpful in error detection. Ensure that the input register (RS) contains valid data; otherwise, the output may not reflect meaningful parity information. This instruction operates at user privilege level and does not generate exceptions under normal conditions.", "example": "prtyw r4, r3" }, { "mnemonic": "prtyd", "architecture": "PowerISA", "full_name": "Parity Doubleword", "summary": "Calculates parity of a doubleword (Scalar).", "syntax": "prtyd RA, RS", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | / | 186 | /", "hex_opcode": "0x7C000174", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "/", "clean": "/" }, { "raw": "186", "clean": "186" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "RS", "desc": "Source" }, { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RB", "desc": "Source General Purpose Register" } ], "extension": "Base", "special_registers": "CR0, XER", "page_found": "Page 1379 - 1380", "description": "Computes the parity of the entire 64-bit doubleword in register RS by XORing all 64 bits and stores the result (a single bit) in the low bit of register RA. All other bits of RA are cleared to zero. No condition registers or status fields are affected.", "pseudocode": "parity_bit ← 0\nfor i in 0 to 63 do\n parity_bit ← parity_bit XOR RS[i]\nend\nRA ← (0b0000000000000000000000000000000000000000000000000000000000000 || parity_bit)", "programming_notes": "The prtyd instruction is useful for parity checking on doubleword values. It sets the least significant bit of RA based on the parity of each byte in RS, which can be helpful for error detection. Ensure that RS and RA are properly aligned to avoid unexpected behavior. This instruction operates at user privilege level.", "example": "prtyd r4, r3" }, { "mnemonic": "modsw", "architecture": "PowerISA", "full_name": "Modulo Signed Word", "summary": "Calculates remainder of signed word division.", "syntax": "modsw RT, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | RA | RB | 779 | /", "hex_opcode": "0x7C000616", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "779", "clean": "779" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RA", "desc": "Dividend" }, { "name": "RB", "desc": "Divisor" } ], "extension": "Base", "description": "The 32-bit dividend is (RA)32:63. The 32-bit divisor is (RB)32:63. The 32-bit remainder of the dividend divided by the divisor is placed into RT32:63. The contents of RT0:31 are undefined.", "pseudocode": "dividend = (RA)32:63\n divisor = (RB)32:63\n if dividend >= 0 then\n quotient = floor(dividend / divisor)\n else\n quotient = ceil(dividend / divisor)\n RT32:63 <- dividend - (quotient * divisor)\n RT0:31 <- undefined", "programming_notes": "If an attempt is made to perform any of the divisions 0x8000_0000 % -1 or % 0, then the contents of register RT are undefined.", "page_found": "Page 118 - 120", "example": "modsw r3, r4, r5" }, { "mnemonic": "moduw", "architecture": "PowerISA", "full_name": "Modulo Unsigned Word", "summary": "Calculates remainder of unsigned word division.", "syntax": "moduw RT, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | RA | RB | 267 | /", "hex_opcode": "0x7C000216", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "267", "clean": "267" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RA", "desc": "Dividend" }, { "name": "RB", "desc": "Divisor" } ], "extension": "Base", "description": "Calculates the unsigned remainder (modulo) of a 32-bit word division, storing the result in RT. The dividend is in RA and the divisor is in RB. No status flags are affected; division by zero is not trapped and produces undefined results.", "pseudocode": "RT ← (RA mod RB)", "page_found": "Page 119", "programming_notes": "The moduw instruction is used for performing modulo operations on unsigned integers. Ensure the divisor in RB32:63 is not zero to avoid division by zero exceptions. The result is placed in RT32:63, while RT0:31 remains undefined and should not be relied upon.", "example": "moduw r3, r4, r5" }, { "mnemonic": "modsd", "architecture": "PowerISA", "full_name": "Modulo Signed Doubleword", "summary": "Calculates remainder of signed doubleword division.", "syntax": "modsd RT, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | RA | RB | 777 | /", "hex_opcode": "0x7C000612", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "777", "clean": "777" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RA", "desc": "Dividend" }, { "name": "RB", "desc": "Divisor" } ], "extension": "Base", "description": "The 64-bit dividend is (RA). The 64-bit divisor is (RB). The 64-bit remainder of the dividend divided by the divisor is placed into register RT. The quotient is not supplied as a result. Both operands and the remainder are interpreted as signed integers. The remainder is the unique signed integer that satisfies remainder = dividend - (quotient × divisor) where 0 ≤remainder < |divisor| if the dividend is nonnegative, and -|divisor| < remainder ≤0 if the dividend is negative.", "pseudocode": "dividend ← (RA)\ndivisor ← (RB)\nRT ← dividend % divisor", "programming_notes": "If an attempt is made to perform any of the divisions % 0 or 0x8000_0000_0000_0000 % -1, then the contents of register RT are undefined.", "page_found": "Page 124 - 126", "example": "modsd r3, r4, r5" }, { "mnemonic": "modud", "architecture": "PowerISA", "full_name": "Modulo Unsigned Doubleword", "summary": "Calculates remainder of unsigned doubleword division.", "syntax": "modud RT, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | RA | RB | 265 | /", "hex_opcode": "0x7C000212", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "265", "clean": "265" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RA", "desc": "Dividend" }, { "name": "RB", "desc": "Divisor" } ], "extension": "Base", "description": "Calculates the unsigned remainder (modulo) of a 64-bit doubleword division, storing the result in RT. The dividend is in RA and the divisor is in RB. No status flags are affected; division by zero is not trapped and produces undefined results.", "pseudocode": "RT ← (RA mod RB)", "page_found": "Page 125", "programming_notes": "The modud instruction is used for performing an unsigned doubleword modulo operation. Ensure that the divisor in register RB is not zero to avoid undefined behavior. The result is placed in register RT, and this instruction operates at user privilege level.", "example": "modud r3, r4, r5" }, { "mnemonic": "ftdiv", "architecture": "PowerISA", "full_name": "Float Test for Divide", "summary": "Tests the double-precision floating-point operand in register FRB and sets flags based on certain conditions.", "syntax": "ftdiv BF, FRA, FRB", "encoding": { "format": "X-form", "binary_pattern": "63 | BF | / | FRA | FRB | 128 | /", "hex_opcode": "0xFC000100", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "BF", "clean": "BF" }, { "raw": "/", "clean": "/" }, { "raw": "FRA", "clean": "FRA" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "128", "clean": "128" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:8 | 9:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "BF", "desc": "CR Field" }, { "name": "FRA", "desc": "A" }, { "name": "FRB", "desc": "B" } ], "extension": "Floating-Point", "description": "This instruction tests the double-precision floating-point operand in register FRB and sets flags based on certain conditions related to its value and exponent. The CR field BF is updated accordingly.", "pseudocode": "Let e_a be the unbiased exponent of the double-precision floating-point operand in register FRA.\nLet e_b be the unbiased exponent of the double-precision floating-point operand in register FRB.\n\nfe_flag is set to 1 if any of the following conditions occur:\n• The double-precision floating-point operand in register FRA is a NaN or an Infinity.\n• The double-precision floating-point operand in register FRB is a Zero, a NaN, or an Infinity.\n• e_b is less than or equal to -1022.\n• e_b is greater than or equal to 1021.\n• The double-precision floating-point operand in register FRA is not a zero and the difference, e_a - e_b, is greater than or equal to 1023.\n• The double-precision floating-point operand in register FRA is not a zero and the difference, e_a - e_b, is less than or equal to -1021.\n• The double-precision floating-point operand in register FRA is not a zero and e_a is less than or equal to -970.\n\nOtherwise fe_flag is set to 0.\n\ngf_flag is set to 1 if the following condition occurs:\n• The double-precision floating-point operand in register FRB is a Zero, an Infinity, or a denormalized value.\n• The double-precision floating-point operand in register FRA is an Infinity.\n\nOtherwise fg_flag is set to 0.\n\nIf the implementation guarantees a relative error of fre[s][.] of less than or equal to 2^-14, then fl_flag is set to 1. Otherwise fl_flag is set to 0.\n\nCR field BF is set to the value fl_flag || fg_flag || fe_flag || 0b0.", "special_registers": "CR, FPSCR", "programming_notes": "ftdiv and ftsqrt are provided to accelerate software emulation of divide and square root operations, by performing the requisite special case checking. Software needs only a single branch, on FE=1 (in CR[BF]), to a special case handler. FG and FL may provide further acceleration opportunities.", "page_found": "Page 202 - 204", "example": "ftdiv cr0, f2, f3" }, { "mnemonic": "ftsqrt", "architecture": "PowerISA", "full_name": "Float Test for Square Root", "summary": "Tests for conditions that would cause a sqrt exception.", "syntax": "ftsqrt BF, FRB", "encoding": { "format": "X-form", "binary_pattern": "63 | BF | / | 0 | FRB | 160 | /", "hex_opcode": "0xFC000140", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "BF", "clean": "BF" }, { "raw": "/", "clean": "/" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "160", "clean": "160" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:8 | 9:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "BF", "desc": "CR Field" }, { "name": "FRB", "desc": "Source" } ], "extension": "Floating-Point", "description": "Tests the floating-point value in FRB to determine if it would cause an exception when used as the operand to a square root instruction, setting the condition bits in CR field BF accordingly. The result encodes whether the operand is negative, zero, positive, or a special value (NaN, infinity). No floating-point result is produced and FPSCR is not modified.", "pseudocode": "if FRB < 0.0 then\n CR[BF] ← 0b1000\nelse if FRB = 0.0 then\n CR[BF] ← 0b0100\nelse if FRB > 0.0 then\n CR[BF] ← 0b0010\nelse\n CR[BF] ← 0b0001", "page_found": "Page 203", "special_registers": "FPSCR", "programming_notes": "The ftsqrt instruction is useful for checking special conditions of a floating-point number before performing square root operations. It sets the FE flag if the operand is zero, NaN, infinity, negative, or has an exponent less than or equal to -970. The FG flag is set if the operand is zero, infinity, or denormalized. Ensure the operand is properly aligned and in double-precision format to avoid unexpected results.", "example": "ftsqrt cr0, f3" }, { "mnemonic": "fre", "architecture": "PowerISA", "full_name": "Floating Reciprocal Estimate", "summary": "Estimates the reciprocal of a floating-point operand.", "syntax": "fre FRT,FRB", "encoding": { "format": "A-form", "binary_pattern": "63 | FRT | 0 | 0 | FRB | 24 | /", "hex_opcode": "0xFC000030", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "24", "clean": "24" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" } ], "extension": "Floating-Point", "description": "An estimate of the reciprocal of the floating-point operand in register FRB is placed into register FRT. Unless the reciprocal would be a zero, an infinity, the result of a trap-disabled Overflow exception, or a QNaN, the estimate is correct to a precision of one part in 256 of the reciprocal of (FRB).", "special_registers": "FPSCR (FPRF, FX, OX, UX, ZX, VXSNAN), CR1 (if Rc=1)", "programming_notes": "For the Floating-Point Estimate instructions, some implementations might implement a precision higher than the minimum architected precision.", "page_found": "Page 200 - 202", "pseudocode": "if 'fre' then\n FRT <- estimate(1 / (FRB))\nelse if 'fre.' then\n FRT <- estimate(1 / (FRB))\n CR1 <- result_class(FRT)", "example": "fre f1, f3" }, { "mnemonic": "fres", "architecture": "PowerISA", "full_name": "Floating Reciprocal Estimate Single", "summary": "Estimates the reciprocal of a single-precision floating-point number.", "syntax": "fres FRT, FRB", "encoding": { "format": "A-form", "binary_pattern": "59 | FRT | 0 | 0 | FRB | 24 | /", "hex_opcode": "0xEC000030", "visual_parts": [ { "raw": "59", "clean": "59" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "24", "clean": "24" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" }, { "name": "FT", "desc": "Target Floating-Point Register" }, { "name": "FB", "desc": "Source Floating-Point Register" } ], "extension": "Floating-Point", "description": "Computes an estimate of the reciprocal (1/x) of the single-precision floating-point value in FRB and stores the result in FRT. The estimate is accurate to approximately 1 part in 256 for normalized values. If Rc=1, CR1 is set based on the result; FPSCR exception bits are set according to the floating-point exception enable controls.", "pseudocode": "FRT ← estimate(1.0 / FRB)\nif Rc = 1 then\n CR1 ← (FRT_exception_summary)", "special_registers": "FPSCR, CR0", "page_found": "Page 174 - 175", "programming_notes": "The fres instruction provides a fast estimate of the reciprocal for single-precision floating-point numbers. It's useful in performance-critical applications where exact precision is not required, but speed is essential. Be cautious with inputs that have an unbiased exponent greater than +127, as they are treated as Infinity, which might lead to unexpected results if not handled properly.", "example": "fres f1, f3" }, { "mnemonic": "frsqrte", "architecture": "PowerISA", "full_name": "Floating Reciprocal Square Root Estimate", "summary": "Estimates the reciprocal of the square root of a floating-point operand.", "syntax": "frsqrte FRT,FRB", "encoding": { "format": "A-form", "binary_pattern": "63 | FRT | 0 | 0 | FRB | 26 | /", "hex_opcode": "0xFC000034", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "26", "clean": "26" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" } ], "extension": "Floating-Point", "description": "A estimate of the reciprocal of the square root of the floating-point operand in register FRB is placed into register FRT. The estimate placed into register FRT is correct to a precision of one part in 32 of the reciprocal of the square root of (FRB).", "special_registers": "FPSCR, CR1", "page_found": "Page 201 - 202", "pseudocode": "FRT ← estimate(1 / √FRB)", "programming_notes": "The frsqrte instruction provides a fast, approximate reciprocal square root calculation. It is useful for performance-critical applications where precision can be traded for speed. Ensure the input in FRB is positive to avoid undefined behavior. The result may need refinement for higher precision applications.", "example": "frsqrte f1, f3" }, { "mnemonic": "frsqrtes", "architecture": "PowerISA", "full_name": "Floating Reciprocal Square Root Estimate Single", "summary": "Estimates 1/sqrt(x) (Single Precision).", "syntax": "frsqrtes FRT, FRB", "encoding": { "format": "A-form", "binary_pattern": "59 | FRT | 0 | 0 | FRB | 26 | /", "hex_opcode": "0xEC000034", "visual_parts": [ { "raw": "59", "clean": "59" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "26", "clean": "26" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:30 | 31", "length": "32" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" } ], "extension": "Floating-Point", "description": "Computes an estimate of the reciprocal of the square root (1/sqrt(x)) of the single-precision floating-point value in FRB and stores the result in FRT. The estimate is accurate to approximately 1 part in 256 for normalized positive values. If Rc=1, CR1 is set based on the result; FPSCR exception bits are set according to floating-point exception enable controls.", "pseudocode": "FRT ← estimate(1.0 / sqrt(FRB))\nif Rc = 1 then\n CR1 ← (FRT_exception_summary)", "page_found": "Page 202", "special_registers": "FPSCR", "programming_notes": "The frsqrtes instruction provides a fast estimate of the reciprocal square root, suitable for performance-critical applications where precision is less critical than speed. Be aware that it may raise exceptions for special values like NaN or infinity, and results are only accurate to within one part in 32 of the true value.", "example": "frsqrtes f1, f3" }, { "mnemonic": "rfebb", "architecture": "PowerISA", "full_name": "Return From Event-Based Branch", "summary": "Returns control to the address specified by EBBRR0:61 || 0b00 or 320 || EBBRR32:61 || 0b00, depending on MSRSF.", "syntax": "rfebb S", "encoding": { "format": "XL-form", "binary_pattern": "0 | 6 | 11 | 16 | 20 | 21 | 31", "hex_opcode": "0x4C000124", "visual_parts": [ { "raw": "19", "clean": "19" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "S", "clean": "S" }, { "raw": "146", "clean": "146" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0 | 6 | 11 | 16 | 20 | 21 | 31" }, "operands": [ { "name": "S", "desc": "State" } ], "extension": "Base", "description": "The instruction sets BESCRGE to S and updates NIA based on the event-based branch facility's state. If there are no pending exceptions, it fetches the next instruction from a specific address; otherwise, it generates an event-based branch.", "pseudocode": "if 'rfebb' then\n BESCRGE <- S\n if MSRSF=1 then\n NIA <- iea EBBRR0:61 || 0b00\n else\n NIA <- 320 || EBBRR32:61 || 0b00", "special_registers": "BESCR, MSR, NIA, EBBRR", "programming_notes": "rfebb serves as both a basic and an extended mnemonic. The Assembler will recognize an rfebb mnemonic with one operand as the basic form, and an rfebb mnemonic with no operand as the intended form. In the extended form, the S operand is omitted and assumed to be 1.", "extended_mnemonics": [ "rfebb" ], "page_found": "Page 1072 - 1073", "example": "rfebb 0" }, { "mnemonic": "setb", "architecture": "PowerISA", "full_name": "Set Boolean", "summary": "Sets the target register based on the condition register field BFA.", "syntax": "setb RT, BFA", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | BFA | / | 128 | /", "hex_opcode": "0x7C000100", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "BFA", "clean": "BFA" }, { "raw": "/", "clean": "/" }, { "raw": "128", "clean": "128" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "BFA", "desc": "CR Field" } ], "extension": "Base", "description": "If bit 0 of CR field BFA is set to 1, the contents of register RT are set to 0xFFFF_FFFF_FFFF_FFFF. If bit 1 of CR field BFA is set to 1, the contents of register RT are set to 0x0000_0000_0000_0001. Otherwise, the contents of register RT are set to 0x0000_0000_0000_0000.", "pseudocode": "if CR4×BFA+32=1 then\n RT ←0xFFFF_FFFF_FFFF_FFFF\nelse if CR4×BFA+33=1 then\n RT ←0x0000_0000_0000_0001\nelse\n RT ←0x0000_0000_0000_0000", "special_registers": "CR, RT", "page_found": "Page 166 - 168", "programming_notes": "The setb instruction is commonly used to conditionally set a register based on the state of specific bits in the CR (Condition Register). Ensure that the BFA field correctly reflects the desired condition before executing this instruction. This instruction operates at user privilege level and does not generate exceptions under normal conditions.", "example": "setb r3, cr1" }, { "mnemonic": "divde", "architecture": "PowerISA", "full_name": "Divide Doubleword Extended", "summary": "Divides the contents of two registers and updates the condition register.", "syntax": "divde RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "31 | RT | RA | RB | OE | 425 | Rc", "hex_opcode": "0x7C000352", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "OE", "clean": "OE" }, { "raw": "425", "clean": "425" }, { "raw": "Rc", "clean": "Rc" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21 | 22:30 | 31" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RA", "desc": "Dividend" }, { "name": "RB", "desc": "Divisor" } ], "extension": "Base", "description": "For divde, the quotient of the contents of register RA (dividend) divided by RB (divisor) is placed into register RT. The operands are interpreted as signed integers.", "pseudocode": "if 'divde' then\n RT <- (RA) ÷ (RB)", "special_registers": "CR0, XER", "page_found": "Page 123 - 124", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.", "example": "divde r3, r4, r5" }, { "mnemonic": "divdeu", "architecture": "PowerISA", "full_name": "Divide Doubleword Extended Unsigned", "summary": "64-bit extended unsigned division.", "syntax": "divdeu RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "31 | RT | RA | RB | OE | 393 | Rc", "hex_opcode": "0x7C000312", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "OE", "clean": "OE" }, { "raw": "393", "clean": "393" }, { "raw": "Rc", "clean": "Rc" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21 | 22:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RA", "desc": "Dividend" }, { "name": "RB", "desc": "Divisor" } ], "extension": "Base", "description": "Performs unsigned extended division of a 128-bit dividend (RA || R0) by the 64-bit unsigned divisor in RB, placing the 64-bit quotient in RT. If OE=1 and overflow occurs, the OV bit in XER is set; if Rc=1, CR0 is set based on the quotient. Division by zero produces undefined results.", "pseudocode": "dividend ← (RA || 0) # 128-bit value: RA in high 64 bits, 0 in low 64 bits\nRT ← dividend / RB\nif OE = 1 then\n XER[OV] ← overflow_flag\nif Rc = 1 then\n CR0 ← (RT_comparison_summary)", "page_found": "Page 124", "special_registers": "CR0", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.", "example": "divdeu r3, r4, r5" }, { "mnemonic": "divwe", "architecture": "PowerISA", "full_name": "Divide Word Extended", "summary": "Performs a signed division of a 64-bit dividend by a 32-bit divisor and places the result in a 32-bit register.", "syntax": "divwe RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "31 | RT | RA | RB | OE | 427 | Rc", "hex_opcode": "0x7C000356", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "OE", "clean": "OE" }, { "raw": "427", "clean": "427" }, { "raw": "Rc", "clean": "Rc" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21 | 22:30 | 31" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RA", "desc": "Dividend" }, { "name": "RB", "desc": "Divisor" } ], "extension": "Base", "description": "The 64-bit dividend is formed from the upper 32 bits of RA (RA32:63) concatenated with 320. The 32-bit divisor is taken from RB (RB32:63). If the quotient can be represented in 32 bits, it is placed into RT32:63. The contents of RT0:31 are undefined.", "pseudocode": "if 'divwe' then\n dividend0:63 ← (RA)32:63 || 320\n divisor0:31 ← (RB)32:63\n RT32:63 ← dividend ÷ divisor\n RT0:31 ← undefined", "special_registers": "CR0, XER", "page_found": "Page 116 - 118", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.", "example": "divwe r3, r4, r5" }, { "mnemonic": "divweu", "architecture": "PowerISA", "full_name": "Divide Word Extended Unsigned", "summary": "Performs an unsigned division of a 64-bit dividend by a 32-bit divisor and returns the quotient in a 32-bit register.", "syntax": "divweu RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "31 | RT | RA | RB | OE | 395 | Rc", "hex_opcode": "0x7C000316", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "OE", "clean": "OE" }, { "raw": "395", "clean": "395" }, { "raw": "Rc", "clean": "Rc" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21 | 22:30 | 31" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RA", "desc": "Dividend" }, { "name": "RB", "desc": "Divisor" } ], "extension": "Base", "description": "Performs unsigned extended division of a 64-bit dividend (RA || R0) by the 32-bit unsigned divisor in RB, placing the 32-bit quotient in RT. If OE=1 and overflow occurs, the OV bit in XER is set; if Rc=1, CR0 is set based on the quotient. Division by zero produces undefined results.", "pseudocode": "dividend ← (RA || 0) # 64-bit value: RA in high 32 bits, 0 in low 32 bits\nRT ← dividend / RB\nif OE = 1 then\n XER[OV] ← overflow_flag\nif Rc = 1 then\n CR0 ← (RT_comparison_summary)", "special_registers": "CR0, XER", "page_found": "Page 117 - 118", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.", "example": "divweu r3, r4, r5" }, { "mnemonic": "vand", "architecture": "PowerISA", "full_name": "Vector Logical AND VX-form", "summary": "Performs a bitwise AND operation on the contents of two vector registers and stores the result in another vector register.", "syntax": "vand vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 1028", "hex_opcode": "0x10000404", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1028", "clean": "1028" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "Performs a bitwise logical AND of the 128-bit contents of vector registers vA and vB, storing the 128-bit result in vector register vD. This operation is performed element-independently across all bits without regard to element boundaries. No status flags are affected.", "pseudocode": "vD ← vA & vB", "page_found": "Page 427 - 428", "special_registers": "MSR", "programming_notes": "The vand instruction requires the vector facility to be enabled (MSR.VEC=1); otherwise, it will raise a Vector_Unavailable exception. Ensure that the vector registers are properly aligned and initialized before performing operations.", "example": "vand vd, va, vb" }, { "mnemonic": "vor", "architecture": "PowerISA", "full_name": "Vector OR", "summary": "Bitwise OR of two 128-bit vectors.", "syntax": "vor vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 1156", "hex_opcode": "0x10000484", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1156", "clean": "1156" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Performs a bitwise OR of two 128-bit vector registers and stores the result in a third vector register. Each bit position of the result is set if the corresponding bit in either input vector is set. No status flags are affected.", "pseudocode": "vD ← vA | vB", "page_found": "Page 429", "special_registers": "MSR", "programming_notes": "The vor instruction requires the Vector Facility to be enabled in the MSR register; otherwise, it will raise a Vector Unavailable exception. Ensure that the vector registers involved are properly aligned and contain valid data for accurate results.", "example": "vor vd, va, vb" }, { "mnemonic": "vxor", "architecture": "PowerISA", "full_name": "Vector XOR", "summary": "Bitwise XOR of two 128-bit vectors.", "syntax": "vxor vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 1220", "hex_opcode": "0x100004C4", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1220", "clean": "1220" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Performs a bitwise XOR (exclusive OR) of two 128-bit vector registers and stores the result in a third vector register. Each bit position of the result is set if the corresponding bits in the two input vectors differ. No status flags are affected.", "pseudocode": "vD ← vA ^ vB", "page_found": "Page 430", "special_registers": "MSR", "programming_notes": "The vxor instruction is used to perform a bitwise XOR operation on two vector registers and store the result in another. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. This instruction operates on 128-bit vector registers.", "example": "vxor vd, va, vb" }, { "mnemonic": "vnor", "architecture": "PowerISA", "full_name": "Vector NOR", "summary": "Performs a logical NOR operation on the contents of two vector registers and stores the result in another vector register.", "syntax": "vnor vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 1284", "hex_opcode": "0x10000504", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1284", "clean": "1284" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "The contents of VSR[VRA+32] are ORed with the contents of VSR[VRB+32], and the complemented result is placed into VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nelse\n VSR[VRT+32] ←¬( VSR[VRA+32] | VSR[VRB+32] )", "extended_mnemonics": [ { "mnemonic": "vnot", "equivalent_to": "vnor Vx,Vy,Vy" } ], "page_found": "Page 429 - 430", "special_registers": "MSR", "programming_notes": "The vnor instruction performs a bitwise NOR operation on two vector registers and stores the result in another register. Ensure that the Vector Facility is enabled by checking and setting the MSR.VEC bit; otherwise, a Vector_Unavailable exception will be raised. This instruction operates at the user privilege level.", "example": "vnor vd, va, vb" }, { "mnemonic": "vandc", "architecture": "PowerISA", "full_name": "Vector AND with Complement", "summary": "Bitwise AND of vA with the ones' complement of vB (vA & ~vB).", "syntax": "vandc vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 1092", "hex_opcode": "0x10000444", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1092", "clean": "1092" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Performs a bitwise AND of vA with the ones' complement of vB, effectively computing vA & ~vB, and stores the result in vD. Each bit is set in the result only if it is set in vA and clear in vB. No status flags are affected.", "pseudocode": "vD ← vA & ~vB", "page_found": "Page 428", "special_registers": "MSR", "programming_notes": "The vandc instruction requires the Vector Facility to be enabled; otherwise, it will raise an exception. Ensure that the MSR.VEC bit is set before using this instruction. This operation is useful for masking bits where you want to retain certain bits while complementing others.", "example": "vandc vd, va, vb" }, { "mnemonic": "vcmpequb", "architecture": "PowerISA", "full_name": "Vector Compare Equal Byte", "summary": "Compares two vector registers element by element as unsigned bytes and sets the target vector register based on the comparison.", "syntax": "vcmpequb VRT,VRA,VRB", "encoding": { "format": "VC-form", "binary_pattern": "18 | VRT | VRA | VRB | Rc", "hex_opcode": "0x10000006", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "6", "clean": "6" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "The Vector Integer Compare instructions compare two VSRs element by element, interpreting the elements as unsigned or signed integers depending on the instruction, and set the corresponding element of the target VSR to all 1s if the relation being tested is true and to all 0s if the relation being tested is false.", "pseudocode": "if MSR.VEC=0 then Vector_Unavailable()\nall_true ←1\nall_false ←1\ndo i = 0 to 15\n src1 ←VSR[VRA+32].byte[i]\n src2 ←VSR[VRB+32].byte[i]\n if src1 = src2 then do\n VSR[VRT+32].byte[i] ←0xFF\n all_false ←0\n end\n else do\n VSR[VRT+32].byte[i] ←0x00\n all_true ←0\n end\nend\nif Rc=1 then\n CR.field[6] ←all_true || 0b0 || all_false || 0b0", "special_registers": "CR6", "programming_notes": "vcmpequb[.], vcmpequh[.], vcmpequw[.], and vcmpequd[.] can be used for unsigned or signed integers.", "page_found": "Page 413 - 414", "example": "vcmpequb v1, v2, v3" }, { "mnemonic": "vcmpequh", "architecture": "PowerISA", "full_name": "Vector Compare Equal Halfword", "summary": "Compares each halfword of two vector registers and sets the corresponding halfword in the target register to all 1s if they are equal, otherwise all 0s.", "syntax": "vcmpequh VRT,VRA,VRB", "encoding": { "format": "VC-form", "binary_pattern": "4 | VRT | VRA | VRB | Rc", "hex_opcode": "0x10000046", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "70", "clean": "70" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vcmpequh, each halfword of VSR[VRA+32] is compared with the corresponding halfword of VSR[VRB+32]. If they are equal, the corresponding halfword in VSR[VRT+32] is set to all 1s (0xFFFF); otherwise, it is set to all 0s (0x0000).", "pseudocode": "if MSR.VEC=0 then Vector_Unavailable()\n\nall_true ←1\nall_false ←1\ndo i = 0 to 7\n src1 ←VSR[VRA+32].hword[i]\n src2 ←VSR[VRB+32].hword[i]\n if src1 = src2 then do\n VSR[VRT+32].hword[i] ←0xFFFF\n all_false ←0\n end\n else do\n VSR[VRT+32].hword[i] ←0x0000\n all_true ←0\n end\nend\ndo i = 0 to 7\n src1 ←VSR[VRA+32].hword[i]\n src2 ←VSR[VRB+32].hword[i]\n if src1 = src2 then do\n VSR[VRT+32].hword[i] ←0xFFFF\n all_false ←0\n end\n else do\n VSR[VRT+32].hword[i] ←0x0000\n all_true ←0\n end\nend\nif Rc=1 then\n CR.field[6] ←all_true || 0b0 || all_false || 0b0", "special_registers": "CR6", "page_found": "Page 414 - 415", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "vcmpequh v1, v2, v3" }, { "mnemonic": "vcmpequd", "architecture": "PowerISA", "full_name": "Vector Compare Equal Doubleword", "summary": "Compares two vector registers for equality on an unsigned doubleword basis and stores the result in a third vector register.", "syntax": "vcmpequd VRT,VRA,VRB", "encoding": { "format": "VC-form", "binary_pattern": "4 | VRT | VRA | VRB | Rc | 199", "hex_opcode": "0x100000C7", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "199", "clean": "199" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21 | 22:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "Compares two vector registers element-wise for equality on an unsigned doubleword basis (2 64-bit elements) and stores a mask in the destination vector register, with all 1s where elements are equal and all 0s where unequal. When the record bit (.) is set, the CR6 field is updated to reflect whether any or all comparisons are equal.", "pseudocode": "for i in 0 to 1 do\n if VRA[i] = VRB[i] then\n VRT[i] ← 0xFFFF_FFFF_FFFF_FFFF\n else\n VRT[i] ← 0x0000_0000_0000_0000\nif Rc = 1 then CR6 ← comparison results", "special_registers": "CR6", "page_found": "Page 416 - 417", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "vcmpequd v1, v2, v3" }, { "mnemonic": "vcmpgtub", "architecture": "PowerISA", "full_name": "Vector Compare Greater Than Unsigned Byte", "summary": "Unsigned > comparison for 16 bytes.", "syntax": "vcmpgtub vD, vA, vB", "encoding": { "format": "VC-form", "binary_pattern": "4 | vD | vA | vB | 518", "hex_opcode": "0x10000206", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "518", "clean": "518" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Performs an unsigned greater-than comparison of two vector registers on a byte-by-byte basis (16 bytes) and stores a mask in the destination vector register, with all 1s where the comparison is true and all 0s where false. No CR or XER flags are modified by this instruction.", "pseudocode": "for i in 0 to 15 do\n if vA[i] > vB[i] (unsigned) then\n vD[i] ← 0xFF\n else\n vD[i] ← 0x00", "page_found": "Page 419", "special_registers": "MSR, CR6", "programming_notes": "vcmpgtub is useful for comparing unsigned byte values in vectors. Ensure both source vectors are properly aligned to avoid alignment faults. The instruction updates CR field 6 if Rc=1, indicating comparison results; check this for conditional logic. Performance may vary based on vector length and data distribution.", "example": "vcmpgtub vd, va, vb" }, { "mnemonic": "vcmpgtsb", "architecture": "PowerISA", "full_name": "Vector Compare Greater Than Signed Byte", "summary": "Compares each byte of two vector registers and sets the corresponding result byte to all 1s if the signed byte in the first source register is greater than the signed byte in the second source register, otherwise sets it to all 0s.", "syntax": "vcmpgtsb VRT,VRA,VRB", "encoding": { "format": "VC-form", "binary_pattern": "0 | VRT | VRA | VRB | Rc", "hex_opcode": "0x10000306", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "774", "clean": "774" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vcmpgtsb, each byte of VSR[VRA+32] is compared with the corresponding byte of VSR[VRB+32]. If the signed byte in VSR[VRA+32] is greater than the signed byte in VSR[VRB+32], then the corresponding byte in VSR[VRT+32] is set to all 1s (0xFF). Otherwise, it is set to all 0s (0x00).", "pseudocode": "if MSR.VEC=0 then Vector_Unavailable()\nall_true ←1\nall_false ←1\ndo i = 0 to 15\n src1 ←EXTS(VSR[VRA+32].byte[i])\n src2 ←EXTS(VSR[VRB+32].byte[i])\n if src1 > src2 then do\n VSR[VRT+32].byte[i] ←0xFF\n all_false ←0\n end\n else do\n VSR[VRT+32].byte[i] ←0x00\n all_true ←0\n end\nend\nif Rc=1 then\n CR.field[6] ←all_true || 0b0 || all_false || 0b0", "special_registers": "CR0, XER", "page_found": "Page 418 - 419", "extended_mnemonics": [ "vcmpgtsb." ], "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "vcmpgtsb v1, v2, v3" }, { "mnemonic": "vcmpgtuh", "architecture": "PowerISA", "full_name": "Vector Compare Greater Than Unsigned Halfword", "summary": "Unsigned > comparison for 8 halfwords.", "syntax": "vcmpgtuh vD, vA, vB", "encoding": { "format": "VC-form", "binary_pattern": "4 | vD | vA | vB | 582", "hex_opcode": "0x10000246", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "582", "clean": "582" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Performs an unsigned greater-than comparison of two vector registers on a halfword-by-halfword basis (8 halfwords) and stores a mask in the destination vector register, with all 1s where the comparison is true and all 0s where false. No CR or XER flags are modified by this instruction.", "pseudocode": "for i in 0 to 7 do\n if vA[i] > vB[i] (unsigned) then\n vD[i] ← 0xFFFF\n else\n vD[i] ← 0x0000", "page_found": "Page 420", "special_registers": "MSR, CR", "programming_notes": "The vcmpgtuh instruction is commonly used for comparing unsigned halfword elements in vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The instruction updates the CR field if Rc=1, which can be useful for conditional branching based on the comparison results.", "example": "vcmpgtuh vd, va, vb" }, { "mnemonic": "vcmpgtsh", "architecture": "PowerISA", "full_name": "Vector Compare Greater Than Signed Halfword", "summary": "Compares each halfword of two vector registers and sets the corresponding result element to all 1s if the first operand is greater than the second, otherwise all 0s.", "syntax": "vcmpgtsh VRT,VRA,VRB", "encoding": { "format": "VC-form", "binary_pattern": "0 | VRT | VRA | VRB | Rc", "hex_opcode": "0x10000346", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "838", "clean": "838" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vcmpgtsh, each halfword of VSR[VRA+32] is compared with the corresponding halfword of VSR[VRB+32]. If the signed value in VSR[VRA+32].hword[i] is greater than that in VSR[VRB+32].hword[i], then VSR[VRT+32].hword[i] is set to 0xFFFF; otherwise, it is set to 0x0000.", "pseudocode": "if MSR.VEC=0 then Vector_Unavailable()\nall_true ←1\nall_false ←1\ndo i = 0 to 7\n src1 ←EXTS(VSR[VRA+32].hword[i])\n src2 ←EXTS(VSR[VRB+32].hword[i])\n if src1 > src2 then do\n VSR[VRT+32].hword[i] ←0xFFFF\n all_false ←0\n end\n else do\n VSR[VRT+32].hword[i] ←0x0000\n all_true ←0\n end\nend\nif Rc=1 then\n CR.field[6] ←all_true || 0b0 || all_false || 0b0", "special_registers": "CR6 (if Rc=1)", "page_found": "Page 419 - 420", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "vcmpgtsh v1, v2, v3" }, { "mnemonic": "vcmpgtuw", "architecture": "PowerISA", "full_name": "Vector Compare Greater Than Unsigned Word", "summary": "Unsigned > comparison for 4 words.", "syntax": "vcmpgtuw vD, vA, vB", "encoding": { "format": "VC-form", "binary_pattern": "4 | vD | vA | vB | 646", "hex_opcode": "0x10000286", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "646", "clean": "646" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Performs an unsigned greater-than comparison of two vector registers on a word-by-word basis (4 words) and stores a mask in the destination vector register, with all 1s where the comparison is true and all 0s where false. No CR or XER flags are modified by this instruction.", "pseudocode": "for i in 0 to 3 do\n if vA[i] > vB[i] (unsigned) then\n vD[i] ← 0xFFFF_FFFF\n else\n vD[i] ← 0x0000_0000", "page_found": "Page 421", "special_registers": "MSR, CR6", "programming_notes": "This instruction is commonly used for element-wise comparison of unsigned integers in vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The result register must be aligned to 128 bits, and both source registers should contain valid data. If Rc=1, CR field 6 will reflect whether all comparisons were true or false, which can be useful for conditional branching based on vector comparison results.", "example": "vcmpgtuw vd, va, vb" }, { "mnemonic": "vcmpgtsw", "architecture": "PowerISA", "full_name": "Vector Compare Greater Than Signed Word", "summary": "Compares each word of two vector registers and sets the corresponding word in the target vector register to all 1s if the first operand is greater than the second, otherwise to all 0s.", "syntax": "vcmpgtsw VRT,VRA,VRB", "encoding": { "format": "VC-form", "binary_pattern": "4 | VRT | VRA | VRB | Rc", "hex_opcode": "0x10000386", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "902", "clean": "902" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vcmpgtsw, each word of VSR[VRA+32] is compared with the corresponding word of VSR[VRB+32]. If the signed integer value in the word element i of VSR[VRA+32] is greater than that in VSR[VRB+32], then the contents of word element i of VSR[VRT+32] are set to all 1s; otherwise, they are set to all 0s.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nall_true ←1\nall_false ←1\ndo i = 0 to 3\n src1 ←EXTS(VSR[VRA+32].word[i])\n src2 ←EXTS(VSR[VRB+32].word[i])\n if src1 > src2 then do\n VSR[VRT+32].word[i] ←0xFFFF_FFFF\n all_false ←0\n end\n else do\n VSR[VRT+32].word[i] ←0x0000_0000\n all_true ←0\n end\nend\nif Rc=1 then\n CR.field[6] ←all_true || 0b0 || all_false || 0b0", "special_registers": "CR6 (if Rc=1)", "page_found": "Page 420 - 421", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "vcmpgtsw v1, v2, v3" }, { "mnemonic": "vcmpgtud", "architecture": "PowerISA", "full_name": "Vector Compare Greater Than Unsigned Doubleword", "summary": "Compares the contents of two vector registers and sets a result based on whether each element in the first register is greater than the corresponding element in the second register.", "syntax": "vcmpgtud vD, vA, vB", "encoding": { "format": "VC-form", "binary_pattern": "4 | vD | vA | vB | 711", "hex_opcode": "0x100002C7", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "711", "clean": "711" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "pseudocode": "for i in 0 to 1 do\n if vA[i] > vB[i] (unsigned) then\n vD[i] ← 0xFFFF_FFFF_FFFF_FFFF\n else\n vD[i] ← 0x0000_0000_0000_0000", "page_found": "Page 1440 - 1441", "description": "Performs an unsigned greater-than comparison of two vector registers on a doubleword-by-doubleword basis (2 doublewords) and stores a mask in the destination vector register, with all 1s where the comparison is true and all 0s where false. No CR or XER flags are modified by this instruction.", "special_registers": "CR6", "programming_notes": "This instruction is commonly used in scenarios where you need to compare unsigned integers stored in vector registers. Ensure that the input vectors are properly aligned and that the Rc flag is set if you need to use CR6 for further conditional logic. Be aware that this instruction operates on doublewords, so each element must be 32 bits wide.", "example": "vcmpgtud vd, va, vb" }, { "mnemonic": "vcmpgtsd", "architecture": "PowerISA", "full_name": "Vector Compare Greater Than Signed Doubleword", "summary": "Compares two doublewords of signed integers and sets the result vector based on the comparison.", "syntax": "vcmpgtsd VRT,VRA,VRB", "encoding": { "format": "VC-form", "binary_pattern": "4 | VRT | VRA | VRB | Rc", "hex_opcode": "0x100003C7", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "967", "clean": "967" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vcmpgtsd, each doubleword in VSR[VRA+32] is compared to the corresponding doubleword in VSR[VRB+32]. If a doubleword in VSR[VRA+32] is greater than the corresponding doubleword in VSR[VRB+32], the corresponding doubleword in VSR[VRT+32] is set to all 1s; otherwise, it is set to all 0s.", "pseudocode": "if MSR.VEC=0 then Vector_Unavailable()\nall_true ←1\nall_false ←1\ndo i = 0 to 1\n src1 ←EXTS(VSR[VRA+32].dword[i])\n src2 ←EXTS(VSR[VRB+32].dword[i])\n if src1 > src2 then do\n VSR[VRT+32].dword[i] ←0xFFFF_FFFF_FFFF_FFFF\n all_false ←0\n end\n else do\n VSR[VRT+32].dword[i] ←0x0000_0000_0000_0000\n all_true ←0\n end\nend\nif Rc=1 then\n CR.field[6] ←all_true || 0b0 || all_false || 0b0", "special_registers": "CR6 (if Rc=1)", "page_found": "Page 421 - 422", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "vcmpgtsd v1, v2, v3" }, { "mnemonic": "vavgub", "architecture": "PowerISA", "full_name": "Vector Average Unsigned Byte", "summary": "Computes (a+b+1)/2 for bytes.", "syntax": "vavgub vD, vA, vB", "encoding": { "format": "VA-form", "binary_pattern": "4 | vD | vA | vB | 1026", "hex_opcode": "0x10000402", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1026", "clean": "1026" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Computes the average of corresponding unsigned bytes in vA and vB using rounding (vA + vB + 1) >> 1, storing the result in vD. This is a vector operation that processes 16 independent byte elements in parallel. No condition flags or status fields are affected.", "pseudocode": "for i in 0 to 15 do\n vD[8*i:8*i+7] ← ((vA[8*i:8*i+7] + vB[8*i:8*i+7] + 1) >> 1)[7:0]\nend for", "page_found": "Page 401", "special_registers": "MSR", "programming_notes": "The vavgub instruction is commonly used for averaging pixel values in image processing tasks. Ensure that the source vectors are properly aligned to avoid performance penalties. This instruction operates at user privilege level and will raise an exception if the vector facility is not enabled (MSR.VEC=0).", "example": "vavgub vd, va, vb" }, { "mnemonic": "vavgsb", "architecture": "PowerISA", "full_name": "Vector Average Signed Byte", "summary": "Performs a signed byte-wise average of two vector registers and stores the result in another vector register.", "syntax": "vavgsb vD, vA, vB", "encoding": { "format": "VA-form", "binary_pattern": "4 | vD | vA | vB | 1282", "hex_opcode": "0x10000502", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1282", "clean": "1282" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vavgsb, each byte element of VSR[VRA+32] is added to the corresponding byte element of VSR[VRB+32], incremented by 1, then right-shifted by 1 bit. The low-order 8 bits of the result are placed into the corresponding byte element of VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 15\n src1 ←EXTS(VSR[VRA+32].byte[i])\n src2 ←EXTS(VSR[VRB+32].byte[i])\n VSR[VRT+32].byte[i] ←CHOP8((src1 + src2 + 1) >> 1)\nend", "page_found": "Page 400 - 401", "special_registers": "MSR", "programming_notes": "The vavgsb instruction performs a signed byte average, rounding up by adding 1 before shifting. Ensure that the Vector Facility is enabled in the MSR register to avoid exceptions. This operation is useful for blending two images or averaging data with precision.", "example": "vavgsb vd, va, vb" }, { "mnemonic": "vavguh", "architecture": "PowerISA", "full_name": "Vector Average Unsigned Halfword", "summary": "Computes (a+b+1)/2 for halfwords.", "syntax": "vavguh vD, vA, vB", "encoding": { "format": "VA-form", "binary_pattern": "4 | vD | vA | vB | 1090", "hex_opcode": "0x10000442", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1090", "clean": "1090" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Computes the average of corresponding unsigned halfwords in vA and vB using rounding (vA + vB + 1) >> 1, storing the result in vD. This is a vector operation that processes 8 independent halfword elements in parallel. No condition flags or status fields are affected.", "pseudocode": "for i in 0 to 7 do\n vD[16*i:16*i+15] ← ((vA[16*i:16*i+15] + vB[16*i:16*i+15] + 1) >> 1)[15:0]\nend for", "page_found": "Page 402", "special_registers": "MSR", "programming_notes": "The vavguh instruction is used to compute the average of corresponding halfwords from two source vectors, rounding up. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set; otherwise, a Vector_Unavailable exception will be raised. This instruction operates on 16-bit unsigned integers and stores the result in the destination vector. Be cautious of overflow when adding the two source halfwords before rounding.", "example": "vavguh vd, va, vb" }, { "mnemonic": "vavgsh", "architecture": "PowerISA", "full_name": "Vector Average Signed Halfword", "summary": "Performs a signed halfword average operation on vector elements.", "syntax": "vavgsh vD, vA, vB", "encoding": { "format": "VA-form", "binary_pattern": "0 | VRT | VRA | VRB | 1346", "hex_opcode": "0x10000542", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1346", "clean": "1346" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vavgsh, the sum of the contents of each corresponding pair of halfwords from VSR[VRA+32] and VSR[VRB+32] is calculated, incremented by 1, shifted right by 1 bit, and then placed into the corresponding halfword in VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 7\n src1 ←EXTS(VSR[VRA+32].hword[i])\n src2 ←EXTS(VSR[VRB+32].hword[i])\n VSR[VRT+32].hword[i] ← CHOP16((src1 + src2 + 1) >> 1)\nend", "page_found": "Page 401 - 402", "special_registers": "MSR", "programming_notes": "The vavgsh instruction performs a signed halfword average, rounding up by adding 1 before shifting. Ensure that the vector facility is enabled in the MSR register to avoid exceptions. This operation processes each pair of halfwords independently, so alignment requirements are minimal.", "example": "vavgsh vd, va, vb" }, { "mnemonic": "vavguw", "architecture": "PowerISA", "full_name": "Vector Average Unsigned Word", "summary": "Computes (a+b+1)/2 for words.", "syntax": "vavguw vD, vA, vB", "encoding": { "format": "VA-form", "binary_pattern": "4 | vD | vA | vB | 1154", "hex_opcode": "0x10000482", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1154", "clean": "1154" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Computes the average of corresponding unsigned words in vA and vB using rounding (vA + vB + 1) >> 1, storing the result in vD. This is a vector operation that processes 4 independent word elements in parallel. No condition flags or status fields are affected.", "pseudocode": "for i in 0 to 3 do\n vD[32*i:32*i+31] ← ((vA[32*i:32*i+31] + vB[32*i:32*i+31] + 1) >> 1)[31:0]\nend for", "page_found": "Page 403", "special_registers": "MSR", "programming_notes": "The vavguw instruction is used to compute the average of unsigned word elements from two vectors. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set; otherwise, a Vector_Unavailable exception will be raised. This instruction processes each 32-bit word element independently, so alignment requirements are not strict. Be cautious with potential overflow when summing large unsigned integers.", "example": "vavguw vd, va, vb" }, { "mnemonic": "vavgsw", "architecture": "PowerISA", "full_name": "Vector Average Signed Word", "summary": "Performs a vector average of signed words from two source vectors and stores the result in a destination vector.", "syntax": "vavgsw vD, vA, vB", "encoding": { "format": "VA-form", "binary_pattern": "4 | vD | vA | vB | 1410", "hex_opcode": "0x10000582", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1410", "clean": "1410" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vavgsw, each word element in VSR[VRA+32] is added to the corresponding word element in VSR[VRB+32], incremented by 1, and then shifted right by 1 bit. The low-order 32 bits of the result are placed into the corresponding word element in VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n src1 ←EXTS(VSR[VRA+32].word[i])\n src2 ←EXTS(VSR[VRB+32].word[i])\n VSR[VRT+32].word[i] ← Chop32((src1 + src2 + 1) >> 1)", "page_found": "Page 402 - 403", "special_registers": "MSR", "programming_notes": "vavgsw is used for averaging signed word elements from two vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. The operation includes an implicit rounding by adding 1 before shifting right, which can affect results for negative numbers. This instruction operates on 32-bit word elements and requires proper alignment of input vectors.", "example": "vavgsw vd, va, vb" }, { "mnemonic": "vminub", "architecture": "PowerISA", "full_name": "Vector Minimum Unsigned Byte", "summary": "Selects minimum value per byte (unsigned).", "syntax": "vminub vD, vA, vB", "encoding": { "format": "VA-form", "binary_pattern": "4 | vD | vA | vB | 1026", "hex_opcode": "0x10000202", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1026", "clean": "1026" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Selects the minimum unsigned value for each corresponding byte pair from vA and vB, storing the results in vD. This is a vector operation that performs 16 independent byte-wise minimum comparisons in parallel. No condition flags or status fields are affected.", "pseudocode": "for i in 0 to 15 do\n vD[8*i:8*i+7] ← MIN_UNSIGNED(vA[8*i:8*i+7], vB[8*i:8*i+7])\nend for", "page_found": "Page 410", "special_registers": "MSR", "programming_notes": "The vminub instruction is used to perform element-wise minimum comparison of unsigned bytes between two vector registers and store the results in a third register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation is straightforward but requires both source vectors to be properly aligned for optimal performance.", "example": "vminub vd, va, vb" }, { "mnemonic": "vminsb", "architecture": "PowerISA", "full_name": "Vector Minimum Signed Byte", "summary": "Compares the signed byte elements of two vector registers and stores the minimum values in a third vector register.", "syntax": "vminsb vD, vA, vB", "encoding": { "format": "VA-form", "binary_pattern": "4 | vD | vA | vB | 1538", "hex_opcode": "0x10000302", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1538", "clean": "1538" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vminsb, each byte element of VSR[VRA+32] is compared to the corresponding byte element of VSR[VRB+32]. The smaller value is stored in the corresponding byte element of VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 15\n src1 ← VSR[VRA+32].byte[i]\n src2 ← VSR[VRB+32].byte[i]\n lt_flag ← EXTS(src1) < EXTS(src2)\n VSR[VRT+32].byte[i] ← lt_flag=1 ? src1 : src2\nend", "page_found": "Page 409 - 410", "special_registers": "MSR", "programming_notes": "This instruction is used to perform element-wise minimum comparison on signed byte values. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation respects the sign of the bytes, so it correctly handles negative numbers. There are no specific alignment requirements for the vector registers involved.", "example": "vminsb vd, va, vb" }, { "mnemonic": "vminuh", "architecture": "PowerISA", "full_name": "Vector Minimum Unsigned Halfword", "summary": "Selects minimum value per halfword (unsigned).", "syntax": "vminuh vD, vA, vB", "encoding": { "format": "VA-form", "binary_pattern": "4 | vD | vA | vB | 1090", "hex_opcode": "0x10000242", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1090", "clean": "1090" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Selects the minimum unsigned value for each corresponding halfword pair from vA and vB, storing the results in vD. This is a vector operation that performs 8 independent halfword-wise minimum comparisons in parallel. No condition flags or status fields are affected.", "pseudocode": "for i in 0 to 7 do\n vD[16*i:16*i+15] ← MIN_UNSIGNED(vA[16*i:16*i+15], vB[16*i:16*i+15])\nend for", "page_found": "Page 411", "special_registers": "MSR", "programming_notes": "The vminuh instruction is used to perform element-wise minimum operations on unsigned halfwords from two source vectors. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation does not require any specific alignment for the data, but both source and destination vectors must be properly loaded into the vector registers VRA, VRB, and VRT respectively.", "example": "vminuh vd, va, vb" }, { "mnemonic": "vminsh", "architecture": "PowerISA", "full_name": "Vector Minimum Signed Halfword", "summary": "Compares the signed halfwords of two vector registers and selects the minimum value for each corresponding pair.", "syntax": "vminsh vD, vA, vB", "encoding": { "format": "VA-form", "binary_pattern": "4 | vD | vA | vB | 1602", "hex_opcode": "0x10000342", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1602", "clean": "1602" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vminsh, the instruction compares the signed halfwords of VSR[VRA+32] and VSR[VRB+32]. The smaller value is placed into the corresponding halfword element of VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 7\n src1 ← VSR[VRA+32].hword[i]\n src2 ← VSR[VRB+32].hword[i]\n lt_flag ← EXTS(src1) < EXTS(src2)\n VSR[VRT+32].hword[i] ← lt_flag=1 ? src1 : src2\nend", "page_found": "Page 410 - 411", "special_registers": "MSR", "programming_notes": "This instruction is used to perform element-wise minimum comparison of signed halfwords from two vector registers and store the results in another vector register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation respects the sign of the halfwords, so negative values are correctly handled. There are no specific alignment requirements for the data being processed.", "example": "vminsh vd, va, vb" }, { "mnemonic": "vminuw", "architecture": "PowerISA", "full_name": "Vector Minimum Unsigned Word", "summary": "Selects minimum value per word (unsigned).", "syntax": "vminuw vD, vA, vB", "encoding": { "format": "VA-form", "binary_pattern": "4 | vD | vA | vB | 1154", "hex_opcode": "0x10000282", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1154", "clean": "1154" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Selects the minimum unsigned value for each corresponding word pair from vA and vB, storing the results in vD. This is a vector operation that performs 4 independent word-wise minimum comparisons in parallel. No condition flags or status fields are affected.", "pseudocode": "for i in 0 to 3 do\n vD[32*i:32*i+31] ← MIN_UNSIGNED(vA[32*i:32*i+31], vB[32*i:32*i+31])\nend for", "page_found": "Page 412", "special_registers": "MSR", "programming_notes": "The vminuw instruction is used to perform element-wise minimum operations on unsigned words from two vectors. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation is performed in parallel across four elements per vector register.", "example": "vminuw vd, va, vb" }, { "mnemonic": "vminsw", "architecture": "PowerISA", "full_name": "Vector Minimum Signed Word", "summary": "Compares the signed integer values in each word element of two vector registers and stores the smaller value into a target vector register.", "syntax": "vminsw vD, vA, vB", "encoding": { "format": "VA-form", "binary_pattern": "4 | vD | vA | vB | 1666", "hex_opcode": "0x10000382", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1666", "clean": "1666" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vminsw, the instruction compares the signed integer values in each word element of VSR[VRA+32] and VSR[VRB+32]. The smaller value is placed into the corresponding word element of VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n src1 ← VSR[VRA+32].word[i]\n src2 ← VSR[VRB+32].word[i]\n lt_flag ← EXTS(src1) < EXTS(src2)\n VSR[VRT+32].word[i] ← lt_flag=1 ? src1 : src2", "page_found": "Page 411 - 412", "special_registers": "MSR", "programming_notes": "This instruction is used to perform element-wise minimum comparison of signed 32-bit integers in vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation respects the sign of the integers, so negative numbers are correctly handled as expected in signed comparisons.", "example": "vminsw vd, va, vb" }, { "mnemonic": "vmaxub", "architecture": "PowerISA", "full_name": "Vector Maximum Unsigned Byte", "summary": "Selects maximum value per byte (unsigned).", "syntax": "vmaxub vD, vA, vB", "encoding": { "format": "VA-form", "binary_pattern": "4 | vD | vA | vB | 4", "hex_opcode": "0x10000002", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "4", "clean": "4" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Selects the maximum unsigned value for each corresponding byte pair from vA and vB, storing the results in vD. This is a vector operation that performs 16 independent byte-wise maximum comparisons in parallel. No condition flags or status fields are affected.", "pseudocode": "for i in 0 to 15 do\n vD[8*i:8*i+7] ← MAX_UNSIGNED(vA[8*i:8*i+7], vB[8*i:8*i+7])\nend for", "page_found": "Page 406", "special_registers": "MSR", "programming_notes": "The vmaxub instruction is used to perform element-wise comparison of unsigned bytes from two vector registers and store the maximum values in a third register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. This instruction operates on 16-byte vectors, so ensure proper alignment for optimal performance.", "example": "vmaxub vd, va, vb" }, { "mnemonic": "vmaxsb", "architecture": "PowerISA", "full_name": "Vector Maximum Signed Byte", "summary": "Performs a signed byte-wise maximum operation on two vector registers and stores the result in another vector register.", "syntax": "vmaxsb vD, vA, vB", "encoding": { "format": "VA-form", "binary_pattern": "4 | vD | vA | vB | 516", "hex_opcode": "0x10000102", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "516", "clean": "516" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vmaxsb, each byte element of VSR[VRA+32] is compared with the corresponding byte element of VSR[VRB+32]. The larger value is stored in the corresponding byte element of VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 15\n src1 ← VSR[VRA+32].byte[i]\n src2 ← VSR[VRB+32].byte[i]\n gt_flag ← EXTS(src1) > EXTS(src2)\n VSR[VRT+32].byte[i] ← gt_flag=1 ? src1 : src2\nend", "page_found": "Page 405 - 406", "special_registers": "MSR", "programming_notes": "This instruction is used to perform element-wise signed byte comparisons and store the maximum values in the destination vector. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation respects the signed nature of bytes, so developers should be cautious with negative values. This instruction operates on 16 byte elements and does not require any specific alignment for the vector registers.", "example": "vmaxsb vd, va, vb" }, { "mnemonic": "vmaxuh", "architecture": "PowerISA", "full_name": "Vector Maximum Unsigned Halfword", "summary": "Selects maximum value per halfword (unsigned).", "syntax": "vmaxuh vD, vA, vB", "encoding": { "format": "VA-form", "binary_pattern": "4 | vD | vA | vB | 68", "hex_opcode": "0x10000042", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "68", "clean": "68" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Selects the maximum unsigned value for each corresponding halfword pair from vA and vB, storing the results in vD. This is a vector operation that performs 8 independent halfword-wise maximum comparisons in parallel. No condition flags or status fields are affected.", "pseudocode": "for i in 0 to 7 do\n vD[16*i:16*i+15] ← MAX_UNSIGNED(vA[16*i:16*i+15], vB[16*i:16*i+15])\nend for", "page_found": "Page 407", "special_registers": "MSR", "programming_notes": "The vmaxuh instruction is used to perform element-wise comparisons of unsigned halfwords from two source vectors and store the maximum values in a destination vector. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. This instruction operates on 16-bit unsigned integers, so ensure proper alignment and data type handling to avoid unexpected results.", "example": "vmaxuh vd, va, vb" }, { "mnemonic": "vmaxsh", "architecture": "PowerISA", "full_name": "Vector Maximum Signed Halfword", "summary": "Compares the signed halfwords of two vector registers and stores the maximum values in a third vector register.", "syntax": "vmaxsh vD, vA, vB", "encoding": { "format": "VA-form", "binary_pattern": "4 | vD | vA | vB | 580", "hex_opcode": "0x10000142", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "580", "clean": "580" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vmaxsh, each pair of corresponding halfwords from VSR[VRA+32] and VSR[VRB+32] are compared. The larger value is stored in the corresponding halfword of VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 7\n src1 ← VSR[VRA+32].hword[i]\n src2 ← VSR[VRB+32].hword[i]\n gt_flag ← EXTS(src1) > EXTS(src2)\n VSR[VRT+32].hword[i] ← gt_flag=1 ? src1 : src2\nend", "page_found": "Page 406 - 407", "special_registers": "MSR", "programming_notes": "This instruction is used to perform element-wise signed halfword maximum operations between two vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation respects the sign of the halfwords and stores the larger value in the corresponding position of the destination register. Be cautious with alignment as unaligned access might lead to performance penalties or exceptions depending on the system configuration.", "example": "vmaxsh vd, va, vb" }, { "mnemonic": "vmaxuw", "architecture": "PowerISA", "full_name": "Vector Maximum Unsigned Word", "summary": "Selects maximum value per word (unsigned).", "syntax": "vmaxuw vD, vA, vB", "encoding": { "format": "VA-form", "binary_pattern": "4 | vD | vA | vB | 132", "hex_opcode": "0x10000082", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "132", "clean": "132" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Compares four unsigned word elements from vA and vB, writing the maximum value of each pair to the corresponding word element in vD. This is a VMX (AltiVec) instruction that operates on all four 32-bit words in parallel with no condition register or status updates.", "pseudocode": "vD[0:31] ← max(vA[0:31], vB[0:31])\nvD[32:63] ← max(vA[32:63], vB[32:63])\nvD[64:95] ← max(vA[64:95], vB[64:95])\nvD[96:127] ← max(vA[96:127], vB[96:127])", "page_found": "Page 408", "special_registers": "MSR", "programming_notes": "The vmaxuw instruction is used to perform element-wise comparison of unsigned 32-bit words in vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation does not require any specific alignment for the data being processed.", "example": "vmaxuw vd, va, vb" }, { "mnemonic": "vmaxsw", "architecture": "PowerISA", "full_name": "Vector Maximum Signed Word", "summary": "Compares the signed integer values in each word element of two vector registers and stores the larger value into a third vector register.", "syntax": "vmaxsw vD, vA, vB", "encoding": { "format": "VA-form", "binary_pattern": "4 | vD | vA | vB | 644", "hex_opcode": "0x10000182", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "644", "clean": "644" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vmaxsw, for each integer value i from 0 to 3, the signed integer value in word element i of VSR[VRA+32] is compared to the signed integer value in word element i of VSR[VRB+32]. The larger of the two values is placed into word element i of VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n src1 ← VSR[VRA+32].word[i]\n src2 ← VSR[VRB+32].word[i]\n gt_flag ← EXTS(src1) > EXTS(src2)\n VSR[VRT+32].word[i] ← gt_flag=1 ? src1 : src2", "page_found": "Page 407 - 408", "special_registers": "MSR", "programming_notes": "The vmaxsw instruction compares each signed word element of two vector registers and stores the maximum value in the destination register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on 4-word elements, so input vectors must be properly aligned. Be cautious with signed integer overflow; if both operands are negative and one is closer to zero than the other, the result may not be as expected.", "example": "vmaxsw vd, va, vb" }, { "mnemonic": "vmrghb", "architecture": "PowerISA", "full_name": "Vector Merge High Byte", "summary": "Interleaves high-order bytes from two vectors (Permutation).", "syntax": "vmrghb vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 12", "hex_opcode": "0x1000000C", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "12", "clean": "12" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vmrghb, the high byte elements of VSR[VRA+32] and VSR[VRB+32] are merged into VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 7\n VSR[VRT+32].hword[i].byte[0] ← VSR[VRA+32].byte[i]\n VSR[VRT+32].hword[i].byte[1] ← VSR[VRB+32].byte[i]", "page_found": "Page 314 - 316", "special_registers": "MSR", "programming_notes": "This instruction is used to merge the high byte elements from two vector registers into a third. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. The operation processes each of the 8 high bytes, placing them alternately into the destination register. This instruction operates at the user privilege level and does not generate exceptions beyond those related to facility availability or invalid operand access.", "example": "vmrghb vd, va, vb" }, { "mnemonic": "vmrghh", "architecture": "PowerISA", "full_name": "Vector Merge High Halfword", "summary": "Merges the high halfwords of two vector registers into a target vector register.", "syntax": "vmrghh vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 76", "hex_opcode": "0x1000004C", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "76", "clean": "76" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vmrghh, the contents of halfword elements 0 to 3 of VSR[VRA+32] are placed into halfword elements 0 to 7 of VSR[VRT+32], and the contents of halfword elements 0 to 3 of VSR[VRB+32] are placed into halfword elements 1 to 8 of VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n VSR[VRT+32].word[i].hword[0] ← VSR[VRA+32].hword[i]\n VSR[VRT+32].word[i].hword[1] ← VSR[VRB+32].hword[i]", "page_found": "Page 315 - 316", "special_registers": "MSR", "programming_notes": "The vmrghh instruction is used to merge the high halfwords from two vector registers into a single destination register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. This operation is useful for combining data from two sources into one vector, but be cautious of alignment issues if the data elements are not properly aligned to halfword boundaries.", "example": "vmrghh vd, va, vb" }, { "mnemonic": "vmrghw", "architecture": "PowerISA", "full_name": "Vector Merge High Word", "summary": "Merges the high words of two vector registers into a target vector register.", "syntax": "vmrghw vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O | O", "hex_opcode": "0x1000008C", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "140", "clean": "140" } ], "length": "32", "bit_positions": "0 | 6 | 11 | 16 | | | | | | | | | | | | | | | | | | | | | | | | | | | | " }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "VT", "desc": "Target Vector Register" }, { "name": "VS30", "desc": "Source Vector Register" }, { "name": "VS31", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "The contents of word element 0 of VSR[VRA+32] are placed into word element 0 of VSR[VRT+32]. The contents of word element 0 of VSR[VRB+32] are placed into word element 1 of VSR[VRT+32]. The contents of word element 1 of VSR[VRA+32] are placed into word element 2 of VSR[VRT+32]. The contents of word element 1 of VSR[VRB+32] are placed into word element 3 of VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nelse\n VSR[VRT+32].word[0] ← VSR[VRA+32].word[0]\n VSR[VRT+32].word[1] ← VSR[VRB+32].word[0]\n VSR[VRT+32].word[2] ← VSR[VRA+32].word[1]\n VSR[VRT+32].word[3] ← VSR[VRB+32].word[1]", "page_found": "Page 316 - 318", "special_registers": "MSR", "programming_notes": "The vmrghw instruction is used to merge high words from two vector registers into a third. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. This operation is useful for combining specific elements from different vectors into a single output vector.", "example": "vmrghw vd, va, vb" }, { "mnemonic": "vmrglb", "architecture": "PowerISA", "full_name": "Vector Merge Low Byte", "summary": "Interleaves low-order bytes.", "syntax": "vmrglb vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 268", "hex_opcode": "0x1000010C", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "268", "clean": "268" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Merges the eight low-order (rightmost) bytes from vA and vB in an alternating interleaved pattern into vD, with vA bytes in even positions and vB bytes in odd positions. This VMX instruction does not affect any condition or status registers.", "pseudocode": "vD[0:7] ← vA[120:127]\nvD[8:15] ← vB[120:127]\nvD[16:23] ← vA[112:119]\nvD[24:31] ← vB[112:119]\nvD[32:39] ← vA[104:111]\nvD[40:47] ← vB[104:111]\nvD[48:55] ← vA[96:103]\nvD[56:63] ← vB[96:103]\nvD[64:71] ← vA[88:95]\nvD[72:79] ← vB[88:95]\nvD[80:87] ← vA[80:87]\nvD[88:95] ← vB[80:87]\nvD[96:103] ← vA[72:79]\nvD[104:111] ← vB[72:79]\nvD[112:119] ← vA[64:71]\nvD[120:127] ← vB[64:71]", "page_found": "Page 315", "special_registers": "MSR", "programming_notes": "The vmrglb instruction is useful for merging data from two vectors by alternating bytes into a third vector. Ensure that the target and source registers are properly aligned to avoid unexpected behavior. This instruction requires the Vector Facility to be enabled in the MSR register; otherwise, it will raise an exception. Performance may vary based on the specific implementation and alignment of the data.", "example": "vmrglb vd, va, vb" }, { "mnemonic": "vmrglh", "architecture": "PowerISA", "full_name": "Vector Merge Low Halfword", "summary": "Interleaves low-order halfwords.", "syntax": "vmrglh vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 332", "hex_opcode": "0x1000014C", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "332", "clean": "332" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Merges the four low-order (rightmost) halfwords from vA and vB in an alternating interleaved pattern into vD, with vA halfwords in even positions and vB halfwords in odd positions. This VMX instruction does not affect any condition or status registers.", "pseudocode": "vD[0:15] ← vA[112:127]\nvD[16:31] ← vB[112:127]\nvD[32:47] ← vA[96:111]\nvD[48:63] ← vB[96:111]\nvD[64:79] ← vA[80:95]\nvD[80:95] ← vB[80:95]\nvD[96:111] ← vA[64:79]\nvD[112:127] ← vB[64:79]", "page_found": "Page 316", "special_registers": "MSR", "programming_notes": "The vmrglh instruction is used to merge the lower halfwords from two source vectors into a destination vector. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation interleaves the halfwords from the two sources, so the resulting vector will have elements from both sources in an alternating pattern.", "example": "vmrglh vd, va, vb" }, { "mnemonic": "vmrglw", "architecture": "PowerISA", "full_name": "Vector Merge Low Word", "summary": "Interleaves low-order words.", "syntax": "vmrglw vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 396", "hex_opcode": "0x1000018C", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "396", "clean": "396" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Merges the two low-order (rightmost) words from vA and vB in an alternating interleaved pattern into vD, with vA word in even position and vB word in odd position. This VMX instruction does not affect any condition or status registers.", "pseudocode": "vD[0:31] ← vA[96:127]\nvD[32:63] ← vB[96:127]\nvD[64:95] ← vA[64:95]\nvD[96:127] ← vB[64:95]", "page_found": "Page 317", "special_registers": "MSR", "programming_notes": "The vmrglw instruction is used to merge the low words from two source vectors into a destination vector. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set; otherwise, a Vector_Unavailable exception will be raised. This instruction operates on 128-bit vector registers and requires proper alignment of the input vectors to avoid unexpected results.", "example": "vmrglw vd, va, vb" }, { "mnemonic": "vpkuhum", "architecture": "PowerISA", "full_name": "Vector Pack Unsigned Halfword Unsigned Modulo", "summary": "Packs the upper half of each 16-bit element from two vector registers into a single byte in another vector register.", "syntax": "vpkuhum vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "18 | VRT | VRA | VRB | 14", "hex_opcode": "0x1000000E", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "14", "clean": "14" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "The instruction packs the upper half of each 16-bit element from VSR[VRA+32] and VSR[VRB+32] into the corresponding byte elements of VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nelse\n vsrc.qword[0] ← VSR[VRA+32]\n vsrc.qword[1] ← VSR[VRB+32]\n for i = 0 to 15 do\n VSR[VRT+32].byte[i] ← vsrc.hword[i].bit[8:15]\n end\nend", "page_found": "Page 307 - 308", "special_registers": "MSR", "programming_notes": "This instruction is used to pack the upper half of each 16-bit element from two source vectors into a destination vector. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set before using this instruction; otherwise, it will raise an exception. The operation processes 32 bytes (16 elements) from each source vector and packs them into the destination vector, maintaining the upper half of each element. This instruction does not require any specific alignment but must be executed in a privileged context where the VEC bit is enabled.", "example": "vpkuhum vd, va, vb" }, { "mnemonic": "vpkuwum", "architecture": "PowerISA", "full_name": "Vector Pack Unsigned Word Unsigned Modulo", "summary": "Packs the upper half of each word from two vector registers into a single vector register using modulo arithmetic.", "syntax": "vpkuwum vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 78", "hex_opcode": "0x1000004E", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "78", "clean": "78" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "The instruction concatenates the contents of VSR[VRA+32] and VSR[VRB+32], then extracts the upper half of each word (bits 16:31) and places them into the corresponding halfword elements of VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nvsrc.qword[0] ← VSR[VRA+32]\nvsrc.qword[1] ← VSR[VRB+32]\ndo i = 0 to 7\n VSR[VRT+32].hword[i] ← vsrc.word[i].bit[16:31]\nend", "page_found": "Page 308 - 310", "special_registers": "MSR", "programming_notes": "This instruction is used for packing the upper half of each word from two vector registers into a single destination register. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to 1; otherwise, a Vector Unavailable exception will be raised. The operation requires both source vectors to be aligned on 16-byte boundaries for optimal performance.", "example": "vpkuwum vd, va, vb" }, { "mnemonic": "vpkuhus", "architecture": "PowerISA", "full_name": "Vector Pack Unsigned Halfword Unsigned Saturate", "summary": "Saturates 8 halfwords to 16 unsigned bytes.", "syntax": "vpkuhus vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 142", "hex_opcode": "0x1000008E", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "142", "clean": "142" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Packs and saturates eight unsigned halfword elements from vA and vB into sixteen unsigned bytes in vD, discarding or saturating values that exceed 255. The saturation flag in VSCR is set if any saturation occurred. This VMX instruction operates in saturating mode for unsigned values.", "pseudocode": "for i in 0 to 3:\n vD[2*i:2*i+7] ← Saturate_UH_to_UB(vA[16*i:16*i+15])\n vD[2*i+8:2*i+15] ← Saturate_UH_to_UB(vB[16*i:16*i+15])\nif any saturation occurred:\n VSCR[SAT] ← 1", "page_found": "Page 308", "special_registers": "MSR", "programming_notes": "The vpkuhus instruction is used to pack unsigned halfwords from two source vectors into a destination vector, with saturation applied if the values exceed 8 bits. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The operation processes each halfword from the input vectors and clamps the result to fit within an 8-bit unsigned integer range.", "example": "vpkuhus vd, va, vb" }, { "mnemonic": "vpkshss", "architecture": "PowerISA", "full_name": "Vector Pack Signed Halfword Signed Saturate", "summary": "Packs signed halfwords from two vector registers into a single vector register with signed saturation.", "syntax": "vpkshss vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 462", "hex_opcode": "0x1000018E", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "462", "clean": "462" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "The instruction concatenates the contents of VSR[VRA+32] and VSR[VRB+32], then for each integer value i from 0 to 15, it places the signed integer value in halfword element i of the concatenated source into byte element i of VSR[VRT+32] in signed integer format. If the value is greater than 2^7 - 1 or less than -2^7, it saturates and sets SAT to 1.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nvsrc.qword[0] ← VSR[VRA+32]\nvsrc.qword[1] ← VSR[VRB+32]\ndo i = 0 to 15\n VSR[VRT+32].byte[i] ← si8_CLAMP(EXTS(vsrc.hword[i]))\nend", "special_registers": "VSCR (SAT)", "page_found": "Page 304 - 306", "programming_notes": "This instruction is useful for packing signed halfwords into bytes with saturation. Ensure that the source vectors are correctly aligned and that the vector facility (MSR.VEC) is enabled to avoid exceptions. Be aware of saturation conditions, as they will set the SAT bit in VSCR.", "example": "vpkshss vd, va, vb" }, { "mnemonic": "vpkswss", "architecture": "PowerISA", "full_name": "Vector Pack Signed Word Signed Saturate", "summary": "Packs signed words from two vector registers into a single vector register with signed saturation.", "syntax": "vpkswss vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 526", "hex_opcode": "0x100001CE", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "526", "clean": "526" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "The instruction vpkswss packs the contents of VSR[VRA+32] and VSR[VRB+32] into VSR[VRT+32], converting each word to a halfword with signed saturation.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nvsrc.qword[0] ← VSR[VRA+32]\nvsrc.qword[1] ← VSR[VRB+32]\ndo i = 0 to 7\n VSR[VRT+32].hword[i] ← si16_CLAMP(EXTS(vsrc.word[i]))\nend", "special_registers": "VSCR.SAT", "page_found": "Page 305 - 306", "programming_notes": "This instruction is commonly used for efficiently packing and saturating signed word values into halfwords. Ensure that the vector facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation involves extending each 32-bit word to 64 bits with sign extension, then clamping the result to fit within a 16-bit signed integer range. Be aware of potential saturation effects when dealing with values that exceed the halfword range.", "example": "vpkswss vd, va, vb" }, { "mnemonic": "vupkhsb", "architecture": "PowerISA", "full_name": "Vector Unpack High Signed Byte", "summary": "Unpacks the high signed byte from each element of a vector register into halfwords of another vector register.", "syntax": "vupkhsb vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "0 | VRT | VRB | 18 | LI | AA | LK", "hex_opcode": "0x1000020E", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "526", "clean": "526" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:29 | 30 | 31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vupkhsb, the signed integer value in byte element i of VSR[VRB+32] is sign-extended and placed into half-word element i in VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 7\n VSR[VRT+32].hword[i] ←EXTS16(VSR[VRB+32].byte[i])\nend", "page_found": "Page 310 - 312", "special_registers": "MSR", "programming_notes": "This instruction is used to unpack the high signed bytes from one vector register into half-words of another. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector Unavailable exception will be raised. The operation processes each byte element, sign-extending it to a half-word, which can affect the result if the original byte values are negative.", "example": "vupkhsb vd, vb" }, { "mnemonic": "vupkhsh", "architecture": "PowerISA", "full_name": "Vector Unpack High Signed Halfword", "summary": "Unpacks the high signed halfwords from a vector register into a new vector register.", "syntax": "vupkhsh vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 0 | vB | 590", "hex_opcode": "0x1000024E", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "590", "clean": "590" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "The instruction unpacks the high signed halfwords from VSR[VRB+32] and places them into VSR[VRT+32]. Each halfword is sign-extended to form a word.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nfor each integer value i from 0 to 3 do\n VSR[VRT+32].word[i] ←EXTS32(VSR[VRB+32].hword[i])", "page_found": "Page 311 - 312", "special_registers": "MSR", "programming_notes": "This instruction is used to extract the high signed halfwords from a vector register and sign-extend them into another vector register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The operation processes each of the four halfwords in the source register, so ensure proper alignment if dealing with specific data structures.", "example": "vupkhsh vd, vb" }, { "mnemonic": "vupklsb", "architecture": "PowerISA", "full_name": "Vector Unpack Low Signed Byte", "summary": "Unpacks low 8 signed bytes to 8 signed halfwords.", "syntax": "vupklsb vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 0 | vB | 654", "hex_opcode": "0x1000028E", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "654", "clean": "654" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" } ], "extension": "VMX (AltiVec)", "description": "Unpacks the eight low-order (rightmost) signed bytes from vB into eight signed halfwords in vD, sign-extending each byte to 16 bits. This is a VMX instruction that does not modify condition or status registers.", "pseudocode": "vD[0:15] ← sign_extend(vB[120:127])\nvD[16:31] ← sign_extend(vB[112:119])\nvD[32:47] ← sign_extend(vB[104:111])\nvD[48:63] ← sign_extend(vB[96:103])\nvD[64:79] ← sign_extend(vB[88:95])\nvD[80:95] ← sign_extend(vB[80:87])\nvD[96:111] ← sign_extend(vB[72:79])\nvD[112:127] ← sign_extend(vB[64:71])", "page_found": "Page 311", "special_registers": "MSR", "programming_notes": "This instruction is useful for processing byte data by converting it into signed halfwords, which can be beneficial for operations requiring sign extension. Ensure that the vector facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will occur. The input vector must be properly aligned to avoid unexpected results.", "example": "vupklsb vd, vb" }, { "mnemonic": "vupklsh", "architecture": "PowerISA", "full_name": "Vector Unpack Low Signed Halfword", "summary": "Unpacks low 4 signed halfwords to 4 signed words.", "syntax": "vupklsh vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 0 | vB | 718", "hex_opcode": "0x100002CE", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "718", "clean": "718" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" } ], "extension": "VMX (AltiVec)", "description": "Unpacks the four low-order (rightmost) signed halfwords from vB into four signed words in vD, sign-extending each halfword to 32 bits. This is a VMX instruction that does not modify condition or status registers.", "pseudocode": "vD[0:31] ← sign_extend(vB[112:127])\nvD[32:63] ← sign_extend(vB[96:111])\nvD[64:95] ← sign_extend(vB[80:95])\nvD[96:127] ← sign_extend(vB[64:79])", "page_found": "Page 312", "special_registers": "MSR", "programming_notes": "This instruction is used to unpack the low halfwords from a source vector register into a destination vector register, sign-extending each halfword to form words. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation targets the high 128 bits of the vector registers, so ensure that VRB and VRT are correctly set for the desired vector elements.", "example": "vupklsh vd, vb" }, { "mnemonic": "vaddubm", "architecture": "PowerISA", "full_name": "Vector Add Unsigned Byte Modulo", "summary": "Adds the contents of two vector registers and updates the result in another vector register, modulo operation for bytes.", "syntax": "vaddubm vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 0", "hex_opcode": "0x10000000", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "0", "clean": "0" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vaddubm, each byte element of VSR[VRA+32] is added to the corresponding byte element of VSR[VRB+32], and the low-order 8 bits of the result are placed into the corresponding byte element of VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 15\n src1 ←EXTZ(VSR[VRA+32].byte[i])\n src2 ←EXTZ(VSR[VRB+32].byte[i])\n VSR[VRT+32].byte[i] ←CHOP8(src1 + src2)\nend", "programming_notes": "vaddubm can be used for unsigned or signed integers.", "page_found": "Page 350 - 351", "special_registers": "MSR", "example": "vaddubm vd, va, vb" }, { "mnemonic": "vadduhm", "architecture": "PowerISA", "full_name": "Vector Add Unsigned Halfword Modulo", "summary": "Adds 8 halfwords modulo 65536.", "syntax": "vadduhm vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 64", "hex_opcode": "0x10000040", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "64", "clean": "64" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Adds eight pairs of unsigned halfword elements from vA and vB with modulo 65536 arithmetic (overflow wraps around) and stores the results in vD. This VMX instruction does not affect condition or status registers and operates in modulo mode without saturation.", "pseudocode": "vD[0:15] ← (vA[0:15] + vB[0:15]) mod 2^16\nvD[16:31] ← (vA[16:31] + vB[16:31]) mod 2^16\nvD[32:47] ← (vA[32:47] + vB[32:47]) mod 2^16\nvD[48:63] ← (vA[48:63] + vB[48:63]) mod 2^16\nvD[64:79] ← (vA[64:79] + vB[64:79]) mod 2^16\nvD[80:95] ← (vA[80:95] + vB[80:95]) mod 2^16\nvD[96:111] ← (vA[96:111] + vB[96:111]) mod 2^16\nvD[112:127] ← (vA[112:127] + vB[112:127]) mod 2^16", "page_found": "Page 351", "special_registers": "MSR", "programming_notes": "This instruction is commonly used for vectorized addition of unsigned 16-bit integers with modulo behavior, useful in applications like image processing or cryptography. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation processes each halfword element independently, so there are no ordering requirements between elements, but alignment of input vectors to 16-byte boundaries can improve performance.", "example": "vadduhm vd, va, vb" }, { "mnemonic": "vadduwm", "architecture": "PowerISA", "full_name": "Vector Add Unsigned Word Modulo", "summary": "Adds 4 words modulo 2^32.", "syntax": "vadduwm vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 128", "hex_opcode": "0x10000080", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "128", "clean": "128" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Adds each of four unsigned 32-bit words in vA to the corresponding word in vB, with results modulo 2^32 (wrapping on overflow). No status flags are affected; this is a basic VMX/AltiVec arithmetic operation.", "pseudocode": "for i in 0 to 3 do\n vD[i*32:(i+1)*32-1] ← (vA[i*32:(i+1)*32-1] + vB[i*32:(i+1)*32-1]) mod 2^32", "page_found": "Page 352", "special_registers": "MSR", "programming_notes": "This instruction is commonly used for performing element-wise addition of unsigned 32-bit integers in vector registers. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to avoid a Vector_Unavailable exception. The operation wraps around using modulo arithmetic, so there's no need to handle overflow separately. This instruction operates at the user privilege level and does not generate exceptions for normal arithmetic operations.", "example": "vadduwm vd, va, vb" }, { "mnemonic": "vaddudm", "architecture": "PowerISA", "full_name": "Vector Add Unsigned Doubleword Modulo", "summary": "Adds 2 doublewords modulo 2^64.", "syntax": "vaddudm vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 192", "hex_opcode": "0x100000C0", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "192", "clean": "192" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Adds each of two unsigned 64-bit doublewords in vA to the corresponding doubleword in vB, with results modulo 2^64 (wrapping on overflow). No status flags are affected; this is a VMX/AltiVec arithmetic operation available on some implementations.", "pseudocode": "for i in 0 to 1 do\n vD[i*64:(i+1)*64-1] ← (vA[i*64:(i+1)*64-1] + vB[i*64:(i+1)*64-1]) mod 2^64", "page_found": "Page 352", "special_registers": "MSR", "programming_notes": "This instruction is commonly used for performing element-wise addition of two vectors treating each element as a 64-bit unsigned integer. Ensure that the vector registers are properly aligned and that the VEC bit in the MSR register is set to 1 to avoid exceptions. Be cautious of overflow, as the operation uses modulo arithmetic, which wraps around without generating an exception.", "example": "vaddudm vd, va, vb" }, { "mnemonic": "vaddubs", "architecture": "PowerISA", "full_name": "Vector Add Unsigned Byte Saturate", "summary": "Adds the contents of two vector registers and saturates the result if it overflows.", "syntax": "vaddubs vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | VRT | VRA | VRB | 512", "hex_opcode": "0x10000200", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "512", "clean": "512" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vaddubs, each byte element in VSR[VRA+32] is added to the corresponding byte element in VSR[VRB+32]. If the sum exceeds 255, it saturates to 255 and sets the SAT field in VSCR.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 15\n src1 ←EXTZ(VSR[VRA+32].byte[i])\n src2 ←EXTZ(VSR[VRB+32].byte[i])\n VSR[VRT+32].byte[i] ←ui8_CLAMP(src1 + src2)\nend", "special_registers": "VSCR", "page_found": "Page 352 - 353", "programming_notes": "vaddubs is commonly used for adding unsigned byte elements in vector registers with saturation to handle overflow. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. The operation processes 16 bytes per instruction, and results are clamped to 255 if they exceed this value, setting the SAT field in VSCR accordingly.", "example": "vaddubs vd, va, vb" }, { "mnemonic": "vadduhs", "architecture": "PowerISA", "full_name": "Vector Add Unsigned Halfword Saturate", "summary": "Adds the contents of two vector registers and saturates the result.", "syntax": "vadduhs vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 576", "hex_opcode": "0x10000240", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "576", "clean": "576" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "page_found": "Page 1439 - 1440", "description": "Adds each of eight unsigned 16-bit halfwords in vA to the corresponding halfword in vB, with saturation at the unsigned range [0, 65535]. Any result exceeding 65535 is clamped to 65535; no status flags are affected.", "pseudocode": "for i in 0 to 7 do\n sum ← vA[i*16:(i+1)*16-1] + vB[i*16:(i+1)*16-1]\n if sum > 65535 then\n vD[i*16:(i+1)*16-1] ← 65535\n else\n vD[i*16:(i+1)*16-1] ← sum", "special_registers": "MSR", "programming_notes": "The vadduhs instruction is commonly used for adding pairs of unsigned halfwords with saturation, which prevents overflow by clamping results to the maximum representable value. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation processes 8 halfword elements in parallel, and both source registers must be properly aligned for optimal performance.", "example": "vadduhs vd, va, vb" }, { "mnemonic": "vadduws", "architecture": "PowerISA", "full_name": "Vector Add Unsigned Word Saturate", "summary": "Adds the contents of two vector registers and saturates the result if it exceeds 32 bits.", "syntax": "vadduws vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 640", "hex_opcode": "0x10000280", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "640", "clean": "640" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vadduws, each word element in VSR[VRA+32] is added to the corresponding word element in VSR[VRB+32]. If the sum exceeds 2^32 - 1, it saturates to 2^32 - 1 and sets the SAT field in VSCR.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n src1 ←EXTZ(VSR[VRA+32].word[i])\n src2 ←EXTZ(VSR[VRB+32].word[i])\n\n VSR[VRT+32].word[i] ←ui32_CLAMP(src1 + src2)\nend", "special_registers": "VSCR.SAT", "page_found": "Page 353 - 354", "programming_notes": "vadduws is used for adding unsigned 32-bit integers in vector registers with saturation. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will occur. The operation saturates sums exceeding 2^32 - 1 and sets the SAT field in VSCR to indicate saturation occurred.", "example": "vadduws vd, va, vb" }, { "mnemonic": "vaddsbs", "architecture": "PowerISA", "full_name": "Vector Add Signed Byte Saturate", "summary": "Adds 16 signed bytes with saturation (-128..127).", "syntax": "vaddsbs vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 768", "hex_opcode": "0x10000300", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "768", "clean": "768" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Adds each of sixteen signed 8-bit bytes in vA to the corresponding byte in vB, with saturation at the signed range [-128, 127]. Results below -128 are clamped to -128, and results above 127 are clamped to 127; no status flags are affected.", "pseudocode": "for i in 0 to 15 do\n sum ← SIGN_EXTEND(vA[i*8:(i+1)*8-1], 9) + SIGN_EXTEND(vB[i*8:(i+1)*8-1], 9)\n if sum > 127 then\n vD[i*8:(i+1)*8-1] ← 127\n else if sum < -128 then\n vD[i*8:(i+1)*8-1] ← -128\n else\n vD[i*8:(i+1)*8-1] ← sum[7:0]", "page_found": "Page 349", "special_registers": "MSR", "programming_notes": "The vaddsbs instruction is commonly used for vectorized addition of signed bytes, ensuring that results are clamped to the 8-bit signed integer range. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. This instruction operates on 16-byte vectors and processes each byte independently.", "example": "vaddsbs vd, va, vb" }, { "mnemonic": "vaddshs", "architecture": "PowerISA", "full_name": "Vector Add Signed Halfword Saturate", "summary": "Adds the contents of two vector registers and saturates the result if it overflows.", "syntax": "vaddshs vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 832", "hex_opcode": "0x10000340", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "832", "clean": "832" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vaddshs, each halfword element in VSR[VRA+32] is added to the corresponding halfword element in VSR[VRB+32]. The result is saturated if it exceeds the range of a signed 16-bit integer.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 7\n src1 ←EXTS(VSR[VRA+32].hword[i])\n src2 ←EXTS(VSR[VRB+32].hword[i])\n VSR[VRT+32].hword[i] ←si16_CLAMP(src1 + src2)\nend", "special_registers": "VSCR (SAT)", "page_found": "Page 349 - 350", "programming_notes": "vaddshs is used for adding signed halfwords with saturation. Ensure that the vector facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will occur. The operation saturates results if they exceed the 16-bit signed integer range, preventing overflow. This instruction operates on elements in the upper half of the VSX registers.", "example": "vaddshs vd, va, vb" }, { "mnemonic": "vaddsws", "architecture": "PowerISA", "full_name": "Vector Add Signed Word Saturate", "summary": "Adds 4 signed words with saturation.", "syntax": "vaddsws vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 896", "hex_opcode": "0x10000380", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "896", "clean": "896" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Adds each of four signed 32-bit words in vA to the corresponding word in vB, with saturation at the signed range [-2^31, 2^31-1]. Results are clamped to the valid signed 32-bit range; no status flags are affected.", "pseudocode": "for i in 0 to 3 do\n sum ← SIGN_EXTEND(vA[i*32:(i+1)*32-1], 33) + SIGN_EXTEND(vB[i*32:(i+1)*32-1], 33)\n if sum > 2147483647 then\n vD[i*32:(i+1)*32-1] ← 2147483647\n else if sum < -2147483648 then\n vD[i*32:(i+1)*32-1] ← -2147483648\n else\n vD[i*32:(i+1)*32-1] ← sum[31:0]", "page_found": "Page 350", "special_registers": "MSR", "programming_notes": "The vaddsws instruction is useful for adding signed integers with overflow protection, ensuring that results do not exceed the bounds of a 32-bit signed integer. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to 1 before using this instruction; otherwise, a Vector_Unavailable exception will be raised. Be cautious of potential performance overhead due to saturation checks, which can impact execution speed if many elements overflow.", "example": "vaddsws vd, va, vb" }, { "mnemonic": "vsububm", "architecture": "PowerISA", "full_name": "Vector Subtract Unsigned Byte Modulo", "summary": "Subtracts the contents of two vector registers and updates the result in another vector register using modulo operation for bytes.", "syntax": "vsububm vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 1024", "hex_opcode": "0x10000400", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1024", "clean": "1024" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vsububm, each byte element in VSR[VRB+32] is subtracted from the corresponding byte element in VSR[VRA+32], and the result is placed into the corresponding byte element of VSR[VRT+32]. The operation uses modulo arithmetic.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 15\n src1 ←EXTZ(VSR[VRA+32].byte[i])\n src2 ←EXTZ(VSR[VRB+32].byte[i])\n VSR[VRT+32].byte[i] ←CHOP8(src1 + ¬src2 + 1)\nend", "page_found": "Page 358 - 359", "special_registers": "MSR", "programming_notes": "This instruction performs vectorized byte-wise subtraction with modulo arithmetic. Ensure that the Vector Facility is enabled by checking and setting the appropriate bit in the MSR register. Be cautious of potential overflow issues due to the modulo operation, which can wrap around values. This instruction operates at a privilege level where the Vector Facility is accessible.", "example": "vsububm vd, va, vb" }, { "mnemonic": "vsubuhm", "architecture": "PowerISA", "full_name": "Vector Subtract Unsigned Halfword Modulo", "summary": "Subtracts 8 halfwords modulo 65536.", "syntax": "vsubuhm vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 1088", "hex_opcode": "0x10000440", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1088", "clean": "1088" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Subtracts each of eight unsigned 16-bit halfwords in vB from the corresponding halfword in vA, with results modulo 2^16 (wrapping on underflow). No status flags are affected; this is a basic VMX/AltiVec arithmetic operation.", "pseudocode": "for i in 0 to 7 do\n vD[i*16:(i+1)*16-1] ← (vA[i*16:(i+1)*16-1] - vB[i*16:(i+1)*16-1]) mod 2^16", "page_found": "Page 359", "special_registers": "MSR", "programming_notes": "This instruction is useful for performing element-wise subtraction of unsigned halfwords with modulo 65536, which can be particularly handy in graphics or audio processing where overflow needs to wrap around. Ensure that the vector registers are properly aligned and that the VEC bit in the MSR register is set to enable vector operations. Be cautious of potential performance overhead if used in tight loops without optimization.", "example": "vsubuhm vd, va, vb" }, { "mnemonic": "vsubudm", "architecture": "PowerISA", "full_name": "Vector Subtract Unsigned Doubleword Modulo", "summary": "Subtracts the contents of two vector registers and places the result in a third vector register, modulo operation.", "syntax": "vsubudm vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "000100 | vD | vA | vB | 10011 | 000000", "hex_opcode": "0x100004C0", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1216", "clean": "1216" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "page_found": "Page 1447 - 1448", "description": "Subtracts each of two unsigned 64-bit doublewords in vB from the corresponding doubleword in vA, with results modulo 2^64 (wrapping on underflow). No status flags are affected; this is a VMX/AltiVec arithmetic operation.", "pseudocode": "for i in 0 to 1 do\n vD[i*64:(i+1)*64-1] ← (vA[i*64:(i+1)*64-1] - vB[i*64:(i+1)*64-1]) mod 2^64", "special_registers": "MSR", "programming_notes": "This instruction is used for performing unsigned doubleword subtraction with modulo arithmetic. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation is performed on each pair of elements from two source vectors, and the results are stored in the destination vector. Be cautious with alignment as it may affect performance or cause exceptions if not properly managed.", "example": "vsubudm vd, va, vb" }, { "mnemonic": "vsububs", "architecture": "PowerISA", "full_name": "Vector Subtract Unsigned Byte Saturate", "summary": "Subtracts the contents of two vector registers and saturates the result to zero if it underflows.", "syntax": "vsububs vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 1536", "hex_opcode": "0x10000600", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1536", "clean": "1536" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vsububs, each byte element in VSR[VRA+32] is subtracted from the corresponding byte element in VSR[VRB+32]. If the result is less than zero, it saturates to zero and sets the SAT flag in VSCR.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 15\n src1 ←EXTZ(VSR[VRA+32].byte[i])\n src2 ←EXTZ(VSR[VRB+32].byte[i])\n VSR[VRT+32].byte[i] ←ui8_CLAMP(src1 + ¬src2 + 1)\nend", "special_registers": "VSCR.SAT", "page_found": "Page 360 - 361", "programming_notes": "Use vsububs for subtracting unsigned byte elements with saturation. Ensure vectors are properly aligned and check VSCR.SAT to verify saturation occurred. Requires vector facility enabled; otherwise, triggers an exception.", "example": "vsububs vd, va, vb" }, { "mnemonic": "vsubuhs", "architecture": "PowerISA", "full_name": "Vector Subtract Unsigned Halfword Saturate", "summary": "Subtracts 8 unsigned halfwords with saturation.", "syntax": "vsubuhs vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 1600", "hex_opcode": "0x10000640", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1600", "clean": "1600" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Subtracts each of eight unsigned 16-bit halfwords in vB from the corresponding halfword in vA, with saturation at the unsigned range [0, 65535]. Results below 0 are clamped to 0; no status flags are affected.", "pseudocode": "for i in 0 to 7 do\n diff ← vA[i*16:(i+1)*16-1] - vB[i*16:(i+1)*16-1]\n if diff < 0 then\n vD[i*16:(i+1)*16-1] ← 0\n else\n vD[i*16:(i+1)*16-1] ← diff", "page_found": "Page 361", "special_registers": "MSR, VSCR", "programming_notes": "This instruction is useful for performing element-wise unsigned subtraction on vectors with saturation to handle overflow. Ensure that the vector registers are properly aligned and that the VEC bit in the MSR register is set to 1. Be aware of potential performance implications due to saturation handling, which may affect throughput.", "example": "vsubuhs vd, va, vb" }, { "mnemonic": "vsubuws", "architecture": "PowerISA", "full_name": "Vector Subtract Unsigned Word Saturate", "summary": "Subtracts the contents of two vector registers and saturates the result if it underflows.", "syntax": "vsubuws vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 1664", "hex_opcode": "0x10000680", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1664", "clean": "1664" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vsubuws, each word element in VSR[VRB+32] is subtracted from the corresponding word element in VSR[VRA+32]. If the intermediate result is less than 0, it saturates to 0 and sets the SAT field in VSCR.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n src1 ←EXTZ(VSR[VRA+32].word[i])\n src2 ←EXTZ(VSR[VRB+32].word[i])\n VSR[VRT+32].word[i] ←ui32_CLAMP(src1 + ¬src2 + 1)\nend", "special_registers": "VSCR.SAT", "page_found": "Page 361 - 362", "programming_notes": "This instruction is commonly used for vectorized unsigned word subtraction with saturation, useful in image processing and other applications requiring bounded arithmetic. Ensure that the Vector Status and Control Register (VSCR) is properly managed to handle saturation flags. The operation saturates underflows to zero, so be cautious of cases where results might wrap around unexpectedly.", "example": "vsubuws vd, va, vb" }, { "mnemonic": "vsubsbs", "architecture": "PowerISA", "full_name": "Vector Subtract Signed Byte Saturate", "summary": "Subtracts 16 signed bytes with saturation.", "syntax": "vsubsbs vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 1792", "hex_opcode": "0x10000700", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1792", "clean": "1792" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Subtracts each of 16 signed 8-bit elements in vB from the corresponding element in vA, with saturation to the signed 8-bit range [-128, 127]. If overflow or underflow occurs, the result saturates to the minimum or maximum signed byte value. No condition register fields are affected.", "pseudocode": "for i in 0 to 15 do\n result ← vA[8*i:8*i+7] - vB[8*i:8*i+7]\n if result < -128 then vD[8*i:8*i+7] ← -128\n elsif result > 127 then vD[8*i:8*i+7] ← 127\n else vD[8*i:8*i+7] ← result", "page_found": "Page 357", "special_registers": "MSR", "programming_notes": "This instruction is commonly used in applications requiring vectorized arithmetic operations on signed bytes, such as image processing or audio signal processing. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation saturates results to prevent overflow or underflow, which can be crucial for maintaining data integrity in certain applications.", "example": "vsubsbs vd, va, vb" }, { "mnemonic": "vsubshs", "architecture": "PowerISA", "full_name": "Vector Subtract Signed Halfword Saturate", "summary": "Subtracts the contents of two vector registers and saturates the result to halfword elements.", "syntax": "vsubshs vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 1856", "hex_opcode": "0x10000740", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1856", "clean": "1856" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vsubshs, each signed halfword element in VSR[VRB+32] is subtracted from the corresponding signed halfword element in VSR[VRA+32]. The result is saturated if it exceeds the range of a signed 16-bit integer.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 7\n src1 ←EXTS(VSR[VRA+32].hword[i])\n src2 ←EXTS(VSR[VRB+32].hword[i])\n VSR[VRT+32].hword[i] ←si16_CLAMP(src1 + ¬src2 + 1)\nend", "special_registers": "VSCR (SAT)", "page_found": "Page 357 - 358", "programming_notes": "vsubshs is used for subtracting signed halfwords with saturation. Ensure that the vector facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will occur. The operation saturates results if they exceed the signed 16-bit integer range, preventing overflow. This instruction operates on elements in VSR[VRB+32] and VSR[VRA+32], storing the result in VSR[VRT+32].", "example": "vsubshs vd, va, vb" }, { "mnemonic": "vsubsws", "architecture": "PowerISA", "full_name": "Vector Subtract Signed Word Saturate", "summary": "Subtracts 4 signed words with saturation.", "syntax": "vsubsws vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 1920", "hex_opcode": "0x10000780", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1920", "clean": "1920" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Subtracts each of 4 signed 32-bit elements in vB from the corresponding element in vA, with saturation to the signed 32-bit range [-2147483648, 2147483647]. If overflow or underflow occurs, the result saturates to the minimum or maximum signed word value. No condition register fields are affected.", "pseudocode": "for i in 0 to 3 do\n result ← vA[32*i:32*i+31] - vB[32*i:32*i+31]\n if result < -2147483648 then vD[32*i:32*i+31] ← -2147483648\n elsif result > 2147483647 then vD[32*i:32*i+31] ← 2147483647\n else vD[32*i:32*i+31] ← result", "page_found": "Page 358", "special_registers": "MSR, VSCR", "programming_notes": "The vsubsws instruction is useful for performing vectorized subtraction of signed words with saturation, ensuring that results do not overflow. Ensure that the VEC bit in the MSR register is set to enable vector operations; otherwise, a Vector_Unavailable exception will be raised. Be aware that the SAT flag in the VSCR register indicates if any result was saturated during the operation.", "example": "vsubsws vd, va, vb" }, { "mnemonic": "xsaddsp", "architecture": "PowerISA", "full_name": "VSX Scalar Add Single-Precision", "summary": "Adds the contents of two single-precision floating-point numbers and places the result in a double-precision format.", "syntax": "xsaddsp XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "18 | XA | XB | 000000 | 000000 | 000000 | 000000 | 000000", "hex_opcode": "0xF0000000", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "0", "clean": "0" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:28 | 29 | 30 | 31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "The instruction adds the contents of src1 and src2, producing a sum with unbounded range and precision. The sum is normalized and rounded to single-precision using the rounding mode specified by RN. The result is placed into doubleword element 0 of VSR[XT] in double-precision format, while doubleword element 1 of VSR[XT] is set to 0.", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nreset_xflags()\nsrc1 ← bfp_CONVERT_FROM_BFP64(VSR[VRA+32].dword[0])\nsrc2 ← bfp_CONVERT_FROM_BFP64(VSR[VRB+32].dword[0])\nv ← bfp_ADD(src1, src2)\nrnd ← bfp_ROUND_TO_BFP32(FPSCR.RN, v)\nresult32 ← bfp32_CONVERT_FROM_BFP(rnd)\nresult64 ← bfp64_CONVERT_FROM_BFP(rnd)\nif vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\nif vxisi_flag=1 then SetFX(FPSCR.VXISI)\nif ox_flag=1 then SetFX(FPSCR.OX)\nif ux_flag=1 then SetFX(FPSCR.UX)\nif xx_flag=1 then SetFX(FPSCR.XX)\nvx_flag ← vxsnan_flag | vxisi_flag\nvex_flag ← FPSCR.VE & vx_flag\nif vex_flag=0 then do\n VSR[32×TX+T].dword[0] ← result64\n VSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000\n FPSCR.FPRF ← fprf_CLASS_BFP32(result32)\n FPSCR.FR ← inc_flag\n FPSCR.FI ← xx_flag\nend else do\n FPSCR.FR ← 0b0\n FPSCR.FI ← 0b0\nend", "special_registers": "FPSCR, VXSNAN, VXISI, OX, UX", "programming_notes": "Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.", "page_found": "Page 657 - 658", "example": "xsaddsp vs1, vs2, vs3" }, { "mnemonic": "xssubsp", "architecture": "PowerISA", "full_name": "VSX Scalar Subtract Single-Precision", "summary": "Subtracts the contents of two single-precision floating-point values and places the result in a vector register.", "syntax": "xssubsp XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "T | A | B | 8 | AX | BX | TX", "hex_opcode": "0xF0000040", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "8", "clean": "8" } ], "length": "32", "bit_positions": "0 | 1:4 | 5:9 | 10:15 | 16:20 | 21:25 | 26:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "The instruction subtracts the double-precision floating-point value in doubleword element 0 of VSR[XB] from the double-precision floating-point value in doubleword element 0 of VSR[XA], negates the result, and adds it to src1. The result is normalized and rounded to single-precision using the rounding mode specified by RN.", "pseudocode": "if src1 is NaN or src2 is NaN then\n v <- Q(src1) if src1 is SNaN else Q(src2) if src2 is SNaN else dQNaN\nelse if src1 is +Infinity and src2 is +Infinity then\n v <- +Infinity\n vxisi_flag <- 1\nelse if src1 is -Infinity and src2 is -Infinity then\n v <- -Infinity\n vxisi_flag <- 1\nelse if src1 is NZF and src2 is NZF then\n v <- S(src1, src2)\nelse if src1 is Zero and src2 is Zero then\n v <- Rezd\nelse if src1 is +Zero and src2 is -Zero then\n v <- +Zero\nelse if src1 is -Zero and src2 is +Zero then\n v <- -Zero\nelse if src1 is NZF and src2 is Zero then\n v <- src1\nelse if src1 is Zero and src2 is NZF then\n v <- -src2\nelse if src1 is +Infinity and src2 is NZF then\n v <- +Infinity\n vxisi_flag <- 1\nelse if src1 is NZF and src2 is +Infinity then\n v <- -Infinity\n vxisi_flag <- 1\nelse if src1 is -Infinity and src2 is NZF then\n v <- -Infinity\n vxisi_flag <- 1\nelse if src1 is NZF and src2 is -Infinity then\n v <- +Infinity\n vxisi_flag <- 1\nelse if src1 is QNaN or src2 is QNaN then\n v <- src1 if src1 is QNaN else src2 if src2 is QNaN else dQNaN\nelse if src1 is SNaN or src2 is SNaN then\n v <- Q(src1) if src1 is SNaN else Q(src2) if src2 is SNaN else dQNaN\n vxsnan_flag <- 1", "special_registers": "FPSCR, VSR[XT]", "programming_notes": "Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.", "page_found": "Page 681 - 682", "example": "xssubsp vs1, vs2, vs3" }, { "mnemonic": "xsmulsp", "architecture": "PowerISA", "full_name": "VSX Scalar Multiply Single-Precision", "summary": "Multiplies two single-precision floating-point numbers and stores the result in a doubleword element of a VSX register.", "syntax": "xsmulsp XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "60 | XT | XA | XB | 16", "hex_opcode": "0xF0000080", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "16", "clean": "16" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "Multiplies the single-precision floating-point value in the lower 32 bits of XA by the single-precision floating-point value in the lower 32 bits of XB, produces a single-precision result, and stores it in the lower 32 bits of XT. The upper 32 bits of XT are set to zero. FPSCR is updated with the exception flags and result class from the operation.", "pseudocode": "SP_A ← XA[32:63]\nSP_B ← XB[32:63]\nproduct ← SPFP_multiply(SP_A, SP_B)\nXT[0:31] ← 0\nXT[32:63] ← product\nFPSCR ← update_fpscr(FPSCR, product)", "special_registers": "FPSCR, VSR[XT]", "programming_notes": "Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.", "page_found": "Page 669 - 670", "example": "xsmulsp vs1, vs2, vs3" }, { "mnemonic": "xsdivsp", "architecture": "PowerISA", "full_name": "VSX Scalar Divide Single-Precision", "summary": "Divides the contents of two doubleword elements in VSX registers and places the result in a single-precision format.", "syntax": "xsdivsp XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "111100 | XA | XB | XT | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000", "hex_opcode": "0xF00000C0", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "24", "clean": "24" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "The instruction divides the double-precision floating-point value in doubleword element 0 of VSR[XB] by the double-precision floating-point value in doubleword element 0 of VSR[XA]. The quotient is normalized, rounded to single-precision using the rounding mode specified by RN, and placed into doubleword element 0 of VSR[XT] in double-precision format. Doubleword element 1 of VSR[XT] is set to 0.", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nreset_xflags()\nsrc1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])\nsrc2 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])\nv ←bfp_DIVIDE(src1,src2)\nrnd ←bfp_ROUND_TO_BFP32(FPSCR.RN,v)\nresult32 ←bfp32_CONVERT_FROM_BFP(rnd)\nresult64 ←bfp64_CONVERT_FROM_BFP(rnd)\nif vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\nif vxidi_flag=1 then SetFX(FPSCR.VXIDI)\nif vxzdz_flag=1 then SetFX(FPSCR.VXZDZ)\nvx_flag ←vxsnan_flag | vxidi_flag | vxzdz_flag\nvex_flag ←FPSCR.VE & vx_flag\nzex_flag ←FPSCR.ZE & zx_flag\nif vex_flag=0 & zex_flag=0 then do\n VSR[32×TX+T].dword[0] ←result64\n VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000\n FPSCR.FPRF ←fprf_CLASS_BFP32(result32)\n FPSCR.FR ←inc_flag\n FPSCR.FI ←xx_flag\nelse do\n FPSCR.FR ←0b0\n FPSCR.FI ←0b0\nend", "special_registers": "FPSCR, VXSNAN, VXIDI, VXZDZ, OX, UX, ZX, XX", "programming_notes": "Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.", "page_found": "Page 663 - 664", "example": "xsdivsp vs1, vs2, vs3" }, { "mnemonic": "xsmaxdp", "architecture": "PowerISA", "full_name": "Vector Scalar Maximum Double-Precision Floating-Point", "summary": "Compares the doubleword elements of two vector scalar registers and stores the maximum value in another vector scalar register.", "syntax": "xsmaxdp XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "60 | XT | XA | XB | 160", "hex_opcode": "0xF0000500", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "160", "clean": "160" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "Compares the double-precision floating-point value in XA with the value in XB and stores the maximum (or quiet NaN if either operand is NaN) in XT. Following IEEE 754 semantics, quiet NaNs propagate, and negative zero is considered less than positive zero. FPSCR is updated with the comparison result flags.", "pseudocode": "result ← DPFP_maximum(XA[0:63], XB[0:63])\nXT[0:63] ← result\nFPSCR ← update_fpscr(FPSCR, result)", "special_registers": "FPSCR, VXSNAN", "programming_notes": "This instruction can be used to operate on single-precision source operands. Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.", "page_found": "Page 794 - 795", "example": "xsmaxdp vs1, vs2, vs3" }, { "mnemonic": "xsmindp", "architecture": "PowerISA", "full_name": "VSX Scalar Minimum Double-Precision", "summary": "Computes the minimum of two double-precision floating-point values and places the result into a vector scalar register.", "syntax": "xsmindp XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "60 | XT | XA | XB | 168", "hex_opcode": "0xF0000540", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "168", "clean": "168" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "Compares the double-precision floating-point value in XA with the value in XB and stores the minimum (or quiet NaN if either operand is NaN) in XT. Following IEEE 754 semantics, quiet NaNs propagate, and negative zero is considered less than positive zero. FPSCR is updated with the comparison result flags.", "pseudocode": "result ← DPFP_minimum(XA[0:63], XB[0:63])\nXT[0:63] ← result\nFPSCR ← update_fpscr(FPSCR, result)", "special_registers": "FPSCR, VXSNAN", "programming_notes": "The minimum of +0 and -0 is -0. The minimum of a QNaN and any value is that value. The minimum of any value and an SNaN is that SNaN converted to a QNaN. FPRF, FR and FI are not modified. If a trap-enabled invalid operation exception occurs, VSR[XT] is not modified. This instruction can be used to operate on single-precision source operands.", "page_found": "Page 802 - 803", "example": "xsmindp vs1, vs2, vs3" }, { "mnemonic": "xssqrtdp", "architecture": "PowerISA", "full_name": "VSX Scalar Square Root Double-Precision", "summary": "Computes the unbounded-precision square root of a double-precision floating-point value and rounds it to double-precision format.", "syntax": "xssqrtdp XT, XB", "encoding": { "format": "XX2-form", "binary_pattern": "11110001 | 00000000 | 00000000 | 1000", "hex_opcode": "0xF000012C", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "0", "clean": "0" }, { "raw": "XB", "clean": "XB" }, { "raw": "75", "clean": "75" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XB", "desc": "Source" }, { "name": "VX", "desc": "Target Vector Register" }, { "name": "VB", "desc": "Source Vector Register" } ], "extension": "VSX", "description": "The instruction computes the square root of the double-precision floating-point value in doubleword element 0 of VSR[XB]. The result is placed into doubleword element 0 of VSR[XT] in double-precision format, with doubleword element 1 set to 0. The FPRF is updated to reflect the class and sign of the result, and FR and FI are set based on rounding operations.", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nreset_xflags()\nsrc ← bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])\nv ← bfp_SQUARE_ROOT(src)\nrnd ← bfp_ROUND_TO_BFP64(0b0, FPSCR.RN, v)\nresult ← bfp64_CONVERT_FROM_BFP(rnd)\nif vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\nif vxsqrt_flag=1 then SetFX(FPSCR.VXSQRT)\nif xx_flag=1 then SetFX(FPSCR.XX)\nvx_flag ← vxsnan_flag | vxsqrt_flag\nvex_flag ← FPSCR.VE & vx_flag\nif vex_flag=0 then do\n VSR[32×TX+T].dword[0] ← result\n VSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000\n FPSCR.FPRF ← fprf_CLASS_BFP64(result)\n FPSCR.FR ← inc_flag\n FPSCR.FI ← xx_flag\nend else do\n FPSCR.FR ← 0b0\n FPSCR.FI ← 0b0\nend", "special_registers": "FPSCR (FPRF, FR, FI, FX, XX), VXSNAN, VXSQRT", "programming_notes": "Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.", "page_found": "Page 671 - 672", "example": "xssqrtdp vs1, vs3" }, { "mnemonic": "xsabsdp", "architecture": "PowerISA", "full_name": "VSX Scalar Absolute Value Double-Precision", "summary": "Computes the absolute value of a double-precision floating-point number.", "syntax": "xsabsdp XT, XB", "encoding": { "format": "XX2-form", "binary_pattern": "60 | XT | 0 | XB | 345", "hex_opcode": "0xF0000564", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "0", "clean": "0" }, { "raw": "XB", "clean": "XB" }, { "raw": "345", "clean": "345" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XB", "desc": "Source" } ], "extension": "VSX", "description": "The absolute value of the double-precision floating-point operand in doubleword element 0 of VSR[XB] is placed into doubleword element 0 of VSR[XT] in double-precision format. The contents of doubleword element 1 of VSR[XT] are set to 0.", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nsrc ←VSR[32×BX+B].dword[0]\nLet XT be the value 32×TX + T.\nVSR[XT].dword[0] ←bfp64_ABSOLUTE(src)\nVSR[XT].dword[1] ←0x0000_0000_0000_0000", "programming_notes": "This instruction can be used to operate on a single-precision source operand.\nPrevious versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.", "page_found": "Page 642 - 643", "special_registers": "MSR", "example": "xsabsdp vs1, vs3" }, { "mnemonic": "xsnegdp", "architecture": "PowerISA", "full_name": "VSX Scalar Negate Double-Precision", "summary": "Negates the contents of a double-precision floating-point register and stores the result in another register.", "syntax": "xsnegdp XT, XB", "encoding": { "format": "XX2-form", "binary_pattern": "60 | T | B | BX | TX | 0 | 0", "hex_opcode": "0xF00005E4", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "0", "clean": "0" }, { "raw": "XB", "clean": "XB" }, { "raw": "361", "clean": "361" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XB", "desc": "Source" } ], "extension": "VSX", "description": "The instruction negates the value in VSR[32×BX+B].dword[0] (which represents a single-precision floating-point number) and places the result into VSR[32×TX+T].dword[0]. The contents of doubleword element 1 of VSR[XT] are set to 0.", "pseudocode": "if MSR.VSX=0 then\n VSX_Unavailable()\nsrc ←VSR[32×BX+B].dword[0]\nVSR[32×TX+T].dword[0] ←bfp64_NEGATE(src)\nVSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000", "programming_notes": "This instruction can be used to operate on a single-precision source operand. Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.", "page_found": "Page 645 - 646", "special_registers": "MSR", "example": "xsnegdp vs1, vs3" }, { "mnemonic": "xscmpodp", "architecture": "PowerISA", "full_name": "VSX Scalar Compare Ordered Double-Precision", "summary": "Compares two double-precision floating-point values and sets the condition register based on the comparison.", "syntax": "xscmpodp BF, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "60 | BF | / | XA | XB | 43", "hex_opcode": "0xF0000158", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "BF", "clean": "BF" }, { "raw": "/", "clean": "/" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "43", "clean": "43" } ], "length": "32", "bit_positions": "0:5 | 6:8 | 9:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "BF", "desc": "CR Field" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "Performs an ordered comparison of the double-precision floating-point values in XA and XB, setting the specified CR field (BF) with the comparison result: less-than, greater-than, equal, or unordered. If either operand is a signaling NaN, an invalid operation exception is raised in FPSCR. Quiet NaNs result in an unordered condition.", "pseudocode": "if isnan(XA[0:63]) | isnan(XB[0:63]) then\n FPSCR[VXVC] ← 1\n CR[BF*4:BF*4+3] ← 0001\nelsif XA[0:63] < XB[0:63] then\n CR[BF*4:BF*4+3] ← 1000\nelsif XA[0:63] > XB[0:63] then\n CR[BF*4:BF*4+3] ← 0100\nelse\n CR[BF*4:BF*4+3] ← 0010", "special_registers": "CR, FPSCR, VXSNAN, VXVC", "programming_notes": "This instruction can be used to operate on single-precision source operands.", "page_found": "Page 778 - 779", "example": "xscmpodp cr0, vs2, vs3" }, { "mnemonic": "xscmpudp", "architecture": "PowerISA", "full_name": "VSX Scalar Compare Unordered Double-Precision", "summary": "Compares two double-precision floating-point values and sets the condition register based on the comparison.", "syntax": "xscmpudp BF, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "111100 | XA | XB | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000", "hex_opcode": "0xF0000118", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "BF", "clean": "BF" }, { "raw": "/", "clean": "/" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "35", "clean": "35" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "BF", "desc": "CR Field" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" }, { "name": "VS32", "desc": "Target Vector Register" } ], "extension": "VSX", "description": "The instruction compares the double-precision floating-point value in doubleword element 0 of VSR[XA] with the double-precision floating-point value in doubleword element 0 of VSR[XB]. The result is placed into CR field BF and the FPCC. If either operand is a NaN, VXSNAN is set.", "pseudocode": "if 'xscmpudp' then\n src1 <- VSR[XA][0]\n src2 <- VSR[XB][0]\n cc <- C(src1, src2)\n FPCC <- cc\n CR[BF] <- cc\n if vxsnan_flag then\n fx(VXSNAN)\n if VE and not ignore-exception mode then\n error()\n", "special_registers": "CR, FPSCR", "programming_notes": "This instruction can be used to operate on single-precision source operands. Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register.", "page_found": "Page 781 - 782", "example": "xscmpudp cr0, vs2, vs3" }, { "mnemonic": "vsl", "architecture": "PowerISA", "full_name": "Vector Shift Left", "summary": "Shifts the contents of a vector register left by a specified number of bits.", "syntax": "vsl vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 452", "hex_opcode": "0x100001C4", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "452", "clean": "452" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Data" }, { "name": "vB", "desc": "Shift Count" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Shift Amount Vector Register" } ], "extension": "VMX (AltiVec)", "description": "The contents of VSR[VRA+32] are shifted left by the number of bits specified in bits 125:127 of VSR[VRB+32]. Bits shifted out of bit 0 are lost, and zeros are supplied to the vacated bits on the right. The result is placed into VSR[VRT+32], except if, for any byte element in VSR[VRB+32], the low-order 3 bits are not equal to the shift amount, then VSR[VRT+32] is undefined.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nsh ←VSR[VRB+32].bit[125:127]\nt ←1\ndo i = 0 to 14\n t ←t & (VSR[VRB+32].byte[i].bit[5:7] = sh)\nend\nif t=1 then\n VSR[VRT+32] ←VSR[VRA+32] << sh\nelse\n VSR[VRT+32] ←UNDEFINED", "page_found": "Page 325 - 326", "special_registers": "MSR", "programming_notes": "The vsl instruction shifts the contents of a vector register left by a specified number of bits. Ensure that the shift amount is consistent across all byte elements in the control vector to avoid undefined results. This instruction requires the Vector Facility (MSR.VEC) to be enabled; otherwise, it will raise an exception.", "example": "vsl vd, va, vb" }, { "mnemonic": "vsr", "architecture": "PowerISA", "full_name": "Vector Shift Right", "summary": "Shifts vector right by octet count in vB.", "syntax": "vsr vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 708", "hex_opcode": "0x100002C4", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "708", "clean": "708" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Data" }, { "name": "vB", "desc": "Shift Count" } ], "extension": "VMX (AltiVec)", "description": "Shifts the 128-bit value in vA right by the number of octets (bytes) specified in the low 5 bits of vB, filling vacated positions on the left with zeros. The shift amount is taken from bits 123-127 of vB (the low-order 5 bits). No condition register fields are affected.", "page_found": "Page 290", "programming_notes": "The vsr instruction is commonly used for bit manipulation in vector operations, where each element of the vector is shifted right by a number of bits specified in a control register. Ensure that the control register contains valid shift amounts to avoid unexpected results. This operation does not require any specific privilege level and will not generate exceptions unless there are alignment issues with the vector data.", "pseudocode": "shift_count ← vB[123:127]\nif shift_count > 16 then shift_count ← 16\nvD ← vA >> (shift_count * 8)", "example": "vsr vd, va, vb" }, { "mnemonic": "vslo", "architecture": "PowerISA", "full_name": "Vector Shift Left by Octet", "summary": "Shifts the contents of a vector register left by a specified number of bytes.", "syntax": "vslo vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | VRT | VRA | VRB | 1036", "hex_opcode": "0x1000040C", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1036", "clean": "1036" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Data" }, { "name": "vB", "desc": "Shift Count" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Shift Count Vector Register" }, { "name": "VZ", "desc": "Target Vector Register" }, { "name": "VX", "desc": "Source Vector Register" }, { "name": "VY", "desc": "Shift Count Vector Register" } ], "extension": "VMX (AltiVec)", "description": "The contents of VSR[VRA+32] are shifted left by the number of bytes specified in bits 121:124 of VSR[VRB+32]. Bytes shifted out of byte 0 are lost, and zeros are supplied to the vacated bytes on the right. The result is placed into VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nshb ← VSR[VRB+32].bit[121:124] << 3\nVSR[VRT+32] ← VSR[VRA+32] << shb", "page_found": "Page 326 - 328", "programming_notes": "A pair of these instructions, specifying the same shift count register, can be used to shift the contents of a VSR left or right by the number of bits (0-127) specified in the shift count register.", "special_registers": "MSR", "example": "vslo vd, va, vb" }, { "mnemonic": "vsro", "architecture": "PowerISA", "full_name": "Vector Shift Right by Octet", "summary": "Shifts vector right by byte count.", "syntax": "vsro vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 1100", "hex_opcode": "0x1000044C", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1100", "clean": "1100" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Data" }, { "name": "vB", "desc": "Shift Count" } ], "extension": "VMX (AltiVec)", "description": "Shifts the 128-bit value in vA right by the number of octets (bytes) specified in the low 4 bits of vB, filling vacated positions on the left with zeros. This instruction is similar to vsr but uses only the low 4 bits of the shift count, limiting the shift to 0-15 bytes. No condition register fields are affected.", "pseudocode": "shift_count ← vB[124:127]\nvD ← vA >> (shift_count * 8)", "page_found": "Page 327", "special_registers": "MSR", "programming_notes": "The vsro instruction shifts the contents of a vector register right by a specified number of bytes. Ensure that the shift amount is within the valid range (0-15) to avoid undefined behavior. This instruction requires the VEC bit in the MSR to be set; otherwise, it will raise an exception. Be cautious with alignment as shifting by byte boundaries can lead to unexpected results if not handled properly.", "example": "vsro vd, va, vb" }, { "mnemonic": "vrlb", "architecture": "PowerISA", "full_name": "Vector Rotate Left Byte", "summary": "Rotates each byte of the source vector left by a specified number of bits.", "syntax": "vrlb vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 4", "hex_opcode": "0x10000004", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "4", "clean": "4" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Data" }, { "name": "vB", "desc": "Rotate Count" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Shift Control Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vrlb, each byte in VSR[VRA+32] is rotated left by the number of bits specified in the low-order 3 bits of the corresponding byte in VSR[VRB+32]. The result is stored in VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 7\n src ← VSR[VRA+32].byte[i]\n sh ← VSR[VRB+32].byte[i].bit[5:7]\n VSR[VRT+32].byte[i] ← src <<< sh", "page_found": "Page 430 - 431", "special_registers": "MSR", "programming_notes": "The vrlb instruction rotates each byte in the source vector left by a specified number of bits determined by another vector. Ensure that the Vector Facility is enabled (MSR.VEC=1) to avoid exceptions. The shift amount is derived from the high-order 3 bits of each byte in the second vector, so be cautious with bit manipulation to achieve the desired rotation.", "example": "vrlb vd, va, vb" }, { "mnemonic": "vrlh", "architecture": "PowerISA", "full_name": "Vector Rotate Left Halfword", "summary": "Rotates each halfword left.", "syntax": "vrlh vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 68", "hex_opcode": "0x10000044", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "68", "clean": "68" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Data" }, { "name": "vB", "desc": "Rotate Count" } ], "extension": "VMX (AltiVec)", "description": "Rotates each of the eight 16-bit elements in vA left by the number of bits specified by the corresponding 16-bit element in vB. The rotate count is masked to bits 0-3 (modulo 16). No condition register or status flags are affected.", "pseudocode": "for i in 0 to 7 do\n shift_amount ← vB[i*16+0:i*16+15] & 0xF\n vD[i*16+0:i*16+15] ← ROTL16(vA[i*16+0:i*16+15], shift_amount)", "page_found": "Page 431", "special_registers": "MSR", "programming_notes": "The vrlh instruction is commonly used for bit manipulation tasks that require rotating halfwords within a vector. Ensure that the source and destination vectors are properly aligned to avoid data corruption. This instruction operates at user privilege level, but if MSR.VEC is not set, it will raise a Vector_Unavailable exception. Performance may vary based on the specific implementation and the alignment of the input vectors.", "example": "vrlh vd, va, vb" }, { "mnemonic": "vrlw", "architecture": "PowerISA", "full_name": "Vector Rotate Left Word", "summary": "Rotates each word element of the source vector left by a specified number of bits.", "syntax": "vrlw vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | VRT | VRA | VRB | 132", "hex_opcode": "0x10000084", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "132", "clean": "132" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Data" }, { "name": "vB", "desc": "Rotate Count" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vrlw, each word element in VSR[VRA+32] is rotated left by the number of bits specified in the low-order 5 bits of the corresponding word element in VSR[VRB+32]. The result is placed into the corresponding word element in VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n src1 ← VSR[VRA+32].word[i]\n sh ← VSR[VRB+32].word[i].bit[27:31]\n VSR[VRT+32].word[i] ← src1 <<< sh", "page_found": "Page 431 - 432", "special_registers": "MSR", "programming_notes": "The vrlw instruction is commonly used for performing bitwise rotations on vector elements. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to 1; otherwise, a Vector_Unavailable exception will be raised. The shift amount is determined by the low-order 5 bits of each word element in the second source vector register (VRB). Be cautious with alignment as unaligned access can lead to performance penalties or exceptions depending on the system configuration.", "example": "vrlw vd, va, vb" }, { "mnemonic": "vrld", "architecture": "PowerISA", "full_name": "Vector Rotate Left Doubleword", "summary": "Rotates each doubleword left.", "syntax": "vrld vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 196", "hex_opcode": "0x100000C4", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "196", "clean": "196" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Data" }, { "name": "vB", "desc": "Rotate Count" } ], "extension": "VMX (AltiVec)", "description": "Rotates each of the two 64-bit elements in vA left by the number of bits specified by the corresponding 64-bit element in vB. The rotate count is masked to bits 0-5 (modulo 64). No condition register or status flags are affected.", "pseudocode": "for i in 0 to 1 do\n shift_amount ← vB[i*64+0:i*64+63] & 0x3F\n vD[i*64+0:i*64+63] ← ROTL64(vA[i*64+0:i*64+63], shift_amount)", "page_found": "Page 432", "special_registers": "MSR", "programming_notes": "The vrld instruction is commonly used for bit manipulation tasks that require rotating doublewords within a vector. Ensure that the source vectors are properly aligned to avoid unexpected behavior. This instruction operates at user privilege level and will raise an exception if the VEC bit in the MSR register is not set.", "example": "vrld vd, va, vb" }, { "mnemonic": "daddq", "architecture": "PowerISA", "full_name": "Decimal Add Quad-Precision", "summary": "Adds two 128-bit DFP numbers.", "syntax": "daddq vD, vA, vB", "encoding": { "format": "X-form", "binary_pattern": "63 | vD | vA | vB | 2 | /", "hex_opcode": "0xFC000004", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "2", "clean": "2" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "Decimal Floating-Point", "description": "Adds two 128-bit Decimal Floating-Point (DFP) values held in vA and vB, storing the result in vD. The operation follows DFP semantics, respecting the current rounding mode in FPSCR and producing an exact result or DFP overflow/underflow exception as appropriate. The FPSCR is updated with exception flags.", "page_found": "Page 240", "special_registers": "FPSCR", "programming_notes": "The daddq instruction is used for adding two quad-precision decimal numbers. Ensure that the operands are correctly aligned to avoid precision errors. Be aware of potential overflow conditions, which will be indicated in the FPSCR register. This operation requires floating-point privilege level access.", "pseudocode": "vD ← vA + vB (DFP arithmetic)\nFPSCR ← updated with exception flags (XX, ZX, UX, OX, IE)", "example": "daddq vd, va, vb" }, { "mnemonic": "dsubq", "architecture": "PowerISA", "full_name": "Decimal Subtract Quad-Precision", "summary": "Subtracts two 128-bit DFP numbers.", "syntax": "dsubq vD, vA, vB", "encoding": { "format": "X-form", "binary_pattern": "63 | vD | vA | vB | 514 | /", "hex_opcode": "0xFC000404", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "514", "clean": "514" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "Decimal Floating-Point", "description": "Subtracts the 128-bit Decimal Floating-Point value in vB from vA, storing the result in vD. The operation follows DFP semantics, respecting the current rounding mode in FPSCR and producing an exact result or DFP exception as appropriate. The FPSCR is updated with exception flags.", "pseudocode": "vD ← vA - vB (DFP arithmetic)\nFPSCR ← updated with exception flags (XX, ZX, UX, OX, IE)", "page_found": "Page 241", "special_registers": "FPSCR", "programming_notes": "The dsubq instruction is used for precise decimal subtraction of quad-precision numbers. Ensure that the operands are correctly aligned and formatted to avoid precision loss. The result's rounding mode is controlled by the FPSCR register, so verify DRN settings before execution. This operation requires floating-point privilege level.", "example": "dsubq vd, va, vb" }, { "mnemonic": "dmulq", "architecture": "PowerISA", "full_name": "Decimal Multiply Quad-Precision", "summary": "Multiplies two 128-bit DFP numbers.", "syntax": "dmulq vD, vA, vB", "encoding": { "format": "X-form", "binary_pattern": "63 | vD | vA | vB | 34 | /", "hex_opcode": "0xFC000044", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "34", "clean": "34" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "Decimal Floating-Point", "description": "Multiplies two 128-bit Decimal Floating-Point values in vA and vB, storing the result in vD. The operation follows DFP semantics, respecting the current rounding mode in FPSCR. The result may be rounded or may signal overflow, underflow, or inexact exception. The FPSCR is updated with exception flags.", "pseudocode": "vD ← vA × vB (DFP arithmetic)\nFPSCR ← updated with exception flags (XX, ZX, UX, OX, IE)", "page_found": "Page 242", "special_registers": "FPSCR", "programming_notes": "The dmulq instruction is used for multiplying two decimal floating-point numbers with quad-precision. Ensure that the operands are correctly aligned and formatted as DFP. The result's precision is controlled by the FPSCR register, specifically the DRN bits. Be aware of potential rounding errors based on the target format precision.", "example": "dmulq vd, va, vb" }, { "mnemonic": "ddivq", "architecture": "PowerISA", "full_name": "Decimal Divide Quad-Precision", "summary": "Divides two 128-bit DFP numbers.", "syntax": "ddivq vD, vA, vB", "encoding": { "format": "X-form", "binary_pattern": "63 | vD | vA | vB | 546 | /", "hex_opcode": "0xFC000444", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "546", "clean": "546" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "Decimal Floating-Point", "description": "Divides the 128-bit Decimal Floating-Point value in vA by the value in vB, storing the result in vD. The operation follows DFP semantics, respecting the current rounding mode in FPSCR. Division by zero signals the ZX exception, and inexact results are rounded according to FPSCR[RN]. The FPSCR is updated with exception flags.", "pseudocode": "vD ← vA ÷ vB (DFP arithmetic)\nFPSCR ← updated with exception flags (XX, ZX, UX, OX, IE)", "page_found": "Page 243", "special_registers": "FPSCR", "programming_notes": "The ddivq instruction is used for performing decimal division with quad-precision operands. Ensure that the operands are correctly aligned and formatted to avoid precision loss. The result rounding mode is controlled by the DRN field in the FPSCR register, so verify this setting before execution. This instruction operates at a privilege level that allows access to floating-point registers and may raise exceptions if operands are invalid or division by zero occurs.", "example": "ddivq vd, va, vb" }, { "mnemonic": "dcmpuq", "architecture": "PowerISA", "full_name": "Decimal Compare Unordered Quad-Precision", "summary": "Compares two 128-bit DFP numbers (Non-signaling).", "syntax": "dcmpuq BF, vA, vB", "encoding": { "format": "X-form", "binary_pattern": "63 | BF | / | vA | vB | 642 | /", "hex_opcode": "0xFC000504", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "BF", "clean": "BF" }, { "raw": "/", "clean": "/" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "642", "clean": "642" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:8 | 9:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "BF", "desc": "CR Field" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "Decimal Floating-Point", "description": "Compares two 128-bit Decimal Floating-Point values in vA and vB without signaling an exception on QNaN operands (unordered comparison). The result is written to the condition register field BF as: LT, GT, EQ, or UN (unordered). NaN comparisons result in UN, and FPSCR[VXSNAN] is not set unless SNaN is present.", "special_registers": "FPSCR", "programming_notes": "Use dcmpuq for comparing two DFP operands while handling unordered cases, which include NaNs. Ensure that the operands are properly aligned and check the FPSCR for exception conditions after execution.", "pseudocode": "if vA is NaN or vB is NaN then\n CR[BF] ← 0b0001 (UN)\nelse if vA < vB then\n CR[BF] ← 0b1000 (LT)\nelse if vA > vB then\n CR[BF] ← 0b0100 (GT)\nelse\n CR[BF] ← 0b0010 (EQ)", "example": "dcmpuq cr0, va, vb" }, { "mnemonic": "dcmpoq", "architecture": "PowerISA", "full_name": "Decimal Compare Ordered Quad-Precision", "summary": "Compares two DFP values and sets the condition register based on their order.", "syntax": "dcmpoq BF, vA, vB", "encoding": { "format": "X-form", "binary_pattern": "63 | BF | / | vA | vB | 130 | /", "hex_opcode": "0xFC000104", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "BF", "clean": "BF" }, { "raw": "/", "clean": "/" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "130", "clean": "130" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:8 | 9:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "BF", "desc": "CR Field" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "RB", "desc": "Source General Purpose Register" } ], "extension": "Decimal Floating-Point", "pseudocode": "if vA is SNaN or vB is SNaN then\n FPSCR[VXSNAN] ← 1\nif vA is NaN or vB is NaN then\n CR[BF] ← 0b0001 (UN)\nelse if vA < vB then\n CR[BF] ← 0b1000 (LT)\nelse if vA > vB then\n CR[BF] ← 0b0100 (GT)\nelse\n CR[BF] ← 0b0010 (EQ)", "special_registers": "CR0, FPSCR", "page_found": "Page 1392 - 1393", "description": "Compares two 128-bit Decimal Floating-Point values in vA and vB with signaling behavior on NaN (ordered comparison). The result is written to the condition register field BF as: LT, GT, EQ, or UN (unordered). If either operand is QNaN, the VXSNAN exception is raised and FPSCR[VE] or FPSCR[FEX] handling applies; SNaN always signals VXSNAN.", "programming_notes": "The dcmpoq instruction is used to compare two quad-precision decimal floating-point numbers. It sets the CR0 register field to indicate whether the first operand is less than, greater than, or equal to the second operand. Ensure that operands are properly aligned and that the FPSCR (Floating Point Status and Control Register) is correctly configured for accurate comparison results.", "example": "dcmpoq cr0, va, vb" }, { "mnemonic": "dquaq", "architecture": "PowerISA", "full_name": "Decimal Quantize Quad-Precision", "summary": "Adjusts exponent of 128-bit DFP number.", "syntax": "dquaq vD, vA, vB", "encoding": { "format": "X-form", "binary_pattern": "63 | vD | vA | vB | 66 | /", "hex_opcode": "0xFC000006", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "66", "clean": "66" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Source" }, { "name": "vB", "desc": "Reference" } ], "extension": "Decimal Floating-Point", "description": "Quantizes a 128-bit decimal floating-point number in vA to match the exponent of the reference value in vB, producing a result in vD. The operation adjusts the exponent and coefficient of the source operand while preserving the value's significance. Rounding is performed if necessary according to the current DFP rounding mode in FPSCR. The instruction is part of the Decimal Floating-Point extension.", "pseudocode": "vD ← QuantizeDFP128(vA, vB, FPSCR[RN])", "page_found": "Page 251", "special_registers": "FPSCR", "programming_notes": "The dquaq instruction is used to convert and round a decimal floating-point number to a specified exponent. Ensure the operand is correctly aligned and check the FPSCR for rounding mode settings. This instruction operates at the problem state privilege level and may raise exceptions if overflow occurs or if invalid operands are provided.", "example": "dquaq vd, va, vb" }, { "mnemonic": "drrndq", "architecture": "PowerISA", "full_name": "Decimal Reround Quad-Precision", "summary": "Rerounds a 128-bit DFP number to fewer digits.", "syntax": "drrndq vD, vA, vB", "encoding": { "format": "X-form", "binary_pattern": "63 | vD | vA | vB | 98 | /", "hex_opcode": "0xFC000046", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "98", "clean": "98" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Source" }, { "name": "vB", "desc": "Control" } ], "extension": "Decimal Floating-Point", "description": "Rerounds a 128-bit decimal floating-point number in vA to a precision specified by control information in vB, storing the result in vD. This operation reduces the number of significant digits while adjusting the exponent accordingly. Rounding uses the mode specified in FPSCR[RN]. The instruction is part of the Decimal Floating-Point extension.", "page_found": "Page 253", "special_registers": "FPSCR", "programming_notes": "The drrndq instruction is used for precise decimal arithmetic operations, particularly useful in financial applications where exact decimal representation is crucial. Ensure that the source operands (FRA and FRB) are correctly aligned and formatted as quad-precision decimals to avoid precision loss. The rounding mode control (RMC) should be set according to the desired rounding behavior, such as round-to-nearest or truncate. This instruction operates at a privilege level that allows access to floating-point operations, and it may raise exceptions if operands are out of range or if there are invalid operations.", "pseudocode": "vD ← ReroundDFP128(vA, vB, FPSCR[RN])", "example": "drrndq vd, va, vb" }, { "mnemonic": "dcffixq", "architecture": "PowerISA", "full_name": "Decimal Convert From Fixed Quad-Precision", "summary": "Converts 64-bit integer to 128-bit DFP.", "syntax": "dcffixq vD, vB", "encoding": { "format": "X-form", "binary_pattern": "63 | vD | 0 | vB | 802 | /", "hex_opcode": "0xFC000642", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "802", "clean": "802" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" } ], "extension": "Decimal Floating-Point", "special_registers": "FPSCR", "description": "Converts a 64-bit signed fixed-point integer from vB into a 128-bit decimal floating-point number, storing the result in vD. The integer is interpreted as an exact value with an implied exponent of zero. No rounding is required since the conversion is exact. The instruction is part of the Decimal Floating-Point extension.", "pseudocode": "vD ← ConvertFromFixedDFP128(vB[0:63])", "example": "dcffixq vd, vb" }, { "mnemonic": "dctfixq", "architecture": "PowerISA", "full_name": "Decimal Convert To Fixed Quad-Precision", "summary": "Converts 128-bit DFP to 64-bit integer.", "syntax": "dctfixq vD, vB", "encoding": { "format": "X-form", "binary_pattern": "63 | vD | 0 | vB | 290 | /", "hex_opcode": "0xFC000244", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "290", "clean": "290" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" } ], "extension": "Decimal Floating-Point", "description": "Converts a 128-bit decimal floating-point number from vB into a 64-bit signed integer, storing the result in vD. The conversion rounds toward zero (truncates). If the DFP value is out of range for a 64-bit integer or is NaN, the result is undefined and FPSCR status flags may be set. The instruction is part of the Decimal Floating-Point extension.", "pseudocode": "vD ← ConvertToFixedDFP128(vB, FPSCR[RN])", "page_found": "Page 264", "special_registers": "FPSCR", "programming_notes": "The dctfixq instruction is used to convert a DFP Extended value to a 64-bit signed integer. It rounds the result and preserves the sign of the source operand. If the source is zero, the result is explicitly set to +0. This instruction operates at the FPSCR privilege level and may raise exceptions based on rounding modes or overflow conditions.", "example": "dctfixq vd, vb" }, { "mnemonic": "dxexq", "architecture": "PowerISA", "full_name": "Decimal Extract Exponent Quad-Precision", "summary": "Extracts exponent from 128-bit DFP.", "syntax": "dxexq vD, vB", "encoding": { "format": "X-form", "binary_pattern": "63 | vD | 0 | vB | 354 | /", "hex_opcode": "0xFC0002C4", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "354", "clean": "354" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" } ], "extension": "Decimal Floating-Point", "description": "Extracts the exponent field from a 128-bit decimal floating-point number in vB and stores it as a 64-bit signed integer in vD. For normal numbers, the result is the biased exponent; for special values (zero, infinity, NaN), the result follows the DFP specification. The instruction is part of the Decimal Floating-Point extension.", "page_found": "Page 267", "special_registers": "FPSCR", "programming_notes": "The dxexq instruction is used to extract the biased exponent from a quad-precision decimal floating-point number. Ensure the source operand is properly aligned, as misalignment can lead to exceptions. This operation requires FPSCR (Floating Point Status and Control Register) to be correctly set for proper rounding modes and exception handling.", "pseudocode": "vD ← ExponentExtractDFP128(vB)", "example": "dxexq vd, vb" }, { "mnemonic": "diexq", "architecture": "PowerISA", "full_name": "Decimal Insert Exponent Quad-Precision", "summary": "Inserts exponent into 128-bit DFP.", "syntax": "diexq vD, vA, vB", "encoding": { "format": "X-form", "binary_pattern": "63 | vD | vA | vB | 866 | /", "hex_opcode": "0xFC0006C4", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "866", "clean": "866" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Coeff" }, { "name": "vB", "desc": "Exp" } ], "extension": "Decimal Floating-Point", "description": "Inserts a 64-bit signed exponent from vB into a 128-bit DFP coefficient from vA, producing a complete 128-bit DFP number in vD. The coefficient in vA is interpreted as having an exponent of zero, and the exponent from vB replaces it. The resulting value may be a normal number, zero, or special value depending on the inputs. The instruction is part of the Decimal Floating-Point extension.", "page_found": "Page 267", "special_registers": "FPSCR", "programming_notes": "The `diexq` instruction is used to insert the biased exponent from one decimal floating-point (DFP) operand into another. Ensure both operands are properly aligned and that the FPSCR register is correctly configured for desired rounding modes and exception handling. This instruction operates at the problem state privilege level, so ensure your program has the appropriate privileges. Be cautious of potential exceptions such as invalid operations or overflow, which may require additional error handling code.", "pseudocode": "vD ← InsertExponentDFP128(vA, vB)", "example": "diexq vd, va, vb" }, { "mnemonic": "denbcdq", "architecture": "PowerISA", "full_name": "Decimal Encode BCD Quad-Precision", "summary": "Encodes 128-bit DFP to BCD.", "syntax": "denbcdq vD, vB, S", "encoding": { "format": "X-form", "binary_pattern": "63 | vD | S | vB | 834 | /", "hex_opcode": "0xFC000684", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "vD", "clean": "vD" }, { "raw": "S", "clean": "S" }, { "raw": "vB", "clean": "vB" }, { "raw": "834", "clean": "834" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "S", "desc": "Sign" } ], "extension": "Decimal Floating-Point", "description": "Encodes a 128-bit decimal floating-point number from vB into binary-coded decimal (BCD) format, storing the result in vD. The sign field S specifies how the sign is encoded. The instruction converts the DFP representation to BCD digits with appropriate sign handling. The instruction is part of the Decimal Floating-Point extension.", "pseudocode": "vD ← EncodeBCDDFP128(vB, S)", "special_registers": "FPSCR", "programming_notes": "The denbcdq instruction is used to convert BCD values into DPD format, which is essential for handling high-precision decimal arithmetic. Ensure that the input data is correctly aligned and formatted as BCD before encoding. This instruction operates at user privilege level and may raise exceptions if the input data contains invalid BCD values.", "example": "denbcdq vd, vb, 0" }, { "mnemonic": "ddedpdq", "architecture": "PowerISA", "full_name": "Decimal Decode DPD Quad-Precision", "summary": "Decodes BCD to 128-bit DFP.", "syntax": "ddedpdq vD, vB, SP", "encoding": { "format": "X-form", "binary_pattern": "63 | vD | SP | vB | 322 | /", "hex_opcode": "0xFC000284", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "vD", "clean": "vD" }, { "raw": "SP", "clean": "SP" }, { "raw": "vB", "clean": "vB" }, { "raw": "322", "clean": "322" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "SP", "desc": "Sign" } ], "extension": "Decimal Floating-Point", "description": "Decodes a binary-coded decimal (BCD) value from vB into a 128-bit decimal floating-point number, storing the result in vD. The sign field SP specifies how to interpret the sign encoding in the BCD representation. The instruction converts BCD digits to the internal DFP representation. The instruction is part of the Decimal Floating-Point extension.", "pseudocode": "vD ← DecodeDFP128(vB, SP)", "special_registers": "FPSCR", "programming_notes": "The ddedpdq instruction is used to convert a DPD-encoded decimal value from one register to BCD format in another. Ensure that the source register contains valid DPD data; otherwise, the result will be undefined. This operation does not require any specific privilege level but may alter the FPSCR register based on the conversion outcome.", "example": "ddedpdq vd, vb, 0" }, { "mnemonic": "vspltb", "architecture": "PowerISA", "full_name": "Vector Splat Byte", "summary": "Splat a byte from one vector element into all elements of another vector.", "syntax": "vspltb vD, vB, UIM", "encoding": { "format": "VX-form", "binary_pattern": "1001010 | VRT | UIM | VRB", "hex_opcode": "0x1000020C", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "UIM", "clean": "UIM" }, { "raw": "vB", "clean": "vB" }, { "raw": "524", "clean": "524" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "UIM", "desc": "Index" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "Splats (replicates) a single byte element from vB across all 16 byte elements of vD. The byte element selected is determined by the 4-bit unsigned immediate UIM (where UIM=0 selects byte 0, UIM=15 selects byte 15 in big-endian order). No status flags are affected. This is a VMX/AltiVec instruction.", "pseudocode": "index ← UIM\nvD ← replicate(vB[index*8:index*8+7] to all 16 byte positions)", "programming_notes": "The Vector Splat instructions can be used in preparation for performing arithmetic for which one source vector is to consist of elements that all have the same value (e.g., multiplying all elements of a VSR by a constant).", "page_found": "Page 318 - 320", "special_registers": "MSR", "example": "vspltb vd, vb, uim" }, { "mnemonic": "vsplth", "architecture": "PowerISA", "full_name": "Vector Splat Halfword", "summary": "Duplicates a halfword element across the vector.", "syntax": "vsplth vD, vB, UIM", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | UIM | vB | 588", "hex_opcode": "0x1000024C", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "UIM", "clean": "UIM" }, { "raw": "vB", "clean": "vB" }, { "raw": "588", "clean": "588" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "UIM", "desc": "Index" } ], "extension": "VMX (AltiVec)", "description": "Splats (replicates) a single halfword element from vB across all 8 halfword elements of vD. The halfword element selected is determined by the 3-bit unsigned immediate UIM (where UIM=0 selects halfword 0, UIM=7 selects halfword 7 in big-endian order). No status flags are affected. This is a VMX/AltiVec instruction.", "pseudocode": "index ← UIM\nvD ← replicate(vB[index*16:index*16+15] to all 8 halfword positions)", "page_found": "Page 319", "programming_notes": "The vsplth instruction is commonly used when you need to replicate a specific halfword from a source vector into all elements of a destination vector, which is useful for operations requiring uniform operands. Ensure the specified bit position (b) is within the valid range to avoid undefined behavior. This instruction operates at user privilege level and does not generate exceptions under normal circumstances.", "example": "vsplth vd, vb, uim" }, { "mnemonic": "vspltisb", "architecture": "PowerISA", "full_name": "Vector Splat Immediate Signed Byte", "summary": "Splat an immediate signed byte value into all elements of a vector register.", "syntax": "vspltisb vD, SIM", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | SIM | 00000 | 780", "hex_opcode": "0x1000030C", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "SIM", "clean": "SIM" }, { "raw": "00000", "clean": "00000" }, { "raw": "780", "clean": "780" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "SIM", "desc": "Immediate" }, { "name": "VRT", "desc": "Target Vector Register" } ], "extension": "VMX (AltiVec)", "description": "Splats a 5-bit signed immediate value into all 16 byte elements of vD, sign-extended to 8 bits per byte. The immediate SIM is a signed 5-bit value (range -16 to 15). No status flags are affected. This is a VMX/AltiVec instruction.", "pseudocode": "value ← sign_extend(SIM, 8)\nvD ← replicate(value to all 16 byte positions)", "page_found": "Page 320 - 322", "special_registers": "MSR", "programming_notes": "This instruction is used to fill a vector register with the sign-extended value of an 8-bit immediate. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise a Vector Unavailable exception. The immediate value is sign-extended and replicated across all elements of the target vector register.", "example": "vspltisb vd, 4" }, { "mnemonic": "vspltish", "architecture": "PowerISA", "full_name": "Vector Splat Immediate Signed Halfword", "summary": "Fills vector with immediate 5-bit signed value.", "syntax": "vspltish vD, SIM", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | SIM | 00000 | 844", "hex_opcode": "0x1000034C", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "SIM", "clean": "SIM" }, { "raw": "00000", "clean": "00000" }, { "raw": "844", "clean": "844" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "SIM", "desc": "Immediate" } ], "extension": "VMX (AltiVec)", "description": "Splats a 5-bit signed immediate value into all 8 halfword elements of vD, sign-extended to 16 bits per halfword. The immediate SIM is a signed 5-bit value (range -16 to 15). No status flags are affected. This is a VMX/AltiVec instruction.", "pseudocode": "value ← sign_extend(SIM, 16)\nvD ← replicate(value to all 8 halfword positions)", "page_found": "Page 321", "special_registers": "MSR", "programming_notes": "The vspltish instruction is used to replicate a signed halfword value across all elements of a vector register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The immediate value is sign-extended to 16 bits and then replicated in each halfword element of the target vector register.", "example": "vspltish vd, 4" }, { "mnemonic": "vspltisw", "architecture": "PowerISA", "full_name": "Vector Splat Immediate Signed Word", "summary": "Splat a signed immediate value into all elements of a vector register.", "syntax": "vspltisw vD, SIM", "encoding": { "format": "VX-form", "binary_pattern": "000100 | vD | SIM | // | 01110 | 001100", "hex_opcode": "0x1000038C", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "SIM", "clean": "SIM" }, { "raw": "00000", "clean": "00000" }, { "raw": "908", "clean": "908" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "SIM", "desc": "Immediate" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "SI16", "desc": "Signed Immediate Value (16-bit)" } ], "extension": "VMX (AltiVec)", "page_found": "Page 1421 - 1422", "description": "Splats a 5-bit signed immediate value into all 4 word elements of vD, sign-extended to 32 bits per word. The immediate SIM is a signed 5-bit value (range -16 to 15). No status flags are affected. This is a VMX/AltiVec instruction.", "pseudocode": "value ← sign_extend(SIM, 32)\nvD ← replicate(value to all 4 word positions)", "special_registers": "MSR", "programming_notes": "The vspltisw instruction is commonly used to initialize a vector register with a repeated signed word value. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The immediate value is sign-extended from 16 bits to 32 bits and replicated across all four elements of the target vector register.", "example": "vspltisw vd, 4" }, { "mnemonic": "vslb", "architecture": "PowerISA", "full_name": "Vector Shift Left Byte", "summary": "Shifts each byte element of the source vector left by a specified number of bits.", "syntax": "vslb vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 260", "hex_opcode": "0x10000104", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "260", "clean": "260" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Data" }, { "name": "vB", "desc": "Shift" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Shift Control Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vslb, each byte element of VSR[VRA+32] is shifted left by the number of bits specified in the low-order 3 bits of the corresponding byte element of VSR[VRB+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 15\n src1 ← VSR[VRA+32].byte[i]\n src2 ← VSR[VRB+32].byte[i].bit[5:7]\n VSR[VRT+32].byte[i] ← src1 << src2", "page_found": "Page 437 - 438", "special_registers": "MSR", "programming_notes": "The vslb instruction shifts each byte of the source vector left by a specified number of bits, determined by the lower 3 bits of the corresponding byte in the second source vector. Ensure that the Vector Facility is enabled (MSR.VEC=1) to avoid a Vector_Unavailable exception. This operation is useful for bit manipulation tasks but requires careful handling of alignment and privilege levels.", "example": "vslb vd, va, vb" }, { "mnemonic": "vslh", "architecture": "PowerISA", "full_name": "Vector Shift Left Halfword", "summary": "Shifts each halfword left.", "syntax": "vslh vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 324", "hex_opcode": "0x10000144", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "324", "clean": "324" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Data" }, { "name": "vB", "desc": "Shift" } ], "extension": "VMX (AltiVec)", "description": "Shifts each of the 8 halfword elements in vA left by a variable number of bits specified by the low 4 bits of the corresponding halfword element in vB. Bits shifted out are lost; positions vacated are filled with zeros. No status flags are affected. This is a VMX/AltiVec instruction.", "pseudocode": "for i ← 0 to 7 do\n shift_amount ← vB[i*16:i*16+3]\n vD[i*16:i*16+15] ← vA[i*16:i*16+15] << shift_amount", "page_found": "Page 438", "special_registers": "MSR", "programming_notes": "The vslh instruction shifts each halfword element of the source vector left by a specified number of bits. Ensure that the shift amount is within the valid range to avoid unexpected results. This instruction operates at the user privilege level and does not generate exceptions under normal conditions.", "example": "vslh vd, va, vb" }, { "mnemonic": "vsrb", "architecture": "PowerISA", "full_name": "Vector Shift Right Byte", "summary": "Shifts each byte element of the source vector right by a specified number of bits.", "syntax": "vsrb vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "0 | VRT | VRA | VRB | 516", "hex_opcode": "0x10000204", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "516", "clean": "516" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Data" }, { "name": "vB", "desc": "Shift" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Shift Control Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vsrb, each byte element of VSR[VRA+32] is shifted right by the number of bits specified in the low-order 3 bits of the corresponding byte element in VSR[VRB+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 15\n src1 ← VSR[VRA+32].byte[i]\n src2 ← VSR[VRB+32].byte[i].bit[5:7]\n VSR[VRT+32].byte[i] ← CHOP8(EXTZ(src1) >> src2)\nend", "page_found": "Page 440 - 441", "special_registers": "MSR", "programming_notes": "The vsrb instruction shifts each byte of the source vector right by a specified number of bits, determined by the lower 3 bits of the corresponding byte in another vector. Ensure that the Vector Facility is enabled (MSR.VEC=1); otherwise, a Vector_Unavailable exception will be raised. This operation is useful for bit manipulation tasks but requires careful handling of alignment and privilege levels to avoid exceptions.", "example": "vsrb vd, va, vb" }, { "mnemonic": "vsrh", "architecture": "PowerISA", "full_name": "Vector Shift Right Halfword", "summary": "Shifts the contents of each element in a vector right by a specified number of bits.", "syntax": "vsrh vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "000100 | vD | vA | vB | 01001 | 000100", "hex_opcode": "0x10000244", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "580", "clean": "580" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Data" }, { "name": "vB", "desc": "Shift" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "page_found": "Page 1366 - 1367", "description": "Shifts each of the 8 halfword elements in vA right (logically, without sign extension) by a variable number of bits specified by the low 4 bits of the corresponding halfword element in vB. Bits shifted out are lost; positions vacated are filled with zeros. No status flags are affected. This is a VMX/AltiVec instruction.", "pseudocode": "for i ← 0 to 7 do\n shift_amount ← vB[i*16:i*16+3]\n vD[i*16:i*16+15] ← vA[i*16:i*16+15] >> shift_amount", "special_registers": "MSR", "programming_notes": "The vsrh instruction is used to perform element-wise right shifts on halfwords within a vector. Ensure that the shift amounts in the second source vector are within the range of 0-15 to avoid unexpected behavior. This instruction requires the VEC bit in the MSR register to be set; otherwise, it will raise an exception. Be cautious with alignment as unaligned access might lead to performance penalties or exceptions depending on the system configuration.", "example": "vsrh vd, va, vb" }, { "mnemonic": "vsrw", "architecture": "PowerISA", "full_name": "Vector Shift Right Word", "summary": "Shifts each word element of the source vector right by a specified number of bits.", "syntax": "vsrw vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 644", "hex_opcode": "0x10000284", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "644", "clean": "644" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Data" }, { "name": "vB", "desc": "Shift" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vsrw, each word element of VSR[VRA+32] is shifted right by the number of bits specified in the low-order 5 bits of the corresponding word element of VSR[VRB+32]. The result is placed into the corresponding word element of VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n src1 ← VSR[VRA+32].word[i]\n src2 ← VSR[VRB+32].word[i].bit[27:31]\n VSR[VRT+32].word[i] ← CHOP32(EXTZ(src1) >> src2)\nend", "page_found": "Page 441 - 442", "special_registers": "MSR", "programming_notes": "The vsrw instruction shifts each word element of the source vector right by a specified number of bits, determined by the corresponding word element in another vector. Ensure that the shift amount is within the range of 0 to 31 to avoid undefined behavior. This instruction requires the Vector Facility to be enabled; otherwise, it will raise an exception.", "example": "vsrw vd, va, vb" }, { "mnemonic": "vsrab", "architecture": "PowerISA", "full_name": "Vector Shift Right Algebraic Byte", "summary": "Shifts each byte of the source vector right by a specified number of bits, filling vacated bits with copies of the sign bit.", "syntax": "vsrab vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 772", "hex_opcode": "0x10000304", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "772", "clean": "772" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Data" }, { "name": "vB", "desc": "Shift" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Shift Amount Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vsrab, each byte element in VSR[VRA+32] is shifted right by the number of bits specified in the low-order 3 bits of the corresponding byte element in VSR[VRB+32]. The result is placed into the corresponding byte element in VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 15\n src1 ← VSR[VRA+32].byte[i]\n src2 ← VSR[VRB+32].byte[i].bit[5:7]\n VSR[VRT+32].byte[i] ← CHOP8(EXTS(src1) >> src2)\nend", "page_found": "Page 443 - 444", "special_registers": "MSR", "programming_notes": "The vsrab instruction performs a right algebraic shift on each byte of the source vector, using the low-order 3 bits of the corresponding byte in the second source vector as the shift amount. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates at the user privilege level and does not generate exceptions for valid shifts; however, invalid shifts (e.g., shifting more than 7 bits) will result in undefined behavior.", "example": "vsrab vd, va, vb" }, { "mnemonic": "vsrah", "architecture": "PowerISA", "full_name": "Vector Shift Right Algebraic Halfword", "summary": "Arithmetic right shift of halfwords.", "syntax": "vsrah vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 836", "hex_opcode": "0x10000344", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "836", "clean": "836" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Data" }, { "name": "vB", "desc": "Shift" } ], "extension": "VMX (AltiVec)", "description": "Shifts each of the 8 halfword elements in vA right arithmetically (with sign extension) by a variable number of bits specified by the low 4 bits of the corresponding halfword element in vB. The sign bit is replicated into vacated positions; bits shifted out are lost. No status flags are affected. This is a VMX/AltiVec instruction.", "pseudocode": "for i ← 0 to 7 do\n shift_amount ← vB[i*16:i*16+3]\n vD[i*16:i*16+15] ← arithmetic_shift_right(vA[i*16:i*16+15], shift_amount)", "page_found": "Page 444", "special_registers": "MSR", "programming_notes": "The vsrah instruction is used to perform right algebraic shifts on halfword elements of a vector. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The shift amount for each element is determined by the low-order 4 bits of the corresponding element in the second source vector. Be cautious with alignment as halfword operations require proper alignment to avoid undefined behavior.", "example": "vsrah vd, va, vb" }, { "mnemonic": "vsraw", "architecture": "PowerISA", "full_name": "Vector Shift Right Algebraic Word", "summary": "Shifts each word element of the source vector right by a specified number of bits, filling vacated bits with copies of the sign bit.", "syntax": "vsraw vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 900", "hex_opcode": "0x10000384", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "900", "clean": "900" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Data" }, { "name": "vB", "desc": "Shift" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Shift Count Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vsraw, each word element of VSR[VRA+32] is shifted right by the number of bits specified in the low-order 5 bits of the corresponding word element of VSR[VRB+32]. The result is placed into the corresponding word element of VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n src1 ← VSR[VRA+32].word[i]\n src2 ← VSR[VRB+32].word[i].bit[27:31]\n VSR[VRT+32].word[i] ← CHOP32(EXTS(src1) >> src2)\nend", "page_found": "Page 444 - 445", "special_registers": "MSR", "programming_notes": "The vsraw instruction performs a right algebraic shift on each word element of the source vector, using the low-order 5 bits of the corresponding element in the second source vector as the shift count. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. Be cautious with alignment; while vsraw does not require specific alignment, incorrect alignment can lead to performance penalties or exceptions if data is not properly aligned in memory.", "example": "vsraw vd, va, vb" }, { "mnemonic": "vmrgew", "architecture": "PowerISA", "full_name": "Vector Merge Even Word", "summary": "Merges even word elements from two vector registers into a third.", "syntax": "vmrgew vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 1932", "hex_opcode": "0x1000078C", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1932", "clean": "1932" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "The contents of word element 0 of VSR[VRA+32] are placed into word element 0 of VSR[VRT+32]. The contents of word element 0 of VSR[VRB+32] are placed into word element 1 of VSR[VRT+32]. The contents of word element 2 of VSR[VRA+32] are placed into word element 2 of VSR[VRT+32]. The contents of word element 2 of VSR[VRB+32] are placed into word element 3 of VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nelse\n VSR[VRT+32].word[0] ←VSR[VRA+32].word[0]\n VSR[VRT+32].word[1] ←VSR[VRB+32].word[0]\n VSR[VRT+32].word[2] ←VSR[VRA+32].word[2]\n VSR[VRT+32].word[3] ←VSR[VRB+32].word[2]", "programming_notes": "vmrgew is treated as a Vector instruction in terms of resource availability.", "page_found": "Page 317 - 318", "special_registers": "MSR", "example": "vmrgew vd, va, vb" }, { "mnemonic": "vmrgow", "architecture": "PowerISA", "full_name": "Vector Merge Odd Word", "summary": "Merges odd words from two vectors.", "syntax": "vmrgow vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 1676", "hex_opcode": "0x1000068C", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1676", "clean": "1676" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Merges the odd-indexed words (words 1 and 3) from vector registers vA and vB into vD. This instruction interleaves odd-positioned word elements: vD[0] ← vA[1], vD[1] ← vB[1], vD[2] ← vA[3], vD[3] ← vB[3]. No condition flags are affected.", "pseudocode": "vD[0:31] ← vA[32:63]\nvD[32:63] ← vB[32:63]\nvD[64:95] ← vA[96:127]\nvD[96:127] ← vB[96:127]", "page_found": "Page 318", "special_registers": "MSR", "programming_notes": "The vmrgow instruction is used to merge odd-numbered words from two source vectors into a destination vector. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set; otherwise, a Vector_Unavailable exception will be raised. This instruction operates on 128-bit vectors and requires proper alignment of the source and destination registers.", "example": "vmrgow vd, va, vb" }, { "mnemonic": "vmulesb", "architecture": "PowerISA", "full_name": "Vector Multiply Even Signed Byte", "summary": "Multiplies the even-indexed bytes of two vector registers and stores the results in a destination vector register.", "syntax": "vmulesb vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 776", "hex_opcode": "0x10000308", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "776", "clean": "776" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vmulesb, each pair of even-indexed bytes from VSR[VRA+32] and VSR[VRB+32] are multiplied, and the 16-bit products are stored in halfwords of VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 7\n src1 ←EXTS(VSR[VRA+32].byte[2×i])\n src2 ←EXTS(VSR[VRB+32].byte[2×i])\n VSR[VRT+32].hword[i] ←CHOP16(src1 × src2)\nend", "page_found": "Page 364 - 365", "special_registers": "MSR", "programming_notes": "The vmulesb instruction multiplies even-indexed bytes from two vector registers and stores the 16-bit products in another vector register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on 32-byte vectors, so ensure proper alignment of data for optimal performance. Be cautious with overflow conditions as the multiplication results are truncated to 16 bits.", "example": "vmulesb vd, va, vb" }, { "mnemonic": "vmuleub", "architecture": "PowerISA", "full_name": "Vector Multiply Even Unsigned Byte", "summary": "Multiplies even-indexed bytes of two vector registers and stores the results in a destination vector register.", "syntax": "vmuleub vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 520", "hex_opcode": "0x10000208", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "520", "clean": "520" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vmuleub, each pair of even-indexed bytes from VSR[VRA+32] and VSR[VRB+32] are multiplied, and the 16-bit products are stored in halfwords of VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 7\n src1 ←EXTZ(VSR[VRA+32].byte[2×i])\n src2 ←EXTZ(VSR[VRB+32].byte[2×i])\n VSR[VRT+32].hword[i] ←CHOP16(src1 × src2)\nend", "page_found": "Page 365 - 366", "special_registers": "MSR", "programming_notes": "This instruction multiplies even-indexed bytes from two vector registers and stores the 16-bit products in another vector register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. Be cautious of overflow, as the multiplication results are truncated to 16 bits.", "example": "vmuleub vd, va, vb" }, { "mnemonic": "vmulesh", "architecture": "PowerISA", "full_name": "Vector Multiply Even Signed Halfword", "summary": "Multiplies the even-numbered halfwords of two vector registers and places the results into a destination vector register.", "syntax": "vmulesh vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | VRT | VRA | VRB | 840", "hex_opcode": "0x10000348", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "840", "clean": "840" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vmulesh, the signed integer value in each even-numbered halfword element of VSR[VRA+32] is multiplied by the corresponding signed integer value in each even-numbered halfword element of VSR[VRB+32]. The 32-bit product is placed into each word element of VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n src1 ←EXTS(VSR[VRA+32].hword[2×i])\n src2 ←EXTS(VSR[VRB+32].hword[2×i])\n VSR[VRT+32].word[i] ←CHOP32(src1 × src2)\nend", "page_found": "Page 366 - 367", "special_registers": "MSR", "programming_notes": "This instruction is used for multiplying signed halfwords from two vector registers and storing the 32-bit results in another vector register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation processes even-numbered halfwords, so developers should ensure proper alignment of data within the vector registers to avoid unexpected results.", "example": "vmulesh vd, va, vb" }, { "mnemonic": "vmuleuh", "architecture": "PowerISA", "full_name": "Vector Multiply Even Unsigned Halfword", "summary": "Multiplies the even-numbered halfwords of two vector registers and places the results into a destination vector register.", "syntax": "vmuleuh vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 584", "hex_opcode": "0x10000248", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "584", "clean": "584" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vmuleuh, each pair of even-numbered halfwords from VSR[VRA+32] and VSR[VRB+32] are multiplied, and the 32-bit products are placed into corresponding word elements of VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n src1 ← EXTZ(VSR[VRA+32].hword[2×i])\n src2 ← EXTZ(VSR[VRB+32].hword[2×i])\n VSR[VRT+32].word[i] ← CHOP32(src1 × src2)\nend", "page_found": "Page 367 - 368", "special_registers": "MSR", "programming_notes": "This instruction multiplies even-numbered halfwords from two vector registers and stores the 32-bit products in another register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. Be cautious of overflow, as only the lower 32 bits of each product are stored. This operation requires the use of VSX (Vector Scalar Extensions) registers.", "example": "vmuleuh vd, va, vb" }, { "mnemonic": "vmulosb", "architecture": "PowerISA", "full_name": "Vector Multiply Odd Signed Byte", "summary": "Multiplies odd signed bytes to halfwords.", "syntax": "vmulosb vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 264", "hex_opcode": "0x10000108", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "264", "clean": "264" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Multiplies the odd-indexed signed bytes from vA and vB, producing signed halfword results in vD. Operates on bytes at indices 1, 3, 5, 7, 9, 11, 13, 15, generating four halfword products. No condition flags are affected.", "pseudocode": "vD[0:15] ← (vA[8:15] × vB[8:15]) as signed\nvD[16:31] ← (vA[24:31] × vB[24:31]) as signed\nvD[32:47] ← (vA[40:47] × vB[40:47]) as signed\nvD[48:63] ← (vA[56:63] × vB[56:63]) as signed\nvD[64:79] ← (vA[72:79] × vB[72:79]) as signed\nvD[80:95] ← (vA[88:95] × vB[88:95]) as signed\nvD[96:111] ← (vA[104:111] × vB[104:111]) as signed\nvD[112:127] ← (vA[120:127] × vB[120:127]) as signed", "page_found": "Page 365", "special_registers": "MSR", "programming_notes": "This instruction is useful for performing element-wise multiplication of odd-numbered bytes from two vectors, storing the results as signed halfwords. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. The operation respects byte ordering, so developers must ensure proper alignment and data format to avoid unexpected results.", "example": "vmulosb vd, va, vb" }, { "mnemonic": "vmuloub", "architecture": "PowerISA", "full_name": "Vector Multiply Odd Unsigned Byte", "summary": "Multiplies odd unsigned bytes to halfwords.", "syntax": "vmuloub vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "00000 | 001000 | VRT | VRA | VRB", "hex_opcode": "0x10000008", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "8", "clean": "8" } ], "length": "32", "bit_positions": "0:5 | 6:15 | 16:20 | 21:25 | 26:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register A" }, { "name": "VRB", "desc": "Source Vector Register B" } ], "extension": "VMX (AltiVec)", "page_found": "Page 1328 - 1329", "description": "Multiplies the odd-indexed unsigned bytes from vA and vB, producing unsigned halfword results in vD. Operates on bytes at indices 1, 3, 5, 7, 9, 11, 13, 15, generating eight halfword products without sign extension. No condition flags are affected.", "pseudocode": "vD[0:15] ← (vA[8:15] × vB[8:15]) as unsigned\nvD[16:31] ← (vA[24:31] × vB[24:31]) as unsigned\nvD[32:47] ← (vA[40:47] × vB[40:47]) as unsigned\nvD[48:63] ← (vA[56:63] × vB[56:63]) as unsigned\nvD[64:79] ← (vA[72:79] × vB[72:79]) as unsigned\nvD[80:95] ← (vA[88:95] × vB[88:95]) as unsigned\nvD[96:111] ← (vA[104:111] × vB[104:111]) as unsigned\nvD[112:127] ← (vA[120:127] × vB[120:127]) as unsigned", "programming_notes": "This instruction is useful for performing element-wise multiplication of odd-numbered bytes from two vectors. Ensure that the input vectors are properly aligned to avoid unexpected results. The operation does not require any special privileges, but it's important to handle potential overflow by zero-extending the 8-bit result to 16 bits.", "example": "vmuloub vd, va, vb" }, { "mnemonic": "vmulosh", "architecture": "PowerISA", "full_name": "Vector Multiply Odd Signed Halfword", "summary": "Multiplies odd signed halfwords to words.", "syntax": "vmulosh vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 328", "hex_opcode": "0x10000148", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "328", "clean": "328" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Multiplies the odd-indexed signed halfwords from vA and vB, producing signed word results in vD. Operates on halfwords at indices 1 and 3, generating two word products. No condition flags are affected.", "pseudocode": "vD[0:31] ← (vA[16:31] × vB[16:31]) as signed\nvD[32:63] ← (vA[48:63] × vB[48:63]) as signed\nvD[64:95] ← (vA[80:95] × vB[80:95]) as signed\nvD[96:127] ← (vA[112:127] × vB[112:127]) as signed", "page_found": "Page 367", "special_registers": "MSR", "programming_notes": "This instruction is useful for performing element-wise multiplication of odd-numbered signed halfwords from two vectors. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The result is stored as 32-bit words in the destination vector, so ensure proper alignment and size of the vectors to avoid unexpected behavior.", "example": "vmulosh vd, va, vb" }, { "mnemonic": "vmulouh", "architecture": "PowerISA", "full_name": "Vector Multiply Odd Unsigned Halfword", "summary": "Multiplies odd unsigned halfwords to words.", "syntax": "vmulouh vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 72", "hex_opcode": "0x10000048", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "72", "clean": "72" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Multiplies the odd-indexed unsigned halfwords from vA and vB, producing unsigned word results in vD. Operates on halfwords at indices 1 and 3, generating four word products without sign extension. No condition flags are affected.", "pseudocode": "vD[0:31] ← (vA[16:31] × vB[16:31]) as unsigned\nvD[32:63] ← (vA[48:63] × vB[48:63]) as unsigned\nvD[64:95] ← (vA[80:95] × vB[80:95]) as unsigned\nvD[96:127] ← (vA[112:127] × vB[112:127]) as unsigned", "page_found": "Page 368", "special_registers": "MSR", "programming_notes": "This instruction is useful for performing element-wise multiplication of unsigned halfwords from two vectors. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation targets odd-numbered halfwords, so developers should align their data accordingly to achieve the desired results.", "example": "vmulouh vd, va, vb" }, { "mnemonic": "vabsdub", "architecture": "PowerISA", "full_name": "Vector Absolute Difference Unsigned Byte", "summary": "Returns the absolute value of the difference of integer values in byte elements.", "syntax": "vabsdub vD, vA, vB", "encoding": { "format": "VA-form", "binary_pattern": "4 | VRT | VRA | VRB | 1027", "hex_opcode": "0x10000403", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1027", "clean": "1027" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vabsdub, the absolute value of the difference between corresponding byte elements of VSR[VRA+32] and VSR[VRB+32] is placed into corresponding byte elements of VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 15\n src1 ← EXTZ(VSR[VRA+32].byte[i])\n src2 ← EXTZ(VSR[VRB+32].byte[i])\n if src1 > src2 then\n VSR[VRT+32].byte[i] ← CHOP8(src1 + ¬src2 + 1)\n else\n VSR[VRT+32].byte[i] ← CHOP8(src2 + ¬src1 + 1)\nend", "page_found": "Page 403 - 404", "special_registers": "MSR", "programming_notes": "This instruction computes the absolute difference between corresponding bytes of two vector registers and stores the result in another register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. The operation does not require any specific alignment, but both input vectors must be properly loaded into the specified registers. This instruction operates at a high performance due to its parallel processing capabilities on vector elements.", "example": "vabsdub vd, va, vb" }, { "mnemonic": "vabsduh", "architecture": "PowerISA", "full_name": "Vector Absolute Difference Unsigned Halfword", "summary": "Computes |A - B| for halfwords.", "syntax": "vabsduh vD, vA, vB", "encoding": { "format": "VA-form", "binary_pattern": "4 | vD | vA | vB | 1091", "hex_opcode": "0x10000443", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1091", "clean": "1091" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Computes the absolute value of the difference between corresponding unsigned halfwords in vA and vB, storing results in vD. Each result is calculated as |vA[i] - vB[i]| for each of four halfword elements. No condition flags are affected.", "pseudocode": "vD[0:15] ← |vA[0:15] - vB[0:15]| as unsigned\nvD[16:31] ← |vA[16:31] - vB[16:31]| as unsigned\nvD[32:47] ← |vA[32:47] - vB[32:47]| as unsigned\nvD[48:63] ← |vA[48:63] - vB[48:63]| as unsigned\nvD[64:79] ← |vA[64:79] - vB[64:79]| as unsigned\nvD[80:95] ← |vA[80:95] - vB[80:95]| as unsigned\nvD[96:111] ← |vA[96:111] - vB[96:111]| as unsigned\nvD[112:127] ← |vA[112:127] - vB[112:127]| as unsigned", "page_found": "Page 404", "special_registers": "MSR", "programming_notes": "The vabsduh instruction is commonly used for vectorized image processing tasks where pixel intensity differences need to be calculated. Ensure that the input vectors are properly aligned to halfword boundaries to avoid misaligned access exceptions. This instruction operates at user privilege level and does not generate any exceptions under normal operation, but it will raise a Vector_Unavailable exception if the VEC bit in the MSR is not set.", "example": "vabsduh vd, va, vb" }, { "mnemonic": "vabsduw", "architecture": "PowerISA", "full_name": "Vector Absolute Difference Unsigned Word", "summary": "Calculates the absolute difference of unsigned words from two vector registers and stores the result in another vector register.", "syntax": "vabsduw vD, vA, vB", "encoding": { "format": "VA-form", "binary_pattern": "4 | vD | vA | vB | 1155", "hex_opcode": "0x10000483", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1155", "clean": "1155" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vabsduw, the absolute difference of each word element from VSR[VRA+32] and VSR[VRB+32] is calculated and stored in VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then Vector_Unavailable()\ndo i = 0 to 3\n src1 ←EXTZ(VSR[VRA+32].word[i])\n src2 ←EXTZ(VSR[VRB+32].word[i])\n\n if src1 > src2 then\n VSR[VRT+32].word[i] ←CHOP32(src1 + ¬src2 + 1)\n else\n VSR[VRT+32].word[i] ←CHOP32(src2 + ¬src1 + 1)\nend", "page_found": "Page 404 - 405", "special_registers": "MSR", "programming_notes": "This instruction calculates the absolute difference of each word element between two vector registers and stores the result in another register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. The operation handles unsigned integers, so be cautious with negative values if they are interpreted as signed. This instruction does not require any specific alignment for the data it operates on.", "example": "vabsduw vd, va, vb" }, { "mnemonic": "xsmaxcqp", "architecture": "PowerISA", "full_name": "VSX Scalar Maximum Type-C Quad-Precision", "summary": "Compares two quad-precision floating-point values and selects the maximum.", "syntax": "xsmaxcqp vD, vA, vB", "encoding": { "format": "X-form", "binary_pattern": "63 | FRT | FRA | FRB | 674 | Rc", "hex_opcode": "0xFC000548", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "676", "clean": "676" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector-Scalar Register" }, { "name": "VRA", "desc": "Source Vector-Scalar Register" }, { "name": "VRB", "desc": "Source Vector-Scalar Register" }, { "name": "XT", "desc": "Target Vector Register" } ], "extension": "VSX", "description": "Compares two quad-precision floating-point values in VSRs and returns the maximum, using Type-C comparison rules (NaN handling as per VSX specification). Results are written to the VSR specified by XT. No exception or condition register fields are altered unless Rc=1 for VSX comparisons.", "pseudocode": "fD ← max(fA, fB) using Type-C comparison\nif fA is NaN or fB is NaN then\n fD ← QNaN\nend if", "special_registers": "FPSCR (FX, VXSNAN)", "programming_notes": "xsmaxcqp can be used to implement the C/C++ conditional operation (x>y)?x:y for quad-precision arguments. VSR[VRT+32] ←result", "page_found": "Page 792 - 793", "example": "xsmaxcqp vd, va, vb" }, { "mnemonic": "xsmincqp", "architecture": "PowerISA", "full_name": "VSX Scalar Minimum Type-C Quad-Precision", "summary": "Compares two quad-precision floating-point values and selects the minimum value.", "syntax": "xsmincqp vD, vA, vB", "encoding": { "format": "X-form", "binary_pattern": "63 | FRT | FRA | FRB | 710 | Rc", "hex_opcode": "0xFC0005C8", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "708", "clean": "708" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VSX", "description": "Compares two quad-precision floating-point values in VSRs and returns the minimum, using Type-C comparison rules (NaN handling as per VSX specification). Results are written to the VSR specified by XT. No exception or condition register fields are altered unless Rc=1 for VSX comparisons.", "pseudocode": "fD ← min(fA, fB) using Type-C comparison\nif fA is NaN or fB is NaN then\n fD ← QNaN\nend if", "special_registers": "FPSCR.FX, FPSCR.VXSNAN", "programming_notes": "xsmincqp can be used to implement the C/C++ conditional operator (x src2.exponent)\neq_flag ← (src1.exponent = src2.exponent)\nuo_flag ← src1.class.NaN | src2.class.NaN\n\nCR.bit[4×BF+32] ← FPSCR.FL ← !uo_flag & lt_flag\nCR.bit[4×BF+33] ← FPSCR.FG ← !uo_flag & gt_flag\nCR.bit[4×BF+34] ← FPSCR.FE ← !uo_flag & eq_flag\nCR.bit[4×BF+35] ← FPSCR.FU ← uo_flag", "special_registers": "CR, FPSCR", "page_found": "Page 898 - 899", "programming_notes": "This instruction compares the exponents of two quad-precision floating-point numbers. Ensure that VSX is enabled in the MSR register to avoid exceptions. The result is stored in both the CR and FPSCR registers, with flags indicating less than, greater than, equal, or unordered comparisons. Handle NaN values appropriately as they set the unordered flag.", "example": "xscmpexpqp cr0, va, vb" }, { "mnemonic": "tcheck", "architecture": "PowerISA", "full_name": "Transaction Check", "summary": "Checks transaction status and updates CR.", "syntax": "tcheck BF", "encoding": { "format": "X-form", "binary_pattern": "31 | BF | / | / | 716 | /", "hex_opcode": "0x7C00059C", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "BF", "clean": "BF" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "716", "clean": "716" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "BF", "desc": "CR Field" } ], "extension": "Transactional Memory", "description": "Transaction Check. Tests the state of the current transaction and sets CR field BF based on whether a transaction is active, suspended, or whether a failure has been recorded. No effect outside a transaction.", "pseudocode": "if Transactional_or_Suspended() then\n CR[4*BF:4*BF+3] ← transaction_state_bits()\nelse\n CR[4*BF:4*BF+3] ← 0b0000", "special_registers": "CR", "programming_notes": "The tcheck instruction is used to determine the state of the current transaction, setting the condition register field BF accordingly. It should be used within a transactional context; outside transactions, it will clear the specified CR field. Ensure proper alignment and ordering relative to other transactional instructions for accurate state checks.", "example": "tcheck cr0" }, { "mnemonic": "tsuspend", "architecture": "PowerISA", "full_name": "Transaction Suspend", "summary": "Suspends the current transaction.", "syntax": "tsuspend.", "encoding": { "format": "X-form", "binary_pattern": "31 | 0 | 0 | 0 | 750 | 1", "hex_opcode": "0x7C0005DE", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "750", "clean": "750" }, { "raw": "1", "clean": "1" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [], "extension": "Transactional Memory", "description": "Suspends the current transaction without aborting it, allowing the processor to handle interrupts and other exceptions while preserving transactional state for later resumption via tresume. This instruction requires Transactional Memory support and always sets CR0 to indicate successful suspension. The instruction has a dot form that updates CR0.", "pseudocode": "Transaction ← Suspended\nCR0 ← 0b0010", "example": "tsuspend." }, { "mnemonic": "tresume", "architecture": "PowerISA", "full_name": "Transaction Resume", "summary": "Resumes a suspended transaction.", "syntax": "tresume.", "encoding": { "format": "X-form", "binary_pattern": "31 | 1 | 0 | 0 | 750 | 1", "hex_opcode": "0x7C2005DE", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "1", "clean": "1" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "750", "clean": "750" }, { "raw": "1", "clean": "1" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [], "extension": "Transactional Memory", "description": "Resumes a transaction that was previously suspended via tsuspend, restoring the transactional state and continuing execution. This instruction requires Transactional Memory support and always sets CR0 to indicate successful resumption. The instruction has a dot form that updates CR0.", "pseudocode": "Transaction ← Active\nCR0 ← 0b0010", "example": "tresume." }, { "mnemonic": "dcbtls", "architecture": "PowerISA", "full_name": "Data Cache Block Touch and Lock Set", "summary": "Locks a cache line in the L1 cache.", "syntax": "dcbtls CT, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | CT | RA | RB | 166 | /", "hex_opcode": "0x7C00014C", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "CT", "clean": "CT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "166", "clean": "166" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "CT", "desc": "Cache Target" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Privileged", "description": "Locks a data cache line in the L1 data cache at the address computed from RA+RB. The cache target (CT) field specifies the cache level and operation type. This is a privileged instruction that provides cache locking hints to the processor and does not modify any general-purpose registers or condition flags.", "pseudocode": "EA ← (RA|0) + RB\nLock cache line at EA in L1 data cache based on CT", "example": "dcbtls 0, r4, r5" }, { "mnemonic": "slbsync", "architecture": "PowerISA", "full_name": "SLB Synchronize", "summary": "Provides an ordering function for the effects of all slbieg and slbiag instructions executed by the thread executing the slbsync instruction.", "syntax": "slbsync", "encoding": { "format": "X-form", "binary_pattern": "31 | / | / | / | 870 | /", "hex_opcode": "0x7C0002A4", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "438", "clean": "438" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [], "extension": "Privileged", "description": "Provides a synchronization point ensuring that all slbieg and slbiag instructions executed by the current thread prior to this instruction have completed their effects before any subsequent memory operations are visible. This is a privileged instruction with no operands that enforces ordering of segment lookaside buffer (SLB) invalidation operations.", "programming_notes": "slbsync should not be used to synchronize the completion of slbie.", "page_found": "Page 1206 - 1207", "pseudocode": "Synchronize all prior slbieg and slbiag effects", "example": "slbsync" }, { "mnemonic": "lbarx", "architecture": "PowerISA", "full_name": "Load Byte And Reserve Indexed", "summary": "Loads a byte from memory and reserves the location for exclusive access.", "syntax": "lbarx RT,RA,RB,EH", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | RA | RB | 52 | 0", "hex_opcode": "0x7C000068", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "52", "clean": "52" }, { "raw": "0", "clean": "0" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" }, { "name": "EH", "desc": "Hint for subsequent store operation" } ], "extension": "Base", "description": "Loads a single byte from memory at the address computed from RA+RB into RT, zero-extending to 64 bits, and reserves the location for exclusive access for a subsequent stbcx. instruction. The optional EH field provides a hint for the subsequent store. No condition register fields are affected by this load.", "pseudocode": "EA ← (RA|0) + RB\nRT ← (56)0 || MEM[EA, 1]\nRESERVED ← EA", "programming_notes": "lbarx serves as both a basic and an extended mnemonic. The Assembler will recognize a lbarx mnemonic with four operands as the basic form, and a lbarx mnemonic with three operands as the extended form. In the extended form the EH operand is omitted and assumed to be 0.", "page_found": "Page 1051 - 1052", "special_registers": "RESERVE, RESERVE_LENGTH, RESERVE_ADDR", "example": "lbarx r3, r4, r5, 0" }, { "mnemonic": "lharx", "architecture": "PowerISA", "full_name": "Load Halfword And Reserve Indexed", "summary": "Atomic Load Halfword.", "syntax": "lharx RT, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | RA | RB | 116 | 0", "hex_opcode": "0x7C0000E8", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "116", "clean": "116" }, { "raw": "0", "clean": "0" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Base", "description": "Load the halfword at the effective address into the low 16 bits of RT, sign-extending to 32 bits in 32-bit mode or 64 bits in 64-bit mode, and reserve the addressed halfword for atomic update. Sets the reservation granule; any store to the reserved address by any processor will clear the reservation. This instruction requires that RA or 0 is added to RB to form the effective address.", "page_found": "Page 1052", "programming_notes": "Places a reservation on the cache line containing the effective address. The subsequent store-conditional (stwcx./stdcx. etc.) will fail if the reservation has been lost due to an intervening store from any processor or an exception. Always check the EQ bit in CR0 after the store-conditional.", "pseudocode": "EA ← (RA | 0) + RB\nRT ← EXTS(MEM(EA, 2), 16)\nReserveWord(EA)", "example": "lharx r3, r4, r5" }, { "mnemonic": "lqarx", "architecture": "PowerISA", "full_name": "Load Quadword And Reserve Indexed", "summary": "Loads a quadword from memory and reserves the location for conditional store.", "syntax": "lqarx RTp, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RTp | RA | RB | 276 | 0", "hex_opcode": "0x7C000228", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RTp", "clean": "RTp" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "276", "clean": "276" }, { "raw": "0", "clean": "0" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RTp", "desc": "Target Pair" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" }, { "name": "EH", "desc": "Hint operand" } ], "extension": "Base", "description": "For lqarx, the quadword in storage addressed by EA is loaded into an even-odd pair of GPRs. In Big-Endian mode, the even-numbered GPR is loaded with the doubleword from storage addressed by EA and the odd-numbered GPR is loaded with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed by EA.", "pseudocode": "if RA = 0 then\n b ← 0\nelse\n b ← (RA)\nEA ← b + (RB)\nRESERVE ← 1\nRESERVE_LENGTH ← 16\nRESERVE_ADDR ← real_addr(EA)\nRTp ← MEM(EA, 16)", "programming_notes": "lqarx serves as both a basic and an extended mnemonic. The Assembler will recognize a lqarx mnemonic with four operands as the basic form, and a lqarx mnemonic with three operands as the extended form. In the extended form the EH operand is omitted and assumed to be 0.", "extended_mnemonics": [ { "mnemonic": "lqarx", "syntax": "lqarx RTp,RA,RB", "description": "Equivalent to lqarx RTp,RA,RB,0" } ], "page_found": "Page 1058 - 1059", "special_registers": "RESERVE, RESERVE_LENGTH, RESERVE_ADDR", "example": "lqarx r4, r4, r5" }, { "mnemonic": "stbcx.", "architecture": "PowerISA", "full_name": "Store Byte Conditional Indexed", "summary": "Stores a byte from a register to memory if the reservation is valid and matches the address.", "syntax": "stbcx. RS, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 694 | 1", "hex_opcode": "0x7C00056D", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "694", "clean": "694" }, { "raw": "1", "clean": "1" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RS", "desc": "Source" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Base", "description": "The stbcx. instruction stores a byte from the specified source register (RS) into memory at an effective address calculated by adding the contents of two registers (RA and RB). The operation is conditional on whether a reservation exists and matches the target address.", "pseudocode": "if RA = 0 then\n b ← 0\nelse\n b ← (RA)\nEA ← b + (RB)\nif RESERVE then\n if RESERVE_LENGTH = 1 &\n RESERVE_ADDR = real_addr(EA) then\n MEM(EA, 1) ← (RS)56:63\n undefined_case ← 0\n store_performed ← 1\n else\n z ← smallest real page size supported by implementation\n if RESERVE_ADDR ÷ z = real_addr(EA) ÷ z then\n undefined_case ← 1\n else\n undefined_case ← 0\n store_performed ← 0\nelse\n undefined_case ← 0\n store_performed ← 0\nif undefined_case then\n u1 ← undefined 1-bit value\n if u1 then\n MEM(EA, 1) ← (RS)56:63\n u2 ← undefined 1-bit value\n CR0 ← 0b00 || u2 || XERSO\nelse\n CR0 ← 0b00 || store_performed || XERSO\nRESERVE ← 0", "special_registers": "CR0, XER", "page_found": "Page 1053 - 1054", "programming_notes": "Succeeds only if a valid reservation exists on the target address. Sets CR0[EQ] to 1 on success, 0 on failure. Must always be used in a retry loop that re-executes the load-reserve instruction on failure.", "example": "stbcx. r3, r4, r5" }, { "mnemonic": "sthcx.", "architecture": "PowerISA", "full_name": "Store Halfword Conditional Indexed", "summary": "Stores a halfword from a register to memory conditionally based on a reservation.", "syntax": "sthcx. RS, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "011111 | RS | RA | RB | 10110 | 101101", "hex_opcode": "0x7C0005AD", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "726", "clean": "726" }, { "raw": "1", "clean": "1" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RS", "desc": "Source" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Base", "description": "The sthcx. instruction stores the upper half of the contents of register RS into memory at the effective address (EA) if a reservation exists and meets certain conditions. The EA is calculated as the sum of RA and RB, with RA being zero-extended to 64 bits. If the reservation length is not 2 bytes or the real storage location does not match the reservation, the store may be undefined or no store may occur.", "pseudocode": "if RA = 0 then\n b ← 0\nelse\n b ← (RA)\nEA ← b + (RB)\nif RESERVE then\n if RESERVE_LENGTH = 2 &\n RESERVE_ADDR = real_addr(EA) then\n MEM(EA, 2) ← (RS)48:63\n undefined_case ← 0\n store_performed ← 1\n else\n z ← smallest real page size supported by implementation\n if RESERVE_ADDR ÷ z = real_addr(EA) ÷ z then\n undefined_case ← 1\n else\n undefined_case ← 0\n store_performed ← 0\nelse\n undefined_case ← 0\n store_performed ← 0\nif undefined_case then\n u1 ← undefined 1-bit value\n if u1 then\n MEM(EA, 2) ← (RS)48:63\n u2 ← undefined 1-bit value\n CR0 ← 0b00 || u2 || XERSO\nelse\n CR0 ← 0b00 || store_performed || XERSO\nRESERVE ← 0", "special_registers": "CR0, XER", "page_found": "Page 1054 - 1055", "programming_notes": "Succeeds only if a valid reservation exists on the target address. Sets CR0[EQ] to 1 on success, 0 on failure. Must always be used in a retry loop that re-executes the load-reserve instruction on failure.", "example": "sthcx. r3, r4, r5" }, { "mnemonic": "slw", "architecture": "PowerISA", "full_name": "Shift Left Word", "summary": "Shifts a 32-bit register left by the amount specified in RB.", "syntax": "slw RT,RA,RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 24 | Rc", "hex_opcode": "0x7C000030", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "24", "clean": "24" }, { "raw": "Rc", "clean": "Rc" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RA", "desc": "Target Register" }, { "name": "RS", "desc": "Source Register" }, { "name": "RB", "desc": "Shift Amount Register" }, { "name": "RT", "desc": "Target General Purpose Register" } ], "pseudocode": "n ← (RB)59:63\nr ← ROTL32((RS)32:63, n)\nif (RB)58 = 0 then\n m ← MASK(32, 63-n)\nelse\n m ← 640\nRA ← r & m", "example": "slw r3, r4, r5", "example_note": "r3 = r4 << r5 (32-bit).", "extension": "Base", "description": "The contents of the low-order 32 bits of register RS are shifted left the number of bits specified by (RB)58:63. Bits shifted out of position 32 are lost. Zeros are supplied to the vacated positions on the right. The 32-bit result is placed into RA32:63. RA0:31 are set to zero. Shift amounts from 32 to 63 give a zero result.", "special_registers": "CR0", "page_found": "Page 148 - 150", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER." }, { "mnemonic": "srw", "architecture": "PowerISA", "full_name": "Shift Right Word", "summary": "Performs a logical right shift (zeros shifted in) on a 32-bit word.", "syntax": "srw RA, RS, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 536 | Rc", "hex_opcode": "0x7C000430", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "536", "clean": "536" }, { "raw": "Rc", "clean": "Rc" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target Register" }, { "name": "RS", "desc": "Source Register" }, { "name": "RB", "desc": "Shift Amount Register" } ], "pseudocode": "n ← RB[27:31]\nif n < 32 then\n RA[0:63] ← EXTZ(RS[32:63] >> n, 32)\nelse\n RA[0:63] ← 0\nif Rc = 1 then\n CR0 ← (RA = 0) || LT || GT || SO", "example": "srw r3, r4, r5", "example_note": "r3 = r4 >> r5 (Unsigned 32-bit).", "extension": "Base", "description": "Logically shift the 32-bit word in RS right by the number of bits specified in RB[27:31] (only the low 5 bits are used), filling vacated positions with zeros. The result is placed in RA. If Rc=1, CR0 is updated based on the result.", "page_found": "Page 149", "special_registers": "CR0", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER." }, { "mnemonic": "sraw", "architecture": "PowerISA", "full_name": "Shift Right Algebraic Word", "summary": "Performs an arithmetic right shift (sign bit replicated) on a 32-bit word. Updates Carry (CA) if bits are shifted out.", "syntax": "sraw RA, RS, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 792 | Rc", "hex_opcode": "0x7C000630", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "792", "clean": "792" }, { "raw": "Rc", "clean": "Rc" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target Register" }, { "name": "RS", "desc": "Source Register" }, { "name": "RB", "desc": "Shift Amount Register" } ], "pseudocode": "n ← RB[27:31]\nif n = 0 then\n RA ← RS\n CA ← 0\nelse if n < 32 then\n shifted ← RS >> n\n if RS[0] = 1 ∧ (RS & ((1 << n) - 1)) ≠ 0 then\n CA ← 1\n else\n CA ← 0\n RA ← shifted\nelse\n if RS[0] = 1 then\n RA ← -1\n CA ← 1\n else\n RA ← 0\n CA ← 0\nif Rc = 1 then\n CR0 ← (RA = 0) || LT || GT || SO", "example": "sraw r3, r4, r5", "example_note": "r3 = r4 >> r5 (Signed 32-bit).", "extension": "Base", "description": "Arithmetically shift the 32-bit word in RS right by the number of bits specified in RB[27:31], replicating the sign bit into vacated positions. The result is placed in RA. The CA bit in XER is set if any 1-bits are shifted out from a negative value, otherwise cleared. If Rc=1, CR0 is updated based on the result.", "page_found": "Page 149", "special_registers": "CR0", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER." }, { "mnemonic": "srawi", "architecture": "PowerISA", "full_name": "Shift Right Algebraic Word Immediate", "summary": "Shifts the contents of a register right by an immediate value and replicates the sign bit.", "syntax": "srawi RA, RS, SH", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | SH | 824 | Rc", "hex_opcode": "0x7C000670", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "SH", "clean": "SH" }, { "raw": "824", "clean": "824" }, { "raw": "Rc", "clean": "Rc" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RA", "desc": "Target Register" }, { "name": "RS", "desc": "Source Register" }, { "name": "SH", "desc": "Shift Amount (0-31)" }, { "name": "RT", "desc": "Target General Purpose Register" } ], "pseudocode": "if 'srawi' then\n n ← SH\n r ← ROTL32((RS)32:63, 64-n)\n m ← MASK(n+32, 63)\n s ← (RS)32\n RA ← r&m | (64s) & ¬m\n carry ← s & ((r & ¬m)32:63 ≠ 0 )\n CA ← carry\n CA32 ← carry", "example": "srawi r3, r4, 5", "example_note": "r3 = r4 >> 5 (Signed).", "extension": "Base", "description": "The low-order 32 bits of register RS are shifted right SH bits. Bits shifted out of position 63 are lost. Bit 32 of RS is replicated to fill the vacated positions on the left. The 32-bit result is placed into RA32:63. Bit 32 of RS is replicated to fill RA0:31. CA and CA32 are set to 1 if the low-order 32 bits of (RS) contain a negative number and any 1-bits are shifted out of position 63; otherwise CA and CA32 are set to 0. A shift amount of zero causes RA to receive EXTS((RS)32:63), and CA and CA32 to be set to 0.", "special_registers": "CR0, XER", "page_found": "Page 149 - 150", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER." }, { "mnemonic": "stb", "architecture": "PowerISA", "full_name": "Store Byte", "summary": "Stores the low 8 bits of a register to memory.", "syntax": "stb RS, D(RA)", "encoding": { "format": "D-form", "binary_pattern": "10 | DS | RS | RA | SIMM[15:0]", "hex_opcode": "0x98000000", "visual_parts": [ { "raw": "38", "clean": "38" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "D", "clean": "D" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "RS", "desc": "Source Register" }, { "name": "D", "desc": "Displacement" }, { "name": "RA", "desc": "Base Register" }, { "name": "EA", "desc": "Effective Address" } ], "pseudocode": "EA ← EXTS(D, 16) + (RA | 0)\nMEM(EA, 1) ← RS[56:63]", "example": "stb r3, 0(r4)", "example_note": "Store byte from r3 to address r4.", "extension": "Base", "description": "Store the low 8 bits of RS to the byte in memory at the effective address formed by adding the displacement D (sign-extended) to RA, or to the displacement alone if RA is 0. This is a Base category instruction with no status field updates.", "page_found": "Page 92 - 94", "programming_notes": "The stb instruction is commonly used to store a single byte from a register into memory. Ensure that the destination address is properly aligned for optimal performance and avoid accessing invalid or protected memory regions to prevent exceptions." }, { "mnemonic": "sth", "architecture": "PowerISA", "full_name": "Store Halfword", "summary": "Stores the high half of a doubleword from a register to memory.", "syntax": "sth RS, D(RA)", "encoding": { "format": "D-form", "binary_pattern": "44 | RS | RA | D", "hex_opcode": "0xB0000000", "visual_parts": [ { "raw": "44", "clean": "44" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "D", "clean": "D" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "operands": [ { "name": "RS", "desc": "Source Register" }, { "name": "D", "desc": "Displacement" }, { "name": "RA", "desc": "Base Register" } ], "pseudocode": "EA ← EXTS(D, 16) + (RA | 0)\nMEM(EA, 2) ← RS[48:63]", "example": "sth r3, 0(r4)", "example_note": "Store 16-bit halfword.", "extension": "Base", "description": "Store the low 16 bits of RS to the halfword in memory at the effective address formed by adding the displacement D (sign-extended) to RA, or to the displacement alone if RA is 0. This is a Base category instruction with no status field updates.", "page_found": "Page 93 - 94", "programming_notes": "The sth instruction stores the high half of a register value into memory. Ensure that the destination address is properly aligned to avoid alignment faults. This instruction operates at user privilege level and will raise an exception if the EA is out of bounds or if there are insufficient permissions." }, { "mnemonic": "stw", "architecture": "PowerISA", "full_name": "Store Word", "summary": "Stores the low 32 bits of a register to memory.", "syntax": "stw RS, D(RA)", "encoding": { "format": "D-form", "binary_pattern": "36 | RS | RA | D", "hex_opcode": "0x90000000", "visual_parts": [ { "raw": "36", "clean": "36" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "D", "clean": "D" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "operands": [ { "name": "RS", "desc": "Source Register" }, { "name": "D", "desc": "Displacement" }, { "name": "RA", "desc": "Base Register" } ], "pseudocode": "EA ← EXTS(D, 16) + (RA | 0)\nMEM(EA, 4) ← RS[32:63]", "example": "stw r3, 0(r4)", "example_note": "Store 32-bit word.", "extension": "Base", "description": "Store the low 32 bits of RS to the word in memory at the effective address formed by adding the displacement D (sign-extended) to RA, or to the displacement alone if RA is 0. This is a Base category instruction with no status field updates.", "page_found": "Page 94 - 96", "programming_notes": "The stw instruction stores the lower 32 bits of a register into memory. Ensure that the destination address is properly aligned to avoid alignment faults. This instruction operates at user privilege level and will raise an exception if the EA is out of bounds or access permissions are violated." }, { "mnemonic": "std", "architecture": "PowerISA", "full_name": "Store Doubleword", "summary": "Stores a 64-bit doubleword to memory.", "syntax": "std RS, DS(RA)", "encoding": { "format": "DS-form", "binary_pattern": "62 | RS | RA | DS | 00", "hex_opcode": "0xF8000000", "visual_parts": [ { "raw": "62", "clean": "62" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "DS", "clean": "DS" }, { "raw": "00", "clean": "00" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:29 | 30:31", "length": "32" }, "operands": [ { "name": "RS", "desc": "Source Register" }, { "name": "DS", "desc": "Displacement (Multiple of 4)" }, { "name": "RA", "desc": "Base Register" } ], "pseudocode": "EA ← EXTS(DS || 00, 16) + (RA | 0)\nMEM(EA, 8) ← RS[0:63]", "example": "std r3, 16(r4)", "example_note": "Store 64-bit value.", "extension": "Base", "description": "Store the 64-bit doubleword in RS to memory at the effective address formed by adding the displacement DS (a 14-bit field shifted left 2 positions, thus a multiple of 4) to RA, or to the displacement alone if RA is 0. This is a Base category, 64-bit mode instruction with no status field updates.", "page_found": "Page 96", "programming_notes": "The std instruction stores a doubleword from a source register into memory. Ensure that the destination address is properly aligned to avoid performance penalties or exceptions. This instruction operates at user privilege level and will raise an exception if the EA is out of bounds." }, { "mnemonic": "trap", "architecture": "PowerISA", "full_name": "Trap (Pseudo)", "summary": "Unconditional trap. Forces an exception. (Encoded as tw 31, 0, 0).", "syntax": "trap", "encoding": { "format": "Pseudo", "binary_pattern": "3 | 11111 | 00000 | 00000 | 4 | /", "hex_opcode": "0x0FE00008", "visual_parts": [ { "raw": "tw 31, r0, r0", "clean": "tw 31, r0, r0" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [], "pseudocode": "Trap()", "example": "trap", "example_note": "Crash/Breakpoint.", "extension": "Base", "description": "Trap. Extended mnemonic for TW (tw 31,0,0). Unconditionally traps, transferring control to the system trap handler.", "special_registers": "MSR, SRR0, SRR1", "programming_notes": "Generates a program exception (System Call or Trap type) when the trap condition is true. The condition codes in TO select which comparisons trigger the trap: bit 0 = LT, bit 1 = GT, bit 2 = EQ, bit 3 = LU (unsigned), bit 4 = GU (unsigned). TO=31 (all bits set) always traps." }, { "mnemonic": "xor", "architecture": "PowerISA", "full_name": "XOR", "summary": "Performs a bitwise Exclusive OR comparison.", "syntax": "xor RA, RS, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 316 | Rc", "hex_opcode": "0x7C000278", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "316", "clean": "316" }, { "raw": "Rc", "clean": "Rc" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target Register" }, { "name": "RS", "desc": "Source Register 1" }, { "name": "RB", "desc": "Source Register 2" } ], "pseudocode": "RA ← RS ⊕ RB\nif Rc = 1 then\n CR0 ← (RA = 0) || LT || GT || SO", "example": "xor r3, r4, r5", "example_note": "r3 = r4 ^ r5", "extension": "Base", "description": "Perform a bitwise XOR of RS and RB, storing the result in RA. If Rc=1, CR0 is updated with the comparison flags based on the result. This is a Base category logical instruction.", "page_found": "Page 141", "special_registers": "CR0", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER." }, { "mnemonic": "xori", "architecture": "PowerISA", "full_name": "XOR Immediate", "summary": "Performs a bitwise XOR with a 16-bit unsigned immediate.", "syntax": "xori RA, RS, UI", "encoding": { "format": "D-form", "binary_pattern": "26 | RS | RA | UI", "hex_opcode": "0x68000000", "visual_parts": [ { "raw": "26", "clean": "26" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "UI", "clean": "UI" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target Register" }, { "name": "RS", "desc": "Source Register" }, { "name": "UI", "desc": "Unsigned 16-bit Immediate" } ], "pseudocode": "RA ← RS XOR (0x0000 || UI)", "example": "xori r3, r4, 0x1", "example_note": "Toggle bit 0.", "extension": "Base", "description": "XOR Immediate performs a bitwise XOR between the contents of GPR RS and a 16-bit zero-extended unsigned immediate, storing the result in GPR RA. This is a Base category instruction that does not affect condition registers or status fields.", "page_found": "Page 134", "programming_notes": "The xori instruction is commonly used for setting or clearing specific bits in a register by XORing with a mask. Be cautious of overflow as this operation does not affect the carry flag. The immediate value is zero-extended to 64 bits before the XOR operation, so ensure that the upper bits are not inadvertently set if only lower bits are intended to be modified." }, { "mnemonic": "xoris", "architecture": "PowerISA", "full_name": "XOR Immediate Shifted", "summary": "Performs a bitwise XOR with a 16-bit immediate shifted left by 16 bits.", "syntax": "xoris RA, RS, UI", "encoding": { "format": "D-form", "binary_pattern": "27 | RS | RA | UI", "hex_opcode": "0x6C000000", "visual_parts": [ { "raw": "27", "clean": "27" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "UI", "clean": "UI" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target Register" }, { "name": "RS", "desc": "Source Register" }, { "name": "UI", "desc": "Unsigned 16-bit Immediate" } ], "pseudocode": "RA ← RS XOR (UI || 0x0000)", "example": "xoris r3, r4, 0xFFFF", "example_note": "Toggle upper 16 bits.", "extension": "Base", "description": "XOR Immediate Shifted performs a bitwise XOR between the contents of GPR RS and a 16-bit unsigned immediate shifted left by 16 bits, storing the result in GPR RA. This is a Base category instruction that does not affect condition registers or status fields.", "page_found": "Page 134", "programming_notes": "The xoris instruction is useful for performing bitwise operations with a large immediate value. Be cautious of overflow if the immediate value exceeds 16 bits, as only the lower 16 bits are considered. This instruction operates at user privilege level and does not generate exceptions under normal circumstances." }, { "mnemonic": "xvsubdp", "architecture": "PowerISA", "full_name": "VSX Vector Subtract Double-Precision", "summary": "Subtracts the contents of two vector registers and places the result in a target vector register.", "syntax": "xvsubdp XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "11110001 | 00000000 | 00000000 | 1000", "hex_opcode": "0xF0000340", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "104", "clean": "104" } ], "length": "32", "bit_positions": "0:5 | 6:15 | 16:20 | 21:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" }, { "name": "VX", "desc": "Target Vector Register" } ], "extension": "VSX", "description": "For xvsubdp, each double-precision floating-point operand in the source vector registers is negated and added to the corresponding operand in the other source vector register. The results are normalized and rounded to double precision before being stored in the target vector register.", "pseudocode": "for i = {0, 1} do\n src1 <- VSR[XA][i]\n src2 <- VSR[XB][i]\n if src1 is NaN or src2 is NaN then\n v <- Q(src1) if src1 is NaN else Q(src2)\n vxsnan_flag <- 1 if either src1 or src2 is SNaN\n else if src1 is +Infinity and src2 is +Infinity then\n v <- +Infinity\n vxisi_flag <- 1\n else if src1 is -Infinity and src2 is -Infinity then\n v <- -Infinity\n vxisi_flag <- 1\n else if src1 is NZF and src2 is NZF then\n v <- S(src1, -src2)\n else if src1 is Zero and src2 is Zero then\n v <- Rezd\n else if src1 is +Zero and src2 is -Zero then\n v <- +Zero\n else if src1 is -Zero and src2 is +Zero then\n v <- -Zero\n else if src1 is NZF and src2 is Zero then\n v <- src1\n else if src1 is Zero and src2 is NZF then\n v <- -src2\n else if src1 is NZF and src2 is +Infinity then\n v <- -Infinity\n else if src1 is NZF and src2 is -Infinity then\n v <- +Infinity\n else if src1 is Zero and src2 is +Infinity then\n v <- -Infinity\n else if src1 is Zero and src2 is -Infinity then\n v <- +Infinity\n VSR[VX][i] <- v", "special_registers": "vxisi_flag, vxsnan_flag", "page_found": "Page 741 - 742", "programming_notes": "The xvsubdp instruction performs element-wise subtraction of double-precision floating-point numbers from two source vectors, negating the operands before addition. Be cautious with NaN and infinity values as they can set flags (vxsnan_flag, vxisi_flag) and affect results. Ensure proper alignment for vector registers to avoid performance penalties.", "example": "xvsubdp vs1, vs2, vs3" }, { "mnemonic": "xvmuldp", "architecture": "PowerISA", "full_name": "VSX Vector Multiply Double-Precision", "summary": "Multiplies two double-precision floating-point numbers in vector registers and stores the result.", "syntax": "xvmuldp XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "60 | XT | XA | XB | 112", "hex_opcode": "0xF0000380", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "112", "clean": "112" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "VSX Vector Multiply Double-Precision multiplies two double-precision floating-point elements from VSX registers XA and XB, storing the results in VSX register XT. This VSX category instruction processes two 64-bit elements in parallel and may update FPSCR with floating-point exception flags.", "pseudocode": "XT[0:63] ← XA[0:63] × XB[0:63]\nXT[64:127] ← XA[64:127] × XB[64:127]", "special_registers": "FPSCR", "page_found": "Page 735 - 736", "programming_notes": "The xvmuldp instruction performs element-wise multiplication of double-precision floating-point values in VSX registers. Ensure that the input vectors are properly aligned to avoid alignment faults. Be cautious with NaN and infinity handling, as they follow specific rules for propagation and sign determination. This instruction operates at user privilege level.", "example": "xvmuldp vs1, vs2, vs3" }, { "mnemonic": "xvdivdp", "architecture": "PowerISA", "full_name": "VSX Vector Divide Double-Precision", "summary": "Divides the contents of two vector registers and places the result in another vector register.", "syntax": "xvdivdp XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "60 | XT | XA | XB | 120", "hex_opcode": "0xF00003C0", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "120", "clean": "120" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register (Dividend)" }, { "name": "VRB", "desc": "Source Vector Register (Divisor)" } ], "extension": "VSX", "description": "For xvdivdp, each double-precision floating-point operand in doubleword elements of VSR[XA] is divided by the corresponding operand in VSR[XB], producing a quotient that is normalized and rounded to double precision. The result is placed into doubleword elements of VSR[XT].", "pseudocode": "for i = 0 to 1 do\n src1 <- VSR[XA][i]\n src2 <- VSR[XB][i]\n if src2 is NaN then\n v <- Q(src2)\n vxsnan_flag <- 1\n else if src1 is NaN then\n v <- Q(src1)\n vxsnan_flag <- 1\n else if src1 is +Infinity and src2 is +Infinity then\n v <- +Infinity\n vxidi_flag <- 1\n else if src1 is -Infinity and src2 is -Infinity then\n v <- +Infinity\n vxidi_flag <- 1\n else if src1 is +Infinity and src2 is -Infinity then\n v <- -Infinity\n vxidi_flag <- 1\n else if src1 is -Infinity and src2 is +Infinity then\n v <- -Infinity\n vxidi_flag <- 1\n else if src1 is +Zero and src2 is +Zero then\n v <- +Zero\n zx_flag <- 1\n else if src1 is -Zero and src2 is -Zero then\n v <- +Zero\n zx_flag <- 1\n else if src1 is +Zero and src2 is -Zero then\n v <- -Zero\n zx_flag <- 1\n else if src1 is -Zero and src2 is +Zero then\n v <- -Zero\n zx_flag <- 1\n else if src1 is +Infinity or src1 is -Infinity and src2 is not zero then\n v <- Q(src2)\n vxidi_flag <- 1\n else if src2 is +Zero or src2 is -Zero and src1 is not zero then\n v <- dQNaN\n vxzdz_flag <- 1\n else\n v <- D(src1, src2)\n VSR[VRT][i] <- v", "special_registers": "FPSCR, VXSNAN, VXIDI, VXZDZ, OX, UX, ZX, XX", "page_found": "Page 731 - 732", "programming_notes": "The xvdivdp instruction performs element-wise division of double-precision floating-point numbers. Ensure that the input vectors are properly aligned and that the destination vector is distinct to avoid unintended data corruption. Be aware of special cases like division by zero, which sets VXZDZ flag and results in a NaN. Handle exceptions by checking the FPSCR register flags after execution.", "example": "xvdivdp vs1, vs2, vs3" }, { "mnemonic": "xvabsdp", "architecture": "PowerISA", "full_name": "VSX Vector Absolute Value Double-Precision", "summary": "Computes the absolute value of each double-precision floating-point element in a vector.", "syntax": "xvabsdp XT, XB", "encoding": { "format": "XX2-form", "binary_pattern": "60 | XT | 0 | XB | 473", "hex_opcode": "0xF0000764", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "0", "clean": "0" }, { "raw": "XB", "clean": "XB" }, { "raw": "473", "clean": "473" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XB", "desc": "Source" } ], "extension": "VSX", "description": "The instruction computes the absolute value of each double-precision floating-point element in the source vector VSR[XB] and stores the result in the target vector VSR[XT].", "pseudocode": "if MSR.VSX=0 then\n VSX_Unavailable()\ndo i = 0 to 1\n src ←VSR[32×BX+B].dword[i]\n VSR[32×TX+T].dword[i] ←bfp64_ABSOLUTE(src)\nend", "page_found": "Page 646 - 647", "special_registers": "MSR", "programming_notes": "This instruction is used to compute the absolute value of each double-precision floating-point element in a vector. Ensure that VSX (Vector Scalar Extensions) is enabled by checking and setting the appropriate bit in the MSR register. The operation processes two elements per vector register, so ensure proper alignment if manipulating individual elements directly.", "example": "xvabsdp vs1, vs3" }, { "mnemonic": "xvnegdp", "architecture": "PowerISA", "full_name": "VSX Vector Negate Double-Precision", "summary": "Negates the contents of a double-precision floating-point vector register and stores the result in another vector register.", "syntax": "xvnegdp XT, XB", "encoding": { "format": "XX2-form", "binary_pattern": "60 | XT | 0 | XB | 489", "hex_opcode": "0xF00007E4", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "0", "clean": "0" }, { "raw": "XB", "clean": "XB" }, { "raw": "489", "clean": "489" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XB", "desc": "Source" } ], "extension": "VSX", "description": "The instruction negates each doubleword element of the source vector register VSR[XB] and stores the results in the target vector register VSR[XT].", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\ndo i = 0 to 3\n src ←VSR[32×BX+B].dword[i]\n VSR[32×TX+T].dword[i] ←bfp64_NEGATE(src)\nend", "page_found": "Page 649 - 650", "special_registers": "MSR", "programming_notes": "This instruction is used to negate each double-precision floating-point element in a vector. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking and setting the appropriate bit in the MSR register. The operation processes four elements per vector register, so ensure proper alignment of data for optimal performance. This instruction operates at the user privilege level and will raise an exception if VSX is not available.", "example": "xvnegdp vs1, vs3" }, { "mnemonic": "xvsqrtdp", "architecture": "PowerISA", "full_name": "VSX Vector Square Root Double-Precision", "summary": "Computes the square root of each double-precision floating-point element in a vector.", "syntax": "xvsqrtdp XT, XB", "encoding": { "format": "XX2-form", "binary_pattern": "60 | XT | 0 | XB | 203", "hex_opcode": "0xF000032C", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "0", "clean": "0" }, { "raw": "XB", "clean": "XB" }, { "raw": "203", "clean": "203" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XB", "desc": "Source" } ], "extension": "VSX", "description": "For xvsqrtdp, the unbounded-precision square root of each double-precision floating-point operand in doubleword elements of VSR[XB] is computed and rounded to double-precision format. The result is placed into corresponding elements of VSR[XT].", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nex_flag ←0b0\ndo i = 0 to 1\n reset_xflags()\n src ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])\n v ←bfp_SQUARE_ROOT(src)\n rnd ←bfp_ROUND_TO_BFP64(0b0,FPSCR.RN,v)\n vresult.dword[i] ←bfp64_CONVERT_FROM_BFP(rnd)\n if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\n if vxsqrt_flag=1 then SetFX(FPSCR.VXSQRT)\n if xx_flag=1 then SetFX(FPSCR.XX)\n ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vxsqrt_flag) | (FPSCR.XE & xx_flag)\nend\nif ex_flag=0 then VSR[32×TX+T] ←vresult", "special_registers": "FPSCR FX XX VXSNAN VXSQRT", "page_found": "Page 739 - 740", "programming_notes": "The xvsqrtdp instruction computes the square root of each double-precision floating-point operand in a vector. Ensure that VSX is enabled by checking MSR.VSX. Handle exceptions by examining FPSCR flags such as VXSNAN, VXSQRT, and XX. The instruction operates on aligned data and requires supervisor privilege level.", "example": "xvsqrtdp vs1, vs3" }, { "mnemonic": "xvmaxdp", "architecture": "PowerISA", "full_name": "Vector Scalar Maximum Double-Precision Floating Point", "summary": "Compares two double-precision floating-point values and selects the maximum value for each element.", "syntax": "xvmaxdp XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "60 | XT | XA | XB | 224", "hex_opcode": "0xF0000700", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "224", "clean": "224" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "For xvmaxdp, the instruction compares the double-precision floating-point values in the elements of VSR[XA] and VSR[XB], and places the maximum value into the corresponding elements of VSR[XT].", "pseudocode": "for i in {0, 1} do\n src1 <- VSR[XA][i]\n src2 <- VSR[XB][i]\n if src1 is QNaN or src2 is QNaN then\n T(Q(src2))\n else if src1 is SNaN or src2 is SNaN then\n fx(VXSNAN)\n else if src1 is +Infinity and src2 is -Infinity then\n T(src1)\n else if src1 is -Infinity and src2 is +Infinity then\n T(src2)\n else if src1 is NZF and src2 is Zero then\n T(src1)\n else if src1 is Zero and src2 is NZF then\n T(src2)\n else if src1 is NZF and src2 is NZF then\n T(M(src1,src2))\n else if src1 is +Zero and src2 is +Zero then\n T(src1)\n else if src1 is -Zero and src2 is -Zero then\n T(src2)\n else if src1 is +Infinity and src2 is +Infinity then\n T(src1)\n else if src1 is -Infinity and src2 is -Infinity then\n T(src2)\n else if src1 is QNaN or SNaN then\n T(src2)\n end if\nend for", "special_registers": "FPSCR (FX, VXSNAN)", "page_found": "Page 812 - 813", "programming_notes": "This instruction compares two double-precision floating-point vectors element-wise and stores the maximum value in each corresponding element of the destination vector. Be cautious with NaN values, as they can trigger exceptions or propagate through the operation. Ensure that the input vectors are properly aligned to avoid performance penalties.", "example": "xvmaxdp vs1, vs2, vs3" }, { "mnemonic": "xvmindp", "architecture": "PowerISA", "full_name": "VSX Vector Minimum Double-Precision", "summary": "Compares two double-precision floating-point values and selects the minimum value for each element.", "syntax": "xvmindp XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "111100 | XA | XT | 000000 | 000000 | 000000 | 000000 | 000000 | 000000", "hex_opcode": "0xF0000740", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "232", "clean": "232" } ], "length": "32", "bit_positions": "0:5 | 6:8 | 9:10 | 11:15 | 16:20 | 21:28 | 29 | 30 | 31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "VSX Vector Minimum Double-Precision compares two double-precision floating-point elements from VSX registers XA and XB element-wise, selecting the minimum value for each element and storing results in VSX register XT. This VSX category instruction processes two 64-bit elements in parallel and follows IEEE 754 minimum semantics.", "pseudocode": "XT[0:63] ← min(XA[0:63], XB[0:63])\nXT[64:127] ← min(XA[64:127], XB[64:127])", "special_registers": "FPSCR (FX, VXSNAN)", "page_found": "Page 816 - 817", "programming_notes": "The xvmindp instruction is used to perform element-wise minimum comparison of double-precision floating-point values in VSX registers. Ensure that the input vectors are properly aligned and that the FPSCR register is correctly configured to handle exceptions like NaNs or infinities. This instruction operates at a privilege level that allows access to VSX registers, typically requiring supervisor or higher privileges.", "example": "xvmindp vs1, vs2, vs3" }, { "mnemonic": "xvcmpeqdp", "architecture": "PowerISA", "full_name": "VSX Vector Compare Equal Double-Precision", "summary": "Compares two double-precision floating-point values in vector registers and sets the target register based on equality.", "syntax": "xvcmpeqdp XT,XA,XB", "encoding": { "format": "XX3-form", "binary_pattern": "T | A | B | Rc | AX | BX | TX", "hex_opcode": "0xF0000318", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "99", "clean": "99" } ], "length": "32", "bit_positions": "6:10 | 11:15 | 16:20 | 21:28 | 29 | 30 | 31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "For xvcmpeqdp, each element of the source vectors VSR[XA] and VSR[XB] is compared. The result is stored in VSR[XT]. If Rc=1, CR field 6 is updated with comparison results.", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nex_flag ←0b0\nall_false ←0b1\nall_true ←0b1\ndo i = 0 to 1\n reset_xflags()\n src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[i])\n src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])\n vxsnan_flag ←IsSNaN(src1) | IsSNaN(src2)\n if src1 = src2 then do\n all_false ←0b0\n end\n else do\n vresult.dword[i] ←0x0000_0000_0000_0000\n all_true ←0b0\n end\n if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\n ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag)\nend\nif Rc=1 then do\n if vex_flag=0 then\n CR[6] ←all_true || 0b0 || all_false || 0b0\n else\n CR[6] ←0bUUUU\nend", "special_registers": "CR, FPSCR", "page_found": "Page 806 - 807", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "xvcmpeqdp vs1, vs2, vs3" }, { "mnemonic": "xvcmpgtdp", "architecture": "PowerISA", "full_name": "VSX Vector Compare Greater Than Double-Precision", "summary": "Compares two double-precision floating-point values and sets the target vector register based on the comparison.", "syntax": "xvcmpgtdp XT,XA,XB", "encoding": { "format": "XX3-form", "binary_pattern": "T | A | B | Rc | AX | BX | TX", "hex_opcode": "0xF0000358", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "107", "clean": "107" } ], "length": "32", "bit_positions": "6:10 | 11:15 | 16:20 | 21:28 | 29 | 30 | 31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "For xvcmpgtdp, each element of the source vectors VSR[XA] and VSR[XB] is compared. The result is stored in VSR[XT]. If Rc=1, CR Field 6 is updated with the results of the comparison.", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\n\nex_flag ← 0b0\nall_false ← 0b1\nall_true ← 0b1\ndo i = 0 to 1\n reset_xflags()\n src1 ← bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[i])\n src2 ← bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])\n if src1.class.SNaN | src2.class.SNaN then do\n vxsnan_flag ← 0b1\n if FPSCR.VE=0 then vxvc_flag ← 0b1\n end else vxvc_flag ← IsQNaN(src1) | IsQNaN(src2)\n if src1 > src2 then do\n vresult.dword[i] ← 0xFFFF_FFFF_FFFF_FFFF\n all_false ← 0b0\n end else do\n all_true ← 0b0\n vresult.dword[i] ← 0x0000_0000_0000_0000\n end\n if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\n if vxvc_flag=1 then SetFX(FPSCR.VXVC)\n ex_flag ← ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vxvc_flag)\nend\nif ex_flag=0 then VSR[32×TX+T] ← vresult\nif Rc=1 then do\n if vex_flag=0 then CR.field[6] ← all_true || 0b0 || all_false || 0b0 else CR.field[6] ← 0bUUUU\nend", "special_registers": "CR, FPSCR", "page_found": "Page 810 - 811", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "xvcmpgtdp vs1, vs2, vs3" }, { "mnemonic": "xvcmpgedp", "architecture": "PowerISA", "full_name": "VSX Vector Compare Greater or Equal Double-Precision", "summary": "Compares two double-precision floating-point values and sets the target vector register based on the comparison.", "syntax": "xvcmpgedp XT,XA,XB", "encoding": { "format": "XX3-form", "binary_pattern": "T | A | B | Rc | 115 | AX | BX | TX", "hex_opcode": "0xF0000398", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "115", "clean": "115" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:28 | 29 | 30 | 31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VSX", "description": "For xvcmpgedp, each integer value i from 0 to 1, the double-precision floating-point operand in doubleword element i of VSR[XA] is compared to the double-precision floating-point operand in doubleword element i of VSR[XB]. The contents of doubleword element i of VSR[XT] are set to all 1s if src1 is greater than or equal to src2, and is set to all 0s otherwise.", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nex_flag ←0b0\nall_false ←0b1\nall_true ←0b1\ndo i = 0 to 1\n reset_xflags()\n src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[i])\n src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])\n if src1.class.SNaN | src2.class.SNaN then do\n vxsnan_flag ←0b1\n if FPSCR.VE=0 then vxvc_flag ←0b1\n end\n else vxvc_flag ←IsQNaN(src1) | IsQNaN(src2)\n if src1 >= src2 then do\n vresult.dword[i] ←0xFFFF_FFFF_FFFF_FFFF\n all_false ←0b0\n end\n else do\n vresult.dword[i] ←0x0000_0000_0000_0000\n all_true ←0b0\n end\n if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\n if vxvc_flag=1 then SetFX(FPSCR.VXVC)\n ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vxvc_flag)\nend\nif ex_flag=0 then VSR[32×TX+T] ←vresult\nif Rc=1 then do\n if vex_flag=0 then CR.field[6] ←all_true || 0b0 || all_false || 0b0\n else CR.field[6] ←0bUUUU\nend", "special_registers": "CR6, FPSCR", "page_found": "Page 808 - 809", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "xvcmpgedp vs1, vs2, vs3" }, { "mnemonic": "xvaddsp", "architecture": "PowerISA", "full_name": "VSX Vector Add Single-Precision", "summary": "Adds the contents of two single-precision floating-point vector registers and places the result in another vector register.", "syntax": "xvaddsp XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "60 | XT | XA | XB | 64", "hex_opcode": "0xF0000200", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "64", "clean": "64" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" }, { "name": "VSRD", "desc": "Destination Vector-Single-Precision Register" }, { "name": "VSRA", "desc": "Source Vector-Single-Precision Register" }, { "name": "VSRC", "desc": "Source Vector-Single-Precision Register" } ], "extension": "VSX", "description": "For xvaddsp, each element of the source vector VSRA is added to the corresponding element of the source vector VSRC, and the results are placed into the destination vector VSRD.", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\n\nex_flag ←0b0\ndo i = 0 to 3\n reset_xflags()\n src1 ←bfp_CONVERT_FROM_BFP32(VSR[32×AX+A].word[i])\n src2 ←bfp_CONVERT_FROM_BFP32(VSR[32×BX+B].word[i])\n v ←bfp_ADD(src1,src2)\n rnd ←bfp_ROUND_TO_BFP32(FPSCR.RN,v)\n vresult.word[i] ←bfp32_CONVERT_FROM_BFP(rnd)\n\n if vxisi_flag=1 then SetFX(FPSCR.VXISI)\n if ox_flag=1 then SetFX(FPSCR.OX)\n if ux_flag=1 then SetFX(FPSCR.UX)\n if xx_flag=1 then SetFX(FPSCR.XX)\n\n ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vxisi_flag) | (FPSCR.OE & ox_flag) | (FPSCR.UE & ux_flag) | (FPSCR.XE & xx_flag)\nend\n\nif ex_flag=0 then VSR[32×TX+T] ←vresult", "page_found": "Page 564 - 565", "special_registers": "VSR, vxsnan_flag, vxisi_flag", "programming_notes": "The xvaddsp instruction is used for adding single-precision floating-point numbers in vector registers. Ensure that the VSX feature is enabled by checking and setting MSR.VSX. Be aware of potential exceptions such as invalid operations (VXISI), overflow (OX), underflow (UX), or inexact results (XX). These conditions can be checked using the FPSCR flags.", "example": "xvaddsp vs1, vs2, vs3" }, { "mnemonic": "xvsubsp", "architecture": "PowerISA", "full_name": "VSX Vector Subtract Single-Precision", "summary": "Subtracts the contents of two vector registers and places the result in another vector register.", "syntax": "xvsubsp XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "110000 | VX | XA | XB | 000000 | 000000 | 000000 | 000000", "hex_opcode": "0xF0000240", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "72", "clean": "72" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:28 | 29 | 30 | 31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" }, { "name": "VX", "desc": "Target Vector Register" } ], "extension": "VSX", "description": "For xvsubsp, each single-precision floating-point operand in word elements of VSR[XA] is negated and added to the corresponding element in VSR[XB]. The results are normalized and rounded to single precision before being placed into VSR[XT].", "pseudocode": "for i = 0 to 3 do\n src1 <- VSR[XA][i]\n src2 <- VSR[XB][i]\n if src1 is NaN or src2 is NaN then\n v <- Q(src1) or Q(src2)\n vxsnan_flag <- 1\n else if src1 is +Infinity and src2 is +Infinity then\n v <- +Infinity\n vxisi_flag <- 1\n else if src1 is -Infinity and src2 is -Infinity then\n v <- -Infinity\n vxisi_flag <- 1\n else if src1 is NZF and src2 is NZF then\n v <- S(src1, -src2)\n else if src1 is Zero and src2 is Zero then\n v <- Rezd\n else if src1 is +Zero and src2 is -Zero then\n v <- +Zero\n else if src1 is -Zero and src2 is +Zero then\n v <- -Zero\n else if src1 is NZF and src2 is Zero then\n v <- src1\n else if src1 is Zero and src2 is NZF then\n v <- -src2\n else if src1 is +Infinity and src2 is NZF then\n v <- +Infinity\n else if src1 is NZF and src2 is +Infinity then\n v <- -Infinity\n else if src1 is -Infinity and src2 is NZF then\n v <- -Infinity\n else if src1 is NZF and src2 is -Infinity then\n v <- +Infinity\n VSR[VX][i] <- v", "special_registers": "vxsnan_flag, vxisi_flag", "page_found": "Page 743 - 744", "programming_notes": "The xvsubsp instruction performs element-wise subtraction of single-precision floating-point numbers in VSX registers. Be cautious with NaNs, infinities, and zeros as they can trigger special flags (vxsnan_flag, vxisi_flag) and may result in unexpected outcomes. Ensure that the input vectors are properly aligned to avoid alignment faults.", "example": "xvsubsp vs1, vs2, vs3" }, { "mnemonic": "xvmulsp", "architecture": "PowerISA", "full_name": "VSX Vector Multiply Single-Precision", "summary": "Multiplies the contents of two single-precision floating-point values and places the result into a vector register.", "syntax": "xvmulsp XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "60 | XT | XA | XB | 80", "hex_opcode": "0xF0000280", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "80", "clean": "80" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "VSX Vector Multiply Single-Precision multiplies four single-precision floating-point elements from VSX registers XA and XB, storing the results in VSX register XT. This VSX category instruction processes four 32-bit elements in parallel and may update FPSCR with floating-point exception flags.", "pseudocode": "XT[0:31] ← XA[0:31] × XB[0:31]\nXT[32:63] ← XA[32:63] × XB[32:63]\nXT[64:95] ← XA[64:95] × XB[64:95]\nXT[96:127] ← XA[96:127] × XB[96:127]", "special_registers": "FPSCR", "page_found": "Page 737 - 738", "programming_notes": "The xvmulsp instruction performs element-wise multiplication of single-precision floating-point values in vector registers. Ensure that the input vectors are properly aligned to avoid alignment faults. Be cautious with NaN and infinity handling, as they follow specific rules for propagation and sign determination. This instruction operates at user privilege level.", "example": "xvmulsp vs1, vs2, vs3" }, { "mnemonic": "xvdivsp", "architecture": "PowerISA", "full_name": "VSX Vector Divide Single-Precision", "summary": "Divides the contents of two vector registers and places the result in another vector register.", "syntax": "xvdivsp XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "60 | XT | XA | XB | 88", "hex_opcode": "0xF00002C0", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "88", "clean": "88" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" }, { "name": "VD", "desc": "Destination Vector Register" }, { "name": "VA", "desc": "Source Vector Register (Dividend)" }, { "name": "VB", "desc": "Source Vector Register (Divisor)" } ], "extension": "VSX", "description": "For xvdivsp, each element of the source vectors VSR[XA] and VSR[XB] is divided to produce a quotient that is placed into the corresponding element of the target vector VSR[XT].", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\n\nex_flag ←0b0\ndo i = 0 to 3\n reset_xflags()\n src1 ←bfp_CONVERT_FROM_BFP32(VSR[32×AX+A].word[i])\n src2 ←bfp_CONVERT_FROM_BFP32(VSR[32×BX+B].word[i])\n v ←bfp_DIVIDE(src1,src2)\n rnd ←bfp_ROUND_TO_BFP32(FPSCR.RN,v)\n vresult.word[i] ←bfp32_CONVERT_FROM_BFP(rnd)\n if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\n if vxidi_flag=1 then SetFX(FPSCR.VXIDI)\n if vxisi_flag=1 then SetFX(FPSCR.VXZDZ)\n if ox_flag=1 then SetFX(FPSCR.OX)\n if ux_flag=1 then SetFX(FPSCR.UX)\n if xx_flag=1 then SetFX(FPSCR.XX)\n if zx_flag=1 then SetFX(FPSCR.ZX)\n\n ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) \n | (FPSCR.VE & vxidi_flag) \n | (FPSCR.VE & vxzdz_flag) \n | (FPSCR.OE & ox_flag) \n | (FPSCR.UE & ux_flag) \n | (FPSCR.ZE & zx_flag) \n | (FPSCR.XE & xx_flag)\nend\n\nif ex_flag=0 then VSR[32×TX+T] ←vresult", "special_registers": "FPSCR, VXSNAN, VXIDI, VXZDZ, OX, UX, ZX, XX", "page_found": "Page 733 - 734", "programming_notes": "The xvdivsp instruction performs element-wise division of single-precision floating-point numbers in VSX vectors. Ensure that the VSX facility is enabled (MSR.VSX=1) to avoid exceptions. Handle potential exceptions by checking the FPSCR flags, especially VXSNAN, VXIDI, VXZDZ, OX, UX, ZX, and XX. Be cautious of alignment requirements for vector registers to maintain performance.", "example": "xvdivsp vs1, vs2, vs3" }, { "mnemonic": "xvabssp", "architecture": "PowerISA", "full_name": "VSX Vector Absolute Value Single-Precision", "summary": "Computes absolute value for four single-precision floats.", "syntax": "xvabssp XT, XB", "encoding": { "format": "XX2-form", "binary_pattern": "60 | XT | 0 | XB | 409", "hex_opcode": "0xF0000664", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "0", "clean": "0" }, { "raw": "XB", "clean": "XB" }, { "raw": "409", "clean": "409" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XB", "desc": "Source" } ], "extension": "VSX", "description": "VSX Vector Absolute Value Single-Precision computes the absolute value of four single-precision floating-point elements from VSX register XB, storing the results in VSX register XT. This VSX category instruction clears the sign bit of each 32-bit element and does not affect floating-point status flags.", "pseudocode": "XT[0:31] ← |XB[0:31]|\nXT[32:63] ← |XB[32:63]|\nXT[64:95] ← |XB[64:95]|\nXT[96:127] ← |XB[96:127]|", "page_found": "Page 647", "special_registers": "MSR", "programming_notes": "The xvabssp instruction is used to compute the absolute value of each single-precision floating-point element in a vector register. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking and setting the appropriate bit in the MSR register. This instruction processes four elements per operation, so ensure your data is appropriately aligned for optimal performance.", "example": "xvabssp vs1, vs3" }, { "mnemonic": "xvnegsp", "architecture": "PowerISA", "full_name": "VSX Vector Negate Single-Precision", "summary": "Negates the contents of a single-precision floating-point register.", "syntax": "xvnegsp XT, XB", "encoding": { "format": "XX2-form", "binary_pattern": "60 | XT | 0 | XB | 425", "hex_opcode": "0xF00006E4", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "0", "clean": "0" }, { "raw": "XB", "clean": "XB" }, { "raw": "425", "clean": "425" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XB", "desc": "Source" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VSX", "pseudocode": "XT[0:31] ← -XB[0:31]\nXT[32:63] ← -XB[32:63]\nXT[64:95] ← -XB[64:95]\nXT[96:127] ← -XB[96:127]", "page_found": "Page 1452 - 1453", "description": "VSX Vector Negate Single-Precision negates four single-precision floating-point elements from VSX register XB, storing the results in VSX register XT. This VSX category instruction inverts the sign bit of each 32-bit element and does not affect floating-point status flags.", "programming_notes": "Use xvnegsp to negate each single-precision float in a VSX vector. Ensure vectors are properly aligned; misalignment can cause exceptions. This instruction operates at user privilege level.", "example": "xvnegsp vs1, vs3" }, { "mnemonic": "xvsqrtsp", "architecture": "PowerISA", "full_name": "VSX Vector Square Root Single-Precision", "summary": "Computes the square root of each single-precision floating-point element in a vector.", "syntax": "xvsqrtsp XT, XB", "encoding": { "format": "XX2-form", "binary_pattern": "60 | XT | 0 | XB | 139", "hex_opcode": "0xF000022C", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "0", "clean": "0" }, { "raw": "XB", "clean": "XB" }, { "raw": "139", "clean": "139" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XB", "desc": "Source" } ], "extension": "VSX", "description": "For xvsqrtsp, the unbounded-precision square root of each single-precision floating-point operand in word elements i of VSR[XB] is computed. The result is rounded to single precision using the rounding mode specified by RN and placed into word element i of VSR[XT].", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nex_flag ←0b0\ndo i = 0 to 3\n reset_xflags()\n src ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].word[i])\n v ←bfp_SQUARE_ROOT(src)\n rnd ←bfp_ROUND_TO_BFP32(FPSCR.RN,v)\n vresult.word[i] ←bfp32_CONVERT_FROM_BFP(rnd)\n if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\n if vxsqrt_flag=1 then SetFX(FPSCR.VXSQRT)\n if xx_flag=1 then SetFX(FPSCR.XX)\n ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vxsqrt_flag) | (FPSCR.XE & xx_flag)\nend\nif ex_flag=0 then VSR[32×TX+T] ←vresult", "special_registers": "FPSCR, VXSNAN, VXSQRT, XX", "page_found": "Page 740 - 741", "programming_notes": "The xvsqrtsp instruction computes the square root of each single-precision floating-point element in a vector. Ensure that VSX is enabled (MSR.VSX=1) to avoid exceptions. Handle potential exceptions by checking FPSCR flags such as VXSNAN, VXSQRT, and XX. The instruction operates on 4 elements per vector register.", "example": "xvsqrtsp vs1, vs3" }, { "mnemonic": "xvmaxsp", "architecture": "PowerISA", "full_name": "VSX Vector Maximum Single-Precision", "summary": "Computes the maximum of corresponding single-precision floating-point elements in two vector registers and stores the result in a third vector register.", "syntax": "xvmaxsp XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "60 | XT | XA | XB | 192", "hex_opcode": "0xF0000600", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "192", "clean": "192" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "For xvmaxsp, the instruction compares each element of the source vectors VSR[XA] and VSR[XB] and places the larger value into the corresponding element of the target vector VSR[XT].", "pseudocode": "for i = 0 to 3 do\n src1 <- VSR[XA][i]\n src2 <- VSR[XB][i]\n if isNaN(src1) or isNaN(src2) then\n fx(VXSNAN)\n T(Q(src2))\n else if isInfinity(src1) and isInfinity(src2) and sign(src1) != sign(src2) then\n fx(VXSNAN)\n T(Q(src2))\n else if isZero(src1) and isZero(src2) and sign(src1) != sign(src2) then\n fx(VXSNAN)\n T(Q(src2))\n else\n T(M(src1, src2))\n end if\nend for", "special_registers": "FPSCR (FX, VXSNAN)", "page_found": "Page 814 - 815", "programming_notes": "The xvmaxsp instruction compares each element of two source vectors and stores the larger value in the target vector. It handles NaNs by setting VXSNAN in the FPSCR and transferring the quiet NaN to the result. Be cautious with infinities and zeros of opposite signs, as they also trigger VXSNAN. Ensure that the vectors are properly aligned for optimal performance.", "example": "xvmaxsp vs1, vs2, vs3" }, { "mnemonic": "xvminsp", "architecture": "PowerISA", "full_name": "VSX Vector Minimum Single-Precision", "summary": "Performs a minimum operation on single-precision floating-point values from two vector scalar registers and stores the result in another vector scalar register.", "syntax": "xvminsp XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "60 | XT | XA | XB | 200", "hex_opcode": "0xF0000640", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "200", "clean": "200" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "VSX Vector Minimum Single-Precision compares four single-precision floating-point elements from VSX registers XA and XB element-wise, selecting the minimum value for each element and storing results in VSX register XT. This VSX category instruction processes four 32-bit elements in parallel and follows IEEE 754 minimum semantics.", "pseudocode": "XT[0:31] ← min(XA[0:31], XB[0:31])\nXT[32:63] ← min(XA[32:63], XB[32:63])\nXT[64:95] ← min(XA[64:95], XB[64:95])\nXT[96:127] ← min(XA[96:127], XB[96:127])", "special_registers": "FPSCR (FX, VXSNAN)", "page_found": "Page 818 - 819", "programming_notes": "The xvminsp instruction is commonly used for performing element-wise minimum comparisons on single-precision floating-point values in VSX registers. Ensure that the VSX facility is enabled by checking and setting the MSR.VSX bit. Be aware of the VXSNAN flag, which indicates a quiet NaN result; this can be checked via the FPSCR register. The instruction operates at the user privilege level and does not raise exceptions unless enabled through the FPSCR's VE (Invalid Operation Enable) bit.", "example": "xvminsp vs1, vs2, vs3" }, { "mnemonic": "xvcmpeqsp", "architecture": "PowerISA", "full_name": "VSX Vector Compare Equal Single-Precision", "summary": "Compares each single-precision floating-point element of two VSX registers and sets the corresponding element in the target register to all 1s if they are equal, otherwise all 0s.", "syntax": "xvcmpeqsp XT,XA,XB", "encoding": { "format": "XX3-form", "binary_pattern": "T | A | B | Rc | AX | BX | TX", "hex_opcode": "0xF0000218", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "67", "clean": "67" } ], "length": "32", "bit_positions": "6:10 | 11:15 | 16:20 | 21:28 | 29 | 30 | 31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "For xvcmpeqsp, each integer value i from 0 to 3, the single-precision floating-point operand in word element i of VSR[XA] is compared to the single-precision floating-point operand in word element i of VSR[XB]. The contents of word element i of VSR[XT] are set to all 1s if they are equal, and all 0s otherwise.", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nex_flag ←0b0\nall_false ←0b1\nall_true ←0b1\ndo i = 0 to 3\n reset_xflags()\n src1 ←bfp_CONVERT_FROM_BFP32(VSR[32×AX+A].word[i])\n src2 ←bfp_CONVERT_FROM_BFP32(VSR[32×BX+B].word[i])\n vxsnan_flag ←IsSNaN(src1) | IsSNaN(src2)\n if src1 = src2 then do\n all_false ←0b0\n end\n else do\n vresult.word[i] ←0x0000_0000\n all_true ←0b0\n end\n if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\n ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag)\nend\nif Rc=1 then do\n if vex_flag=0 then\n CR.field[6] ←all_true || 0b0 || all_false || 0b0\n else\n CR.field[6] ←0bUUUU\nend", "special_registers": "CR, FPSCR", "page_found": "Page 807 - 808", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "xvcmpeqsp vs1, vs2, vs3" }, { "mnemonic": "xvcmpgtsp", "architecture": "PowerISA", "full_name": "VSX Vector Compare Greater Than Single-Precision", "summary": "Compares each single-precision floating-point element in two vector registers and sets the corresponding element in a target vector register to all 1s if the first element is greater than the second, otherwise all 0s.", "syntax": "xvcmpgtsp XT,XA,XB", "encoding": { "format": "XX3-form", "binary_pattern": "T | A | B | Rc | AX | BX | TX", "hex_opcode": "0xF0000258", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "75", "clean": "75" } ], "length": "32", "bit_positions": "6:10 | 11:15 | 16:20 | 21 | 22:28 | 29 | 30:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "For xvcmpgtsp, each integer value i from 0 to 3, the single-precision floating-point operand in word element i of VSR[XA] is compared to the single-precision floating-point operand in word element i of VSR[XB]. The contents of word element i of VSR[XT] are set to all 1s if the first operand is greater than the second, and all 0s otherwise.", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\n\nex_flag ←0b0\nall_false ←0b1\nall_true ←0b1\ndo i = 0 to 3\n reset_xflags()\n src1 ←bfp_CONVERT_FROM_BFP32(VSR[32×AX+A].word[i])\n src2 ←bfp_CONVERT_FROM_BFP32(VSR[32×BX+B].word[i])\n if IsSNaN(src1)=1 | IsSNaN(src2)=1 then do\n vxsnan_flag ←0b1\n if FPSCR.VE=0 then vxvc_flag ←0b1\n end\n else\n vxvc_flag ←src1.class.QNaN | src2.class.QNaN\n if src1 > src2 then do\n vresult.word[i] ←0xFFFF_FFFF\n all_false ←0b0\n end\n else\n vresult.word[i] ←0x0000_0000\n all_true ←0b0\n end\n if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\n if vxvc_flag=1 then SetFX(FPSCR.VXVC)\n ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vxvc_flag)\nend\nif ex_flag=0 then VSR[32×TX+T] ←vresult\nif Rc=1 then do\n if vex_flag=0 then\n CR.field[6] ←all_true || 0b0 || all_false || 0b0\n else\n CR.field[6] ←0bUUUU\nend", "special_registers": "CR6, FPSCR", "page_found": "Page 811 - 812", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "xvcmpgtsp vs1, vs2, vs3" }, { "mnemonic": "xvcmpgesp", "architecture": "PowerISA", "full_name": "VSX Vector Compare Greater or Equal Single-Precision", "summary": "Compares each element of two single-precision floating-point vectors and sets the target vector elements to all 1s if the corresponding source elements are greater than or equal, otherwise all 0s.", "syntax": "xvcmpgesp XT,XA,XB", "encoding": { "format": "XX3-form", "binary_pattern": "T | A | B | Rc | 83 | AX | BX | TX", "hex_opcode": "0xF0000298", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "83", "clean": "83" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:28 | 29 | 30 | 31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "For xvcmpgesp, each element of the single-precision floating-point vector in VSR[XA] is compared with the corresponding element in VSR[XB]. The result is stored in VSR[XT]. If Rc=1, CR field 6 is updated based on the comparison results.", "pseudocode": "if 'xvcmpgesp' then\n for each integer value i from 0 to 3 do\n src1 ← bfp_CONVERT_FROM_BFP32(VSR[32×AX+A].word[i])\n src2 ← bfp_CONVERT_FROM_BFP32(VSR[32×BX+B].word[i])\n if src1.class.SNaN | src2.class.SNaN then\n vxsnan_flag ← 0b1\n if FPSCR.VE=0 then vxvc_flag ← 0b1\n else vxvc_flag ← IsQNaN(src1) | IsQNaN(src2)\n if src1 >= src2 then\n vresult.word[i] ← 0xFFFF_FFFF\n else\n vresult.word[i] ← 0x0000_0000\n ex_flag ← ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vxvc_flag)\n end\n if ex_flag=0 then VSR[32×TX+T] ← vresult\n if Rc=1 then do\n CR.field[6] ← all_true || 0b0 || all_false || 0b0\n end", "special_registers": "CR6, FPSCR (FX VXSNAN VXVC)", "page_found": "Page 809 - 810", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "xvcmpgesp vs1, vs2, vs3" }, { "mnemonic": "xscvdpsxds", "architecture": "PowerISA", "full_name": "VSX Scalar Convert Double-Precision to Signed Doubleword with Round to Zero", "summary": "Converts a double-precision floating-point value to a signed doubleword integer using round towards zero.", "syntax": "xscvdpsxds XT, XB", "encoding": { "format": "XX2-form", "binary_pattern": "60 | T | B | 344 | BX | TX", "hex_opcode": "0xF0000560", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "0", "clean": "0" }, { "raw": "XB", "clean": "XB" }, { "raw": "344", "clean": "344" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XB", "desc": "Source" } ], "extension": "VSX", "description": "The instruction converts the double-precision floating-point value in doubleword element 0 of VSR[XB] to a signed doubleword integer. The result is placed into doubleword element 0 of VSR[XT], and doubleword element 1 of VSR[XT] is set to 0.", "pseudocode": "if src ≤ Nmin - 1 then\n T(Nmin)\n fr(0)\n fi(0)\n fx(VXCVI)\n if error() then invoke system error handler\nelse if Nmin - 1 < src < Nmin then\n T(Nmin)\n fr(0)\n fi(1)\n fx(XX)\n if error() then invoke system error handler\nelse if src = Nmin then\n T(Nmin)\n fr(0)\n fi(0)\nelse if Nmin < src < Nmax then\n T(f2i(trunc(src)))\n fr(0)\n fi(1)\n fx(XX)\n if error() then invoke system error handler\nelse if src = Nmax then\n T(Nmax)\n fr(0)\n fi(0)\nelse if Nmax < src < Nmax + 1 then\n T(Nmax)\n fr(0)\n fi(1)\n fx(XX)\n if error() then invoke system error handler\nelse if src ≥ Nmax + 1 then\n T(Nmin)\n fr(0)\n fi(0)\n fx(VXCVI)\n if error() then invoke system error handler\nelse if src is a QNaN then\n T(Nmin)\n fr(0)\n fi(0)\n fx(VXCVI)\n if error() then invoke system error handler\nelse if src is a SNaN then\n T(Nmin)\n fr(0)\n fi(0)\n fx(VXCVI)\n fx(VXSNAN)\n if error() then invoke system error handler", "special_registers": "FPSCR, VSR[XT]", "programming_notes": "xscvdpsxds rounds using Round towards Zero rounding mode. For other rounding modes, software must use a Round to Double-Precision Integer instruction that corresponds to the desired rounding mode. Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.", "page_found": "Page 851 - 852", "example": "xscvdpsxds vs1, vs3" }, { "mnemonic": "xscvdpuxds", "architecture": "PowerISA", "full_name": "VSX Scalar Convert Double-Precision to Unsigned Doubleword with Round to Zero", "summary": "Converts a double-precision floating-point value to an unsigned 64-bit integer using round towards zero.", "syntax": "xscvdpuxds XT, XB", "encoding": { "format": "XX2-form", "binary_pattern": "18 | T | B | 328 | BX | TX", "hex_opcode": "0xF0000520", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "0", "clean": "0" }, { "raw": "XB", "clean": "XB" }, { "raw": "328", "clean": "328" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XB", "desc": "Source" } ], "extension": "VSX", "description": "The instruction converts the double-precision floating-point value in doubleword element 0 of VSR[XB] to an unsigned 64-bit integer. The result is placed into doubleword element 0 of VSR[XT], and doubleword element 1 of VSR[XT] is set to 0.", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nreset_xflags()\nsrc ← bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])\nrnd ← bfp_ROUND_TO_INTEGER(0b001, src)\nresult ← ui64_CONVERT_FROM_BFP(rnd)\nvxsnan_flag ← vxsnan(src)\nvxcvi_flag ← vxcvi(src)\nxx_flag ← xx(src)\nvx_flag ← vxsnan_flag | vxcvi_flag\nvex_flag ← FPSCR.VE & vx_flag\nif vex_flag=0 then\ndo\n VSR[32×TX+T].dword[1] ← result\n VSR[32×TX+T].dword[2] ← 0x0000_0000_0000_0000\n FPSCR.FPRF ← 0bUUUUU\n FPSCR.FR ← inc_flag\n FPSCR.FI ← xx_flag\nend\nelse\ndo\n FPSCR.FR ← 0b0\n FPSCR.FI ← 0b0\nend", "special_registers": "FPSCR (undefined), VXSNAN, VXCVI, FX, XX", "programming_notes": "If src is a NaN, the result is 0x0000_0000_0000_0000 and VXCVI is set to 1. If src is an SNaN, VXSNAN is also set to 1. If the rounded value is greater than 264 -1, the result is 0xFFFF_FFFF_FFFF_FFFF and VXCVI is set to 1. Otherwise, if the rounded value is less than 0, the result is 0x0000_0000_0000_0000 and VXCVI is set to 1. Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.", "page_found": "Page 855 - 856", "example": "xscvdpuxds vs1, vs3" }, { "mnemonic": "xscvspdp", "architecture": "PowerISA", "full_name": "Vector Scalar Convert Single-Precision to Double-Precision format Non-signalling", "summary": "Converts a single-precision floating-point value in VSR[XB] to double-precision format and places the result into VSR[XT].", "syntax": "xscvspdp XT, XB", "encoding": { "format": "XX2-form", "binary_pattern": "60 | XT | 0 | XB | 408", "hex_opcode": "0xF0000524", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "0", "clean": "0" }, { "raw": "XB", "clean": "XB" }, { "raw": "408", "clean": "408" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XB", "desc": "Source" } ], "extension": "VSX", "description": "Converts a single-precision floating-point value in the lower 32 bits of VSR[XB] to double-precision format and places the result in VSR[XT]. This is a scalar VSX instruction that operates on element 0 of the VSR. The instruction does not signal on NaN or other exceptional floating-point conditions.", "pseudocode": "VSR[XT].element[0] ← ConvertSP_to_DP(VSR[XB].element[0])", "special_registers": "FPSCR, VXSNAN", "programming_notes": "xscvspdp can be used to convert a single-precision value in single-precision format to double-precision format for use by Floating-Point scalar single-precision operations. Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.", "page_found": "Page 832 - 833", "example": "xscvspdp vs1, vs3" }, { "mnemonic": "xscvdpsp", "architecture": "PowerISA", "full_name": "VSX Scalar Convert Double-Precision to Single-Precision", "summary": "Converts a double-precision floating-point value in VSR[XB] to single-precision format and places the result into VSR[XT].", "syntax": "xscvdpsp XT, XB", "encoding": { "format": "XX2-form", "binary_pattern": "60 | XT | 0 | XB | 264", "hex_opcode": "0xF0000424", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "0", "clean": "0" }, { "raw": "XB", "clean": "XB" }, { "raw": "264", "clean": "264" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XB", "desc": "Source" } ], "extension": "VSX", "description": "The instruction converts the double-precision floating-point value from word element 0 of VSR[XB] to single-precision format. The result is placed into word elements 0 and 1 of VSR[XT], with word elements 2 and 3 set to zero.", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nreset_xflags()\nsrc ← bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])\nrnd ← bfp_ROUND_TO_BFP32(FPSCR.RN, src)\nresult ← bfp32_CONVERT_FROM_BFP(rnd)\nif vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\nif xx_flag=1 then SetFX(FPSCR.XX)\nif ox_flag=1 then SetFX(FPSCR.OX)\nif ux_flag=1 then SetFX(FPSCR.UX)\nvex_flag ← FPSCR.VE & vxsnan_flag\nif vex_flag=0 then do\n VSR[32×TX+T].word[0] ← result\n VSR[32×TX+T].word[1] ← result\n VSR[32×TX+T].word[2] ← 0x0000_0000\n VSR[32×TX+T].word[3] ← 0x0000_0000\n FPSCR.FPRF ← fprf_CLASS_BFP32(result)\n FPSCR.FR ← inc_flag\n FPSCR.FI ← xx_flag\nend else do\n FPSCR.FI ← 0b0\nend", "special_registers": "FPSCR, FPRF, FR, FI, VXSNAN", "programming_notes": "This instruction can be used to operate on a single-precision source operand. Previous versions of the architecture allowed the contents of words 1, 2, and 3 of the result register to be undefined, however, all processors that support this instruction write the result into both words 0 and 1 of the result register, as is required by this version of the architecture. If src is a SNaN, the result is src converted to a QNaN (i.e., bit 12 of src is set to 1). VXSNAN is set to 1.", "page_found": "Page 824 - 825", "example": "xscvdpsp vs1, vs3" }, { "mnemonic": "xvcvdpsp", "architecture": "PowerISA", "full_name": "Vector Convert Double-Precision to Single-Precision", "summary": "Converts double-precision floating-point values in a vector to single-precision format.", "syntax": "xvcvdpsp XT, XB", "encoding": { "format": "XX2-form", "binary_pattern": "60 | XT | 0 | XB | 393", "hex_opcode": "0xF0000624", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "0", "clean": "0" }, { "raw": "XB", "clean": "XB" }, { "raw": "393", "clean": "393" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XB", "desc": "Source" } ], "extension": "VSX", "description": "Converts two double-precision floating-point values in VSR[XB] to single-precision format and places the results in VSR[XT]. The two double-precision elements (0 and 1) are converted and packed into the single-precision elements (0 and 1) of the target. Rounding is performed according to the current rounding mode in FPSCR.", "pseudocode": "VSR[XT].element[0] ← ConvertDP_to_SP(VSR[XB].element[0])\nVSR[XT].element[1] ← ConvertDP_to_SP(VSR[XB].element[1])", "special_registers": "FPSCR", "programming_notes": "Previous versions of the architecture allowed the contents of bits 32:63 of each doubleword in the result register to be undefined, however, all processors that support this instruction write the result into bits 32:63 of each doubleword in the result register as well as into bits 0:31, as is required by this version of the architecture. Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.", "page_found": "Page 828 - 829", "example": "xvcvdpsp vs1, vs3" }, { "mnemonic": "xvcvspdp", "architecture": "PowerISA", "full_name": "VSX Vector Convert Single to Double", "summary": "Converts two floats to two doubles.", "syntax": "xvcvspdp XT, XB", "encoding": { "format": "XX2-form", "binary_pattern": "60 | XT | 0 | XB | 457", "hex_opcode": "0xF0000724", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "0", "clean": "0" }, { "raw": "XB", "clean": "XB" }, { "raw": "457", "clean": "457" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XB", "desc": "Source" } ], "extension": "VSX", "description": "Converts two single-precision floating-point values in VSR[XB] to double-precision format and places the results in VSR[XT]. The single-precision elements (0 and 1) are expanded to double-precision elements (0 and 1). No rounding is required for this widening conversion.", "pseudocode": "VSR[XT].element[0] ← ConvertSP_to_DP(VSR[XB].element[0])\nVSR[XT].element[1] ← ConvertSP_to_DP(VSR[XB].element[1])", "page_found": "Page 836", "special_registers": "FPSCR, MSR", "programming_notes": "The xvcvspdp instruction is used to convert a vector of single-precision floating-point values to double-precision. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register, otherwise, an exception will be raised. Handle special cases like signaling NaNs by checking and setting the appropriate flags in FPSCR.", "example": "xvcvspdp vs1, vs3" }, { "mnemonic": "xvcvdpsxds", "architecture": "PowerISA", "full_name": "VSX Vector Convert Double-Precision to Signed Doubleword for- mat XX2-form", "summary": "Converts a double-precision floating-point value to a signed doubleword integer, rounding according to the current rounding mode.", "syntax": "xvcvdpsxds XT, XB", "encoding": { "format": "XX2-form", "binary_pattern": "60 | XT | / | XB | 472", "hex_opcode": "0xF0000760", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "0", "clean": "0" }, { "raw": "XB", "clean": "XB" }, { "raw": "472", "clean": "472" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XB", "desc": "Source" } ], "extension": "VSX", "description": "Converts two double-precision floating-point values in VSR[XB] to signed 64-bit integer format (doubleword) and places the results in VSR[XT]. Rounding is performed according to the current rounding mode in FPSCR. On overflow or invalid operation, the result is saturated to the maximum or minimum signed 64-bit integer.", "pseudocode": "VSR[XT].element[0] ← ConvertDP_to_SXD_Round(VSR[XB].element[0], RoundMode)\nVSR[XT].element[1] ← ConvertDP_to_SXD_Round(VSR[XB].element[1], RoundMode)", "special_registers": "FPSCR, VSR[XT], VSR[XB]", "programming_notes": "xvcvdpsxds rounds using Round towards Zero rounding mode. For other rounding modes, software must use a Round to Double-Precision Integer instruction that corresponds to the desired rounding mode.", "page_found": "Page 871 - 872", "example": "xvcvdpsxds vs1, vs3" }, { "mnemonic": "xvcvdpuxds", "architecture": "PowerISA", "full_name": "Vector Convert Double-Precision to Unsigned Doubleword with Round to Zero", "summary": "Converts double-precision floating-point values in a vector to unsigned doublewords using round towards zero.", "syntax": "xvcvdpuxds XT, XB", "encoding": { "format": "XX2-form", "binary_pattern": "60 | XT | / | XB | 456 | BX | TX", "hex_opcode": "0xF0000720", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "0", "clean": "0" }, { "raw": "XB", "clean": "XB" }, { "raw": "456", "clean": "456" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:29 | 30 | 31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XB", "desc": "Source" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" } ], "extension": "VSX", "description": "This instruction converts each element of the source vector (VSR[XB]) from double-precision floating-point format to an unsigned 64-bit integer, rounding towards zero. The result is stored in the corresponding element of the target vector (VSR[XT]). If any element results in a NaN or SNaN, VXSNAN and VXCVI are set accordingly.", "pseudocode": "for i = 0 to 1 do\n src <- VSR[XB][i]\n if src is a QNaN then\n T(Nmin), fx(VXCVI)\n if FPSCR.VXCVI=0 and MSR.FE0!=ignore-exception-mode then error()\n else if src is a SNaN then\n T(Nmin), fx(VXCVI), fx(VXSNAN)\n if FPSCR.VXSNAN=0 and MSR.FE1!=ignore-exception-mode then error()\n else if src ≤ Nmin-1 then\n T(Nmin), fx(VXCVI)\n if FPSCR.VXCVI=0 and MSR.FE0!=ignore-exception-mode then error()\n else if Nmin-1 < src < Nmin then\n if FPSCR.VE=0 then\n T(Nmin), fx(XX)\n if FPSCR.XX=0 and MSR.FE1!=ignore-exception-mode then error()\n else\n fx(XX), error()\n else if src = Nmin then\n T(Nmin)\n else if Nmin < src < Nmax then\n if FPSCR.VE=0 then\n T(f2i(trunc(src))), fx(XX)\n if FPSCR.XX=0 and MSR.FE1!=ignore-exception-mode then error()\n else\n fx(XX), error()\n else if src = Nmax then\n T(Nmax)\n else if Nmax < src < Nmax+1 then\n if FPSCR.VE=0 then\n T(Nmax), fx(XX)\n if FPSCR.XX=0 and MSR.FE1!=ignore-exception-mode then error()\n else\n fx(XX), error()\n else if src ≥ Nmax+1 then\n T(Nmin), fx(VXCVI)\n if FPSCR.VXCVI=0 and MSR.FE0!=ignore-exception-mode then error()\n end if\nend for", "special_registers": "FPSCR, VXSNAN, VXCVI, XX", "programming_notes": "xvcvdpuxds rounds using Round towards Zero rounding mode. For other rounding modes, software must use a Round to Double-Precision Integer instruction that corresponds to the desired rounding mode.", "page_found": "Page 875 - 876", "example": "xvcvdpuxds vs1, vs3" }, { "mnemonic": "xvcvspsxds", "architecture": "PowerISA", "full_name": "Vector Convert with round to zero Single-Precision to Signed Doubleword format XX2-form", "summary": "Converts single-precision floating-point values in a vector to signed doublewords, rounding towards zero.", "syntax": "xvcvspsxds XT, XB", "encoding": { "format": "XX2-form", "binary_pattern": "110000 | T | B | 000000 | 000000 | 000000 | BX | TX", "hex_opcode": "0xF0000660", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "0", "clean": "0" }, { "raw": "XB", "clean": "XB" }, { "raw": "408", "clean": "408" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XB", "desc": "Source" } ], "extension": "VSX", "description": "Converts single-precision floating-point values in VSR[XB] to signed 64-bit integer format (doubleword) and places the results in VSR[XT], rounding towards zero (truncation). Only the first two single-precision elements are converted; results are placed in the two doubleword elements of the target.", "pseudocode": "VSR[XT].element[0] ← ConvertSP_to_SXD_Truncate(VSR[XB].element[0])\nVSR[XT].element[1] ← ConvertSP_to_SXD_Truncate(VSR[XB].element[1])", "special_registers": "FPSCR, VXSNAN, VXCVI, XX", "programming_notes": "xvcvspsxds rounds using Round towards Zero rounding mode. For other rounding modes, software must use a Round to Single-Precision Integer instruction that corresponds to the desired rounding mode, including xvrspic which uses the rounding mode specified by RN.", "page_found": "Page 879 - 880", "example": "xvcvspsxds vs1, vs3" }, { "mnemonic": "xvcvsxwsp", "architecture": "PowerISA", "full_name": "VSX Vector Convert with round Signed Word to Single-Precision format", "summary": "Converts a signed integer in each word of the source vector to single-precision floating-point and rounds it.", "syntax": "xvcvsxwsp XT, XB", "encoding": { "format": "XX2-form", "binary_pattern": "60 | XT | 0 | XB | 168", "hex_opcode": "0xF00002E0", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "0", "clean": "0" }, { "raw": "XB", "clean": "XB" }, { "raw": "168", "clean": "168" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XB", "desc": "Source" } ], "extension": "VSX", "description": "For xvcvsxwsp, each word element of VSR[XB] is converted from a signed integer to an unbounded-precision floating-point value, rounded to single-precision using the rounding mode specified by RN, and placed into the corresponding word element of VSR[XT].", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\n\nex_flag ←0b0\n\ndo i = 0 to 3\n reset_xflags()\n\n src ←bfp_CONVERT_FROM_SI32(VSR[32×BX+B].word[i])\n rnd ←bfp_ROUND_TO_BFP32(FPSCR.RN,src)\n\n vresult.word[i] ←bfp32_CONVERT_FROM_BFP(rnd)\n\n if xx_flag=1 then SetFX(FPSCR.XX)\n ex_flag ←ex_flag | (FPSCR.XE & xx_flag)\nend\n\nif ex_flag=0 then VSR[32×TX+T] ←vresult", "special_registers": "FPSCR.FX, FPSCR.XX", "page_found": "Page 896 - 897", "programming_notes": "This instruction is commonly used for converting signed integer values to single-precision floating-point numbers in vector operations. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking and setting MSR.VSX if necessary. Be aware of rounding modes specified by FPSCR.RN, as they can affect the precision of the conversion. Handle exceptions properly by checking FPSCR.XX and FPSCR.XE after execution.", "example": "xvcvsxwsp vs1, vs3" }, { "mnemonic": "xvcvuxwsp", "architecture": "PowerISA", "full_name": "VSX Vector Convert Unsigned Word to Single", "summary": "Converts four 32-bit unsigned integers to four floats.", "syntax": "xvcvuxwsp XT, XB", "encoding": { "format": "XX2-form", "binary_pattern": "60 | XT | 0 | XB | 136", "hex_opcode": "0xF00002A0", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "0", "clean": "0" }, { "raw": "XB", "clean": "XB" }, { "raw": "136", "clean": "136" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XB", "desc": "Source" } ], "extension": "VSX", "description": "Converts four 32-bit unsigned integer values in VSR[XB] to four single-precision floating-point results and places them in VSR[XT]. Each unsigned word element is converted to the corresponding single-precision element. Rounding is performed according to the current rounding mode in FPSCR.", "pseudocode": "VSR[XT].element[0] ← ConvertUW_to_SP(VSR[XB].element[0])\nVSR[XT].element[1] ← ConvertUW_to_SP(VSR[XB].element[1])\nVSR[XT].element[2] ← ConvertUW_to_SP(VSR[XB].element[2])\nVSR[XT].element[3] ← ConvertUW_to_SP(VSR[XB].element[3])", "page_found": "Page 897", "special_registers": "FPSCR, MSR", "programming_notes": "This instruction is commonly used for converting unsigned integer data to floating-point format in vector operations. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking and setting MSR.VSX before using this instruction. Be aware of potential exceptions during conversion, as no results will be written to the target register if any trap-enabled exception occurs. The rounding mode is determined by FPSCR.RN, so ensure it's set appropriately for your application.", "example": "xvcvuxwsp vs1, vs3" }, { "mnemonic": "xxspltiw", "architecture": "PowerISA", "full_name": "VSX Vector Splat Immediate Word", "summary": "Spatially duplicates a 32-bit immediate into all 4 words of the target.", "syntax": "xxspltiw XT, IMM", "encoding": { "format": "8RR:D-form", "binary_pattern": "000001 | 01000 | imm[7:0] | VT[4:0]", "hex_opcode": "0x0500000080060000", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "...", "clean": "..." } ], "length": "64", "bit_positions": "0:5 | 6:10 | 11:20 | 21:63" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "IMM", "desc": "32-bit Value" }, { "name": "VT", "desc": "Target Vector Register" }, { "name": "imm", "desc": "Immediate Word Value" } ], "extension": "VSX", "description": "Duplicates a 32-bit immediate value into all four 32-bit word elements of VSR[XT]. This is a VSX vector splat immediate instruction that fills the entire 128-bit register with copies of the 32-bit immediate. No floating-point status updates occur.", "pseudocode": "imm32 ← sign_extend(IMM)\nVSR[XT].element[0] ← imm32\nVSR[XT].element[1] ← imm32\nVSR[XT].element[2] ← imm32\nVSR[XT].element[3] ← imm32", "page_found": "Page 1493 - 1494", "programming_notes": "The xxspltiw instruction is commonly used to initialize a VSX vector with a repeated immediate word value. Ensure that the 'imm' field is within the valid range of a 32-bit signed integer to avoid unexpected behavior. This instruction operates at user privilege level and does not generate exceptions under normal circumstances.", "example": "xxspltiw vs1, 1" }, { "mnemonic": "xxspltidp", "architecture": "PowerISA", "full_name": "VSX Vector Splat Immediate Double-Precision", "summary": "Spatially duplicates a 32-bit immediate (converted to double) into both double elements.", "syntax": "xxspltidp XT, IMM", "encoding": { "format": "8RR:D-form", "binary_pattern": "1 | 0 | 0 | // | // | imm0", "hex_opcode": "0x0500000080040000", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "...", "clean": "..." } ], "length": "64", "bit_positions": "0:5 | 6:7 | 8:11 | 12:13 | 14:15 | 16:63" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "IMM", "desc": "32-bit Value" }, { "name": "IMM32", "desc": "Immediate Value" } ], "extension": "VSX", "description": "The instruction splats the double-precision value formed by concatenating imm0 and imm1 into each doubleword element of VSR[XT].", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nIMM32 ←imm0<<16 | imm1\nVSR[32×TX+T].dword[0] ←bfp64_CONVERT_FROM_BFP(IMM32)\nVSR[32×TX+T].dword[1] ←bfp64_CONVERT_FROM_BFP(IMM32)", "page_found": "Page 955 - 956", "special_registers": "MSR", "programming_notes": "This instruction is used to replicate a double-precision floating-point value across all elements of a VSX vector register. Ensure that the VSX facility is enabled in the MSR register; otherwise, it will raise an exception. The immediate values imm0 and imm1 are concatenated to form a 32-bit integer, which is then converted to a double-precision float and replicated across the vector. Be cautious of alignment requirements for the target vector register.", "example": "xxspltidp vs1, 1" }, { "mnemonic": "xxmrghd", "architecture": "PowerISA", "full_name": "VSX Vector Merge High Doubleword", "summary": "Merges high doublewords from XA and XB.", "syntax": "xxmrghd XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "60 | XT | XA | XB | 144", "hex_opcode": "0xF0000050", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "144", "clean": "144" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "Merges the two high-order doubleword elements from VSR[XA] and VSR[XB] into VSR[XT]. Element 0 of XA is placed in element 0 of XT, and element 0 of XB is placed in element 1 of XT. This is a vector permutation instruction with no floating-point status updates.", "pseudocode": "VSR[XT].element[0] ← VSR[XA].element[0]\nVSR[XT].element[1] ← VSR[XB].element[0]", "page_found": "Page 958", "special_registers": "MSR", "programming_notes": "The xxmrghd instruction is used to merge the high doublewords from two source vector registers into a target vector register. Ensure that the VSX facility is enabled by checking and setting the appropriate bit in the MSR register. Be cautious with the DM bits, as they determine which source doubleword is merged into the target register. This instruction operates at the user privilege level and will raise an exception if the VSX facility is not available.", "example": "xxmrghd vs1, vs2, vs3" }, { "mnemonic": "xxmrgld", "architecture": "PowerISA", "full_name": "VSX Vector Merge Low Doubleword", "summary": "Merges low doublewords from XA and XB.", "syntax": "xxmrgld XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "60 | XT | XA | XB | 208", "hex_opcode": "0xF0000050", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "208", "clean": "208" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "Merges the low (rightmost) doubleword from XA and the low doubleword from XB into the target register XT, placing XA's low doubleword in the high position and XB's low doubleword in the low position. This is a VSX instruction that operates on 128-bit vector registers and does not affect any condition or status flags.", "pseudocode": "XT[0:63] ← XB[64:127]\nXT[64:127] ← XA[64:127]", "page_found": "Page 958", "special_registers": "MSR", "programming_notes": "The xxmrgld instruction is used to merge the low doublewords of two VSX registers into a target register. Ensure that the VSX facility is enabled by checking and setting the appropriate bit in the MSR register. Be cautious with the DM bits as they determine which doubleword from the source registers is placed into the target register's second doubleword position.", "example": "xxmrgld vs1, vs2, vs3" }, { "mnemonic": "xxswapd", "architecture": "PowerISA", "full_name": "VSX Vector Swap Doubleword", "summary": "Swaps the two doublewords in the register.", "syntax": "xxswapd XT, XB", "encoding": { "format": "XX2-form", "binary_pattern": "60 | XT | 0 | XB | 250", "hex_opcode": "0xF00000FA", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "0", "clean": "0" }, { "raw": "XB", "clean": "XB" }, { "raw": "250", "clean": "250" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XB", "desc": "Source" } ], "extension": "VSX", "description": "Swaps the two doublewords within the XB register and stores the result in XT. The high doubleword becomes the low doubleword and vice versa. This is a VSX instruction that does not affect condition or status flags.", "pseudocode": "XT[0:63] ← XB[64:127]\nXT[64:127] ← XB[0:63]", "page_found": "Page 958", "special_registers": "MSR", "programming_notes": "The xxswapd instruction swaps doubleword elements between two VSX registers based on the DM bit setting. Ensure that the VSX facility is enabled in the MSR register to avoid a VSX_Unavailable exception. This instruction operates at user privilege level and does not require specific alignment of data.", "example": "xxswapd vs1, vs3" }, { "mnemonic": "xxsel", "architecture": "PowerISA", "full_name": "VSX Vector Select", "summary": "Selects elements from two source vectors based on a mask vector.", "syntax": "xxsel XT, XA, XB, XC", "encoding": { "format": "XX4-form", "binary_pattern": "60 | XT | XA | XB | XC | 3", "hex_opcode": "0xF0000030", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "XC", "clean": "XC" }, { "raw": "3", "clean": "3" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "True Src" }, { "name": "XB", "desc": "False Src" }, { "name": "XC", "desc": "Mask" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "VRC", "desc": "Source Vector Register" } ], "extension": "VSX", "description": "Selects bits from XA or XB for each bit position based on the corresponding bit in the mask register XC. Where XC has a 1 bit, the result takes the bit from XA; where XC has a 0 bit, the result takes the bit from XB. This is a VSX instruction with no effect on condition or status flags.", "pseudocode": "for i in 0 to 127 do\n if XC[i] = 1 then\n XT[i] ← XA[i]\n else\n XT[i] ← XB[i]", "page_found": "Page 944 - 945", "special_registers": "MSR", "programming_notes": "The xxsel instruction is commonly used for conditional vector selection based on a mask. Ensure that the VSX feature is enabled in the MSR register to avoid an exception. The source and destination vectors must be properly aligned, typically requiring 16-byte alignment for optimal performance.", "example": "xxsel vs1, vs2, vs3, vs4" }, { "mnemonic": "xxlor", "architecture": "PowerISA", "full_name": "VSX Vector Logical OR", "summary": "Bitwise OR.", "syntax": "xxlor XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "60 | XT | XA | XB | 448", "hex_opcode": "0xF0000490", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "448", "clean": "448" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "Performs a bitwise logical OR of the contents of XA and XB, storing the result in XT. This is a VSX instruction that does not affect condition or status flags.", "pseudocode": "XT ← XA | XB", "page_found": "Page 944", "special_registers": "MSR", "programming_notes": "The xxlor instruction is used to perform a bitwise OR operation on two VSX registers. Ensure that the VSX facility is enabled by checking and setting the MSR.VSX bit; otherwise, a VSX_Unavailable exception will be raised. This instruction operates on 128-bit vectors and requires proper alignment of the input and output registers.", "example": "xxlor vs1, vs2, vs3" }, { "mnemonic": "xxlxor", "architecture": "PowerISA", "full_name": "VSX Vector Logical XOR", "summary": "Bitwise XOR.", "syntax": "xxlxor XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "60 | XT | XA | XB | 456", "hex_opcode": "0xF00004D0", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "456", "clean": "456" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "Performs a bitwise logical XOR of the contents of XA and XB, storing the result in XT. This is a VSX instruction that does not affect condition or status flags.", "pseudocode": "XT ← XA XOR XB", "page_found": "Page 944", "special_registers": "MSR", "programming_notes": "The xxlxor instruction requires the VSX facility to be enabled; otherwise, it will raise an exception. Ensure that the VSX bit in the MSR register is set before using this instruction. The operation is performed on 128-bit vector registers, so ensure proper alignment and that the input registers contain valid data for accurate results.", "example": "xxlxor vs1, vs2, vs3" }, { "mnemonic": "xxland", "architecture": "PowerISA", "full_name": "VSX Vector Logical AND", "summary": "Performs a bitwise AND operation on the contents of two vector registers and stores the result in another vector register.", "syntax": "xxland XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "T | A | B | 130 | AX | BX | TX", "hex_opcode": "0xF0000410", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "440", "clean": "440" } ], "length": "32", "bit_positions": "6:10 | 11:15 | 16:20 | 21:28 | 29 | 30 | 31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "The contents of VSR[XA] are ANDed with the contents of VSR[XB] and the result is placed into VSR[XT].", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nVSR[32×TX+T] ← VSR[32×AX+A] & VSR[32×BX+B]", "page_found": "Page 942 - 943", "special_registers": "MSR", "programming_notes": "Ensure that the VSX (Vector Scalar Extensions) is enabled in the MSR register before using this instruction. The operation is performed on 128-bit vector registers, so both input and output must be properly aligned. This instruction operates at a high performance for bitwise operations on vectors.", "example": "xxland vs1, vs2, vs3" }, { "mnemonic": "xxlnor", "architecture": "PowerISA", "full_name": "VSX Vector Logical NOR", "summary": "Performs a logical NOR operation on the contents of two VSX registers and stores the result in another VSX register.", "syntax": "xxlnor XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "18 | T | A | B | AX | BX | TX", "hex_opcode": "0xF0000510", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "464", "clean": "464" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "The contents of VSR[XA] are ORed with the contents of VSR[XB], then the complemented result is placed into VSR[XT].", "pseudocode": "if MSR.VSX=0 then\n VSX_Unavailable()\nXT <- ¬(XA | XB)", "page_found": "Page 943 - 944", "special_registers": "MSR", "programming_notes": "The xxlnor instruction performs a logical NOR operation between two vector registers and stores the result in another. Ensure that the VSX (Vector Scalar Extensions) is enabled by checking and setting the MSR.VSX bit; otherwise, handle the VSX_Unavailable exception. This instruction operates on 128-bit vectors and requires proper alignment of the input and output registers.", "example": "xxlnor vs1, vs2, vs3" }, { "mnemonic": "vmulouw", "architecture": "PowerISA", "full_name": "Vector Multiply Odd Unsigned Word", "summary": "Multiplies the 1st and 3rd words of the source vectors to produce two 64-bit results.", "syntax": "vmulouw vD, vA, vB", "encoding": { "format": "VA-form", "binary_pattern": "4 | vD | vA | vB | 128", "hex_opcode": "0x10000088", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "128", "clean": "128" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Source A" }, { "name": "vB", "desc": "Source B" } ], "pseudocode": "vD[0:63] ← (vA[32:63] unsigned) × (vB[32:63] unsigned)\nvD[64:127] ← (vA[96:127] unsigned) × (vB[96:127] unsigned)", "example": "vmulouw v1, v2, v3", "example_note": "Widening multiply (32x32->64).", "extension": "VMX (AltiVec)", "description": "Multiplies the unsigned 32-bit words at positions 1 and 3 of vA by the corresponding words in vB, producing two unsigned 64-bit results stored in vD. This is a VMX (AltiVec) instruction that does not affect condition or status flags.", "page_found": "Page 370", "programming_notes": "This instruction is useful for performing element-wise multiplication of unsigned integers stored in odd-numbered positions of two vectors. Ensure that the input vectors are properly aligned to avoid alignment faults. The result is a vector with doubleword elements, so be mindful of potential overflow if the product exceeds 64 bits." }, { "mnemonic": "vmulosw", "architecture": "PowerISA", "full_name": "Vector Multiply Odd Signed Word", "summary": "Multiplies odd words (1,3) to 64-bit signed result.", "syntax": "vmulosw vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 392", "hex_opcode": "0x10000188", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "392", "clean": "392" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Multiplies the signed 32-bit words at positions 1 and 3 of vA by the corresponding words in vB, producing two signed 64-bit results stored in vD. This is a VMX (AltiVec) instruction that does not affect condition or status flags.", "pseudocode": "vD[0:63] ← (vA[32:63] signed) × (vB[32:63] signed)\nvD[64:127] ← (vA[96:127] signed) × (vB[96:127] signed)", "page_found": "Page 369", "special_registers": "MSR", "programming_notes": "The vmulosw instruction is used for multiplying signed integers located in the odd word elements of two vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The result is stored in doubleword elements of the destination register, and developers should handle potential overflow by checking the sign extension of the products.", "example": "vmulosw vd, va, vb" }, { "mnemonic": "vmuleuw", "architecture": "PowerISA", "full_name": "Vector Multiply Even Unsigned Word", "summary": "Multiplies the even-numbered words of two vector registers and places the results in a destination vector register.", "syntax": "vmuleuw vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 136", "hex_opcode": "0x10000288", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "136", "clean": "136" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vmuleuw, each pair of even-numbered words from VSR[VRA+32] and VSR[VRB+32] are multiplied, and the results are placed into VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 1\n src1 ←EXTZ(VSR[VRA+32].word[2×i])\n src2 ←EXTZ(VSR[VRB+32].word[2×i])\n VSR[VRT+32].dword[i] ←CHOP64(src1 × src2)\nend", "page_found": "Page 369 - 370", "special_registers": "MSR", "programming_notes": "This instruction multiplies even-numbered words from two vector registers and stores the results in another register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. Be cautious of overflow, as the multiplication result is truncated to 64 bits before storage.", "example": "vmuleuw vd, va, vb" }, { "mnemonic": "vmulesw", "architecture": "PowerISA", "full_name": "Vector Multiply Even Signed Word", "summary": "Multiplies even-indexed signed words from two vector registers and stores the results in a destination vector register.", "syntax": "vmulesw vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 392", "hex_opcode": "0x10000388", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "392", "clean": "392" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vmulesw, each pair of even-indexed signed words from VSR[VRA+32] and VSR[VRB+32] are multiplied, and the 64-bit products are stored in VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 1\n src1 ←EXTS(VSR[VRA+32].word[2×i])\n src2 ←EXTS(VSR[VRB+32].word[2×i])\n VSR[VRT+32].dword[i] ←CHOP64(src1 × src2)\nend", "page_found": "Page 368 - 369", "special_registers": "MSR", "programming_notes": "This instruction multiplies even-indexed signed words from two vector registers and stores the 64-bit products in another register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. Be cautious of overflow, as the multiplication results are truncated to 64 bits.", "example": "vmulesw vd, va, vb" }, { "mnemonic": "vmsumubm", "architecture": "PowerISA", "full_name": "Vector Multiply-Sum Unsigned Byte Modulo", "summary": "Multiplies bytes and sums adjacent results into words.", "syntax": "vmsumubm vD, vA, vB, vC", "encoding": { "format": "VA-form", "binary_pattern": "4 | vD | vA | vB | vC | 36", "hex_opcode": "0x10000024", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "vC", "clean": "vC" }, { "raw": "36", "clean": "36" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "vC", "desc": "Accumulator" } ], "extension": "VMX (AltiVec)", "description": "Multiplies each unsigned byte in vA by the corresponding byte in vB, then sums the products of adjacent byte pairs to produce four unsigned 32-bit word results. The results are added to the four words in the accumulator vC and stored in vD. This is a VMX (AltiVec) instruction that does not affect condition or status flags.", "pseudocode": "vD[0:31] ← (vA[0:7] × vB[0:7]) + (vA[8:15] × vB[8:15]) + vC[0:31]\nvD[32:63] ← (vA[16:23] × vB[16:23]) + (vA[24:31] × vB[24:31]) + vC[32:63]\nvD[64:95] ← (vA[32:39] × vB[32:39]) + (vA[40:47] × vB[40:47]) + vC[64:95]\nvD[96:127] ← (vA[48:55] × vB[48:55]) + (vA[56:63] × vB[56:63]) + vC[96:127]", "special_registers": "MSR", "programming_notes": "This instruction is commonly used for performing efficient vectorized operations on unsigned byte data. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation processes 8 bytes per iteration, multiplying corresponding elements and adding to the third source vector's word element, storing the result in the destination vector. Be cautious of overflow as only the low-order 16 bits are stored.", "example": "vmsumubm vd, va, vb, vc" }, { "mnemonic": "vmsumshm", "architecture": "PowerISA", "full_name": "Vector Multiply-Sum Signed Halfword Modulo", "summary": "Multiplies halfwords and sums adjacent results into words.", "syntax": "vmsumshm vD, vA, vB, vC", "encoding": { "format": "VA-form", "binary_pattern": "4 | VRT | VRA | VRB | VRC | 40", "hex_opcode": "0x10000028", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "vC", "clean": "vC" }, { "raw": "40", "clean": "40" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "vC", "desc": "Accumulator" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "VRC", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "special_registers": "VSCR", "page_found": "Page 1332 - 1333", "description": "Multiplies four pairs of signed halfword elements from vA and vB, then sums the adjacent pairs of products modulo 2^32 and adds the corresponding word element from vC (accumulator), storing the result in vD. This instruction operates on Classic VMX (AltiVec) and does not set any condition flags.", "pseudocode": "for i in 0 to 1 do\n prod_hi ← vA[i*2] × vB[i*2]\n prod_lo ← vA[i*2+1] × vB[i*2+1]\n vD[i] ← (prod_hi + prod_lo + vC[i]) mod 2^32\nendfor", "programming_notes": "This instruction is useful for performing vectorized multiply-sum operations on signed halfwords, ensuring results are within the range of a 16-bit signed integer by applying modulo arithmetic. Ensure that input vectors and accumulator are properly aligned to avoid performance penalties. This operation does not require any special privileges but can generate exceptions if input data exceeds expected ranges.", "example": "vmsumshm vd, va, vb, vc" }, { "mnemonic": "vmsumshs", "architecture": "PowerISA", "full_name": "Vector Multiply-Sum Signed Halfword Saturate", "summary": "Performs a vector multiply-sum operation on signed halfwords and saturates the result.", "syntax": "vmsumshs vD, vA, vB, vC", "encoding": { "format": "VA-form", "binary_pattern": "4 | vD | vA | vB | vC | 41", "hex_opcode": "0x10000029", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "vC", "clean": "vC" }, { "raw": "41", "clean": "41" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "vC", "desc": "Accumulator" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "VRC", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vmsumshs, each element in VRA and VRB is multiplied by corresponding elements in VRC. The results are summed and saturated if necessary.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n temp ←EXTS(VSR[VRC+32].word[i])\n do j = 0 to 1\n src1 ←EXTS(VSR[VRA+32].word[i].hword[j])\n src2 ←EXTS(VSR[VRB+32].word[i].hword[j])\n temp ←temp + (src1 × src2)\n end\n VSR[VRT+32].word[i] ←si32_CLAMP(temp)\n VSCR.SAT ←sat_flag\nend", "special_registers": "VSCR", "page_found": "Page 379 - 380", "programming_notes": "vmsumshs is used for vectorized operations involving signed halfword multiplication and summation. Ensure that the Vector Status and Control Register (VSCR) is properly managed, especially when handling saturation flags. This instruction operates at the user privilege level and will raise an exception if the vector facility is not enabled in the Machine State Register (MSR).", "example": "vmsumshs vd, va, vb, vc" }, { "mnemonic": "vsum4ubs", "architecture": "PowerISA", "full_name": "Vector Sum-across Partial (1/4) Unsigned Byte Saturate", "summary": "Sums the unsigned byte elements of two vector registers and saturates the result.", "syntax": "vsum4ubs vD, vA, vB", "encoding": { "format": "VA-form", "binary_pattern": "4 | vD | vA | vB | 1632", "hex_opcode": "0x10000608", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1632", "clean": "1632" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Accumulator" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vsum4ubs, the sum of the unsigned integer values in the four byte elements contained in each word element of VSR[VRA+32] is added to the unsigned integer value in the corresponding word element of VSR[VRB+32]. If the intermediate result exceeds 2^32 - 1, it saturates to 2^32 - 1 and sets the SAT flag.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n temp ← EXTZ(VSR[VRB+32].word[i])\n do j = 0 to 3\n temp ← temp + EXTZ(VSR[VRA+32].word[i].byte[j])\n end\n VSR[VRT+32].word[i] ← ui32_CLAMP(temp)\n VSCR.SAT ← sat_flag\nend", "special_registers": "VSCR.SAT", "page_found": "Page 395 - 396", "programming_notes": "vsum4ubs is commonly used for accumulating sums of byte elements within vector registers, with saturation to prevent overflow. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation processes four bytes per word, and results are clamped to 32-bit unsigned integers, setting the VSCR.SAT flag if saturation occurs.", "example": "vsum4ubs vd, va, vb" }, { "mnemonic": "vsum4sbs", "architecture": "PowerISA", "full_name": "Vector Sum-across Partial (1/4) Signed Byte Saturate", "summary": "Adds the contents of four signed byte elements from two vector registers and saturates the result.", "syntax": "vsum4sbs vD, vA, vB", "encoding": { "format": "VA-form", "binary_pattern": "4 | vD | vA | vB | 1888", "hex_opcode": "0x10000708", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1888", "clean": "1888" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Accumulator" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vsum4sbs, the sum of the signed integer values in the four byte elements contained in word element i of VSR[VRA+32] is added to the signed integer value in word element i of VSR[VRB+32]. If the intermediate result is greater than 2^31-1 or less than -2^31, the result saturates and SAT is set to 1.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n temp ←EXTS(VSR[VRB+32].word[i])\n do j = 0 to 3\n temp ←temp + EXTS(VSR[VRA+32].word[i].byte[j])\n end\n VSR[VRT+32].word[i] ←si32_CLAMP(temp)\n VSCR.SAT ←sat_flag\nend", "special_registers": "VSCR.SAT", "page_found": "Page 394 - 395", "programming_notes": "vsum4sbs is useful for accumulating sums of byte elements within words, with saturation handling. Ensure vectors are properly aligned and check VSCR.SAT after execution to handle overflow cases. This instruction operates at the user privilege level.", "example": "vsum4sbs vd, va, vb" }, { "mnemonic": "vsum4shs", "architecture": "PowerISA", "full_name": "Vector Sum-across Partial (1/4) Signed Halfword Saturate", "summary": "Sums every 2 halfwords into a word.", "syntax": "vsum4shs vD, vA, vB", "encoding": { "format": "VA-form", "binary_pattern": "4 | vD | vA | vB | 1608", "hex_opcode": "0x10000648", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1608", "clean": "1608" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Accumulator" } ], "extension": "VMX (AltiVec)", "description": "Sums pairs of signed halfword elements from vA and accumulates into words in vB (accumulator), storing saturated results in vD. The instruction processes 2 halfword pairs per word, setting the saturation bit (VSCR[SAT]) if any result overflows. This is a Classic VMX (AltiVec) instruction.", "pseudocode": "for i in 0 to 3 do\n sum ← vA[i*2] + vA[i*2+1] + vB[i]\n vD[i] ← SATURATE_SIGNED_WORD(sum)\n if overflow then VSCR[SAT] ← 1\nendfor", "page_found": "Page 395", "special_registers": "MSR, VSCR", "programming_notes": "The vsum4shs instruction is commonly used for performing saturated addition of signed halfwords within vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. Be cautious with saturation handling as it can affect the results if intermediate sums exceed 32-bit integer limits.", "example": "vsum4shs vd, va, vb" }, { "mnemonic": "vsum2sws", "architecture": "PowerISA", "full_name": "Vector Sum-across Partial (1/2) Signed Word Saturate", "summary": "Adds the contents of two vector registers and updates the saturation flag.", "syntax": "vsum2sws vD, vA, vB", "encoding": { "format": "VA-form", "binary_pattern": "4 | vD | vA | vB | 1672", "hex_opcode": "0x10000688", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1672", "clean": "1672" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Accumulator" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "Sums pairs of signed word elements from vA and accumulates into doublewords conceptually, storing the lower 32 bits of saturated results in alternating word positions of vD. The instruction sets the saturation bit (VSCR[SAT]) if any result overflows a signed 32-bit word. This is a Classic VMX (AltiVec) instruction.", "pseudocode": "for i in 0 to 1 do\n sum ← sign_extend_64(vA[i*2]) + sign_extend_64(vA[i*2+1]) + sign_extend_64(vB[i*2])\n vD[i*2] ← SATURATE_SIGNED_WORD(sum)\n if overflow then VSCR[SAT] ← 1\nendfor", "special_registers": "VSCR.SAT", "page_found": "Page 393 - 394", "programming_notes": "This instruction is useful for performing saturated addition of word elements in vector registers. Ensure that the VSCR.SAT flag is checked after execution to handle saturation cases. The instruction operates on 32-bit signed integers and requires the vector facility to be enabled (MSR.VEC=1).", "example": "vsum2sws vd, va, vb" }, { "mnemonic": "vsumsws", "architecture": "PowerISA", "full_name": "Vector Sum-across Signed Word Saturate", "summary": "Adds the contents of four word elements of one vector register to a single word element of another vector register and saturates the result.", "syntax": "vsumsws vD, vA, vB", "encoding": { "format": "VA-form", "binary_pattern": "000100 | vD | vA | vB | 11110 | 001000", "hex_opcode": "0x10000788", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1928", "clean": "1928" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Accumulator" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "VA", "desc": "Source Vector Register" }, { "name": "VB", "desc": "Source Vector Register" }, { "name": "VC", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "The sum of the signed integer values in the four word elements of VSR[VRA+32] is added to the signed integer value in the word element 3 of VSR[VRB+32]. The low-order 32 bits of the result are placed into word element 3 of VSR[VRT+32], and the high-order 96 bits are set to zero. If the intermediate result is greater than 2^31 - 1, it saturates to 2^31 - 1; if less than -2^31, it saturates to -2^31.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ntemp ←EXTS(VSR[VRB+32].word[3])\ndo i = 0 to 3\n temp ←temp + EXTS(VSR[VRA+32].word[i])\nend\nVSR[VRT+32].word[0] ←0x0000_0000\nVSR[VRT+32].word[1] ←0x0000_0000\nVSR[VRT+32].word[2] ←0x0000_0000\nVSR[VRT+32].word[3] ←si32_CLAMP(temp)\nVSCR.SAT ←sat_flag", "special_registers": "VSCR", "page_found": "Page 392 - 393", "programming_notes": "This instruction is useful for accumulating sums of signed integers with saturation, preventing overflow. Ensure that the vector registers are properly aligned and that the VEC bit in the MSR is set to 1. Be aware of the saturation behavior; if the sum exceeds the 32-bit signed integer range, it will be clamped to the maximum or minimum value. The result is stored only in the fourth word element of the destination register, with the other elements zeroed out.", "example": "vsumsws vd, va, vb" }, { "mnemonic": "vaddfp", "architecture": "PowerISA", "full_name": "Vector Add Floating-Point", "summary": "Adds the contents of two vector registers and places the result in another vector register.", "syntax": "vaddfp vD, vA, vB", "encoding": { "format": "VA-form", "binary_pattern": "4 | vD | vA | vB | 10", "hex_opcode": "0x1000000A", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "10", "clean": "10" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vaddfp, each element of the source vectors VRA and VRB is added to produce corresponding elements in the destination vector VRT.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n src1 ← VSR[VRA+32].word[i]\n src2 ← VSR[VRB+32].word[i]\n VSR[VRT+32].word[i] ← bfp32_ADD(src1,src2)\nend", "page_found": "Page 446 - 447", "special_registers": "MSR", "programming_notes": "The vaddfp instruction adds corresponding elements of two source vectors and stores the results in a destination vector. Ensure that the Vector Facility is enabled by setting MSR.VEC to 1; otherwise, a Vector_Unavailable exception will be raised. This instruction operates on single-precision floating-point numbers and processes four elements per operation.", "example": "vaddfp vd, va, vb" }, { "mnemonic": "vsubfp", "architecture": "PowerISA", "full_name": "Vector Subtract Floating-Point", "summary": "Subtracts four single-precision floats (Classic VMX).", "syntax": "vsubfp vD, vA, vB", "encoding": { "format": "VA-form", "binary_pattern": "4 | vD | vA | vB | 74", "hex_opcode": "0x1000004A", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "74", "clean": "74" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Subtracts four single-precision floating-point elements in vB from the corresponding elements in vA, storing the IEEE 754 results in vD. No condition flags are set by this instruction. This is a Classic VMX (AltiVec) floating-point operation.", "pseudocode": "for i in 0 to 3 do\n vD[i] ← vA[i] - vB[i] (IEEE 754 single precision)\nendfor", "page_found": "Page 447", "special_registers": "MSR", "programming_notes": "The vsubfp instruction is used for vectorized subtraction of single-precision floating-point numbers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation processes four elements at a time, so ensure that the input vectors are properly aligned and contain valid floating-point data to avoid unexpected results.", "example": "vsubfp vd, va, vb" }, { "mnemonic": "vctuxs", "architecture": "PowerISA", "full_name": "Vector Convert to Unsigned Fixed-Point Word Saturate", "summary": "Converts 4 floats to 4 unsigned 32-bit integers.", "syntax": "vctuxs vD, vB, UIM", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | UIM | vB | 906", "hex_opcode": "0x1000038A", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "UIM", "clean": "UIM" }, { "raw": "vB", "clean": "vB" }, { "raw": "906", "clean": "906" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "UIM", "desc": "Fraction bits" } ], "extension": "VMX (AltiVec)", "description": "Converts four single-precision floating-point elements in vB to unsigned 32-bit fixed-point integers with UIM fractional bits, saturating to the unsigned 32-bit range and storing results in vD. Sets the saturation bit (VSCR[SAT]) if any conversion saturates. This is a Classic VMX (AltiVec) instruction.", "pseudocode": "scale ← 2^UIM\nfor i in 0 to 3 do\n converted ← round(vB[i] × scale)\n vD[i] ← SATURATE_UNSIGNED_WORD(converted)\n if saturated then VSCR[SAT] ← 1\nendfor", "page_found": "Page 450", "special_registers": "MSR", "programming_notes": "The vctuxs instruction converts floating-point elements to unsigned fixed-point words with saturation. Ensure the vector facility is enabled by checking and setting MSR.VEC. Handle exceptions for invalid operations or overflow carefully. The conversion respects the rounding mode specified by UIM, so verify its configuration for accurate results.", "example": "vctuxs vd, vb, uim" }, { "mnemonic": "vctsxs", "architecture": "PowerISA", "full_name": "Vector Convert to Signed Fixed-Point Word Saturate", "summary": "Converts a vector of floating-point values to signed fixed-point integers with rounding towards zero and saturation.", "syntax": "vctsxs vD, vB, UIM", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | UIM | vB | 970", "hex_opcode": "0x100003CA", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "UIM", "clean": "UIM" }, { "raw": "vB", "clean": "vB" }, { "raw": "970", "clean": "970" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "UIM", "desc": "Fraction bits" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vctsxs, each element in the source vector VRB is converted to a signed fixed-point integer using the specified scale factor UIM. The result is saturated if it exceeds the range of a 32-bit signed integer.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n src ← VSR[VRB+32].word[i]\n VSR[VRT+32].word[i] ← si32_CONVERT_FROM_BFP32(src, UIM)\nend", "special_registers": "VSCR (SAT)", "extended_mnemonics": [ "vcfpsxws" ], "page_found": "Page 449 - 450", "programming_notes": "The vctsxs instruction converts each element of the source vector to a signed fixed-point integer using the specified scale factor. Ensure that the scale factor is appropriate for your data range to avoid saturation. This instruction operates at user privilege level and will raise an exception if the VEC bit in the MSR register is not set.", "example": "vctsxs vd, vb, uim" }, { "mnemonic": "vcfux", "architecture": "PowerISA", "full_name": "Vector Convert from Unsigned Fixed-Point Word", "summary": "Converts 4 unsigned 32-bit integers to floats.", "syntax": "vcfux vD, vB, UIM", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | UIM | vB | 778", "hex_opcode": "0x1000030A", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "UIM", "clean": "UIM" }, { "raw": "vB", "clean": "vB" }, { "raw": "778", "clean": "778" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "UIM", "desc": "Fraction bits" } ], "extension": "VMX (AltiVec)", "description": "Converts four unsigned 32-bit fixed-point integers in vB (with UIM fractional bits) to single-precision floating-point elements, storing IEEE 754 results in vD. No saturation or condition flags are set. This is a Classic VMX (AltiVec) instruction.", "pseudocode": "scale ← 2^(-UIM)\nfor i in 0 to 3 do\n vD[i] ← unsigned_word_to_float(vB[i]) × scale (IEEE 754)\nendfor", "page_found": "Page 451", "special_registers": "MSR", "programming_notes": "The vcfux instruction is used for converting signed floating-point values to unsigned fixed-point integers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. Be cautious of saturation when results exceed 2^32 - 1.", "example": "vcfux vd, vb, uim" }, { "mnemonic": "vcfsx", "architecture": "PowerISA", "full_name": "Vector Convert from Signed Fixed-Point Word to Single-Precision Floating-Point", "summary": "Converts signed fixed-point values in a vector register to single-precision floating-point values.", "syntax": "vcfsx vD, vB, UIM", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | UIM | vB | 842", "hex_opcode": "0x1000034A", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "UIM", "clean": "UIM" }, { "raw": "vB", "clean": "vB" }, { "raw": "842", "clean": "842" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "UIM", "desc": "Fraction bits" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vcfsx, each word element of the source vector register VRB is converted to a nearest single-precision floating-point value and divided by 2^UIM. The results are stored in the corresponding word elements of the target vector register VRT.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n src ← VSR[VRB+32].word[i]\n VSR[VRT+32].word[i] ← bfp32_CONVERT_FROM_SI32(src, UIM)\nend", "programming_notes": "The fixed-point integers used by the Vector Convert instructions can be interpreted as consisting of 32-UIM integer bits followed by UIM fraction bits.", "extended_mnemonics": [ { "mnemonic": "vcsxwfp", "equivalent_to": "vcfsx VRT,VRB,UIM" } ], "page_found": "Page 450 - 451", "special_registers": "MSR", "example": "vcfsx vd, vb, uim" }, { "mnemonic": "vrfim", "architecture": "PowerISA", "full_name": "Vector Round to Floating-Point Integer towards Minus Infinity", "summary": "Rounds each element of a vector toward negative infinity.", "syntax": "vrfim vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 0 | vB | 714", "hex_opcode": "0x100002CA", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "714", "clean": "714" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vrfim, each single-precision floating-point value in the elements of VSR[VRB+32] is rounded toward negative infinity and placed into the corresponding elements of VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n src ← VSR[VRB+32].word[i]\n VSR[VRT+32].word[i] ← bfp32_ROUND_TO_INTEGER_FLOOR(src)\nend", "page_found": "Page 451 - 452", "special_registers": "MSR", "programming_notes": "This instruction rounds each single-precision floating-point value in the source vector towards negative infinity. Ensure that the Vector Facility is enabled by checking and setting the appropriate bit in the MSR register. Be cautious of potential exceptions if the input values are out of range for integer representation.", "example": "vrfim vd, vb" }, { "mnemonic": "vrfin", "architecture": "PowerISA", "full_name": "Vector Round to Floating-Point Integer Nearest", "summary": "Rounds 4 floats to nearest integer.", "syntax": "vrfin vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 0 | vB | 522", "hex_opcode": "0x1000020A", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "522", "clean": "522" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" } ], "extension": "VMX (AltiVec)", "description": "Rounds four single-precision floating-point elements in vB to the nearest integer value (using round-to-nearest-even), storing IEEE 754 results in vD. No condition flags are set. This is a Classic VMX (AltiVec) instruction.", "pseudocode": "for i in 0 to 3 do\n vD[i] ← round_nearest_even(vB[i]) (IEEE 754 single precision)\nendfor", "page_found": "Page 452", "special_registers": "MSR", "programming_notes": "The vrfin instruction is commonly used for rounding floating-point numbers in vector operations. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. Be aware of potential precision loss when rounding to integers, especially with ties. This instruction operates on 32-bit floating-point elements and requires proper alignment for optimal performance.", "example": "vrfin vd, vb" }, { "mnemonic": "vrfip", "architecture": "PowerISA", "full_name": "Vector Round to Floating-Point Integer towards Plus Infinity", "summary": "Rounds each element of a vector to the nearest integer towards positive infinity.", "syntax": "vrfip vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | VRT | VRB | 11 | 0", "hex_opcode": "0x1000028A", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "650", "clean": "650" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:30 | 31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vrfip, each single-precision floating-point value in VSR[VRB+32] is rounded towards positive infinity and placed into the corresponding word element of VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n src ← VSR[VRB+32].word[i]\n VSR[VRT+32].word[i] ← bfp32_ROUND_TO_INTEGER_CEIL(src)\nend", "page_found": "Page 452 - 453", "special_registers": "MSR", "programming_notes": "This instruction rounds each single-precision floating-point value in the source vector towards positive infinity. Ensure that the Vector Facility is enabled by checking and setting the appropriate bit in the MSR register. Be cautious of potential overflow when rounding very large numbers.", "example": "vrfip vd, vb" }, { "mnemonic": "vrfiz", "architecture": "PowerISA", "full_name": "Vector Round to Floating-Point Integer towards Zero", "summary": "Rounds 4 floats to integer (trunc).", "syntax": "vrfiz vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 0 | vB | 586", "hex_opcode": "0x1000024A", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "586", "clean": "586" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" } ], "extension": "VMX (AltiVec)", "description": "Rounds each of four 32-bit floating-point elements in vB towards zero (truncate) and stores the integer results as floating-point values in vD. This instruction operates on the VMX/AltiVec extension and does not modify condition registers or exception flags.", "pseudocode": "for i in 0 to 3:\n vD[32*i:32*i+31] ← RoundTowardZero(vB[32*i:32*i+31])", "page_found": "Page 453", "special_registers": "MSR", "programming_notes": "The vrfiz instruction rounds each single-precision floating-point value in the source vector towards zero. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on 32-bit words, so ensure proper alignment of the data for optimal performance.", "example": "vrfiz vd, vb" }, { "mnemonic": "vcmpeqfp", "architecture": "PowerISA", "full_name": "Vector Compare Equal Floating-Point", "summary": "Compares the elements of two vector registers for equality and stores the result in a third vector register.", "syntax": "vcmpeqfp VRT,VRA,VRB", "encoding": { "format": "VC-form", "binary_pattern": "4 | VRT | VRA | VRB | Rc", "hex_opcode": "0x100000C6", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "198", "clean": "198" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vcmpeqfp, each element of VSR[VRA+32] is compared to the corresponding element of VSR[VRB+32]. If they are equal, the corresponding element of VSR[VRT+32] is set to all 1s; otherwise, it is set to all 0s.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nall_true ←1\nall_false ←1\ndo i = 0 to 3\n src1 ←VSR[VRA+32].word[i]\n src2 ←VSR[VRB+32].word[i]\n if bool_COMPARE_EQ_BFP32(src1,src2)=1 then\n VSR[VRT+32].word[i] ←0xFFFF_FFFF\n all_false ←0\n else\n VSR[VRT+32].word[i] ←0x0000_0000\n all_true ←0\nend\nif Rc=1 then\n CR.field[6] ←all_true || 0b0 || all_false || 0b0", "special_registers": "CR0, XER", "page_found": "Page 454 - 455", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "vcmpeqfp v1, v2, v3" }, { "mnemonic": "vcmpgtfp", "architecture": "PowerISA", "full_name": "Vector Compare Greater Than Floating-Point", "summary": "Compares the contents of two vector registers and sets the target vector register based on whether each element is greater than the corresponding element in the other vector.", "syntax": "vcmpgtfp VRT,VRA,VRB", "encoding": { "format": "VC-form", "binary_pattern": "4 | VRT | VRA | VRB | Rc", "hex_opcode": "0x100002C6", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "710", "clean": "710" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vcmpgtfp, the contents of VSR[VRA+32] are compared to the contents of VSR[VRB+32]. The result is stored in VSR[VRT+32], with each word set to all 1s if the corresponding element in VSR[VRA+32] is greater than that in VSR[VRB+32], and all 0s otherwise.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nall_true ←1\nall_false ←1\ndo i = 0 to 3\n src1 ←VSR[VRA+32].word[i]\n src2 ←VSR[VRB+32].word[i]\n if bool_COMPARE_GT_BFP32(src1,src2)=1 then\n VSR[VRT+32].word[i] ←0xFFFF_FFFF\n all_false ←0\n else\n all_true ←0\n VSR[VRT+32].word[i] ←0x0000_0000\nend\nif Rc=1 then\n CR.field[6] ←all_true || 0b0 || all_false || 0b0", "special_registers": "CR6", "page_found": "Page 455 - 456", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "vcmpgtfp v1, v2, v3" }, { "mnemonic": "vcmpgefp", "architecture": "PowerISA", "full_name": "Vector Compare Greater Equal Floating-Point", "summary": "Compares 4 floats (A >= B).", "syntax": "vcmpgefp vD, vA, vB", "encoding": { "format": "VC-form", "binary_pattern": "4 | vD | vA | vB | 454", "hex_opcode": "0x100001C6", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "454", "clean": "454" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Compares each of four 32-bit floating-point elements: vA >= vB. For each element, stores all 1s (0xFFFFFFFF) if the condition is true, or all 0s if false, into the corresponding word of vD. This instruction operates on VMX/AltiVec and does not modify the condition register.", "pseudocode": "for i in 0 to 3:\n if vA[32*i:32*i+31] >= vB[32*i:32*i+31] then\n vD[32*i:32*i+31] ← 0xFFFFFFFF\n else\n vD[32*i:32*i+31] ← 0x00000000", "special_registers": "MSR, CR6", "programming_notes": "This instruction is commonly used for element-wise comparison of single-precision floating-point numbers in vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The result of each comparison is stored as 0xFFFFFFFF if true or 0x0000_0000 if false in the target VSR. If Rc=1, CR Field 6 is updated to reflect whether all comparisons were true, all were false, or a mix of both.", "example": "vcmpgefp vd, va, vb" }, { "mnemonic": "vcmpbfp", "architecture": "PowerISA", "full_name": "Vector Compare Bounds Floating-Point", "summary": "Compares two VSRs word element by word and sets the target VSR if Rc=1.", "syntax": "vcmpbfp VRT,VRA,VRB", "encoding": { "format": "VC-form", "binary_pattern": "4 | VRT | VRA | VRB | Rc | 966", "hex_opcode": "0x100003C6", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "966", "clean": "966" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21 | 22:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "Performs a bounds check comparing each of four 32-bit floating-point elements in VRA against the range defined by two bounds in VRB. The result is stored in VRT as a 4-bit value per element indicating which bound(s) the value violates. When the Rc bit is set (vcmpbfp.), the CR6 field is updated based on the result.", "pseudocode": "for i in 0 to 3:\n if isnan(VRA[32*i:32*i+31]) or isnan(VRB[32*i:32*i+31]) then\n VRT[30*i:30*i+29] ← 0b11\n else if VRA[32*i:32*i+31] < -VRB[32*i:32*i+31] then\n VRT[30*i:30*i+29] ← 0b10\n else if VRA[32*i:32*i+31] > VRB[32*i:32*i+31] then\n VRT[30*i:30*i+29] ← 0b01\n else\n VRT[30*i:30*i+29] ← 0b00\nif Rc = 1 then\n CR6 ← 0b0001 if all results are within bounds else 0b0000", "special_registers": "CR6", "programming_notes": "Each single-precision floating-point value in VSR[VRB+32] should be non-negative; if it is negative, the corresponding element in VSR[VRA+32] will necessarily be out of bounds. One exception to this is when the value of an element in VSR[VRB+32] is -0.0 and the value of the corresponding element in VSR[VRA+32] is either +0.0 or -0.0. +0.0 and -0.0 compare equal to -0.0.", "page_found": "Page 453 - 454", "example": "vcmpbfp v1, v2, v3" }, { "mnemonic": "vpkpx", "architecture": "PowerISA", "full_name": "Vector Pack Pixel", "summary": "Packs the contents of two vector registers into a single vector register, with each source word being considered as a 32-bit pixel and each target halfword as a 16-bit pixel.", "syntax": "vpkpx vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 782", "hex_opcode": "0x1000030E", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "782", "clean": "782" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vpkpx, the contents of VSR[VRA+32] and VSR[VRB+32] are concatenated to form a single vector. Each word element from this concatenated vector is then packed into a halfword element in VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nlet vsrc be the concatenation of the contents of VSR[VRA+32] followed by the contents of VSR[VRB+32].\ndo i = 0 to 7\n VSR[VRT+32].hword[i].bit[0] ← vsrc.word[i].bit[7]\n VSR[VRT+32].hword[i].bit[1:5] ← vsrc.word[i].bit[8:12]\n VSR[VRT+32].hword[i].bit[6:10] ← vsrc.word[i].bit[16:20]\n VSR[VRT+32].hword[i].bit[11:15] ← vsrc.word[i].bit[24:28]", "programming_notes": "Each source word can be considered to be a 32-bit 'pixel', consisting of four 8-bit 'channels'. Each target halfword can be considered to be a 16-bit pixel, consisting of one 1-bit channel and three 5-bit channels.", "page_found": "Page 303 - 304", "special_registers": "MSR", "example": "vpkpx vd, va, vb" }, { "mnemonic": "vupkhpx", "architecture": "PowerISA", "full_name": "Vector Unpack High Pixel", "summary": "Unpacks high 4 pixels to 4 words.", "syntax": "vupkhpx vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 0 | vB | 846", "hex_opcode": "0x1000034E", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "846", "clean": "846" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" } ], "extension": "VMX (AltiVec)", "description": "Unpacks the four high-order pixel values (each 8 bits) from vB into four 32-bit word elements in vD, expanding each pixel into a word with implicit format expansion. This VMX/AltiVec instruction is commonly used in graphics processing and does not affect status registers.", "pseudocode": "for i in 0 to 3:\n pixel ← vB[8*(i+4):8*(i+4)+7]\n vD[32*i:32*i+31] ← ExpandPixel(pixel)", "page_found": "Page 314", "special_registers": "MSR", "programming_notes": "The vupkhpx instruction is used to unpack the high halfwords of a vector register into bytes, sign-extending the most significant bit and zero-extending the remaining bits. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. This operation is useful for processing pixel data where each pixel requires byte-level manipulation.", "example": "vupkhpx vd, vb" }, { "mnemonic": "vupklpx", "architecture": "PowerISA", "full_name": "Vector Unpack Low Pixel", "summary": "Unpacks low 4 pixels to 4 words.", "syntax": "vupklpx vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 0 | vB | 974", "hex_opcode": "0x100003CE", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "974", "clean": "974" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" } ], "extension": "VMX (AltiVec)", "description": "Unpacks the four low-order pixel values (each 8 bits) from vB into four 32-bit word elements in vD, expanding each pixel into a word with implicit format expansion. This VMX/AltiVec instruction is commonly used in graphics processing and does not affect status registers.", "pseudocode": "for i in 0 to 3:\n pixel ← vB[8*i:8*i+7]\n vD[32*i:32*i+31] ← ExpandPixel(pixel)", "page_found": "Page 314", "special_registers": "MSR", "programming_notes": "The vupklpx instruction is used to unpack the low halfwords of a vector register into bytes, sign-extending the first bit and zero-extending the remaining bits. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. This instruction operates on 128-bit vector registers and processes each halfword in the source register to produce four bytes per iteration.", "example": "vupklpx vd, vb" }, { "mnemonic": "vpermr", "architecture": "PowerISA", "full_name": "Vector Permute Right", "summary": "Bitwise byte shuffle similar to vperm but for little-endian access optimization.", "syntax": "vpermr vD, vA, vB, vC", "encoding": { "format": "VA-form", "binary_pattern": "4 | vD | vA | vB | vC | 59", "hex_opcode": "0x1000003B", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "vC", "clean": "vC" }, { "raw": "59", "clean": "59" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "vC", "desc": "Permute" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "page_found": "Page 1334 - 1335", "description": "Performs a byte permutation by selecting bytes from the concatenation of vA and vB using indices from vC, optimized for little-endian access patterns. This VMX/AltiVec instruction rearranges 16 bytes across the three source registers and stores the result in vD, with no impact on condition registers.", "programming_notes": "The vpermr instruction is used to perform a right permutation on the elements of a vector register. It is commonly used in scenarios where data needs to be shifted or rotated within a vector for operations like cryptography, signal processing, or custom algorithms. Ensure that the input vector is properly aligned and that the operation does not exceed the bounds of the vector register to avoid undefined behavior. This instruction operates at user privilege level and may raise exceptions if the alignment requirements are not met.", "pseudocode": "src ← vA || vB\nfor i in 0 to 15:\n index ← vC[4*i:4*i+3]\n vD[8*i:8*i+7] ← src[8*index:8*index+7]", "example": "vpermr vd, va, vb, vc" }, { "mnemonic": "vpmsumb", "architecture": "PowerISA", "full_name": "Vector Polynomial Multiply-Sum Byte", "summary": "Performs GF(2) polynomial arithmetic (Carryless Multiply) on bytes.", "syntax": "vpmsumb vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 1032", "hex_opcode": "0x10000408", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1032", "clean": "1032" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "Vector Crypto", "description": "For vpmsumb, each byte element in VSR[VRA+32] is multiplied by each byte element in VSR[VRB+32], and the results are summed. The final result is stored in VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 15\n prod[i].bit[0:14] ←0\n srcA ←VSR[VRA+32].byte[i]\n srcB ←VSR[VRB+32].byte[i]\n do j = 0 to 7\n do k = 0 to j\n gbit ←srcA.bit[k] & srcB.bit[j-k]\n prod[i].bit[j] ←prod[i].bit[j] ⊕gbit\n end\n end\n do j = 8 to 14\n do k = j-7 to 7\n gbit ←(srcA.bit[k] & srcB.bit[j-k])\n prod[i].bit[j] ←prod[i].bit[j] ⊕gbit\n end\n end\nend\ndo i = 0 to 7\n VSR[VRT+32].hword[i] ←0b0 || (prod[2×i] ⊕prod[2×i+1])\nend", "page_found": "Page 465 - 466", "special_registers": "MSR", "programming_notes": "The vpmsumb instruction performs a polynomial multiplication and summation on byte elements of vector registers. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on 16-byte vectors, so input and output vectors must be properly aligned. Be cautious with handling overflow as the result is truncated to fit into the destination register.", "example": "vpmsumb vd, va, vb" }, { "mnemonic": "vpmsumh", "architecture": "PowerISA", "full_name": "Vector Polynomial Multiply-Sum Halfword", "summary": "Performs GF(2) polynomial arithmetic on halfwords.", "syntax": "vpmsumh vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "000100 | vD | vA | vB | 10001 | 001000", "hex_opcode": "0x10000448", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1096", "clean": "1096" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "page_found": "Page 1410 - 1411", "description": "Performs GF(2) polynomial multiplication on pairs of 16-bit halfword elements from vA and vB, accumulating the results into vD. This VMX/AltiVec instruction is used in cryptographic and polynomial arithmetic operations and does not modify condition registers or exception status.", "pseudocode": "for i in 0 to 3:\n prod ← PolyMultiply_GF2(vA[32*i:32*i+31], vB[32*i:32*i+31])\n vD[64*i:64*i+63] ← vD[64*i:64*i+63] XOR prod", "special_registers": "MSR", "programming_notes": "The vpmsumh instruction is commonly used for finite field arithmetic operations, particularly in cryptographic algorithms. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. Be cautious of alignment requirements; source vectors must be aligned to halfword boundaries. This instruction operates at a privilege level where vector operations are supported, typically user or supervisor mode. Exception conditions include a Vector Unavailable exception if the facility is not enabled.", "example": "vpmsumh vd, va, vb" }, { "mnemonic": "vpmsumw", "architecture": "PowerISA", "full_name": "Vector Polynomial Multiply-Sum Word", "summary": "Performs a polynomial multiply-sum operation on word elements of two vector registers and stores the result in another vector register.", "syntax": "vpmsumw vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 1160", "hex_opcode": "0x10000488", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1160", "clean": "1160" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "Vector Crypto", "description": "Performs GF(2) polynomial multiplication on pairs of 32-bit word elements from vA and vB, accumulating the results into vD. This instruction is part of the Vector Crypto extension and is essential for cryptographic operations such as CRC and GHASH computation. No condition registers or exception flags are modified.", "pseudocode": "for i in 0 to 1:\n prod ← PolyMultiply_GF2(vA[32*i:32*i+31], vB[32*i:32*i+31])\n vD[64*i:64*i+63] ← vD[64*i:64*i+63] XOR prod", "page_found": "Page 466 - 467", "special_registers": "MSR", "programming_notes": "The vpmsumw instruction is used for polynomial multiplication of word elements in vector registers. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on 128-bit vectors, processing four 32-bit words each. Be cautious with alignment; input vectors must be properly aligned to avoid undefined behavior. The result is a 64-bit word for each pair of input words, XORed together and stored in the destination vector. Exception conditions include invalid use of registers or disabled Vector Facility.", "example": "vpmsumw vd, va, vb" }, { "mnemonic": "vpmsumd", "architecture": "PowerISA", "full_name": "Vector Polynomial Multiply-Sum Doubleword", "summary": "Performs GF(2) polynomial arithmetic on doublewords.", "syntax": "vpmsumd vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 1224", "hex_opcode": "0x100004C8", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1224", "clean": "1224" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "Vector Crypto", "description": "Performs Galois Field GF(2) polynomial multiplication and summation on doubleword elements. The instruction multiplies corresponding doubleword elements from vA and vB using polynomial arithmetic over GF(2), accumulating partial products into the destination register vD. This instruction is part of the Vector Crypto extension and does not affect CR0 or condition registers.", "page_found": "Page 467", "programming_notes": "The vpmsumd instruction is commonly used for performing polynomial multiplication and summation operations on large datasets efficiently. Ensure that the input vectors are properly aligned to doubleword boundaries to avoid alignment faults. This instruction operates at user privilege level, but care must be taken to handle potential overflow conditions in the sum results. Performance can be optimized by ensuring that the data is loaded into vector registers before executing vpmsumd.", "pseudocode": "vD[0:63] ← GF(2)_multiply_sum(vA[0:63], vB[0:63])\nvD[64:127] ← GF(2)_multiply_sum(vA[64:127], vB[64:127])", "example": "vpmsumd vd, va, vb" }, { "mnemonic": "lxv", "architecture": "PowerISA", "full_name": "Load VSX Vector", "summary": "Loads a 128-bit vector from memory (VSX aligned offset).", "syntax": "lxv XT, DQ(RA)", "encoding": { "format": "DQ-form", "binary_pattern": "0 | T | RA | DQ | TX | 1", "hex_opcode": "0xF4000001", "visual_parts": [ { "raw": "61", "clean": "61" }, { "raw": "XT", "clean": "XT" }, { "raw": "RA", "clean": "RA" }, { "raw": "DQ", "clean": "DQ" }, { "raw": "1", "clean": "1" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:27 | 28:30 | 31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "DQ", "desc": "Offset" }, { "name": "RA", "desc": "Base" }, { "name": "disp", "desc": "Displacement value" } ], "extension": "VSX", "description": "For lxv, the contents of the quadword in storage at address EA are placed into load_data. The order of bytes depends on the endianness (Big-Endian or Little-Endian). load_data is then placed into VSR[XT].", "pseudocode": "if 'lxv' & TX=0 & MSR.VSX=0 then VSX_Unavailable()\nif 'lxv' & TX=1 & MSR.VEC=0 then Vector_Unavailable()\nEA ←(RA|0) + EXTS64(DQ||0b0000)\nVSR[32×TX+T] ←MEM(EA,16)", "page_found": "Page 610 - 611", "special_registers": "MSR", "programming_notes": "The lxv instruction loads a 16-byte vector from memory into a VSX register. Ensure the address is properly aligned to avoid alignment faults. Check that the appropriate privilege levels (MSR.VSX for VSX operations and MSR.VEC for vector operations) are enabled before executing this instruction.", "example": "lxv vs1, 0(r4)" }, { "mnemonic": "stxv", "architecture": "PowerISA", "full_name": "Store VSX Vector", "summary": "Stores a 128-bit vector to memory (VSX aligned offset).", "syntax": "stxv XS, DQ(RA)", "encoding": { "format": "DQ-form", "binary_pattern": "61 | XS | RA | DQ | 5 | TX", "hex_opcode": "0xF4000005", "visual_parts": [ { "raw": "61", "clean": "61" }, { "raw": "XS", "clean": "XS" }, { "raw": "RA", "clean": "RA" }, { "raw": "DQ", "clean": "DQ" }, { "raw": "5", "clean": "5" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:27 | 28:30 | 31" }, "operands": [ { "name": "XS", "desc": "Source" }, { "name": "DQ", "desc": "Offset" }, { "name": "RA", "desc": "Base" }, { "name": "disp", "desc": "Displacement value" }, { "name": "VX", "desc": "VSX Register" }, { "name": "RB", "desc": "Index General Purpose Register" }, { "name": "VS32", "desc": "Source VSX Register" } ], "extension": "VSX", "description": "For stxv, the contents of VSR[XS] are stored into memory at the effective address (EA), which is the sum of the contents of GPR[RA] and the value DQ sign-extended to 64 bits. If RA=0, EA is set to 0.", "pseudocode": "if 'stxv' & SX=0 & MSR.VSX=0 then VSX_Unavailable()\nif 'stxv' & SX=1 & MSR.VEC=0 then Vector_Unavailable()\nEA ← (RA|0) + EXTS64(DQ||0b0000)\nMEM(EA,16) ← VSR[32×SX+S]", "page_found": "Page 626 - 627", "special_registers": "MSR", "programming_notes": "The stxv instruction stores a VSX vector from the VSR register to memory. Ensure that the VSX or Vector facility is enabled in the MSR register based on the SX field value. The effective address (EA) is calculated by adding the contents of GPR[RA] and the sign-extended DQ value. If RA is 0, EA defaults to 0. This instruction operates at user privilege level unless otherwise specified.", "example": "stxv vs1, 0(r4)" }, { "mnemonic": "lxvdsx", "architecture": "PowerISA", "full_name": "Load VSX Vector Doubleword and Splat Indexed", "summary": "Loads a doubleword from memory and splats it into two elements of a VSX vector register.", "syntax": "lxvdsx XT, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | XT | RA | RB | 332 | TX", "hex_opcode": "0x7C000298", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "XT", "clean": "XT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "332", "clean": "332" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" }, { "name": "VX", "desc": "Destination Vector Register" } ], "extension": "VSX", "description": "Loads a doubleword from memory at the address computed from RA+RB and splats it across two doubleword elements in the VSX vector register XT. The effective address is formed by adding the contents of RA (or 0 if RA=0) and RB. The 64-bit value is replicated into both elements of the 128-bit VSX register. This VSX extension instruction does not affect condition registers.", "pseudocode": "EA ← (RA = 0) ? RB : RA + RB\ndoubleword ← [EA]\nXT[0:63] ← doubleword\nXT[64:127] ← doubleword", "page_found": "Page 617 - 618", "special_registers": "CR0, XER", "programming_notes": "The lxvdsx instruction is commonly used to load a doubleword from memory and replicate it across both elements of a VSX vector register. Ensure that the VSX facility is enabled (MSR.VSX=1) to avoid exceptions. The effective address must be aligned to an 8-byte boundary for optimal performance, although unaligned accesses are supported with potential performance penalties.", "example": "lxvdsx vs1, r4, r5" }, { "mnemonic": "lxvw4x", "architecture": "PowerISA", "full_name": "Load VSX Vector Word*4 Indexed", "summary": "Loads four words into a vector (unaligned).", "syntax": "lxvw4x XT, RA, RB", "encoding": { "format": "XX1-form", "binary_pattern": "31 | XT | RA | RB | 780", "hex_opcode": "0x7C000618", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "XT", "clean": "XT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "780", "clean": "780" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "VSX", "description": "The contents of the byte in storage at address EA+4×i+3 are placed into byte element 3 of load_data. When Little-Endian byte ordering is employed, the contents of the word in storage at address EA+4×i are placed into word element i of VSR[XT] in such an order that; if MSR.VSX=0 then VSX_Unavailable(). EA ←((RA=0) ? 0 : GPR[RA]) + GPR[RB]. Let XT be the value 32×TX + T. Let EA be the sum of the contents of GPR[RA], or 0 if RA is equal to 0, and the contents of GPR[RB]. For each integer value i from 0 to 3, do the following.", "pseudocode": "if MSR.VSX=0 then\n VSX_Unavailable()\nEA ←((RA=0) ? 0 : GPR[RA]) + GPR[RB]\nfor i from 0 to 3 do\n VSR[32×TX+T].word[i] ←MEM(EA+4×i, 4)", "programming_notes": "lxvd2x, lxvw4x, lxvh8x, lxvb16x, and lxvx exhibit identical behavior in Big-Endian mode.", "page_found": "Page 614 - 615", "special_registers": "MSR", "example": "lxvw4x vs1, r4, r5" }, { "mnemonic": "stxvw4x", "architecture": "PowerISA", "full_name": "Store VSX Vector Word*4 Indexed", "summary": "Stores four words from a vector (unaligned).", "syntax": "stxvw4x XS, RA, RB", "encoding": { "format": "XX1-form", "binary_pattern": "18 | S | RA | RB | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0", "hex_opcode": "0x7C000718", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "XS", "clean": "XS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "972", "clean": "972" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "XS", "desc": "Source" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "VSX", "description": "Stores four 32-bit word elements from a VSX vector register XS into memory at an unaligned address computed as RA+RB. The effective address is calculated by adding RA (or 0 if RA=0) and RB, and the four words from the source register are written to consecutive memory locations. This VSX extension instruction does not affect condition registers and permits unaligned access.", "pseudocode": "EA ← (RA = 0) ? RB : RA + RB\n[EA:EA+3] ← XS[0:31]\n[EA+4:EA+7] ← XS[32:63]\n[EA+8:EA+11] ← XS[64:95]\n[EA+12:EA+15] ← XS[96:127]", "programming_notes": "stxvd2x, stxvw4x, stxvh8x, stxvb16x, and stxvx exhibit identical behavior in Big-Endian mode.", "page_found": "Page 630 - 631", "special_registers": "MSR", "example": "stxvw4x vs1, r4, r5" }, { "mnemonic": "lxsiwax", "architecture": "PowerISA", "full_name": "Load VSX Scalar as Integer Word Algebraic Indexed", "summary": "Loads a word from memory into the left-most doubleword element of a VSR, sign-extends it to 64 bits, and aligns it.", "syntax": "lxsiwax XT, RA, RB", "encoding": { "format": "XX1-form", "binary_pattern": "31 | XT | RA | RB | 76 | TX", "hex_opcode": "0x7C000098", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "XT", "clean": "XT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "76", "clean": "76" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" }, { "name": "VX", "desc": "Target Vector-Specific Register" } ], "extension": "VSX", "description": "Loads a 32-bit signed integer word from memory at address RA+RB into the left-most doubleword element of VSX register XT, with the value sign-extended to 64 bits. The effective address is computed by adding RA (or 0 if RA=0) and RB. The loaded and sign-extended value occupies bits 0-63 of the VSX register, leaving the right element undefined. This VSX extension instruction does not affect condition registers.", "pseudocode": "EA ← (RA = 0) ? RB : RA + RB\nword ← [EA:EA+3]\nXT[0:63] ← sign_extend(word, 64)\nXT[64:127] ← undefined", "page_found": "Page 596 - 597", "special_registers": "MSR", "programming_notes": "The lxsiwax instruction is commonly used to load a 32-bit integer from memory into the left-most doubleword of a VSX register, with sign extension. Ensure that the VSX facility is enabled in the MSR register; otherwise, a VSX_Unavailable exception will be raised. The effective address (EA) must be properly calculated and aligned to a word boundary for optimal performance and correct data loading.", "example": "lxsiwax vs1, r4, r5" }, { "mnemonic": "lxsiwzx", "architecture": "PowerISA", "full_name": "Load VSX Scalar as Integer Word Zero Indexed", "summary": "Loads a word from memory and places it into the specified VSX register, zero-extending it.", "syntax": "lxsiwzx XT, RA, RB", "encoding": { "format": "XX1-form", "binary_pattern": "0 | T | RA | RB | 12 | TX", "hex_opcode": "0x7C000018", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "XT", "clean": "XT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "12", "clean": "12" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "VSX", "description": "Loads a 32-bit unsigned integer word from memory at address RA+RB into the left-most doubleword element of VSX register XT, with the value zero-extended to 64 bits. The effective address is computed by adding RA (or 0 if RA=0) and RB. The loaded and zero-extended value occupies bits 0-63 of the VSX register. This VSX extension instruction does not affect condition registers.", "pseudocode": "EA ← (RA = 0) ? RB : RA + RB\nword ← [EA:EA+3]\nXT[0:63] ← zero_extend(word, 64)\nXT[64:127] ← undefined", "page_found": "Page 601 - 602", "special_registers": "MSR", "programming_notes": "The lxsiwzx instruction is commonly used to load a word from memory into a VSX register, ensuring zero-extension. Ensure that the VSX facility is enabled in the MSR register; otherwise, a VSX_Unavailable exception will be raised. The address calculation respects the base and offset registers, with RA being optional (use 0 if not needed). This instruction does not require any specific alignment but must be executed at a privilege level where VSX operations are permitted.", "example": "lxsiwzx vs1, r4, r5" }, { "mnemonic": "stxsiwx", "architecture": "PowerISA", "full_name": "Store VSX Scalar as Integer Word Indexed", "summary": "Stores a single-precision floating-point value from a VSX register into memory, indexed by another register.", "syntax": "stxsiwx XS, RA, RB", "encoding": { "format": "XX1-form", "binary_pattern": "011111 | RS | B | RB | 00100 | 01100", "hex_opcode": "0x7C000118", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "XS", "clean": "XS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "140", "clean": "140" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "XS", "desc": "Source" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" }, { "name": "RS", "desc": "Source VSX Register" }, { "name": "B", "desc": "Base General Purpose Register" } ], "extension": "VSX", "description": "Stores the low-order 32 bits from the left-most doubleword element of VSX register XS into memory at the address computed as RA+RB. The effective address is formed by adding RA (or 0 if RA=0) and RB. The 32-bit word from XS[32:63] is written to the memory location. This VSX extension instruction does not affect condition registers.", "pseudocode": "EA ← (RA = 0) ? RB : RA + RB\n[EA:EA+3] ← XS[32:63]", "page_found": "Page 607 - 608", "special_registers": "MSR", "programming_notes": "The stxsiwx instruction stores the second word of a VSX register into memory. Ensure that the VSX facility is enabled in the MSR register to avoid exceptions. The effective address is calculated from two GPRs, so ensure proper alignment and bounds checking to prevent memory access errors.", "example": "stxsiwx vs1, r4, r5" }, { "mnemonic": "mfvsrd", "architecture": "PowerISA", "full_name": "Move From VSR Doubleword", "summary": "Moves the contents of a doubleword element from a Vector-Scalar Register (VSR) to a General Purpose Register (GPR).", "syntax": "mfvsrd RA, XS", "encoding": { "format": "XX1-form", "binary_pattern": "31 | S | RA | /// | 51 | SX", "hex_opcode": "0x7C000066", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "XS", "clean": "XS" }, { "raw": "RA", "clean": "RA" }, { "raw": "0", "clean": "0" }, { "raw": "51", "clean": "51" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RA", "desc": "Target GPR" }, { "name": "XS", "desc": "Source VSR" } ], "extension": "VSX", "description": "The contents of doubleword element 0 of VSR[XS] are placed into GPR[RA]. For SX=0, mfvsrd is treated as a Floating-Point instruction in terms of resource availability. For SX=1, mfvsrd is treated as a Vector instruction in terms of resource availability.", "pseudocode": "if SX=0 & MSR.FP=0 then FP_Unavailable()\nif SX=1 & MSR.VEC=0 then Vector_Unavailable()\nGPR[RA] ← VSR[32×SX+S].dword[0]", "programming_notes": "For SX=0, mfvsrd is treated as a Floating-Point instruction in terms of resource availability.\nFor SX=1, mfvsrd is treated as a Vector instruction in terms of resource availability.", "extended_mnemonics": [ { "mnemonic": "mffprd", "equivalent_to": "mfvsrd RA,frs" }, { "mnemonic": "mfvrd", "equivalent_to": "mfvsrd RA,vrs+32" } ], "page_found": "Page 156 - 158", "special_registers": "MSR", "example": "mfvsrd r4, vs1" }, { "mnemonic": "mtvsrd", "architecture": "PowerISA", "full_name": "Move To VSR Doubleword", "summary": "Moves 64 bits from a GPR to a VSR.", "syntax": "mtvsrd XT, RA", "encoding": { "format": "XX1-form", "binary_pattern": "31 | XT | RA | 0 | 179", "hex_opcode": "0x7C000166", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "XT", "clean": "XT" }, { "raw": "RA", "clean": "RA" }, { "raw": "0", "clean": "0" }, { "raw": "179", "clean": "179" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "XT", "desc": "Target VSR" }, { "name": "RA", "desc": "Source GPR" } ], "extension": "VSX", "description": "Moves a 64-bit value from general-purpose register RA into the left-most doubleword element of VSX register XT. The entire 64-bit content of RA is copied to bits 0-63 of the target VSX register; the right doubleword element (bits 64-127) is left undefined. This VSX extension instruction does not affect condition registers.", "pseudocode": "XT[0:63] ← RA\nXT[64:127] ← undefined", "page_found": "Page 159", "special_registers": "MSR", "programming_notes": "The mtvsrd instruction is commonly used to transfer data from a general-purpose register to the first doubleword of a vector-scalar register. Ensure that the appropriate privilege level (FP or VEC) is enabled in the MSR register, otherwise, an exception will be raised. Note that the second doubleword of the VSR is zeroed out during this operation.", "example": "mtvsrd vs1, r4" }, { "mnemonic": "mfvsrwz", "architecture": "PowerISA", "full_name": "Move From VSR Word and Zero", "summary": "Moves the contents of a word element from a vector-scalar register to a general-purpose register, zeroing the upper bits.", "syntax": "mfvsrwz RA, XS", "encoding": { "format": "XX1-form", "binary_pattern": "31 | XS | RA | 0 | 115", "hex_opcode": "0x7C0000E6", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "XS", "clean": "XS" }, { "raw": "RA", "clean": "RA" }, { "raw": "0", "clean": "0" }, { "raw": "115", "clean": "115" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "RA", "desc": "Target GPR" }, { "name": "XS", "desc": "Source VSR" } ], "extension": "VSX", "description": "The contents of word element 1 of VSR[XS] are placed into bits 32:63 of GPR[RA]. The contents of bits 0:31 of GPR[RA] are set to 0. Let XS be the value 32×SX + S.", "pseudocode": "if SX=0 & MSR.FP=0 then FP_Unavailable()\nif SX=1 & MSR.VEC=0 then Vector_Unavailable()\nGPR[RA] ←EXTZ64(VSR[32×SX+S].word[1])", "programming_notes": "For SX=0, mfvsrwz is treated as a Floating-Point instruction in terms of resource availability.\nFor SX=1, mfvsrwz is treated as a Vector instruction in terms of resource availability.", "extended_mnemonics": [ { "mnemonic": "mffprwz", "equivalent_to": "mfvsrwz RA,frs" }, { "mnemonic": "mfvrwz", "equivalent_to": "mfvsrwz RA,vrs+32" } ], "page_found": "Page 158 - 160", "special_registers": "MSR", "example": "mfvsrwz r4, vs1" }, { "mnemonic": "mtvsrwa", "architecture": "PowerISA", "full_name": "Move To VSR Word Algebraic", "summary": "Moves the two's-complement integer in bits 32:63 of GPR[RA] to doubleword element 0 of VSR[XT], sign-extended to 64 bits.", "syntax": "mtvsrwa XT, RA", "encoding": { "format": "XX1-form", "binary_pattern": "31 | XT | RA | / | 211 | TX", "hex_opcode": "0x7C0001A6", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "XT", "clean": "XT" }, { "raw": "RA", "clean": "RA" }, { "raw": "0", "clean": "0" }, { "raw": "211", "clean": "211" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "XT", "desc": "Target VSR" }, { "name": "RA", "desc": "Source GPR" }, { "name": "VS", "desc": "Target Vector Scalar Register" } ], "extension": "VSX", "description": "The two’s-complement integer in bits 32:63 of GPR[RA] is sign-extended to 64 bits and placed into doubleword element 0 of VSR[XT]. The contents of doubleword element 1 of VSR[XT] are undefined.", "pseudocode": "if TX=0 & MSR.FP=0 then FP_Unavailable()\nif TX=1 & MSR.VEC=0 then Vector_Unavailable()\nVSR[32×TX+T].dword[0] ←EXTS64(GPR[RA].bit[32:63])\nVSR[32×TX+T].dword[1] ←0xUUUU_UUUU_UUUU_UUUU", "programming_notes": "For TX=0, mtvsrwa is treated as a Floating-Point instruction in terms of resource availability.\nFor TX=1, mtvsrwa is treated as a Vector instruction in terms of resource availability.", "extended_mnemonics": [ { "mnemonic": "mtfprwa", "equivalent_to": "mtvsrwa frt,RA" }, { "mnemonic": "mtvrwa", "equivalent_to": "mtvsrwa vrt+32,RA" } ], "page_found": "Page 159 - 160", "special_registers": "MSR", "example": "mtvsrwa vs1, r4" }, { "mnemonic": "cmp", "architecture": "PowerISA", "full_name": "Compare", "summary": "Compares two registers as signed integers and records the result in the specified Condition Register Field.", "syntax": "cmp BF, L, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | BF | / | L | RA | RB | 0000000000 | 1", "hex_opcode": "0x7C000000", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "BF", "clean": "BF" }, { "raw": "/", "clean": "/" }, { "raw": "L", "clean": "L" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "0000000000", "clean": "0000000000" }, { "raw": "1", "clean": "1" } ], "bit_positions": "0:5 | 6:8 | 9 | 10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "BF", "desc": "Condition Register Field (0-7)" }, { "name": "L", "desc": "Operand Size (0=32-bit, 1=64-bit)" }, { "name": "RA", "desc": "Source Register 1" }, { "name": "RB", "desc": "Source Register 2" } ], "pseudocode": "if (RA) < (RB) then CR[BF] <- 0b1000 (LT)...", "example": "cmp cr7, 0, r3, r4", "example_note": "Compare r3 vs r4 (32-bit signed), result in cr7.", "extension": "Base", "description": "The fixed-point Compare instructions compare the contents of register RA with either the sign-extended value of the SI field, the zero-extended value of the UI field, or the contents of register RB. The comparison is signed for cmpi and cmp, and unsigned for cmpli and cmpl. The L field determines whether the operands are treated as 32-bit or 64-bit quantities.", "page_found": "Page 126", "special_registers": "CR", "programming_notes": "The cmp instruction is commonly used for signed comparisons between two registers. Ensure that the operands are correctly aligned and consider the L field to specify whether the comparison should be performed on 32-bit or 64-bit values. The result of the comparison updates the Condition Register (CR), so always check CR[BF] after executing cmp to determine the outcome." }, { "mnemonic": "cmpi", "architecture": "PowerISA", "full_name": "Compare Immediate", "summary": "Compares the contents of register RA with a sign-extended immediate value.", "syntax": "cmpi BF, L, RA, SI", "encoding": { "format": "D-form", "binary_pattern": "11 | BF | / | L | RA | SI", "hex_opcode": "0x2C000000", "visual_parts": [ { "raw": "11", "clean": "11" }, { "raw": "BF", "clean": "BF" }, { "raw": "/", "clean": "/" }, { "raw": "L", "clean": "L" }, { "raw": "RA", "clean": "RA" }, { "raw": "SI", "clean": "SI" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "BF", "desc": "Condition Register Field" }, { "name": "L", "desc": "Size (0=32-bit, 1=64-bit)" }, { "name": "RA", "desc": "Source Register" }, { "name": "SI", "desc": "Signed 16-bit Immediate" } ], "pseudocode": "if L = 0 then a ←EXTS((RA)32:63)\nelse a ←(RA)\nif a < EXTS(SI) then c ←0b100\nelse if a > EXTS(SI) then c ←0b010\nelse c ←0b001\nCR4×BF+32:4×BF+35 ←c || XERSO", "example": "cmpi cr0, 1, r3, -5", "example_note": "Compare r3 vs -5 (64-bit signed).", "extension": "Base", "description": "The contents of register RA ((RA)32:63 sign-extended to 64 bits if L=0) are compared with the sign-extended value of the SI field, treating the operands as signed integers. The result of the comparison is placed into CR field BF.", "special_registers": "CR, XER", "extended_mnemonics": [ { "mnemonic": "cmpdi", "equivalent_to": "cmpi BF,1,RA,SI" }, { "mnemonic": "cmpwi", "equivalent_to": "cmpi BF,0,RA,SI" } ], "page_found": "Page 125 - 126", "programming_notes": "The cmpi instruction is commonly used for signed integer comparisons where one operand is an immediate value. Be cautious with the alignment of the register RA, as incorrect alignment can lead to unexpected results. This instruction operates at user privilege level and does not generate exceptions under normal circumstances." }, { "mnemonic": "cmpl", "architecture": "PowerISA", "full_name": "Compare Logical", "summary": "Compares two registers as unsigned integers.", "syntax": "cmpl BF, L, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | BF | / | L | RA | RB | 0000100000 | 1", "hex_opcode": "0x7C000040", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "BF", "clean": "BF" }, { "raw": "/", "clean": "/" }, { "raw": "L", "clean": "L" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "0000100000", "clean": "0000100000" }, { "raw": "1", "clean": "1" } ], "bit_positions": "0:5 | 6:8 | 9 | 10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "BF", "desc": "Condition Register Field" }, { "name": "L", "desc": "Size (0=32-bit, 1=64-bit)" }, { "name": "RA", "desc": "Source Register 1" }, { "name": "RB", "desc": "Source Register 2" } ], "pseudocode": "if L = 0 then\n a ← zero_extend(RA[32:63], 64)\n b ← zero_extend(RB[32:63], 64)\nelse\n a ← RA\n b ← RB\nif a < b then\n CR[BF] ← 0b100 || SO\nelseif a > b then\n CR[BF] ← 0b010 || SO\nelse\n CR[BF] ← 0b001 || SO", "example": "cmpl cr1, 1, r3, r4", "example_note": "Unsigned compare of r3 vs r4.", "extension": "Base", "description": "Performs an unsigned logical comparison between RA and RB, with L determining the operand size (L=0 for 32-bit, L=1 for 64-bit). The comparison result is written to condition register field BF. The comparison sets the LT, GT, or EQ bits in the target CR field based on whether RA is less than, greater than, or equal to RB when interpreted as unsigned integers. This Base category instruction affects only the specified condition register field, not CR0.", "page_found": "Page 126", "special_registers": "CR", "programming_notes": "Use cmpl for unsigned comparisons. Ensure registers RA and RB are properly aligned if they contain pointers or data structures. The instruction modifies the Condition Register (CR), so check the appropriate field after execution to determine the result of the comparison." }, { "mnemonic": "cmpli", "architecture": "PowerISA", "full_name": "Compare Logical Immediate", "summary": "Compares the contents of a register with an immediate value and updates the condition register.", "syntax": "cmpli BF, L, RA, UI", "encoding": { "format": "D-form", "binary_pattern": "10 | BF | / | L | RA | UI", "hex_opcode": "0x28000000", "visual_parts": [ { "raw": "10", "clean": "10" }, { "raw": "BF", "clean": "BF" }, { "raw": "/", "clean": "/" }, { "raw": "L", "clean": "L" }, { "raw": "RA", "clean": "RA" }, { "raw": "UI", "clean": "UI" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "BF", "desc": "Condition Register Field" }, { "name": "L", "desc": "Size" }, { "name": "RA", "desc": "Source Register" }, { "name": "UI", "desc": "Unsigned 16-bit Immediate" }, { "name": "CRb", "desc": "Condition Register Field" }, { "name": "SIMM", "desc": "Signed Immediate Value" } ], "pseudocode": "if L = 0 then a ←320 || (RA)32:63\nelse a ←(RA)\nif a u (480 || UI) then c ←0b010\nelse c ←0b001\nCR4×BF+32:4×BF+35 ←c || XERSO", "example": "cmpli cr0, 0, r3, 0xFF", "example_note": "Check if r3 < 255 (unsigned).", "extension": "Base", "description": "The contents of register RA ((RA)32:63 zero-extended to 64 bits if L=0) are compared with 480 || UI, treating the operands as unsigned integers. The result of the comparison is placed into CR field BF.", "special_registers": "CR, XER", "extended_mnemonics": [ { "mnemonic": "cmpldi", "equivalent_to": "cmpli BF,1,RA,UI" } ], "page_found": "Page 126 - 128", "programming_notes": "The cmpli instruction is commonly used for unsigned integer comparisons where one operand is an immediate value. Be cautious with the zero-extension behavior when L=0, as it can lead to unexpected results if not accounted for. This instruction operates at user privilege level and does not generate exceptions under normal circumstances." }, { "mnemonic": "cntlzw", "architecture": "PowerISA", "full_name": "Count Leading Zeros Word", "summary": "Counts the number of consecutive 0 bits starting from bit 32 (MSB of the low word).", "syntax": "cntlzw RA, RS", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | 00000 | 000011010 | Rc", "hex_opcode": "0x7C000034", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "00000", "clean": "00000" }, { "raw": "000011010", "clean": "000011010" }, { "raw": "Rc", "clean": "Rc" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target Register" }, { "name": "RS", "desc": "Source Register" } ], "pseudocode": "n ← 0\nwhile n < 32 and RS[n] = 0 do n ← n + 1\nRA ← n\nif Rc = 1 then CR0 ← (RA = 0, RA < 0, RA > 0, SO)", "example": "cntlzw r3, r4", "example_note": "r3 = Leading Zeros in lower 32-bits of r4.", "extension": "Base", "description": "Counts the number of consecutive zero bits from the MSB (bit 0) of the 32-bit word in RS and stores the result in RA. The count ranges from 0 to 32. If Rc=1, CR0 is updated based on the result.", "page_found": "Page 137", "special_registers": "CR0", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER." }, { "mnemonic": "cntlzd", "architecture": "PowerISA", "full_name": "Count Leading Zeros Doubleword", "summary": "Counts the number of consecutive 0 bits starting from bit 0 (MSB of 64-bit reg).", "syntax": "cntlzd RT,RA", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | 00000 | 000111010 | Rc", "hex_opcode": "0x7C000074", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "00000", "clean": "00000" }, { "raw": "000111010", "clean": "000111010" }, { "raw": "Rc", "clean": "Rc" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RA", "desc": "Target Register" }, { "name": "RS", "desc": "Source Register" }, { "name": "RT", "desc": "Target General Purpose Register" } ], "pseudocode": "n ← 0\nwhile n < 64 and RS[n] = 0 do n ← n + 1\nRT ← n\nif Rc = 1 then CR0 ← (RT = 0, RT < 0, RT > 0, SO)", "example": "cntlzd r3, r4", "example_note": "r3 = Leading Zeros in 64-bit r4.", "extension": "Base", "description": "Counts the number of consecutive zero bits from the MSB (bit 0) of the 64-bit doubleword in RS and stores the result in RT. The count ranges from 0 to 64. If Rc=1, CR0 is updated based on the result.", "special_registers": "CR0", "page_found": "Page 139 - 140", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER." }, { "mnemonic": "crand", "architecture": "PowerISA", "full_name": "Condition Register AND", "summary": "Performs a bitwise AND between two bits in the Condition Register.", "syntax": "crand BT, BA, BB", "encoding": { "format": "XL-form", "binary_pattern": "19 | BT | BA | BB | 257 | /", "hex_opcode": "0x4C000202", "visual_parts": [ { "raw": "19", "clean": "19" }, { "raw": "BT", "clean": "BT" }, { "raw": "BA", "clean": "BA" }, { "raw": "BB", "clean": "BB" }, { "raw": "257", "clean": "257" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "BT", "desc": "Target Bit (0-31)" }, { "name": "BA", "desc": "Source Bit A" }, { "name": "BB", "desc": "Source Bit B" } ], "pseudocode": "CR[BT] <- CR[BA] & CR[BB]", "example": "crand 4*cr0+eq, 4*cr1+lt, 4*cr2+gt", "example_note": "If (cr1.lt AND cr2.gt), set cr0.eq.", "extension": "Base", "description": "The bit in the Condition Register specified by BA+32 is ANDed with the bit in the Condition Register specified by BB+32, and the result is placed into the bit in the Condition Register specified by BT+32.", "special_registers": "CR", "page_found": "Page 78 - 80", "programming_notes": "The crand instruction performs a bitwise AND operation on specific bits of the Condition Register (CR). It's commonly used to combine condition flags from different operations. Ensure that the BA, BB, and BT fields are correctly set to avoid unintended results. This instruction operates at user privilege level." }, { "mnemonic": "cror", "architecture": "PowerISA", "full_name": "Condition Register OR", "summary": "Performs a bitwise OR between two bits in the Condition Register.", "syntax": "cror BT, BA, BB", "encoding": { "format": "XL-form", "binary_pattern": "19 | BT | BA | BB | 449 | /", "hex_opcode": "0x4C000382", "visual_parts": [ { "raw": "19", "clean": "19" }, { "raw": "BT", "clean": "BT" }, { "raw": "BA", "clean": "BA" }, { "raw": "BB", "clean": "BB" }, { "raw": "449", "clean": "449" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "BT", "desc": "Target Bit" }, { "name": "BA", "desc": "Source Bit A" }, { "name": "BB", "desc": "Source Bit B" } ], "pseudocode": "CR[BT] ← CR[BA] | CR[BB]", "example": "cror 0, 1, 2", "example_note": "CR[0] = CR[1] | CR[2].", "extension": "Base", "description": "Performs a bitwise OR of CR bit BA and CR bit BB, storing the result in CR bit BT. This instruction operates only on the Condition Register and is commonly used in conditional branch sequences.", "page_found": "Page 79", "special_registers": "CR", "programming_notes": "The cror instruction is commonly used to combine condition flags from different parts of the Condition Register (CR) for conditional branching or logical operations. Ensure that the BA, BB, and BT fields correctly specify the bits you intend to OR; otherwise, it may lead to incorrect results. This instruction operates at user privilege level and does not generate exceptions under normal circumstances." }, { "mnemonic": "crxor", "architecture": "PowerISA", "full_name": "Condition Register XOR", "summary": "Performs a bitwise XOR between two bits in the Condition Register. Used to clear CR bits (crxor x,x,x).", "syntax": "crxor BT, BA, BB", "encoding": { "format": "XL-form", "binary_pattern": "19 | BT | BA | BB | 193 | /", "hex_opcode": "0x4C000182", "visual_parts": [ { "raw": "19", "clean": "19" }, { "raw": "BT", "clean": "BT" }, { "raw": "BA", "clean": "BA" }, { "raw": "BB", "clean": "BB" }, { "raw": "193", "clean": "193" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "BT", "desc": "Target Bit" }, { "name": "BA", "desc": "Source Bit A" }, { "name": "BB", "desc": "Source Bit B" } ], "pseudocode": "CR[BT] ← CR[BA] ^ CR[BB]", "example": "crxor 0, 0, 0", "example_note": "Clears CR bit 0 (sets it to 0).", "extension": "Base", "description": "Performs a bitwise XOR of CR bit BA and CR bit BB, storing the result in CR bit BT. When BA and BB are the same bit, this effectively clears CR[BT]; this form is frequently used for clearing condition register fields.", "page_found": "Page 79", "special_registers": "CR", "programming_notes": "The crxor instruction is used to perform a bitwise XOR operation between two condition register bits and store the result in another condition register bit. Ensure that the BA, BB, and BT fields are correctly set to avoid unintended behavior. This instruction operates at the problem state privilege level." }, { "mnemonic": "b", "architecture": "PowerISA", "full_name": "Branch", "summary": "Unconditionally branches to a target address relative to the current instruction pointer.", "syntax": "b target_addr (AA=0 LK=0)", "encoding": { "format": "I-form", "binary_pattern": "18 | LI | AA | LK", "hex_opcode": "0x48000000", "visual_parts": [ { "raw": "18", "clean": "18" }, { "raw": "LI", "clean": "LI" }, { "raw": "AA", "clean": "AA" }, { "raw": "LK", "clean": "LK" } ], "length": "32", "bit_positions": "0:5 | 6:29 | 30 | 31" }, "operands": [ { "name": "LI", "desc": "24-bit Signed Immediate (Displacement / 4)" }, { "name": "target_addr", "desc": "Branch Target Address" } ], "pseudocode": "if AA then\n NIA ←iea EXTS(LI || 0b00)\nelse\n NIA ←iea CIA + EXTS(LI || 0b00)\nif LK then\n LR ←iea CIA + 4", "example": "b label", "example_note": "Jump to 'label'.", "extension": "Base", "description": "The branch target address is the sum of LI || 0b00 sign-extended and the address of this instruction, with the high-order 32 bits of the branch target address set to 0 in 32-bit mode.", "special_registers": "LR", "page_found": "Page 74 - 76", "programming_notes": "The b instruction is used for unconditional branching. The AA and LK fields control whether the address is absolute or relative and whether to link back to the current instruction." }, { "mnemonic": "ba", "architecture": "PowerISA", "full_name": "Branch Absolute", "summary": "Unconditionally branches to an absolute address.", "syntax": "ba target_addr", "encoding": { "format": "I-form", "binary_pattern": "18 | LI | 1 | LK", "hex_opcode": "0x48000002", "visual_parts": [ { "raw": "18", "clean": "18" }, { "raw": "LI", "clean": "LI" }, { "raw": "1", "clean": "1" }, { "raw": "LK", "clean": "LK" } ], "bit_positions": "0:5 | 6:29 | 30 | 31", "length": "32" }, "operands": [ { "name": "LI", "desc": "24-bit Signed Immediate (Address / 4)" } ], "pseudocode": "NIA ← (LI || 0b00)\nif LK = 1 then LR ← CIA + 4", "example": "ba 0x1000", "example_note": "Jump to address 0x1000.", "extension": "Base", "description": "Unconditionally branches to an absolute address formed by sign-extending the 24-bit immediate LI and shifting left by 2 bits. The Link Register is not modified unless LK=1. This instruction does not check any condition bits.", "page_found": "Page 76", "programming_notes": "When LK=1, the address of the next sequential instruction is placed in LR, making this a subroutine call. Use blr to return." }, { "mnemonic": "bl", "architecture": "PowerISA", "full_name": "Branch and Link", "summary": "Branches to a target address and saves the return address (CIA + 4) in the Link Register (LR). Used for function calls.", "syntax": "bl target_addr", "encoding": { "format": "I-form", "binary_pattern": "18 | LI | AA | 1", "hex_opcode": "0x48000001", "visual_parts": [ { "raw": "18", "clean": "18" }, { "raw": "LI", "clean": "LI" }, { "raw": "AA", "clean": "AA" }, { "raw": "1", "clean": "1" } ], "bit_positions": "0:5 | 6:29 | 30 | 31", "length": "32" }, "operands": [ { "name": "LI", "desc": "24-bit Signed Immediate" } ], "pseudocode": "if AA = 0 then NIA ← CIA + (LI || 0b00) else NIA ← (LI || 0b00)\nLR ← CIA + 4", "example": "bl printf", "example_note": "Call 'printf' function.", "extension": "Base", "description": "Branches to a target address calculated from the 24-bit signed immediate and saves the return address (CIA + 4) in the Link Register (LR). The AA bit determines whether the address is absolute or relative. This is the standard instruction for subroutine calls.", "page_found": "Page 76", "special_registers": "LR", "programming_notes": "The bl instruction is commonly used for function calls where a return to the caller is required. Ensure that the target address is correctly calculated and aligned, as misalignment can lead to exceptions. The link register (LR) must be preserved if nested subroutine calls are made to maintain correct return paths." }, { "mnemonic": "bc", "architecture": "PowerISA", "full_name": "Branch Conditional", "summary": "Branches conditionally based on the Count Register (CTR) and/or a bit in the Condition Register (CR).", "syntax": "bc BO,BI,target_addr (AA=0 LK=0)", "encoding": { "format": "B-form", "binary_pattern": "10 | BO | BI | AA | LK | target_addr", "hex_opcode": "0x40000000", "visual_parts": [ { "raw": "16", "clean": "16" }, { "raw": "BO", "clean": "BO" }, { "raw": "BI", "clean": "BI" }, { "raw": "BD", "clean": "BD" }, { "raw": "AA", "clean": "AA" }, { "raw": "LK", "clean": "LK" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "BO", "desc": "Branch Options (5 bits)" }, { "name": "BI", "desc": "CR Bit Index (5 bits)" }, { "name": "BD", "desc": "14-bit Signed Displacement" }, { "name": "target_addr", "desc": "Target address" } ], "pseudocode": "ctr_ok ← (BO[2] = 1) | (CTR ≠ 0 ⊕ BO[3])\nif BO[2] = 0 then CTR ← CTR - 1\ncr_ok ← (BO[0] = 1) | (CR[BI] = BO[1])\nif ctr_ok & cr_ok then\n if AA = 0 then NIA ← CIA + (BD || 0b00) else NIA ← (BD || 0b00)\nif LK = 1 then LR ← CIA + 4", "example": "bc 12, 2, label", "example_note": "Branch if CR bit 2 is set (beq).", "extension": "Base", "description": "Branches conditionally based on the state of the Count Register (CTR) and/or a bit in the Condition Register (CR), as controlled by the BO field. The AA field determines absolute vs. relative addressing; LK=1 saves the return address in LR. This is the fundamental conditional branch instruction.", "special_registers": "LR, CTR", "extended_mnemonics": [ "bca", "bclr", "bcctr" ], "page_found": "Page 990 - 991", "programming_notes": "The bc instruction branches to a target address based on the condition bits in the Condition Register (CR). Ensure that the branch condition and target address are correctly set. The instruction operates at user privilege level, but care must be taken with conditional logic to avoid unintended execution paths." }, { "mnemonic": "bclr", "architecture": "PowerISA", "full_name": "Branch Conditional to Link Register", "summary": "Branches to the address in the Link Register (LR) if the condition is met. Used for function returns.", "syntax": "bclr BO,BI,BH", "encoding": { "format": "XL-form", "binary_pattern": "19 | BO | BI | 000 | 16 | LK", "hex_opcode": "0x4C000020", "visual_parts": [ { "raw": "19", "clean": "19" }, { "raw": "BO", "clean": "BO" }, { "raw": "BI", "clean": "BI" }, { "raw": "000", "clean": "000" }, { "raw": "16", "clean": "16" }, { "raw": "LK", "clean": "LK" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "BO", "desc": "Branch Options" }, { "name": "BI", "desc": "CR Bit Index" }, { "name": "BH", "desc": "Hint bits" }, { "name": "LK", "desc": "Link Register Update field" } ], "pseudocode": "ctr_ok ← (BO[2] = 1) | (CTR ≠ 0 ⊕ BO[3])\nif BO[2] = 0 then CTR ← CTR - 1\ncr_ok ← (BO[0] = 1) | (CR[BI] = BO[1])\nif ctr_ok & cr_ok then NIA ← LR[0:61] || 0b00\nif LK = 1 then LR ← CIA + 4", "example": "bclr 20, 0", "example_note": "Unconditional return (blr).", "extension": "Base", "description": "Branches to the address in the Link Register (LR) if the condition specified by BO and BI is satisfied. The CTR is decremented if BO[2]=0. If LK=1, the return address (CIA + 4) is saved in LR, enabling exception-safe subroutine returns. The BH field provides a branch prediction hint to the processor.", "special_registers": "CTR, LR", "programming_notes": "bclr, bclrl, bcctr, and bcctrl each serve as both a basic and an extended mnemonic. The Assembler will recognize a bclr, bclrl, bcctr, or bcctrl mnemonic with three operands as the basic form, and a bclr, bclrl, bcctr, or bcctrl mnemonic with two operands as the extended form. In the extended form the BH operand is omitted and assumed to be 0b00.", "extended_mnemonics": [ { "mnemonic": "bcctr", "equivalent_to": "bcctr BO,BI,BH" }, { "mnemonic": "bltctr", "equivalent_to": "bcctr 12,0,0" }, { "mnemonic": "bnectr", "equivalent_to": "bcctr 4,10,0" }, { "mnemonic": "bclr", "equivalent_to": "bclr BO,BI,BH" }, { "mnemonic": "bltlr", "equivalent_to": "bclr 12,0,0" }, { "mnemonic": "bnelr", "equivalent_to": "bclr 4,10,0" }, { "mnemonic": "bdnzlr", "equivalent_to": "bclr 16,0,0" }, { "mnemonic": "bcctr", "equivalent_to": "bcctr BO,BI,BH (LK=0)" }, { "mnemonic": "bcctrl", "equivalent_to": "bcctr BO,BI,BH (LK=1)" }, { "mnemonic": "bclr 4,6", "equivalent_to": "bclr 4,6,0" }, { "mnemonic": "bnelr cr2", "equivalent_to": "bclr 4,10,0" } ], "page_found": "Page 76 - 78" }, { "mnemonic": "bcctr", "architecture": "PowerISA", "full_name": "Branch Conditional to Count Register", "summary": "Branches to the address in the Count Register (CTR) if the condition is met. Used for computed jumps and switch statements.", "syntax": "bcctr BO, BI", "encoding": { "format": "XL-form", "binary_pattern": "19 | BO | BI | 000 | 528 | LK", "hex_opcode": "0x4C000420", "visual_parts": [ { "raw": "19", "clean": "19" }, { "raw": "BO", "clean": "BO" }, { "raw": "BI", "clean": "BI" }, { "raw": "000", "clean": "000" }, { "raw": "528", "clean": "528" }, { "raw": "LK", "clean": "LK" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "BO", "desc": "Branch Options" }, { "name": "BI", "desc": "CR Bit Index" } ], "pseudocode": "if (BO[0] = 0) then CTR ← CTR - 1; ctr_ok ← (BO[2] ∨ (CTR ≠ 0)); cond_ok ← (BO[4] ∨ (CR[BI] = BO[3])); if (ctr_ok ∧ cond_ok) then NIA ← CTR[0:61]; if (LK = 1) then LR ← CIA + 4;", "example": "bcctr 20, 0", "example_note": "Jump to address in CTR (bctr).", "extension": "Base", "description": "Conditionally branches to the address in the Count Register based on the Branch Options (BO) field and the state of the condition register bit selected by BI. The link register is optionally updated if LK=1. This instruction is commonly used for computed jumps and indirect branches in switch statements and virtual function calls.", "page_found": "Page 77", "special_registers": "CTR", "programming_notes": "When LK=1, the address of the next sequential instruction is placed in LR, making this a subroutine call. Use blr to return.\nCTR is decremented before the branch condition is tested; the branch is taken only if the combined CTR-and-condition test passes. Do not use this instruction inside a loop that also modifies CTR." }, { "mnemonic": "bpermd", "architecture": "PowerISA", "full_name": "Bit Permute Doubleword", "summary": "Permutes bits from RS based on the index values in RB. Highly optimized for bit shuffling.", "syntax": "bpermd RA, RS, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 252 | /", "hex_opcode": "0x7C0001F8", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "252", "clean": "252" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RA", "desc": "Target Register" }, { "name": "RS", "desc": "Source Register (Data)" }, { "name": "RB", "desc": "Permute Control Byte Selects" } ], "pseudocode": "for i in 0 to 7 do; index ← RB[i*8+2:i*8+7]; if (index < 64) then RA[i] ← RS[index]; else RA[i] ← 0;", "example": "bpermd r3, r4, r5", "example_note": "Complex bit permutation.", "extension": "Base", "description": "Permutes the bits of RS according to bit indices specified in RB, placing the result in RA. Each byte of RB contains a 6-bit index (0-63) that selects which bit from RS to place at that bit position in RA. This is a Base-category scalar instruction with no CR or XER updates.", "programming_notes": "The fact that the permuted bit is 0 if the corresponding index value exceeds 63 permits the permuted bits to be selected from a 128-bit quantity, using a single index register.", "page_found": "Page 140 - 142" }, { "mnemonic": "cfuged", "architecture": "PowerISA", "full_name": "Centrifuge Doubleword", "summary": "Separates bits of the source register into two groups based on a mask (Power10 Scalar).", "syntax": "cfuged RA, RS, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 68 | /", "hex_opcode": "0x7C0001B8", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "68", "clean": "68" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "RS", "desc": "Source" }, { "name": "RB", "desc": "Mask" } ], "extension": "Base", "description": "Centrifuges a 64-bit doubleword by separating bits according to a mask RB, moving masked bits to the low order of the result and unmasked bits to the high order (Power10 Scalar). The result is placed in RA. No CR, XER, or FPSCR fields are affected.", "pseudocode": "do_mask ← RB; result_low ← []; result_high ← []; j_low ← 0; j_high ← 0; for i in 0 to 63 do; if (do_mask[i] = 1) then result_low[j_low] ← RS[i]; j_low ← j_low + 1; else result_high[j_high] ← RS[i]; j_high ← j_high + 1; RA ← result_low || result_high;", "page_found": "Page 141", "programming_notes": "The cfuged instruction is useful for counting leading zeros in a doubleword value, but only considering the bits that are set to 1 in a mask. Ensure the mask register (RB) has bits set where you want to consider leading zeros in the source register (RS). The result is zero-extended to 64 bits before being stored in the destination register (RA). This instruction operates at user privilege level and does not generate exceptions under normal conditions.", "example": "cfuged r4, r3, r5" }, { "mnemonic": "pdepd", "architecture": "PowerISA", "full_name": "Parallel Bits Deposit Doubleword", "summary": "Deposits bits from RS to RA under control of mask RB (Scalar).", "syntax": "pdepd RA, RS, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 196 | /", "hex_opcode": "0x7C000138", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "196", "clean": "196" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "RS", "desc": "Source" }, { "name": "RB", "desc": "Mask" } ], "extension": "Base", "description": "Deposits bits from RS into RA at positions specified by the mask RB (Power10 Scalar). Bits set to 1 in RB indicate positions where bits from RS are placed in RA; bits set to 0 in RB receive zeros. No CR, XER, or FPSCR fields are affected.", "pseudocode": "mask ← RB; result ← [0]*64; src_idx ← 0; for i in 0 to 63 do; if (mask[i] = 1) then result[i] ← RS[src_idx]; src_idx ← src_idx + 1; RA ← result;", "page_found": "Page 142", "programming_notes": "The pdepd instruction is useful for selectively depositing bits from one register into another based on a mask. Ensure that the source and destination registers are properly aligned to avoid unexpected behavior. This instruction operates at user privilege level, but care must be taken with the mask to prevent unintended data corruption.", "example": "pdepd r4, r3, r5" }, { "mnemonic": "pextd", "architecture": "PowerISA", "full_name": "Parallel Bits Extract Doubleword", "summary": "Extracts bits from a source register based on a mask and places them into the target register.", "syntax": "pextd RA, RS, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 132 | /", "hex_opcode": "0x7C000178", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "132", "clean": "132" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "RS", "desc": "Source" }, { "name": "RB", "desc": "Mask" } ], "extension": "Base", "description": "The contents of the bits in register RS corresponding to bits in mask containing a 1 are packed into an n-bit value. The extracted value is placed into register RA.", "pseudocode": "result ← 0\nmask ← (RB)\nm ← 0\nk ← 0\ndo while (m < 64) \n if ((RB)63-m == 1) then do\n result63-k ← (RS)63-m\n k ← k + 1\n end\n m ← m + 1\nend\nRA ← result", "page_found": "Page 141 - 142", "programming_notes": "The pextd instruction is useful for extracting and packing bits from a source register based on a mask. Ensure the mask register (RB) has bits set to 1 where you want to extract corresponding bits from the source register (RS). The operation is performed in little-endian order, so the least significant bit of the result corresponds to the first bit set in the mask. This instruction operates at user privilege level and does not generate exceptions for normal use cases.", "example": "pextd r4, r3, r5" }, { "mnemonic": "cntlzdm", "architecture": "PowerISA", "full_name": "Count Leading Zeros Doubleword under Mask", "summary": "Counts leading zeros in RS, but only considering bits set in mask RB.", "syntax": "cntlzdm RA, RS, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 59 | /", "hex_opcode": "0x7C000076", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "59", "clean": "59" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "RS", "desc": "Source" }, { "name": "RB", "desc": "Mask" } ], "extension": "Base", "description": "Counts the number of leading zeros in RS considering only the bit positions set to 1 in the mask RB (Power10 Scalar). The count is placed in RA. No CR, XER, or FPSCR fields are affected.", "pseudocode": "mask ← RB; masked_value ← RS ∧ mask; if (masked_value = 0) then RA ← 64; else count ← 0; for i in 0 to 63 do; if (masked_value[i] = 1) then break; count ← count + 1; RA ← count;", "page_found": "Page 140", "programming_notes": "The cntlzdm instruction is useful for counting leading zeros in a doubleword while considering only the bits that are set to 1 in a mask. Ensure that both the source and mask registers are correctly aligned and that the mask register has at least one bit set to 1 to avoid undefined behavior. This instruction operates at user privilege level and does not generate exceptions under normal conditions, but it may incur performance penalties on processors without hardware support for this operation.", "example": "cntlzdm r4, r3, r5" }, { "mnemonic": "cnttzdm", "architecture": "PowerISA", "full_name": "Count Trailing Zeros Doubleword under Mask", "summary": "Counts trailing zeros in RS, but only considering bits set in mask RB.", "syntax": "cnttzdm RA, RS, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 571 | /", "hex_opcode": "0x7C000476", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "571", "clean": "571" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "RS", "desc": "Source" }, { "name": "RB", "desc": "Mask" }, { "name": "RT", "desc": "Target General Purpose Register" } ], "extension": "Base", "special_registers": "CR0, XER", "page_found": "Page 1434 - 1435", "description": "Counts the number of trailing zeros in RS considering only the bit positions set to 1 in the mask RB (Power10 Scalar). The count is placed in RA. No CR, XER, or FPSCR fields are affected.", "pseudocode": "mask ← RB; masked_value ← RS ∧ mask; if (masked_value = 0) then RA ← 64; else count ← 0; for i in 63 downto 0 do; if (masked_value[i] = 1) then break; count ← count + 1; RA ← count;", "programming_notes": "The cnttzdm instruction is useful for counting trailing zeros in a doubleword while applying a mask. Ensure that the mask register (RB) has bits set to 1 where you want to consider the corresponding bits in the source register (RS). The result is zero-extended to 64 bits before being stored in the destination register (RA). This instruction operates at user privilege level and does not generate any exceptions under normal conditions. Performance may vary based on the distribution of zeros and ones in the registers.", "example": "cnttzdm r4, r3, r5" }, { "mnemonic": "crc32b", "architecture": "PowerISA", "full_name": "Cyclic Redundancy Check 32-bit Byte", "summary": "Accumulates a CRC32 checksum using the low byte of RS.", "syntax": "crc32b RA, RS", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | 0 | 522 | /", "hex_opcode": "0x7C00020A", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "0", "clean": "0" }, { "raw": "522", "clean": "522" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target/Accumulator" }, { "name": "RS", "desc": "Data" } ], "extension": "Base", "description": "Accumulates a 32-bit CRC checksum using the low byte (bits 56-63) of RS, with the running CRC value in RA. The updated CRC result is written to RA. This is a Base-category instruction with no CR, XER, or FPSCR updates.", "pseudocode": "byte_val ← RS[56:63]; crc ← RA ⊕ (byte_val || [0]*24); for i in 0 to 7 do; if (crc[31] = 1) then crc ← (crc << 1) ⊕ 0x04C11DB7; else crc ← crc << 1; crc ← crc ∧ 0xFFFFFFFF; RA ← crc;", "example": "crc32b r4, r3" }, { "mnemonic": "crc32h", "architecture": "PowerISA", "full_name": "Cyclic Redundancy Check 32-bit Halfword", "summary": "Accumulates a CRC32 checksum using the low halfword of RS.", "syntax": "crc32h RA, RS", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | 0 | 586 | /", "hex_opcode": "0x7C00024A", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "0", "clean": "0" }, { "raw": "586", "clean": "586" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target/Accumulator" }, { "name": "RS", "desc": "Data" } ], "extension": "Base", "description": "Accumulates a 32-bit CRC checksum using the low halfword (bits 48-63) of RS, with the running CRC value in RA. The updated CRC result is written to RA. This is a Base-category instruction with no CR, XER, or FPSCR updates.", "pseudocode": "halfword_val ← RS[48:63]; crc ← RA ⊕ (halfword_val || [0]*16); for i in 0 to 15 do; if (crc[31] = 1) then crc ← (crc << 1) ⊕ 0x04C11DB7; else crc ← crc << 1; crc ← crc ∧ 0xFFFFFFFF; RA ← crc;", "example": "crc32h r4, r3" }, { "mnemonic": "crc32w", "architecture": "PowerISA", "full_name": "Cyclic Redundancy Check 32-bit Word", "summary": "Accumulates a CRC32 checksum using the word in RS.", "syntax": "crc32w RA, RS", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | 0 | 650 | /", "hex_opcode": "0x7C00028A", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "0", "clean": "0" }, { "raw": "650", "clean": "650" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target/Accumulator" }, { "name": "RS", "desc": "Data" } ], "extension": "Base", "description": "Accumulates a CRC32 checksum by processing the 32-bit word in RS using the Castagnoli polynomial. The result is XORed with the accumulator in RA and stored back to RA. This instruction is part of the Base extension and does not affect condition registers or status fields.", "pseudocode": "RA ← CRC32(RA, RS[32:63])", "example": "crc32w r4, r3" }, { "mnemonic": "crc32d", "architecture": "PowerISA", "full_name": "Cyclic Redundancy Check 32-bit Doubleword", "summary": "Accumulates a CRC32 checksum using the doubleword in RS.", "syntax": "crc32d RA, RS", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | 0 | 714 | /", "hex_opcode": "0x7C0002CA", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "0", "clean": "0" }, { "raw": "714", "clean": "714" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target/Accumulator" }, { "name": "RS", "desc": "Data" } ], "extension": "Base", "description": "Accumulates a CRC32 checksum by processing the 64-bit doubleword in RS using the Castagnoli polynomial. The result is XORed with the accumulator in RA and stored back to RA. This instruction is part of the Base extension and does not affect condition registers or status fields.", "pseudocode": "RA ← CRC32(RA, RS[0:63])", "example": "crc32d r4, r3" }, { "mnemonic": "pli", "architecture": "PowerISA", "full_name": "Prefixed Load Immediate", "summary": "Loads a 34-bit signed immediate into a register. (Replaces multiple 'lis/ori' instructions).", "syntax": "pli RT, SI34", "encoding": { "format": "MLS:D-form", "binary_pattern": "1 | 2 | R | 0 | D0 | 14 | RT | 0 | D1", "hex_opcode": "0x0400000038000000", "visual_parts": [ { "raw": "000001", "clean": "000001" }, { "raw": "10", "clean": "10" }, { "raw": "0", "clean": "0" }, { "raw": "...", "clean": "..." }, { "raw": "14", "clean": "14" }, { "raw": "RT", "clean": "RT" }, { "raw": "...", "clean": "..." } ], "length": "64", "bit_positions": "0:5 | 6:7 | 8 | 9:13 | 14:31 | 32:37 | 38:42 | 43:47 | 48:63" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "SI34", "desc": "Immediate" } ], "extension": "Prefixed", "description": "Loads a 34-bit signed immediate value into GPR RT, replacing the need for multiple lis/ori instructions. This is a prefixed instruction (2 words / 64 bits total) where the prefix encodes bits 0-17 and the main instruction encodes bits 18-33 of the immediate. No condition registers or status fields are affected.", "pseudocode": "RA ← SI34 (sign-extended to 64 bits)", "page_found": "Page 109", "programming_notes": "The pli instruction is used to load an immediate value directly into a target register. This is useful for initializing registers with constants or small values. Ensure the immediate value fits within the 16-bit signed integer range to avoid overflow issues.", "example": "pli r3, 16" }, { "mnemonic": "xxpermx", "architecture": "PowerISA", "full_name": "VSX Vector Permute Extended", "summary": "Permutes bytes from two source vectors using a control vector and a 3-bit selector.", "syntax": "xxpermx XT, XA, XB, XC, UIM", "encoding": { "format": "XX4-form", "binary_pattern": "1 | 8 | 0 | / | 60 | XT | XA | XB | XC | UIM", "hex_opcode": "0x0500000088000000", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "XC", "clean": "XC" }, { "raw": "UIM", "clean": "UIM" }, { "raw": "...", "clean": "..." } ], "length": "64", "bit_positions": "0:5 | 6:8 | 9 | 10:31 | 32:37 | 38:42 | 43:47 | 48:52 | 53:57 | 58:63" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" }, { "name": "XC", "desc": "Control" }, { "name": "UIM", "desc": "Selector" }, { "name": "VX1", "desc": "Target Vector Register" }, { "name": "VX2", "desc": "Source Vector Register" }, { "name": "VX3", "desc": "Source Vector Register" } ], "extension": "VSX", "description": "Permutes bytes from source vectors XA and XB using byte indices in XC, with a 3-bit UIM field selecting between different permutation modes. The permutation control bytes in XC determine which source byte maps to each position in XT. This VSX instruction does not affect condition registers or status fields.", "pseudocode": "for i in 0 to 15:\n idx ← (XC[8*i:8*i+7] & 0x1F) | (UIM << 5)\n if idx < 16:\n XT[8*i:8*i+7] ← XA[8*idx:8*idx+7]\n else:\n XT[8*i:8*i+7] ← XB[8*(idx-16):8*(idx-16)+7]", "programming_notes": "The following is an example of emulating 256-bit xxperm, where a 256-bit vector is contained in a pair of VSRs. The instruction is capable of emulating up to a 2048-bit xxperm.", "page_found": "Page 959 - 960", "special_registers": "MSR", "example": "xxpermx vs1, vs2, vs3, vs4, uim" }, { "mnemonic": "xxblendvb", "architecture": "PowerISA", "full_name": "VSX Vector Blend Variable Byte", "summary": "Selects bytes from XA or XB based on the MSB of bytes in XC.", "syntax": "xxblendvb XT, XA, XB, XC", "encoding": { "format": "XX4-form", "binary_pattern": "60 | XT | XA | XB | XC | 33", "hex_opcode": "0x0500000084000000", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "XC", "clean": "XC" }, { "raw": "33", "clean": "33" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" }, { "name": "XC", "desc": "Control" } ], "extension": "VSX", "description": "For xxblendvb, the contents of VSR[XT] are determined by the contents of VSR[XC]. If bit 0 of byte element i in VSR[XC] is 0, then byte element i of VSR[XT] is taken from VSR[XA]; otherwise, it is taken from VSR[XB].", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\ndo i = 0 to 15\n if VSR[32×CX+C].byte[i].bit[0]=0 then\n VSR[32×TX+T].byte[i] ←VSR[32*AX+A].byte[i]\n else\n VSR[32×TX+T].byte[i] ←VSR[32*BX+B].byte[i]\nend", "page_found": "Page 947 - 948", "special_registers": "MSR", "programming_notes": "The xxblendvb instruction blends bytes from two source vectors based on a control vector. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid an exception. The instruction operates on 16-byte vectors, and each byte is independently selected from either of the two source vectors based on the corresponding bit in the control vector. This instruction is useful for conditional data merging but requires careful handling of the control vector to achieve the desired result.", "example": "xxblendvb vs1, vs2, vs3, vs4" }, { "mnemonic": "xxblendvh", "architecture": "PowerISA", "full_name": "VSX Vector Blend Variable Halfword", "summary": "Selects halfwords from XA or XB based on the MSB of halfwords in XC.", "syntax": "xxblendvh XT, XA, XB, XC", "encoding": { "format": "XX4-form", "binary_pattern": "60 | XT | XA | XB | XC | 34", "hex_opcode": "0x0500000084000010", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "XC", "clean": "XC" }, { "raw": "34", "clean": "34" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" }, { "name": "XC", "desc": "Control" }, { "name": "VRT", "desc": "Target VSX Register" }, { "name": "VRA", "desc": "Source VSX Register" }, { "name": "VRB", "desc": "Source VSX Register" } ], "extension": "VSX", "description": "For xxblendvh, the contents of each halfword in the target vector are selected from either the first or second source vector based on the corresponding bit in the control vector.", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\ndo i = 0 to 7\n if VSR[32×CX+C].hword[i].bit[0]=0 then\n VSR[32×TX+T].hword[i] ←VSR[32×AX+A].hword[i]\n else\n VSR[32×TX+T].hword[i] ←VSR[32×BX+B].hword[i]\nend", "page_found": "Page 948 - 949", "special_registers": "MSR", "programming_notes": "Ensure VSX is enabled by checking and setting the appropriate bit in the MSR register. This instruction blends halfwords from two source vectors into a target vector based on a control vector's bits. Be cautious of alignment requirements for vector registers to avoid undefined behavior.", "example": "xxblendvh vs1, vs2, vs3, vs4" }, { "mnemonic": "xxblendvw", "architecture": "PowerISA", "full_name": "VSX Vector Blend Variable Word", "summary": "Selects words from XA or XB based on the MSB of words in XC.", "syntax": "xxblendvw XT, XA, XB, XC", "encoding": { "format": "XX4-form", "binary_pattern": "60 | XT | XA | XB | XC | 35", "hex_opcode": "0x0500000084000020", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "XC", "clean": "XC" }, { "raw": "35", "clean": "35" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:31", "length": "32" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" }, { "name": "XC", "desc": "Control" } ], "extension": "VSX", "description": "Selects whole words from XA or XB based on the MSB of the corresponding word in control register XC. If the MSB of a word in XC is 1, the word from XB is selected; otherwise the word from XA is selected. This VSX instruction does not affect condition registers or status fields.", "pseudocode": "for i in 0 to 3:\n if XC[32*i] == 1:\n XT[32*i:32*i+31] ← XB[32*i:32*i+31]\n else:\n XT[32*i:32*i+31] ← XA[32*i:32*i+31]", "page_found": "Page 949", "special_registers": "MSR", "programming_notes": "The xxblendvw instruction is commonly used for conditional blending of word elements from two source vectors based on a control vector. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. This instruction operates on 16-word elements, so alignment and ordering of input registers must be correct to prevent data corruption or incorrect results.", "example": "xxblendvw vs1, vs2, vs3, vs4" }, { "mnemonic": "xxblendvd", "architecture": "PowerISA", "full_name": "VSX Vector Blend Variable Doubleword", "summary": "Selects doublewords from XA or XB based on the MSB of doublewords in XC.", "syntax": "xxblendvd XT, XA, XB, XC", "encoding": { "format": "XX4-form", "binary_pattern": "60 | XT | XA | XB | XC | 36", "hex_opcode": "0x0500000084000030", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "XC", "clean": "XC" }, { "raw": "36", "clean": "36" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" }, { "name": "XC", "desc": "Control" }, { "name": "VRT", "desc": "Target VSX Register" }, { "name": "VRA", "desc": "Source VSX Register" }, { "name": "VRB", "desc": "Source VSX Register" } ], "extension": "VSX", "page_found": "Page 1380 - 1381", "description": "Selects whole doublewords from XA or XB based on the MSB of the corresponding doubleword in control register XC. If the MSB of a doubleword in XC is 1, the doubleword from XB is selected; otherwise the doubleword from XA is selected. This VSX instruction does not affect condition registers or status fields.", "programming_notes": "The xxblendvd instruction is useful for selectively blending elements from two source vectors (A and B) into a destination vector based on control bits derived from a third vector (C). Ensure that all input vectors are properly aligned to avoid alignment faults. This instruction operates at the user privilege level and may raise exceptions if the immediate field value exceeds valid range or if there are invalid operand types.", "pseudocode": "for i in 0 to 1:\n if XC[64*i] == 1:\n XT[64*i:64*i+63] ← XB[64*i:64*i+63]\n else:\n XT[64*i:64*i+63] ← XA[64*i:64*i+63]", "example": "xxblendvd vs1, vs2, vs3, vs4" }, { "mnemonic": "lxvwsx", "architecture": "PowerISA", "full_name": "Load VSX Vector Word and Splat Indexed", "summary": "Loads a 32-bit word and replicates it across the vector.", "syntax": "lxvwsx XT, RA, RB", "encoding": { "format": "XX1-form", "binary_pattern": "31 | XT | RA | RB | 364", "hex_opcode": "0x7C0002D8", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "XT", "clean": "XT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "364", "clean": "364" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "VSX", "description": "Loads a 32-bit word from memory at address RA + RB, then replicates it across all four 32-bit word positions in the target VSX register XT. This VSX instruction does not affect condition registers or status fields.", "pseudocode": "EA ← RA + RB\nword ← [EA:EA+3]\nfor i in 0 to 3:\n XT[32*i:32*i+31] ← word", "page_found": "Page 619", "special_registers": "MSR", "programming_notes": "The lxvwsx instruction is commonly used for loading a word from memory and replicating it across all elements of a VSX vector register. Ensure that the appropriate privilege levels (MSR.VSX or MSR.VEC) are enabled to avoid exceptions. The instruction requires 4-byte alignment for the memory address; unaligned accesses may result in performance penalties or exceptions depending on the system configuration.", "example": "lxvwsx vs1, r4, r5" }, { "mnemonic": "mtvsrws", "architecture": "PowerISA", "full_name": "Move To VSR Word and Splat", "summary": "Moves a 32-bit word from a GPR and replicates it across the vector.", "syntax": "mtvsrws XT, RA", "encoding": { "format": "XX1-form", "binary_pattern": "31 | XT | RA | 0 | 243", "hex_opcode": "0x7C000326", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "XT", "clean": "XT" }, { "raw": "RA", "clean": "RA" }, { "raw": "0", "clean": "0" }, { "raw": "243", "clean": "243" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "RA", "desc": "Source GPR" } ], "extension": "VSX", "description": "Moves the low 32 bits from GPR RA into a VSX register, then replicates that 32-bit word across all four 32-bit word positions in XT. This VSX instruction does not affect condition registers or status fields.", "pseudocode": "word ← RA[32:63]\nfor i in 0 to 3:\n XT[32*i:32*i+31] ← word", "page_found": "Page 161", "special_registers": "MSR", "programming_notes": "The mtvsrws instruction is used to move the upper 32 bits of a general-purpose register into the first word element of a vector-scalar register and splat it across the remaining elements. Ensure that the VSX or Vector facility is enabled in the MSR before using this instruction, otherwise, an exception will be raised. This instruction treats the operation as a Vector instruction, so developers should consider resource availability accordingly.", "example": "mtvsrws vs1, r4" }, { "mnemonic": "xsmaxcdp", "architecture": "PowerISA", "full_name": "VSX Scalar Maximum Type-C Double-Precision", "summary": "Computes the maximum of two double-precision floating-point values and stores the result in a vector scalar register.", "syntax": "xsmaxcdp XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "60 | XT | XA | XB | 152", "hex_opcode": "0xF0000400", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "152", "clean": "152" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "Computes the maximum of two double-precision floating-point scalar values and stores the result in the target VSR. The operation follows the IEEE 754 maximum semantics where positive zero is greater than negative zero, and any comparison with NaN returns NaN. This instruction is part of the VSX category and does not set CR or XER flags.", "pseudocode": "XT_dp ← maxc_dp(XA_dp, XB_dp)", "special_registers": "FPSCR (FX, VXSNAN)", "programming_notes": "xsmaxcdp can be used to implement the C/C++/Java conditional operation (x>y)?x:y for single-precision and double-precision arguments. Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.", "page_found": "Page 790 - 791", "example": "xsmaxcdp vs1, vs2, vs3" }, { "mnemonic": "xsmincdp", "architecture": "PowerISA", "full_name": "VSX Scalar Minimum Type-C Double-Precision", "summary": "Computes the minimum of two double-precision floating-point numbers and handles NaNs according to Type-C rules.", "syntax": "xsmincdp XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "60 | XT | XA | XB | 153", "hex_opcode": "0xF0000440", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "153", "clean": "153" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "If either src1 or src2 is a NaN, result is src2. Otherwise, if src1 is less than src2, result is src1. Otherwise, result is src2. The contents of doubleword 0 of VSR[XT] are set to the value result. The contents of doubleword 1 of VSR[XT] are set to 0.", "pseudocode": "if 'xsmincdp' then\n src1 <- VSR[XA]\n src2 <- VSR[XB]\n if src2 is QNaN or SNaN then\n fx(VXSNAN)\n else if src2 is -Infinity then\n T(src2) <- src2\n else if src2 is +Zero then\n T(src2) <- src2\n else if src2 is +NZF then\n T(src2) <- M(src1, src2)\n else if src2 is +Infinity then\n T(src2) <- src2\n VSR[XT] <- T(src2)", "special_registers": "FPSCR (FX, VXSNAN)", "programming_notes": "xsmincdp can be used to implement the C/C++/Java conditional operator (x (FRB) then\n CR[BF] ← 0b0100\nelse\n CR[BF] ← 0b0010", "example": "fcmpu cr0, f1, f2", "example_note": "Compare f1 vs f2.", "extension": "Floating-Point", "description": "Compares two floating-point registers (FRA and FRB) and writes the result (less-than, equal, greater-than, or unordered) into the specified CR field (BF). Unlike fcmpo, this instruction does not trap on signaling NaN operands. The FPSCR may record VXCC (invalid operation) for signaling NaNs.", "special_registers": "FPSCR, CR", "page_found": "Page 214 - 216", "programming_notes": "The fcmpu instruction is commonly used for unordered floating-point comparisons, which are useful in scenarios where NaN values need to be handled gracefully. Be cautious with signaling NaNs (SNaNs), as they can trigger exceptions and set the VXSNAN flag. Ensure that the FPSCR and CR registers are properly managed to handle comparison results and exceptions correctly." }, { "mnemonic": "fctiw", "architecture": "PowerISA", "full_name": "Floating Convert with round Double-Precision To Signed Word format", "summary": "Converts a float to a 32-bit signed integer (using the current rounding mode) and stores it in the lower half of the FPR.", "syntax": "fctiw FRT,FRB", "encoding": { "format": "X-form", "binary_pattern": "63 | FRT | / | FRB | 14 | Rc", "hex_opcode": "0xFC00001C", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "/", "clean": "/" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "14", "clean": "14" }, { "raw": "Rc", "clean": "Rc" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target FPR" }, { "name": "FRB", "desc": "Source FPR" }, { "name": "RT", "desc": "Target Floating Point Register" }, { "name": "RA", "desc": "Source Floating Point Register" } ], "pseudocode": "round_mode ← FPSCRRN\ntgt_precision ← '32-bit signed integer'\n\nsign ← (FRB)0\nif (FRB)1:11 = 2047 and (FRB)12:63 = 0 then goto Infinity Operand\nif (FRB)1:11 = 2047 and (FRB)12 = 0 then goto SNaN Operand\nif (FRB)1:11 = 2047 and (FRB)12 = 1 then goto QNaN Operand\nif (FRB)1:11 > 1086 then goto Large Operand\n\nif (FRB)1:11 > 0 then exp ← (FRB)1:11 - 1023 /* exp - bias */\nif (FRB)1:11 = 0 then exp ← -1022\nif (FRB)1:11 > 0 then frac0:64 ← 0b01 || (FRB)12:63 || 110 /* normal */\nif (FRB)1:11 = 0 then frac0:64 ← 0b00 || (FRB)12:63 || 110 /* denormal */\n\nrbit || xbit ← 0b00\nfor i=1,63-exp /* do the loop 0 times if exp = 63 */\n frac0:64 || rbit || xbit ← 0b0 || frac0:64 || (rbit | xbit)\nend\n\nFRT ← Round Integer(sign, frac0:64, gbit, rbit, xbit, round_mode)", "example": "fctiw f1, f2", "example_note": "Convert float f2 to int in f1.", "extension": "Floating-Point", "description": "The instruction converts the double-precision floating-point value in FRB to a signed word using the specified rounding mode. If the result is out of range, it saturates to the maximum or minimum signed integer value.", "special_registers": "FPSCR, (FR, FI, FX, XX, VXSNAN, VXCVI), CR1, (if, Rc=1), CR0", "page_found": "Page 208 - 210", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes." }, { "mnemonic": "isel", "architecture": "PowerISA", "full_name": "Integer Select", "summary": "Conditionally copies RA or RB to RT based on a CR bit. (Equivalent to C ternary operator 'cond ? a : b').", "syntax": "isel RT, RA, RB, BC", "encoding": { "format": "A-form", "binary_pattern": "31 | RT | RA | RB | BC | 15 | /", "hex_opcode": "0x7C00001E", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "BC", "clean": "BC" }, { "raw": "15", "clean": "15" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:30 | 31" }, "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "RA", "desc": "Source (If True) - 0 means 0" }, { "name": "RB", "desc": "Source (If False)" }, { "name": "BC", "desc": "CR Bit Index (Condition)" }, { "name": "CR", "desc": "Condition Register Field" } ], "pseudocode": "BIT ← CR[BC]\nif BIT = 1 then\n RT ← (RA)\nelse\n RT ← (RB)", "example": "isel r3, r4, r5, 2", "example_note": "r3 = (CR.eq) ? r4 : r5", "extension": "Base", "description": "Conditionally selects between RA and RB based on the value of a single bit in the Condition Register, writing the result to RT. If the CR bit BC is 1, RT ← RA (or 0 if RA=0); otherwise RT ← RB. This provides a branch-free ternary operation.", "extended_mnemonics": [ { "mnemonic": "iselgt", "equivalent_to": "isel RT,RA,RB,1" }, { "mnemonic": "iseleq", "equivalent_to": "isel RT,RA,RB,2" }, { "mnemonic": "isellt", "equivalent_to": "isel RT,RA,RB,0" } ], "page_found": "Page 131 - 132", "special_registers": "CR0, CR1-CR7", "programming_notes": "isel is used for conditional moves based on the condition register." }, { "mnemonic": "icbi", "architecture": "PowerISA", "full_name": "Instruction Cache Block Invalidate", "summary": "Invalidates the instruction cache block associated with the address. Critical for self-modifying code or JITs.", "syntax": "icbi RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | / | RA | RB | 982 | /", "hex_opcode": "0x7C0007AC", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "982", "clean": "982" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Base Address" }, { "name": "RB", "desc": "Index Address" } ], "pseudocode": "EA ← (RA) + (RB)\nInvalidate_ICacheBlock(EA)", "example": "icbi 0, r3", "example_note": "Invalidate instruction cache at r3.", "extension": "Base", "description": "Invalidates the instruction cache block that contains the address RA + RB, forcing subsequent instruction fetches from that block to reload from lower cache levels or memory. Essential for self-modifying code and JIT compilers. May affect performance on some implementations.", "page_found": "Page 1027", "programming_notes": "Use icbi to ensure that changes to executable code in memory are reflected in the instruction cache. This is crucial after modifying code at runtime. Ensure the address is properly aligned; typically, block boundaries align with cache line sizes. This instruction operates at user privilege level and may raise an exception if the address is invalid or access is denied." }, { "mnemonic": "isync", "architecture": "PowerISA", "full_name": "Instruction Synchronize", "summary": "Ensures that all instructions preceding the isync instruction have completed before it completes, and that no subsequent instructions are initiated until after the isync instruction completes.", "syntax": "isync", "encoding": { "format": "XL-form", "binary_pattern": "19 | 00000 | 00000 | 00000 | 150 | /", "hex_opcode": "0x4C00012C", "visual_parts": [ { "raw": "19", "clean": "19" }, { "raw": "00000", "clean": "00000" }, { "raw": "00000", "clean": "00000" }, { "raw": "00000", "clean": "00000" }, { "raw": "150", "clean": "150" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [], "pseudocode": "ContextSynchronize()", "example": "isync", "example_note": "Refetch instructions.", "extension": "Base", "description": "Executing an isync instruction ensures that all instructions preceding the isync instruction have completed before the isync instruction completes, and that no subsequent instructions are initiated until after the isync instruction completes. It also ensures that all instruction cache block invalidations caused by icbi instructions preceding the isync instruction have been performed with respect to the processor executing the isync instruction, and then causes any prefetched instructions to be discarded.", "programming_notes": "Except as described in the preceding sentence, the isync instruction may complete before storage accesses associated with instructions preceding the isync instruction have been performed.", "page_found": "Page 1049 - 1050" }, { "mnemonic": "mcrf", "architecture": "PowerISA", "full_name": "Move Condition Register Field", "summary": "Copies the contents of one Condition Register field to another. Used to save comparison results.", "syntax": "mcrf BF, BFA", "encoding": { "format": "XL-form", "binary_pattern": "00000 | CRFD | CRFS | 00000 | 00000 | 00000 | 00000 | 00000", "hex_opcode": "0x4C000000", "visual_parts": [ { "raw": "19", "clean": "19" }, { "raw": "BF", "clean": "BF" }, { "raw": "/", "clean": "/" }, { "raw": "BFA", "clean": "BFA" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "16", "clean": "16" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:8 | 9:10 | 11:13 | 14:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "BF", "desc": "Target Field (0-7)" }, { "name": "BFA", "desc": "Source Field (0-7)" }, { "name": "CRFD", "desc": "Destination Condition Register Field" }, { "name": "CRFS", "desc": "Source Condition Register Field" } ], "pseudocode": "CR4×BF+32:4×BF+35 ← CR4×BFA+32:4×BFA+35", "example": "mcrf cr0, cr7", "example_note": "Copy result from CR7 to CR0.", "extension": "Base", "description": "The contents of Condition Register field BFA are copied to Condition Register field BF.", "special_registers": "CR0, CR1-CR7", "page_found": "Page 80 - 82", "programming_notes": "Use mcrf to copy condition register fields, ensuring BFA and BF are valid. This instruction operates at user privilege level and does not raise exceptions under normal conditions." }, { "mnemonic": "mfcr", "architecture": "PowerISA", "full_name": "Move From Condition Register", "summary": "Copies the entire 32-bit Condition Register into a General Purpose Register.", "syntax": "mfcr RT", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | 00000 | 00000 | 19 | /", "hex_opcode": "0x7C000026", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "00000", "clean": "00000" }, { "raw": "00000", "clean": "00000" }, { "raw": "19", "clean": "19" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RT", "desc": "Target Register" } ], "pseudocode": "RT ← CR", "example": "mfcr r3", "example_note": "Save flags to r3.", "extension": "Base", "description": "Moves the entire 32-bit Condition Register into the target GPR. All eight 4-bit CR fields (CR0-CR7) are copied as a single 32-bit value. No condition register or status fields are modified by this operation.", "special_registers": "CR", "page_found": "Page 165 - 166", "programming_notes": "The mfcr instruction is commonly used to save the current state of the condition register for later use, such as before a function call or when implementing exception handling. It's important to note that this instruction does not affect any flags in the condition register itself; it merely copies its contents. Ensure that the target general-purpose register RT is properly aligned and accessible at the privilege level where the instruction is executed." }, { "mnemonic": "mtcrf", "architecture": "PowerISA", "full_name": "Move To Condition Register Fields", "summary": "Copies bits from a register into the Condition Register, updated only the fields specified by the mask (FXM).", "syntax": "mtcrf FXM, RS", "encoding": { "format": "XFX-form", "binary_pattern": "31 | RS | 0 | FXM | 144 | /", "hex_opcode": "0x7C000120", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "0", "clean": "0" }, { "raw": "FXM", "clean": "FXM" }, { "raw": "144", "clean": "144" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11 | 12:19 | 20:30 | 31", "length": "32" }, "operands": [ { "name": "FXM", "desc": "Field Mask (8 bits)" }, { "name": "RS", "desc": "Source Register" } ], "pseudocode": "do i = 0 to 7\n if FXM[i] = 1 then\n CR[4*i:4*i+3] ← RS[4*i:4*i+3]\nend do", "example": "mtcrf 0xFF, r3", "example_note": "Restore all CR fields from r3.", "extension": "Base", "description": "Moves bits from the source register (RS) into the Condition Register (CR), updating only the fields specified by the mask FXM. Each bit in FXM corresponds to one of the eight 4-bit CR fields; a 1 indicates that field should be updated. This instruction affects the CR as specified by the mask, with no other status register modifications.", "page_found": "Page 165", "special_registers": "CR", "programming_notes": "The mtcrf instruction is used to move specific fields of the Condition Register (CR) into general-purpose registers. It's important to note that if the SPR number is between 808 and 811, the instruction acts as a no-op. Ensure that the FXM field correctly specifies which CR fields to transfer to avoid unintended behavior." }, { "mnemonic": "xsaddqp", "architecture": "PowerISA", "full_name": "VSX Scalar Add Quad-Precision", "summary": "Adds two 128-bit Quad-Precision floating-point numbers held in VSX registers (pairs).", "syntax": "xsaddqp vD, vA, vB", "encoding": { "format": "X-form", "binary_pattern": "0 | VRT | VRA | VRB | RO | 11000000000000000000000000000000", "hex_opcode": "0xFC000008", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "4", "clean": "4" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "vD", "desc": "Target (128-bit)" }, { "name": "vA", "desc": "Source A" }, { "name": "vB", "desc": "Source B" }, { "name": "VRT", "desc": "Target Vector-Specific Register" }, { "name": "VRA", "desc": "Source Vector-Specific Register" }, { "name": "VRB", "desc": "Source Vector-Specific Register" }, { "name": "VT", "desc": "Target Vector Register" } ], "pseudocode": "FPR[vD:vD+1] ← quad_precision(FPR[vA:vA+1] + FPR[vB:vB+1])\nFPSCR ← updated with exception flags", "example": "xsaddqp v2, v3, v4", "example_note": "Scientific Quad-Float Add.", "extension": "VSX", "description": "Adds two 128-bit quad-precision floating-point numbers held in VSX register pairs and stores the result in another VSX register pair. The operation uses full precision during computation and rounds the result to quad-precision format. This instruction requires VSX support and updates FPSCR with exception flags as appropriate.", "special_registers": "vxisi_flag, vxsnan_flag", "page_found": "Page 655 - 656", "programming_notes": "The xsaddqp instruction is used for adding two quad-precision floating-point numbers. Ensure that the VSX feature is enabled by checking and setting MSR.VSX. Be aware of special cases like NaNs, which can set flags such as vxsnan_flag or vxisi_flag. The result is stored in VSR[VT+32], and proper rounding and exception handling are managed internally." }, { "mnemonic": "xsmulqp", "architecture": "PowerISA", "full_name": "VSX Scalar Multiply Quad-Precision", "summary": "Multiplies two quad-precision floating-point numbers and rounds the result to odd.", "syntax": "xsmulqp vD, vA, vB", "encoding": { "format": "X-form", "binary_pattern": "63 | FRT | FRA | FRB | 36 | Rc", "hex_opcode": "0xFC000048", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "36", "clean": "36" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Source A" }, { "name": "vB", "desc": "Source B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "pseudocode": "FPR[vD:vD+1] ← quad_precision_round_to_odd(FPR[vA:vA+1] × FPR[vB:vB+1])\nFPSCR ← updated with exception flags", "example": "xsmulqp v2, v3, v4", "example_note": "Scientific Quad-Float Multiply.", "extension": "VSX", "description": "Multiplies two 128-bit quad-precision floating-point numbers held in VSX register pairs and stores the result in another VSX register pair, rounding to odd. The operation computes the full product and rounds using the round-to-odd mode to ensure correct rounding behavior. This instruction requires VSX support and updates FPSCR with exception flags.", "special_registers": "vximz_flag, vxsnan_flag", "page_found": "Page 667 - 668", "programming_notes": "The xsmulqp instruction handles special cases like NaNs and infinities, setting flags accordingly. Ensure proper handling of these conditions to avoid unexpected results. The instruction operates at the VSX privilege level and may raise exceptions for invalid operations. Performance can vary based on input values and rounding modes." }, { "mnemonic": "xscvdpqp", "architecture": "PowerISA", "full_name": "VSX Scalar Convert Double-Precision to Quad-Precision format", "summary": "Converts a double-precision floating-point value to a quad-precision floating-point value.", "syntax": "xscvdpqp vD, vB", "encoding": { "format": "X-form", "binary_pattern": "0 | VRT | VRB | 11000000000000000000000000000000", "hex_opcode": "0xFC160688", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "vD", "clean": "vD" }, { "raw": "/", "clean": "/" }, { "raw": "vB", "clean": "vB" }, { "raw": "340", "clean": "340" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target (Quad)" }, { "name": "vB", "desc": "Source (Double)" }, { "name": "VRT", "desc": "Target Vector-Scalar Register" }, { "name": "VRB", "desc": "Source Vector-Scalar Register" } ], "pseudocode": "FPR[vD:vD+1] ← convert_to_quad_precision(FPR[vB])\nFPSCR ← updated with exception flags", "example": "xscvdpqp v2, v3", "example_note": "Promote Double to Quad.", "extension": "VSX", "description": "Converts a double-precision floating-point value held in a VSX register to quad-precision format and stores the result in a VSX register pair. The conversion is exact since double-precision has fewer significant bits than quad-precision. This instruction requires VSX support and updates FPSCR with exception flags as needed.", "special_registers": "FPSCR.FPRF, FPSCR.FX, FPSCR.VXSNAN, FPSCR.FR, FPSCR.FI", "page_found": "Page 830 - 831", "programming_notes": "This instruction is used to convert a double-precision floating-point number to a quad-precision format. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register, otherwise, an exception will be raised. Be cautious with signaling NaNs (SNaNs), as they are converted to quiet NaNs and may trigger exceptions based on the FPSCR settings." }, { "mnemonic": "dadd", "architecture": "PowerISA", "full_name": "Decimal Add", "summary": "Adds two 64-bit Decimal Floating Point (DFP) numbers. Used in financial calculations to avoid rounding errors.", "syntax": "dadd FRT,FRA,FRB", "encoding": { "format": "X-form", "binary_pattern": "59 | FRT | FRA | FRB | 2 | /", "hex_opcode": "0xEC000004", "visual_parts": [ { "raw": "59", "clean": "59" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "FRA", "clean": "FRA" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "2", "clean": "2" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target FPR" }, { "name": "FRA", "desc": "Source A" }, { "name": "FRB", "desc": "Source B" } ], "pseudocode": "FPR[FRT] ← DFP_add(FPR[FRA], FPR[FRB])\nFPSCR ← updated with exception flags", "example": "dadd f1, f2, f3", "example_note": "Financial Add.", "extension": "Decimal Floating-Point", "description": "Adds two 64-bit Decimal Floating Point (DFP) numbers held in FPRs and stores the result in another FPR. DFP arithmetic maintains decimal precision without binary rounding errors, making it essential for financial applications. This instruction updates FPSCR with exception flags and condition codes based on the result.", "special_registers": "FPSCR, CR1", "extended_mnemonics": [ "dadd." ], "page_found": "Page 238 - 240", "programming_notes": "The dadd instruction is used for adding two decimal floating-point numbers. Ensure that the source registers FRA and FRB are correctly aligned and contain valid decimal floating-point values. The result will be rounded according to the rounding mode specified in the FPSCR register's DRN field. Be aware of potential exceptions such as overflow or underflow, which may require handling in your code." }, { "mnemonic": "dmul", "architecture": "PowerISA", "full_name": "Decimal Multiply", "summary": "Multiplies the contents of two DFP registers and places the result in another DFP register.", "syntax": "dmul FRT,FRA,FRB", "encoding": { "format": "X-form", "binary_pattern": "0 | FRT | FRA | FRB | Rc | 0 | 0 | 0", "hex_opcode": "0xEC000044", "visual_parts": [ { "raw": "59", "clean": "59" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "FRA", "clean": "FRA" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "34", "clean": "34" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26 | 27:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target FPR" }, { "name": "FRA", "desc": "Source A" }, { "name": "FRB", "desc": "Source B" } ], "pseudocode": "FPR[FRT] ← DFP_multiply(FPR[FRA], FPR[FRB])\nFPSCR ← updated with exception flags\nif Rc = 1 then CR0 ← condition_code(FPR[FRT])", "example": "dmul f1, f2, f3", "example_note": "Financial Multiply.", "extension": "Decimal Floating-Point", "description": "Multiplies two 64-bit Decimal Floating Point (DFP) numbers held in FPRs and stores the result in another FPR. DFP multiplication preserves decimal precision required for financial calculations. The instruction can optionally update CR0 (via the dot form); FPSCR is always updated with exception flags and rounding information.", "special_registers": "FPSCR, CR1", "programming_notes": "dmul[q][.] are treated as Floating-Point instructions in terms of resource availability.", "page_found": "Page 241 - 242" }, { "mnemonic": "dqua", "architecture": "PowerISA", "full_name": "Decimal Quantize", "summary": "Adjusts the exponent of a DFP number to match a reference. Critical for aligning decimal points before addition.", "syntax": "dqua FRT,FRA,FRB,RMC", "encoding": { "format": "X-form", "binary_pattern": "0 | FRT | FRA | FRB | RMC | Rc | 3 | 21 | 23", "hex_opcode": "0xEC000006", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "FRA", "clean": "FRA" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "66", "clean": "66" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRA", "desc": "Source Value" }, { "name": "FRB", "desc": "Reference Exponent" }, { "name": "RMC", "desc": "Rounding Mode Control" } ], "pseudocode": "FPR[FRT] ← DFP_quantize(FPR[FRA], FPR[FRB], RMC)\nFPSCR ← updated with exception flags\nif Rc = 1 then CR0 ← condition_code(FPR[FRT])", "example": "dqua f1, f2, f3", "example_note": "Align decimal points.", "extension": "Decimal Floating-Point", "description": "Adjusts the exponent of a 64-bit DFP number to match a reference exponent, rounding the significand as needed according to the RMC control bits. This operation is essential for aligning decimal points before addition in financial calculations. The instruction can optionally update CR0 via the dot form; FPSCR is always updated with exception flags.", "special_registers": "FPSCR, FPRF, FR, FI, FX, XX, VXSNAN, VXCVI, CR1", "programming_notes": "DFP Quantize can be used to adjust one DFP value to a form having the same exponent as another DFP value. If the adjustment requires the significand to be shifted left and would cause overflow from the most significant digit, the result is a default QNaN.", "page_found": "Page 250 - 252", "extended_mnemonics": [ "dqua", "dqua." ] }, { "mnemonic": "vbrh", "architecture": "PowerISA", "full_name": "Vector Byte-Reverse Halfword", "summary": "Reverses bytes within each halfword (Endian Swap).", "syntax": "vbrh vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 0 | vB | 1606", "hex_opcode": "0x10000646", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1606", "clean": "1606" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" } ], "extension": "VMX (AltiVec)", "description": "Reverses the order of bytes within each halfword (16-bit element) of the source vector, effectively performing a 16-bit endianness swap. The operation processes all 8 halfwords in the 128-bit vector independently. This instruction requires VMX/AltiVec support and does not affect any status registers.", "pseudocode": "for i = 0 to 7 do\n VR[vD][i*16:i*16+15] ← reverse_bytes(VR[vB][i*16:i*16+15])\nend for", "example": "vbrh vd, vb" }, { "mnemonic": "vbrw", "architecture": "PowerISA", "full_name": "Vector Byte-Reverse Word", "summary": "Reverses bytes within each word.", "syntax": "vbrw vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 0 | vB | 1670", "hex_opcode": "0x10000686", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1670", "clean": "1670" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" } ], "extension": "VMX (AltiVec)", "description": "Reverses the byte order within each 32-bit word of the source vector and stores the result in the destination vector. This instruction operates on four words in parallel across the 128-bit vector. No condition flags are affected; this is a VMX/AltiVec instruction.", "pseudocode": "vD[0:31] ← vB[24:31] || vB[16:23] || vB[8:15] || vB[0:7]\nvD[32:63] ← vB[56:63] || vB[48:55] || vB[40:47] || vB[32:39]\nvD[64:95] ← vB[88:95] || vB[80:87] || vB[72:79] || vB[64:71]\nvD[96:127] ← vB[120:127] || vB[112:119] || vB[104:111] || vB[96:103]", "example": "vbrw vd, vb" }, { "mnemonic": "vbrd", "architecture": "PowerISA", "full_name": "Vector Byte-Reverse Doubleword", "summary": "Reverses bytes within each doubleword.", "syntax": "vbrd vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 0 | vB | 1734", "hex_opcode": "0x100006C6", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1734", "clean": "1734" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" } ], "extension": "VMX (AltiVec)", "description": "Reverses the byte order within each 64-bit doubleword of the source vector and stores the result in the destination vector. This instruction operates on two doublewords in parallel across the 128-bit vector. No condition flags are affected; this is a VMX/AltiVec instruction.", "pseudocode": "vD[0:63] ← vB[56:63] || vB[48:55] || vB[40:47] || vB[32:39] || vB[24:31] || vB[16:23] || vB[8:15] || vB[0:7]\nvD[64:127] ← vB[120:127] || vB[112:119] || vB[104:111] || vB[96:103] || vB[88:95] || vB[80:87] || vB[72:79] || vB[64:71]", "example": "vbrd vd, vb" }, { "mnemonic": "vbrq", "architecture": "PowerISA", "full_name": "Vector Byte-Reverse Quadword", "summary": "Reverses bytes within the entire 128-bit quadword.", "syntax": "vbrq vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 0 | vB | 1798", "hex_opcode": "0x10000706", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1798", "clean": "1798" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" } ], "extension": "VMX (AltiVec)", "description": "Reverses the byte order across the entire 128-bit quadword of the source vector and stores the result in the destination vector. This is a single whole-vector operation. No condition flags are affected; this is a VMX/AltiVec instruction.", "pseudocode": "vD[0:127] ← vB[120:127] || vB[112:119] || vB[104:111] || vB[96:103] || vB[88:95] || vB[80:87] || vB[72:79] || vB[64:71] || vB[56:63] || vB[48:55] || vB[40:47] || vB[32:39] || vB[24:31] || vB[16:23] || vB[8:15] || vB[0:7]", "example": "vbrq vd, vb" }, { "mnemonic": "vextsb2w", "architecture": "PowerISA", "full_name": "Vector Extend Sign Byte To Word", "summary": "Sign-extends each byte in a vector to a word.", "syntax": "vextsb2w vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | VRT | 16 | VRB | 1538", "hex_opcode": "0x10100602", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1542", "clean": "1542" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vextsb2w, the signed integer in bits 24:31 of each word element of VSR[VRB+32] is sign-extended and placed into the corresponding word element of VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n src ← VSR[VRB+32].word[i].bit[24:31]\n VSR[VRT+32].word[i] ← EXTS32(src)\nend", "page_found": "Page 397 - 398", "special_registers": "MSR", "programming_notes": "This instruction is used to sign-extend the most significant byte of each word in a vector register. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set; otherwise, a Vector Unavailable exception will be raised. The operation processes four words per vector register, and it's important to handle exceptions properly to avoid program crashes.", "example": "vextsb2w vd, vb" }, { "mnemonic": "vextsh2w", "architecture": "PowerISA", "full_name": "Vector Extend Sign Halfword To Word", "summary": "Sign-extends halfwords to words.", "syntax": "vextsh2w vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 0 | vB | 1606", "hex_opcode": "0x10110602", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1606", "clean": "1606" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" } ], "extension": "VMX (AltiVec)", "description": "Sign-extends each of four 16-bit halfwords in the source vector to 32-bit words, filling the upper bits with the sign bit, and stores the result in the destination vector. The instruction operates on the four halfwords in the lower 64 bits of the source. No condition flags are affected; this is a VMX/AltiVec instruction.", "pseudocode": "vD[0:31] ← (vB[0] replicated to 16 bits) || vB[0:15]\nvD[32:63] ← (vB[16] replicated to 16 bits) || vB[16:31]\nvD[64:95] ← (vB[32] replicated to 16 bits) || vB[32:47]\nvD[96:127] ← (vB[48] replicated to 16 bits) || vB[48:63]", "page_found": "Page 398", "special_registers": "MSR", "programming_notes": "This instruction is used to sign-extend the upper half of each word in a vector register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The operation processes four 32-bit words per vector register, and there are no specific alignment requirements for the data.", "example": "vextsh2w vd, vb" }, { "mnemonic": "vextsb2d", "architecture": "PowerISA", "full_name": "Vector Extend Sign Byte To Doubleword", "summary": "Sign-extends the byte elements of a vector register to doublewords.", "syntax": "vextsb2d vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | VRT | 24 | VRB | 1538", "hex_opcode": "0x10180602", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1798", "clean": "1798" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vextsb2d, each byte element in VSR[VRB+32] is sign-extended and placed into corresponding doubleword elements in VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 1\n src ← VSR[VRB+32].dword[i].bit[56:63]\n VSR[VRT+32].dword[i] ← EXTS64(src)\nend", "page_found": "Page 398 - 399", "special_registers": "MSR", "programming_notes": "This instruction is used to sign-extend each byte in the source vector register into a doubleword in the destination vector register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The operation processes two elements per iteration, and there are no specific alignment requirements for the data. This instruction operates at the user privilege level.", "example": "vextsb2d vd, vb" }, { "mnemonic": "vextsh2d", "architecture": "PowerISA", "full_name": "Vector Extend Sign Halfword To Doubleword", "summary": "Extends the sign of each halfword in a vector to doubleword.", "syntax": "vextsh2d vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 0 | vB | 1862", "hex_opcode": "0x10190602", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1862", "clean": "1862" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VSRC", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "page_found": "Page 1365 - 1366", "description": "Sign-extends each of two 16-bit halfwords in the source vector to 64-bit doublewords, filling the upper bits with the sign bit, and stores the result in the destination vector. The instruction operates on the two halfwords in the lower 32 bits of the source. No condition flags are affected; this is a VMX/AltiVec instruction.", "pseudocode": "vD[0:63] ← (vB[0] replicated to 48 bits) || vB[0:15]\nvD[64:127] ← (vB[16] replicated to 48 bits) || vB[16:31]", "special_registers": "MSR", "programming_notes": "This instruction is used for sign-extending the upper 16 bits of each doubleword in a vector from VRB to VRT. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The operation processes two elements per instruction execution.", "example": "vextsh2d vd, vb" }, { "mnemonic": "vextsw2d", "architecture": "PowerISA", "full_name": "Vector Extend Sign Word To Doubleword", "summary": "Extends the sign of each word in a vector to doubleword.", "syntax": "vextsw2d vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 0 | vB | 1926", "hex_opcode": "0x101A0602", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1926", "clean": "1926" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "The signed integer in bits 32:63 of each doubleword element of VSR[VRB+32] is sign-extended and placed into the corresponding doubleword element of VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 1\n src ← VSR[VRB+32].dword[i].bit[32:63]\n VSR[VRT+32].dword[i] ← EXTS64(src)\nend", "page_found": "Page 399 - 400", "special_registers": "MSR", "programming_notes": "This instruction is used to sign-extend the upper 32 bits of each doubleword in a vector register. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector Unavailable exception will be raised. The operation processes two elements per iteration, and it's important to verify that the source and target registers are correctly aligned for optimal performance.", "example": "vextsw2d vd, vb" }, { "mnemonic": "vcmpneb", "architecture": "PowerISA", "full_name": "Vector Compare Not Equal Byte", "summary": "Compares each byte of two vector registers and sets the result register to all 1s if the bytes are not equal, otherwise all 0s.", "syntax": "vcmpneb VRT,VRA,VRB", "encoding": { "format": "VC-form", "binary_pattern": "4 | VRT | VRA | VRB | Rc", "hex_opcode": "0x10000007", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "7", "clean": "7" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vcmpneb, each byte of VSR[VRA+32] is compared with the corresponding byte of VSR[VRB+32]. If they are not equal, the corresponding byte in VSR[VRT+32] is set to 0xFF; otherwise, it is set to 0x00.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nall_true ←1\nall_false ←1\ndo i = 0 to 15\n src1 ←VSR[VRA+32].byte[i]\n src2 ←VSR[VRB+32].byte[i]\n if src1 != src2 then do\n VSR[VRT+32].byte[i] ←0xFF\n all_false ←0\n end\n else do\n VSR[VRT+32].byte[i] ←0x00\n all_true ←0\n end\nend\nif Rc=1 then\n CR.field[6] ←all_true || 0b0 || all_false || 0b0", "special_registers": "CR0, XER", "page_found": "Page 423 - 424", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "vcmpneb v1, v2, v3" }, { "mnemonic": "vcmpneh", "architecture": "PowerISA", "full_name": "Vector Compare Not Equal Halfword", "summary": "Compares the contents of two vector registers and sets the result register to all 1s if the elements are not equal, otherwise all 0s.", "syntax": "vcmpneh VRT,VRA,VRB", "encoding": { "format": "VC-form", "binary_pattern": "4 | VRT | VRA | VRB | Rc", "hex_opcode": "0x10000047", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "71", "clean": "71" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vcmpneh, each halfword element in VSR[VRA+32] is compared with the corresponding element in VSR[VRB+32]. If they are not equal, the corresponding element in VSR[VRT+32] is set to all 1s; otherwise, it is set to all 0s.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nall_true ←1\nall_false ←1\ndo i = 0 to 7\n src1 ←VSR[VRA+32].hword[i]\n src2 ←VSR[VRB+32].hword[i]\n if src1 != src2 then do\n VSR[VRT+32].hword[i] ←0xFFFF\n all_false ←0\n end\n else do\n VSR[VRT+32].hword[i] ←0x0000\n all_true ←0\n end\nend\nif Rc=1 then\n CR.field[6] ←all_true || 0b0 || all_false || 0b0", "special_registers": "CR6 (if Rc=1)", "page_found": "Page 424 - 425", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "vcmpneh v1, v2, v3" }, { "mnemonic": "vcmpnew", "architecture": "PowerISA", "full_name": "Vector Compare Not Equal Word", "summary": "Compares each word of two vector registers and sets the corresponding word in the target vector register to all 1s if the words are not equal, otherwise to all 0s.", "syntax": "vcmpnew VRT,VRA,VRB", "encoding": { "format": "VC-form", "binary_pattern": "4 | VRT | VRA | VRB | Rc", "hex_opcode": "0x10000087", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "135", "clean": "135" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vcmpnew, each word of VSR[VRA+32] is compared with the corresponding word of VSR[VRB+32]. If they are not equal, the corresponding word in VSR[VRT+32] is set to 0xFFFF_FFFF; otherwise, it is set to 0x0000_0000.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nall_true ←1\nall_false ←1\ndo i = 0 to 3\n src1 ←VSR[VRA+32].word[i]\n src2 ←VSR[VRB+32].word[i]\n if src1 != src2 then do\n VSR[VRT+32].word[i] ←0xFFFF_FFFF\n all_false ←0\n end\n else do\n VSR[VRT+32].word[i] ←0x0000_0000\n all_true ←0\n end\nend\nif Rc=1 then\n CR.field[6] ←all_true || 0b0 || all_false || 0b0", "special_registers": "CR6 (if Rc=1)", "page_found": "Page 425 - 426", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "vcmpnew v1, v2, v3" }, { "mnemonic": "vadduqm", "architecture": "PowerISA", "full_name": "Vector Add Unsigned Quadword Modulo", "summary": "Adds the contents of two vector registers and updates the destination register with the result modulo 2^128.", "syntax": "vadduqm vD, vA, vB", "encoding": { "format": "VA-form", "binary_pattern": "4 | vD | vA | vB | 256", "hex_opcode": "0x10000100", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "256", "clean": "256" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vadduqm, the sum of the contents of vector registers VRA and VRB is placed into vector register VRT. The operation is performed modulo 2^128.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nsrc1 ←EXTZ(VSR[VRA+32])\nsrc2 ←EXTZ(VSR[VRB+32])\nVSR[VRT+32] ←CHOP128(src1 + src2)", "page_found": "Page 354 - 355", "special_registers": "MSR", "programming_notes": "This instruction is used for adding two 128-bit unsigned integers stored in vector registers modulo 2^128. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to 1; otherwise, a Vector_Unavailable exception will be raised. The operation does not require any specific alignment for the data being processed.", "example": "vadduqm vd, va, vb" }, { "mnemonic": "vsubuqm", "architecture": "PowerISA", "full_name": "Vector Subtract Unsigned Quadword Modulo", "summary": "Subtracts the contents of two vector registers and places the result in another vector register, modulo operation.", "syntax": "vsubuqm vD, vA, vB", "encoding": { "format": "VA-form", "binary_pattern": "4 | vD | vA | vB | 1280", "hex_opcode": "0x10000500", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1280", "clean": "1280" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vsubuqm, the unsigned quadword subtraction of the contents of VSR[VRA+32] and the one's complement of VSR[VRB+32], plus 1, is placed into VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nsrc1 ←EXTZ(VSR[VRA+32])\nsrc2 ←EXTZ(¬VSR[VRB+32])\nVSR[VRT+32] ←CHOP128(src1 + src2 + 1)", "page_found": "Page 362 - 363", "special_registers": "MSR", "programming_notes": "This instruction performs an unsigned quadword subtraction modulo operation. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. Be cautious with alignment as it may affect performance or cause exceptions if not properly aligned. The result is placed in the destination vector register, and developers should handle potential overflow conditions appropriately.", "example": "vsubuqm vd, va, vb" }, { "mnemonic": "vrlq", "architecture": "PowerISA", "full_name": "Vector Rotate Left Quadword", "summary": "Rotates the contents of a vector register left by a specified number of bits.", "syntax": "vrlq vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 260", "hex_opcode": "0x10000005", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "260", "clean": "260" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Data" }, { "name": "vB", "desc": "Shift" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "Rotates the 128-bit contents of the source vector left by the number of bits specified in the shift-count register and stores the result in the destination vector. The rotate amount is taken modulo 128; bits shifted out the left end wrap around to the right. No condition flags are affected; this is a VMX/AltiVec instruction.", "pseudocode": "shiftAmount ← vB[121:127] mod 128\nvD[0:127] ← (vA[0:127] << shiftAmount) | (vA[0:127] >> (128 - shiftAmount))", "page_found": "Page 432 - 433", "special_registers": "MSR", "programming_notes": "The vrlq instruction is used to perform a left rotation of 128 bits in a vector register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The shift amount is determined by the upper 7 bits of another vector register, so ensure these bits are set correctly to avoid unexpected results.", "example": "vrlq vd, va, vb" }, { "mnemonic": "vslq", "architecture": "PowerISA", "full_name": "Vector Shift Left Quadword", "summary": "Shifts the contents of a vector register left by a specified number of bits.", "syntax": "vslq vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 261", "hex_opcode": "0x10000105", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "261", "clean": "261" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Data" }, { "name": "vB", "desc": "Shift" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Shift Count Vector Register" } ], "extension": "VMX (AltiVec)", "description": "Shifts the 128-bit contents of the source vector left by the number of bits specified in the shift-count register and stores the result in the destination vector. Bits shifted out the left end are discarded; zeros are shifted in from the right. The shift amount is taken modulo 128. No condition flags are affected; this is a VMX/AltiVec instruction.", "pseudocode": "shiftAmount ← vB[121:127] mod 128\nvD[0:127] ← vA[0:127] << shiftAmount\nvD[shiftAmount:127] ← 0 (shifted-in zeros)", "page_found": "Page 439 - 440", "special_registers": "MSR", "programming_notes": "Ensure that the Vector Facility (MSR.VEC) is enabled before using vslq; otherwise, a Vector_Unavailable exception will occur. The shift amount is determined by the low-order 7 bits of the second source vector register, and shifts greater than 63 bits will result in zero being placed into the destination register.", "example": "vslq vd, va, vb" }, { "mnemonic": "vsrq", "architecture": "PowerISA", "full_name": "Vector Shift Right Quadword", "summary": "Shifts the contents of a vector register right by a specified number of bits.", "syntax": "vsrq vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 517", "hex_opcode": "0x10000205", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "517", "clean": "517" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Data" }, { "name": "vB", "desc": "Shift" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "Shifts the 128-bit contents of the source vector right by the number of bits specified in the shift-count register and stores the result in the destination vector. Bits shifted out the right end are discarded; zeros are shifted in from the left. The shift amount is taken modulo 128. No condition flags are affected; this is a VMX/AltiVec instruction.", "pseudocode": "shiftAmount ← vB[121:127] mod 128\nvD[0:127] ← vA[0:127] >> shiftAmount\nvD[0:(127-shiftAmount)] ← 0 (shifted-in zeros)", "page_found": "Page 442 - 443", "special_registers": "MSR", "programming_notes": "The vsrq instruction requires the Vector Facility to be enabled in the MSR register. Ensure that the shift amount is within the range of 0-127 bits to avoid unexpected results. The operation is performed on quadword elements, so alignment considerations are not necessary for this specific instruction.", "example": "vsrq vd, va, vb" }, { "mnemonic": "vsraq", "architecture": "PowerISA", "full_name": "Vector Shift Right Algebraic Quadword", "summary": "Shifts the contents of a vector register right algebraically by a specified number of bits.", "syntax": "vsraq vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 773", "hex_opcode": "0x10000305", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "773", "clean": "773" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Data" }, { "name": "vB", "desc": "Shift" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Shift Count Vector Register" } ], "extension": "VMX (AltiVec)", "description": "Shifts the 128-bit contents of vector register vA right algebraically (with sign extension) by the number of bits specified in the low 7 bits of vB, placing the result in vD. Each of the two 64-bit doublewords in vA is independently shifted right with sign extension. No condition register or status field modifications occur.", "pseudocode": "shift_amount ← vB[57:63]\nvD ← arithmetic_shift_right(vA, shift_amount)", "page_found": "Page 445 - 446", "special_registers": "MSR", "programming_notes": "The vsraq instruction is used for performing algebraic right shifts on quadword vector elements. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to 1; otherwise, a Vector_Unavailable exception will be raised. The shift amount is derived from the low-order 7 bits of the second source register, and the result is stored in the destination register. Be cautious with alignment as it affects performance and correctness.", "example": "vsraq vd, va, vb" }, { "mnemonic": "vmulhsw", "architecture": "PowerISA", "full_name": "Vector Multiply High Signed Word", "summary": "Multiplies the signed integer values in each word element of two vector registers and places the high-order 32 bits of the 64-bit product into the corresponding word element of a third vector register.", "syntax": "vmulhsw vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 904", "hex_opcode": "0x10000389", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "904", "clean": "904" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vmulhsw, the signed integer value in word element i of VSR[VRA+32] is multiplied by the signed integer value in word element i of VSR[VRB+32]. The high-order 32 bits of the 64-bit product are placed into word element i of VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n src1 ←EXTS(VSR[VRA+32].word[i])\n src2 ←EXTS(VSR[VRB+32].word[i])\n VSR[VRT+32].word[i] ←CHOP32((src1 × src2) >> 32)\nend", "page_found": "Page 373 - 374", "special_registers": "MSR", "programming_notes": "This instruction is used for multiplying signed integers stored in the high half of vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation processes four 32-bit words per vector register, and the result is the high-order 32 bits of each 64-bit product. Be cautious with overflow conditions as they are not handled by this instruction.", "example": "vmulhsw vd, va, vb" }, { "mnemonic": "vmulhuw", "architecture": "PowerISA", "full_name": "Vector Multiply High Unsigned Word", "summary": "Multiplies unsigned words, returning the high 32 bits.", "syntax": "vmulhuw vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 648", "hex_opcode": "0x10000289", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "648", "clean": "648" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Multiplies each pair of unsigned 32-bit words from vA and vB, producing 64-bit products, and places the high 32 bits of each product into the corresponding 32-bit word of vD. Four independent word multiplications are performed. No condition register or status field modifications occur.", "pseudocode": "for i = 0 to 3 do\n product ← (vA[i*32:(i+1)*32]) × (vB[i*32:(i+1)*32])\n vD[i*32:(i+1)*32] ← product[32:63]\nend for", "page_found": "Page 374", "special_registers": "MSR", "programming_notes": "The vmulhuw instruction is used for multiplying pairs of unsigned 32-bit integers from two source vectors and storing the high-order 32 bits of each product in a destination vector. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to 1; otherwise, a Vector_Unavailable exception will be raised. This instruction operates on 128-bit vectors, so ensure proper alignment and ordering of data for accurate results.", "example": "vmulhuw vd, va, vb" }, { "mnemonic": "vmulhsd", "architecture": "PowerISA", "full_name": "Vector Multiply High Signed Doubleword", "summary": "Multiplies the signed doublewords of two vector registers and stores the high-order 64 bits of each product in a result vector register.", "syntax": "vmulhsd vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 968", "hex_opcode": "0x100003C9", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "968", "clean": "968" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vmulhsd, the signed integer value in doubleword element i of VSR[VRA+32] is multiplied by the signed integer value in doubleword element i of VSR[VRB+32]. The high-order 64 bits of the 128-bit product are placed into doubleword element i of VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 1\n src1 ←EXTS(VSR[VRA+32].dword[i])\n src2 ←EXTS(VSR[VRB+32].dword[i])\n VSR[VRT+32].dword[i] ←CHOP64((src1 × src2) >> 64)\nend", "page_found": "Page 374 - 375", "special_registers": "MSR", "programming_notes": "This instruction is used for high-precision multiplication of signed doublewords. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation is performed on each pair of doubleword elements from the input vectors, and only the high 64 bits of the 128-bit product are stored in the result vector. Be cautious of overflow conditions as they can lead to unexpected results.", "example": "vmulhsd vd, va, vb" }, { "mnemonic": "vmulhud", "architecture": "PowerISA", "full_name": "Vector Multiply High Unsigned Doubleword", "summary": "Multiplies unsigned doublewords, returning the high 64 bits.", "syntax": "vmulhud vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 712", "hex_opcode": "0x100002C9", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "712", "clean": "712" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VMX (AltiVec)", "description": "Multiplies each pair of unsigned 64-bit doublewords from vA and vB, producing 128-bit products, and places the high 64 bits of each product into the corresponding 64-bit doubleword of vD. Two independent doubleword multiplications are performed. No condition register or status field modifications occur.", "pseudocode": "for i = 0 to 1 do\n product ← (vA[i*64:(i+1)*64]) × (vB[i*64:(i+1)*64])\n vD[i*64:(i+1)*64] ← product[64:127]\nend for", "page_found": "Page 375", "special_registers": "MSR", "programming_notes": "The vmulhud instruction is used for high-precision multiplication of unsigned doublewords. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. This instruction processes each pair of elements from two source vectors and stores the upper 64 bits of their product in the destination vector. Be cautious with alignment as unaligned access can lead to exceptions.", "example": "vmulhud vd, va, vb" }, { "mnemonic": "xxlandc", "architecture": "PowerISA", "full_name": "VSX Vector Logical AND with Complement", "summary": "vD = vA & ~vB", "syntax": "xxlandc XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "60 | XT | XA | XB | 444", "hex_opcode": "0xF0000450", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "444", "clean": "444" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "Performs a bitwise logical AND operation between XT and the bitwise complement of XB, storing the result in XT. The operation is XT ← XT & ~XB on all 128 bits. No condition register or status field modifications occur.", "pseudocode": "XT ← XA & ~XB", "page_found": "Page 943", "special_registers": "MSR", "programming_notes": "The xxlandc instruction is used for performing a bitwise logical AND operation between the contents of two vector registers, where one register's bits are complemented before the operation. Ensure that the VSX (Vector Scalar Extensions) facility is enabled in the MSR (Machine State Register) to avoid an exception. This instruction operates on 128-bit vectors and requires proper alignment of the input and output registers.", "example": "xxlandc vs1, vs2, vs3" }, { "mnemonic": "xxlorc", "architecture": "PowerISA", "full_name": "VSX Vector Logical OR with Complement", "summary": "vD = vA | ~vB", "syntax": "xxlorc XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "60 | XT | XA | XB | 452", "hex_opcode": "0xF0000550", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "452", "clean": "452" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "Performs a bitwise logical OR operation between XA and the bitwise complement of XB, storing the result in XT. The operation is XT ← XA | ~XB on all 128 bits. No condition register or status field modifications occur.", "pseudocode": "XT ← XA | ~XB", "page_found": "Page 944", "special_registers": "MSR", "programming_notes": "The xxlorc instruction is useful for performing bitwise operations on VSX registers. Ensure that the VSX facility is enabled by checking and setting the MSR.VSX bit; otherwise, a VSX_Unavailable exception will occur. The operation is performed on 128-bit vectors, so ensure proper alignment of the data in the registers to avoid unexpected results.", "example": "xxlorc vs1, vs2, vs3" }, { "mnemonic": "xxlnand", "architecture": "PowerISA", "full_name": "VSX Vector Logical NAND", "summary": "vD = ~(vA & vB)", "syntax": "xxlnand XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "60 | XT | XA | XB | 442", "hex_opcode": "0xF0000590", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "442", "clean": "442" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "Performs a bitwise logical NAND operation on XA and XB, storing the result in XT. The operation is XT ← ~(XA & XB) on all 128 bits. No condition register or status field modifications occur.", "pseudocode": "XT ← ~(XA & XB)", "page_found": "Page 943", "programming_notes": "The xxlnand instruction is commonly used for bitwise logical operations in VSX registers. Ensure that the source and target registers are properly aligned to avoid alignment faults. This instruction operates at user privilege level, but care should be taken to handle potential exceptions if unaligned access occurs.", "example": "xxlnand vs1, vs2, vs3" }, { "mnemonic": "xxleqv", "architecture": "PowerISA", "full_name": "VSX Vector Logical Equivalence", "summary": "vD = ~(vA ^ vB) (XNOR)", "syntax": "xxleqv XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "60 | XT | XA | XB | 458", "hex_opcode": "0xF00005D0", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "458", "clean": "458" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "Performs a bitwise logical equivalence (XNOR) operation on XA and XB, storing the result in XT. The operation is XT ← ~(XA ^ XB) on all 128 bits, producing all 1-bits where XA and XB have the same bit value. No condition register or status field modifications occur.", "pseudocode": "XT ← ~(XA ^ XB)", "page_found": "Page 943", "programming_notes": "The xxleqv instruction is used to perform a vector logical equivalence operation between two VSX registers. It's useful for comparing vectors and determining where elements are not equal, as it effectively computes the bitwise NOT of the equality result. Ensure that the input registers (XA and XB) are properly aligned and contain valid data to avoid unexpected results. This instruction operates at the user privilege level and does not generate exceptions under normal conditions.", "example": "xxleqv vs1, vs2, vs3" }, { "mnemonic": "vgbbd", "architecture": "PowerISA", "full_name": "Vector Gather Bits by Bytes by Doubleword", "summary": "The contents of bit j of each byte of doubleword element i of VSR[VRB+32] are concatenated and placed into byte j of doubleword element i of VSR[VRT+32].", "syntax": "vgbbd vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "0 | 6 | 11 | 16 | 21 | 31", "hex_opcode": "0x1000050C", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1282", "clean": "1282" } ], "length": "32", "bit_positions": "0 | 6 | 11 | 16 | 21 | 31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vgbbd, the contents of bit j of each byte of doubleword element i of VSR[VRB+32] are concatenated and placed into byte j of doubleword element i of VSR[VRT+32]. An 8-bit × 8-bit bit-matrix transpose is performed on the contents of each doubleword element of VSR[VRB+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 1\n do j = 0 to 7\n do k = 0 to 7\n b ← VSR[VRB+32].dword[i].byte[k].bit[j]\n VSR[VRT+32].dword[i].byte[j].bit[k] ← b\n end\n end\nend", "page_found": "Page 468 - 469", "special_registers": "MSR", "programming_notes": "The vgbbd instruction performs a bit-matrix transpose on each doubleword element of the source vector, effectively rotating bits within bytes. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This operation requires aligned access to the vector registers. Be cautious with privilege levels; this instruction may require supervisor or hypervisor mode depending on system configuration.", "example": "vgbbd vd, vb" }, { "mnemonic": "vpdepd", "architecture": "PowerISA", "full_name": "Vector Parallel Bits Deposit Doubleword", "summary": "Deposits bits from source to target under control of a mask (Power10).", "syntax": "vpdepd vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 1485", "hex_opcode": "0x100005CD", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1485", "clean": "1485" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Source" }, { "name": "vB", "desc": "Mask" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Mask Vector Register" } ], "extension": "VMX (AltiVec)", "description": "The contents of bits in doubleword element i of VSR[VRT+32] corresponding to bits in doubleword element i of VSR[VRB+32] that contain a 0 are set to 0. The contents of the rightmost n bits of doubleword element i of VSR[VRA+32] are placed into doubleword element i of VSR[VRT+32] under control of the mask in doubleword element i of VSR[VRB+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 1\n VSR[VRT+32].dword[i] ←0\n m ←0\n k ←0\n do while(m < 64)\n if VSR[VRB+32].dword[i].bit[63-m]=1 then do\n result ←VSR[VRA+32].dword[i].bit[63-k]\n VSR[VRT+32].dword[i].bit[63-m] ←result\n k ←k + 1\n end\n m ←m + 1\n end\nend", "page_found": "Page 477 - 478", "special_registers": "MSR", "programming_notes": "The vpdepd instruction is used to deposit bits from one vector register into another based on a mask specified in a third vector register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The operation processes each doubleword element independently, and the alignment of the input vectors must be considered to avoid unexpected results. This instruction is particularly useful for bit manipulation tasks where selective depositing of bits is required.", "example": "vpdepd vd, va, vb" }, { "mnemonic": "vpextd", "architecture": "PowerISA", "full_name": "Vector Parallel Bits Extract Doubleword", "summary": "Extracts bits from one vector register based on the bit positions specified in another vector register and places them into a third vector register.", "syntax": "vpextd vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 1421", "hex_opcode": "0x1000058D", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1421", "clean": "1421" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Source" }, { "name": "vB", "desc": "Mask" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register A" }, { "name": "VRB", "desc": "Source Vector Register B" } ], "extension": "VMX (AltiVec)", "description": "Extracts bits from vA based on bit-position indices specified in vB, placing extracted bits into the corresponding doubleword elements of vD. The instruction operates on 64-bit doubleword elements, where vB contains bit indices (0-63) that select which bits from vA are gathered into vD. This is a VMX extension instruction with no condition register or status flag updates.", "pseudocode": "for i in 0 to 1 do\n vD[i*64:(i+1)*64] ← 0\n for j in 0 to 63 do\n if vB[i*64+j] < 64 then\n vD[i*64+j] ← vA[i*64 + vB[i*64+j:i*64+j+5]]\n else\n vD[i*64+j] ← 0", "page_found": "Page 478 - 479", "special_registers": "MSR", "programming_notes": "The vpextd instruction is used to extract bits from one vector register based on the bit positions specified in another vector register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. This operation is performed on each doubleword element of the vectors, so ensure proper alignment and indexing to avoid unexpected results.", "example": "vpextd vd, va, vb" }, { "mnemonic": "vcfuged", "architecture": "PowerISA", "full_name": "Vector Centrifuge Doubleword", "summary": "Separates bits of source into two groups based on mask (Power10).", "syntax": "vcfuged vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 1357", "hex_opcode": "0x1000054D", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1357", "clean": "1357" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Source" }, { "name": "vB", "desc": "Mask" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Mask Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vcfuged, the bits of VSR[VRA+32] are rearranged based on the mask in VSR[VRB+32]. Bits corresponding to 1s in the mask are placed in the rightmost positions, and other bits are placed in the leftmost positions.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 1\n ptr0 ←0\n ptr1 ←0\n do j = 0 to 63\n if VSR[VRB+32].dword[i].bit[j]=0b0 then do\n result.bit[ptr0] ←\n VSR[VRA+32].dword[i].bit[j]\n ptr0 ←ptr0 + 1\n end\n if VSR[VRB+32].dword[i].bit[63-j]=1 then do\n result.bit[63-ptr1] ←\n VSR[VRA+32].dword[i].bit[63-j]\n ptr1 ←ptr1 + 1\n end\n end\n VSR[VRT+32].dword[i] ←result\nend", "page_found": "Page 479 - 480", "special_registers": "MSR", "programming_notes": "The vcfuged instruction rearranges bits in a vector register based on a mask from another vector register. Ensure the Vector Facility is enabled by checking and setting the MSR.VEC bit. The operation processes each doubleword independently, moving bits to the right or left based on the mask's 0s and 1s. Be cautious of alignment issues when accessing vector registers.", "example": "vcfuged vd, va, vb" }, { "mnemonic": "vgnb", "architecture": "PowerISA", "full_name": "Vector Gather Non-Zero Bytes", "summary": "Gathers every Nth bit from a vector register and places it into a general-purpose register.", "syntax": "vgnb vD, vB, UIM", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | UIM | vB | 1228", "hex_opcode": "0x100004CC", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "UIM", "clean": "UIM" }, { "raw": "vB", "clean": "vB" }, { "raw": "1228", "clean": "1228" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "UIM", "desc": "Stream" }, { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "N", "desc": "Gather interval (2 to 7)" } ], "extension": "VMX (AltiVec)", "description": "Gathers every Nth bit (where N is 2-7 as specified by UIM) from vector register vB and packs them into a 64-bit general-purpose register. The bits are gathered starting from bit 0 of vB and compacted into the lower bits of the result; unused upper bits are zeroed. This is a VMX extension instruction with no condition register or status flag updates.", "pseudocode": "N ← UIM\nresult ← 0\nbit_pos ← 0\nfor i in 0 to 127 by N do\n if i < 128 then\n result[bit_pos] ← vB[i]\n bit_pos ← bit_pos + 1\nvD[0:63] ← result", "programming_notes": "N must be between 2 and 7 inclusive.", "page_found": "Page 469 - 470", "special_registers": "MSR", "example": "vgnb vd, vb, uim" }, { "mnemonic": "vclrlb", "architecture": "PowerISA", "full_name": "Vector Clear Left Bytes", "summary": "Clears the leftmost bytes in a vector register based on the value in a general-purpose register.", "syntax": "vclrlb vD, vA, RB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | RB | 397", "hex_opcode": "0x1000018D", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "RB", "clean": "RB" }, { "raw": "397", "clean": "397" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Source" }, { "name": "RB", "desc": "Count (GPR)" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "The contents of VSR[VRA+32] are placed into VSR[VRT+32] with the leftmost 16-N bytes set to 0, where N is the integer value in GPR[RB] or 16 if GPR[RB] > 15.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nN ← (GPR[RB] > 15) ? 16 : GPR[RB]\ndo i = 0 to N-1\n VSR[VRT+32].byte[15-i] ← VSR[VRA+32].byte[15-i]\nend\ndo i = N to 15\n VSR[VRT+32].byte[15-i] ← 0x00\nend", "page_found": "Page 499 - 500", "special_registers": "MSR", "programming_notes": "The vclrlb instruction is useful for clearing the leftmost bytes of a vector register based on the value in GPR[RB]. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. Be cautious with alignment and ensure that the values in VRA and VRT are correctly set to avoid unintended data manipulation.", "example": "vclrlb vd, va, r5" }, { "mnemonic": "vclrrb", "architecture": "PowerISA", "full_name": "Vector Clear Right Bytes", "summary": "Clears the N rightmost bytes of a vector.", "syntax": "vclrrb vD, vA, RB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | RB | 461", "hex_opcode": "0x100001CD", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "RB", "clean": "RB" }, { "raw": "461", "clean": "461" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Source" }, { "name": "RB", "desc": "Count (GPR)" } ], "extension": "VMX (AltiVec)", "description": "Clears the rightmost N bytes of vector register vA (where N is derived from the low 4 bits of RB) and places the result in vD. Bits corresponding to the rightmost N bytes are set to zero while remaining bits are preserved. This is a VMX extension instruction with no condition register or status flag updates.", "pseudocode": "N ← RB[60:63]\nif N > 16 then N ← 16\nvD ← vA\nfor i in 0 to N-1 do\n vD[128-8*(i+1):128-8*i] ← 0", "page_found": "Page 500", "special_registers": "MSR", "programming_notes": "The vclrrb instruction is useful for clearing the rightmost bytes of a vector register based on a specified count. Ensure that the Vector Facility (MSR.VEC) is enabled to avoid a Vector_Unavailable exception. The value in GPR[RB] should be between 0 and 15; values greater than 15 will result in all bytes being cleared. This instruction operates on vector registers, so ensure proper alignment and privilege level as required by the system.", "example": "vclrrb vd, va, r5" }, { "mnemonic": "plq", "architecture": "PowerISA", "full_name": "Prefixed Load Quadword", "summary": "Loads 128 bits into two GPRs using a 34-bit offset.", "syntax": "plq RTp, D(RA), R", "encoding": { "format": "MLS:D-form", "binary_pattern": "1 | 2 | R | 0 | D0 | 56 | RT | RA | D1", "hex_opcode": "0x04000000E0000000", "visual_parts": [ { "raw": "000001", "clean": "000001" }, { "raw": "10", "clean": "10" }, { "raw": "...", "clean": "..." }, { "raw": "56", "clean": "56" }, { "raw": "...", "clean": "..." } ], "length": "64", "bit_positions": "0:5 | 6:7 | 8 | 9:13 | 14:31 | 32:37 | 38:42 | 43:47 | 48:63" }, "operands": [ { "name": "RTp", "desc": "Target Pair" }, { "name": "D", "desc": "Offset" }, { "name": "RA", "desc": "Base" }, { "name": "R", "desc": "PC-Rel" } ], "extension": "Prefixed", "description": "Prefixed load of 128 bits from memory into two consecutive general-purpose registers (RT and RT+1) using a 34-bit signed offset. The effective address is computed as RA + D (if R=0) or the prefixed address. This is a prefixed instruction requiring the Prefixed extension; no condition register or status flags are affected.", "pseudocode": "if RA = 0 then\n EA ← D\nelse\n EA ← (RA) + D\nRT ← [EA]\nRT+1 ← [EA+8]", "page_found": "Page 99", "programming_notes": "The plq instruction is used to load a quadword from memory into an even-odd pair of GPRs. Ensure that the effective address (EA) is properly aligned to 16 bytes for optimal performance and to avoid alignment exceptions. This instruction operates at the problem state privilege level, so it cannot be executed in supervisor or hypervisor states.", "example": "plq r4, 0(r4), 0" }, { "mnemonic": "pstq", "architecture": "PowerISA", "full_name": "Prefixed Store Quadword", "summary": "Stores 128 bits from two GPRs using a 34-bit offset.", "syntax": "pstq RSp, D(RA), R", "encoding": { "format": "MLS:D-form", "binary_pattern": "1 | 2 | R | 0 | D0 | 60 | RS | RA | D1", "hex_opcode": "0x04000000F0000000", "visual_parts": [ { "raw": "000001", "clean": "000001" }, { "raw": "10", "clean": "10" }, { "raw": "...", "clean": "..." }, { "raw": "60", "clean": "60" }, { "raw": "...", "clean": "..." } ], "length": "64", "bit_positions": "0:5 | 6:7 | 8 | 9:13 | 14:31 | 32:37 | 38:42 | 43:47 | 48:63" }, "operands": [ { "name": "RSp", "desc": "Src Pair" }, { "name": "D", "desc": "Offset" }, { "name": "RA", "desc": "Base" }, { "name": "R", "desc": "PC-Rel" } ], "extension": "Prefixed", "description": "Prefixed store of 128 bits from two consecutive general-purpose registers (RS and RS+1) to memory using a 34-bit signed offset. The effective address is computed as RA + D (if R=0) or the prefixed address. This is a prefixed instruction requiring the Prefixed extension; no condition register or status flags are affected.", "pseudocode": "if RA = 0 then\n EA ← D\nelse\n EA ← (RA) + D\n[EA] ← RS\n[EA+8] ← RS+1", "page_found": "Page 100", "special_registers": "CIA", "programming_notes": "The pstq instruction is used to store a quadword from registers RSp and RSp+1 into memory. It calculates the effective address based on the base register RA, displacement, and current instruction address CIA, depending on the prefix field R. Ensure proper alignment for optimal performance and be aware of byte ordering differences between Big-Endian and Little-Endian systems.", "example": "pstq r4, 0(r4), 0" }, { "mnemonic": "xxmrghw", "architecture": "PowerISA", "full_name": "VSX Vector Merge High Word", "summary": "Merges the high words of two VSX registers into a target VSX register.", "syntax": "xxmrghw XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "18 | T | A | B | AX | BX | TX", "hex_opcode": "0xF0000090", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "18", "clean": "18" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "Merges the high-order words (words 0 and 1) from VSX registers XA and XB into XT, interleaving them as: XT[0:31] ← XA[0:31], XT[32:63] ← XB[0:31], XT[64:95] ← XA[32:63], XT[96:127] ← XB[32:63]. This is a VSX instruction with no condition register or status flag updates.", "pseudocode": "XT[0:31] ← XA[0:31]\nXT[32:63] ← XB[0:31]\nXT[64:95] ← XA[32:63]\nXT[96:127] ← XB[32:63]", "page_found": "Page 953 - 954", "special_registers": "MSR", "programming_notes": "The xxmrghw instruction is commonly used to merge high words from two vector registers into a third register. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register; otherwise, a VSX_Unavailable exception will be raised. This instruction operates on 128-bit vectors and requires proper alignment of the input registers for optimal performance.", "example": "xxmrghw vs1, vs2, vs3" }, { "mnemonic": "xxmrglw", "architecture": "PowerISA", "full_name": "VSX Vector Merge Low Word", "summary": "Merges low words from two VSRs.", "syntax": "xxmrglw XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "60 | XT | XA | XB | 82", "hex_opcode": "0xF0000190", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "82", "clean": "82" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "Merges the low-order words (words 2 and 3) from VSX registers XA and XB into XT, interleaving them as: XT[0:31] ← XA[64:95], XT[32:63] ← XB[64:95], XT[64:95] ← XA[96:127], XT[96:127] ← XB[96:127]. This is a VSX instruction with no condition register or status flag updates.", "pseudocode": "XT[0:31] ← XA[64:95]\nXT[32:63] ← XB[64:95]\nXT[64:95] ← XA[96:127]\nXT[96:127] ← XB[96:127]", "page_found": "Page 954", "special_registers": "MSR", "programming_notes": "The xxmrglw instruction is commonly used for merging specific word elements from two VSX vectors into a new vector. Ensure that the VSX facility is enabled by checking and setting the appropriate bit in the MSR register. This instruction operates on 128-bit vectors, so source and destination registers must be properly aligned. Be cautious of potential exceptions if the VSX facility is not available or if there are alignment issues with the vector registers.", "example": "xxmrglw vs1, vs2, vs3" }, { "mnemonic": "vexpandbm", "architecture": "PowerISA", "full_name": "Vector Expand Byte Mask", "summary": "Expands the mask from bit 0 of each byte element in the source VSR to all bits in the corresponding element in the target VSR.", "syntax": "vexpandbm vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | VRT | 0 | VRB | 1602", "hex_opcode": "0x10000642", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1602", "clean": "1602" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "Expands the mask bit (bit 0) of each byte element in vB to all 8 bits of the corresponding byte in vD. If vB[byte][0] = 1, the entire byte in vD becomes 0xFF; if vB[byte][0] = 0, the entire byte in vD becomes 0x00. This is a VMX extension instruction with no condition register or status flag updates.", "pseudocode": "for i in 0 to 15 do\n if vB[i*8] = 1 then\n vD[i*8:(i+1)*8] ← 0xFF\n else\n vD[i*8:(i+1)*8] ← 0x00", "page_found": "Page 489 - 490", "special_registers": "MSR", "programming_notes": "The vexpandbm instruction is useful for creating masks where each byte is either all zeros or all ones based on the least significant bit of the corresponding source byte. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. This operation is efficient for processing data in parallel across multiple bytes.", "example": "vexpandbm vd, vb" }, { "mnemonic": "vexpandhm", "architecture": "PowerISA", "full_name": "Vector Expand Halfword Mask", "summary": "Expands bits from a GPR mask into a halfword-element vector.", "syntax": "vexpandhm vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 0 | vB | 1666", "hex_opcode": "0x10010642", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1666", "clean": "1666" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" } ], "extension": "VMX (AltiVec)", "description": "Expands individual bits from a source vector register into halfword-sized elements in the destination vector register, where each bit controls whether the corresponding halfword is set to all 1s or all 0s. This is a VMX instruction with no effect on condition registers or status fields.", "pseudocode": "for i in 0 to 7 do\n if vB[i] = 1 then\n vD[i*16:(i+1)*16-1] ← 0xFFFF\n else\n vD[i*16:(i+1)*16-1] ← 0x0000\n end if\nend for", "page_found": "Page 490", "special_registers": "MSR", "programming_notes": "The vexpandhm instruction is useful for creating masks based on the least significant bit of each halfword in the source vector. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to 1 before using this instruction, as attempting to execute it with VEC=0 will result in a Vector Unavailable exception. This instruction operates on 8 halfwords per vector register and does not require any specific alignment of the data.", "example": "vexpandhm vd, vb" }, { "mnemonic": "vexpandwm", "architecture": "PowerISA", "full_name": "Vector Expand Word Mask", "summary": "Expands bits from a GPR mask into a word-element vector.", "syntax": "vexpandwm vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | VRT | 2 | VRB | 1602", "hex_opcode": "0x10020642", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1730", "clean": "1730" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vexpandwm, each word element of VSR[VRT+32] is set to all 0s or all 1s based on the value of bit 0 of the corresponding word element in VSR[VRB+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n let bmi be the contents of bit 0 of word element i of VSR[VRB+32]\n if bmi is equal to 0 then\n VSR[VRT+32].word[i] ←0xFFFF_FFFF\n else\n VSR[VRT+32].word[i] ←0x0000_0000\nend", "page_found": "Page 490 - 491", "special_registers": "MSR", "programming_notes": "The vexpandwm instruction sets each word in the destination vector to all 1s or all 0s based on the least significant bit of the corresponding word in the source vector. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on 32-bit words, so ensure proper alignment if manipulating data directly. The operation is performed on vectors, so verify that the input vectors are correctly loaded before execution.", "example": "vexpandwm vd, vb" }, { "mnemonic": "vexpanddm", "architecture": "PowerISA", "full_name": "Vector Expand Doubleword Mask", "summary": "Expands bits from a GPR mask into a doubleword-element vector.", "syntax": "vexpanddm vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 0 | vB | 1794", "hex_opcode": "0x10030642", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1794", "clean": "1794" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" } ], "extension": "VMX (AltiVec)", "description": "Expands individual bits from a source vector register into doubleword-sized elements in the destination vector register, where each bit controls whether the corresponding doubleword is set to all 1s or all 0s. This is a VMX instruction with no effect on condition registers or status fields.", "pseudocode": "for i in 0 to 3 do\n if vB[i] = 1 then\n vD[i*64:(i+1)*64-1] ← 0xFFFFFFFFFFFFFFFF\n else\n vD[i*64:(i+1)*64-1] ← 0x0000000000000000\n end if\nend for", "page_found": "Page 491", "special_registers": "MSR", "programming_notes": "This instruction is useful for creating masks where each doubleword element in the target vector register is either all ones or all zeros based on the least significant bit of the corresponding source vector element. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to 1; otherwise, a Vector Unavailable exception will be raised. The instruction operates on doubleword elements, so ensure proper alignment and indexing when using this instruction.", "example": "vexpanddm vd, vb" }, { "mnemonic": "vexpandqm", "architecture": "PowerISA", "full_name": "Vector Expand Quadword Mask", "summary": "Expands bits from a GPR mask into a quadword-element vector.", "syntax": "vexpandqm vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 0 | vB | 1858", "hex_opcode": "0x10040642", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1858", "clean": "1858" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "Expands individual bits from a source vector register into quadword-sized elements in the destination vector register, where each bit controls whether the corresponding quadword is set to all 1s or all 0s. This is a VMX instruction with no effect on condition registers or status fields.", "pseudocode": "for i in 0 to 1 do\n if vB[i] = 1 then\n vD[i*128:(i+1)*128-1] ← 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF\n else\n vD[i*128:(i+1)*128-1] ← 0x00000000000000000000000000000000\n end if\nend for", "page_found": "Page 491 - 492", "special_registers": "MSR", "programming_notes": "The vexpandqm instruction is used to set all elements in a vector register based on the value of a single mask bit. Ensure that the Vector Facility (VEC) is enabled in the MSR before using this instruction; otherwise, it will raise an exception. This instruction is useful for quickly initializing vectors with either all ones or all zeros based on a condition.", "example": "vexpandqm vd, vb" }, { "mnemonic": "vextractbm", "architecture": "PowerISA", "full_name": "Vector Extract Byte Mask", "summary": "Extracts bit 0 of each byte element from a VSR into a GPR.", "syntax": "vextractbm RA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | RT | 8 | VRB | 1602", "hex_opcode": "0x10080642", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "RA", "clean": "RA" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1602", "clean": "1602" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "The contents of bit 0 of each byte element of VSR[VRB+32] are concatenated and placed into bits 48:63 of GPR[RT]. Bits 0:47 of GPR[RT] are set to 0.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 15\n GPR[RT].bit[48+i] ← VSR[VRB+32].byte[i].bit[0]\nend\nGPR[RT].bit[0:47] ← 0", "page_found": "Page 494 - 495", "special_registers": "MSR", "programming_notes": "This instruction is used to extract the least significant bit from each byte of a vector register and pack them into the upper half of a general-purpose register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The lower half of the target GPR is always zeroed out, so be cautious if you need to preserve existing data in that portion.", "example": "vextractbm r4, vb" }, { "mnemonic": "vextracthm", "architecture": "PowerISA", "full_name": "Vector Extract Halfword Mask", "summary": "Extracts MSB of each halfword into a GPR mask.", "syntax": "vextracthm RA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | RA | 0 | vB | 1666", "hex_opcode": "0x10090642", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "RA", "clean": "RA" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1666", "clean": "1666" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "vB", "desc": "Source" } ], "extension": "VMX (AltiVec)", "description": "Extracts the most significant bit from each halfword element in the source vector and packs these bits into a general-purpose register as a mask. This is a VMX instruction with no effect on condition registers or status fields.", "pseudocode": "result ← 0\nfor i in 0 to 7 do\n if vB[i*16] = 1 then\n result[i] ← 1\n else\n result[i] ← 0\n end if\nend for\nRA ← result", "page_found": "Page 495", "special_registers": "MSR", "programming_notes": "The vextracthm instruction is useful for extracting the least significant bit of each halfword from a vector register and placing them into a general-purpose register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The upper 16 bits of the destination GPR will contain the extracted bits, with the lower 48 bits set to zero.", "example": "vextracthm r4, vb" }, { "mnemonic": "vextractwm", "architecture": "PowerISA", "full_name": "Vector Extract Word Mask", "summary": "Extracts the least significant bit of each word element from a vector register and places them into a general-purpose register.", "syntax": "vextractwm RA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | RA | 0 | vB | 1730", "hex_opcode": "0x100A0642", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "RA", "clean": "RA" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1730", "clean": "1730" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "The contents of bit 0 of each word element of VSR[VRB+32] are concatenated and placed into bits 60:63 of GPR[RT]. Bits 0:59 of GPR[RT] are set to 0.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n GPR[RT].bit[60+i] ← VSR[VRB+32].word[i].bit[0]\nend\nGPR[RT].bit[0:59] ← 0", "page_found": "Page 495 - 496", "special_registers": "MSR", "programming_notes": "This instruction is used to extract the least significant bit of each word from a vector register and pack them into the upper four bits of a general-purpose register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The lower 60 bits of the target GPR are always cleared, so be cautious if you need to preserve existing data in those positions.", "example": "vextractwm r4, vb" }, { "mnemonic": "vextractdm", "architecture": "PowerISA", "full_name": "Vector Extract Doubleword Mask", "summary": "Extracts MSB of each doubleword into a GPR mask.", "syntax": "vextractdm RA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | RA | 0 | vB | 1794", "hex_opcode": "0x100B0642", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "RA", "clean": "RA" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1794", "clean": "1794" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "vB", "desc": "Source" } ], "extension": "VMX (AltiVec)", "description": "Extracts the most significant bit from each doubleword element in the source vector and packs these bits into a general-purpose register as a mask. This is a VMX instruction with no effect on condition registers or status fields.", "pseudocode": "result ← 0\nfor i in 0 to 3 do\n if vB[i*64] = 1 then\n result[i] ← 1\n else\n result[i] ← 0\n end if\nend for\nRA ← result", "page_found": "Page 496", "special_registers": "MSR", "programming_notes": "This instruction is useful for extracting the least significant bit of each doubleword in a vector register and placing it into a general-purpose register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The result is stored in bits 62:63 of the target GPR, with all other bits set to zero.", "example": "vextractdm r4, vb" }, { "mnemonic": "vextractqm", "architecture": "PowerISA", "full_name": "Vector Extract Quadword Mask", "summary": "Extracts the least significant bit of a vector register and places it into a general-purpose register.", "syntax": "vextractqm RA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | RA | 0 | vB | 1858", "hex_opcode": "0x100C0642", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "RA", "clean": "RA" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1858", "clean": "1858" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "The contents of bit 0 of VSR[VRB+32] are placed into bit 63 of GPR[RT]. Bits 0:62 of GPR[RT] are set to 0.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nGPR[RT] ← EXTZ64(VSR[VRB+32].bit[0])", "page_found": "Page 496 - 497", "special_registers": "MSR", "programming_notes": "This instruction extracts the least significant bit from a vector register and places it into the most significant bit of a general-purpose register, setting all other bits in the GPR to zero. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register before using this instruction. This operation is useful for extracting flags or status information from vector operations.", "example": "vextractqm r4, vb" }, { "mnemonic": "mtvsrdd", "architecture": "PowerISA", "full_name": "Move To VSR Double Double", "summary": "Moves the contents of two general-purpose registers into a vector-scalar register (VSR) as doublewords.", "syntax": "mtvsrdd XT, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | XT | RA | RB | 435 | /", "hex_opcode": "0x7C000366", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "XT", "clean": "XT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "435", "clean": "435" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "XT", "desc": "Target VSR" }, { "name": "RA", "desc": "High GPR" }, { "name": "RB", "desc": "Low GPR" } ], "extension": "VSX", "description": "Moves the contents of two general-purpose registers into a VSR as doublewords, with RA forming the high doubleword and RB forming the low doubleword. This is a VSX instruction that does not affect condition registers or status fields.", "pseudocode": "XT[0:63] ← RA\nXT[64:127] ← RB", "programming_notes": "For TX=0, mtvsrdd is treated as a VSX instruction in terms of resource availability.\nFor TX=1, mtvsrdd is treated as a Vector instruction in terms of resource availability.", "page_found": "Page 160 - 162", "special_registers": "MSR", "example": "mtvsrdd vs1, r4, r5" }, { "mnemonic": "mfvsrld", "architecture": "PowerISA", "full_name": "Move From VSR Lower Doubleword", "summary": "Moves the lower doubleword of a vector register to a general-purpose register.", "syntax": "mfvsrld RA, XS", "encoding": { "format": "XX1-form", "binary_pattern": "31 | XS | RA | 0 | 307", "hex_opcode": "0x7C000266", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "XS", "clean": "XS" }, { "raw": "RA", "clean": "RA" }, { "raw": "0", "clean": "0" }, { "raw": "307", "clean": "307" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "RA", "desc": "Target GPR" }, { "name": "XS", "desc": "Source VSR" }, { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "VSRL", "desc": "Source Vector Register Lower Doubleword" } ], "extension": "VSX", "pseudocode": "RA ← XS[64:127]", "page_found": "Page 1377 - 1378", "description": "Moves the lower doubleword of a VSR to a general-purpose register. This is a VSX instruction that does not affect condition registers or status fields.", "programming_notes": "Use mfvsrld to transfer data from a vector register's lower doubleword into a general-purpose register. Ensure that the VSR index (determined by SX and S fields) is correctly specified to avoid unintended data access. This instruction operates at user privilege level but will raise an exception if executed in supervisor mode with invalid register indices.", "example": "mfvsrld r4, vs1" }, { "mnemonic": "vstribl", "architecture": "PowerISA", "full_name": "Vector String Isolate Byte Left", "summary": "Stores the leftmost byte of each element in a vector register to memory.", "syntax": "vstribl vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | VRT | 0 | VRB | Rc | 13", "hex_opcode": "0x1000000D", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "518", "clean": "518" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21 | 22:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "VS32", "desc": "Target Vector Register" }, { "name": "VS31", "desc": "Source Vector Register" }, { "name": "RB", "desc": "Base Address General Purpose Register" } ], "extension": "VMX (AltiVec)", "page_found": "Page 1359 - 1360", "description": "Isolates the leftmost non-zero byte in each element of the source vector register and stores the result in the destination vector register. This is a VMX instruction that does not affect condition registers or status fields.", "programming_notes": "The vstribl instruction is useful for extracting the first character from strings stored in vector registers. Ensure that the input vectors are properly aligned to avoid alignment faults. This instruction operates at user privilege level and will raise an exception if executed in a kernel context without proper permissions.", "pseudocode": "for i in 0 to 15 do\n found ← 0\n for j in 0 to 7 do\n if vB[i*8 + j] != 0 then\n vD[i*8:(i+1)*8-1] ← vB[j*8:(j+1)*8-1]\n found ← 1\n break\n end if\n end for\n if found = 0 then\n vD[i*8:(i+1)*8-1] ← 0\n end if\nend for", "example": "vstribl vd, vb" }, { "mnemonic": "vstribr", "architecture": "PowerISA", "full_name": "Vector String Isolate Byte Right", "summary": "Isolates the rightmost non-zero byte in a vector string and shifts it to the left.", "syntax": "vstribr VRT,VRB", "encoding": { "format": "VX-form", "binary_pattern": "0 | VRT | VRB | Rc | 13", "hex_opcode": "0x1001000D", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "582", "clean": "582" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "Isolates the rightmost non-zero byte in each 16-byte element of the source vector and shifts it to the leftmost position of the corresponding result element; all other bytes in the result are zeroed. When Rc=1, the instruction updates CR6 based on whether a zero vector was produced.", "pseudocode": "for i in 0 to 15:\n byte_value ← VRB[i*8:(i+1)*8]\n if byte_value ≠ 0 then\n VRT[i*8:(i+1)*8] ← byte_value\n else\n VRT[i*8:(i+1)*8] ← 0\nif Rc = 1 then CR6 ← record_zero_vector(VRT)", "special_registers": "CR6 (if Rc=1)", "page_found": "Page 497 - 498", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "vstribr v1, v3" }, { "mnemonic": "xststdcsp", "architecture": "PowerISA", "full_name": "VSX Scalar Test Data Class Single-Precision", "summary": "Tests the data class of a single-precision floating-point value in a VSX register and sets condition bits accordingly.", "syntax": "xststdcsp BF, vB, DCM", "encoding": { "format": "XX2-form", "binary_pattern": "60 | BF | / | DCM | vB | 298", "hex_opcode": "0xF00004A8", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "BF", "clean": "BF" }, { "raw": "/", "clean": "/" }, { "raw": "DCM", "clean": "DCM" }, { "raw": "vB", "clean": "vB" }, { "raw": "298", "clean": "298" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "BF", "desc": "CR Field" }, { "name": "vB", "desc": "Source" }, { "name": "DCM", "desc": "Mask" }, { "name": "XB", "desc": "Index of VSX register containing the double-precision floating-point value" }, { "name": "DCMX", "desc": "Data Class Mask" } ], "extension": "VSX", "description": "The instruction tests the data class of the double-precision floating-point value in the doubleword element 0 of VSR[XB] and sets the corresponding condition bits in CR field BF and FPCC based on the specified data classes in DCMX.", "pseudocode": "if MSR.VSX=0 then\n VSX_Unavailable()\nsrc ← VSR[32×BX+B].dword[0]\nexponent ← src.bit[1:11]\nfraction ← src.bit[12:63]\nclass.Infinity ← (exponent = 0x7FF) & (fraction = 0)\nclass.NaN ← (exponent = 0x7FF) & (fraction != 0)\nclass.Zero ← (exponent = 0x000) & (fraction = 0)\nclass.Denormal ← (exponent = 0x000) & (fraction != 0) | (exponent > 0x000) & (exponent < 0x381)\nmatch ← (DCMX.bit[0] & class.NaN) | (DCMX.bit[1] & class.Infinity & !sign) | (DCMX.bit[2] & class.Infinity & sign) | (DCMX.bit[3] & class.Zero & !sign) | (DCMX.bit[4] & class.Zero & sign) | (DCMX.bit[5] & class.Denormal & !sign) | (DCMX.bit[6] & class.Denormal & sign)\nnot_SP_value ← ¬bfp64_IS_BFP32_VALUE(src)\nCR.bit[4×BF] ← FPSCR.FL ← src.sign\nCR.bit[4×BF+1] ← FPSCR.FG ← 0b0\nCR.bit[4×BF+2] ← FPSCR.FE ← match\nCR.bit[4×BF+3] ← FPSCR.FU ← not_SP_value", "special_registers": "CR, FPSCR", "page_found": "Page 903 - 904", "programming_notes": "This instruction is used to test the data class of a single-precision floating-point value in VSX registers. Ensure that the VSX facility is enabled (MSR.VSX=1) before using this instruction, otherwise it will raise an exception. The result sets condition bits in CR and FPSCR, which can be used for conditional branching based on the tested data class. Be cautious with alignment; the source value must be properly aligned within the VSR register to avoid undefined behavior.", "example": "xststdcsp cr0, vb, 0" }, { "mnemonic": "tlbiel", "architecture": "PowerISA", "full_name": "TLB Invalidate Entry Local", "summary": "Invalidates a TLB entry on the current processor only.", "syntax": "tlbiel RS, RIC, PRS, effR", "encoding": { "format": "X-form", "binary_pattern": "0 | RS | RIC | PRS | R | RB", "hex_opcode": "0x7C000224", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "RB", "clean": "RB" }, { "raw": "274", "clean": "274" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RB", "desc": "Addr" }, { "name": "RS", "desc": "Source General Purpose Register containing the LPID or PID" }, { "name": "RIC", "desc": "Radix Invalidate Control bits" }, { "name": "PRS", "desc": "Partition Scope bit" }, { "name": "effR", "desc": "Effective Radix bit" }, { "name": "R", "desc": "Effective Register bit, indicates if the operation affects effective registers" } ], "extension": "Privileged", "description": "Invalidates a TLB entry on the current processor without affecting other processors. The operation is controlled by RIC (Radix Invalidate Control), PRS (Partition Scope), and R (Effective Radix) bits; RS contains the LPID or PID, and RB provides the address to invalidate. This is a privileged instruction requiring Hypervisor mode.", "pseudocode": "// Invalidate TLB entry based on address, LPID/PID, and control fields\nif R = 0 then\n // Page Table (PT) invalidation\n tlb_invalidate_pt(RB, RS, PRS, RIC)\nelse\n // Radix Table (RT) invalidation\n tlb_invalidate_rt(RB, RS, PRS, RIC)", "page_found": "Page 1210 - 1211", "special_registers": "MSR", "programming_notes": "The tlbiel instruction is used to locally invalidate Translation Lookaside Buffer (TLB) entries based on various criteria specified by the RB, RS, RIC, PRS, and R fields. It is important to ensure that the correct values are set in these fields to achieve the desired TLB invalidation. This instruction operates at a privilege level that requires supervisor or higher authority, and it should be used carefully to avoid unintended side effects on system performance.", "example": "tlbiel r3, 0, 0, effr" }, { "mnemonic": "msgsync", "architecture": "PowerISA", "full_name": "Message Synchronize", "summary": "Provides an ordering function for stores relative to data accesses by other threads after a Directed Ultravisor Doorbell or Directed Hypervisor Doorbell interrupt.", "syntax": "msgsync", "encoding": { "format": "X-form", "binary_pattern": "31 | / | / | / | 894 | /", "hex_opcode": "0x7C0006EC", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "894", "clean": "894" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [], "extension": "Privileged", "description": "Provides memory ordering semantics for stores relative to data accesses by other threads following a Directed Ultravisor Doorbell or Directed Hypervisor Doorbell interrupt. This privileged instruction acts as a synchronization point with no operands.", "programming_notes": "When used in conjunction with msgsndu or msgsnd, Synchronize with L = 0 or 2 is executed on the thread that will execute the msgsndu or msgsnd, and msgsync is executed on another thread, typically the thread that is the target of the msgsndu or msgsnd, but possibly any other thread (partly because the software that services the Directed Ultravisor Doorbell or Directed Hypervisor Doorbell interrupt may ultimately run on a thread other than that which received the exception). The Synchronize precedes the msgsndu or msgsnd; the msgsync is executed after the Directed Ultravisor Doorbell or Directed Hypervisor Doorbell interrupt occurs, and precedes all instructions that need to 'see' the values stored by the stores that are in set A of the memory barrier created by the Synchronize.", "page_found": "Page 1312 - 1313", "pseudocode": "// Memory synchronization point for message-based interrupts\nMemory_Synchronize()", "example": "msgsync" }, { "mnemonic": "msgslp", "architecture": "PowerISA", "full_name": "Message Sleep", "summary": "Transitions the processor to a sleep state via message.", "syntax": "msgslp RB", "encoding": { "format": "X-form", "binary_pattern": "31 | / | / | RB | 118 | /", "hex_opcode": "0x7C0000EC", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "RB", "clean": "RB" }, { "raw": "118", "clean": "118" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RB", "desc": "Msg" } ], "extension": "Privileged", "description": "Transitions the processor to a sleep state via a message-based mechanism. The message content is provided in register RB. This is a privileged instruction that may put the processor into a low-power state pending an interrupt.", "pseudocode": "message ← RB\nenter_sleep_state(message)", "example": "msgslp r5" }, { "mnemonic": "vnegw", "architecture": "PowerISA", "full_name": "Vector Negate Word", "summary": "Negates the contents of each word element in a vector register.", "syntax": "vnegw vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "000100 | vD | 00110 | vB | 11000 | 000010", "hex_opcode": "0x10060602", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1540", "clean": "1540" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "VX", "desc": "Destination Vector Register" }, { "name": "VS", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vnegw, the one's-complement of each signed integer in word elements of VSR[VRB+32] is added to 1 and placed into corresponding word elements of VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n src ←EXTS(VSR[VRB+32].word[i])\n VSR[VRT+32].word[i] ←CHOP32(¬src + 1)\nend", "page_found": "Page 396 - 397", "special_registers": "MSR", "programming_notes": "The vnegw instruction negates each signed integer in the word elements of a vector register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on 32-bit words, so input data must be properly aligned. Be cautious of overflow conditions when negating large positive numbers.", "example": "vnegw vd, vb" }, { "mnemonic": "vnegd", "architecture": "PowerISA", "full_name": "Vector Negate Doubleword", "summary": "Negates each doubleword integer.", "syntax": "vnegd vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 0 | vB | 1604", "hex_opcode": "0x10070602", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1604", "clean": "1604" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" } ], "extension": "VMX (AltiVec)", "description": "Computes the two's complement negation (0 - value) of each doubleword (64-bit) element in the source vector and writes the result to the target vector. No status register updates occur.", "pseudocode": "for i in 0 to 1:\n dword ← (VRB[i*64:(i+1)*64])\n VRT[i*64:(i+1)*64] ← -dword", "page_found": "Page 397", "special_registers": "MSR", "programming_notes": "The vnegd instruction is used to negate each doubleword element in a vector. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. This operation is performed on 64-bit elements, so ensure proper alignment and size of the vectors involved.", "example": "vnegd vd, vb" }, { "mnemonic": "mtocrf", "architecture": "PowerISA", "full_name": "Move To One Condition Register Field", "summary": "Moves a GPR field to a single CR field.", "syntax": "mtocrf FXM, RS", "encoding": { "format": "XFX-form", "binary_pattern": "31 | RS | FXM | 144 | /", "hex_opcode": "0x7C100120", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "FXM", "clean": "FXM" }, { "raw": "144", "clean": "144" } ], "bit_positions": "0:5 | 6:10 | 11:18 | 19:30 | 31", "length": "32" }, "operands": [ { "name": "FXM", "desc": "Mask" }, { "name": "RS", "desc": "Source" } ], "extension": "Base", "description": "Moves a single condition register field from a GPR to the condition register, using FXM as a mask to select which CR field (CR0-CR7) receives the update. The FXM field must have only one bit set to specify a single CR field; CR bits outside the selected field are unchanged.", "pseudocode": "// Move GPR bits [0:31] to CR field selected by FXM\nfor i in 0 to 7:\n if FXM[i] = 1 then\n CR[i*4:(i+1)*4] ← RS[i*4:(i+1)*4]", "special_registers": "CR", "programming_notes": "The mtocrf instruction is used to transfer a specific field from the Condition Register (CR) to a general-purpose register. Ensure that exactly one bit in the FXM field is set to avoid undefined behavior of the Condition Register. This instruction operates at user privilege level and does not generate exceptions under normal conditions.", "example": "mtocrf 0xFF, r3" }, { "mnemonic": "mfocrf", "architecture": "PowerISA", "full_name": "Move From One Condition Register Field", "summary": "Moves a single CR field to a GPR.", "syntax": "mfocrf RT, FXM", "encoding": { "format": "XFX-form", "binary_pattern": "31 | RT | FXM | 19 | /", "hex_opcode": "0x7C100026", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "FXM", "clean": "FXM" }, { "raw": "19", "clean": "19" } ], "bit_positions": "0:5 | 6:10 | 11:18 | 19:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "FXM", "desc": "Mask" } ], "extension": "Base", "description": "Moves a single condition register field to a GPR, using FXM as a mask to select which CR field (CR0-CR7) is read. The FXM field must have only one bit set; the selected 4-bit CR field is placed in bits [0:3] of RT, with all other GPR bits zeroed.", "pseudocode": "// Move CR field selected by FXM to GPR bits [0:31]\nRT ← 0\nfor i in 0 to 7:\n if FXM[i] = 1 then\n RT[i*4:(i+1)*4] ← CR[i*4:(i+1)*4]", "page_found": "Page 166", "special_registers": "CR", "programming_notes": "The mfocrf instruction is used to extract a specific condition register field into a general-purpose register. Ensure that exactly one bit in the FXM field is set to avoid undefined behavior. This instruction operates at user privilege level and does not generate exceptions under normal conditions.", "example": "mfocrf r3, 0xFF" }, { "mnemonic": "neg", "architecture": "PowerISA", "full_name": "Negate", "summary": "Computes the two's complement negation of a register (0 - RT).", "syntax": "neg RT, RA", "encoding": { "format": "XO-form", "binary_pattern": "31 | RT | RA | 00000 | OE | 104 | Rc", "hex_opcode": "0x7C0000D0", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "00000", "clean": "00000" }, { "raw": "OE", "clean": "OE" }, { "raw": "104", "clean": "104" }, { "raw": "Rc", "clean": "Rc" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21 | 22:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "RA", "desc": "Source Register" } ], "pseudocode": "result ← -(RA)\nRT ← result\nif OE = 1 then\n if RA = 0x8000_0000_0000_0000 then\n XER[OV] ← 1; XER[SO] ← 1\n else\n XER[OV] ← 0\nif Rc = 1 then\n CR0 ← record_result(result)", "example": "neg r3, r4", "example_note": "r3 = -r4", "extension": "Base", "description": "Computes the two's complement negation (0 - RA) of the source register and stores the result in RT. If OE=1, sets OV and SO in XER on signed overflow (when RA=0x8000_0000_0000_0000). When Rc=1, updates CR0 based on the result.", "page_found": "Page 114", "special_registers": "CR0", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER." }, { "mnemonic": "or", "architecture": "PowerISA", "full_name": "OR Logical Operation", "summary": "Performs a bitwise OR operation on the contents of two registers and places the result in a third register.", "syntax": "or RT,RA,RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 444 | Rc", "hex_opcode": "0x7C000378", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "444", "clean": "444" }, { "raw": "Rc", "clean": "Rc" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RA", "desc": "Target Register" }, { "name": "RS", "desc": "Source Register 1" }, { "name": "RB", "desc": "Source Register 2" }, { "name": "RT", "desc": "Target General Purpose Register" } ], "pseudocode": "RA ← RS | RB\nif Rc = 1 then CR0 ← (RA = 0, RA < 0, RA > 0, SO)", "example": "or r3, r4, r5", "example_note": "r3 = r4 | r5", "extension": "Base", "description": "Performs a bitwise OR operation on two general-purpose registers and stores the result in a third register. This is a base category instruction that operates on the full 64-bit register width. If Rc=1, the instruction updates CR0 based on the result.", "programming_notes": "Warning: Other forms of or Rx,Rx,Rx that are not described in this section and in Section 4.3.3 may also cause program priority to change. Use of these forms should be avoided except when software explicitly intends to alter program priority. If a no-op is needed, the preferred no-op (ori 0,0,0) should be used.", "page_found": "Page 1022 - 1023", "special_registers": "CR0, XER", "extended_mnemonics": [ { "mnemonic": "miso", "equivalent": "or 26,26,26" } ] }, { "mnemonic": "ori", "architecture": "PowerISA", "full_name": "OR Immediate", "summary": "Performs a bitwise OR operation between the contents of a register and an immediate value, placing the result in another register.", "syntax": "ori RT,RS,SImm", "encoding": { "format": "D-form", "binary_pattern": "24 | RS | RA | UI", "hex_opcode": "0x60000000", "visual_parts": [ { "raw": "24", "clean": "24" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "UI", "clean": "UI" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "operands": [ { "name": "RA", "desc": "Target Register" }, { "name": "RS", "desc": "Source Register" }, { "name": "UI", "desc": "Unsigned 16-bit Immediate" }, { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "SImm", "desc": "Sign-Extended 16-bit Immediate Value" } ], "pseudocode": "RA ← RS | (0x0000 || UI)", "example": "ori r3, r4, 0x1", "example_note": "Set bit 0.", "extension": "Base", "description": "Performs a bitwise OR between a general-purpose register and a 16-bit unsigned immediate value, storing the result in another register. This is a base category instruction with no condition register or status updates.", "programming_notes": "Warning: Other forms of ori Rx,Rx,0 that are not described in this section may also have micro-architectural effects on program execution. Use of these forms should be avoided except when software needs the associated micro-architectural effects.\n\nProgramming Note: This no-op is intended to be used by software for providing protection against the Spectre class of transient execution attacks by restricting eventually discarded out-of-order execution effects with transient register values, which may compromise confidential data via other covert channels.", "extended_mnemonics": [ { "mnemonic": "nop", "equivalent_to": "ori 0,0,0" }, "exser" ], "page_found": "Page 133 - 134" }, { "mnemonic": "oris", "architecture": "PowerISA", "full_name": "OR Immediate Shifted", "summary": "Performs a bitwise OR with a 16-bit immediate shifted left by 16 bits.", "syntax": "oris RA, RS, UI", "encoding": { "format": "D-form", "binary_pattern": "25 | RS | RA | UI", "hex_opcode": "0x64000000", "visual_parts": [ { "raw": "25", "clean": "25" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "UI", "clean": "UI" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target Register" }, { "name": "RS", "desc": "Source Register" }, { "name": "UI", "desc": "Unsigned 16-bit Immediate" } ], "pseudocode": "RA ← RS | (UI || 0x0000)", "example": "oris r3, r4, 0xFFFF", "example_note": "Set upper 16 bits.", "extension": "Base", "description": "Performs a bitwise OR between a general-purpose register and a 16-bit unsigned immediate value shifted left by 16 bits, storing the result in another register. This is a base category instruction used to set high-order bits with no condition register updates.", "page_found": "Page 134", "programming_notes": "The oris instruction is commonly used to set specific bits in a register by ORing it with an immediate value. Be cautious of overflow if UI exceeds the upper limit, as it will be truncated. This instruction operates at user privilege level and does not generate exceptions under normal circumstances." }, { "mnemonic": "popcntd", "architecture": "PowerISA", "full_name": "Population Count Doubleword", "summary": "Counts the number of set bits (1s) in a 64-bit register.", "syntax": "popcntd RA, RS", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | 00000 | 506 | /", "hex_opcode": "0x7C0003F4", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "00000", "clean": "00000" }, { "raw": "506", "clean": "506" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target Register" }, { "name": "RS", "desc": "Source Register" } ], "pseudocode": "RA ← popcount(RS[0:63])", "example": "popcntd r3, r4", "example_note": "Hamming weight of r4.", "extension": "Base", "description": "Counts the number of set bits (population count) in a 64-bit general-purpose register and stores the count in another register. This is a base category instruction that produces the count of 1-bits across the entire doubleword with no condition register or status updates.", "page_found": "Page 139", "programming_notes": "The popcntd instruction is useful for counting the number of set bits (1s) in a 64-bit value. It operates on each doubleword independently, so if you're working with 128-bit values, ensure that both halves are processed separately. This instruction does not require any special alignment and can be executed at user privilege level. Be cautious when using this instruction in performance-critical sections, as it may have varying execution times depending on the input data." }, { "mnemonic": "popcntw", "architecture": "PowerISA", "full_name": "Population Count Word", "summary": "Counts the number of set bits (1s) in the lower 32 bits of a register.", "syntax": "popcntw RA, RS", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | 00000 | 378 | /", "hex_opcode": "0x7C0002F4", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "00000", "clean": "00000" }, { "raw": "378", "clean": "378" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target Register" }, { "name": "RS", "desc": "Source Register" } ], "pseudocode": "RA ← popcount(RS[32:63])", "example": "popcntw r3, r4", "example_note": "Hamming weight of 32-bit word.", "extension": "Base", "description": "Counts the number of set bits in the lower 32 bits of a general-purpose register and stores the count in another register. This is a base category instruction that produces the count of 1-bits in the word, with the upper 32 bits of the result cleared and no condition register or status updates.", "programming_notes": "The popcntw instruction is useful for counting the number of set bits (1s) in a 32-bit word. It operates on each 32-bit segment of the source register, making it ideal for bit manipulation tasks where population count is needed. Ensure that the source and destination registers are properly aligned to avoid unexpected behavior. This instruction does not require any special privileges and will execute without exceptions if the operands are valid." }, { "mnemonic": "tlbilx", "architecture": "PowerISA", "full_name": "TLB Invalidate Local Extended", "summary": "Invalidates TLB entries on the local processor based on Process ID (PID).", "syntax": "tlbilx T, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | T | RA | RB | 18 | /", "hex_opcode": "0x7C000024", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "T", "clean": "T" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "18", "clean": "18" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "T", "desc": "Type" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Embedded", "description": "Invalidates TLB entries on the local processor based on Process ID and address criteria specified by the T field. This is an embedded category, privileged instruction that performs no condition register updates but modifies TLB state; behavior depends on the processor's memory management architecture.", "pseudocode": "Invalidate TLB entries matching: T field type, EA = (RA), PID = MMUPID, based on processor implementation", "example": "tlbilx 0, r4, r5" }, { "mnemonic": "lwdi", "architecture": "PowerISA", "full_name": "Load Word with Decoration Indexed", "summary": "Loads a word and sends decoration sideband signals to the bus.", "syntax": "lwdi RT, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | RA | RB | 788 | /", "hex_opcode": "0x7C000628", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "788", "clean": "788" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Embedded", "description": "Loads a 32-bit word from memory at an address computed from two general-purpose registers and transmits sideband decoration signals. This is an embedded category instruction used in specialized memory systems with no condition register or status updates.", "pseudocode": "EA ← RA + RB\nRT ← [EA][32:63]\nSend decoration signals on memory bus", "example": "lwdi r3, r4, r5" }, { "mnemonic": "stdi", "architecture": "PowerISA", "full_name": "Store Word with Decoration Indexed", "summary": "Stores a word and sends decoration sideband signals.", "syntax": "stdi RS, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 916 | /", "hex_opcode": "0x7C000728", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "916", "clean": "916" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RS", "desc": "Source" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Embedded", "description": "Stores a 32-bit word from a general-purpose register to memory at an address computed from two other registers and transmits sideband decoration signals. This is an embedded category instruction used in specialized memory systems with no condition register or status updates.", "pseudocode": "EA ← RA + RB\n[EA][32:63] ← RS\nSend decoration signals on memory bus", "example": "stdi r3, r4, r5" }, { "mnemonic": "ehpriv", "architecture": "PowerISA", "full_name": "Embedded Hypervisor Privilege", "summary": "Enters embedded hypervisor privileged state.", "syntax": "ehpriv OC", "encoding": { "format": "X-form", "binary_pattern": "31 | 0 | 0 | OC | 270 | /", "hex_opcode": "0x7C00021E", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "OC", "clean": "OC" }, { "raw": "270", "clean": "270" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "OC", "desc": "Opcode" } ], "extension": "Embedded", "description": "Enters embedded hypervisor privileged state, allowing execution of hypervisor-privileged instructions. This instruction is only available in embedded processor implementations and requires hypervisor privilege level. No condition registers or status fields are affected by this instruction.", "pseudocode": "if not in hypervisor mode then\n raise Hypervisor Privilege exception\nelse\n enter hypervisor privileged state based on OC field", "example": "ehpriv 0" }, { "mnemonic": "msync", "architecture": "PowerISA", "full_name": "Memory Synchronize", "summary": "Synchronizes memory accesses (Alias for sync).", "syntax": "msync", "encoding": { "format": "X-form", "binary_pattern": "31 | 0 | 0 | 0 | 598 | /", "hex_opcode": "0x7C0004AC", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "598", "clean": "598" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [], "extension": "Embedded", "description": "Provides full memory synchronization for embedded processors, equivalent to sync with no operands. This instruction ensures all prior loads and stores are globally visible before any subsequent memory accesses are initiated. No condition registers or status fields are affected.", "pseudocode": "wait until all prior memory accesses complete\nwait until all prior memory accesses are globally visible", "example": "msync" }, { "mnemonic": "add", "architecture": "PowerISA", "full_name": "Add", "summary": "Adds the contents of two registers and places the result in a third register.", "syntax": "add RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "31 | RT | RA | RB | OE | 266 | Rc", "hex_opcode": "0x7C000214", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "OE", "clean": "OE" }, { "raw": "266", "clean": "266" }, { "raw": "Rc", "clean": "Rc" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21 | 22:30 | 31" }, "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "RA", "desc": "Source Register 1" }, { "name": "RB", "desc": "Source Register 2" }, { "name": "rPX", "desc": "Destination General Purpose Register" }, { "name": "rPS", "desc": "Source General Purpose Register" }, { "name": "rNS", "desc": "Source General Purpose Register" } ], "pseudocode": "RT ← RA + RB\nif OE = 1 then\n if overflow then XER[OV] ← 1; XER[SO] ← 1\nif Rc = 1 then\n CR0 ← (RT < 0) || (RT > 0) || (RT = 0) || XER[SO]", "example": "add r3, r4, r5", "example_note": "r3 = r4 + r5", "extension": "Base", "description": "Adds the values in registers RA and RB and places the result in RT. If OE=1, sets XER[SO] and XER[OV] on signed overflow. If Rc=1, updates CR0 to reflect the result (LT, GT, EQ, SO). No exception is raised on overflow unless OE=1.", "special_registers": "CR0, XER", "page_found": "Page 624 - 625", "programming_notes": "add, add., and subf are the preferred instructions..." }, { "mnemonic": "addc", "architecture": "PowerISA", "full_name": "Add Carrying", "summary": "Adds the contents of two registers and a carry bit, placing the result in a target register.", "syntax": "addc RT,RA,RB", "encoding": { "format": "XO-form", "binary_pattern": "31 | RT | RA | RB | OE | 10 | Rc", "hex_opcode": "0x7C000014", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "OE", "clean": "OE" }, { "raw": "10", "clean": "10" }, { "raw": "Rc", "clean": "Rc" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21 | 22:30 | 31" }, "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "RA", "desc": "Source Register 1" }, { "name": "RB", "desc": "Source Register 2" } ], "pseudocode": "if 'addc' then\n RT <- (RA) + (RB)\nelse if 'addc.' then\n RT <- (RA) + (RB)\n if Rc=1 then update CR0\nelse if 'addco' then\n RT <- (RA) + (RB)\n if OE=1 then update XER[SO], XER[OV]\nelse if 'addco.' then\n RT <- (RA) + (RB)\n if Rc=1 then update CR0\n if OE=1 then update XER[SO], XER[OV]", "example": "addc r3, r4, r5", "example_note": "r3 = r4 + r5 (Updates Carry)", "extension": "Base", "description": "The sum (RA) + (RB) is placed into register RT.", "special_registers": "CR0, XER", "page_found": "Page 111 - 112", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER." }, { "mnemonic": "adde", "architecture": "PowerISA", "full_name": "Add Extended", "summary": "Adds two registers plus the current Carry bit.", "syntax": "adde RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "31 | RT | RA | RB | OE | 138 | Rc", "hex_opcode": "0x7C000114", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "OE", "clean": "OE" }, { "raw": "138", "clean": "138" }, { "raw": "Rc", "clean": "Rc" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21 | 22:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "RA", "desc": "Source Register 1" }, { "name": "RB", "desc": "Source Register 2" } ], "pseudocode": "RT ← RA + RB + XER[CA]\nif OE = 1 then\n if overflow then XER[OV] ← 1; XER[SO] ← 1\nif result > 2^64-1 or result < -2^64 then XER[CA] ← 1 else XER[CA] ← 0\nif Rc = 1 then\n CR0 ← (RT < 0) || (RT > 0) || (RT = 0) || XER[SO]", "example": "adde r3, r4, r5", "example_note": "r3 = r4 + r5 + CA", "extension": "Base", "description": "Adds the values in registers RA and RB plus the Carry bit from XER and places the result in RT. If OE=1, sets XER[SO] and XER[OV] on signed overflow. If Rc=1, updates CR0 based on the result. This instruction is used for multi-precision arithmetic.", "page_found": "Page 112", "special_registers": "CR0", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER." }, { "mnemonic": "addi", "architecture": "PowerISA", "full_name": "Add Immediate", "summary": "Adds a signed immediate value to the contents of a register and places the result in another register.", "syntax": "addi RT, RA, SI", "encoding": { "format": "D-form", "binary_pattern": "14 | RT | RA | SI", "hex_opcode": "0x38000000", "visual_parts": [ { "raw": "14", "clean": "14" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "SI", "clean": "SI" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "RA", "desc": "Source Register (0 means 0)" }, { "name": "SI", "desc": "Signed 16-bit Immediate" }, { "name": "SIMM", "desc": "16-bit Signed Immediate Value" } ], "pseudocode": "RT ← (RA | 0) + sign_extend(SI)", "example": "addi r3, r4, 10", "example_note": "r3 = r4 + 10", "extension": "Base", "description": "Adds the signed 16-bit immediate value SI to the contents of register RA (or 0 if RA=0) and stores the result in RT. This instruction does not affect any condition registers or XER flags, and no overflow checking is performed.", "programming_notes": "addi, addis, add, and subf are the preferred instructions for addition and subtraction, because they set few status bits.", "extended_mnemonics": [ { "mnemonic": "la", "equivalent_to": "addi RT,RA,SI" }, { "mnemonic": "li", "equivalent_to": "addi RT,0,SI" }, { "mnemonic": "subi", "equivalent_to": "addi RT,RA,-si" } ], "page_found": "Page 108 - 110" }, { "mnemonic": "addic", "architecture": "PowerISA", "full_name": "Add Immediate Carrying", "summary": "Adds an immediate to a register and updates the Carry bit.", "syntax": "addic RT,RA,SI", "encoding": { "format": "D-form", "binary_pattern": "12 | RT | RA | SI", "hex_opcode": "0x30000000", "visual_parts": [ { "raw": "12", "clean": "12" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "SI", "clean": "SI" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "RA", "desc": "Source Register" }, { "name": "SI", "desc": "Signed 16-bit Immediate" } ], "pseudocode": "RT <- (RA) + EXTS(SI); CA <- Carry", "example": "addic r3, r4, 10", "example_note": "r3 = r4 + 10 (Updates CA)", "extension": "Base", "description": "The sum (RA) + SI is placed into register RT.", "special_registers": "XER, CR0", "extended_mnemonics": [ { "mnemonic": "subic", "equivalent_to": "addic RT,RA,-si" } ], "page_found": "Page 110 - 112", "programming_notes": "The `addic` instruction adds an immediate value to a register and sets the carry bit in the XER. It's commonly used for arithmetic operations where overflow detection is needed. Ensure that the immediate value fits within 16 bits, as it is sign-extended before addition. This instruction operates at user privilege level." }, { "mnemonic": "addic.", "architecture": "PowerISA", "full_name": "Add Immediate Carrying and Record", "summary": "Adds an immediate, updates Carry, and updates Condition Register Field 0 (CR0).", "syntax": "addic. RT, RA, SI", "encoding": { "format": "D-form", "binary_pattern": "13 | RT | RA | SI", "hex_opcode": "0x34000000", "visual_parts": [ { "raw": "13", "clean": "13" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "SI", "clean": "SI" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "RA", "desc": "Source Register" }, { "name": "SI", "desc": "Signed 16-bit Immediate" } ], "pseudocode": "RT ← RA + sign_extend(SI)\nif RT > 2^64-1 or RT < -2^64 then XER[CA] ← 1 else XER[CA] ← 0\nCR0 ← (RT < 0) || (RT > 0) || (RT = 0) || XER[SO]", "example": "addic. r3, r4, -5", "example_note": "r3 = r4 - 5 (Updates CA and CR0)", "extension": "Base", "description": "Adds the signed 16-bit immediate SI to register RA and stores the result in RT, updating the Carry bit in XER and CR0. The '.' suffix indicates that CR0 is updated based on the result (LT, GT, EQ, SO). The Carry flag reflects whether the addition produced a result greater than 2^64-1.", "page_found": "Page 111", "special_registers": "CR0", "programming_notes": "The addic instruction is useful for adding an immediate value to a register while also handling potential overflow by setting the carry flag. Be cautious of overflow conditions that may affect subsequent operations. The result and comparison are recorded in separate registers, so ensure proper register management to avoid unintended data loss." }, { "mnemonic": "addis", "architecture": "PowerISA", "full_name": "Add Immediate Shifted", "summary": "Adds an immediate value shifted left by 16 bits to the contents of a register and places the result in another register.", "syntax": "addis RT, RA, SI", "encoding": { "format": "D-form", "binary_pattern": "001111 | RT | RA | SIMM", "hex_opcode": "0x3C000000", "visual_parts": [ { "raw": "15", "clean": "15" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "SI", "clean": "SI" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "RA", "desc": "Source Register (0 means 0)" }, { "name": "SI", "desc": "Signed 16-bit Immediate" }, { "name": "SIMM", "desc": "16-bit signed immediate value shifted left by 16 bits" } ], "pseudocode": "RT ← (RA | 0) + (sign_extend(SI) << 16)", "example": "addis r3, r4, 1", "example_note": "r3 = r4 + 65536 (0x10000)", "extension": "Base", "description": "Adds the signed 16-bit immediate SI shifted left by 16 bits to register RA (or 0 if RA=0) and stores the result in RT. This is commonly used to load the high-order 16 bits of a 32-bit constant. No condition registers or XER flags are affected.", "extended_mnemonics": [ { "mnemonic": "lis", "equivalent_to": "addis RT,0,SI" }, { "mnemonic": "subis", "equivalent_to": "addis RT,RA,-si" } ], "page_found": "Page 109 - 110", "programming_notes": "The addis instruction is commonly used for loading large immediate values into a register by shifting the 16-bit immediate value left by 16 bits and adding it to the contents of another register. If RA is zero, the instruction effectively sign-extends the immediate value and places it in RT. This instruction does not require any special privileges and can be used at any privilege level. However, developers should ensure that the immediate value does not cause overflow when shifted and added, as this could lead to unexpected results." }, { "mnemonic": "addme", "architecture": "PowerISA", "full_name": "Add to Minus One Extended", "summary": "Adds the contents of a register and a constant minus one, with optional overflow exception.", "syntax": "addme RT,RA", "encoding": { "format": "XO-form", "binary_pattern": "31 | RT | RA | 00000 | OE | 234 | Rc", "hex_opcode": "0x7C0001D4", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "00000", "clean": "00000" }, { "raw": "OE", "clean": "OE" }, { "raw": "234", "clean": "234" }, { "raw": "Rc", "clean": "Rc" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21 | 22:30 | 31" }, "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "RA", "desc": "Source Register" } ], "pseudocode": "if 'addme' then\n RT <- (RA) + CA - 1", "example": "addme r3, r4", "example_note": "r3 = r4 + CA - 1", "extension": "Base", "description": "The sum (RA) + CA - 1 is placed into register RT. The carry bit (CA) is used in the calculation.", "special_registers": "CR0, XER", "extended_mnemonics": [ "addme.", "addmeo", "addmeo." ], "page_found": "Page 112 - 114", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER." }, { "mnemonic": "addze", "architecture": "PowerISA", "full_name": "Add to Zero Extended", "summary": "Adds a register, 0, and the Carry bit.", "syntax": "addze RT, RA", "encoding": { "format": "XO-form", "binary_pattern": "31 | RT | RA | 00000 | OE | 202 | Rc", "hex_opcode": "0x7C000194", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "00000", "clean": "00000" }, { "raw": "OE", "clean": "OE" }, { "raw": "202", "clean": "202" }, { "raw": "Rc", "clean": "Rc" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21 | 22:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "RA", "desc": "Source Register" } ], "pseudocode": "RT ← RA + 0 + XER[CA]\nif OE = 1 then\n (OV, CA) ← overflow and carry results\nif Rc = 1 then\n CR0 ← (RT == 0, RT < 0, RT > 0, XER[SO])", "example": "addze r3, r4", "example_note": "r3 = r4 + CA", "extension": "Base", "description": "Adds the value in RA, zero, and the Carry bit (XER[CA]), storing the result in RT. This instruction is commonly used to propagate a carry or decrement by one when combined with other arithmetic operations. Condition register CR0 is updated if Rc=1; overflow is recorded in XER[OV] if OE=1.", "page_found": "Page 113", "special_registers": "CR0", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER." }, { "mnemonic": "and", "architecture": "PowerISA", "full_name": "AND", "summary": "Performs a bitwise AND operation on the contents of two registers and places the result into another register.", "syntax": "and RT,RS,RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 28 | Rc", "hex_opcode": "0x7C000038", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "28", "clean": "28" }, { "raw": "Rc", "clean": "Rc" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RA", "desc": "Target Register" }, { "name": "RS", "desc": "Source Register 1" }, { "name": "RB", "desc": "Source Register 2" }, { "name": "RT", "desc": "Target General Purpose Register" } ], "pseudocode": "if 'and' then\n RT <- (RS) & (RB)\nelse if 'and.' then\n RT <- (RS) & (RB)", "example": "and r3, r4, r5", "example_note": "r3 = r4 & r5", "extension": "Base", "description": "The contents of register RS are ANDed with the contents of register RB and the result is placed into register RA.", "special_registers": "CR0", "programming_notes": "Some forms of and Rx, Rx, Rx provide special functions; see Section 11.3 of Book III.", "page_found": "Page 134 - 136" }, { "mnemonic": "andc", "architecture": "PowerISA", "full_name": "AND with Complement", "summary": "Performs a bitwise AND between RS and the one's complement of RB.", "syntax": "andc RA, RS, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 60 | Rc", "hex_opcode": "0x7C000078", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "60", "clean": "60" }, { "raw": "Rc", "clean": "Rc" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target Register" }, { "name": "RS", "desc": "Source Register 1" }, { "name": "RB", "desc": "Source Register 2" } ], "pseudocode": "RA ← RS & ~RB\nif Rc = 1 then\n CR0 ← (RA == 0, RA < 0, RA > 0, XER[SO])", "example": "andc r3, r4, r5", "example_note": "r3 = r4 & ~r5", "extension": "Base", "description": "Performs a bitwise AND between RS and the one's complement (bitwise NOT) of RB, storing the result in RA. This is equivalent to RS AND (NOT RB). Condition register CR0 is updated if Rc=1.", "page_found": "Page 136", "special_registers": "CR0", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER." }, { "mnemonic": "andi.", "architecture": "PowerISA", "full_name": "AND Immediate D-form with Record Update", "summary": "Performs a bitwise AND operation between the contents of a register and an immediate value, and updates the condition register.", "syntax": "andi. RA, RS, UI", "encoding": { "format": "D-form", "binary_pattern": "28 | RS | RA | UI", "hex_opcode": "0x70000000", "visual_parts": [ { "raw": "28", "clean": "28" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "UI", "clean": "UI" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "operands": [ { "name": "RA", "desc": "Target Register" }, { "name": "RS", "desc": "Source Register" }, { "name": "UI", "desc": "Unsigned 16-bit Immediate" }, { "name": "RT", "desc": "Target General Purpose Register" } ], "pseudocode": "RA <- (RS) & (0x0000 || UI); CR0 <- Compare(RA, 0)", "example": "andi. r3, r4, 0xF", "example_note": "r3 = r4 & 0xF", "extension": "Base", "description": "The contents of register RS are ANDed with 480 || UI and the result is placed into register RA. The first three bits of CR Field 0 are set as described in Section 3.3.8.", "special_registers": "CR0", "page_found": "Page 132 - 134", "programming_notes": "The andi. instruction performs a bitwise AND operation between the contents of register RS and an immediate value UI, storing the result in RA. It also updates CR0 to reflect if the result is zero or not. Ensure that the immediate value fits within 16 bits as it is zero-extended to 32 bits before the operation." }, { "mnemonic": "andis.", "architecture": "PowerISA", "full_name": "AND Immediate Shifted", "summary": "Performs a bitwise AND between a register and a 16-bit immediate shifted left by 16 bits. Always updates CR0.", "syntax": "andis. RA, RS, UI", "encoding": { "format": "D-form", "binary_pattern": "29 | RS | RA | UI", "hex_opcode": "0x74000000", "visual_parts": [ { "raw": "29", "clean": "29" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "UI", "clean": "UI" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target Register" }, { "name": "RS", "desc": "Source Register" }, { "name": "UI", "desc": "Unsigned 16-bit Immediate" } ], "pseudocode": "RA ← RS & (UI << 16)\nCR0 ← (RA == 0, RA < 0, RA > 0, XER[SO])", "example": "andis. r3, r4, 0x1234", "example_note": "r3 = r4 & 0x12340000", "extension": "Base", "description": "Performs a bitwise AND between RS and UI shifted left by 16 bits, storing the result in RA. The immediate operand is treated as unsigned and positioned in bits 16-31 of a 32-bit value with bits 0-15 cleared. Condition register CR0 is always updated regardless of the Rc bit (the dot indicates this behavior).", "page_found": "Page 133", "special_registers": "CR0", "programming_notes": "The andis. instruction is useful for masking or clearing specific bits in a register by shifting an immediate value left by 5 bits before performing the AND operation. Be cautious with alignment as it affects performance; ensure that the immediate value does not exceed 31 to avoid unexpected results. This instruction operates at user privilege level and can generate exceptions if RA is an invalid register. The result of the operation sets CR0, which can be used for conditional branching." }, { "mnemonic": "paddi", "architecture": "PowerISA", "full_name": "Prefixed Add Immediate", "summary": "Adds 34-bit immediate.", "syntax": "paddi RT, RA, SI, R", "encoding": { "format": "MLS:D-form", "binary_pattern": "1 | 2 | R | 0 | D0 | 14 | RT | RA | D1", "hex_opcode": "0x0600000038000000", "visual_parts": [ { "raw": "000001", "clean": "000001" }, { "raw": "10", "clean": "10" }, { "raw": "...", "clean": "..." }, { "raw": "14", "clean": "14" }, { "raw": "...", "clean": "..." } ], "length": "64", "bit_positions": "0:5 | 6:7 | 8 | 9:13 | 14:31 | 32:37 | 38:42 | 43:47 | 48:63" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RA", "desc": "Src" }, { "name": "SI", "desc": "Imm" }, { "name": "R", "desc": "PC-Rel" } ], "extension": "Prefixed", "description": "Adds a 34-bit sign-extended immediate to RA (or 0 if RA=0) and stores the result in RT. The immediate is formed by concatenating prefix and suffix fields across a 64-bit prefixed instruction pair. When R=0, the offset is absolute; when R=1, it is PC-relative. This is a privileged Base extension instruction for 64-bit processors.", "pseudocode": "if R = 1 then\n RT ← (RA | 0 if RA=0) + sign_extend(SI, 34) + CIA\nelse\n RT ← (RA | 0 if RA=0) + sign_extend(SI, 34)", "page_found": "Page 109", "programming_notes": "The paddi instruction is commonly used for loading addresses or small immediate values into registers. Be cautious with alignment; ensure that the immediate value does not cause overflow, which could lead to unexpected results. This instruction operates at user privilege level and does not generate exceptions under normal circumstances.", "example": "paddi r3, r4, 16, 0" }, { "mnemonic": "pla", "architecture": "PowerISA", "full_name": "Prefixed Load Address (Pseudo)", "summary": "Pseudo-instruction for paddi with R=1. Loads the address of a label.", "syntax": "pla RT, label", "encoding": { "format": "Pseudo", "binary_pattern": "1 | 2 | R | 0 | D0 | 14 | RT | 0 | D1", "hex_opcode": "0x0600000038000000", "visual_parts": [ { "raw": "paddi RT, 0, label, 1", "clean": "paddi RT, 0, label, 1" } ], "length": "64", "bit_positions": "0:5 | 6:7 | 8 | 9:13 | 14:31 | 32:37 | 38:42 | 43:47 | 48:63" }, "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "label", "desc": "Symbol Name" } ], "pseudocode": "RT ← CIA + sign_extend(label_offset, 34)", "example": "pla r3, my_var", "example_note": "Get address of my_var without TOC.", "extension": "Prefixed", "description": "Pseudo-instruction that loads the address of a label into RT. It is an assembly-time alias for 'paddi RT, 0, label, 1', where R=1 selects PC-relative addressing. This is a 64-bit prefixed instruction available only on compatible processors.", "page_found": "Page 109", "special_registers": "PC", "programming_notes": "The pla instruction is used to load the address of a label into a register, effectively calculating the absolute address of the target. This is useful for setting up pointers or addresses dynamically. Ensure that the label is correctly defined and accessible in your code. The instruction operates at the same privilege level as the current execution context." }, { "mnemonic": "pld", "architecture": "PowerISA", "full_name": "Prefixed Load Doubleword", "summary": "Loads a 64-bit value from memory using a 34-bit immediate offset (PC-relative or absolute).", "syntax": "pld RT, D34(RA), R", "encoding": { "format": "MLS:D-form", "binary_pattern": "1 | 2 | R | 0 | D0 | 57 | RT | RA | D1", "hex_opcode": "0x04000000E4000000", "visual_parts": [ { "raw": "000001", "clean": "000001" }, { "raw": "10", "clean": "10" }, { "raw": "0", "clean": "0" }, { "raw": "00000", "clean": "00000" }, { "raw": "...", "clean": "..." }, { "raw": "57", "clean": "57" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "D34", "clean": "D34" } ], "length": "64", "bit_positions": "0:5 | 6:7 | 8 | 9:13 | 14:31 | 32:37 | 38:42 | 43:47 | 48:63" }, "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "D34", "desc": "34-bit Displacement" }, { "name": "RA", "desc": "Base Register" }, { "name": "R", "desc": "PC-Relative Flag" } ], "pseudocode": "if R = 1 then\n EA ← (RA | 0 if RA=0) + sign_extend(D34, 34) + CIA\nelse\n EA ← (RA | 0 if RA=0) + sign_extend(D34, 34)\nRT ← [EA]", "example": "pld r3, label@pcrel(0), 1", "example_note": "Load value from label.", "extension": "Prefixed", "description": "Loads a 64-bit doubleword from memory at the address calculated from RA plus a 34-bit immediate displacement, storing the result in RT. When R=1, the displacement is PC-relative; when R=0, it is treated as absolute. This is a 64-bit prefixed instruction from the Prefixed extension.", "page_found": "Page 91", "programming_notes": "The pld instruction is commonly used for loading doubleword data from memory into a register. Ensure the base address and offset are correctly calculated to avoid accessing invalid memory locations. This instruction operates at user privilege level unless specified otherwise." }, { "mnemonic": "pststd", "architecture": "PowerISA", "full_name": "Prefixed Store Doubleword", "summary": "Stores a 64-bit value to memory using a 34-bit immediate offset.", "syntax": "pststd RS, D34(RA), R", "encoding": { "format": "MLS:D-form", "binary_pattern": "1 | 2 | R | 0 | D0 | 61 | RS | RA | D1", "hex_opcode": "0x04000000F4000000", "visual_parts": [ { "raw": "000001", "clean": "000001" }, { "raw": "10", "clean": "10" }, { "raw": "0", "clean": "0" }, { "raw": "00000", "clean": "00000" }, { "raw": "...", "clean": "..." }, { "raw": "61", "clean": "61" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "D34", "clean": "D34" } ], "length": "64", "bit_positions": "0:5 | 6:7 | 8 | 9:13 | 14:31 | 32:37 | 38:42 | 43:47 | 48:63" }, "operands": [ { "name": "RS", "desc": "Source Register" }, { "name": "D34", "desc": "34-bit Displacement" }, { "name": "RA", "desc": "Base Register" }, { "name": "R", "desc": "PC-Relative Flag" } ], "pseudocode": "if R = 1 then\n EA ← (RA | 0 if RA=0) + sign_extend(D34, 34) + CIA\nelse\n EA ← (RA | 0 if RA=0) + sign_extend(D34, 34)\n[EA] ← RS", "example": "pststd r3, label@pcrel(0), 1", "example_note": "Store value to label.", "extension": "Prefixed", "special_registers": "PC", "programming_notes": "The pststd instruction stores a doubleword from the source register to memory. It uses the Program Counter (PC) or an effective address calculated from the base register and displacement. Ensure proper alignment for optimal performance; unaligned accesses may incur penalties. This instruction operates at user privilege level.", "description": "Stores a 64-bit doubleword from RS to memory at the address calculated from RA plus a 34-bit immediate displacement. When R=1, the displacement is PC-relative; when R=0, it is treated as absolute. This is a 64-bit prefixed instruction from the Prefixed extension." }, { "mnemonic": "plwz", "architecture": "PowerISA", "full_name": "Prefixed Load Word and Zero", "summary": "Loads a 32-bit word and zero-extends it to 64 bits, using a 34-bit offset.", "syntax": "plwz RT, D34(RA), R", "encoding": { "format": "MLS:D-form", "binary_pattern": "1 | 2 | R | 0 | D0 | 34 | RT | RA | D1", "hex_opcode": "0x0600000080000000", "visual_parts": [ { "raw": "000001", "clean": "000001" }, { "raw": "10", "clean": "10" }, { "raw": "0", "clean": "0" }, { "raw": "00000", "clean": "00000" }, { "raw": "...", "clean": "..." }, { "raw": "34", "clean": "34" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "D34", "clean": "D34" } ], "length": "64", "bit_positions": "0:5 | 6:7 | 8 | 9:13 | 14:31 | 32:37 | 38:42 | 43:47 | 48:63" }, "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "D34", "desc": "34-bit Displacement" }, { "name": "RA", "desc": "Base Register" } ], "pseudocode": "if R = 1 then\n EA ← (RA | 0 if RA=0) + sign_extend(D34, 34) + CIA\nelse\n EA ← (RA | 0 if RA=0) + sign_extend(D34, 34)\nRT ← zero_extend([EA]0:31, 64)", "example": "plwz r3, 0(r4), 0", "example_note": "Load word with large offset.", "extension": "Prefixed", "description": "Loads a 32-bit word from memory at the address calculated from RA plus a 34-bit immediate displacement, zero-extends it to 64 bits, and stores the result in RT. When R=1, the displacement is PC-relative; when R=0, it is treated as absolute. This is a 64-bit prefixed instruction from the Prefixed extension.", "page_found": "Page 89", "programming_notes": "Use plwz when loading a word from memory into a 64-bit register with zero extension. Ensure the EA (Effective Address) is correctly calculated using the prefix and suffix fields. This instruction operates at user privilege level." }, { "mnemonic": "plbz", "architecture": "PowerISA", "full_name": "Prefixed Load Byte and Zero", "summary": "Loads a byte and zero-extends it, using a 34-bit offset.", "syntax": "plbz RT, D34(RA), R", "encoding": { "format": "MLS:D-form", "binary_pattern": "1 | 2 | R | 0 | D0 | 35 | RT | RA | D1", "hex_opcode": "0x0600000088000000", "visual_parts": [ { "raw": "000001", "clean": "000001" }, { "raw": "10", "clean": "10" }, { "raw": "0", "clean": "0" }, { "raw": "00000", "clean": "00000" }, { "raw": "...", "clean": "..." }, { "raw": "35", "clean": "35" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "D34", "clean": "D34" } ], "length": "64", "bit_positions": "0:5 | 6:7 | 8 | 9:13 | 14:31 | 32:37 | 38:42 | 43:47 | 48:63" }, "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "D34", "desc": "34-bit Displacement" }, { "name": "RA", "desc": "Base Register" } ], "pseudocode": "EA ← (RA) + D34\nRT ← (0)56 || ([EA])", "example": "plbz r3, 0x12345678(0), 0", "example_note": "Load byte from absolute address.", "extension": "Prefixed", "description": "Loads a single byte from memory at the address formed by adding the 34-bit signed displacement D34 to the base register RA, zero-extends it to 64 bits, and stores the result in RT. This is a prefixed instruction using the MLS:D-form encoding with a 34-bit effective address offset. No condition flags are affected.", "page_found": "Page 84", "programming_notes": "The plbz instruction is used to load a single byte from memory and zero-extend it to fill the entire register. Ensure that the effective address (EA) is properly aligned for optimal performance, although misalignment does not cause an exception. This instruction operates at user privilege level." }, { "mnemonic": "pmxvbf16ger2", "architecture": "PowerISA", "full_name": "Prefixed Masked VSX Vector BFloat16 Ger (Rank-2 Update)", "summary": "Matrix Multiply Assist (MMA) instruction. Computes ACC <- ACC + (A * B) using BF16 inputs.", "syntax": "pmxvbf16ger2 AT, XA, XB, XMSK, YMSK", "encoding": { "format": "MMIRR-form", "binary_pattern": "1 | 3 | PMSK | XMSK | YMSK | 0 | 59 | AT | / | XA | XB | XO | AX | BX | /", "hex_opcode": "0x07900000EC000198", "visual_parts": [ { "raw": "000001", "clean": "000001" }, { "raw": "11", "clean": "11" }, { "raw": "...", "clean": "..." }, { "raw": "59", "clean": "59" }, { "raw": "...", "clean": "..." } ], "length": "64", "bit_positions": "0 | 6 | 8 | 9 | 14 | 32 | 38 | 41 | 43 | 48 | 53 | 56 | 57 | 58 | " }, "operands": [ { "name": "AT", "desc": "Accumulator (0-7)" }, { "name": "XA", "desc": "Vector A" }, { "name": "XB", "desc": "Vector B" }, { "name": "XMSK", "desc": "Mask for A" }, { "name": "YMSK", "desc": "Mask for B" } ], "pseudocode": "acc ← ACC[AT]\nfor i in 0..1 do\n for j in 0..3 do\n if XMSK[i] = 1 ∧ YMSK[j] = 1 then\n acc[i,j] ← acc[i,j] + (BF16(XA[i]) × BF16(XB[j]))\nACC[AT] ← acc\nCR6 ← saturation_status(acc)", "example": "pmxvbf16ger2 0, 1, 2, 0, 0", "example_note": "AI Tensor Core operation.", "extension": "Prefixed", "description": "Prefixed MMA instruction that performs a masked rank-2 generalized matrix multiply using BFloat16 inputs. Computes ACC(AT) ← ACC(AT) + (A × B) with element-wise masking via XMSK (for rows of A) and YMSK (for columns of B). Requires MMA support and VSX category. Updates CR6 to reflect accumulator saturation status.", "page_found": "Page 925", "programming_notes": "The pmxvbf16ger2 instruction is useful for performing matrix operations on bfloat16 data types with masking, allowing selective computation based on a mask. Ensure that the input vectors and accumulator are properly aligned to avoid performance penalties. This instruction operates at the user privilege level and will raise an exception if the result exceeds the 32-bit signed integer range, requiring saturation handling." }, { "mnemonic": "xxeval", "architecture": "PowerISA", "full_name": "VSX Vector Evaluation", "summary": "Performs an arbitrary 3-input boolean logic function (LUT3) on vectors. The 8-bit immediate 'IMM' defines the truth table.", "syntax": "xxeval XT, XA, XB, XC, IMM", "encoding": { "format": "8RR:XX4-form", "binary_pattern": "1 | 1 | 0 | / | 60 | XT | XA | XB | XC | IMM", "hex_opcode": "0x0500000088000010", "visual_parts": [ { "raw": "000001", "clean": "000001" }, { "raw": "01", "clean": "01" }, { "raw": "...", "clean": "..." }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "XC", "clean": "XC" }, { "raw": "IMM", "clean": "IMM" } ], "length": "64", "bit_positions": "0:5 | 6:7 | 8 | 9:31 | 32:37 | 38:42 | 43:47 | 48:52 | 53:55 | 56:63" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Source A" }, { "name": "XB", "desc": "Source B" }, { "name": "XC", "desc": "Source C" }, { "name": "IMM", "desc": "Truth Table (8-bits)" }, { "name": "RT", "desc": "Target Vector Register" }, { "name": "RA", "desc": "Source Vector Register A" }, { "name": "RB", "desc": "Source Vector Register B" }, { "name": "RC", "desc": "Source Vector Register C" } ], "pseudocode": "for i in 0..127 do\n selector ← (XC[i] || XB[i] || XA[i])\n XT[i] ← IMM[selector]\nend for", "example": "xxeval 0, 1, 2, 3, 0x96", "example_note": "Custom logic function (e.g., A^B^C).", "extension": "VSX", "description": "VSX instruction that performs a three-input lookup-table (LUT3) boolean operation on 128-bit vectors. The 8-bit immediate IMM encodes a truth table; for each bit position, the corresponding bit is determined by treating the three input bits (from XA, XB, XC) as a 3-bit selector into IMM. Requires VSX support; no condition flags are affected.", "page_found": "Page 945 - 946", "programming_notes": "The xxeval instruction is used to perform complex logical operations on vector registers.", "special_registers": "MSR" }, { "mnemonic": "divw", "architecture": "PowerISA", "full_name": "Divide Word", "summary": "Divides the contents of two registers and places the quotient into a target register.", "syntax": "divw RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "31 | RT | RA | RB | OE | 491 | Rc", "hex_opcode": "0x7C0003D6", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "OE", "clean": "OE" }, { "raw": "491", "clean": "491" }, { "raw": "Rc", "clean": "Rc" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21 | 22:30 | 31" }, "operands": [ { "name": "RT", "desc": "Target Register (Quotient)" }, { "name": "RA", "desc": "Dividend" }, { "name": "RB", "desc": "Divisor" } ], "pseudocode": "if 'divw' then\n RT32:63 <- (RA)32:63 ÷ (RB)32:63\n RT0:31 <- undefined", "example": "divw r3, r4, r5", "example_note": "r3 = r4 / r5 (32-bit Signed).", "extension": "Base", "description": "For divw, the 32-bit dividend is (RA)32:63. The 32-bit divisor is (RB)32:63. The 32-bit quotient is placed into RT32:63. The contents of RT0:31 are undefined.", "special_registers": "CR0, XER", "page_found": "Page 115 - 116", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER." }, { "mnemonic": "divwu", "architecture": "PowerISA", "full_name": "Divide Word Unsigned", "summary": "Divides the lower 32 bits of RA by the lower 32 bits of RB (Unsigned).", "syntax": "divwu RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "31 | RT | RA | RB | OE | 459 | Rc", "hex_opcode": "0x7C000396", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "OE", "clean": "OE" }, { "raw": "459", "clean": "459" }, { "raw": "Rc", "clean": "Rc" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21 | 22:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target Register (Quotient)" }, { "name": "RA", "desc": "Dividend" }, { "name": "RB", "desc": "Divisor" } ], "pseudocode": "dividend ← (RA)[32:63]\ndivisor ← (RB)[32:63]\nif divisor = 0 then\n quotient ← undefined\nelse\n quotient ← dividend ÷ divisor\nRT ← (0)32 || quotient\nif Rc = 1 then\n CR0 ← (quotient = 0) || (quotient < 0) || (quotient > 0) || SO", "example": "divwu r3, r4, r5", "example_note": "r3 = r4 / r5 (32-bit Unsigned).", "extension": "Base", "description": "Divides the lower 32 bits of RA (treated as unsigned) by the lower 32 bits of RB (treated as unsigned) and places the 32-bit quotient in RT with the upper 32 bits of RT set to zero. If RB is zero, RT is undefined and no exception is raised (wrap-on-overflow behavior). When Rc=1, CR0 is updated based on the result; OE is reserved and must be 0.", "page_found": "Page 118", "special_registers": "CR0", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER." }, { "mnemonic": "divd", "architecture": "PowerISA", "full_name": "Divide Doubleword", "summary": "Divides the contents of two registers and places the quotient into a target register.", "syntax": "divd RT,RA,RB", "encoding": { "format": "XO-form", "binary_pattern": "31 | RT | RA | RB | OE | 489 | Rc", "hex_opcode": "0x7C0003D2", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "OE", "clean": "OE" }, { "raw": "489", "clean": "489" }, { "raw": "Rc", "clean": "Rc" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21 | 22:30 | 31" }, "operands": [ { "name": "RT", "desc": "Target Register (Quotient)" }, { "name": "RA", "desc": "Dividend" }, { "name": "RB", "desc": "Divisor" } ], "pseudocode": "dividend0:63 ←(RA)\ndivisor0:63 ←(RB)\nRT ←dividend ÷ divisor", "example": "divd r3, r4, r5", "example_note": "r3 = r4 / r5 (64-bit Signed).", "extension": "Base", "description": "For divd, the 64-bit dividend is (RA) and the 64-bit divisor is (RB). The 64-bit quotient is placed into register RT. Both operands and the quotient are interpreted as signed integers.", "special_registers": "CR0, XER", "page_found": "Page 122 - 124", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER." }, { "mnemonic": "divdu", "architecture": "PowerISA", "full_name": "Divide Doubleword Unsigned", "summary": "Divides the 64-bit value in RA by the 64-bit value in RB (Unsigned).", "syntax": "divdu RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "31 | RT | RA | RB | OE | 457 | Rc", "hex_opcode": "0x7C000392", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "OE", "clean": "OE" }, { "raw": "457", "clean": "457" }, { "raw": "Rc", "clean": "Rc" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21 | 22:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target Register (Quotient)" }, { "name": "RA", "desc": "Dividend" }, { "name": "RB", "desc": "Divisor" } ], "pseudocode": "dividend ← (RA)\ndivisor ← (RB)\nif divisor = 0 then\n quotient ← undefined\nelse\n quotient ← dividend ÷ divisor\nRT ← quotient\nif Rc = 1 then\n CR0 ← (quotient = 0) || (quotient < 0) || (quotient > 0) || SO", "example": "divdu r3, r4, r5", "example_note": "r3 = r4 / r5 (64-bit Unsigned).", "extension": "Base", "description": "Divides the full 64-bit value in RA (treated as unsigned) by the full 64-bit value in RB (treated as unsigned) and places the 64-bit quotient in RT. If RB is zero, RT is undefined and no exception is raised. When Rc=1, CR0 is updated based on the result; OE is reserved and must be 0.", "page_found": "Page 123", "special_registers": "CR0", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER." }, { "mnemonic": "dcbz", "architecture": "PowerISA", "full_name": "Data Cache Block Set to Zero", "summary": "Zeros out an entire cache block (usually 128 bytes) in memory. Critical for optimizing memory clears (memset).", "syntax": "dcbz RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | / | RA | RB | 1014 | /", "hex_opcode": "0x7C0007EC", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "1014", "clean": "1014" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RA", "desc": "Base Address" }, { "name": "RB", "desc": "Index Address" } ], "pseudocode": "EA ← (RA) + (RB)\nblock_start ← EA & ~(cache_block_size - 1)\nfor addr in block_start to block_start + cache_block_size - 1 step word_size do\n [addr] ← 0\nend for", "example": "dcbz 0, r3", "example_note": "Zero the cache line at address in r3.", "extension": "Base", "description": "Data cache instruction that writes zeros to an entire cache block (typically 128 bytes) in memory at the effective address formed by RA + RB. The block is zero-filled and typically written back or marked clean in the cache. This is a memory hint instruction; no general-purpose registers are modified and no condition flags are affected.", "programming_notes": "dcbz does not cause the block to exist in the data cache if the block is in storage that is Caching Inhibited. For storage that is neither Write Through Required nor Caching Inhibited, dcbz provides an efficient means of setting blocks of storage to zero. It can be used to initialize large areas of such storage, in a manner that is likely to consume less memory bandwidth than an equivalent sequence of Store instructions. For storage that is either Write Through Required or Caching Inhibited, dcbz is likely to take significantly longer to execute than an equivalent sequence of Store instructions.", "page_found": "Page 1036 - 1037" }, { "mnemonic": "dcbt", "architecture": "PowerISA", "full_name": "Data Cache Block Touch", "summary": "Hints to the hardware to prefetch the cache block at the specified address into the cache.", "syntax": "dcbt RA,RB,TH", "encoding": { "format": "X-form", "binary_pattern": "0 | GO | S | DEP | UNITCNT | T | U | ID", "hex_opcode": "0x7C00022C", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "TH", "clean": "TH" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "278", "clean": "278" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "TH", "desc": "Touch Hint (Stream ID)" }, { "name": "RA", "desc": "Base Address" }, { "name": "RB", "desc": "Index Address" }, { "name": "EA", "desc": "Effective Address" } ], "pseudocode": "EA ← (RA) + (RB)\nPrefetch_cache_block(EA, touch_hint=TH)", "example": "dcbt 0, 0, r3", "example_note": "Prefetch data at r3.", "extension": "Base", "description": "Data cache prefetch hint that loads the cache block at effective address RA + RB into the data cache with streaming characteristics controlled by the TH field. Variants (dcbtt, dcbna, dcbtds) provide transient, non-allocating, and data stream hints. This is a memory hint with no side effects on registers or condition flags; the prefetch is advisory and may be ignored.", "programming_notes": "To maximize the utility of the Depth control mechanism, the architecture provides a hierarchy of three ways to program it. The DPFD field in the LPCR is used by the provisory/firmware to set a safe or appropriate default depth for unaware operating systems and applications. The DPFD field in the DSCR may be initialized by the aware OS and overwritten by an application via the OS-provided service when per stream control is unnecessary or unaffordable.", "page_found": "Page 1028 - 1029", "extended_mnemonics": [ { "mnemonic": "dcbt RA,RB", "equivalent": "dcbt RA,RB,0b00000" }, { "mnemonic": "dcbtt RA,RB", "equivalent": "dcbt RA,RB,0b10000" }, { "mnemonic": "dcbna RA,RB", "equivalent": "dcbt RA,RB,0b10001" }, { "mnemonic": "dcbtds RA,RB,TH", "equivalent": "dcbt RA,RB,TH (TH=0b00000 or 0b01000-0b01111)" } ] }, { "mnemonic": "dcbf", "architecture": "PowerISA", "full_name": "Data Cache Block Flush", "summary": "Flushes the cache block from the data cache to main memory and invalidates it. Used for DMA coherency.", "syntax": "dcbf RA,RB,L", "encoding": { "format": "X-form", "binary_pattern": "31 | / | RA | RB | 86 | /", "hex_opcode": "0x7C0000AC", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "86", "clean": "86" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RA", "desc": "Base Address" }, { "name": "RB", "desc": "Index Address" }, { "name": "L", "desc": "Level of cache flush (0, 1, 3, 4, 6)" }, { "name": "RT", "desc": "Target General Purpose Register" } ], "pseudocode": "EA ← (RA) + (RB)\nblock_start ← EA & ~(cache_block_size - 1)\nFlush_and_invalidate_cache_block(block_start, level=L)", "example": "dcbf 0, r3", "example_note": "Flush cache line at r3 to RAM.", "extension": "Base", "description": "Data cache flush instruction that writes back and invalidates the cache block at effective address RA + RB to ensure coherency with main memory. Variants (dcbfl, dcbflp, dcbfps, dcbstps) control the level and scope of the flush operation. The L field (if present) selects the cache level. No general-purpose registers are modified and no condition flags are affected.", "programming_notes": "dcbf serves as both a basic and an extended mnemonic. The Assembler will recognize a dcbf mnemonic with three operands as the basic form, and a dcbf mnemonic with two operands as the extended form. In the extended form the L operand is omitted and assumed to be 0.\ndcbf with L=1 can be used to provide a hint that a block in this processor’s data cache will not be reused soon.\ndcbf with L=3 can be used to flush a block from the processor’s primary data cache but reduce the latency of a subsequent access. For example, the block may be evicted from the primary data cache but a copy retained in a lower level of the cache hierarchy.", "extended_mnemonics": [ { "mnemonic": "dcbf RA,RB", "equivalent": "dcbf RA,RB,0" }, { "mnemonic": "dcbfl RA,RB", "equivalent": "dcbf RA,RB,1" }, { "mnemonic": "dcbflp RA,RB", "equivalent": "dcbf RA,RB,3" }, { "mnemonic": "dcbfps RA,RB", "equivalent": "dcbf RA,RB,4" }, { "mnemonic": "dcbstps RA,RB", "equivalent": "dcbf RA,RB,6" } ], "page_found": "Page 1038 - 1039" }, { "mnemonic": "dcbst", "architecture": "PowerISA", "full_name": "Data Cache Block Store", "summary": "Writes the cache block to main memory if it is modified (Clean), but keeps it in the cache.", "syntax": "dcbst RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | / | RA | RB | 54 | /", "hex_opcode": "0x7C00006C", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "54", "clean": "54" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RA", "desc": "Base Address" }, { "name": "RB", "desc": "Index Address" } ], "pseudocode": "EA ← (RA) + (RB)\nCacheBlock ← CacheBlock at EA\nif CacheBlock.Modified then\n WriteToMemory(CacheBlock)\n CacheBlock.Modified ← 0\nend if", "example": "dcbst 0, r3", "example_note": "Ensure RAM has latest data for r3.", "extension": "Base", "description": "Writes a cache block containing the byte addressed by RA+RB to main memory if the block is modified, then keeps the block in the cache in a clean state. This instruction is used to synchronize cache contents with memory without invalidating the cache line. No condition registers or status fields are affected.", "programming_notes": "Data Cache Block Store to Persistent Storage is encoded as a variant of Data Cache Block Flush. The extended mnemonic (dcbstps) indicates the intended function.", "extended_mnemonics": [ "dcbstps" ], "page_found": "Page 1037 - 1038" }, { "mnemonic": "xxsetaccz", "architecture": "PowerISA", "full_name": "VSX Set Accumulator to Zero", "summary": "Clears a 512-bit Accumulator register (composed of 4 VSRs) to zero.", "syntax": "xxsetaccz AT", "encoding": { "format": "X-form", "binary_pattern": "31 | / | / | AT | 185 | /", "hex_opcode": "0x7C030162", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "AT", "clean": "AT" }, { "raw": "185", "clean": "185" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "AT", "desc": "Accumulator (0-7)" } ], "extension": "MMA", "description": "Clears the 512-bit accumulator register AT (which consists of four 128-bit VSRs) to all zeros. This instruction is part of the MMA (Matrix Multiply Assist) extension and provides a fast way to initialize an accumulator before a sequence of matrix operations. No condition registers or status fields are affected.", "pseudocode": "ACC[AT] ← 0x0000...0000 (512 bits of zeros)", "page_found": "Page 913", "special_registers": "MSR", "programming_notes": "This instruction zeroes out all elements of the specified VSX accumulator. Ensure that VSX is enabled in the MSR register before using this instruction; otherwise, a VSX_Unavailable exception will be raised. This operation is useful for initializing accumulators or resetting them between operations.", "example": "xxsetaccz acc0" }, { "mnemonic": "xxmtacc", "architecture": "PowerISA", "full_name": "VSX Move to Accumulator", "summary": "Copies data from 4 adjacent VSRs into an Accumulator.", "syntax": "xxmtacc AT", "encoding": { "format": "X-form", "binary_pattern": "31 | / | / | AT | 153 | /", "hex_opcode": "0x7C010162", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "AT", "clean": "AT" }, { "raw": "153", "clean": "153" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "AT", "desc": "Target ACC" } ], "extension": "MMA", "description": "Copies data from four consecutive VSRs (VSR[4×AT], VSR[4×AT+1], VSR[4×AT+2], VSR[4×AT+3]) into the 512-bit accumulator AT. This instruction transfers vector data from the VSR file into MMA accumulator state. This instruction requires MMA support and does not affect any condition registers or status fields.", "pseudocode": "ACC[AT][0:127] ← VSR[4×AT]\nACC[AT][128:255] ← VSR[4×AT+1]\nACC[AT][256:383] ← VSR[4×AT+2]\nACC[AT][384:511] ← VSR[4×AT+3]", "page_found": "Page 912 - 913", "special_registers": "MSR", "programming_notes": "Ensure VSX is enabled in the MSR before using xxmtacc; otherwise, a VSX_Unavailable exception will occur. This instruction moves data from four consecutive vector scalar registers into the accumulator, so verify register allocation to avoid unintended data movement.", "example": "xxmtacc acc0" }, { "mnemonic": "xxmfacc", "architecture": "PowerISA", "full_name": "VSX Move from Accumulator", "summary": "Copies data from an Accumulator back to 4 adjacent VSRs.", "syntax": "xxmfacc AT", "encoding": { "format": "X-form", "binary_pattern": "31 | / | / | AT | 185 | /", "hex_opcode": "0x7C000162", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "AT", "clean": "AT" }, { "raw": "185", "clean": "185" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "AT", "desc": "Source ACC" }, { "name": "AS", "desc": "Accumulator Select" } ], "extension": "MMA", "description": "For xxmfacc, the contents of row i of ACC[AS] are placed into VSR[4×AS+i]. The contents of ACC[0] will be undefined after the first execution, which can degrade performance on subsequent executions.", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nfor each integer value i from 0 to 3 do\n VSR[4×AS+i] ← ACC[AS][i]", "programming_notes": "During extended periods of execution when there isn't any active use of the accumulators and VSX Vector GER instructions, hardware may deactivate these facilities for power savings. Once deactivated, while any attempted execution of any xxmfacc, xxmtacc, xxsetaccz, or VSX Vector GER instruction will cause these facilities to become reactivated, this reactivation causes significant delay beyond the normal execution of these instructions. This delay can be avoided by periodically issuing an xxmfacc with AS=0 instruction during extended times that the facilities are not being used to keep the facilities activated. Since the contents of ACC[0] will be undefined after the first execution, performance on subsequent executions of xxmfacc 0 can be expected to be degraded compared to performance when the contents of ACC[0] are defined. As such, to keep the facilities activated, xxmfacc 0 should be used with attention to performance implications.", "page_found": "Page 911 - 912", "special_registers": "MSR", "example": "xxmfacc acc0" }, { "mnemonic": "xvi8ger4", "architecture": "PowerISA", "full_name": "VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update)", "summary": "Performs an 8-bit integer outer product (GER) and accumulates into a 512-bit register.", "syntax": "xvi8ger4 AT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "0 | AT | XA | XB | 3 | AXBX", "hex_opcode": "0xEC000018", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "AT", "clean": "AT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "34", "clean": "34" } ], "length": "32", "bit_positions": "0:5 | 6:9 | 10:13 | 14:17 | 18:20 | 21:31" }, "operands": [ { "name": "AT", "desc": "Accumulator" }, { "name": "XA", "desc": "Vector A (8-bit)" }, { "name": "XB", "desc": "Vector B (8-bit)" } ], "extension": "MMA", "description": "Performs a rank-4 outer product of two 8-bit signed/unsigned integer vectors, accumulating the result into the 512-bit accumulator AT. The operation treats elements of XA and XB as 8-bit integers, computes pairwise products, and accumulates them into 32-bit or 64-bit result lanes within the accumulator. This MMA instruction does not affect condition registers or status fields.", "pseudocode": "for i = 0 to 15 do\n for j = 0 to 15 do\n ACC[AT][4×(i×16+j)] ← ACC[AT][4×(i×16+j)] + (int8)XA[8×i:8×i+7] × (int8)XB[8×j:8×j+7]\n end for\nend for", "page_found": "Page 920 - 921", "special_registers": "MSR", "programming_notes": "The xvi8ger4 instruction requires the VSX facility to be enabled in the MSR register. It performs a rank-4 update on VSX vector elements, multiplying and accumulating 8-bit signed/unsigned integers based on specified masks. Ensure that the VSX feature is available and properly configured before using this instruction.", "example": "xvi8ger4 acc0, vs2, vs3" }, { "mnemonic": "xvi8ger4pp", "architecture": "PowerISA", "full_name": "VSX Vector Integer 8-bit GER (Rank-4 Update) Plus/Plus", "summary": "Signed/Unsigned variations of 8-bit matrix multiply accumulate.", "syntax": "xvi8ger4pp AT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "60 | AT | XA | XB | 35", "hex_opcode": "0xEC000010", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "AT", "clean": "AT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "35", "clean": "35" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "AT", "desc": "Accumulator" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "MMA", "description": "Performs a rank-4 outer product accumulation of two 8-bit integer vectors, with sign/unsignedness controlled by inline suffix bits. The accumulate step uses saturating or wrapping semantics depending on configuration. This MMA instruction does not affect condition registers or status fields.", "pseudocode": "for i = 0 to 15 do\n for j = 0 to 15 do\n prod ← (int8)XA[8×i:8×i+7] × (int8)XB[8×j:8×j+7]\n ACC[AT][4×(i×16+j)] ← ACC[AT][4×(i×16+j)] + prod\n end for\nend for", "page_found": "Page 921", "special_registers": "ACC", "programming_notes": "This instruction is commonly used in matrix operations where rank-4 updates are required. Ensure that the input vectors VSR[XA] and VSR[XB] are properly aligned to avoid performance penalties. The result is automatically chopped to fit into a 32-bit signed integer, so be cautious of overflow if intermediate results exceed this range.", "example": "xvi8ger4pp acc0, vs2, vs3" }, { "mnemonic": "xvi16ger2", "architecture": "PowerISA", "full_name": "VSX Vector Integer 16-bit GER (Rank-2 Update)", "summary": "Performs a rank-2 update of the contents of two registers and updates the condition register.", "syntax": "xvi16ger2 AT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "0 | AT | XA | XB | 75 | AXBX", "hex_opcode": "0xEC000258", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "AT", "clean": "AT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "75", "clean": "75" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:28 | 29:31" }, "operands": [ { "name": "AT", "desc": "Accumulator" }, { "name": "XA", "desc": "Src A (16-bit)" }, { "name": "XB", "desc": "Src B (16-bit)" } ], "extension": "MMA", "description": "For xvi16ger2, the sum of the contents of register RA and RB is placed into register RT.", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\n\nPMSK ←0b11\nXMSK ←0b1111\nYMSK ←0b1111\n\ndo i = 0 to 3\n do j = 0 to 3\n if XMSK.bit[i] & YMSK.bit[j] then do\n prod0 ←(PMSK.bit[0]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].hword[0]) *\n EXTS(VSR[32×BX+B].word[j].hword[0])\n prod1 ←(PMSK.bit[1]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].hword[1]) *\n EXTS(VSR[32×BX+B].word[j].hword[1])\n\n psum ←prod0 + prod1\n\n ACC[AT][i].word[j] ←CHOP32(psum)\n end\n else\n ACC[AT][i][j] ←0x0000_0000\n end\nend", "page_found": "Page 913 - 914", "special_registers": "MSR", "programming_notes": "The xvi16ger2 instruction performs a 16-bit integer GER (Rank-2 Update) operation on VSX registers. Ensure that the VSX facility is enabled by checking and setting the MSR.VSX bit. The instruction processes 4x4 matrices of halfwords, multiplying corresponding elements and accumulating the results. Be cautious with overflow conditions as the products are summed without intermediate overflow checks. This instruction operates at the user privilege level and will raise an exception if VSX is unavailable.", "example": "xvi16ger2 acc0, vs2, vs3" }, { "mnemonic": "xvi16ger2s", "architecture": "PowerISA", "full_name": "VSX Vector Integer 16-bit GER (Rank-2 Update) Saturate", "summary": "Performs a vectorized signed integer multiply and accumulate operation with saturation.", "syntax": "xvi16ger2s AT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "0 | AT | XA | XB | AXBX", "hex_opcode": "0xEC000158", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "AT", "clean": "AT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "43", "clean": "43" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "AT", "desc": "Accumulator" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "MMA", "description": "The instruction performs a vectorized signed integer multiply and accumulate operation with saturation. It multiplies the elements of two vectors and accumulates the results into a destination vector, saturating any overflow values.", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\n\nPMSK ←0b11\nXMSK ←0b1111\nYMSK ←0b1111\nsat_flag ←0\n\ndo i = 0 to 3\ndo j = 0 to 3\n if XMSK.bit[i] & YMSK.bit[j] then do\n prod0 ←(PMSK.bit[0]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].hword[0]) * EXTS(VSR[32×BX+B].word[j].hword[0])\n prod1 ←(PMSK.bit[1]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].hword[1]) * EXTS(VSR[32×BX+B].word[j].hword[1])\n\n psum ←prod0 + prod1\n\n ACC[AT][i].word[j] ←si32_CLAMP( psum )\n\n if sat_flag=1 then VSCR.SAT ←1\n end\n else\n ACC[AT][i][j] ←0x0000_0000\nend\nend", "special_registers": "VSCR, VSX registers", "page_found": "Page 915 - 916", "programming_notes": "This instruction is commonly used for vectorized operations involving 16-bit integer multiplication and accumulation with saturation. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. Be cautious of overflow conditions, as they will be saturated, which might affect the precision of your results. The instruction operates on 128-bit vectors, so ensure proper alignment for optimal performance.", "example": "xvi16ger2s acc0, vs2, vs3" }, { "mnemonic": "xvf16ger2", "architecture": "PowerISA", "full_name": "VSX Vector Float16 GER (Rank-2 Update)", "summary": "Performs a vector floating-point general element-wise rank-2 update operation.", "syntax": "xvf16ger2 AT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "59 | AT | // | A | B | 19 | AX | BX | /", "hex_opcode": "0xEC000098", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "AT", "clean": "AT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "19", "clean": "19" } ], "length": "32", "bit_positions": "0:5 | 6:8 | 9:10 | 11:15 | 16:20 | 21:28 | 29 | 30 | 31" }, "operands": [ { "name": "AT", "desc": "Accumulator" }, { "name": "XA", "desc": "Src A (FP16)" }, { "name": "XB", "desc": "Src B (FP16)" } ], "extension": "MMA", "page_found": "Page 929 - 930", "description": "Performs a rank-2 outer product of two FP16 (half-precision floating-point) vectors, accumulating the result into the 512-bit accumulator AT. Each element of XA is multiplied by each element of XB, and products are summed across appropriate lanes. This MMA instruction requires floating-point support and does not modify condition registers or status fields.", "pseudocode": "for i = 0 to 31 do\n for j = 0 to 31 do\n ACC[AT][result_lane] ← ACC[AT][result_lane] + (fp16)XA[16×i:16×i+15] × (fp16)XB[16×j:16×j+15]\n end for\nend for", "programming_notes": "The xvf16ger2 instruction is useful for performing matrix operations in VSX registers, specifically for rank-2 update accumulations. Ensure that the input matrices are correctly aligned and that the destination accumulator register is properly initialized to avoid incorrect results. This instruction operates at a high privilege level and may raise exceptions if the operands are not valid bfloat16 values.", "example": "xvf16ger2 acc0, vs2, vs3" }, { "mnemonic": "xvbf16ger2", "architecture": "PowerISA", "full_name": "VSX Vector BFloat16 GER (Rank-2 Update)", "summary": "Performs BFloat16 (Brain Float) matrix multiply accumulate.", "syntax": "xvbf16ger2 AT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "60 | AT | XA | XB | 51", "hex_opcode": "0xEC000198", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "AT", "clean": "AT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "51", "clean": "51" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "AT", "desc": "Accumulator" }, { "name": "XA", "desc": "Src A (BF16)" }, { "name": "XB", "desc": "Src B (BF16)" } ], "extension": "MMA", "page_found": "Page 924 - 925", "description": "Performs a rank-2 outer product of two BFloat16 (Brain Float) vectors, accumulating results into the 512-bit accumulator AT. BFloat16 is a truncated 32-bit floating-point format used in machine-learning workloads. This MMA instruction does not affect condition registers or status fields.", "special_registers": "ACC", "programming_notes": "The xvbf16ger2 instruction is used for performing a rank-2 update on the accumulator using bfloat16 values from two VSX registers. Ensure that the input registers are properly aligned and that the operation does not exceed the bounds of the accumulator to avoid saturation issues. This instruction operates at privilege level 0.", "pseudocode": "for i = 0 to 31 do\n for j = 0 to 31 do\n ACC[AT][result_lane] ← ACC[AT][result_lane] + (bf16)XA[16×i:16×i+15] × (bf16)XB[16×j:16×j+15]\n end for\nend for", "example": "xvbf16ger2 acc0, vs2, vs3" }, { "mnemonic": "xvf32ger", "architecture": "PowerISA", "full_name": "VSX Vector Float32 GER (Rank-1 Update)", "summary": "Performs a vector floating-point general element-wise reduction with rank-1 update.", "syntax": "xvf32ger AT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "0 | 6 | 9 | 11 | 16 | 21 | 27 | AXBX", "hex_opcode": "0xEC0000D8", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "AT", "clean": "AT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "27", "clean": "27" } ], "length": "32", "bit_positions": "0:5 | 6:8 | 9:10 | 11:15 | 16:20 | 21:26 | 27:30 | 31" }, "operands": [ { "name": "AT", "desc": "Accumulator" }, { "name": "XA", "desc": "Src A (FP32)" }, { "name": "XB", "desc": "Src B (FP32)" } ], "extension": "MMA", "page_found": "Page 934 - 935", "description": "Performs a rank-1 outer product of two FP32 (single-precision floating-point) vectors, accumulating the result into the 512-bit accumulator AT. This reduction-style MMA operation multiplies corresponding FP32 elements and accumulates the products with appropriate rounding and exception behavior. No condition registers or status fields are modified.", "pseudocode": "for i = 0 to 15 do\n for j = 0 to 15 do\n prod ← (fp32)XA[32×i:32×i+31] × (fp32)XB[32×j:32×j+31]\n ACC[AT][result_lane] ← ACC[AT][result_lane] + prod\n end for\nend for", "special_registers": "ACC", "programming_notes": "The xvf32ger instruction is commonly used for matrix operations, specifically rank-1 updates. Ensure that the input matrices in VSR[XA] and VSR[XB] are correctly aligned and formatted as 4x2 matrices to avoid incorrect results. This operation requires floating-point precision and may raise exceptions if inputs are out of range or if there are NaNs or infinities involved.", "example": "xvf32ger acc0, vs2, vs3" }, { "mnemonic": "xvf64ger", "architecture": "PowerISA", "full_name": "VSX Vector Float64 GER (Rank-1 Update)", "summary": "Performs a vector floating-point general element-wise reduction on 64-bit elements.", "syntax": "xvf64ger AT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "59 | AT | // | Ap | B | 59 | AX | BX | /", "hex_opcode": "0xEC0001D8", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "AT", "clean": "AT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "59", "clean": "59" } ], "length": "32", "bit_positions": "0:5 | 6:8 | 9:10 | 11:15 | 16:20 | 21:28 | 29 | 30 | 31" }, "operands": [ { "name": "AT", "desc": "Accumulator" }, { "name": "XA", "desc": "Src A (FP64)" }, { "name": "XB", "desc": "Src B (FP64)" }, { "name": "XAp", "desc": "Source Vector Register" } ], "extension": "MMA", "page_found": "Page 938 - 939", "description": "Performs a rank-1 update of a 4×4 matrix accumulator using 64-bit floating-point elements from two VSX source registers. This MMA instruction computes the outer product of two vectors (each with 2 double-precision elements, implicitly extended) and accumulates the result into the 512-bit accumulator AT. No condition register or status flags are affected.", "pseudocode": "AT ← AT + (XA[0] * XB[0] || XA[0] * XB[1] || XA[1] * XB[0] || XA[1] * XB[1]) (as 4×4 FP64 matrix)", "programming_notes": "The xvf64ger instruction is commonly used for performing matrix operations in scientific computing and linear algebra. Ensure that the input vectors X and Y are properly aligned to avoid performance penalties. This instruction operates at user privilege level, but improper use can lead to undefined behavior if the accumulator register is not correctly initialized.", "example": "xvf64ger acc0, vs2, vs3" }, { "mnemonic": "pmxvi8ger4", "architecture": "PowerISA", "full_name": "Prefixed Masked VSX Vector Integer 8-bit GER", "summary": "Masked version of 8-bit integer MMA.", "syntax": "pmxvi8ger4 AT, XA, XB, XMSK, YMSK", "encoding": { "format": "MMIRR-form", "binary_pattern": "1 | 3 | PMSK | XMSK | YMSK | 0 | 59 | AT | / | XA | XB | 35 | AX | BX | /", "hex_opcode": "0x07900000EC000018", "visual_parts": [ { "raw": "000001", "clean": "000001" }, { "raw": "11", "clean": "11" }, { "raw": "...", "clean": "..." } ], "length": "64", "bit_positions": "0 | 6 | 8 | 9 | 14 | 32 | 38 | 41 | 43 | 48 | 53 | 56 | 57 | 58 | " }, "operands": [ { "name": "AT", "desc": "Accumulator" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" }, { "name": "XMSK", "desc": "Mask A" }, { "name": "YMSK", "desc": "Mask B" } ], "extension": "Prefixed", "description": "Prefixed masked version of the 8-bit integer matrix multiply-accumulate (MMA) instruction. Performs a rank-1 update of a 4×4 matrix accumulator using masked 8-bit integer elements, where XMSK controls which columns of XA participate and YMSK controls which rows of XB participate. No condition register or status flags are affected; this is a privileged MMA extension instruction.", "pseudocode": "for i in 0..3:\n for j in 0..3:\n if (XMSK[i] == 1) & (YMSK[j] == 1):\n AT[i][j] ← AT[i][j] + (XA[i] × XB[j]) (8-bit signed × 8-bit signed → 32-bit result)", "page_found": "Page 921", "programming_notes": "This instruction is useful for performing efficient matrix multiplication on 8-bit signed integers with masking. Ensure that the mask registers (XMSK, YMSK, PMSK) are correctly set to control which elements participate in the accumulation. The operation requires VSX registers, so ensure they are properly aligned and accessible at the privilege level required by your application. Be cautious of potential overflow when accumulating products, as the result is chopped to 32 bits.", "example": "pmxvi8ger4 acc0, vs2, vs3, 15, 15" }, { "mnemonic": "pmxvf64ger", "architecture": "PowerISA", "full_name": "Prefixed Masked VSX Vector Float64 GER", "summary": "Masked version of Double-Precision MMA.", "syntax": "pmxvf64ger AT, XA, XB, XMSK, YMSK", "encoding": { "format": "MMIRR-form", "binary_pattern": "1 | 3 | PMSK | XMSK | YMSK | 0 | 59 | AT | / | XA | XB | 19 | AX | BX | /", "hex_opcode": "0x07900000EC0001D8", "visual_parts": [ { "raw": "000001", "clean": "000001" }, { "raw": "11", "clean": "11" }, { "raw": "...", "clean": "..." } ], "length": "64", "bit_positions": "0 | 6 | 8 | 9 | 14 | 32 | 38 | 41 | 43 | 48 | 53 | 56 | 57 | 58 | " }, "operands": [ { "name": "AT", "desc": "Accumulator" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" }, { "name": "XMSK", "desc": "Mask A" }, { "name": "YMSK", "desc": "Mask B" } ], "extension": "Prefixed", "description": "Prefixed masked version of the 64-bit floating-point matrix multiply-accumulate (MMA) instruction. Performs a rank-1 update of a 4×4 matrix accumulator using masked 64-bit floating-point elements, where XMSK controls which columns of XA participate and YMSK controls which rows of XB participate. No condition register or status flags are affected; this is a privileged MMA extension instruction.", "pseudocode": "for i in 0..1:\n for j in 0..1:\n if (XMSK[i] == 1) & (YMSK[j] == 1):\n AT[i][j] ← AT[i][j] + (XA[i] × XB[j]) (FP64 × FP64 → FP64)", "page_found": "Page 939", "programming_notes": "The pmxvf64ger instruction is useful for performing masked outer product accumulation on floating-point vectors. Ensure that the mask registers XMSK and YMSK are correctly set to control which elements of the input vectors XAp and XB participate in the computation. This instruction operates at a privilege level that allows access to VSX (Vector Scalar Extensions) and requires proper alignment of the input and accumulator vectors for optimal performance.", "example": "pmxvf64ger acc0, vs2, vs3, 15, 15" }, { "mnemonic": "cnttzw", "architecture": "PowerISA", "full_name": "Count Trailing Zeros Word", "summary": "Counts the number of trailing zeros in the low 32-bits.", "syntax": "cnttzw RA, RS", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | / | 538 | /", "hex_opcode": "0x7C000434", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "/", "clean": "/" }, { "raw": "538", "clean": "538" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "RS", "desc": "Source" } ], "extension": "Base", "description": "Counts the number of trailing zero bits in the low 32 bits of general-purpose register RS and stores the count in RA. The count ranges from 0 to 32; if all 32 bits are zero, the result is 32. No condition register or status flags are affected.", "pseudocode": "count ← 0\nfor i in 0..31:\n if RS[32+i] == 0 then count ← count + 1\n else break\nRA ← count", "page_found": "Page 137", "special_registers": "CR0", "programming_notes": "The cnttzw instruction is useful for quickly determining the number of trailing zeros in a word, which can be helpful in bit manipulation tasks. Be cautious with Rc=1 as it modifies CR0 based on the result, affecting subsequent conditional operations. Ensure that the input register (RS) is correctly aligned and contains valid data to avoid unexpected results.", "example": "cnttzw r4, r3" }, { "mnemonic": "cnttzd", "architecture": "PowerISA", "full_name": "Count Trailing Zeros Doubleword", "summary": "Counts the number of trailing zeros in 64-bits.", "syntax": "cnttzd RA, RS", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | / | 570 | /", "hex_opcode": "0x7C000474", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "/", "clean": "/" }, { "raw": "570", "clean": "570" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "RS", "desc": "Source" } ], "extension": "Base", "description": "Counts the number of trailing zero bits in the full 64-bit general-purpose register RS and stores the count in RA. The count ranges from 0 to 64; if all 64 bits are zero, the result is 64. No condition register or status flags are affected.", "pseudocode": "count ← 0\nfor i in 0..63:\n if RS[i] == 0 then count ← count + 1\n else break\nRA ← count", "page_found": "Page 140", "programming_notes": "The cnttzd instruction is useful for quickly determining the position of the least significant set bit in a 64-bit value. It operates efficiently on any aligned doubleword, but be cautious with unaligned data as it may lead to unexpected results or exceptions. This instruction can be executed at user privilege level without requiring special permissions.", "example": "cnttzd r4, r3" }, { "mnemonic": "bctar", "architecture": "PowerISA", "full_name": "Branch Conditional to Target Address Register", "summary": "Conditional branch based on the contents of the Condition Register and the Count Register.", "syntax": "bctar BO,BI,BH (LK=0)", "encoding": { "format": "XL-form", "binary_pattern": "19 | BO | BI | / | BH | 560 | /", "hex_opcode": "0x4C000460", "visual_parts": [ { "raw": "19", "clean": "19" }, { "raw": "BO", "clean": "BO" }, { "raw": "BI", "clean": "BI" }, { "raw": "/", "clean": "/" }, { "raw": "BH", "clean": "BH" }, { "raw": "560", "clean": "560" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:18 | 19:20 | 21:30 | 31" }, "operands": [ { "name": "BO", "desc": "Options" }, { "name": "BI", "desc": "CR Bit" }, { "name": "BH", "desc": "Hint" } ], "extension": "Base", "description": "Performs a conditional branch to the target address held in the Target Address Register (TAR). The branch condition is determined by the values of the Branch Options (BO) field and the Condition Register bit (BI). The Count Register may also influence the branch condition depending on BO. No status flags are updated; the instruction may update the Link Register if suffixed with LK=1.", "pseudocode": "if condition(BO, BI, CTR) then\n NIA ← TAR\nelse\n NIA ← CIA + 4", "special_registers": "CTR, LR", "programming_notes": "In some systems, the system software will restrict usage of the bctar[l] instruction to only selected programs. If an attempt is made to execute the instruction when it is not available, the system error handler will be invoked.", "page_found": "Page 77 - 78", "example": "bctar 20, 0, BH (LK=0)" }, { "mnemonic": "mttar", "architecture": "PowerISA", "full_name": "Move To Target Address Register", "summary": "Moves a GPR value to the TAR.", "syntax": "mttar RS", "encoding": { "format": "XFX-form", "binary_pattern": "31 | RS | 129 | 467 | /", "hex_opcode": "0x7C0FCBA6", "visual_parts": [ { "raw": "mtspr 129, RS", "clean": "mtspr 129, RS" } ], "bit_positions": "0:5 | 6:10 | 11:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RS", "desc": "Source" } ], "extension": "Base", "description": "Move To Target Address Register. Extended mnemonic for MTSPR (mtspr 815,RS). Copies register RS into the Target Address Register (TAR).", "pseudocode": "TAR ← RS", "special_registers": "TAR", "programming_notes": "The mttar instruction is used to copy a value from a general-purpose register (RS) into the Target Address Register (TAR). This register is typically used in conjunction with address translation operations. Ensure that the source register contains the correct address value before executing this instruction, as incorrect values can lead to unpredictable behavior or exceptions. This operation requires supervisor privilege level.", "example": "mttar r3" }, { "mnemonic": "mftar", "architecture": "PowerISA", "full_name": "Move From Target Address Register", "summary": "Reads the TAR into a GPR.", "syntax": "mftar RT", "encoding": { "format": "XFX-form", "binary_pattern": "31 | RT | 129 | 339 | /", "hex_opcode": "0x7C0FCAA6", "visual_parts": [ { "raw": "mfspr RT, 129", "clean": "mfspr RT, 129" } ], "bit_positions": "0:5 | 6:10 | 11:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" } ], "extension": "Base", "description": "Move From Target Address Register. Extended mnemonic for MFSPR (mfspr RT,815). Copies the Target Address Register (TAR) into register RT.", "pseudocode": "RT ← TAR", "special_registers": "TAR", "programming_notes": "The mftar instruction is used to copy the value of the Target Address Register (TAR) into a general-purpose register. This is typically done in contexts where precise control over branch targets or speculative execution is required. Ensure that the destination register RT is properly aligned and accessible at the privilege level executing the instruction, as accessing certain registers may require supervisor or hypervisor privileges.", "example": "mftar r3" }, { "mnemonic": "cmprb", "architecture": "PowerISA", "full_name": "Compare Ranged Byte", "summary": "Compares a byte value in one register to see if it falls within a range defined by another register.", "syntax": "cmprb BF, L, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | BF | / | L | RA | RB | 192 | Rc", "hex_opcode": "0x7C000180", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "BF", "clean": "BF" }, { "raw": "L", "clean": "L" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "192", "clean": "192" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:8 | 9 | 10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "BF", "desc": "CR Field" }, { "name": "L", "desc": "Mode" }, { "name": "RA", "desc": "Byte" }, { "name": "RB", "desc": "Range" }, { "name": "RT", "desc": "Target General Purpose Register" } ], "extension": "Base", "description": "Compares a byte value from RA against a range defined by two bytes in RB, setting the Condition Register field BF with the comparison result. The L field controls whether the comparison is unsigned (L=0) or signed (L=1). The instruction writes only the specified CR field; CR0 is not affected unless BF designates CR0.", "pseudocode": "byte_val ← RA[56:63]\nrange_low ← RB[56:63]\nrange_high ← RB[48:55]\nif L == 0 then\n // unsigned comparison\n result ← (byte_val >= range_low) & (byte_val <= range_high)\nelse\n // signed comparison\n result ← (byte_val[signed] >= range_low[signed]) & (byte_val[signed] <= range_high[signed])\nCR[BF] ← (result, 0, 0, 0)", "special_registers": "CR, CR0", "programming_notes": "cmprb is useful for implementing character typing functions such as isalpha(), isdigit(), isupper(), and islower() that are implemented using one or two range compares of the character. A single-range compare can be implemented with an addi to load the upper and lower bounds in the range, such as isdigit(). A combination of addi-addis can be used to set up 2 ranges, such as for isalpha().", "page_found": "Page 127 - 128", "example": "cmprb cr0, 0, r4, r5" }, { "mnemonic": "paste.", "architecture": "PowerISA", "full_name": "Paste and Record", "summary": "Paste operation that updates CR0 to indicate success/fail.", "syntax": "paste. RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | / | RA | RB | 770 | 1", "hex_opcode": "0x7C00070C", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "770", "clean": "770" }, { "raw": "1", "clean": "1" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Dest" }, { "name": "RB", "desc": "Control" } ], "extension": "Privileged", "description": "A privileged operation that pastes data into a target addressed by RA, with control information from RB. The record form (Rc=1) updates CR0 to reflect the success or failure of the paste operation. This instruction is used in conjunction with copy-paste semantics for atomic data movement and synchronization in a multithreaded environment.", "pseudocode": "status ← paste_operation(RA, RB)\nif Rc == 1 then\n CR0[LT] ← 0\n CR0[GT] ← 0\n CR0[EQ] ← (status == success)\n CR0[SO] ← 0", "page_found": "Page 1044", "special_registers": "CR0", "programming_notes": "The paste instruction is used to transfer data from the copy buffer to memory. Ensure that RA and RB are correctly set to calculate the effective address (EA). If L=1, metadata in the copy buffer will be cleared before posting. Handle errors by checking CR0 for error codes.", "example": "paste. r4, r5" }, { "mnemonic": "stqcx.", "architecture": "PowerISA", "full_name": "Store Quadword Conditional Indexed", "summary": "Stores a quadword from a register to memory if a reservation exists and the conditions are met.", "syntax": "stqcx. RS, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 182 | 1", "hex_opcode": "0x7C00016D", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "182", "clean": "182" }, { "raw": "1", "clean": "1" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RS", "desc": "Src Pair (Even/Odd)" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" }, { "name": "RSp", "desc": "Source General Purpose Register containing the data to be stored" } ], "extension": "Base", "description": "The stqcx. instruction stores a quadword from RSp to memory at the effective address (EA) calculated as RA + RB, but only if a reservation exists for that location and the reservation length is 16 bytes. If the reservation does not exist or the conditions are not met, no store is performed.", "pseudocode": "if RA = 0 then\n b ← 0\nelse\n b ← (RA)\nEA ← b + (RB)\nif RESERVE then\n if RESERVE_LENGTH = 16 and RESERVE_ADDR = real_addr(EA) then\n MEM(EA, 16) ← (RSp)\n undefined_case ← 0\n store_performed ← 1\n else\n z ← smallest real page size supported by implementation\n if RESERVE_ADDR ÷ z = real_addr(EA) ÷ z then\n undefined_case ← 1\n else\n undefined_case ← 0\n store_performed ← 0\nelse\n undefined_case ← 0\n store_performed ← 0\nif undefined_case then\n u1 ← undefined 1-bit value\n if u1 then\n MEM(EA, 16) ← (RSp)\n u2 ← undefined 1-bit value\n CR0 ← 0b00 || u2 || XERSO\nelse\n CR0 ← 0b00 || store_performed || XERSO\nRESERVE ← 0", "special_registers": "CR0, XER", "page_found": "Page 1059 - 1060", "programming_notes": "Succeeds only if a valid reservation exists on the target address. Sets CR0[EQ] to 1 on success, 0 on failure. Must always be used in a retry loop that re-executes the load-reserve instruction on failure.", "example": "stqcx. r3, r4, r5" }, { "mnemonic": "lq", "architecture": "PowerISA", "full_name": "Load Quadword", "summary": "Loads 128 bits into two adjacent GPRs (Even/Odd pair).", "syntax": "lq RTp, DQ(RA)", "encoding": { "format": "DQ-form", "binary_pattern": "56 | RTp | RA | DQ | /", "hex_opcode": "0xE0000000", "visual_parts": [ { "raw": "56", "clean": "56" }, { "raw": "RTp", "clean": "RTp" }, { "raw": "RA", "clean": "RA" }, { "raw": "DQ", "clean": "DQ" }, { "raw": "0", "clean": "0" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:27 | 28:31" }, "operands": [ { "name": "RTp", "desc": "Target Pair" }, { "name": "DQ", "desc": "Disp" }, { "name": "RA", "desc": "Base" }, { "name": "disp", "desc": "Displacement value" }, { "name": "EA", "desc": "Effective Address" } ], "extension": "Base", "description": "For lq, the quadword in storage addressed by EA is loaded into an even-odd pair of GPRs. In Big-Endian mode, the even-numbered GPR is loaded with the doubleword from storage addressed by EA and the odd-numbered GPR is loaded with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed by EA.", "pseudocode": "if 'lq' then\n EA ← (RA|0) + EXTS64(DQ||0b0000)\n if Big-Endian byte ordering then\n RTp||RTp+1 ← MEM(EA,16)\n if Little-Endian byte ordering then\n RTp||RTp+1 ← MEM(EA,16)", "programming_notes": "The lq and stq instructions exist primarily to permit software to access quadwords in storage “atomically”.", "page_found": "Page 98 - 100", "example": "lq r4, 0(r4)" }, { "mnemonic": "stq", "architecture": "PowerISA", "full_name": "Store Quadword", "summary": "Stores a quadword from two general-purpose registers into memory.", "syntax": "stq RSp, DQ(RA)", "encoding": { "format": "DQ-form", "binary_pattern": "1 | RSp | RA | DS | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0", "hex_opcode": "0xF8000002", "visual_parts": [ { "raw": "62", "clean": "62" }, { "raw": "RSp", "clean": "RSp" }, { "raw": "RA", "clean": "RA" }, { "raw": "DQ", "clean": "DQ" }, { "raw": "2", "clean": "2" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "RSp", "desc": "Src Pair" }, { "name": "DQ", "desc": "Disp" }, { "name": "RA", "desc": "Base" }, { "name": "disp", "desc": "Displacement value" } ], "extension": "Base", "description": "Stores a 128-bit quadword from two consecutive general-purpose registers (RSp and RSp+1) into memory at the address formed by adding the base register (RA) and a 16-byte-aligned displacement. The displacement is a signed 12-bit value left-shifted by 4 bits, providing a range of ±2048 bytes on a 16-byte boundary. This instruction does not modify the condition register or status flags.", "pseudocode": "EA ← if RA = 0 then 0 else GPR[RA]\nEA ← EA + EXTS(DQ || 0b0000)\nMEM(EA, 16) ← GPR[RSp] || GPR[RSp+1]", "programming_notes": "In versions of the architecture prior to V. 2.07, this instruction was privileged.", "page_found": "Page 99 - 100", "example": "stq r4, 0(r4)" }, { "mnemonic": "plh", "architecture": "PowerISA", "full_name": "Prefixed Load Halfword", "summary": "Loads 16-bit halfword using 34-bit offset.", "syntax": "plh RT, D(RA), R", "encoding": { "format": "MLS:D-form", "binary_pattern": "1 | 2 | R | 0 | D0 | 40 | RT | RA | D1", "hex_opcode": "0x04000000A0000000", "visual_parts": [ { "raw": "000001", "clean": "000001" }, { "raw": "10", "clean": "10" }, { "raw": "...", "clean": "..." }, { "raw": "40", "clean": "40" }, { "raw": "...", "clean": "..." } ], "length": "64", "bit_positions": "0:5 | 6:7 | 8 | 9:13 | 14:31 | 32:37 | 38:42 | 43:47 | 48:63" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "D", "desc": "Offset" }, { "name": "RA", "desc": "Base" }, { "name": "R", "desc": "PC-Rel" } ], "extension": "Prefixed", "description": "Loads a 16-bit halfword from memory using a 34-bit signed offset (split between prefix and suffix) and zero-extends the loaded value into the target register. The effective address is computed from a base register or the program counter (determined by the R bit), and both absolute and PC-relative modes are supported. This is a two-instruction prefixed load with no condition register or status flag effects.", "pseudocode": "D ← EXTS(D0 || D1)\nEA ← if R = 0 then (if RA = 0 then 0 else GPR[RA]) + D else CIA + D\nRT ← (0)^48 || MEM(EA, 2)", "example": "plh r3, 0(r4), 0" }, { "mnemonic": "plha", "architecture": "PowerISA", "full_name": "Prefixed Load Halfword Algebraic", "summary": "Loads 16-bit halfword (Sign Extended) using 34-bit offset.", "syntax": "plha RT, D(RA), R", "encoding": { "format": "MLS:D-form", "binary_pattern": "1 | 2 | R | 0 | D0 | 42 | RT | RA | D1", "hex_opcode": "0x06000000A8000000", "visual_parts": [ { "raw": "000001", "clean": "000001" }, { "raw": "10", "clean": "10" }, { "raw": "...", "clean": "..." }, { "raw": "42", "clean": "42" }, { "raw": "...", "clean": "..." } ], "length": "64", "bit_positions": "0:5 | 6:7 | 8 | 9:13 | 14:31 | 32:37 | 38:42 | 43:47 | 48:63" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "D", "desc": "Offset" }, { "name": "RA", "desc": "Base" }, { "name": "R", "desc": "PC-Rel" } ], "extension": "Prefixed", "description": "Loads a 16-bit halfword from memory using a 34-bit signed offset (split between prefix and suffix), sign-extends the loaded value to 64 bits, and stores the result in the target register. The effective address is computed from a base register or the program counter (determined by the R bit), supporting both absolute and PC-relative addressing modes. This is a two-instruction prefixed load with no condition register or status flag effects.", "pseudocode": "D ← EXTS(D0 || D1)\nEA ← if R = 0 then (if RA = 0 then 0 else GPR[RA]) + D else CIA + D\nRT ← EXTS(MEM(EA, 2))", "page_found": "Page 87", "programming_notes": "The plha instruction is commonly used for loading a halfword from memory into the upper half of a register while zeroing out the lower half. Ensure that the base and index registers are correctly set to avoid incorrect memory access. This instruction operates at user privilege level and may raise an exception if the effective address is invalid or if there's a protection fault.", "example": "plha r3, 0(r4), 0" }, { "mnemonic": "plwa", "architecture": "PowerISA", "full_name": "Prefixed Load Word Algebraic", "summary": "Loads 32-bit word (Sign Extended) using 34-bit offset.", "syntax": "plwa RT, D(RA), R", "encoding": { "format": "MLS:D-form", "binary_pattern": "1 | 2 | R | 0 | D0 | 41 | RT | RA | D1", "hex_opcode": "0x04000000A4000000", "visual_parts": [ { "raw": "000001", "clean": "000001" }, { "raw": "10", "clean": "10" }, { "raw": "...", "clean": "..." }, { "raw": "41", "clean": "41" }, { "raw": "...", "clean": "..." } ], "length": "64", "bit_positions": "0:5 | 6:7 | 8 | 9:13 | 14:31 | 32:37 | 38:42 | 43:47 | 48:63" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "D", "desc": "Offset" }, { "name": "RA", "desc": "Base" }, { "name": "R", "desc": "PC-Rel" } ], "extension": "Prefixed", "description": "Loads a 32-bit word from memory using a 34-bit signed offset (split between prefix and suffix), sign-extends the loaded value to 64 bits, and stores the result in the target register. The effective address is computed from a base register or the program counter (determined by the R bit), supporting both absolute and PC-relative addressing modes. This is a two-instruction prefixed load with no condition register or status flag effects.", "pseudocode": "D ← EXTS(D0 || D1)\nEA ← if R = 0 then (if RA = 0 then 0 else GPR[RA]) + D else CIA + D\nRT ← EXTS(MEM(EA, 4))", "page_found": "Page 90", "programming_notes": "The plwa instruction is commonly used for loading a word from memory into a register while ensuring the upper 32 bits are zeroed. Ensure that the base address in RA and the offset in RB are correctly set to avoid incorrect memory access. This instruction operates at user privilege level and will raise an exception if the effective address is out of bounds or if there is a protection fault.", "example": "plwa r3, 0(r4), 0" }, { "mnemonic": "pstb", "architecture": "PowerISA", "full_name": "Prefixed Store Byte", "summary": "Stores byte using 34-bit offset.", "syntax": "pstb RS, D(RA), R", "encoding": { "format": "MLS:D-form", "binary_pattern": "1 | 2 | R | 0 | D0 | 38 | RS | RA | D1", "hex_opcode": "0x0600000098000000", "visual_parts": [ { "raw": "000001", "clean": "000001" }, { "raw": "10", "clean": "10" }, { "raw": "...", "clean": "..." }, { "raw": "38", "clean": "38" }, { "raw": "...", "clean": "..." } ], "length": "64", "bit_positions": "0:5 | 6:7 | 8 | 9:13 | 14:31 | 32:37 | 38:42 | 43:47 | 48:63" }, "operands": [ { "name": "RS", "desc": "Source" }, { "name": "D", "desc": "Offset" }, { "name": "RA", "desc": "Base" }, { "name": "R", "desc": "PC-Rel" } ], "extension": "Prefixed", "description": "Stores the least significant byte of the source register to memory using a 34-bit signed offset (split between prefix and suffix). The effective address is computed from a base register or the program counter (determined by the R bit), supporting both absolute and PC-relative addressing modes. This is a two-instruction prefixed store with no condition register or status flag effects.", "pseudocode": "D ← EXTS(D0 || D1)\nEA ← if R = 0 then (if RA = 0 then 0 else GPR[RA]) + D else CIA + D\nMEM(EA, 1) ← GPR[RS][56:63]", "page_found": "Page 93", "programming_notes": "The pstb instruction is useful for storing a single byte from the uppermost byte of a register into memory. Ensure that RA and RB are correctly set to avoid incorrect memory addresses. This instruction operates at user privilege level and can raise an exception if the EA is out of bounds or if there's a protection fault.", "example": "pstb r3, 0(r4), 0" }, { "mnemonic": "psth", "architecture": "PowerISA", "full_name": "Prefixed Store Halfword", "summary": "Stores halfword using 34-bit offset.", "syntax": "psth RS, D(RA), R", "encoding": { "format": "MLS:D-form", "binary_pattern": "1 | 2 | R | 0 | D0 | 44 | RS | RA | D1", "hex_opcode": "0x06000000B0000000", "visual_parts": [ { "raw": "000001", "clean": "000001" }, { "raw": "10", "clean": "10" }, { "raw": "...", "clean": "..." }, { "raw": "44", "clean": "44" }, { "raw": "...", "clean": "..." } ], "length": "64", "bit_positions": "0:5 | 6:7 | 8 | 9:13 | 14:31 | 32:37 | 38:42 | 43:47 | 48:63" }, "operands": [ { "name": "RS", "desc": "Source" }, { "name": "D", "desc": "Offset" }, { "name": "RA", "desc": "Base" }, { "name": "R", "desc": "PC-Rel" } ], "extension": "Prefixed", "description": "Stores the least significant 16 bits of the source register to memory using a 34-bit signed offset (split between prefix and suffix). The effective address is computed from a base register or the program counter (determined by the R bit), supporting both absolute and PC-relative addressing modes. This is a two-instruction prefixed store with no condition register or status flag effects.", "pseudocode": "D ← EXTS(D0 || D1)\nEA ← if R = 0 then (if RA = 0 then 0 else GPR[RA]) + D else CIA + D\nMEM(EA, 2) ← GPR[RS][48:63]", "page_found": "Page 94", "programming_notes": "The psth instruction is used to store the lower half of a doubleword from register RS into memory. It's important to ensure that RA and RB are correctly set to calculate the effective address. If RA is zero, the base address is considered as zero. This instruction operates at user privilege level and can raise an exception if there's a memory access violation.", "example": "psth r3, 0(r4), 0" }, { "mnemonic": "pstw", "architecture": "PowerISA", "full_name": "Prefixed Store Word", "summary": "Stores word using 34-bit offset.", "syntax": "pstw RS, D(RA), R", "encoding": { "format": "MLS:D-form", "binary_pattern": "1 | 2 | R | 0 | D0 | 36 | RS | RA | D1", "hex_opcode": "0x0600000090000000", "visual_parts": [ { "raw": "000001", "clean": "000001" }, { "raw": "10", "clean": "10" }, { "raw": "...", "clean": "..." }, { "raw": "36", "clean": "36" }, { "raw": "...", "clean": "..." } ], "length": "64", "bit_positions": "0:5 | 6:7 | 8 | 9:13 | 14:31 | 32:37 | 38:42 | 43:47 | 48:63" }, "operands": [ { "name": "RS", "desc": "Source" }, { "name": "D", "desc": "Offset" }, { "name": "RA", "desc": "Base" }, { "name": "R", "desc": "PC-Rel" } ], "extension": "Prefixed", "description": "Stores the least significant 32 bits of the source register to memory using a 34-bit signed offset (split between prefix and suffix). The effective address is computed from a base register or the program counter (determined by the R bit), supporting both absolute and PC-relative addressing modes. This is a two-instruction prefixed store with no condition register or status flag effects.", "pseudocode": "D ← EXTS(D0 || D1)\nEA ← if R = 0 then (if RA = 0 then 0 else GPR[RA]) + D else CIA + D\nMEM(EA, 4) ← GPR[RS][32:63]", "programming_notes": "The pstw instruction is used to store a word from a source register into memory. It supports different addressing modes based on the prefix field and privilege level. Ensure that the base address in RA is properly aligned for optimal performance, and be cautious of potential exceptions if the EA calculation results in an invalid address.", "example": "pstw r3, 0(r4), 0" }, { "mnemonic": "xscvudqp", "architecture": "PowerISA", "full_name": "VSX Scalar Convert Unsigned Doubleword to Quad-Precision", "summary": "Converts 64-bit Unsigned Integer to 128-bit Float.", "syntax": "xscvudqp vD, vB", "encoding": { "format": "X-form", "binary_pattern": "63 | vD | / | vB | 724 | /", "hex_opcode": "0xFC020688", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "vD", "clean": "vD" }, { "raw": "/", "clean": "/" }, { "raw": "vB", "clean": "vB" }, { "raw": "724", "clean": "724" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" } ], "extension": "VSX", "description": "Converts an unsigned 64-bit doubleword value from the source VSR into a 128-bit IEEE 754 quadruple-precision (quad) floating-point value and stores the result in the target VSR. This VSX scalar operation uses the default rounding mode from FPSCR and updates the floating-point status and control register (FPSCR) with exception flags if applicable. The instruction requires VSX facility enablement.", "pseudocode": "FRT ← ConvertUnsignedIntegerToQuadPrecision(FRB[0:63], FPSCR[RN])\nFPSCR ← UpdateFlags(FPSCR)", "page_found": "Page 888", "special_registers": "FPSCR, MSR", "programming_notes": "This instruction is used to convert an unsigned doubleword integer into a quad-precision floating-point format. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking and setting the MSR.VSX bit. The conversion may alter the FPSCR register fields, so be aware of potential precision flags. This operation does not raise exceptions for normal input ranges.", "example": "xscvudqp vd, vb" }, { "mnemonic": "xscvsdqp", "architecture": "PowerISA", "full_name": "VSX Scalar Convert Signed Doubleword to Quad-Precision", "summary": "Converts a signed doubleword integer from VSR[VRB+32] to quad-precision floating-point in VSR[VRT+32].", "syntax": "xscvsdqp vD, vB", "encoding": { "format": "X-form", "binary_pattern": "63 | vD | / | vB | 756 | /", "hex_opcode": "0xFC0A0688", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "vD", "clean": "vD" }, { "raw": "/", "clean": "/" }, { "raw": "vB", "clean": "vB" }, { "raw": "756", "clean": "756" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "VRT", "desc": "Target Vector-Scalar Register" }, { "name": "VRB", "desc": "Source Vector-Scalar Register" } ], "extension": "VSX", "description": "The instruction converts the signed integer value in doubleword element 0 of VSR[VRB+32] to quad-precision floating-point format and stores it in VSR[VRT+32]. The FPSCR.FPRF, FPSCR.FR, and FPSCR.FI fields are updated accordingly.", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nsrc ← bfp_CONVERT_FROM_SI64(VSR[VRB+32].dword[0])\nresult ← bfp128_CONVERT_FROM_BFP(src)\nVSR[VRT+32] ← result\nFPSCR.FPRF ← fprf_CLASS_BFP128(result)\nFPSCR.FR ← 0\nFPSCR.FI ← 0", "special_registers": "FPSCR (FPRF, FR, FI)", "page_found": "Page 887 - 888", "programming_notes": "This instruction is commonly used for converting signed integers to quad-precision floating-point numbers in VSX registers. Ensure that the VSX facility is enabled (MSR.VSX=1) to avoid exceptions. The conversion respects standard rounding rules, and the FPSCR flags are updated accordingly. Be cautious of potential overflow or underflow conditions when dealing with very large or small integers.", "example": "xscvsdqp vd, vb" }, { "mnemonic": "xscvqpdp", "architecture": "PowerISA", "full_name": "VSX Scalar Convert Quad-Precision to Double", "summary": "Converts a quad-precision floating-point value to a double-precision floating-point value with round-to-even rounding.", "syntax": "xscvqpdp vD, vB", "encoding": { "format": "X-form", "binary_pattern": "1 | VRT | 0 | VRB | RO | 0 | 0 | 0", "hex_opcode": "0xFC140688", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "vD", "clean": "vD" }, { "raw": "/", "clean": "/" }, { "raw": "vB", "clean": "vB" }, { "raw": "836", "clean": "836" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:8 | 9 | 10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VSX", "description": "Converts a 128-bit quad-precision floating-point value in VSR vB to a 64-bit double-precision floating-point value, placing the result in the low 64 bits of VSR vD using round-to-even rounding. FPSCR exception flags (XX, ZX, OX, UX) are updated based on the conversion result. Requires VSX support.", "pseudocode": "vD[0:63] ← ConvertQuadPrecisionToDoublePrecision(vB[0:127])\nFPSCR[XX,ZX,OX,UX] ← updated based on conversion result", "special_registers": "FPSCR, FPRF, FR, FI, VXSNAN, OX, UX, XX", "page_found": "Page 826 - 827", "programming_notes": "This instruction is used to convert a quad-precision floating-point number to a double-precision floating-point number. Ensure that the VSX facility is enabled in the MSR register, as attempting to use this instruction when VSX is unavailable will result in an exception. The conversion respects the rounding mode specified in the FPSCR register, and any exceptions such as invalid operation (VXSNAN), overflow (OX), underflow (UX), or inexact (XX) are recorded in the FPSCR. The result is stored in the first doubleword of the destination vector register, with the second doubleword set to zero.", "example": "xscvqpdp vd, vb" }, { "mnemonic": "xsaddqpo", "architecture": "PowerISA", "full_name": "VSX Scalar Add Quad-Precision Odd", "summary": "Used for Quad-Precision arithmetic on hardware that splits quads.", "syntax": "xsaddqpo vD, vA, vB", "encoding": { "format": "X-form", "binary_pattern": "63 | vD | vA | vB | 4 | /", "hex_opcode": "0xFC000008", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "4", "clean": "4" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VSX", "description": "Adds the odd (high-order) portions of two 128-bit quad-precision floating-point values in VSRs vA and vB, placing the result in VSR vD. This instruction is used on systems that split quad-precision operands into even/odd register pairs. FPSCR exception flags are updated based on the operation result. Requires VSX support.", "pseudocode": "vD ← (vA + vB) as quad-precision (odd portion operation)\nFPSCR[XX,ZX,OX,UX,VXISI] ← updated based on operation result", "page_found": "Page 656", "special_registers": "FPSCR", "programming_notes": "The xsaddqpo instruction is used for adding two quad-precision floating-point numbers using the round-to-odd rounding mode. Ensure that the input operands are correctly aligned and that the VSX registers are properly set up. This instruction operates at a privilege level that allows access to floating-point operations, and it may raise exceptions if invalid operations occur, such as signaling NaNs or infinities. Performance can be impacted by the precision of the operation and the current rounding mode settings in the FPSCR register.", "example": "xsaddqpo vd, va, vb" }, { "mnemonic": "xssubqpo", "architecture": "PowerISA", "full_name": "VSX Scalar Subtract Quad-Precision Odd", "summary": "Used for Quad-Precision arithmetic on hardware that splits quads.", "syntax": "xssubqpo VRT,VRA,VRB", "encoding": { "format": "X-form", "binary_pattern": "63 | FRT | FRA | FRB | 514 | Rc", "hex_opcode": "0xFC000408", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "516", "clean": "516" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector-Scalar Register" }, { "name": "VRA", "desc": "Source Vector-Scalar Register" }, { "name": "VRB", "desc": "Source Vector-Scalar Register" } ], "extension": "VSX", "description": "Subtracts the odd (high-order) portion of a 128-bit quad-precision floating-point value in VSR vB from the odd portion in VSR vA, placing the result in VSR vD. This instruction is used on systems that split quad-precision operands into even/odd register pairs. FPSCR exception flags are updated based on the operation result. Requires VSX support.", "pseudocode": "vD ← (vA - vB) as quad-precision (odd portion operation)\nFPSCR[XX,ZX,OX,UX,VXISI] ← updated based on operation result", "page_found": "Page 679 - 680", "special_registers": "FPSCR", "programming_notes": "This instruction is commonly used for precise floating-point arithmetic operations in scientific computing. Be cautious of NaN handling; if src2 is a Quiet NaN, it will propagate as the result without performing any subtraction. Ensure that inputs are properly aligned to avoid alignment faults. This operation requires FPSCR for exception flags and rounding modes.", "example": "xssubqpo vd, va, vb" }, { "mnemonic": "xsdivqpo", "architecture": "PowerISA", "full_name": "VSX Scalar Divide Quad-Precision Odd", "summary": "Used for Quad-Precision arithmetic on hardware that splits quads.", "syntax": "xsdivqpo vD, vA, vB", "encoding": { "format": "X-form", "binary_pattern": "63 | vD | vA | vB | 548 | /", "hex_opcode": "0xFC000448", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "548", "clean": "548" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VSX", "description": "Divides the odd (high-order) portion of a 128-bit quad-precision floating-point value in VSR vA by the odd portion in VSR vB, placing the result in VSR vD. This instruction is used on systems that split quad-precision operands into even/odd register pairs. FPSCR exception flags are updated, including division-by-zero detection (ZX). Requires VSX support.", "pseudocode": "vD ← (vA / vB) as quad-precision (odd portion operation)\nFPSCR[XX,ZX,OX,UX,VXIDI,VXISI] ← updated based on operation result", "page_found": "Page 662", "special_registers": "FPSCR, MSR", "programming_notes": "The xsdivqpo instruction performs a scalar divide operation on two quad-precision floating-point values, rounding the result to the nearest odd integer when there is a tie. Ensure that VSX is enabled in the MSR register; otherwise, an exception will be raised. Be cautious with division by zero, as it results in infinity or NaN depending on the sign of the dividend.", "example": "xsdivqpo vd, va, vb" }, { "mnemonic": "xssqrtqpo", "architecture": "PowerISA", "full_name": "VSX Scalar Square Root Quad-Precision Odd", "summary": "Used for Quad-Precision arithmetic on hardware that splits quads.", "syntax": "xssqrtqpo vD, vB", "encoding": { "format": "X-form", "binary_pattern": "63 | vD | 0 | vB | 676 | /", "hex_opcode": "0xFC1B0648", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "676", "clean": "676" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" } ], "extension": "VSX", "description": "Computes the square root of the odd (high-order) portion of a 128-bit quad-precision floating-point value in VSR vB, placing the result in VSR vD. This instruction is used on systems that split quad-precision operands into even/odd register pairs. FPSCR exception flags are updated based on the operation result. Requires VSX support.", "pseudocode": "vD ← sqrt(vB) as quad-precision (odd portion operation)\nFPSCR[XX,ZX,OX,UX,VXSQRT] ← updated based on operation result", "page_found": "Page 674", "special_registers": "FPSCR", "programming_notes": "The xssqrtqpo instruction is used to compute the square root of a quad-precision floating-point value using the Round to Odd rounding mode. It handles signaling NaNs by raising an Invalid Operation exception and setting VXSNAN in the FPSCR. Ensure that the input is properly aligned and check the FPSCR for exceptions after execution.", "example": "xssqrtqpo vd, vb" }, { "mnemonic": "xsrqpi", "architecture": "PowerISA", "full_name": "VSX Scalar Round Quad-Precision to Integer", "summary": "Rounds a quad-precision floating-point value in VRB to an integer and places the result in VRT.", "syntax": "xsrqpi vD, vB, R", "encoding": { "format": "Z23-form", "binary_pattern": "63 | VRT | /// | R | VRB | RMC | 5 | EX", "hex_opcode": "0xFC00000A", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "vD", "clean": "vD" }, { "raw": "/", "clean": "/" }, { "raw": "vB", "clean": "vB" }, { "raw": "R", "clean": "R" }, { "raw": "5", "clean": "5" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:14 | 15 | 16:20 | 21:22 | 23:30 | 31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "R", "desc": "Mode" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "RMC", "desc": "Rounding Mode Control" } ], "extension": "VSX", "description": "Rounds a 128-bit quad-precision floating-point value in VSR vB to an integer value using rounding mode R, placing the result back in VSR vD as a quad-precision value. The rounding mode R is encoded in bit 31 (0=round-to-nearest-even, 1=round-toward-zero). FPSCR exception flags (XX, ZX) are updated based on the rounding operation. Requires VSX support.", "pseudocode": "rmode ← (R == 0) ? RoundToNearestEven : RoundTowardZero\nvD ← RoundToInteger(vB, rmode) as quad-precision\nFPSCR[XX,ZX] ← updated based on rounding result", "special_registers": "FPSCR, VXSNAN, FX", "page_found": "Page 841 - 842", "programming_notes": "The xsrqpi instruction is used to round a quad-precision floating-point value to an integer. Ensure that the VSX feature is enabled in the MSR register. Be cautious with NaN values, as they can trigger exceptions and set specific flags. The rounding mode is determined by the RMC field and the FPSCR.RN setting when R=0.", "example": "xsrqpi vd, vb, 0" }, { "mnemonic": "xsrqpix", "architecture": "PowerISA", "full_name": "VSX Scalar Round Quad-Precision to Integer Extended", "summary": "Rounds a Quad float to a Quad integer (Exact).", "syntax": "xsrqpix vD, vB, R", "encoding": { "format": "Z23-form", "binary_pattern": "63 | VRT | /// | R | VRB | RMC | 5 | EX", "hex_opcode": "0xFC00000B", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "vD", "clean": "vD" }, { "raw": "/", "clean": "/" }, { "raw": "vB", "clean": "vB" }, { "raw": "R", "clean": "R" }, { "raw": "37", "clean": "37" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:14 | 15 | 16:20 | 21:22 | 23:30 | 31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "R", "desc": "Mode" } ], "extension": "VSX", "description": "Rounds a quad-precision floating-point value in FRB to a quad-precision integer, placing the result in FRT. The rounding mode is specified by the R operand. FPSCR is updated with exceptions; this is a VSX instruction requiring VSX support.", "pseudocode": "let temp ← RoundToQuadInt(FRB, R)\nFRT ← temp\nFPSCR[FPRF, XX, ZX, UX, OX] ← updated based on operation", "page_found": "Page 842", "special_registers": "FPSCR, MSR", "programming_notes": "The xsrqpix instruction is used to round a quad-precision floating-point number to an integer. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register, as attempting to use this instruction when VSX is unavailable will result in an exception. The rounding mode is determined by the FPSCR register, and the instruction handles special cases like NaNs by setting appropriate flags in the FPSCR.", "example": "xsrqpix vd, vb, 0" }, { "mnemonic": "fmr", "architecture": "PowerISA", "full_name": "Floating Move Register", "summary": "Copies a float register (Pseudo: for FRB).", "syntax": "fmr FRT,FRB", "encoding": { "format": "X-form", "binary_pattern": "63 | FRT | 0 | FRB | 72 | /", "hex_opcode": "0xFC000090", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "72", "clean": "72" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" } ], "extension": "Floating-Point", "description": "The contents of register FRB are placed into register FRT.", "pseudocode": "FRT <- FRB", "special_registers": "CR1, (if, Rc=1), FPSCR", "page_found": "Page 195 - 196", "programming_notes": "The fmr instruction is used to copy the contents of one floating-point register (FRB) to another (FRT). It does not alter any special registers unless Rc=1, in which case it updates CR1. Ensure that both source and destination registers are properly aligned for optimal performance.", "example": "fmr f1, f3" }, { "mnemonic": "fabs", "architecture": "PowerISA", "full_name": "Floating Absolute Value", "summary": "Computes absolute value of a float.", "syntax": "fabs FRT, FRB", "encoding": { "format": "X-form", "binary_pattern": "63 | FRT | 0 | FRB | 264 | /", "hex_opcode": "0xFC000210", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "264", "clean": "264" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" } ], "extension": "Floating-Point", "description": "Computes the absolute value of a double-precision floating-point number in FRB and places the result in FRT. The sign bit is cleared while all other bits remain unchanged. No exception flags are set.", "pseudocode": "FRT ← abs(FRB)", "page_found": "Page 196", "special_registers": "FPSCR", "programming_notes": "The fabs instruction is commonly used when you need to ensure that a floating-point number is positive without altering its magnitude. Be cautious with NaN (Not-a-Number) values, as fabs will return a quiet NaN if the input is a signaling NaN. This instruction operates at user privilege level and does not raise exceptions for normal inputs; however, it respects the rounding mode set in the FPSCR register.", "example": "fabs f1, f3" }, { "mnemonic": "fneg", "architecture": "PowerISA", "full_name": "Floating Negate", "summary": "Negates a float.", "syntax": "fneg FRT, FRB", "encoding": { "format": "X-form", "binary_pattern": "63 | FRT | 0 | FRB | 40 | /", "hex_opcode": "0xFC000050", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "40", "clean": "40" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" } ], "extension": "Floating-Point", "description": "Negates a double-precision floating-point number in FRB by flipping the sign bit and places the result in FRT. No exception flags are set.", "pseudocode": "FRT ← -FRB", "special_registers": "FPSCR", "programming_notes": "The fneg instruction is commonly used to change the sign of a floating-point number. Ensure that the source register (FRA) contains a valid floating-point value before executing this instruction. The result is stored in the target register (FRT), which must be distinct from FRA. This operation does not affect any special registers like FPSCR unless there are exceptions such as invalid operations or overflow.", "example": "fneg f1, f3" }, { "mnemonic": "fnabs", "architecture": "PowerISA", "full_name": "Floating Negative Absolute Value", "summary": "Computes negative absolute value of a float.", "syntax": "fnabs FRT, FRB", "encoding": { "format": "X-form", "binary_pattern": "63 | FRT | 0 | FRB | 136 | /", "hex_opcode": "0xFC000110", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "136", "clean": "136" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" } ], "extension": "Floating-Point", "description": "Computes the negative absolute value of a double-precision floating-point number in FRB and places the result in FRT. The sign bit is set to 1 while all other bits are taken from the absolute value. No exception flags are set.", "pseudocode": "FRT ← -abs(FRB)", "page_found": "Page 196", "special_registers": "FPSCR", "programming_notes": "The fnabs instruction is useful for converting a positive floating-point number to its negative counterpart while maintaining its magnitude. Ensure that the input register (FRB) contains a valid floating-point value; otherwise, the result may be undefined. This operation does not affect the FPSCR register, so no exception flags are set based on the input value.", "example": "fnabs f1, f3" }, { "mnemonic": "fcpsgn", "architecture": "PowerISA", "full_name": "Floating Copy Sign", "summary": "Copies sign from FRB to FRA.", "syntax": "fcpsgn FRT, FRA, FRB", "encoding": { "format": "X-form", "binary_pattern": "63 | FRT | FRA | FRB | 8 | /", "hex_opcode": "0xFC000010", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "FRA", "clean": "FRA" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "8", "clean": "8" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRA", "desc": "Source" }, { "name": "FRB", "desc": "Sign Source" } ], "extension": "Floating-Point", "description": "Copies the sign bit from FRB to FRA, placing the result in FRT. The magnitude of FRA is preserved while the sign is replaced by that of FRB. No exception flags are set.", "pseudocode": "FRT ← (abs(FRA) with sign bit from FRB)", "page_found": "Page 196", "special_registers": "FPSCR", "programming_notes": "Use fcpsgn to change the sign of a floating-point number without altering its magnitude. Ensure both source and target registers are properly aligned and accessible. This instruction operates at user privilege level but may raise exceptions if operands are invalid or if there are precision issues.", "example": "fcpsgn f1, f2, f3" }, { "mnemonic": "fsel", "architecture": "PowerISA", "full_name": "Floating Select", "summary": "Selects FRA if FRC >= 0, else FRB (Optional).", "syntax": "fsel FRT,FRA,FRC,FRB", "encoding": { "format": "A-form", "binary_pattern": "63 | FRT | FRA | FRB | FRC | 23 | /", "hex_opcode": "0xFC00002E", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "FRA", "clean": "FRA" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "FRC", "clean": "FRC" }, { "raw": "23", "clean": "23" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRA", "desc": "True" }, { "name": "FRC", "desc": "Cond" }, { "name": "FRB", "desc": "False" } ], "extension": "Floating-Point", "description": "Selects between FRA and FRB based on the sign of FRC: if FRC ≥ 0, the result is FRA; otherwise, the result is FRB. The optional dot (.) form sets CR1 based on the result's FPRF. This is an optional category instruction.", "pseudocode": "if FRC ≥ 0.0 then\n FRT ← FRA\nelse\n FRT ← FRB\nif Rc = 1 then CR1 ← FPRF(FRT)", "special_registers": "CR1, FPSCR", "programming_notes": "Warning: Care must be taken in using fsel if IEEE compatibility is required, or if the values being tested can be NaNs or infinities.", "page_found": "Page 215 - 216", "example": "fsel f1, f2, f4, f3" }, { "mnemonic": "fsqrt", "architecture": "PowerISA", "full_name": "Floating Square Root", "summary": "Computes the square root of a floating-point number.", "syntax": "fsqrt FRT,FRB", "encoding": { "format": "X-form", "binary_pattern": "63 | FRT | 0 | FRB | 22 | /", "hex_opcode": "0xFC00002C", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "22", "clean": "22" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" } ], "extension": "Floating-Point", "description": "The square root of the floating-point operand in register FRB is placed into register FRT. If the most significant bit of the resultant significand is not 1, the result is normalized. The result is rounded to the target precision under control of RN and placed into register FRT.", "special_registers": "FPSCR, CR1", "page_found": "Page 199 - 200", "pseudocode": "if FRB < 0 then\n FRT ← QNaN\n if VE = 1 then raise VXSQRT exception\nelse\n FRT ← sqrt(FRB)\n if most significant bit of FRT's significand is not 1 then normalize FRT\n round FRT to target precision under control of RN\nend if\nFPSCR.FPRF ← class and sign of FRT\nif VE = 1 and result is invalid operation exception then raise VXSQRT exception", "programming_notes": "The fsqrt instruction computes the square root of a floating-point number. It handles negative inputs by returning a quiet NaN (QNaN) and may raise an exception if enabled. Ensure the input is non-negative to avoid unexpected results. The result is normalized and rounded according to the current rounding mode, which can affect precision.", "example": "fsqrt f1, f3" }, { "mnemonic": "fsqrts", "architecture": "PowerISA", "full_name": "Floating Square Root Single", "summary": "Computes square root (Single).", "syntax": "fsqrts FRT, FRB", "encoding": { "format": "X-form", "binary_pattern": "59 | FRT | 0 | FRB | 22 | /", "hex_opcode": "0xEC00002C", "visual_parts": [ { "raw": "59", "clean": "59" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "22", "clean": "22" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" } ], "extension": "Floating-Point", "description": "Computes the square root of a single-precision floating-point value in FRB and places the double-precision result in FRT. FPSCR exception flags (XX, ZX, UX, OX, VXSQRT) are updated appropriately.", "pseudocode": "FRT ← sqrt(FRB)\nFPSCR[FPRF, XX, ZX, UX, OX, VXSQRT] ← updated based on operation", "page_found": "Page 200", "special_registers": "FPSCR", "programming_notes": "The fsqrts instruction is commonly used for calculating the square root of single-precision floating-point numbers. Ensure that the input register FRB contains a valid single-precision float; otherwise, the result may be undefined or trigger an exception. The instruction operates at user privilege level and does not require any specific ordering or alignment of data. Be aware of rounding modes controlled by RN, as they can affect the precision of the result.", "example": "fsqrts f1, f3" }, { "mnemonic": "fmsub", "architecture": "PowerISA", "full_name": "Floating Multiply-Subtract", "summary": "Multiplies two floating-point values and subtracts a third.", "syntax": "fmsub FRT, FRA, FRC, FRB", "encoding": { "format": "A-form", "binary_pattern": "63 | FRT | FRA | FRB | FRC | 28 | /", "hex_opcode": "0xFC000038", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "FRA", "clean": "FRA" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "FRC", "clean": "FRC" }, { "raw": "28", "clean": "28" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:30 | 31", "length": "32" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRA", "desc": "A" }, { "name": "FRC", "desc": "C" }, { "name": "FRB", "desc": "B" } ], "extension": "Floating-Point", "description": "Performs a fused multiply-subtract operation: (FRA × FRC) - FRB in extended precision, then rounds to double-precision and places the result in FRT. FPSCR exception flags and FPRF are updated; this provides higher precision than separate multiply and subtract instructions.", "pseudocode": "FRT ← Round((FRA × FRC) - FRB)\nFPSCR[FPRF, XX, ZX, UX, OX, VXISI] ← updated based on operation", "special_registers": "FPSCR", "programming_notes": "The fmsub instruction is useful for performing fused multiply-subtract operations, which can help reduce rounding errors. Ensure that the input registers are properly aligned and contain valid floating-point numbers to avoid exceptions. This operation requires FPSCR to manage precision and exception flags.", "example": "fmsub f1, f2, f4, f3" }, { "mnemonic": "fnmadd", "architecture": "PowerISA", "full_name": "Floating Negative Multiply-Add", "summary": "Performs a floating-point negative multiply-add operation.", "syntax": "fnmadd FRT,FRA,FRC,FRB", "encoding": { "format": "A-form", "binary_pattern": "63 | FRT | FRA | FRB | FRC | 31 | /", "hex_opcode": "0xFC00003E", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "FRA", "clean": "FRA" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "FRC", "clean": "FRC" }, { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRA", "desc": "A" }, { "name": "FRC", "desc": "C" }, { "name": "FRB", "desc": "B" } ], "extension": "Floating-Point", "description": "The operation FRT ←- ( [(FRA)×(FRC)] + (FRB) ) is performed. The result is negated and placed into register FRT.", "pseudocode": "FRT ←- ( [(FRA)×(FRC)] + (FRB) )\nif 'fnmadd.' then\n update CR1 and FPSCR fields", "special_registers": "FPSCR, CR1", "page_found": "Page 204 - 206", "programming_notes": "The fnmadd instruction is useful for performing a negated multiply-add operation on floating-point numbers. Ensure that the input registers FRA, FRC, and FRB are correctly aligned and contain valid floating-point values to avoid exceptions. If using the 'fnmadd.' form, be aware that it updates CR1 and FPSCR, which can affect subsequent conditional operations or exception handling.", "example": "fnmadd f1, f2, f4, f3" }, { "mnemonic": "fnmsub", "architecture": "PowerISA", "full_name": "Floating Negative Multiply-Subtract", "summary": "-(A*C - B)", "syntax": "fnmsub FRT, FRA, FRC, FRB", "encoding": { "format": "A-form", "binary_pattern": "63 | FRT | FRA | FRB | FRC | 30 | /", "hex_opcode": "0xFC00003C", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "FRA", "clean": "FRA" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "FRC", "clean": "FRC" }, { "raw": "30", "clean": "30" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:30 | 31", "length": "32" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRA", "desc": "A" }, { "name": "FRC", "desc": "C" }, { "name": "FRB", "desc": "B" } ], "extension": "Floating-Point", "description": "Floating Negative Multiply-Subtract computes -(A*C - B) using fused multiply-subtract, where the intermediate product is not rounded. The result is rounded to the target precision according to the current rounding mode in FPSCR. FPSCR is updated with FPRF, FR, FI, and exception flags based on the result.", "pseudocode": "FRT ← -((FRA × FRC) - FRB)\nUpdate FPSCR[FPRF, FR, FI, exception flags]", "page_found": "Page 205", "special_registers": "FPSCR", "programming_notes": "The fnmsub instruction is commonly used in scenarios requiring efficient floating-point arithmetic operations, such as in scientific computations or graphics processing. Ensure that the input registers FRA, FRC, and FRB are properly aligned to avoid precision loss. Be aware of potential exceptions like underflow or overflow, which can be managed by checking the FPSCR register after execution.", "example": "fnmsub f1, f2, f4, f3" }, { "mnemonic": "frsp", "architecture": "PowerISA", "full_name": "Floating Round to Single-Precision", "summary": "Rounds the contents of a floating-point register to single-precision.", "syntax": "frsp FRT,FRB", "encoding": { "format": "X-form", "binary_pattern": "63 | FRT | / | FRB | 12 | Rc", "hex_opcode": "0xFC000018", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "12", "clean": "12" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" } ], "extension": "Floating-Point", "description": "The floating-point operand in register FRB is rounded to single-precision using the rounding mode specified by RN and placed into register FRT.", "pseudocode": "if (FRB)1:11 < 897 and (FRB)1:63 > 0 then\n if FPSCRUE = 0 then goto Disabled Exponent Underflow\n if FPSCRUE = 1 then goto Enabled Exponent Underflow\nend\n\nif (FRB)1:11 > 1150 and (FRB)1:11 < 2047 then\n if FPSCROE = 0 then goto Disabled Exponent Overflow\n if FPSCROE = 1 then goto Enabled Exponent Overflow\nend\n\nif (FRB)1:11 > 896 and (FRB)1:11 < 1151 then goto Normal Operand\n\nif (FRB)1:63 = 0 then goto Zero Operand\n\nif (FRB)1:11 = 2047 then\n if (FRB)12:63 = 0 then goto Infinity Operand\n if (FRB)12 = 1 then goto QNaN Operand\n if (FRB)12 = 0 and (FRB)13:63 > 0 then goto SNaN Operand\nend\n\nDisabled Exponent Underflow:\n sign ←(FRB)0\n if (FRB)1:11 = 0 then\n exp ←-1022\n frac0:52 ←0b0 || (FRB)12:63\n end\n if (FRB)1:11 > 0 then\n exp ←(FRB)1:11 -1023\n frac0:52 ←0b1 || (FRB)12:63\n end\n Denormalize operand:\n G || R || X ←0b000\n do while exp < -126\n exp ←exp + 1\n frac0:52 || G || R || X ←0b0 || frac0:52 || G || (R | X)\n end\n FPSCRUX ←(frac24:52 || G || R || X) > 0\n Round Single(sign,exp,frac0:52,G,R,X)\n FPSCRXX ←FPSCRXX | FPSCRFI", "special_registers": "FPSCR (FPRF FR FI FX OX UX XX VXSNAN), CR1", "page_found": "Page 205 - 206", "programming_notes": "The frsp instruction rounds a double-precision floating-point number to single precision. It handles various cases like underflow, overflow, and NaNs, setting appropriate flags in the FPSCR register. Ensure that the input register FRB is correctly set before calling this instruction.", "example": "frsp f1, f3" }, { "mnemonic": "fctid", "architecture": "PowerISA", "full_name": "Floating Convert with round Double-Precision To Signed Doubleword format X-form (Rc=0)", "summary": "Converts a double-precision floating-point value to a signed 64-bit integer using rounding.", "syntax": "fctid FRT, FRB", "encoding": { "format": "X-form", "binary_pattern": "63 | FRT | / | FRB | 814 | Rc", "hex_opcode": "0xFC00065C", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "814", "clean": "814" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" } ], "extension": "Floating-Point", "description": "Let src be the double-precision floating-point value in FRB. If src is a NaN, then the result is 0x8000_0000_0000_0000, VXCVI is set to 1, and if src is an SNaN, VXSNAN is set to 1. Otherwise, src is rounded to a floating-point integer using the rounding mode specified by RN. If the rounded value is greater than 263-1, then the result is 0x7FFF_FFFF_FFFF_FFFF and VXCVI is set to 1. Otherwise, if the rounded value is less than -263, then the result is 0x8000_0000_0000_0000 and VXCVI is set to 1. Otherwise, the result is the rounded value converted to 64-bit signed-integer format, and XX is set to 1 if the result is inexact. If an enabled Invalid Operation Exception does not occur, then the result is placed into FRT.", "pseudocode": "if src is a NaN then\n FRT <- 0x8000_0000_0000_0000\n VXCVI <- 1\n if src is an SNaN then VXSNAN <- 1\nelse\n rounded_value <- round(src, RN)\n if rounded_value > 263-1 then\n FRT <- 0x7FFF_FFFF_FFFF_FFFF\n VXCVI <- 1\n else if rounded_value < -263 then\n FRT <- 0x8000_0000_0000_0000\n VXCVI <- 1\n else\n FRT <- convert_to_signed_integer(rounded_value)\n XX <- is_inexact(FRT)\nif not enabled Invalid Operation Exception then\n place result into FRT", "special_registers": "FPSCR, (FR, FI, FX, XX, VXSNAN, VXCVI), CR1, (if, Rc=1), CR0", "page_found": "Page 206 - 208", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "fctid f1, f3" }, { "mnemonic": "fctidz", "architecture": "PowerISA", "full_name": "Floating Convert to Integer Doubleword with Round to Zero", "summary": "Converts Double to 64-bit Int (Truncate).", "syntax": "fctidz FRT, FRB", "encoding": { "format": "X-form", "binary_pattern": "63 | FRT | 0 | FRB | 815 | /", "hex_opcode": "0xFC00065E", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "815", "clean": "815" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" } ], "extension": "Floating-Point", "description": "Floating Convert to Integer Doubleword with Round to Zero converts the double-precision floating-point value in FRB to a signed 64-bit integer, truncating toward zero (round-to-zero), and places the result in FRT as a floating-point representation. FPSCR is updated with FPRF, FR, and FI flags; exception flags (XX, ZX) are set if applicable.", "pseudocode": "FRT ← (int64_t)truncate(FRB)\nUpdate FPSCR[FPRF, FR, FI, XX, ZX]", "page_found": "Page 207", "special_registers": "FPSCR", "programming_notes": "The fctidz instruction converts a double-precision floating-point value to a signed 64-bit integer, rounding towards zero. If the source value is NaN, it returns 0x8000_0000_0000_0000 and sets VXCVI to 1. If the rounded value exceeds the range of a 64-bit signed integer, it saturates to either 0x7FFF_FFFF_FFFF_FFFF or 0x8000_0000_0000_0000.", "example": "fctidz f1, f3" }, { "mnemonic": "fctiwz", "architecture": "PowerISA", "full_name": "Floating Convert to Integer Word with Round to Zero", "summary": "Converts Double to 32-bit Int (Truncate).", "syntax": "fctiwz FRT, FRB", "encoding": { "format": "X-form", "binary_pattern": "63 | FRT | 0 | FRB | 15 | /", "hex_opcode": "0xFC00001E", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "15", "clean": "15" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" } ], "extension": "Floating-Point", "description": "Floating Convert to Integer Word with Round to Zero converts the double-precision floating-point value in FRB to a signed 32-bit integer, truncating toward zero, and places the result in FRT as a floating-point representation. FPSCR is updated with FPRF, FR, and FI flags; exception flags (XX, ZX) are set if applicable.", "pseudocode": "FRT ← (int32_t)truncate(FRB)\nUpdate FPSCR[FPRF, FR, FI, XX, ZX]", "page_found": "Page 209", "special_registers": "FPSCR", "programming_notes": "The fctiwz instruction is commonly used for converting floating-point numbers to integers with truncation. Be cautious of NaN inputs, which will result in zero and set VXCVI; SNaNs also set VXSNAN. Ensure the input is within the 32-bit signed integer range to avoid saturation. This instruction operates at user privilege level.", "example": "fctiwz f1, f3" }, { "mnemonic": "fcfid", "architecture": "PowerISA", "full_name": "Floating Convert with round Signed Doubleword to Double-Precision format", "summary": "Converts a signed doubleword integer to a double-precision floating-point number.", "syntax": "fcfid FRT,FRB", "encoding": { "format": "X-form", "binary_pattern": "63 | FRT | 0 | FRB | 846 | /", "hex_opcode": "0xFC00069C", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "846", "clean": "846" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" } ], "extension": "Floating-Point", "description": "The 64-bit signed fixed-point operand in register FRB is converted to an infinitely precise floating-point integer. The result of the conversion is rounded to double-precision, using the rounding mode specified by RN, and placed into register FRT.", "pseudocode": "if 'fcfid' then\n FRT <- (FRB) converted to double-precision floating-point integer\n round result using RN\n if Rc=1 then update CR1", "special_registers": "FPSCR, CR1 (if Rc=1)", "programming_notes": "Converting a signed integer word to double-precision floating-point can be accomplished by loading the word from storage using Load Float Word Algebraic Indexed and then using fcfid.", "page_found": "Page 210 - 212", "example": "fcfid f1, f3" }, { "mnemonic": "fcfids", "architecture": "PowerISA", "full_name": "Floating Convert with round Signed Doubleword to Single-Precision format", "summary": "Converts a 64-bit signed fixed-point operand in register FRB to single-precision floating-point.", "syntax": "fcfids FRT,FRB", "encoding": { "format": "X-form", "binary_pattern": "59 | FRT | 0 | FRB | 846 | /", "hex_opcode": "0xEC00069C", "visual_parts": [ { "raw": "59", "clean": "59" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "846", "clean": "846" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" } ], "extension": "Floating-Point", "description": "The 64-bit signed fixed-point operand in register FRB is converted to an infinitely precise floating-point integer. The result of the conversion is rounded to single-precision, using the rounding mode specified by RN, and placed into register FRT.", "special_registers": "FPSCR (FPRF, FR, FI, FX, XX), CR1 (if Rc=1)", "programming_notes": "Converting a signed integer word to single-precision floating-point can be accomplished by loading the word from storage using Load Float Word Algebraic and then using fcfids.", "page_found": "Page 211 - 212", "pseudocode": "FRT ← ConvertToFloat(FRB, RN)\nSetFlags(FPRF, FR, FI)", "example": "fcfids f1, f3" }, { "mnemonic": "fcfidu", "architecture": "PowerISA", "full_name": "Floating Convert from Unsigned Integer Doubleword", "summary": "Converts 64-bit Unsigned Int to Double.", "syntax": "fcfidu FRT, FRB", "encoding": { "format": "X-form", "binary_pattern": "63 | FRT | 0 | FRB | 974 | /", "hex_opcode": "0xFC00079C", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "974", "clean": "974" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" } ], "extension": "Floating-Point", "description": "Floating Convert from Unsigned Integer Doubleword converts the unsigned 64-bit integer held in FRB to a double-precision floating-point value and places the result in FRT. The conversion uses the current rounding mode in FPSCR. FPSCR is updated with FPRF, FR, and FI flags.", "pseudocode": "FRT ← (double)(uint64_t)FRB\nUpdate FPSCR[FPRF, FR, FI]", "page_found": "Page 211", "special_registers": "FPSCR", "programming_notes": "The fcfidu instruction converts a 64-bit unsigned integer to a double-precision floating-point value. Be cautious of NaN inputs, which will result in zero with VXCVI set. Ensure the source register contains valid data; otherwise, unexpected results may occur. This instruction operates at user privilege level.", "example": "fcfidu f1, f3" }, { "mnemonic": "fcfidus", "architecture": "PowerISA", "full_name": "Floating Convert from Unsigned Integer Doubleword Single", "summary": "Converts 64-bit Unsigned Int to Single.", "syntax": "fcfidus FRT, FRB", "encoding": { "format": "X-form", "binary_pattern": "59 | FRT | 0 | FRB | 974 | /", "hex_opcode": "0xEC00079C", "visual_parts": [ { "raw": "59", "clean": "59" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "974", "clean": "974" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" } ], "extension": "Floating-Point", "description": "Floating Convert from Unsigned Integer Doubleword Single converts the unsigned 64-bit integer held in FRB to a single-precision floating-point value and places the result in FRT. The conversion uses the current rounding mode in FPSCR. FPSCR is updated with FPRF, FR, and FI flags.", "pseudocode": "FRT ← (float)(uint64_t)FRB\nUpdate FPSCR[FPRF, FR, FI]", "page_found": "Page 212", "special_registers": "FPSCR", "programming_notes": "The fcfidus instruction is used to convert a 64-bit unsigned integer from one register to a single-precision floating-point number in another register. Ensure the source register contains a valid unsigned integer and that the rounding mode specified by RN is appropriate for your application. This instruction alters several fields in the FPSCR, so be aware of potential flag changes that may affect subsequent operations.", "example": "fcfidus f1, f3" }, { "mnemonic": "lvx", "architecture": "PowerISA", "full_name": "Load Vector Indexed", "summary": "Loads a 128-bit vector from memory into a Vector Register. Address must be 16-byte aligned (bits 60-63 of effective address are ignored).", "syntax": "lvx vD, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | VRT | RA | RB | 103 | /", "hex_opcode": "0x7C0000CE", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "vD", "clean": "vD" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "7", "clean": "7" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "vD", "desc": "Target Vector Register" }, { "name": "RA", "desc": "Base Register" }, { "name": "RB", "desc": "Index Register" }, { "name": "Vt", "desc": "Target Vector Register" }, { "name": "Rb", "desc": "Base General Purpose Register" }, { "name": "VRT", "desc": "Target Vector Register" } ], "pseudocode": "EA ← (RA + RB) & 0xFFF...FF0\nVRT ← [EA]", "example": "lvx v1, r3, r4", "example_note": "Load aligned vector.", "extension": "VMX (AltiVec)", "description": "Load Vector Indexed loads a 128-bit vector from memory at the address computed from RA and RB, placing the result in VRT. The effective address must be 16-byte aligned; the low 4 bits of the computed address are ignored. This is a VMX/AltiVec instruction requiring the Vector facility to be enabled.", "page_found": "Page 288 - 290", "programming_notes": "The Load Vector Element instructions load the specified element into the same location in the target register as the location into which it would be loaded using the Load Vector instruction.", "special_registers": "MSR" }, { "mnemonic": "stvx", "architecture": "PowerISA", "full_name": "Store Vector Indexed", "summary": "Stores a quadword from a vector register to memory at an address formed by adding two general-purpose registers.", "syntax": "stvx vS, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | vS | RA | RB | 231 | /", "hex_opcode": "0x7C0001CE", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "vS", "clean": "vS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "231", "clean": "231" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "vS", "desc": "Source Vector Register" }, { "name": "RA", "desc": "Base Register" }, { "name": "RB", "desc": "Index Register" }, { "name": "VRS", "desc": "Vector Register" } ], "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nEA ←((RA=0) ? 0 : GPR[RA]) + GPR[RB]\nEA ←EA & 0xFFFF_FFFF_FFFF_FFF0\nMEM(EA, 16) ←VSR[VRS+32]", "example": "stvx v1, r3, r4", "example_note": "Store aligned vector.", "extension": "VMX (AltiVec)", "description": "The contents of VSR[VRS+32] are placed into the quad-word in storage at address EA, which is the result of ANDing 0xFFFF_FFFF_FFFF_FFF0 with the sum (RA|0) + (RB).", "page_found": "Page 300 - 302", "special_registers": "MSR", "programming_notes": "The stvx instruction stores a vector register into memory. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register if necessary. The effective address (EA) must be aligned to a 16-byte boundary, as indicated by the AND operation with 0xFFFF_FFFF_FFFF_FFF0. This instruction operates at user privilege level but will raise an exception if the Vector Facility is not available." }, { "mnemonic": "vsubuwm", "architecture": "PowerISA", "full_name": "Vector Subtract Unsigned Word Modulo", "summary": "Subtracts the contents of two vector registers and updates the result in another vector register.", "syntax": "vsubuwm vD, vA, vB", "encoding": { "format": "VA-form", "binary_pattern": "4 | VRT | VRA | VRB | 1152", "hex_opcode": "0x10000480", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1152", "clean": "1152" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Source A" }, { "name": "vB", "desc": "Source B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n src1 ←EXTZ(VSR[VRA+32].word[i])\n src2 ←EXTZ(VSR[VRB+32].word[i])\n VSR[VRT+32].word[i] ←CHOP32(src1 + ¬src2 + 1)\nend", "example": "vsubuwm v1, v2, v3", "example_note": "4 parallel word subtractions.", "extension": "VMX (AltiVec)", "description": "For vsubuwm, each word element in VSR[VRB+32] is subtracted from the corresponding word element in VSR[VRA+32]. The low-order 32 bits of the result are placed into the corresponding word element in VSR[VRT+32].", "page_found": "Page 359 - 360", "special_registers": "MSR", "programming_notes": "This instruction performs unsigned word modulo subtraction on vector registers. Ensure that the Vector Facility is enabled by checking and setting the appropriate bit in the MSR register. Be cautious of potential overflow conditions, as this operation does not handle carry-out explicitly. The operation is performed on 32-bit words, so ensure proper alignment if dealing with larger data types." }, { "mnemonic": "vspltw", "architecture": "PowerISA", "full_name": "Vector Splat Word", "summary": "Copies a single word element from the source vector into all four word elements of the destination.", "syntax": "vspltw vD, vB, UIM", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | UIM | vB | 652", "hex_opcode": "0x1000028C", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "UIM", "clean": "UIM" }, { "raw": "vB", "clean": "vB" }, { "raw": "652", "clean": "652" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "UIM", "desc": "Element Index (0-3)" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "pseudocode": "word ← VRB[4×UIM : 4×UIM+31]\nVRT[0:31] ← word\nVRT[32:63] ← word\nVRT[64:95] ← word\nVRT[96:127] ← word", "example": "vspltw v1, v2, 0", "example_note": "Broadcast word 0 to all lanes.", "extension": "VMX (AltiVec)", "description": "Vector Splat Word copies a single word element (32 bits) from the source vector VRB at position UIM into all four word elements of the destination vector VRT. UIM selects one of the four words (0-3) in the source. This is a VMX/AltiVec instruction.", "page_found": "Page 319 - 320", "special_registers": "MSR", "programming_notes": "The vspltw instruction is used to replicate a selected word from one vector register into all words of another vector register. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. The index 'b' is derived by concatenating the UIM field with four zeros, and it specifies which 32-bit word to replicate. This instruction operates at the user privilege level." }, { "mnemonic": "vperm", "architecture": "PowerISA", "full_name": "Vector Permute", "summary": "The signature AltiVec instruction. Constructs a new vector by selecting bytes from two source vectors based on a permute control vector.", "syntax": "vperm vD, vA, vB, vC", "encoding": { "format": "VA-form", "binary_pattern": "4 | vD | vA | vB | vC | 43", "hex_opcode": "0x1000002B", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "vC", "clean": "vC" }, { "raw": "43", "clean": "43" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Source 1 (Bytes 0-15)" }, { "name": "vB", "desc": "Source 2 (Bytes 16-31)" }, { "name": "vC", "desc": "Control Vector" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "VRC", "desc": "Permute Control Vector Register" } ], "pseudocode": "for i ← 0 to 15\n control ← VRC[8×i : 8×i+4]\n if control < 16 then\n VRT[8×i : 8×i+7] ← VRA[8×control : 8×control+7]\n else\n VRT[8×i : 8×i+7] ← VRB[8×(control-16) : 8×(control-16)+7]", "example": "vperm v1, v2, v3, v4", "example_note": "Arbitrary byte shuffle/merge.", "extension": "VMX (AltiVec)", "description": "Vector Permute constructs a new 128-bit vector in VRT by selecting bytes from two source vectors (VRA and VRB) using a permute control vector VRC. Bytes 0-15 of the result come from VRA, bytes 16-31 from VRB; the low 5 bits of each byte in VRC index into the 32-byte concatenated source. This is the signature VMX/AltiVec instruction and requires the Vector facility.", "programming_notes": "See the Programming Notes with the Load Vector for Shift Left and Load Vector for Shift Right instructions on page 266 for examples of uses of vperm.", "page_found": "Page 321 - 322", "special_registers": "MSR" }, { "mnemonic": "vslw", "architecture": "PowerISA", "full_name": "Vector Shift Left Word", "summary": "Shifts each of the four words in vA left by the number of bits specified in the corresponding word of vB.", "syntax": "vslw vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 388", "hex_opcode": "0x10000184", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "388", "clean": "388" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Source Data" }, { "name": "vB", "desc": "Shift Amounts" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n src1 ← VSR[VRA+32].word[i]\n src2 ← VSR[VRB+32].word[i].bit[27:31]\n VSR[VRT+32].word[i] ← src1 << src2", "example": "vslw v1, v2, v3", "example_note": "Parallel shift.", "extension": "VMX (AltiVec)", "description": "For vslw, each word element of VSR[VRA+32] is shifted left by the number of bits specified in the low-order 5 bits of the corresponding word element of VSR[VRB+32].", "page_found": "Page 438 - 439", "special_registers": "MSR", "programming_notes": "The vslw instruction shifts each word element of the source vector left by a specified number of bits. Ensure that the shift amount is within the range 0-31 to avoid undefined behavior. This operation requires the Vector Facility to be enabled in the MSR register; otherwise, it will raise an exception." }, { "mnemonic": "vcmpequw", "architecture": "PowerISA", "full_name": "Vector Compare Equal Word", "summary": "Compares each word of two vector registers and sets the corresponding word in the target register to all 1s if they are equal, otherwise all 0s.", "syntax": "vcmpequw VRT,VRA,VRB", "encoding": { "format": "VC-form", "binary_pattern": "0 | VRT | VRA | VRB | Rc", "hex_opcode": "0x10000086", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "134", "clean": "134" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target (Mask)" }, { "name": "vA", "desc": "Source A" }, { "name": "vB", "desc": "Source B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "pseudocode": "if MSR.VEC=0 then Vector_Unavailable()\n\nall_true ←1\nall_false ←1\ndo i = 0 to 3\n src1 ←VSR[VRA+32].word[i]\n src2 ←VSR[VRB+32].word[i]\n if src1 = src2 then do\n VSR[VRT+32].word[i] ←0xFFFF_FFFF\n all_false ←0\n end\n else do\n VSR[VRT+32].word[i] ←0x0000_0000\n all_true ←0\n end\nend\ndo i = 0 to 3\n src1 ←VSR[VRA+32].word[i]\n src2 ←VSR[VRB+32].word[i]\n if src1 = src2 then do\n VSR[VRT+32].word[i] ←0xFFFF_FFFF\n all_false ←0\n end\n else do\n VSR[VRT+32].word[i] ←0x0000_0000\n all_true ←0\n end\nend\nif Rc=1 then\n CR.field[6] ←all_true || 0b0 || all_false || 0b0", "example": "vcmpequw v1, v2, v3", "example_note": "Generate mask for equality.", "extension": "VMX (AltiVec)", "description": "For vcmpequw, each word of VSR[VRA+32] is compared with the corresponding word of VSR[VRB+32]. If they are equal, the corresponding word in VSR[VRT+32] is set to 0xFFFF_FFFF; otherwise, it is set to 0x0000_0000.", "special_registers": "CR6", "page_found": "Page 415 - 416", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes." }, { "mnemonic": "vsel", "architecture": "PowerISA", "full_name": "Vector Select", "summary": "Bitwise selection. copies bits from vA if the corresponding bit in vC is 0, or from vB if vC is 1. (Like 'mux').", "syntax": "vsel vD, vA, vB, vC", "encoding": { "format": "VA-form", "binary_pattern": "0 | VRT | VRA | VRB | VRC | 42", "hex_opcode": "0x1000002A", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "vC", "clean": "vC" }, { "raw": "42", "clean": "42" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Source 0" }, { "name": "vB", "desc": "Source 1" }, { "name": "vC", "desc": "Control (Selector)" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "VRC", "desc": "Mask Vector Register" } ], "pseudocode": "for i in 0 to 127:\n if vC[i] = 0 then vD[i] ← vA[i]\n else vD[i] ← vB[i]", "example": "vsel v1, v2, v3, v4", "example_note": "Bitwise MUX.", "extension": "VMX (AltiVec)", "description": "Performs bitwise selection from two source vectors based on a control vector. For each bit position, copies the bit from vA if the corresponding bit in vC is 0, or from vB if vC is 1. This is a three-operand mux operation. No condition registers or status flags are affected.", "page_found": "Page 322 - 324", "special_registers": "MSR", "programming_notes": "The vsel instruction requires the Vector Facility to be enabled in the MSR. Ensure that VRA, VRB, and VRC are properly aligned and contain valid data. The result is stored in VRT, so ensure it is not being used elsewhere in your computation until the operation completes." }, { "mnemonic": "lxvd2x", "architecture": "PowerISA", "full_name": "Load VSX Vector Doubleword*2 Indexed", "summary": "Loads a 128-bit vector from memory into a VSX register. Does NOT require 16-byte alignment (unlike lvx).", "syntax": "lxvd2x XT, RA, RB", "encoding": { "format": "XX1-form", "binary_pattern": "31 | XT | RA | RB | 844 | 1", "hex_opcode": "0x7C000698", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "XT", "clean": "XT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "844", "clean": "844" }, { "raw": "1", "clean": "1" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "XT", "desc": "Target VSR (0-63)" }, { "name": "RA", "desc": "Base Register" }, { "name": "RB", "desc": "Index Register" } ], "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nEA ←((RA=0) ? 0 : GPR[RA]) + GPR[RB]\nfor i from 0 to 1 do\n VSR[32×TX+T].dword[i] ←MEM(EA+8×i, 8)", "example": "lxvd2x 32, r3, r4", "example_note": "Unaligned 128-bit load to vs32 (v0).", "extension": "VSX", "description": "The contents of the byte in storage at address EA+8×i+7 are placed into byte element 7 of load_data. When Little-Endian byte ordering is employed, the contents of the doubleword in storage at address EA+8×i are placed into load_data in such an order that; the contents of the byte in storage at address EA+8×i are placed into byte element 7 of load_data, and so forth until the contents of the byte in storage at address EA+8×i+7 are placed into byte element 0 of load_data. For each integer value i from 0 to 1, do the following.", "programming_notes": "lxvd2x, lxvw4x, lxvh8x, lxvb16x, and lxvx exhibit identical behavior in Big-Endian mode.", "page_found": "Page 612 - 613", "special_registers": "MSR" }, { "mnemonic": "stxvd2x", "architecture": "PowerISA", "full_name": "Store VSX Vector Doubleword*2 Indexed", "summary": "Stores a 128-bit VSX register to memory. Does NOT require alignment.", "syntax": "stxvd2x XS, RA, RB", "encoding": { "format": "XX1-form", "binary_pattern": "31 | XS | RA | RB | 972 | 1", "hex_opcode": "0x7C000798", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "XS", "clean": "XS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "972", "clean": "972" }, { "raw": "1", "clean": "1" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "XS", "desc": "Source VSR" }, { "name": "RA", "desc": "Base Register" }, { "name": "RB", "desc": "Index Register" } ], "pseudocode": "EA ← (RA = 0) ? RB : (RA + RB)\n[EA : EA+15] ← XS[0:127]", "example": "stxvd2x 32, r3, r4", "example_note": "Unaligned 128-bit store.", "extension": "VSX", "description": "Stores a 128-bit VSX register to memory at the address computed from the base and index registers. The address is the sum of RA and RB (or 0 if RA = 0). Unlike some VSX store instructions, this instruction does not require natural alignment. No condition registers or status flags are affected.", "programming_notes": "stxvd2x, stxvw4x, stxvh8x, stxvb16x, and stxvx exhibit identical behavior in Big-Endian mode.", "page_found": "Page 628 - 629", "special_registers": "MSR" }, { "mnemonic": "xvadddp", "architecture": "PowerISA", "full_name": "VSX Vector Add Double-Precision", "summary": "Adds the contents of two double-precision floating-point elements from two vector registers and places the result into a target vector register.", "syntax": "xvadddp XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "T | A | B | AX | BX | TX", "hex_opcode": "0xF0000300", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "96", "clean": "96" } ], "length": "32", "bit_positions": "0:10 | 11:15 | 16:20 | 21:25 | 26:30 | 31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Source A" }, { "name": "XB", "desc": "Source B" } ], "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\n\nex_flag ←0b0\ndo i = 0 to 1\n reset_xflags()\n src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[i])\n src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])\n v ←bfp_ADD(src1,src2)\n rnd ←bfp_ROUND_TO_BFP64(0b0,FPSCR.RN,v)\n vresult.dword[i] ←bfp64_CONVERT_FROM_BFP(rnd)\n\n if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\n if vxisi_flag=1 then SetFX(FPSCR.VXISI)\n if ox_flag=1 then SetFX(FPSCR.OX)\n if ux_flag=1 then SetFX(FPSCR.UX)\n if xx_flag=1 then SetFX(FPSCR.XX)\n\n ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vxisi_flag) | (FPSCR.OE & ox_flag) | (FPSCR.UE & ux_flag) | (FPSCR.XE & xx_flag)\nend\n\nif ex_flag=0 then VSR[32×TX+T] ←vresult", "example": "xvadddp 0, 1, 2", "example_note": "2-way parallel double add.", "extension": "VSX", "description": "For xvadddp, the sum of the contents of doubleword element i of VSR[XA] and VSR[XB] is placed into doubleword element i of VSR[XT].", "special_registers": "FPSCR", "page_found": "Page 726 - 727", "programming_notes": "This instruction is commonly used for adding two double-precision floating-point numbers stored in VSX registers. Ensure that the VSX facility is enabled by checking and setting the MSR.VSX bit. Be aware of potential exceptions such as NaNs or infinities, which can set flags in the FPSCR register. The operation respects the rounding mode specified in FPSCR.RN." }, { "mnemonic": "xvmaddadp", "architecture": "PowerISA", "full_name": "VSX Vector Multiply-Add Double-Precision", "summary": "Performs a double-precision floating-point multiply-add operation on vector elements.", "syntax": "xvmaddadp XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "1000 | XA | XB | XT | 0000 | 0000 | 0000 | 0000", "hex_opcode": "0xF0000308", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "104", "clean": "104" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:28 | 29 | 30 | 31" }, "operands": [ { "name": "XT", "desc": "Target/Addend (Accumulator)" }, { "name": "XA", "desc": "Multiplier" }, { "name": "XB", "desc": "Multiplicand" } ], "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nex_flag ←0b0\ndo i = 0 to 1\n reset_xflags()\n src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[i])\n src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×TX+T].dword[i])\n src3 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])\n v ←bfp_MULTIPLY_ADD(src1,src3,src2)\n rnd ←bfp_ROUND_TO_BFP64(0b0,FPSCR.RN,v)\n vresult.dword[i] ←bfp64_CONVERT_FROM_BFP(rnd)\n if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\n if vximz_flag=1 then SetFX(FPSCR.VXIMZ)\n if vxisi_flag=1 then SetFX(FPSCR.VXISI)\n if ox_flag=1 then SetFX(FPSCR.OX)\n if ux_flag=1 then SetFX(FPSCR.UX)\n if xx_flag=1 then SetFX(FPSCR.XX)\n ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vximz_flag) | (FPSCR.VE & vxisi_flag) | (FPSCR.OE & ox_flag) | (FPSCR.UE & ux_flag) | (FPSCR.XE & xx_flag)\nend\nif ex_flag=0 then VSR[32×TX+T] ←result", "example": "xvmaddadp 0, 1, 2", "example_note": "Vector FMA.", "extension": "VSX", "description": "For xvmaddadp, the double-precision floating-point operand in doubleword element i of VSR[XA] is multiplied by the double-precision floating-point operand in doubleword element i of VSR[XB], and then added to the double-precision floating-point operand in doubleword element i of VSR[XT]. The result is normalized and rounded to double precision.", "special_registers": "FPSCR", "page_found": "Page 745 - 746", "programming_notes": "This instruction is commonly used for performing vectorized floating-point operations in parallel, which can significantly speed up computations involving large datasets. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking and setting the appropriate bits in the MSR register. Be cautious of potential exceptions such as NaNs or infinities, which can trigger flags in the FPSCR register. The instruction operates on double-precision floating-point numbers, so ensure proper alignment and data types to avoid undefined behavior." }, { "mnemonic": "xxpermdi", "architecture": "PowerISA", "full_name": "VSX Permute Doubleword Immediate", "summary": "Selects two doublewords from the four available in source registers XA and XB based on a 2-bit selector.", "syntax": "xxpermdi XT, XA, XB, DM", "encoding": { "format": "XX3-form", "binary_pattern": "T | A | B | 0 | DM | 10 | AX | BX | TX", "hex_opcode": "0xF0000050", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "10", "clean": "10" }, { "raw": "DM", "clean": "DM" } ], "length": "32", "bit_positions": "0:4 | 5:9 | 10:14 | 15 | 16:20 | 21 | 22:26 | 27:30 | 31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Source A" }, { "name": "XB", "desc": "Source B" }, { "name": "DM", "desc": "Selector (2 bits)" } ], "pseudocode": "case DM[1:0]:\n 0: XT[0:63] ← XA[0:63]\n 1: XT[0:63] ← XA[64:127]\n otherwise: XT[0:63] ← ?\ncase DM[3:2]:\n 0: XT[64:127] ← XB[0:63]\n 1: XT[64:127] ← XB[64:127]\n otherwise: XT[64:127] ← ?", "example": "xxpermdi 0, 1, 1, 2", "example_note": "Swap high/low doublewords of vs1.", "extension": "VSX", "description": "Selects two 64-bit doublewords from source registers XA and XB and places them in target register XT. The 2-bit selector DM controls which doubleword is chosen: bits [1:0] of DM select from XA for the high half of XT, and bits [3:2] select from XB for the low half. No condition registers or status flags are affected.", "extended_mnemonics": [ { "mnemonic": "xxspltd", "equivalent_to": "xxpermdi XT,XA,XA,0b00" }, { "mnemonic": "xxmrghd", "equivalent_to": "xxpermdi XT,XA,XB,0b00" }, { "mnemonic": "xxmrgld", "equivalent_to": "xxpermdi XT,XA,XB,0b11" }, { "mnemonic": "xxswapd", "equivalent_to": "xxpermdi XT,XA,XA,0b10" } ], "page_found": "Page 957 - 958", "special_registers": "MSR", "programming_notes": "The xxpermdi instruction is used to permute doublewords from two VSX registers into a third register based on an immediate value. Ensure that the VSX facility is enabled in the MSR register; otherwise, a VSX_Unavailable exception will be raised. The immediate value DM controls which doubleword elements are selected from VSR[XB] for placement in VSR[XT]." }, { "mnemonic": "xsadddp", "architecture": "PowerISA", "full_name": "VSX Scalar Add Double-Precision", "summary": "Adds two double-precision floating-point values from vector scalar registers and stores the result in a target vector scalar register.", "syntax": "xsadddp XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "T | A | B | 32 | AX | BX | TX", "hex_opcode": "0xF0000100", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "32", "clean": "32" } ], "length": "32", "bit_positions": "6:10 | 11:15 | 16:20 | 21:28 | 29 | 30 | 31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Source A" }, { "name": "XB", "desc": "Source B" } ], "pseudocode": "XT[0:63] ← unchanged\nXT[64:127] ← XA[64:127] + XB[64:127]\nFPSCR ← updated based on operation and rounding", "example": "xsadddp 0, 1, 2", "example_note": "Scalar float add using Vector unit.", "extension": "VSX", "special_registers": "FPSCR, VXSNAN, VXISI, OX, UX", "page_found": "Page 558 - 559", "description": "Adds two double-precision floating-point scalar values held in the least-significant 64 bits of VSX registers XA and XB. The result is placed in the least-significant 64 bits of XT; the high 64 bits of XT are unchanged. Floating-point exceptions and FPSCR flags (VX, OX, UX, etc.) are updated according to the result and rounding mode.", "programming_notes": "Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture." }, { "mnemonic": "dsub", "architecture": "PowerISA", "full_name": "Decimal Subtract", "summary": "Subtracts the contents of two DFP registers and places the result in another DFP register.", "syntax": "dsub FRT,FRA,FRB", "encoding": { "format": "X-form", "binary_pattern": "59 | FRT | FRA | FRB | 514 | /", "hex_opcode": "0xEC000404", "visual_parts": [ { "raw": "59", "clean": "59" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "FRA", "clean": "FRA" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "514", "clean": "514" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRA", "desc": "Src A" }, { "name": "FRB", "desc": "Src B" } ], "extension": "Decimal Floating-Point", "description": "The DFP operand in FRB[p] is subtracted from the DFP operand in FRA[p]. The result is rounded to the target-format precision under control of DRN (bits 29:31 of the FPSCR). An appropriate form of the rounded result is selected based on the ideal exponent and is placed in FRT[p]. The ideal exponent is the smaller exponent of the two source operands.", "pseudocode": "if 'dsub' then\n FRT[p] <- (FRA[p]) - (FRB[p])", "special_registers": "FPSCR, FPRF, FR, FI, FX, OX, UX, XX, VXSNAN, VXISI, CR1", "page_found": "Page 240 - 242", "programming_notes": "The dsub instruction performs a decimal subtraction between two DFP operands. Ensure that both operands are properly aligned and formatted according to the target precision specified in the FPSCR register. Be aware of potential rounding errors based on the current rounding mode set in DRN, and check for any exceptions or flags (like VXSNAN) that may indicate invalid operations or special results.", "example": "dsub f1, f2, f3" }, { "mnemonic": "ddiv", "architecture": "PowerISA", "full_name": "Decimal Divide", "summary": "Divides the contents of two decimal floating-point registers and places the result in a target register.", "syntax": "ddiv FRT,FRA,FRB", "encoding": { "format": "X-form", "binary_pattern": "59 | FRT | FRA | FRB | 546 | /", "hex_opcode": "0xEC000444", "visual_parts": [ { "raw": "59", "clean": "59" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "FRA", "clean": "FRA" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "546", "clean": "546" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRA", "desc": "Src A" }, { "name": "FRB", "desc": "Src B" } ], "extension": "Decimal Floating-Point", "description": "The DFP operand in FRA is divided by the DFP operand in FRB. The result is rounded to the target-format precision under control of the DRN (bits 29:31 of the FPSCR). An appropriate form of the rounded result is selected based on the ideal exponent and is placed in FRT.", "pseudocode": "if 'ddiv' then\n FRT <- (FRA) / (FRB)\n if Rc=1 then\n CR1 <- result of comparison", "special_registers": "FPSCR, CR1", "page_found": "Page 242 - 244", "programming_notes": "The ddiv instruction performs a decimal division, rounding the result according to the precision control bits in FPSCR. Ensure that operands are properly aligned and check for division by zero or overflow conditions, which may trigger exceptions. The result can be compared if Rc is set, updating CR1 accordingly.", "example": "ddiv f1, f2, f3" }, { "mnemonic": "dcmpu", "architecture": "PowerISA", "full_name": "Decimal Compare Unordered", "summary": "Compares two DFP operands and sets the CR field to indicate the result.", "syntax": "dcmpu BF, FRA, FRB", "encoding": { "format": "X-form", "binary_pattern": "63 | BF | FRA | FRB | 0 | 0 | 0 | 0", "hex_opcode": "0xEC000504", "visual_parts": [ { "raw": "59", "clean": "59" }, { "raw": "BF", "clean": "BF" }, { "raw": "/", "clean": "/" }, { "raw": "FRA", "clean": "FRA" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "642", "clean": "642" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:29 | 30 | 31" }, "operands": [ { "name": "BF", "desc": "CR Field" }, { "name": "FRA", "desc": "Src A" }, { "name": "FRB", "desc": "Src B" } ], "extension": "Decimal Floating-Point", "description": "Compares two decimal floating-point numbers and updates the specified condition register field. The comparison treats quiet NaNs as unordered (unlike ordered compare). The result sets the Less Than, Greater Than, Equal, or Unordered bits in the target CR field. No other status flags are affected.", "pseudocode": "if FRA is NaN or FRB is NaN then\n CR[BF] ← 0b0001 (Unordered)\nelse if FRA < FRB then\n CR[BF] ← 0b1000 (Less Than)\nelse if FRA > FRB then\n CR[BF] ← 0b0100 (Greater Than)\nelse\n CR[BF] ← 0b0010 (Equal)", "special_registers": "CR, FPSCR", "page_found": "Page 243 - 244", "programming_notes": "The dcmpu instruction is used to compare two decimal floating-point numbers. It sets the condition register field BF based on the comparison result, which can be less than (FL), greater than (FG), equal to (FE), or unordered (FU) if either operand is NaN. Ensure that both operands are properly aligned and valid DFP values to avoid undefined behavior.", "example": "dcmpu cr0, f2, f3" }, { "mnemonic": "dcmpo", "architecture": "PowerISA", "full_name": "Decimal Compare Ordered", "summary": "Compares two decimal floating-point operands and updates the condition register.", "syntax": "dcmpo BF, FRA, FRB", "encoding": { "format": "X-form", "binary_pattern": "59 | BF | / | FRA | FRB | 130 | /", "hex_opcode": "0xEC000104", "visual_parts": [ { "raw": "59", "clean": "59" }, { "raw": "BF", "clean": "BF" }, { "raw": "/", "clean": "/" }, { "raw": "FRA", "clean": "FRA" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "130", "clean": "130" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:8 | 9:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "BF", "desc": "CR Field" }, { "name": "FRA", "desc": "Src A" }, { "name": "FRB", "desc": "Src B" } ], "extension": "Decimal Floating-Point", "description": "The DFP operand in FRA is compared to the DFP operand in FRB. The result of the compare is placed into CR field BF and the FPCC.", "special_registers": "CR, FPSCR", "programming_notes": "dcmpo[q] are treated as Floating-Point instructions in terms of resource availability.", "page_found": "Page 244 - 246", "pseudocode": "f1 <- DFP_operation(f2, f3)", "example": "dcmpo cr0, f2, f3" }, { "mnemonic": "dctdp", "architecture": "PowerISA", "full_name": "Decimal Convert To DFP Long", "summary": "Converts DFP Short (32-bit compressed) to DFP Long (64-bit).", "syntax": "dctdp FRT, FRB", "encoding": { "format": "X-form", "binary_pattern": "59 | FRT | / | FRB | 258 | Rc", "hex_opcode": "0xEC000204", "visual_parts": [ { "raw": "59", "clean": "59" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "258", "clean": "258" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" } ], "extension": "Decimal Floating-Point", "description": "The DFP short operand in bits 32:63 of FRB is converted to DFP long format and the converted result is placed into FRT. The sign of the result is the same as the sign of the source operand. The ideal exponent is the exponent of the source operand.", "special_registers": "FPSCR (FPRF, FR, FI), CR (CR1)", "programming_notes": "Note that DFP short format is a storage-only format. Therefore, conversion of a short SNaN to long format will not cause an exception and the SNaN is preserved. Subsequent operation on that SNaN in long format will cause an exception.", "page_found": "Page 260 - 262", "pseudocode": "FRT <- ConvertToDFPLong(FRB)", "example": "dctdp f1, f3" }, { "mnemonic": "drsp", "architecture": "PowerISA", "full_name": "Decimal Round To DFP Short", "summary": "Rounds DFP Long (64-bit) to DFP Short (32-bit compressed).", "syntax": "drsp FRT,FRB", "encoding": { "format": "X-form", "binary_pattern": "59 | FRT | 0 | FRB | 770 | /", "hex_opcode": "0xEC000604", "visual_parts": [ { "raw": "59", "clean": "59" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "770", "clean": "770" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" } ], "extension": "Decimal Floating-Point", "description": "The DFP long operand in FRB is converted and rounded to DFP short format. The DFP short value is extended on the left with zeros to form a 64-bit entity and placed into FRT. The sign of the result is the same as the sign of the source operand.", "pseudocode": "if 'drsp' then\n FRT <- (FRB) rounded to DFP short format\n if Rc=1 then\n CR0, CR1 <- updated based on result", "special_registers": "FPSCR, CR0, CR1", "programming_notes": "Note that DFP short format is a storage-only format. Therefore, conversion of a long SNaN to short for mat will not cause an exception.", "page_found": "Page 261 - 262", "example": "drsp f1, f3" }, { "mnemonic": "dcffix", "architecture": "PowerISA", "full_name": "Decimal Convert From Fixed", "summary": "Converts a 64-bit integer to DFP.", "syntax": "dcffix FRT, FRB", "encoding": { "format": "X-form", "binary_pattern": "59 | FRT | 0 | FRB | 802 | /", "hex_opcode": "0xEC000644", "visual_parts": [ { "raw": "59", "clean": "59" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "802", "clean": "802" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" }, { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "RB", "desc": "Source General Purpose Register" } ], "extension": "Decimal Floating-Point", "page_found": "Page 1463 - 1464", "special_registers": "FPSCR", "description": "Converts a 64-bit signed integer from FRB to a decimal floating-point value and places it in FRT. The integer is interpreted as a two's-complement 64-bit value. The result is an exact representation in the decimal floating-point format. FPSCR is updated if the integer is out of range for DFP.", "pseudocode": "integer_value ← FRB[0:63] (signed)\nFRT ← convert_to_DFP(integer_value)\nFPSCR ← updated based on conversion result", "example": "dcffix f1, f3" }, { "mnemonic": "dctfix", "architecture": "PowerISA", "full_name": "Decimal Convert To Fixed", "summary": "Converts a decimal floating-point number to a fixed-point integer.", "syntax": "dctfix FRT,FRB", "encoding": { "format": "X-form", "binary_pattern": "59 | FRT | / | FRB | 290 | Rc", "hex_opcode": "0xEC000244", "visual_parts": [ { "raw": "59", "clean": "59" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "290", "clean": "290" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" } ], "extension": "Decimal Floating-Point", "description": "The DFP operand in FRB is rounded to an integer value and placed into FRT in the 64-bit signed binary integer format. The sign of the result is the same as the sign of the source operand, except when the source operand is a NaN or a zero.", "pseudocode": "if 'dctfix' then\n FRT <- round(FRB)\nelse if 'dctfix.' then\n FRT <- round(FRB)\n CR1 <- result of comparison", "special_registers": "FPSCR (FPRF, FR, FI, FX, VXSNAN, VXCVI, XX), CR1 (if Rc=1)", "page_found": "Page 270 - 272", "programming_notes": "It is recommended that software pre-round the operand to a floating-point integral using drintx[q] or drintn[q] if a rounding mode other than the current rounding mode specified by DRN is needed.", "example": "dctfix f1, f3" }, { "mnemonic": "denbcd", "architecture": "PowerISA", "full_name": "Decimal Encode BCD", "summary": "Encodes a DFP number into BCD format.", "syntax": "denbcd FRT, FRB, S", "encoding": { "format": "X-form", "binary_pattern": "59 | FRT | S | FRB | 834 | /", "hex_opcode": "0xEC000684", "visual_parts": [ { "raw": "59", "clean": "59" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "S", "clean": "S" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "834", "clean": "834" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" }, { "name": "S", "desc": "Sign Control" } ], "extension": "Decimal Floating-Point", "description": "Encodes a decimal floating-point number in FRB into Binary Coded Decimal (BCD) format and places the result in FRT. The sign control field S determines how the sign is encoded. This instruction handles conversion of the coefficient and exponent into BCD representation. FPSCR is updated based on invalid operations.", "pseudocode": "dfp_value ← FRB\nsign ← extract_sign(dfp_value)\ncoefficient ← extract_coefficient(dfp_value)\nexponent ← extract_exponent(dfp_value)\nbcd_result ← encode_to_bcd(sign, coefficient, exponent, S)\nFRT ← bcd_result\nFPSCR ← updated based on encoding result", "special_registers": "FPSCR", "programming_notes": "The denbcd instruction is used to convert a Binary-Coded Decimal (BCD) value into Data-Packed Decimal (DPD) format. Ensure that the input BCD value in FRB is correctly formatted and aligned as required by the instruction. This operation does not raise exceptions for valid inputs but may require careful handling of special cases like overflow or invalid data.", "example": "denbcd f1, f3, 0" }, { "mnemonic": "ddedpd", "architecture": "PowerISA", "full_name": "Decode DPD To BCD (Single Precision)", "summary": "Converts a portion of the significand of a DFP operand to a signed or unsigned BCD number.", "syntax": "ddedpd SP,FRT,FRB", "encoding": { "format": "X-form", "binary_pattern": "59 | FRT | SP | / | FRB | 322 | Rc", "hex_opcode": "0xEC000284", "visual_parts": [ { "raw": "59", "clean": "59" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "SP", "clean": "SP" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "322", "clean": "322" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:12 | 13:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" }, { "name": "SP", "desc": "Sign Control" } ], "extension": "Decimal Floating-Point", "description": "The rightmost 16 digits of the significand (32 digits for ddedpdq) is converted to an unsigned BCD number and the result is placed into FRT[p].", "pseudocode": "if 'ddedpd' then\n if SP = 0 then\n FRT <- unsigned BCD conversion of rightmost 16 digits of FRB[p]\n else if SP = 1 then\n FRT <- signed BCD conversion of rightmost 15 digits of FRB[p] with the same sign as FRB[p]\n end if", "special_registers": "FPSCR, (FPRF, FX, VXCVI), FPSCR, (FR, set, to, 0), CR1, (if, Rc=1), CR0", "page_found": "Page 264 - 266", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "ddedpd 0, f1, f3" }, { "mnemonic": "diex", "architecture": "PowerISA", "full_name": "Decimal Insert Exponent", "summary": "Combines a sign/coefficient from FRA and exponent from FRB.", "syntax": "diex FRT, FRA, FRB", "encoding": { "format": "X-form", "binary_pattern": "59 | FRT | FRA | FRB | 866 | /", "hex_opcode": "0xEC0006C4", "visual_parts": [ { "raw": "59", "clean": "59" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "FRA", "clean": "FRA" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "866", "clean": "866" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRA", "desc": "Coeff Source" }, { "name": "FRB", "desc": "Exp Source" } ], "extension": "Decimal Floating-Point", "description": "Combines a sign and coefficient from FRA with an exponent from FRB to form a decimal floating-point result in FRT. FRA provides the mantissa/coefficient; FRB provides the exponent. The instruction reconstructs a DFP value from its components. FPSCR is updated if the result is invalid or out of range.", "pseudocode": "coefficient ← extract_mantissa(FRA)\nSign ← extract_sign(FRA)\nexponent ← extract_exponent_field(FRB)\nFRT ← compose_DFP(Sign, coefficient, exponent)\nFPSCR ← updated based on composition result", "page_found": "Page 255", "special_registers": "FPSCR", "programming_notes": "The diex instruction is used to adjust the exponent of a decimal floating-point number by inserting the exponent from one operand (FRA) into another (FRB). Ensure that both operands are properly aligned and in the correct format to avoid exceptions. This operation requires FPSCR to manage rounding modes and exception flags.", "example": "diex f1, f2, f3" }, { "mnemonic": "dxex", "architecture": "PowerISA", "full_name": "Decimal Extract Exponent", "summary": "Extracts the biased exponent of a DFP operand in FRB and places it into FRT.", "syntax": "dxex FRT,FRB", "encoding": { "format": "X-form", "binary_pattern": "59 | FRT | 0 | FRB | 354 | /", "hex_opcode": "0xEC0002C4", "visual_parts": [ { "raw": "59", "clean": "59" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "354", "clean": "354" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" } ], "extension": "Decimal Floating-Point", "description": "The biased exponent of the operand in FRB is extracted and placed into FRT in the 64-bit signed binary integer format. Special codes are returned for infinity, QNaN, or SNaN operands.", "pseudocode": "if 'dxex' then\n a <- biased exponent of FRB[p]\n if a > MBE1 then\n FRT[p] <- QNaNSNaN\n else if 0 ≤a ≤MBE then\n FRT[p] <- Finite number with biased exponent a\n else if a = -1 then\n FRT[p] <- Infinity\n else if a = -2 then\n FRT[p] <- QNaN\n else if a = -3 then\n FRT[p] <- SNaN\n else if a < -3 then\n FRT[p] <- QNaN", "special_registers": "CR1, (if, Rc=1), FPSCR", "programming_notes": "The exponent bias value is 101 for DFP Short, 398 for DFP Long, and 6176 for DFP Extended.", "page_found": "Page 266 - 268", "example": "dxex f1, f3" }, { "mnemonic": "dscli", "architecture": "PowerISA", "full_name": "Decimal Shift Coefficient Left Immediate", "summary": "Shifts the significand of a DFP operand left by a specified number of digits.", "syntax": "dscli FRT,FRA,SH", "encoding": { "format": "Z23-form", "binary_pattern": "59 | FRT | FRA | SH | 66 | /", "hex_opcode": "0xEC000084", "visual_parts": [ { "raw": "59", "clean": "59" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "FRA", "clean": "FRA" }, { "raw": "SH", "clean": "SH" }, { "raw": "66", "clean": "66" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRA", "desc": "Source" }, { "name": "SH", "desc": "Shift Amount" } ], "extension": "Decimal Floating-Point", "description": "The significand of the DFP operand in FRA is shifted left SH digits. For NaN or infinity, all significand digits are in the trailing significand field. SH is a 6-bit unsigned binary integer. Digits shifted out of the leftmost digit are lost. Zeros are supplied to the vacated positions on the right. The result is placed into FRT. The sign of the result is the same as the sign of the source operand in FRA.", "pseudocode": "if 'dscli' then\n FRT <- (FRA) << SH", "special_registers": "CR1, (if, Rc=1), FPSCR", "page_found": "Page 268 - 270", "programming_notes": "The dscli instruction shifts the significand of a decimal floating-point number to the left by a specified number of digits. Ensure that the shift amount (SH) is within the 0-63 range, as it's a 6-bit unsigned integer. This operation does not affect the sign or exponent of the operand. If SH is greater than the precision of the significand, leading zeros will be introduced to fill the vacated positions on the right.", "example": "dscli f1, f2, 3" }, { "mnemonic": "dsri", "architecture": "PowerISA", "full_name": "Decimal Shift Coefficient Right Immediate", "summary": "Shifts the coefficient of a DFP number right.", "syntax": "dsri FRT, FRA, SH", "encoding": { "format": "Z23-form", "binary_pattern": "59 | FRT | FRA | SH | 98 | Rc", "hex_opcode": "0xEC0000C4", "visual_parts": [ { "raw": "59", "clean": "59" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "FRA", "clean": "FRA" }, { "raw": "SH", "clean": "SH" }, { "raw": "98", "clean": "98" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRA", "desc": "Source" }, { "name": "SH", "desc": "Shift Amount" } ], "extension": "Decimal Floating-Point", "special_registers": "FPSCR", "description": "Shifts the coefficient of a 64-bit Decimal Floating-Point number right by an immediate amount (0-63 places), with zeros shifted in from the left. The exponent remains unchanged. This instruction is part of the Decimal Floating-Point extension and does not affect condition registers unless Rc=1.", "pseudocode": "coefficient ← coefficient >> SH\nFRT ← DFP_construct(sign, exponent, coefficient)", "example": "dsri f1, f2, 3" }, { "mnemonic": "xssubqp", "architecture": "PowerISA", "full_name": "VSX Scalar Subtract Quad-Precision", "summary": "Subtracts the contents of two quad-precision floating-point registers and handles special cases like NaNs.", "syntax": "xssubqp VRT,VRA,VRB", "encoding": { "format": "X-form", "binary_pattern": "63 | FRT | FRA | FRB | 514 | Rc", "hex_opcode": "0xFC000408", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "516", "clean": "516" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector-Scalar Register" }, { "name": "VRA", "desc": "Source Vector-Scalar Register" }, { "name": "VRB", "desc": "Source Vector-Scalar Register" } ], "extension": "VSX", "description": "Subtracts the quad-precision floating-point operand in VSR VRB from VSR VRA and stores the result in VSR VRT, handling infinities, NaNs, and denormalised numbers according to IEEE 754 semantics. This VSX instruction may update FPSCR exception flags and the result sign. The 'o' suffix variant enables underflow/overflow exception.", "pseudocode": "FRT ← FRA - FRB\nFPSCR ← updated with exception flags (XX, ZX, UX, OX, VXISI, VXSNAN, etc.)", "special_registers": "FPSCR FPRF FR FI FX VXSNAN VXISI OX UX XX", "page_found": "Page 679 - 680", "programming_notes": "The xssubqp instruction is used for subtracting quad-precision floating-point numbers. Ensure that the VSX feature is enabled in the MSR register to avoid exceptions. Handle special cases like NaNs and infinities by checking the FPSCR flags after execution. The result is rounded according to the rounding mode specified in FPSCR.RN.", "example": "xssubqp v1, v2, v3" }, { "mnemonic": "xsdivqp", "architecture": "PowerISA", "full_name": "VSX Scalar Divide Quad-Precision", "summary": "Divides the contents of two quad-precision floating-point registers and places the result in another register.", "syntax": "xsdivqp vD, vA, vB", "encoding": { "format": "X-form", "binary_pattern": "63 | FRT | FRA | FRB | 546 | Rc", "hex_opcode": "0xFC000448", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "548", "clean": "548" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector-Specific Register" }, { "name": "VRA", "desc": "Source Vector-Specific Register" }, { "name": "VRB", "desc": "Source Vector-Specific Register" } ], "extension": "VSX", "description": "Divides the quad-precision floating-point operand in VSR vA by the quad-precision operand in VSR vB, placing the quotient in VSR vD, with IEEE 754 rounding and exception handling. This VSX instruction updates FPSCR flags including division-by-zero, invalid operation, and underflow/overflow conditions.", "pseudocode": "vD ← vA ÷ vB\nFPSCR ← updated with exception flags (ZX, XX, UX, OX, VXSNAN, VXIDI, VXDZ, etc.)", "special_registers": "FPSCR, VXSNAN, VXIDI, VXZDZ, OX, UX, ZX, XX", "page_found": "Page 661 - 662", "programming_notes": "The xsdivqp instruction is used for dividing two quad-precision floating-point numbers. Be cautious of division by zero, which results in infinity or quiet NaN, and set appropriate flags. Handle infinities and zeros carefully as they can lead to special cases like zero or infinity in the result. Ensure that operands are correctly aligned and consider performance implications when using this instruction in loops.", "example": "xsdivqp vd, va, vb" }, { "mnemonic": "xssqrtqp", "architecture": "PowerISA", "full_name": "VSX Scalar Square Root Quad-Precision", "summary": "Computes the square root of a quad-precision floating-point value with unbounded significand precision and exponent range.", "syntax": "xssqrtqp vD, vB", "encoding": { "format": "X-form", "binary_pattern": "63 | FRT | / | FRB | 674 | Rc", "hex_opcode": "0xFC1B0648", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "676", "clean": "676" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "VRT", "desc": "Target Vector-Specific Register" }, { "name": "VRB", "desc": "Source Vector-Specific Register" }, { "name": "VRA", "desc": "Target Vector-Specific Register" } ], "extension": "VSX", "description": "The normalized square root of src is produced with unbounded significand precision and exponent range. If RO=1, the rounding mode is Round to Odd; otherwise, it is specified by RN.", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nreset_xflags()\nsrc ← bfp_CONVERT_FROM_BFP128(VSR[VRB+32])\nv ← bfp_SQUARE_ROOT(src)\nrnd ← bfp_ROUND_TO_BFP128(RO, FPSCR.RN, v)\nresult ← bfp128_CONVERT_FROM_BFP(rnd)\nif vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\nif vxsqrt_flag=1 then SetFX(FPSCR.VXSQRT)\nif xx_flag=1 then SetFX(FPSCR.XX)\nvx_flag ← vxsnan_flag | vxsqrt_flag\nvex_flag ← FPSCR.VE & vx_flag\nif vex_flag=0 then do\n VSR[VRT+32] ← result\n FPSCR.FPRF ← fprf_CLASS_BFP128(result)\nend\nFPSCR.FR ← (vx_flag=0) & inc_flag\nFPSCR.FI ← (vx_flag=0) & xx_flag", "special_registers": "FPSCR, VSR[VRT+32]", "page_found": "Page 673 - 674", "programming_notes": "The xssqrtqp instruction computes the square root of a quad-precision floating-point number. Ensure that VSX is enabled in the MSR register to avoid exceptions. Be cautious with rounding modes; setting RO=1 enables Round to Odd, which may differ from standard rounding behaviors. This instruction handles special cases like NaNs and infinities, updating the FPSCR accordingly.", "example": "xssqrtqp vd, vb" }, { "mnemonic": "xscmpuqp", "architecture": "PowerISA", "full_name": "VSX Scalar Compare Unordered Quad-Precision", "summary": "Compares two quad-precision floating-point values and updates the condition register.", "syntax": "xscmpuqp BF, vA, vB", "encoding": { "format": "X-form", "binary_pattern": "63 | BF | / | vA | vB | 644 | /", "hex_opcode": "0xFC000508", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "BF", "clean": "BF" }, { "raw": "/", "clean": "/" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "644", "clean": "644" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:8 | 9:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "BF", "desc": "CR Field" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRA", "desc": "Vector Register A" }, { "name": "VRB", "desc": "Vector Register B" } ], "extension": "VSX", "description": "The instruction compares the contents of VSR[VRA+32] (src1) and VSR[VRB+32] (src2) in quad-precision format. It sets bits in the CR field BF to indicate the result of the comparison.", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nreset_xflags()\nsrc1 ←bfp_CONVERT_FROM_BFP128(VSR[VRA+32])\nsrc2 ←bfp_CONVERT_FROM_BFP128(VSR[VRB+32])\nvxsnan_flag ←src1.class.SNaN | src2.class.SNaN\nif vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\nCR.bit[4×BF+32] ←FPSCR.FL ←src1 < src2\nCR.bit[4×BF+33] ←FPSCR.FG ←src1 > src2\nCR.bit[4×BF+34] ←FPSCR.FE ←src1 = src2\nCR.bit[4×BF+35] ←FPSCR.FU ←src1.class.SNaN | src1.class.QNaN | src2.class.SNaN | src2.class.QNaN", "special_registers": "CR, FPSCR", "page_found": "Page 783 - 784", "programming_notes": "This instruction is used for comparing two quad-precision floating-point numbers. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. Be cautious with NaN values, as they can trigger VXSNAN and FU flags in the FPSCR register. The comparison results are stored in the CR register bits corresponding to BF.", "example": "xscmpuqp cr0, va, vb" }, { "mnemonic": "xscmpopoqp", "architecture": "PowerISA", "full_name": "VSX Scalar Compare Ordered Quad-Precision", "summary": "Compares Quad floats (Signaling on NaN).", "syntax": "xscmpopoqp BF, vA, vB", "encoding": { "format": "X-form", "binary_pattern": "63 | BF | / | vA | vB | 132 | /", "hex_opcode": "0xFC000108", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "BF", "clean": "BF" }, { "raw": "/", "clean": "/" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "132", "clean": "132" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:8 | 9:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "BF", "desc": "CR Field" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" } ], "extension": "VSX", "description": "Compares two quad-precision floating-point values in VSRs vA and vB, signaling (raising exception) if either operand is a quiet NaN, and stores the comparison result (Less Than, Greater Than, Equal, or Unordered) in condition register field BF. The FPSCR VE flag may be set on NaN detection.", "pseudocode": "if (vA is NaN) or (vB is NaN) then FPSCR[VXSNAN] ← 1\nif vA < vB then CR[BF] ← 0b100\nelse if vA > vB then CR[BF] ← 0b010\nelse if vA = vB then CR[BF] ← 0b001\nelse CR[BF] ← 0b011 (unordered)", "example": "xscmpopoqp cr0, va, vb" }, { "mnemonic": "xsnegqp", "architecture": "PowerISA", "full_name": "VSX Scalar Negate Quad-Precision", "summary": "Negates a 128-bit Quad float.", "syntax": "xsnegqp vD, vB", "encoding": { "format": "X-form", "binary_pattern": "63 | vD | 0 | vB | 804 | /", "hex_opcode": "0xFC100648", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "804", "clean": "804" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" } ], "extension": "VSX", "description": "Negates the sign bit of a 128-bit quad-precision floating-point value in VSR vB and stores the result in VSR vD. This is a simple bit-flip operation that does not affect FPSCR exception flags or condition registers.", "pseudocode": "vD ← vB with sign bit flipped", "page_found": "Page 646", "special_registers": "MSR", "programming_notes": "This instruction is used to negate a quad-precision floating-point value. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking and setting the appropriate bit in the MSR register. The operation affects two consecutive doublewords, so ensure proper alignment of the source register.", "example": "xsnegqp vd, vb" }, { "mnemonic": "xsabsqp", "architecture": "PowerISA", "full_name": "VSX Scalar Absolute Quad-Precision", "summary": "Computes the absolute value of a quad-precision floating-point number.", "syntax": "xsabsqp vD, vB", "encoding": { "format": "X-form", "binary_pattern": "111111 | vD | 00000 | vB | 11001 | 00100 | Rc", "hex_opcode": "0xFC000648", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "772", "clean": "772" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:8 | 9:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "RT", "desc": "Target Vector Register" }, { "name": "RA", "desc": "Source Vector Register" } ], "extension": "VSX", "pseudocode": "vD ← vB with sign bit cleared", "page_found": "Page 1393 - 1394", "description": "Computes the absolute value of a 128-bit quad-precision floating-point number in VSR vB by clearing the sign bit and stores the result in VSR vD. This VSX instruction does not modify FPSCR exception flags or condition registers.", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "xsabsqp vd, vb" }, { "mnemonic": "xxinsertw", "architecture": "PowerISA", "full_name": "VSX Vector Insert Word", "summary": "Inserts a 32-bit word from a GPR into a specific element of a VSR.", "syntax": "xxinsertw XT, RB, UIM", "encoding": { "format": "XX2-form", "binary_pattern": "60 | XT | UIM | RB | 181", "hex_opcode": "0xF00002D4", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "UIM", "clean": "UIM" }, { "raw": "RB", "clean": "RB" }, { "raw": "181", "clean": "181" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "XT", "desc": "Target VSR" }, { "name": "RB", "desc": "Source GPR" }, { "name": "UIM", "desc": "Element Index" } ], "extension": "VSX", "description": "Inserts a 32-bit word from GPR RB into a specified 32-bit element of VSR XT, with the element index selected by UIM[2:0]. This is a VSX instruction that operates on vector data and does not affect condition registers or status fields.", "pseudocode": "element_index ← UIM[2:0]\nXT[32*element_index : 32*element_index+31] ← RB[32:63]", "page_found": "Page 953", "special_registers": "MSR", "programming_notes": "The xxinsertw instruction is used to insert a word from one vector register into another at a specified byte offset. Ensure that the UIM (Upper Immediate) field does not exceed 12 to avoid undefined behavior. This instruction requires VSX (Vector Scalar Extensions) to be enabled in the MSR.VSX bit; otherwise, it will raise an exception.", "example": "xxinsertw vs1, r5, uim" }, { "mnemonic": "xxextractuw", "architecture": "PowerISA", "full_name": "VSX Vector Extract Unsigned Word", "summary": "Extracts an unsigned word from a vector register and places it into another vector register.", "syntax": "xxextractuw RT, XS, UIM", "encoding": { "format": "XX2-form", "binary_pattern": "60 | XS | UIM | RT | 165", "hex_opcode": "0xF0000294", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XS", "clean": "XS" }, { "raw": "UIM", "clean": "UIM" }, { "raw": "RT", "clean": "RT" }, { "raw": "165", "clean": "165" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "RT", "desc": "Target GPR" }, { "name": "XS", "desc": "Source VSR" }, { "name": "UIM", "desc": "Element Index" }, { "name": "XT", "desc": "Target Vector Register" }, { "name": "XB", "desc": "Source Vector Register" } ], "extension": "VSX", "description": "The instruction extracts the contents of byte elements UIM:UIM+3 from VSR[XB] and places them into word element 1 of VSR[XT]. The remaining byte elements of VSR[XT] are not modified, and the remaining word elements of VSR[XT] are set to 0.", "pseudocode": "if MSR.VSX=0 then\n VSX_Unavailable()\nsrc ←VSR[32×BX+B].byte[UIM:UIM+3]\nVSR[32×TX+T].dword[0] ←EXTZ64(src)\nVSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000", "page_found": "Page 952 - 953", "special_registers": "MSR", "programming_notes": "This instruction is useful for extracting a specific 4-byte segment from one vector register and placing it into another, while zeroing out the rest of the destination register. Ensure that VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. Be cautious with byte alignment; UIM must be a multiple of 4 to correctly extract a word. This instruction operates at the user privilege level and does not generate any exceptions beyond those related to VSX availability.", "example": "xxextractuw r3, vs1, uim" }, { "mnemonic": "xxspltw", "architecture": "PowerISA", "full_name": "VSX Vector Splat Word", "summary": "Replicates a word element from one vector register into all elements of another vector register.", "syntax": "xxspltw XT, XS, UIM", "encoding": { "format": "XX2-form", "binary_pattern": "60 | XT | UIM | XS | 164", "hex_opcode": "0xF0000290", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "UIM", "clean": "UIM" }, { "raw": "XS", "clean": "XS" }, { "raw": "164", "clean": "164" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XS", "desc": "Source" }, { "name": "UIM", "desc": "Index" }, { "name": "XB", "desc": "Source Vector Register" } ], "extension": "VSX", "description": "The contents of the specified word element UIM in VSR[XB] are replicated into each word element of VSR[XT].", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\n\nXT <- XB.word[UIM]\nVSR[32×TX+T].word[0] ← XT\nVSR[32×TX+T].word[1] ← XT\nVSR[32×TX+T].word[2] ← XT\nVSR[32×TX+T].word[3] ← XT", "page_found": "Page 956 - 957", "special_registers": "MSR", "programming_notes": "The xxspltw instruction is commonly used to replicate a word element from one vector register into all elements of another vector register. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register; otherwise, an exception will be raised. This instruction does not have specific alignment requirements and operates at user privilege level.", "example": "xxspltw vs1, vs1, uim" }, { "mnemonic": "lmw", "architecture": "PowerISA", "full_name": "Load Multiple Word", "summary": "Loads words from memory into registers RT through R31 (Context Switch).", "syntax": "lmw RT, D(RA)", "encoding": { "format": "D-form", "binary_pattern": "46 | RT | RA | D", "hex_opcode": "0xB8000000", "visual_parts": [ { "raw": "46", "clean": "46" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "D", "clean": "D" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "operands": [ { "name": "RT", "desc": "Start Register" }, { "name": "D", "desc": "Displacement" }, { "name": "RA", "desc": "Base" } ], "extension": "Base", "description": "Loads a sequence of words from memory starting at address (RA + D) into GPRs RT through R31, incrementing the address by 4 bytes for each register. This instruction is part of the Base ISA and does not update condition registers; it may be used for context switching.", "pseudocode": "if RA = 0 then EA ← 0 + D else EA ← RA + D\nfor i ← 0 to (31 - RT) do\n GPRC[RT+i] ← MEM[EA+4*i : EA+4*i+31]\nend for", "programming_notes": "This instruction is not supported in Little-Endian mode. If it is executed in Little-Endian mode, the system alignment error handler is invoked.", "page_found": "Page 103 - 104", "example": "lmw r3, 0(r4)" }, { "mnemonic": "stmw", "architecture": "PowerISA", "full_name": "Store Multiple Word", "summary": "Stores words from registers RT through R31 to memory (Context Switch).", "syntax": "stmw RT, D(RA)", "encoding": { "format": "D-form", "binary_pattern": "47 | RT | RA | D", "hex_opcode": "0xBC000000", "visual_parts": [ { "raw": "47", "clean": "47" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "D", "clean": "D" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Start Register" }, { "name": "D", "desc": "Displacement" }, { "name": "RA", "desc": "Base" } ], "extension": "Base", "description": "Stores a sequence of words from GPRs RT through R31 to memory starting at address (RA + D), incrementing the address by 4 bytes for each register. This instruction is part of the Base ISA and does not update condition registers; it is commonly used for context switching.", "pseudocode": "if RA = 0 then EA ← 0 + D else EA ← RA + D\nfor i ← 0 to (31 - RT) do\n MEM[EA+4*i : EA+4*i+31] ← GPRC[RT+i]\nend for", "page_found": "Page 104", "programming_notes": "Loads (or stores) a sequence of GPRs from consecutive word-aligned memory locations. Not pipelined on most implementations; for bulk data movement consider using vector or floating-point load/store multiples instead.", "example": "stmw r3, 0(r4)" }, { "mnemonic": "lswi", "architecture": "PowerISA", "full_name": "Load String Word Immediate", "summary": "Loads a sequence of bytes from memory into general-purpose registers.", "syntax": "lswi RT, RA, NB", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | RA | NB | 597 | /", "hex_opcode": "0x7C0004AA", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "NB", "clean": "NB" }, { "raw": "597", "clean": "597" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RT", "desc": "Start Register" }, { "name": "RA", "desc": "Base" }, { "name": "NB", "desc": "Byte Count" } ], "extension": "Base", "description": "Loads NB bytes from memory starting at address RA into a sequence of GPRs beginning at RT, filling registers left-to-right and wrapping from R31 back to R0 if necessary. This Base ISA instruction does not affect condition registers and provides a byte-oriented string load capability.", "pseudocode": "EA ← RA\nreg ← RT\nbyte_index ← 0\nfor i ← 0 to (NB - 1) do\n GPRC[reg][(32 - 8*(byte_index+1)) : (31 - 8*byte_index)] ← MEM[EA+i : EA+i+7]\n byte_index ← byte_index + 1\n if byte_index = 4 then\n byte_index ← 0\n reg ← (reg + 1) mod 32\n end if\nend for", "programming_notes": "This instruction is not supported in Little-Endian mode. If it is executed in Little-Endian mode, the system alignment error handler is invoked.", "page_found": "Page 104 - 106", "example": "lswi r3, r4, 4" }, { "mnemonic": "stswi", "architecture": "PowerISA", "full_name": "Store String Word Immediate", "summary": "Stores a string of words from general-purpose registers to memory, starting at the address in RA and using an immediate byte count.", "syntax": "stswi RT, RA, NB", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | RA | NB | 725 | /", "hex_opcode": "0x7C0005AA", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "NB", "clean": "NB" }, { "raw": "725", "clean": "725" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RT", "desc": "Start Register" }, { "name": "RA", "desc": "Base" }, { "name": "NB", "desc": "Byte Count" }, { "name": "RS", "desc": "Source General Purpose Register" } ], "extension": "Base", "description": "Stores NB bytes from a sequence of GPRs beginning at RS to memory starting at address RA, extracting bytes left-to-right and wrapping from R31 back to R0 if necessary. This Base ISA instruction does not affect condition registers and provides a byte-oriented string store capability.", "pseudocode": "EA ← RA\nreg ← RS\nbyte_index ← 0\nfor i ← 0 to (NB - 1) do\n MEM[EA+i : EA+i+7] ← GPRC[reg][(32 - 8*(byte_index+1)) : (31 - 8*byte_index)]\n byte_index ← byte_index + 1\n if byte_index = 4 then\n byte_index ← 0\n reg ← (reg + 1) mod 32\n end if\nend for", "programming_notes": "This instruction is not supported in Little-Endian mode. If it is executed in Little-Endian mode and NB > 0, the system alignment error handler is invoked.", "page_found": "Page 106 - 108", "example": "stswi r3, r4, 4" }, { "mnemonic": "slbia", "architecture": "PowerISA", "full_name": "Segment Lookaside Buffer Invalidate All", "summary": "Invalidates all Segment Lookaside Buffer entries (OS Management).", "syntax": "slbia IH", "encoding": { "format": "X-form", "binary_pattern": "111111 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000", "hex_opcode": "0x7C0003E4", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "IH", "clean": "IH" }, { "raw": "498", "clean": "498" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:8 | 9 | 10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "IH", "desc": "Hint" } ], "extension": "Privileged", "description": "Invalidates all Segment Lookaside Buffer (SLB) entries, optionally using an invalidation hint. This is a privileged instruction that flushes virtual-to-real address translation caches and is typically used during context switches or address-space changes.", "pseudocode": "for each SLB entry do\n invalidate entry\nend for", "programming_notes": "slbia does not affect SLBs on other threads.\nIf slbia is executed when instruction address translation is enabled, software can ensure that attempting to fetch the instruction following the slbia does not cause an Instruction Segment interrupt by placing the slbia and the subsequent instruction in the effective segment mapped by SLB entry 0.", "extended_mnemonics": [ { "mnemonic": "slbia", "equivalent_to": "slbia 0" } ], "page_found": "Page 1199 - 1200", "special_registers": "MSR", "example": "slbia" }, { "mnemonic": "slbmte", "architecture": "PowerISA", "full_name": "SLB Move To Entry", "summary": "Writes an SLB entry (Mapping effective to virtual address).", "syntax": "slbmte RS, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | / | RB | 402 | /", "hex_opcode": "0x7C000324", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "/", "clean": "/" }, { "raw": "RB", "clean": "RB" }, { "raw": "402", "clean": "402" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RS", "desc": "Source VSID" }, { "name": "RB", "desc": "Effective Addr" } ], "extension": "Privileged", "description": "Writes an entry to the Segment Lookaside Buffer, mapping an effective segment address (from RB) to a virtual segment ID and protection bits (from RS). This is a privileged 64-bit instruction that modifies virtual address translation state.", "special_registers": "MSR", "programming_notes": "The slbmte instruction is used to install temporary ESID-to-VSID translations in the SLB for a specific hardware thread. These entries are thread-specific and can be made permanent (bolted) if LPCRUPRT=1, allowing up to four bolted entries per thread. Ensure that the MSR[PR] bit is clear when executing this instruction, as it requires supervisor privilege level. Be cautious of alignment requirements for the SLB entry data.", "pseudocode": "SLB[RB[36:63]] ← RS", "example": "slbmte r3, r5" }, { "mnemonic": "msgclr", "architecture": "PowerISA", "full_name": "Message Clear", "summary": "Clears a pending doorbell interrupt (Inter-processor comms).", "syntax": "msgclr RB", "encoding": { "format": "X-form", "binary_pattern": "31 | / | / | RB | 118 | /", "hex_opcode": "0x7C0001DC", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "RB", "clean": "RB" }, { "raw": "118", "clean": "118" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RB", "desc": "Message Type" } ], "extension": "Privileged", "description": "Clears a pending doorbell or message interrupt from another processor, based on the message type specified in RB. This is a privileged instruction used for inter-processor communication and does not affect condition registers.", "pseudocode": "clear_pending_message(RB[62:63])", "page_found": "Page 1311", "programming_notes": "Use msgclr to clear messages accepted by the current thread. If clearing a message of type 0x05, it also clears any associated Directed Ultravisor Doorbell exception. This instruction is typically used in hypervisor environments where message handling and doorbell management are required.", "example": "msgclr r5" }, { "mnemonic": "msgsnd", "architecture": "PowerISA", "full_name": "Message Send", "summary": "Sends a doorbell interrupt to another processor.", "syntax": "msgsnd RB", "encoding": { "format": "X-form", "binary_pattern": "31 | / | / | RB | 206 | /", "hex_opcode": "0x7C00019C", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "RB", "clean": "RB" }, { "raw": "206", "clean": "206" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RB", "desc": "Message Type" } ], "extension": "Privileged", "description": "The instruction sends a message to other threads based on the contents of register RB. The message type and destination thread(s) are specified in RB.", "pseudocode": "msgtype ← GPR(RB)32:36\npayload ← GPR(RB)37:63\nif (msgtype = 0x05)\nthen\n send_msg(msgtype, payload)", "programming_notes": "If msgsnd is used to notify the receiver that updates have been made to storage, a sync should be placed between the stores and the msgsnd. See Section 6.9.2.", "page_found": "Page 1310 - 1311", "example": "msgsnd r5" }, { "mnemonic": "attn", "architecture": "PowerISA", "full_name": "Attention", "summary": "Stops execution and alerts the hardware debugger.", "syntax": "attn", "encoding": { "format": "X-form", "binary_pattern": "000000 | 00000 | 00000 | 00000 | 256 | /", "hex_opcode": "0x00000200", "visual_parts": [ { "raw": "000000", "clean": "000000" }, { "raw": "00000", "clean": "00000" }, { "raw": "00000", "clean": "00000" }, { "raw": "00000", "clean": "00000" }, { "raw": "256", "clean": "256" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [], "extension": "Privileged", "description": "Stops execution and signals the hardware debugger, allowing entry into debug mode. This is a privileged instruction that halts the processor and alerts external debugging hardware. No condition registers or status fields are affected by the instruction itself; the processor state is frozen pending debugger intervention.", "pseudocode": "SignalDebugger()", "example": "attn" }, { "mnemonic": "clrbhrb", "architecture": "PowerISA", "full_name": "Clear Branch History Rolling Buffer", "summary": "Clear Branch History Rolling Buffer. Clears all entries in the Branch History Rolling Buffer (BHRB) to zero. Used to flush branch prediction history, for example when switching execution contexts to prevent information leakage between security domains.", "syntax": "clrbhrb", "encoding": { "format": "X-form", "binary_pattern": "31 | / | / | / | 894 | /", "hex_opcode": "0x7C00035C", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "894", "clean": "894" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [], "extension": "Base", "description": "Sets all BHRB entries to 0s.", "pseudocode": "for n = 0 to (number_of_BHRBEs implemented - 1)\n BHRB(n) ←0", "page_found": "Page 1076 - 1077", "programming_notes": "The clrbhrb instruction is used to clear the Branch History Rolling Buffer, resetting all its entries to zero. This can be useful for ensuring a predictable state before branch prediction analysis or when isolating performance tests. However, it should be used with caution as it affects speculative execution paths, potentially impacting performance if not necessary.", "example": "clrbhrb" }, { "mnemonic": "tabortwc", "architecture": "PowerISA", "full_name": "Transaction Abort Word Conditional", "summary": "Aborts a transaction if the condition is met (Word comparison).", "syntax": "tabortwc TO, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | TO | RA | RB | 782 | 1", "hex_opcode": "0x7C00061D", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "TO", "clean": "TO" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "782", "clean": "782" }, { "raw": "1", "clean": "1" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "TO", "desc": "Options" }, { "name": "RA", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Transactional Memory", "description": "Transaction Abort Word Conditional. Aborts the current transaction if the condition formed by TO and the comparison of RA and RB is true. Records the abort cause in TEXASR.", "pseudocode": "if Transactional() then\n if TO_condition(TO, RA, RB) then\n Abort_Transaction(cause=Explicit)", "special_registers": "CR, CR0, CR1, CR6, MSR, TAR", "programming_notes": "Use tabortwc to conditionally abort a transaction based on a comparison between two registers. Ensure that the transaction is active when using this instruction; otherwise, it will have no effect. The TO field specifies the type of comparison (e.g., equal, less than). Be cautious with the privilege level and ensure the MSR[TS] bit is set to enable transactions.", "example": "tabortwc 4, r4, r5" }, { "mnemonic": "tabortdc", "architecture": "PowerISA", "full_name": "Transaction Abort Doubleword Conditional", "summary": "Aborts a transaction if the condition is met (Doubleword comparison).", "syntax": "tabortdc TO, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | TO | RA | RB | 814 | 1", "hex_opcode": "0x7C00065D", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "TO", "clean": "TO" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "814", "clean": "814" }, { "raw": "1", "clean": "1" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "TO", "desc": "Options" }, { "name": "RA", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Transactional Memory", "description": "Transaction Abort Doubleword Conditional. Aborts the current transaction if the condition formed by TO and the 64-bit comparison of RA and RB is true. Records the abort cause in TEXASR.", "pseudocode": "if Transactional() then\n if TO_condition_64(TO, RA, RB) then\n Abort_Transaction(cause=Explicit)", "special_registers": "CR, CR0, CR1, CR6, MSR, TAR", "programming_notes": "Use tabortdc to conditionally abort a transaction based on a 64-bit comparison. Ensure that the transaction is active when using this instruction; otherwise, it has no effect. The TO field specifies the condition for the comparison, and RA and RB are the registers holding the values to compare. This instruction operates at the problem state privilege level.", "example": "tabortdc 4, r4, r5" }, { "mnemonic": "trechkpt", "architecture": "PowerISA", "full_name": "Transaction Recheckpoint", "summary": "Updates the transaction checkpoint.", "syntax": "trechkpt", "encoding": { "format": "X-form", "binary_pattern": "31 | / | / | / | 1006 | /", "hex_opcode": "0x7C0007DD", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "1006", "clean": "1006" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [], "extension": "Transactional Memory", "description": "Transaction Recheckpoint. Restores the transactional register state from the checkpoint saved by a prior tbegin. Used to restart a transaction after a non-transactional abort.", "pseudocode": "if Suspended() then\n Restore_Checkpoint()\n Resume_Transaction()", "special_registers": "LR, CTR, CR, FPSCR, XER, MSR, SRR0, SRR1, TAR", "programming_notes": "The trechkpt instruction is used to restore the transactional register state from a previous checkpoint, allowing a transaction to be restarted after a non-transactional abort. It should only be used within a transactional region and requires that the transaction was previously suspended. Ensure proper ordering of instructions to maintain consistency and avoid data corruption.", "example": "trechkpt" }, { "mnemonic": "lxvl", "architecture": "PowerISA", "full_name": "Load VSX Vector Length", "summary": "Loads N bytes into a vector, where N is specified in a GPR.", "syntax": "lxvl XT, RA, RB", "encoding": { "format": "XX1-form", "binary_pattern": "0 | T | RA | RB | TX | 0 | 0 | 0", "hex_opcode": "0x7C00021A", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "XT", "clean": "XT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "269", "clean": "269" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Length Reg" } ], "extension": "VSX", "description": "Loads up to 16 bytes from memory into a VSX register, with the byte count specified by bits 0-4 of RB. Bytes from address RA|0 (or RA + RB if RA is non-zero) are loaded left-aligned into XT; unloaded bytes are zeroed. This is a VSX category instruction with no effect on condition registers.", "pseudocode": "N ← RB[0:4]\nif N > 16 then N ← 16\naddr ← RA + 0 (if RA != 0 else address from context)\nfor i ← 0 to N-1\n XT[8*i:8*i+7] ← [addr + i]\nfor i ← N to 15\n XT[8*i:8*i+7] ← 0", "programming_notes": "Loading less than 16 bytes of data using lxvl in BE mode results in data being loaded into the target VSR left-to-right, placing the first byte in the leftmost byte of the target VSR, and padded on the right with 0s. Loading less than 16 bytes of data using lxvl in LE mode results in data being loaded into the target VSR right-to-left, placing the first byte in the rightmost byte of the target VSR, and padded on the left with 0s.", "page_found": "Page 623 - 624", "special_registers": "MSR", "example": "lxvl vs1, r4, r5" }, { "mnemonic": "stxvl", "architecture": "PowerISA", "full_name": "Store VSX Vector Length", "summary": "Stores a specified number of bytes from a VSX vector register to memory.", "syntax": "stxvl XS, RA, RB", "encoding": { "format": "XX1-form", "binary_pattern": "31 | XS | RA | RB | 397", "hex_opcode": "0x7C00031A", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "XS", "clean": "XS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "397", "clean": "397" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "XS", "desc": "Source" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Length Reg" } ], "extension": "VSX", "description": "Stores up to 16 bytes from a VSX register to memory, with the byte count specified by bits 0-4 of RB. Bytes are stored from XS starting at address RA|0 (or RA + RB if RA is non-zero). This is a VSX category instruction with no effect on condition registers.", "pseudocode": "N ← RB[0:4]\nif N > 16 then N ← 16\naddr ← RA + 0 (if RA != 0 else address from context)\nfor i ← 0 to N-1\n [addr + i] ← XS[8*i:8*i+7]", "programming_notes": "Storing N bytes of data from the source VSR using stxvl in BE mode, results in the leftmost N bytes in the source VSR being placed in storage, starting with the leftmost byte of the source VSR.\n\nStoring N bytes of data from the source VSR using stxvl in LE mode, results in the rightmost N bytes in the source VSR being placed in storage, starting with the rightmost byte of the source VSR.", "page_found": "Page 635 - 636", "special_registers": "MSR", "example": "stxvl vs1, r4, r5" }, { "mnemonic": "xxperm", "architecture": "PowerISA", "full_name": "VSX Vector Permute", "summary": "Performs a vector permute operation on the contents of three VSX registers.", "syntax": "xxperm XT, XA, XB, XC", "encoding": { "format": "XX4-form", "binary_pattern": "18 | T | A | B | AX | BX | TX", "hex_opcode": "0xF00000D0", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "XC", "clean": "XC" }, { "raw": "26", "clean": "26" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" }, { "name": "XC", "desc": "Control" } ], "extension": "VSX", "description": "Permutes bytes from two 128-bit VSX registers (XA and XB) using a control vector in XC to produce a 128-bit result in XT. Each byte in the control vector specifies which byte from the 32-byte concatenation of XA and XB is selected into the corresponding output byte. This is a VSX category instruction with no effect on condition registers.", "pseudocode": "concat ← XA || XB\nfor i ← 0 to 15\n control_byte ← XC[8*i:8*i+7]\n idx ← control_byte[1:4]\n XT[8*i:8*i+7] ← concat[8*idx:8*idx+7]", "page_found": "Page 958 - 959", "special_registers": "MSR", "programming_notes": "The xxperm instruction requires VSX (Vector Scalar Extensions) to be enabled in the MSR register. Ensure that the control vector register is correctly set up, as it defines how the source bytes are permuted. This instruction operates on 32-byte vectors and can be used for tasks like data reordering or encryption. Be cautious of alignment requirements; the VSX registers must be properly aligned to avoid exceptions.", "example": "xxperm vs1, vs2, vs3, vs4" }, { "mnemonic": "xxpermr", "architecture": "PowerISA", "full_name": "VSX Vector Permute Right", "summary": "Little-endian optimized permute.", "syntax": "xxpermr XT, XA, XB, XC", "encoding": { "format": "XX4-form", "binary_pattern": "60 | XT | XA | XB | XC | 58", "hex_opcode": "0xF00001D0", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "XC", "clean": "XC" }, { "raw": "58", "clean": "58" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:31", "length": "32" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" }, { "name": "XC", "desc": "Control" } ], "extension": "VSX", "description": "Permutes bytes from two 128-bit VSX registers (XA and XB) using a control vector in XC, optimized for little-endian byte ordering. Each byte in the control vector specifies which byte from the concatenation of XB and XA is selected into the corresponding output byte in XT. This is a VSX category instruction with no effect on condition registers.", "pseudocode": "concat ← XB || XA\nfor i ← 0 to 15\n control_byte ← XC[8*i:8*i+7]\n idx ← control_byte[1:4]\n XT[8*i:8*i+7] ← concat[8*idx:8*idx+7]", "page_found": "Page 959", "programming_notes": "The xxpermr instruction is useful for complex byte-level data manipulation, especially when merging and reordering bytes from two source vectors. Ensure that the control vector (second source) correctly specifies the desired permutation indices to avoid unexpected results. This instruction operates at a privilege level that allows it in user mode, but developers should be cautious of potential performance overhead due to its complexity.", "example": "xxpermr vs1, vs2, vs3, vs4" }, { "mnemonic": "lswx", "architecture": "PowerISA", "full_name": "Load String Word Indexed", "summary": "Loads N bytes from memory (N in XER).", "syntax": "lswx RT, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | RA | RB | 533 | /", "hex_opcode": "0x7C00042A", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "533", "clean": "533" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Start Reg" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Base", "description": "Loads a variable number of bytes from memory into a sequence of GPRs starting at RT, where the byte count is stored in XER[25:31]. Bytes are loaded from address RA|0 (or RA + RB if RA is non-zero) into consecutive 32-bit words. This is a Base category instruction that does not affect condition registers.", "pseudocode": "N ← XER[25:31]\naddr ← (RA == 0) ? 0 : RA + RB\nreg ← RT\nfor i ← 0 to N-1\n byte_offset ← i mod 4\n if byte_offset == 0 and i > 0 then\n reg ← (reg + 1) mod 32\n reg[8*byte_offset:8*byte_offset+7] ← [addr + i]", "page_found": "Page 106", "special_registers": "XER", "programming_notes": "String instructions are not pipelined on most implementations and can be very slow for large counts. Consider using byte loops or vector instructions for performance-critical paths. NB: these instructions are optional in Power ISA 3.0+ and may trap on some implementations.", "example": "lswx r3, r4, r5" }, { "mnemonic": "stswx", "architecture": "PowerISA", "full_name": "Store String Word Indexed", "summary": "Stores N bytes to memory (N in XER).", "syntax": "stswx RT, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | RA | RB | 661 | /", "hex_opcode": "0x7C00052A", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "661", "clean": "661" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Start Reg" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Base", "description": "Stores a variable number of bytes from a sequence of GPRs starting at RT to memory, where the byte count is stored in XER[25:31]. Bytes are stored from consecutive 32-bit words to address RA|0 (or RA + RB if RA is non-zero). This is a Base category instruction that does not affect condition registers.", "pseudocode": "N ← XER[25:31]\naddr ← (RA == 0) ? 0 : RA + RB\nreg ← RT\nfor i ← 0 to N-1\n byte_offset ← i mod 4\n if byte_offset == 0 and i > 0 then\n reg ← (reg + 1) mod 32\n [addr + i] ← reg[8*byte_offset:8*byte_offset+7]", "page_found": "Page 107", "special_registers": "XER", "programming_notes": "String instructions are not pipelined on most implementations and can be very slow for large counts. Consider using byte loops or vector instructions for performance-critical paths. NB: these instructions are optional in Power ISA 3.0+ and may trap on some implementations.", "example": "stswx r3, r4, r5" }, { "mnemonic": "wait", "architecture": "PowerISA", "full_name": "Wait for Interrupt", "summary": "Stops instruction execution and places the processor in a lower power state until an interrupt occurs.", "syntax": "wait WC,PL", "encoding": { "format": "X-form", "binary_pattern": "31 | / | WC | / | 62 | /", "hex_opcode": "0x7C00003C", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "WC", "clean": "WC" }, { "raw": "/", "clean": "/" }, { "raw": "62", "clean": "62" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "WC", "desc": "Wait Condition (0=Interrupt, 1=Resume)" }, { "name": "PL", "desc": "Programmable Length Field" } ], "pseudocode": "if WC == 0 then\n WaitForInterrupt()\nelse if WC == 1 then\n WaitForResume()", "example": "wait 0", "example_note": "Idle CPU.", "extension": "Base", "description": "Suspends instruction execution and places the processor in a low-power idle state until an interrupt is pending. The WC field selects the wait condition (interrupt vs. resume), and the PL field optionally specifies a programmable length timeout. This is a Base/privileged instruction with no effect on condition registers; execution resumes after the specified event.", "programming_notes": "Because the waiting begins when the instruction completes, if the waiting is ended by an exception that causes a change of control flow (interrupt, event-based branch), the SPR that is set to reflect the point in the instruction stream at which the change of control flow occurred (e.g., SRR0 for Decrementer interrupt) will contain the EA of the instruction following the wait instruction. Bits 6 and 7 of the wait instruction may be used in some implementations for an implementation-dependent field. Unless the intention is to use the implementation-dependent field, these bits must be coded zero. wait serves as both a basic and an extended mnemonic. The Assembler will recognize a wait mnemonic with two operands as the basic form and a wait mnemonic with one operand or with no operand as an extended form. In the extended form with one operand the PL operand is omitted and assumed to be 0. In the extended form with no operand the WC and PL operands are omitted and assumed to be 0. The wait instruction frees computational resources which might be allocated to another program or converted into power savings.", "extended_mnemonics": [ { "mnemonic": "waitrsv", "equivalent_to": "wait 1,0" }, { "mnemonic": "pause_short", "equivalent_to": "wait 2,0" } ], "page_found": "Page 1064 - 1065" }, { "mnemonic": "dcbzl", "architecture": "PowerISA", "full_name": "Data Cache Block Zero Long", "summary": "Zeros a cache block (implementation defined size).", "syntax": "dcbzl RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | / | RA | RB | 1014 | /", "hex_opcode": "0x7C0007EC", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "1014", "clean": "1014" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Base", "description": "Zeros a cache block of implementation-defined size (typically larger than the standard dcbz 128-byte block) specified by the address computed as RA + RB. This instruction operates on the data cache and may affect cache coherency on multiprocessor systems. No condition or status registers are modified; cache operations are weakly ordered.", "pseudocode": "EA ← (RA) + (RB)\nZero cache block at EA with implementation-defined block size", "example": "dcbzl r4, r5" }, { "mnemonic": "slbmfee", "architecture": "PowerISA", "full_name": "SLB Move From Entry ESID", "summary": "Reads the ESID part of an SLB entry.", "syntax": "slbmfee RT, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | / | RB | 366 | /", "hex_opcode": "0x7C000726", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "/", "clean": "/" }, { "raw": "RB", "clean": "RB" }, { "raw": "366", "clean": "366" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RB", "desc": "Index" } ], "extension": "Privileged", "description": "Reads the ESID (Effective Segment ID) portion of a Segment Lookaside Buffer entry. The SLB entry is selected by the index in RB. This privileged instruction is used in 64-bit mode for TLB management. No condition or status registers are modified.", "pseudocode": "RT ← SLB[RB].ESID", "special_registers": "LPCRUPRT", "programming_notes": "The slbmfee instruction is used to read software-loaded SLB entries, placing the ESID and V fields into register RT. If the entry is valid and LPCRUPRT is set, it also places the BO field into RT. Ensure that the index calculation respects the LPCRUPRT setting to avoid accessing invalid SLB entries.", "example": "slbmfee r3, r5" }, { "mnemonic": "slbmfev", "architecture": "PowerISA", "full_name": "SLB Move From Entry VSID", "summary": "Reads software-loaded SLB entries and places the contents of the B, VSID, Ks, Kp, N, L, C, and LP fields into register RT.", "syntax": "slbmfev RT, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | / | RB | 851 | /", "hex_opcode": "0x7C0006A6", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "/", "clean": "/" }, { "raw": "RB", "clean": "RB" }, { "raw": "334", "clean": "334" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RB", "desc": "Index" }, { "name": "RS", "desc": "Source General Purpose Register" } ], "extension": "Privileged", "description": "This instruction is used to read software-loaded SLB entries. When LPCRUPRT=0, the entry is specified by bits 52:63 of register RB. When LPCRUPRT=1, only the first four entries can be read, so bits 52:61 of register RB are ignored. If the specified entry is valid (V=1), the contents of the B, VSID, Ks, Kp, N, L, C, and LP fields of the entry are placed into register RT.", "pseudocode": "if 'slbmfev' then\n if LPCRUPRT=0 then\n entry_index <- (RB)[52:63]\n else\n entry_index <- (RB)[52:61] & 0xF\n end if\n if SLB[entry_index].V=1 then\n RT[0:1] <- SLB[entry_index].B\n RT[2:51] <- SLB[entry_index].VSID\n RT[52] <- SLB[entry_index].Ks\n RT[53] <- SLB[entry_index].Kp\n RT[54] <- SLB[entry_index].N\n RT[55] <- SLB[entry_index].L\n RT[56] <- SLB[entry_index].C\n RT[57] <- 0b0\n RT[58:59] <- SLB[entry_index].LP\n RT[60:63] <- 0b0000\n else\n RT <- 0\n end if", "programming_notes": "This instruction is privileged. The use of the L field is implementation specific.", "page_found": "Page 1204 - 1205", "special_registers": "LPCRUPRT", "example": "slbmfev r3, r5" }, { "mnemonic": "msgclrp", "architecture": "PowerISA", "full_name": "Message Clear Privileged", "summary": "Clears a privileged doorbell interrupt.", "syntax": "msgclrp RB", "encoding": { "format": "X-form", "binary_pattern": "31 | / | / | RB | 150 | /", "hex_opcode": "0x7C00015C", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "RB", "clean": "RB" }, { "raw": "150", "clean": "150" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RB", "desc": "Type" } ], "extension": "Privileged", "description": "Clears a privileged doorbell interrupt message matching the type specified in RB. This privileged instruction is used for inter-processor communication and interrupt management. Clearing a message may affect pending interrupts. No explicit status registers are modified, but interrupt state is affected.", "pseudocode": "Clear privileged doorbell message of type (RB)", "page_found": "Page 1312", "programming_notes": "The msgclrp instruction is used to clear messages accepted by the current thread, specifically handling Directed Hypervisor Doorbell exceptions when the message type is 0x05. It operates at a privileged level and should be used carefully to avoid unintended side effects on exception handling.", "example": "msgclrp r5" }, { "mnemonic": "msgsndp", "architecture": "PowerISA", "full_name": "Message Send Privileged", "summary": "Sends a message to other threads on the same processor or sub-processor.", "syntax": "msgsndp RB", "encoding": { "format": "X-form", "binary_pattern": "31 | / | / | RB | 142 | /", "hex_opcode": "0x7C00011C", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "RB", "clean": "RB" }, { "raw": "142", "clean": "142" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RB", "desc": "Type" } ], "extension": "Privileged", "description": "The instruction sends a message to other threads based on the contents of RB. The message type and destination thread(s) are specified in RB.", "pseudocode": "msgtype ← (RB)32:36\npayload ← (RB)37:63\nt ← (RB)57:63\nif msgtype = 5 and t ≤ maximum privileged thread number on processor or sub-processor then\n DPDES63-t ← 1\n send_msg(msgtype, payload, t)", "special_registers": "DPDES", "programming_notes": "If msgsndp is used to notify the receiver that updates have been made to storage, a lwsync or sync should be placed between the stores and the msgsndp. See Section 6.9.2.", "page_found": "Page 1311 - 1312", "example": "msgsndp r5" }, { "mnemonic": "mfsr", "architecture": "PowerISA", "full_name": "Move From Segment Register", "summary": "Legacy 32-bit segment register read.", "syntax": "mfsr RT, SR", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | SR | / | 595 | /", "hex_opcode": "0x7C0004A6", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "SR", "clean": "SR" }, { "raw": "/", "clean": "/" }, { "raw": "595", "clean": "595" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "SR", "desc": "Segment Reg" } ], "extension": "Base", "description": "Reads a 32-bit Segment Register (legacy 32-bit PowerPC mode) and stores the value in RT. This instruction is used only in 32-bit addressing mode and is deprecated in 64-bit architecture. No condition or status registers are modified.", "pseudocode": "RT ← SR[SR number from instruction]", "example": "mfsr r3, 0" }, { "mnemonic": "mtsr", "architecture": "PowerISA", "full_name": "Move To Segment Register", "summary": "Legacy 32-bit segment register write.", "syntax": "mtsr SR, RS", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | SR | / | 210 | /", "hex_opcode": "0x7C0001A4", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "SR", "clean": "SR" }, { "raw": "/", "clean": "/" }, { "raw": "210", "clean": "210" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "SR", "desc": "Segment Reg" }, { "name": "RS", "desc": "Source" } ], "extension": "Base", "description": "Move the contents of GPR RS into the specified 32-bit segment register SR. This is a legacy instruction used in 32-bit PowerPC address translation and is not available in 64-bit mode. No status fields are affected.", "pseudocode": "SR ← RS[32:63]", "example": "mtsr 0, r3" }, { "mnemonic": "mfsrin", "architecture": "PowerISA", "full_name": "Move From Segment Register Indirect", "summary": "Indirect read of segment register using RB.", "syntax": "mfsrin RT, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | / | RB | 659 | /", "hex_opcode": "0x7C000526", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "/", "clean": "/" }, { "raw": "RB", "clean": "RB" }, { "raw": "659", "clean": "659" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RB", "desc": "Effective Addr" } ], "extension": "Base", "description": "Move the contents of the segment register selected by bits 0-3 of GPR RB into GPR RT. This is an indirect read of the 32-bit segment register and is not available in 64-bit mode. No status fields are affected.", "pseudocode": "SR_index ← RB[0:3]\nRT ← SR[SR_index]", "example": "mfsrin r3, r5" }, { "mnemonic": "mtsrin", "architecture": "PowerISA", "full_name": "Move To Segment Register Indirect", "summary": "Indirect write of segment register using RB.", "syntax": "mtsrin RS, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | / | RB | 242 | /", "hex_opcode": "0x7C0001E4", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "/", "clean": "/" }, { "raw": "RB", "clean": "RB" }, { "raw": "242", "clean": "242" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RS", "desc": "Source" }, { "name": "RB", "desc": "Effective Addr" } ], "extension": "Base", "description": "Move the contents of GPR RS into the segment register selected by bits 0-3 of GPR RB. This is an indirect write of the 32-bit segment register and is not available in 64-bit mode. No status fields are affected.", "pseudocode": "SR_index ← RB[0:3]\nSR[SR_index] ← RS[32:63]", "example": "mtsrin r3, r5" }, { "mnemonic": "mfbhrbe", "architecture": "PowerISA", "full_name": "Move From Branch History Rolling Buffer Entry", "summary": "Reads a specific entry from the BHRB.", "syntax": "mfbhrbe RT, BHRBE", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | BHRBE | / | 302 | /", "hex_opcode": "0x7C00025C", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "BHRBE", "clean": "BHRBE" }, { "raw": "/", "clean": "/" }, { "raw": "302", "clean": "302" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "BHRBE", "desc": "Entry Index" } ], "extension": "Base", "description": "Move the contents of a Branch History Rolling Buffer (BHRB) entry, indexed by BHRBE, into GPR RT. The BHRB records branch addresses and is used for performance monitoring. This is a hypervisor-privileged or performance-monitoring register operation. No architected status fields are affected.", "pseudocode": "RT ← BHRB[BHRBE]", "page_found": "Page 1077", "special_registers": "BHRBE0:9", "programming_notes": "The mfbhrbe instruction is used to access entries in the Branch History Rolling Buffer (BHRB). Ensure that the specified entry index is within the range of implemented entries to avoid placing zero in the target register. This instruction operates at user privilege level and does not generate exceptions under normal conditions.", "example": "mfbhrbe r3, 0" }, { "mnemonic": "tsr", "architecture": "PowerISA", "full_name": "Transaction Suspend or Resume", "summary": "Suspends or resumes a transaction based on L.", "syntax": "tsr L", "encoding": { "format": "X-form", "binary_pattern": "31 | L | / | / | 750 | /", "hex_opcode": "0x7C0005DE", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "L", "clean": "L" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "750", "clean": "750" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "L", "desc": "1=Suspend" } ], "extension": "Transactional Memory", "description": "Transaction Suspend or Resume. Suspends an active transaction (L=0) or resumes a suspended transaction (L=1). The transactional state is preserved across the suspend/resume boundary.", "pseudocode": "if L = 0 then\n Suspend_Transaction()\nelse\n Resume_Transaction()", "special_registers": "MSR", "programming_notes": "The tsr instruction is used to either suspend or resume a transaction based on the value of the L bit. Ensure that the transactional state is properly managed to avoid data corruption. This instruction operates at the privilege level of the executing context and may raise exceptions if used incorrectly, such as attempting to resume a non-existent suspended transaction.", "example": "tsr 0" }, { "mnemonic": "tabortwci", "architecture": "PowerISA", "full_name": "Transaction Abort Word Conditional Immediate", "summary": "Aborts transaction if word condition (Immediate) is met.", "syntax": "tabortwci TO, RA, SI", "encoding": { "format": "X-form", "binary_pattern": "31 | TO | RA | SI | 782 | 1", "hex_opcode": "0x7C00061D", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "TO", "clean": "TO" }, { "raw": "RA", "clean": "RA" }, { "raw": "SI", "clean": "SI" }, { "raw": "782", "clean": "782" }, { "raw": "1", "clean": "1" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "TO", "desc": "Options" }, { "name": "RA", "desc": "Src" }, { "name": "SI", "desc": "Immediate" } ], "extension": "Transactional Memory", "description": "Transaction Abort Word Conditional Immediate. Aborts the current transaction if the condition formed by TO and the comparison of RA with the sign-extended immediate SI is true.", "pseudocode": "if Transactional() then\n if TO_condition(TO, RA, EXTS(SI)) then\n Abort_Transaction(cause=Explicit)", "special_registers": "CR, MSR", "programming_notes": "Use tabortwci to conditionally abort a transaction based on the comparison of a register with an immediate value. Ensure that the transactional state is active; otherwise, the instruction has no effect. Be cautious with the TO condition and immediate sign extension to avoid unintended aborts.", "example": "tabortwci 4, r4, 16" }, { "mnemonic": "tabortdci", "architecture": "PowerISA", "full_name": "Transaction Abort Doubleword Conditional Immediate", "summary": "Aborts transaction if doubleword condition (Immediate) is met.", "syntax": "tabortdci TO, RA, SI", "encoding": { "format": "X-form", "binary_pattern": "31 | TO | RA | SI | 814 | 1", "hex_opcode": "0x7C00065D", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "TO", "clean": "TO" }, { "raw": "RA", "clean": "RA" }, { "raw": "SI", "clean": "SI" }, { "raw": "814", "clean": "814" }, { "raw": "1", "clean": "1" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "TO", "desc": "Options" }, { "name": "RA", "desc": "Src" }, { "name": "SI", "desc": "Immediate" } ], "extension": "Transactional Memory", "description": "Transaction Abort Doubleword Conditional Immediate. Aborts the current transaction if the condition formed by TO and the 64-bit comparison of RA with the sign-extended immediate SI is true.", "pseudocode": "if Transactional() then\n if TO_condition_64(TO, RA, EXTS(SI)) then\n Abort_Transaction(cause=Explicit)", "special_registers": "CR, MSR", "programming_notes": "Use tabortdci to conditionally abort a transaction based on a comparison between a register and an immediate value. Ensure the transaction is active; otherwise, the instruction has no effect. Be cautious with TO conditions to avoid unintended transaction aborts.", "example": "tabortdci 4, r4, 16" }, { "mnemonic": "xsrintqp", "architecture": "PowerISA", "full_name": "VSX Scalar Round to Integer Quad-Precision", "summary": "Rounds Quad float to nearest Integer.", "syntax": "xsrintqp vD, vB", "encoding": { "format": "X-form", "binary_pattern": "63 | vD | / | vB | 484 | /", "hex_opcode": "0xFC0003C4", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "vD", "clean": "vD" }, { "raw": "/", "clean": "/" }, { "raw": "vB", "clean": "vB" }, { "raw": "484", "clean": "484" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" } ], "extension": "VSX", "description": "Round the quad-precision floating-point value in VSR vB to the nearest integer, using the rounding mode specified in FPSCR[RN], and store the result in VSR vD. This is a VSX instruction. FPSCR is read for rounding mode and may have status flags updated (XX, ZX, etc.) depending on the rounding operation.", "pseudocode": "vD ← round_to_integer_qp(vB, FPSCR[RN])\nFPSCR[FPCC, VXCVI, XX, ZX, ...] ← updated as per rounding", "example": "xsrintqp vd, vb" }, { "mnemonic": "dctqpq", "architecture": "PowerISA", "full_name": "Decimal Convert To Quad-Precision DFP", "summary": "Converts DFP Long (64-bit) to DFP Quad (128-bit).", "syntax": "dctqpq vD, FRB", "encoding": { "format": "X-form", "binary_pattern": "63 | vD | / | FRB | 258 | /", "hex_opcode": "0xFC000204", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "vD", "clean": "vD" }, { "raw": "/", "clean": "/" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "258", "clean": "258" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target Quad" }, { "name": "FRB", "desc": "Source Long" } ], "extension": "Decimal Floating-Point", "description": "Convert a DFP long (64-bit) value from FPR FRB into a DFP quad (128-bit) value and store it in VSR vD. This is a Decimal Floating-Point (DFP) instruction. FPSCR status fields may be updated to indicate conversion results.", "pseudocode": "quad_value ← convert_dfp_long_to_quad(FRB)\nvD ← quad_value\nFPSCR[...] ← updated as per conversion", "special_registers": "FPSCR", "programming_notes": "The dctqpq instruction is used to convert a DFP number from long format to extended format. Ensure that the source register (FRAp) contains a valid DFP value in long format, and the target register (FRTp) is properly aligned for storing an extended format DFP number. This operation does not alter the FPSCR register.", "example": "dctqpq vd, f3" }, { "mnemonic": "drdpq", "architecture": "PowerISA", "full_name": "Decimal Round To DFP Quad-Precision", "summary": "Rounds DFP Quad (128-bit) to DFP Long (64-bit).", "syntax": "drdpq FRT, vB", "encoding": { "format": "X-form", "binary_pattern": "63 | FRT | / | vB | 770 | /", "hex_opcode": "0xFC000604", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "/", "clean": "/" }, { "raw": "vB", "clean": "vB" }, { "raw": "770", "clean": "770" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "FRT", "desc": "Target Long" }, { "name": "vB", "desc": "Source Quad" } ], "extension": "Decimal Floating-Point", "description": "Round a DFP quad (128-bit) value from VSR vB to DFP long (64-bit) precision using the rounding mode in FPSCR[RN], and store the result in FPR FRT. This is a Decimal Floating-Point (DFP) instruction. FPSCR status fields are updated to reflect rounding or conversion results.", "special_registers": "FPSCR", "programming_notes": "The drdpq instruction is used for rounding decimal floating-point numbers to quad-precision. Ensure that the input number in FRA[p] is within the valid range for quad-precision format to avoid overflow or underflow exceptions. The rounding mode is controlled by the FPSCR register, so make sure it's set according to your application's requirements before executing drdpq.", "pseudocode": "long_value ← round_dfp_quad_to_long(vB, FPSCR[RN])\nFRT ← long_value\nFPSCR[...] ← updated as per rounding", "example": "drdpq f1, vb" }, { "mnemonic": "vcipherlast", "architecture": "PowerISA", "full_name": "Vector Cipher Last", "summary": "Performs the final round of AES encryption (SubBytes, ShiftRows, AddRoundKey). No MixColumns.", "syntax": "vcipherlast vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 1289", "hex_opcode": "0x10000509", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1289", "clean": "1289" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "State" }, { "name": "vB", "desc": "Round Key" } ], "extension": "Vector Crypto", "description": "Perform the final round of AES encryption on 128-bit blocks. Applies SubBytes, ShiftRows, and AddRoundKey transformations (but not MixColumns, which is done in prior rounds). Operates on one or more 128-bit AES blocks. No status flags are affected.", "pseudocode": "vD ← AES_SubBytes(vA)\nvD ← AES_ShiftRows(vD)\nvD ← AES_AddRoundKey(vD, vB)", "page_found": "Page 460", "special_registers": "MSR", "programming_notes": "The vcipherlast instruction is used to perform the final round of AES encryption on a vector of data. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. This instruction processes each 32-bit word of the input data with the corresponding round key from the VRA register to produce the encrypted output in the VRT register.", "example": "vcipherlast vd, va, vb" }, { "mnemonic": "vncipherlast", "architecture": "PowerISA", "full_name": "Vector Inverse Cipher Last", "summary": "Performs the final round of AES decryption.", "syntax": "vncipherlast vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 1353", "hex_opcode": "0x10000549", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1353", "clean": "1353" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "State" }, { "name": "vB", "desc": "Round Key" } ], "extension": "Vector Crypto", "description": "Performs the final round of AES decryption on a 128-bit block, applying the inverse MixColumns and InvSubBytes operations followed by AddRoundKey with the provided round key. This instruction is part of the Vector Crypto extension and operates on 128-bit values held in vector registers. No status flags are affected.", "pseudocode": "vD ← InvCipherLast(vA, vB)", "page_found": "Page 461", "special_registers": "MSR", "programming_notes": "The vncipherlast instruction is used to complete the AES inverse cipher process by applying the final transformations. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The input State and RoundKey must be correctly loaded into VSR registers VRA+32 and VRB+32, respectively, to avoid incorrect results.", "example": "vncipherlast vd, va, vb" }, { "mnemonic": "vsbox", "architecture": "PowerISA", "full_name": "Vector S-Box", "summary": "Performs the SubBytes operation (S-Box lookup) on a vector.", "syntax": "vsbox vD, vA", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 0 | vA | 1480", "hex_opcode": "0x100005C8", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vA", "clean": "vA" }, { "raw": "1480", "clean": "1480" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Source" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" } ], "extension": "Vector Crypto", "description": "Performs the SubBytes operation (S-Box lookup) on all 16 bytes of a 128-bit vector, applying the AES S-box transformation to each byte independently. This instruction is part of the Vector Crypto extension and is used during AES encryption and decryption. No status flags are affected.", "pseudocode": "for i = 0 to 15 do vD[8*i:8*i+7] ← AES_SBOX[vA[8*i:8*i+7]]", "page_found": "Page 461 - 462", "special_registers": "MSR", "programming_notes": "The vsbox instruction applies the AES SubBytes transformation to a vector register, requiring the Vector Facility to be enabled (MSR.VEC=1). Ensure that the input vector is correctly aligned and that the destination register is properly set to avoid data corruption. This instruction operates at user privilege level but will raise an exception if the Vector Facility is not available.", "example": "vsbox vd, va" }, { "mnemonic": "vshasigmad", "architecture": "PowerISA", "full_name": "Vector SHA-512 Sigma Doubleword", "summary": "Performs the SHA-512 σ0, σ1, Σ0, or Σ1 functions on doubleword elements of vector registers.", "syntax": "vshasigmad vD, vA, ST, SIX", "encoding": { "format": "VX-form", "binary_pattern": "1730 | VRT | VRA | ST | SIX", "hex_opcode": "0x100006C2", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "ST", "clean": "ST" }, { "raw": "1730", "clean": "1730" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Source" }, { "name": "ST", "desc": "Type" }, { "name": "SIX", "desc": "Shift" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" } ], "extension": "Vector Crypto", "description": "For vshasigmad, the instruction performs either a SHA-512 σ0, σ1, Σ0, or Σ1 function on each doubleword element of VSR[VRA+32] based on the values in ST and SIX. The result is placed into corresponding elements of VSR[VRT+32].", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 1\n src ← VSR[VRA+32].dword[i]\n if ST=0 & SIX.bit[2×i]=0 then\n // SHA-512 σ0 function\n VSR[VRT+32].dword[i] ← (src >>> 1) ⊕ (src >>> 8) ⊕ (src >> 7)\n if ST=0 & SIX.bit[2×i]=1 then\n // SHA-512 σ1 function\n VSR[VRT+32].dword[i] ← (src >>> 19) ⊕ (src >>> 61) ⊕ (src >> 6)\n if ST=1 & SIX.bit[2×i]=0 then\n // SHA-512 Σ0 function\n VSR[VRT+32].dword[i] ← (src >>> 28) ⊕ (src >>> 34) ⊕ (src >>> 39)\n if ST=1 & SIX.bit[2×i]=1 then\n // SHA-512 Σ1 function\n VSR[VRT+32].dword[i] ← (src >>> 14) ⊕ (src >>> 18) ⊕ (src >>> 41)\nend", "programming_notes": "Bits 1 and 3 of SIX are reserved.", "page_found": "Page 462 - 463", "special_registers": "MSR", "example": "vshasigmad vd, va, r4, 0" }, { "mnemonic": "vpermxor", "architecture": "PowerISA", "full_name": "Vector Permute and Exclusive-OR", "summary": "Permutes bytes from vA and vB, then XORs with vC. Used for finite field arithmetic.", "syntax": "vpermxor vD, vA, vB, vC", "encoding": { "format": "VA-form", "binary_pattern": "0 | VRT | VRA | VRB | VRC | 45", "hex_opcode": "0x1000002D", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "vC", "clean": "vC" }, { "raw": "45", "clean": "45" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "vC", "desc": "Permute" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "VRC", "desc": "Control Vector Register" } ], "extension": "Vector Crypto", "description": "Permutes bytes from vA and vB according to the permutation control vector vC, then XORs the result with vC. This instruction is used for finite field arithmetic operations in cryptographic algorithms within the Vector Crypto extension. No status flags are affected.", "pseudocode": "temp ← Permute(vA || vB, vC); vD ← temp XOR vC", "page_found": "Page 467 - 468", "special_registers": "MSR", "programming_notes": "The vpermxor instruction requires the Vector Facility to be enabled in the MSR. Ensure that the index values in VRC do not exceed 15 to avoid undefined behavior. This instruction operates on byte-level data and is useful for complex data transformations involving permutation and bitwise operations.", "example": "vpermxor vd, va, vb, vc" }, { "mnemonic": "bcdcfn.", "architecture": "PowerISA", "full_name": "Decimal Convert from National", "summary": "Converts a national decimal value to packed decimal format and stores it in the target vector register.", "syntax": "bcdcfn. vD, vB, PS", "encoding": { "format": "VX-form", "binary_pattern": "4 | VRT | 7 | VRB | 1 | PS | 385", "hex_opcode": "0x10070581", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "1", "clean": "1" }, { "raw": "vB", "clean": "vB" }, { "raw": "1473", "clean": "1473" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:29 | 30 | 31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "PS", "desc": "Sign" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "Vector BCD", "description": "The instruction checks if the source vector register contains a valid national decimal value. If valid, it converts it to packed decimal format and stores it in the target vector register. The condition register is updated based on the comparison of the source with zero.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nsrc_sign ←(VSR[VRB+32].hword[7] = 0x002D)\neq_flag ←1\ninv_flag ←(VSR[VRB+32].hword[7] != 0x002B) & (VSR[VRB+32].hword[7] != 0x002D)\ndo i = 0 to 6\neq_flag ←eq_flag & (VSR[VRB+32].hword[i] = 0x0030)\ninv_flag ←inv_flag | (VSR[VRB+32].hword[i] < 0x0030) | (VSR[VRB+32].hword[i] > 0x0039)\nend\nlt_flag ←(eq_flag=0) & (src_sign=1)\ngt_flag ←(eq_flag=0) & (src_sign=0)\ndo i = 0 to 23\nresult.nibble[i] ←0x0\nend\ndo i = 0 to 6\nresult.nibble[i+24] ← VSR[VRB+32].hword[i].nibble[3]\nend\nresult.nibble[31] ← (src_sign=0) ? ((PS=0) ? 0xC : 0xF) : 0xD\nVSR[VRT+32] ←inv_flag ? undefined : result\nCR.bit[56] ←inv_flag ? 0b0 : lt_flag\nCR.bit[57] ←inv_flag ? 0b0 : gt_flag\nCR.bit[58] ←inv_flag ? 0b0 : eq_flag\nCR.bit[59] ←inv_flag", "special_registers": "CR6, VSR[VRT+32], VSR[VRB+32]", "page_found": "Page 503 - 504", "programming_notes": "The bcdcfn. instruction is used to convert a national decimal value in a vector register to packed decimal format, updating the condition register based on comparison with zero. Ensure the source vector contains valid national decimal values; otherwise, the result is undefined and flags are set accordingly. This instruction requires the Vector Facility (MSR.VEC) enabled.", "example": "bcdcfn. vd, vb, 0" }, { "mnemonic": "bcdctn.", "architecture": "PowerISA", "full_name": "Decimal Convert to National", "summary": "Converts a packed decimal value to national decimal format and stores it in a vector register.", "syntax": "bcdctn. vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | VRT | 5 | VRB | 1 | / | 385", "hex_opcode": "0x10050581", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "1473", "clean": "1473" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:29 | 30 | 31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "Vector BCD", "description": "The instruction converts the packed decimal value from VSR[VRB+32] into national decimal format and places it into VSR[VRT+32]. It also updates the condition register CR6 based on the validity of the input and its comparison to zero.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nend\nsrc_sign ←(VSR[VRB+32].nibble[31] = 0xB) | (VSR[VRB+32].nibble[31] = 0xD)\neq_flag ←(VSR[VRB+32].nibble[0:30] = 0)\nlt_flag ←(eq_flag=0) & (src_sign=1)\ngt_flag ←(eq_flag=0) & (src_sign=0)\ninv_flag ←false\nox_flag ←false\ndo i = 0 to 23\n ox_flag ←ox_flag | (VSR[VRB+32].nibble[i] != 0x0)\nend\ndo i = 0 to 30\n inv_flag ←inv_flag | (VSR[VRB+32].nibble[i] > 0x9)\nend\nif inv_flag then\n VSR[VRT+32] ←undefined\nelse\n do i = 0 to 6\n result.hword[i].nibble[0:2] ←0x003\n result.hword[i].nibble[3] ←VSR[VRB+32].nibble[i+24]\n end\n result.hword[7] ←(src_sign=1) ? 0x002D : 0x002B\n VSR[VRT+32] ←result\nend\nCR.bit[56] ←inv_flag ? 0b0 : lt_flag\nCR.bit[57] ←inv_flag ? 0b0 : gt_flag\nCR.bit[58] ←inv_flag ? 0b0 : eq_flag\nCR.bit[59] ←inv_flag | ox_flag", "special_registers": "CR6", "page_found": "Page 505 - 506", "programming_notes": "The bcdctn. instruction is used to convert packed decimal values into national decimal format, updating CR6 with flags indicating the result's validity and sign. Ensure VSR[VRB+32] contains valid packed decimal data; otherwise, VSR[VRT+32] will be undefined. This instruction requires vector mode enabled (MSR.VEC=1) and operates at user privilege level.", "example": "bcdctn. vd, vb" }, { "mnemonic": "bcdcfz.", "architecture": "PowerISA", "full_name": "Decimal Convert from Zoned", "summary": "Converts BCD Zoned format to Signed Packed BCD.", "syntax": "bcdcfz. vD, vB, PS", "encoding": { "format": "VX-form", "binary_pattern": "4 | VRT | 6 | VRB | 1 | PS | 385", "hex_opcode": "0x10060581", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "1", "clean": "1" }, { "raw": "vB", "clean": "vB" }, { "raw": "1217", "clean": "1217" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:29 | 30 | 31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "PS", "desc": "Sign" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "Vector BCD", "description": "The bcdcfz. instruction converts a zoned decimal value in VSR[VRB+32] to a packed decimal format and stores the result in VSR[VRT+32]. The conversion is based on the sign code and digit values of the source operand.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ninv_flag ← ((VSR[VRB+32].byte[15].nibble[0] < 0xA) & (PS=1)) | (VSR[VRB+32].byte[15].nibble[1] > 0x9)\nMIN ← (PS=0) ? 0x30 : 0xF0\nMAX ← (PS=0) ? 0x39 : 0xF9\ndo i = 0 to 14\n inv_flag ← inv_flag | (VSR[VRB+32].byte[i] < MIN) | (VSR[VRB+32].byte[i] > MAX)\nend\nif PS=0 then\n src_sign ← VSR[VRB+32].nibble[30].bit[1]\nelse\n src_sign ← (VSR[VRB+32].nibble[30] = 0b1011) | (VSR[VRB+32].nibble[30] = 0b1101)\neq_flag ← 1\ndo i = 0 to 14\n result.nibble[i] ← 0x0\nend\ndo i = 0 to 15\n result.nibble[i+15] ← VSR[VRB+32].byte[i].nibble[1]\n eq_flag ← eq_flag & (VSR[VRB+32].byte[i].nibble[1]=0x0)\nend\nlt_flag ← (eq_flag=0) & (src_sign=1)\ngt_flag ← (eq_flag=0) & (src_sign=0)\nresult.nibble[31] ← (src_sign=0) ? 0xC : 0xD\nCR.bit[56] ← inv_flag ? 0b0 : lt_flag\nCR.bit[57] ← inv_flag ? 0b0 : gt_flag\nCR.bit[58] ← inv_flag ? 0b0 : eq_flag\nCR.bit[59] ← inv_flag\nVSR[VRT+32] ← inv_flag ? undefined : result", "special_registers": "CR6", "page_found": "Page 504 - 505", "programming_notes": "The bcdcfz. instruction is used to convert zoned decimal values to packed decimal format. Ensure that the source vector register (VRB) contains valid zoned decimal data, as invalid input can lead to undefined results and set the CR6 flags accordingly. This instruction operates at the user privilege level and requires the Vector Facility to be enabled; otherwise, a Vector_Unavailable exception is raised.", "example": "bcdcfz. vd, vb, 0" }, { "mnemonic": "bcdctz.", "architecture": "PowerISA", "full_name": "Decimal Convert to Zoned", "summary": "Converts Signed Packed BCD to Zoned format.", "syntax": "bcdctz. vD, vB, PS", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 1 | vB | 1217", "hex_opcode": "0x10040581", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "1", "clean": "1" }, { "raw": "vB", "clean": "vB" }, { "raw": "1217", "clean": "1217" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "PS", "desc": "Sign" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "Vector BCD", "description": "The contents of each nibble 0-30 must be a value in the range 0x0 to 0x9. Packed decimal values with sign codes of 0xA, 0xC, 0xE, or 0xF are interpreted as positive values. Packed decimal values with sign codes of 0xB or 0xD are interpreted as negative values.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ninv_flag ←(VSR[VRB+32].nibble[31] < 0xA)\ndo i = 0 to 30\n inv_flag ←inv_flag | (VSR[VRB+32].nibble[i] > 0x9)\nox_flag ←0\ndo i = 0 to 15\n ox_flag ←ox_flag | (VSR[VRB+32].nibble[i] != 0x0)\nsrc_sign ←(VSR[VRB+32].nibble[31] = 0xB) | (VSR[VRB+32].nibble[31] = 0xD)\neq_flag ←(VSR[VRB+32].nibble[0:30] = 0)\nlt_flag ←(eq_flag=0) & (src_sign=1)\ngt_flag ←(eq_flag=0) & (src_sign=0)\ndo i = 0 to 14\n result.byte[i].nibble[0] ←(PS=0) ? 0x3 : 0xF\n result.byte[i].nibble[1] ←VSR[VRB+32].nibble[i+15]\nend\nif src.sign=0 then\n result.byte[15].nibble[0] ←(PS=0) ? 0x3 : 0xC\nelse\n result.byte[15].nibble[0] ←(PS=0) ? 0x7 : 0xD\nend\nresult.byte[15].nibble[1] ←VSR[VRB+32].nibble[30]\nVSR[VRT+32] ←inv_flag ? undefined : result\nCR.bit[56] ←inv_flag ? 0b0 : lt_flag\nCR.bit[57] ←inv_flag ? 0b0 : gt_flag\nCR.bit[58] ←inv_flag ? 0b0 : eq_flag\nCR.bit[59] ←inv_flag | ox_flag", "special_registers": "CR6", "page_found": "Page 506 - 507", "programming_notes": "The bcdctz. instruction converts packed decimal values to zoned format, interpreting sign codes and handling invalid nibble values. Ensure that the input data is correctly formatted with valid nibbles (0x0-0x9) and appropriate sign codes. The instruction operates on vector registers and requires the Vector Facility to be enabled; otherwise, it raises a Vector Unavailable exception. Check the condition register bits for flags indicating invalid input, less than, greater than, or equal conditions.", "example": "bcdctz. vd, vb, 0" }, { "mnemonic": "bcdcfsq.", "architecture": "PowerISA", "full_name": "Decimal Convert from Signed Quadword", "summary": "Converts a signed quadword integer to packed decimal format and updates the condition register.", "syntax": "bcdcfsq. vD, vB, PS", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | 1 | vB | 193", "hex_opcode": "0x10020581", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "1", "clean": "1" }, { "raw": "vB", "clean": "vB" }, { "raw": "193", "clean": "193" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "PS", "desc": "Sign" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "Vector BCD", "description": "The bcdcfsq. instruction converts a signed quadword integer from VSR[VRB+32] to packed decimal format and stores it in VSR[VRT+32]. It also updates the condition register CR6 based on the conversion result.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\n\nox_flag ←(EXTS(VSR[VRB+32]) > 1031-1) |\n (EXTS(VSR[VRB+32]) < -(1031-1))\nlt_flag ←(EXTS(VSR[VRB+32]) < 0)\ngt_flag ←(EXTS(VSR[VRB+32]) > 0)\neq_flag ←(EXTS(VSR[VRB+32]) = 0)\n\nif ox_flag=0 then\n result ←bcd_CONVERT_FROM_SI128(EXTS(VSR[VRB+32]),PS)\nelse\n result ←0xUUUU_UUUU_UUUU_UUUU_UUUU_UUUU_UUUU_UUUU\n\nVSR[VRT+32] ←ox_flag ? undefined : result\n\nCR.bit[56] ←lt_flag\nCR.bit[57] ←gt_flag\nCR.bit[58] ←eq_flag\nCR.bit[59] ←ox_flag", "special_registers": "CR0, CR1-CR7, XER, LR, CTR", "page_found": "Page 507 - 508", "programming_notes": "The bcdcfsq. instruction is used to convert a signed quadword integer to packed decimal format, storing the result in VSR[VRT+32]. It updates CR6 with flags indicating overflow (OX), less than (LT), greater than (GT), and equal (EQ) conditions. Ensure that the Vector Facility is enabled by checking MSR.VEC before using this instruction. Be cautious of overflow conditions, as they result in an undefined value being stored.", "example": "bcdcfsq. vd, vb, 0" }, { "mnemonic": "bcdctsq.", "architecture": "PowerISA", "full_name": "Binary Coded Decimal Compare and Test Sign Quadword", "summary": "Compares two binary coded decimal (BCD) numbers in a quadword format and tests the sign.", "syntax": "bcdctsq. vD, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | VRT | 0 | VRB | 1 | / | 385", "hex_opcode": "0x10000581", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "193", "clean": "193" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:29 | 30 | 31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "RB", "desc": "Source General Purpose Register" } ], "extension": "Vector BCD", "description": "The instruction converts the packed decimal value in VSR[VRB+32] to a signed integer and places it into VSR[VRT+32]. The sign code must be within the range 0xA to 0xF, with specific interpretations for positive and negative values. If the input is invalid, the result is undefined.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ninv_flag ←(VSR[VRB+32].nibble[31] < 0xA)\ndo i = 0 to 30\n inv_flag ←inv_flag | (VSR[VRB+32].nibble[i] > 0x9)\nsrc_sign ←(VSR[VRB+32].nibble[31] = 0xB) | (VSR[VRB+32].nibble[31] = 0xD)\neq_flag ←(VSR[VRB+32].nibble[0:30] = 0)\nlt_flag ←(eq_flag=0) & (src_sign=1)\ngt_flag ←(eq_flag=0) & (src_sign=0)\nresult ←si128_CONVERT_FROM_BCD(VSR[VRB+32])\nVSR[VRT+32] ←inv_flag ? undefined : result\nCR.bit[56] ←inv_flag ? 0b0 : lt_flag\nCR.bit[57] ←inv_flag ? 0b0 : gt_flag\nCR.bit[58] ←inv_flag ? 0b0 : eq_flag\nCR.bit[59] ←inv_flag", "special_registers": "CR6", "page_found": "Page 508 - 509", "programming_notes": "The bcdctsq. instruction is used to convert a packed decimal value to a signed integer, storing the result in VSR[VRT+32]. Ensure the input sign code is within 0xA to 0xF; otherwise, the result is undefined. The instruction sets condition register bits CR6 based on comparison results, but these are only valid if the input is not invalid.", "example": "bcdctsq. vd, vb" }, { "mnemonic": "mulhd", "architecture": "PowerISA", "full_name": "Multiply High Doubleword", "summary": "Multiplies two 64-bit integers and returns the upper 64 bits of the 128-bit result (Signed).", "syntax": "mulhd RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "31 | RT | RA | RB | OE | 73 | Rc", "hex_opcode": "0x7C000092", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "OE", "clean": "OE" }, { "raw": "73", "clean": "73" }, { "raw": "Rc", "clean": "Rc" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21 | 22:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RA", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Base", "description": "Multiplies two 64-bit signed integers (RA and RB) and stores the upper 64 bits of the 128-bit signed result in RT. The overflow flag (OE) is not typically set by this instruction as it returns the mathematically correct upper bits. If Rc=1, CR0 is updated based on the result.", "pseudocode": "prod ← (RA) *s (RB); RT ← prod[64:127]; if Rc then CR0 ← (RT < 0, RT > 0, RT = 0, SO)", "page_found": "Page 121", "special_registers": "CR0", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.", "example": "mulhd r3, r4, r5" }, { "mnemonic": "mulhdu", "architecture": "PowerISA", "full_name": "Multiply High Doubleword Unsigned", "summary": "Multiplies two 64-bit integers and returns the upper 64 bits of the 128-bit result (Unsigned).", "syntax": "mulhdu RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "31 | RT | RA | RB | OE | 9 | Rc", "hex_opcode": "0x7C000012", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "OE", "clean": "OE" }, { "raw": "9", "clean": "9" }, { "raw": "Rc", "clean": "Rc" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21 | 22:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RA", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Base", "description": "Multiplies two 64-bit unsigned integers (RA and RB) and stores the upper 64 bits of the 128-bit unsigned result in RT. The overflow flag is not set as the full 128-bit product is well-defined for unsigned multiplication. If Rc=1, CR0 is updated based on the result.", "pseudocode": "prod ← (RA) *u (RB); RT ← prod[64:127]; if Rc then CR0 ← (RT < 0, RT > 0, RT = 0, SO)", "page_found": "Page 121", "special_registers": "CR0", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.", "example": "mulhdu r3, r4, r5" }, { "mnemonic": "mulhw", "architecture": "PowerISA", "full_name": "Multiply High Word", "summary": "Multiplies two 32-bit integers and returns the upper 32 bits (Signed).", "syntax": "mulhw RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "31 | RT | RA | RB | OE | 75 | Rc", "hex_opcode": "0x7C000096", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "OE", "clean": "OE" }, { "raw": "75", "clean": "75" }, { "raw": "Rc", "clean": "Rc" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21 | 22:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RA", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Base", "description": "Multiplies two 32-bit signed integers (RA[32:63] and RB[32:63]) and stores the upper 32 bits of the 64-bit signed result in RT[32:63], with RT[0:31] undefined. If Rc=1, CR0 is updated based on the result. No overflow is recorded.", "pseudocode": "prod ← (RA[32:63]) *s (RB[32:63]); RT[32:63] ← prod[32:63]; if Rc then CR0 ← (RT[32:63] < 0, RT[32:63] > 0, RT[32:63] = 0, SO)", "page_found": "Page 115", "special_registers": "CR0", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.", "example": "mulhw r3, r4, r5" }, { "mnemonic": "mulhwu", "architecture": "PowerISA", "full_name": "Multiply High Word Unsigned", "summary": "Multiplies two 32-bit integers and returns the upper 32 bits (Unsigned).", "syntax": "mulhwu RT, RA, RB", "encoding": { "format": "XO-form", "binary_pattern": "31 | RT | RA | RB | OE | 11 | Rc", "hex_opcode": "0x7C000016", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "OE", "clean": "OE" }, { "raw": "11", "clean": "11" }, { "raw": "Rc", "clean": "Rc" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21 | 22:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RA", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Base", "description": "Multiplies two 32-bit unsigned integers (RA[32:63] and RB[32:63]) and stores the upper 32 bits of the 64-bit unsigned result in RT[32:63], with RT[0:31] undefined. If Rc=1, CR0 is updated based on the result.", "pseudocode": "prod ← (RA[32:63]) *u (RB[32:63]); RT[32:63] ← prod[32:63]; if Rc then CR0 ← (RT[32:63] < 0, RT[32:63] > 0, RT[32:63] = 0, SO)", "page_found": "Page 115", "special_registers": "CR0", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.", "example": "mulhwu r3, r4, r5" }, { "mnemonic": "divsq", "architecture": "PowerISA", "full_name": "Divide Signed Quadword", "summary": "Divides a 128-bit signed integer by a 128-bit signed integer (using VSX pairs).", "syntax": "divsq vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 265", "hex_opcode": "0x10000109", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "265", "clean": "265" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Dividend" }, { "name": "vB", "desc": "Divisor" } ], "extension": "Base", "description": "Divides a 128-bit signed integer dividend (vA) by a 128-bit signed integer divisor (vB) and stores the 128-bit signed quotient in vD. This instruction operates on VSX vector register pairs and is part of the Base category with extended integer support. Division by zero results in undefined behavior; no overflow exception is generated.", "pseudocode": "vD ← (vA) /s (vB)", "example": "divsq vd, va, vb" }, { "mnemonic": "divuq", "architecture": "PowerISA", "full_name": "Divide Unsigned Quadword", "summary": "Divides a 128-bit unsigned integer by a 128-bit unsigned integer.", "syntax": "divuq vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 9", "hex_opcode": "0x10000009", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "9", "clean": "9" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Dividend" }, { "name": "vB", "desc": "Divisor" } ], "extension": "Base", "description": "Divides a 128-bit unsigned integer (vA) by a 128-bit unsigned integer (vB), storing the 128-bit unsigned quotient in vD. This is a VSX or MMA category instruction that performs quadword division. If division by zero is attempted, the result is undefined.", "pseudocode": "vD ← vA ÷ vB (128-bit unsigned integer division)", "example": "divuq vd, va, vb" }, { "mnemonic": "modsq", "architecture": "PowerISA", "full_name": "Modulo Signed Quadword", "summary": "Computes remainder of 128-bit signed division.", "syntax": "modsq vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 267", "hex_opcode": "0x1000070B", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "267", "clean": "267" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Dividend" }, { "name": "vB", "desc": "Divisor" } ], "extension": "Base", "description": "Computes the remainder of a 128-bit signed integer division, storing the 128-bit signed remainder in vD. This is a VSX or MMA category instruction. The operation uses the dividend (vA) and divisor (vB) to compute the modulo result, with sign following the dividend.", "pseudocode": "vD ← vA mod vB (128-bit signed integer modulo)", "example": "modsq vd, va, vb" }, { "mnemonic": "moduq", "architecture": "PowerISA", "full_name": "Modulo Unsigned Quadword", "summary": "Computes remainder of 128-bit unsigned division.", "syntax": "moduq vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 11", "hex_opcode": "0x1000000B", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "11", "clean": "11" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31", "length": "32" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Dividend" }, { "name": "vB", "desc": "Divisor" } ], "extension": "Base", "description": "Computes the remainder of a 128-bit unsigned integer division, storing the 128-bit unsigned remainder in vD. This is a VSX or MMA category instruction. The operation uses the dividend (vA) and divisor (vB) to compute the modulo result.", "pseudocode": "vD ← vA mod vB (128-bit unsigned integer modulo)", "example": "moduq vd, va, vb" }, { "mnemonic": "lhzci", "architecture": "PowerISA", "full_name": "Load Halfword and Zero Caching Inhibited", "summary": "Loads a halfword bypassing the cache.", "syntax": "lhzci RT, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | RA | RB | 886 | /", "hex_opcode": "0x7C0006EA", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "886", "clean": "886" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Base", "description": "Loads an unsigned halfword (16 bits) from memory at address (RA + RB) with caching inhibited, zero-extending the result to 64 bits in RT. This instruction bypasses the cache and is used for memory-mapped I/O. No condition registers are affected.", "pseudocode": "EA ← (RA) + (RB); RT ← 0x000000000000ZZZZ where ZZZZ = [EA]", "example": "lhzci r3, r4, r5" }, { "mnemonic": "lwzci", "architecture": "PowerISA", "full_name": "Load Word and Zero Caching Inhibited", "summary": "Loads a word bypassing the cache.", "syntax": "lwzci RT, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | RA | RB | 855 | /", "hex_opcode": "0x7C0006AB", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "855", "clean": "855" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Base", "description": "Loads an unsigned word (32 bits) from memory at address (RA + RB) with caching inhibited, zero-extending the result to 64 bits in RT. This instruction bypasses the cache and is commonly used for memory-mapped I/O device access. No condition registers are affected.", "pseudocode": "EA ← (RA) + (RB); RT ← 0x00000000ZZZZZZZZ where ZZZZZZZZ = [EA]", "example": "lwzci r3, r4, r5" }, { "mnemonic": "ldci", "architecture": "PowerISA", "full_name": "Load Doubleword Caching Inhibited", "summary": "Loads a doubleword bypassing the cache.", "syntax": "ldci RT, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | RA | RB | 887 | /", "hex_opcode": "0x7C0006EB", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "887", "clean": "887" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Base", "description": "Loads a doubleword (64 bits) from memory at address (RA + RB) with caching inhibited, storing the result in RT. This instruction bypasses the cache hierarchy and is used for memory-mapped I/O operations in 64-bit mode. No condition registers are affected.", "pseudocode": "EA ← (RA) + (RB); RT ← [EA]", "example": "ldci r3, r4, r5" }, { "mnemonic": "stbci", "architecture": "PowerISA", "full_name": "Store Byte Caching Inhibited", "summary": "Stores a byte bypassing the cache.", "syntax": "stbci RS, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 982 | /", "hex_opcode": "0x7C0007AE", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "982", "clean": "982" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RS", "desc": "Source" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Base", "description": "Stores the low-order byte from RS to memory at address (RA + RB) with caching inhibited. This instruction bypasses the cache hierarchy and is typically used for memory-mapped I/O operations. No condition registers are affected.", "pseudocode": "EA ← (RA) + (RB); [EA] ← (RS)[56:63]", "example": "stbci r3, r4, r5" }, { "mnemonic": "sthci", "architecture": "PowerISA", "full_name": "Store Halfword Caching Inhibited", "summary": "Stores a halfword bypassing the cache.", "syntax": "sthci RS, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 1014 | /", "hex_opcode": "0x7C0007EE", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "1014", "clean": "1014" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RS", "desc": "Source" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Base", "description": "Store a halfword from register RS to memory at address (RA + RB), with cache inhibit semantics to bypass the L1 data cache. The halfword is written directly to L2 or memory depending on cache hierarchy. This instruction requires cache-inhibited access and is typically used for memory-mapped I/O or special memory regions.", "pseudocode": "addr ← (RA) + (RB)\n[(addr)] ← (RS)[48:63]\nMemory write with cache inhibit attribute", "example": "sthci r3, r4, r5" }, { "mnemonic": "stwci", "architecture": "PowerISA", "full_name": "Store Word Caching Inhibited", "summary": "Stores a word bypassing the cache.", "syntax": "stwci RS, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 983 | /", "hex_opcode": "0x7C0007AF", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "983", "clean": "983" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RS", "desc": "Source" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Base", "description": "Store a word from register RS to memory at address (RA + RB), with cache inhibit semantics to bypass the L1 data cache. The word is written directly to L2 or memory. This instruction is used for memory-mapped I/O or device registers where cache bypass is required.", "pseudocode": "addr ← (RA) + (RB)\n[(addr)] ← (RS)[32:63]\nMemory write with cache inhibit attribute", "example": "stwci r3, r4, r5" }, { "mnemonic": "stdci", "architecture": "PowerISA", "full_name": "Store Doubleword Caching Inhibited", "summary": "Stores a doubleword bypassing the cache.", "syntax": "stdci RS, RA, RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 1015 | /", "hex_opcode": "0x7C0007EF", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "1015", "clean": "1015" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RS", "desc": "Source" }, { "name": "RA", "desc": "Base" }, { "name": "RB", "desc": "Index" } ], "extension": "Base", "description": "Store a doubleword from register RS to memory at address (RA + RB), with cache inhibit semantics to bypass the L1 data cache. The doubleword is written directly to L2 or memory. This instruction is used for memory-mapped I/O operations requiring full 64-bit cache-bypassed writes.", "pseudocode": "addr ← (RA) + (RB)\n[(addr)] ← (RS)[0:63]\nMemory write with cache inhibit attribute", "example": "stdci r3, r4, r5" }, { "mnemonic": "cp_abort", "architecture": "PowerISA", "full_name": "Copy-Paste Abort", "summary": "Aborts a hardware accelerator copy-paste sequence.", "syntax": "cp_abort", "encoding": { "format": "X-form", "binary_pattern": "31 | 0 | 0 | 0 | 450 | /", "hex_opcode": "0x7C000382", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "450", "clean": "450" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [], "extension": "Privileged", "description": "Abort an ongoing copy-paste sequence initiated by a prior COPY instruction. This privileged instruction clears the copy-paste state, terminating any in-flight hardware accelerator operation. It is typically used in exception handlers or during context switches to ensure no stale copy-paste state persists.", "pseudocode": "Copy-paste buffer state ← cleared\nAny pending copy-paste operation ← aborted", "example": "cp_abort" }, { "mnemonic": "mcrxrx", "architecture": "PowerISA", "full_name": "Move to Condition Register from XER Extended", "summary": "Copies the contents of the XER register fields OV, OV32, CA, and CA32 to the specified condition register field.", "syntax": "mcrxrx BF", "encoding": { "format": "X-form", "binary_pattern": "0 | BF | // | RS | FXM | //", "hex_opcode": "0x7C000480", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "BF", "clean": "BF" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "512", "clean": "512" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "BF", "desc": "Target CR Field" }, { "name": "RS", "desc": "Source General Purpose Register" } ], "extension": "Base", "description": "The contents of the OV, OV32, CA, and CA32 are copied to Condition Register field BF. The contents of bits 32:63 of register RS are placed into the Condition Register under control of the field mask specified by FXM.", "pseudocode": "mask ←4(FXM0) || 4(FXM1) || ... 4(FXM7)\nCR ←((RS)32:63 & mask) | (CR & ¬mask)", "special_registers": "CR, XER", "page_found": "Page 164 - 166", "programming_notes": "The mcrxrx instruction is used to transfer specific bits from the XER register into the Condition Register. Ensure that the FXM field correctly specifies which bits of RS should be moved to CR, as incorrect masking can lead to unexpected results. This instruction operates at user privilege level and does not generate exceptions under normal conditions.", "example": "mcrxrx cr0" }, { "mnemonic": "scv", "architecture": "PowerISA", "full_name": "System Call Vectored", "summary": "Performs a system call to a fixed vector address (Faster than 'sc').", "syntax": "scv LEV", "encoding": { "format": "SC-form", "binary_pattern": "0 | 6 | 11 | 16 | 20 | 27 | 30 | 31", "hex_opcode": "0x44000001", "visual_parts": [ { "raw": "17", "clean": "17" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "LEV", "clean": "LEV" }, { "raw": "/", "clean": "/" }, { "raw": "1", "clean": "1" } ], "length": "32", "bit_positions": "0 | 6 | 11 | 16 | 20 | 27 | 30 | 31" }, "operands": [ { "name": "LEV", "desc": "Level" } ], "extension": "Base", "description": "Perform a system call with a vectored trap to a fixed address determined by the LEV (level) field, providing faster dispatch than the traditional sc instruction. The instruction saves SRR0 and SRR1, sets MSR[PR]=0 to enter privileged mode, and jumps to the system call vector. LEV is a 7-bit field (bits 20-26) that selects among up to 128 vector addresses.", "pseudocode": "SRR0 ← CIA + 4\nSRR1 ← MSR\nMSR[PR] ← 0\nMSR[EE] ← 0\nMSR[IR] ← 0\nMSR[DR] ← 0\nPC ← Interrupt Vector Base + (LEV << 7) + System Call Vectored Offset", "special_registers": "LR, CTR, MSR", "programming_notes": "If this instruction sets MSRPR to 1, it also sets MSREE, MSRIR, and MSRDR to 1. If this instruction results in MSRS HV PR being equal to 0b110, it also sets MSRIR and MSRDR to 0.\n\nThis instruction does not alter MSRHV, MSRS, or MSRME.", "page_found": "Page 1120 - 1121", "example": "scv 0" }, { "mnemonic": "rfscv", "architecture": "PowerISA", "full_name": "Return from System Call Vectored", "summary": "Returns from a vectored system call.", "syntax": "rfscv", "encoding": { "format": "XL-form", "binary_pattern": "19 | / | / | / | 82 | /", "hex_opcode": "0x4C0000A4", "visual_parts": [ { "raw": "19", "clean": "19" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "82", "clean": "82" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [], "extension": "Privileged", "description": "Return from a vectored system call by restoring the processor state from SRR0 and SRR1. This privileged instruction restores PC from SRR0 and MSR from SRR1, typically returning to user mode if MSR[PR] was set in the saved state. It is the inverse of scv.", "pseudocode": "PC ← SRR0\nMSR ← SRR1", "page_found": "Page 1121", "special_registers": "SRR0, SRR1, MSR", "programming_notes": "The rfscv instruction is used to return from a system call vectored, restoring the program's execution context by setting the CIA to the value in SRR0 and the MSR from SRR1. Ensure that this instruction is executed at the appropriate privilege level and be aware of any potential exceptions or performance implications related to restoring the machine state.", "example": "rfscv" }, { "mnemonic": "stop", "architecture": "PowerISA", "full_name": "Stop", "summary": "Stops instruction execution and enters a power-saving state (replaces nap/doze on P9+).", "syntax": "stop", "encoding": { "format": "X-form", "binary_pattern": "19 | / | / | / | 722 | /", "hex_opcode": "0x4C0002E4", "visual_parts": [ { "raw": "19", "clean": "19" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "722", "clean": "722" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [], "extension": "Privileged", "description": "The thread is placed into power-saving mode and execution is stopped. The power-saving level that is entered is determined by the contents of the PSSCR. The thread remains in power-saving mode until either a System Reset exception or certain other events occur.", "programming_notes": "This instruction should not be executed in ultravisor state because that scenario may not be thoroughly verified. This instruction is privileged and context synchronizing.", "page_found": "Page 1124 - 1125", "pseudocode": "PSSCR ← (PSSCR & ~0x3F) | power-saving-level\nstop", "special_registers": "PSSCR", "example": "stop" }, { "mnemonic": "urfid", "architecture": "PowerISA", "full_name": "Ultravisor Return from Interrupt Doubleword", "summary": "Returns from an ultravisor interrupt.", "syntax": "urfid", "encoding": { "format": "XL-form", "binary_pattern": "19 | / | / | / | 274 | /", "hex_opcode": "0x4C000264", "visual_parts": [ { "raw": "19", "clean": "19" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "274", "clean": "274" }, { "raw": "/", "clean": "/" } ], "length": "64", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31:63" }, "operands": [], "extension": "Privileged", "description": "The 'urfid' instruction is used to return from an interrupt in the ultravisor context. It updates the Machine State Register (MSR) and sets the next instruction address based on the values in USRR0 and USRR1.", "pseudocode": "MSR48 ← USRR148 | USRR149\nMSR58 ← (USRR158 | USRR149) & ¬(USRR141 & USRR13 & (¬USRR149))\nMSR59 ← (USRR159 | USRR149) & ¬(USRR141 & USRR13 & (¬USRR149))\nMSR0:32 37:41 49:57 60:63 ← USRR10:32 37:41 49:57 60:63\nNIA ← iea USRR00:61 || 0b00", "special_registers": "MSR, SRR0, SRR1", "programming_notes": "If this instruction sets MSRPR to 1, it also sets MSREE, MSRIR, and MSRDR to 1. If this instruction sets MSRS HV PR to 0b110, it also sets MSRIR and MSRDR to 0.", "page_found": "Page 1122 - 1123", "example": "urfid" }, { "mnemonic": "setbc", "architecture": "PowerISA", "full_name": "Set Boolean Condition", "summary": "Sets RT to 1 if CR bit is set, else 0. (Branchless logic).", "syntax": "setbc RT, BI", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | BI | / | 384 | /", "hex_opcode": "0x7C000300", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "BI", "clean": "BI" }, { "raw": "/", "clean": "/" }, { "raw": "384", "clean": "384" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "BI", "desc": "CR Bit" } ], "extension": "Base", "description": "Set register RT to 1 if the condition register bit identified by BI is set, else set RT to 0. This instruction provides a branchless way to materialize a boolean value from a condition register bit, useful for conditional assignment without branching.", "pseudocode": "if CR[BI] = 1 then\n RT ← 1\nelse\n RT ← 0", "page_found": "Page 167", "special_registers": "CR", "programming_notes": "The setbc instruction is useful for conditionally setting a register based on the state of a specific bit in the Condition Register. Ensure that the correct bit index BI is specified to avoid unintended behavior. This instruction operates at user privilege level and does not generate exceptions under normal conditions.", "example": "setbc r3, 0" }, { "mnemonic": "setbcr", "architecture": "PowerISA", "full_name": "Set Boolean Condition Reverse", "summary": "Sets RT to 1 if CR bit is clear, else 0.", "syntax": "setbcr RT, BI", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | BI | / | 416 | /", "hex_opcode": "0x7C000340", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "BI", "clean": "BI" }, { "raw": "/", "clean": "/" }, { "raw": "416", "clean": "416" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "BI", "desc": "CR Bit" } ], "extension": "Base", "description": "Set register RT to 1 if the condition register bit identified by BI is clear (0), else set RT to 0. This is the logical inverse of setbc, allowing branchless negation of a condition register bit test.", "pseudocode": "if CR[BI] = 0 then\n RT ← 1\nelse\n RT ← 0", "page_found": "Page 167", "special_registers": "CR", "programming_notes": "The setbcr instruction is useful for setting a register based on the state of a specific bit in the Condition Register. Ensure that the correct bit index BI is specified to avoid unintended behavior. This instruction operates at user privilege level and does not generate exceptions under normal conditions.", "example": "setbcr r3, 0" }, { "mnemonic": "setnbc", "architecture": "PowerISA", "full_name": "Set Negative Boolean Condition", "summary": "Sets RT to -1 if CR bit is set, else 0.", "syntax": "setnbc RT, BI", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | BI | / | 448 | /", "hex_opcode": "0x7C000380", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "BI", "clean": "BI" }, { "raw": "/", "clean": "/" }, { "raw": "448", "clean": "448" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "BI", "desc": "CR Bit" } ], "extension": "Base", "description": "Sets the target GPR to -1 (all bits set) if the specified condition register bit is set, otherwise sets it to 0. This instruction operates entirely on the CR and target register, with no side effects on other status fields.", "pseudocode": "if CR[BI] = 1 then RT ← -1 else RT ← 0", "page_found": "Page 167", "special_registers": "CR", "programming_notes": "Use setnbc to conditionally set a register based on a specific bit in the Condition Register. Ensure CRBI is within valid range; otherwise, results are undefined. This instruction operates at user privilege level and does not generate exceptions under normal conditions.", "example": "setnbc r3, 0" }, { "mnemonic": "setnbcr", "architecture": "PowerISA", "full_name": "Set Negative Boolean Condition Reverse", "summary": "Sets RT to -1 if CR bit is clear, else 0.", "syntax": "setnbcr RT, BI", "encoding": { "format": "X-form", "binary_pattern": "31 | RT | BI | / | 480 | /", "hex_opcode": "0x7C0003C0", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "BI", "clean": "BI" }, { "raw": "/", "clean": "/" }, { "raw": "480", "clean": "480" }, { "raw": "/", "clean": "/" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "BI", "desc": "CR Bit" } ], "extension": "Base", "description": "Sets the target GPR to -1 (all bits set) if the specified condition register bit is clear, otherwise sets it to 0. This is the logical inverse of setnbc, with no side effects on other status fields.", "pseudocode": "if CR[BI] = 0 then RT ← -1 else RT ← 0", "page_found": "Page 167", "special_registers": "CR", "programming_notes": "Use setnbcr when you need to invert a condition bit in the Condition Register into a boolean value. Ensure that the target register RT is properly aligned and accessible. This instruction operates at user privilege level, so no special permissions are required. Be cautious of potential performance impacts if used in tight loops.", "example": "setnbcr r3, 0" }, { "mnemonic": "xscmpexpdp", "architecture": "PowerISA", "full_name": "VSX Scalar Compare Exponents Double-Precision", "summary": "Compares the exponents of two double-precision floating-point values in VSX registers and updates the condition register.", "syntax": "xscmpexpdp BF, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "60 | BF | / | XA | XB | 59", "hex_opcode": "0xF00001D8", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "BF", "clean": "BF" }, { "raw": "/", "clean": "/" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "59", "clean": "59" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "BF", "desc": "CR Field" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "The exponent of src1 is compared with the exponent of src2. The result of the compare is placed into FPCC and CR field BF.", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nsrc1 ←VSR[32×AX+A].dword[0]\nsrc2 ←VSR[32×BX+B].dword[0]\nsrc1.exponent ←EXTZ(src1.bit[1:11])\nsrc1.fraction ←EXTZ(src1.bit[12:63])\nsrc2.exponent ←EXTZ(src2.bit[1:11])\nsrc2.fraction ←EXTZ(src2.bit[12:63])\nsrc1.class.NaN ←(src1.exponent = 2047) & (src1.fraction != 0)\nsrc2.class.NaN ←(src2.exponent = 2047) & (src2.fraction != 0)\nlt_flag ←(src1.exponent < src2.exponent)\ngt_flag ←(src1.exponent > src2.exponent)\neq_flag ←(src1.exponent = src2.exponent)\nuo_flag ←src1.class.NaN | src2.class.NaN\nCR.bit[4×BF+32] ←FPSCR.FL ←!uo_flag & lt_flag\nCR.bit[4×BF+33] ←FPSCR.FG ←!uo_flag & gt_flag\nCR.bit[4×BF+34] ←FPSCR.FE ←!uo_flag & eq_flag\nCR.bit[4×BF+35] ←FPSCR.FU ←uo_flag", "special_registers": "CR, FPSCR", "programming_notes": "This instruction can be used to operate on single-precision source operands.", "page_found": "Page 897 - 898", "example": "xscmpexpdp cr0, vs2, vs3" }, { "mnemonic": "xsiexpdp", "architecture": "PowerISA", "full_name": "VSX Scalar Insert Exponent Double-Precision", "summary": "Inserts exponent from one double into another.", "syntax": "xsiexpdp XT, XA, XB", "encoding": { "format": "XX3-form", "binary_pattern": "60 | XT | XA | XB | 219", "hex_opcode": "0xF000072C", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "219", "clean": "219" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Significand" }, { "name": "XB", "desc": "Exponent" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "RB", "desc": "Source General Purpose Register" } ], "extension": "VSX", "description": "Inserts the exponent bits from XB (bits 0-10) into the exponent field of the significand in XA, placing the result in XT. This operation constructs a double-precision floating-point value by combining a significand with a new exponent. Requires VSX support.", "pseudocode": "XT ← (XA[0:51] || XB[0:10])", "special_registers": "VSR[XT]", "programming_notes": "This instruction can be used to produce a single-precision result. Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.", "page_found": "Page 899 - 900", "example": "xsiexpdp vs1, vs2, vs3" }, { "mnemonic": "xsxexpdp", "architecture": "PowerISA", "full_name": "VSX Scalar Extract Exponent Double-Precision", "summary": "Extracts the exponent from a double-precision floating-point value in VSR and places it into GPR.", "syntax": "xsxexpdp XT, XB", "encoding": { "format": "XX2-form", "binary_pattern": "60 | XT | 0 | XB | 27", "hex_opcode": "0xF000056C", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "0", "clean": "0" }, { "raw": "XB", "clean": "XB" }, { "raw": "27", "clean": "27" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XB", "desc": "Source" }, { "name": "RT", "desc": "Target General Purpose Register" } ], "extension": "VSX", "description": "The instruction extracts the exponent field of a double-precision floating-point value located in the specified VSX register and stores it in a general-purpose register.", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nsrc ←VSR[32×BX+B].dword[0]\nGPR[RT] ←EXTZ64(src.bit[1:11])", "programming_notes": "This instruction can be used to operate on a single-precision source operand.", "page_found": "Page 904 - 905", "special_registers": "MSR", "example": "xsxexpdp vs1, vs3" }, { "mnemonic": "xsxsigdp", "architecture": "PowerISA", "full_name": "VSX Scalar Extract Significand Double-Precision", "summary": "Extracts the significand of a double-precision floating-point value from a VSX register and places it into a general-purpose register.", "syntax": "xsxsigdp XT, XB", "encoding": { "format": "XX2-form", "binary_pattern": "60 | XT | / | XB | 347 | BX | TX", "hex_opcode": "0xF001056C", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "0", "clean": "0" }, { "raw": "XB", "clean": "XB" }, { "raw": "11", "clean": "11" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:29 | 30 | 31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XB", "desc": "Source" }, { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "VS32", "desc": "Target Vector Register" }, { "name": "VS31", "desc": "Source Vector Register" } ], "extension": "VSX", "description": "Extracts the significand (mantissa) from a double-precision floating-point value in XB and places it as a 52-bit value into the lower half of XT, sign-extended. This instruction isolates the fractional part of the floating-point representation. Requires VSX support.", "pseudocode": "XT ← (0x0000000000000000 || significand(XB[32:63]))", "programming_notes": "This instruction can be used to operate on a single-precision source operand.", "page_found": "Page 905 - 906", "special_registers": "MSR", "example": "xsxsigdp vs1, vs3" }, { "mnemonic": "xststdcdp", "architecture": "PowerISA", "full_name": "VSX Scalar Test Data Class Double-Precision", "summary": "Tests the data class of a double-precision floating-point value in VSR[XB] and sets bits in CR field BF and FPCC accordingly.", "syntax": "xststdcdp BF, XB, DCM", "encoding": { "format": "XX2-form", "binary_pattern": "60 | BF | / | DCM | XB | 362", "hex_opcode": "0xF00005A8", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "BF", "clean": "BF" }, { "raw": "/", "clean": "/" }, { "raw": "DCM", "clean": "DCM" }, { "raw": "XB", "clean": "XB" }, { "raw": "362", "clean": "362" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "BF", "desc": "CR Field" }, { "name": "XB", "desc": "Source" }, { "name": "DCM", "desc": "Data Class Mask" }, { "name": "DCMX", "desc": "Data Class Mask" } ], "extension": "VSX", "description": "The instruction tests the data class of the double-precision floating-point value in VSR[XB].dword[0] and sets bits in CR field BF and FPCC based on the result.", "pseudocode": "if MSR.VSX=0 then\n VSX_Unavailable()\nsrc ← VSR[32×BX+B].dword[0]\nexponent ← src.bit[1:11]\nfraction ← src.bit[12:63]\nclass.NaN ← (exponent = 0x7FF) & (fraction != 0)\nclass.Infinity ← (exponent = 0x7FF) & (fraction = 0)\nclass.Zero ← (exponent = 0x000) & (fraction = 0)\nclass.Denormal ← (exponent = 0x000) & (fraction != 0)\nmatch ←\n (DCMX.bit[0] & class.NaN) |\n (DCMX.bit[2] & class.Infinity & sign) |\n (DCMX.bit[3] & class.Zero & !sign) |\n (DCMX.bit[4] & class.Zero & sign) |\n (DCMX.bit[5] & class.Denormal & !sign) |\n (DCMX.bit[6] & class.Denormal & sign)\nCR.bit[4×BF+32] ← FPSCR.FL ← src.sign\nCR.bit[4×BF+33] ← FPSCR.FG ← 0b0\nCR.bit[4×BF+34] ← FPSCR.FE ← match\nCR.bit[4×BF+35] ← FPSCR.FU ← 0b0", "special_registers": "CR, FPSCR", "page_found": "Page 901 - 902", "programming_notes": "This instruction is used to test the data class of a double-precision floating-point value. Ensure that VSX (Vector Scalar Extensions) is enabled in the MSR register, otherwise, an exception will be raised. The result updates both the CR and FPSCR registers, so check these for further processing. Be cautious with alignment; the source vector register must be properly aligned to avoid undefined behavior.", "example": "xststdcdp cr0, vs3, 0" }, { "mnemonic": "lxvp", "architecture": "PowerISA", "full_name": "Load VSX Vector Pair", "summary": "Loads a double quadword from memory into two VSX registers.", "syntax": "lxvp XT, DQ(RA)", "encoding": { "format": "DQ-form", "binary_pattern": "6 | Tp | TX | RA | DQ | 0", "hex_opcode": "0x18000000", "visual_parts": [ { "raw": "61", "clean": "61" }, { "raw": "XT", "clean": "XT" }, { "raw": "RA", "clean": "RA" }, { "raw": "DQ", "clean": "DQ" }, { "raw": "0", "clean": "0" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "XT", "desc": "Target Even VSR" }, { "name": "DQ", "desc": "Offset" }, { "name": "RA", "desc": "Base" }, { "name": "XTp", "desc": "Target Vector-Specific Register" }, { "name": "disp", "desc": "Displacement field" }, { "name": "VRT", "desc": "Target Vector-Specific Register" }, { "name": "EA", "desc": "Effective Address" } ], "extension": "VSX", "description": "Loads a 256-bit (32-byte) aligned vector pair from memory at the effective address (RA + DQ), storing the first 128 bits into XT and the second 128 bits into XT+1. DQ is a 4-bit field that specifies the offset in units of 16 bytes, requiring 16-byte alignment. Requires VSX support.", "pseudocode": "EA ← (RA) + (DQ << 4); XT ← [EA]; (XT+1) ← [EA+16]", "programming_notes": "For best performance, EA should be word-aligned.", "page_found": "Page 638 - 639", "special_registers": "MSR", "example": "lxvp vs1, 0(r4)" }, { "mnemonic": "stxvp", "architecture": "PowerISA", "full_name": "Store VSX Vector Pair", "summary": "Stores a pair of VSX vector registers to memory.", "syntax": "stxvp XS, DQ(RA)", "encoding": { "format": "DQ-form", "binary_pattern": "61 | XS | RA | DQ | 4", "hex_opcode": "0x18000001", "visual_parts": [ { "raw": "61", "clean": "61" }, { "raw": "XS", "clean": "XS" }, { "raw": "RA", "clean": "RA" }, { "raw": "DQ", "clean": "DQ" }, { "raw": "4", "clean": "4" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:27 | 28:31" }, "operands": [ { "name": "XS", "desc": "Source Even VSR" }, { "name": "DQ", "desc": "Offset" }, { "name": "RA", "desc": "Base" }, { "name": "XSp", "desc": "VSX Vector Register Pair" }, { "name": "disp", "desc": "Displacement Value" } ], "extension": "VSX", "description": "For stxvp, the effective address (EA) is the sum of the integer value in GPR[RA] or 0 if RA=0 and the value DQ||0b0000, sign-extended to 64 bits. The contents of VSR[XSp] concatenated with VSR[XSp+1] are stored into memory at address EA.", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nEAbase ←(RA=0) ? 0 : GPR[RA]\nEAdisp ←EXTS64(DQ || 0b0000)\nEA ←EAbase + EAdisp\nstore_data.bit[128:255] ←VSR[32×SX+2×Sp+1]\nMEM(EA,32) ←store_data", "programming_notes": "For best performance, EA should be word-aligned.", "page_found": "Page 640 - 641", "special_registers": "MSR", "example": "stxvp vs1, 0(r4)" }, { "mnemonic": "plxvp", "architecture": "PowerISA", "full_name": "Prefixed Load VSX Vector Pair", "summary": "Loads a 256-bit vector pair with 34-bit offset.", "syntax": "plxvp XT, D(RA), R", "encoding": { "format": "8LS:D-form", "binary_pattern": "1 | 2 | R | 0 | D0 | 58 | XT | RA | D1", "hex_opcode": "0x04000000E8000000", "visual_parts": [ { "raw": "000001", "clean": "000001" }, { "raw": "10", "clean": "10" }, { "raw": "0", "clean": "0" }, { "raw": "...", "clean": "..." }, { "raw": "58", "clean": "58" }, { "raw": "XT", "clean": "XT" }, { "raw": "...", "clean": "..." } ], "length": "64", "bit_positions": "0:5 | 6:7 | 8 | 9:13 | 14:31 | 32:37 | 38:42 | 43:47 | 48:63" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "D", "desc": "Offset" }, { "name": "RA", "desc": "Base" }, { "name": "R", "desc": "PC-Rel" } ], "extension": "Prefixed", "description": "Loads a 256-bit (32-byte) vector pair from memory using a 34-bit signed offset encoded as a 8-byte prefix + suffix. When R=0, the offset is relative to RA; when R=1, the offset is relative to the current instruction address. Requires VSX and Prefixed instruction support.", "pseudocode": "D ← EXTS(D0 || D1); EA ← (R=0 ? (RA) : NIA) + D; XT ← [EA]; (XT+1) ← [EA+16]", "page_found": "Page 639", "special_registers": "MSR", "programming_notes": "The plxvp instruction is used to load a pair of VSX vectors from memory into the VSRs. Ensure that the number of bytes specified in GPR[RB] does not exceed 16, as it will be clamped if it does. This instruction requires the VSX or Vector facility to be enabled in the MSR register, depending on the SX bit setting.", "example": "plxvp vs1, 0(r4), 0" }, { "mnemonic": "pstxvp", "architecture": "PowerISA", "full_name": "Prefixed Store VSX Vector Pair", "summary": "Stores a 256-bit vector pair with 34-bit offset.", "syntax": "pstxvp XS, D(RA), R", "encoding": { "format": "8LS:D-form", "binary_pattern": "1 | 2 | R | 0 | D0 | 62 | XS | RA | D1", "hex_opcode": "0x04000000F8000000", "visual_parts": [ { "raw": "000001", "clean": "000001" }, { "raw": "10", "clean": "10" }, { "raw": "0", "clean": "0" }, { "raw": "...", "clean": "..." }, { "raw": "62", "clean": "62" }, { "raw": "XS", "clean": "XS" }, { "raw": "...", "clean": "..." } ], "length": "64", "bit_positions": "0:5 | 6:7 | 8 | 9:13 | 14:31 | 32:37 | 38:42 | 43:47 | 48:63" }, "operands": [ { "name": "XS", "desc": "Source" }, { "name": "D", "desc": "Offset" }, { "name": "RA", "desc": "Base" }, { "name": "R", "desc": "PC-Rel" } ], "extension": "Prefixed", "description": "Stores a 256-bit (32-byte) vector pair from XS and XS+1 to memory using a 34-bit signed offset encoded as a 8-byte prefix + suffix. When R=0, the offset is relative to RA; when R=1, the offset is relative to the current instruction address. Requires VSX and Prefixed instruction support.", "pseudocode": "D ← EXTS(D0 || D1); EA ← (R=0 ? (RA) : NIA) + D; [EA] ← XS; [EA+16] ← (XS+1)", "page_found": "Page 641", "special_registers": "PC", "programming_notes": "The pstxvp instruction is used to store a VSX vector pair from the VSR registers to memory. It supports both prefixed and non-prefixed addressing modes. Ensure that the destination address is properly aligned for optimal performance. This instruction operates at privilege level 0.", "example": "pstxvp vs1, 0(r4), 0" }, { "mnemonic": "xscvhpdp", "architecture": "PowerISA", "full_name": "VSX Scalar Convert Half-Precision to Double-Precision format XX2-form", "summary": "Converts a half-precision floating-point value to a double-precision floating-point value.", "syntax": "xscvhpdp XT, XB", "encoding": { "format": "XX2-form", "binary_pattern": "T | 16 | B | 347 | BX TX", "hex_opcode": "0xF010056C", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "0", "clean": "0" }, { "raw": "XB", "clean": "XB" }, { "raw": "344", "clean": "344" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XB", "desc": "Source" } ], "extension": "VSX", "description": "The instruction converts the half-precision floating-point value in the rightmost halfword of doubleword element 0 of VSR[XB] to a double-precision floating-point value and places it into doubleword element 0 of VSR[XT]. Doubleword element 1 of VSR[XT] is set to 0.", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nreset_flags()\nsrc ←bfp_CONVERT_FROM_BFP16(VSR[BX×32+B].hword[3])\nif src.class.SNaN=1 then\n result ←bfp64_CONVERT_FROM_BFP(bfp_QUIET(src))\nelse\n result ←bfp64_CONVERT_FROM_BFP(src)\nvxsnan_flag ←src.class.SNaN\nif vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\nvex_flag ←FPSCR.VE & vxsnan_flag\nif vex_flag=0 then do\n VSR[TX×32+T].dword[0] ←result\n VSR[TX×32+T].dword[1] ←0x0000_0000_0000_0000\n FPSCR.FPRF ←fprf_CLASS_BFP64(result)\nend\nFPSCR.FR ←0\nFPSCR.FI ←0", "special_registers": "FPSCR, FPRF, FX, VXSNAN", "programming_notes": "Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.", "page_found": "Page 831 - 832", "example": "xscvhpdp vs1, vs3" }, { "mnemonic": "xscvdphp", "architecture": "PowerISA", "full_name": "VSX Scalar Convert Double to Half-Precision", "summary": "Converts a double-precision floating-point value to a half-precision floating-point value with rounding.", "syntax": "xscvdphp XT, XB", "encoding": { "format": "XX2-form", "binary_pattern": "60 | T | 17 | B | 347 | BX TX", "hex_opcode": "0xF011056C", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "0", "clean": "0" }, { "raw": "XB", "clean": "XB" }, { "raw": "376", "clean": "376" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XB", "desc": "Source" } ], "extension": "VSX", "description": "Converts the double-precision floating-point value in XB to a half-precision floating-point value, placing the result in the lower half of XT. The conversion applies rounding according to the current floating-point rounding mode in FPSCR. Requires VSX support.", "pseudocode": "XT ← convert_to_half_precision(XB, round_mode=FPSCR[RN])", "special_registers": "FPSCR, VSR[TX×32+T].hword[3]", "programming_notes": "This instruction can be used to operate on a single-precision source operand. Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.", "page_found": "Page 823 - 824", "example": "xscvdphp vs1, vs3" }, { "mnemonic": "xvcvhpsp", "architecture": "PowerISA", "full_name": "VSX Vector Convert Half-Precision to Single", "summary": "Converts half-precision floating-point values in a vector register to single-precision floating-point values.", "syntax": "xvcvhpsp XT, XB", "encoding": { "format": "XX2-form", "binary_pattern": "60 | XT | 0 | XB | 409", "hex_opcode": "0xF018076C", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "0", "clean": "0" }, { "raw": "XB", "clean": "XB" }, { "raw": "409", "clean": "409" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XB", "desc": "Source" } ], "extension": "VSX", "description": "For xvcvhpsp, each half-precision floating-point value in the rightmost halfword of word element i of VSR[XB] is converted to a single-precision floating-point value and placed into word element i of VSR[XT].", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nreset_flags()\nex_flag ← 0\nfor i from 0 to 3 do\n src ← bfp_CONVERT_FROM_BFP16(VSR[BX×32+B].word[i].hword[1])\n if src.class.SNaN = 1 then\n vresult.word[i] ← bfp32_CONVERT_FROM_BFP(bfp_QUIET(src))\n vxsnan_flag ← src.class.SNaN\n if vxsnan_flag = 1 then SetFX(FPSCR.VXSNAN)\n ex_flag ← ex_flag | (FPSCR.VE & vxsnan_flag)\n else\n vresult.word[i] ← bfp32_CONVERT_FROM_BFP(src)\n end\nend\nif ex_flag = 0 then VSR[32×TX+T] ← vresult", "special_registers": "FPSCR (FX, VXSNAN)", "page_found": "Page 834 - 835", "programming_notes": "This instruction is used to convert half-precision floating-point values to single-precision. Ensure that the VSX feature is enabled in the MSR register. Handle exceptions by checking the FPSCR for VXSNAN and VE flags. The conversion respects NaN handling, converting signaling NaNs to quiet NaNs.", "example": "xvcvhpsp vs1, vs3" }, { "mnemonic": "xvcvsphp", "architecture": "PowerISA", "full_name": "Vector Convert Single-Precision to Half-Precision format XX2-form", "summary": "Converts each single-precision floating-point value in a vector register to half-precision and stores the result in another vector register.", "syntax": "xvcvsphp XT, XB", "encoding": { "format": "XX2-form", "binary_pattern": "T | 25 | B | 475 | BX | TX", "hex_opcode": "0xF019076C", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "0", "clean": "0" }, { "raw": "XB", "clean": "XB" }, { "raw": "441", "clean": "441" } ], "length": "32", "bit_positions": "0 | 6 | 11 | 16 | 21 | 30 31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XB", "desc": "Source" } ], "extension": "VSX", "description": "For xvcvsphp, each integer value i from 0 to 3, do the following. Let src be the single-precision floating-point value in word element i of VSR[XB]. If src is an SNaN, the result is the half-precision representation of that SNaN converted to a QNaN. Otherwise, if src is a QNaN, the result is the half-precision representation of that QNaN. Otherwise, if src is an Infinity, the result is the half-precision representation of Infinity with the same sign as src. Otherwise, if src is a Zero, the result is the half-precision representation of Zero with the same sign as src. Otherwise, the result is the half-precision representation of src rounded to half-precision using the rounding mode specified by RN. The result is zero-extended and placed into word element i of VSR[XT]. If a trap-enabled exception occurs, VSR[XT] is not modified.", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nreset_flags()\ndo i = 0 to 3\n src ←bfp_CONVERT_FROM_BFP32(VSR[BX×32+B].word[i])\n rnd ←bfp_ROUND_TO_BFP16(FPSCR.RN,src)\n vresult.word[i].hword[0] ←0x0000\n vresult.word[i].hword[1] ← bfp16_CONVERT_FROM_BFP(rnd)\n if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\n if ox_flag=1 then SetFX(FPSCR.OX)\n if ux_flag=1 then SetFX(FPSCR.UX)\n if xx_flag=1 then SetFX(FPSCR.XX)\nex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.OE & ox_flag) | (FPSCR.UE & ux_flag) | (FPSCR.XE & xx_flag)\nend\nLet XT be the value 32×TX + T.\nLet XB be the value 32×BX + B.", "special_registers": "FPSCR", "page_found": "Page 829 - 830", "programming_notes": "This instruction converts single-precision floating-point values to half-precision format, handling special cases like NaNs and infinities. Ensure VSX is enabled; otherwise, a VSX_Unavailable exception occurs. The result is zero-extended into the destination vector register. Be cautious of rounding modes specified by FPSCR.RN and exceptions that may set flags in FPSCR.", "example": "xvcvsphp vs1, vs3" }, { "mnemonic": "sync", "architecture": "PowerISA", "full_name": "Synchronize", "summary": "Ensures that all instructions preceding the sync instruction have completed before the sync instruction completes, and no subsequent instructions are initiated until after the sync instruction completes.", "syntax": "sync L,SC", "encoding": { "format": "X-form", "binary_pattern": "31 | / | / | L | 598 | /", "hex_opcode": "0x7C0004AC", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "L", "clean": "L" }, { "raw": "598", "clean": "598" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "L", "desc": "Level (0=Heavy, 1=Light)" }, { "name": "SC", "desc": "Store Caching Inhibited Sync Control" } ], "pseudocode": "Synchronize memory operations as specified by L and SC fields; ensure prior instructions complete before this instruction completes; ensure subsequent instructions do not begin until this instruction completes.", "example": "sync 0", "example_note": "Full hardware fence.", "extension": "Base", "description": "Synchronizes memory operations by ensuring all instructions preceding the sync complete before the sync completes, and no subsequent instructions are initiated until after sync completes. The L field specifies the synchronization scope: L=0 (hwsync) enforces a heavy-weight synchronization across all storage types, while L=1 (lwsync) provides a lighter-weight barrier suitable for most memory ordering. The SC field (bits 9-10) controls store-caching-inhibited synchronization for specific storage classes. No condition or status registers are affected.", "programming_notes": "sync serves as both a basic and an extended mnemonic. The Assembler will recognize a sync mnemonic with two operands as the basic form, and a sync mnemonic with one operand or with no operand as an extended form.", "page_found": "Page 1060 - 1061", "extended_mnemonics": [ { "mnemonic": "hwsync", "equivalent": "sync L=0,SC=0" }, { "mnemonic": "lwsync", "equivalent": "sync L=1,SC=0" }, { "mnemonic": "ptesync", "equivalent": "sync L=2,SC=0" }, { "mnemonic": "phwsync", "equivalent": "sync L=4,SC=0" }, { "mnemonic": "plwsync", "equivalent": "sync L=5,SC=0" }, { "mnemonic": "stncisync", "equivalent": "sync SC=1" }, { "mnemonic": "stcisync", "equivalent": "sync SC=2" }, { "mnemonic": "stsync", "equivalent": "sync SC=3" } ] }, { "mnemonic": "lwsync", "architecture": "PowerISA", "full_name": "Lightweight Synchronize (Pseudo)", "summary": "Orders loads with loads, stores with stores, and loads with stores. Does NOT order stores with loads. (Encoded as sync 1).", "syntax": "lwsync", "encoding": { "format": "Pseudo", "binary_pattern": "31 | 0 | 1 | 0 | 598 | /", "hex_opcode": "0x7C2004AC", "visual_parts": [ { "raw": "sync 1", "clean": "sync 1" } ], "bit_positions": "0:5 | 6:7 | 8:10 | 11:20 | 21:30 | 31", "length": "32" }, "operands": [], "pseudocode": "MemoryBarrier(Light)", "example": "lwsync", "example_note": "Standard multicore barrier.", "extension": "Base", "description": "Lightweight Sync. Extended mnemonic for SYNC (sync 1). Provides a lightweight memory synchronization barrier for ordering loads and stores without full heavyweight sync semantics.", "programming_notes": "Lightweight sync. Orders loads and stores before the barrier against loads and stores after it, but does not guarantee store-to-load ordering. Sufficient for producer-consumer patterns without data-dependent stores." }, { "mnemonic": "rfid", "architecture": "PowerISA", "full_name": "Return From Interrupt Doubleword", "summary": "Returns from an interrupt handler. Restores PC from SRR0 and MSR from SRR1.", "syntax": "rfid", "encoding": { "format": "XL-form", "binary_pattern": "19 | / | / | / | 18 | /", "hex_opcode": "0x4C000024", "visual_parts": [ { "raw": "19", "clean": "19" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "18", "clean": "18" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [], "pseudocode": "CIA ← SRR0; MSR ← SRR1; context is fully restored", "example": "rfid", "example_note": "Exit Kernel Mode.", "extension": "Privileged", "description": "Returns from an interrupt handler by restoring the Program Counter from SRR0 and the Machine State Register from SRR1. This is a privileged instruction that must be executed in Hypervisor or privileged state. Execution continues at the address loaded from SRR0 with the MSR value from SRR1, enabling recovery from exceptions and context restoration. No condition or status registers are affected; the entire processor state is restored from the saved registers.", "special_registers": "MSR, SRR0, SRR1, HSRR0, HSRR1, USRR0", "programming_notes": "If this instruction sets MSRPR to 1, it also sets MSREE, MSRIR, and MSRDR to 1. If this instruction results in MSRS HV PR being equal to 0b110, it also sets MSRIR and MSRDR to 0.", "page_found": "Page 1121 - 1122" }, { "mnemonic": "tlbie", "architecture": "PowerISA", "full_name": "Translation Lookaside Buffer Invalidate Entry", "summary": "Invalidates a TLB entry corresponding to the address in RB.", "syntax": "tlbie RB, RS", "encoding": { "format": "X-form", "binary_pattern": "0 | RS | 6 | 11 | RIC | PRS | R | RB", "hex_opcode": "0x7C000264", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "/", "clean": "/" }, { "raw": "RB", "clean": "RB" }, { "raw": "306", "clean": "306" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:8 | 9 | 10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RB", "desc": "Effective Address" }, { "name": "RS", "desc": "Process ID (PID)" }, { "name": "RIC", "desc": "Radix Invalidation Control" }, { "name": "PRS", "desc": "Process Scoped" }, { "name": "effR", "desc": "Effective R" }, { "name": "R", "desc": "Effective R bit indicating whether to use the effective address or segment/page size information." } ], "pseudocode": "Invalidate TLB entry(ies) corresponding to address in RB, process ID in RS, controlled by RIC, PRS, and R fields; synchronization semantics depend on the radix MMU configuration.", "example": "tlbie r3, r4", "example_note": "Flush page translation.", "extension": "Privileged", "description": "Invalidates a translation lookaside buffer (TLB) entry corresponding to the effective address in RB. This privileged instruction allows selective invalidation controlled by the RIC (Radix Invalidation Control), PRS (Process Scoped), and R fields. The RS operand may contain a Process ID for process-scoped invalidations in radix MMU implementations. This instruction affects only the TLB state and does not modify condition or status registers.", "programming_notes": "The use of effR in the RTL and verbal descriptions of tlbie[l] beginning in Version 3.1B of the architecture is a clarification of earlier architecture, not a functional change.", "page_found": "Page 1207 - 1208", "special_registers": "MSR" }, { "mnemonic": "slbie", "architecture": "PowerISA", "full_name": "Segment Lookaside Buffer Invalidate Entry", "summary": "Invalidates an SLB entry. Critical for memory management on Power systems.", "syntax": "slbie RB", "encoding": { "format": "X-form", "binary_pattern": "31 | / | / | RB | 434 | /", "hex_opcode": "0x7C000364", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "/", "clean": "/" }, { "raw": "RB", "clean": "RB" }, { "raw": "434", "clean": "434" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RB", "desc": "Effective Address" } ], "pseudocode": "if 'slbie' then\n RB0:35 ← (RB)0:35\n if, for SLB entry that translates or most recently translated ea,\n entry_class = (RB)36 and entry_seg_size = size specified in (RB)37:38,\n then for SLB entry (if any) that translates ea\n SLBEV ←0\n all other fields of SLBE ←undefined\n else\n s ←log_base_2(entry_seg_size)\n esid ←(RB)0:63-s\n u ←undefined 1-bit value\n if u then\n if an SLB entry translates esid\n SLBEV ←0\n all other fields of SLBE ←undefined", "example": "slbie r3", "example_note": "Flush segment translation.", "extension": "Privileged", "description": "The instruction terminates any Segment Table walks being performed on behalf of the thread that executes it. The hardware ignores the contents of RB listed below, and software must set them to 0s.", "programming_notes": "slbie does not affect SLBs on other threads.\nThe class value specified by slbie must be the same as the Class value that is or was in the relevant SLB entry. The reason for this is that the hardware may use these values to optimize invalidation of implementation-specific lookaside information used in address translation. If the value specified by slbie differs from the value that is or was in the relevant SLB entry, these optimizations may produce incorrect results.\nWhen switching tasks in certain cases, it may be advantageous to preserve some implementation-specific lookaside entries while invalidating others. The slbia instruction specifying IH value 0b001 or 0b011 can be used for this purpose if SLB class values are appropriately assigned.", "page_found": "Page 1195 - 1196", "special_registers": "RB" }, { "mnemonic": "tbegin.", "architecture": "PowerISA", "full_name": "Transaction Begin", "summary": "Initiates a hardware transaction. If the transaction fails, execution rolls back to this point. Sets CR0 based on success/failure.", "syntax": "tbegin. R", "encoding": { "format": "X-form", "binary_pattern": "31 | / | R | / | 654 | 1", "hex_opcode": "0x7C00051D", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "R", "clean": "R" }, { "raw": "/", "clean": "/" }, { "raw": "654", "clean": "654" }, { "raw": "1", "clean": "1" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "R", "desc": "Rollback Handler (0=External, 1=Internal)" } ], "pseudocode": "if transaction initiated successfully then CR0[EQ] ← 1 else CR0[EQ] ← 0; CR0[LT,GT,SO] set based on abort cause; transaction state is active", "example": "tbegin. 0", "example_note": "Start atomic hardware transaction.", "extension": "Transactional Memory", "description": "Initiates a hardware transaction, setting the transaction active state and recording checkpoint information. If execution completes successfully within the transaction, tbegin. sets CR0[EQ] = 1; if the transaction is aborted, execution rolls back to this instruction and CR0[EQ] = 0, with CR0[SO] indicating the abort cause. The R field determines whether a transaction failure causes an external rollback (R=0) or an internal retry (R=1). Requires Transactional Memory (TM) facility support.", "page_found": "Page 1321", "special_registers": "CR0", "programming_notes": "In synthetic TM mode, transactions initiated by tbegin will fail immediately, invoking the failure handler. Ensure that your application logic correctly handles transaction failures to maintain data integrity." }, { "mnemonic": "tend.", "architecture": "PowerISA", "full_name": "Transaction End", "summary": "Commits the current hardware transaction. If successful, memory changes become visible atomically.", "syntax": "tend. A", "encoding": { "format": "X-form", "binary_pattern": "31 | / | A | / | 686 | 1", "hex_opcode": "0x7C00055D", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "A", "clean": "A" }, { "raw": "/", "clean": "/" }, { "raw": "686", "clean": "686" }, { "raw": "1", "clean": "1" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "A", "desc": "Abort Control" } ], "pseudocode": "CommitTransaction()", "example": "tend. 0", "example_note": "Commit transaction.", "extension": "Transactional Memory", "description": "Transaction End. Ends the current transaction. If A=1 (All), ends all nested transactions. On success the memory updates made in the transaction become visible. On failure a non-transactional abort occurs.", "special_registers": "CR0", "programming_notes": "Use `tend` to end a transaction, making its changes permanent if successful. If an error occurs, it triggers a non-transactional abort. Ensure all nested transactions are properly managed when using the A=1 option." }, { "mnemonic": "tabort.", "architecture": "PowerISA", "full_name": "Transaction Abort", "summary": "Forces a transaction failure and rollback.", "syntax": "tabort. RA", "encoding": { "format": "X-form", "binary_pattern": "31 | / | RA | / | 910 | 1", "hex_opcode": "0x7C00071D", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" }, { "raw": "RA", "clean": "RA" }, { "raw": "/", "clean": "/" }, { "raw": "910", "clean": "910" }, { "raw": "1", "clean": "1" } ], "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31", "length": "32" }, "operands": [ { "name": "RA", "desc": "Abort Code" } ], "pseudocode": "Abort transaction; rollback to most recent tbegin.; CR0[EQ] ← 0; CR0[SO] ← 1; TEXASR abort code ← RA", "example": "tabort. r3", "example_note": "Force rollback.", "extension": "Transactional Memory", "description": "Forces an abort of the current hardware transaction, rolling back all transactional state and returning control to the point of the most recent tbegin. The RA operand contains the abort code (or a register holding the code) that is reflected in TEXASR. CR0 is set to indicate transaction failure, with CR0[SO] holding abort status. This instruction requires Transactional Memory facility support and can only be executed within a transaction.", "special_registers": "CR0", "programming_notes": "Use tabort to explicitly abort a transaction and discard all changes. Ensure this is called within a transactional region; otherwise, it will raise an exception. Check CR0 for transaction status before or after calling tabort." }, { "mnemonic": "vcipher", "architecture": "PowerISA", "full_name": "Vector Cipher (AES)", "summary": "Performs one round of AES encryption (SubBytes, ShiftRows, MixColumns, AddRoundKey).", "syntax": "vcipher vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 1288", "hex_opcode": "0x10000508", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1288", "clean": "1288" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target State" }, { "name": "vA", "desc": "Current State" }, { "name": "vB", "desc": "Round Key" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register containing the intermediate state array" }, { "name": "VRB", "desc": "Source Vector Register containing the round key" } ], "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nState ←VSR[VRA+32]\nRoundKey ←VSR[VRB+32]\nvtemp1 ←SubBytes(State)\nvtemp2 ←ShiftRows(vtemp1)\nvtemp3 ←MixColumns(vtemp2)\nVSR[VRT+32] ←vtemp3 ⊕ RoundKey", "example": "vcipher v1, v2, v3", "example_note": "Hardware AES Encrypt.", "extension": "Vector Crypto", "description": "The instruction performs one round of the AES cipher operation on the intermediate State array, sequentially applying the transforms SubBytes(), ShiftRows(), MixColumns(), and AddRoundKey() as defined in FIPS-197. The result is placed into VSR[VRT+32], representing the new intermediate state of the cipher operation.", "page_found": "Page 459 - 460", "special_registers": "MSR", "programming_notes": "The vcipher instruction performs a single AES cipher round, requiring the Vector Facility to be enabled. Ensure that the VRA and VRB registers point to the correct intermediate state and round key in vector storage registers. The result is stored in VSR[VRT+32]. This instruction operates at the user privilege level and will raise an exception if the Vector Facility is not available." }, { "mnemonic": "vncipher", "architecture": "PowerISA", "full_name": "Vector Inverse Cipher (AES)", "summary": "Performs one round of an AES inverse cipher operation on the intermediate state array.", "syntax": "vncipher vD, vA, vB", "encoding": { "format": "VX-form", "binary_pattern": "4 | vD | vA | vB | 1352", "hex_opcode": "0x10000548", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "1352", "clean": "1352" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target State" }, { "name": "vA", "desc": "Current State" }, { "name": "vB", "desc": "Round Key" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register containing the intermediate state array" }, { "name": "VRB", "desc": "Source Vector Register containing the round key" } ], "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nState ← VSR[VRA+32]\nRoundKey ← VSR[VRB+32]\nvtemp1 ← InvShiftRows(State)\nvtemp2 ← InvSubBytes(vtemp1)\nvtemp3 ← vtemp2 ⊕ RoundKey\nVSR[VRT+32] ← InvMixColumns(vtemp3)", "example": "vncipher v1, v2, v3", "example_note": "Hardware AES Decrypt.", "extension": "Vector Crypto", "description": "The instruction performs one round of an AES inverse cipher operation, sequentially applying the transforms InvShiftRows(), InvSubBytes(), AddRoundKey(), and InvMixColumns() to the intermediate State array.", "page_found": "Page 460 - 461", "special_registers": "MSR", "programming_notes": "This instruction is used to perform a single round of the AES inverse cipher, which includes operations like InvShiftRows, InvSubBytes, AddRoundKey, and InvMixColumns. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The input state and round key must be correctly loaded into the appropriate vector registers (VRA+32 and VRB+32), respectively, and the result will be stored in VRT+32. This operation is typically used in cryptographic algorithms that require AES decryption." }, { "mnemonic": "vshasigmaw", "architecture": "PowerISA", "full_name": "Vector SHA-256 Sigma Word", "summary": "Performs the Sigma0/Sigma1/sigma0/sigma1 functions for SHA-256.", "syntax": "vshasigmaw vD, vA, ST, SIX", "encoding": { "format": "VX-form", "binary_pattern": "4 | VRT | VRA | ST | SIX", "hex_opcode": "0x10000682", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "ST", "clean": "ST" }, { "raw": "1666", "clean": "1666" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16 | 17:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Source" }, { "name": "ST", "desc": "Sigma Type (0/1)" }, { "name": "SIX", "desc": "Shift Index (Immediate)" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" } ], "pseudocode": "for i = 0 to 3: vD[32i:32i+31] ← SHA256_sigma(vA[32i:32i+31], ST, SIX)", "example": "vshasigmaw v1, v2, 0, 0", "example_note": "SHA-256 Acceleration.", "extension": "Vector Crypto", "description": "Performs one of the four SHA-256 sigma functions (Sigma0, Sigma1, sigma0, or sigma1) on each 32-bit word in the source vector and stores the result in the destination vector. The ST field selects between Sigma-type and sigma-type operations, and SIX selects the specific operation. This is a Vector Crypto instruction that operates on four 32-bit elements in parallel within a 128-bit vector register. No condition or status registers are affected.", "page_found": "Page 463 - 464", "special_registers": "MSR", "programming_notes": "The vshasigmaw instruction is used to perform SHA-256 sigma or sigma-like functions on vector register elements. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. The instruction operates on each 32-bit word of the source vector, applying different bitwise rotations and XORs based on the ST and SIX fields. This instruction requires supervisor privilege level to execute." }, { "mnemonic": "lbzu", "architecture": "PowerISA", "full_name": "Load Byte and Zero with Update D-form", "summary": "Loads a byte from memory into a register, zeroing the upper bits of the target register, and updates the base address register.", "description": "The effective address (EA) is calculated as the sum of the contents of register RA and the sign-extended displacement D. The byte at EA is loaded into RT56:63, with RT0:55 set to zero. The EA is then stored back into RA.", "syntax": "lbzu RT,D(RA)", "operands": [ { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RA", "desc": "Base Address General Purpose Register" }, { "name": "D", "desc": "Displacement" } ], "encoding": { "format": "D-form", "hex_opcode": "0x8C000000", "length": "32", "binary_pattern": "0 | RT | RA | D", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "Base", "pseudocode": "EA ← (RA) + EXTS(D)\nRT ← 560 || MEM(EA, 1)\nRA ← EA", "special_registers": "", "programming_notes": "The base register (RA) is updated with the effective address after the memory access. RA must not be 0 and must differ from the destination register; violating this constraint produces undefined results.", "extended_mnemonics": [], "page_found": "Page 84 - 86", "example": "lbzu r3, 0(r4)" }, { "mnemonic": "lhzu", "architecture": "PowerISA", "full_name": "Load Halfword and Zero with Update D-form", "summary": "Loads a halfword from memory into a register, zero-extends it to 64 bits, and updates the base address.", "description": "The effective address (EA) is calculated as the sum of the contents of register RA and the sign-extended displacement D. The halfword at EA is loaded into RT48:63, with RT0:47 set to zero. The EA is then placed back into RA.", "syntax": "lhzu RT,D(RA)", "operands": [ { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RA", "desc": "Base General Purpose Register" }, { "name": "D", "desc": "Displacement" } ], "encoding": { "format": "D-form", "hex_opcode": "0xA4000000", "length": "32", "binary_pattern": "0 | RT | RA | D", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "Base", "pseudocode": "EA ← (RA) + EXTS(D)\nRT ← 480 || MEM(EA, 2)\nRA ← EA", "special_registers": "", "programming_notes": "The base register (RA) is updated with the effective address after the memory access. RA must not be 0 and must differ from the destination register; violating this constraint produces undefined results.", "extended_mnemonics": [], "page_found": "Page 86 - 88", "example": "lhzu r3, 0(r4)" }, { "mnemonic": "stdu", "architecture": "PowerISA", "full_name": "Store Doubleword with Update DS-form", "summary": "Stores a doubleword from a register to memory and updates the base address register.", "description": "Stores a 64-bit doubleword from register RS to memory at the address computed from RA plus the sign-extended displacement, then updates RA with the effective address. The displacement is a 14-bit signed value (DS field), scaled by 8 to form a byte offset. This instruction is commonly used in prologue/epilogue code to allocate/deallocate stack space while storing values. No condition or status registers are affected.", "syntax": "stdu RS,disp(RA)", "operands": [ { "name": "RS", "desc": "Source General Purpose Register" }, { "name": "RA", "desc": "Base Address General Purpose Register" }, { "name": "disp", "desc": "Displacement value" } ], "encoding": { "format": "DS-form", "hex_opcode": "0xF8000001", "length": "32", "binary_pattern": "0 | RS | RA | DS | 1", "bit_positions": "0:5 | 6:10 | 11:15 | 16:30 | 31" }, "extension": "Base", "pseudocode": "EA ← (RA) + EXTS(DS || 0b00); M[EA:EA+7] ← (RS); RA ← EA", "special_registers": "", "programming_notes": "The base register (RA) is updated with the effective address after the memory access. RA must not be 0 and must differ from the destination register; violating this constraint produces undefined results.", "extended_mnemonics": [], "page_found": "Page 96 - 98", "example": "stdu r3, disp(RA)" }, { "mnemonic": "mulli", "architecture": "PowerISA", "full_name": "Multiply Low Immediate", "summary": "Multiplies the contents of a register by an immediate value and places the low-order 32 bits of the product into another register.", "description": "The 64-bit first operand is (RA). The 64-bit second operand is the sign-extended value of the SI field. The low-order 32 bits of the 128-bit product of the operands are placed into register RT.", "syntax": "mulli RT,RA,SI", "operands": [ { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "SI", "desc": "16-bit Immediate Value" } ], "encoding": { "format": "D-form", "hex_opcode": "0x1C000000", "length": "32", "binary_pattern": "0 | RT | RA | SI", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "Base", "pseudocode": "prod0:127 ← (RA) × EXTS(SI)\nRT ← prod64:127", "special_registers": "N/A", "programming_notes": "For mulli and mullw, the low-order 32 bits of the product are the correct 32-bit product for 32-bit mode.", "extended_mnemonics": [], "page_found": "Page 114 - 116", "example": "mulli r3, r4, 16" }, { "mnemonic": "addg6s", "architecture": "PowerISA", "full_name": "Add and Generate Sixes", "summary": "Adds the contents of two registers and generates sixes based on carry bits.", "description": "Adds the values in registers RA and RB, then replaces each nibble (4-bit group) of the result with 0x6 if a carry was generated from that nibble, otherwise the low 4 bits of the sum are preserved. This instruction is used in decimal arithmetic for BCD (Binary Coded Decimal) addition to generate correction factors. No condition or status registers are affected, and the Rc bit is not available (non-dot form only).", "syntax": "addg6s RT,RA,RB", "operands": [ { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "RB", "desc": "Source General Purpose Register" } ], "encoding": { "format": "XO-form", "hex_opcode": "0x7C000094", "length": "32", "binary_pattern": "18 | LI | AA | LK", "bit_positions": "0:5 | 6:29 | 30 | 31" }, "extension": "Base", "pseudocode": "sum ← (RA) + (RB); for i = 0 to 15: if carry_from_nibble(i) then RT[4i:4i+3] ← 0x6 else RT[4i:4i+3] ← sum[4i:4i+3]", "special_registers": "", "programming_notes": "addg6s can be used to add or subtract two BCD operands. In these examples it is assumed that r0 contains 0x666...666. (BCD data formats are described in Section 5.3.)", "extended_mnemonics": [], "page_found": "Page 152 - 154", "example": "addg6s r3, r4, r5" }, { "mnemonic": "lfs", "architecture": "PowerISA", "full_name": "Load Floating-Point Single D-form", "summary": "Loads a single-precision floating-point value from memory into a floating-point register and converts it to double precision.", "description": "Loads a single-precision floating-point value from memory at address RA+D, converts it to double precision, and stores the result in FRT. This instruction is part of the Floating-Point category and does not affect condition registers or the XER.", "syntax": "lfs FRT,D(RA)", "operands": [ { "name": "FRT", "desc": "Target Floating-Point Register" }, { "name": "RA", "desc": "Base General Purpose Register" }, { "name": "D", "desc": "Displacement" }, { "name": "offset", "desc": "Immediate Offset" } ], "encoding": { "format": "D-form", "hex_opcode": "0xC0000000", "length": "32", "binary_pattern": "48 | FRT | RA | D", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "Floating-Point", "pseudocode": "EA ← (RA = 0 ? 0 : GPR(RA)) + EXTS(D)\nFPR(FRT) ← ConvertSingleToDouble([EA])", "special_registers": "None, FPSCR", "programming_notes": "The lfs extended mnemonic permits computing an effective address as a Load or Store instruction would, but loads the address itself into a GPR rather than loading the value that is in storage at that address.", "extended_mnemonics": [], "page_found": "Page 184 - 186", "example": "lfs f1, 0(r4)" }, { "mnemonic": "lfsu", "architecture": "PowerISA", "full_name": "Load Floating-Point Single with Update Indexed", "summary": "Loads a floating-point single-precision operand from memory into a register and updates the base address.", "description": "The word in storage addressed by EA is interpreted as a floating-point single-precision operand. This word is converted to floating-point double format (see page 149) and placed into register FRT. The effective address (EA) is the sum of RA and D, and EA is placed into register RA.", "syntax": "lfsu FRT,D(RA)", "operands": [ { "name": "FRT", "desc": "Target Floating-Point Register" }, { "name": "RA", "desc": "Base General Purpose Register" }, { "name": "D", "desc": "Displacement" } ], "encoding": { "format": "X-form", "hex_opcode": "0xC4000000", "length": "32", "binary_pattern": "0 | FRT | RA | D", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "Floating-Point", "pseudocode": "EA ← (RA) + EXTS(D)\nFRT ← DOUBLE(MEM(EA, 4))\nRA ← EA\nif RA=0 then\n the instruction form is invalid", "special_registers": "FPSCR", "programming_notes": "The base register (RA) is updated with the effective address after the memory access. RA must not be 0 and must differ from the destination register; violating this constraint produces undefined results.", "extended_mnemonics": [], "page_found": "Page 186 - 188", "example": "lfsu f1, 0(r4)" }, { "mnemonic": "lfdu", "architecture": "PowerISA", "full_name": "Load Floating-Point Double with Update", "summary": "Loads a doubleword from memory into a floating-point register and updates the base address register.", "description": "The doubleword in storage addressed by EA is loaded into register FRT. The effective address (EA) is the sum of the contents of register RA, or the value 0 if RA=0, and the value D, sign-extended to 64 bits. If RA=0, the instruction form is invalid.", "syntax": "lfdu FRT,D(RA)", "operands": [ { "name": "FRT", "desc": "Target Floating Point Register" }, { "name": "RA", "desc": "Base General Purpose Register" }, { "name": "D", "desc": "Displacement" } ], "encoding": { "format": "D-form", "hex_opcode": "0xCC000000", "length": "32", "binary_pattern": "0 | FRT | RA | D", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "Floating-Point", "pseudocode": "if RA = 0 then\n b ← 0\nelse\n b ← (RA)\nEA ← b + EXTS(D)\nFRT ← MEM(EA, 8)\nRA ← EA", "special_registers": "FPSCR", "programming_notes": "The base register (RA) is updated with the effective address after the memory access. RA must not be 0 and must differ from the destination register; violating this constraint produces undefined results.", "extended_mnemonics": [], "page_found": "Page 188 - 190", "example": "lfdu f1, 0(r4)" }, { "mnemonic": "stfsx", "architecture": "PowerISA", "full_name": "Store Floating-Point Single Indexed X-form", "summary": "Stores a single-precision floating-point value from a register to memory using an indexed address.", "description": "The contents of register FRS are converted to single format and stored into the word in storage addressed by EA, which is the sum of RA (or RA|0) and RB. If RA is not zero, it is used directly; otherwise, b is set to zero.", "syntax": "stfsx FRS,RA,RB", "operands": [ { "name": "FRS", "desc": "Floating-Point Register Source" }, { "name": "RA", "desc": "General Purpose Register (Base Address)" }, { "name": "RB", "desc": "General Purpose Register (Index)" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C00052E", "length": "32", "binary_pattern": "0 | FRS | RA | RB", "bit_positions": "" }, "extension": "Floating-Point", "pseudocode": "if RA = 0 then\n b ← 0\nelse\n b ← (RA)\nEA ← b + (RB)\nMEM(EA, 4) ← SINGLE((FRS))", "special_registers": "FPSCR", "programming_notes": "The stfsx instruction stores a single-precision floating-point value from register FRS to memory. Ensure that the base address (RA or RA|0) and offset (RB) are correctly aligned for optimal performance. If RA is zero, the effective address is solely determined by RB; otherwise, it's the sum of RA and RB. This instruction operates at user privilege level.", "extended_mnemonics": [], "page_found": "Page 190 - 192", "example": "stfsx f1, r4, r5" }, { "mnemonic": "stfdux", "architecture": "PowerISA", "full_name": "Store Floating-Point Double with Update Indexed", "summary": "Stores the contents of a floating-point register into memory and updates the base address register.", "description": "The contents of register FRS are stored into the double-word in storage addressed by EA. The effective address (EA) is the sum of the contents of registers RA and RB. If RA=0, the instruction form is invalid. EA is placed back into register RA.", "syntax": "stfdux FRS,RA,RB", "operands": [ { "name": "FRS", "desc": "Floating-Point Register Source" }, { "name": "RA", "desc": "General Purpose Register Address" }, { "name": "RB", "desc": "General Purpose Register Index" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C0005EE", "length": "32", "binary_pattern": "0 | FRS | RA | RB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "Floating-Point", "pseudocode": "if RA = 0 then\n b ← 0\nelse\n b ← (RA)\nEA ← b + (RB)\nMEM(EA, 8) ← (FRS)\nRA ← EA", "special_registers": "FPSCR", "programming_notes": "The base register (RA) is updated with the effective address after the memory access. RA must not be 0 and must differ from the destination register; violating this constraint produces undefined results.", "extended_mnemonics": [], "page_found": "Page 192 - 194", "example": "stfdux f1, r4, r5" }, { "mnemonic": "stfdp", "architecture": "PowerISA", "full_name": "Store Floating-Point Double Pair", "summary": "Stores the contents of two floating-point registers into memory as a doubleword pair.", "description": "The instruction stores the contents of the even-numbered register of FRSp into the doubleword in storage addressed by EA, and the contents of the odd-numbered register of FRSp into the doubleword in storage addressed by EA+8.", "syntax": "stfdp FRSp,disp(RA)", "operands": [ { "name": "FRSp", "desc": "Floating-Point Register Pair" }, { "name": "disp", "desc": "Displacement" }, { "name": "RA", "desc": "Base General Purpose Register" } ], "encoding": { "format": "DS-form", "hex_opcode": "0xF4000000", "length": "32", "binary_pattern": "0 | FRSp | RA | DS | 0b00", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "Floating-Point", "pseudocode": "if RA = 0 then\n b ← 0\nelse\n b ← (RA)\nEA ← b + EXTS(DS || 0b00)\nMEM(EA, 8) ← FRSpeven\nMEM(EA+8, 8) ← FRSpodd", "special_registers": "FPSCR", "programming_notes": "The stfdp instruction is commonly used to store two consecutive double-precision floating-point numbers from the FPSCR into memory. Ensure that the base address (EA) is properly aligned to an 8-byte boundary to avoid alignment exceptions. This instruction operates at user privilege level and will raise a program interrupt if attempting to access protected memory.", "extended_mnemonics": [], "page_found": "Page 194 - 196", "example": "stfdp f2, disp(RA)" }, { "mnemonic": "fmrgew", "architecture": "PowerISA", "full_name": "Floating Merge Even Word", "summary": "Merges the even words from two floating-point registers into a third.", "description": "The contents of word element 0 of FPR[FRA] are placed into word element 0 of FPR[FRT], and the contents of word element 0 of FPR[FRB] are placed into word element 1 of FPR[FRT].", "syntax": "fmrgew FRT,FRA,FRB", "operands": [ { "name": "FRT", "desc": "Target Floating-Point Register" }, { "name": "FRA", "desc": "Source Floating-Point Register" }, { "name": "FRB", "desc": "Source Floating-Point Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0xFC00078C", "length": "32", "binary_pattern": "0 | FRT | FRA | FRB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "Floating-Point", "pseudocode": "if MSR.FP=0 then\n FP_Unavailable()\nFPR[FRT].word[0] ← FPR[FRA].word[0]\nFPR[FRT].word[1] ← FPR[FRB].word[0]", "special_registers": "FPSCR", "programming_notes": "fmrgew and fmrgow are provided to support direct move operations in 32-bit mode.", "extended_mnemonics": [], "page_found": "Page 196 - 198", "example": "fmrgew f1, f2, f3" }, { "mnemonic": "frin", "architecture": "PowerISA", "full_name": "Floating Round to Integer Nearest", "summary": "Rounds the floating-point operand in register FRB to an integral value using the rounding mode round to nearest.", "description": "The floating-point operand in register FRB is rounded to an integral value as follows, with the result placed into register FRT. If the sign of the operand is positive, (FRB) + 0.5 is truncated to an integral value, otherwise (FRB) - 0.5 is truncated to an integral value.", "syntax": "frin FRT,FRB", "operands": [ { "name": "FRT", "desc": "Target Floating-Point Register" }, { "name": "FRB", "desc": "Source Floating-Point Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0xFC000310", "length": "32", "binary_pattern": "18 | FRT | FRB | Rc", "bit_positions": "0:5 | 6:29 | 30 | 31" }, "extension": "Floating-Point", "pseudocode": "if 'frin' then\n if (FRB) >= 0 then\n FRT <- truncate((FRB) + 0.5)\n else\n FRT <- truncate((FRB) - 0.5)", "special_registers": "FPSCR, (FPRF, FX, VXSNAN), FPSCR, (FR, FI), CR1, (if, Rc=1), CR0", "programming_notes": "These instructions set FR and FI to 0b00 regardless of whether the result is inexact or rounded because there is a desire to preserve the value of XX.", "extended_mnemonics": [], "page_found": "Page 212 - 214", "example": "frin f1, f3" }, { "mnemonic": "mffscdrn", "architecture": "PowerISA", "full_name": "Move From FPSCR Control & Set DRN", "summary": "Moves control bits from FPSCR to a register and sets the DRN field.", "description": "The contents of the control bits in the FPSCR, that is, bits 29:31 (DRN) and bits 56:63 (VE, OE, UE, ZE, XE, NI, RN), are placed into the corresponding bits in register FRT. All other bits in register FRT are set to 0. The contents of bits 29:31 of the FPSCR (DRN) are set to the value of FRB.", "syntax": "mffscdrn FRT,FRB", "operands": [ { "name": "FRT", "desc": "Target Floating-Point Register" }, { "name": "FRB", "desc": "Source Floating-Point Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0xFC14048E", "length": "32", "binary_pattern": "0 | FRT | FRB | 583", "bit_positions": "0:5 | 6:10 | 11:20 | 21:31" }, "extension": "Floating-Point", "pseudocode": "FRT <- FPSCR[29:31] & FPSCR[56:63]\nFPSCR[DRN] <- FRB[29:31]", "special_registers": "FPSCR", "programming_notes": "mffscdrn permits software to simultaneously read control bits in the FPSCR and set the DRN field without the higher latency typically associated with accessing the status bits.", "extended_mnemonics": [], "page_found": "Page 218 - 220", "example": "mffscdrn f1, f3" }, { "mnemonic": "dtstex", "architecture": "PowerISA", "full_name": "DFP Test Exponent X-form", "summary": "Compares the exponent values of two DFP operands and updates CR field BF and FPCC.", "description": "The exponent value (Ea) of the DFP operand in FRA is compared to the exponent value (Eb) of the DFP operand in FRB. The result of the compare is placed into CR field BF and the FPCC.", "syntax": "dtstex BF,FRA,FRB", "operands": [ { "name": "BF", "desc": "Condition Register Field" }, { "name": "FRA", "desc": "First Source DFP Floating-Point Register" }, { "name": "FRB", "desc": "Second Source DFP Floating-Point Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0xEC000144", "length": "32", "binary_pattern": "0 | BF | FRA | FRB | 162", "bit_positions": "0:5 | 6:8 | 9:10 | 11:15 | 16:31" }, "extension": "Decimal Floating-Point", "pseudocode": "Ea ← exponent of DFP operand in FRA\nEb ← exponent of DFP operand in FRB\nif (FRA is F) and (FRB is F) then\n if Ea < Eb then CR_BF || FPCC ← 0b1000\n else if Ea > Eb then CR_BF || FPCC ← 0b0100\n else CR_BF || FPCC ← 0b0010\nelse if (FRA is ∞) and (FRB is ∞) then CR_BF || FPCC ← 0b0010\nelse if (FRA is QNaN or SNaN) and (FRB is QNaN or SNaN) then CR_BF || FPCC ← 0b0010\nelse CR_BF || FPCC ← 0b0001", "special_registers": "CR field BF, FPSCR FPCC", "programming_notes": "The dtstex instruction compares the exponents of two DFP operands and sets the condition register field BF and floating-point status and control register (FPSCR) FPCC based on the comparison. Ensure that both operands are properly aligned and valid; otherwise, the instruction may raise exceptions. This instruction is useful for sorting or filtering operations where exponent values need to be compared.", "extended_mnemonics": [], "page_found": "Page 246 - 248", "example": "dtstex cr0, f2, f3" }, { "mnemonic": "drrnd", "architecture": "PowerISA", "full_name": "Decimal Floating-Point Reround", "summary": "Rounds a decimal floating-point value to the specified number of significant digits.", "description": "Rounds a decimal floating-point value in FRB to the number of significant digits specified in FRA, using the rounding mode in RMC, and stores the result in FRT. This instruction is part of the Decimal Floating-Point category. The Rc bit controls whether the condition register CR1 is updated with FPCC and exception flags.", "syntax": "drrnd FRT,FRA,FRB,RMC", "operands": [ { "name": "FRT", "desc": "Target Floating-Point Register" }, { "name": "FRA", "desc": "Source Floating-Point Register containing the reference significance" }, { "name": "FRB", "desc": "Source Floating-Point Register containing the value to be rounded" }, { "name": "RMC", "desc": "Rounding Mode Control" }, { "name": "k", "desc": "Number of significant digits" } ], "encoding": { "format": "Z23-form", "hex_opcode": "0xEC000046", "length": "32", "binary_pattern": "0 | FRT | FRA | FRB | RMC | Rc", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "Decimal Floating-Point", "pseudocode": "k ← DecimalSignificance(FRA)\nFPR(FRT) ← RoundDecimal(FRB, k, RMC)\nif Rc = 1 then CR1 ← FPCC || FPSCR[OX,UX,ZX,XX]", "special_registers": "FPSCR, (FPRF, FR, FI, FX, XX), VXSNAN, VXCVI, CR0", "programming_notes": "DFP Reround can be used to adjust a DFP value to have no more than a specified number of significant digits. The result is right-justified and rounded as specified by RMC.", "extended_mnemonics": [], "page_found": "Page 252 - 254", "example": "drrnd f1, f2, f3, 0" }, { "mnemonic": "drintx", "architecture": "PowerISA", "full_name": "Decimal Floating-Point Round To FP Integer With Inexact", "summary": "Rounds a decimal floating-point number to the nearest integer and places it into a floating-point register.", "description": "The DFP operand in FRB is rounded to a floating-point integer and placed into FRT. The sign of the result is the same as the sign of the operand in FRB. The ideal exponent is the larger value of zero and the exponent of the operand in FRB. The rounding mode used is specified by RMC.", "syntax": "drintx R,FRT,FRB,RMC", "operands": [ { "name": "R", "desc": "Rounding mode control bit" }, { "name": "FRT", "desc": "Target Floating-Point Register" }, { "name": "FRB", "desc": "Source Floating-Point Register" }, { "name": "RMC", "desc": "Rounding mode control field" } ], "encoding": { "format": "Z23-form", "hex_opcode": "0xEC0000C6", "length": "32", "binary_pattern": "0 | R | FRT | FRB | RMC | Rc", "bit_positions": "0:5 | 6:10 | 11:14 | 15 | 16:20 | 21:31" }, "extension": "Decimal Floating-Point", "pseudocode": "if 'drintx' then\n FRT <- round(FRB, RMC)\n if result differs from FRB then\n raise inexact exception", "special_registers": "FPSCR, (FPRF, FR, FI, FX, XX), VXSNAN, CR1, (if, Rc=1), CR0", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "extended_mnemonics": [ "drintx." ], "page_found": "Page 254 - 256", "example": "drintx 0, f1, f3, 0" }, { "mnemonic": "drintn", "architecture": "PowerISA", "full_name": "Decimal Floating-Point Round To FP Integer Without Inexact", "summary": "Rounds a decimal floating-point number to an integer without recognizing an inexact exception.", "description": "This operation rounds the value in FRB to an integer using the specified rounding mode (RMC) and places the result in FRT. It does not recognize an inexact exception.", "syntax": "drintn R,FRT,FRB,RMC", "operands": [ { "name": "R", "desc": "Rounding mode control" }, { "name": "FRT", "desc": "Target Floating-Point Register" }, { "name": "FRB", "desc": "Source Floating-Point Register" }, { "name": "RMC", "desc": "Rounding Mode Control" } ], "encoding": { "format": "Z23-form", "hex_opcode": "0xEC0001C6", "length": "32", "binary_pattern": "0 | FRT | R | FRB | RMC | Rc", "bit_positions": "0:5 | 6:10 | 11:14 | 15 | 16:20 | 21:31" }, "extension": "Decimal Floating-Point", "pseudocode": "if 'drintn' then\n FRT <- Round(FRB, RMC)\n FI <- 0\n FR <- 0\n VXSNAN <- 0\n if Rc=1 then\n CR1 <- ClassAndSign(FRT)\nelse if 'drintn.' then\n FRT <- Round(FRB, RMC)\n FI <- 0\n FR <- 0\n VXSNAN <- 0\n CR1 <- ClassAndSign(FRT)", "special_registers": "FPSCR, (FPRF, FX, VXSNAN), FPSCR, (FR, FI), CR1, CR0", "programming_notes": "The DFP Round To FP Integer Without Inexact and DFP Round To FP Integer Without Inexact Quad instructions can be used to implement decimal equivalents of several C99 rounding functions by specifying the appropriate R and RMC field values.", "extended_mnemonics": [], "page_found": "Page 256 - 258", "example": "drintn 0, f1, f3, 0" }, { "mnemonic": "lvebx", "architecture": "PowerISA", "full_name": "Load Vector Element Byte Indexed", "summary": "Loads a byte from memory into a vector register element.", "description": "Loads a single byte from memory at address RA+RB and stores it in the rightmost byte of a vector register element in VRT, with zero padding in remaining bytes. This instruction is part of the VMX (AltiVec) category and does not update condition registers.", "syntax": "lvebx VRT,RA,RB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "RB", "desc": "Index General Purpose Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C00000E", "length": "32", "binary_pattern": "0 | VRT | RA | RB | 7", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VMX (AltiVec)", "pseudocode": "EA ← (RA = 0 ? 0 : GPR(RA)) + GPR(RB)\nbyte_index ← EA[28:31]\nVRT ← (0x00000000000000 || [EA & ~0x3])\nVRT[byte_index] ← [EA]", "special_registers": "MSR", "programming_notes": "The Load Vector Element instructions load the specified element into the same location in the target register as the location into which it would be loaded using the Load Vector instruction.", "extended_mnemonics": [], "page_found": "Page 294 - 296", "example": "lvebx v1, r4, r5" }, { "mnemonic": "lvewx", "architecture": "PowerISA", "full_name": "Load Vector Element Word Indexed", "summary": "Loads a word from memory into a vector register element.", "description": "Loads a word (32 bits) from memory at address RA+RB (aligned to 4-byte boundary) and stores it in a vector register element in VRT, with zero padding in remaining doublewords. This instruction is part of the VMX (AltiVec) category and does not update condition registers.", "syntax": "lvewx VRT,RA,RB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "RB", "desc": "Source General Purpose Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C00008E", "length": "32", "binary_pattern": "0 | VRT | RA | RB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VMX (AltiVec)", "pseudocode": "EA ← (RA = 0 ? 0 : GPR(RA)) + GPR(RB)\nword_index ← EA[30:31]\nVRT ← (0x00000000000000000000000000000000 || [EA & ~0x3])\nVRT[word_index] ← [EA & ~0x3]", "special_registers": "MSR", "programming_notes": "The lvewx instruction loads a word from memory into a vector register element. Ensure the effective address is aligned to a 4-byte boundary by ANDing with 0xFFFF_FFFF_FFFF_FFFC. This instruction requires the VEC bit in the MSR to be set; otherwise, it raises a Vector_Unavailable exception. Be aware of endianness when placing the byte into the vector register.", "extended_mnemonics": [], "page_found": "Page 296 - 298", "example": "lvewx v1, r4, r5" }, { "mnemonic": "stvebx", "architecture": "PowerISA", "full_name": "Store Vector Element Byte Indexed", "summary": "Stores a byte element from a vector register into memory.", "description": "Stores the byte element from vector register VRS at the position determined by the effective address RA+RB into memory. This instruction is part of the VMX (AltiVec) category and does not update condition registers.", "syntax": "stvebx VRS,RA,RB", "operands": [ { "name": "VRS", "desc": "Vector Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "RB", "desc": "Source General Purpose Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C00010E", "length": "32", "binary_pattern": "0 | VRS | RA | RB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VMX (AltiVec)", "pseudocode": "EA ← (RA = 0 ? 0 : GPR(RA)) + GPR(RB)\nbyte_index ← EA[28:31]\n[EA] ← VRS[byte_index]", "special_registers": "MSR", "programming_notes": "Unless bits 60:63 of the address are known to match the byte offset of the subject byte element in VSR[VRS+32], software should use Vector Splat to splat the subject byte element before performing the store.", "extended_mnemonics": [], "page_found": "Page 298 - 300", "example": "stvebx v1, r4, r5" }, { "mnemonic": "lvsl", "architecture": "PowerISA", "full_name": "Load Vector for Shift Left Indexed", "summary": "Loads a vector pattern suitable for shifting left indexed.", "description": "Creates a shift-left permutation pattern based on the effective address (RA+RB) modulo 16 and loads it into VRT. This instruction is part of the VMX (AltiVec) category and is typically used to set up permutation vectors for unaligned vector loads. It does not update condition registers.", "syntax": "lvsl VRT,RA,RB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "RB", "desc": "Source General Purpose Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C00000C", "length": "32", "binary_pattern": "31 | VRT | RA | RB | 6 | /", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "VMX (AltiVec)", "pseudocode": "EA ← (RA = 0 ? 0 : GPR(RA)) + GPR(RB)\nshift_amount ← EA[28:31]\nVRT ← PermutationPattern(shift_amount, \"shift_left\")", "special_registers": "MSR", "programming_notes": "The lvsl instruction can be used to create a permute control vector for vperm instructions. It is useful for loading and storing unaligned data, as well as rotating or shifting the contents of a VSR.", "extended_mnemonics": [], "page_found": "Page 302 - 304", "example": "lvsl v1, r4, r5" }, { "mnemonic": "vpksdss", "architecture": "PowerISA", "full_name": "Vector Pack Signed Doubleword Signed Saturate", "summary": "Packs signed doublewords from two vector registers into a single vector register with signed saturation.", "description": "The instruction packs the contents of VSR[VRA+32] and VSR[VRB+32] into VSR[VRT+32], saturating signed values if they exceed the range of a 32-bit integer.", "syntax": "vpksdss VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x100005CE", "length": "32", "binary_pattern": "0 | VRT | VRA | VRB | 1486", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nfor i from 0 to 3 do\n VSR[VRT+32].word[i] ← si32_CLAMP(EXTS(VSR[VRA+32].dword[i]))\n if value > 2^31 - 1 then\n SAT is set to 1\n else if value < -(2^31) then\n SAT is set to 1", "special_registers": "VSCR (SAT)", "programming_notes": "This instruction is useful for packing two 64-bit signed integers into a single 128-bit vector, with saturation applied to handle overflow. Ensure that the input vectors are correctly aligned and that the VSCR.SAT flag is checked after execution to determine if any values were saturated. This operation requires vector processing privileges.", "extended_mnemonics": [], "page_found": "Page 306 - 308", "example": "vpksdss v1, v2, v3" }, { "mnemonic": "vupkhsw", "architecture": "PowerISA", "full_name": "Vector Unpack High Signed Word", "summary": "Unpacks the high signed words from a vector register into a doubleword format.", "description": "Unpacks the two high-order signed 32-bit words from vector register VRB into two signed 64-bit doublewords in VRT, sign-extending each word. This instruction is part of the VMX (AltiVec) category and does not update condition registers.", "syntax": "vupkhsw VRT,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x1000064E", "length": "32", "binary_pattern": "0 | VRT | VRB | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0", "bit_positions": "" }, "extension": "VMX (AltiVec)", "pseudocode": "VRT[0:63] ← EXTS(VRB[0:31])\nVRT[64:127] ← EXTS(VRB[32:63])", "special_registers": null, "programming_notes": "This instruction is used to extract the high signed word from each vector element of VRB and store it in the corresponding doubleword element of VRT. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector Unavailable exception will be raised. The operation is performed on 32-bit elements, so alignment requirements are based on these boundaries.", "extended_mnemonics": [], "page_found": "Page 312 - 314", "example": "vupkhsw v1, v3" }, { "mnemonic": "vsldbi", "architecture": "PowerISA", "full_name": "Vector Shift Left Double by Bit Immediate", "summary": "Shifts the contents of two vector registers left by a specified number of bits and places the result into another vector register.", "description": "The contents of VSR[VRA+32] concatenated with the contents of VSR[VRB+32] are shifted left by SH bits. The result is placed into VSR[VRT+32].", "syntax": "vsldbi VRT,VRA,VRB,SH", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "SH", "desc": "Shift Amount (0-7)" } ], "encoding": { "format": "VN-form", "hex_opcode": "0x10000016", "length": "32", "binary_pattern": "0 | VRT | VRA | VRB | 0 | SH | 22", "bit_positions": "" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nvsrc.qword[0] ← VSR[VRA+32]\nvsrc.qword[1] ← VSR[VRB+32]\nVSR[VRT+32] ← vsrc.bit[SH:SH+127]", "special_registers": null, "programming_notes": "This instruction is used to perform a left shift on the concatenated contents of two vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The shift amount (SH) must be within the range of 0 to 127 bits. Be cautious with alignment as the operation involves concatenating and shifting double quadword values.", "extended_mnemonics": [], "page_found": "Page 324 - 326", "example": "vsldbi v1, v2, v3, 3" }, { "mnemonic": "vextuhlx", "architecture": "PowerISA", "full_name": "Vector Extract Unsigned Halfword to GPR using GPR-specified Left-Index", "summary": "Extracts an unsigned halfword from a vector register and places it into a general-purpose register using the left index specified in another general-purpose register.", "description": "The instruction extracts an unsigned halfword from VSR[VRB+32] based on the left index specified in bits 60:63 of GPR[RA]. The extracted halfword is placed into bits 48:63 of GPR[RT], and bits 0:47 of GPR[RT] are set to zero. If the index is greater than 14, the results are undefined.", "syntax": "vextuhlx RT,RA,VRB", "operands": [ { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "VRB", "desc": "Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x1000064D", "length": "32", "binary_pattern": "4 | RT | RA | VRB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nindex ← GPR[RA].bit[60:63]\nGPR[RT] ← EXTZ64(VSR[VRB+32].byte[index:index+1])\nif index > 14 then\n undefined", "special_registers": "MSR", "programming_notes": "This instruction is used to extract an unsigned halfword from a vector register into a general-purpose register. Ensure the left index specified in bits 60:63 of GPR[RA] does not exceed 14 to avoid undefined behavior. The result is zero-extended to 64 bits, so only the upper 16 bits of GPR[RT] will contain valid data.", "extended_mnemonics": [], "page_found": "Page 332 - 334", "example": "vextuhlx r3, r4, v3" }, { "mnemonic": "vextdubvlx", "architecture": "PowerISA", "full_name": "Vector Extract Double Unsigned Byte to VSR Using GPR-specified Left-Index VA-form", "summary": "Extracts a double unsigned byte from two vector registers using a left-index specified by a general-purpose register and places it into another vector register.", "description": "The instruction extracts a double unsigned byte from the concatenation of two vector registers (VRA+32 and VRB+32) based on an index derived from bits 59:63 of GPR[RC]. The extracted byte is zero-extended and placed into the first doubleword of VSR[VRT+32], while the second doubleword is set to zero.", "syntax": "vextdubvlx VRT,VRA,VRB,RC", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "RC", "desc": "General Purpose Register containing the index" }, { "name": "VD", "desc": "Destination Vector Register" }, { "name": "VS", "desc": "Source Vector Register" }, { "name": "VSRA", "desc": "Index Source Vector Register" } ], "encoding": { "format": "VA-form", "hex_opcode": "0x10000018", "length": "32", "binary_pattern": "0 | VRT | VRA | VRB | RC", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nindex ← GPR[RC].bit[59:63]\nvsrc.qword[0] ← VSR[VRA+32]\nvsrc.qword[1] ← VSR[VRB+32]\nVSR[VRT+32].dword[0] ← EXTZ64(vsrc.byte[index])\nVSR[VRT+32].dword[1] ← 0x0000_0000_0000_0000", "special_registers": "N/A", "programming_notes": "This instruction is useful for extracting a specific byte from two concatenated vector registers and placing it into the first doubleword of another VSR, with the second doubleword zeroed. Ensure that the index derived from GPR[RC] bits 59:63 is within bounds to avoid undefined behavior. The instruction requires the Vector Facility to be enabled; otherwise, a Vector_Unavailable exception will be raised.", "extended_mnemonics": [], "page_found": "Page 334 - 336", "example": "vextdubvlx v1, v2, v3, r6" }, { "mnemonic": "crnor", "architecture": "PowerISA", "full_name": "Condition Register NOR XL-form", "summary": "Performs a bitwise NOR operation on the specified bits of the Condition Registers and stores the result in another bit of the Condition Register.", "description": "The bit in the Condition Register specified by BA+32 is ORed with the bit in the Condition Register specified by BB+32, and the complemented result is placed into the bit in the Condition Register specified by BT+32.", "syntax": "crnor BT,BA,BB", "operands": [ { "name": "BT", "desc": "Target Condition Register Bit" }, { "name": "BA", "desc": "Source Condition Register Bit" }, { "name": "BB", "desc": "Source Condition Register Bit" } ], "encoding": { "format": "XL-form", "hex_opcode": "0x4C000042", "length": "32", "binary_pattern": "0 | BT | BA | BB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "Base", "pseudocode": "CRBT+32 ←¬(CRBA+32 | CRBB+32)", "special_registers": "CR", "programming_notes": "The crnor instruction performs a bitwise OR operation on two condition register bits, then complements the result and stores it in another condition register bit. Ensure that the BA, BB, and BT fields are correctly set to avoid unintended behavior. This instruction operates at user privilege level.", "extended_mnemonics": [ { "mnemonic": "crnot", "equivalent_to": "crnor Bx,By,By" }, { "mnemonic": "crset", "equivalent_to": "creqv Bx,Bx,Bx" } ], "page_found": "Page 79 - 80", "example": "crnor 0, 1, 2" }, { "mnemonic": "lhax", "architecture": "PowerISA", "full_name": "Load Halfword Algebraic Indexed X-form", "summary": "Loads a halfword from memory into a register and extends it to a full word, with indexed addressing.", "description": "The effective address (EA) is the sum of the contents of registers RA and RB. The halfword in storage addressed by EA is loaded into RT48:63, and RT0:47 are filled with a copy of bit 0 of the loaded halfword.", "syntax": "lhax RT,RA,RB", "operands": [ { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RA", "desc": "Base General Purpose Register" }, { "name": "RB", "desc": "Index General Purpose Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C0002AE", "length": "32", "binary_pattern": "18 | LI | AA | LK", "bit_positions": "0:5 | 6:29 | 30 | 31" }, "extension": "Base", "pseudocode": "if RA = 0 then\n b ← 0\nelse\n b ← (RA)\nEA ← b + (RB)\nRT ← EXTS(MEM(EA, 2))", "special_registers": "", "programming_notes": "The lhax instruction is commonly used for loading a signed halfword from memory into the upper half of a register. Ensure that RA and RB are correctly set to avoid incorrect effective address calculation. This instruction requires the operands to be properly aligned; accessing unaligned data can lead to exceptions. The result is sign-extended, so be cautious when interpreting the value in RT.", "extended_mnemonics": [], "page_found": "Page 87 - 88", "example": "lhax r3, r4, r5" }, { "mnemonic": "lwax", "architecture": "PowerISA", "full_name": "Load Word Algebraic Indexed X-form", "summary": "Loads a word from memory into a register using an indexed address.", "description": "Loads a 32-bit signed word from memory at address RA+RB, sign-extends it to 64 bits, and stores the result in GPR RT. This instruction is part of the Base category and does not update condition registers or the XER.", "syntax": "lwax RT,RA,RB", "operands": [ { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RA", "desc": "Source General Purpose Register (base address)" }, { "name": "RB", "desc": "Source General Purpose Register (offset)" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C0002AA", "length": "32", "binary_pattern": "0 | RT | RA | DS | 2", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "Base", "pseudocode": "EA ← (RA = 0 ? 0 : GPR(RA)) + GPR(RB)\nGPR(RT) ← EXTS([EA])", "special_registers": "", "programming_notes": "The lwax instruction is commonly used for loading a word from memory into a register using an indexed addressing mode. Ensure that the base address in RA is properly aligned to avoid misaligned access exceptions. This instruction operates at user privilege level and can raise an exception if the EA is out of bounds or if there are memory protection violations.", "extended_mnemonics": [], "page_found": "Page 89 - 90", "example": "lwax r3, r4, r5" }, { "mnemonic": "stdx", "architecture": "PowerISA", "full_name": "Store Doubleword Indexed X-form", "summary": "Stores a doubleword from a register to memory using an indexed address.", "description": "Stores a doubleword (64 bits) from register RS to memory at the address formed by adding the contents of RA and RB. The effective address is calculated as (RA|0) + RB. No condition registers or status fields are modified by this instruction.", "syntax": "stdx RS,RA,RB", "operands": [ { "name": "RS", "desc": "Source General Purpose Register" }, { "name": "RA", "desc": "Base Address General Purpose Register" }, { "name": "RB", "desc": "Index General Purpose Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C00012A", "length": "32", "binary_pattern": "62 | RS | RA | RB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "Base", "pseudocode": "EA ← (RA|0) + RB\n[EA] ← RS[0:63]", "special_registers": "", "programming_notes": "The stdx instruction is commonly used for storing a doubleword from a register into memory at an address derived from the sum of two registers. Ensure that RA and RB are correctly set to avoid incorrect memory addresses. This instruction operates in user mode and can raise exceptions if there's a protection fault or alignment error.", "extended_mnemonics": [], "page_found": "Page 95 - 96", "example": "stdx r3, r4, r5" }, { "mnemonic": "addex", "architecture": "PowerISA", "full_name": "Add Extended using alternate carry bit", "summary": "Adds the contents of two registers and an alternate carry bit, updating the condition register.", "description": "For addex, the sum of the contents of register RA, RB, and CY is placed into register RT. If CY=0, the sum (RA) + (RB) + OV is placed into register RT. For CY=0, OV is set to 1 if there is a carry out of bit 0 of the sum in 64-bit mode or there is a carry out of bit 32 of the sum in 32-bit mode, and set to 0 otherwise. OV32 is set to 1 if there is a carry out of bit 32 of the sum.", "syntax": "addex RT,RA,RB,CY", "operands": [ { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "RB", "desc": "Source General Purpose Register" }, { "name": "CY", "desc": "Alternate Carry Bit" } ], "encoding": { "format": "XO-form", "hex_opcode": "0x7C000154", "length": "32", "binary_pattern": "31 | RT | RA | RB | CY | 170", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:22 | 23:31" }, "extension": "Base", "pseudocode": "if CY=0 then\n RT ← (RA) + (RB) + OV", "special_registers": "CR0, XER", "programming_notes": "An addc-equivalent instruction using OV is not provided. An equivalent capability can be emulated by first initializing OV to 0, then using addex. OV can be initialized to 0 using subfo, subtracting any operand from itself.", "extended_mnemonics": [], "page_found": "Page 113 - 114", "example": "addex r3, r4, r5, 1" }, { "mnemonic": "maddhd", "architecture": "PowerISA", "full_name": "Multiply-Add High Doubleword", "summary": "Multiplies two 64-bit operands and adds the result to a third 64-bit operand, placing the high-order 64 bits of the sum into a target register.", "description": "The 64-bit operands (RA) and (RB) are multiplied to produce a 128-bit product. This product is then added to the 64-bit operand (RC). The high-order 64 bits of the resulting sum are placed into register RT.", "syntax": "maddhd RT,RA,RB,RC", "operands": [ { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "RB", "desc": "Source General Purpose Register" }, { "name": "RC", "desc": "Source General Purpose Register" } ], "encoding": { "format": "VA-form", "hex_opcode": "0x10000030", "length": "32", "binary_pattern": "0 | RT | RA | RB | RC", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "Base", "pseudocode": "prod0:127 ← (RA) × (RB)\nsum0:127 ← prod + EXTS(RC)\nRT ← sum0:63", "special_registers": "N/A", "programming_notes": "The maddhd instruction is useful for performing high-precision arithmetic operations where the product of two 64-bit numbers needs to be added to another 64-bit number, and only the high-order bits of the result are required. Ensure that the operands are correctly aligned and consider the potential for overflow in the intermediate product before adding RC. This instruction operates at a privilege level that allows it to be used in both user and supervisor modes.", "extended_mnemonics": [], "page_found": "Page 121 - 122", "example": "maddhd r3, r4, r5, r6" }, { "mnemonic": "popcntb", "architecture": "PowerISA", "full_name": "Population Count Bytes", "summary": "Counts the number of one bits in each byte of a register.", "description": "A count of the number of one bits in each byte of register RS is placed into the corresponding byte of register RA. This number ranges from 0 to 8, inclusive.", "syntax": "popcntb RA,RS", "operands": [ { "name": "RA", "desc": "Target General Purpose Register" }, { "name": "RS", "desc": "Source General Purpose Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C0000F4", "length": "32", "binary_pattern": "31 | RS | RA | /// | 122 | /", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "Base", "pseudocode": "for i = 0 to 7\n n ← 0\n for j = 0 to 7\n if (RS)(i×8)+j = 1 then\n n ← n+1\n RA(i×8):(i×8)+7 ← n", "special_registers": "N/A", "extended_mnemonics": [], "page_found": "Page 137 - 138", "example": "popcntb r4, r3" }, { "mnemonic": "rldcr", "architecture": "PowerISA", "full_name": "Rotate Left Doubleword then Clear Right", "summary": "Rotates the contents of register RS left by a variable number of bits specified by (RB)58:63, and clears the rightmost bits.", "description": "The contents of register RS are rotated 64 bits to the left by the number of bits specified by (RB)58:63. A mask is generated having 1-bits from bit 0 through bit ME and 0-bits elsewhere. The rotated data are ANDed with the generated mask, and the result is placed into register RA.", "syntax": "rldcr RT,RS,RB,ME", "operands": [ { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RS", "desc": "Source General Purpose Register" }, { "name": "RB", "desc": "Source General Purpose Register" }, { "name": "ME", "desc": "Mask End bit position" } ], "encoding": { "format": "MDS-form", "hex_opcode": "0x78000012", "length": "32", "binary_pattern": "0 | RS | RA | RB | ME | 9 | Rc", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:26 | 27:30 | 31" }, "extension": "Base", "pseudocode": "if 'rldcr' then\n n ← (RB)58:63\n r ← ROTL64((RS), n)\n ME ← me5 || me0:4\n m ← MASK(0, ME)\n RA ← r & m\nif 'rldcr.' then\n CR0 <- updated based on result", "special_registers": "CR0 (if Rc=1)", "programming_notes": "rldcr can be used to extract an n-bit field that starts at variable bit position b in register RS, left-justified RA), by setting RB58:63=b and ME=n-1. It can also be used to rotate the contents of a register left (right) by variable n bits, by setting RB58:63=n (64-n) and ME=63.", "extended_mnemonics": [ "insrdi RA,RS,b,n" ], "page_found": "Page 147 - 148", "example": "rldcr r3, r3, r5, 31" }, { "mnemonic": "extswsli", "architecture": "PowerISA", "full_name": "Extend Sign Word and Shift Left Immediate", "summary": "Sign-extends the low-order 32 bits of a register, shifts it left by SH bits, and places the result in another register.", "description": "The contents of the low order 32 bits of RS are sign-extended to 64 bits and then shifted left SH bits. Bits shifted out of bit 0 are lost. Zeros are supplied to vacated bits on the right. The result is placed in register RA.", "syntax": "extswsli RA,RS,SH", "operands": [ { "name": "RA", "desc": "Target General Purpose Register" }, { "name": "RS", "desc": "Source General Purpose Register" }, { "name": "SH", "desc": "Shift Amount (0-31)" } ], "encoding": { "format": "XS-form", "hex_opcode": "0x7C0006F4", "length": "32", "binary_pattern": "RS | RA | SH | 445 | Rc", "bit_positions": "6:10 | 11:15 | 16:20 | 21:29 | 30:31" }, "extension": "Base", "pseudocode": "SH ← sh5 || sh0:4\nr ← ROTL64(EXTS64(RS32:63), SH)\nm ← MASK(0, 63-SH)\nRA ← r & m", "special_registers": "CR0", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.", "extended_mnemonics": [], "page_found": "Page 151 - 152", "example": "extswsli r4, r3, 3" }, { "mnemonic": "brh", "architecture": "PowerISA", "full_name": "Byte-Reverse Halfword", "summary": "Reverses the byte order of a halfword in a register.", "description": "The contents of bits 0:15 of register RS are placed into bits 0:15 of register RA in byte-reversed order. The contents of bits 16:31 of register RS are placed into bits 16:31 of register RA in byte-reversed order.", "syntax": "brh RA,RS", "operands": [ { "name": "RA", "desc": "Target General Purpose Register" }, { "name": "RS", "desc": "Source General Purpose Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C0001B6", "length": "32", "binary_pattern": "0 | RS | RA | 6 | 11 | 16 | 21", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:30 | 31" }, "extension": "Base", "pseudocode": "RA ← (RS)8:15 || (RS)0:7\n (RS)24:31 || (RS)16:23", "special_registers": null, "programming_notes": "The brh instruction is useful for reversing the byte order of 16-bit halves within a 32-bit register. Ensure that the source and destination registers are correctly specified to avoid data corruption. This operation does not require any special privileges or alignment considerations.", "extended_mnemonics": [], "page_found": "Page 153 - 154", "example": "brh r4, r3" }, { "mnemonic": "pnop", "architecture": "PowerISA", "full_name": "Prefixed No-Operation Instruction", "summary": "No operation is performed.", "description": "A prefixed 64-bit no-operation instruction that performs no operation and has no side effects. This instruction is available in the Prefixed instruction set extension and occupies 64 bits in memory.", "syntax": "pnop", "operands": [], "encoding": { "format": "*-form", "hex_opcode": "0x07000000", "length": "64", "binary_pattern": "1 | 3 | 0 | /// | 0", "bit_positions": "" }, "extension": "Prefixed", "pseudocode": "No operation is performed.", "special_registers": null, "programming_notes": "The pnop instruction behaves as a b $+8 instruction regardless of its suffix. However, it does not cause any side effects such as modification of the Come From Address Register. If the value in the suffix of a pnop instruction corresponds to a Branch instruction, an rfebb instruction, a context synchronizing instruction other than isync, or a “Service Processor Attention” instruction, the instruction form is invalid.", "extended_mnemonics": [], "page_found": "Page 167 - 168", "example": "pnop" }, { "mnemonic": "lfd", "architecture": "PowerISA", "full_name": "Load Floating-Point Double D-form", "summary": "Loads a double-precision floating-point value from memory into a floating-point register.", "description": "The instruction loads the doubleword in storage addressed by EA into register FRT. The effective address (EA) is the sum of the contents of register RA, or the value 0 if RA=0, and the value D, sign-extended to 64 bits.", "syntax": "lfd FRT,D(RA)", "operands": [ { "name": "FRT", "desc": "Target Floating-Point Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "D", "desc": "16-bit signed displacement" } ], "encoding": { "format": "D-form", "hex_opcode": "0xC8000000", "length": "32", "binary_pattern": "0 | FRT | RA | D", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "Floating-Point", "pseudocode": "if RA = 0 then\n b ← 0\nelse\n b ← (RA)\nEA ← b + EXTS64(D)\nFRT ← MEM(EA, 8)", "special_registers": "N/A", "programming_notes": "The lfd instruction is commonly used to load double-precision floating-point numbers from memory into a floating-point register. Ensure that the address specified by RA and D is properly aligned on an 8-byte boundary to avoid alignment exceptions. This instruction operates at user privilege level, so no special privileges are required.", "extended_mnemonics": [], "page_found": "Page 187 - 188", "example": "lfd f1, 0(r4)" }, { "mnemonic": "stfs", "architecture": "PowerISA", "full_name": "Store Floating-Point Single D-form", "summary": "Stores a single-precision floating-point value from an FPR to memory.", "description": "The contents of register FRS are converted to single format and stored into the word in storage addressed by EA. The effective address (EA) is the sum of the contents of register RA, or the value 0 if RA=0, and the value D, sign-extended to 64 bits.", "syntax": "stfs FRS,D(RA)", "operands": [ { "name": "FRS", "desc": "Source Floating-Point Register" }, { "name": "D", "desc": "Displacement field" }, { "name": "RA", "desc": "Base General Purpose Register" } ], "encoding": { "format": "DS-form", "hex_opcode": "0xD0000000", "length": "32", "binary_pattern": "101000 | FRS | D | RA", "bit_positions": "" }, "extension": "Floating-Point", "pseudocode": "EA ← (RA|0) + EXTS64(D)\nMEM(EA, 4) ← SINGLE((FRS))", "special_registers": "FPSCR", "programming_notes": "The stfs instruction stores a single-precision floating-point value from FRS into memory. Ensure that the destination address is properly aligned to avoid alignment faults. The instruction operates at user privilege level and may raise an exception if the EA exceeds the storage limits or if there are access violations.", "extended_mnemonics": [], "page_found": "Page 189 - 190", "example": "stfs f1, 0(r4)" }, { "mnemonic": "stfd", "architecture": "PowerISA", "full_name": "Store Floating-Point Double D-form", "summary": "Stores a double-precision floating-point value from a register to memory.", "description": "The contents of the specified floating-point register (FRS) are stored into the double-word in storage addressed by the effective address (EA). The EA is calculated as the sum of the contents of register RA or 0 if RA=0, and the sign-extended value D.", "syntax": "stfd FRS,D(RA)", "operands": [ { "name": "FRS", "desc": "Floating-point Source Register" }, { "name": "D", "desc": "16-bit signed displacement" }, { "name": "RA", "desc": "Base General Purpose Register" } ], "encoding": { "format": "D-form", "hex_opcode": "0xD8000000", "length": "32", "binary_pattern": "0 | FRS | RA | D", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "Floating-Point", "pseudocode": "if RA = 0 then\n b ← 0\nelse\n b ← (RA)\nEA ← b + EXTS64(D)\nMEM(EA, 8) ← (FRS)", "special_registers": "FPSCR", "programming_notes": "The stfd instruction stores a double-precision floating-point value from a specified register into memory. Ensure the destination address is properly aligned to avoid alignment faults. The effective address is calculated by adding the base address in RA (or zero if RA is 0) and the sign-extended displacement D. This instruction operates at user privilege level.", "extended_mnemonics": [], "page_found": "Page 191 - 192", "example": "stfd f1, 0(r4)" }, { "mnemonic": "lfdp", "architecture": "PowerISA", "full_name": "Load Floating-Point Double Pair", "summary": "Loads a doubleword-pair from storage into an even-odd pair of FPRs.", "description": "For lfdp, the doubleword-pair in storage addressed by EA is loaded into an even-odd pair of FPRs with the even-numbered FPR being loaded with the leftmost doubleword from storage and the odd-numbered FPR being loaded with the rightmost doubleword.", "syntax": "lfdp FRTp,disp(RA)", "operands": [ { "name": "FRTp", "desc": "Target Floating-Point Register Pair" }, { "name": "RA", "desc": "Base General Purpose Register" }, { "name": "disp", "desc": "Displacement" } ], "encoding": { "format": "DS-form", "hex_opcode": "0xE4000000", "length": "32", "binary_pattern": "0 | FRTp | RA | DS | 0", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "Floating-Point", "pseudocode": "if RA = 0 then\n b ← 0\nelse\n b ← (RA)\nEA ← b + EXTS(DS || 0b00)\nFRTpeven ← MEM(EA, 8)\nFRTpodd ← MEM(EA + 8, 8)", "special_registers": "N/A", "programming_notes": "The instructions described in this section should not be used to access an operand in DFP Extended format when the processor is in Little-Endian mode.", "extended_mnemonics": [], "page_found": "Page 193 - 194", "example": "lfdp f2, disp(RA)" }, { "mnemonic": "fctidu", "architecture": "PowerISA", "full_name": "Floating Convert with round Double-Precision To Unsigned Doubleword format", "summary": "Converts a double-precision floating-point value to an unsigned 64-bit integer using rounding.", "description": "Let src be the double-precision floating-point value in FRB. If src is a NaN, then the result is 0x0000_0000_0000_0000, VXCVI is set to 1, and if src is an SNaN, VXSNAN is set to 1. Otherwise, src is rounded to a floating-point integer using the rounding mode specified by RN. If the rounded value is greater than 264-1, then the result is 0xFFFF_FFFF_FFFF_FFFF, and VXCVI is set to 1. Otherwise, if the rounded value is less than 0, then the result is 0x0000_0000_0000_0000, and VXCVI is set to 1. Otherwise, the result is the rounded value converted to 64-bit unsigned-integer format, and XX is set to 1 if the result is inexact.", "syntax": "fctidu FRT,FRB", "operands": [ { "name": "FRT", "desc": "Target Floating Point Register" }, { "name": "FRB", "desc": "Source Floating Point Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0xFC00075C", "length": "32", "binary_pattern": "63 | FRT | / | FRB | 942 | Rc", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "Floating-Point", "pseudocode": "if src is a NaN then\n FRT <- 0x0000_0000_0000_0000\n VXCVI <- 1\n if src is an SNaN then VXSNAN <- 1\nelse\n rounded_value <- round(src, RN)\n if rounded_value > 264-1 then\n FRT <- 0xFFFF_FFFF_FFFF_FFFF\n VXCVI <- 1\n else if rounded_value < 0 then\n FRT <- 0x0000_0000_0000_0000\n VXCVI <- 1\n else\n FRT <- convert_to_unsigned_integer(rounded_value)\n XX <- is_inexact(FRT)\nif not enabled Invalid Operation Exception then\n place result into FRT", "special_registers": "FPSCR, (FR, FI, FX, XX, VXSNAN, VXCVI), CR1, (if, Rc=1), CR0", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "extended_mnemonics": [], "page_found": "Page 207 - 208", "example": "fctidu f1, f3" }, { "mnemonic": "fctiwu", "architecture": "PowerISA", "full_name": "Floating Convert with round Double-Precision To Unsigned Word format", "summary": "Converts a double-precision floating-point value to an unsigned integer using rounding.", "description": "The instruction converts the double-precision floating-point value in FRB to an unsigned integer using the rounding mode specified by RN. If the result is out of range, it sets VXCVI and returns 0xFFFF_FFFF or 0x0000_0000. The result is placed into FRT32:63 and FRT0:31 is undefined.", "syntax": "fctiwu FRT,FRB", "operands": [ { "name": "FRT", "desc": "Target Floating-Point Register" }, { "name": "FRB", "desc": "Source Floating-Point Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0xFC00011C", "length": "32", "binary_pattern": "0 | FRT | FRB | Rc", "bit_positions": "0:5 | 6:10 | 11:30 | 31" }, "extension": "Floating-Point", "pseudocode": "if src is NaN then\n result <- 0x0000_0000\n VXCVI <- 1\n if src is SNaN then VXSNAN <- 1\nelse\n rounded_value <- round(src, RN)\n if rounded_value > 2^32 - 1 then\n result <- 0xFFFF_FFFF\n VXCVI <- 1\n else if rounded_value < 0 then\n result <- 0x0000_0000\n VXCVI <- 1\n else\n result <- convert_to_unsigned_int(rounded_value)\n XX <- is_inexact(result)\nFRT32:63 <- result\nFRT0:31 is undefined", "special_registers": "FPSCR, (FR, FI, FX, XX, VXSNAN, VXCVI), CR1, (if, Rc=1), CR0", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "extended_mnemonics": [], "page_found": "Page 209 - 210", "example": "fctiwu f1, f3" }, { "mnemonic": "frip", "architecture": "PowerISA", "full_name": "Floating Round to Integer Plus", "summary": "Rounds a floating-point operand towards +infinity and places the result into a register.", "description": "The floating-point operand in register FRB is rounded to an integral value using the rounding mode round toward +infinity, and the result is placed into register FRT. FPRF is set to the class and sign of the result, except for Invalid Operation Exceptions when VE=1.", "syntax": "frip FRT,FRB", "operands": [ { "name": "FRT", "desc": "Target Floating-Point Register" }, { "name": "FRB", "desc": "Source Floating-Point Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0xFC000390", "length": "32", "binary_pattern": "0 | FRT | FRB | Rc", "bit_positions": "0:5 | 6:10 | 11:30 | 31" }, "extension": "Floating-Point", "pseudocode": "if 'frip' then\n FRT <- round_towards_plus_infinity(FRB)\nelse if 'frip.' then\n FRT <- round_towards_plus_infinity(FRB)\n update_CR1_based_on_result(FRT)", "special_registers": "FPSCR, CR, CR0", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "extended_mnemonics": [], "page_found": "Page 213 - 214", "example": "frip f1, f3" }, { "mnemonic": "mffsl", "architecture": "PowerISA", "full_name": "Move From FPSCR Lightweight", "summary": "Moves the control and non-sticky status bits from the FPSCR to a general-purpose register.", "description": "The contents of the control bits in the FPSCR (bits 29:31) and the non-sticky status bits (bits 45:51) are placed into the corresponding bits in register FRT. All other bits in register FRT are set to 0.", "syntax": "mffsl FRT", "operands": [ { "name": "FRT", "desc": "Target General Purpose Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0xFC00048E", "length": "32", "binary_pattern": "63 | FRT | /// | 0", "bit_positions": "0:5 | 6:10 | 11:30 | 31" }, "extension": "Floating-Point", "pseudocode": "FRT <- (FPSCR[29:31] || FPSCR[45:51])", "special_registers": "FPSCR", "programming_notes": "mffsl permits software to read the control and non-sticky status bits in the FPSCR without the higher latency typically associated with accessing the sticky status bits.", "extended_mnemonics": [], "page_found": "Page 219 - 220", "example": "mffsl f1" }, { "mnemonic": "dtstdc", "architecture": "PowerISA", "full_name": "Test Data Class", "summary": "Tests the data class of a DFP operand and sets the CR field.", "description": "Tests the data class of the DFP operand in FRA against the data class mask DCM and stores the test result in condition register field BF. The instruction sets CR field BF based on whether FRA belongs to any of the classes specified by the 8-bit mask DCM. This is a Decimal Floating-Point instruction that requires the DFP category.", "syntax": "dtstdc BF,FRA,DCM", "operands": [ { "name": "BF", "desc": "Condition Register Field" }, { "name": "FRA", "desc": "Floating-Point Register A" }, { "name": "DCM", "desc": "Data Class Mask" } ], "encoding": { "format": "Z22-form", "hex_opcode": "0xEC000184", "length": "32", "binary_pattern": "0 | BF | FRA | DCM | 194", "bit_positions": "0:5 | 6:8 | 9:10 | 11:15 | 16:31" }, "extension": "Decimal Floating-Point", "pseudocode": "if (FRA matches any data class in DCM) then\n CR[BF] ← 0b0010\nelse\n CR[BF] ← 0b0000", "special_registers": "CR, FPSCR", "programming_notes": "The dtstdc instruction is used to test the data class of a decimal floating-point operand against a specified mask. Ensure that the DFP operand is correctly aligned and that the DCM mask accurately reflects the desired data classes for testing. The instruction updates the CR field BF and FPSCR FPCC based on the sign and data class match, which can be used in conditional logic within your program.", "extended_mnemonics": [], "page_found": "Page 245 - 246", "example": "dtstdc cr0, f2, 0" }, { "mnemonic": "dtstsf", "architecture": "PowerISA", "full_name": "Decimal Floating-Point Test Significance Single", "summary": "Tests the significance of a DFP value in FPR[FRB] against a reference significance.", "description": "Compares the number of significant digits (NSDb) of the DFP value in FPR[FRB] with the reference significance specified by bits 58:63 of FPR[FRA]. The result is placed into CR field BF and FPCC.", "syntax": "dtstsf BF,FRA,FRB", "operands": [ { "name": "BF", "desc": "Condition Register Field" }, { "name": "FRA", "desc": "Floating-Point Register A" }, { "name": "FRB", "desc": "Floating-Point Register B" } ], "encoding": { "format": "X-form", "hex_opcode": "0xEC000544", "length": "32", "binary_pattern": "0 | BF | FRA | FRB", "bit_positions": "0:5 | 6:8 | 9:10 | 11:31" }, "extension": "Decimal Floating-Point", "pseudocode": "let k be the contents of bits 58:63 of FPR[FRA]\nlet NSDb be the number of significant digits of the DFP value in FPR[FRB]\nif k != 0 and k < NSDb then\n CR field BF <- 0b0010\n FPCC <- 0b0010\nelse if k != 0 and k > NSDb, or k = 0 then\n CR field BF <- 0b0100\n FPCC <- 0b0100\nelse if k != 0 and k = NSDb then\n CR field BF <- 0b1000\n FPCC <- 0b1000\nelse\n CR field BF <- 0b0001\n FPCC <- 0b0001", "special_registers": "CR, FPSCR", "programming_notes": "The dtstsf instruction is used to compare the number of significant digits in a decimal floating-point value with a reference significance. Ensure that the FPR registers are correctly aligned and initialized before use. The instruction modifies both CR and FPSCR, so check these registers after execution for the comparison result. This instruction operates at user privilege level but may raise exceptions if the input values are invalid or out of range.", "extended_mnemonics": [], "page_found": "Page 247 - 248", "example": "dtstsf cr0, f2, f3" }, { "mnemonic": "dquai", "architecture": "PowerISA", "full_name": "DFP Quantize Immediate", "summary": "Adjusts the value to a form having the specified exponent in the range -16 to 15.", "description": "The DFP operand in FRB is converted and rounded to the form with the exponent specified by TE based on the rounding mode specified in the RMC field. The result of that form is placed in FRT. The sign of the result is the same as the sign of the operand in FRB.", "syntax": "dquai TE,FRT,FRB,RMC", "operands": [ { "name": "TE", "desc": "Target Exponent" }, { "name": "FRT", "desc": "Target Floating-Point Register" }, { "name": "FRB", "desc": "Source Floating-Point Register" }, { "name": "RMC", "desc": "Rounding Mode Control" } ], "encoding": { "format": "Z23-form", "hex_opcode": "0xEC000086", "length": "32", "binary_pattern": "0 | FRT | TE | FRB | RMC | Rc", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "Decimal Floating-Point", "pseudocode": "if 'dquai' then\n FRT <- (FRB) adjusted to exponent TE with rounding based on RMC\n if result would cause overflow from the most significant digit, then\n FRT <- default QNaN\n else\n FRT <- adjusted value (left shifted with matching exponent)\nif 'dquai.' then\n FRT <- (FRB) adjusted to exponent TE with rounding based on RMC\n if result would cause overflow from the most significant digit, then\n FRT <- default QNaN\n else\n FRT <- adjusted value (left shifted with matching exponent)\n CR1 <- updated", "special_registers": "FPSCR(FPRF, FR, FI, FX, XX, VXSNAN, VXCVI), CR(CR1), CR0", "programming_notes": "DFP Quantize Immediate can be used to adjust values to a form having the specified exponent in the range -16 to 15. If the adjustment requires the significand to be shifted left, then: if the result would cause overflow from the most significant digit, the result is a default QNaN; otherwise the result is the adjusted value (left shifted with matching exponent). If the adjustment requires the significand to be shifted right, the result is rounded based on the value of the RMC field.", "extended_mnemonics": [ "dquai", "dquai." ], "page_found": "Page 249 - 250", "example": "dquai te, f1, f3, 0" }, { "mnemonic": "ctfix", "architecture": "PowerISA", "full_name": "Convert To Fixed", "summary": "Converts a decimal floating-point value to a fixed-point integer.", "description": "Converts a Decimal Floating-Point value in FRA to a fixed-point integer representation and stores the result in FRT. This instruction requires the Decimal Floating-Point category and may set exception flags in FPSCR if conversion fails or overflow/underflow occurs.", "syntax": "ctfix FRT,FRA", "operands": [ { "name": "FRT", "desc": "Target Floating-Point Register" }, { "name": "FRA", "desc": "Source Floating-Point Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0xEC000000", "length": "32", "binary_pattern": "10011000 | FRT | FRA | 0000000000000000", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "Decimal Floating-Point", "pseudocode": "FRT ← convert_dfp_to_fixed(FRA)\n# FPSCR exception flags updated as needed", "special_registers": "FI, FR, VXCVI, VXSNAN, XX, FPSCR", "programming_notes": "The ctfix instruction is used to convert floating-point numbers to fixed-point integers. Ensure the source operand is properly aligned and within valid range to avoid exceptions. Be cautious of rounding modes as they can affect the result significantly. This instruction operates at user privilege level but may trigger exceptions like inexact conversion or invalid operations, which need to be handled appropriately.", "extended_mnemonics": [], "page_found": "Page 264 - 265", "example": "ctfix f1, f2" }, { "mnemonic": "stvehx", "architecture": "PowerISA", "full_name": "Store Vector Element Halfword Indexed X-form", "summary": "Stores a halfword element from a vector register to memory.", "description": "Stores a halfword (16 bits) element from vector register VRS to memory at the indexed address (RA|0) + RB. The element is selected based on the least significant bits of the effective address to determine alignment. This is a VMX/AltiVec instruction that accesses memory with vector element granularity.", "syntax": "stvehx VRS,RA,RB", "operands": [ { "name": "VRS", "desc": "Vector Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "RB", "desc": "Source General Purpose Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C00014E", "length": "32", "binary_pattern": "011111 | VRS | RA | RB | 00101 | 00111 | Rc", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:30 | 31" }, "extension": "VMX (AltiVec)", "pseudocode": "EA ← (RA|0) + RB\nelement_index ← EA[61:62]\n[EA & ~0x1] ← VRS[element_index * 16 : element_index * 16 + 15]", "special_registers": "N/A", "programming_notes": "Unless bits 60:62 of the address are known to match the halfword offset of the subject halfword element in VSR[VRS+32], software should use Vector Splat to splat the subject halfword element before performing the store.", "extended_mnemonics": [], "page_found": "Page 299 - 300", "example": "stvehx v1, r4, r5" }, { "mnemonic": "vpkudum", "architecture": "PowerISA", "full_name": "Vector Pack Unsigned Doubleword Modulo", "summary": "Packs the upper halves of doublewords from two source vectors into a destination vector.", "description": "Packs unsigned doubleword elements from source vectors VRA and VRB into a destination vector VRT by selecting the upper halves of each doubleword and concatenating them in pack order. This VMX/AltiVec instruction performs modulo packing without saturation and operates on 64-bit elements.", "syntax": "vpkudum VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x1000044E", "length": "32", "binary_pattern": "4 | VRT | VRA | VRB | 1102", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VMX (AltiVec)", "pseudocode": "VRT[0:63] ← VRA[0:63]\nVRT[64:127] ← VRB[0:63]", "special_registers": "MSR", "programming_notes": "This instruction is used for packing the upper halves of doublewords from two source vectors into a destination vector. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set; otherwise, a Vector Unavailable exception will be raised. The operation processes each element independently, so there are no ordering requirements between elements, but alignment of input vectors to doubleword boundaries is recommended for optimal performance.", "extended_mnemonics": [], "page_found": "Page 309 - 310", "example": "vpkudum v1, v2, v3" }, { "mnemonic": "vslv", "architecture": "PowerISA", "full_name": "Vector Shift Left Variable", "summary": "Shifts the contents of vector elements left by a variable amount.", "description": "Shifts each element of the source vector left by a variable amount specified in the corresponding element of the shift amount vector. The shift amount for each element is taken from the least significant bits of the corresponding element in VRB. No status flags are affected.", "syntax": "vslv VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Shift Amount Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x10000744", "length": "32", "binary_pattern": "4 | VRT | VRA | VRB | 1860", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VMX (AltiVec)", "pseudocode": "for i in 0 to 15 do\n shamt ← (VRB[i*8:(i+1)*8-1]) & 0x7\n VRT[i*8:(i+1)*8-1] ← VRA[i*8:(i+1)*8-1] << shamt\nend for", "special_registers": "N/A", "programming_notes": "The vslv instruction is used to perform variable left shifts on each byte of a vector register. Ensure that the shift amounts in VSR[VRB+32] are within the valid range (0-7) to avoid unexpected results. This instruction operates at user privilege level and will raise an exception if the Vector Facility is not enabled.", "extended_mnemonics": [], "page_found": "Page 327 - 328", "example": "vslv v1, v2, v3" }, { "mnemonic": "vsrv", "architecture": "PowerISA", "full_name": "Vector Shift Right Variable", "summary": "Shifts each element of the source vector right by a variable amount specified in another vector.", "description": "Shifts each element of the source vector right by a variable amount specified in the corresponding element of the shift count vector. The shift amount for each element is taken from the least significant bits of the corresponding element in VRB. No status flags are affected.", "syntax": "vsrv vTMP1, vSRC, vSHCT1", "operands": [ { "name": "vTMP1", "desc": "Destination Vector Register" }, { "name": "vSRC", "desc": "Source Vector Register" }, { "name": "vSHCT1", "desc": "Shift Count Vector Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0x10000704", "length": "32", "binary_pattern": "4 | VRT | VRA | VRB | 1796", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VMX (AltiVec)", "pseudocode": "for i in 0 to 15 do\n shamt ← (VRB[i*8:(i+1)*8-1]) & 0x7\n VRT[i*8:(i+1)*8-1] ← VRA[i*8:(i+1)*8-1] >> shamt\nend for", "special_registers": "N/A", "programming_notes": "The vsrv instruction shifts each element of the source vector right by a variable amount specified in another vector. Ensure that the shift amounts are within the range of 0 to 127 to avoid undefined behavior. This instruction operates at user privilege level and does not generate exceptions for normal operation.", "extended_mnemonics": [], "page_found": "Page 328 - 329", "example": "vsrv vtmp1, vsrc, vshct1" }, { "mnemonic": "vextublx", "architecture": "PowerISA", "full_name": "Vector Extract Unsigned Byte to GPR using GPR-specified Left-Index VX-form", "summary": "Extracts an unsigned byte from a vector register and places it into a general-purpose register using the left-index specified in another general-purpose register.", "description": "The contents of byte element index of VSR[VRB+32] are placed into bits 56:63 of GPR[RT], where index is the contents of bits 60:63 of GPR[RA]. The contents of bits 0:55 of GPR[RT] are set to 0.", "syntax": "vextublx RT,RA,VRB", "operands": [ { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RA", "desc": "Source General Purpose Register containing the index" }, { "name": "VRB", "desc": "Vector Register B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "RB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x1000060D", "length": "32", "binary_pattern": "0 | RT | RA | VRB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nindex ← GPR[RA].bit[60:63]\nGPR[RT] ← EXTZ64(VSR[VRB+32].byte[index])\n// The contents of bits 0:55 of GPR[RT] are set to 0.", "special_registers": "N/A", "programming_notes": "This instruction extracts an unsigned byte from a vector register and places it into the upper 8 bits of a general-purpose register, zeroing out the lower 56 bits. Ensure that the index in GPR[RA] is within bounds (0-15) to avoid undefined behavior. This operation requires the Vector Facility to be enabled; otherwise, a Vector Unavailable exception will occur.", "extended_mnemonics": [], "page_found": "Page 331 - 332", "example": "vextublx r3, r4, v3" }, { "mnemonic": "vextuwlx", "architecture": "PowerISA", "full_name": "Vector Extract Unsigned Word to GPR using GPR-specified Left-Index VX-form", "summary": "Extracts an unsigned word from a vector register and places it into a general-purpose register.", "description": "The instruction extracts an unsigned word from the specified byte index in VSR[VRB+32] and places it into bits 32:63 of GPR[RT]. The contents of bits 0:31 of GPR[RT] are set to 0. If MSR.VEC=0, a Vector_Unavailable() exception is raised.", "syntax": "vextuwlx RT,RA,VRB", "operands": [ { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RA", "desc": "Source General Purpose Register (contains the index)" }, { "name": "VRB", "desc": "Vector Register B" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x1000068D", "length": "32", "binary_pattern": "0 | RT | RA | VRB", "bit_positions": "" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nindex ← GPR[RA].bit[60:63]\nGPR[RT] ← EXTZ64(VSR[VRB+32].byte[index:index+3])\nif index > 12 then\n undefined", "special_registers": "MSR", "programming_notes": "This instruction is used to extract an unsigned word from a vector register and place it into the upper half of a general-purpose register. Ensure that the MSR.VEC bit is set to avoid a Vector_Unavailable exception. The index for extraction is derived from the top 4 bits of the RA register, so be cautious with the value in RA to prevent undefined behavior when the index exceeds 12.", "extended_mnemonics": [], "page_found": "Page 333 - 334", "example": "vextuwlx r3, r4, v3" }, { "mnemonic": "vextduhvlx", "architecture": "PowerISA", "full_name": "Vector Extract Double Unsigned Halfword to VSR using GPR-specified Left-Index VA-form", "summary": "Extracts a double unsigned halfword from two vector registers and places it into another vector register based on the index specified in a general-purpose register.", "description": "The instruction extracts a double unsigned halfword from the concatenation of VSR[VRA+32] and VSR[VRB+32] using the index specified in bits 59:63 of GPR[RC]. The extracted byte elements are zero-extended and placed into doubleword 0 of VSR[VRT+32], while doubleword 1 is set to zero.", "syntax": "vextduhvlx VRT,VRA,VRB,RC", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "RC", "desc": "General Purpose Register specifying the index" } ], "encoding": { "format": "VA-form", "hex_opcode": "0x1000001A", "length": "32", "binary_pattern": "0 | VRT | VRA | VRB | RC | 26", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nindex ← GPR[RC].bit[59:63]\nvsrc.qword[0] ← VSR[VRA+32]\nvsrc.qword[1] ← VSR[VRB+32]\nVSR[VRT+32].dword[0] ← EXTZ64(vsrc.byte[index:index+1])\nVSR[VRT+32].dword[1] ← 0x0000_0000_0000_0000", "special_registers": null, "programming_notes": "This instruction is used to extract a double unsigned halfword from two vector registers and place it into another vector register. Ensure that the index specified in GPR[RC] is within bounds to avoid undefined behavior. The operation requires the VEC bit in the MSR to be set; otherwise, a Vector Unavailable exception will occur.", "extended_mnemonics": [], "page_found": "Page 335 - 336", "example": "vextduhvlx v1, v2, v3, r6" }, { "mnemonic": "vextduwvlx", "architecture": "PowerISA", "full_name": "Vector Extract Double Unsigned Word to VSR using GPR-specified Left-Index VA-form", "summary": "Extracts a doubleword from the concatenation of two vector registers based on an index specified in a general-purpose register.", "description": "The instruction extracts a doubleword from the concatenation of the contents of VSR[VRA+32] and VSR[VRB+32] based on the index derived from bits 59:63 of GPR[RC]. The extracted bytes are zero-extended into the first doubleword of VSR[VRT+32], and the second doubleword is set to zero.", "syntax": "vextduwvlx VRT,VRA,VRB,RC", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "RC", "desc": "General Purpose Register containing the index" } ], "encoding": { "format": "VA-form", "hex_opcode": "0x1000001C", "length": "32", "binary_pattern": "000100 | VRT | VRA | VRB | RC | 011100", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nindex ← GPR[RC].bit[59:63]\nsrc.qword[0] ← VSR[VRA+32]\nsrc.qword[1] ← VSR[VRB+32]\nVSR[VRT+32].dword[0] ← EXTZ64(src.byte[index:index+3])\nVSR[VRT+32].dword[1] ← 0x0000_0000_0000_0000\nif index > 28 then\n undefined result", "special_registers": "N/A", "programming_notes": "This instruction is used to extract a doubleword from the concatenation of two vector registers based on an index specified in a general-purpose register. Ensure that the index does not exceed 28 to avoid undefined results. The operation requires the VEC bit in the Machine State Register (MSR) to be set; otherwise, a Vector Unavailable exception will occur.", "extended_mnemonics": [], "page_found": "Page 336 - 337", "example": "vextduwvlx v1, v2, v3, r6" }, { "mnemonic": "vextddvlx", "architecture": "PowerISA", "full_name": "Vector Extract Double Doubleword to VSR using GPR-specified Left-Index VA-form", "summary": "Extracts a doubleword from the concatenation of two vector registers based on an index specified in a general-purpose register.", "description": "The instruction extracts a doubleword from the concatenation of the contents of VSR[VRA+32] and VSR[VRB+32] using an index derived from bits 59:63 of GPR[RC]. The extracted byte elements are placed into doubleword 0 of VSR[VRT+32], while doubleword 1 is set to zero.", "syntax": "vextddvlx VRT,VRA,VRB,RC", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "RC", "desc": "General Purpose Register containing the index" } ], "encoding": { "format": "VA-form", "hex_opcode": "0x1000001E", "length": "32", "binary_pattern": "0 | VRT | VRA | VRB | RC", "bit_positions": "" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nindex ← GPR[RC].bit[59:63]\nsrc.qword[0] ← VSR[VRA+32]\nsrc.qword[1] ← VSR[VRB+32]\nVSR[VRT+32].dword[0] ← src.byte[index:index+7]\nVSR[VRT+32].dword[1] ← 0x0000_0000_0000_0000", "special_registers": "N/A", "programming_notes": "This instruction is useful for extracting a specific doubleword from two VSX registers based on an index specified in a GPR. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise a Vector Unavailable exception. The index is derived from bits 59:63 of the GPR, so ensure these bits are correctly set to access the desired doubleword. Note that the upper doubleword of the destination register is always zeroed.", "extended_mnemonics": [], "page_found": "Page 337 - 338", "example": "vextddvlx v1, v2, v3, r6" }, { "mnemonic": "vinsblx", "architecture": "PowerISA", "full_name": "Vector Insert Byte from GPR using GPR-specified Left-Index VX-form", "summary": "Inserts a byte from a general-purpose register into a vector register at an index specified by another general-purpose register.", "description": "The contents of bits 56:63 of GPR[RB] are placed into byte element index of VSR[VRT+32], where index is the contents of bits 60:63 of GPR[RA]. All other byte elements of VSR[VRT+32] remain unchanged.", "syntax": "vinsblx VRT,RA,RB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "RA", "desc": "Source General Purpose Register (index)" }, { "name": "RB", "desc": "Source General Purpose Register (data)" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x1000020F", "length": "32", "binary_pattern": "18 | VRT | RA | RB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nindex ← GPR[RA].bit[60:63]\nsrc.byte[0:15] ← 0\nVSR[VRT+32].byte[index] ← GPR[RB].bit[56:63]", "special_registers": null, "programming_notes": "The vinsblx instruction is used to insert a byte from a general-purpose register (GPR) into a vector register, using another GPR to specify the index. Ensure that the MSR.VEC bit is set to 1; otherwise, a Vector_Unavailable exception will be raised. The index must be within the range of 0-15, as it specifies which byte element in the vector register to update. This instruction does not require any special alignment and operates at privilege level 0.", "extended_mnemonics": [], "page_found": "Page 340 - 341", "example": "vinsblx v1, r4, r5" }, { "mnemonic": "vinshlx", "architecture": "PowerISA", "full_name": "Vector Insert Halfword from GPR using GPR-specified Left-Index VX-form", "summary": "Inserts the high halfword of a general-purpose register into a vector register at a position specified by another general-purpose register.", "description": "The contents of bits 48:63 of GPR[RB] are placed into byte elements index:index+1 of VSR[VRT+32], where index is the contents of bits 60:63 of GPR[RA].", "syntax": "vinshlx VRT,RA,RB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "RA", "desc": "Source General Purpose Register (index)" }, { "name": "RB", "desc": "Source General Purpose Register (data)" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x1000024F", "length": "32", "binary_pattern": "4 | VRT | RA | RB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nindex ← GPR[RA].bit[60:63]\nsrc.byte[0:15] ← 0\nVSR[VRT+32].byte[index:index+1] ← GPR[RB].bit[48:63]", "special_registers": null, "programming_notes": "The vinshlx instruction is used to insert the upper halfword of a general-purpose register (GPR) into specific byte elements of a vector register. Ensure that the index specified in bits 60-63 of RA is within valid bounds to avoid undefined behavior. This instruction requires the Vector Facility to be enabled; otherwise, it will raise an exception.", "extended_mnemonics": [], "page_found": "Page 341 - 342", "example": "vinshlx v1, r4, r5" }, { "mnemonic": "vinswlx", "architecture": "PowerISA", "full_name": "Vector Insert Word from GPR using GPR-specified Left-Index VX-form", "summary": "Inserts the contents of bits 32:63 of a general-purpose register into byte elements of a vector register based on an index specified in another general-purpose register.", "description": "The instruction inserts the contents of bits 32:63 of GPR[RB] into byte elements index:index+3 of VSR[VRT+32], where index is the value of bits 60:63 of GPR[RA].", "syntax": "vinswlx VRT,RA,RB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "RA", "desc": "Source General Purpose Register containing the index" }, { "name": "RB", "desc": "Source General Purpose Register containing the data to insert" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x1000028F", "length": "32", "binary_pattern": "4 | VRT | RA | RB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nindex ← GPR[RA].bit[60:63]\nVSR[VRT+32].byte[index:index+3] ← GPR[RB].bit[32:63]", "special_registers": null, "programming_notes": "This instruction is used to insert the upper 32 bits of a general-purpose register (GPR) into specific byte elements of a vector register. Ensure that the index specified by the top 4 bits of GPR[RA] is within the valid range for the target vector register. This operation requires the Vector Facility to be enabled; otherwise, it will raise an exception.", "extended_mnemonics": [], "page_found": "Page 342 - 343", "example": "vinswlx v1, r4, r5" }, { "mnemonic": "vinsdlx", "architecture": "PowerISA", "full_name": "Vector Insert Doubleword from GPR using GPR-specified Left-Index VX-form", "summary": "Inserts a doubleword from a general-purpose register into a vector register at a position specified by another general-purpose register.", "description": "The contents of GPR[RB] are placed into byte elements index:index+7 of VSR[VRT+32], where index is the contents of bits 60:63 of GPR[RA]. All other byte elements of VSR[VRT+32] remain unchanged.", "syntax": "vinsdlx VRT,RA,RB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "RA", "desc": "Source General Purpose Register (contains index)" }, { "name": "RB", "desc": "Source General Purpose Register (contains data to insert)" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x100002CF", "length": "32", "binary_pattern": "0 | VRT | RA | RB", "bit_positions": "" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nindex ← GPR[RA].bit[60:63]\nVSR[VRT+32].byte[index:index+7] ← GPR[RB]", "special_registers": "N/A", "programming_notes": "The vinsdlx instruction is used to insert the contents of a general-purpose register (GPR) into a specific byte range within a vector register. Ensure that the index specified in bits 60:63 of the RA register is within the valid range (0-15) to avoid undefined behavior. This instruction requires the Vector Facility to be enabled; otherwise, it will raise an exception.", "extended_mnemonics": [], "page_found": "Page 343 - 344", "example": "vinsdlx v1, r4, r5" }, { "mnemonic": "vinsw", "architecture": "PowerISA", "full_name": "Vector Insert Word from GPR using Immediate-specified Index", "summary": "Inserts the contents of a word from a general-purpose register into a vector register at an immediate-specified index.", "description": "The contents of bits 32:63 of GPR[RB] are placed into byte elements UIM:UIM+3 of VSR[VRT+32]. All other byte elements of VSR[VRT+32] are not modified. If UIM is greater than 12, the result is undefined.", "syntax": "vinsw VRT,RB,UIM", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "RB", "desc": "Source General Purpose Register" }, { "name": "UIM", "desc": "Immediate-specified Index" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x100000CF", "length": "32", "binary_pattern": "4 | VRT | UIM | RB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nVSR[VRT+32].byte[UIM:UIM+3] ← GPR[RB].bit[32:63]", "special_registers": "N/A", "programming_notes": "The vinsw instruction is used to insert the upper 32 bits of a general-purpose register (GPR) into a specific byte range within a vector register. Ensure that the immediate index (UIM) does not exceed 12 to avoid undefined behavior. This instruction operates at user privilege level and will raise an exception if the Vector Facility is unavailable.", "extended_mnemonics": [], "page_found": "Page 344 - 345", "example": "vinsw v1, r5, uim" }, { "mnemonic": "vinsbvlx", "architecture": "PowerISA", "full_name": "Vector Insert Byte from VSR using GPR-specified Left-Index VX-form", "summary": "Inserts a byte from one vector register into another based on an index specified in a general-purpose register.", "description": "The instruction inserts the contents of bits 56:63 of VSR[VRB+32] into byte element 'index' of VSR[VRT+32], where 'index' is the value of bits 60:63 of GPR[RA].", "syntax": "vinsbvlx VRT,RA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "RA", "desc": "Source General Purpose Register containing the index" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x1000000F", "length": "32", "binary_pattern": "000100 | VRT | RA | VRB | 00000 | 001111", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nindex ← GPR[RA].bit[60:63]\nVSR[VRT+32].byte[index] ← VSR[VRB+32].bit[56:63]", "special_registers": "N/A", "programming_notes": "This instruction is used to insert a byte from one vector register into another, with the target index specified by bits 60-63 of a general-purpose register. Ensure that the MSR.VEC bit is set to enable vector operations; otherwise, a Vector_Unavailable exception will be raised. The index must be within the valid range for vector elements to avoid undefined behavior.", "extended_mnemonics": [], "page_found": "Page 345 - 346", "example": "vinsbvlx v1, r4, v3" }, { "mnemonic": "vinshvlx", "architecture": "PowerISA", "full_name": "Vector Insert Halfword from VSR using GPR - specified Left-Index VX-form", "summary": "Inserts halfword from a vector register into another vector register at a position specified by a general-purpose register.", "description": "The instruction inserts the contents of bits 48:63 of VSR[VRB+32] into byte elements index:index+1 of VSR[VRT+32], where index is the contents of bits 60:63 of GPR[RA].", "syntax": "vinshvlx VRT,RA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "VSRT", "desc": "Target Vector Register" }, { "name": "VSRC1", "desc": "Source Vector Register" }, { "name": "VSRC2", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x1000004F", "length": "32", "binary_pattern": "0 | VRT | RA | VRB", "bit_positions": "" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nindex ← GPR[RA].bit[60:63]\nsrc.byte[0:15] ← 0\nVSR[VRT+32].byte[index:index+1] ← VSR[VRB+32].bit[48:63]", "special_registers": "MSR", "programming_notes": "This instruction is used to insert the upper halfword of a vector register into specific byte elements of another vector register, based on an index derived from a general-purpose register. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. The index must be within the valid range for vector operations to avoid undefined behavior.", "extended_mnemonics": [], "page_found": "Page 346 - 347", "example": "vinshvlx v1, r4, v3" }, { "mnemonic": "vinswvlx", "architecture": "PowerISA", "full_name": "Vector Insert Word from VSR using GPR-specified Left-Index VX-form", "summary": "Inserts a word from a vector register into another vector register at a position specified by a general-purpose register.", "description": "The contents of bits 32:63 of VSR[VRB+32] are placed into byte elements index:index+3 of VSR[VRT+32], where index is the contents of bits 60:63 of GPR[RA].", "syntax": "vinswvlx VRT,RA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x1000008F", "length": "32", "binary_pattern": "0 | VRT | RA | VRB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nindex ← GPR[RA].bit[60:63]\nVSR[VRT+32].byte[index:index+3] ← VSR[VRB+32].bit[32:63]", "special_registers": "N/A", "programming_notes": "This instruction is used to insert a 4-byte word from one vector register into another, with the destination index specified by the upper 4 bits of a general-purpose register. Ensure that the MSR.VEC bit is set to enable vector operations; otherwise, a Vector_Unavailable exception will be raised. The source and destination registers must be in the range V32-V63. Be cautious of alignment issues if the index does not align with byte boundaries.", "extended_mnemonics": [], "page_found": "Page 347 - 348", "example": "vinswvlx v1, r4, v3" }, { "mnemonic": "vmuleud", "architecture": "PowerISA", "full_name": "Vector Multiply Even Unsigned Doubleword", "summary": "Multiplies the even doublewords of two vector registers and places the result in another vector register.", "description": "The instruction multiplies the unsigned integer values in the even doublewords of VSR[VRA+32] and VSR[VRB+32], and stores the 128-bit product in VSR[VRT+32].", "syntax": "vmuleud VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x100002C8", "length": "32", "binary_pattern": "4 | VRT | VRA | VRB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nsrc1 ←EXTZ(VSR[VRA+32].dword[0])\nsrc2 ←EXTZ(VSR[VRB+32].dword[0])\nVSR[VRT+32] ←CHOP128(src1 × src2)", "special_registers": "MSR", "programming_notes": "This instruction is used for multiplying unsigned integers in the even doublewords of two vector registers and storing the 128-bit product. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. The operation is performed on the least significant doubleword of each input register, and the result is truncated to 128 bits before being stored.", "extended_mnemonics": [], "page_found": "Page 370 - 371", "example": "vmuleud v1, v2, v3" }, { "mnemonic": "vmulesd", "architecture": "PowerISA", "full_name": "Vector Multiply Even Signed Doubleword", "summary": "Multiplies the even doublewords of two vector registers and places the result in another vector register.", "description": "The instruction multiplies the signed integer values in the even doublewords of VSR[VRA+32] and VSR[VRB+32], and stores the 128-bit product in VSR[VRT+32].", "syntax": "vmulesd VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x100003C8", "length": "32", "binary_pattern": "4 | VRT | VRA | VRB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nsrc1 ←EXTS(VSR[VRA+32].dword[0])\nsrc2 ←EXTS(VSR[VRB+32].dword[0])\nVSR[VRT+32] ←CHOP128(src1 × src2)", "special_registers": "MSR", "programming_notes": "This instruction is used for multiplying signed integers in the even doublewords of two vector registers and storing the 128-bit product. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. The operation is performed on the first doubleword of each input register, and the result is truncated to 128 bits before being stored in the destination register.", "extended_mnemonics": [], "page_found": "Page 371 - 372", "example": "vmulesd v1, v2, v3" }, { "mnemonic": "vmuluwm", "architecture": "PowerISA", "full_name": "Vector Multiply Unsigned Word Modulo", "summary": "Multiplies the contents of two vector registers and places the low-order 32 bits of each product into a target vector register.", "description": "For vmuluwm, each word element in VSR[VRA+32] is multiplied by the corresponding word element in VSR[VRB+32]. The low-order 32 bits of each product are placed into the corresponding word element in VSR[VRT+32].", "syntax": "vmuluwm VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x10000089", "length": "32", "binary_pattern": "4 | VRT | VRA | VRB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n src1 ←EXTZ(VSR[VRA+32].word[i])\n src2 ←EXTZ(VSR[VRB+32].word[i])\n VSR[VRT+32].word[i] ←CHOP32(src1 × src2)\nend", "special_registers": "N/A", "programming_notes": "vmuluwm can be used for unsigned or signed integers.", "extended_mnemonics": [], "page_found": "Page 372 - 373", "example": "vmuluwm v1, v2, v3" }, { "mnemonic": "vmulld", "architecture": "PowerISA", "full_name": "Vector Multiply Low Doubleword", "summary": "Multiplies the contents of two vector registers and places the low-order 64 bits of each product into a target vector register.", "description": "For vmulld, the integer values in doubleword elements of VSR[VRA+32] are multiplied by the corresponding integer values in doubleword elements of VSR[VRB+32]. The low-order 64 bits of each product are placed into doubleword elements of VSR[VRT+32].", "syntax": "vmulld VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x100001C9", "length": "32", "binary_pattern": "0 | VRT | VRA | VRB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 1\n src1 ←EXTS(VSR[VRA+32].dword[i])\n src2 ←EXTS(VSR[VRB+32].dword[i])\n VSR[VRT+32].dword[i] ←CHOP64(src1 × src2)\nend", "special_registers": "MSR", "programming_notes": "This instruction multiplies the integer values in doubleword elements of two vector registers and stores the low-order 64 bits of each product into another vector register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. The operation processes two doublewords per iteration, so be cautious with loop bounds if using this in a larger computation.", "extended_mnemonics": [], "page_found": "Page 375 - 376", "example": "vmulld v1, v2, v3" }, { "mnemonic": "vmhaddshs", "architecture": "PowerISA", "full_name": "Vector Multiply-High-Add Signed Halfword Saturate", "summary": "Performs a vector multiply-high-add signed halfword operation with saturation.", "description": "For each integer value i from 0 to 7, the signed integer value in halfword element i of VSR[VRA+32] is multiplied by the signed integer value in halfword element i of VSR[VRB+32], producing a 32-bit signed integer product. Bits 0:16 of the product are added to the signed integer value in halfword element i of VSR[VRC+32]. The low-order 16 bits of the result are placed into halfword element i of VSR[VRT+32]. If the intermediate result is greater than 2^15-1, the result saturates to 2^15 -1 and SAT is set to 1. If the intermediate result is less than -2^15, the result saturates to -2^15 and SAT is set to 1.", "syntax": "vmhaddshs VRT,VRA,VRB,VRC", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "VRC", "desc": "Source Vector Register" } ], "encoding": { "format": "VA-form", "hex_opcode": "0x10000020", "length": "32", "binary_pattern": "0 | VRT | VRA | VRB | VRC | 32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 7\n src1 ←EXTS(VSR[VRA+32].hword[i])\n src2 ←EXTS(VSR[VRB+32].hword[i])\n src3 ←EXTS(VSR[VRC+32].hword[i])\n result ←((src1 × src2) >> 15) + src3\n VSR[VRT+32].hword[i] ←si16_CLAMP(result)\n VSCR.SAT ←sat_flag", "special_registers": "VSCR.SAT", "programming_notes": "This instruction is commonly used in applications requiring vectorized operations on signed halfwords, such as audio processing or graphics rendering. Ensure that the input vectors are properly aligned to avoid performance penalties. Be aware of saturation conditions; if any result exceeds the 16-bit signed integer range, it will be clamped and the VSCR.SAT flag will be set. This instruction operates at user privilege level.", "extended_mnemonics": [], "page_found": "Page 376 - 377", "example": "vmhaddshs v1, v2, v3, v4" }, { "mnemonic": "vmladduhm", "architecture": "PowerISA", "full_name": "Vector Multiply-Low-Add Unsigned Halfword Modulo", "summary": "Performs a vector multiply-low-add unsigned halfword modulo operation.", "description": "For each integer value i from 0 to 7, the unsigned integer value in halfword element i of VSR[VRA+32] is multiplied by the unsigned integer value in halfword element i in VSR[VRB+32]. The product is added to the unsigned integer value in halfword element i of VSR[VRC+32]. The low-order 16 bits of the sum are placed into halfword element i of VSR[VRT+32].", "syntax": "vmladduhm VRT,VRA,VRB,VRC", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "VRC", "desc": "Source Vector Register" } ], "encoding": { "format": "VA-form", "hex_opcode": "0x10000022", "length": "32", "binary_pattern": "1 | VRT | VRA | VRB | VRC | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0", "bit_positions": "" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then Vector_Unavailable()\ndo i = 0 to 7\n src1 ←EXTZ(VSR[VRA+32].hword[i])\n src2 ←EXTZ(VSR[VRB+32].hword[i])\n src3 ←EXTZ(VSR[VRC+32].hword[i])\n VSR[VRT+32].hword[i] ← CHOP16((src1 × src2) + src3)\nend", "special_registers": null, "programming_notes": "vmladduhm can be used for unsigned or signed integers.", "extended_mnemonics": [], "page_found": "Page 377 - 378", "example": "vmladduhm v1, v2, v3, v4" }, { "mnemonic": "vmsummbm", "architecture": "PowerISA", "full_name": "Vector Multiply-Sum Mixed Byte Modulo", "summary": "Performs a vector multiply-sum operation with mixed byte elements.", "description": "For each integer value i from 0 to 3, do the following. For each integer value j from 0 to 3, do the following. The signed integer value in byte element j of word element i of VSR[VRA+32] is multiplied by the unsigned integer value in byte element j of word element i of VSR[VRB+32]. The sum of the four products is added to the signed integer value in word element i of VSR[VRC+32]. The low-order 32 bits of the result are placed into word element i of VSR[VRT+32].", "syntax": "vmsummbm VRT,VRA,VRB,VRC", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "VRC", "desc": "Source Vector Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0x10000025", "length": "32", "binary_pattern": "18 | VRT | VRA | VRB | VRC", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n temp ←EXTS(VSR[VRC+32].word[i])\n do j = 0 to 3\n src1 ←EXTS(VSR[VRA+32].word[i].byte[j])\n src2 ←EXTZ(VSR[VRB+32].word[i].byte[j])\n temp ←temp + (src1 × src2)\n end\n VSR[VRT+32].word[i] ←CHOP32(temp)\nend", "special_registers": "N/A", "programming_notes": "This instruction is useful for performing vectorized multiply-sum operations on byte elements. Ensure that the vector registers are properly aligned and that the Vector Facility (MSR.VEC) is enabled to avoid exceptions. The result is truncated to 32 bits, so be cautious of overflow if the sum exceeds this range.", "extended_mnemonics": [], "page_found": "Page 378 - 379", "example": "vmsummbm v1, v2, v3, v4" }, { "mnemonic": "vmsumuhs", "architecture": "PowerISA", "full_name": "Vector Multiply-Sum Unsigned Halfword Saturate", "summary": "Performs a vector multiply-sum operation on unsigned halfwords and saturates the result.", "description": "Computes the sum of products of unsigned halfword elements from VRA and VRB, adds the result to the corresponding word element in VRC, and saturates the final result to unsigned 32-bit range. This instruction requires VMX support and no condition flags are affected.", "syntax": "vmsumuhs VRT,VRA,VRB,VRC", "operands": [ { "name": "VRT", "desc": "Destination Vector Register" }, { "name": "VRA", "desc": "Source Vector Register A" }, { "name": "VRB", "desc": "Source Vector Register B" }, { "name": "VRC", "desc": "Source Vector Register C" } ], "encoding": { "format": "VA-form", "hex_opcode": "0x10000027", "length": "32", "binary_pattern": "4 | VRT | VRA | VRB | VRC", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VMX (AltiVec)", "pseudocode": "for i in 0 to 3 do\n product0 ← (u16)VRA[i*32:(i*32+15)] * (u16)VRB[i*32:(i*32+15)]\n product1 ← (u16)VRA[i*32+16:(i*32+31)] * (u16)VRB[i*32+16:(i*32+31)]\n sum ← product0 + product1 + (u32)VRC[i*32:(i*32+31)]\n VRT[i*32:(i*32+31)] ← Saturate_U32(sum)\nend for", "special_registers": "VSCR", "programming_notes": "The vmsumuhs instruction is commonly used for performing vectorized multiply-sum operations on unsigned halfwords, which can be particularly useful in graphics and signal processing applications. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will occur. The operation saturates results to prevent overflow, setting the VSCR.SAT flag if saturation occurs. This instruction operates on 128-bit vectors, so ensure proper alignment of vector registers for optimal performance.", "extended_mnemonics": [], "page_found": "Page 380 - 381", "example": "vmsumuhs v1, v2, v3, v4" }, { "mnemonic": "vmsumudm", "architecture": "PowerISA", "full_name": "Vector Multiply-Sum Unsigned Doubleword Modulo", "summary": "Performs a horizontal add of the doubleword elements in VSR[VRA+32] using vmsumudm.", "description": "The instruction performs a horizontal add of the doubleword elements in VSR[VRA+32]. It can also be used for horizontal subtract, multiply even unsigned doubleword, and multiply odd unsigned doubleword operations by setting specific values in VSR[VRB+32] and VSR[VRC+32].", "syntax": "vmsumudm VRT,VRA,VRB,VRC", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "VRC", "desc": "Source Vector Register" }, { "name": "VA", "desc": "Source Vector Register" }, { "name": "VB", "desc": "Source Vector Register" }, { "name": "VC", "desc": "Source Vector Register" } ], "encoding": { "format": "VA-form", "hex_opcode": "0x10000023", "length": "32", "binary_pattern": "0 | VRT | VRA | VRB | VRC | 35", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ntemp ←EXTZ(VSR[VRC+32])\ndo i = 0 to 1\n src1 ←EXTZ(VSR[VRA+32].dword[i])\n src2 ←EXTZ(VSR[VRB+32].dword[i])\n temp ←temp + (src1 × src2)\nend\nVSR[VRT+32] ←CHOP128(temp)", "special_registers": "MSR", "programming_notes": "A horizontal add of the doubleword elements in VSR[VRA+32] can be performed using vmsumudm when VSR[VRB+32] contains the doubleword integer values {1,1} and VSR[VRC+32] contains the quad-word integer value 0. A horizontal subtract of the doubleword elements in VSR[VRA+32] can be performed using vmsumudm when VSR[VRB+32] contains the doubleword integer values {1,-1} and VSR[VRC+32] contains the quad-word integer value 0. A multiply even unsigned doubleword operation can be performed using vmsumudm when the contents of doubleword element 1 of VSR[VRA+32] or VSR[VRB+32] are 0 and the contents of VSR[VRC+32] to 0. A multiply odd unsigned doubleword operation can be performed using vmsumudm when the contents of doubleword element 0 of VSR[VRA+32] or VSR[VRB+32] are 0 and the contents of VSR[VRC+32] to 0.", "extended_mnemonics": [], "page_found": "Page 381 - 382", "example": "vmsumudm v1, v2, v3, v4" }, { "mnemonic": "vmsumcud", "architecture": "PowerISA", "full_name": "Vector Multiply-Sum & write Carry-out Unsigned Doubleword", "summary": "Performs vector multiply-sum and writes the carry-out of the low-order 128 bits to a destination register.", "description": "The instruction performs two unsigned doubleword multiplications, sums the results along with an additional source register, and writes the carry-out of the low-order 128 bits to the destination register.", "syntax": "vmsumcud VRT,VRA,VRB,VRC", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "VRC", "desc": "Source Vector Register" } ], "encoding": { "format": "VA-form", "hex_opcode": "0x10000017", "length": "32", "binary_pattern": "4 | VRT | VRA | VRB | VRC | 23", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then Vector_Unavailable()\n\ntemp ←EXTZ(VSR[VRC+32])\ndo i = 0 to 1\n src1 ←EXTZ(VSR[VRA+32].dword[i])\n src2 ←EXTZ(VSR[VRB+32].dword[i])\n temp ←temp + (src1 × src2)\nend\n\nVSR[VRT+32] ←CHOP128(temp >> 128)", "special_registers": "N/A", "programming_notes": "This instruction is useful for performing high-precision arithmetic operations involving unsigned doublewords. Ensure that the vector facility is enabled by checking and setting the appropriate bits in the Machine State Register (MSR). Be cautious of overflow conditions, as the carry-out from the low-order 128 bits is written to the destination register. The instruction operates on 64-bit elements, so ensure proper alignment for optimal performance.", "extended_mnemonics": [], "page_found": "Page 382 - 383", "example": "vmsumcud v1, v2, v3, v4" }, { "mnemonic": "vdivsw", "architecture": "PowerISA", "full_name": "Vector Divide Signed Word", "summary": "Divides the contents of two vector registers and updates the result in another vector register.", "description": "For vdivsw, each word element of VSR[VRA+32] is divided by the corresponding word element of VSR[VRB+32]. The quotient is placed into the corresponding word element of VSR[VRT+32].", "syntax": "vdivsw VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x1000018B", "length": "32", "binary_pattern": "4 | VRT | VRA | VRB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n dividend ←EXTS(VSR[VRA+32].word[i])\n divisor ←EXTS(VSR[VRB+32].word[i])\n VSR[VRT+32].word[i] ←CHOP32(dividend ÷ divisor)\nend", "special_registers": null, "programming_notes": "vdivsw performs element-wise signed word division. Ensure that the vector facility is enabled (MSR.VEC=1) to avoid a Vector_Unavailable exception. Handle potential division by zero and overflow conditions in your application logic.", "extended_mnemonics": [], "page_found": "Page 383 - 384", "example": "vdivsw v1, v2, v3" }, { "mnemonic": "vdivesw", "architecture": "PowerISA", "full_name": "Vector Divide Extended Signed Word", "summary": "Divides the contents of two vector registers and updates the result in another vector register.", "description": "For vdivesw, each word element of VSR[VRA+32] is treated as a signed integer, shifted left by 32 bits, and divided by the corresponding word element of VSR[VRB+32], which is also treated as a signed integer. The quotient is placed into the corresponding word element of VSR[VRT+32].", "syntax": "vdivesw VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x1000038B", "length": "32", "binary_pattern": "4 | VRT | VRA | VRB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n dividend ←EXTS(VSR[VRA+32].word[i]) << 32\n divisor ←EXTS(VSR[VRB+32].word[i])\n VSR[VRT+32].word[i] ←CHOP32(dividend ÷ divisor)\nend", "special_registers": null, "programming_notes": "The vdivesw instruction performs a signed division on each word element of the input vectors, shifting the dividend left by 32 bits before dividing. Ensure that the vector facility is enabled (MSR.VEC=1) to avoid exceptions. Be cautious of division by zero, which may result in undefined behavior or exceptions. The operation is performed at the user privilege level unless otherwise specified.", "extended_mnemonics": [], "page_found": "Page 384 - 385", "example": "vdivesw v1, v2, v3" }, { "mnemonic": "vdivsd", "architecture": "PowerISA", "full_name": "Vector Divide Signed Doubleword", "summary": "Divides the contents of two vector registers and updates the result in another vector register.", "description": "For vdivsd, each doubleword element in VSR[VRA+32] is divided by the corresponding doubleword element in VSR[VRB+32]. The quotient is placed into the corresponding doubleword element in VSR[VRT+32].", "syntax": "vdivsd VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x100001CB", "length": "32", "binary_pattern": "0 | VRT | VRA | VRB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 1\n dividend ←EXTS(VSR[VRA+32].dword[i])\n divisor ←EXTS(VSR[VRB+32].dword[i])\n VSR[VRT+32].dword[i] ←CHOP64(dividend ÷ divisor)\nend", "special_registers": null, "programming_notes": "This instruction performs element-wise division of signed doublewords. Ensure that the vector facility is enabled (MSR.VEC=1) to avoid exceptions. Handle potential division by zero and overflow conditions in your application logic.", "extended_mnemonics": [], "page_found": "Page 385 - 386", "example": "vdivsd v1, v2, v3" }, { "mnemonic": "vdivesd", "architecture": "PowerISA", "full_name": "Vector Divide Extended Signed Doubleword", "summary": "Performs extended signed doubleword division on vector elements.", "description": "For vdivesd, each element of the source vectors VRA and VRB is treated as a signed doubleword. The dividend is shifted left by 64 bits, then divided by the divisor. The quotient is placed into the corresponding element of the destination vector VRT.", "syntax": "vdivesd VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Destination Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x100003CB", "length": "32", "binary_pattern": "4 | VRT | VRA | VRB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 1\n dividend ←EXTS(VSR[VRA+32].dword[i]) << 64\n divisor ←EXTS(VSR[VRB+32].dword[i])\n VSR[VRT+32].dword[i] ←CHOP64(dividend ÷ divisor)\nend", "special_registers": "MSR", "programming_notes": "This instruction is used for performing extended signed doubleword division on vector elements. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation involves shifting each dividend left by 64 bits and then dividing it by the corresponding divisor, with the quotient being stored in the destination vector. Be cautious of potential division by zero errors, which may result in undefined behavior or exceptions.", "extended_mnemonics": [], "page_found": "Page 386 - 387", "example": "vdivesd v1, v2, v3" }, { "mnemonic": "vdivsq", "architecture": "PowerISA", "full_name": "Vector Divide Signed Quadword", "summary": "Divides the contents of two vector registers and updates the destination register with the quotient.", "description": "For vdivsq, the signed integer value in VSR[VRA+32] is divided by the signed integer value in VSR[VRB+32], and the result is placed into VSR[VRT+32].", "syntax": "vdivsq VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x1000010B", "length": "32", "binary_pattern": "0 | VRT | VRA | VRB", "bit_positions": "" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\n\ndividend ← EXTS(VSR[VRA+32])\ndivisor ← EXTS(VSR[VRB+32])\nVSR[VRT+32] ← CHOP128(dividend ÷ divisor)\n\nLet src1 be the signed integer value in VSR[VRA+32].\nLet src2 be the signed integer value in VSR[VRB+32].\nThe quotient of src1 divided by src2 is placed into VSR[VRT+32].\nThe quotient is the unique signed integer that satisfies dividend = (quotient × divisor) + r where 0 ≤ remainder < |divisor| if the dividend is nonnegative, and -|divisor| < remainder ≤ 0 if the dividend is negative.\n\nIf an attempt is made to perform any of the divisions ÷ 0 or 0x8000_0000_0000_0000_0000_0000_0000_0000 ÷ -1 then the contents of VSR[VRT+32] are undefined.", "special_registers": null, "programming_notes": "The vdivsq instruction performs a signed division of two 64-bit integers stored in vector registers. Ensure that the divisor is not zero to avoid undefined results. The operation requires the Vector Facility (MSR.VEC) to be enabled; otherwise, a Vector_Unavailable exception will occur. Be cautious with edge cases like dividing the smallest possible negative number by -1, which results in an undefined quotient.", "extended_mnemonics": [], "page_found": "Page 387 - 388", "example": "vdivsq v1, v2, v3" }, { "mnemonic": "vdivesq", "architecture": "PowerISA", "full_name": "Vector Divide Extended Signed Quadword", "summary": "Divides the contents of two vector registers and updates the destination register with the quotient.", "description": "For vdivesq, the signed integer value in VSR[VRA+32] concatenated with 128 0s is divided by the signed integer value in VSR[VRB+32]. The quotient is placed into VSR[VRT+32].", "syntax": "vdivesq VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x1000030B", "length": "32", "binary_pattern": "0 | VRT | VRA | VRB", "bit_positions": "" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\n\ndividend ← EXTS(VSR[VRA+32]) << 128\ndivisor ← EXTS(VSR[VRB+32])\nVSR[VRT+32] ← CHOP128(dividend ÷ divisor)", "special_registers": null, "programming_notes": "This instruction is used for dividing a signed quadword value by another signed quadword value. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The operation involves extending the sign of the operands and handling division with potential overflow or zero divisor scenarios carefully.", "extended_mnemonics": [], "page_found": "Page 388 - 389", "example": "vdivesq v1, v2, v3" }, { "mnemonic": "vmodsw", "architecture": "PowerISA", "full_name": "Vector Modulo Signed Word", "summary": "Performs modulo operation on signed integers in vector registers.", "description": "For vmodsw, the signed integer in word element i of VSR[VRA+32] is divided by the signed integer in word element i of VSR[VRB+32]. The remainder is placed into word element i of VSR[VRT+32].", "syntax": "vmodsw VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x1000078B", "length": "32", "binary_pattern": "4 | VRT | VRA | VRB | 1931", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n dividend ←EXTS(VSR[VRA+32].word[i])\n divisor ←EXTS(VSR[VRB+32].word[i])\n VSR[VRT+32].word[i] ←CHOP32(dividend % divisor)\nend", "special_registers": null, "programming_notes": "The vmodsw instruction performs element-wise signed modulo division on vectors. Ensure that the vector registers are properly aligned and that the Vector Facility is enabled (MSR.VEC=1). Be cautious of division by zero, which may result in undefined behavior or exceptions. This operation is typically used in scenarios requiring periodic or cyclic calculations with signed integers.", "extended_mnemonics": [], "page_found": "Page 389 - 390", "example": "vmodsw v1, v2, v3" }, { "mnemonic": "vmodsd", "architecture": "PowerISA", "full_name": "Vector Modulo Signed Doubleword", "summary": "Performs vector modulo signed doubleword operation.", "description": "For vmodsd, each integer value i from 0 to 1, the signed integer in doubleword element i of VSR[VRA+32] is divided by the signed integer in doubleword element i of VSR[VRB+32]. The remainder is placed into doubleword element i of VSR[VRT+32].", "syntax": "vmodsd VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x100007CB", "length": "32", "binary_pattern": "4 | VRT | VRA | VRB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 1\n dividend ←EXTS(VSR[VRA+32].dword[i])\n divisor ←EXTS(VSR[VRB+32].dword[i])\n VSR[VRT+32].dword[i] ←CHOP64(dividend % divisor)\nend", "special_registers": null, "programming_notes": "The vmodsd instruction performs element-wise signed modulo division on doublewords. Ensure that the vector facility is enabled (MSR.VEC=1) to avoid a Vector_Unavailable exception. Handle potential division by zero, as it will result in an undefined remainder. The operation is performed on elements 0 and 1 of the specified vector registers.", "extended_mnemonics": [], "page_found": "Page 390 - 391", "example": "vmodsd v1, v2, v3" }, { "mnemonic": "vmodsq", "architecture": "PowerISA", "full_name": "Vector Modulo Signed Quadword", "summary": "Performs signed modulo operation on quadword elements of two vector registers and stores the result in another vector register.", "description": "Computes the signed modulo operation on quadword elements: each quadword element of VRA is divided by the corresponding quadword element of VRB and the remainder is stored in VRT. Division by zero results in undefined behavior. No condition flags are affected.", "syntax": "vmodsq VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x1000070B", "length": "32", "binary_pattern": "4 | VRT | VRA | VRB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VMX (AltiVec)", "pseudocode": "for i in 0 to 1 do\n dividend ← (s128)VRA[i*128:(i+1)*128-1]\n divisor ← (s128)VRB[i*128:(i+1)*128-1]\n VRT[i*128:(i+1)*128-1] ← dividend mod divisor\nend for", "special_registers": null, "programming_notes": "The vmodsq instruction performs a signed modulo operation on quadword elements. Ensure that the vector facility is enabled (MSR.VEC=1) to avoid exceptions. Be cautious with division by zero and handle cases where the dividend is 0x8000_0000_0000_0000_0000_0000_0000_0000 and the divisor is -1, as the result is undefined.", "extended_mnemonics": [], "page_found": "Page 391 - 392", "example": "vmodsq v1, v2, v3" }, { "mnemonic": "vmaxsd", "architecture": "PowerISA", "full_name": "Vector Maximum Signed Doubleword", "summary": "Compares the signed doublewords of two vector registers and stores the maximum value in a third vector register.", "description": "For vmaxsd, each pair of corresponding doublewords from VSR[VRA+32] and VSR[VRB+32] are compared. The larger value is stored in the corresponding position in VSR[VRT+32].", "syntax": "vmaxsd VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x100001C2", "length": "32", "binary_pattern": "18 | VRT | VRA | VRB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 1\n src1 ← VSR[VRA+32].dword[i]\n src2 ← VSR[VRB+32].dword[i]\n gt_flag ← EXTS(src1) > EXTS(src2)\n VSR[VRT+32].dword[i] ← gt_flag=1 ? src1 : src2\nend", "special_registers": "N/A", "programming_notes": "The vmaxsd instruction is used to perform element-wise maximum operations on signed doublewords from two vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation compares each pair of corresponding elements and stores the larger value in the destination register. This instruction operates at the user privilege level.", "extended_mnemonics": [], "page_found": "Page 408 - 409", "example": "vmaxsd v1, v2, v3" }, { "mnemonic": "vminsd", "architecture": "PowerISA", "full_name": "Vector Minimum Signed Doubleword", "summary": "Compares the signed doublewords of two vector registers and stores the minimum values in a third vector register.", "description": "For vminsd, each pair of corresponding doublewords from VSR[VRA+32] and VSR[VRB+32] is compared. The smaller value is stored in the corresponding position in VSR[VRT+32].", "syntax": "vminsd VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x100003C2", "length": "32", "binary_pattern": "0 | VRT | VRA | VRB", "bit_positions": "" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 1\n src1 ← VSR[VRA+32].dword[i]\n src2 ← VSR[VRB+32].dword[i]\n lt_flag ← EXTS(src1) < EXTS(src2)\n VSR[VRT+32].dword[i] ← lt_flag=1 ? src1 : src2\nend", "special_registers": null, "programming_notes": "This instruction is used to perform element-wise minimum comparison on signed doublewords from two vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation respects the sign of the operands, so negative numbers are correctly handled. There are no specific alignment requirements for the data in the vector registers.", "extended_mnemonics": [], "page_found": "Page 412 - 413", "example": "vminsd v1, v2, v3" }, { "mnemonic": "vcmpequq", "architecture": "PowerISA", "full_name": "Vector Compare Equal Quadword", "summary": "Compares two quadwords and sets the result to all ones if they are equal, otherwise all zeros.", "description": "Compares each quadword element of VRA with the corresponding quadword element of VRB for equality; the result for each quadword is all ones if equal or all zeros if not equal. If the Rc bit is set, CR6 is updated with summary information. Requires VMX support.", "syntax": "vcmpequq VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VC-form", "hex_opcode": "0x100001C7", "length": "32", "binary_pattern": "0 | VRT | VRA | VRB | Rc", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VMX (AltiVec)", "pseudocode": "for i in 0 to 1 do\n if VRA[i*128:(i+1)*128-1] = VRB[i*128:(i+1)*128-1] then\n VRT[i*128:(i+1)*128-1] ← 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF\n else\n VRT[i*128:(i+1)*128-1] ← 0x00000000000000000000000000000000\n end if\nend for\nif Rc then\n CR6 ← summary of results\nend if", "special_registers": "CR6", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "extended_mnemonics": [], "page_found": "Page 417 - 418", "example": "vcmpequq v1, v2, v3" }, { "mnemonic": "vcmpgtsq", "architecture": "PowerISA", "full_name": "Vector Compare Greater Than Signed Quadword", "summary": "Compares two signed quadwords and sets the result based on whether the first is greater than the second.", "description": "For vcmpgtsq, the contents of VSR[VRA+32] (src1) are compared to the contents of VSR[VRB+32] (src2). If src1 > src2, VSR[VRT+32] is set to all 1s; otherwise, it is set to all 0s. If Rc=1, CR field 6 is updated.", "syntax": "vcmpgtsq VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VC-form", "hex_opcode": "0x10000387", "length": "32", "binary_pattern": "4 | VRT | VRA | VRB | Rc", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nall_true ←1\nall_false ←1\nsrc1 ←EXTS(VSR[VRA+32])\nsrc2 ←EXTS(VSR[VRB+32])\nif src1 > src2 then do\n VSR[VRT+32] ← 0xFFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF\n all_false ←0\nend else do\n VSR[VRT+32] ← 0x0000_0000_0000_0000_0000_0000_0000_0000\n all_true ←0\nend\nif Rc=1 then\n CR.field[6] ←all_true || 0b0 || all_false || 0b0", "special_registers": "CR6 (if Rc=1)", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "extended_mnemonics": [], "page_found": "Page 422 - 423", "example": "vcmpgtsq v1, v2, v3" }, { "mnemonic": "vcmpsq", "architecture": "PowerISA", "full_name": "Vector Compare Signed Quadword", "summary": "Compares the signed integer values in two vector registers and updates the condition register.", "description": "For vcmpsq, the signed integer value in VSR[VRA+32] is compared with the signed integer value in VSR[VRB+32]. The comparison flags are placed into CR field BF.", "syntax": "vcmpsq BF,VRA,VRB", "operands": [ { "name": "BF", "desc": "Condition Register Field" }, { "name": "VRA", "desc": "Vector Register A" }, { "name": "VRB", "desc": "Vector Register B" }, { "name": "VRT", "desc": "Target Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x10000141", "length": "32", "binary_pattern": "18 | BF | VRA | VRB", "bit_positions": "0:5 | 6:8 | 9:10 | 11:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nsrc1 ←EXTS(VSR[VRA+32])\nsrc2 ←EXTS(VSR[VRB+32])\nlt_flag ←src1 < src2\ngt_flag ←src1 > src2\neq_flag ←src1 = src2\nCR.field[BF] ←lt_flag<<3 | gt_flag<<2 | eq_flag<<1", "special_registers": "CR", "programming_notes": "The vcmpsq instruction compares two signed quadword values from vector registers and sets the condition register (CR) field BF based on the comparison results. Ensure that the Vector Facility is enabled by checking and setting MSR.VEC before using this instruction. Be cautious of potential exceptions if the Vector Facility is not available.", "extended_mnemonics": [], "page_found": "Page 426 - 427", "example": "vcmpsq cr0, v2, v3" }, { "mnemonic": "veqv", "architecture": "PowerISA", "full_name": "Vector Logical Equivalence", "summary": "Performs a logical equivalence operation on the contents of two vector registers and stores the result in another vector register.", "description": "The contents of VSR[VRA+32] are XORed with the contents of VSR[VRB+32] and the complemented result is placed into VSR[VRT+32].", "syntax": "veqv VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x10000684", "length": "32", "binary_pattern": "0 | VRT | VRA | VRB | 1412", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nelse\n VSR[VRT+32] ← ¬(VSR[VRA+32] ≡ VSR[VRB+32])", "special_registers": null, "programming_notes": "The veqv instruction performs a logical equivalence operation between two vector registers, followed by a bitwise NOT on the result. This is useful for comparing vectors and determining where they differ. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised.", "extended_mnemonics": [], "page_found": "Page 428 - 429", "example": "veqv v1, v2, v3" }, { "mnemonic": "vrlwnm", "architecture": "PowerISA", "full_name": "Vector Rotate Left Word then AND with Mask", "summary": "Rotates each word element of the source vector left by a specified number of bits and then performs a bitwise AND operation with a mask.", "description": "For vrlwnm, each word element of VSR[VRA+32] is rotated left by the number of bits specified in the corresponding word element of VSR[VRB+32]. The result is then ANDed with a mask generated from bits 11:15 and 19:23 of the same source vector element. The final result is stored in VSR[VRT+32].", "syntax": "vrlwnm VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x10000185", "length": "32", "binary_pattern": "4 | VRT | VRA | VRB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then Vector_Unavailable()\ndo i = 0 to 3\n src1.word[0] ← VSR[VRA+32].word[i]\n src1.word[1] ← VSR[VRA+32].word[i]\n src2 ← VSR[VRB+32].word[i]\n b ← src2.bit[11:15]\n e ← src2.bit[19:23]\n n ← src2.bit[27:31]\n r ← src1.bit[n:n+31]\n m ← MASK(b, e)\n VSR[VRT+32].word[i] ← r & m", "special_registers": null, "programming_notes": "The vrlwnm instruction is useful for performing bitwise operations on vector elements. Ensure that the mask bits (11:15 and 19:23) are set correctly to achieve the desired AND operation. This instruction operates at the user privilege level and does not generate exceptions under normal conditions, but it requires the vector facility to be enabled in the MSR register.", "extended_mnemonics": [], "page_found": "Page 433 - 434", "example": "vrlwnm v1, v2, v3" }, { "mnemonic": "vrlqnm", "architecture": "PowerISA", "full_name": "Vector Rotate Left Quadword then AND with Mask VX-form", "summary": "Rotates the contents of a vector register left by a specified number of bits and performs a bitwise AND operation with a mask derived from another vector register.", "description": "Rotates the quadword element in VRA left by a number of bits specified in VRB, then performs a bitwise AND with a mask derived from the lower bits of VRB to produce the result in VRT. No condition flags are affected.", "syntax": "vrlqnm VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x10000145", "length": "32", "binary_pattern": "4 | VRT | VRA | VRB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VMX (AltiVec)", "pseudocode": "shamt ← (VRB[120:127]) & 0x7F\nmask_bits ← (VRB[120:127]) & 0x3F\nrotated ← (VRA << shamt) | (VRA >> (128 - shamt))\nmask ← Generate_Mask(mask_bits)\nVRT ← rotated & mask", "special_registers": "MSR", "programming_notes": "The vrlqnm instruction is used for vectorized operations involving rotation and masking of quadword data. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to 1, otherwise a Vector_Unavailable exception will be raised. The mask generation from bits 41:47 and 49:55 of VSR[VRB+32] should be carefully managed to achieve the desired bitwise AND operation result.", "extended_mnemonics": [], "page_found": "Page 434 - 435", "example": "vrlqnm v1, v2, v3" }, { "mnemonic": "vrlwmi", "architecture": "PowerISA", "full_name": "Vector Rotate Left Word then Mask Insert VX-form", "summary": "Rotates the contents of each word element in a vector left by a specified number of bits and inserts the result into another vector under control of a mask.", "description": "Rotates each word element of VRA left by the number of bits specified in VRB, then inserts the rotated result into VRT under control of a mask generated from VRB. No condition flags are affected.", "syntax": "vrlwmi VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x10000085", "length": "32", "binary_pattern": "4 | VRT | VRA | VRB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VMX (AltiVec)", "pseudocode": "for i in 0 to 3 do\n shamt ← (VRB[i*32+27:i*32+31]) & 0x1F\n word ← (u32)VRA[i*32:(i*32+31)]\n rotated ← (word << shamt) | (word >> (32 - shamt))\n mask ← Generate_Mask_From_VRB(i)\n VRT[i*32:(i*32+31)] ← (VRT[i*32:(i*32+31)] & ~mask) | (rotated & mask)\nend for", "special_registers": "N/A", "programming_notes": "The vrlwmi instruction is useful for performing masked insertions after rotating word elements. Ensure that the mask bits (11:15 and 19:23) are set correctly to achieve the desired insertion pattern. This instruction operates on vector registers, so ensure that the Vector Facility is enabled in the Machine State Register (MSR).", "extended_mnemonics": [], "page_found": "Page 435 - 436", "example": "vrlwmi v1, v2, v3" }, { "mnemonic": "vrldmi", "architecture": "PowerISA", "full_name": "Vector Rotate Left Doubleword then Mask Insert", "summary": "Rotates the contents of a vector register left by a specified number of bits and inserts the result into another vector register under control of a mask.", "description": "Rotates each doubleword element of VRA left by the number of bits specified in VRB, then inserts the rotated result into VRT under control of a mask derived from corresponding bits in VRB. No condition flags are affected.", "syntax": "vrldmi VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "VX", "desc": "Target Vector Register" }, { "name": "VY", "desc": "Source Vector Register" }, { "name": "VB", "desc": "Mask Vector Register" }, { "name": "SH", "desc": "Shift Amount" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x100000C5", "length": "32", "binary_pattern": "00011 | SH[5:0] | VX[4:0] | VY[4:0] | VB[4:0]", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VMX (AltiVec)", "pseudocode": "for i in 0 to 1 do\n shamt ← (VRB[i*64+58:i*64+63]) & 0x3F\n dword ← (u64)VRA[i*64:(i*64+63)]\n rotated ← (dword << shamt) | (dword >> (64 - shamt))\n mask ← Generate_Mask_From_VRB(i)\n VRT[i*64:(i*64+63)] ← (VRT[i*64:(i*64+63)] & ~mask) | (rotated & mask)\nend for", "special_registers": "MSR", "programming_notes": "The vrldmi instruction is used for rotating doubleword elements and performing masked insertions. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. Be cautious with the alignment of source and target vectors to avoid unexpected results. This operation requires supervisor privilege level.", "extended_mnemonics": [], "page_found": "Page 436 - 437", "example": "vrldmi v1, v2, v3" }, { "mnemonic": "vmaddfp", "architecture": "PowerISA", "full_name": "Vector Multiply-Add Floating-Point", "summary": "Performs a multiply-add operation on vector elements.", "description": "For vmaddfp, the instruction multiplies each element of VSR[VRA+32] by the corresponding element of VSR[VRC+32], adds the result to the corresponding element of VSR[VRB+32], and stores the final result in VSR[VRT+32].", "syntax": "vmaddfp VRT,VRA,VRB,VRC", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "VRC", "desc": "Source Vector Register" } ], "encoding": { "format": "VA-form", "hex_opcode": "0x1000002E", "length": "32", "binary_pattern": "0 | VRT | VRA | VRB | VRC", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n src1 ← VSR[VRA+32].word[i]\n src2 ← VSR[VRB+32].word[i]\n src3 ← VSR[VRC+32].word[i]\n result ← bfp32_MULTIPLY_ADD(src1,src3,src2)\n VSR[VRT+32].word[i] ← result\nend", "special_registers": "MSR", "programming_notes": "To use a multiply-add to perform an IEEE or Java compliant multiply, the addend must be -0.0.", "extended_mnemonics": [], "page_found": "Page 447 - 448", "example": "vmaddfp v1, v2, v3, v4" }, { "mnemonic": "vmaxfp", "architecture": "PowerISA", "full_name": "Vector Maximum Floating-Point", "summary": "Performs element-wise maximum of two vector registers and stores the result in a third vector register.", "description": "For vmaxfp, for each integer value i from 0 to 3, the single-precision floating-point values in word elements i of VSR[VRA+32] and VSR[VRB+32] are compared. The larger of the two values is placed into word element i of VSR[VRT+32].", "syntax": "vmaxfp VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x1000040A", "length": "32", "binary_pattern": "4 | VRT | VRA | VRB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n src1 ← VSR[VRA+32].word[i]\n src2 ← VSR[VRB+32].word[i]\n VSR[VRT+32].word[i] ← bfp32_MAXIMUM(src1,src2)\nend", "special_registers": "N/A", "programming_notes": "The vmaxfp instruction is used to perform element-wise maximum comparison of single-precision floating-point values in vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. This instruction operates on 4 elements per vector register and requires proper alignment of the input vectors for accurate results.", "extended_mnemonics": [], "page_found": "Page 448 - 449", "example": "vmaxfp v1, v2, v3" }, { "mnemonic": "vexptefp", "architecture": "PowerISA", "full_name": "Vector Exponentiate Estimate Floating Point", "summary": "Estimates the result of raising 2 to the power of each element in a vector.", "description": "For vexptefp, the single-precision floating-point estimate of 2 raised to the power of each element in VSR[VRB+32] is placed into corresponding elements in VSR[VRT+32].", "syntax": "vexptefp VRT, VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x1000018A", "length": "32", "binary_pattern": "0 | VRT | VRB | 0", "bit_positions": "0:5 | 6:10 | 11:30 | 31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n src ← VSR[VRB+32].word[i]\n VSR[VRT+32].word[i] ← bfp32_POWER2_ESTIMATE(src)\nend", "special_registers": "MSR", "programming_notes": "The result for various special cases of the source value is given below.\n\nValue Result\n-Infinity +0\n-0 +1\n+0 +1\n+Infinity +Infinity\nNaN QNaN", "extended_mnemonics": [], "page_found": "Page 456 - 457", "example": "vexptefp v1, v3" }, { "mnemonic": "vlogefp", "architecture": "PowerISA", "full_name": "Vector Log Base 2 Estimate Floating-Point", "summary": "Estimates the base 2 logarithm of single-precision floating-point elements in a vector register.", "description": "For vlogefp, the single-precision floating-point estimate of the base 2 logarithm of each element in VSR[VRB+32] is placed into the corresponding element in VSR[VRT+32].", "syntax": "vlogefp VRT,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x100001CA", "length": "32", "binary_pattern": "0 | VRT | VRB | 11000000000000000000000000000000", "bit_positions": "0:5 | 6:10 | 11:30 | 31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n src ← VSR[VRB+32].word[i]\n VSR[VRT+32].word[i] ← bfp32_LOG_BASE2_ESTIMATE(src)\nend", "special_registers": "MSR", "programming_notes": "This instruction is used for estimating the base 2 logarithm of single-precision floating-point numbers in vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation processes four elements at a time, so ensure proper alignment and data handling to avoid unexpected results.", "extended_mnemonics": [], "page_found": "Page 457 - 458", "example": "vlogefp v1, v3" }, { "mnemonic": "vrefp", "architecture": "PowerISA", "full_name": "Vector Reciprocal Estimate Floating-Point VX-form", "summary": "Estimates the reciprocal of single-precision floating-point elements in a vector.", "description": "For vrefp, the single-precision floating-point estimate of the reciprocal of each element in VSR[VRB+32] is placed into corresponding elements in VSR[VRT+32].", "syntax": "vrefp VRT,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x1000010A", "length": "32", "binary_pattern": "4 | VRT | VRB", "bit_positions": "0:5 | 6:10 | 11:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n src ← VSR[VRB+32].word[i]\n VSR[VRT+32].word[i] ← bfp32_RECIPROCAL_ESTIMATE(src)\nend", "special_registers": "MSR", "programming_notes": "The vrefp instruction estimates the reciprocal of each single-precision floating-point element in the source vector and stores it in the destination vector. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on vectors containing 32-bit floating-point numbers, and it does not raise exceptions for invalid operations like division by zero; instead, it returns a NaN or infinity as appropriate.", "extended_mnemonics": [], "page_found": "Page 458 - 459", "example": "vrefp v1, v3" }, { "mnemonic": "vbpermd", "architecture": "PowerISA", "full_name": "Vector Bit Permute Doubleword", "summary": "Performs a bit permute operation on doublewords of two vector registers and stores the result in another vector register.", "description": "Performs a bit permutation on doubleword elements of two vector registers. For each of the two doubleword elements in VRA, the bits are rearranged according to indices specified in the corresponding doubleword of VRB, with the result stored in VRT. No condition registers or status fields are affected.", "syntax": "vbpermd VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Index Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x100005CC", "length": "32", "binary_pattern": "0 | VRT | VRA | VRB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VMX (AltiVec)", "pseudocode": "for i in 0 to 1:\n for j in 0 to 63:\n bit_index ← VRB[i].doubleword[j][0:5]\n VRT[i].doubleword[j] ← VRA[i].doubleword[bit_index]", "special_registers": "MSR", "programming_notes": "The vbpermd instruction is used to perform bit-level permutation on doublewords of two source vectors. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. Each byte in VRB acts as an index to select bits from VRA; if the index exceeds 63, the corresponding bit in the result is set to zero. This operation is useful for tasks requiring precise control over bit manipulation within vector registers.", "extended_mnemonics": [], "page_found": "Page 484 - 485", "example": "vbpermd v1, v2, v3" }, { "mnemonic": "vbpermq", "architecture": "PowerISA", "full_name": "Vector Bit Permute Quadword", "summary": "Performs a bit permutation on two vector registers and stores the result in another vector register.", "description": "Performs a bit permutation on the 128-bit quadword formed by concatenating two vector registers. The bits of the concatenated source are rearranged according to indices in VRB, with the 64-bit result placed in the left doubleword of VRT and the right doubleword cleared. No condition registers or status fields are affected.", "syntax": "vbpermq VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Index Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x1000054C", "length": "32", "binary_pattern": "1001 | VRT | VRA | VRB | 10000000000000000000000000000000", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VMX (AltiVec)", "pseudocode": "source ← VRA || VRB\nresult ← 0\nfor i in 0 to 63:\n bit_index ← VRB.doubleword[i][0:6]\n result[i] ← source[bit_index]\nVRT[0].doubleword ← result\nVRT[1].doubleword ← 0", "special_registers": "MSR", "programming_notes": "The fact that the permuted bit is 0 if the corresponding index value exceeds 127 permits the permuted bits to be selected from a 256-bit quantity, using a single index register.", "extended_mnemonics": [], "page_found": "Page 485 - 486", "example": "vbpermq v1, v2, v3" }, { "mnemonic": "mtvsrbm", "architecture": "PowerISA", "full_name": "Move to VSR Byte Mask", "summary": "Moves a byte mask from a GPR to a VSR.", "description": "The contents of bits 48:63 of GPR[RB] are used to create a field mask in VSR[VRT+32]. Each bit in the GPR determines whether the corresponding byte in the VSR is set to all 0s or all 1s.", "syntax": "mtvsrbm VRT,RB", "operands": [ { "name": "VRT", "desc": "Target Vector-Specific Register" }, { "name": "RB", "desc": "Source General Purpose Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x10100642", "length": "32", "binary_pattern": "4 | VRT | 16 | RB | 17", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 15\n if GPR[RB].bit[48+i]=0 then\n VSR[VRT+32].byte[i] ←0x00\n else\n VSR[VRT+32].byte[i] ←0xFF\nend", "special_registers": "N/A", "programming_notes": "This instruction is used to set each byte in a vector register to either all zeros or all ones based on the bits in a general-purpose register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The instruction processes 16 bytes, so ensure that the GPR contains valid bit values for positions 48 to 63.", "extended_mnemonics": [], "page_found": "Page 486 - 487", "example": "mtvsrbm v1, r5" }, { "mnemonic": "mtvsrwm", "architecture": "PowerISA", "full_name": "Move to VSR Word Mask", "summary": "Moves a word mask from a general-purpose register to a vector scalar register.", "description": "The contents of bits 60-63 of GPR[RB] are used to set the corresponding word elements in VSR[VRT+32] to either all 0s or all 1s based on the bit value.", "syntax": "mtvsrwm VRT,RB", "operands": [ { "name": "VRT", "desc": "Target Vector Scalar Register" }, { "name": "RB", "desc": "Source General Purpose Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x10120642", "length": "32", "binary_pattern": "4 | VRT | 18 | RB | 1602", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ndo i = 0 to 3\n if GPR[RB].bit[60+i]=0 then\n VSR[VRT+32].word[i] ←0x0000_0000\n else\n VSR[VRT+32].word[i] ←0xFFFF_FFFF\nend", "special_registers": "MSR", "programming_notes": "This instruction is used to set each word in a vector register to either all zeros or all ones based on the corresponding bits in a general-purpose register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The instruction operates on 32-bit words and requires the source general-purpose register to be properly aligned for bit manipulation.", "extended_mnemonics": [], "page_found": "Page 487 - 488", "example": "mtvsrwm v1, r5" }, { "mnemonic": "mtvsrqm", "architecture": "PowerISA", "full_name": "Move to VSR Quadword Mask VX-form", "summary": "Moves a quadword mask from a general-purpose register to a vector scalar register.", "description": "The contents of GPR[RB] are used to determine the mask for VSR[VRT+32]. If bit 63 of GPR[RB] is 0, VSR[VRT+32] is set to all zeros. If bit 63 is 1, VSR[VRT+32] is set to all ones.", "syntax": "mtvsrqm VRT,RB", "operands": [ { "name": "VRT", "desc": "Target Vector Scalar Register" }, { "name": "RB", "desc": "Source General Purpose Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x10140642", "length": "32", "binary_pattern": "18 | VRT | RB | 1602", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nelse if GPR[RB].bit[63]=0 then\n VSR[VRT+32] ← 0x0000_0000_0000_0000_0000_0000_0000_0000\nelse\n VSR[VRT+32] ← 0xFFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF\nend", "special_registers": "MSR, VSR[VRT+32]", "programming_notes": "This instruction sets the mask for a vector register based on the most significant bit of a general-purpose register. Ensure that the Vector Facility is enabled in the Machine State Register (MSR) before using this instruction; otherwise, it will raise an exception. The instruction does not require any specific alignment or ordering of operations.", "extended_mnemonics": [], "page_found": "Page 488 - 489", "example": "mtvsrqm v1, r5" }, { "mnemonic": "vcntmbb", "architecture": "PowerISA", "full_name": "Vector Count Mask Bits Byte", "summary": "Counts the number of true (or false) mask bits in a VSR and places the count in the leftmost byte of a GPR.", "description": "Counts the number of byte elements in VRB that have bit 0 set to the value specified by MP (0 or 1), and places the count in the leftmost byte of the target GPR RT. This instruction is part of the VMX category and does not affect condition registers or status fields.", "syntax": "vcntmbb RT,VRB,MP", "operands": [ { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "MP", "desc": "Mask Bit (0 or 1)" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x10180642", "length": "32", "binary_pattern": "0 | RT | MP | VRB | 1602", "bit_positions": "0:5 | 6:10 | 11:14 | 15 | 16:31" }, "extension": "VMX (AltiVec)", "pseudocode": "count ← 0\nfor i in 0 to 15:\n if (VRB.byte[i][0] == MP) then\n count ← count + 1\nRT[56:63] ← count\nRT[0:55] ← 0", "special_registers": null, "programming_notes": "This instruction is useful for counting the number of bytes in a vector register where the least significant bit matches a specified mask value (MP). Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the Machine State Register (MSR) before using this instruction. The result is left-shifted 56 bits, so only the lower byte of GPR[RT] contains the count. This instruction operates at the problem state privilege level.", "extended_mnemonics": [], "page_found": "Page 492 - 493", "example": "vcntmbb r3, v3, 0" }, { "mnemonic": "vcntmbw", "architecture": "PowerISA", "full_name": "Vector Count Mask Bits Word", "summary": "Counts the number of word elements in a vector register that have bit 0 set to a specified value.", "description": "Counts the number of word elements in VRB that have bit 0 set to the value specified by MP (0 or 1), and places the count in the leftmost byte of the target GPR RT. This instruction is part of the VMX category and does not affect condition registers or status fields.", "syntax": "vcntmbw RT,VRB,MP", "operands": [ { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "MP", "desc": "Mask Bit Value" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x101C0642", "length": "32", "binary_pattern": "4 | RT | 14 | MP | VRB", "bit_positions": "0:5 | 6:10 | 11:14 | 15 | 16:31" }, "extension": "VMX (AltiVec)", "pseudocode": "count ← 0\nfor i in 0 to 3:\n if (VRB.word[i][0] == MP) then\n count ← count + 1\nRT[56:63] ← count\nRT[0:55] ← 0", "special_registers": null, "programming_notes": "The vcntmbw instruction is useful for counting the number of word elements in a vector register that have their least significant bit set to a specified value. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The result is stored in the upper bits of the target GPR, so be cautious when interpreting the output.", "extended_mnemonics": [], "page_found": "Page 493 - 494", "example": "vcntmbw r3, v3, 0" }, { "mnemonic": "vstrihr", "architecture": "PowerISA", "full_name": "Vector String Isolate Halfword Right-justified", "summary": "Isolates the rightmost non-zero halfword in a vector string.", "description": "From right to left, the contents of each halfword element of VSR[VRB+32] are placed into the corresponding halfword element in VSR[VRT+32]. If a halfword element in VSR[VRB+32] is found to contain 0, the corresponding halfword element and all halfword elements to the left of that halfword element in VSR[VRT+32] are set to 0.", "syntax": "vstrihr VRT,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VC-form", "hex_opcode": "0x1003000D", "length": "32", "binary_pattern": "0 | VRT | VRB | Rc | 13", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nnull_found ← 0\nwhile (!null_found) do i = 0 to 7\n null_found ← (VSR[VRB+32].hword[7-i] = 0)\n VSR[VRT+32].hword[7-i] ← VSR[VRB+32].hword[7-i]\nend\ndo j = i to 7\n VSR[VRT+32].hword[7-j] ← 0\nend\nif Rc=1 then\n CR.field[6] ← 0b00 || null_found || 0b0", "special_registers": "CR6 (if Rc=1)", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "extended_mnemonics": [], "page_found": "Page 498 - 499", "example": "vstrihr v1, v3" }, { "mnemonic": "bcdadd.", "architecture": "PowerISA", "full_name": "Binary Coded Decimal Add Record", "summary": "Adds two packed decimal integers and updates the condition register.", "description": "The bcdadd. instruction adds two binary coded decimal numbers stored in vector registers VRA and VRB, and stores the result in vector register VRT. The PS field specifies whether to set the sign code to 0b1100 or 0b1111 if the unbounded result is zero.", "syntax": "bcdadd. VRT,RA,RB", "operands": [ { "name": "VRT", "desc": "Target Vector Storage Register" }, { "name": "RA", "desc": "Source General Purpose Register containing the first packed decimal integer" }, { "name": "RB", "desc": "Source General Purpose Register containing the second packed decimal integer" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "PS", "desc": "Programmable Sign Code" }, { "name": "vTmp", "desc": "Target Vector-Scalar Register" }, { "name": "vA", "desc": "Source Vector-Scalar Register" }, { "name": "vB", "desc": "Source Vector-Scalar Register" }, { "name": "RT", "desc": "Target General Purpose Register" } ], "encoding": { "format": "XO-form", "hex_opcode": "0x10000401", "length": "32", "binary_pattern": "0 | VRT | VRA | VRB | PS", "bit_positions": "" }, "extension": "Decimal Floating-Point", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nVRT[32] ← bcd_ADD(VRA[32], VRB[32], PS)\nCR.bit[56] ← inv_flag ? 0b0 : lt_flag\nCR.bit[57] ← inv_flag ? 0b0 : gt_flag\nCR.bit[58] ← inv_flag ? 0b0 : eq_flag\nCR.bit[59] ← ox_flag | inv_flag", "special_registers": "CR0, XER, FPSCR", "programming_notes": "When bit 3 of CR field 6 is set to 1 by bcdadd. or bcdsub., either an overflow occurred or one or both operands are not valid encodings of decimal values.", "extended_mnemonics": [], "page_found": "Page 500 - 501", "example": "bcdadd. v1, r4, r5" }, { "mnemonic": "vmul10uq", "architecture": "PowerISA", "full_name": "Vector Multiply-by-10 Unsigned Quadword", "summary": "Multiplies the contents of a vector register by 10 and places the result in another vector register.", "description": "The rightmost 128 bits of the product of src multiplied by the value 10 are placed into VSR[VRT+32]. Let src be the unsigned integer value in VSR[VRA+32].", "syntax": "vmul10uq VRT,VRA", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x10000201", "length": "32", "binary_pattern": "0 | VRT | VRA | 0", "bit_positions": "0:5 | 6:10 | 11:30 | 31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nsrc ←EXTZ(VSR[VRA+32])\nprod ←(src << 3) + (src << 1)\nVSR[VRT+32] ←CHOP128(prod)", "special_registers": "MSR", "programming_notes": "This instruction multiplies the upper 64 bits of a vector register by 10 and stores the result in another vector register. Ensure that the Vector Facility is enabled (MSR.VEC=1); otherwise, a Vector_Unavailable exception will be raised. The operation involves shifting and adding to achieve multiplication by 10, so be cautious with overflow if the input value is close to the maximum unsigned 64-bit integer.", "extended_mnemonics": [], "page_found": "Page 509 - 510", "example": "vmul10uq v1, v2" }, { "mnemonic": "vmul10euq", "architecture": "PowerISA", "full_name": "Vector Multiply-by-10 Extended Unsigned Quadword", "summary": "Multiplies the contents of two vector registers by 10 and extends the result.", "description": "The instruction multiplies the unsigned integer value in VSR[VRA+32] by 10, adds the unsigned packed decimal value from bits 124:127 of VSR[VRB+32], and places the rightmost 128 bits of the result into VSR[VRT+32].", "syntax": "vmul10euq VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x10000241", "length": "32", "binary_pattern": "4 | VRT | VRA | VRB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nsrc ← EXTZ(VSR[VRA+32])\ncin ← EXTZ(VSR[VRB+32].bit[124:127])\nprod ← (src << 3) + (src << 1) + cin\nVSR[VRT+32] ← CHOP128(prod)", "special_registers": "MSR", "programming_notes": "This instruction is used for multiplying an unsigned integer by 10 and adding a packed decimal value. Ensure that the Vector Facility is enabled in the MSR register to avoid exceptions. The operation requires proper alignment of input values, specifically focusing on bits 124:127 of the second source vector. Be cautious with overflow conditions as the result is truncated to 128 bits.", "extended_mnemonics": [], "page_found": "Page 510 - 511", "example": "vmul10euq v1, v2, v3" }, { "mnemonic": "bcdcpsgn.", "architecture": "PowerISA", "full_name": "Decimal Copy Sign VX-form", "summary": "Copies the sign of a decimal value from one register to another while preserving the magnitude.", "description": "The bcdcpsgn. instruction copies the sign of the decimal value in VSR[VRB+32] to the decimal value in VSR[VRA+32], placing the result into VSR[VRT+32]. If either input is an invalid encoding, the result is undefined.", "syntax": "bcdcpsgn. VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x10000341", "length": "32", "binary_pattern": "4 | VRT | VRA | VRB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "Decimal Floating-Point", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ninv_flag ←(VSR[VRA+32].nibble[31] < 0xA) |\n (VSR[VRB+32].nibble[31] < 0xA)\ndo i = 0 to 30\n inv_flag ←inv_flag |\n (VSR[VRA+32].nibble[i] > 0x9) |\n (VSR[VRB+32].nibble[i] > 0x9)\nend\nsrc_sign ←(VSR[VRB+32].nibble[31] = 0xB) |\n (VSR[VRB+32].nibble[31] = 0xD)\neq_flag ←(VSR[VRA+32].nibble[0:30] = 0)\nlt_flag ←(eq_flag=0) & (src_sign=1)\ngt_flag ←(eq_flag=0) & (src_sign=0)\nresult.nibble[0:30] ←VSR[VRA+32].nibble[0:30]\nresult.nibble[31] ←VSR[VRB+32].nibble[31]\nVSR[VRT+32] ←inv_flag ? undefined : result\nCR.bit[56] ←inv_flag ? 0b0 : lt_flag\nCR.bit[57] ←inv_flag ? 0b0 : gt_flag\nCR.bit[58] ←inv_flag ? 0b0 : eq_flag\nCR.bit[59] ←inv_flag", "special_registers": "CR6, FPSCR", "programming_notes": "The bcdcpsgn. instruction is used to copy the sign of a decimal value from one vector register to another, while preserving the magnitude. Ensure that both input vectors are valid decimal encodings; otherwise, the result is undefined. This instruction operates at the user privilege level and does not raise exceptions for invalid inputs, instead setting CR6 bits accordingly.", "extended_mnemonics": [], "page_found": "Page 511 - 512", "example": "bcdcpsgn. v1, v2, v3" }, { "mnemonic": "bcdsetsgn.", "architecture": "PowerISA", "full_name": "Set Sign for Packed Decimal", "summary": "Sets the sign of a packed decimal value in a vector register based on the specified conditions.", "description": "The bcdsetsgn. instruction sets the sign of a packed decimal value in VSR[VRT+32] based on the contents of VSR[VRB+32] and the PS flag.", "syntax": "bcdsetsgn. VRT,VRB,PS", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "PS", "desc": "Packed Sign Flag" }, { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "RB", "desc": "Source General Purpose Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x101F0581", "length": "32", "binary_pattern": "4 | VRT | VRB | PS", "bit_positions": "0:5 | 6:10 | 11:20 | 21:31" }, "extension": "Decimal Floating-Point", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\n\ninv_flag ←(VSR[VRB+32].nibble[31] < 0xA)\ndo i = 0 to 30\n inv_flag ←inv_flag |\n (VSR[VRB+32].nibble[i] > 0x9)\nend\n\nsrc_sign ←(VSR[VRB+32].nibble[31] = 0xB) |\n (VSR[VRB+32].nibble[31] = 0xD)\n\neq_flag ←(VSR[VRB+32].nibble[0:30] = 0)\nlt_flag ←(eq_flag=0) & (src_sign=1)\ngt_flag ←(eq_flag=0) & (src_sign=0)\n\nresult.nibble[0:30] ←VSR[VRB+32].nibble[0:30]\nresult.nibble[31] ←\n (src_sign=0) ? ((PS=0) ? 0xC:0xF) : 0xD\n\nVSR[VRT+32] ←inv_flag ? undefined : result\n\nCR.bit[56] ←inv_flag ? 0b0 : lt_flag\nCR.bit[57] ←inv_flag ? 0b0 : gt_flag\nCR.bit[58] ←inv_flag ? 0b0 : eq_flag\nCR.bit[59] ←inv_flag", "special_registers": "CR6, FPSCR", "programming_notes": "The bcdsetsgn. instruction is used to set the sign of a packed decimal value in VSR[VRT+32] based on the contents of VSR[VRB+32]. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. The instruction checks for invalid characters in the input and sets the sign accordingly, updating condition register bits CR[56-59] to reflect the result's status.", "extended_mnemonics": [], "page_found": "Page 512 - 513", "example": "bcdsetsgn. v1, v3, 0" }, { "mnemonic": "bcds.", "architecture": "PowerISA", "full_name": "Decimal Shift VX-form", "summary": "Shifts a signed packed decimal value by a specified number of digits and rounds the result.", "description": "The bcds. instruction shifts a signed packed decimal value in VSR[VRB+32] by a number of digits specified in byte element 7 of VSR[VRA+32]. The result is placed into VSR[VRT+32].", "syntax": "bcds. VRT,VRA,VRB,PS", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register containing the shift count" }, { "name": "VRB", "desc": "Source Vector Register containing the packed decimal value to be shifted" }, { "name": "PS", "desc": "Packed Decimal Sign Control" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x100004C1", "length": "32", "binary_pattern": "4 | VRT | VRA | VRB | PS | 0 | 0 | 0", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21 | 22 | 23:30 | 31" }, "extension": "Decimal Floating-Point", "pseudocode": "if MSR.VEC=0 then Vector_Unavailable()\nn ← EXTS(VSR[VRA+32].byte[7])\ninv_flag ← (VSR[VRB+32].nibble[31] < 0xA)\ndo i = 0 to 30\n inv_flag ← inv_flag | (VSR[VRB+32].nibble[i] > 0x9)\nend\nsrc_sign ← (VSR[VRB+32].nibble[31] = 0xB) | (VSR[VRB+32].nibble[31] = 0xD)\neq_flag ← (VSR[VRB+32].nibble[0:30] = 0)\nlt_flag ← (eq_flag=0) & (src_sign=1)\ngt_flag ← (eq_flag=0) & (src_sign=0)\nif n > 0 then do // shift left\n shcnt ← (n<32) ? n : 31\n src.nibble[0:30] ← VSR[VRB+32].nibble[0:30]\n src.nibble[31:61] ← 0\n ox_flag ← (shcnt > 0) & (src.nibble[0:shcnt-1] != 0)\nend else do // shift right\n shcnt ← ((¬n+1)<32) ? (¬n+1) : 31\n src.nibble[0:30] ← 0\n src.nibble[31:61] ← VSR[VRB+32].nibble[0:30]\n result.nibble[0:30] ← src.nibble[31-shcnt:61-shcnt]\n ox_flag ← 0b0\nend\nresult.nibble[31] ← (src_sign=0) ? ((PS=0) ? 0xC : 0xF) : 0xD\nVSR[VRT+32] ← inv_flag ? undefined : result\nCR.bit[56] ← inv_flag ? 0b0 : lt_flag\nCR.bit[57] ← inv_flag ? 0b0 : gt_flag\nCR.bit[58] ← inv_flag ? 0b0 : eq_flag\nCR.bit[59] ← inv_flag | ox_flag", "special_registers": "CR6, VSR, FPSCR", "programming_notes": "The bcds. instruction is used for shifting signed packed decimal values in vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will occur. The shift amount is determined by byte element 7 of the source register, and the result is stored in the target register. Be cautious with negative shifts as they are treated as right shifts. The instruction updates condition registers for comparison purposes.", "extended_mnemonics": [], "page_found": "Page 513 - 514", "example": "bcds. v1, v2, v3, 0" }, { "mnemonic": "bcdus.", "architecture": "PowerISA", "full_name": "Binary Coded Decimal Unsigned Shift", "summary": "Performs an unsigned shift on packed decimal values in vector registers.", "description": "The bcdus. instruction shifts the contents of VSR[VRB+32] by a number of digits specified by the signed integer value in byte element 7 of VSR[VRA+32]. The result is placed into VSR[VRT+32].", "syntax": "bcdus. VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register containing the shift count" }, { "name": "VRB", "desc": "Source Vector Register containing the packed decimal value to be shifted" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x10000481", "length": "32", "binary_pattern": "0 | 6 | 11 | 16 | 21 | 22 | 23 | 31", "bit_positions": "0 | 6 | 11 | 16 | 21 | 22 | 23 | 31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\n\ninv_flag ←0\ndo i = 0 to 31\n inv_flag ←inv_flag | (VSR[VRB+32].nibble[i] > 0x9)\nend\neq_flag ←(VSR[VRB+32].nibble[0:31] = 0)\ngt_flag ←(eq_flag=0)\n\nif n > 0 then do // shift left\n shcnt ←(n<33) ? n : 32\n src.nibble[0:31] ←VSR[VRB+32]\n src.nibble[32:63] ←0\n ox_flag ←(shcnt > 0) & (src.nibble[0:shcnt-1] != 0)\nend else do // shift right\n shcnt ←((¬n+1)<33) ? (¬n+1) : 32\n src.nibble[0:31] ←0\n src.nibble[32:63] ←VSR[VRB+32]\n result ←src.nibble[32-shcnt:63-shcnt]\n ox_flag ←0\nend\n\nVSR[VRT+32] ←inv_flag ? undefined : result\n\nCR.bit[56] ←0b0\nCR.bit[57] ←inv_flag ? 0b0 : gt_flag\nCR.bit[58] ←inv_flag ? 0b0 : eq_flag\nCR.bit[59] ←inv_flag | ox_flag", "special_registers": "CR, XER", "programming_notes": "The bcdus. instruction is used for shifting Binary Coded Decimal (BCD) values within vector registers. Ensure that the shift count in byte element 7 of VSR[VRA+32] is valid; otherwise, the result is undefined. This instruction operates at the user privilege level and may raise an exception if vector processing is unavailable. Be cautious with alignment as it affects the interpretation of BCD digits.", "extended_mnemonics": [], "page_found": "Page 514 - 515", "example": "bcdus. v1, v2, v3" }, { "mnemonic": "bcdsr.", "architecture": "PowerISA", "full_name": "Binary Coded Decimal Shift and Round", "summary": "Shifts a binary coded decimal value by a specified number of digits and rounds the result.", "description": "The bcdsr. instruction shifts a signed packed decimal value in VSR[VRB+32] by a number of digits specified by the signed integer value in byte element 7 of VSR[VRA+32]. The result is rounded and placed into VSR[VRT+32].", "syntax": "bcdsr. VRT,VRA,VRB,PS", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register containing the shift count" }, { "name": "VRB", "desc": "Source Vector Register containing the packed decimal value to be shifted and rounded" }, { "name": "PS", "desc": "Packed Sign field" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x100005C1", "length": "32", "binary_pattern": "000100 | VRT | VRA | VRB | 1.111 | 000001", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ninv_flag ←(VSR[VRB+32].nibble[31] < 0xA)\ndo i = 0 to 30\n inv_flag ←inv_flag | (VSR[VRB+32].nibble[i] > 0x9)\nend\nsrc_sign ←(VSR[VRB+32].nibble[31] = 0xB) | (VSR[VRB+32].nibble[31] = 0xD)\neq_flag ←(VSR[VRB+32].nibble[0:30] = 0)\ngt_flag ←(eq_flag=0) & (src_sign=0)\nlt_flag ←(eq_flag=0) & (src_sign=1)\nn ←EXTS(VSR[VRA+32].byte[7])\nif n > 0 then do // shift left\n shcnt ←Clamp(n, 0, 31)\n src.nibble[0:30] ←VSR[VRB+32].nibble[0:30]\n src.nibble[31:61] ←0\n result.nibble[0:30] ←src.nibble[shcnt:shcnt+30]\n ox_flag ←(shcnt > 0) & (src.nibble[0:shcnt-1] != 0)\n g_flag ←0\nend else do // shift right\n shcnt ←Clamp(¬n + 1, 0, 31)\n src.nibble[31:61] ←VSR[VRB+32].nibble[0:30]\n ox_flag ←0\ng_flag ←(shcnt > 0) & (EXTZ(src.nibble[62-shcnt]) >= 5)\nend\nresult.nibble[31] ← (src_sign=0) ? ((PS=0) ? 0xC : 0xF) : 0xD\nresult ←(g_flag=0) ? result : bcd_INCREMENT(result)\nVSR[VRT+32] ←inv_flag ? undefined : result\nCR.bit[56] ←inv_flag ? 0b0 : lt_flag\nCR.bit[57] ←inv_flag ? 0b0 : gt_flag\nCR.bit[58] ←inv_flag ? 0b0 : eq_flag\nCR.bit[59] ←inv_flag | ox_flag", "special_registers": "CR6, VSR", "programming_notes": "The bcdsr. instruction is used for shifting and rounding packed decimal values in vector registers. Ensure the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will occur. The instruction handles both left and right shifts based on the sign of the shift count in byte element 7 of the source register. Be cautious with invalid input detection, as any nibble outside the range 0x0 to 0x9 or special nibbles (0xB, 0xD) will set the CR6[3] bit and result in undefined output.", "extended_mnemonics": [], "page_found": "Page 515 - 516", "example": "bcdsr. v1, v2, v3, 0" }, { "mnemonic": "bcdtrunc.", "architecture": "PowerISA", "full_name": "Decimal Truncate VX-form", "summary": "Truncates a decimal value to a specified length and updates the condition register.", "description": "The bcdtrunc. instruction truncates a packed decimal value in VSR[VRB+32] to a specified length and stores the result in VSR[VRT+32]. The length is determined by bits 48:63 of VSR[VRA+32].", "syntax": "bcdtrunc. VRT,VRA,VRB,PS", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register containing the length" }, { "name": "VRB", "desc": "Source Vector Register containing the packed decimal value" }, { "name": "PS", "desc": "Packed Sign flag" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x10000501", "length": "32", "binary_pattern": "4 | VRT | VRA | VRB | PS | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0", "bit_positions": "" }, "extension": "Decimal Floating-Point", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ninv_flag ←(VSR[VRB+32].nibble[31] < 0xA)\ndo i = 0 to 30\n inv_flag ←inv_flag |\n (VSR[VRB+32].nibble[i] > 0x9)\nend\nlength ←VSR[VRA+32].bit[48:63]\nox_flag ←0\nsrc_sign ←(VSR[VRB+32].nibble[31] = 0xB) |\n (VSR[VRB+32].nibble[31] = 0xD)\neq_flag ←(VSR[VRB+32].nibble[0:30] = 0)\nlt_flag ← src_sign & ¬eq_flag\ngt_flag ←¬src_sign & ¬eq_flag\nif length < 31 then do\ndo i = 0 to 30-length\n if VSR[VRB+32].nibble[i]!=0b0000 then\n ox_flag ←1\n result.nibble[i] ←0b0000\nend\nif length > 0 then do\ndo i = 31-length to 30\n result.nibble[i] ←VSR[VRB+32].nibble[i]\nend\nend\nelse\n result.nibble[0:30] ←VSR[VRB+32].nibble[0:30]\nresult.nibble[31] ←\n (src_sign=0) ? ((PS=0) ? 0xC : 0xF) : 0xD\nVSR[VRT+32] ←inv_flag ? undefined : result\nCR.bit[56] ←inv_flag ? 0b0 : lt_flag\nCR.bit[57] ←inv_flag ? 0b0 : gt_flag\nCR.bit[58] ←inv_flag ? 0b0 : eq_flag\nCR.bit[59] ←inv_flag | ox_flag", "special_registers": "CR6, FPSCR", "programming_notes": "The bcdtrunc. instruction is used to truncate a packed decimal value in VSR[VRB+32] to a specified length, determined by bits 48:63 of VSR[VRA+32]. Ensure that the vector facility (MSR.VEC) is enabled before using this instruction. The instruction checks for invalid nibbles and sets flags accordingly. Be cautious with alignment and ensure proper handling of special cases like overflow and sign preservation.", "extended_mnemonics": [], "page_found": "Page 516 - 517", "example": "bcdtrunc. v1, v2, v3, 0" }, { "mnemonic": "bcdutrunc.", "architecture": "PowerISA", "full_name": "Binary Coded Decimal Unsigned Truncate", "summary": "Truncates the unsigned decimal value in VRB to a specified length and places it into VRT.", "description": "The instruction truncates the unsigned decimal value in VSR[VRB+32] to the length specified by the integer value in bits 48:63 of VSR[VRA+32]. The result is placed into VSR[VRT+32].", "syntax": "bcdutrunc. VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register containing the length" }, { "name": "VRB", "desc": "Source Vector Register containing the unsigned decimal value" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x10000541", "length": "32", "binary_pattern": "4 | VRT | VRA | VRB | 1 | / | 321", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:29 | 30 | 31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\ninv_flag ←0\ndo i = 0 to 31\n inv_flag ←inv_flag |\n (VSR[VRB+32].nibble[i] > 0x9)\nend\nlength ←VSR[VRA+32].bit[48:63]\nox_flag ←0\neq_flag ←(VSR[VRB+32].nibble[0:31] = 0)\ngt_flag ←(VSR[VRB+32].nibble[0:31] != 0)\nif length < 32 then do\n do i = 0 to 31-length\n ox_flag ←1\n result.nibble[i] ←0b0000\n end\n if length > 0 then do\n do i = 32-length to 31\n result.nibble[i] ←VSR[VRB+32].nibble[i]\n end\n end\nend\nelse result ←VSR[VRB+32]\nVSR[VRT+32] ←inv_flag ? undefined : result\nCR.bit[56] ←0b0\nCR.bit[57] ←inv_flag ? 0b0 : gt_flag\nCR.bit[58] ←inv_flag ? 0b0 : eq_flag\nCR.bit[59] ←inv_flag | ox_flag", "special_registers": "CR6, CR", "programming_notes": "The bcdutrunc. instruction is used to truncate an unsigned decimal value stored in a vector register. Ensure that the length specified in VSR[VRA+32] does not exceed 32 nibbles, as truncating beyond this will result in undefined behavior. The instruction sets various condition register bits (CR6) based on the operation's outcome, such as overflow and equality flags. Be cautious of invalid nibble values greater than 0x9, which can lead to incorrect results.", "extended_mnemonics": [], "page_found": "Page 517 - 518", "example": "bcdutrunc. v1, v2, v3" }, { "mnemonic": "mtvscr", "architecture": "PowerISA", "full_name": "Move To Vector Status and Control Register", "summary": "Moves the contents of a vector register word into the VSCR.", "description": "The contents of word element 3 of VSR[VRB+32] are placed into the VSCR.", "syntax": "mtvscr VRB", "operands": [ { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x10000644", "length": "32", "binary_pattern": "16 | VRB | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0", "bit_positions": "" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nVSCR ← VSR[VRB+32].word[3]", "special_registers": "MSR, VSCR", "programming_notes": "The mtvscr instruction is used to transfer a value from a vector register to the VSCR. Ensure that the Vector Facility (MSR.VEC) is enabled before executing this instruction; otherwise, a Vector_Unavailable exception will be raised. This instruction requires proper alignment of the source vector register and operates at user privilege level.", "extended_mnemonics": [], "page_found": "Page 518 - 519", "example": "mtvscr v3" }, { "mnemonic": "lxssp", "architecture": "PowerISA", "full_name": "Load VSX Scalar Single-Precision", "summary": "Accesses a floating-point operand in single-precision format from storage, converts it to double-precision format, and loads it into a VSR.", "description": "When Big-Endian byte ordering is employed, the contents of the word in storage at address EA are placed into load_data in such an order that; the contents of the byte in storage at address EA are placed into byte 0 of load_data, the contents of the byte in storage at address EA+1 are placed into byte 1 of load_data, the contents of the byte in storage at address EA+2 are placed into byte 2 of load_data, and the contents of the byte in storage at address EA+3 are placed into byte 3 of load_data. When Little-Endian byte ordering is employed, the contents of the word in storage at address EA are placed into load_data in such an order that; the contents of the byte in storage at address EA are placed into byte 3 of load_data, the contents of the byte in storage at address EA+1 are placed into byte 2 of load_data, the contents of the byte in storage at address EA+2 are placed into byte 1 of load_data, and the contents of the byte in storage at address EA+3 are placed into byte 0 of load_data. The contents of doubleword element 1 of VSR[VRT+32] are set to 0.", "syntax": "lxssp RT,RA,RB", "operands": [ { "name": "RT", "desc": "Target Vector-Specific Register" }, { "name": "RA", "desc": "Base Address General Purpose Register" }, { "name": "RB", "desc": "Offset General Purpose Register" }, { "name": "VRT", "desc": "Target VSX Register" }, { "name": "disp", "desc": "Displacement" } ], "encoding": { "format": "XX2-form", "hex_opcode": "0xE4000003", "length": "32", "binary_pattern": "0 | VRT | RA | DS | 16 | 18 | 20 | 22 | 24 | 26 | 28 | 30 | 31", "bit_positions": "" }, "extension": "VSX", "pseudocode": "if MSR.VEC=0 then Vector_Unavailable()\nEA ← (RA|0) + EXTS64(DS||0b00)\nload_data ← MEM(EA,4)\nresult ← bfp_CONVERT_FROM_BFP32(MEM(EA,4))\nVSR[VRT+32].dword[0] ← bfp64_CONVERT_FROM_BFP(result)\nVSR[VRT+32].dword[1] ← 0x0000_0000_0000_0000", "special_registers": "N/A", "programming_notes": "The lxssp instruction loads a single-precision floating-point value from memory into the VSX register, ensuring proper byte ordering based on the system's endianness. It is commonly used for loading scalar floating-point data into VSX registers for further processing. Ensure that the address (EA) is properly aligned to avoid potential performance penalties or exceptions. This instruction operates at user privilege level and will raise a Vector_Unavailable exception if the VEC bit in the MSR register is not set.", "extended_mnemonics": [], "page_found": "Page 532 - 533", "example": "lxssp r3, r4, r5" }, { "mnemonic": "xsrdpi", "architecture": "PowerISA", "full_name": "Round to Floating-Point Integer (Double-Precision)", "summary": "Rounds a double-precision floating-point value to an integer using the specified rounding mode.", "description": "The result is placed into doubleword element 0 of VSR[XT] in double-precision format. The contents of doubleword element 1 of VSR[XT] are set to 0.", "syntax": "xsrdpi VRT, VRA", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "XT", "desc": "Target Vector-Scalar Register" }, { "name": "XB", "desc": "Source Vector-Scalar Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0xF0000124", "length": "32", "binary_pattern": "60 | T | B | 11 | 16 | BX | TX", "bit_positions": "0:5 | 6:8 | 9:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nreset_xflags()\nsrc ← bfp_CONVERT_FROM_BFP64(VSR[VRB+32].dword[0])\nrnd ← bfp_ROUND_TO_INTEGER(0b100, src)\nresult ← bfp64_CONVERT_FROM_BFP(rnd)\nif vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\nvex_flag ← FPSCR.VE & vxsnan_flag\nif vex_flag=0 then do\n VSR[32×TX+T].dword[0] ← result\n VSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000\n FPSCR.FPRF ← fprf_CLASS_BFP64(result)\nend\nFPSCR.FR ← 0b0\nFPSCR.FI ← 0b0", "special_registers": "FPSCR (FPRF, FX, VXSNAN, FR, FI)", "programming_notes": "This instruction can be used to operate on a single-precision source operand. Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.", "extended_mnemonics": [], "page_found": "Page 534 - 535", "example": "xsrdpi v1, v2" }, { "mnemonic": "xscvdpsxw", "architecture": "PowerISA", "full_name": "VSX Scalar Convert with round to zero Double-Precision to Signed Word", "summary": "Converts a double-precision floating-point number to a signed word, rounding towards zero.", "description": "This instruction converts the double-precision floating-point number in VSR[XB] to a signed word and places it into word elements 0 and 1 of VSR[XT]. If the operand is positive or +Infinity, 0x7FFF_FFFF is placed. If negative, -Infinity, or NaN, 0x8000_0000 is placed.", "syntax": "xscvdpsxw XT,XB", "operands": [ { "name": "XT", "desc": "Target Vector-Scalar Register" }, { "name": "XB", "desc": "Source Vector-Scalar Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0xF0000160", "length": "32", "binary_pattern": "60 | XT | / | XB | 352", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VSX", "pseudocode": "if (VSR[XB][0] is positive or +Infinity) then\n VSR[XT][0:31] <- 0x7FFF_FFFF\nelse if (VSR[XB][0] is negative, -Infinity, or NaN) then\n VSR[XT][0:31] <- 0x8000_0000\nVSR[XT][32:63] <- 0", "special_registers": "FR, FI, VXSNAN, VXCVI", "programming_notes": "This instruction is useful for converting double-precision floating-point numbers to a signed word format, with specific handling for edge cases like infinity and NaN. Ensure that the input register contains valid double-precision values to avoid unexpected results. The instruction operates at user privilege level and does not generate exceptions under normal conditions.", "extended_mnemonics": [], "page_found": "Page 548 - 549", "example": "xscvdpsxw vs1, vs3" }, { "mnemonic": "xscvsxddp", "architecture": "PowerISA", "full_name": "VSX Scalar Convert with round Signed Doubleword to Double-Precision format", "summary": "Converts a signed doubleword integer from VSX register XB to a double-precision floating-point number in VSX register XT, rounding according to the FPSCR.RN setting.", "description": "The instruction converts the signed integer value in doubleword element 0 of VSR[XB] to an unbounded-precision floating-point value and rounds it to double-precision format using the rounding mode specified by RN. The result is placed into doubleword element 0 of VSR[XT], with doubleword element 1 set to zero.", "syntax": "xscvsxddp XT,RB", "operands": [ { "name": "XT", "desc": "Target Vector-Scalar Register" }, { "name": "RB", "desc": "Source Vector-Scalar Register" }, { "name": "XB", "desc": "Source VSX Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0xF00005E0", "length": "32", "binary_pattern": "60 | XT | / | XB | 752", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nreset_xflags()\nsrc ← bfp_CONVERT_FROM_SI64(VSR[32×BX+B].dword[0])\nrnd ← bfp_ROUND_TO_BFP64(0b0, FPSCR.RN, v)\nresult ← bfp64_CONVERT_FROM_BFP(rnd)\nif xx_flag=1 then SetFX(FPSCR.XX)\nVSR[32×TX+T].dword[0] ← result\nVSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000\nFPSCR.FPRF ← fprf_CLASS_BFP64(result)\nFPSCR.FR ← inc_flag\nFPSCR.FI ← xx_flag", "special_registers": "XX, FPRF", "programming_notes": "Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.", "extended_mnemonics": [], "page_found": "Page 562 - 563", "example": "xscvsxddp vs1, r5" }, { "mnemonic": "lxsd", "architecture": "PowerISA", "full_name": "Load VSX Scalar Doubleword", "summary": "Loads a doubleword from memory into a VSX scalar register.", "description": "When Big-Endian byte ordering is employed, the contents of the doubleword in storage at address EA are placed into load_data in such an order that; the contents of the byte in storage at address EA are placed into byte 0 of load_data, and so forth until the contents of the byte in storage at address EA+7 are placed into byte 7 of load_data. When Little-Endian byte ordering is employed, let load_data be the contents of the doubleword in storage at address EA such that; the contents of the byte in storage at address EA are placed into byte 7 of load_data, and so forth until the contents of the byte in storage at address EA+7 are placed into byte 0 of load_data.", "syntax": "lxsd VRT,disp(RA)", "operands": [ { "name": "VRT", "desc": "Target VSX Scalar Register" }, { "name": "RA", "desc": "Base General Purpose Register" }, { "name": "disp", "desc": "Displacement" } ], "encoding": { "format": "DS-form", "hex_opcode": "0xE4000002", "length": "32", "binary_pattern": "0 | VRT | RA | DS | 16 | 2", "bit_positions": "0:5 | 6:10 | 11:15 | 16:28 | 29:30 | 31" }, "extension": "VSX", "pseudocode": "if 'lxsd' then\n EA ← (RA|0) + EXTS64(DS||0b00)\n VSR[VRT+32].dword[0] ← MEM(EA,8)\n VSR[VRT+32].dword[1] ← 0x0000_0000_0000_0000", "special_registers": "N/A", "programming_notes": "The lxsd instruction loads a doubleword from memory into the VSX register, handling both Big-Endian and Little-Endian byte orderings. Ensure that the address is properly aligned to avoid potential performance penalties or exceptions. This instruction operates at user privilege level.", "extended_mnemonics": [], "page_found": "Page 597 - 598", "example": "lxsd v1, disp(RA)" }, { "mnemonic": "lxsdx", "architecture": "PowerISA", "full_name": "Load VSX Scalar Doubleword Indexed", "summary": "Loads a doubleword from memory into a VSX scalar register.", "description": "Loads a doubleword from memory at the address computed as (RA) + (RB) and places it into the specified VSX scalar register XT. The upper 64 bits of the VSX register remain unchanged. This is a VSX instruction and does not affect condition registers or status fields.", "syntax": "lxsdx XT,RA,RB", "operands": [ { "name": "XT", "desc": "Target VSX Scalar Register" }, { "name": "RA", "desc": "Source General Purpose Register (Base Address)" }, { "name": "RB", "desc": "Source General Purpose Register (Index)" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C000498", "length": "32", "binary_pattern": "0 | T | RA | RB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VSX", "pseudocode": "ea ← (RA) + (RB)\nXT.doubleword[1] ← [ea]", "special_registers": "MSR", "programming_notes": "The lxsdx instruction is commonly used to load a doubleword from memory into a VSX scalar register. Ensure that the VSX facility is enabled by checking and setting the appropriate bit in the MSR register. Be cautious of alignment requirements; while the instruction can handle unaligned accesses, performance may be improved with aligned data. This instruction operates at user privilege level but will raise an exception if the VSX facility is not available.", "extended_mnemonics": [], "page_found": "Page 598 - 599", "example": "lxsdx vs1, r4, r5" }, { "mnemonic": "lxsibzx", "architecture": "PowerISA", "full_name": "Load VSX Scalar as Integer Byte & Zero Indexed X-form", "summary": "Loads a byte from memory and places it into the specified VSX register, zeroing the upper half.", "description": "Loads a signed byte from memory at address (RA) + (RB), converts it to a 64-bit integer, and places the result into the right element of VSX register XT. The left element of XT is cleared. This is a VSX instruction and does not affect condition registers or status fields.", "syntax": "lxsibzx XT,RA,RB", "operands": [ { "name": "XT", "desc": "Target VSX Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "RB", "desc": "Source General Purpose Register" }, { "name": "VRT", "desc": "Target VSX Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C00061A", "length": "32", "binary_pattern": "31 | XT | RA | RB | 781 | TX", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "VSX", "pseudocode": "ea ← (RA) + (RB)\nbyte_value ← [ea] (sign-extended to 64 bits)\nXT.doubleword[1] ← byte_value\nXT.doubleword[0] ← 0", "special_registers": "N/A", "programming_notes": "The lxsibzx instruction is commonly used to load an unsigned byte from memory into a VSX register, with the upper 64 bits set to zero. Ensure that the effective address (EA) is properly aligned and within bounds to avoid exceptions. This instruction requires VSX or Vector facility enabled in the MSR register, depending on the transactional execution context.", "extended_mnemonics": [], "page_found": "Page 599 - 600", "example": "lxsibzx vs1, r4, r5" }, { "mnemonic": "lxsspx", "architecture": "PowerISA", "full_name": "Load VSX Scalar Single-Precision Indexed X-form", "summary": "Loads a single-precision floating-point value from memory and converts it to double-precision format in a VSX register.", "description": "Loads a single-precision floating-point value from memory at address (RA) + (RB), converts it to double-precision format, and places the result into the right doubleword of VSX register XT. The left doubleword is cleared. This is a VSX instruction and does not affect condition registers or status fields.", "syntax": "lxsspx XT,RA,RB", "operands": [ { "name": "XT", "desc": "Target Vector-Scalar Register" }, { "name": "RA", "desc": "Source General Purpose Register (Base Address)" }, { "name": "RB", "desc": "Source General Purpose Register (Index)" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C000418", "length": "32", "binary_pattern": "0 | T | RA | RB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VSX", "pseudocode": "ea ← (RA) + (RB)\nsp_value ← [ea] (single-precision)\ndp_value ← convert_sp_to_dp(sp_value)\nXT.doubleword[1] ← dp_value\nXT.doubleword[0] ← 0", "special_registers": "MSR", "programming_notes": "The lxsspx instruction is used to load a single-precision floating-point value from memory into a VSX register, converting it to double-precision format. Ensure that the VSX facility is enabled by checking and setting the MSR.VSX bit. The instruction requires 4-byte alignment for the source data in memory to avoid potential exceptions. This instruction operates at user privilege level.", "extended_mnemonics": [], "page_found": "Page 603 - 604", "example": "lxsspx vs1, r4, r5" }, { "mnemonic": "stxsd", "architecture": "PowerISA", "full_name": "Store VSX Scalar Doubleword", "summary": "Stores the contents of doubleword element 0 of VSR[XS] to memory.", "description": "The instruction stores the contents of doubleword element 0 of VSR[XS] to memory at the effective address (EA) calculated from RA and DS.", "syntax": "stxsd VRS,disp(RA)", "operands": [ { "name": "VRS", "desc": "Vector-Scalar Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "disp", "desc": "Displacement value" } ], "encoding": { "format": "DS-form", "hex_opcode": "0xF4000002", "length": "32", "binary_pattern": "0 | VRS | RA | DS | 2", "bit_positions": "0:5 | 6:10 | 11:15 | 16:29 | 30:31" }, "extension": "VSX", "pseudocode": "if MSR.VEC=0 then Vector_Unavailable()\nEA ← (RA|0) + EXTS64(DS||0b00)\nMEM(EA,8) ← VSR[VRS+32].dword[0]", "special_registers": "MSR", "programming_notes": "The stxsd instruction stores the first doubleword of a VSX register to memory. Ensure that the Vector Facility is enabled by checking and setting MSR.VEC if necessary. The EA must be 8-byte aligned for optimal performance, though unaligned accesses are supported with potential performance penalties.", "extended_mnemonics": [], "page_found": "Page 604 - 605", "example": "stxsd v1, disp(RA)" }, { "mnemonic": "stxsdx", "architecture": "PowerISA", "full_name": "Store VSX Scalar Doubleword Indexed X-form", "summary": "Stores a doubleword from a VSX scalar register to memory.", "description": "The instruction stores the contents of the specified doubleword element of a VSX scalar register into memory at an address calculated from two general-purpose registers.", "syntax": "stxsdx XS,RA,RB", "operands": [ { "name": "XS", "desc": "VSX Scalar Register" }, { "name": "RA", "desc": "Source General Purpose Register (Base Address)" }, { "name": "RB", "desc": "Source General Purpose Register (Index)" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C000598", "length": "32", "binary_pattern": "0 | S | RA | RB | SX", "bit_positions": "" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then\n VSX_Unavailable()\nEA ←((RA=0) ? 0 : GPR[RA]) + GPR[RB]\nMEM(EA,8) ←VSR[XS].dword[0]", "special_registers": "MSR", "programming_notes": "The stxsdx instruction stores a doubleword from a VSX scalar register into memory. Ensure the VSX facility is enabled by checking and setting the MSR.VSX bit. The effective address (EA) is calculated by adding the contents of two general-purpose registers, RA and RB. This instruction requires 8-byte alignment for the memory address to avoid exceptions.", "extended_mnemonics": [], "page_found": "Page 605 - 606", "example": "stxsdx vs1, r4, r5" }, { "mnemonic": "stxsibx", "architecture": "PowerISA", "full_name": "Store VSX Scalar as Integer Byte Indexed X-form", "summary": "Stores a byte from a VSX scalar register into memory at an address formed by adding two general-purpose registers.", "description": "The instruction stores the byte element 7 of VSR[XS] into the memory location specified by the effective address (EA), which is the sum of GPR[RA] and GPR[RB]. If RA is zero, EA is simply GPR[RB].", "syntax": "stxsibx XS,RA,RB", "operands": [ { "name": "XS", "desc": "VSX Scalar Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "RB", "desc": "Source General Purpose Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C00071A", "length": "32", "binary_pattern": "18 | S | RA | RB | SX", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VSX", "pseudocode": "if SX=0 & MSR.VSX=0 then\n VSX_Unavailable()\nif SX=1 & MSR.VEC=0 then\n Vector_Unavailable()\nEA ←((RA=0) ? 0 : GPR[RA]) + GPR[RB]\nMEM(EA,1) ←VSR[32×SX+S].byte[7]", "special_registers": "MSR", "programming_notes": "This instruction is used to store a specific byte from a VSX register into memory. Ensure that the appropriate privilege level and MSR bits (VSX or VEC) are set before using this instruction, as it may raise exceptions if not. The effective address is calculated based on GPR[RA] and GPR[RB], with special handling if RA is zero. Be cautious of alignment requirements to avoid potential performance penalties or exceptions.", "extended_mnemonics": [], "page_found": "Page 606 - 607", "example": "stxsibx vs1, r4, r5" }, { "mnemonic": "stxssp", "architecture": "PowerISA", "full_name": "Store VSX Scalar Single-Precision DS-form", "summary": "Stores a single-precision floating-point value from a VSX register to memory.", "description": "The instruction stores the double-precision floating-point value in doubleword element 0 of VSR[XS] converted to single-precision format into memory at the effective address (EA). The EA is calculated as the sum of the contents of register RA and the sign-extended DS field. If MSR.VEC=0, a Vector_Unavailable() exception is raised.", "syntax": "stxssp VRS,disp(RA)", "operands": [ { "name": "VRS", "desc": "VSX Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "disp", "desc": "Displacement Field" } ], "encoding": { "format": "DS-form", "hex_opcode": "0xF4000003", "length": "32", "binary_pattern": "0 | VRS | RA | DS", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VSX", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nelse if 'stxssp' then\n EA ← (RA|0) + EXTS64(DS||0b00)\n MEM(EA,4) ← bfp32_CONVERT_FROM_BFP64(VSR[VRS+32].dword[0])", "special_registers": "N/A", "programming_notes": "The stxssp instruction stores a single-precision floating-point value from the VSX register into memory. Ensure that the Vector Facility is enabled (MSR.VEC=1) to avoid exceptions. The effective address is calculated by adding the contents of RA and the sign-extended DS field. This instruction requires 4-byte alignment for the memory address.", "extended_mnemonics": [], "page_found": "Page 608 - 609", "example": "stxssp v1, disp(RA)" }, { "mnemonic": "stxsspx", "architecture": "PowerISA", "full_name": "Store VSX Scalar Single-Precision Indexed X-form", "summary": "Stores a single-precision floating-point value from a VSX register to memory.", "description": "Converts the value in the right doubleword of VSX register XS from double-precision to single-precision floating-point format and stores it to memory at address (RA) + (RB). This is a VSX instruction and does not affect condition registers or status fields.", "syntax": "stxsspx XS,RA,RB", "operands": [ { "name": "XS", "desc": "VSX Scalar Register Index" }, { "name": "RA", "desc": "Source General Purpose Register (Base Address)" }, { "name": "RB", "desc": "Source General Purpose Register (Index)" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C000518", "length": "32", "binary_pattern": "0 | S | RA | RB | 18 | SX", "bit_positions": "" }, "extension": "VSX", "pseudocode": "ea ← (RA) + (RB)\ndp_value ← XS.doubleword[1]\nsp_value ← convert_dp_to_sp(dp_value)\n[ea] ← sp_value", "special_registers": "MSR", "programming_notes": "The stxsspx instruction is used to store a single-precision floating-point value from the VSX register into memory. Ensure that the VSX facility is enabled by checking and setting the MSR.VSX bit. Be cautious of alignment requirements; the EA must be 4-byte aligned for optimal performance. If RA is zero, the effective address (EA) will be set to zero, which might lead to unexpected behavior if not intended.", "extended_mnemonics": [], "page_found": "Page 609 - 610", "example": "stxsspx vs1, r4, r5" }, { "mnemonic": "lxvb16x", "architecture": "PowerISA", "full_name": "Load VSX Vector Byte*16 Indexed", "summary": "Loads a vector of 16 byte elements from memory into a VSX register.", "description": "Loads a 128-bit vector containing 16 byte elements from memory into a VSX register. The effective address is computed as RA|0 + RB. No status fields are modified by this instruction.", "syntax": "lxvb16x XT,RA,RB", "operands": [ { "name": "XT", "desc": "Target VSX Register" }, { "name": "RA", "desc": "Source General Purpose Register (Base Address)" }, { "name": "RB", "desc": "Source General Purpose Register (Index)" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C0006D8", "length": "32", "binary_pattern": "1000 | 0111 | 0110 | TX | T | RA | RB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:30 | 31" }, "extension": "VSX", "pseudocode": "EA ← (RA=0 ? 0 : GPR[RA]) + GPR[RB]\nVSR[XT] ← MEM(EA, 16)", "special_registers": "MSR", "programming_notes": "Exhibits identical behavior in Big-Endian mode.", "extended_mnemonics": [], "page_found": "Page 611 - 612", "example": "lxvb16x vs1, r4, r5" }, { "mnemonic": "lxvh8x", "architecture": "PowerISA", "full_name": "Load VSX Vector Halfword*8 Indexed", "summary": "Loads a vector of 8 halfwords from memory into a VSX register.", "description": "Loads a 128-bit vector containing 8 halfword elements from memory into a VSX register. The effective address is computed as RA|0 + RB. No status fields are modified by this instruction.", "syntax": "lxvh8x XT,RA,RB", "operands": [ { "name": "XT", "desc": "Target VSX Register" }, { "name": "RA", "desc": "Source General Purpose Register (Base Address)" }, { "name": "RB", "desc": "Source General Purpose Register (Index)" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C000658", "length": "32", "binary_pattern": "0 | T | RA | RB | TX", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VSX", "pseudocode": "EA ← (RA=0 ? 0 : GPR[RA]) + GPR[RB]\nVSR[XT] ← MEM(EA, 16)", "special_registers": "MSR", "programming_notes": "lxvh8x, lxvd2x, lxvw4x, lxvb16x, and lxvx exhibit identical behavior in Big-Endian mode.", "extended_mnemonics": [], "page_found": "Page 613 - 614", "example": "lxvh8x vs1, r4, r5" }, { "mnemonic": "lxvx", "architecture": "PowerISA", "full_name": "Load VSX Vector Indexed X-form", "summary": "Loads a quadword from memory into a VSX register.", "description": "Loads a 128-bit quadword from memory into a VSX register using indexed addressing. The effective address is computed as RA|0 + RB. No status fields are modified by this instruction.", "syntax": "lxvx XT,RA,RB", "operands": [ { "name": "XT", "desc": "Target VSX Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "RB", "desc": "Source General Purpose Register" }, { "name": "xT", "desc": "Target Vector-Scalar Register" }, { "name": "rA", "desc": "Index General Purpose Register" }, { "name": "rB", "desc": "Base Address General Purpose Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C000218", "length": "32", "binary_pattern": "31 | XT | RA | RB | 268 | TX", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "VSX", "pseudocode": "EA ← (RA=0 ? 0 : GPR[RA]) + GPR[RB]\nVSR[XT] ← MEM(EA, 16)", "special_registers": "MSR", "programming_notes": "The lxvx instruction is used to load vector data from memory into VSX registers.", "extended_mnemonics": [], "page_found": "Page 615 - 616", "example": "lxvx vs1, r4, r5" }, { "mnemonic": "lxvrbx", "architecture": "PowerISA", "full_name": "Load VSX Vector Rightmost Byte Indexed X-form", "summary": "Loads a byte from memory into the rightmost byte of a VSX vector register.", "description": "Loads a single byte from memory and places it in the rightmost (least significant) byte position of a VSX register, with all other bytes set to 0. The effective address is computed as RA|0 + RB. No status fields are modified by this instruction.", "syntax": "lxvrbx XT,RA,RB", "operands": [ { "name": "XT", "desc": "Target Vector-Specific Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "RB", "desc": "Source General Purpose Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C00001A", "length": "32", "binary_pattern": "0 | T | RA | RB | 13 | TX", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:31" }, "extension": "VSX", "pseudocode": "EA ← (RA=0 ? 0 : GPR[RA]) + GPR[RB]\nVSR[XT] ← (0x00000000000000000000000000 || MEM(EA, 1))", "special_registers": "MSR", "programming_notes": "The lxvrbx instruction is used to load a single byte from memory into the rightmost byte of a VSX vector register. Ensure that the VSX facility is enabled in the MSR register; otherwise, an exception will be raised. The address calculation involves adding two general-purpose registers, RA and RB, where RA can be zero. This instruction zeroes out all other bytes in the target vector register except for the rightmost byte.", "extended_mnemonics": [], "page_found": "Page 619 - 620", "example": "lxvrbx vs1, r4, r5" }, { "mnemonic": "lxvrdx", "architecture": "PowerISA", "full_name": "Load VSX Vector Rightmost Doubleword Indexed X-form", "summary": "Loads a doubleword from memory into the rightmost element of a VSX vector register.", "description": "Loads a 64-bit doubleword from memory and places it in the rightmost (least significant) doubleword element of a VSX register, with the left doubleword set to 0. The effective address is computed as RA|0 + RB. No status fields are modified by this instruction.", "syntax": "lxvrdx XT,RA,RB", "operands": [ { "name": "XT", "desc": "Target VSX Vector Register" }, { "name": "RA", "desc": "Source General Purpose Register (address base)" }, { "name": "RB", "desc": "Source General Purpose Register (offset)" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C0000DA", "length": "32", "binary_pattern": "0 | T | RA | RB | 109 | TX", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:31" }, "extension": "VSX", "pseudocode": "EA ← (RA=0 ? 0 : GPR[RA]) + GPR[RB]\nVSR[XT] ← (0x0000000000000000 || MEM(EA, 8))", "special_registers": "MSR", "programming_notes": "The lxvrdx instruction is used to load a doubleword from memory into the rightmost element of a VSX vector register. Ensure that the VSX facility is enabled in the MSR register; otherwise, a VSX_Unavailable exception will be raised. The address calculation uses two general-purpose registers, RA and RB, where RA can be zero. Be cautious of alignment requirements for optimal performance and to avoid potential exceptions.", "extended_mnemonics": [], "page_found": "Page 620 - 621", "example": "lxvrdx vs1, r4, r5" }, { "mnemonic": "lxvrhx", "architecture": "PowerISA", "full_name": "Load VSX Vector Rightmost Halfword Indexed", "summary": "Loads a halfword from memory into the rightmost element of a VSX vector register.", "description": "Loads a 16-bit halfword from memory and places it in the rightmost (least significant) halfword position of a VSX register, with all other bits set to 0. The effective address is computed as RA|0 + RB. No status fields are modified by this instruction.", "syntax": "lxvrhx XT,RA,RB", "operands": [ { "name": "XT", "desc": "Target Vector-Scalar Register" }, { "name": "RA", "desc": "Source General Purpose Register (Base Address)" }, { "name": "RB", "desc": "Source General Purpose Register (Index)" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C00005A", "length": "32", "binary_pattern": "0 | T | RA | RB | TX", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VSX", "pseudocode": "EA ← (RA=0 ? 0 : GPR[RA]) + GPR[RB]\nVSR[XT] ← (0x000000000000000000000000 || MEM(EA, 2))", "special_registers": "MSR", "programming_notes": "The lxvrhx instruction is used to load a halfword from memory into the rightmost element of a VSX vector register. Ensure that the VSX facility is enabled in the MSR register; otherwise, an exception will be raised. The address calculation uses two general-purpose registers, RA and RB, where RA can be zero. The loaded halfword is placed in the rightmost halfword element (element 7) of the specified VSX vector register, with all other elements set to zero. Endianness affects how the halfword is stored in the vector register; ensure proper handling for both big-endian and little-endian systems.", "extended_mnemonics": [], "page_found": "Page 621 - 622", "example": "lxvrhx vs1, r4, r5" }, { "mnemonic": "lxvrwx", "architecture": "PowerISA", "full_name": "Load VSX Vector Rightmost Word Indexed X-form", "summary": "Loads a word from memory into the rightmost word of a VSX vector register.", "description": "Loads a 32-bit word from memory and places it in the rightmost (least significant) word position of a VSX register, with all other bits set to 0. The effective address is computed as RA|0 + RB. No status fields are modified by this instruction.", "syntax": "lxvrwx XT,RA,RB", "operands": [ { "name": "XT", "desc": "Target VSX Vector Register" }, { "name": "RA", "desc": "Source General Purpose Register (Base Address)" }, { "name": "RB", "desc": "Source General Purpose Register (Offset)" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C00009A", "length": "32", "binary_pattern": "0 | T | RA | RB | 77 | TX", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:31" }, "extension": "VSX", "pseudocode": "EA ← (RA=0 ? 0 : GPR[RA]) + GPR[RB]\nVSR[XT] ← (0x00000000000000000000000 || MEM(EA, 4))", "special_registers": "MSR", "programming_notes": "The lxvrwx instruction is used to load a word from memory into the rightmost word of a VSX vector register. Ensure that the VSX facility is enabled in the MSR register; otherwise, an exception will be raised. The address calculation involves adding two general-purpose registers, RA and RB, with a special case where if RA is zero, the base address defaults to zero. This instruction zeroes out the first three words of the target vector register before placing the loaded word into the rightmost position.", "extended_mnemonics": [], "page_found": "Page 622 - 623", "example": "lxvrwx vs1, r4, r5" }, { "mnemonic": "lxvll", "architecture": "PowerISA", "full_name": "Load VSX Vector with Length Left-justified X-form", "summary": "Loads a variable-length vector from memory into a VSX register, left-justifying the data.", "description": "Loads a variable-length data element from memory into a VSX register, left-justifying the loaded bytes within the 128-bit register. The effective address is RA|0, and the length in bytes is taken from bits 0-6 of RB (capped at 16). Remaining bytes in the register are zeroed. No status fields are modified by this instruction.", "syntax": "lxvll XT,RA,RB", "operands": [ { "name": "XT", "desc": "Target VSX Register" }, { "name": "RA", "desc": "Source General Purpose Register (Effective Address)" }, { "name": "RB", "desc": "Source General Purpose Register (Length and Data)" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C00025A", "length": "32", "binary_pattern": "0 | T | RA | RB | TX", "bit_positions": "0:5 | 6:10 | 11:15 | 16:29 | 30:31" }, "extension": "VSX", "pseudocode": "EA ← (RA=0 ? 0 : GPR[RA])\nlen ← GPR[RB][0:6] & 0xF\nfor i ← 0 to (len - 1) do\n VSR[XT][i*8:(i*8)+7] ← MEM(EA + i, 1)\nfor i ← len to 15 do\n VSR[XT][i*8:(i*8)+7] ← 0", "special_registers": "MSR", "programming_notes": "lxvll always performs storage accesses using Big-Endian byte-ordering. As such, care must be taken when using these instructions in Little-Endian systems.", "extended_mnemonics": [], "page_found": "Page 625 - 626", "example": "lxvll vs1, r4, r5" }, { "mnemonic": "stxvb16x", "architecture": "PowerISA", "full_name": "Store VSX Vector Byte*16 Indexed", "summary": "Stores a vector of 16 byte elements from VSR[XS] into Big-Endian storage using stxvb16x, retaining left-to-right element ordering.", "description": "The instruction stores a vector of 16 byte elements from VSR[XS] into Big-Endian storage using stxvb16x, retaining left-to-right element ordering.", "syntax": "stxvb16x XS,RA,RB", "operands": [ { "name": "XS", "desc": "Vector-Specific Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "RB", "desc": "Source General Purpose Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C0007D8", "length": "32", "binary_pattern": "S | RA | RB | SX", "bit_positions": "6:15 | 16:20 | 21:30 | 31" }, "extension": "VSX", "pseudocode": "if SX=0 & MSR.VSX=0 then VSX_Unavailable()\nif SX=1 & MSR.VEC=0 then Vector_Unavailable()\nEA ←((RA=0) ? 0 : GPR[RA]) + GPR[RB]\ndo i = 0 to 15\n MEM(EA+i,1) ←VSR[32×SX+S].byte[i]\nend", "special_registers": "MSR", "programming_notes": "stxvd2x, stxvw4x, stxvh8x, stxvb16x, and stxvx exhibit identical behavior in Big-Endian mode.", "extended_mnemonics": [], "page_found": "Page 627 - 628", "example": "stxvb16x vs1, r4, r5" }, { "mnemonic": "stxvh8x", "architecture": "PowerISA", "full_name": "Store VSX Vector Halfword*8 Indexed", "summary": "Stores a vector of 8 halfword elements from VSR[X] into memory using indexed addressing.", "description": "Stores a 128-bit VSX vector containing 8 halfword elements to memory using indexed addressing. The effective address is computed as (RA|0) + RB. This is a VSX extension instruction that does not affect condition registers or status flags.", "syntax": "stxvh8x XS,RA,RB", "operands": [ { "name": "XS", "desc": "VSX Register Index" }, { "name": "RA", "desc": "Source General Purpose Register (Base Address)" }, { "name": "RB", "desc": "Source General Purpose Register (Index)" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C000758", "length": "32", "binary_pattern": "0 | S | RA | RB | SX", "bit_positions": "" }, "extension": "VSX", "pseudocode": "EA ← (RA|0) + RB\n[EA] ← VSR[XS]", "special_registers": "MSR", "programming_notes": "stxvd2x, stxvw4x, stxvh8x, stxvb16x, and stxvx exhibit identical behavior in Big-Endian mode.", "extended_mnemonics": [], "page_found": "Page 629 - 630", "example": "stxvh8x vs1, r4, r5" }, { "mnemonic": "stxvx", "architecture": "PowerISA", "full_name": "Store VSX Vector Indexed X-form", "summary": "Stores a vector element from the VSX register file to memory.", "description": "Stores a 128-bit VSX vector element to memory using indexed addressing in X-form. The effective address is computed as (RA|0) + RB, and the vector is stored with element size determined by the instruction form. This VSX instruction does not affect condition registers or status flags.", "syntax": "stxvx xW,r0,rPW", "operands": [ { "name": "XS", "desc": "VSX Register Index" }, { "name": "RA", "desc": "Source General Purpose Register for Base Address" }, { "name": "RB", "desc": "Source General Purpose Register for Offset" }, { "name": "xW", "desc": "VSX Register containing the vector to store" }, { "name": "r0", "desc": "General Purpose Register (typically used as zero register)" }, { "name": "rPW", "desc": "Base address General Purpose Register for W" }, { "name": "rPX", "desc": "Base address General Purpose Register for X" }, { "name": "rPY", "desc": "Base address General Purpose Register for Y" }, { "name": "rPZ", "desc": "Base address General Purpose Register for Z" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C000318", "length": "32", "binary_pattern": "101100 | XS | 00000 | rA | rB | 00000 | 00000 | 00000", "bit_positions": "0:5 | 6:8 | 9 | 10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "VSX", "pseudocode": "EA ← (RA|0) + RB\n[EA] ← VSR[XS]", "special_registers": "MSR", "programming_notes": "The stxvx instruction is used for storing VSX vectors to memory. The index value in XS is multiplied by 16 bytes.", "extended_mnemonics": [], "page_found": "Page 631 - 632", "example": "stxvx xw, r0, rpw" }, { "mnemonic": "stxvrbx", "architecture": "PowerISA", "full_name": "Store VSX Vector Rightmost Byte Indexed X-form", "summary": "Stores the rightmost byte of a VSX vector element to memory.", "description": "The contents of byte element 15 of VSR[XS] are placed into storage at address EA, which is the sum of GPR[RA] and GPR[RB]. If RA=0, EA is just GPR[RB].", "syntax": "stxvrbx XS,RA,RB", "operands": [ { "name": "XS", "desc": "VSX Vector Register" }, { "name": "RA", "desc": "General Purpose Register (Base Address)" }, { "name": "RB", "desc": "General Purpose Register (Index)" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C00011A", "length": "32", "binary_pattern": "31 | S | RA | RB | 141 | SX", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nEA = ((RA=0) ? 0 : GPR[RA]) + GPR[RB];\nMEM(EA,1) = VSR[32×SX+S].byte[15];", "special_registers": "N/A", "programming_notes": "This instruction stores the rightmost byte of a VSX vector register into memory. Ensure that the VSX facility is enabled (MSR.VSX=1) to avoid an exception. The effective address (EA) is calculated by adding GPR[RA] and GPR[RB], unless RA is 0, in which case EA is just GPR[RB]. Be cautious of alignment; while not strictly required for a single byte, proper alignment can improve performance.", "extended_mnemonics": [], "page_found": "Page 633 - 634", "example": "stxvrbx vs1, r4, r5" }, { "mnemonic": "stxvrhx", "architecture": "PowerISA", "full_name": "Store VSX Vector Rightmost Halfword Indexed X-form", "summary": "Stores the rightmost halfword of a VSX vector element to memory.", "description": "Stores the rightmost halfword (least significant 16 bits) of the first double-precision element in a VSX vector to memory using indexed addressing. The effective address is computed as (RA|0) + RB. This VSX instruction does not affect condition registers or status flags.", "syntax": "stxvrhx XS,RA,RB", "operands": [ { "name": "XS", "desc": "VSX Vector Register" }, { "name": "RA", "desc": "General Purpose Register (Base Address)" }, { "name": "RB", "desc": "General Purpose Register (Index)" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C00015A", "length": "32", "binary_pattern": "0 | S | RA | RB | 16 | SX", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "VSX", "pseudocode": "EA ← (RA|0) + RB\n[EA:EA+1] ← VSR[XS][48:63]", "special_registers": "N/A", "programming_notes": "The stxvrhx instruction stores the rightmost halfword of a VSX vector element into memory. Ensure that the VSX facility is enabled (MSR.VSX=1); otherwise, a VSX_Unavailable exception will occur. The effective address is calculated by adding GPR[RA] and GPR[RB], so ensure these registers contain valid addresses. This instruction operates at user privilege level.", "extended_mnemonics": [], "page_found": "Page 634 - 635", "example": "stxvrhx vs1, r4, r5" }, { "mnemonic": "stxvll", "architecture": "PowerISA", "full_name": "Store VSX Vector with Length Left-justified", "summary": "Stores a left-justified vector from a VSX register to memory.", "description": "Stores a variable-length left-justified portion of a VSX vector to memory. The number of bytes to store (0-16) is specified in the low-order 4 bits of RB; bytes are stored starting at the effective address (RA|0). This VSX instruction does not affect condition registers or status flags.", "syntax": "stxvll XS,RA,RB", "operands": [ { "name": "XS", "desc": "VSX Register" }, { "name": "RA", "desc": "Source General Purpose Register (Effective Address)" }, { "name": "RB", "desc": "General Purpose Register containing the number of bytes to store" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C00035A", "length": "32", "binary_pattern": "0 | S | RA | RB | SX", "bit_positions": "" }, "extension": "VSX", "pseudocode": "EA ← (RA|0)\nlength ← RB[60:63]\nfor i ← 0 to length-1 do\n [EA+i] ← VSR[XS][8*i:8*i+7]\nend for", "special_registers": "MSR", "programming_notes": "stxvll always performs storage accesses using Big-Endian byte-ordering. As such, care must be taken when using these instructions in Little-Endian systems.", "extended_mnemonics": [], "page_found": "Page 637 - 638", "example": "stxvll vs1, r4, r5" }, { "mnemonic": "lxvpx", "architecture": "PowerISA", "full_name": "Load VSX Vector Paired Indexed X-form", "summary": "Loads a vector from memory into two VSR registers.", "description": "The contents of the octword in storage at address EA are placed into load_data. The order of bytes in load_data depends on the byte ordering (Little-Endian or Big-Endian). Bits 0-127 of load_data are placed into VSR[XTp], and bits 128-255 of load_data are placed into VSR[XTp+1].", "syntax": "lxvpx XTp,RA,RB", "operands": [ { "name": "XTp", "desc": "Target Vector-Specific Register (VSR) index" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "RB", "desc": "Source General Purpose Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C00029A", "length": "32", "binary_pattern": "10011000 | Tp | TX | RA | RB", "bit_positions": "0:5 | 6:9 | 10:14 | 15:19 | 20:31" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then\n VSX_Unavailable()\nEA ←((RA=0) ? 0 : GPR[RA]) + GPR[RB]\nload_data ←MEM(EA,32)\nVSR[32×TX+2×Tp] ←load_data.bit[ 0:127]\nVSR[32×TX+2×Tp+1] ←load_data.bit[128:255]", "special_registers": "N/A", "programming_notes": "For best performance, EA should be word-aligned.", "extended_mnemonics": [], "page_found": "Page 639 - 640", "example": "lxvpx vs2, r4, r5" }, { "mnemonic": "stxvpx", "architecture": "PowerISA", "full_name": "Store VSX Vector Paired Indexed X-form", "summary": "Stores a vector from two VSR registers into memory at the effective address.", "description": "The instruction stores an octword (128 bits) of data from two VSR registers into memory. The data is stored in big-endian order if the system is configured for big-endian byte ordering, and little-endian order if the system is configured for little-endian byte ordering.", "syntax": "stxvpx XSp,RA,RB", "operands": [ { "name": "XSp", "desc": "Index into VSR registers" }, { "name": "RA", "desc": "Base address register (GPR)" }, { "name": "RB", "desc": "Offset address register (GPR)" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C00039A", "length": "32", "binary_pattern": "0 | Sp | SX | RA | RB | 461", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then\n VSX_Unavailable()\nEA ←((RA=0) ? 0 : GPR[RA]) + GPR[RB]\nstore_data.bit[0:127] ← VSR[32×SX+2×Sp]\nstore_data.bit[128:255] ← VSR[32×SX+2×Sp+1]\nMEM(EA,32) ← store_data", "special_registers": "N/A", "programming_notes": "For best performance, EA should be word-aligned.", "extended_mnemonics": [], "page_found": "Page 641 - 642", "example": "stxvpx vs2, r4, r5" }, { "mnemonic": "xscpsgndp", "architecture": "PowerISA", "full_name": "VSX Scalar Copy Sign Double-Precision", "summary": "Copies the sign of a double-precision floating-point value from one register to another.", "description": "Copies the sign bit from the double-precision floating-point value in VSR[XA] to the double-precision value in VSR[XB], placing the result in VSR[XT]. The magnitude of the result comes from XB and the sign comes from XA. FPSCR is not affected; this instruction operates on the scalar element of the VSX register.", "syntax": "xscpsgndp XT,XA,XB", "operands": [ { "name": "XT", "desc": "Target Vector-Scalar Register" }, { "name": "XA", "desc": "Source Vector-Scalar Register for Sign Bit" }, { "name": "XB", "desc": "Source Vector-Scalar Register for Magnitude" } ], "encoding": { "format": "X-form", "hex_opcode": "0xF0000580", "length": "32", "binary_pattern": "176 | AX | BX | TX | T | A | B", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:28 | 29 | 30:31" }, "extension": "VSX", "pseudocode": "XT[0] ← XA[0]\nXT[1:63] ← XB[1:63]", "special_registers": "MSR", "programming_notes": "This instruction can be used to operate on single-precision source operands.\nPrevious versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.", "extended_mnemonics": [], "page_found": "Page 643 - 644", "example": "xscpsgndp vs1, vs2, vs3" }, { "mnemonic": "xsnabsdp", "architecture": "PowerISA", "full_name": "VSX Scalar Negative Absolute Double-Precision", "summary": "Computes the negative absolute value of a double-precision floating-point number.", "description": "The instruction computes the negative absolute value of the double-precision floating-point number in VSR[XB] and stores it in VSR[XT]. The result is zeroed out for the second doubleword.", "syntax": "xsnabsdp XT,XB", "operands": [ { "name": "XT", "desc": "Target Vector-Specific Register" }, { "name": "XB", "desc": "Source Vector-Specific Register" } ], "encoding": { "format": "XX2-form", "hex_opcode": "0xF00005A4", "length": "32", "binary_pattern": "T | B | BX | TX", "bit_positions": "6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then\n VSX_Unavailable()\nsrc ←VSR[32×BX+B].dword[0]\nVSR[32×TX+T].dword[0] ←bfp64_NEGATIVE_ABSOLUTE(src)\nVSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000", "special_registers": null, "programming_notes": "This instruction can be used to operate on a single-precision source operand. Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register.", "extended_mnemonics": [], "page_found": "Page 644 - 645", "example": "xsnabsdp vs1, vs3" }, { "mnemonic": "xvcpsgndp", "architecture": "PowerISA", "full_name": "VSX Vector Copy Sign Double-Precision", "summary": "Copies the sign bit from one double-precision vector element to another.", "description": "For xvcpsgndp, the sign bit of each doubleword element in VSR[XB] is copied to the corresponding doubleword element in VSR[XT], while the magnitude bits remain unchanged.", "syntax": "xvcpsgndp XT,XA,XB", "operands": [ { "name": "XT", "desc": "Target Vector-Specific Register" }, { "name": "XA", "desc": "Source Vector-Specific Register" }, { "name": "XB", "desc": "Source Vector-Specific Register" } ], "encoding": { "format": "XX3-form", "hex_opcode": "0xF0000780", "length": "32", "binary_pattern": "T | A | B | AX | BX | TX", "bit_positions": "0:10 | 11:15 | 16:20 | 21:28 | 29 | 30:31" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\ndo i = 0 to 1\n src1 ←VSR[32×AX+A].dword[i] & 0x8000_0000_0000_0000\n src2 ←VSR[32×BX+B].dword[i] & 0x7FFF_FFFF_FFFF_FFFF\n VSR[32×TX+T].dword[i] ←src1 | src2\nend", "special_registers": "N/A", "programming_notes": "This instruction is useful for copying the sign of double-precision floating-point numbers while preserving their magnitude. Ensure that VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. The operation is performed on each doubleword element independently, so alignment requirements are per-element rather than per-vector.", "extended_mnemonics": [ { "mnemonic": "xvmovdp", "equivalent_to": "xvcpsgndp XT,XB,XB" } ], "page_found": "Page 647 - 648", "example": "xvcpsgndp vs1, vs2, vs3" }, { "mnemonic": "xvnabsdp", "architecture": "PowerISA", "full_name": "Vector Negative Absolute Double-Precision", "summary": "Computes the negative absolute value of each double-precision floating-point element in a vector.", "description": "For xvnabsdp, the negative absolute value of each double-precision floating-point element in VSR[XB] is computed and stored in VSR[XT].", "syntax": "xvnabsdp XT,XB", "operands": [ { "name": "XT", "desc": "Target Vector Register" }, { "name": "XB", "desc": "Source Vector Register" } ], "encoding": { "format": "XX2-form", "hex_opcode": "0xF00007A4", "length": "32", "binary_pattern": "T | B | BX | TX", "bit_positions": "0:10 | 11:15 | 16:20 | 21:31" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\ndo i = 0 to 1\n src ←VSR[32×BX+B].dword[i]\n VSR[32×TX+T].dword[i] ←bfp64_NEGATIVE_ABSOLUTE(src)\nend", "special_registers": null, "programming_notes": "This instruction computes the negative absolute value of each double-precision floating-point element in a vector. Ensure that VSX (Vector Scalar Extensions) is enabled by checking and setting the appropriate bit in the Machine State Register (MSR). The operation processes two elements per vector register, so ensure proper alignment if manipulating individual elements.", "extended_mnemonics": [], "page_found": "Page 648 - 649", "example": "xvnabsdp vs1, vs3" }, { "mnemonic": "xsdivdp", "architecture": "PowerISA", "full_name": "VSX Scalar Divide Double-Precision", "summary": "Divides the double-precision floating-point value in VSR[XA] by the double-precision floating-point value in VSR[XB].", "description": "Divides the scalar double-precision floating-point value in VSR[XA] by the scalar double-precision floating-point value in VSR[XB], storing the result in VSR[XT]. The operation follows IEEE 754 semantics; FPSCR is updated with exception flags and the result sign/exponent. This VSX instruction requires the VSX extension.", "syntax": "xsdivdp XT,XA,XB", "operands": [ { "name": "XT", "desc": "Target Vector-Scalar Register" }, { "name": "XA", "desc": "Source Vector-Scalar Register" }, { "name": "XB", "desc": "Source Vector-Scalar Register" } ], "encoding": { "format": "XX3-form", "hex_opcode": "0xF00001C0", "length": "32", "binary_pattern": "111100 | XA | XB | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000", "bit_positions": "" }, "extension": "VSX", "pseudocode": "XT ← VSR[XA] ÷ VSR[XB]\nFPSCR ← updated with exception flags and rounding", "special_registers": "FPSCR FPRF FR FI FX OX UX ZX XX VXSNAN VXIDI VXZDZ", "programming_notes": "The xsdivdp instruction is used for dividing double-precision floating-point numbers. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. Handle special cases like NaNs and infinities by checking the FPSCR flags after execution. The result is rounded according to the rounding mode set in FPSCR.RN.", "extended_mnemonics": [], "page_found": "Page 659 - 660", "example": "xsdivdp vs1, vs2, vs3" }, { "mnemonic": "xsmuldp", "architecture": "PowerISA", "full_name": "VSX Scalar Multiply Double-Precision", "summary": "Multiplies two double-precision floating-point numbers and places the result in a vector register.", "description": "Multiplies the scalar double-precision floating-point value in VSR[XA] by the scalar double-precision floating-point value in VSR[XB], storing the result in VSR[XT]. The operation follows IEEE 754 semantics; FPSCR is updated with exception flags and rounding control. This VSX instruction requires the VSX extension.", "syntax": "xsmuldp XT,XA,XB", "operands": [ { "name": "XT", "desc": "Target Vector-Specific Register" }, { "name": "XA", "desc": "Source Vector-Specific Register" }, { "name": "XB", "desc": "Source Vector-Specific Register" } ], "encoding": { "format": "XX3-form", "hex_opcode": "0xF0000180", "length": "32", "binary_pattern": "111100 | XA | XB | XT | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000", "bit_positions": "" }, "extension": "VSX", "pseudocode": "XT ← VSR[XA] × VSR[XB]\nFPSCR ← updated with exception flags and rounding", "special_registers": "FPSCR.FPRF, FPSCR.FR, FPSCR.FI, FPSCR.FX, FPSCR.OX, FPSCR.UX, XX, VXSNAN, VXIMZ", "programming_notes": "Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.", "extended_mnemonics": [], "page_found": "Page 665 - 666", "example": "xsmuldp vs1, vs2, vs3" }, { "mnemonic": "xssqrtsp", "architecture": "PowerISA", "full_name": "VSX Scalar Square Root Single-Precision", "summary": "Computes the square root of a single-precision floating-point number in VSX.", "description": "The unbounded-precision square root of src is produced. The intermediate result is rounded to single-precision using the rounding mode specified by RN. The result is placed into doubleword element 0 of VSR[XT] in double-precision format. The contents of doubleword element 1 of VSR[XT] are set to 0.", "syntax": "xssqrtsp XT,XB", "operands": [ { "name": "XT", "desc": "Target Vector-Specific Register" }, { "name": "XB", "desc": "Source Vector-Specific Register" }, { "name": "VX", "desc": "Target Vector Register" }, { "name": "VB", "desc": "Source Vector Register" } ], "encoding": { "format": "XX2-form", "hex_opcode": "0xF000002C", "length": "32", "binary_pattern": "1111 | 0001 | 0000 | 0000 | 0000 | 0000 | 0000 | 1000", "bit_positions": "" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nreset_xflags()\nsrc ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])\nv ←bfp_SQUARE_ROOT(src)\nrnd ←bfp_ROUND_TO_BFP32(FPSCR.RN,v)\nresult32 ←bfp32_CONVERT_FROM_BFP(rnd)\nresult64 ←bfp64_CONVERT_FROM_BFP(rnd)\nif vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\nif vxsqrt_flag=1 then SetFX(FPSCR.VXSQRT)\nif ox_flag=1 then SetFX(FPSCR.OX)\nif ux_flag=1 then SetFX(FPSCR.UX)\nif xx_flag=1 then SetFX(FPSCR.XX)\nvx_flag ←vxsnan_flag | vxsqrt_flag\nvex_flag ←FPSCR.VE & vx_flag\nif vex_flag=0 then do\n VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000\n FPSCR.FPRF ←fprf_CLASS_BFP32(result32)\n FPSCR.FR ←inc_flag\n FPSCR.FI ←xx_flag\nend else do\n FPSCR.FR ←0b0\n FPSCR.FI ←0b0\nend", "special_registers": "FPSCR, VSR[XT], FPRF, FR, FI, FX, OX, UX, VXSNAN, VXSQRT", "programming_notes": "Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.", "extended_mnemonics": [], "page_found": "Page 675 - 676", "example": "xssqrtsp vs1, vs3" }, { "mnemonic": "xssubdp", "architecture": "PowerISA", "full_name": "VSX Scalar Subtract Double-Precision", "summary": "Subtracts the contents of two double-precision floating-point registers and places the result in another register.", "description": "The instruction subtracts the value of src2 (negated) from src1, producing a sum with unbounded range and precision. The sum is normalized and rounded to double-precision using the rounding mode specified by RN. The result is placed into doubleword element 0 of VSR[XT], and doubleword element 1 of VSR[XT] is set to 0.", "syntax": "xssubdp XT,XA,XB", "operands": [ { "name": "XT", "desc": "Target Vector-Scalar Register" }, { "name": "XA", "desc": "Source Vector-Scalar Register" }, { "name": "XB", "desc": "Source Vector-Scalar Register" } ], "encoding": { "format": "XX3-form", "hex_opcode": "0xF0000140", "length": "32", "binary_pattern": "111100 | XA | XB | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000", "bit_positions": "" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nreset_xflags()\nsrc1 ← bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])\nsrc2 ← bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])\nv ← bfp_ADD(src1, bfp_NEGATE(src2))\nrnd ← bfp_ROUND_TO_BFP64(0b0, FPSCR.RN, v)\nresult ← bfp64_CONVERT_FROM_BFP(rnd)\nif vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\nif vxisi_flag=1 then SetFX(FPSCR.VXISI)\nif ox_flag=1 then SetFX(FPSCR.OX)\nif ux_flag=1 then SetFX(FPSCR.UX)\nif xx_flag=1 then SetFX(FPSCR.XX)\nvx_flag ← vxsnan_flag | vxisi_flag\nvex_flag ← FPSCR.VE & vx_flag\nif vex_flag=0 then do\n VSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000\n FPSCR.FR ← inc_flag\n FPSCR.FI ← xx_flag\nelse do\n FPSCR.FR ← 0b0\n FPSCR.FI ← 0b0\nend\nVSR[32×TX+T].dword[0] ← result\nFPSCR.FPRF ← fprf_CLASS_BFP64(result)", "special_registers": "vxsnan_flag, vxisi_flag", "programming_notes": "Let XT be the value 32×TX + T. Let XA be the value 32×AX + A. Let XB be the value 32×BX + B. Let src1 be the double-precision floating-point value in doubleword element 0 of VSR[XA]. Let src2 be the double-precision floating-point value in doubleword element 0 of VSR[XB].", "extended_mnemonics": [], "page_found": "Page 677 - 678", "example": "xssubdp vs1, vs2, vs3" }, { "mnemonic": "xsmaddadp", "architecture": "PowerISA", "full_name": "VSX Scalar Multiply-Add Type-A Double-Precision", "summary": "Performs a double-precision floating-point multiply-add operation.", "description": "For xsmaddadp, do the following. Let src1 be the double-precision floating-point value in doubleword element 0 of VSR[XA]. Let src2 be the double-precision floating-point value in doubleword element 0 of VSR[XT]. Let src3 be the double-precision floating-point value in doubleword element 0 of VSR[XB].", "syntax": "xsmaddadp XT,XA,XB", "operands": [ { "name": "XT", "desc": "Target Vector-Specific Register" }, { "name": "XA", "desc": "Source Vector-Specific Register" }, { "name": "XB", "desc": "Source Vector-Specific Register" } ], "encoding": { "format": "XX3-form", "hex_opcode": "0xF0000108", "length": "32", "binary_pattern": "111100 | XA | XB | XT | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000 | 000000", "bit_positions": "" }, "extension": "VSX", "pseudocode": "if 'xsmaddadp' then do\n src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])\n src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×TX+T].dword[0])\n src3 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])\n v ←bfp_MULTIPLY_ADD(src1, src3, src2)\n rnd ←bfp_ROUND_TO_BFP64(0b0, FPSCR.RN, v)\n result ←bfp64_CONVERT_FROM_BFP(rnd)\n\n if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\n if vximz_flag=1 then SetFX(FPSCR.VXIMZ)\n if vxisi_flag=1 then SetFX(FPSCR.VXISI)\n if ox_flag=1 then SetFX(FPSCR.OX)\n if ux_flag=1 then SetFX(FPSCR.UX)\n if xx_flag=1 then SetFX(FPSCR.XX)\n\n vx_flag ←vxsnan_flag | vximz_flag | vxisi_flag\n vex_flag ←FPSCR.VE & vx_flag\n\n if vex_flag=0 then do\n VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000\n FPSCR.FPRF ←fprf_CLASS_BFP64(result)\n FPSCR.FR ←inc_flag\n FPSCR.FI ←xx_flag\n end else do\n FPSCR.FR ←0b0\n FPSCR.FI ←0b0\n end\nend", "special_registers": "FPSCR, VSR[XT], VSR[XA], VSR[XB]", "programming_notes": "This instruction performs a scalar multiply-add operation on double-precision floating-point values. Ensure that the VSX registers are properly aligned and initialized before use. The result is rounded according to the rounding mode specified in the FPSCR register. Be aware of potential exceptions such as NaNs, infinities, or underflows, which can set flags in the FPSCR.", "extended_mnemonics": [], "page_found": "Page 683 - 684", "example": "xsmaddadp vs1, vs2, vs3" }, { "mnemonic": "xsmaddasp", "architecture": "PowerISA", "full_name": "VSX Scalar Multiply-Add Type-A Single-Precision", "summary": "Performs a single-precision floating-point multiply-add operation.", "description": "For xsmaddasp, the double-precision floating-point value in doubleword element 0 of VSR[XA] is multiplied by the double-precision floating-point value in doubleword element 0 of VSR[XT], and then the result is added to the double-precision floating-point value in doubleword element 0 of VSR[XB]. The final result is normalized and rounded to single-precision format.", "syntax": "xsmaddasp XT,XA,XB", "operands": [ { "name": "XT", "desc": "Target Vector-Specific Register" }, { "name": "XA", "desc": "Source Vector-Specific Register" }, { "name": "XB", "desc": "Source Vector-Specific Register" } ], "encoding": { "format": "XX3-form", "hex_opcode": "0xF0000008", "length": "32", "binary_pattern": "60 | XT | XA | XB | 8", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nreset_xflags()\nsrc1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])\nsrc2 ←bfp_CONVERT_FROM_BFP64(VSR[32×TX+T].dword[0])\nsrc3 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])\nv ←bfp_MULTIPLY_ADD(src1, src3, src2)\nrnd ←bfp_ROUND_TO_BFP32(FPSCR.RN, v)\nresult32 ←bfp32_CONVERT_FROM_BFP(rnd)\nresult64 ←bfp64_CONVERT_FROM_BFP(rnd)\nif vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\nif vximz_flag=1 then SetFX(FPSCR.VXIMZ)\nif vxisi_flag=1 then SetFX(FPSCR.VXISI)\nif ox_flag=1 then SetFX(FPSCR.OX)\nif ux_flag=1 then SetFX(FPSCR.UX)\nif xx_flag=1 then SetFX(FPSCR.XX)\nvx_flag ←vxsnan_flag | vximz_flag | vxisi_flag\nvex_flag ←FPSCR.VE & vx_flag\nif vex_flag=0 then do\n VSR[32×TX+T].dword[0] ←result64\n VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000\n FPSCR.FPRF ←fprf_CLASS_BFP32(result32)\n FPSCR.FR ←inc_flag\n FPSCR.FI ←xx_flag\nelse do\n FPSCR.FI ←0b0", "special_registers": "FPSCR, VSR[XT]", "programming_notes": "See Table 7.10, “VSX Scalar Floating-Point Final Result,” on page 618.", "extended_mnemonics": [], "page_found": "Page 686 - 687", "example": "xsmaddasp vs1, vs2, vs3" }, { "mnemonic": "xsmaddqp", "architecture": "PowerISA", "full_name": "VSX Scalar Multiply-Add Quad-Precision", "summary": "Performs a quad-precision floating-point multiply-add operation with rounding to even.", "description": "This instruction multiplies two quad-precision floating-point numbers and adds the third number, rounding the result according to the specified mode.", "syntax": "xsmaddqp VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0xFC000308", "length": "32", "binary_pattern": "0 | VRT | VRA | VRB | RO | 18", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nreset_xflags()\nsrc1 ← bfp_CONVERT_FROM_BFP128(VSR[VRA+32])\nsrc2 ← bfp_CONVERT_FROM_BFP128(VSR[VRT+32])\nsrc3 ← bfp_CONVERT_FROM_BFP128(VSR[VRB+32])\nv ← bfp_MULTIPLY_ADD(src1, src3, src2)\nrnd ← bfp_ROUND_TO_BFP128(RO, FPSCR.RN, v)\nresult ← bfp128_CONVERT_FROM_BFP(rnd)\nif vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\nif vximz_flag=1 then SetFX(FPSCR.VXIMZ)\nif vxisi_flag=1 then SetFX(FPSCR.VXISI)\nif ox_flag=1 then SetFX(FPSCR.OX)\nif ux_flag=1 then SetFX(FPSCR.UX)\nif xx_flag=1 then SetFX(FPSCR.XX)\nvx_flag ← vxsnan_flag | vximz_flag | vxisi_flag\nex_flag ← FPSCR.VE & vx_flag\nif ex_flag=0 then do\n VSR[VRT+32] ← result\n FPSCR.FPRF ← fprf_CLASS_BFP128(result)\nend\nFPSCR.FR ← (vx_flag=0) & inc_flag\nFPSCR.FI ← (vx_flag=0) & xx_flag", "special_registers": "FPSCR", "programming_notes": "This instruction is used for performing a multiply-add operation on quad-precision floating-point numbers. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. Be aware of rounding modes specified by FPSCR.RN and handle potential exceptions like VXSNAN, VXIMZ, Vxisi, OX, UX, and XX appropriately. The result is stored back into the destination register if no exceptions occur.", "extended_mnemonics": [], "page_found": "Page 689 - 690", "example": "xsmaddqp v1, v2, v3" }, { "mnemonic": "xsmsubadp", "architecture": "PowerISA", "full_name": "VSX Scalar Multiply-Subtract Type-A Double-Precision", "summary": "Performs a double-precision floating-point multiply-subtract operation.", "description": "For xsmsubadp, the value in VSR[XA] is multiplied by the value in VSR[XT], and then the result is subtracted from the value in VSR[XB].", "syntax": "xsmsubadp XT,XA,XB", "operands": [ { "name": "XT", "desc": "Target Vector-Scalar Register" }, { "name": "XA", "desc": "Source Vector-Scalar Register" }, { "name": "XB", "desc": "Source Vector-Scalar Register" } ], "encoding": { "format": "XX3-form", "hex_opcode": "0xF0000188", "length": "32", "binary_pattern": "18 | T | A | B | AX | BX | TX", "bit_positions": "" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nreset_xflags()\nsrc1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])\nsrc2 ←bfp_CONVERT_FROM_BFP64(VSR[32×TX+T].dword[0])\nsrc3 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])\nv ←bfp_MULTIPLY_ADD(src1, src3, bfp_NEGATE(src2))\nrnd ←bfp_ROUND_TO_BFP64(0b0, FPSCR.RN, v)\nresult ←bfp64_CONVERT_FROM_BFP(rnd)\nif vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\nif vximz_flag=1 then SetFX(FPSCR.VXIMZ)\nif vxisi_flag=1 then SetFX(FPSCR.VXISI)\nif ox_flag=1 then SetFX(FPSCR.OX)\nif ux_flag=1 then SetFX(FPSCR.UX)\nif xx_flag=1 then SetFX(FPSCR.XX)\nvx_flag ←vxsnan_flag | vximz_flag | vxisi_flag\nvex_flag ←FPSCR.VE & vx_flag\nif vex_flag=0 then do\n VSR[32×TX+T].dword[0] ←result\n VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000\n FPSCR.FPRF ←fprf_CLASS_BFP64(result)\n FPSCR.FR ←inc_flag\n FPSCR.FI ←xx_flag\nend else do\n FPSCR.FI ←0b0\nend", "special_registers": "FPSCR, VSR[XT]", "programming_notes": "This instruction is commonly used for performing complex floating-point arithmetic operations involving multiplication and subtraction. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. Be cautious of potential overflow or underflow conditions, as indicated by the FPSCR flags. The operation requires proper alignment of the input values, specifically 64-bit double-precision floating-point numbers.", "extended_mnemonics": [], "page_found": "Page 692 - 693", "example": "xsmsubadp vs1, vs2, vs3" }, { "mnemonic": "xmsubasp", "architecture": "PowerISA", "full_name": "VSX Scalar Multiply-Subtract Type-A Single-Precision", "summary": "Performs a multiply-subtract operation on single-precision floating-point values.", "description": "For xmsubasp, the double-precision floating-point value in doubleword element 0 of VSR[XA] is multiplied by the double-precision floating-point value in doubleword element 0 of VSR[XB], and the result is subtracted from the double-precision floating-point value in doubleword element 0 of VSR[XT]. The result is then rounded to single-precision format and placed into doubleword element 0 of VSR[XT] in double-precision format.", "syntax": "xmsubasp XT,XA,XB", "operands": [ { "name": "XT", "desc": "Target Vector-Scalar Register" }, { "name": "XA", "desc": "Source Vector-Scalar Register" }, { "name": "XB", "desc": "Source Vector-Scalar Register" } ], "encoding": { "format": "XX3-form", "hex_opcode": "0xF0000088", "length": "32", "binary_pattern": "18 | T | A | B | AX | BX | TX", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:30 | 31" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nreset_xflags()\nsrc1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])\nsrc2 ←bfp_CONVERT_FROM_BFP64(VSR[32×TX+T].dword[0])\nsrc3 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])\nv ←bfp_MULTIPLY_ADD(src1, src3, bfp_NEGATE(src2))\nrnd ←bfp_ROUND_TO_BFP32(FPSCR.RN, v)\nresult32 ←bfp32_CONVERT_FROM_BFP(rnd)\nresult64 ←bfp64_CONVERT_FROM_BFP(rnd)\nif vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\nif vximz_flag=1 then SetFX(FPSCR.VXIMZ)\nif vxisi_flag=1 then SetFX(FPSCR.VXISI)\nif ox_flag=1 then SetFX(FPSCR.OX)\nif ux_flag=1 then SetFX(FPSCR.UX)\nif xx_flag=1 then SetFX(FPSCR.XX)\nvx_flag ←vxsnan_flag | vximz_flag | vxisi_flag\nvex_flag ←FPSCR.VE & vx_flag\nif vex_flag=0 then do\n VSR[32×TX+T].dword[0] ←result64\n VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000\n FPSCR.FPRF ←fprf_CLASS_BFP32(result32)\n FPSCR.FR ←inc_flag\n FPSCR.FI ←xx_flag\nelse do\n FPSCR.FR ←0b0\n FPSCR.FI ←0b0", "special_registers": "FPSCR, VSR[XT], FPRF", "programming_notes": "This instruction is commonly used for performing complex floating-point arithmetic operations in single-precision format while maintaining double-precision intermediate results. Ensure that the VSX (Vector Scalar Extensions) are enabled, as attempting to use this instruction without them will result in an unavailable exception. Be cautious of rounding modes and exceptions; check the FPSCR register for flags indicating overflow, underflow, or invalid operations. The instruction requires proper alignment of input values in VSR registers, specifically targeting doubleword elements.", "extended_mnemonics": [], "page_found": "Page 695 - 696", "example": "xmsubasp vs1, vs2, vs3" }, { "mnemonic": "xsmsubasp", "architecture": "PowerISA", "full_name": "VSX Scalar Multiply Subtract Add Pair Single Precision", "summary": "Performs a multiply-subtract-add operation on single-precision floating-point values.", "description": "Performs a fused multiply-subtract-add operation on scalar single-precision floating-point values. The operation computes (XA × XB) - XT + implicit_addend and stores the result in XT. This MMA/VSX fusion instruction updates FPSCR with exception flags and follows IEEE 754 rounding semantics.", "syntax": "xsmsubasp XT,XA,XB", "operands": [ { "name": "XT", "desc": "Target Vector-Scalar Register" }, { "name": "XA", "desc": "Source Vector-Scalar Register" }, { "name": "XB", "desc": "Source Vector-Scalar Register" }, { "name": "FRT", "desc": "Target Floating Point Register" }, { "name": "FRB", "desc": "Source Floating Point Register" }, { "name": "FRA", "desc": "Source Floating Point Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0xF0000088", "length": "32", "binary_pattern": "60 | XT | XA | XB | 136", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VSX", "pseudocode": "XT ← (XA × XB) - XT + (addend)\nFPSCR ← updated with exception flags and rounding", "special_registers": "FPSCR", "programming_notes": "See Table 7.10, “VSX Scalar Floating-Point Final Result,” on page 618.", "extended_mnemonics": [], "page_found": "Page 696 - 697", "example": "xsmsubasp vs1, vs2, vs3" }, { "mnemonic": "xsmsubqp", "architecture": "PowerISA", "full_name": "VSX Scalar Multiply-Subtract Quad-Precision", "summary": "Performs a multiply-subtract operation on quad-precision floating-point values.", "description": "Performs a scalar multiply-subtract operation on quad-precision floating-point values, computing VRT = VRT - (VRA × VRB). The result is rounded according to the current rounding mode in FPSCR. This instruction requires VSX support and updates FPSCR exception flags based on the operation result.", "syntax": "xsmsubqp VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0xFC000348", "length": "32", "binary_pattern": "18 | VRT | VRA | VRB | RO", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VSX", "pseudocode": "VRT[0:127] ← VRT[0:127] - (VRA[0:127] × VRB[0:127])\nFPSCR ← update_exception_flags(FPSCR, result)", "special_registers": "FPSCR", "programming_notes": "The xsmsubqp instruction is used for performing a multiply-subtract operation on quad-precision floating-point numbers. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid an exception. Be cautious of rounding modes and exceptions, as they can affect the result and set flags in the FPSCR register. This instruction operates on 128-bit aligned data in vector registers VSR[VRA+32], VSR[VRT+32], and VSR[VRB+32].", "extended_mnemonics": [], "page_found": "Page 698 - 699", "example": "xsmsubqp v1, v2, v3" }, { "mnemonic": "xsnmaddadp", "architecture": "PowerISA", "full_name": "VSX Scalar Negative Multiply-Add Double-Precision Type-A", "summary": "Performs a negative multiply-add operation on double-precision floating-point values.", "description": "For xsnmaddadp, the value in VSR[XA] is multiplied by the value in VSR[XB], and then the result is added to the value in VSR[XT]. The final result is negated and stored back into VSR[XT].", "syntax": "xsnmaddadp XT,XA,XB", "operands": [ { "name": "XT", "desc": "Target Vector-Scalar Register" }, { "name": "XA", "desc": "Source Vector-Scalar Register" }, { "name": "XB", "desc": "Source Vector-Scalar Register" } ], "encoding": { "format": "XX3-form", "hex_opcode": "0xF0000508", "length": "32", "binary_pattern": "60 | XT | XA | XB | 1288", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nreset_xflags()\nsrc1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])\nsrc2 ←bfp_CONVERT_FROM_BFP64(VSR[32×TX+T].dword[0])\nsrc3 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])\nv ←bfp_MULTIPLY_ADD(src1, src3, src2)\nrnd ←bfp_NEGATE(bfp_ROUND_TO_BFP64(0b0, FPSCR.RN, v))\nresult ←bfp64_CONVERT_FROM_BFP(rnd)\nif vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\nif vximz_flag=1 then SetFX(FPSCR.VXIMZ)\nif vxisi_flag=1 then SetFX(FPSCR.VXISI)\nif ox_flag=1 then SetFX(FPSCR.OX)\nif ux_flag=1 then SetFX(FPSCR.UX)\nif xx_flag=1 then SetFX(FPSCR.XX)\nvx_flag ←vxsnan_flag | vximz_flag | vxisi_flag\nvex_flag ←FPSCR.VE & vx_flag\nif vex_flag=0 then do\n VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000\n FPSCR.FPRF ←fprf_CLASS_BFP32(result)\n FPSCR.FI ←xx_flag\nelse do\n FPSCR.FR ←0b0\n FPSCR.FI ←0b0\nend\nVSR[32×TX+T].dword[0] ←result", "special_registers": "FPSCR, VSR[XT]", "programming_notes": "This instruction is commonly used in applications requiring precise floating-point arithmetic, such as scientific computations and financial calculations. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking the MSR.VSX bit; otherwise, handle the VSX_Unavailable exception. Be cautious of potential exceptions like VXSNAN, VXIMZ, Vxisi, OX, UX, and XX, which can alter the FPSCR flags and affect program flow. The instruction operates on double-precision floating-point numbers and requires proper alignment of the input registers.", "extended_mnemonics": [], "page_found": "Page 701 - 702", "example": "xsnmaddadp vs1, vs2, vs3" }, { "mnemonic": "xsnmaddasp", "architecture": "PowerISA", "full_name": "VSX Scalar Negative Multiply-Add Single-Precision Type-A", "summary": "Performs a negative multiply-add operation on single-precision floating-point values.", "description": "For xsnmaddasp, the double-precision floating-point value in doubleword element 0 of VSR[XA] is multiplied by the double-precision floating-point value in doubleword element 0 of VSR[XB], and then added to the double-precision floating-point value in doubleword element 0 of VSR[XT]. The result is negated, rounded to single-precision format, and placed into doubleword element 0 of VSR[XT] in double-precision format.", "syntax": "xsnmaddasp XT,XA,XB", "operands": [ { "name": "XT", "desc": "Target Vector-Scalar Register" }, { "name": "XA", "desc": "Source Vector-Scalar Register" }, { "name": "XB", "desc": "Source Vector-Scalar Register" } ], "encoding": { "format": "XX3-form", "hex_opcode": "0xF0000408", "length": "32", "binary_pattern": "1111 | 0001 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000", "bit_positions": "" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nreset_xflags()\nsrc1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])\nsrc2 ←bfp_CONVERT_FROM_BFP64(VSR[32×TX+T].dword[0])\nsrc3 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])\nv ←bfp_MULTIPLY_ADD(src1, src3, src2)\nrnd ←bfp_NEGATE(bfp_ROUND_TO_BFP32(FPSCR.RN, v))\nresult32 ←bfp32_CONVERT_FROM_BFP(rnd)\nresult64 ←bfp64_CONVERT_FROM_BFP(rnd)\nvxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\nvximz_flag=1 then SetFX(FPSCR.VXIMZ)\nvxisi_flag=1 then SetFX(FPSCR.VXISI)\nox_flag=1 then SetFX(FPSCR.OX)\nux_flag=1 then SetFX(FPSCR.UX)\nxx_flag=1 then SetFX(FPSCR.XX)\nvx_flag ←vxsnan_flag | vximz_flag | vxisi_flag\nvex_flag ←FPSCR.VE & vx_flag\nif vex_flag=0 then do\n VSR[32×TX+T].dword[0] ←result64\n VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000\n FPSCR.FPRF ←fprf_CLASS_BFP32(result32)\n FPSCR.FR ←inc_flag\n FPSCR.FI ←xx_flag\nelse do\n FPSCR.FR ←0b0\n FPSCR.FI ←0b0\nend", "special_registers": "FPSCR, VSR[XT], VSR[XA], VSR[XB]", "programming_notes": "See Table 7.32, “Scalar Floating-Point Final Result with Negation,” on page 669.", "extended_mnemonics": [], "page_found": "Page 705 - 706", "example": "xsnmaddasp vs1, vs2, vs3" }, { "mnemonic": "xsnmaddqp", "architecture": "PowerISA", "full_name": "VSX Scalar Negative Multiply-Add Quad-Precision", "summary": "Performs a negative multiply-add operation on quad-precision floating-point values.", "description": "Performs a scalar negative multiply-add operation on quad-precision floating-point values, computing VRT = -(VRA × VRB) + VRT. The result is rounded according to the current rounding mode in FPSCR. This instruction requires VSX support and updates FPSCR exception flags based on the operation result.", "syntax": "xsnmaddqp VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0xFC000388", "length": "32", "binary_pattern": "11110001 | 00000000 | 00000000 | 1000", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VSX", "pseudocode": "VRT[0:127] ← -(VRA[0:127] × VRB[0:127]) + VRT[0:127]\nFPSCR ← update_exception_flags(FPSCR, result)", "special_registers": "FPSCR FPRF FR FI FX VXSNAN VXIMZ VXISI OX UX XX", "programming_notes": "This instruction is used for performing a scalar negative multiply-add operation on quad-precision floating-point numbers. Ensure that the VSX feature is enabled in the MSR register to avoid exceptions. Be cautious of potential overflow and underflow conditions, as indicated by the OX and UX flags in the FPSCR register. The result is rounded according to the rounding mode specified in FPSCR.RN.", "extended_mnemonics": [ "xsnmaddqp[o]" ], "page_found": "Page 708 - 709", "example": "xsnmaddqp v1, v2, v3" }, { "mnemonic": "xsnmsubadp", "architecture": "PowerISA", "full_name": "VSX Scalar Negative Multiply-Subtract Type-A Double-Precision", "summary": "Performs a negative multiply-subtract operation on double-precision floating-point values.", "description": "For xsnmsubadp, the double-precision floating-point value in doubleword element 0 of VSR[XA] is multiplied by the double-precision floating-point value in doubleword element 0 of VSR[XT], and the result is added to the negated double-precision floating-point value in doubleword element 0 of VSR[XB]. The final result is normalized, rounded to double-precision using the rounding mode specified by RN, and placed into doubleword element 0 of VSR[XT] in double-precision format. Doubleword element 1 of VSR[XT] is set to 0.", "syntax": "xsnmsubadp XT,XA,XB", "operands": [ { "name": "XT", "desc": "Target Vector-Specific Register" }, { "name": "XA", "desc": "Source Vector-Specific Register" }, { "name": "XB", "desc": "Source Vector-Specific Register" } ], "encoding": { "format": "XX3-form", "hex_opcode": "0xF0000588", "length": "32", "binary_pattern": "0 | 6 | 11 | 16 | 21 | 29 | 30 | 31", "bit_positions": "0 | 6 | 11 | 16 | 21 | 29 | 30 | 31" }, "extension": "VSX", "pseudocode": "if 'xsnmsubadp' then do\n src1 ← bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])\n src2 ← bfp_CONVERT_FROM_BFP64(VSR[32×TX+T].dword[0])\n src3 ← bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])\nend\nv ← bfp_MULTIPLY_ADD(src1, src3, bfp_NEGATE(src2))\nrnd ← bfp_NEGATE(bfp_ROUND_TO_BFP64(0b0, FPSCR.RN, v))\nresult ← bfp64_CONVERT_FROM_BFP(rnd)\nif vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\nif vxisi_flag=1 then SetFX(FPSCR.VXISI)\nif ux_flag=1 then SetFX(FPSCR.UX)\nif xx_flag=1 then SetFX(FPSCR.XX)\nvx_flag ← vxsnan_flag | vximz_flag | vxisi_flag\nvex_flag ← FPSCR.VE & vx_flag\nif vex_flag=0 then do\n VSR[32×TX+T].dword[0] ← result\n VSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000\n FPSCR.FPRF ← fprf_CLASS_BFP64(result)\n FPSCR.FR ← inc_flag\n FPSCR.FI ← xx_flag\nend else do\n FPSCR.FR ← 0b0\n FPSCR.FI ← 0b0\nend", "special_registers": "FPSCR, VSR[XT]", "programming_notes": "This instruction is commonly used in applications requiring complex floating-point arithmetic, such as scientific computations and simulations. Ensure that the input values are properly aligned to avoid precision loss. The instruction operates at the user privilege level and may raise exceptions if invalid operations occur, such as division by zero or overflow. Performance can be optimized by ensuring that the VSX registers are preloaded with the necessary data.", "extended_mnemonics": [], "page_found": "Page 711 - 712", "example": "xsnmsubadp vs1, vs2, vs3" }, { "mnemonic": "xsnmsubasp", "architecture": "PowerISA", "full_name": "VSX Scalar Negative Multiply-Subtract Type-A Single-Precision", "summary": "Performs a negative multiply-subtract operation on single-precision floating-point values.", "description": "For xsnmsubasp, the double-precision floating-point value in doubleword element 0 of VSR[XA] is multiplied by the double-precision floating-point value in doubleword element 0 of VSR[XT], and then the result is negated and added to the double-precision floating-point value in doubleword element 0 of VSR[XB]. The final result is normalized, rounded to single-precision using the rounding mode specified by RN, negated, and placed into doubleword element 0 of VSR[XT] in double-precision format. Doubleword element 1 of VSR[XT] is set to 0.", "syntax": "xsnmsubasp XT,XA,XB", "operands": [ { "name": "XT", "desc": "Target Vector-Scalar Register" }, { "name": "XA", "desc": "Source Vector-Scalar Register" }, { "name": "XB", "desc": "Source Vector-Scalar Register" } ], "encoding": { "format": "XX3-form", "hex_opcode": "0xF0000488", "length": "32", "binary_pattern": "60 | XT | XA | XB | 1160", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nreset_xflags()\nsrc1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])\nsrc2 ←bfp_CONVERT_FROM_BFP64(VSR[32×TX+T].dword[0])\nsrc3 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])\nv ←bfp_MULTIPLY_ADD(src1, src3, bfp_NEGATE(src2))\nrnd ←bfp_NEGATE(bfp_ROUND_TO_BFP32(FPSCR.RN, v))\nresult32 ←bfp32_CONVERT_FROM_BFP(rnd)\nresult64 ←bfp64_CONVERT_FROM_BFP(rnd)\nif vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\nif vximz_flag=1 then SetFX(FPSCR.VXIMZ)\nif vxisi_flag=1 then SetFX(FPSCR.VXISI)\nif ox_flag=1 then SetFX(FPSCR.OX)\nif ux_flag=1 then SetFX(FPSCR.UX)\nif xx_flag=1 then SetFX(FPSCR.XX)\nvx_flag ←vxsnan_flag | vximz_flag | vxisi_flag\nvex_flag ←FPSCR.VE & vx_flag\nif vex_flag=0 then do\n VSR[32×TX+T].dword[0] ←result64\n VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000\n FPSCR.FPRF ←fprf_CLASS_BFP32(result32)\n FPSCR.FR ←inc_flag\n FPSCR.FI ←xx_flag\nelse do\n FPSCR.FI ←0b0\nend", "special_registers": "FPSCR, VSR[XT]", "programming_notes": "This instruction is commonly used in applications requiring complex floating-point arithmetic, such as scientific computations and graphics processing. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking the MSR.VSX bit; otherwise, handle the VSX_Unavailable exception. Be cautious of potential exceptions like VXSNAN, VXIMZ, Vxisi, OX, UX, and XX, which can alter the FPSCR flags and affect program flow. The instruction operates on double-precision values but rounds the result to single-precision, so consider precision implications in your application.", "extended_mnemonics": [], "page_found": "Page 714 - 715", "example": "xsnmsubasp vs1, vs2, vs3" }, { "mnemonic": "xsnmsubqp", "architecture": "PowerISA", "full_name": "VSX Scalar Negative Multiply-Subtract Quad-Precision", "summary": "Performs a negative multiply-subtract operation on quad-precision floating-point values.", "description": "Performs a scalar negative multiply-subtract operation on quad-precision floating-point values, computing VRT = -(VRA × VRB) - VRT. The result is rounded according to the current rounding mode in FPSCR. This instruction requires VSX support and updates FPSCR exception flags based on the operation result.", "syntax": "xsnmsubqp VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0xFC0003C8", "length": "32", "binary_pattern": "64 | VRT | VRA | VRB | RO", "bit_positions": "" }, "extension": "VSX", "pseudocode": "VRT[0:127] ← -(VRA[0:127] × VRB[0:127]) - VRT[0:127]\nFPSCR ← update_exception_flags(FPSCR, result)", "special_registers": "FPSCR, VXSNAN, VXIMZ, Vxisi, OX, UX, XX, FPRF, FR, FI", "programming_notes": "The xsnmsubqp instruction is used for performing a scalar negative multiply-subtract operation on quad-precision floating-point numbers. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. Be cautious of potential overflow and underflow conditions, as indicated by the exception flags in FPSCR. The result is rounded using round-to-nearest mode by default.", "extended_mnemonics": [], "page_found": "Page 717 - 718", "example": "xsnmsubqp v1, v2, v3" }, { "mnemonic": "xsredp", "architecture": "PowerISA", "full_name": "Vector Scalar Reciprocal Estimate Double Precision", "summary": "Estimates the reciprocal of a double-precision floating-point value.", "description": "Computes an estimate of the reciprocal (1/XB) for a double-precision floating-point scalar value, placing the result in XT. The estimate is accurate to about 15 bits of precision. This instruction requires VSX support and may update FPSCR exception flags if the source is invalid or zero.", "syntax": "xsredp XT,XB", "operands": [ { "name": "XT", "desc": "Target Vector-Specific Register" }, { "name": "XB", "desc": "Source Vector-Specific Register" } ], "encoding": { "format": "XX2-form", "hex_opcode": "0xF0000168", "length": "32", "binary_pattern": "18 | T | B | 90", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VSX", "pseudocode": "XT[0:63] ← reciprocal_estimate(XB[0:63])\nFPSCR ← update_exception_flags(FPSCR, result)", "special_registers": "FPSCR.FR, FPSCR.FPRF, FPSCR.FI, FPSCR.VXSNAN, FPSCR.OX, FPSCR.UX, FPSCR.ZX", "programming_notes": "Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.", "extended_mnemonics": [], "page_found": "Page 720 - 721", "example": "xsredp vs1, vs3" }, { "mnemonic": "xsresp", "architecture": "PowerISA", "full_name": "VSX Scalar Reciprocal Estimate Single-Precision", "summary": "Estimates the reciprocal of a single-precision floating-point value.", "description": "Computes an estimate of the reciprocal (1/XB) for a single-precision floating-point scalar value, placing the result in XT. The estimate is accurate to about 7 bits of precision. This instruction requires VSX support and may update FPSCR exception flags if the source is invalid or zero.", "syntax": "xsresp XT,XB", "operands": [ { "name": "XT", "desc": "Target Vector-Scalar Register" }, { "name": "XB", "desc": "Source Vector-Scalar Register" } ], "encoding": { "format": "XX2-form", "hex_opcode": "0xF0000068", "length": "32", "binary_pattern": "T | B | 26 | BX | TX", "bit_positions": "6:10 | 11:15 | 16:20 | 21:29 | 30:31" }, "extension": "VSX", "pseudocode": "XT[32:63] ← reciprocal_estimate(XB[32:63])\nFPSCR ← update_exception_flags(FPSCR, result)", "special_registers": "FPSCR, VXSNAN", "programming_notes": "Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register.", "extended_mnemonics": [], "page_found": "Page 721 - 722", "example": "xsresp vs1, vs3" }, { "mnemonic": "xsrsqrtedp", "architecture": "PowerISA", "full_name": "Double-Precision XX2-form Scalar Reciprocal Square Root Estimate", "summary": "Estimates the reciprocal square root of a double-precision floating-point value.", "description": "The instruction estimates the reciprocal square root of the double-precision floating-point value in doubleword element 0 of VSR[XB] and places the result into doubleword element 0 of VSR[XT]. Doubleword element 1 of VSR[XT] is set to 0.", "syntax": "xsrsqrtedp XT,XB", "operands": [ { "name": "XT", "desc": "Target Vector-Scalar Register" }, { "name": "XB", "desc": "Source Vector-Scalar Register" } ], "encoding": { "format": "XX2-form", "hex_opcode": "0xF0000128", "length": "32", "binary_pattern": "18 | T | B | 74", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nreset_xflags()\nsrc ← bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])\nv ← bfp_RECIPROCAL_SQUARE_ROOT_ESTIMATE(src)\nrnd ← bfp_ROUND_TO_BFP64(0b0, FPSCR.RN, v)\nresult ← bfp64_CONVERT_FROM_BFP(rnd)\nif vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\nif vxsqrt_flag=1 then SetFX(FPSCR.VXSQRT)\nif zx_flag=1 then SetFX(FPSCR.ZX)\nvx_flag ← vxsnan_flag | vxsqrt_flag\nvex_flag ← FPSCR.VE & vx_flag\nzex_flag ← FPSCR.ZE & zx_flag\nif vex_flag=0 & zex_flag=0 then do\n VSR[32×TX+T].dword[0] ← result\n VSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000\n FPSCR.FPRF ← fprf_CLASS_BFP64(result)\n FPSCR.FR ← 0bU\n FPSCR.FI ← 0bU\nend", "special_registers": "FPSCR (FPRF, FX, VXSNAN, FR, FI)", "programming_notes": "Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register.", "extended_mnemonics": [], "page_found": "Page 722 - 723", "example": "xsrsqrtedp vs1, vs3" }, { "mnemonic": "xsrsqrtesp", "architecture": "PowerISA", "full_name": "VSX Scalar Reciprocal Square Root Estimate (Single-Precision)", "summary": "Estimates the reciprocal square root of a single-precision floating-point value.", "description": "The instruction estimates the reciprocal square root of a single-precision floating-point value in doubleword element 0 of VSR[XB] and places the result into doubleword element 0 of VSR[XT]. Doubleword element 1 of VSR[XT] is set to 0.", "syntax": "xsrsqrtesp XT,XB", "operands": [ { "name": "XT", "desc": "Target Vector-Scalar Register" }, { "name": "XB", "desc": "Source Vector-Scalar Register" }, { "name": "FRT", "desc": "Target Floating Point Register" }, { "name": "FRB", "desc": "Source Floating Point Register" } ], "encoding": { "format": "XX2-form", "hex_opcode": "0xF0000028", "length": "32", "binary_pattern": "T | B | 10 | BX | TX", "bit_positions": "6 | 11 | 16 | 21 | 30 31" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nreset_xflags()\nsrc ← bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])\nv ← bfp_RECIPROCAL_SQUARE_ROOT_ESTIMATE(src)\nrnd ← bfp_ROUND_TO_BFP32(FPSCR.RN, v)\nresult32 ← bfp32_CONVERT_FROM_BFP(rnd)\nresult64 ← bfp64_CONVERT_FROM_BFP(rnd)\nif vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\nif vxsqrt_flag=1 then SetFX(FPSCR.VXSQRT)\nif ox_flag=1 then SetFX(FPSCR.OX)\nif ux_flag=1 then SetFX(FPSCR.UX)\nif 0bU then SetFX(FPSCR.XX)\nif zx_flag=1 then SetFX(FPSCR.ZX)\nvx_flag ← vxsnan_flag | vxsqrt_flag\nvex_flag ← FPSCR.VE & vx_flag\nzex_flag ← FPSCR.ZE & zx_flag\nif vex_flag=0 & zex_flag=0 then do\n VSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000\n FPSCR.FPRF ← fprf_CLASS_BFP32(result32)\n FPSCR.FR ← 0bU\n FPSCR.FI ← 0bU\nelse do\n FPSCR.FR ← 0b0\n FPSCR.FI ← 0b0\nend", "special_registers": "FPSCR (FPRF, FX, OX, UX, ZX, VXSNAN, VXSQRT, FR, FI, XX)", "programming_notes": "Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.", "extended_mnemonics": [], "page_found": "Page 723 - 724", "example": "xsrsqrtesp vs1, vs3" }, { "mnemonic": "xstdivdp", "architecture": "PowerISA", "full_name": "VSX Scalar Test for software Divide Double-Precision", "summary": "Performs a double-precision floating-point division and sets condition flags based on the result.", "description": "Tests for special cases in double-precision floating-point division (such as division by zero or invalid operands) and sets a condition register field with the result. No actual division is performed; instead, the instruction is used to check operand validity before software performs the division. This instruction requires VSX support.", "syntax": "xstdivdp BF,XA,XB", "operands": [ { "name": "BF", "desc": "Condition Register Field" }, { "name": "XA", "desc": "Index for Source Vector Register (src1)" }, { "name": "XB", "desc": "Index for Source Vector Register (src2)" } ], "encoding": { "format": "XX3-form", "hex_opcode": "0xF00001E8", "length": "32", "binary_pattern": "18 | BF | XA | XB", "bit_positions": "0:5 | 6:8 | 9:10 | 11:31" }, "extension": "VSX", "pseudocode": "BF ← test_division(XA[0:63], XB[0:63])\nCR[BF:BF+3] ← BF", "special_registers": "CR (field BF)", "programming_notes": "The xstdivdp instruction is used for performing double-precision floating-point division and setting condition flags based on various error conditions or special cases. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking the MSR.VSX bit; otherwise, a VSX_Unavailable exception will be raised. Be cautious of division by zero, overflow, underflow, and NaN/Infinity values, as these can set specific condition flags in the CR register.", "extended_mnemonics": [], "page_found": "Page 724 - 725", "example": "xstdivdp cr0, vs2, vs3" }, { "mnemonic": "xstsqrtdp", "architecture": "PowerISA", "full_name": "VSX Scalar Test for software Square Root, Double-Precision", "summary": "Tests the double-precision floating-point value in VSR[XB] and sets condition register field BF based on various flags.", "description": "The instruction tests the double-precision floating-point value in VSR[XB].dword[0] and sets CR.field[BF] based on flags fe_flag, fg_flag, and fl_flag.", "syntax": "xstsqrtdp BF,XB", "operands": [ { "name": "BF", "desc": "Condition Register Field" }, { "name": "XB", "desc": "Vector-Scalar Register Index" } ], "encoding": { "format": "XX2-form", "hex_opcode": "0xF00001A8", "length": "32", "binary_pattern": "18 | BF | XB", "bit_positions": "0:5 | 6:8 | 9:31" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then\n VSX_Unavailable()\nsrc ← VSR[32×XB+B].dword[0]\ne_b ← src.bit[1:11] - 1023\nfe_flag ← IsNaN(src) | IsInf(src) | IsZero(src) |\n IsNeg(src) | (e_b <= -970)\nfg_flag ← IsInf(src) | IsZero(src) | IsDen(src)\nfl_flag ← xsrsqrtedp_error() <= 2-14\nCR.field[BF] ← 0b1 || fg_flag || fe_flag || 0b0", "special_registers": "CR", "programming_notes": "This instruction is used to test a double-precision floating-point value for special conditions like NaN, infinity, zero, and denormal numbers. It sets the condition register field based on these flags. Ensure VSX is enabled in the MSR; otherwise, an exception will be raised. The instruction does not require any specific alignment or privilege level.", "extended_mnemonics": [], "page_found": "Page 725 - 726", "example": "xstsqrtdp cr0, vs3" }, { "mnemonic": "xvmaddasp", "architecture": "PowerISA", "full_name": "Vector Multiply-Add Single-Precision Type-A", "summary": "Performs a single-precision floating-point multiply-add operation on vector elements.", "description": "Performs a vector multiply-add operation on single-precision floating-point elements, computing XT = XT + (XA × XB) for each element. The operation is fused, rounding only once at the end. This instruction requires VSX support and updates FPSCR exception flags based on the operation results.", "syntax": "xvmaddasp XT,XA,XB", "operands": [ { "name": "XT", "desc": "Destination Vector Register" }, { "name": "XA", "desc": "Source Vector Register" }, { "name": "XB", "desc": "Source Vector Register" } ], "encoding": { "format": "XX3-form", "hex_opcode": "0xF0000208", "length": "32", "binary_pattern": "6 | T | A | B | AX | BX | TX", "bit_positions": "" }, "extension": "VSX", "pseudocode": "for i ∈ {0, 1, 2, 3}\n XT[i*32:(i+1)*32] ← XT[i*32:(i+1)*32] + (XA[i*32:(i+1)*32] × XB[i*32:(i+1)*32])\nFPSCR ← update_exception_flags(FPSCR, results)", "special_registers": "FPSCR, VXSNAN, VXIMZ, Vxisi, OX, UX, XX", "programming_notes": "The xvmaddasp instruction is commonly used for performing vectorized single-precision floating-point multiply-add operations. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid a VSX_Unavailable exception. Be cautious of potential exceptions such as VXSNAN, VXIMZ, Vxisi, OX, UX, and XX, which can be set based on the operation's result and FPSCR settings. The instruction operates on 128-bit vectors, so ensure proper alignment for optimal performance.", "extended_mnemonics": [], "page_found": "Page 748 - 749", "example": "xvmaddasp vs1, vs2, vs3" }, { "mnemonic": "xvmsubadp", "architecture": "PowerISA", "full_name": "VSX Vector Multiply-Subtract Type-A Double-Precision", "summary": "Performs a double-precision floating-point multiply-subtract operation on vector elements.", "description": "Performs a vector multiply-subtract operation on double-precision floating-point elements, computing XT = XT - (XA × XB) for each element. The operation is fused, rounding only once at the end. This instruction requires VSX support and updates FPSCR exception flags based on the operation results.", "syntax": "xvmsubadp XT,XA,XB", "operands": [ { "name": "XT", "desc": "Target Vector Register" }, { "name": "XA", "desc": "Source Vector Register" }, { "name": "XB", "desc": "Source Vector Register" } ], "encoding": { "format": "XX3-form", "hex_opcode": "0xF0000388", "length": "32", "binary_pattern": "1000 | XA | XB | XT | 000000 | 000000 | 000000 | 000000", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:28 | 29 | 30 | 31" }, "extension": "VSX", "pseudocode": "for i ∈ {0, 1}\n XT[i*64:(i+1)*64] ← XT[i*64:(i+1)*64] - (XA[i*64:(i+1)*64] × XB[i*64:(i+1)*64])\nFPSCR ← update_exception_flags(FPSCR, results)", "special_registers": "FPSCR", "programming_notes": "The xvmsubadp instruction is commonly used for complex floating-point arithmetic operations involving multiplication, subtraction, and addition. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid a VSX_Unavailable exception. Be cautious of potential exceptions such as VXSNAN, VXIMZ, VXISI, OX, UX, and XX, which can be triggered by invalid operations or overflow conditions. The instruction operates on double-precision floating-point numbers and requires proper alignment of the input vectors.", "extended_mnemonics": [], "page_found": "Page 751 - 752", "example": "xvmsubadp vs1, vs2, vs3" }, { "mnemonic": "xvmsubasp", "architecture": "PowerISA", "full_name": "VSX Vector Multiply-Subtract Type-A Single-Precision", "summary": "Performs a vector multiply-subtract operation on single-precision floating-point values.", "description": "Performs a single-precision floating-point multiply-subtract operation (XT ← (XA × XB) - XT) on vector elements using the Type-A fused operation. This VSX instruction operates on two 128-bit vector registers, each containing four single-precision floating-point elements. The instruction does not affect condition registers or status flags; rounding behavior follows the FPSCR settings.", "syntax": "xvmsubasp XT,XA,XB", "operands": [ { "name": "XT", "desc": "Destination Vector Register" }, { "name": "XA", "desc": "Source Vector Register A" }, { "name": "XB", "desc": "Source Vector Register B" }, { "name": "VX", "desc": "Target Vector Register" } ], "encoding": { "format": "XX3-form", "hex_opcode": "0xF0000288", "length": "32", "binary_pattern": "111100 | XA | XT | XB | VX | 000000 | 000000 | 000000", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:28 | 29 | 30 | 31" }, "extension": "VSX", "pseudocode": "XT ← (XA × XB) - XT", "special_registers": "FPSCR", "programming_notes": "The xvmsubasp instruction is commonly used for vectorized floating-point operations, particularly in scientific computing and graphics processing. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking the MSR.VSX bit; otherwise, a VSX_Unavailable exception will be raised. Be cautious of alignment requirements for vector registers to avoid performance penalties or exceptions. This instruction operates at user privilege level but can generate various floating-point exceptions based on the FPSCR settings, which should be handled appropriately in error-checking code.", "extended_mnemonics": [], "page_found": "Page 754 - 755", "example": "xvmsubasp vs1, vs2, vs3" }, { "mnemonic": "xvnmaddadp", "architecture": "PowerISA", "full_name": "Vector Negative Multiply-Add Type-A Double-Precision", "summary": "Performs a negative multiply-add operation on double-precision floating-point elements.", "description": "For xvnmaddadp, for each integer value i from 0 to 1, the following operations are performed: src1 is multiplied by src3, then src2 is added to the product. The result is normalized and rounded to double precision using the rounding mode specified by RN. The final result is negated and placed into VSR[XT].", "syntax": "xvnmaddadp XT,XA,XB", "operands": [ { "name": "XT", "desc": "Target Vector Register" }, { "name": "XA", "desc": "Source Vector Register" }, { "name": "XB", "desc": "Source Vector Register" } ], "encoding": { "format": "XX3-form", "hex_opcode": "0xF0000708", "length": "32", "binary_pattern": "60 | XT | XA | XB | 1800", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\n\nex_flag ←0b0\ndo i = 0 to 1\n reset_xflags()\n src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[i])\n src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×TX+T].dword[i])\n src3 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])\n\n v ←bfp_MULTIPLY_ADD(src1,src3,src2)\n rnd ←bfp_NEGATE(bfp_ROUND_TO_BFP64(FPSCR.RN,v))\n vresult.dword[i] ←bfp64_CONVERT_FROM_BFP(rnd)\n\n if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\n if vximz_flag=1 then SetFX(FPSCR.VXIMZ)\n if vxisi_flag=1 then SetFX(FPSCR.VXISI)\n if ox_flag=1 then SetFX(FPSCR.OX)\n if ux_flag=1 then SetFX(FPSCR.UX)\n if xx_flag=1 then SetFX(FPSCR.XX)\n\n ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vximz_flag) | (FPSCR.VE & vxisi_flag) | (FPSCR.OE & ox_flag) | (FPSCR.UE & ux_flag) | (FPSCR.XE & xx_flag)\nend\n\nif ex_flag=0 then VSR[32×TX+T] ←vresult", "special_registers": "FPSCR, VXSNAN, VXIMZ, Vxisi, OX, UX, XX", "programming_notes": "This instruction performs vectorized negative multiply-add operations on double-precision floating-point numbers. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. Be cautious with rounding modes specified by FPSCR.RN, as they can affect precision and performance. Handle exceptions properly by checking the VXSNAN, VXIMZ, Vxisi, OX, UX, and XX flags after execution.", "extended_mnemonics": [], "page_found": "Page 757 - 758", "example": "xvnmaddadp vs1, vs2, vs3" }, { "mnemonic": "xvnmaddasp", "architecture": "PowerISA", "full_name": "Vector Negative Multiply-Add Single-Precision Type-A", "summary": "Performs a negative multiply-add operation on single-precision floating-point elements.", "description": "Performs a negative multiply-add operation on single-precision floating-point vector elements (XT ← -(XA × XB) + XT) using Type-A fused arithmetic. This VSX instruction operates on 128-bit vector registers each containing four single-precision values. The operation does not affect condition registers; rounding and exception behavior follows FPSCR settings.", "syntax": "xvnmaddasp XT,XA,XB", "operands": [ { "name": "XT", "desc": "Target Vector Register" }, { "name": "XA", "desc": "Source Vector Register" }, { "name": "XB", "desc": "Source Vector Register" } ], "encoding": { "format": "XX3-form", "hex_opcode": "0xF0000608", "length": "32", "binary_pattern": "60 | XT | XA | XB | 1544", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VSX", "pseudocode": "XT ← -(XA × XB) + XT", "special_registers": "FPSCR, VXSNAN, VXIMZ, Vxisi, OX, UX, XX", "programming_notes": "This instruction is commonly used in vectorized floating-point computations where negative multiplication and addition are required. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking MSR.VSX before using this instruction. Be aware of potential exceptions such as NaNs, infinities, or underflows, which can set flags in FPSCR and may trigger exceptions based on the current settings.", "extended_mnemonics": [], "page_found": "Page 761 - 762", "example": "xvnmaddasp vs1, vs2, vs3" }, { "mnemonic": "xvnmsubadp", "architecture": "PowerISA", "full_name": "VSX Vector Negative Multiply-Subtract Type-A Double-Precision", "summary": "Performs a negative multiply-subtract operation on double-precision floating-point elements.", "description": "For each integer value i from 0 to 1, the instruction performs the following operations: multiplies src1 by src3, negates src2, adds the result to the product, normalizes the sum, rounds it to double precision, and places the final result into VSR[XT].", "syntax": "xvnmsubadp XT,XA,XB", "operands": [ { "name": "XT", "desc": "Target Vector Register" }, { "name": "XA", "desc": "Source Vector Register" }, { "name": "XB", "desc": "Source Vector Register" } ], "encoding": { "format": "XX3-form", "hex_opcode": "0xF0000788", "length": "32", "binary_pattern": "60 | XT | XA | XB | 1928", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\n\nex_flag ←0b0\ndo i = 0 to 1\n reset_xflags()\n src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[i])\n src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×TX+T].dword[i])\n src3 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])\n\n v ←bfp_MULTIPLY_ADD(src1,src3,bfp_NEGATE(src2))\n rnd ←bfp_NEGATE(bfp_ROUND_TO_BFP64(FPSCR.RN,v))\n vresult.dword[i] ←bfp64_CONVERT_FROM_BFP(rnd)\n\n if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\n if vximz_flag=1 then SetFX(FPSCR.VXIMZ)\n if vxisi_flag=1 then SetFX(FPSCR.VXISI)\n if ox_flag=1 then SetFX(FPSCR.OX)\n if ux_flag=1 then SetFX(FPSCR.UX)\n if xx_flag=1 then SetFX(FPSCR.XX)\n\n ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vximz_flag) | (FPSCR.VE & vxisi_flag) | (FPSCR.OE & ox_flag) | (FPSCR.UE & ux_flag) | (FPSCR.XE & xx_flag)\nend\n\nif ex_flag=0 then VSR[32×TX+T] ←vresult", "special_registers": "FPSCR, VXSNAN, VXIMZ, Vxisi, OX, UX, XX", "programming_notes": "This instruction is used for performing vectorized negative multiply-subtract operations on double-precision floating-point numbers. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. Be cautious of potential overflow and underflow conditions, as indicated by the exception flags. The operation processes two elements at a time, so ensure your data is correctly aligned for optimal performance.", "extended_mnemonics": [], "page_found": "Page 764 - 765", "example": "xvnmsubadp vs1, vs2, vs3" }, { "mnemonic": "xvnmsubasp", "architecture": "PowerISA", "full_name": "VSX Vector Negative Multiply-Subtract Type-A Single-Precision", "summary": "Performs a negative multiply-subtract operation on single-precision floating-point elements.", "description": "For xvnmsubasp, for each integer value i from 0 to 3, the following operations are performed: src1 is multiplied by src3, producing a product having unbounded range and precision. src2 is negated and added to the product, producing a sum having unbounded range and precision. The sum is normalized. The intermediate result is rounded to single-precision using the rounding mode specified by RN. The result is negated and placed into word element i of VSR[XT] in single-precision format.", "syntax": "xvnmsubasp XT,XA,XB", "operands": [ { "name": "XT", "desc": "Target Vector Register" }, { "name": "XA", "desc": "Source Vector Register" }, { "name": "XB", "desc": "Source Vector Register" } ], "encoding": { "format": "XX3-form", "hex_opcode": "0xF0000688", "length": "32", "binary_pattern": "60 | XT | XA | XB | 1672", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nex_flag ←0b0\ndo i = 0 to 3\n reset_xflags()\n src1 ←bfp_CONVERT_FROM_BFP32(VSR[32×AX+A].word[i])\n src2 ←bfp_CONVERT_FROM_BFP32(VSR[32×TX+T].word[i])\n src3 ←bfp_CONVERT_FROM_BFP32(VSR[32×BX+B].word[i])\n v ←bfp_MULTIPLY_ADD(src1,src3,bfp_NEGATE(src2))\n rnd ←bfp_NEGATE(bfp_ROUND_TO_BFP32(FPSCR.RN,v))\n vresult.word[i] ←bfp32_CONVERT_FROM_BFP(rnd)\n if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\n if vximz_flag=1 then SetFX(FPSCR.VXIMZ)\n if vxisi_flag=1 then SetFX(FPSCR.VXISI)\n if ox_flag=1 then SetFX(FPSCR.OX)\n if ux_flag=1 then SetFX(FPSCR.UX)\n if xx_flag=1 then SetFX(FPSCR.XX)\n ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vximz_flag) | (FPSCR.VE & vxisi_flag) | (FPSCR.OE & ox_flag) | (FPSCR.UE & ux_flag) | (FPSCR.XE & xx_flag)\nend\nif ex_flag=0 then VSR[32×TX+T] ←vresult", "special_registers": "FPSCR, VXSNAN, VXIMZ, Vxisi, OX, UX, XX", "programming_notes": "This instruction performs a vectorized negative multiply-subtract operation on single-precision floating-point numbers. Ensure that the VSX feature is enabled in the MSR register to avoid exceptions. Be cautious with rounding modes specified by FPSCR.RN, as they can affect precision and performance. Handle exceptions properly by checking the VXSNAN, VXIMZ, Vxisi, OX, UX, and XX flags after execution.", "extended_mnemonics": [], "page_found": "Page 767 - 768", "example": "xvnmsubasp vs1, vs2, vs3" }, { "mnemonic": "xvredp", "architecture": "PowerISA", "full_name": "Vector Reciprocal Estimate Double-Precision", "summary": "A double-precision floating-point estimate of the reciprocal of src is placed into doubleword element i of VSR[XT] in double-precision format.", "description": "Unless the reciprocal of src would be a zero, an infinity, or a QNaN, the estimate has a relative error in precision no greater than one part in 16384 of the reciprocal of src.", "syntax": "xvredp XT,XB", "operands": [ { "name": "XT", "desc": "Target Vector Register" }, { "name": "XB", "desc": "Source Vector Register" } ], "encoding": { "format": "XX2-form", "hex_opcode": "0xF0000368", "length": "32", "binary_pattern": "0 | 6 | 11 | 16 | 21 | 26 | 30 | 31", "bit_positions": "0 | 6 | 11 | 16 | 21 | 26 | 30 | 31" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\n\nreset_xflags()\nvresult = bfp_RECIPROCAL_ESTIMATE(VSR[32×BX+B].dword[i])\nrnd = bfp_ROUND_TO_BFP64(0b0, FPSCR.RN, vresult)\nvresult.word[i] = bfp64_CONVERT_FROM_BFP(rnd)\n\nif vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\nif ox_flag=1 then SetFX(FPSCR.OX)\nif ux_flag=1 then SetFX(FPSCR.UX)\nif zx_flag=1 then SetFX(FPSCR.ZX)\nex_flag = ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.OE & ox_flag) | (FPSCR.UE & ux_flag) | (FPSCR.ZE & zx_flag)\n\nif ex_flag=0 then VSR[32×TX+T] ←vresult", "special_registers": "FPSCR FX OX UX ZX VXSNAN", "programming_notes": "The xvredp instruction is used to estimate the reciprocal of a double-precision floating-point number with high precision. It's important to ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register, otherwise, an exception will be raised. Developers should also handle exceptions by checking the FPSCR flags for overflow (OX), underflow (UX), zero divide (ZX), and invalid operation (VXSNAN).", "extended_mnemonics": [], "page_found": "Page 770 - 771", "example": "xvredp vs1, vs3" }, { "mnemonic": "xvresp", "architecture": "PowerISA", "full_name": "Vector Reciprocal Estimate Single-Precision", "summary": "Estimates the reciprocal of single-precision floating-point values in a vector.", "description": "A single-precision floating-point estimate of the reciprocal of src is placed into word element i of VSR[XT] in single-precision format. Unless the reciprocal of src would be a zero, an infinity, or a QNaN, the estimate has a relative error in precision no greater than one part in 16384 of the reciprocal of src.", "syntax": "xvresp XT,XB", "operands": [ { "name": "XT", "desc": "Target Vector Register" }, { "name": "XB", "desc": "Source Vector Register" } ], "encoding": { "format": "XX2-form", "hex_opcode": "0xF0000268", "length": "32", "binary_pattern": "T | B | BX | TX", "bit_positions": "0:10 | 11:15 | 16:20 | 21:31" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nex_flag ←0b0\nreset_xflags()\ndo i = 0 to 3\n src ←bfp_CONVERT_FROM_BFP32(VSR[32×BX+B].word[i])\n rnd ←bfp_ROUND_TO_BFP32(FPSCR.RN,v)\n vresult.word[i] ←bfp32_CONVERT_FROM_BFP(rnd)\n if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\n if ox_flag=1 then SetFX(FPSCR.OX)\n if ux_flag=1 then SetFX(FPSCR.UX)\n if zx_flag=1 then SetFX(FPSCR.ZX)\n ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.OE & ox_flag) | (FPSCR.UE & ux_flag) | (FPSCR.ZE & zx_flag)\nend\nif ex_flag=0 then VSR[32×TX+T] ←vresult", "special_registers": "FPSCR FX OX UX ZX VXSNAN", "programming_notes": "The xvresp instruction is used to estimate the reciprocal of single-precision floating-point numbers in vector registers. It's important to ensure that the VSX (Vector Scalar Extensions) are enabled, as attempting to use this instruction when they are not will result in an exception. The instruction handles NaNs and infinities by setting appropriate flags in the FPSCR register, but developers should be cautious of potential precision loss due to the estimation process.", "extended_mnemonics": [], "page_found": "Page 771 - 772", "example": "xvresp vs1, vs3" }, { "mnemonic": "xvrsqrtedp", "architecture": "PowerISA", "full_name": "Vector Reciprocal Square Root Estimate Double-Precision", "summary": "Estimates the reciprocal square root of double-precision floating-point values in vector registers.", "description": "This instruction estimates the reciprocal square root of each element in a double-precision floating-point vector and stores the result in another vector register. The estimate has a relative error no greater than one part in 16384 of the reciprocal of the square root of the source value.", "syntax": "xvrsqrtedp XT,XB", "operands": [ { "name": "XT", "desc": "Target Vector Register" }, { "name": "XB", "desc": "Source Vector Register" } ], "encoding": { "format": "XX2-form", "hex_opcode": "0xF0000328", "length": "32", "binary_pattern": "T | B | 202 | BX | TX", "bit_positions": "6 | 11 | 16 | 21 | 30 31" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\n\nex_flag ←0b0\n\ndo i = 0 to 1\n reset_xflags()\n src ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])\n v ←bfp_RECIPROCAL_SQUARE_ROOT_ESTIMATE(src)\n rnd ←bfp_ROUND_TO_BFP64(0b0,FPSCR.RN,v)\n vresult.dword[i] ←bfp64_CONVERT_FROM_BFP(rnd)\n if vxsqrt_flag=1 then SetFX(FPSCR.VXSQRT)\n if zx_flag=1 then SetFX(FPSCR.ZX)\n if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN) if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\nend\n\nif ex_flag=0 then VSR[32×TX+T] ←vresult", "special_registers": "FPSCR (FX, ZX, VXSNAN, VXSQRT)", "programming_notes": "The xvrsqrtedp instruction is used to estimate the reciprocal square root of each element in a double-precision floating-point vector. It requires VSX (Vector Scalar Extensions) to be enabled, otherwise, it will raise an exception. The result has a relative error no greater than one part in 16384. Be cautious with special values like NaNs or zeros, as they can trigger exceptions and set specific flags in the FPSCR register.", "extended_mnemonics": [], "page_found": "Page 772 - 773", "example": "xvrsqrtedp vs1, vs3" }, { "mnemonic": "xvrsqrtesp", "architecture": "PowerISA", "full_name": "VSX Vector Reciprocal Square Root Estimate Single-Precision", "summary": "Estimates the reciprocal square root of single-precision floating-point values in a vector.", "description": "The instruction estimates the reciprocal square root of each element in the source vector and stores the result in the target vector. The estimate has a relative error no greater than one part in 16384 of the reciprocal of the square root of the source value.", "syntax": "xvrsqrtesp XT,XB", "operands": [ { "name": "XT", "desc": "Target Vector Register" }, { "name": "XB", "desc": "Source Vector Register" } ], "encoding": { "format": "XX2-form", "hex_opcode": "0xF0000228", "length": "32", "binary_pattern": "18 | T | B | BX | TX", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\n\nex_flag ←0b0\n\ndo i = 0 to 3\n reset_xflags()\n src ←bfp_CONVERT_FROM_BFP32(VSR[32×BX+B].word[i])\n v ←bfp_RECIPROCAL_SQUARE_ROOT_ESTIMATE(src)\n rnd ←bfp_ROUND_TO_BFP32(FPSCR.RN,v)\n vresult.word[i] ←bfp32_CONVERT_FROM_BFP(rnd)\n if vxsqrt_flag=1 then SetFX(FPSCR.VXSQRT)\n if zx_flag=1 then SetFX(FPSCR.ZX)\nend\n\nif ex_flag=0 then VSR[32×TX+T] ←vresult", "special_registers": "FPSCR (FX, ZX, VXSNAN, VXSQRT)", "programming_notes": "The xvrsqrtesp instruction is commonly used for fast reciprocal square root estimation in single-precision floating-point operations. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking and setting the MSR.VSX bit. Be aware of potential exceptions such as VXSNAN or VXSQRT, which can be handled by examining the FPSCR register flags. The instruction operates on 4-element vectors, so ensure proper alignment and ordering of data for accurate results.", "extended_mnemonics": [], "page_found": "Page 773 - 774", "example": "xvrsqrtesp vs1, vs3" }, { "mnemonic": "xvtdivdp", "architecture": "PowerISA", "full_name": "Vector Test for software Divide Double-Precision", "summary": "Performs a double-precision floating-point division on vector elements and sets condition flags based on the results.", "description": "Tests whether a double-precision floating-point divide operation would be valid for each vector element and sets bits in the specified condition register field accordingly. This VSX instruction compares operands in XA and XB (two double-precision values per 128-bit register) against division validity conditions (divide-by-zero, invalid operands, etc.). The condition register field BF is set to reflect the test results; no other registers are modified.", "syntax": "xvtdivdp BF,XA,XB", "operands": [ { "name": "BF", "desc": "Condition Register Field" }, { "name": "XA", "desc": "Index for Source Vector Register A" }, { "name": "XB", "desc": "Index for Source Vector Register B" } ], "encoding": { "format": "XX3-form", "hex_opcode": "0xF00003E8", "length": "32", "binary_pattern": "18 | BF | XA | XB", "bit_positions": "0:5 | 6:15 | 16:20 | 21:31" }, "extension": "VSX", "pseudocode": "for i in 0 to 1 do\n quotient_valid ← test_divide_conditions(XA[i], XB[i])\n CR[BF] ← (quotient_valid, 0, 0, 0)\nend for", "special_registers": "CR field BF", "programming_notes": "The xvtdivdp instruction is used for performing double-precision floating-point division on vector elements. It sets condition flags based on the results, which can be useful for error checking and conditional operations. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. Be cautious of division by zero and other special cases like NaNs or infinities, as these will set specific condition flags.", "extended_mnemonics": [], "page_found": "Page 774 - 775", "example": "xvtdivdp cr0, vs2, vs3" }, { "mnemonic": "xvtdivsp", "architecture": "PowerISA", "full_name": "VSX Vector Test for software Divide Single-Precision XX3-form", "summary": "Performs a vectorized single-precision floating-point division test.", "description": "Tests whether a single-precision floating-point divide operation would be valid for each vector element and sets the specified condition register field based on the results. This VSX instruction examines operands in XA and XB (four single-precision values per 128-bit register) for division validity conditions such as divide-by-zero or invalid operands. The condition register field BF is updated to reflect test outcomes; no other state is modified.", "syntax": "xvtdivsp BF,XA,XB", "operands": [ { "name": "BF", "desc": "Condition Register Field" }, { "name": "XA", "desc": "Index for Source VSX Register A" }, { "name": "XB", "desc": "Index for Source VSX Register B" } ], "encoding": { "format": "XX3-form", "hex_opcode": "0xF00002E8", "length": "32", "binary_pattern": "18 | BF | XA | XB", "bit_positions": "0:5 | 6:15 | 16:20 | 21:31" }, "extension": "VSX", "pseudocode": "for i in 0 to 3 do\n quotient_valid ← test_divide_conditions(XA[i], XB[i])\n CR[BF] ← (quotient_valid, 0, 0, 0)\nend for", "special_registers": "CR field BF", "programming_notes": "The xvtdivsp instruction is used for vectorized single-precision floating-point division testing. It sets condition register flags based on the results of dividing elements from two VSX registers. Ensure that the VSX facility is enabled (MSR.VSX=1) before using this instruction. Be cautious with NaNs, infinities, and zero values in the operands, as they can trigger special flag conditions. The instruction operates on 4-element vectors, so ensure proper alignment of data in the VSX registers.", "extended_mnemonics": [], "page_found": "Page 775 - 776", "example": "xvtdivsp cr0, vs2, vs3" }, { "mnemonic": "xvtsqrtdp", "architecture": "PowerISA", "full_name": "Vector Test for software Square Root, Double-Precision", "summary": "Tests the double-precision floating-point operands in VSR[XB] and sets condition register field BF based on certain conditions.", "description": "This instruction tests each of the two double-precision floating-point elements in VSR[XB] and updates the condition register field BF accordingly. It checks for NaN, infinity, zero, negative values, and denormalized values, setting flags fe_flag and fg_flag based on these conditions.", "syntax": "xvtsqrtdp BF,XB", "operands": [ { "name": "BF", "desc": "Condition Register Field" }, { "name": "XB", "desc": "Vector-Scalar Register Index" } ], "encoding": { "format": "XX2-form", "hex_opcode": "0xF00003A8", "length": "32", "binary_pattern": "18 | BF | XB", "bit_positions": "0:5 | 6:8 | 9:31" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then\n VSX_Unavailable()\n\nfe_flag ←0b0\nfg_flag ←0b0\n\ndo i = 0 to 1\n src ←VSR[32×BX+B].dword[i]\n e_b ←src.bit[1:11] - 1023\n fe_flag ←fe_flag |\n IsNaN(src) | IsInf(src) |\n IsZero(src) | IsNeg(src) |\n (e_a <= -970)\n fg_flag ←fg_flag |\n IsInf(src) | IsZero(src) | IsDen(src)\nend\n\nfl_flag ←xvrsqrtedp_error() <= 2-14\nCR.field[BF] ←0b1 || fg_flag || fe_flag || 0b0", "special_registers": "CR", "programming_notes": "The xvtsqrtdp instruction is used to test double-precision floating-point elements for various conditions like NaN, infinity, zero, negative values, and denormalized values. It updates the condition register (CR) with flags indicating these conditions. Ensure that VSX is enabled in the MSR before using this instruction; otherwise, a VSX_Unavailable exception will occur. The instruction does not require specific alignment for its operands.", "extended_mnemonics": [], "page_found": "Page 776 - 777", "example": "xvtsqrtdp cr0, vs3" }, { "mnemonic": "xvtsqrtsp", "architecture": "PowerISA", "full_name": "VSX Vector Test for software Square Root, Single-Precision", "summary": "Tests each element of a vector for conditions related to square root operations.", "description": "Tests whether a square root operation would be valid for each single-precision floating-point vector element and sets the specified condition register field accordingly. This VSX instruction examines the four single-precision values in XB against square root validity conditions (e.g., negative operands). The condition register field BF is set to reflect the test outcome; no other registers are modified.", "syntax": "xvtsqrtsp BF,XB", "operands": [ { "name": "BF", "desc": "Condition Register Field" }, { "name": "XB", "desc": "Vector-Scalar Register" } ], "encoding": { "format": "XX2-form", "hex_opcode": "0xF00002A8", "length": "32", "binary_pattern": "18 | BF | XB", "bit_positions": "0:5 | 6:8 | 9:31" }, "extension": "VSX", "pseudocode": "for i in 0 to 3 do\n sqrt_valid ← test_sqrt_conditions(XB[i])\n CR[BF] ← (sqrt_valid, 0, 0, 0)\nend for", "special_registers": "CR", "programming_notes": "The xvtsqrtsp instruction is used to test each element of a vector for NaN, infinity, zero, negative values, and underflow conditions. It sets the condition register based on these tests. Ensure that VSX is enabled in the MSR before using this instruction; otherwise, it will raise an exception. The instruction does not require specific alignment but must be executed at a privilege level where VSX is available.", "extended_mnemonics": [], "page_found": "Page 777 - 778", "example": "xvtsqrtsp cr0, vs3" }, { "mnemonic": "xscmpoqp", "architecture": "PowerISA", "full_name": "VSX Scalar Compare Ordered Quad-Precision", "summary": "Compares two quad-precision floating-point values and updates the condition register.", "description": "The instruction compares the contents of VSR[VRA+32] (src1) and VSR[VRB+32] (src2) represented in quad-precision format. The comparison results are stored in the CR field BF and FPSCR fields FL, FG, FE, and FU.", "syntax": "xscmpoqp BF,VRA,VRB", "operands": [ { "name": "BF", "desc": "Condition Register Field" }, { "name": "VRA", "desc": "Vector Register A" }, { "name": "VRB", "desc": "Vector Register B" }, { "name": "VRT", "desc": "Target Vector Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0xFC000108", "length": "32", "binary_pattern": "63 | BF | / | FRA | FRB | 132 | Rc", "bit_positions": "0:5 | 6:8 | 9:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nreset_xflags()\nsrc1 ←bfp_CONVERT_FROM_BFP128(VSR[VRA+32])\nsrc2 ←bfp_CONVERT_FROM_BFP128(VSR[VRB+32])\nif src1.class.SNaN=1 | src2.class.SNaN=1 then do\n vxsnan_flag ←0b1\n if FPSCR.VE=0 then vxvc_flag ←0b1\nend else\n vxvc_flag ←src1.class.QNaN | src2.class.QNaN\nif vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\nif vxvc_flag=1 then SetFX(FPSCR.VXVC)\nCR.bit[4×BF+32] ←FPSCR.FL ←src1 < src2\nCR.bit[4×BF+33] ←FPSCR.FG ←src1 > src2\nCR.bit[4×BF+34] ←FPSCR.FE ←src1 = src2\nCR.bit[4×BF+35] ←FPSCR.FU ←src1.class.SNaN | src1.class.QNaN | src2.class.SNaN | src2.class.QNaN", "special_registers": "CR, FPSCR, VXVC", "programming_notes": "This instruction is used for comparing two quad-precision floating-point numbers. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid an exception. Be cautious with NaN values, as they can trigger exceptions and set specific flags in FPSCR. The comparison results update both the CR field and FPSCR fields, so always check these registers after execution for proper handling of unordered comparisons or exceptions.", "extended_mnemonics": [], "page_found": "Page 780 - 781", "example": "xscmpoqp cr0, v2, v3" }, { "mnemonic": "xscmpeqdp", "architecture": "PowerISA", "full_name": "VSX Scalar Compare Equal Double-Precision", "summary": "Compares two double-precision floating-point values and sets the target vector register based on equality.", "description": "The instruction compares the double-precision floating-point values in the specified source vector registers. If either value is a SNaN, an Invalid Operation exception occurs. The result of the comparison is stored in the target vector register.", "syntax": "xscmpeqdp XT,XA,XB", "operands": [ { "name": "XT", "desc": "Target Vector Register" }, { "name": "XA", "desc": "Source Vector Register" }, { "name": "XB", "desc": "Source Vector Register" } ], "encoding": { "format": "XX3-form", "hex_opcode": "0xF0000018", "length": "32", "binary_pattern": "T | A | B | 3 | AX | BX | TX", "bit_positions": "6:10 | 11:15 | 16:20 | 21:28 | 29 | 30 | 31" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nsrc1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])\nsrc2 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])\nvxsnan_flag ←src1.class.SNaN | src2.class.SNaN\nvex_flag ←FPSCR.VE & vxsnan_flag\nif vxsnan_flag=1 SetFX(FPSCR.VXSNAN)\nif vex_flag=0 then do\n if src1=src2 then\n VSR[32×TX+T].dword[0] ←0xFFFF_FFFF_FFFF_FFFF\n VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000\n else do\n VSR[32×TX+T].dword[0] ←0x0000_0000_0000_0000\n VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000\n end\nend", "special_registers": "FPSCR (FX, VXSNAN)", "programming_notes": "xscmpeqdp can be used to implement the C/C++/Java conditional operation, RESULT = (x=y) ? a:b.\nxscmpeqdp fEQ,fX,fY\nxxsel fRESULT,fA,fB,fEQ", "extended_mnemonics": [], "page_found": "Page 784 - 785", "example": "xscmpeqdp vs1, vs2, vs3" }, { "mnemonic": "xscmpeqqp", "architecture": "PowerISA", "full_name": "VSX Scalar Compare Equal Quad-Precision X-form", "summary": "Compares two quad-precision floating-point values and sets the target vector register to all 1s if they are equal, otherwise all 0s.", "description": "The instruction compares the quad-precision floating-point values in VSR[VRA+32] and VSR[VRB+32]. If either value is a SNaN, an Invalid Operation exception occurs. The contents of VSR[VRT+32] are set to all 1s if the values are equal, otherwise all 0s.", "syntax": "xscmpeqqp VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0xFC000088", "length": "32", "binary_pattern": "0 | VRT | VRA | VRB", "bit_positions": "" }, "extension": "VSX", "pseudocode": "src1 ← bfp_CONVERT_FROM_BFP128(VSR[VRA+32])\nsrc2 ← bfp_CONVERT_FROM_BFP128(VSR[VRB+32])\nvxsnan_flag ← src1.class.SNaN | src2.class.SNaN\nvex_flag ← FPSCR.VE & vxsnan_flag\nif vxsnan_flag=1 SetFX(FPSCR.VXSNAN)\nif vex_flag=0 then do\n if bfp_COMPARE_EQ(src1, src2)=1 then\n VSR[VRT+32] ← 0xFFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF\n else\n VSR[VRT+32] ← 0x0000_0000_0000_0000_0000_0000_0000_0000", "special_registers": "FPSCR", "programming_notes": "xscmpeqqp can be used to implement the C/C++ conditional operation, RESULT = (x=y) ? a : b.\nxscmpeqqp vEQ,vX,vY\nxxsel vRESULT,vA,vB,vEQ", "extended_mnemonics": [], "page_found": "Page 785 - 786", "example": "xscmpeqqp v1, v2, v3" }, { "mnemonic": "xscmpgedp", "architecture": "PowerISA", "full_name": "VSX Scalar Compare Greater Than or Equal (Double-Precision)", "summary": "Compares two double-precision floating-point values and sets the target vector register based on the comparison result.", "description": "The instruction compares the double-precision floating-point value in doubleword 0 of VSR[XA] with the double-precision floating-point value in doubleword 0 of VSR[XB]. If the first value is greater than or equal to the second, it sets the target vector register's doubleword 0 to 0xFFFF_FFFF_FFFF_FFFF and doubleword 1 to 0x0000_0000_0000_0000. Otherwise, both doublewords are set to 0x0000_0000_0000_0000.", "syntax": "xscmpgedp XT,XA,XB", "operands": [ { "name": "XT", "desc": "Target Vector-Specific Register" }, { "name": "XA", "desc": "Source Vector-Specific Register" }, { "name": "XB", "desc": "Source Vector-Specific Register" } ], "encoding": { "format": "XX3-form", "hex_opcode": "0xF0000098", "length": "32", "binary_pattern": "19 | T | A | B | AX | BX | TX", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:30 | 31" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\n\nsrc1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])\nsrc2 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])\n\nif src1.class.SNaN=1 | src2.class.SNaN=1 then do\n vxsnan_flag ←0b1\n if FPSCR.VE=0 then vxvc_flag ←0b1\nend else\n vxvc_flag ←src1.class.QNaN | src2.class.QNaN\nvex_flag ←FPSCR.VE & (vxsnan_flag | vxvc_flag)\n\nif vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\nif vxvc_flag=1 then SetFX(FPSCR.VXVC)\n\nif vex_flag=0 then do\n if src1 >= src2 then\n VSR[32×TX+T].dword[0] ←0xFFFF_FFFF_FFFF_FFFF\n VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000\n end else do\n VSR[32×TX+T].dword[0] ←0x0000_0000_0000_0000\n VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000\n end\nend", "special_registers": "FPSCR (FX, VXSNAN, VXVC)", "programming_notes": "xscmpgedp can be used to implement the C/C++/Java conditional operation, RESULT = (x>=y) ? a : b.\nxscmpgedp fGE,fX,fY\nxxsel fRESULT,fA,fB,fGE\n\nxscmpgedp can also be used to implement the C/C++/Java conditional operation, RESULT = (x<=y) ? a : b.\nxscmpgedp fLE,fY,fX\nxxsel fRESULT,fA,fB,fLE", "extended_mnemonics": [], "page_found": "Page 786 - 787", "example": "xscmpgedp vs1, vs2, vs3" }, { "mnemonic": "xscmpgeqp", "architecture": "PowerISA", "full_name": "VSX Scalar Compare Greater Than or Equal Quad-Precision", "summary": "Compares two quad-precision floating-point values and sets the target register based on the comparison.", "description": "The instruction compares the quad-precision floating-point value in VSR[VRA+32] with the value in VSR[VRB+32]. If the first value is greater than or equal to the second, VSR[VRT+32] is set to all 1s; otherwise, it is set to all 0s. Special handling is provided for NaN and QNaN values.", "syntax": "xscmpgeqp VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector-Scalar Register" }, { "name": "VRA", "desc": "Source Vector-Scalar Register" }, { "name": "VRB", "desc": "Source Vector-Scalar Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0xFC000188", "length": "32", "binary_pattern": "18 | VRT | VRA | VRB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nsrc1 ←bfp_CONVERT_FROM_BFP128(VSR[VRA+32])\nsrc2 ←bfp_CONVERT_FROM_BFP128(VSR[VRB+32])\nif src1.class.SNaN=1 | src2.class.SNaN=1 then do\n vxsnan_flag ←0b1\n if FPSCR.VE=0 then vxvc_flag ←0b1\nend\nelse\n vxvc_flag ←src1.class.QNaN | src2.class.QNaN\nvex_flag ←FPSCR.VE & (vxsnan_flag | vxvc_flag)\nif vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\nif vxvc_flag=1 then SetFX(FPSCR.VXVC)\nif vex_flag=0 then do\n if bfp_COMPARE_GE(src1, src2)=1 then\n VSR[VRT+32] ← 0xFFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF\n else\n VSR[VRT+32] ← 0x0000_0000_0000_0000_0000_0000_0000_0000\nend", "special_registers": "FPSCR", "programming_notes": "xscmpgeqp can be used to implement the C/C++ conditional operation, RESULT = (x>=y) ? a : b.\nxscmpgeqp vGE,vX,vY\nxxsel vRESULT,vA,vB,vGE\nxscmpgeqp can also be used to implement the C/C++ conditional operation, RESULT = (x<=y) ? a : b.\nxscmpgeqp vLE,vY,vX\nxxsel vRESULT,vA,vB,vLE", "extended_mnemonics": [], "page_found": "Page 787 - 788", "example": "xscmpgeqp v1, v2, v3" }, { "mnemonic": "xscmpgtdp", "architecture": "PowerISA", "full_name": "VSX Scalar Compare Greater Than Double-Precision", "summary": "Compares two double-precision floating-point values and sets the target vector register based on the comparison.", "description": "Compares the double-precision floating-point value in the scalar portion of XA with that in XB and sets the corresponding elements in XT to all 1s (true) or all 0s (false) based on whether XA > XB. This VSX scalar instruction operates on the preferred slot (upper doubleword) of the registers. The comparison does not set condition registers but produces a vector result; quiet NaN operands compare as false without signaling.", "syntax": "xscmpgtdp XT,XA,XB", "operands": [ { "name": "XT", "desc": "Target Vector Register" }, { "name": "XA", "desc": "Source Vector Register" }, { "name": "XB", "desc": "Source Vector Register" } ], "encoding": { "format": "XX3-form", "hex_opcode": "0xF0000058", "length": "32", "binary_pattern": "T | A | B | AX | BX | TX", "bit_positions": "11:15 | 16:20 | 21:28 | 29 | 30 | 31" }, "extension": "VSX", "pseudocode": "if XA[0] > XB[0] then\n XT[0] ← 0xFFFFFFFFFFFFFFFF\nelse\n XT[0] ← 0x0000000000000000\nend if\nXT[1] ← undefined", "special_registers": "FPSCR (FX, VXSNAN, VXVC)", "programming_notes": "xscmpgtdp can be used to implement the C/C++/Java conditional operation, RESULT = (x>y) ? a : b.\nxscmpgtdp fGT,fX,fY\nxxsel fRESULT,fA,fB,fGT\nxscmpgtdp can also be used to implement the C/C++/Java conditional operation, RESULT = (xy) ? a : b.\nxscmpgtqp vGT,vX,vY\nxxsel vRESULT,vA,vB,vGT\nxscmpgtqp can also be used to implement the C/C++ conditional operation, RESULT = (x SI then CR[bF] <- 0b00000010\n else CR[bF] <- 0b00000100", "special_registers": "CR0, CR1-CR7", "programming_notes": "Use cmpdi to compare a register with an immediate value and set the condition register field accordingly. Ensure the immediate value fits within the signed 16-bit range. The comparison result is used in conditional branches, so check CR Field BF after execution.", "extended_mnemonics": [ "cmpdi" ], "page_found": "Page 994 - 995", "example": "cmpdi bf, ra, si" }, { "mnemonic": "extldi", "architecture": "PowerISA", "full_name": "Extract and Left Justify Immediate", "summary": "Extracts a field of n bits starting at bit position b in the source register, left justifies this field in the target register, and clears all other bits of the target register to 0.", "description": "For extldi, the field of n bits starting at bit position b in the source register is extracted, left justified in the target register, and all other bits are cleared to 0.", "syntax": "extldi ra,rs,n,b (n > 0)", "operands": [ { "name": "ra", "desc": "Target General Purpose Register" }, { "name": "rs", "desc": "Source General Purpose Register" }, { "name": "n", "desc": "Number of bits to extract" }, { "name": "b", "desc": "Starting bit position" } ], "encoding": { "format": "XO-form", "hex_opcode": "0x78000004", "length": "32", "binary_pattern": "18 | LI | AA | LK", "bit_positions": "0:5 | 6:29 | 30 | 31" }, "extension": "Base", "pseudocode": "if 'extldi' then\n ra <- (rs >> b) & ((1 << n) - 1)", "special_registers": "N/A", "programming_notes": "Use extldi to extract a specific bit field from a source register, left-justifying it in the target register. Ensure that the bit position and length are correctly specified to avoid data corruption. This instruction operates at user privilege level.", "extended_mnemonics": [], "page_found": "Page 997 - 998", "example": "extldi ra, rs, n, b (n > 0)" }, { "mnemonic": "extlwi", "architecture": "PowerISA", "full_name": "Extract and Left Justify Immediate", "summary": "Extracts a specified number of bits from the source register, left-justifies them, and places them in the target register.", "description": "Extracts n bits starting at bit position b from GPR rs, left-justifies them in the target GPR ra, and zeros the remaining bits. This is a pseudo-instruction (alias) for rlwimi with specific parameters and operates in 32-bit mode. The instruction updates CR0 if the record bit (Rc) is set.", "syntax": "extlwi ra,rs,n,b (n > 0)", "operands": [ { "name": "ra", "desc": "Target General Purpose Register" }, { "name": "rs", "desc": "Source General Purpose Register" }, { "name": "n", "desc": "Number of bits to extract (must be greater than 0)" }, { "name": "b", "desc": "Starting bit position for extraction" } ], "encoding": { "format": "XO-form", "hex_opcode": "0x54000000", "length": "32", "binary_pattern": "18 | LI | AA | LK", "bit_positions": "0:5 | 6:29 | 30 | 31" }, "extension": "Base", "pseudocode": "mask ← MASK(0, n-1)\nra ← (rs >> b) & mask\nra ← ra << (32 - n)\nif Rc then CR0 ← record_cr(ra) endif", "special_registers": "N/A", "programming_notes": "The extlwi instruction is useful for extracting a specific bit field from a source register and left-justifying it in the target register. Ensure that the bit positions 'b' and 'n' are correctly specified to avoid data corruption. The operation preserves or rotates the high-order bits of the target register, so be aware of this behavior if you need to maintain specific register contents.", "extended_mnemonics": [ "rlwinm" ], "page_found": "Page 998 - 999", "example": "extlwi ra, rs, n, b (n > 0)" }, { "mnemonic": "lwat", "architecture": "PowerISA", "full_name": "Load Word Atomic", "summary": "Loads a word from memory atomically.", "description": "Loads a 32-bit word from memory at an address computed from RA with atomic semantics determined by function code FC. The loaded value is placed in GPR RT. This instruction requires alignment and may be restricted to hypervisor mode depending on FC value.", "syntax": "lwat RT,RA,FC", "operands": [ { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "FC", "desc": "Function Code" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C00048C", "length": "32", "binary_pattern": "18 | LI | AA | LK", "bit_positions": "0:5 | 6:29 | 30 | 31" }, "extension": "Base", "pseudocode": "EA ← RA\nRT ← [EA]\n# Atomic load with fence behavior determined by FC", "special_registers": "N/A", "programming_notes": "EA must be a multiple of 4, and the portion of mem(EA-4,12) accessed by the instruction must be contained within an aligned 32-byte block of storage. If either of these requirements is not satisfied, the system alignment error handler is invoked.", "extended_mnemonics": [], "page_found": "Page 1046 - 1047", "example": "lwat r3, r4, fc" }, { "mnemonic": "stwat", "architecture": "PowerISA", "full_name": "Store Word Atomic", "summary": "Stores a word atomically to memory.", "description": "Stores a 32-bit word from GPR RS to memory at an address in RA with atomic semantics specified by function code FC. The store is performed atomically with fence behavior determined by FC. Alignment requirements and potential privilege restrictions apply.", "syntax": "stwat RS,RA,FC", "operands": [ { "name": "RS", "desc": "Source General Purpose Register" }, { "name": "RA", "desc": "Address General Purpose Register" }, { "name": "FC", "desc": "Function Code" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C00058C", "length": "32", "binary_pattern": "0 | RS | RA | FC", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "Base", "pseudocode": "EA ← RA\n[EA] ← RS\n# Atomic store with fence behavior determined by FC", "special_registers": "N/A", "programming_notes": "The stwat instruction atomically updates a word in memory at the address specified by register RA. Ensure that RA is properly aligned to avoid exceptions. The function code FC determines the specific update operation; consult the ISA documentation for valid operations. This instruction operates at user privilege level and does not generate any exceptions under normal conditions.", "extended_mnemonics": [], "page_found": "Page 1048 - 1049", "example": "stwat r3, r4, fc" }, { "mnemonic": "brd", "architecture": "PowerISA", "full_name": "Byte-Reverse Doubleword", "summary": "Reverses the bytes in a doubleword.", "description": "Reverses the byte order of a 64-bit doubleword from the source register and places the result in the target register. This instruction operates at the architectural level to perform a complete byte reversal (byte 0 ↔ byte 7, byte 1 ↔ byte 6, etc.). No status fields are affected. This is a Base category instruction with no privilege requirements.", "syntax": "brd RT,RA", "operands": [ { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RA", "desc": "Source General Purpose Register" } ], "encoding": { "format": "XO-form", "hex_opcode": "0x7C000176", "length": "32", "binary_pattern": "18 | LI | AA | LK", "bit_positions": "0:5 | 6:29 | 30 | 31" }, "extension": "Base", "pseudocode": "RT ← BYTESWAP64(RA)", "special_registers": "", "programming_notes": "The brd instruction is useful for reversing the byte order of a doubleword in a register, which can be necessary for data format conversion between big-endian and little-endian systems. Ensure that the source register (RA) contains a valid doubleword value to avoid undefined behavior. This operation does not require any special privileges or alignment considerations.", "extended_mnemonics": [], "page_found": "Page 1099 - 1100", "example": "brd r3, r4" }, { "mnemonic": "vclzdm", "architecture": "PowerISA", "full_name": "Vector Count Leading Zeros Doubleword under bit Mask", "summary": "Counts the number of leading zeros in each doubleword element of a vector, considering a mask.", "description": "Counts the number of leading zero bits in each doubleword element of the source vector, using a bit mask from a second source vector to selectively apply the count operation. The results are placed in the target vector as doubleword elements. This is a VMX (AltiVec) category instruction that does not affect condition register or status fields.", "syntax": "vclzdm VRT, VRA, VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0x10000784", "length": "32", "binary_pattern": "18 | LI | AA | LK", "bit_positions": "0:5 | 6:29 | 30 | 31" }, "extension": "VMX (AltiVec)", "pseudocode": "for i in 0 to 1 do\n if VRB[i*64:(i+1)*64] != 0 then\n VRT[i*64:(i+1)*64] ← LEADING_ZEROS(VRA[i*64:(i+1)*64])\n else\n VRT[i*64:(i+1)*64] ← 0\nend for", "special_registers": "N/A", "programming_notes": "Use vclzdm to efficiently count leading zeros in masked bit positions within doublewords. Ensure that VRB contains a valid mask where 1s indicate bits to be considered for zero counting. This instruction operates at user privilege level and does not generate exceptions under normal conditions.", "extended_mnemonics": [], "page_found": "Page 1100 - 1101", "example": "vclzdm v1, v2, v3" }, { "mnemonic": "lbzcix", "architecture": "PowerISA", "full_name": "Load Byte and Zero Caching Inhibited Indexed", "summary": "Loads a byte from memory into a register, zeroing the upper bits of the target register.", "description": "The effective address (EA) is calculated as the sum of RA and RB. The byte at EA is loaded into RT56:63, while RT0:55 are set to 0. The storage access is performed as though the location is Caching Inhibited and Guarded.", "syntax": "lbzcix RT,RA,RB", "operands": [ { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "RB", "desc": "Source General Purpose Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C0006AA", "length": "32", "binary_pattern": "0 | RT | RA | RB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "Base", "pseudocode": "if RA = 0 then\n b ← 0\nelse\n b ← (RA)\nEA ← b + (RB)\nRT ← 560 || MEM(EA, 1)", "special_registers": "N/A", "programming_notes": "The lbzcix instruction is useful for loading a single byte from memory into the upper bits of a register while zeroing out the lower bits. It ensures that the access is treated as caching inhibited and guarded, which can be crucial for accessing special memory regions. Be cautious with RA being zero, as it results in an effective address equal to RB, potentially leading to unintended memory accesses if not handled properly.", "extended_mnemonics": [], "page_found": "Page 1132 - 1133", "example": "lbzcix r3, r4, r5" }, { "mnemonic": "stbcix", "architecture": "PowerISA", "full_name": "Store Byte Caching Inhibited Indexed X-form", "summary": "Stores a byte from a register to memory with caching inhibited and guarded.", "description": "The instruction stores the byte (RS)56:63 into the memory location addressed by the effective address (EA), which is calculated as the sum of RA and RB. The storage access is performed as though the specified storage location is Caching Inhibited and Guarded.", "syntax": "stbcix RS,RA,RB", "operands": [ { "name": "RS", "desc": "Source General Purpose Register" }, { "name": "RA", "desc": "Base Address General Purpose Register" }, { "name": "RB", "desc": "Index General Purpose Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C0007AA", "length": "32", "binary_pattern": "0 | RS | RA | RB", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "Base", "pseudocode": "if RA = 0 then\n b ← 0\nelse\n b ← (RA)\nEA ← b + (RB)\nMEM(EA, 1) ← (RS)56:63", "special_registers": "N/A", "programming_notes": "This instruction is hypervisor privileged.", "extended_mnemonics": [], "page_found": "Page 1133 - 1134", "example": "stbcix r3, r4, r5" }, { "mnemonic": "slbieg", "architecture": "PowerISA", "full_name": "SLB Invalidate Entry Global", "summary": "Invalidates SLB entries based on the contents of registers RS and RB.", "description": "Invalidates one or more entries in the Segment Lookaside Buffer (SLB) based on the effective address class and segment size specified in RB and the process ID specified in RS, with global scope affecting all processors. This is a privileged instruction (Hypervisor-level) that requires supervisor privileges and does not affect condition register or status fields. It is used for SLB maintenance in virtual memory operations.", "syntax": "slbieg RS,RB", "operands": [ { "name": "RS", "desc": "Source General Purpose Register containing the target PID (and optionally the target LPID)" }, { "name": "RB", "desc": "Source General Purpose Register containing the EA, class, and segment size" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C0003A4", "length": "32", "binary_pattern": "0 | RS | RB | 466", "bit_positions": "" }, "extension": "Base", "pseudocode": "for each SLB entry matching (RS and RB parameters) do\n INVALIDATE_SLB_ENTRY(entry)\nend for", "special_registers": "LR,CTR,CR,FPSCR,XER,MSR,SRR0,SRR1,TAR,SPR,DSISR,DAR,HMER", "programming_notes": "slbieg does affect SLBs on other threads.", "extended_mnemonics": [], "page_found": "Page 1197 - 1198", "example": "slbieg r3, r5" }, { "mnemonic": "slbiag", "architecture": "PowerISA", "full_name": "SLB Invalidate All Global", "summary": "Invalidates all SLBs for a specified LPID and PID.", "description": "The instruction invalidates all SLB entries for the target LPID and PID. If L=0, the target PID is taken from RS0:31. If executed in hypervisor state, the target LPID is taken from RS32:63; otherwise, it is taken from LPIDR.", "syntax": "slbiag RS,L", "operands": [ { "name": "RS", "desc": "Source General Purpose Register" }, { "name": "L", "desc": "Logical flag (0 or 1)" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C0006A4", "length": "32", "binary_pattern": "0 | RS | L | 0", "bit_positions": "0:5 | 6:10 | 11:14 | 15:31" }, "extension": "Base", "pseudocode": "if 'slbiag' then\n if L=0 then target_PID = RS0:31\n if MSRHV=1 then target_LPID = RS32:63\n else target_LPID = LPIDR\n for each nest SLB\n for each SLBE with LPID=target_LPID and (PID=target_PID | L=1)\n SLBEV ←0\n all other fields of SLBE ←undefined", "special_registers": "LPIDR", "programming_notes": "slbiag does not affect SLBs on processor threads. slbiag serves as both a basic and an extended mnemonic. The Assembler will recognize an slbiag mnemonic with two operands as the basic form, and an slbiag mnemonic with one operand as the extended form. In the extended form the L operand is omitted and assumed to be 0.", "extended_mnemonics": [ "slbiag RS,0" ], "page_found": "Page 1202 - 1203", "example": "slbiag r3, 0" }, { "mnemonic": "slbfee.", "architecture": "PowerISA", "full_name": "SLB Find Entry ESID", "summary": "Searches the SLB for an entry that matches the effective address specified by register RB.", "description": "The SLB is searched for an entry that matches the effective address specified by register RB. If exactly one matching entry is found, the contents of the B, VSID, Ks, Kp, N, L, C, and LP fields of the entry are placed into register RT. If no matching entry is found, register RT is set to 0. If more than one matching entry is found, either one of the matching entries is used, or a Machine Check occurs.", "syntax": "slbfee. RT,RB", "operands": [ { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RB", "desc": "Source General Purpose Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C0007A7", "length": "32", "binary_pattern": "0 | RT | RB | 18 | 1", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "Base", "pseudocode": "if LPCRUPRT=1 then\n // Instruction is nonfunctional\nelse\n search SLB for entry matching (RB)0:63-s\n if exactly one match found then\n RT <- B | VSID | KsKpNLC | LP\n else if no match found then\n RT <- 0\n else\n // More than one match, Machine Check occurs\nend", "special_registers": "CR0, XER", "programming_notes": "The contents of registers RT and RB are interpreted as shown below.\nRT0:1 B\nRT2:51 VSID\nRT52 Ks\nRT53 Kp\nRT54 N\nRT55 L\nRT56 C\nRT57 set to 0b0\nRT58:59 LP\nRT60:63 set to 0b0000\nRB0:35 ESID\nRB36:39 must be 0b0000\nRB40:63 must be 0x000000\nIf s > 28, RT80-s:51 are set to zeros. On implementations that support a virtual address size of only n bits, n < 78, RT2:79-n are set to zeros.\nCR Field 0 is set as follows. j is a 1-bit value that is equal to 0b1 if a matching entry was found. Otherwise, j is 0b0. When LPCRUPRT̸=0, j=0b0.\nCR0LT GT EQ SO = 0b00 || j || XERSO", "extended_mnemonics": [], "page_found": "Page 1205 - 1206", "example": "slbfee. r3, r5" }, { "mnemonic": "msgsndu", "architecture": "PowerISA", "full_name": "Message Send Ultravisor", "summary": "Sends a message to other threads in the system.", "description": "The instruction sends a message to other threads in the system. The message type and destination thread(s) are specified in RB.", "syntax": "msgsndu RB", "operands": [ { "name": "RB", "desc": "Source General Purpose Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C00009C", "length": "32", "binary_pattern": "18 | LI | AA | LK", "bit_positions": "0:5 | 6:29 | 30 | 31" }, "extension": "Privileged", "pseudocode": "msgtype ← GPR(RB)32:36\npayload ← GPR(RB)37:63\nif (msgtype = 0x05)\nthen\n send_msg(msgtype, payload)", "special_registers": "", "programming_notes": "If msgsndu is used to notify the receiver that updates have been made to storage, a sync should be placed between the stores and the msgsndu. See Section 6.9.2.", "extended_mnemonics": [], "page_found": "Page 1309 - 1310", "example": "msgsndu r5" }, { "mnemonic": "mtvsrbmi", "architecture": "PowerISA", "full_name": "Move to Vector Scalar Register with Bit Mask Immediate", "summary": "Moves a bit mask immediate value into a vector scalar register, setting each byte element based on corresponding bits of the immediate.", "description": "Moves an 8-bit immediate value into a VSR (Vector Scalar Register) with each bit of the immediate controlling whether the corresponding byte element is set to all-ones (0xFF) or all-zeros (0x00). This is a Base category instruction that does not affect condition register or other status fields. The instruction provides a quick way to create byte-level masks in vector registers.", "syntax": "mtvsrbmi VRT,bm", "operands": [ { "name": "VRT", "type": "VSR", "desc": "Target vector scalar register that receives the byte mask pattern generated from the immediate value." }, { "name": "IMM8", "type": "imm8", "desc": "8-bit immediate value where each bit controls the corresponding byte element (1 = 0xFF, 0 = 0x00)." } ], "encoding": { "format": "XO-form", "hex_opcode": "0x10000014", "length": "32", "binary_pattern": "4 | VRT | b1 | b0 | 10 | b2", "bit_positions": "0:5 | 6:10 | 11:15 | 16:25 | 26:30 | 31" }, "extension": "Base", "pseudocode": "for i in 0 to 7 do\n if IMM[i] = 1 then\n VSR_target[i*8:(i+1)*8] ← 0xFF\n else\n VSR_target[i*8:(i+1)*8] ← 0x00\nend for", "special_registers": "N/A", "programming_notes": "The mtvsrbmi instruction is useful for initializing vector registers with specific byte patterns based on an immediate bit mask. Ensure that the immediate value correctly reflects the desired byte-wise initialization to avoid unexpected results. This instruction operates at user privilege level and does not raise exceptions under normal conditions.", "extended_mnemonics": [], "page_found": "Page 1329 - 1330", "example": "mtvsrbmi vs1, 0, 0xFF" }, { "mnemonic": "subfc.", "architecture": "PowerISA", "full_name": "Subtract from Complement with Carry-Out", "summary": "Subtracts the contents of one register from the complement of another and updates the carry-out flag.", "description": "For subfc., the complement of the contents of register RB is subtracted from the contents of register RA, and the result is placed into register RT. The carry-out flag is updated based on the operation.", "syntax": "subfc. RT,RA,RB", "operands": [ { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "RB", "desc": "Source General Purpose Register" } ], "encoding": { "format": "XO-form", "hex_opcode": "0x7C000010", "length": "32", "binary_pattern": "01000 | LI | AA | LK", "bit_positions": "0:5 | 6:29 | 30 | 31" }, "extension": "Base", "pseudocode": "if 'subfc.' then\n RT <- (RA) - (~RB)\n XER.CA <- carry-out", "special_registers": "CR0, XER", "programming_notes": "Use subfc. to subtract the bitwise complement of one register from another, updating the carry-out flag in XER.CA. Ensure registers are properly aligned and consider the effect on CR0 for conditional branching.", "extended_mnemonics": [], "page_found": "Page 1342 - 1343", "example": "subfc. r3, r4, r5" }, { "mnemonic": "slw.", "architecture": "PowerISA", "full_name": "Shift Left Word Immediate", "summary": "Shifts the contents of a register left by a specified number of bits and updates the condition register.", "description": "For slw., the contents of register RA are shifted left by the amount specified in RB, and the result is placed into register RT. The shift count is masked to 5 bits.", "syntax": "slw. RT,RA,RB", "operands": [ { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "RB", "desc": "Shift Count (0-31)" } ], "encoding": { "format": "XO-form", "hex_opcode": "0x7C000030", "length": "32", "binary_pattern": "18 | LI | AA | LK", "bit_positions": "0:5 | 6:29 | 30 | 31" }, "extension": "Base", "pseudocode": "if 'slw.' then\n RT <- (RA) << ((RB) & 31)", "special_registers": "CR0, XER", "programming_notes": "The slw instruction shifts the contents of RA left by a number of bits specified in RB, with the shift count masked to 5 bits. This operation is useful for bit manipulation tasks but be cautious as shifting large values can lead to overflow. The result is stored in RT, and this instruction operates at user privilege level.", "extended_mnemonics": [], "page_found": "Page 1344 - 1345", "example": "slw. r3, r4, r5" }, { "mnemonic": "dadd.", "architecture": "PowerISA", "full_name": "Double Precision Add Record", "summary": "Adds the contents of two double precision floating-point registers and updates the condition register.", "description": "Adds two double-precision decimal floating-point operands and places the result in the target register, then updates CR1 based on the result, exception status, and FPSCR flags. This instruction requires the Decimal Floating-Point (DFP) category and updates FPSCR condition bits and CR1 field based on the result classification and exception conditions.", "syntax": "dadd. FRD,FRB,FRC", "operands": [ { "name": "FRD", "desc": "Target Double Precision Floating-Point Register" }, { "name": "FRB", "desc": "Source Double Precision Floating-Point Register" }, { "name": "FRC", "desc": "Source Double Precision Floating-Point Register" } ], "encoding": { "format": "XO-form", "hex_opcode": "0xEC000004", "length": "32", "binary_pattern": "18 | LI | AA | LK", "bit_positions": "0:5 | 6:29 | 30 | 31" }, "extension": "Base", "pseudocode": "FRD ← FRB + FRC\nCR1 ← FPSCR[FPRF]\nFPSCR[exception bits] ← updated based on result", "special_registers": "CR0, XER", "programming_notes": "The dadd. instruction is used for adding two double-precision decimal floating-point numbers. It updates Condition Register Field 1 to indicate the result, which can be useful for conditional operations. Ensure that the input registers contain valid decimal floating-point values to avoid undefined behavior.", "extended_mnemonics": [], "page_found": "Page 1345 - 1346", "example": "dadd. f5, f3, f4" }, { "mnemonic": "fdivs", "architecture": "PowerISA", "full_name": "Floating Point Divide Single Precision", "summary": "Divides the contents of two single precision floating point registers.", "description": "For fdivs, the value in register FRB is divided by the value in register FRA, and the result is placed into register FRT.", "syntax": "fdivs FRT,FRA,FRB", "operands": [ { "name": "FRT", "desc": "Target Floating Point Register" }, { "name": "FRA", "desc": "Source Floating Point Register" }, { "name": "FRB", "desc": "Source Floating Point Register" } ], "encoding": { "format": "XO-form", "hex_opcode": "0xEC000024", "length": "32", "binary_pattern": "18 | LI | AA | LK", "bit_positions": "0:5 | 6:29 | 30 | 31" }, "extension": "Floating-Point", "pseudocode": "FRT <- (FRA) / (FRB)", "special_registers": "FPSCR", "programming_notes": "The fdivs instruction performs a single-precision floating-point division. Ensure that neither operand is zero to avoid division by zero exceptions. The FPSCR register may be updated with status flags such as overflow or underflow. This operation can raise exceptions if the result overflows, underflows, or is invalid (e.g., NaN).", "extended_mnemonics": [], "page_found": "Page 1347 - 1348", "example": "fdivs f1, f2, f3" }, { "mnemonic": "fcpsgn.", "architecture": "PowerISA", "full_name": "Copy Sign", "summary": "Copies the sign of one floating-point number to another.", "description": "The fcpsgn. instruction copies the sign bit from the source operand B to the target operand A and places the result in the destination operand C.", "syntax": "fcpsgn. FRT,FRB,FRA", "operands": [ { "name": "FRT", "desc": "Target Floating-Point Register" }, { "name": "FRB", "desc": "Source Floating-Point Register (sign source)" }, { "name": "FRA", "desc": "Source Floating-Point Register (magnitude source)" }, { "name": "RT", "desc": "Target Floating-Point Register" }, { "name": "RB", "desc": "Source Floating-Point Register (sign source)" }, { "name": "RA", "desc": "Source Floating-Point Register (magnitude source)" } ], "encoding": { "format": "X-form", "hex_opcode": "0xFC000010", "length": "32", "binary_pattern": "18 | LI | AA | LK", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "Floating-Point", "pseudocode": "if 'fcpsgn.' then\n RT <- (RA) with sign of (RB)", "special_registers": "N/A", "programming_notes": "The fcpsgn. instruction is useful for manipulating the sign of floating-point numbers without changing their magnitude. Ensure that operands A and B are properly aligned in memory to avoid alignment faults. This operation does not require any special privileges and will not generate exceptions under normal circumstances.", "extended_mnemonics": [], "page_found": "Page 1354 - 1355", "example": "fcpsgn. f1, f3, f2" }, { "mnemonic": "fdiv.", "architecture": "PowerISA", "full_name": "Floating Point Divide Record", "summary": "Divides the contents of two floating-point registers and updates the condition register.", "description": "For fdiv., the quotient of the contents of register FA and FB is placed into register FC.", "syntax": "fdiv. FC,FA,FB", "operands": [ { "name": "FC", "desc": "Target Floating Point Register" }, { "name": "FA", "desc": "Source Floating Point Register" }, { "name": "FB", "desc": "Source Floating Point Register" } ], "encoding": { "format": "XO-form", "hex_opcode": "0xFC000024", "length": "32", "binary_pattern": "18 | LI | AA | LK", "bit_positions": "0:5 | 6:29 | 30 | 31" }, "extension": "Floating-Point", "pseudocode": "if 'fdiv.' then\n FC <- (FA) / (FB)", "special_registers": "CR0, FPSCR", "programming_notes": "The fdiv. instruction performs a floating-point division, storing the result in register FC. Ensure that registers FA and FB are properly initialized to avoid undefined behavior. This operation may raise exceptions if FB is zero or if there are overflow/underflow conditions; check FPSCR for exception flags after execution.", "extended_mnemonics": [], "page_found": "Page 1355 - 1356", "example": "fdiv. fc, fa, fb" }, { "mnemonic": "fre.", "architecture": "PowerISA", "full_name": "Reciprocal Estimate", "summary": "Estimates the reciprocal of a floating-point number.", "description": "The fre. instruction estimates the reciprocal of the contents of register RA and places the result into register RT.", "syntax": "fre. FRT,FRB", "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" } ], "encoding": { "format": "A-form", "binary_pattern": "63 | FRT | 0 | 0 | FRB | 24 | /", "hex_opcode": "0xFC000030", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "24", "clean": "24" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:30 | 31" }, "extension": "Floating-Point", "pseudocode": "if 'fre.' then\n RT <- estimate_reciprocal(RA)", "special_registers": "N/A", "programming_notes": "The fre. instruction provides a fast, approximate reciprocal value, useful for performance-critical applications like graphics or scientific computing where precision can be traded for speed. Ensure that the input register RA contains a non-zero value to avoid undefined behavior; otherwise, consider adding checks to handle zero inputs gracefully.", "extended_mnemonics": [], "page_found": "Page 200 - 202", "example": "fre. r3, r4" }, { "mnemonic": "dcffixqq", "architecture": "PowerISA", "full_name": "Double-Precision Floating-Point Fix to Quadword", "summary": "Converts a double-precision floating-point value to a quadword integer.", "description": "Converts a double-precision decimal floating-point value to a 128-bit signed quadword integer, storing the result in a GPR pair or related register file location. This Floating-Point category instruction does not update condition registers but may set exception flags in FPSCR. The conversion uses the current rounding mode from FPSCR.", "syntax": "dcffixqq RT,RA", "operands": [ { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RA", "desc": "Source General Purpose Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0xFC0007C4", "length": "32", "binary_pattern": "18 | LI | AA | LK", "bit_positions": "0:5 | 6:29 | 30 | 31" }, "extension": "Floating-Point", "pseudocode": "RT ← CONVERT_DFP_TO_INT128(FRA, FPSCR[RN])", "special_registers": "FPSCR", "programming_notes": "The dcffixqq instruction is commonly used for converting double-precision floating-point numbers to integers, rounding towards zero. Ensure that the input value in RA is within the range representable by a quadword integer to avoid overflow or underflow exceptions. This instruction operates at user privilege level and does not require any specific ordering or alignment of registers.", "extended_mnemonics": [], "page_found": "Page 1361 - 1362", "example": "dcffixqq r3, r4" }, { "mnemonic": "vinshvrx", "architecture": "PowerISA", "full_name": "Vector Insert Halfword from VSR using GPR-specified Right-Index VX-form", "summary": "Inserts a halfword from a vector register into another vector register at a position specified by a general-purpose register.", "description": "Inserts a halfword-sized element from one vector register into another vector register at a byte position determined by the contents of a general-purpose register. This VMX (AltiVec) category instruction does not affect condition register or status fields. The GPR value specifies the insertion position within the destination vector.", "syntax": "vinshvrx VRT,RA,VRB", "operands": [ { "name": "VRT", "type": "VR", "desc": "Target vector register. Bits 48:63 of VSR[VRB+32] are placed into its byte elements 14-index:15-index." }, { "name": "RA", "type": "GPR", "desc": "General purpose register whose bits 60:63 supply the byte index, counted from the right end of the target." }, { "name": "VRB", "type": "VR", "desc": "Source vector register supplying the halfword held in its bits 48:63." } ], "encoding": { "format": "VX-form", "hex_opcode": "0x1000014F", "length": "32", "binary_pattern": "00101 001111", "bit_positions": "" }, "extension": "VMX (AltiVec)", "pseudocode": "index ← GPR[RA].bit[60:63]\nVSR[VRT+32].byte[14-index:15-index] ← VSR[VRB+32].bit[48:63]\nIf index is greater than 14, the result is undefined.", "special_registers": "N/A", "programming_notes": "The vinshvrx instruction is useful for selectively updating a halfword within a vector register based on a dynamic index provided by a general-purpose register. Ensure that the right-index specified in the GPR does not exceed the bounds of the 16-byte vector to avoid undefined behavior. This instruction operates at user privilege level and does not generate exceptions under normal circumstances, but incorrect indexing can lead to data corruption.", "extended_mnemonics": [], "page_found": "Page 1371 - 1372", "example": "vinshvrx" }, { "mnemonic": "creqv", "architecture": "PowerISA", "full_name": "Condition Register Equivalent", "summary": "Sets the condition register field to 1 if the corresponding fields of two source registers are equal, otherwise sets it to 0.", "description": "Performs a bitwise equivalence operation on two condition register fields and places the result in the target condition register field (setting the target bit to 1 if both source bits are equal, 0 otherwise). This Base category instruction operates entirely within the condition register and does not affect other status fields. It is commonly used in conditional branch logic and CR field manipulation.", "syntax": "creqv CRb,CRA,CRB", "operands": [ { "name": "CRb", "desc": "Target Condition Register Field" }, { "name": "CRA", "desc": "Source Condition Register Field" }, { "name": "CRB", "desc": "Source Condition Register Field" } ], "encoding": { "format": "XL-form", "hex_opcode": "0x4C000242", "length": "32", "binary_pattern": "010011 | CRb | CRA | CRB | 01001 | 00001 | Rc", "bit_positions": "0:5 | 6:10 | 11:15 | 16:18 | 19:20 | 21:30 | 31" }, "extension": "Base", "pseudocode": "CR[CRb] ← CR[CRA] XNOR CR[CRB]\nCR[CRb] ← (CR[CRA] AND CR[CRB]) OR (NOT CR[CRA] AND NOT CR[CRB])", "special_registers": "CR0, CR1-CR7", "programming_notes": "The creqv instruction is useful for comparing two condition register fields and determining where they are equivalent. It's important to ensure that the source registers (CRA and CRB) are correctly set before using this instruction, as incorrect values can lead to unexpected results in subsequent conditional logic. This instruction operates at the user privilege level and does not generate exceptions under normal circumstances.", "extended_mnemonics": [], "page_found": "Page 1373 - 1374", "example": "creqv 0, cr0, cr1" }, { "mnemonic": "ldat", "architecture": "PowerISA", "full_name": "Load Doubleword Atomic", "summary": "Atomically loads a doubleword from memory.", "description": "Atomically loads a doubleword from memory at the address formed by RA + RB and places the result in RT. This instruction provides atomic semantics for load operations on Power10 and later processors. The instruction updates CR0 when Rc=1.", "syntax": "ldat RT,RA,RB", "operands": [ { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RA", "desc": "Base Address General Purpose Register" }, { "name": "RB", "desc": "Offset General Purpose Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C0004CC", "length": "32", "binary_pattern": "011111 | RT | RA | RB | 10011 | 00110 | Rc", "bit_positions": "0:5 | 6:8 | 9:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "Base", "pseudocode": "EA ← (RA) + (RB)\nRT ← [EA]", "special_registers": "N/A", "programming_notes": "Places a reservation on the cache line containing the effective address. The subsequent store-conditional (stwcx./stdcx. etc.) will fail if the reservation has been lost due to an intervening store from any processor or an exception. Always check the EQ bit in CR0 after the store-conditional.", "extended_mnemonics": [], "page_found": "Page 1374 - 1375", "example": "ldat r3, r4, r5" }, { "mnemonic": "addme.", "architecture": "PowerISA", "full_name": "Add to Minus One Extended", "summary": "Adds the contents of two registers and subtracts one, then updates the condition register.", "description": "For addme., the sum of the contents of register RA and RB minus one is placed into register RT.", "syntax": "addme. RT,RA", "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "RA", "desc": "Source Register" } ], "encoding": { "format": "XO-form", "binary_pattern": "31 | RT | RA | 00000 | OE | 234 | Rc", "hex_opcode": "0x7C0001D4", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "00000", "clean": "00000" }, { "raw": "OE", "clean": "OE" }, { "raw": "234", "clean": "234" }, { "raw": "Rc", "clean": "Rc" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21 | 22:30 | 31" }, "extension": "Base", "pseudocode": "if 'addme.' then\n RT <- (RA) + (RB) - 1", "special_registers": "CR0, XER", "programming_notes": "The addme. instruction adds two registers, subtracts one from the result, and stores it in a third register. It updates the CR0 and XER special registers with the arithmetic results. Ensure that the input registers RA and RB are correctly aligned for optimal performance. This instruction is available at user privilege level.", "extended_mnemonics": [], "page_found": "Page 112 - 114", "example": "addme. r3, r4, r5" }, { "mnemonic": "stxvrdx", "architecture": "PowerISA", "full_name": "Store VSX Vector Rightmost Doubleword Indexed X-form", "summary": "Stores the rightmost doubleword of a VSX vector register to memory.", "description": "Stores the rightmost (low-order) doubleword of the VSX vector register VX to memory at the address formed by RA + RB. This instruction is part of the VSX extension and operates on the 64-bit portion of the 128-bit VSX register.", "syntax": "stxvrdx VX,RA,RB", "operands": [ { "name": "VX", "desc": "VSX Vector Register" }, { "name": "RA", "desc": "Base Address General Purpose Register" }, { "name": "RB", "desc": "Index General Purpose Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C0001DA", "length": "32", "binary_pattern": "31 | XS | RA | RB | 237 | TX", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "VSX", "pseudocode": "EA ← (RA) + (RB)\n[EA] ← VX[64:127]", "special_registers": "N/A", "programming_notes": "The stxvrdx instruction is used to store the rightmost doubleword (8 bytes) of a VSX vector register to memory. Ensure that the effective address formed by RA and RB is properly aligned to 8 bytes to avoid alignment faults. This instruction requires supervisor or hypervisor privilege level.", "extended_mnemonics": [], "page_found": "Page 1376 - 1377", "example": "stxvrdx v1, r4, r5" }, { "mnemonic": "plfd", "architecture": "PowerISA", "full_name": "Prefixed Load Floating-Point Double MLS:D-form", "summary": "Loads a double-precision floating-point value from memory into a VSX register.", "description": "A prefixed load instruction that loads a double-precision floating-point value from memory into a VSX register using a 34-bit immediate displacement. The effective address is formed using a prefix word and suffix word together, supporting a much larger displacement range than standard instructions.", "syntax": "plfd RT,RA,RB", "operands": [ { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "RB", "desc": "Source General Purpose Register" }, { "name": "VRT", "desc": "Destination VSX Register" }, { "name": "B", "desc": "Base General Purpose Register" } ], "encoding": { "format": "D-form", "hex_opcode": "0x06000000C8000000", "length": "32", "binary_pattern": "01 | 100 | Rc | .//.. | RT | RA | RB", "bit_positions": "0:5 | 6:10 | 11 | 12 | 13:17 | 18:22 | 23:31" }, "extension": "Prefixed", "pseudocode": "EA ← (RA) + EXTS(D)\nVRT ← [EA]", "special_registers": "N/A", "programming_notes": "The plfd instruction is used to load a double-precision floating-point value from memory into a VSX register. Ensure that the base and index registers point to a correctly aligned 8-byte boundary to avoid alignment faults. This instruction operates at user privilege level.", "extended_mnemonics": [], "page_found": "Page 1381 - 1382", "example": "plfd r3, r4, r5" }, { "mnemonic": "dquai.", "architecture": "PowerISA", "full_name": "DFP Quantize Immediate", "summary": "Quantizes a DFP value to an immediate number of decimal digits.", "description": "Quantizes a decimal floating-point (DFP) value in FRB to the number of decimal digits specified by immediate UI, storing the result in FRT. This instruction is part of the Decimal Floating-Point category and updates FPSCR and CR1 when Rc=1.", "syntax": "dquai. TE,FRT,FRB,RMC", "operands": [ { "name": "TE", "desc": "Target Exponent" }, { "name": "FRT", "desc": "Target Floating-Point Register" }, { "name": "FRB", "desc": "Source Floating-Point Register" }, { "name": "RMC", "desc": "Rounding Mode Control" } ], "encoding": { "format": "Z23-form", "hex_opcode": "0xEC000086", "length": "32", "binary_pattern": "0 | FRT | TE | FRB | RMC | Rc", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "Decimal Floating-Point", "pseudocode": "FRT ← Quantize(FRB, UI)\nFPSCR ← updated with DFP status\nCR1 ← (FRT is NaN, FRT is Infinity, FRT is Zero, FRT is Negative) if Rc=1", "special_registers": "N/A", "programming_notes": "The dquai. instruction is used for quantizing DFP values with an immediate quantum, rounding as necessary. Ensure that the immediate field UI specifies a valid quantum and that the source operand FRB is correctly formatted. This instruction operates at the problem state privilege level.", "extended_mnemonics": [], "page_found": "Page 249 - 250", "example": "dquai. f1, f3, 4" }, { "mnemonic": "xvf64gernn", "architecture": "PowerISA", "full_name": "VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate XX3-form", "summary": "Performs a VSX Vector 64-bit Floating-Point GER (rank-1 update) with negative multiply and negative accumulate, updating an accumulator register.", "description": "Performs a VSX vector 64-bit floating-point outer-product update (GER rank-1 update) with negative multiply and negative accumulate. This MMA instruction is part of the Matrix Multiply Accumulate facility and requires MMA support; it reads two VSX vector registers and updates a 512-bit accumulator.", "syntax": "xvf64gernn AT,XAp,XB", "operands": [ { "name": "AT", "type": "ACC", "desc": "Target accumulator. ACC[AT] holds a 4x2 matrix of double-precision values." }, { "name": "XAp", "type": "VSR", "desc": "Source VSR pair (even/odd). VSR[XAp] and VSR[XAp+1] are concatenated to supply the four row values." }, { "name": "XB", "type": "VSR", "desc": "Source VSR supplying the two column values." } ], "encoding": { "format": "XX3-form", "hex_opcode": "0xEC0007D0", "length": "32", "binary_pattern": "59 | AT | / | XA | XB | 250 | AX | BX | /", "bit_positions": "0:5 | 6:8 | 9:10 | 11:15 | 16:20 | 21:28 | 29 | 30 | 31" }, "extension": "MMA", "pseudocode": "vsrcX ← VSR[XAp] || VSR[XAp+1]\nvsrcY ← VSR[XB]\ndo i = 0 to 3\n do j = 0 to 1\n ACC[AT][i].dword[j] ← -( vsrcX.dword[i] × vsrcY.dword[j] + ACC[AT][i].dword[j] )\nThe product and the accumulated value are negated together.", "special_registers": "N/A", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.", "extended_mnemonics": [], "page_found": "Page 1384 - 1385", "example": "xvf64gernn" }, { "mnemonic": "fcfidus.", "architecture": "PowerISA", "full_name": "Floating Convert with round Unsigned Doubleword to Single-Precision format", "summary": "Converts an unsigned doubleword integer in a floating-point register to a single-precision floating-point number, rounding the result.", "description": "The instruction converts the contents of the source floating-point register (FRB) from an unsigned doubleword integer to a single-precision floating-point number and stores it in the target floating-point register (FRT).", "syntax": "fcfidus. FRT,FRB", "operands": [ { "name": "FRT", "desc": "Target Floating Point Register" }, { "name": "FRB", "desc": "Source Floating Point Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0xEC00079C", "length": "32", "binary_pattern": "111011 | FRT | // | FRB | 11110 | 01110", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "Floating-Point", "pseudocode": "FRT <- ConvertToSinglePrecision(FRB, unsigned)", "special_registers": "FPSCR, CR0", "programming_notes": "Use fcfidus. when converting unsigned 64-bit integers to single-precision floats. Ensure the source register contains a valid unsigned integer; otherwise, the result is undefined. This instruction operates at user privilege level and does not raise exceptions for invalid input values.", "extended_mnemonics": [], "page_found": "Page 1385 - 1386", "example": "fcfidus. f1, f3" }, { "mnemonic": "xsmaddmsp", "architecture": "PowerISA", "full_name": "VSX Scalar Multiply-Add Type-M Single-Precision", "summary": "Multiplies two single-precision floating-point values and adds a third, storing the result in the target register (Type-M form).", "description": "Performs a scalar single-precision floating-point multiply-add operation (Type-M form) using VSX registers, computing FRB × FRC + FRT and storing the result in FRT. The Type-M form provides additional semantics for rounding and exception handling in VSX scalar operations.", "syntax": "xsmaddmsp FRT,FRB,FRC", "operands": [ { "name": "FRT", "desc": "Target Floating Point Register" }, { "name": "FRB", "desc": "Source Floating Point Register" }, { "name": "FRC", "desc": "Source Floating Point Register" } ], "encoding": { "format": "XX3-form", "hex_opcode": "0xF0000048", "length": "32", "binary_pattern": "111100 | FRT | FRB | FRC | 00001 | 001", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "VSX", "pseudocode": "FRT ← FRT + (FRB × FRC)", "special_registers": "FPSCR", "programming_notes": "The xsmaddmsp instruction is commonly used for efficient scalar floating-point arithmetic operations, particularly in applications requiring high performance and precision. Ensure that the input registers are properly aligned to avoid potential exceptions. This instruction operates at a privilege level that allows it to be executed by user-mode programs, making it accessible for general-purpose computations. Be aware of the FPSCR register's impact on rounding modes and exception flags.", "extended_mnemonics": [], "page_found": "Page 1386 - 1387", "example": "xsmaddmsp f1, f3, f4" }, { "mnemonic": "xvnmaddmsp", "architecture": "PowerISA", "full_name": "VSX Vector Negative Multiply-Add Type-M Single-Precision", "summary": "Performs a vector single-precision floating-point negative multiply-add operation (Type-M), computing the negation of (XB * XT + XA) for each single-precision element.", "description": "Performs a VSX vector single-precision floating-point negative multiply-add operation (Type-M form), computing -(XA + XB × XT) for each single-precision element. This instruction is part of the VSX extension and operates on four single-precision values per 128-bit vector.", "syntax": "xvnmaddmsp XT,XA,XB", "operands": [ { "name": "XT", "type": "VSR", "desc": "Target VSX vector register that serves as both the third multiplicand and destination for negated results." }, { "name": "XA", "type": "VSR", "desc": "Source VSX vector register providing the first operand (addend)." }, { "name": "XB", "type": "VSR", "desc": "Source VSX vector register providing the first multiplier operand." } ], "encoding": { "format": "XX3-form", "hex_opcode": "0xF0000648", "length": "32", "binary_pattern": "60 | XT | XA | XB | 1608", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VSX", "pseudocode": "for i ∈ [0,3]:\n XA[32*i:32*i+31] ← -(XA[32*i:32*i+31] + (XB[32*i:32*i+31] × XT[32*i:32*i+31]))", "special_registers": "N/A", "programming_notes": "This instruction is useful for performing complex vector operations involving single-precision floating-point arithmetic. Ensure that all input and output vectors are properly aligned to avoid performance penalties or exceptions. The operation is performed at the user privilege level, so no special privileges are required. Be cautious of potential overflow or underflow conditions during multiplication and addition steps.", "extended_mnemonics": [], "page_found": "Page 1387 - 1388", "example": "xvnmaddmsp vs1, vs2, vs3" }, { "mnemonic": "xvcvuxddp", "architecture": "PowerISA", "full_name": "VSX Vector Convert with round Unsigned Doubleword to Double-Precision format", "summary": "Converts an unsigned doubleword vector element to a double-precision floating-point value.", "description": "For each doubleword element in the source vector register VRB, the instruction converts the unsigned 64-bit integer value to a double-precision floating-point value and places the result in the corresponding doubleword element of the target vector register VRT. The conversion uses the current rounding mode. Two elements are processed in parallel, one per doubleword lane.", "syntax": "xvcvuxddp VRT, VRA, VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "XX2-form", "hex_opcode": "0xF00007A0", "length": "32", "binary_pattern": "111100 | VRT | // | VRA | 11110 | 1000", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "VSX", "pseudocode": "do i = 0 to 1\n VRT.dword[i] ← ConvertUnsignedFixed64ToFP64(VRB.dword[i])", "special_registers": "N/A", "programming_notes": "This instruction is useful for converting unsigned 64-bit integers in a vector to double-precision floating-point numbers. Ensure that the source vector elements are correctly aligned and consider the current rounding mode's effect on conversion results. This operation processes two elements per cycle, making it efficient for bulk conversions.", "extended_mnemonics": [], "page_found": "Page 1389 - 1390", "example": "xvcvuxddp v1, v2, v3" }, { "mnemonic": "pmxvf16ger2pp", "architecture": "PowerISA", "full_name": "Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Positive accumulate", "summary": "Performs a prefixed masked VSX vector 16-bit floating-point GER rank-2 update with positive multiply and positive accumulate.", "description": "A prefixed masked VSX vector 16-bit floating-point outer-product update (GER rank-2 update) with positive multiply and positive accumulate. This 64-bit MMA instruction requires both prefix and suffix encoding and supports register-based masking for selective accumulator updates.", "syntax": "pmxvf16ger2pp AT,XA,XB,XMSK,YMSK,PMSK", "operands": [ { "name": "AT", "type": "ACC", "desc": "Target accumulator. ACC[AT] holds a 4x4 matrix of 32-bit floating-point values." }, { "name": "XA", "type": "VSR", "desc": "Source VSR supplying four words, each holding two 16-bit values." }, { "name": "XB", "type": "VSR", "desc": "Source VSR supplying four words, each holding two 16-bit values." }, { "name": "XMSK", "type": "imm4", "desc": "4-bit row mask. Row i is updated only when bit i is 1; a masked-off element is set to zero." }, { "name": "YMSK", "type": "imm4", "desc": "4-bit column mask. Column j is updated only when bit j is 1; a masked-off element is set to zero." }, { "name": "PMSK", "type": "imm2", "desc": "2-bit product mask selecting which of the two 16-bit lanes contribute to each product." } ], "encoding": { "format": "MMIRR:XX3-form", "hex_opcode": "0x07900000EC000090", "length": "64", "binary_pattern": "000001 | 11100 | 1 | Rc | ../// | ///.. | ?", "bit_positions": "0:5 | 6:10 | 11 | 12 | 13 | 14 | 15:63" }, "extension": "MMA", "pseudocode": "do i = 0 to 3\n do j = 0 to 3\n if XMSK.bit[i]=1 & YMSK.bit[j]=1 then\n a0 ← (PMSK.bit[0]=1) ? VSR[XA].word[i].hword[0] : 0\n a1 ← (PMSK.bit[1]=1) ? VSR[XA].word[i].hword[1] : 0\n b0 ← (PMSK.bit[0]=1) ? VSR[XB].word[j].hword[0] : 0\n b1 ← (PMSK.bit[1]=1) ? VSR[XB].word[j].hword[1] : 0\n ACC[AT][i].word[j] ← round(a0 × b0 + a1 × b1) + ACC[AT][i].word[j]\n else\n ACC[AT][i].word[j] ← 0", "special_registers": "N/A", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.", "extended_mnemonics": [], "page_found": "Page 1397 - 1398", "example": "pmxvf16ger2pp" }, { "mnemonic": "pmxvi8ger4pp", "architecture": "PowerISA", "full_name": "Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) Positive multiply, Positive accumulate", "summary": "Performs a prefixed masked VSX vector 8-bit signed/unsigned integer GER rank-4 update with positive multiply and positive accumulate, adding the result to the accumulator.", "description": "Performs a prefixed masked VSX vector 8-bit signed/unsigned integer generalized matrix multiply (GER) rank-4 update with positive multiply and positive accumulate semantics, adding the outer product result to the target accumulator register. This instruction is part of the MMA (Matrix-Multiply Assist) extension and uses masking to selectively update the accumulator based on mask fields AT, AX, and BX.", "syntax": "pmxvi8ger4pp AT,XA,XB,XMSK,YMSK,PMSK", "operands": [ { "name": "AT", "type": "ACC", "desc": "Target accumulator. ACC[AT] holds a 4x4 matrix of 32-bit signed integer values." }, { "name": "XA", "type": "VSR", "desc": "Source VSR supplying four words, each holding four signed 8-bit values." }, { "name": "XB", "type": "VSR", "desc": "Source VSR supplying four words, each holding four unsigned 8-bit values." }, { "name": "XMSK", "type": "imm4", "desc": "4-bit row mask. Row i is updated only when bit i is 1; a masked-off element is set to zero." }, { "name": "YMSK", "type": "imm4", "desc": "4-bit column mask. Column j is updated only when bit j is 1; a masked-off element is set to zero." }, { "name": "PMSK", "type": "imm4", "desc": "4-bit product mask selecting which of the four byte lanes contribute to each product." } ], "encoding": { "format": "MMIRR:XX3-form", "hex_opcode": "0x07900000EC000010", "length": "32", "binary_pattern": "59 | AT | / | XA | XB | 2 | AX | BX | /", "bit_positions": "0:5 | 6:8 | 9:10 | 11:15 | 16:20 | 21:28 | 29 | 30 | 31" }, "extension": "MMA", "pseudocode": "do i = 0 to 3\n do j = 0 to 3\n if XMSK.bit[i]=1 & YMSK.bit[j]=1 then\n psum ← 0\n do k = 0 to 3\n if PMSK.bit[k]=1 then\n psum ← psum + EXTS(VSR[XA].word[i].byte[k]) × EXTZ(VSR[XB].word[j].byte[k])\n ACC[AT][i].word[j] ← CHOP32( psum + EXTS(ACC[AT][i].word[j]) )\n else\n ACC[AT][i].word[j] ← 0", "special_registers": "N/A", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.", "extended_mnemonics": [], "page_found": "Page 1398 - 1399", "example": "pmxvi8ger4pp" }, { "mnemonic": "xvf16ger2pn", "architecture": "PowerISA", "full_name": "VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Negative accumulate", "summary": "Performs a rank-2 update of an accumulator register using 16-bit floating-point outer product, with positive multiply and negative accumulate.", "description": "Performs a VSX rank-2 generalized matrix multiply (GER) update using 16-bit floating-point elements with positive multiply and negative accumulate semantics. The instruction computes an outer product of two 2-element vectors and subtracts the result from the target accumulator. This is an MMA extension instruction that updates a 2×2 block of the accumulator.", "syntax": "xvf16ger2pn AT,XA,XB", "operands": [ { "name": "AT", "type": "imm3", "desc": "Accumulator target index (specifies which accumulator register in the range ACC0-ACC7)" }, { "name": "XA", "type": "VSR", "desc": "Source VSX register containing 2 16-bit floating-point elements" }, { "name": "XB", "type": "VSR", "desc": "Source VSX register containing 2 16-bit floating-point elements" }, { "name": "AX", "type": "imm1", "desc": "Accumulator mask for rows (2 16-bit FP values, positive multiply)" }, { "name": "BX", "type": "imm1", "desc": "Source mask for columns (2 16-bit FP values, negative accumulate)" } ], "encoding": { "format": "XX3-form", "hex_opcode": "0xEC000490", "length": "32", "binary_pattern": "59 | AT | / | XA | XB | 146 | AX | BX | /", "bit_positions": "0:5 | 6:8 | 9:10 | 11:15 | 16:20 | 21:28 | 29 | 30 | 31" }, "extension": "MMA", "pseudocode": "acc ← acc - (outer product of 2 16-bit FP elements from XA and 2 from XB)", "special_registers": "N/A", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.", "extended_mnemonics": [], "page_found": "Page 1402 - 1403", "example": "xvf16ger2pn" }, { "mnemonic": "xsxsigqp", "architecture": "PowerISA", "full_name": "VSX Scalar Extract Significand Quad-Precision", "summary": "Extracts the significand of a quad-precision floating-point number.", "description": "Extracts the significand (mantissa) field from a quad-precision (128-bit) floating-point value in the source VSX register and places the extracted significand into the target VSX register. The result preserves the sign of the original significand and right-justifies it within a 64-bit field. The instruction does not modify condition registers or exception flags.", "syntax": "xsxsigqp VRT, VRA", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0xFC120648", "length": "32", "binary_pattern": "111111 | VRT | 10010 | VRA | 11001 | 00100 | Rc", "bit_positions": "0:5 | 6:8 | 9:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "Floating-Point", "pseudocode": "significand ← extract_significand(VRA[0:127])\nVRT[0:127] ← sign_extend_to_128bit(significand)", "special_registers": "N/A", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "extended_mnemonics": [], "page_found": "Page 1408 - 1409", "example": "xsxsigqp v1, v2" }, { "mnemonic": "xsnmsubmsp", "architecture": "PowerISA", "full_name": "VSX Scalar Negative Multiply-Subtract Type-M Single-Precision", "summary": "Performs a scalar negative multiply-subtract operation in single-precision floating-point, storing the result using the Type-M (multiplicand) form where the target register provides one of the multiplicand operands.", "description": "Performs a VSX scalar negative multiply-subtract operation on single-precision floating-point values using the Type-M form, where the target register (VRT) provides the subtrahend multiplicand operand. Computes -(VRA × VRT - VRB) and stores the result in VRT. This operation uses the FPSCR rounding mode and may set exception flags FPSCR[VXSNAN, VXISI, VXSQRT, VXCVI, XX, ZX, UX, OX].", "syntax": "xsnmsubmsp XT,XA,XB", "operands": [ { "name": "XT", "type": "VSR", "desc": "Target VSR. In the Type-M form it also supplies the multiplier, and it receives the negated result." }, { "name": "XA", "type": "VSR", "desc": "First source VSR, the multiplicand." }, { "name": "XB", "type": "VSR", "desc": "Second source VSR, subtracted from the product." } ], "encoding": { "format": "XX3-form", "hex_opcode": "0xF00004C8", "length": "32", "binary_pattern": "60 | XT | XA | XB | 1224", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VSX", "pseudocode": "VSR[XT].dword[0] ← -( VSR[XA].dword[0] × VSR[XT].dword[0] - VSR[XB].dword[0] )\nThe result is rounded to single precision and FPSCR exception flags are updated.", "special_registers": "N/A", "programming_notes": "The xsnmsubmsp instruction is useful for performing complex floating-point calculations involving multiplication, subtraction, and negation in a single operation. Ensure that the target register (XT) is properly aligned and contains valid single-precision floating-point values to avoid undefined behavior. This instruction operates at user privilege level and may raise exceptions if operands are out of range or if there are NaNs involved.", "extended_mnemonics": [], "page_found": "Page 1411 - 1412", "example": "xsnmsubmsp" }, { "mnemonic": "xsnmaddmdp", "architecture": "PowerISA", "full_name": "VSX Scalar Negative Multiply-Add Type-M Double-Precision", "summary": "Computes the negative of the fused multiply-add of the double-precision floating-point operands, storing the result in the target scalar VSX register (Type-M: target register is used as the addend).", "description": "Performs a VSX scalar fused negative multiply-add operation on double-precision floating-point values using the Type-M form, where VRT is used as the addend operand. Computes -(VRA × VRB + VRT) and stores the result in VRT. The instruction operates on scalar elements (bits 0:63 of the VSX registers) and updates FPSCR exception flags accordingly.", "syntax": "xsnmaddmdp VRT, VRA, VRB, VRC", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "VRC", "desc": "Source Vector Register" } ], "encoding": { "format": "XX3-form", "hex_opcode": "0xF0000548", "length": "32", "binary_pattern": "60 | XT | XA | XB | 1352", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VSX", "pseudocode": "VRT[0:63] ← -(VRA[0:63] × VRB[0:63] + VRT[0:63])\nUpdate FPSCR exception flags based on floating-point result", "special_registers": "N/A", "programming_notes": "Use xsnmaddmdp for performing a fused multiply-add operation on double-precision floating-point numbers, negating the result. Ensure that the target register provides the addend, and be aware that this instruction operates as a single fused step without intermediate rounding.", "extended_mnemonics": [], "page_found": "Page 1413 - 1414", "example": "xsnmaddmdp v1, v2, v3, v4" }, { "mnemonic": "xvmsubmdp", "architecture": "PowerISA", "full_name": "VSX Vector Multiply-Subtract Type-M Double-Precision", "summary": "Multiplies corresponding double-precision floating-point elements of two VSX registers, subtracts the corresponding element of a third register, and stores the results, using the Type-M (multiplicand) form.", "description": "For each of the two double-precision floating-point elements, the instruction multiplies the corresponding elements of VRA and VRT, subtracts the corresponding element of VRB, and places the result into the corresponding element of VRT. This is the Type-M variant, meaning VRT serves as both a source (multiplicand) and the destination register. The operation computes VRT ← (VRA × VRT) - VRB for each element.", "syntax": "xvmsubmdp VRT, VRA, VRB, VRC", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "VRC", "desc": "Source Vector Register" } ], "encoding": { "format": "XX3-form", "hex_opcode": "0xF00003C8", "length": "32", "binary_pattern": "111100 | VRT | VRA | VRB | 01111 | 001", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "VSX", "pseudocode": "do i = 0 to 1\n VRT.fpr[i] ← RND(VRA.fpr[i] × VRT.fpr[i] - VRB.fpr[i])\nend", "special_registers": "N/A", "programming_notes": "This instruction is commonly used in applications requiring complex floating-point arithmetic operations, such as scientific computations and graphics processing. Ensure that the input registers (VRA, VRT, VRB) are properly aligned to avoid performance penalties or exceptions. The Type-M variant requires careful handling since VRT is both a source and destination register, which can lead to unexpected results if not managed correctly. This instruction operates at user privilege level but may raise exceptions for invalid operations like division by zero or overflow.", "extended_mnemonics": [], "page_found": "Page 1415 - 1416", "example": "xvmsubmdp v1, v2, v3, v4" }, { "mnemonic": "diexq.", "architecture": "PowerISA", "full_name": "DFP Insert Biased Exponent Quad X-form", "summary": "Inserts the biased exponent from a source register into a destination register in quad format.", "description": "Inserts a biased exponent from a source general-purpose register into a quad-precision decimal floating-point number, replacing the exponent field of the destination. The instruction requires Decimal Floating-Point (DFP) support. The update form (indicated by the dot) sets condition register field CR0 based on the result classification (zero, normal, infinity, or NaN).", "syntax": "diexq. RT,RA,RB", "operands": [ { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "RB", "desc": "Source General Purpose Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0xFC0006C4", "length": "32", "binary_pattern": "111111 | RT | RA | RB | 11011 | 00010 | Rc", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:30 | 31" }, "extension": "Decimal Floating-Point", "pseudocode": "exponent ← RA[32:63]\nRT ← insert_exponent_into_DFP_quad(RB, exponent)\nif Rc = 1 then CR0 ← classify_DFP_result(RT)", "special_registers": "N/A", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "extended_mnemonics": [], "page_found": "Page 1417 - 1418", "example": "diexq. r3, r4, r5" }, { "mnemonic": "sthcix", "architecture": "PowerISA", "full_name": "Store Halfword Caching Inhibited Indexed X-form", "summary": "Stores a halfword from a general-purpose register to memory, with caching inhibited.", "description": "The contents of the lower 16 bits (bits 48:63) of register RS are stored into the halfword in memory addressed by the effective address (EA). The EA is the sum of the contents of register RA and register RB. The store is performed with caching inhibited, meaning the data is written directly to memory bypassing the cache. This instruction is a privileged hypervisor instruction available in Book III.", "syntax": "sthcix RT,RB,RA", "operands": [ { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RB", "desc": "Base Address General Purpose Register" }, { "name": "RA", "desc": "Index General Purpose Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C00076A", "length": "32", "binary_pattern": "31 | RS | RA | RB | 949 | /", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "Base", "pseudocode": "EA ← (RA) + (RB)\nMEM(EA, 2) ← (RS)[48:63]", "special_registers": "", "programming_notes": "This instruction is used for storing data directly to memory without caching, which can be useful for ensuring data consistency in hypervisor environments. It requires supervisor privilege level and should be used with caution as it bypasses the cache, potentially affecting performance. Ensure that registers RA and RB contain valid addresses, and RS contains the data to be stored in its lower 16 bits.", "extended_mnemonics": [], "page_found": "Page 1418 - 1419", "example": "sthcix r3, r5, r4" }, { "mnemonic": "vcmpgefp.", "architecture": "PowerISA", "full_name": "Vector Compare Greater Than or Equal Floating-Point", "summary": "Compares the elements of two vector registers and sets the result in a third vector register based on whether each element is greater than or equal to the corresponding element in the other vector.", "description": "The vcmpgefp. instruction compares corresponding single-precision floating-point elements of vector registers VRA and VRB. For each of the four 32-bit floating-point elements, if the element in VRA is greater than or equal to the corresponding element in VRB, the corresponding element in VRT is set to all 1s (0xFFFFFFFF); otherwise, it is set to all 0s (0x00000000). The dot form (vcmpgefp.) additionally updates the CR6 field of the Condition Register to reflect whether all elements, some elements, or no elements satisfied the comparison.", "syntax": "vcmpgefp. VRT, VRA, VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register A" }, { "name": "VRB", "desc": "Source Vector Register B" } ], "encoding": { "format": "VC-form", "hex_opcode": "0x100001C6", "length": "32", "binary_pattern": "000100 | VRT | VRA | VRB | .0111 | 000110", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "Base", "pseudocode": "for i = 0 to 7 do\n if (VRA[i] >= VRB[i]) then\n VRT[i] <- 1\n else\n VRT[i] <- 0\n end if\nend for", "special_registers": "N/A", "programming_notes": "Use vcmpgefp. to compare four single-precision floating-point elements in two vector registers. Ensure both input vectors are properly aligned and initialized. The dot form updates CR6, indicating the comparison results, which can be useful for conditional branching.", "extended_mnemonics": [], "page_found": "Page 1419 - 1420", "example": "vcmpgefp. v1, v2, v3" }, { "mnemonic": "mulhd.", "architecture": "PowerISA", "full_name": "Multiply High Doubleword", "summary": "Multiplies the contents of two registers and places the high-order 64 bits of the product into a target register.", "description": "For mulhd., the product of the contents of register RA and RB is computed, and the high-order 64 bits of this product are placed into register RT.", "syntax": "mulhd. RT,RA,RB", "operands": [ { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "RB", "desc": "Source General Purpose Register" } ], "encoding": { "format": "XO-form", "hex_opcode": "0x7C000092", "length": "32", "binary_pattern": "011111 | RT | RA | RB | /0010 | 01001", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "Base", "pseudocode": "if 'mulhd.' then\n RT <- (RA) * (RB)", "special_registers": "CR0, XER", "programming_notes": "The mulhd. instruction multiplies two 64-bit integers and stores the high 64 bits of the result in a destination register. It does not affect any special registers like CR0 or XER, so developers should be cautious when relying on carry flags or overflow conditions. This instruction is commonly used in cryptographic algorithms where large integer multiplication is required without needing the lower half of the product.", "extended_mnemonics": [], "page_found": "Page 1423 - 1424", "example": "mulhd. r3, r4, r5" }, { "mnemonic": "lbzux", "architecture": "PowerISA", "full_name": "Load Byte and Zero with Update Indexed X-form", "summary": "Loads a byte from memory into a register, zero-extends it to 32 bits, and updates the base address.", "description": "The sum of the contents of general-purpose register RA and the contents of general-purpose register RB is the effective address (EA). The byte in memory addressed by EA is loaded into the low-order 8 bits of general-purpose register RT, and the remaining bits of RT are cleared to 0. The effective address EA is placed into register RA. If RA = 0 or RA = RT, the instruction form is invalid.", "syntax": "lbzux RT,RA,RB", "operands": [ { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RA", "desc": "Base Address General Purpose Register" }, { "name": "RB", "desc": "Index General Purpose Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C0000EE", "length": "32", "binary_pattern": "31 | RT | RA | RB | 119 | /", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "Base", "pseudocode": "EA ← (RA) + (RB)\nRT ← 0x000000 || MEM(EA, 1)\nRA ← EA", "special_registers": "N/A", "programming_notes": "The base register (RA) is updated with the effective address after the memory access. RA must not be 0 and must differ from the destination register; violating this constraint produces undefined results.", "extended_mnemonics": [], "page_found": "Page 1425 - 1426", "example": "lbzux r3, r4, r5" }, { "mnemonic": "or.", "architecture": "PowerISA", "full_name": "OR Record", "summary": "Performs a bitwise OR operation on the contents of two registers and updates the condition register.", "description": "For or., the bitwise OR of the contents of register RA and RB is placed into register RT.", "syntax": "or. RT,RA,RB", "operands": [ { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "RB", "desc": "Source General Purpose Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C000378", "length": "32", "binary_pattern": "18 | LI | AA | LK", "bit_positions": "0:5 | 6:29 | 30 | 31" }, "extension": "Base", "pseudocode": "if 'or.' then\n RT <- (RA) OR (RB)", "special_registers": "CR0, XER", "programming_notes": "The or. instruction performs a bitwise OR operation between two registers, storing the result in another register. This instruction does not require any special alignment and can be executed at any privilege level. It is commonly used for combining flags or setting specific bits in a register.", "extended_mnemonics": [], "page_found": "Page 1426 - 1427", "example": "or. r3, r4, r5" }, { "mnemonic": "add.", "architecture": "PowerISA", "full_name": "Add Record", "summary": "Adds the contents of two registers and updates the condition register.", "description": "For add., the sum of the contents of register RA and RB is placed into register RT.", "syntax": "add. RT,RA,RB", "operands": [ { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "RB", "desc": "Source General Purpose Register" } ], "encoding": { "format": "XO-form", "hex_opcode": "0x7C000214", "length": "32", "binary_pattern": "18 | LI | AA | LK", "bit_positions": "0:5 | 6:29 | 30 | 31" }, "extension": "Base", "pseudocode": "if 'add.' then\n RT <- (RA) + (RB)", "special_registers": "CR0, XER", "programming_notes": "The add. instruction adds the values in registers RA and RB, storing the result in RT. It updates the CR0 and XER special registers to reflect overflow and carry conditions. Ensure that the operands are correctly aligned for optimal performance.", "extended_mnemonics": [], "page_found": "Page 1428 - 1429", "example": "add. r3, r4, r5" }, { "mnemonic": "fctiwuz", "architecture": "PowerISA", "full_name": "Floating Convert with truncate Double-Precision To Unsigned Word format", "summary": "Converts a double-precision floating-point number to an unsigned integer word.", "description": "The double-precision floating-point operand in FRB is converted to a 32-bit unsigned integer using truncation (round toward zero), and the result is placed in the low-order 32 bits of FRT. If the operand is a NaN or less than 0, the result is 0. If the operand is greater than the maximum unsigned 32-bit value, the result is 0xFFFFFFFF. The high-order 32 bits of FRT are undefined. The FPSCR is updated to reflect the result of the operation.", "syntax": "fctiwuz[.] FRT,FRB", "operands": [ { "name": "FRT", "desc": "Target Floating Point Register" }, { "name": "FRB", "desc": "Source Floating Point Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0xFC00011E", "length": "32", "binary_pattern": "18 | LI | AA | LK", "bit_positions": "0:5 | 6:29 | 30 | 31" }, "extension": "Floating-Point", "pseudocode": "if FPSCR[VXSNAN] then FRT ← undefined\nelse\n src ← (FRB)\n if src is NaN or src < 0 then\n result ← 0x00000000\n FPSCR[VXCVI] ← 1\n else if src > 2^32 - 1 then\n result ← 0xFFFFFFFF\n FPSCR[VXCVI] ← 1\n else\n result ← truncate(src) converted to unsigned 32-bit integer\n FRT[32:63] ← result\n FRT[0:31] ← undefined", "special_registers": "CR0, XER, FPSCR", "programming_notes": "The fctiwuz instruction converts a double-precision floating-point number to an unsigned 32-bit integer by truncating towards zero. If the input is NaN, negative, or exceeds the maximum unsigned 32-bit value, it results in 0 or 0xFFFFFFFF respectively, and sets VXCVI in FPSCR. The high-order bits of FRT are undefined after this operation.", "extended_mnemonics": [], "page_found": "Page 1432 - 1433", "example": "fctiwuz[.] f1, f3" }, { "mnemonic": "lfsx", "architecture": "PowerISA", "full_name": "Load Floating-Point Single Indexed X-form", "summary": "Loads a single-precision floating-point value from memory into a floating-point register.", "description": "Loads a single-precision floating-point value from memory into a floating-point register using indexed addressing. The effective address is computed as RA + RB. If RA is 0, the address is simply RB. The instruction does not affect condition registers or exception flags; any floating-point exceptions are determined by the loaded value itself.", "syntax": "lfsx FT,RA,RB", "operands": [ { "name": "FT", "desc": "Target Floating-Point Register" }, { "name": "RA", "desc": "Index General Purpose Register" }, { "name": "RB", "desc": "Base General Purpose Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C00042E", "length": "32", "binary_pattern": "011111 | FT | RA | RB | 10000 | 10111 | Rc", "bit_positions": "0:5 | 6:8 | 9:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "Floating-Point", "pseudocode": "EA ← (RA = 0) ? RB : RA + RB\nFT ← [EA:EA+3]", "special_registers": "CR0, FPSCR", "programming_notes": "The lfsx instruction is commonly used to load single-precision floating-point values from memory into a floating-point register. Ensure that the base and index registers contain valid addresses, and be aware of potential alignment issues that may affect performance or cause exceptions. This instruction operates at user privilege level.", "extended_mnemonics": [], "page_found": "Page 1433 - 1434", "example": "lfsx f1, r4, r5" }, { "mnemonic": "pstfd", "architecture": "PowerISA", "full_name": "Prefixed Store Floating-Point Double MLS:D-form", "summary": "Stores a double-precision floating-point value from a register to memory.", "description": "Stores a double-precision floating-point value from a floating-point register to memory using a prefixed instruction format (64 bits total: 32-bit prefix + 32-bit instruction). The addressing mode uses a base register and a displacement that can be formed from the prefix and suffix portions, allowing for a wider displacement range than non-prefixed forms. This instruction does not update condition registers.", "syntax": "pstfd FRT,RA,RB", "operands": [ { "name": "FRT", "desc": "Target Floating-Point Register" }, { "name": "RA", "desc": "Base General Purpose Register" }, { "name": "RB", "desc": "Offset General Purpose Register" } ], "encoding": { "format": "MLS:D-form", "hex_opcode": "0x06000000D8000000", "length": "64", "binary_pattern": "01 | 100 | Rc | .//.. | FRT | RA | RB", "bit_positions": "0:5 | 6:10 | 11 | 12 | 13:17 | 18:22 | 23:63" }, "extension": "Prefixed", "pseudocode": "displacement ← (prefix_immediate || suffix_immediate) [sign-extended to 64 bits]\nEA ← RA + displacement\n[EA:EA+7] ← FRT[0:63]", "special_registers": "N/A", "programming_notes": "The pstfd instruction is used to store a double-precision floating-point value from a register into memory. Ensure that the effective address calculation does not result in an overflow or underflow. This instruction requires the EA to be aligned on an 8-byte boundary for optimal performance and correctness.", "extended_mnemonics": [], "page_found": "Page 1437 - 1438", "example": "pstfd f1, r4, r5" }, { "mnemonic": "stwcix", "architecture": "PowerISA", "full_name": "Store Word Caching Inhibited Indexed X-form", "summary": "Stores a word from a source register to memory with caching inhibited.", "description": "Stores a 32-bit word from register RS to memory at the address formed by adding RA and RB, with caching inhibited to bypass L1 cache. This instruction is used for I/O operations and memory-mapped device access where cache coherency is not desired. No condition registers or status fields are modified.", "syntax": "stwcix RS,RA,RB", "operands": [ { "name": "RS", "desc": "Source General Purpose Register" }, { "name": "RA", "desc": "Base Address General Purpose Register" }, { "name": "RB", "desc": "Index General Purpose Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C00072A", "length": "32", "binary_pattern": "0 | RS | RA | RB | 11100 | 10101", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:31" }, "extension": "Base", "pseudocode": "EA ← (RA) + (RB)\n[EA] ← (RS)[32:63]", "special_registers": "N/A", "programming_notes": "The stwcix instruction is used to store a 32-bit word from a register to memory with caching inhibited, which can be useful for ensuring data consistency between the CPU and external storage. This instruction requires hypervisor privilege (level HV) and should be used sparingly due to its performance impact. Ensure that the destination address is properly aligned to avoid potential exceptions.", "extended_mnemonics": [], "page_found": "Page 1438 - 1439", "example": "stwcix r3, r4, r5" }, { "mnemonic": "vextuwrx", "architecture": "PowerISA", "full_name": "Vector Extract Unsigned Word to GPR using GPR-specified Right-Index VX-form", "summary": "Extracts an unsigned word from a vector register and places it into a general-purpose register.", "description": "Extracts a 32-bit unsigned word from vector register RB using a byte-offset index contained in GPR RA, and places the extracted value into GPR VRT. The index specifies which 4-byte element to extract from the 128-bit vector. This instruction requires VMX/AltiVec support and no condition flags are affected.", "syntax": "vextuwrx VRT,RA,RB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "RA", "desc": "Source General Purpose Register (index)" }, { "name": "RB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x1000078D", "length": "32", "binary_pattern": "000100 | VRT | // | RA | 10100 | 001100", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:31" }, "extension": "VMX (AltiVec)", "pseudocode": "idx ← (RA)[29:31] || 0b00\nVRT ← (RB)[idx*8 : idx*8+31]", "special_registers": "N/A", "programming_notes": "Use vextuwrx to extract a 32-bit unsigned word from a vector register using a right-index specified by a GPR. Ensure the index is correctly calculated to avoid out-of-bounds access. The result is zero-extended to 64 bits before being stored in the target GPR.", "extended_mnemonics": [], "page_found": "Page 1442 - 1443", "example": "vextuwrx v1, r4, r5" }, { "mnemonic": "vmul10ecuq", "architecture": "PowerISA", "full_name": "Vector Multiply-by-10 Extended & write Carry-out Unsigned Quadword", "summary": "Multiplies the unsigned quadword integer in vector register VA by 10, adds the least-significant bit of VB as a carry-in digit, and writes the carry-out of the result to vector register VX.", "description": "Multiplies the unsigned 128-bit quadword in vector register VA by 10, adds the least-significant bit of VB as a carry-in, and writes only the carry-out (overflow) of the result to vector register VX. The result discards the low 128 bits, retaining only the high carry. This instruction requires VMX/AltiVec support and no condition registers are modified.", "syntax": "vmul10ecuq VX,VA,VB", "operands": [ { "name": "VX", "desc": "Target Vector Register" }, { "name": "VA", "desc": "Source Vector Register" }, { "name": "VB", "desc": "Source Vector Register" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x10000041", "length": "32", "binary_pattern": "000100 | VX | VA | VB | 00001 | 000001", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:31" }, "extension": "VMX (AltiVec)", "pseudocode": "product ← (VA) × 10 + ((VB)[127] as carry-in)\nVX ← product[128:191]", "special_registers": "N/A", "programming_notes": "This instruction is ideal for high-performance multi-precision decimal arithmetic, especially when performing chained multiply-by-10 operations. Ensure that the input values in VA and VB are correctly aligned as unsigned 128-bit integers to avoid unexpected results. The carry-out written to VX should be used as the extended carry-in for subsequent operations to maintain precision.", "extended_mnemonics": [], "page_found": "Page 1444 - 1445", "example": "vmul10ecuq v1, v2, v2" }, { "mnemonic": "vpkswus", "architecture": "PowerISA", "full_name": "Vector Pack Signed Word Unsigned Saturate", "summary": "Packs signed words from two source vectors into one destination vector with unsigned saturation.", "description": "Packs signed 32-bit word elements from vectors VSRA and VSRB into 16-bit unsigned elements in VRT, saturating to the unsigned 16-bit range [0, 65535] if any source element overflows. The operation interleaves words from VSRA and VSRB into the result. This instruction requires VMX/AltiVec support and no condition registers are modified.", "syntax": "vpkswus VRT,VSRA,VSRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VSRA", "desc": "Source Vector Register A" }, { "name": "VSRB", "desc": "Source Vector Register B" } ], "encoding": { "format": "VX-form", "hex_opcode": "0x1000014E", "length": "32", "binary_pattern": "000100 | VRT | VSRA | VSRB | 00101 | 001110", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:31" }, "extension": "VMX (AltiVec)", "pseudocode": "for i in 0..3:\n VRT[i*16 : i*16+15] ← saturate_unsigned_16bit(VSRA[i*32 : i*32+31])\n VRT[(i+4)*16 : (i+4)*16+15] ← saturate_unsigned_16bit(VSRB[i*32 : i*32+31])", "special_registers": "N/A", "programming_notes": "The vpkswus instruction is useful for efficiently packing and converting signed 32-bit integers to unsigned 16-bit integers with saturation. Ensure that the input vectors are correctly aligned and that the operation does not exceed the bounds of the target vector register. This instruction operates at user privilege level and will raise an exception if any invalid operand access occurs.", "extended_mnemonics": [], "page_found": "Page 1445 - 1446", "example": "vpkswus v1, vs2, vs3" }, { "mnemonic": "cpabort", "architecture": "PowerISA", "full_name": "Copy-Paste Abort", "summary": "Aborts any in-progress copy-paste operation, discarding any pending copy target set by a previous Copy instruction.", "description": "Aborts any in-progress copy-paste operation initiated by a previous Copy instruction, discarding the pending copy buffer and resetting the copy-paste state. This is a privileged Base instruction that has no operands and does not modify any condition or status registers.", "syntax": "cpabort", "operands": [], "encoding": { "format": "X-form", "hex_opcode": "0x7C00068C", "length": "32", "binary_pattern": "31 | / | / | / | 838 | Rc", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "Base", "pseudocode": "CopyPasteState ← ABORT", "special_registers": "N/A", "programming_notes": "Use cpabort to safely terminate an ongoing copy-paste sequence, preventing any subsequent paste operations from completing with the reserved data. This is useful in error handling scenarios where a copy operation needs to be aborted without allowing further processing of the copied data. Ensure that cpabort is called at the appropriate privilege level and consider its impact on performance if used frequently.", "extended_mnemonics": [], "page_found": "Page 1457 - 1458", "example": "cpabort" }, { "mnemonic": "pmxvf32gerpp", "architecture": "PowerISA", "full_name": "Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive multiply, Positive accumulate", "summary": "Performs a prefixed masked VSX vector 32-bit floating-point GER rank-1 update with positive multiply and positive accumulate.", "description": "A prefixed MMA instruction that performs a masked rank-1 matrix update using 32-bit floating-point elements, with positive multiply (no sign flip) and positive accumulate semantics. The prefix word controls masking and additional configuration. This instruction requires MMA support and updates the accumulator register; no condition registers are directly modified by this operation.", "syntax": "pmxvf32gerpp", "operands": [], "encoding": { "format": "MMIRR:XX3-form", "hex_opcode": "0x07900000EC0000D0", "length": "32", "binary_pattern": "59 | AT | / | XA | XB | 26 | AX | BX | /", "bit_positions": "0:5 | 6:8 | 9:10 | 11:15 | 16:20 | 21:28 | 29 | 30 | 31" }, "extension": "MMA", "pseudocode": "Accumulator ← Accumulator + (masked_multiply_by_vsrX(XA) ⊗ masked_multiply_by_vsrY(XB))", "special_registers": "N/A", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.", "extended_mnemonics": [], "page_found": "Page 1458 - 1459", "example": "pmxvf32gerpp" }, { "mnemonic": "drrnd.", "architecture": "PowerISA", "full_name": "DFP Reround", "summary": "Rerounds a decimal floating-point number to the specified precision.", "description": "Rerounds a decimal floating-point number from FRB to the precision specified by the rounding mode control, placing the result in FRA and setting CR1 based on the result (if Rc=1). The instruction handles overflow, underflow, and inexact exceptions according to FPSCR settings. This instruction requires Decimal Floating-Point support and modifies CR1 and FPSCR when Rc is set.", "syntax": "drrnd. FRT,FRA,FRB,RMC", "operands": [ { "name": "FRT", "desc": "Target Floating-Point Register" }, { "name": "FRA", "desc": "Source Floating-Point Register containing the reference significance" }, { "name": "FRB", "desc": "Source Floating-Point Register containing the value to be rounded" }, { "name": "RMC", "desc": "Rounding Mode Control" }, { "name": "k", "desc": "Number of significant digits" } ], "encoding": { "format": "Z23-form", "hex_opcode": "0xEC000046", "length": "32", "binary_pattern": "0 | FRT | FRA | FRB | RMC | Rc", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "Decimal Floating-Point", "pseudocode": "FRA ← dround(FRB, RMC)\nif Rc = 1 then CR1 ← (FRA_exception_flags)", "special_registers": "FPSCR, CR0", "programming_notes": "The drrnd instruction is used to reround a decimal floating-point number in register RA according to the rounding mode specified in the FPSCR. Ensure that the FPSCR's rounding mode is set appropriately before executing this instruction to achieve the desired precision. This instruction operates at user privilege level and does not raise exceptions under normal circumstances, but it may alter the contents of CR0 if an exception occurs during execution.", "extended_mnemonics": [], "page_found": "Page 252 - 254", "example": "drrnd. r4, r5" }, { "mnemonic": "lvehx", "architecture": "PowerISA", "full_name": "Load Vector Element Halfword Indexed X-form", "summary": "Loads a halfword element from memory into the corresponding halfword element of a vector register, with the address computed as the sum of RA and RB, aligned to a halfword boundary.", "description": "Loads a halfword (16-bit) element from memory at the address formed by RA + RB into the corresponding halfword element of vector register VRT. The effective address is aligned to a halfword boundary. This is a VMX/AltiVec instruction with no effect on condition or status registers.", "syntax": "lvehx VX,RA,RB", "operands": [ { "name": "VX", "desc": "Target VSX Register" }, { "name": "RA", "desc": "Base Address General Purpose Register" }, { "name": "RB", "desc": "Index General Purpose Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C00004E", "length": "32", "binary_pattern": "31 | VRT | RA | RB | 39 | /", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "VMX (AltiVec)", "pseudocode": "EA ← (RA) + (RB)\nVRT[element] ← MEM(EA, 2)", "special_registers": "N/A", "programming_notes": "The lvehx instruction loads a halfword from memory into a specific element of a vector register. Ensure the effective address is halfword-aligned to avoid alignment faults. The operation does not require any special privileges, but it may raise an exception if the access violates memory protection rules.", "extended_mnemonics": [], "page_found": "Page 1467 - 1468", "example": "lvehx v1, r4, r5" }, { "mnemonic": "plxv", "architecture": "PowerISA", "full_name": "Prefixed Load VSX Vector 8LS:D-form", "summary": "Loads a 128-bit VSX vector from memory into a VSX register using a prefixed instruction with a large displacement.", "description": "Loads a 128-bit VSX vector from memory into VSX register RT using a prefixed instruction with a 34-bit signed displacement. The address is computed as RA + displacement (scaled by 4). This is a VSX instruction requiring the VSX category and the Prefixed instruction set.", "syntax": "plxv RT,RA,RB", "operands": [ { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "RB", "desc": "Source General Purpose Register" } ], "encoding": { "format": "D-form", "hex_opcode": "0x04000000C8000000", "length": "64", "binary_pattern": "000001 | 000 | Rc | .//.. | RT | RA | RB", "bit_positions": "0:5 | 6:8 | 9 | 10 | 11:15 | 16:20 | 21:63" }, "extension": "Prefixed", "pseudocode": "EA ← (RA) + (DQ || Disp)\nRT ← MEM(EA, 16)", "special_registers": "N/A", "programming_notes": "The plxv instruction is used for loading a 128-bit VSX vector from memory into a target register, using an extended displacement field provided by the prefix word. Ensure that the base address register (RA) contains the correct pointer or is zero if no base address is needed. This instruction requires the VSX facility and is available in PowerISA v3.1 and later.", "extended_mnemonics": [], "page_found": "Page 1470 - 1471", "example": "plxv r3, r4, r5" }, { "mnemonic": "pmxvf64gernn", "architecture": "PowerISA", "full_name": "Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate", "summary": "Performs a prefixed masked VSX vector 64-bit floating-point GER (rank-1 update) with negative multiply and negative accumulate.", "description": "A prefixed MMA instruction that performs a masked 64-bit floating-point GER (generalized matrix element rank-1 update) with negative multiply and negative accumulate into an accumulator. The operation updates a 4×4 matrix accumulator using VSX registers with optional row and column masking. This instruction requires MMA support and updates FPSCR.", "syntax": "pmxvf64gernn AT,XAp,XB,XMSK,YMSK", "operands": [ { "name": "AT", "type": "ACC", "desc": "Target accumulator. ACC[AT] holds a 4x2 matrix of double-precision values." }, { "name": "XAp", "type": "VSR", "desc": "Source VSR pair (even/odd). VSR[XAp] and VSR[XAp+1] are concatenated to supply the four row values." }, { "name": "XB", "type": "VSR", "desc": "Source VSR supplying the two column values." }, { "name": "XMSK", "type": "imm4", "desc": "4-bit row mask. Row i is updated only when bit i is 1; a masked-off element is set to zero." }, { "name": "YMSK", "type": "imm2", "desc": "2-bit column mask. Column j is updated only when bit j is 1; a masked-off element is set to zero." } ], "encoding": { "format": "MMIRR:XX3-form", "hex_opcode": "0x07900000EC0007D0", "length": "64", "binary_pattern": "000001 | 11100 | 1 | Rc | // | ///.. | ?", "bit_positions": "0:5 | 6:10 | 11 | 12 | 13 | 14 | 15:63" }, "extension": "MMA", "pseudocode": "vsrcX ← VSR[XAp] || VSR[XAp+1]\nvsrcY ← VSR[XB]\ndo i = 0 to 3\n do j = 0 to 1\n if XMSK.bit[i]=1 & YMSK.bit[j]=1 then\n ACC[AT][i].dword[j] ← -( vsrcX.dword[i] × vsrcY.dword[j] + ACC[AT][i].dword[j] )\n else\n ACC[AT][i].dword[j] ← 0", "special_registers": "N/A", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.", "extended_mnemonics": [], "page_found": "Page 1471 - 1472", "example": "pmxvf64gernn" }, { "mnemonic": "pstfs", "architecture": "PowerISA", "full_name": "Prefixed Store Floating-Point Single MLS:D-form", "summary": "Stores a single-precision floating-point value from a register to memory.", "description": "The double-precision floating-point value in register FRS is converted to single-precision and stored as a 32-bit single-precision value at the effective address (EA). The EA is formed by adding the sign-extended 34-bit immediate displacement D to the contents of general-purpose register RA (or zero if RA=0). This is the prefixed form of the stfs instruction, allowing a larger displacement field than the non-prefixed variant.", "syntax": "pstfs FRT,RA,RB", "operands": [ { "name": "FRT", "desc": "Target Floating-Point Register" }, { "name": "RA", "desc": "Base General Purpose Register" }, { "name": "RB", "desc": "Offset General Purpose Register" } ], "encoding": { "format": "MLS:D-form", "hex_opcode": "0x06000000D0000000", "length": "64", "binary_pattern": "000001 | 100 | Rc | .//.. | FRT | RA | RB", "bit_positions": "0:5 | 6:10 | 11 | 12:16 | 17:21 | 22:26 | 27:63" }, "extension": "Floating-Point", "pseudocode": "EA ← (RA|0) + D\nMEM(EA, 4) ← SINGLE(FRS)", "special_registers": "N/A", "programming_notes": "The pstfs instruction is useful for storing single-precision floating-point values with an extended displacement. Ensure that the EA calculation does not result in an invalid memory address to avoid exceptions. This instruction operates at user privilege level and requires proper alignment of the EA for optimal performance.", "extended_mnemonics": [], "page_found": "Page 1472 - 1473", "example": "pstfs f1, r4, r5" }, { "mnemonic": "srad.", "architecture": "PowerISA", "full_name": "Shift Right Algebraic Doubleword", "summary": "Shifts the contents of a doubleword register right algebraically, shifting in sign bits.", "description": "The contents of register RA are shifted right by the number of bits specified by the low-order 7 bits of register RB. Bits shifted out of position 63 are lost. Sign bits are shifted into the high-order bits, replicating the sign bit (RA[0]). If the shift amount is greater than 63, each bit of the result is equal to the sign bit of RA. The XER[CA] bit is set if the result is negative and any '1' bits are shifted out; otherwise XER[CA] is cleared. If the Rc bit is set, CR0 is updated.", "syntax": "srad. RT,RA,RB", "operands": [ { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RA", "desc": "Source General Purpose Register" }, { "name": "RB", "desc": "Source General Purpose Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C000634", "length": "32", "binary_pattern": "31 | RS | RA | RB | 794 | Rc", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "Base", "pseudocode": "n ← rB[58:63]\nif rB[57] = 0 then\n r ← ROTL64(rA, 64-n)\n mask ← MASK(n, 63)\n rT ← r & mask | (64)rA[0] & ¬mask\nelse\n rT ← (64)rA[0]\nXER[CA] ← rA[0] & (rT ≠ rA)\nXER[CA32] ← rA[0] & (rT[32:63] ≠ rA[32:63])", "special_registers": "CR0, XER", "programming_notes": "The srad. instruction is commonly used for right-shifting signed integers while preserving the sign bit. Be cautious with shift amounts greater than 63, as they result in a full replication of the sign bit. The XER[CA] flag indicates if negative bits were shifted out, which can be useful for overflow detection. Ensure that register RB contains a valid shift amount to avoid unexpected results.", "extended_mnemonics": [], "page_found": "Page 1473 - 1474", "example": "srad. r3, r4, r5" }, { "mnemonic": "stvxl", "architecture": "PowerISA", "full_name": "Store Vector Indexed Last", "summary": "Stores a vector element to memory, with the last element being stored if the index is out of bounds.", "description": "Stores a vector from register VS to memory at the address formed by RA + RB. The address is aligned to the vector element size. This is a Base category instruction with no effect on condition or status registers.", "syntax": "stvxl VS,RA,RB", "operands": [ { "name": "VS", "desc": "Vector Register" }, { "name": "RA", "desc": "Base Address General Purpose Register" }, { "name": "RB", "desc": "Index General Purpose Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0x7C0003CE", "length": "32", "binary_pattern": "31 | VS | RA | RB | 487 | /", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "Base", "pseudocode": "EA ← (RA) + (RB)\nMEM(EA, 16) ← VS", "special_registers": "N/A", "programming_notes": "Use stvxl when storing vector data with a 'last touch' hint, potentially reducing cache line allocations. Ensure RA and RB are correctly set to form the aligned 16-byte address. This instruction is useful for optimizing memory usage in performance-critical sections.", "extended_mnemonics": [], "page_found": "Page 1474 - 1475", "example": "stvxl vs1, r4, r5" }, { "mnemonic": "xvcvuxdsp", "architecture": "PowerISA", "full_name": "VSX Vector Convert with round Unsigned Doubleword to Single-Precision format", "summary": "Converts an unsigned doubleword to a single-precision floating-point value with rounding.", "description": "Converts a 64-bit unsigned doubleword integer (in the doubleword elements of VS64) to 32-bit single-precision floating-point format with rounding and stores the result in the corresponding word elements of VS32. This is a VSX instruction that performs IEEE-compliant rounding and may update FPSCR.", "syntax": "xvcvuxdsp VS32,VS64", "operands": [ { "name": "VS32", "desc": "Target Vector Register" }, { "name": "VS64", "desc": "Source Vector Register" } ], "encoding": { "format": "XX2-form", "hex_opcode": "0xF00006A0", "length": "32", "binary_pattern": "111100 | VS32 | // | VS64 | 11010 | 1000", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "VSX", "pseudocode": "for i in 0 to 1:\n VS32[2*i:2*i+1] ← CONVERT_UNSIGNED_DWORD_TO_SINGLE_PRECISION_ROUNDED(VS64[i])", "special_registers": "N/A", "programming_notes": "This instruction is useful for converting unsigned 64-bit integers to single-precision floating-point numbers. Ensure that the source vector elements are properly aligned and consider the current rounding mode's effect on conversion results. The target vector register will have its lower words zeroed out, so handle this if you need to preserve data in those positions.", "extended_mnemonics": [], "page_found": "Page 1489 - 1490", "example": "xvcvuxdsp vs1, vs1" }, { "mnemonic": "xvnmsubmdp", "architecture": "PowerISA", "full_name": "VSX Vector Negative Multiply-Subtract Type-M Double-Precision", "summary": "Performs a negative multiply-subtract operation on double-precision floating-point values.", "description": "For each double-precision floating-point element, the instruction multiplies the corresponding elements of VRA and VRT, subtracts the corresponding element of VRB from the product, negates the result, and stores it in VRT. This is the Type-M variant, meaning VRT serves as both a source operand (multiplicand) and the destination register. The operation is performed in double-precision floating-point arithmetic with IEEE 754 rounding rules applied.", "syntax": "xvnmsubmdp VRT, VRA, VRB, VRC", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" }, { "name": "VRC", "desc": "Source Vector Register" } ], "encoding": { "format": "XX3-form", "hex_opcode": "0xF00007C8", "length": "32", "binary_pattern": "60 | XT | XA | XB | 1992", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VSX", "pseudocode": "do i = 0 to 1\n VRT.dword[i] ← RoundFP64(-(FP64(VRA.dword[i]) × FP64(VRT.dword[i])) - FP64(VRB.dword[i]))", "special_registers": "FPSCR", "programming_notes": "This instruction is commonly used in scenarios requiring complex floating-point arithmetic operations, such as in scientific computations or graphics processing. Be cautious of potential overflow or underflow conditions due to the nature of double-precision multiplication and subtraction. Ensure that VRT is properly aligned for optimal performance, as misalignment can lead to significant slowdowns. This instruction operates at user privilege level but may generate exceptions if invalid operations occur, such as division by zero or NaN results.", "extended_mnemonics": [], "page_found": "Page 1491 - 1492", "example": "xvnmsubmdp v1, v2, v3, v4" }, { "mnemonic": "xscvqpudz", "architecture": "PowerISA", "full_name": "VSX Scalar Convert with round to zero Quad-Precision to Unsigned Doubleword format X-form", "summary": "Converts a quad-precision floating-point value to an unsigned doubleword integer, rounding towards zero.", "description": "The instruction converts the quad-precision floating-point value in VSR[VRB+32] to an unsigned doubleword integer, rounding towards zero. The result is placed into doubleword element 0 of VSR[VRT+32]. Doubleword element 1 of VSR[VRT+32] is set to 0.", "syntax": "xscvqpudz VRT,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0xFC110688", "length": "32", "binary_pattern": "63 | VRT | 17 | VRB | 836 | /", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "extension": "VSX", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nreset_xflags()\nsrc ←bfp_CONVERT_FROM_BFP128(VSR[VRB+32])\nvxsnan_flag ←0\nvxcvi_flag ←0\nif src.class.QNaN=1 | src.class.SNaN=1 then do\n result ←0x0000_0000_0000_0000\n vxsnan_flag ←src.class.SNaN\n vxcvi_flag ←1\nend else if src.class.Infinity=1 then do\n vxcvi_flag ←1\n if src.sign=0 then\n result ←0xFFFF_FFFF_FFFF_FFFF\n else\n result ←0x0000_0000_0000_0000\n end\nend else if src.class.Zero then\n result ←0x0000_0000_0000_0000\nelse do\n rnd ←bfp_ROUND_TO_INTEGER(0b001,src)\n if bfp_COMPARE_GT(rnd, +264-1) then do\n result ←0xFFFF_FFFF_FFFF_FFFF\n vxcvi_flag ←1\n end else if bfp_COMPARE_LT(rnd, 0) then do\n result ←0x0000_0000_0000_0000\n vxcvi_flag ←1\n end else do\n result ←ui64_CONVERT_FROM_BFP(rnd)\n if xx_flag=1 then SetFX(FPSCR.XX)\n end\nend\nif vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\nif vxcvi_flag=1 then SetFX(FPSCR.VXCVI)\nvx_flag ←vxsnan_flag | vxcvi_flag\nex_flag ←FPSCR.VE & vx_flag\nif ex_flag=0 then do\n VSR[VRT+32].dword[0] ←result\n VSR[VRT+32].dword[1] ←0x0000_0000_0000_0000\nend\nFPSCR.FR ←(vx_flag=0) & inc_flag\nFPSCR.FI ←(vx_flag=0) & xx_flag", "special_registers": "FPSCR.FPRF, FPSCR.FR, FPSCR.FI, FPSCR.XX, FPSCR.VXSNAN, FPSCR.VXCVI", "programming_notes": "This instruction is used to convert a quad-precision floating-point number to an unsigned doubleword integer, rounding towards zero. Ensure the VSX facility is enabled; otherwise, it will raise an exception. Be cautious of NaNs and infinities, as they result in specific values and set condition flags. The operation does not require any particular alignment or privilege level.", "extended_mnemonics": [], "page_found": "Page 865 - 866", "example": "xscvqpudz v1, v3" }, { "mnemonic": "mulldo", "architecture": "PowerISA", "full_name": "Multiply Low Doubleword (Overflow)", "summary": "Multiplies the contents of two registers and places the low-order 64 bits of the product into a target register.", "syntax": "mulldo RT,RA,RB", "encoding": { "format": "XO-form", "binary_pattern": "31 | RT | RA | RB | OE | 233 | Rc", "hex_opcode": "0x7C0001D2", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "OE", "clean": "OE" }, { "raw": "233", "clean": "233" }, { "raw": "Rc", "clean": "Rc" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21 | 22:30 | 31" }, "operands": [ { "name": "RT", "desc": "Target" }, { "name": "RA", "desc": "Src 1" }, { "name": "RB", "desc": "Src 2" } ], "pseudocode": "prod0:127 ← (RA) × (RB)\nRT ← prod0:63\nif OE=1 then\n OV and OV32 are set to 1 if the product cannot be represented in 64 bits.", "example": "mulld r3, r4, r5", "example_note": "64-bit multiply.", "extension": "Base", "description": "The 64-bit operands are (RA) and (RB). The low-order 64 bits of the 128-bit product of the operands are placed into register RT. Both operands and the product are interpreted as signed integers.", "special_registers": "CR0, XER", "programming_notes": "The XO-form Multiply instructions may execute faster on some implementations if RB contains the operand having the smaller absolute value.", "page_found": "Page 120 - 122" }, { "mnemonic": "not.", "architecture": "PowerISA", "full_name": "Complement Register (Record)", "summary": "Complements the contents of one register and places the result into another register.", "syntax": "not. Rx,Ry", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RS | 124 | /", "hex_opcode": "0x7C0000F8", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RS", "clean": "RS" }, { "raw": "124", "clean": "124" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "RS", "desc": "Source" }, { "name": "Rx", "desc": "Target General Purpose Register" }, { "name": "Ry", "desc": "Source General Purpose Register" } ], "extension": "Base", "description": "The 'not' instruction complements the contents of register Ry and places the result into register Rx. This mnemonic can be coded with a final '.' to cause the Rc bit to be set in the underlying instruction.", "pseudocode": "if 'not' then\n Rx <- ~Ry\nif 'not.' then\n Rx <- ~Ry\n Rc = 1", "special_registers": "CR0, XER", "page_found": "Page 1001 - 1002", "programming_notes": "The 'not' instruction is commonly used for bitwise negation of a register's contents. Be cautious with the '.' suffix as it affects the condition register (CR0) by setting the Rc bit, which can impact subsequent conditional branches. Ensure that the registers are properly aligned and accessible at the privilege level required for execution.", "example": "not r3, r4" }, { "mnemonic": "rlwinm.", "architecture": "PowerISA", "full_name": "Rotate Left Word Immediate Then AND with Mask (Record)", "summary": "Rotates the low-order 32 bits of a register left by a specified number of bit positions, generates a mask, and performs an AND operation.", "syntax": "rlwinm. RA,RS,SH,MB,ME", "encoding": { "format": "M-form", "binary_pattern": "21 | RS | RA | SH | MB | ME | Rc", "hex_opcode": "0x54000000", "visual_parts": [ { "raw": "21", "clean": "21" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "SH", "clean": "SH" }, { "raw": "MB", "clean": "MB" }, { "raw": "ME", "clean": "ME" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:30 | 31" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "RS", "desc": "Source" }, { "name": "SH", "desc": "Shift" }, { "name": "MB", "desc": "Mask Begin" }, { "name": "ME", "desc": "Mask End" } ], "extension": "Base", "description": "The contents of register RS are rotated32 left SH bits. A mask is generated having 1-bits from bit MB+32 through bit ME+32 and 0-bits elsewhere. The rotated data are ANDed with the generated mask and the result is placed into register RA.", "pseudocode": "if 'rlwinm' then\n n ← SH\n r ← ROTL32((RS)32:63, n)\n m ← MASK(MB+32, ME+32)\n RA ← r & m", "special_registers": "CR0", "programming_notes": "Let RSL represent the low-order 32 bits of register RS, with the bits numbered from 0 through 31. rlwinm can be used to extract an n-bit field that starts at bit position b in RSL, right-justified into the low-order 32 bits of register RA (clearing the remaining 32-n bits of the low-order 32 bits of RA), by setting SH=b+n, MB=32-n, and ME=31. It can be used to extract an n-bit field that starts at bit position b in RSL, left-justified into the low-order 32 bits of register RA (clearing the remaining 32-n bits of the low-order 32 bits of RA), by setting SH=b, MB = 0, and ME=n-1. It can be used to rotate the contents of the low-order 32 bits of a register left (right) by n bits, by setting SH=n (32-n), MB=0, and ME=31. It can be used to shift the contents of the low-order 32 bits of a register right by n bits, by setting SH=32-n, MB=n, and ME=31. It can be used to clear the high-order b bits of the low-order 32 bits of the contents of a register and then shift the result left by n bits, by setting SH=n, MB=b-n, and ME=31-n. It can be used to clear the low-order n bits of the low-order 32 bits of a register, by setting SH=0, MB=0, and ME=31-n.", "extended_mnemonics": [ { "mnemonic": "extlwi", "equivalent_to": "rlwinm RA,RS,b,0,n-1" }, { "mnemonic": "srwi", "equivalent_to": "rlwinm RA,RS,32-n,n,31" }, { "mnemonic": "clrrwi", "equivalent_to": "rlwinm RA,RS,0,0,31-n" }, { "name": "extlwi", "equivalent_to": "rlwinm RA,RS,b,0,n-1" }, { "name": "srwi", "equivalent_to": "rlwinm RA,RS,32-n,n,31" }, { "name": "clrrwi", "equivalent_to": "rlwinm RA,RS,0,0,31-n" } ], "page_found": "Page 142 - 144", "example": "rlwinm r4, r3, 3, 0, 31" }, { "mnemonic": "rlwnm.", "architecture": "PowerISA", "full_name": "Rotate Left Word Then AND with Mask (Record)", "summary": "Rotates the contents of register RS left by the number of bits specified by (RB)59:63, and then performs a bitwise AND operation with a mask.", "syntax": "rlwnm. RT,RS,RB,MB,ME", "encoding": { "format": "M-form", "binary_pattern": "23 | RS | RA | RB | MB | ME | Rc", "hex_opcode": "0x5C000000", "visual_parts": [ { "raw": "23", "clean": "23" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "MB", "clean": "MB" }, { "raw": "ME", "clean": "ME" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:30 | 31" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "RS", "desc": "Source" }, { "name": "RB", "desc": "Shift Reg" }, { "name": "MB", "desc": "Mask Begin" }, { "name": "ME", "desc": "Mask End" }, { "name": "RT", "desc": "Target General Purpose Register" } ], "extension": "Base", "description": "The contents of register RS are rotated 32 left the number of bits specified by (RB)59:63. A mask is generated having 1-bits from bit MB+32 through bit ME+32 and 0-bits elsewhere. The rotated data are ANDed with the generated mask and the result is placed into register RA.", "pseudocode": "if 'rlwnm' then\n n ← (RB)59:63\n r ← ROTL32((RS)32:63, n)\n m ← MASK(MB+32, ME+32)\n RA ← r & m\nelse if 'rlwnm.' then\n n ← (RB)59:63\n r ← ROTL32((RS)32:63, n)\n m ← MASK(MB+32, ME+32)\n RA ← r & m", "special_registers": "CR0", "programming_notes": "RS, with the bits numbered from 0 through 31. rlwnm can be used to extract an n-bit field that starts at variable bit position b in RSL, right-justified into the low-order 32 bits of register RA (clearing the remaining 32-n bits of the low-order 32 bits of RA), by setting RB59:63=b+n, MB=32-n, and ME=31. It can be used to extract an n-bit field that starts at variable bit position b in RSL, left-justified into the low-order 32 bits of register RA (clearing the remaining 32-n bits of the low-order 32 bits of RA), by setting RB59:63=b, MB = 0, and ME=n-1. It can be used to rotate the contents of the low-order 32 bits of a register left (right) by variable n bits, by setting RB59:63=n (32-n), MB=0, and ME=31.", "extended_mnemonics": [ { "mnemonic": "rotlw", "equivalent_to": "rlwnm RA,RS,RB,0,31" }, { "mnemonic": "rotlw.", "equivalent_to": "rlwnm. RA,RS,RB,0,31" } ], "page_found": "Page 144 - 146", "example": "rlwnm r3, r3, r5, 0, 31" }, { "mnemonic": "rldic.", "architecture": "PowerISA", "full_name": "Rotate Left Doubleword Immediate Clear (Record)", "summary": "Rotates a 64-bit register left, then clears bits based on a mask. 64-bit equivalent of rlwinm.", "syntax": "rldic. RT,RA,RB,MB", "encoding": { "format": "MD-form", "binary_pattern": "30 | RS | RA | SH | MB | 2 | sh Rc", "hex_opcode": "0x78000008", "visual_parts": [ { "raw": "30", "clean": "30" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "SH", "clean": "SH" }, { "raw": "MB", "clean": "MB" }, { "raw": "00", "clean": "00" }, { "raw": "Rc", "clean": "Rc" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "RS", "desc": "Source" }, { "name": "SH", "desc": "Shift Amount" }, { "name": "MB", "desc": "Mask Begin" }, { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RB", "desc": "Immediate Value for SH (Shift Amount)" } ], "pseudocode": "if 'rldic' then\n SH ← sh5 || sh0:4\n r ← ROTL64((RS), SH)\n MB ← mb5 || mb0:4\n m ← MASK(MB, 63-SH)\n RA ← r & m", "example": "rldic r3, r4, 4, 10", "example_note": "Rotate left 4, clear bits 0-9.", "extension": "Base", "description": "The contents of register RS are rotated64 left SH bits. A mask is generated having 1-bits from bit MB through bit 63-SH and 0-bits elsewhere. The rotated data are ANDed with the generated mask and the result is placed into register RA.", "special_registers": "CR0", "programming_notes": "rldic can be used to clear the high-order b bits of the contents of a register and then shift the result left by n bits, by setting SH=n and MB=b-n. It can be used to clear the high-order n bits of a register, by setting SH=0 and MB=n.", "extended_mnemonics": [ { "mnemonic": "clrlsldi", "equivalent_to": "rldic RA,RS,n,b-n" }, { "mnemonic": "clrlsldi.RA,RS,b,n", "equivalent_to": "rldic. RA,RS,n,b-n" } ], "page_found": "Page 146 - 148" }, { "mnemonic": "extsb.", "architecture": "PowerISA", "full_name": "Extend Sign Byte (Record)", "summary": "Sign extends the low byte of a register to the full width.", "syntax": "extsb. RT,RS", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | 954 | /", "hex_opcode": "0x7C000774", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "954", "clean": "954" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "RS", "desc": "Source" }, { "name": "RT", "desc": "Target General Purpose Register" } ], "extension": "Base", "description": "The contents of the specified byte (RS)56 are placed into RA56:63, and RA0:55 are filled with a copy of (RS)56.", "pseudocode": "if 'extsb' then\n s ← (RS)56\n RA56:63 ← (RS)56:63\n RA0:55 ← 56s\nelse if 'extsb.' then\n s ← (RS)56\n RA56:63 ← (RS)56:63\n RA0:55 ← 56s", "special_registers": "CR0, XER", "page_found": "Page 136 - 138", "programming_notes": "The extsb instruction is commonly used to sign-extend a byte value into a full word. Ensure the source register contains the correct byte to avoid unexpected results. This instruction operates at user privilege level and does not generate exceptions under normal conditions.", "example": "extsb r3, r3" }, { "mnemonic": "extsw.", "architecture": "PowerISA", "full_name": "Extend Sign Word (Record)", "summary": "Sign extends the low word (32-bit) to 64 bits.", "syntax": "extsw. RT,RS", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | 986 | /", "hex_opcode": "0x7C0007B4", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "986", "clean": "986" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "RS", "desc": "Source" }, { "name": "RT", "desc": "Target General Purpose Register" } ], "extension": "Base", "description": "The contents of register RS are extended to fill the upper 32 bits of register RA, and the lower 32 bits of RA are filled with a copy of the upper 32 bits of RS.", "pseudocode": "if 'extsw' then\n s ← (RS)32\n RA32:63 ← (RS)32:63\n RA0:31 ← 32s\nelse if 'extsw.' then\n s ← (RS)32\n RA32:63 ← (RS)32:63\n RA0:31 ← 32s", "special_registers": "CR0, XER", "page_found": "Page 138 - 140", "programming_notes": "The extsw instruction is commonly used to sign-extend a 32-bit value in RS to a 64-bit value in RA. Ensure that the source register RS contains the correct 32-bit signed integer to avoid unexpected results. This instruction operates at user privilege level and does not generate exceptions under normal circumstances.", "example": "extsw r3, r3" }, { "mnemonic": "orc.", "architecture": "PowerISA", "full_name": "OR with Complement (Record)", "summary": "Performs a bitwise OR operation between the contents of two registers and the complement of the third register.", "syntax": "orc. RA,RS,RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 412 | /", "hex_opcode": "0x7C000338", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "412", "clean": "412" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RA", "desc": "Target" }, { "name": "RS", "desc": "Src A" }, { "name": "RB", "desc": "Src B" } ], "extension": "Base", "description": "The contents of register RS are ORed with the complement of the contents of register RB, and the result is placed into register RA.", "pseudocode": "if 'orc' then\n RA <- (RS) | ¬(RB)\nelse if 'orc.' then\n RA <- (RS) | ¬(RB)\n CR0 <- result of OR operation", "special_registers": "CR0", "page_found": "Page 135 - 136", "programming_notes": "The orc instruction is useful for setting bits in a register based on the complement of another register. Be cautious with bit manipulation as incorrect usage can lead to unexpected results. The instruction operates at user privilege level and does not generate exceptions under normal conditions. Performance may vary depending on the specific implementation and architecture.", "example": "orc r4, r3, r5" }, { "mnemonic": "mffs.", "architecture": "PowerISA", "full_name": "Move From FPSCR (Record)", "summary": "Moves the contents of the Floating-Point Status and Control Register (FPSCR) into a floating-point register.", "syntax": "mffs. FRT", "encoding": { "format": "X-form", "binary_pattern": "63 | FRT | / | / | 583 | Rc", "hex_opcode": "0xFC00048E", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "583", "clean": "583" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" } ], "extension": "Floating-Point", "description": "Moves the contents of the Floating-Point Status and Control Register (FPSCR) into floating-point register FRT. If Rc=1 (mffs.), the instruction updates CR1 based on the moved FPSCR value. This is a privileged instruction that does not alter FPSCR itself.", "pseudocode": "FRT ← FPSCR\nif Rc = 1 then\n CR1 ← (FRT[0:3])", "special_registers": "FPSCR, CR1, (if, Rc=1), CR0", "extended_mnemonics": [ "mffs.", "mffs" ], "page_found": "Page 216 - 218", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "mffs f1" }, { "mnemonic": "mtfsf.", "architecture": "PowerISA", "full_name": "Move To FPSCR Fields (Record)", "summary": "Moves the contents of a floating-point register into specified fields of the FPSCR.", "syntax": "mtfsf. FLM,FRB,L,W", "encoding": { "format": "XFL-form", "binary_pattern": "63 | L | FLM | W | FRB | 711 | /", "hex_opcode": "0xFC00058E", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "L", "clean": "L" }, { "raw": "FLM", "clean": "FLM" }, { "raw": "W", "clean": "W" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "711", "clean": "711" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "FLM", "desc": "Field Mask" }, { "name": "FRB", "desc": "Source" }, { "name": "L", "desc": "Load Control Bit" }, { "name": "W", "desc": "Word Select Bit" } ], "extension": "Floating-Point", "description": "The FPSCR is modified as specified by the FLM, L, and W fields. If L=0, the contents of register FRB are placed into the FPSCR under control of the W field and the field mask specified by FLM. If L=1, the contents of register FRB are placed into the FPSCR.", "pseudocode": "if 'mtfsf' then\n if L=0 then\n for i from 0 to 7 do\n if FLMi=1 then\n FPSCR[k] <- FRB[i+8*(1-W)]\n end if\n end for\n else if L=1 then\n FPSCR <- FRB\n end if\nend if", "special_registers": "FPSCR, CR1", "programming_notes": "Bits 33 and 34 (FEX and VX) cannot be explicitly reset.\nIf L=1 or if L=0 and FPSCR32:35 is specified, bits 32 (FX) and 35 (OX) are set to the values of (FRB)32 and (FRB)35.", "extended_mnemonics": [ "mtfsf FLM,FRB" ], "page_found": "Page 220 - 222", "example": "mtfsf 0xFF, f3, 0, 0" }, { "mnemonic": "frsqrte.", "architecture": "PowerISA", "full_name": "Floating Reciprocal Square Root Estimate (Record)", "summary": "Estimates the reciprocal of the square root of a floating-point operand.", "syntax": "frsqrte. FRT,FRB", "encoding": { "format": "A-form", "binary_pattern": "63 | FRT | 0 | 0 | FRB | 26 | /", "hex_opcode": "0xFC000034", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "26", "clean": "26" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" } ], "extension": "Floating-Point", "description": "A estimate of the reciprocal of the square root of the floating-point operand in register FRB is placed into register FRT. The estimate placed into register FRT is correct to a precision of one part in 32 of the reciprocal of the square root of (FRB).", "special_registers": "FPSCR, CR1", "page_found": "Page 201 - 202", "pseudocode": "FRT ← estimate(1 / √FRB)", "programming_notes": "The frsqrte instruction provides a fast, approximate reciprocal square root calculation. It is useful for performance-critical applications where precision can be traded for speed. Ensure the input in FRB is positive to avoid undefined behavior. The result may need refinement for higher precision applications.", "example": "frsqrte f1, f3" }, { "mnemonic": "vcmpequb.", "architecture": "PowerISA", "full_name": "Vector Compare Equal Byte (Record)", "summary": "Compares two vector registers element by element as unsigned bytes and sets the target vector register based on the comparison.", "syntax": "vcmpequb. VRT,VRA,VRB", "encoding": { "format": "VC-form", "binary_pattern": "18 | VRT | VRA | VRB | Rc", "hex_opcode": "0x10000006", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "6", "clean": "6" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "The Vector Integer Compare instructions compare two VSRs element by element, interpreting the elements as unsigned or signed integers depending on the instruction, and set the corresponding element of the target VSR to all 1s if the relation being tested is true and to all 0s if the relation being tested is false.", "pseudocode": "if MSR.VEC=0 then Vector_Unavailable()\nall_true ←1\nall_false ←1\ndo i = 0 to 15\n src1 ←VSR[VRA+32].byte[i]\n src2 ←VSR[VRB+32].byte[i]\n if src1 = src2 then do\n VSR[VRT+32].byte[i] ←0xFF\n all_false ←0\n end\n else do\n VSR[VRT+32].byte[i] ←0x00\n all_true ←0\n end\nend\nif Rc=1 then\n CR.field[6] ←all_true || 0b0 || all_false || 0b0", "special_registers": "CR6", "programming_notes": "vcmpequb[.], vcmpequh[.], vcmpequw[.], and vcmpequd[.] can be used for unsigned or signed integers.", "page_found": "Page 413 - 414", "example": "vcmpequb v1, v2, v3" }, { "mnemonic": "vcmpequh.", "architecture": "PowerISA", "full_name": "Vector Compare Equal Halfword (Record)", "summary": "Compares each halfword of two vector registers and sets the corresponding halfword in the target register to all 1s if they are equal, otherwise all 0s.", "syntax": "vcmpequh. VRT,VRA,VRB", "encoding": { "format": "VC-form", "binary_pattern": "4 | VRT | VRA | VRB | Rc", "hex_opcode": "0x10000046", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "70", "clean": "70" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vcmpequh, each halfword of VSR[VRA+32] is compared with the corresponding halfword of VSR[VRB+32]. If they are equal, the corresponding halfword in VSR[VRT+32] is set to all 1s (0xFFFF); otherwise, it is set to all 0s (0x0000).", "pseudocode": "if MSR.VEC=0 then Vector_Unavailable()\n\nall_true ←1\nall_false ←1\ndo i = 0 to 7\n src1 ←VSR[VRA+32].hword[i]\n src2 ←VSR[VRB+32].hword[i]\n if src1 = src2 then do\n VSR[VRT+32].hword[i] ←0xFFFF\n all_false ←0\n end\n else do\n VSR[VRT+32].hword[i] ←0x0000\n all_true ←0\n end\nend\ndo i = 0 to 7\n src1 ←VSR[VRA+32].hword[i]\n src2 ←VSR[VRB+32].hword[i]\n if src1 = src2 then do\n VSR[VRT+32].hword[i] ←0xFFFF\n all_false ←0\n end\n else do\n VSR[VRT+32].hword[i] ←0x0000\n all_true ←0\n end\nend\nif Rc=1 then\n CR.field[6] ←all_true || 0b0 || all_false || 0b0", "special_registers": "CR6", "page_found": "Page 414 - 415", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "vcmpequh v1, v2, v3" }, { "mnemonic": "vcmpequd.", "architecture": "PowerISA", "full_name": "Vector Compare Equal Doubleword (Record)", "summary": "Compares two vector registers for equality on an unsigned doubleword basis and stores the result in a third vector register.", "syntax": "vcmpequd. VRT,VRA,VRB", "encoding": { "format": "VC-form", "binary_pattern": "4 | VRT | VRA | VRB | Rc | 199", "hex_opcode": "0x100000C7", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "199", "clean": "199" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21 | 22:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "Compares two vector registers element-wise for equality on an unsigned doubleword basis (2 64-bit elements) and stores a mask in the destination vector register, with all 1s where elements are equal and all 0s where unequal. When the record bit (.) is set, the CR6 field is updated to reflect whether any or all comparisons are equal.", "pseudocode": "for i in 0 to 1 do\n if VRA[i] = VRB[i] then\n VRT[i] ← 0xFFFF_FFFF_FFFF_FFFF\n else\n VRT[i] ← 0x0000_0000_0000_0000\nif Rc = 1 then CR6 ← comparison results", "special_registers": "CR6", "page_found": "Page 416 - 417", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "vcmpequd v1, v2, v3" }, { "mnemonic": "vcmpgtsb.", "architecture": "PowerISA", "full_name": "Vector Compare Greater Than Signed Byte (Record)", "summary": "Compares each byte of two vector registers and sets the corresponding result byte to all 1s if the signed byte in the first source register is greater than the signed byte in the second source register, otherwise sets it to all 0s.", "syntax": "vcmpgtsb. VRT,VRA,VRB", "encoding": { "format": "VC-form", "binary_pattern": "0 | VRT | VRA | VRB | Rc", "hex_opcode": "0x10000306", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "774", "clean": "774" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vcmpgtsb, each byte of VSR[VRA+32] is compared with the corresponding byte of VSR[VRB+32]. If the signed byte in VSR[VRA+32] is greater than the signed byte in VSR[VRB+32], then the corresponding byte in VSR[VRT+32] is set to all 1s (0xFF). Otherwise, it is set to all 0s (0x00).", "pseudocode": "if MSR.VEC=0 then Vector_Unavailable()\nall_true ←1\nall_false ←1\ndo i = 0 to 15\n src1 ←EXTS(VSR[VRA+32].byte[i])\n src2 ←EXTS(VSR[VRB+32].byte[i])\n if src1 > src2 then do\n VSR[VRT+32].byte[i] ←0xFF\n all_false ←0\n end\n else do\n VSR[VRT+32].byte[i] ←0x00\n all_true ←0\n end\nend\nif Rc=1 then\n CR.field[6] ←all_true || 0b0 || all_false || 0b0", "special_registers": "CR0, XER", "page_found": "Page 418 - 419", "extended_mnemonics": [ "vcmpgtsb." ], "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "vcmpgtsb v1, v2, v3" }, { "mnemonic": "vcmpgtsh.", "architecture": "PowerISA", "full_name": "Vector Compare Greater Than Signed Halfword (Record)", "summary": "Compares each halfword of two vector registers and sets the corresponding result element to all 1s if the first operand is greater than the second, otherwise all 0s.", "syntax": "vcmpgtsh. VRT,VRA,VRB", "encoding": { "format": "VC-form", "binary_pattern": "0 | VRT | VRA | VRB | Rc", "hex_opcode": "0x10000346", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "838", "clean": "838" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vcmpgtsh, each halfword of VSR[VRA+32] is compared with the corresponding halfword of VSR[VRB+32]. If the signed value in VSR[VRA+32].hword[i] is greater than that in VSR[VRB+32].hword[i], then VSR[VRT+32].hword[i] is set to 0xFFFF; otherwise, it is set to 0x0000.", "pseudocode": "if MSR.VEC=0 then Vector_Unavailable()\nall_true ←1\nall_false ←1\ndo i = 0 to 7\n src1 ←EXTS(VSR[VRA+32].hword[i])\n src2 ←EXTS(VSR[VRB+32].hword[i])\n if src1 > src2 then do\n VSR[VRT+32].hword[i] ←0xFFFF\n all_false ←0\n end\n else do\n VSR[VRT+32].hword[i] ←0x0000\n all_true ←0\n end\nend\nif Rc=1 then\n CR.field[6] ←all_true || 0b0 || all_false || 0b0", "special_registers": "CR6 (if Rc=1)", "page_found": "Page 419 - 420", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "vcmpgtsh v1, v2, v3" }, { "mnemonic": "vcmpgtsw.", "architecture": "PowerISA", "full_name": "Vector Compare Greater Than Signed Word (Record)", "summary": "Compares each word of two vector registers and sets the corresponding word in the target vector register to all 1s if the first operand is greater than the second, otherwise to all 0s.", "syntax": "vcmpgtsw. VRT,VRA,VRB", "encoding": { "format": "VC-form", "binary_pattern": "4 | VRT | VRA | VRB | Rc", "hex_opcode": "0x10000386", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "902", "clean": "902" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vcmpgtsw, each word of VSR[VRA+32] is compared with the corresponding word of VSR[VRB+32]. If the signed integer value in the word element i of VSR[VRA+32] is greater than that in VSR[VRB+32], then the contents of word element i of VSR[VRT+32] are set to all 1s; otherwise, they are set to all 0s.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nall_true ←1\nall_false ←1\ndo i = 0 to 3\n src1 ←EXTS(VSR[VRA+32].word[i])\n src2 ←EXTS(VSR[VRB+32].word[i])\n if src1 > src2 then do\n VSR[VRT+32].word[i] ←0xFFFF_FFFF\n all_false ←0\n end\n else do\n VSR[VRT+32].word[i] ←0x0000_0000\n all_true ←0\n end\nend\nif Rc=1 then\n CR.field[6] ←all_true || 0b0 || all_false || 0b0", "special_registers": "CR6 (if Rc=1)", "page_found": "Page 420 - 421", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "vcmpgtsw v1, v2, v3" }, { "mnemonic": "vcmpgtsd.", "architecture": "PowerISA", "full_name": "Vector Compare Greater Than Signed Doubleword (Record)", "summary": "Compares two doublewords of signed integers and sets the result vector based on the comparison.", "syntax": "vcmpgtsd. VRT,VRA,VRB", "encoding": { "format": "VC-form", "binary_pattern": "4 | VRT | VRA | VRB | Rc", "hex_opcode": "0x100003C7", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "967", "clean": "967" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vcmpgtsd, each doubleword in VSR[VRA+32] is compared to the corresponding doubleword in VSR[VRB+32]. If a doubleword in VSR[VRA+32] is greater than the corresponding doubleword in VSR[VRB+32], the corresponding doubleword in VSR[VRT+32] is set to all 1s; otherwise, it is set to all 0s.", "pseudocode": "if MSR.VEC=0 then Vector_Unavailable()\nall_true ←1\nall_false ←1\ndo i = 0 to 1\n src1 ←EXTS(VSR[VRA+32].dword[i])\n src2 ←EXTS(VSR[VRB+32].dword[i])\n if src1 > src2 then do\n VSR[VRT+32].dword[i] ←0xFFFF_FFFF_FFFF_FFFF\n all_false ←0\n end\n else do\n VSR[VRT+32].dword[i] ←0x0000_0000_0000_0000\n all_true ←0\n end\nend\nif Rc=1 then\n CR.field[6] ←all_true || 0b0 || all_false || 0b0", "special_registers": "CR6 (if Rc=1)", "page_found": "Page 421 - 422", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "vcmpgtsd v1, v2, v3" }, { "mnemonic": "xvcmpeqdp.", "architecture": "PowerISA", "full_name": "VSX Vector Compare Equal Double-Precision (Record)", "summary": "Compares two double-precision floating-point values in vector registers and sets the target register based on equality.", "syntax": "xvcmpeqdp. XT,XA,XB", "encoding": { "format": "XX3-form", "binary_pattern": "T | A | B | Rc | AX | BX | TX", "hex_opcode": "0xF0000318", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "99", "clean": "99" } ], "length": "32", "bit_positions": "6:10 | 11:15 | 16:20 | 21:28 | 29 | 30 | 31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "For xvcmpeqdp, each element of the source vectors VSR[XA] and VSR[XB] is compared. The result is stored in VSR[XT]. If Rc=1, CR field 6 is updated with comparison results.", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nex_flag ←0b0\nall_false ←0b1\nall_true ←0b1\ndo i = 0 to 1\n reset_xflags()\n src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[i])\n src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])\n vxsnan_flag ←IsSNaN(src1) | IsSNaN(src2)\n if src1 = src2 then do\n all_false ←0b0\n end\n else do\n vresult.dword[i] ←0x0000_0000_0000_0000\n all_true ←0b0\n end\n if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\n ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag)\nend\nif Rc=1 then do\n if vex_flag=0 then\n CR[6] ←all_true || 0b0 || all_false || 0b0\n else\n CR[6] ←0bUUUU\nend", "special_registers": "CR, FPSCR", "page_found": "Page 806 - 807", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "xvcmpeqdp vs1, vs2, vs3" }, { "mnemonic": "xvcmpgtdp.", "architecture": "PowerISA", "full_name": "VSX Vector Compare Greater Than Double-Precision (Record)", "summary": "Compares two double-precision floating-point values and sets the target vector register based on the comparison.", "syntax": "xvcmpgtdp. XT,XA,XB", "encoding": { "format": "XX3-form", "binary_pattern": "T | A | B | Rc | AX | BX | TX", "hex_opcode": "0xF0000358", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "107", "clean": "107" } ], "length": "32", "bit_positions": "6:10 | 11:15 | 16:20 | 21:28 | 29 | 30 | 31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "For xvcmpgtdp, each element of the source vectors VSR[XA] and VSR[XB] is compared. The result is stored in VSR[XT]. If Rc=1, CR Field 6 is updated with the results of the comparison.", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\n\nex_flag ← 0b0\nall_false ← 0b1\nall_true ← 0b1\ndo i = 0 to 1\n reset_xflags()\n src1 ← bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[i])\n src2 ← bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])\n if src1.class.SNaN | src2.class.SNaN then do\n vxsnan_flag ← 0b1\n if FPSCR.VE=0 then vxvc_flag ← 0b1\n end else vxvc_flag ← IsQNaN(src1) | IsQNaN(src2)\n if src1 > src2 then do\n vresult.dword[i] ← 0xFFFF_FFFF_FFFF_FFFF\n all_false ← 0b0\n end else do\n all_true ← 0b0\n vresult.dword[i] ← 0x0000_0000_0000_0000\n end\n if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\n if vxvc_flag=1 then SetFX(FPSCR.VXVC)\n ex_flag ← ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vxvc_flag)\nend\nif ex_flag=0 then VSR[32×TX+T] ← vresult\nif Rc=1 then do\n if vex_flag=0 then CR.field[6] ← all_true || 0b0 || all_false || 0b0 else CR.field[6] ← 0bUUUU\nend", "special_registers": "CR, FPSCR", "page_found": "Page 810 - 811", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "xvcmpgtdp vs1, vs2, vs3" }, { "mnemonic": "xvcmpgedp.", "architecture": "PowerISA", "full_name": "VSX Vector Compare Greater or Equal Double-Precision (Record)", "summary": "Compares two double-precision floating-point values and sets the target vector register based on the comparison.", "syntax": "xvcmpgedp. XT,XA,XB", "encoding": { "format": "XX3-form", "binary_pattern": "T | A | B | Rc | 115 | AX | BX | TX", "hex_opcode": "0xF0000398", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "115", "clean": "115" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:28 | 29 | 30 | 31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VSX", "description": "For xvcmpgedp, each integer value i from 0 to 1, the double-precision floating-point operand in doubleword element i of VSR[XA] is compared to the double-precision floating-point operand in doubleword element i of VSR[XB]. The contents of doubleword element i of VSR[XT] are set to all 1s if src1 is greater than or equal to src2, and is set to all 0s otherwise.", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nex_flag ←0b0\nall_false ←0b1\nall_true ←0b1\ndo i = 0 to 1\n reset_xflags()\n src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[i])\n src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])\n if src1.class.SNaN | src2.class.SNaN then do\n vxsnan_flag ←0b1\n if FPSCR.VE=0 then vxvc_flag ←0b1\n end\n else vxvc_flag ←IsQNaN(src1) | IsQNaN(src2)\n if src1 >= src2 then do\n vresult.dword[i] ←0xFFFF_FFFF_FFFF_FFFF\n all_false ←0b0\n end\n else do\n vresult.dword[i] ←0x0000_0000_0000_0000\n all_true ←0b0\n end\n if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\n if vxvc_flag=1 then SetFX(FPSCR.VXVC)\n ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vxvc_flag)\nend\nif ex_flag=0 then VSR[32×TX+T] ←vresult\nif Rc=1 then do\n if vex_flag=0 then CR.field[6] ←all_true || 0b0 || all_false || 0b0\n else CR.field[6] ←0bUUUU\nend", "special_registers": "CR6, FPSCR", "page_found": "Page 808 - 809", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "xvcmpgedp vs1, vs2, vs3" }, { "mnemonic": "xvcmpeqsp.", "architecture": "PowerISA", "full_name": "VSX Vector Compare Equal Single-Precision (Record)", "summary": "Compares each single-precision floating-point element of two VSX registers and sets the corresponding element in the target register to all 1s if they are equal, otherwise all 0s.", "syntax": "xvcmpeqsp. XT,XA,XB", "encoding": { "format": "XX3-form", "binary_pattern": "T | A | B | Rc | AX | BX | TX", "hex_opcode": "0xF0000218", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "67", "clean": "67" } ], "length": "32", "bit_positions": "6:10 | 11:15 | 16:20 | 21:28 | 29 | 30 | 31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "For xvcmpeqsp, each integer value i from 0 to 3, the single-precision floating-point operand in word element i of VSR[XA] is compared to the single-precision floating-point operand in word element i of VSR[XB]. The contents of word element i of VSR[XT] are set to all 1s if they are equal, and all 0s otherwise.", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\nex_flag ←0b0\nall_false ←0b1\nall_true ←0b1\ndo i = 0 to 3\n reset_xflags()\n src1 ←bfp_CONVERT_FROM_BFP32(VSR[32×AX+A].word[i])\n src2 ←bfp_CONVERT_FROM_BFP32(VSR[32×BX+B].word[i])\n vxsnan_flag ←IsSNaN(src1) | IsSNaN(src2)\n if src1 = src2 then do\n all_false ←0b0\n end\n else do\n vresult.word[i] ←0x0000_0000\n all_true ←0b0\n end\n if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\n ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag)\nend\nif Rc=1 then do\n if vex_flag=0 then\n CR.field[6] ←all_true || 0b0 || all_false || 0b0\n else\n CR.field[6] ←0bUUUU\nend", "special_registers": "CR, FPSCR", "page_found": "Page 807 - 808", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "xvcmpeqsp vs1, vs2, vs3" }, { "mnemonic": "xvcmpgtsp.", "architecture": "PowerISA", "full_name": "VSX Vector Compare Greater Than Single-Precision (Record)", "summary": "Compares each single-precision floating-point element in two vector registers and sets the corresponding element in a target vector register to all 1s if the first element is greater than the second, otherwise all 0s.", "syntax": "xvcmpgtsp. XT,XA,XB", "encoding": { "format": "XX3-form", "binary_pattern": "T | A | B | Rc | AX | BX | TX", "hex_opcode": "0xF0000258", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "75", "clean": "75" } ], "length": "32", "bit_positions": "6:10 | 11:15 | 16:20 | 21 | 22:28 | 29 | 30:31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "For xvcmpgtsp, each integer value i from 0 to 3, the single-precision floating-point operand in word element i of VSR[XA] is compared to the single-precision floating-point operand in word element i of VSR[XB]. The contents of word element i of VSR[XT] are set to all 1s if the first operand is greater than the second, and all 0s otherwise.", "pseudocode": "if MSR.VSX=0 then VSX_Unavailable()\n\nex_flag ←0b0\nall_false ←0b1\nall_true ←0b1\ndo i = 0 to 3\n reset_xflags()\n src1 ←bfp_CONVERT_FROM_BFP32(VSR[32×AX+A].word[i])\n src2 ←bfp_CONVERT_FROM_BFP32(VSR[32×BX+B].word[i])\n if IsSNaN(src1)=1 | IsSNaN(src2)=1 then do\n vxsnan_flag ←0b1\n if FPSCR.VE=0 then vxvc_flag ←0b1\n end\n else\n vxvc_flag ←src1.class.QNaN | src2.class.QNaN\n if src1 > src2 then do\n vresult.word[i] ←0xFFFF_FFFF\n all_false ←0b0\n end\n else\n vresult.word[i] ←0x0000_0000\n all_true ←0b0\n end\n if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)\n if vxvc_flag=1 then SetFX(FPSCR.VXVC)\n ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vxvc_flag)\nend\nif ex_flag=0 then VSR[32×TX+T] ←vresult\nif Rc=1 then do\n if vex_flag=0 then\n CR.field[6] ←all_true || 0b0 || all_false || 0b0\n else\n CR.field[6] ←0bUUUU\nend", "special_registers": "CR6, FPSCR", "page_found": "Page 811 - 812", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "xvcmpgtsp vs1, vs2, vs3" }, { "mnemonic": "xvcmpgesp.", "architecture": "PowerISA", "full_name": "VSX Vector Compare Greater or Equal Single-Precision (Record)", "summary": "Compares each element of two single-precision floating-point vectors and sets the target vector elements to all 1s if the corresponding source elements are greater than or equal, otherwise all 0s.", "syntax": "xvcmpgesp. XT,XA,XB", "encoding": { "format": "XX3-form", "binary_pattern": "T | A | B | Rc | 83 | AX | BX | TX", "hex_opcode": "0xF0000298", "visual_parts": [ { "raw": "60", "clean": "60" }, { "raw": "XT", "clean": "XT" }, { "raw": "XA", "clean": "XA" }, { "raw": "XB", "clean": "XB" }, { "raw": "83", "clean": "83" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:28 | 29 | 30 | 31" }, "operands": [ { "name": "XT", "desc": "Target" }, { "name": "XA", "desc": "Src A" }, { "name": "XB", "desc": "Src B" } ], "extension": "VSX", "description": "For xvcmpgesp, each element of the single-precision floating-point vector in VSR[XA] is compared with the corresponding element in VSR[XB]. The result is stored in VSR[XT]. If Rc=1, CR field 6 is updated based on the comparison results.", "pseudocode": "if 'xvcmpgesp' then\n for each integer value i from 0 to 3 do\n src1 ← bfp_CONVERT_FROM_BFP32(VSR[32×AX+A].word[i])\n src2 ← bfp_CONVERT_FROM_BFP32(VSR[32×BX+B].word[i])\n if src1.class.SNaN | src2.class.SNaN then\n vxsnan_flag ← 0b1\n if FPSCR.VE=0 then vxvc_flag ← 0b1\n else vxvc_flag ← IsQNaN(src1) | IsQNaN(src2)\n if src1 >= src2 then\n vresult.word[i] ← 0xFFFF_FFFF\n else\n vresult.word[i] ← 0x0000_0000\n ex_flag ← ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vxvc_flag)\n end\n if ex_flag=0 then VSR[32×TX+T] ← vresult\n if Rc=1 then do\n CR.field[6] ← all_true || 0b0 || all_false || 0b0\n end", "special_registers": "CR6, FPSCR (FX VXSNAN VXVC)", "page_found": "Page 809 - 810", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "xvcmpgesp vs1, vs2, vs3" }, { "mnemonic": "vcmpeqfp.", "architecture": "PowerISA", "full_name": "Vector Compare Equal Floating-Point (Record)", "summary": "Compares the elements of two vector registers for equality and stores the result in a third vector register.", "syntax": "vcmpeqfp. VRT,VRA,VRB", "encoding": { "format": "VC-form", "binary_pattern": "4 | VRT | VRA | VRB | Rc", "hex_opcode": "0x100000C6", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "198", "clean": "198" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vcmpeqfp, each element of VSR[VRA+32] is compared to the corresponding element of VSR[VRB+32]. If they are equal, the corresponding element of VSR[VRT+32] is set to all 1s; otherwise, it is set to all 0s.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nall_true ←1\nall_false ←1\ndo i = 0 to 3\n src1 ←VSR[VRA+32].word[i]\n src2 ←VSR[VRB+32].word[i]\n if bool_COMPARE_EQ_BFP32(src1,src2)=1 then\n VSR[VRT+32].word[i] ←0xFFFF_FFFF\n all_false ←0\n else\n VSR[VRT+32].word[i] ←0x0000_0000\n all_true ←0\nend\nif Rc=1 then\n CR.field[6] ←all_true || 0b0 || all_false || 0b0", "special_registers": "CR0, XER", "page_found": "Page 454 - 455", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "vcmpeqfp v1, v2, v3" }, { "mnemonic": "vcmpgtfp.", "architecture": "PowerISA", "full_name": "Vector Compare Greater Than Floating-Point (Record)", "summary": "Compares the contents of two vector registers and sets the target vector register based on whether each element is greater than the corresponding element in the other vector.", "syntax": "vcmpgtfp. VRT,VRA,VRB", "encoding": { "format": "VC-form", "binary_pattern": "4 | VRT | VRA | VRB | Rc", "hex_opcode": "0x100002C6", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "710", "clean": "710" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vcmpgtfp, the contents of VSR[VRA+32] are compared to the contents of VSR[VRB+32]. The result is stored in VSR[VRT+32], with each word set to all 1s if the corresponding element in VSR[VRA+32] is greater than that in VSR[VRB+32], and all 0s otherwise.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nall_true ←1\nall_false ←1\ndo i = 0 to 3\n src1 ←VSR[VRA+32].word[i]\n src2 ←VSR[VRB+32].word[i]\n if bool_COMPARE_GT_BFP32(src1,src2)=1 then\n VSR[VRT+32].word[i] ←0xFFFF_FFFF\n all_false ←0\n else\n all_true ←0\n VSR[VRT+32].word[i] ←0x0000_0000\nend\nif Rc=1 then\n CR.field[6] ←all_true || 0b0 || all_false || 0b0", "special_registers": "CR6", "page_found": "Page 455 - 456", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "vcmpgtfp v1, v2, v3" }, { "mnemonic": "vcmpbfp.", "architecture": "PowerISA", "full_name": "Vector Compare Bounds Floating-Point (Record)", "summary": "Compares two VSRs word element by word and sets the target VSR if Rc=1.", "syntax": "vcmpbfp. VRT,VRA,VRB", "encoding": { "format": "VC-form", "binary_pattern": "4 | VRT | VRA | VRB | Rc | 966", "hex_opcode": "0x100003C6", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "966", "clean": "966" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21 | 22:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "Performs a bounds check comparing each of four 32-bit floating-point elements in VRA against the range defined by two bounds in VRB. The result is stored in VRT as a 4-bit value per element indicating which bound(s) the value violates. When the Rc bit is set (vcmpbfp.), the CR6 field is updated based on the result.", "pseudocode": "for i in 0 to 3:\n if isnan(VRA[32*i:32*i+31]) or isnan(VRB[32*i:32*i+31]) then\n VRT[30*i:30*i+29] ← 0b11\n else if VRA[32*i:32*i+31] < -VRB[32*i:32*i+31] then\n VRT[30*i:30*i+29] ← 0b10\n else if VRA[32*i:32*i+31] > VRB[32*i:32*i+31] then\n VRT[30*i:30*i+29] ← 0b01\n else\n VRT[30*i:30*i+29] ← 0b00\nif Rc = 1 then\n CR6 ← 0b0001 if all results are within bounds else 0b0000", "special_registers": "CR6", "programming_notes": "Each single-precision floating-point value in VSR[VRB+32] should be non-negative; if it is negative, the corresponding element in VSR[VRA+32] will necessarily be out of bounds. One exception to this is when the value of an element in VSR[VRB+32] is -0.0 and the value of the corresponding element in VSR[VRA+32] is either +0.0 or -0.0. +0.0 and -0.0 compare equal to -0.0.", "page_found": "Page 453 - 454", "example": "vcmpbfp v1, v2, v3" }, { "mnemonic": "cntlzd.", "architecture": "PowerISA", "full_name": "Count Leading Zeros Doubleword (Record)", "summary": "Counts the number of consecutive 0 bits starting from bit 0 (MSB of 64-bit reg).", "syntax": "cntlzd. RT,RA", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | 00000 | 000111010 | Rc", "hex_opcode": "0x7C000074", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "00000", "clean": "00000" }, { "raw": "000111010", "clean": "000111010" }, { "raw": "Rc", "clean": "Rc" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RA", "desc": "Target Register" }, { "name": "RS", "desc": "Source Register" }, { "name": "RT", "desc": "Target General Purpose Register" } ], "pseudocode": "n ← 0\nwhile n < 64 and RS[n] = 0 do n ← n + 1\nRT ← n\nif Rc = 1 then CR0 ← (RT = 0, RT < 0, RT > 0, SO)", "example": "cntlzd r3, r4", "example_note": "r3 = Leading Zeros in 64-bit r4.", "extension": "Base", "description": "Counts the number of consecutive zero bits from the MSB (bit 0) of the 64-bit doubleword in RS and stores the result in RT. The count ranges from 0 to 64. If Rc=1, CR0 is updated based on the result.", "special_registers": "CR0", "page_found": "Page 139 - 140", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER." }, { "mnemonic": "bla", "architecture": "PowerISA", "full_name": "Branch Absolute (Link)", "summary": "Branches to the target address and sets the Link Register to the return address.", "syntax": "bla target_addr (AA=1 LK=1)", "encoding": { "format": "I-form" }, "operands": [ { "name": "target_addr", "desc": "Branch target address" } ], "pseudocode": "if AA then NIA <- EXTS(LI || 0b00)\nelse NIA <- CIA + EXTS(LI || 0b00)\nif LK then LR <- CIA + 4", "example": "b label", "example_note": "Jump to 'label'.", "extension": "Base", "description": "If LK=1 then the effective address of the instruction following the branch is placed into the Link Register. Used for subroutine calls.", "special_registers": "LR", "page_found": "Page 75 (verified)", "programming_notes": "The b instruction is used for unconditional branching. The AA and LK fields control whether the address is absolute or relative and whether to link back to the current instruction." }, { "mnemonic": "bca", "architecture": "PowerISA", "full_name": "Branch Conditional Absolute", "summary": "Branches to the target address if the specified condition is met.", "syntax": "bca BO,BI,target_addr (AA=1 LK=0)", "encoding": { "format": "B-form" }, "operands": [ { "name": "BO", "desc": "Branch options / condition to test" }, { "name": "BI", "desc": "Condition Register bit to test" }, { "name": "target_addr", "desc": "Branch target address" } ], "pseudocode": "(see bc)", "example": "bc 12, 2, label", "example_note": "Branch if CR bit 2 is set (beq).", "extension": "Base", "description": "Conditional branch - see bc for the full BO/BI semantics. AA selects absolute vs. relative addressing; LK selects whether the Link Register is set to the return address.", "special_registers": "LR, CTR", "extended_mnemonics": [ "bca", "bclr", "bcctr" ], "page_found": "Page 75 (verified)", "programming_notes": "The bc instruction branches to a target address based on the condition bits in the Condition Register (CR). Ensure that the branch condition and target address are correctly set. The instruction operates at user privilege level, but care must be taken with conditional logic to avoid unintended execution paths." }, { "mnemonic": "bcl", "architecture": "PowerISA", "full_name": "Branch Conditional (Link)", "summary": "Branches to the target address if the specified condition is met.", "syntax": "bcl BO,BI,target_addr (AA=0 LK=1)", "encoding": { "format": "B-form" }, "operands": [ { "name": "BO", "desc": "Branch options / condition to test" }, { "name": "BI", "desc": "Condition Register bit to test" }, { "name": "target_addr", "desc": "Branch target address" } ], "pseudocode": "(see bc)", "example": "bc 12, 2, label", "example_note": "Branch if CR bit 2 is set (beq).", "extension": "Base", "description": "Conditional branch - see bc for the full BO/BI semantics. AA selects absolute vs. relative addressing; LK selects whether the Link Register is set to the return address.", "special_registers": "LR, CTR", "extended_mnemonics": [ "bca", "bclr", "bcctr" ], "page_found": "Page 75 (verified)", "programming_notes": "The bc instruction branches to a target address based on the condition bits in the Condition Register (CR). Ensure that the branch condition and target address are correctly set. The instruction operates at user privilege level, but care must be taken with conditional logic to avoid unintended execution paths." }, { "mnemonic": "bcla", "architecture": "PowerISA", "full_name": "Branch Conditional Absolute (Link)", "summary": "Branches to the target address if the specified condition is met.", "syntax": "bcla BO,BI,target_addr (AA=1 LK=1)", "encoding": { "format": "B-form" }, "operands": [ { "name": "BO", "desc": "Branch options / condition to test" }, { "name": "BI", "desc": "Condition Register bit to test" }, { "name": "target_addr", "desc": "Branch target address" } ], "pseudocode": "(see bc)", "example": "bc 12, 2, label", "example_note": "Branch if CR bit 2 is set (beq).", "extension": "Base", "description": "Conditional branch - see bc for the full BO/BI semantics. AA selects absolute vs. relative addressing; LK selects whether the Link Register is set to the return address.", "special_registers": "LR, CTR", "extended_mnemonics": [ "bca", "bclr", "bcctr" ], "page_found": "Page 75 (verified)", "programming_notes": "The bc instruction branches to a target address based on the condition bits in the Condition Register (CR). Ensure that the branch condition and target address are correctly set. The instruction operates at user privilege level, but care must be taken with conditional logic to avoid unintended execution paths." }, { "mnemonic": "bclrl", "architecture": "PowerISA", "full_name": "Branch Conditional to Link Register (Link)", "summary": "Branches to the address in the Link Register if the specified condition is met, and sets the Link Register to the return address.", "syntax": "bclrl BO,BI,BH", "encoding": { "format": "XL-form" }, "operands": [ { "name": "BO", "desc": "Branch options / condition to test" }, { "name": "BI", "desc": "Condition Register bit to test" }, { "name": "BH", "desc": "Branch hint" } ], "pseudocode": "(see bclr)", "example": "bclr 20, 0", "example_note": "Unconditional return (blr).", "extension": "Base", "description": "Conditional branch to the Link Register (see bclr) with LK=1 -- the Link Register is set to the return address after the branch is taken.", "special_registers": "CTR, LR", "programming_notes": "bclr, bclrl, bcctr, and bcctrl each serve as both a basic and an extended mnemonic. The Assembler will recognize a bclr, bclrl, bcctr, or bcctrl mnemonic with three operands as the basic form, and a bclr, bclrl, bcctr, or bcctrl mnemonic with two operands as the extended form. In the extended form the BH operand is omitted and assumed to be 0b00.", "extended_mnemonics": [ { "mnemonic": "bcctr", "equivalent_to": "bcctr BO,BI,BH" }, { "mnemonic": "bltctr", "equivalent_to": "bcctr 12,0,0" }, { "mnemonic": "bnectr", "equivalent_to": "bcctr 4,10,0" }, { "mnemonic": "bclr", "equivalent_to": "bclr BO,BI,BH" }, { "mnemonic": "bltlr", "equivalent_to": "bclr 12,0,0" }, { "mnemonic": "bnelr", "equivalent_to": "bclr 4,10,0" }, { "mnemonic": "bdnzlr", "equivalent_to": "bclr 16,0,0" }, { "mnemonic": "bcctr", "equivalent_to": "bcctr BO,BI,BH (LK=0)" }, { "mnemonic": "bcctrl", "equivalent_to": "bcctr BO,BI,BH (LK=1)" }, { "mnemonic": "bclr 4,6", "equivalent_to": "bclr 4,6,0" }, { "mnemonic": "bnelr cr2", "equivalent_to": "bclr 4,10,0" } ], "page_found": "Page 73-78 (verified, Appendix C Table C.2)" }, { "mnemonic": "fadd.", "architecture": "PowerISA", "full_name": "Floating Add (Record)", "summary": "Adds the contents of two floating-point registers and places the result into another register.", "syntax": "fadd. FRT,FRA,FRB", "encoding": { "format": "A-form", "binary_pattern": "63 | FRT | FRA | FRB | 00000 | 21 | Rc", "hex_opcode": "0xFC00002A", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "FRA", "clean": "FRA" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "00000", "clean": "00000" }, { "raw": "21", "clean": "21" }, { "raw": "Rc", "clean": "Rc" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target FPR" }, { "name": "FRA", "desc": "Source FPR A" }, { "name": "FRB", "desc": "Source FPR B" } ], "pseudocode": "if 'fadd' then\n FRT <- (FRA) + (FRB)\nelse if 'fadd.' then\n FRT <- (FRA) + (FRB)\n CR1 <- result class and sign", "example": "fadd f1, f2, f3", "example_note": "f1 = f2 + f3", "extension": "Floating-Point", "description": "The floating-point operand in register FRA is added to the floating-point operand in register FRB. The result is rounded to the target precision under control of RN and placed into register FRT.", "special_registers": "FPSCR, CR1, CR0", "page_found": "Page 197 - 198", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes." }, { "mnemonic": "fmul.", "architecture": "PowerISA", "full_name": "Floating Multiply (Record)", "summary": "Multiplies the contents of two floating-point registers and places the result into another register.", "syntax": "fmul. FRT,FRA,FRC", "encoding": { "format": "A-form", "binary_pattern": "63 | FRT | FRA | 00000 | FRC | 25 | Rc", "hex_opcode": "0xFC000032", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "FRA", "clean": "FRA" }, { "raw": "00000", "clean": "00000" }, { "raw": "FRC", "clean": "FRC" }, { "raw": "25", "clean": "25" }, { "raw": "Rc", "clean": "Rc" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target FPR" }, { "name": "FRA", "desc": "Source FPR A" }, { "name": "FRC", "desc": "Source FPR C" } ], "pseudocode": "if 'fmul' then\n FRT <- (FRA) * (FRC)\nelse if 'fmul.' then\n FRT <- (FRA) * (FRC)", "example": "fmul f1, f2, f3", "example_note": "f1 = f2 * f3", "extension": "Floating-Point", "description": "The floating-point operand in register FRA is multiplied by the floating-point operand in register FRC. The result is rounded to the target precision under control of RN and placed into register FRT.", "special_registers": "FPSCR, CR1, CR0", "page_found": "Page 198 - 200", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes." }, { "mnemonic": "fmadd.", "architecture": "PowerISA", "full_name": "Floating Multiply-Add (Record)", "summary": "Performs (A * C) + B with a single rounding step. (The classic FMA).", "syntax": "fmadd. FRT,FRA,FRC,FRB", "encoding": { "format": "A-form", "binary_pattern": "63 | FRT | FRA | FRB | FRC | 29 | Rc", "hex_opcode": "0xFC00003A", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "FRA", "clean": "FRA" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "FRC", "clean": "FRC" }, { "raw": "29", "clean": "29" }, { "raw": "Rc", "clean": "Rc" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target FPR" }, { "name": "FRA", "desc": "Multiplier" }, { "name": "FRC", "desc": "Multiplicand" }, { "name": "FRB", "desc": "Addend" } ], "pseudocode": "FRT ←[(FRA)×(FRC)] + (FRB)\nif 'fmadd.' then\n CR1 <- result class and sign", "example": "fmadd f1, f2, f3, f4", "example_note": "f1 = (f2 * f3) + f4", "extension": "Floating-Point", "description": "The instruction multiplies the contents of register FRA by the contents of register FRC, then adds the result to the contents of register FRB. The final result is placed into register FRT.", "special_registers": "FPSCR, CR1, CR0", "page_found": "Page 203 - 204", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes." }, { "mnemonic": "fctiw.", "architecture": "PowerISA", "full_name": "Floating Convert with round Double-Precision To Signed Word format (Record)", "summary": "Converts a float to a 32-bit signed integer (using the current rounding mode) and stores it in the lower half of the FPR.", "syntax": "fctiw. FRT,FRB", "encoding": { "format": "X-form", "binary_pattern": "63 | FRT | / | FRB | 14 | Rc", "hex_opcode": "0xFC00001C", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "/", "clean": "/" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "14", "clean": "14" }, { "raw": "Rc", "clean": "Rc" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target FPR" }, { "name": "FRB", "desc": "Source FPR" }, { "name": "RT", "desc": "Target Floating Point Register" }, { "name": "RA", "desc": "Source Floating Point Register" } ], "pseudocode": "round_mode ← FPSCRRN\ntgt_precision ← '32-bit signed integer'\n\nsign ← (FRB)0\nif (FRB)1:11 = 2047 and (FRB)12:63 = 0 then goto Infinity Operand\nif (FRB)1:11 = 2047 and (FRB)12 = 0 then goto SNaN Operand\nif (FRB)1:11 = 2047 and (FRB)12 = 1 then goto QNaN Operand\nif (FRB)1:11 > 1086 then goto Large Operand\n\nif (FRB)1:11 > 0 then exp ← (FRB)1:11 - 1023 /* exp - bias */\nif (FRB)1:11 = 0 then exp ← -1022\nif (FRB)1:11 > 0 then frac0:64 ← 0b01 || (FRB)12:63 || 110 /* normal */\nif (FRB)1:11 = 0 then frac0:64 ← 0b00 || (FRB)12:63 || 110 /* denormal */\n\nrbit || xbit ← 0b00\nfor i=1,63-exp /* do the loop 0 times if exp = 63 */\n frac0:64 || rbit || xbit ← 0b0 || frac0:64 || (rbit | xbit)\nend\n\nFRT ← Round Integer(sign, frac0:64, gbit, rbit, xbit, round_mode)", "example": "fctiw f1, f2", "example_note": "Convert float f2 to int in f1.", "extension": "Floating-Point", "description": "The instruction converts the double-precision floating-point value in FRB to a signed word using the specified rounding mode. If the result is out of range, it saturates to the maximum or minimum signed integer value.", "special_registers": "FPSCR, (FR, FI, FX, XX, VXSNAN, VXCVI), CR1, (if, Rc=1), CR0", "page_found": "Page 208 - 210", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes." }, { "mnemonic": "dmul.", "architecture": "PowerISA", "full_name": "Decimal Multiply (Record)", "summary": "Multiplies the contents of two DFP registers and places the result in another DFP register.", "syntax": "dmul. FRT,FRA,FRB", "encoding": { "format": "X-form", "binary_pattern": "0 | FRT | FRA | FRB | Rc | 0 | 0 | 0", "hex_opcode": "0xEC000044", "visual_parts": [ { "raw": "59", "clean": "59" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "FRA", "clean": "FRA" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "34", "clean": "34" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26 | 27:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target FPR" }, { "name": "FRA", "desc": "Source A" }, { "name": "FRB", "desc": "Source B" } ], "pseudocode": "FPR[FRT] ← DFP_multiply(FPR[FRA], FPR[FRB])\nFPSCR ← updated with exception flags\nif Rc = 1 then CR0 ← condition_code(FPR[FRT])", "example": "dmul f1, f2, f3", "example_note": "Financial Multiply.", "extension": "Decimal Floating-Point", "description": "Multiplies two 64-bit Decimal Floating Point (DFP) numbers held in FPRs and stores the result in another FPR. DFP multiplication preserves decimal precision required for financial calculations. The instruction can optionally update CR0 (via the dot form); FPSCR is always updated with exception flags and rounding information.", "special_registers": "FPSCR, CR1", "programming_notes": "dmul[q][.] are treated as Floating-Point instructions in terms of resource availability.", "page_found": "Page 241 - 242" }, { "mnemonic": "dqua.", "architecture": "PowerISA", "full_name": "Decimal Quantize (Record)", "summary": "Adjusts the exponent of a DFP number to match a reference. Critical for aligning decimal points before addition.", "syntax": "dqua. FRT,FRA,FRB,RMC", "encoding": { "format": "X-form", "binary_pattern": "0 | FRT | FRA | FRB | RMC | Rc | 3 | 21 | 23", "hex_opcode": "0xEC000006", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "FRA", "clean": "FRA" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "66", "clean": "66" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRA", "desc": "Source Value" }, { "name": "FRB", "desc": "Reference Exponent" }, { "name": "RMC", "desc": "Rounding Mode Control" } ], "pseudocode": "FPR[FRT] ← DFP_quantize(FPR[FRA], FPR[FRB], RMC)\nFPSCR ← updated with exception flags\nif Rc = 1 then CR0 ← condition_code(FPR[FRT])", "example": "dqua f1, f2, f3", "example_note": "Align decimal points.", "extension": "Decimal Floating-Point", "description": "Adjusts the exponent of a 64-bit DFP number to match a reference exponent, rounding the significand as needed according to the RMC control bits. This operation is essential for aligning decimal points before addition in financial calculations. The instruction can optionally update CR0 via the dot form; FPSCR is always updated with exception flags.", "special_registers": "FPSCR, FPRF, FR, FI, FX, XX, VXSNAN, VXCVI, CR1", "programming_notes": "DFP Quantize can be used to adjust one DFP value to a form having the same exponent as another DFP value. If the adjustment requires the significand to be shifted left and would cause overflow from the most significant digit, the result is a default QNaN.", "page_found": "Page 250 - 252", "extended_mnemonics": [ "dqua", "dqua." ] }, { "mnemonic": "vcmpneb.", "architecture": "PowerISA", "full_name": "Vector Compare Not Equal Byte (Record)", "summary": "Compares each byte of two vector registers and sets the result register to all 1s if the bytes are not equal, otherwise all 0s.", "syntax": "vcmpneb. VRT,VRA,VRB", "encoding": { "format": "VC-form", "binary_pattern": "4 | VRT | VRA | VRB | Rc", "hex_opcode": "0x10000007", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "7", "clean": "7" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vcmpneb, each byte of VSR[VRA+32] is compared with the corresponding byte of VSR[VRB+32]. If they are not equal, the corresponding byte in VSR[VRT+32] is set to 0xFF; otherwise, it is set to 0x00.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nall_true ←1\nall_false ←1\ndo i = 0 to 15\n src1 ←VSR[VRA+32].byte[i]\n src2 ←VSR[VRB+32].byte[i]\n if src1 != src2 then do\n VSR[VRT+32].byte[i] ←0xFF\n all_false ←0\n end\n else do\n VSR[VRT+32].byte[i] ←0x00\n all_true ←0\n end\nend\nif Rc=1 then\n CR.field[6] ←all_true || 0b0 || all_false || 0b0", "special_registers": "CR0, XER", "page_found": "Page 423 - 424", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "vcmpneb v1, v2, v3" }, { "mnemonic": "vcmpneh.", "architecture": "PowerISA", "full_name": "Vector Compare Not Equal Halfword (Record)", "summary": "Compares the contents of two vector registers and sets the result register to all 1s if the elements are not equal, otherwise all 0s.", "syntax": "vcmpneh. VRT,VRA,VRB", "encoding": { "format": "VC-form", "binary_pattern": "4 | VRT | VRA | VRB | Rc", "hex_opcode": "0x10000047", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "71", "clean": "71" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vcmpneh, each halfword element in VSR[VRA+32] is compared with the corresponding element in VSR[VRB+32]. If they are not equal, the corresponding element in VSR[VRT+32] is set to all 1s; otherwise, it is set to all 0s.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nall_true ←1\nall_false ←1\ndo i = 0 to 7\n src1 ←VSR[VRA+32].hword[i]\n src2 ←VSR[VRB+32].hword[i]\n if src1 != src2 then do\n VSR[VRT+32].hword[i] ←0xFFFF\n all_false ←0\n end\n else do\n VSR[VRT+32].hword[i] ←0x0000\n all_true ←0\n end\nend\nif Rc=1 then\n CR.field[6] ←all_true || 0b0 || all_false || 0b0", "special_registers": "CR6 (if Rc=1)", "page_found": "Page 424 - 425", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "vcmpneh v1, v2, v3" }, { "mnemonic": "vcmpnew.", "architecture": "PowerISA", "full_name": "Vector Compare Not Equal Word (Record)", "summary": "Compares each word of two vector registers and sets the corresponding word in the target vector register to all 1s if the words are not equal, otherwise to all 0s.", "syntax": "vcmpnew. VRT,VRA,VRB", "encoding": { "format": "VC-form", "binary_pattern": "4 | VRT | VRA | VRB | Rc", "hex_opcode": "0x10000087", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "135", "clean": "135" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vA", "desc": "Src A" }, { "name": "vB", "desc": "Src B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "For vcmpnew, each word of VSR[VRA+32] is compared with the corresponding word of VSR[VRB+32]. If they are not equal, the corresponding word in VSR[VRT+32] is set to 0xFFFF_FFFF; otherwise, it is set to 0x0000_0000.", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nall_true ←1\nall_false ←1\ndo i = 0 to 3\n src1 ←VSR[VRA+32].word[i]\n src2 ←VSR[VRB+32].word[i]\n if src1 != src2 then do\n VSR[VRT+32].word[i] ←0xFFFF_FFFF\n all_false ←0\n end\n else do\n VSR[VRT+32].word[i] ←0x0000_0000\n all_true ←0\n end\nend\nif Rc=1 then\n CR.field[6] ←all_true || 0b0 || all_false || 0b0", "special_registers": "CR6 (if Rc=1)", "page_found": "Page 425 - 426", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "vcmpnew v1, v2, v3" }, { "mnemonic": "vstribr.", "architecture": "PowerISA", "full_name": "Vector String Isolate Byte Right (Record)", "summary": "Isolates the rightmost non-zero byte in a vector string and shifts it to the left.", "syntax": "vstribr. VRT,VRB", "encoding": { "format": "VX-form", "binary_pattern": "0 | VRT | VRB | Rc | 13", "hex_opcode": "0x1001000D", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "0", "clean": "0" }, { "raw": "vB", "clean": "vB" }, { "raw": "582", "clean": "582" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target" }, { "name": "vB", "desc": "Source" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "extension": "VMX (AltiVec)", "description": "Isolates the rightmost non-zero byte in each 16-byte element of the source vector and shifts it to the leftmost position of the corresponding result element; all other bytes in the result are zeroed. When Rc=1, the instruction updates CR6 based on whether a zero vector was produced.", "pseudocode": "for i in 0 to 15:\n byte_value ← VRB[i*8:(i+1)*8]\n if byte_value ≠ 0 then\n VRT[i*8:(i+1)*8] ← byte_value\n else\n VRT[i*8:(i+1)*8] ← 0\nif Rc = 1 then CR6 ← record_zero_vector(VRT)", "special_registers": "CR6 (if Rc=1)", "page_found": "Page 497 - 498", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "vstribr v1, v3" }, { "mnemonic": "addc.", "architecture": "PowerISA", "full_name": "Add Carrying (Record)", "summary": "Adds the contents of two registers and a carry bit, placing the result in a target register.", "syntax": "addc. RT,RA,RB", "encoding": { "format": "XO-form", "binary_pattern": "31 | RT | RA | RB | OE | 10 | Rc", "hex_opcode": "0x7C000014", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "OE", "clean": "OE" }, { "raw": "10", "clean": "10" }, { "raw": "Rc", "clean": "Rc" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21 | 22:30 | 31" }, "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "RA", "desc": "Source Register 1" }, { "name": "RB", "desc": "Source Register 2" } ], "pseudocode": "if 'addc' then\n RT <- (RA) + (RB)\nelse if 'addc.' then\n RT <- (RA) + (RB)\n if Rc=1 then update CR0\nelse if 'addco' then\n RT <- (RA) + (RB)\n if OE=1 then update XER[SO], XER[OV]\nelse if 'addco.' then\n RT <- (RA) + (RB)\n if Rc=1 then update CR0\n if OE=1 then update XER[SO], XER[OV]", "example": "addc r3, r4, r5", "example_note": "r3 = r4 + r5 (Updates Carry)", "extension": "Base", "description": "The sum (RA) + (RB) is placed into register RT.", "special_registers": "CR0, XER", "page_found": "Page 111 - 112", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER." }, { "mnemonic": "addco", "architecture": "PowerISA", "full_name": "Add Carrying (Overflow)", "summary": "Adds the contents of two registers and a carry bit, placing the result in a target register.", "syntax": "addco RT,RA,RB", "encoding": { "format": "XO-form", "binary_pattern": "31 | RT | RA | RB | OE | 10 | Rc", "hex_opcode": "0x7C000014", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "OE", "clean": "OE" }, { "raw": "10", "clean": "10" }, { "raw": "Rc", "clean": "Rc" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21 | 22:30 | 31" }, "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "RA", "desc": "Source Register 1" }, { "name": "RB", "desc": "Source Register 2" } ], "pseudocode": "if 'addc' then\n RT <- (RA) + (RB)\nelse if 'addc.' then\n RT <- (RA) + (RB)\n if Rc=1 then update CR0\nelse if 'addco' then\n RT <- (RA) + (RB)\n if OE=1 then update XER[SO], XER[OV]\nelse if 'addco.' then\n RT <- (RA) + (RB)\n if Rc=1 then update CR0\n if OE=1 then update XER[SO], XER[OV]", "example": "addc r3, r4, r5", "example_note": "r3 = r4 + r5 (Updates Carry)", "extension": "Base", "description": "The sum (RA) + (RB) is placed into register RT.", "special_registers": "CR0, XER", "page_found": "Page 111 - 112", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER." }, { "mnemonic": "addco.", "architecture": "PowerISA", "full_name": "Add Carrying (Record)", "summary": "Adds the contents of two registers and a carry bit, placing the result in a target register.", "syntax": "addco. RT,RA,RB", "encoding": { "format": "XO-form", "binary_pattern": "31 | RT | RA | RB | OE | 10 | Rc", "hex_opcode": "0x7C000014", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "OE", "clean": "OE" }, { "raw": "10", "clean": "10" }, { "raw": "Rc", "clean": "Rc" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21 | 22:30 | 31" }, "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "RA", "desc": "Source Register 1" }, { "name": "RB", "desc": "Source Register 2" } ], "pseudocode": "if 'addc' then\n RT <- (RA) + (RB)\nelse if 'addc.' then\n RT <- (RA) + (RB)\n if Rc=1 then update CR0\nelse if 'addco' then\n RT <- (RA) + (RB)\n if OE=1 then update XER[SO], XER[OV]\nelse if 'addco.' then\n RT <- (RA) + (RB)\n if Rc=1 then update CR0\n if OE=1 then update XER[SO], XER[OV]", "example": "addc r3, r4, r5", "example_note": "r3 = r4 + r5 (Updates Carry)", "extension": "Base", "description": "The sum (RA) + (RB) is placed into register RT.", "special_registers": "CR0, XER", "page_found": "Page 111 - 112", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER." }, { "mnemonic": "subf", "architecture": "PowerISA", "full_name": "Subtract From", "summary": "Subtracts the contents of register RA from register RB and places the result in RT.", "syntax": "subf RT,RA,RB", "encoding": { "format": "D-form" }, "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "RA", "desc": "Source Register (subtracted)" }, { "name": "RB", "desc": "Source Register (minuend)" } ], "pseudocode": "RT ← ¬(RA) + (RB) + 1", "example": "subf r3, r4, r5", "example_note": "r3 = r4 + 10 (Updates CA)", "extension": "Base", "description": "The sum ¬(RA) + (RB) + 1 is placed into register RT. This is equivalent to RB - RA.", "special_registers": "CR CR0 (if Rc=1); XER SO OV OV32 (if OE=1)", "extended_mnemonics": [ { "mnemonic": "sub RT,RB,RA", "equivalent": "subf RT,RA,RB" }, { "mnemonic": "sub. RT,RB,RA", "equivalent": "subf. RT,RA,RB" }, { "mnemonic": "subo RT,RB,RA", "equivalent": "subfo RT,RA,RB" }, { "mnemonic": "subo. RT,RB,RA", "equivalent": "subfo. RT,RA,RB" } ], "page_found": "Page 110 (verified, corrected from addic's mis-scraped block)", "programming_notes": "The subf instruction subtracts the contents of register RA from register RB (RT = RB - RA); note the 'subtract from' operand order. Assemblers provide the extended mnemonic sub RT,RA,RB, implemented as subf RT,RB,RA. This instruction operates at user privilege level." }, { "mnemonic": "subf.", "architecture": "PowerISA", "full_name": "Subtract From (Record)", "summary": "Subtracts the contents of register RA from register RB and places the result in RT.", "syntax": "subf. RT,RA,RB", "encoding": { "format": "D-form" }, "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "RA", "desc": "Source Register (subtracted)" }, { "name": "RB", "desc": "Source Register (minuend)" } ], "pseudocode": "RT ← ¬(RA) + (RB) + 1", "example": "subf. r3, r4, r5", "example_note": "r3 = r4 + 10 (Updates CA)", "extension": "Base", "description": "The sum ¬(RA) + (RB) + 1 is placed into register RT. This is equivalent to RB - RA.", "special_registers": "CR CR0 (if Rc=1); XER SO OV OV32 (if OE=1)", "extended_mnemonics": [ { "mnemonic": "sub RT,RB,RA", "equivalent": "subf RT,RA,RB" }, { "mnemonic": "sub. RT,RB,RA", "equivalent": "subf. RT,RA,RB" }, { "mnemonic": "subo RT,RB,RA", "equivalent": "subfo RT,RA,RB" }, { "mnemonic": "subo. RT,RB,RA", "equivalent": "subfo. RT,RA,RB" } ], "page_found": "Page 110 (verified, corrected from addic's mis-scraped block)", "programming_notes": "The subf instruction subtracts the contents of register RA from register RB (RT = RB - RA); note the 'subtract from' operand order. Assemblers provide the extended mnemonic sub RT,RA,RB, implemented as subf RT,RB,RA. This instruction operates at user privilege level." }, { "mnemonic": "subfo", "architecture": "PowerISA", "full_name": "Subtract From (Overflow)", "summary": "Subtracts the contents of register RA from register RB and places the result in RT.", "syntax": "subfo RT,RA,RB", "encoding": { "format": "D-form" }, "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "RA", "desc": "Source Register (subtracted)" }, { "name": "RB", "desc": "Source Register (minuend)" } ], "pseudocode": "RT ← ¬(RA) + (RB) + 1", "example": "subfo r3, r4, r5", "example_note": "r3 = r4 + 10 (Updates CA)", "extension": "Base", "description": "The sum ¬(RA) + (RB) + 1 is placed into register RT. This is equivalent to RB - RA.", "special_registers": "CR CR0 (if Rc=1); XER SO OV OV32 (if OE=1)", "extended_mnemonics": [ { "mnemonic": "sub RT,RB,RA", "equivalent": "subf RT,RA,RB" }, { "mnemonic": "sub. RT,RB,RA", "equivalent": "subf. RT,RA,RB" }, { "mnemonic": "subo RT,RB,RA", "equivalent": "subfo RT,RA,RB" }, { "mnemonic": "subo. RT,RB,RA", "equivalent": "subfo. RT,RA,RB" } ], "page_found": "Page 110 (verified, corrected from addic's mis-scraped block)", "programming_notes": "The subf instruction subtracts the contents of register RA from register RB (RT = RB - RA); note the 'subtract from' operand order. Assemblers provide the extended mnemonic sub RT,RA,RB, implemented as subf RT,RB,RA. This instruction operates at user privilege level." }, { "mnemonic": "subfo.", "architecture": "PowerISA", "full_name": "Subtract From (Overflow, Record)", "summary": "Subtracts the contents of register RA from register RB and places the result in RT.", "syntax": "subfo. RT,RA,RB", "encoding": { "format": "D-form" }, "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "RA", "desc": "Source Register (subtracted)" }, { "name": "RB", "desc": "Source Register (minuend)" } ], "pseudocode": "RT ← ¬(RA) + (RB) + 1", "example": "subfo. r3, r4, r5", "example_note": "r3 = r4 + 10 (Updates CA)", "extension": "Base", "description": "The sum ¬(RA) + (RB) + 1 is placed into register RT. This is equivalent to RB - RA.", "special_registers": "CR CR0 (if Rc=1); XER SO OV OV32 (if OE=1)", "extended_mnemonics": [ { "mnemonic": "sub RT,RB,RA", "equivalent": "subf RT,RA,RB" }, { "mnemonic": "sub. RT,RB,RA", "equivalent": "subf. RT,RA,RB" }, { "mnemonic": "subo RT,RB,RA", "equivalent": "subfo RT,RA,RB" }, { "mnemonic": "subo. RT,RB,RA", "equivalent": "subfo. RT,RA,RB" } ], "page_found": "Page 110 (verified, corrected from addic's mis-scraped block)", "programming_notes": "The subf instruction subtracts the contents of register RA from register RB (RT = RB - RA); note the 'subtract from' operand order. Assemblers provide the extended mnemonic sub RT,RA,RB, implemented as subf RT,RB,RA. This instruction operates at user privilege level." }, { "mnemonic": "addmeo", "architecture": "PowerISA", "full_name": "Add to Minus One Extended (Overflow)", "summary": "Adds the contents of a register and a constant minus one, with optional overflow exception.", "syntax": "addmeo RT,RA", "encoding": { "format": "XO-form", "binary_pattern": "31 | RT | RA | 00000 | OE | 234 | Rc", "hex_opcode": "0x7C0001D4", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "00000", "clean": "00000" }, { "raw": "OE", "clean": "OE" }, { "raw": "234", "clean": "234" }, { "raw": "Rc", "clean": "Rc" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21 | 22:30 | 31" }, "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "RA", "desc": "Source Register" } ], "pseudocode": "if 'addme' then\n RT <- (RA) + CA - 1", "example": "addme r3, r4", "example_note": "r3 = r4 + CA - 1", "extension": "Base", "description": "The sum (RA) + CA - 1 is placed into register RT. The carry bit (CA) is used in the calculation.", "special_registers": "CR0, XER", "extended_mnemonics": [ "addme.", "addmeo", "addmeo." ], "page_found": "Page 112 - 114", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER." }, { "mnemonic": "addmeo.", "architecture": "PowerISA", "full_name": "Add to Minus One Extended (Record)", "summary": "Adds the contents of a register and a constant minus one, with optional overflow exception.", "syntax": "addmeo. RT,RA", "encoding": { "format": "XO-form", "binary_pattern": "31 | RT | RA | 00000 | OE | 234 | Rc", "hex_opcode": "0x7C0001D4", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RT", "clean": "RT" }, { "raw": "RA", "clean": "RA" }, { "raw": "00000", "clean": "00000" }, { "raw": "OE", "clean": "OE" }, { "raw": "234", "clean": "234" }, { "raw": "Rc", "clean": "Rc" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21 | 22:30 | 31" }, "operands": [ { "name": "RT", "desc": "Target Register" }, { "name": "RA", "desc": "Source Register" } ], "pseudocode": "if 'addme' then\n RT <- (RA) + CA - 1", "example": "addme r3, r4", "example_note": "r3 = r4 + CA - 1", "extension": "Base", "description": "The sum (RA) + CA - 1 is placed into register RT. The carry bit (CA) is used in the calculation.", "special_registers": "CR0, XER", "extended_mnemonics": [ "addme.", "addmeo", "addmeo." ], "page_found": "Page 112 - 114", "programming_notes": "When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER." }, { "mnemonic": "and.", "architecture": "PowerISA", "full_name": "AND (Record)", "summary": "Performs a bitwise AND operation on the contents of two registers and places the result into another register.", "syntax": "and. RT,RS,RB", "encoding": { "format": "X-form", "binary_pattern": "31 | RS | RA | RB | 28 | Rc", "hex_opcode": "0x7C000038", "visual_parts": [ { "raw": "31", "clean": "31" }, { "raw": "RS", "clean": "RS" }, { "raw": "RA", "clean": "RA" }, { "raw": "RB", "clean": "RB" }, { "raw": "28", "clean": "28" }, { "raw": "Rc", "clean": "Rc" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "RA", "desc": "Target Register" }, { "name": "RS", "desc": "Source Register 1" }, { "name": "RB", "desc": "Source Register 2" }, { "name": "RT", "desc": "Target General Purpose Register" } ], "pseudocode": "if 'and' then\n RT <- (RS) & (RB)\nelse if 'and.' then\n RT <- (RS) & (RB)", "example": "and r3, r4, r5", "example_note": "r3 = r4 & r5", "extension": "Base", "description": "The contents of register RS are ANDed with the contents of register RB and the result is placed into register RA.", "special_registers": "CR0", "programming_notes": "Some forms of and Rx, Rx, Rx provide special functions; see Section 11.3 of Book III.", "page_found": "Page 134 - 136" }, { "mnemonic": "fmr.", "architecture": "PowerISA", "full_name": "Floating Move Register (Record)", "summary": "Copies a float register (Pseudo: for FRB).", "syntax": "fmr. FRT,FRB", "encoding": { "format": "X-form", "binary_pattern": "63 | FRT | 0 | FRB | 72 | /", "hex_opcode": "0xFC000090", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "72", "clean": "72" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" } ], "extension": "Floating-Point", "description": "The contents of register FRB are placed into register FRT.", "pseudocode": "FRT <- FRB", "special_registers": "CR1, (if, Rc=1), FPSCR", "page_found": "Page 195 - 196", "programming_notes": "The fmr instruction is used to copy the contents of one floating-point register (FRB) to another (FRT). It does not alter any special registers unless Rc=1, in which case it updates CR1. Ensure that both source and destination registers are properly aligned for optimal performance.", "example": "fmr f1, f3" }, { "mnemonic": "fsel.", "architecture": "PowerISA", "full_name": "Floating Select (Record)", "summary": "Selects FRA if FRC >= 0, else FRB (Optional).", "syntax": "fsel. FRT,FRA,FRC,FRB", "encoding": { "format": "A-form", "binary_pattern": "63 | FRT | FRA | FRB | FRC | 23 | /", "hex_opcode": "0xFC00002E", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "FRA", "clean": "FRA" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "FRC", "clean": "FRC" }, { "raw": "23", "clean": "23" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRA", "desc": "True" }, { "name": "FRC", "desc": "Cond" }, { "name": "FRB", "desc": "False" } ], "extension": "Floating-Point", "description": "Selects between FRA and FRB based on the sign of FRC: if FRC ≥ 0, the result is FRA; otherwise, the result is FRB. The optional dot (.) form sets CR1 based on the result's FPRF. This is an optional category instruction.", "pseudocode": "if FRC ≥ 0.0 then\n FRT ← FRA\nelse\n FRT ← FRB\nif Rc = 1 then CR1 ← FPRF(FRT)", "special_registers": "CR1, FPSCR", "programming_notes": "Warning: Care must be taken in using fsel if IEEE compatibility is required, or if the values being tested can be NaNs or infinities.", "page_found": "Page 215 - 216", "example": "fsel f1, f2, f4, f3" }, { "mnemonic": "fsqrt.", "architecture": "PowerISA", "full_name": "Floating Square Root (Record)", "summary": "Computes the square root of a floating-point number.", "syntax": "fsqrt. FRT,FRB", "encoding": { "format": "X-form", "binary_pattern": "63 | FRT | 0 | FRB | 22 | /", "hex_opcode": "0xFC00002C", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "22", "clean": "22" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" } ], "extension": "Floating-Point", "description": "The square root of the floating-point operand in register FRB is placed into register FRT. If the most significant bit of the resultant significand is not 1, the result is normalized. The result is rounded to the target precision under control of RN and placed into register FRT.", "special_registers": "FPSCR, CR1", "page_found": "Page 199 - 200", "pseudocode": "if FRB < 0 then\n FRT ← QNaN\n if VE = 1 then raise VXSQRT exception\nelse\n FRT ← sqrt(FRB)\n if most significant bit of FRT's significand is not 1 then normalize FRT\n round FRT to target precision under control of RN\nend if\nFPSCR.FPRF ← class and sign of FRT\nif VE = 1 and result is invalid operation exception then raise VXSQRT exception", "programming_notes": "The fsqrt instruction computes the square root of a floating-point number. It handles negative inputs by returning a quiet NaN (QNaN) and may raise an exception if enabled. Ensure the input is non-negative to avoid unexpected results. The result is normalized and rounded according to the current rounding mode, which can affect precision.", "example": "fsqrt f1, f3" }, { "mnemonic": "fnmadd.", "architecture": "PowerISA", "full_name": "Floating Negative Multiply-Add (Record)", "summary": "Performs a floating-point negative multiply-add operation.", "syntax": "fnmadd. FRT,FRA,FRC,FRB", "encoding": { "format": "A-form", "binary_pattern": "63 | FRT | FRA | FRB | FRC | 31 | /", "hex_opcode": "0xFC00003E", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "FRA", "clean": "FRA" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "FRC", "clean": "FRC" }, { "raw": "31", "clean": "31" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:25 | 26:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRA", "desc": "A" }, { "name": "FRC", "desc": "C" }, { "name": "FRB", "desc": "B" } ], "extension": "Floating-Point", "description": "The operation FRT ←- ( [(FRA)×(FRC)] + (FRB) ) is performed. The result is negated and placed into register FRT.", "pseudocode": "FRT ←- ( [(FRA)×(FRC)] + (FRB) )\nif 'fnmadd.' then\n update CR1 and FPSCR fields", "special_registers": "FPSCR, CR1", "page_found": "Page 204 - 206", "programming_notes": "The fnmadd instruction is useful for performing a negated multiply-add operation on floating-point numbers. Ensure that the input registers FRA, FRC, and FRB are correctly aligned and contain valid floating-point values to avoid exceptions. If using the 'fnmadd.' form, be aware that it updates CR1 and FPSCR, which can affect subsequent conditional operations or exception handling.", "example": "fnmadd f1, f2, f4, f3" }, { "mnemonic": "frsp.", "architecture": "PowerISA", "full_name": "Floating Round to Single-Precision (Record)", "summary": "Rounds the contents of a floating-point register to single-precision.", "syntax": "frsp. FRT,FRB", "encoding": { "format": "X-form", "binary_pattern": "63 | FRT | / | FRB | 12 | Rc", "hex_opcode": "0xFC000018", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "12", "clean": "12" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" } ], "extension": "Floating-Point", "description": "The floating-point operand in register FRB is rounded to single-precision using the rounding mode specified by RN and placed into register FRT.", "pseudocode": "if (FRB)1:11 < 897 and (FRB)1:63 > 0 then\n if FPSCRUE = 0 then goto Disabled Exponent Underflow\n if FPSCRUE = 1 then goto Enabled Exponent Underflow\nend\n\nif (FRB)1:11 > 1150 and (FRB)1:11 < 2047 then\n if FPSCROE = 0 then goto Disabled Exponent Overflow\n if FPSCROE = 1 then goto Enabled Exponent Overflow\nend\n\nif (FRB)1:11 > 896 and (FRB)1:11 < 1151 then goto Normal Operand\n\nif (FRB)1:63 = 0 then goto Zero Operand\n\nif (FRB)1:11 = 2047 then\n if (FRB)12:63 = 0 then goto Infinity Operand\n if (FRB)12 = 1 then goto QNaN Operand\n if (FRB)12 = 0 and (FRB)13:63 > 0 then goto SNaN Operand\nend\n\nDisabled Exponent Underflow:\n sign ←(FRB)0\n if (FRB)1:11 = 0 then\n exp ←-1022\n frac0:52 ←0b0 || (FRB)12:63\n end\n if (FRB)1:11 > 0 then\n exp ←(FRB)1:11 -1023\n frac0:52 ←0b1 || (FRB)12:63\n end\n Denormalize operand:\n G || R || X ←0b000\n do while exp < -126\n exp ←exp + 1\n frac0:52 || G || R || X ←0b0 || frac0:52 || G || (R | X)\n end\n FPSCRUX ←(frac24:52 || G || R || X) > 0\n Round Single(sign,exp,frac0:52,G,R,X)\n FPSCRXX ←FPSCRXX | FPSCRFI", "special_registers": "FPSCR (FPRF FR FI FX OX UX XX VXSNAN), CR1", "page_found": "Page 205 - 206", "programming_notes": "The frsp instruction rounds a double-precision floating-point number to single precision. It handles various cases like underflow, overflow, and NaNs, setting appropriate flags in the FPSCR register. Ensure that the input register FRB is correctly set before calling this instruction.", "example": "frsp f1, f3" }, { "mnemonic": "fcfid.", "architecture": "PowerISA", "full_name": "Floating Convert with round Signed Doubleword to Double-Precision format (Record)", "summary": "Converts a signed doubleword integer to a double-precision floating-point number.", "syntax": "fcfid. FRT,FRB", "encoding": { "format": "X-form", "binary_pattern": "63 | FRT | 0 | FRB | 846 | /", "hex_opcode": "0xFC00069C", "visual_parts": [ { "raw": "63", "clean": "63" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "846", "clean": "846" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" } ], "extension": "Floating-Point", "description": "The 64-bit signed fixed-point operand in register FRB is converted to an infinitely precise floating-point integer. The result of the conversion is rounded to double-precision, using the rounding mode specified by RN, and placed into register FRT.", "pseudocode": "if 'fcfid' then\n FRT <- (FRB) converted to double-precision floating-point integer\n round result using RN\n if Rc=1 then update CR1", "special_registers": "FPSCR, CR1 (if Rc=1)", "programming_notes": "Converting a signed integer word to double-precision floating-point can be accomplished by loading the word from storage using Load Float Word Algebraic Indexed and then using fcfid.", "page_found": "Page 210 - 212", "example": "fcfid f1, f3" }, { "mnemonic": "fcfids.", "architecture": "PowerISA", "full_name": "Floating Convert with round Signed Doubleword to Single-Precision format (Record)", "summary": "Converts a 64-bit signed fixed-point operand in register FRB to single-precision floating-point.", "syntax": "fcfids. FRT,FRB", "encoding": { "format": "X-form", "binary_pattern": "59 | FRT | 0 | FRB | 846 | /", "hex_opcode": "0xEC00069C", "visual_parts": [ { "raw": "59", "clean": "59" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "846", "clean": "846" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" } ], "extension": "Floating-Point", "description": "The 64-bit signed fixed-point operand in register FRB is converted to an infinitely precise floating-point integer. The result of the conversion is rounded to single-precision, using the rounding mode specified by RN, and placed into register FRT.", "special_registers": "FPSCR (FPRF, FR, FI, FX, XX), CR1 (if Rc=1)", "programming_notes": "Converting a signed integer word to single-precision floating-point can be accomplished by loading the word from storage using Load Float Word Algebraic and then using fcfids.", "page_found": "Page 211 - 212", "pseudocode": "FRT ← ConvertToFloat(FRB, RN)\nSetFlags(FPRF, FR, FI)", "example": "fcfids f1, f3" }, { "mnemonic": "vcmpequw.", "architecture": "PowerISA", "full_name": "Vector Compare Equal Word (Record)", "summary": "Compares each word of two vector registers and sets the corresponding word in the target register to all 1s if they are equal, otherwise all 0s.", "syntax": "vcmpequw. VRT,VRA,VRB", "encoding": { "format": "VC-form", "binary_pattern": "0 | VRT | VRA | VRB | Rc", "hex_opcode": "0x10000086", "visual_parts": [ { "raw": "4", "clean": "4" }, { "raw": "vD", "clean": "vD" }, { "raw": "vA", "clean": "vA" }, { "raw": "vB", "clean": "vB" }, { "raw": "134", "clean": "134" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "operands": [ { "name": "vD", "desc": "Target (Mask)" }, { "name": "vA", "desc": "Source A" }, { "name": "vB", "desc": "Source B" }, { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "pseudocode": "if MSR.VEC=0 then Vector_Unavailable()\n\nall_true ←1\nall_false ←1\ndo i = 0 to 3\n src1 ←VSR[VRA+32].word[i]\n src2 ←VSR[VRB+32].word[i]\n if src1 = src2 then do\n VSR[VRT+32].word[i] ←0xFFFF_FFFF\n all_false ←0\n end\n else do\n VSR[VRT+32].word[i] ←0x0000_0000\n all_true ←0\n end\nend\ndo i = 0 to 3\n src1 ←VSR[VRA+32].word[i]\n src2 ←VSR[VRB+32].word[i]\n if src1 = src2 then do\n VSR[VRT+32].word[i] ←0xFFFF_FFFF\n all_false ←0\n end\n else do\n VSR[VRT+32].word[i] ←0x0000_0000\n all_true ←0\n end\nend\nif Rc=1 then\n CR.field[6] ←all_true || 0b0 || all_false || 0b0", "example": "vcmpequw v1, v2, v3", "example_note": "Generate mask for equality.", "extension": "VMX (AltiVec)", "description": "For vcmpequw, each word of VSR[VRA+32] is compared with the corresponding word of VSR[VRB+32]. If they are equal, the corresponding word in VSR[VRT+32] is set to 0xFFFF_FFFF; otherwise, it is set to 0x0000_0000.", "special_registers": "CR6", "page_found": "Page 415 - 416", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes." }, { "mnemonic": "ddiv.", "architecture": "PowerISA", "full_name": "Decimal Divide (Record)", "summary": "Divides the contents of two decimal floating-point registers and places the result in a target register.", "syntax": "ddiv. FRT,FRA,FRB", "encoding": { "format": "X-form", "binary_pattern": "59 | FRT | FRA | FRB | 546 | /", "hex_opcode": "0xEC000444", "visual_parts": [ { "raw": "59", "clean": "59" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "FRA", "clean": "FRA" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "546", "clean": "546" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRA", "desc": "Src A" }, { "name": "FRB", "desc": "Src B" } ], "extension": "Decimal Floating-Point", "description": "The DFP operand in FRA is divided by the DFP operand in FRB. The result is rounded to the target-format precision under control of the DRN (bits 29:31 of the FPSCR). An appropriate form of the rounded result is selected based on the ideal exponent and is placed in FRT.", "pseudocode": "if 'ddiv' then\n FRT <- (FRA) / (FRB)\n if Rc=1 then\n CR1 <- result of comparison", "special_registers": "FPSCR, CR1", "page_found": "Page 242 - 244", "programming_notes": "The ddiv instruction performs a decimal division, rounding the result according to the precision control bits in FPSCR. Ensure that operands are properly aligned and check for division by zero or overflow conditions, which may trigger exceptions. The result can be compared if Rc is set, updating CR1 accordingly.", "example": "ddiv f1, f2, f3" }, { "mnemonic": "drsp.", "architecture": "PowerISA", "full_name": "Decimal Round To DFP Short (Record)", "summary": "Rounds DFP Long (64-bit) to DFP Short (32-bit compressed).", "syntax": "drsp. FRT,FRB", "encoding": { "format": "X-form", "binary_pattern": "59 | FRT | 0 | FRB | 770 | /", "hex_opcode": "0xEC000604", "visual_parts": [ { "raw": "59", "clean": "59" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "770", "clean": "770" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" } ], "extension": "Decimal Floating-Point", "description": "The DFP long operand in FRB is converted and rounded to DFP short format. The DFP short value is extended on the left with zeros to form a 64-bit entity and placed into FRT. The sign of the result is the same as the sign of the source operand.", "pseudocode": "if 'drsp' then\n FRT <- (FRB) rounded to DFP short format\n if Rc=1 then\n CR0, CR1 <- updated based on result", "special_registers": "FPSCR, CR0, CR1", "programming_notes": "Note that DFP short format is a storage-only format. Therefore, conversion of a long SNaN to short for mat will not cause an exception.", "page_found": "Page 261 - 262", "example": "drsp f1, f3" }, { "mnemonic": "dctfix.", "architecture": "PowerISA", "full_name": "Decimal Convert To Fixed (Record)", "summary": "Converts a decimal floating-point number to a fixed-point integer.", "syntax": "dctfix. FRT,FRB", "encoding": { "format": "X-form", "binary_pattern": "59 | FRT | / | FRB | 290 | Rc", "hex_opcode": "0xEC000244", "visual_parts": [ { "raw": "59", "clean": "59" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "290", "clean": "290" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" } ], "extension": "Decimal Floating-Point", "description": "The DFP operand in FRB is rounded to an integer value and placed into FRT in the 64-bit signed binary integer format. The sign of the result is the same as the sign of the source operand, except when the source operand is a NaN or a zero.", "pseudocode": "if 'dctfix' then\n FRT <- round(FRB)\nelse if 'dctfix.' then\n FRT <- round(FRB)\n CR1 <- result of comparison", "special_registers": "FPSCR (FPRF, FR, FI, FX, VXSNAN, VXCVI, XX), CR1 (if Rc=1)", "page_found": "Page 270 - 272", "programming_notes": "It is recommended that software pre-round the operand to a floating-point integral using drintx[q] or drintn[q] if a rounding mode other than the current rounding mode specified by DRN is needed.", "example": "dctfix f1, f3" }, { "mnemonic": "ddedpd.", "architecture": "PowerISA", "full_name": "Decode DPD To BCD (Single Precision) (Record)", "summary": "Converts a portion of the significand of a DFP operand to a signed or unsigned BCD number.", "syntax": "ddedpd. SP,FRT,FRB", "encoding": { "format": "X-form", "binary_pattern": "59 | FRT | SP | / | FRB | 322 | Rc", "hex_opcode": "0xEC000284", "visual_parts": [ { "raw": "59", "clean": "59" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "SP", "clean": "SP" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "322", "clean": "322" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:12 | 13:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" }, { "name": "SP", "desc": "Sign Control" } ], "extension": "Decimal Floating-Point", "description": "The rightmost 16 digits of the significand (32 digits for ddedpdq) is converted to an unsigned BCD number and the result is placed into FRT[p].", "pseudocode": "if 'ddedpd' then\n if SP = 0 then\n FRT <- unsigned BCD conversion of rightmost 16 digits of FRB[p]\n else if SP = 1 then\n FRT <- signed BCD conversion of rightmost 15 digits of FRB[p] with the same sign as FRB[p]\n end if", "special_registers": "FPSCR, (FPRF, FX, VXCVI), FPSCR, (FR, set, to, 0), CR1, (if, Rc=1), CR0", "page_found": "Page 264 - 266", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "example": "ddedpd 0, f1, f3" }, { "mnemonic": "dxex.", "architecture": "PowerISA", "full_name": "Decimal Extract Exponent (Record)", "summary": "Extracts the biased exponent of a DFP operand in FRB and places it into FRT.", "syntax": "dxex. FRT,FRB", "encoding": { "format": "X-form", "binary_pattern": "59 | FRT | 0 | FRB | 354 | /", "hex_opcode": "0xEC0002C4", "visual_parts": [ { "raw": "59", "clean": "59" }, { "raw": "FRT", "clean": "FRT" }, { "raw": "0", "clean": "0" }, { "raw": "FRB", "clean": "FRB" }, { "raw": "354", "clean": "354" }, { "raw": "/", "clean": "/" } ], "length": "32", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:30 | 31" }, "operands": [ { "name": "FRT", "desc": "Target" }, { "name": "FRB", "desc": "Source" } ], "extension": "Decimal Floating-Point", "description": "The biased exponent of the operand in FRB is extracted and placed into FRT in the 64-bit signed binary integer format. Special codes are returned for infinity, QNaN, or SNaN operands.", "pseudocode": "if 'dxex' then\n a <- biased exponent of FRB[p]\n if a > MBE1 then\n FRT[p] <- QNaNSNaN\n else if 0 ≤a ≤MBE then\n FRT[p] <- Finite number with biased exponent a\n else if a = -1 then\n FRT[p] <- Infinity\n else if a = -2 then\n FRT[p] <- QNaN\n else if a = -3 then\n FRT[p] <- SNaN\n else if a < -3 then\n FRT[p] <- QNaN", "special_registers": "CR1, (if, Rc=1), FPSCR", "programming_notes": "The exponent bias value is 101 for DFP Short, 398 for DFP Long, and 6176 for DFP Extended.", "page_found": "Page 266 - 268", "example": "dxex f1, f3" }, { "mnemonic": "frin.", "architecture": "PowerISA", "full_name": "Floating Round to Integer Nearest (Record)", "summary": "Rounds the floating-point operand in register FRB to an integral value using the rounding mode round to nearest.", "description": "The floating-point operand in register FRB is rounded to an integral value as follows, with the result placed into register FRT. If the sign of the operand is positive, (FRB) + 0.5 is truncated to an integral value, otherwise (FRB) - 0.5 is truncated to an integral value.", "syntax": "frin. FRT,FRB", "operands": [ { "name": "FRT", "desc": "Target Floating-Point Register" }, { "name": "FRB", "desc": "Source Floating-Point Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0xFC000310", "length": "32", "binary_pattern": "18 | FRT | FRB | Rc", "bit_positions": "0:5 | 6:29 | 30 | 31" }, "extension": "Floating-Point", "pseudocode": "if 'frin' then\n if (FRB) >= 0 then\n FRT <- truncate((FRB) + 0.5)\n else\n FRT <- truncate((FRB) - 0.5)", "special_registers": "FPSCR, (FPRF, FX, VXSNAN), FPSCR, (FR, FI), CR1, (if, Rc=1), CR0", "programming_notes": "These instructions set FR and FI to 0b00 regardless of whether the result is inexact or rounded because there is a desire to preserve the value of XX.", "extended_mnemonics": [], "page_found": "Page 212 - 214", "example": "frin f1, f3" }, { "mnemonic": "drintx.", "architecture": "PowerISA", "full_name": "Decimal Floating-Point Round To FP Integer With Inexact (Record)", "summary": "Rounds a decimal floating-point number to the nearest integer and places it into a floating-point register.", "description": "The DFP operand in FRB is rounded to a floating-point integer and placed into FRT. The sign of the result is the same as the sign of the operand in FRB. The ideal exponent is the larger value of zero and the exponent of the operand in FRB. The rounding mode used is specified by RMC.", "syntax": "drintx. R,FRT,FRB,RMC", "operands": [ { "name": "R", "desc": "Rounding mode control bit" }, { "name": "FRT", "desc": "Target Floating-Point Register" }, { "name": "FRB", "desc": "Source Floating-Point Register" }, { "name": "RMC", "desc": "Rounding mode control field" } ], "encoding": { "format": "Z23-form", "hex_opcode": "0xEC0000C6", "length": "32", "binary_pattern": "0 | R | FRT | FRB | RMC | Rc", "bit_positions": "0:5 | 6:10 | 11:14 | 15 | 16:20 | 21:31" }, "extension": "Decimal Floating-Point", "pseudocode": "if 'drintx' then\n FRT <- round(FRB, RMC)\n if result differs from FRB then\n raise inexact exception", "special_registers": "FPSCR, (FPRF, FR, FI, FX, XX), VXSNAN, CR1, (if, Rc=1), CR0", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "extended_mnemonics": [ "drintx." ], "page_found": "Page 254 - 256", "example": "drintx 0, f1, f3, 0" }, { "mnemonic": "drintn.", "architecture": "PowerISA", "full_name": "Decimal Floating-Point Round To FP Integer Without Inexact (Record)", "summary": "Rounds a decimal floating-point number to an integer without recognizing an inexact exception.", "description": "This operation rounds the value in FRB to an integer using the specified rounding mode (RMC) and places the result in FRT. It does not recognize an inexact exception.", "syntax": "drintn. R,FRT,FRB,RMC", "operands": [ { "name": "R", "desc": "Rounding mode control" }, { "name": "FRT", "desc": "Target Floating-Point Register" }, { "name": "FRB", "desc": "Source Floating-Point Register" }, { "name": "RMC", "desc": "Rounding Mode Control" } ], "encoding": { "format": "Z23-form", "hex_opcode": "0xEC0001C6", "length": "32", "binary_pattern": "0 | FRT | R | FRB | RMC | Rc", "bit_positions": "0:5 | 6:10 | 11:14 | 15 | 16:20 | 21:31" }, "extension": "Decimal Floating-Point", "pseudocode": "if 'drintn' then\n FRT <- Round(FRB, RMC)\n FI <- 0\n FR <- 0\n VXSNAN <- 0\n if Rc=1 then\n CR1 <- ClassAndSign(FRT)\nelse if 'drintn.' then\n FRT <- Round(FRB, RMC)\n FI <- 0\n FR <- 0\n VXSNAN <- 0\n CR1 <- ClassAndSign(FRT)", "special_registers": "FPSCR, (FPRF, FX, VXSNAN), FPSCR, (FR, FI), CR1, CR0", "programming_notes": "The DFP Round To FP Integer Without Inexact and DFP Round To FP Integer Without Inexact Quad instructions can be used to implement decimal equivalents of several C99 rounding functions by specifying the appropriate R and RMC field values.", "extended_mnemonics": [], "page_found": "Page 256 - 258", "example": "drintn 0, f1, f3, 0" }, { "mnemonic": "rldcr.", "architecture": "PowerISA", "full_name": "Rotate Left Doubleword then Clear Right (Record)", "summary": "Rotates the contents of register RS left by a variable number of bits specified by (RB)58:63, and clears the rightmost bits.", "description": "The contents of register RS are rotated 64 bits to the left by the number of bits specified by (RB)58:63. A mask is generated having 1-bits from bit 0 through bit ME and 0-bits elsewhere. The rotated data are ANDed with the generated mask, and the result is placed into register RA.", "syntax": "rldcr. RT,RS,RB,ME", "operands": [ { "name": "RT", "desc": "Target General Purpose Register" }, { "name": "RS", "desc": "Source General Purpose Register" }, { "name": "RB", "desc": "Source General Purpose Register" }, { "name": "ME", "desc": "Mask End bit position" } ], "encoding": { "format": "MDS-form", "hex_opcode": "0x78000012", "length": "32", "binary_pattern": "0 | RS | RA | RB | ME | 9 | Rc", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:26 | 27:30 | 31" }, "extension": "Base", "pseudocode": "if 'rldcr' then\n n ← (RB)58:63\n r ← ROTL64((RS), n)\n ME ← me5 || me0:4\n m ← MASK(0, ME)\n RA ← r & m\nif 'rldcr.' then\n CR0 <- updated based on result", "special_registers": "CR0 (if Rc=1)", "programming_notes": "rldcr can be used to extract an n-bit field that starts at variable bit position b in register RS, left-justified RA), by setting RB58:63=b and ME=n-1. It can also be used to rotate the contents of a register left (right) by variable n bits, by setting RB58:63=n (64-n) and ME=63.", "extended_mnemonics": [ "insrdi RA,RS,b,n" ], "page_found": "Page 147 - 148", "example": "rldcr r3, r3, r5, 31" }, { "mnemonic": "frip.", "architecture": "PowerISA", "full_name": "Floating Round to Integer Plus (Record)", "summary": "Rounds a floating-point operand towards +infinity and places the result into a register.", "description": "The floating-point operand in register FRB is rounded to an integral value using the rounding mode round toward +infinity, and the result is placed into register FRT. FPRF is set to the class and sign of the result, except for Invalid Operation Exceptions when VE=1.", "syntax": "frip. FRT,FRB", "operands": [ { "name": "FRT", "desc": "Target Floating-Point Register" }, { "name": "FRB", "desc": "Source Floating-Point Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0xFC000390", "length": "32", "binary_pattern": "0 | FRT | FRB | Rc", "bit_positions": "0:5 | 6:10 | 11:30 | 31" }, "extension": "Floating-Point", "pseudocode": "if 'frip' then\n FRT <- round_towards_plus_infinity(FRB)\nelse if 'frip.' then\n FRT <- round_towards_plus_infinity(FRB)\n update_CR1_based_on_result(FRT)", "special_registers": "FPSCR, CR, CR0", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "extended_mnemonics": [], "page_found": "Page 213 - 214", "example": "frip f1, f3" }, { "mnemonic": "vcmpequq.", "architecture": "PowerISA", "full_name": "Vector Compare Equal Quadword (Record)", "summary": "Compares two quadwords and sets the result to all ones if they are equal, otherwise all zeros.", "description": "Compares each quadword element of VRA with the corresponding quadword element of VRB for equality; the result for each quadword is all ones if equal or all zeros if not equal. If the Rc bit is set, CR6 is updated with summary information. Requires VMX support.", "syntax": "vcmpequq. VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VC-form", "hex_opcode": "0x100001C7", "length": "32", "binary_pattern": "0 | VRT | VRA | VRB | Rc", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VMX (AltiVec)", "pseudocode": "for i in 0 to 1 do\n if VRA[i*128:(i+1)*128-1] = VRB[i*128:(i+1)*128-1] then\n VRT[i*128:(i+1)*128-1] ← 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF\n else\n VRT[i*128:(i+1)*128-1] ← 0x00000000000000000000000000000000\n end if\nend for\nif Rc then\n CR6 ← summary of results\nend if", "special_registers": "CR6", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "extended_mnemonics": [], "page_found": "Page 417 - 418", "example": "vcmpequq v1, v2, v3" }, { "mnemonic": "vcmpgtsq.", "architecture": "PowerISA", "full_name": "Vector Compare Greater Than Signed Quadword (Record)", "summary": "Compares two signed quadwords and sets the result based on whether the first is greater than the second.", "description": "For vcmpgtsq, the contents of VSR[VRA+32] (src1) are compared to the contents of VSR[VRB+32] (src2). If src1 > src2, VSR[VRT+32] is set to all 1s; otherwise, it is set to all 0s. If Rc=1, CR field 6 is updated.", "syntax": "vcmpgtsq. VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VC-form", "hex_opcode": "0x10000387", "length": "32", "binary_pattern": "4 | VRT | VRA | VRB | Rc", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nall_true ←1\nall_false ←1\nsrc1 ←EXTS(VSR[VRA+32])\nsrc2 ←EXTS(VSR[VRB+32])\nif src1 > src2 then do\n VSR[VRT+32] ← 0xFFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF\n all_false ←0\nend else do\n VSR[VRT+32] ← 0x0000_0000_0000_0000_0000_0000_0000_0000\n all_true ←0\nend\nif Rc=1 then\n CR.field[6] ←all_true || 0b0 || all_false || 0b0", "special_registers": "CR6 (if Rc=1)", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "extended_mnemonics": [], "page_found": "Page 422 - 423", "example": "vcmpgtsq v1, v2, v3" }, { "mnemonic": "vstrihr.", "architecture": "PowerISA", "full_name": "Vector String Isolate Halfword Right-justified (Record)", "summary": "Isolates the rightmost non-zero halfword in a vector string.", "description": "From right to left, the contents of each halfword element of VSR[VRB+32] are placed into the corresponding halfword element in VSR[VRT+32]. If a halfword element in VSR[VRB+32] is found to contain 0, the corresponding halfword element and all halfword elements to the left of that halfword element in VSR[VRT+32] are set to 0.", "syntax": "vstrihr. VRT,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "VC-form", "hex_opcode": "0x1003000D", "length": "32", "binary_pattern": "0 | VRT | VRB | Rc | 13", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VMX (AltiVec)", "pseudocode": "if MSR.VEC=0 then\n Vector_Unavailable()\nnull_found ← 0\nwhile (!null_found) do i = 0 to 7\n null_found ← (VSR[VRB+32].hword[7-i] = 0)\n VSR[VRT+32].hword[7-i] ← VSR[VRB+32].hword[7-i]\nend\ndo j = i to 7\n VSR[VRT+32].hword[7-j] ← 0\nend\nif Rc=1 then\n CR.field[6] ← 0b00 || null_found || 0b0", "special_registers": "CR6 (if Rc=1)", "programming_notes": "When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.", "extended_mnemonics": [], "page_found": "Page 498 - 499", "example": "vstrihr v1, v3" }, { "mnemonic": "xsmsubqpo", "architecture": "PowerISA", "full_name": "VSX Scalar Multiply-Subtract Quad-Precision (Overflow)", "summary": "Performs a multiply-subtract operation on quad-precision floating-point values.", "description": "Performs a scalar multiply-subtract operation on quad-precision floating-point values, computing VRT = VRT - (VRA × VRB). The result is rounded according to the current rounding mode in FPSCR. This instruction requires VSX support and updates FPSCR exception flags based on the operation result.", "syntax": "xsmsubqpo VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0xFC000348", "length": "32", "binary_pattern": "18 | VRT | VRA | VRB | RO", "bit_positions": "0:5 | 6:10 | 11:15 | 16:20 | 21:31" }, "extension": "VSX", "pseudocode": "VRT[0:127] ← VRT[0:127] - (VRA[0:127] × VRB[0:127])\nFPSCR ← update_exception_flags(FPSCR, result)", "special_registers": "FPSCR", "programming_notes": "The xsmsubqp instruction is used for performing a multiply-subtract operation on quad-precision floating-point numbers. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid an exception. Be cautious of rounding modes and exceptions, as they can affect the result and set flags in the FPSCR register. This instruction operates on 128-bit aligned data in vector registers VSR[VRA+32], VSR[VRT+32], and VSR[VRB+32].", "extended_mnemonics": [], "page_found": "Page 698 - 699", "example": "xsmsubqp v1, v2, v3" }, { "mnemonic": "xsnmaddqpo", "architecture": "PowerISA", "full_name": "VSX Scalar Negative Multiply-Add Quad-Precision (Overflow)", "summary": "Performs a negative multiply-add operation on quad-precision floating-point values.", "description": "Performs a scalar negative multiply-add operation on quad-precision floating-point values, computing VRT = -(VRA × VRB) + VRT. The result is rounded according to the current rounding mode in FPSCR. This instruction requires VSX support and updates FPSCR exception flags based on the operation result.", "syntax": "xsnmaddqpo VRT,VRA,VRB", "operands": [ { "name": "VRT", "desc": "Target Vector Register" }, { "name": "VRA", "desc": "Source Vector Register" }, { "name": "VRB", "desc": "Source Vector Register" } ], "encoding": { "format": "X-form", "hex_opcode": "0xFC000388", "length": "32", "binary_pattern": "11110001 | 00000000 | 00000000 | 1000", "bit_positions": "0:5 | 6:10 | 11:15 | 16:31" }, "extension": "VSX", "pseudocode": "VRT[0:127] ← -(VRA[0:127] × VRB[0:127]) + VRT[0:127]\nFPSCR ← update_exception_flags(FPSCR, result)", "special_registers": "FPSCR FPRF FR FI FX VXSNAN VXIMZ VXISI OX UX XX", "programming_notes": "This instruction is used for performing a scalar negative multiply-add operation on quad-precision floating-point numbers. Ensure that the VSX feature is enabled in the MSR register to avoid exceptions. Be cautious of potential overflow and underflow conditions, as indicated by the OX and UX flags in the FPSCR register. The result is rounded according to the rounding mode specified in FPSCR.RN.", "extended_mnemonics": [ "xsnmaddqp[o]" ], "page_found": "Page 708 - 709", "example": "xsnmaddqp v1, v2, v3" } ] }