{ "architecture": "RISC-V", "instructions": [ { "mnemonic": "VANDN.VV", "architecture": "RISC-V", "extension": "Zvbb", "full_name": "Vector Bitwise AND-NOT", "summary": "Computes vd = vs2 & ~vs1 (bitwise AND with inverted source).", "syntax": "VANDN.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "000001 | vm | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0x04000057", "visual_parts": [ { "raw": "000001", "clean": "000001", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = vs2[i] & ~vs1[i];", "description": "Performs element-wise AND with inverted source (vs2 op ~vs1), writing results to vd.", "example": "VANDN.VV v1, v4, v2, v0.t" }, { "mnemonic": "VROL.VV", "architecture": "RISC-V", "extension": "Zvbb", "full_name": "Vector Rotate Left", "summary": "Rotates bits in elements of vs2 left by amounts in vs1.", "syntax": "VROL.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "010101 | vm | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0x54000057", "visual_parts": [ { "raw": "010101", "clean": "010101", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = (vs2[i] << vs1[i]) | (vs2[i] >> (SEW - vs1[i]));", "description": "Rotates each vector element left by the corresponding shift amount.", "example": "VROL.VV v1, v4, v2, v0.t" }, { "mnemonic": "VROR.VV", "architecture": "RISC-V", "extension": "Zvbb", "full_name": "Vector Rotate Right", "summary": "Rotates bits in elements of vs2 right by amounts in vs1.", "syntax": "VROR.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "010100 | vm | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0x50000057", "visual_parts": [ { "raw": "010100", "clean": "010100", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = (vs2[i] >> vs1[i]) | (vs2[i] << (SEW - vs1[i]));", "description": "Rotates each vector element right by the corresponding shift amount.", "example": "VROR.VV v1, v4, v2, v0.t" }, { "mnemonic": "VROL.VX", "architecture": "RISC-V", "extension": "Zvbb", "full_name": "Vector Rotate Left Scalar", "summary": "Rotates bits in elements of vs2 left by scalar rs1.", "syntax": "VROL.VX vd, vs2, rs1, vm", "encoding": { "format": "OPIVX", "binary_pattern": "010101 | vm | vs2 | rs1 | 100 | vd | 1010111", "hex_opcode": "0x54004057", "visual_parts": [ { "raw": "010101", "clean": "010101", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "100", "clean": "100", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "rs1", "desc": "Source register 1 (integer)" } ], "pseudocode": "foreach(i < vl): vd[i] = rotate_left(vs2[i], rs1);", "description": "Rotates each vector element left by the corresponding shift amount.", "example": "VROL.VX v1, v4, a0, v0.t" }, { "mnemonic": "VROR.VX", "architecture": "RISC-V", "extension": "Zvbb", "full_name": "Vector Rotate Right Scalar", "summary": "Rotates bits in elements of vs2 right by scalar rs1.", "syntax": "VROR.VX vd, vs2, rs1, vm", "encoding": { "format": "OPIVX", "binary_pattern": "010100 | vm | vs2 | rs1 | 100 | vd | 1010111", "hex_opcode": "0x50004057", "visual_parts": [ { "raw": "010100", "clean": "010100", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "100", "clean": "100", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "rs1", "desc": "Source register 1 (integer)" } ], "pseudocode": "foreach(i < vl): vd[i] = rotate_right(vs2[i], rs1);", "description": "Rotates each vector element right by the corresponding shift amount.", "example": "VROR.VX v1, v4, a0, v0.t" }, { "mnemonic": "VBREV8.V", "architecture": "RISC-V", "extension": "Zvbb", "full_name": "Vector Byte Reverse", "summary": "Reverses the bits within each byte of the source elements.", "syntax": "VBREV8.V vd, vs2, vm", "encoding": { "format": "OPIVV", "binary_pattern": "010010 | vm | vs2 | 01000010 | vd | 1010111", "hex_opcode": "0x48042057", "visual_parts": [ { "raw": "010010", "clean": "010010", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "01000010", "clean": "01000010", "pos": "19:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" } ], "pseudocode": "foreach(i < vl): vd[i] = reverse_bits_in_bytes(vs2[i]);", "description": "Reverses the bit or byte order within each vector element.", "example": "VBREV8.V v1, v4, v0.t" }, { "mnemonic": "VREV8.V", "architecture": "RISC-V", "extension": "Zvbb", "full_name": "Vector Reverse 8", "summary": "Reverses the order of bytes within each element (Endian swap).", "syntax": "VREV8.V vd, vs2, vm", "encoding": { "format": "OPIVV", "binary_pattern": "010010 | vm | vs2 | 01001010 | vd | 1010111", "hex_opcode": "0x4804A057", "visual_parts": [ { "raw": "010010", "clean": "010010", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "01001010", "clean": "01001010", "pos": "19:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" } ], "pseudocode": "foreach(i < vl): vd[i] = bswap(vs2[i]);", "description": "Reverses the bit or byte order within each vector element.", "example": "VREV8.V v1, v4, v0.t" }, { "mnemonic": "VCLZ.V", "architecture": "RISC-V", "extension": "Zvbb", "full_name": "Vector Count Leading Zeros", "summary": "Counts the number of leading zero bits in each element.", "syntax": "VCLZ.V vd, vs2, vm", "encoding": { "format": "OPIVV", "binary_pattern": "010010 | vm | vs2 | 01100010 | vd | 1010111", "hex_opcode": "0x48062057", "visual_parts": [ { "raw": "010010", "clean": "010010", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "01100010", "clean": "01100010", "pos": "19:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" } ], "pseudocode": "foreach(i < vl): vd[i] = count_leading_zeros(vs2[i]);", "description": "Counts the number of leading zero bits in each active vector element, writing counts to vd.", "example": "VCLZ.V v1, v4, v0.t" }, { "mnemonic": "VCTZ.V", "architecture": "RISC-V", "extension": "Zvbb", "full_name": "Vector Count Trailing Zeros", "summary": "Counts the number of trailing zero bits in each element.", "syntax": "VCTZ.V vd, vs2, vm", "encoding": { "format": "OPIVV", "binary_pattern": "010010 | vm | vs2 | 01101010 | vd | 1010111", "hex_opcode": "0x4806A057", "visual_parts": [ { "raw": "010010", "clean": "010010", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "01101010", "clean": "01101010", "pos": "19:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" } ], "pseudocode": "foreach(i < vl): vd[i] = count_trailing_zeros(vs2[i]);", "description": "Counts the number of trailing zero bits in each active vector element, writing counts to vd.", "example": "VCTZ.V v1, v4, v0.t" }, { "mnemonic": "VCPOP.V", "architecture": "RISC-V", "extension": "Zvbb", "full_name": "Vector Population Count", "summary": "Counts the number of set bits (1s) in each element.", "syntax": "VCPOP.V vd, vs2, vm", "encoding": { "format": "OPIVV", "binary_pattern": "010010 | vm | vs2 | 01110010 | vd | 1010111", "hex_opcode": "0x48072057", "visual_parts": [ { "raw": "010010", "clean": "010010", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "01110010", "clean": "01110010", "pos": "19:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" } ], "pseudocode": "foreach(i < vl): vd[i] = count_set_bits(vs2[i]);", "description": "Counts the number of set bits in mask register vs2 that are active (within vl), writing the count to scalar rd.", "example": "VCPOP.V v1, v4, v0.t" }, { "mnemonic": "VWSLL.VV", "architecture": "RISC-V", "extension": "Zvbb", "full_name": "Vector Widening Shift Left Logical", "summary": "Shifts N-bit elements left to produce 2*N-bit results.", "syntax": "VWSLL.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "110101 | vm | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0xD4000057", "visual_parts": [ { "raw": "110101", "clean": "110101", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest (Wide)" }, { "name": "vs2", "desc": "Src (Narrow)" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = zext(vs2[i]) << vs1[i];", "description": "Performs a widening operation, producing results twice as wide as the source elements. Results are written to vd using 2× the element grouping (EEW). The number of elements and masking are governed by vl and vm.", "example": "VWSLL.VV v1, v4, v2, v0.t" }, { "mnemonic": "VAESDF.VV", "architecture": "RISC-V", "extension": "Zvkned", "full_name": "Vector AES Decryption Final Round", "summary": "Performs the final AES decryption round.", "syntax": "VAESDF.VV vd, vs2, vs1", "encoding": { "format": "OPIVV", "binary_pattern": "1010001 | vs2 | 00001010 | vd | 1110111", "hex_opcode": "0xA200A077", "visual_parts": [ { "raw": "1010001", "clean": "1010001", "pos": "31:25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "00001010", "clean": "00001010", "pos": "19:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1110111", "clean": "1110111", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "State" }, { "name": "vs2", "desc": "Round Key" }, { "name": "vs1", "desc": "Undef" } ], "pseudocode": "vd = AES_Decrypt_Final(vd, vs2);", "description": "Performs a vectorised AES cryptographic round operation. Each element group undergoes one step of the cipher algorithm in parallel. See the Zvk vector crypto extension for full semantic details.", "example": "VAESDF.VV v1, v4, v2" }, { "mnemonic": "VAESDM.VV", "architecture": "RISC-V", "extension": "Zvkned", "full_name": "Vector AES Decryption Middle Round", "summary": "Performs a middle AES decryption round.", "syntax": "VAESDM.VV vd, vs2, vs1", "encoding": { "format": "OPIVV", "binary_pattern": "1010001 | vs2 | 00000010 | vd | 1110111", "hex_opcode": "0xA2002077", "visual_parts": [ { "raw": "1010001", "clean": "1010001", "pos": "31:25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "00000010", "clean": "00000010", "pos": "19:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1110111", "clean": "1110111", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "State" }, { "name": "vs2", "desc": "Round Key" }, { "name": "vs1", "desc": "Undef" } ], "pseudocode": "vd = AES_Decrypt_Middle(vd, vs2);", "description": "Performs a vectorised AES cryptographic round operation. Each element group undergoes one step of the cipher algorithm in parallel. See the Zvk vector crypto extension for full semantic details.", "example": "VAESDM.VV v1, v4, v2" }, { "mnemonic": "VAESEF.VV", "architecture": "RISC-V", "extension": "Zvkned", "full_name": "Vector AES Encryption Final Round", "summary": "Performs the final AES encryption round.", "syntax": "VAESEF.VV vd, vs2, vs1", "encoding": { "format": "OPIVV", "binary_pattern": "1010001 | vs2 | 00011010 | vd | 1110111", "hex_opcode": "0xA201A077", "visual_parts": [ { "raw": "1010001", "clean": "1010001", "pos": "31:25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "00011010", "clean": "00011010", "pos": "19:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1110111", "clean": "1110111", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "State" }, { "name": "vs2", "desc": "Round Key" }, { "name": "vs1", "desc": "Undef" } ], "pseudocode": "vd = AES_Encrypt_Final(vd, vs2);", "description": "Performs a vectorised AES cryptographic round operation. Each element group undergoes one step of the cipher algorithm in parallel. See the Zvk vector crypto extension for full semantic details.", "example": "VAESEF.VV v1, v4, v2" }, { "mnemonic": "VAESEM.VV", "architecture": "RISC-V", "extension": "Zvkned", "full_name": "Vector AES Encryption Middle Round", "summary": "Performs a middle AES encryption round.", "syntax": "VAESEM.VV vd, vs2, vs1", "encoding": { "format": "OPIVV", "binary_pattern": "1010001 | vs2 | 00010010 | vd | 1110111", "hex_opcode": "0xA2012077", "visual_parts": [ { "raw": "1010001", "clean": "1010001", "pos": "31:25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "00010010", "clean": "00010010", "pos": "19:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1110111", "clean": "1110111", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "State" }, { "name": "vs2", "desc": "Round Key" }, { "name": "vs1", "desc": "Undef" } ], "pseudocode": "vd = AES_Encrypt_Middle(vd, vs2);", "description": "Performs a vectorised AES cryptographic round operation. Each element group undergoes one step of the cipher algorithm in parallel. See the Zvk vector crypto extension for full semantic details.", "example": "VAESEM.VV v1, v4, v2" }, { "mnemonic": "VAESKF1.VI", "architecture": "RISC-V", "extension": "Zvkned", "full_name": "Vector AES Key Expansion 1", "summary": "Generates the next round key for AES (Step 1).", "syntax": "VAESKF1.VI vd, vs2, uimm", "encoding": { "format": "OPIVI", "binary_pattern": "1000101 | vs2 | zimm5 | 010 | vd | 1110111", "hex_opcode": "0x8A002077", "visual_parts": [ { "raw": "1000101", "clean": "1000101", "pos": "31:25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "zimm5", "clean": "zimm5", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1110111", "clean": "1110111", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "uimm", "desc": "RCON" } ], "pseudocode": "vd = AES_KeyGen_1(vs2, uimm);", "description": "Performs a vectorised AES cryptographic round operation. Each element group undergoes one step of the cipher algorithm in parallel. See the Zvk vector crypto extension for full semantic details.", "example": "VAESKF1.VI v1, v4, 4" }, { "mnemonic": "VAESKF2.VI", "architecture": "RISC-V", "extension": "Zvkned", "full_name": "Vector AES Key Expansion 2", "summary": "Generates the next round key for AES (Step 2).", "syntax": "VAESKF2.VI vd, vs2, uimm", "encoding": { "format": "OPIVI", "binary_pattern": "1010101 | vs2 | zimm5 | 010 | vd | 1110111", "hex_opcode": "0xAA002077", "visual_parts": [ { "raw": "1010101", "clean": "1010101", "pos": "31:25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "zimm5", "clean": "zimm5", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1110111", "clean": "1110111", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "uimm", "desc": "Round" } ], "pseudocode": "vd = AES_KeyGen_2(vs2, uimm);", "description": "Performs a vectorised AES cryptographic round operation. Each element group undergoes one step of the cipher algorithm in parallel. See the Zvk vector crypto extension for full semantic details.", "example": "VAESKF2.VI v1, v4, 4" }, { "mnemonic": "VSHA2CH.VV", "architecture": "RISC-V", "extension": "Zvknha", "full_name": "Vector SHA-2 Compress High", "summary": "Performs SHA-256 compression (high 128 bits).", "syntax": "VSHA2CH.VV vd, vs2, vs1", "encoding": { "format": "OPIVV", "binary_pattern": "1011101 | vs2 | vs1 | 010 | vd | 1110111", "hex_opcode": "0xBA002077", "visual_parts": [ { "raw": "1011101", "clean": "1011101", "pos": "31:25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1110111", "clean": "1110111", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "State" }, { "name": "vs2", "desc": "Message" }, { "name": "vs1", "desc": "State B" } ], "pseudocode": "vd = SHA256_Compress_High(vd, vs1, vs2);", "description": "Performs a vectorised SHA cryptographic round operation. Each element group undergoes one step of the cipher algorithm in parallel. See the Zvk vector crypto extension for full semantic details.", "example": "VSHA2CH.VV v1, v4, v2" }, { "mnemonic": "VSHA2CL.VV", "architecture": "RISC-V", "extension": "Zvknha", "full_name": "Vector SHA-2 Compress Low", "summary": "Performs SHA-256 compression (low 128 bits).", "syntax": "VSHA2CL.VV vd, vs2, vs1", "encoding": { "format": "OPIVV", "binary_pattern": "1011111 | vs2 | vs1 | 010 | vd | 1110111", "hex_opcode": "0xBE002077", "visual_parts": [ { "raw": "1011111", "clean": "1011111", "pos": "31:25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1110111", "clean": "1110111", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "State" }, { "name": "vs2", "desc": "Message" }, { "name": "vs1", "desc": "State B" } ], "pseudocode": "vd = SHA256_Compress_Low(vd, vs1, vs2);", "description": "Performs a vectorised SHA cryptographic round operation. Each element group undergoes one step of the cipher algorithm in parallel. See the Zvk vector crypto extension for full semantic details.", "example": "VSHA2CL.VV v1, v4, v2" }, { "mnemonic": "VSHA2MS.VV", "architecture": "RISC-V", "extension": "Zvknha", "full_name": "Vector SHA-2 Message Schedule", "summary": "Generates SHA-256 message schedule words.", "syntax": "VSHA2MS.VV vd, vs2, vs1", "encoding": { "format": "OPIVV", "binary_pattern": "1011011 | vs2 | vs1 | 010 | vd | 1110111", "hex_opcode": "0xB6002077", "visual_parts": [ { "raw": "1011011", "clean": "1011011", "pos": "31:25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1110111", "clean": "1110111", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "vd = SHA256_MsgSched(vd, vs1, vs2);", "description": "Performs a vectorised SHA cryptographic round operation. Each element group undergoes one step of the cipher algorithm in parallel. See the Zvk vector crypto extension for full semantic details.", "example": "VSHA2MS.VV v1, v4, v2" }, { "mnemonic": "VGHSH.VV", "architecture": "RISC-V", "extension": "Zvkg", "full_name": "Vector GCM Hash", "summary": "Performs GHASH multiply-add for AES-GCM.", "syntax": "VGHSH.VV vd, vs2, vs1", "encoding": { "format": "OPIVV", "binary_pattern": "1011001 | vs2 | vs1 | 010 | vd | 1110111", "hex_opcode": "0xB2002077", "visual_parts": [ { "raw": "1011001", "clean": "1011001", "pos": "31:25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1110111", "clean": "1110111", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Accumulator" }, { "name": "vs2", "desc": "Hash Key" }, { "name": "vs1", "desc": "Data" } ], "pseudocode": "vd = GHASH_MulAdd(vd, vs1, vs2);", "description": "Performs a vectorised GHASH cryptographic round operation. Each element group undergoes one step of the cipher algorithm in parallel. See the Zvk vector crypto extension for full semantic details.", "example": "VGHSH.VV v1, v4, v2" }, { "mnemonic": "VCLMUL.VV", "architecture": "RISC-V", "extension": "Zvbc", "full_name": "Vector Carry-less Multiply", "summary": "Performs carry-less multiplication on vector elements (GF(2^n)).", "syntax": "VCLMUL.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "001100 | vm | vs2 | vs1 | 010 | vd | 1010111", "hex_opcode": "0x30002057", "visual_parts": [ { "raw": "001100", "clean": "001100", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = clmul(vs1[i], vs2[i]);", "description": "Performs carry-less multiplication of vector elements (GF(2^n)), used in GHASH for GCM mode and CRC computation.", "example": "VCLMUL.VV v1, v4, v2, v0.t" }, { "mnemonic": "VCLMULH.VV", "architecture": "RISC-V", "extension": "Zvbc", "full_name": "Vector Carry-less Multiply High", "summary": "Performs carry-less multiplication, keeping the high half.", "syntax": "VCLMULH.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "001101 | vm | vs2 | vs1 | 010 | vd | 1010111", "hex_opcode": "0x34002057", "visual_parts": [ { "raw": "001101", "clean": "001101", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = clmulh(vs1[i], vs2[i]);", "description": "Performs carry-less multiplication of vector elements (GF(2^n)), used in GHASH for GCM mode and CRC computation.", "example": "VCLMULH.VV v1, v4, v2, v0.t" }, { "mnemonic": "VCPOP.M", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Mask Population Count", "summary": "Counts set bits in the source mask register.", "syntax": "VCPOP.M rd, vs2, vm", "encoding": { "format": "OPMVX", "binary_pattern": "010000 | vm | vs2 | 10000010 | rd | 1010111", "hex_opcode": "0x40082057", "visual_parts": [ { "raw": "010000", "clean": "010000", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "10000010", "clean": "10000010", "pos": "19:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Scalar)" }, { "name": "vs2", "desc": "Src Mask" } ], "pseudocode": "rd = count_set_bits(vs2 & vm);", "description": "Counts the number of set bits in mask register vs2 that are active (within vl), writing the count to scalar rd.", "example": "VCPOP.M t0, v4, v0.t" }, { "mnemonic": "VFIRST.M", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Find First Set Mask Bit", "summary": "Finds the index of the first set bit in the mask.", "syntax": "VFIRST.M rd, vs2, vm", "encoding": { "format": "OPMVX", "binary_pattern": "010000 | vm | vs2 | 10001010 | rd | 1010111", "hex_opcode": "0x4008A057", "visual_parts": [ { "raw": "010000", "clean": "010000", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "10001010", "clean": "10001010", "pos": "19:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Index)" }, { "name": "vs2", "desc": "Src Mask" } ], "pseudocode": "rd = find_first_set(vs2 & vm);", "description": "Finds the index of the lowest-numbered active set bit in mask register vs2, writing the index to rd. Returns -1 if no bit is set.", "example": "VFIRST.M t0, v4, v0.t" }, { "mnemonic": "VMSBF.M", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Mask Set Before First", "summary": "Sets mask bits before the first set bit in the source mask.", "syntax": "VMSBF.M vd, vs2, vm", "encoding": { "format": "OPMVV", "binary_pattern": "010100 | vm | vs2 | 00001010 | vd | 1010111", "hex_opcode": "0x5000A057", "visual_parts": [ { "raw": "010100", "clean": "010100", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "00001010", "clean": "00001010", "pos": "19:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest Mask" }, { "name": "vs2", "desc": "Src Mask" } ], "pseudocode": "Set 1s up to the first 1 in vs2.", "description": "Sets each destination mask bit to 1 for elements before the first active set bit in vs2.", "example": "VMSBF.M v1, v4, v0.t" }, { "mnemonic": "VMSIF.M", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Mask Set Including First", "summary": "Sets mask bits up to and including the first set bit in the source.", "syntax": "VMSIF.M vd, vs2, vm", "encoding": { "format": "OPMVV", "binary_pattern": "010100 | vm | vs2 | 00011010 | vd | 1010111", "hex_opcode": "0x5001A057", "visual_parts": [ { "raw": "010100", "clean": "010100", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "00011010", "clean": "00011010", "pos": "19:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest Mask" }, { "name": "vs2", "desc": "Src Mask" } ], "pseudocode": "Set 1s up to and including the first 1 in vs2.", "description": "Sets each destination mask bit to 1 for elements up to and including the first active set bit in vs2.", "example": "VMSIF.M v1, v4, v0.t" }, { "mnemonic": "VMSOF.M", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Mask Set Only First", "summary": "Sets only the first set bit from the source mask.", "syntax": "VMSOF.M vd, vs2, vm", "encoding": { "format": "OPMVV", "binary_pattern": "010100 | vm | vs2 | 00010010 | vd | 1010111", "hex_opcode": "0x50012057", "visual_parts": [ { "raw": "010100", "clean": "010100", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "00010010", "clean": "00010010", "pos": "19:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest Mask" }, { "name": "vs2", "desc": "Src Mask" } ], "pseudocode": "vd = (1 << first_set_index(vs2)) & vm;", "description": "Sets only the destination mask bit corresponding to the first active set bit in vs2.", "example": "VMSOF.M v1, v4, v0.t" }, { "mnemonic": "VANDN.VX", "architecture": "RISC-V", "extension": "Zvbb", "full_name": "Vector Bitwise AND-NOT Scalar", "summary": "Computes vd = vs2 & ~rs1.", "syntax": "VANDN.VX vd, vs2, rs1, vm", "encoding": { "format": "OPIVX", "binary_pattern": "000001 | vm | vs2 | rs1 | 100 | vd | 1010111", "hex_opcode": "0x04004057", "visual_parts": [ { "raw": "000001", "clean": "000001", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "100", "clean": "100", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "rs1", "desc": "Scalar" } ], "pseudocode": "foreach(i < vl): vd[i] = vs2[i] & ~rs1;", "description": "Performs element-wise AND with inverted source (vs2 op ~vs1), writing results to vd.", "example": "VANDN.VX v1, v4, a0, v0.t" }, { "mnemonic": "VWSLL.VX", "architecture": "RISC-V", "extension": "Zvbb", "full_name": "Vector Widening Shift Left Logical Scalar", "summary": "Shifts elements left by scalar rs1, widening the result.", "syntax": "VWSLL.VX vd, vs2, rs1, vm", "encoding": { "format": "OPIVX", "binary_pattern": "110101 | vm | vs2 | rs1 | 100 | vd | 1010111", "hex_opcode": "0xD4004057", "visual_parts": [ { "raw": "110101", "clean": "110101", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "100", "clean": "100", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest (Wide)" }, { "name": "vs2", "desc": "Src (Narrow)" }, { "name": "rs1", "desc": "Source register 1 (integer)" } ], "pseudocode": "foreach(i < vl): vd[i] = zext(vs2[i]) << rs1;", "description": "Performs a widening operation, producing results twice as wide as the source elements. Results are written to vd using 2× the element grouping (EEW). The number of elements and masking are governed by vl and vm.", "example": "VWSLL.VX v1, v4, a0, v0.t" }, { "mnemonic": "VWSLL.VI", "architecture": "RISC-V", "extension": "Zvbb", "full_name": "Vector Widening Shift Left Logical Immediate", "summary": "Shifts elements left by immediate, widening the result.", "syntax": "VWSLL.VI vd, vs2, imm, vm", "encoding": { "format": "OPIVI", "binary_pattern": "110101 | vm | vs2 | zimm5 | 011 | vd | 1010111", "hex_opcode": "0xD4003057", "visual_parts": [ { "raw": "110101", "clean": "110101", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "zimm5", "clean": "zimm5", "pos": "19:15" }, { "raw": "011", "clean": "011", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest (Wide)" }, { "name": "vs2", "desc": "Src (Narrow)" }, { "name": "imm", "desc": "Signed immediate value" } ], "pseudocode": "foreach(i < vl): vd[i] = zext(vs2[i]) << imm;", "description": "Performs a widening operation, producing results twice as wide as the source elements. Results are written to vd using 2× the element grouping (EEW). The number of elements and masking are governed by vl and vm.", "example": "VWSLL.VI v1, v4, 16, v0.t" }, { "mnemonic": "BLTU", "architecture": "RISC-V", "extension": "RV32I", "full_name": "Branch if Less Than Unsigned", "summary": "Take the branch if rs1 is less than rs2 (unsigned comparison).", "syntax": "BLTU rs1, rs2, offset", "encoding": { "format": "B-Type", "binary_pattern": "bimm12hi | rs2 | rs1 | 110 | bimm12lo | 1100011", "hex_opcode": "0x00006063", "visual_parts": [ { "raw": "bimm12hi", "clean": "bimm12hi", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "110", "clean": "110", "pos": "14:12" }, { "raw": "bimm12lo", "clean": "bimm12lo", "pos": "11:7" }, { "raw": "1100011", "clean": "1100011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" }, { "name": "offset", "desc": "Offset" } ], "pseudocode": "if (R[rs1] =u R[rs2]) PC += sext(offset);", "description": "BGEU takes the branch if rs1 is greater than or equal to rs2, treating both as unsigned integers. The branch target is the PC plus the sign-extended B-immediate.", "example": "BGEU a0, a1, 0" }, { "mnemonic": "FMV.X.D", "architecture": "RISC-V", "extension": "D", "full_name": "Move Double to Integer", "summary": "Moves the bit pattern of a 64-bit floating-point register to an integer register (RV64).", "syntax": "FMV.X.D rd, rs1", "encoding": { "format": "I-Type (Float)", "binary_pattern": "111000100000 | rs1 | 000 | rd | 1010011", "hex_opcode": "0xE2000053", "visual_parts": [ { "raw": "111000100000", "clean": "111000100000", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Int64)" }, { "name": "rs1", "desc": "Source (Double)" } ], "pseudocode": "R[rd] = F[rs1];", "description": "Moves bits from a floating-point register to an integer register (or vice versa) without conversion. The bit pattern is preserved exactly.", "example": "FMV.X.D t0, a0" }, { "mnemonic": "FMV.D.X", "architecture": "RISC-V", "extension": "D", "full_name": "Move Integer to Double", "summary": "Moves the bit pattern of a 64-bit integer register to a floating-point register (RV64).", "syntax": "FMV.D.X rd, rs1", "encoding": { "format": "I-Type (Float)", "binary_pattern": "111100100000 | rs1 | 000 | rd | 1010011", "hex_opcode": "0xF2000053", "visual_parts": [ { "raw": "111100100000", "clean": "111100100000", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Double)" }, { "name": "rs1", "desc": "Source (Int64)" } ], "pseudocode": "F[rd] = R[rs1];", "description": "Moves bits from a floating-point register to an integer register (or vice versa) without conversion. The bit pattern is preserved exactly.", "example": "FMV.D.X t0, a0" }, { "mnemonic": "FSGNJX.D", "architecture": "RISC-V", "extension": "D", "full_name": "Float Sign Injection XOR (Double)", "summary": "Injects the XOR of signs of rs1 and rs2 (Double Precision).", "syntax": "FSGNJX.D rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0010001 | rs2 | rs1 | 010 | rd | 1010011", "hex_opcode": "0x22002053", "visual_parts": [ { "raw": "0010001", "clean": "0010001", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" } ], "pseudocode": "F[rd] = {F[rs1][63] ^ F[rs2][63], F[rs1][62:0]};", "description": "Produces a result with the magnitude of rs1 and the sign bit taken from the source rs2. Used to implement floating-point absolute value, negate, and copy-sign.", "example": "FSGNJX.D t0, a0, a1" }, { "mnemonic": "C.NOP", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed No Operation", "summary": "Performs no operation (Compressed encoding).", "syntax": "C.NOP", "encoding": { "format": "CI", "binary_pattern": "? | 000 | c_nzimm6hi | 00000 | c_nzimm6lo | 01", "hex_opcode": "0x00000001", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "000", "clean": "000", "pos": "15:13" }, { "raw": "c_nzimm6hi", "clean": "c_nzimm6hi", "pos": "12" }, { "raw": "00000", "clean": "00000", "pos": "11:7" }, { "raw": "c_nzimm6lo", "clean": "c_nzimm6lo", "pos": "6:2" }, { "raw": "01", "clean": "01", "pos": "1:0" } ], "bit_positions": "31:16 | 15:13 | 12 | 11:7 | 6:2 | 1:0" }, "operands": [], "pseudocode": "R[0] = R[0] + 0;", "description": "No operation. Equivalent to C.ADDI x0, 0.", "example": "C.NOP" }, { "mnemonic": "C.ADDIW", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed Add Immediate Word", "summary": "Adds a signed immediate to a register (32-bit result sign-extended, RV64).", "syntax": "C.ADDIW rd, imm", "encoding": { "format": "CI", "binary_pattern": "? | 001 | c_imm6hi | rd_rs1_n0 | c_imm6lo | 01", "hex_opcode": "0x00002001", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "001", "clean": "001", "pos": "15:13" }, { "raw": "c_imm6hi", "clean": "c_imm6hi", "pos": "12" }, { "raw": "rd_rs1_n0", "clean": "rd_rs1_n0", "pos": "11:7" }, { "raw": "c_imm6lo", "clean": "c_imm6lo", "pos": "6:2" }, { "raw": "01", "clean": "01", "pos": "1:0" } ], "bit_positions": "31:16 | 15:13 | 12 | 11:7 | 6:2 | 1:0" }, "operands": [ { "name": "rd", "desc": "Dest/Src" }, { "name": "imm", "desc": "Signed immediate value" } ], "pseudocode": "R[rd] = sext((R[rd] + sext(imm))[31:0]);", "description": "Adds a 6-bit sign-extended immediate to rd (RV64/RV128 only), truncates to 32 bits, sign-extends to 64 bits.", "example": "C.ADDIW t0, 16" }, { "mnemonic": "C.ADDW", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed Add Word", "summary": "Adds two registers (32-bit result sign-extended, RV64).", "syntax": "C.ADDW rd', rs2'", "encoding": { "format": "CA", "binary_pattern": "? | 100111 | rd_rs1_p | 01 | rs2_p | 01", "hex_opcode": "0x00009C21", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "100111", "clean": "100111", "pos": "15:10" }, { "raw": "rd_rs1_p", "clean": "rd_rs1_p", "pos": "9:7" }, { "raw": "01", "clean": "01", "pos": "6:5" }, { "raw": "rs2_p", "clean": "rs2_p", "pos": "4:2" }, { "raw": "01", "clean": "01", "pos": "1:0" } ], "bit_positions": "31:16 | 15:10 | 9:7 | 6:5 | 4:2 | 1:0" }, "operands": [ { "name": "rd'", "desc": "Dest/Src1" }, { "name": "rs2'", "desc": "Source register 2 (3-bit compressed)" } ], "pseudocode": "R[rd'] = sext((R[rd'] + R[rs2'])[31:0]);", "description": "Adds rd and rs2 (16-bit), sign-extends the 32-bit result to 64 bits (RV64/RV128 only).", "example": "C.ADDW rd', rs2'" }, { "mnemonic": "C.SUBW", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed Subtract Word", "summary": "Subtracts two registers (32-bit result sign-extended, RV64).", "syntax": "C.SUBW rd', rs2'", "encoding": { "format": "CA", "binary_pattern": "? | 100111 | rd_rs1_p | 00 | rs2_p | 01", "hex_opcode": "0x00009C01", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "100111", "clean": "100111", "pos": "15:10" }, { "raw": "rd_rs1_p", "clean": "rd_rs1_p", "pos": "9:7" }, { "raw": "00", "clean": "00", "pos": "6:5" }, { "raw": "rs2_p", "clean": "rs2_p", "pos": "4:2" }, { "raw": "01", "clean": "01", "pos": "1:0" } ], "bit_positions": "31:16 | 15:10 | 9:7 | 6:5 | 4:2 | 1:0" }, "operands": [ { "name": "rd'", "desc": "Dest/Src1" }, { "name": "rs2'", "desc": "Source register 2 (3-bit compressed)" } ], "pseudocode": "R[rd'] = sext((R[rd'] - R[rs2'])[31:0]);", "description": "Subtracts rs2′ from rd′, truncates to 32 bits, sign-extends to 64 bits (RV64).", "example": "C.SUBW rd', rs2'" }, { "mnemonic": "C.LDSP", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed Load Doubleword from Stack Pointer", "summary": "Loads a 64-bit value from the stack pointer (RV64).", "syntax": "C.LDSP rd, offset(x2)", "encoding": { "format": "CI", "binary_pattern": "? | 011 | c_uimm9sphi | rd_n0 | c_uimm9splo | 10", "hex_opcode": "0x00006002", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "011", "clean": "011", "pos": "15:13" }, { "raw": "c_uimm9sphi", "clean": "c_uimm9sphi", "pos": "12" }, { "raw": "rd_n0", "clean": "rd_n0", "pos": "11:7" }, { "raw": "c_uimm9splo", "clean": "c_uimm9splo", "pos": "6:2" }, { "raw": "10", "clean": "10", "pos": "1:0" } ], "bit_positions": "31:16 | 15:13 | 12 | 11:7 | 6:2 | 1:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "offset", "desc": "Offset" } ], "pseudocode": "R[rd] = M[R[2] + offset][63:0];", "description": "Loads a 64-bit doubleword from a stack-pointer-relative address into rd (RV64).", "example": "C.LDSP t0, 0(a0)" }, { "mnemonic": "C.SDSP", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed Store Doubleword to Stack Pointer", "summary": "Stores a 64-bit value to the stack pointer (RV64).", "syntax": "C.SDSP rs2, offset(x2)", "encoding": { "format": "CSS", "binary_pattern": "? | 111 | c_uimm9sp_s | c_rs2 | 10", "hex_opcode": "0x0000E002", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "111", "clean": "111", "pos": "15:13" }, { "raw": "c_uimm9sp_s", "clean": "c_uimm9sp_s", "pos": "12:7" }, { "raw": "c_rs2", "clean": "c_rs2", "pos": "6:2" }, { "raw": "10", "clean": "10", "pos": "1:0" } ], "bit_positions": "31:16 | 15:13 | 12:7 | 6:2 | 1:0" }, "operands": [ { "name": "rs2", "desc": "Source" }, { "name": "offset", "desc": "Offset" } ], "pseudocode": "M[R[2] + offset][63:0] = R[rs2];", "description": "Stores a 64-bit doubleword from rs2 to a stack-pointer-relative address (RV64).", "example": "C.SDSP a1, 0(a0)" }, { "mnemonic": "C.FLWSP", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed Float Load Word from Stack Pointer", "summary": "Loads a single-precision float from the stack pointer.", "syntax": "C.FLWSP rd, offset(x2)", "encoding": { "format": "CI", "binary_pattern": "? | 011 | c_uimm8sphi | rd | c_uimm8splo | 10", "hex_opcode": "0x00006002", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "011", "clean": "011", "pos": "15:13" }, { "raw": "c_uimm8sphi", "clean": "c_uimm8sphi", "pos": "12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "c_uimm8splo", "clean": "c_uimm8splo", "pos": "6:2" }, { "raw": "10", "clean": "10", "pos": "1:0" } ], "bit_positions": "31:16 | 15:13 | 12 | 11:7 | 6:2 | 1:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "offset", "desc": "Offset" } ], "pseudocode": "F[rd] = M[R[2] + offset][31:0];", "description": "Loads a single-precision FP value from a stack-pointer-relative address into fd (RV32 only).", "example": "C.FLWSP t0, 0(a0)" }, { "mnemonic": "C.FSWSP", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed Float Store Word to Stack Pointer", "summary": "Stores a single-precision float to the stack pointer.", "syntax": "C.FSWSP rs2, offset(x2)", "encoding": { "format": "CSS", "binary_pattern": "? | 111 | c_uimm8sp_s | c_rs2 | 10", "hex_opcode": "0x0000E002", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "111", "clean": "111", "pos": "15:13" }, { "raw": "c_uimm8sp_s", "clean": "c_uimm8sp_s", "pos": "12:7" }, { "raw": "c_rs2", "clean": "c_rs2", "pos": "6:2" }, { "raw": "10", "clean": "10", "pos": "1:0" } ], "bit_positions": "31:16 | 15:13 | 12:7 | 6:2 | 1:0" }, "operands": [ { "name": "rs2", "desc": "Source" }, { "name": "offset", "desc": "Offset" } ], "pseudocode": "M[R[2] + offset][31:0] = F[rs2];", "description": "Stores a single-precision FP value from fd to a stack-pointer-relative address (RV32 only).", "example": "C.FSWSP a1, 0(a0)" }, { "mnemonic": "C.FLDSP", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed Float Load Double from Stack Pointer", "summary": "Loads a double-precision float from the stack pointer.", "syntax": "C.FLDSP rd, offset(x2)", "encoding": { "format": "CI", "binary_pattern": "? | 001 | c_uimm9sphi | rd | c_uimm9splo | 10", "hex_opcode": "0x00002002", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "001", "clean": "001", "pos": "15:13" }, { "raw": "c_uimm9sphi", "clean": "c_uimm9sphi", "pos": "12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "c_uimm9splo", "clean": "c_uimm9splo", "pos": "6:2" }, { "raw": "10", "clean": "10", "pos": "1:0" } ], "bit_positions": "31:16 | 15:13 | 12 | 11:7 | 6:2 | 1:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "offset", "desc": "Offset" } ], "pseudocode": "F[rd] = M[R[2] + offset][63:0];", "description": "Loads a double-precision FP value from a stack-pointer-relative address into fd.", "example": "C.FLDSP t0, 0(a0)" }, { "mnemonic": "C.FSDSP", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed Float Store Double to Stack Pointer", "summary": "Stores a double-precision float to the stack pointer.", "syntax": "C.FSDSP rs2, offset(x2)", "encoding": { "format": "CSS", "binary_pattern": "? | 101 | c_uimm9sp_s | c_rs2 | 10", "hex_opcode": "0x0000A002", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "101", "clean": "101", "pos": "15:13" }, { "raw": "c_uimm9sp_s", "clean": "c_uimm9sp_s", "pos": "12:7" }, { "raw": "c_rs2", "clean": "c_rs2", "pos": "6:2" }, { "raw": "10", "clean": "10", "pos": "1:0" } ], "bit_positions": "31:16 | 15:13 | 12:7 | 6:2 | 1:0" }, "operands": [ { "name": "rs2", "desc": "Source" }, { "name": "offset", "desc": "Offset" } ], "pseudocode": "M[R[2] + offset][63:0] = F[rs2];", "description": "Stores a double-precision FP value from fd to a stack-pointer-relative address.", "example": "C.FSDSP a1, 0(a0)" }, { "mnemonic": "VSUB.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Integer Subtract", "summary": "Subtracts elements of two vector registers.", "syntax": "VSUB.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "000010 | vm | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0x08000057", "visual_parts": [ { "raw": "000010", "clean": "000010", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Src 2 (Subtrahend)" }, { "name": "vs1", "desc": "Src 1 (Minuend)" } ], "pseudocode": "foreach(i < vl): vd[i] = vs1[i] - vs2[i];", "description": "Performs element-wise integer subtraction on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VSUB.VV v1, v4, v2, v0.t" }, { "mnemonic": "VRSUB.VX", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Integer Reverse Subtract Scalar", "summary": "Subtracts vector elements from a scalar value (scalar - vector).", "syntax": "VRSUB.VX vd, vs2, rs1, vm", "encoding": { "format": "OPIVX", "binary_pattern": "000011 | vm | vs2 | rs1 | 100 | vd | 1010111", "hex_opcode": "0x0C004057", "visual_parts": [ { "raw": "000011", "clean": "000011", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "100", "clean": "100", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Vector Src" }, { "name": "rs1", "desc": "Scalar Src" } ], "pseudocode": "foreach(i < vl): vd[i] = rs1 - vs2[i];", "description": "Performs element-wise reverse integer subtraction on a vector and a scalar register, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VRSUB.VX v1, v4, a0, v0.t" }, { "mnemonic": "VMIN.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Minimum (Signed)", "summary": "Computes the signed minimum of elements in two vectors.", "syntax": "VMIN.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "000101 | vm | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0x14000057", "visual_parts": [ { "raw": "000101", "clean": "000101", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = min(vs1[i], vs2[i]);", "description": "Performs element-wise signed minimum on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VMIN.VV v1, v4, v2, v0.t" }, { "mnemonic": "VMAX.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Maximum (Signed)", "summary": "Computes the signed maximum of elements in two vectors.", "syntax": "VMAX.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "000111 | vm | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0x1C000057", "visual_parts": [ { "raw": "000111", "clean": "000111", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = max(vs1[i], vs2[i]);", "description": "Performs element-wise signed maximum on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VMAX.VV v1, v4, v2, v0.t" }, { "mnemonic": "VMINU.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Minimum (Unsigned)", "summary": "Computes the unsigned minimum of elements in two vectors.", "syntax": "VMINU.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "000100 | vm | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0x10000057", "visual_parts": [ { "raw": "000100", "clean": "000100", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = min_u(vs1[i], vs2[i]);", "description": "Performs element-wise unsigned minimum on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VMINU.VV v1, v4, v2, v0.t" }, { "mnemonic": "VMAXU.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Maximum (Unsigned)", "summary": "Computes the unsigned maximum of elements in two vectors.", "syntax": "VMAXU.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "000110 | vm | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0x18000057", "visual_parts": [ { "raw": "000110", "clean": "000110", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = max_u(vs1[i], vs2[i]);", "description": "Performs element-wise unsigned maximum on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VMAXU.VV v1, v4, v2, v0.t" }, { "mnemonic": "VOR.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Bitwise OR", "summary": "Performs bitwise OR on elements of two vectors.", "syntax": "VOR.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "001010 | vm | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0x28000057", "visual_parts": [ { "raw": "001010", "clean": "001010", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = vs1[i] | vs2[i];", "description": "Performs element-wise bitwise OR on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VOR.VV v1, v4, v2, v0.t" }, { "mnemonic": "VXOR.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Bitwise XOR", "summary": "Performs bitwise XOR on elements of two vectors.", "syntax": "VXOR.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "001011 | vm | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0x2C000057", "visual_parts": [ { "raw": "001011", "clean": "001011", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = vs1[i] ^ vs2[i];", "description": "Performs element-wise bitwise XOR on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VXOR.VV v1, v4, v2, v0.t" }, { "mnemonic": "VSLL.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Shift Left Logical", "summary": "Shifts elements of vector vs2 left by amounts in vs1.", "syntax": "VSLL.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "100101 | vm | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0x94000057", "visual_parts": [ { "raw": "100101", "clean": "100101", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source" }, { "name": "vs1", "desc": "Shift Amount" } ], "pseudocode": "foreach(i < vl): vd[i] = vs2[i] << (vs1[i] & Mask);", "description": "Performs element-wise left logical shift on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VSLL.VV v1, v4, v2, v0.t" }, { "mnemonic": "VSRL.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Shift Right Logical", "summary": "Shifts elements of vector vs2 right (logical) by amounts in vs1.", "syntax": "VSRL.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "101000 | vm | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0xA0000057", "visual_parts": [ { "raw": "101000", "clean": "101000", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source" }, { "name": "vs1", "desc": "Shift Amount" } ], "pseudocode": "foreach(i < vl): vd[i] = vs2[i] >> (vs1[i] & Mask);", "description": "Performs element-wise right logical shift on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VSRL.VV v1, v4, v2, v0.t" }, { "mnemonic": "VSRA.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Shift Right Arithmetic", "summary": "Shifts elements of vector vs2 right (arithmetic) by amounts in vs1.", "syntax": "VSRA.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "101001 | vm | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0xA4000057", "visual_parts": [ { "raw": "101001", "clean": "101001", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source" }, { "name": "vs1", "desc": "Shift Amount" } ], "pseudocode": "foreach(i < vl): vd[i] = vs2[i] >>s (vs1[i] & Mask);", "description": "Performs element-wise right arithmetic shift on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VSRA.VV v1, v4, v2, v0.t" }, { "mnemonic": "VMSEQ.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Mask Set Equal", "summary": "Sets destination mask bit if elements are equal.", "syntax": "VMSEQ.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "011000 | vm | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0x60000057", "visual_parts": [ { "raw": "011000", "clean": "011000", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest Mask" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = (vs2[i] == vs1[i]) ? 1 : 0;", "description": "Compares elements element-wise for equal and writes a mask result to vd.", "example": "VMSEQ.VV v1, v4, v2, v0.t" }, { "mnemonic": "VMSLT.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Mask Set Less Than (Signed)", "summary": "Sets destination mask bit if vs2 < vs1 (signed).", "syntax": "VMSLT.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "011011 | vm | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0x6C000057", "visual_parts": [ { "raw": "011011", "clean": "011011", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest Mask" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = (vs2[i] = vlmax) ? 0 : vs2[vs1[i]];", "description": "Gathers elements from vs2 using indices in vs1 (or an immediate), writing to vd. Out-of-range indices produce zero.", "example": "VRGATHER.VV v1, v4, v2, v0.t" }, { "mnemonic": "VMAND.MM", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Mask AND", "summary": "Performs bitwise AND on vector mask registers.", "syntax": "VMAND.MM vd, vs2, vs1", "encoding": { "format": "OPMVV", "binary_pattern": "0110011 | vs2 | vs1 | 010 | vd | 1010111", "hex_opcode": "0x66002057", "visual_parts": [ { "raw": "0110011", "clean": "0110011", "pos": "31:25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest Mask" }, { "name": "vs2", "desc": "Src 2 Mask" }, { "name": "vs1", "desc": "Src 1 Mask" } ], "pseudocode": "vd = vs1 & vs2;", "description": "Performs element-wise mask AND on the mask registers vm1 and vm2, writing to vd.", "example": "VMAND.MM v1, v4, v2" }, { "mnemonic": "AMOADD.D", "architecture": "RISC-V", "extension": "A", "full_name": "Atomic Add Doubleword", "summary": "Atomically adds a value to a 64-bit doubleword in memory.", "syntax": "AMOADD.D rd, rs2, (rs1)", "encoding": { "format": "R-Type (Atomic)", "binary_pattern": "00000 | aq | rl | rs2 | rs1 | 011 | rd | 0101111", "hex_opcode": "0x0000302F", "visual_parts": [ { "raw": "00000", "clean": "00000", "pos": "31:27" }, { "raw": "aq", "clean": "aq", "pos": "26" }, { "raw": "rl", "clean": "rl", "pos": "25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "011", "clean": "011", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0101111", "clean": "0101111", "pos": "6:0" } ], "bit_positions": "31:27 | 26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Old Value)" }, { "name": "rs2", "desc": "Value to Add" }, { "name": "rs1", "desc": "Address" } ], "pseudocode": "temp = M[R[rs1]]; M[R[rs1]] = temp + R[rs2]; R[rd] = temp;", "example": "AMOADD.D x10, x11, (x12)", "example_note": "64-bit atomic add.", "description": "AMOADD.D atomically loads a doubleword from the address in rs1 into rd, adds rs2, and stores the result back (RV64 only)." }, { "mnemonic": "AMOSWAP.D", "architecture": "RISC-V", "extension": "A", "full_name": "Atomic Swap Doubleword", "summary": "Atomically swaps a 64-bit value in memory with a register.", "syntax": "AMOSWAP.D rd, rs2, (rs1)", "encoding": { "format": "R-Type (Atomic)", "binary_pattern": "00001 | aq | rl | rs2 | rs1 | 011 | rd | 0101111", "hex_opcode": "0x0800302F", "visual_parts": [ { "raw": "00001", "clean": "00001", "pos": "31:27" }, { "raw": "aq", "clean": "aq", "pos": "26" }, { "raw": "rl", "clean": "rl", "pos": "25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "011", "clean": "011", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0101111", "clean": "0101111", "pos": "6:0" } ], "bit_positions": "31:27 | 26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Old Value)" }, { "name": "rs2", "desc": "New Value" }, { "name": "rs1", "desc": "Address" } ], "pseudocode": "temp = M[R[rs1]]; M[R[rs1]] = R[rs2]; R[rd] = temp;", "example": "AMOSWAP.D x10, x11, (x12)", "example_note": "64-bit atomic swap.", "description": "AMOSWAP.D atomically loads a doubleword, writes it to rd, and stores rs2 to that address (RV64 only)." }, { "mnemonic": "AMOAND.D", "architecture": "RISC-V", "extension": "A", "full_name": "Atomic AND Doubleword", "summary": "Atomically performs bitwise AND on a 64-bit doubleword in memory.", "syntax": "AMOAND.D rd, rs2, (rs1)", "encoding": { "format": "R-Type (Atomic)", "binary_pattern": "01100 | aq | rl | rs2 | rs1 | 011 | rd | 0101111", "hex_opcode": "0x6000302F", "visual_parts": [ { "raw": "01100", "clean": "01100", "pos": "31:27" }, { "raw": "aq", "clean": "aq", "pos": "26" }, { "raw": "rl", "clean": "rl", "pos": "25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "011", "clean": "011", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0101111", "clean": "0101111", "pos": "6:0" } ], "bit_positions": "31:27 | 26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Old Value)" }, { "name": "rs2", "desc": "Operand" }, { "name": "rs1", "desc": "Address" } ], "pseudocode": "temp = M[R[rs1]]; M[R[rs1]] = temp & R[rs2]; R[rd] = temp;", "example": "AMOAND.D x5, x6, (x7)", "example_note": "64-bit atomic AND.", "description": "AMOAND.D atomically loads a doubleword, ANDs with rs2, and stores the result back (RV64 only)." }, { "mnemonic": "AMOOR.D", "architecture": "RISC-V", "extension": "A", "full_name": "Atomic OR Doubleword", "summary": "Atomically performs bitwise OR on a 64-bit doubleword in memory.", "syntax": "AMOOR.D rd, rs2, (rs1)", "encoding": { "format": "R-Type (Atomic)", "binary_pattern": "01000 | aq | rl | rs2 | rs1 | 011 | rd | 0101111", "hex_opcode": "0x4000302F", "visual_parts": [ { "raw": "01000", "clean": "01000", "pos": "31:27" }, { "raw": "aq", "clean": "aq", "pos": "26" }, { "raw": "rl", "clean": "rl", "pos": "25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "011", "clean": "011", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0101111", "clean": "0101111", "pos": "6:0" } ], "bit_positions": "31:27 | 26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Old Value)" }, { "name": "rs2", "desc": "Operand" }, { "name": "rs1", "desc": "Address" } ], "pseudocode": "temp = M[R[rs1]]; M[R[rs1]] = temp | R[rs2]; R[rd] = temp;", "example": "AMOOR.D x10, x11, (x12)", "example_note": "64-bit atomic OR.", "description": "AMOOR.D atomically loads a doubleword, ORs with rs2, and stores the result back (RV64 only)." }, { "mnemonic": "AMOXOR.D", "architecture": "RISC-V", "extension": "A", "full_name": "Atomic XOR Doubleword", "summary": "Atomically performs bitwise XOR on a 64-bit doubleword in memory.", "syntax": "AMOXOR.D rd, rs2, (rs1)", "encoding": { "format": "R-Type (Atomic)", "binary_pattern": "00100 | aq | rl | rs2 | rs1 | 011 | rd | 0101111", "hex_opcode": "0x2000302F", "visual_parts": [ { "raw": "00100", "clean": "00100", "pos": "31:27" }, { "raw": "aq", "clean": "aq", "pos": "26" }, { "raw": "rl", "clean": "rl", "pos": "25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "011", "clean": "011", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0101111", "clean": "0101111", "pos": "6:0" } ], "bit_positions": "31:27 | 26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Old Value)" }, { "name": "rs2", "desc": "Operand" }, { "name": "rs1", "desc": "Address" } ], "pseudocode": "temp = M[R[rs1]]; M[R[rs1]] = temp ^ R[rs2]; R[rd] = temp;", "example": "AMOXOR.D x10, x11, (x12)", "example_note": "64-bit atomic XOR.", "description": "AMOXOR.D atomically loads a doubleword, XORs with rs2, and stores the result back (RV64 only)." }, { "mnemonic": "AMOMAX.D", "architecture": "RISC-V", "extension": "A", "full_name": "Atomic Max Doubleword", "summary": "Atomically updates memory with the maximum of the memory value and register value (64-bit Signed).", "syntax": "AMOMAX.D rd, rs2, (rs1)", "encoding": { "format": "R-Type (Atomic)", "binary_pattern": "10100 | aq | rl | rs2 | rs1 | 011 | rd | 0101111", "hex_opcode": "0xA000302F", "visual_parts": [ { "raw": "10100", "clean": "10100", "pos": "31:27" }, { "raw": "aq", "clean": "aq", "pos": "26" }, { "raw": "rl", "clean": "rl", "pos": "25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "011", "clean": "011", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0101111", "clean": "0101111", "pos": "6:0" } ], "bit_positions": "31:27 | 26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Old Value)" }, { "name": "rs2", "desc": "Operand" }, { "name": "rs1", "desc": "Address" } ], "pseudocode": "temp = M[R[rs1]]; M[R[rs1]] = max(temp, R[rs2]); R[rd] = temp;", "example": "AMOMAX.D x10, x11, (x12)", "example_note": "64-bit atomic max.", "description": "AMOMAX.D performs an atomic signed maximum doubleword operation (RV64 only)." }, { "mnemonic": "AMOMIN.D", "architecture": "RISC-V", "extension": "A", "full_name": "Atomic Min Doubleword", "summary": "Atomically updates memory with the minimum of the memory value and register value (64-bit Signed).", "syntax": "AMOMIN.D rd, rs2, (rs1)", "encoding": { "format": "R-Type (Atomic)", "binary_pattern": "10000 | aq | rl | rs2 | rs1 | 011 | rd | 0101111", "hex_opcode": "0x8000302F", "visual_parts": [ { "raw": "10000", "clean": "10000", "pos": "31:27" }, { "raw": "aq", "clean": "aq", "pos": "26" }, { "raw": "rl", "clean": "rl", "pos": "25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "011", "clean": "011", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0101111", "clean": "0101111", "pos": "6:0" } ], "bit_positions": "31:27 | 26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Old Value)" }, { "name": "rs2", "desc": "Operand" }, { "name": "rs1", "desc": "Address" } ], "pseudocode": "temp = M[R[rs1]]; M[R[rs1]] = min(temp, R[rs2]); R[rd] = temp;", "example": "AMOMIN.D x10, x11, (x12)", "example_note": "64-bit atomic min.", "description": "AMOMIN.D performs an atomic signed minimum doubleword operation (RV64 only)." }, { "mnemonic": "SC.D", "architecture": "RISC-V", "extension": "A", "full_name": "Store Conditional Doubleword", "summary": "Conditionally stores a 64-bit value to memory if the reservation is valid.", "syntax": "SC.D rd, rs2, (rs1)", "encoding": { "format": "R-Type (Atomic)", "binary_pattern": "00011 | aq | rl | rs2 | rs1 | 011 | rd | 0101111", "hex_opcode": "0x1800302F", "visual_parts": [ { "raw": "00011", "clean": "00011", "pos": "31:27" }, { "raw": "aq", "clean": "aq", "pos": "26" }, { "raw": "rl", "clean": "rl", "pos": "25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "011", "clean": "011", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0101111", "clean": "0101111", "pos": "6:0" } ], "bit_positions": "31:27 | 26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (0=Success)" }, { "name": "rs2", "desc": "Source Value" }, { "name": "rs1", "desc": "Address" } ], "pseudocode": "if (ReservationValid) { M[R[rs1]] = R[rs2]; R[rd] = 0; } else { R[rd] = 1; }", "example": "SC.D x10, x11, (x12)", "example_note": "64-bit conditional store.", "description": "SC.D conditionally stores the doubleword in rs2 to the address in rs1, only if the reservation set by LR.D is still valid (RV64 only). It writes 0 to rd on success and a non-zero value on failure." }, { "mnemonic": "FMADD.S", "architecture": "RISC-V", "extension": "F", "full_name": "Float Fused Multiply-Add (Single)", "summary": "Computes (rs1 * rs2) + rs3 with a single rounding.", "syntax": "FMADD.S rd, rs1, rs2, rs3", "encoding": { "format": "R4-Type", "binary_pattern": "rs3 | 00 | rs2 | rs1 | rm | rd | 1000011", "hex_opcode": "0x00000043", "visual_parts": [ { "raw": "rs3", "clean": "rs3", "pos": "31:27" }, { "raw": "00", "clean": "00", "pos": "26:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1000011", "clean": "1000011", "pos": "6:0" } ], "bit_positions": "31:27 | 26:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" }, { "name": "rs3", "desc": "Src 3" } ], "pseudocode": "F[rd] = (F[rs1] * F[rs2]) + F[rs3];", "example": "FMADD.S f0, f1, f2, f3", "example_note": "f0 = (f1 * f2) + f3", "description": "Performs single-precision (32-bit) floating-point fused multiply-add. The operation computes fused multiply-add on the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008." }, { "mnemonic": "FMADD.D", "architecture": "RISC-V", "extension": "D", "full_name": "Float Fused Multiply-Add (Double)", "summary": "Computes (rs1 * rs2) + rs3 with a single rounding (64-bit).", "syntax": "FMADD.D rd, rs1, rs2, rs3", "encoding": { "format": "R4-Type", "binary_pattern": "rs3 | 01 | rs2 | rs1 | rm | rd | 1000011", "hex_opcode": "0x02000043", "visual_parts": [ { "raw": "rs3", "clean": "rs3", "pos": "31:27" }, { "raw": "01", "clean": "01", "pos": "26:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1000011", "clean": "1000011", "pos": "6:0" } ], "bit_positions": "31:27 | 26:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" }, { "name": "rs3", "desc": "Src 3" } ], "pseudocode": "F[rd] = (F[rs1] * F[rs2]) + F[rs3];", "example": "FMADD.D f0, f1, f2, f3", "example_note": "64-bit fused multiply-add.", "description": "Performs double-precision (64-bit) floating-point fused multiply-add. The operation computes fused multiply-add on the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008." }, { "mnemonic": "SUB", "architecture": "RISC-V", "extension": "RV32I", "full_name": "Subtract", "summary": "Subtracts rs2 from rs1.", "syntax": "SUB rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0100000 | rs2 | rs1 | 000 | rd | 0110011", "hex_opcode": "0x40000033", "visual_parts": [ { "raw": "0100000", "clean": "0100000", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Minuend" }, { "name": "rs2", "desc": "Subtrahend" } ], "pseudocode": "R[rd] = R[rs1] - R[rs2];", "description": "SUB subtracts the value in rs2 from rs1 and writes the result to rd. Arithmetic overflow is ignored; the result is the low XLEN bits of the mathematical difference.", "example": "SUB t0, a0, a1" }, { "mnemonic": "SLTU", "architecture": "RISC-V", "extension": "RV32I", "full_name": "Set Less Than Unsigned", "summary": "Sets rd to 1 if rs1 < rs2 (unsigned comparison), otherwise 0.", "syntax": "SLTU rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000000 | rs2 | rs1 | 011 | rd | 0110011", "hex_opcode": "0x00003033", "visual_parts": [ { "raw": "0000000", "clean": "0000000", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "011", "clean": "011", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" } ], "pseudocode": "R[rd] = (R[rs1] > XLEN;", "description": "MULHU multiplies rs1 and rs2 as unsigned values and writes the upper XLEN bits of the product to rd.", "example": "MULHU t0, a0, a1" }, { "mnemonic": "MULHSU", "architecture": "RISC-V", "extension": "M", "full_name": "Multiply High Signed-Unsigned", "summary": "Multiplies signed rs1 by unsigned rs2 and returns the upper XLEN bits.", "syntax": "MULHSU rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000001 | rs2 | rs1 | 010 | rd | 0110011", "hex_opcode": "0x02002033", "visual_parts": [ { "raw": "0000001", "clean": "0000001", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Upper Bits)" }, { "name": "rs1", "desc": "Signed Source" }, { "name": "rs2", "desc": "Unsigned Source" } ], "pseudocode": "R[rd] = (sext(R[rs1]) * zext(R[rs2])) >> XLEN;", "description": "MULHSU multiplies rs1 (signed) by rs2 (unsigned) and writes the upper XLEN bits of the product to rd.", "example": "MULHSU t0, a0, a1" }, { "mnemonic": "REMU", "architecture": "RISC-V", "extension": "M", "full_name": "Remainder Unsigned", "summary": "Computes the unsigned remainder of division.", "syntax": "REMU rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000001 | rs2 | rs1 | 111 | rd | 0110011", "hex_opcode": "0x02007033", "visual_parts": [ { "raw": "0000001", "clean": "0000001", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "111", "clean": "111", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Remainder)" }, { "name": "rs1", "desc": "Dividend" }, { "name": "rs2", "desc": "Divisor" } ], "pseudocode": "R[rd] = R[rs1] %u R[rs2];", "description": "REMU computes the unsigned remainder of rs1 ÷ rs2, writing the result to rd. Remainder by zero yields the dividend.", "example": "REMU t0, a0, a1" }, { "mnemonic": "AMOMINU.W", "architecture": "RISC-V", "extension": "A", "full_name": "Atomic Min Unsigned Word", "summary": "Atomically updates memory with the minimum of the memory value and register value (Unsigned).", "syntax": "AMOMINU.W rd, rs2, (rs1)", "encoding": { "format": "R-Type (Atomic)", "binary_pattern": "11000 | aq | rl | rs2 | rs1 | 010 | rd | 0101111", "hex_opcode": "0xC000202F", "visual_parts": [ { "raw": "11000", "clean": "11000", "pos": "31:27" }, { "raw": "aq", "clean": "aq", "pos": "26" }, { "raw": "rl", "clean": "rl", "pos": "25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0101111", "clean": "0101111", "pos": "6:0" } ], "bit_positions": "31:27 | 26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Old Value)" }, { "name": "rs2", "desc": "Operand" }, { "name": "rs1", "desc": "Address" } ], "pseudocode": "temp = M[R[rs1]]; M[R[rs1]] = min_u(temp, R[rs2]); R[rd] = temp;", "description": "AMOMINU.W atomically computes the unsigned minimum of a memory word and rs2, stores the result, and returns the original in rd.", "example": "AMOMINU.W t0, a1, a0" }, { "mnemonic": "AMOMAXU.W", "architecture": "RISC-V", "extension": "A", "full_name": "Atomic Max Unsigned Word", "summary": "Atomically updates memory with the maximum of the memory value and register value (Unsigned).", "syntax": "AMOMAXU.W rd, rs2, (rs1)", "encoding": { "format": "R-Type (Atomic)", "binary_pattern": "11100 | aq | rl | rs2 | rs1 | 010 | rd | 0101111", "hex_opcode": "0xE000202F", "visual_parts": [ { "raw": "11100", "clean": "11100", "pos": "31:27" }, { "raw": "aq", "clean": "aq", "pos": "26" }, { "raw": "rl", "clean": "rl", "pos": "25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0101111", "clean": "0101111", "pos": "6:0" } ], "bit_positions": "31:27 | 26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Old Value)" }, { "name": "rs2", "desc": "Operand" }, { "name": "rs1", "desc": "Address" } ], "pseudocode": "temp = M[R[rs1]]; M[R[rs1]] = max_u(temp, R[rs2]); R[rd] = temp;", "description": "AMOMAXU.W atomically computes the unsigned maximum of a memory word and rs2, stores the result, and returns the original in rd.", "example": "AMOMAXU.W t0, a1, a0" }, { "mnemonic": "FSUB.S", "architecture": "RISC-V", "extension": "F", "full_name": "Float Subtract (Single)", "summary": "Performs single-precision floating-point subtraction.", "syntax": "FSUB.S rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000100 | rs2 | rs1 | rm | rd | 1010011", "hex_opcode": "0x08000053", "visual_parts": [ { "raw": "0000100", "clean": "0000100", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" } ], "pseudocode": "F[rd] = F[rs1] - F[rs2];", "description": "Performs single-precision (32-bit) floating-point subtraction. The operation subtracts the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.", "example": "FSUB.S t0, a0, a1" }, { "mnemonic": "FMUL.S", "architecture": "RISC-V", "extension": "F", "full_name": "Float Multiply (Single)", "summary": "Performs single-precision floating-point multiplication.", "syntax": "FMUL.S rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0001000 | rs2 | rs1 | rm | rd | 1010011", "hex_opcode": "0x10000053", "visual_parts": [ { "raw": "0001000", "clean": "0001000", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" } ], "pseudocode": "F[rd] = F[rs1] * F[rs2];", "description": "Performs single-precision (32-bit) floating-point multiplication. The operation multiplies the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.", "example": "FMUL.S t0, a0, a1" }, { "mnemonic": "FDIV.S", "architecture": "RISC-V", "extension": "F", "full_name": "Float Divide (Single)", "summary": "Performs single-precision floating-point division.", "syntax": "FDIV.S rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0001100 | rs2 | rs1 | rm | rd | 1010011", "hex_opcode": "0x18000053", "visual_parts": [ { "raw": "0001100", "clean": "0001100", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Dividend" }, { "name": "rs2", "desc": "Divisor" } ], "pseudocode": "F[rd] = F[rs1] / F[rs2];", "description": "Performs single-precision (32-bit) floating-point division. The operation divides the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.", "example": "FDIV.S t0, a0, a1" }, { "mnemonic": "FSQRT.S", "architecture": "RISC-V", "extension": "F", "full_name": "Float Square Root (Single)", "summary": "Computes the square root of a single-precision floating-point number.", "syntax": "FSQRT.S rd, rs1", "encoding": { "format": "I-Type (Float)", "binary_pattern": "010110000000 | rs1 | rm | rd | 1010011", "hex_opcode": "0x58000053", "visual_parts": [ { "raw": "010110000000", "clean": "010110000000", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source" } ], "pseudocode": "F[rd] = sqrt(F[rs1]);", "description": "Stores a floating-point register to memory at address rs1+sext(offset).", "example": "FSQRT.S t0, a0" }, { "mnemonic": "FMIN.S", "architecture": "RISC-V", "extension": "F", "full_name": "Float Minimum (Single)", "summary": "Writes the smaller of two single-precision floating-point values to rd.", "syntax": "FMIN.S rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0010100 | rs2 | rs1 | 000 | rd | 1010011", "hex_opcode": "0x28000053", "visual_parts": [ { "raw": "0010100", "clean": "0010100", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" } ], "pseudocode": "F[rd] = min(F[rs1], F[rs2]);", "description": "Returns the single-precision (32-bit) floating-point minimum of rs1 and rs2, following IEEE 754-2019 minNum/maxNum semantics. Quiet NaN inputs return the non-NaN operand; signalling NaN inputs raise invalid-operation.", "example": "FMIN.S t0, a0, a1" }, { "mnemonic": "FMAX.S", "architecture": "RISC-V", "extension": "F", "full_name": "Float Maximum (Single)", "summary": "Writes the larger of two single-precision floating-point values to rd.", "syntax": "FMAX.S rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0010100 | rs2 | rs1 | 001 | rd | 1010011", "hex_opcode": "0x28001053", "visual_parts": [ { "raw": "0010100", "clean": "0010100", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" } ], "pseudocode": "F[rd] = max(F[rs1], F[rs2]);", "description": "Returns the single-precision (32-bit) floating-point maximum of rs1 and rs2, following IEEE 754-2019 minNum/maxNum semantics. Quiet NaN inputs return the non-NaN operand; signalling NaN inputs raise invalid-operation.", "example": "FMAX.S t0, a0, a1" }, { "mnemonic": "CSRR", "architecture": "RISC-V", "extension": "Pseudo", "full_name": "Control Status Register Read", "summary": "Reads the value of a CSR into a register.", "syntax": "CSRR rd, csr", "encoding": { "format": "I-Type", "binary_pattern": "csr | 00000010 | rd | 1110011", "hex_opcode": "0x00002073", "visual_parts": [ { "raw": "csr", "clean": "csr", "pos": "31:20" }, { "raw": "00000010", "clean": "00000010", "pos": "19:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1110011", "clean": "1110011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "csr", "desc": "CSR Address" } ], "pseudocode": "R[rd] = CSRs[csr];", "example": "CSRR x10, mstatus", "example_note": "Read mstatus.", "description": "CSRR is an assembler pseudoinstruction for CSRRS rd, csr, x0. It reads the CSR into rd without modifying it." }, { "mnemonic": "CSRW", "architecture": "RISC-V", "extension": "Pseudo", "full_name": "Control Status Register Write", "summary": "Writes a register value to a CSR.", "syntax": "CSRW csr, rs", "encoding": { "format": "I-Type", "binary_pattern": "csr | rs1 | 001000001110011", "hex_opcode": "0x00001073", "visual_parts": [ { "raw": "csr", "clean": "csr", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001000001110011", "clean": "001000001110011", "pos": "14:0" } ], "bit_positions": "31:20 | 19:15 | 14:0" }, "operands": [ { "name": "csr", "desc": "CSR Address" }, { "name": "rs", "desc": "Source" } ], "pseudocode": "CSRs[csr] = R[rs];", "example": "CSRW mepc, x10", "example_note": "Write address in x10 to mepc.", "description": "CSRW is an assembler pseudoinstruction for CSRRW x0, csr, rs1. It writes rs1 to the CSR without reading it." }, { "mnemonic": "CSRS", "architecture": "RISC-V", "extension": "Pseudo", "full_name": "Control Status Register Set", "summary": "Sets bits in a CSR (bitwise OR).", "syntax": "CSRS csr, rs", "encoding": { "format": "I-Type", "binary_pattern": "csr | rs1 | 010000001110011", "hex_opcode": "0x00002073", "visual_parts": [ { "raw": "csr", "clean": "csr", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "010000001110011", "clean": "010000001110011", "pos": "14:0" } ], "bit_positions": "31:20 | 19:15 | 14:0" }, "operands": [ { "name": "csr", "desc": "CSR Address" }, { "name": "rs", "desc": "Bit Mask" } ], "pseudocode": "CSRs[csr] |= R[rs];", "example": "CSRS sstatus, x5", "example_note": "Set bits in sstatus.", "description": "CSRS is an assembler pseudoinstruction for CSRRS x0, csr, rs1. It sets bits in the CSR based on rs1 without reading." }, { "mnemonic": "CSRC", "architecture": "RISC-V", "extension": "Pseudo", "full_name": "Control Status Register Clear", "summary": "Clears bits in a CSR (bitwise AND NOT).", "syntax": "CSRC csr, rs", "encoding": { "format": "I-Type", "binary_pattern": "csr | rs1 | 011000001110011", "hex_opcode": "0x00003073", "visual_parts": [ { "raw": "csr", "clean": "csr", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "011000001110011", "clean": "011000001110011", "pos": "14:0" } ], "bit_positions": "31:20 | 19:15 | 14:0" }, "operands": [ { "name": "csr", "desc": "CSR Address" }, { "name": "rs", "desc": "Bit Mask" } ], "pseudocode": "CSRs[csr] &= ~R[rs];", "example": "CSRC sstatus, x5", "example_note": "Clear bits in sstatus.", "description": "CSRC is an assembler pseudoinstruction for CSRRC x0, csr, rs1. It clears bits in the CSR based on rs1 without reading." }, { "mnemonic": "FCVT.LU.D", "architecture": "RISC-V", "extension": "D", "full_name": "Convert Double to Unsigned Long", "summary": "Converts a double-precision float to a 64-bit unsigned integer.", "syntax": "FCVT.LU.D rd, rs1", "encoding": { "format": "I-Type (Float)", "binary_pattern": "110000100011 | rs1 | rm | rd | 1010011", "hex_opcode": "0xC2300053", "visual_parts": [ { "raw": "110000100011", "clean": "110000100011", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (ULong)" }, { "name": "rs1", "desc": "Source (Double)" } ], "pseudocode": "R[rd] = f64_to_u64(F[rs1]);", "example": "FCVT.LU.D x10, f0", "example_note": "Double -> Unsigned 64-bit Int.", "description": "Converts between floating-point types or between floating-point and integer. Result is rounded according to the dynamic rounding mode. Invalid conversions produce the IEEE default NaN or the appropriate integer saturation value." }, { "mnemonic": "FLH", "architecture": "RISC-V", "extension": "Zfh", "full_name": "Float Load Halfword", "summary": "Loads a 16-bit half-precision float from memory.", "syntax": "FLH rd, offset(rs1)", "encoding": { "format": "I-Type", "binary_pattern": "imm12 | rs1 | 001 | rd | 0000111", "hex_opcode": "0x00001007", "visual_parts": [ { "raw": "imm12", "clean": "imm12", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0000111", "clean": "0000111", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Float)" }, { "name": "rs1", "desc": "Base" }, { "name": "offset", "desc": "Offset" } ], "pseudocode": "F[rd] = M[R[rs1] + sext(offset)][15:0];", "example": "FLH f1, 0(x10)", "example_note": "Load 16-bit float.", "description": "Loads a 16-bit halfword from memory at address rs1+sext(offset) into floating-point register rd." }, { "mnemonic": "FSH", "architecture": "RISC-V", "extension": "Zfh", "full_name": "Float Store Halfword", "summary": "Stores a 16-bit half-precision float to memory.", "syntax": "FSH rs2, offset(rs1)", "encoding": { "format": "S-Type", "binary_pattern": "imm12hi | rs2 | rs1 | 001 | imm12lo | 0100111", "hex_opcode": "0x00001027", "visual_parts": [ { "raw": "imm12hi", "clean": "imm12hi", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "imm12lo", "clean": "imm12lo", "pos": "11:7" }, { "raw": "0100111", "clean": "0100111", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rs2", "desc": "Source" }, { "name": "rs1", "desc": "Base" }, { "name": "offset", "desc": "Offset" } ], "pseudocode": "M[R[rs1] + sext(offset)][15:0] = F[rs2];", "example": "FSH f1, 0(x10)", "example_note": "Store 16-bit float.", "description": "Stores a floating-point register to memory at address rs1+sext(offset)." }, { "mnemonic": "FADD.H", "architecture": "RISC-V", "extension": "Zfh", "full_name": "Float Add Half", "summary": "Performs 16-bit floating-point addition.", "syntax": "FADD.H rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000010 | rs2 | rs1 | rm | rd | 1010011", "hex_opcode": "0x04000053", "visual_parts": [ { "raw": "0000010", "clean": "0000010", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" } ], "pseudocode": "F[rd] = F[rs1] + F[rs2];", "example": "FADD.H f0, f1, f2", "example_note": "16-bit float add.", "description": "Performs half-precision (16-bit) floating-point addition. The operation adds the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008." }, { "mnemonic": "FCVT.S.H", "architecture": "RISC-V", "extension": "Zfh", "full_name": "Convert Half to Single", "summary": "Converts a 16-bit half-precision float to a 32-bit single-precision float.", "syntax": "FCVT.S.H rd, rs1", "encoding": { "format": "I-Type (Float)", "binary_pattern": "010000000010 | rs1 | rm | rd | 1010011", "hex_opcode": "0x40200053", "visual_parts": [ { "raw": "010000000010", "clean": "010000000010", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Single)" }, { "name": "rs1", "desc": "Source (Half)" } ], "pseudocode": "F[rd] = f16_to_f32(F[rs1]);", "example": "FCVT.S.H f0, f1", "example_note": "Promote Half to Float.", "description": "Converts between floating-point types or between floating-point and integer. Result is rounded according to the dynamic rounding mode. Invalid conversions produce the IEEE default NaN or the appropriate integer saturation value." }, { "mnemonic": "FCVT.H.S", "architecture": "RISC-V", "extension": "Zfh", "full_name": "Convert Single to Half", "summary": "Converts a 32-bit single-precision float to a 16-bit half-precision float.", "syntax": "FCVT.H.S rd, rs1", "encoding": { "format": "I-Type (Float)", "binary_pattern": "010001000000 | rs1 | rm | rd | 1010011", "hex_opcode": "0x44000053", "visual_parts": [ { "raw": "010001000000", "clean": "010001000000", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Half)" }, { "name": "rs1", "desc": "Source (Single)" } ], "pseudocode": "F[rd] = f32_to_f16(F[rs1]);", "example": "FCVT.H.S f0, f1", "example_note": "Demote Float to Half.", "description": "Converts between floating-point types or between floating-point and integer. Result is rounded according to the dynamic rounding mode. Invalid conversions produce the IEEE default NaN or the appropriate integer saturation value." }, { "mnemonic": "SUBW", "architecture": "RISC-V", "extension": "RV64I", "full_name": "Subtract Word", "summary": "Subtracts the lower 32 bits of rs2 from rs1 and sign-extends the result to 64 bits.", "syntax": "SUBW rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0100000 | rs2 | rs1 | 000 | rd | 0111011", "hex_opcode": "0x4000003B", "visual_parts": [ { "raw": "0100000", "clean": "0100000", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0111011", "clean": "0111011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Minuend" }, { "name": "rs2", "desc": "Subtrahend" } ], "pseudocode": "R[rd] = sext((R[rs1] - R[rs2])[31:0]);", "example": "SUBW x10, x11, x12", "example_note": "32-bit subtraction on 64-bit registers.", "description": "SUBW subtracts rs2 from rs1, truncates to 32 bits, sign-extends to 64 bits, and writes to rd." }, { "mnemonic": "SLLW", "architecture": "RISC-V", "extension": "RV64I", "full_name": "Shift Left Logical Word", "summary": "Performs a 32-bit logical left shift on rs1 by the amount in rs2 (lower 5 bits), sign-extending the result.", "syntax": "SLLW rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000000 | rs2 | rs1 | 001 | rd | 0111011", "hex_opcode": "0x0000103B", "visual_parts": [ { "raw": "0000000", "clean": "0000000", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0111011", "clean": "0111011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source" }, { "name": "rs2", "desc": "Shift Amount" } ], "pseudocode": "R[rd] = sext((R[rs1] << (R[rs2] & 0x1F))[31:0]);", "example": "SLLW x5, x6, x7", "example_note": "32-bit shift.", "description": "SLLW performs a logical left shift of the lower 32 bits of rs1 by the shift amount in the lower 5 bits of rs2, sign-extends the 32-bit result to 64 bits, and writes to rd." }, { "mnemonic": "SRLW", "architecture": "RISC-V", "extension": "RV64I", "full_name": "Shift Right Logical Word", "summary": "Performs a 32-bit logical right shift on rs1 by the amount in rs2, sign-extending the result.", "syntax": "SRLW rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000000 | rs2 | rs1 | 101 | rd | 0111011", "hex_opcode": "0x0000503B", "visual_parts": [ { "raw": "0000000", "clean": "0000000", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "101", "clean": "101", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0111011", "clean": "0111011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source" }, { "name": "rs2", "desc": "Shift Amount" } ], "pseudocode": "R[rd] = sext((R[rs1][31:0] >>u (R[rs2] & 0x1F)));", "example": "SRLW x5, x6, x7", "example_note": "32-bit logical right shift.", "description": "SRLW performs a logical right shift of the lower 32 bits of rs1 by the shift amount in the lower 5 bits of rs2, sign-extends the 32-bit result to 64 bits, and writes to rd." }, { "mnemonic": "SRAW", "architecture": "RISC-V", "extension": "RV64I", "full_name": "Shift Right Arithmetic Word", "summary": "Performs a 32-bit arithmetic right shift on rs1, sign-extending the result.", "syntax": "SRAW rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0100000 | rs2 | rs1 | 101 | rd | 0111011", "hex_opcode": "0x4000503B", "visual_parts": [ { "raw": "0100000", "clean": "0100000", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "101", "clean": "101", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0111011", "clean": "0111011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source" }, { "name": "rs2", "desc": "Shift Amount" } ], "pseudocode": "R[rd] = sext((R[rs1][31:0] >>s (R[rs2] & 0x1F)));", "example": "SRAW x5, x6, x7", "example_note": "32-bit arithmetic right shift.", "description": "SRAW performs an arithmetic right shift of the lower 32 bits of rs1 by the shift amount in the lower 5 bits of rs2, sign-extends the 32-bit result to 64 bits, and writes to rd." }, { "mnemonic": "SLLIW", "architecture": "RISC-V", "extension": "RV64I", "full_name": "Shift Left Logical Immediate Word", "summary": "Shifts the lower 32 bits of rs1 left by a constant, sign-extending the result.", "syntax": "SLLIW rd, rs1, shamt", "encoding": { "format": "I-Type (Shift)", "binary_pattern": "0000000 | shamtw | rs1 | 001 | rd | 0011011", "hex_opcode": "0x0000101B", "visual_parts": [ { "raw": "0000000", "clean": "0000000", "pos": "31:25" }, { "raw": "shamtw", "clean": "shamtw", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0011011", "clean": "0011011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source" }, { "name": "shamt", "desc": "Shift Amount (0-31)" } ], "pseudocode": "R[rd] = sext((R[rs1] << shamt)[31:0]);", "example": "SLLIW x10, x11, 4", "example_note": "Shift lower 32 bits left by 4.", "description": "SLLIW performs a logical left shift of the lower 32 bits of rs1 by the 5-bit immediate, sign-extends the 32-bit result to 64 bits, and writes it to rd." }, { "mnemonic": "SRLIW", "architecture": "RISC-V", "extension": "RV64I", "full_name": "Shift Right Logical Immediate Word", "summary": "Logically shifts the lower 32 bits of rs1 right by a constant, sign-extending the result.", "syntax": "SRLIW rd, rs1, shamt", "encoding": { "format": "I-Type (Shift)", "binary_pattern": "0000000 | shamtw | rs1 | 101 | rd | 0011011", "hex_opcode": "0x0000501B", "visual_parts": [ { "raw": "0000000", "clean": "0000000", "pos": "31:25" }, { "raw": "shamtw", "clean": "shamtw", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "101", "clean": "101", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0011011", "clean": "0011011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source" }, { "name": "shamt", "desc": "Shift Amount" } ], "pseudocode": "R[rd] = sext((R[rs1][31:0] >>u shamt));", "example": "SRLIW x10, x11, 4", "example_note": "Logical right shift of lower word.", "description": "SRLIW performs a logical right shift of the lower 32 bits of rs1 by the 5-bit immediate, sign-extends the 32-bit result to 64 bits, and writes it to rd." }, { "mnemonic": "SRAIW", "architecture": "RISC-V", "extension": "RV64I", "full_name": "Shift Right Arithmetic Immediate Word", "summary": "Arithmetically shifts the lower 32 bits of rs1 right by a constant, sign-extending the result.", "syntax": "SRAIW rd, rs1, shamt", "encoding": { "format": "I-Type (Shift)", "binary_pattern": "0100000 | shamtw | rs1 | 101 | rd | 0011011", "hex_opcode": "0x4000501B", "visual_parts": [ { "raw": "0100000", "clean": "0100000", "pos": "31:25" }, { "raw": "shamtw", "clean": "shamtw", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "101", "clean": "101", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0011011", "clean": "0011011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source" }, { "name": "shamt", "desc": "Shift Amount" } ], "pseudocode": "R[rd] = sext((R[rs1][31:0] >>s shamt));", "example": "SRAIW x10, x11, 4", "example_note": "Arithmetic right shift of lower word.", "description": "SRAIW performs an arithmetic right shift of the lower 32 bits of rs1 by the 5-bit immediate, sign-extends the 32-bit result to 64 bits, and writes it to rd." }, { "mnemonic": "MULW", "architecture": "RISC-V", "extension": "M", "full_name": "Multiply Word", "summary": "Performs 32-bit multiplication of rs1 and rs2, sign-extending the 32-bit result to 64 bits.", "syntax": "MULW rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000001 | rs2 | rs1 | 000 | rd | 0111011", "hex_opcode": "0x0200003B", "visual_parts": [ { "raw": "0000001", "clean": "0000001", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0111011", "clean": "0111011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" } ], "pseudocode": "R[rd] = sext((R[rs1] * R[rs2])[31:0]);", "example": "MULW x10, x11, x12", "example_note": "32-bit multiplication.", "description": "MULW multiplies the lower 32 bits of rs1 and rs2, sign-extends the lower 32 bits of the product to 64 bits, and writes to rd (RV64 only)." }, { "mnemonic": "DIVW", "architecture": "RISC-V", "extension": "M", "full_name": "Divide Word", "summary": "Performs 32-bit signed division of rs1 by rs2, sign-extending the result.", "syntax": "DIVW rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000001 | rs2 | rs1 | 100 | rd | 0111011", "hex_opcode": "0x0200403B", "visual_parts": [ { "raw": "0000001", "clean": "0000001", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "100", "clean": "100", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0111011", "clean": "0111011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Quotient" }, { "name": "rs1", "desc": "Dividend" }, { "name": "rs2", "desc": "Divisor" } ], "pseudocode": "R[rd] = sext(R[rs1][31:0] /s R[rs2][31:0]);", "example": "DIVW x10, x11, x12", "example_note": "32-bit signed division.", "description": "DIVW performs signed 32-bit division of the lower 32 bits of rs1 by rs2, sign-extends the quotient to 64 bits, and writes to rd (RV64 only). Division by zero yields -1." }, { "mnemonic": "DIVUW", "architecture": "RISC-V", "extension": "M", "full_name": "Divide Unsigned Word", "summary": "Performs 32-bit unsigned division of rs1 by rs2, sign-extending the result.", "syntax": "DIVUW rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000001 | rs2 | rs1 | 101 | rd | 0111011", "hex_opcode": "0x0200503B", "visual_parts": [ { "raw": "0000001", "clean": "0000001", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "101", "clean": "101", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0111011", "clean": "0111011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Quotient" }, { "name": "rs1", "desc": "Dividend" }, { "name": "rs2", "desc": "Divisor" } ], "pseudocode": "R[rd] = sext(R[rs1][31:0] /u R[rs2][31:0]);", "example": "DIVUW x10, x11, x12", "example_note": "32-bit unsigned division.", "description": "DIVUW performs unsigned 32-bit division of the lower 32 bits of rs1 by rs2, zero-extends the quotient to 64 bits, and writes to rd (RV64 only). Division by zero yields 2^32 - 1." }, { "mnemonic": "REMW", "architecture": "RISC-V", "extension": "M", "full_name": "Remainder Word", "summary": "Computes the remainder of 32-bit signed division, sign-extending the result.", "syntax": "REMW rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000001 | rs2 | rs1 | 110 | rd | 0111011", "hex_opcode": "0x0200603B", "visual_parts": [ { "raw": "0000001", "clean": "0000001", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "110", "clean": "110", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0111011", "clean": "0111011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Remainder" }, { "name": "rs1", "desc": "Dividend" }, { "name": "rs2", "desc": "Divisor" } ], "pseudocode": "R[rd] = sext(R[rs1][31:0] %s R[rs2][31:0]);", "example": "REMW x10, x11, x12", "example_note": "32-bit signed remainder.", "description": "REMW computes the signed 32-bit remainder of rs1 ÷ rs2, sign-extends to 64 bits, and writes to rd (RV64 only)." }, { "mnemonic": "REMUW", "architecture": "RISC-V", "extension": "M", "full_name": "Remainder Unsigned Word", "summary": "Computes the remainder of 32-bit unsigned division, sign-extending the result.", "syntax": "REMUW rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000001 | rs2 | rs1 | 111 | rd | 0111011", "hex_opcode": "0x0200703B", "visual_parts": [ { "raw": "0000001", "clean": "0000001", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "111", "clean": "111", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0111011", "clean": "0111011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Remainder" }, { "name": "rs1", "desc": "Dividend" }, { "name": "rs2", "desc": "Divisor" } ], "pseudocode": "R[rd] = sext(R[rs1][31:0] %u R[rs2][31:0]);", "example": "REMUW x10, x11, x12", "example_note": "32-bit unsigned remainder.", "description": "REMUW computes the unsigned 32-bit remainder of rs1 ÷ rs2, zero-extends to 64 bits, and writes to rd (RV64 only)." }, { "mnemonic": "FENCE.I", "architecture": "RISC-V", "extension": "Zifencei", "full_name": "Instruction Fence", "summary": "Synchronizes the instruction cache with the data cache (used after self-modifying code).", "syntax": "FENCE.I", "encoding": { "format": "I-Type", "binary_pattern": "imm12 | rs1 | 001 | rd | 0001111", "hex_opcode": "0x0000100F", "visual_parts": [ { "raw": "imm12", "clean": "imm12", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0001111", "clean": "0001111", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [], "pseudocode": "Fence(Store, Fetch);", "example": "FENCE.I", "example_note": "Flushes I-Cache; ensures previous writes are visible to instruction fetch.", "description": "FENCE.I synchronises the instruction and data streams. It ensures that any stores to instruction memory visible to the current hart are made visible to subsequent instruction fetches by that hart." }, { "mnemonic": "HLV.B", "architecture": "RISC-V", "extension": "H", "full_name": "Hypervisor Load Byte", "summary": "Loads a byte from Guest Physical Memory (VS-stage translation only).", "syntax": "HLV.B rd, (rs1)", "encoding": { "format": "R-Type (System)", "binary_pattern": "011000000000 | rs1 | 100 | rd | 1110011", "hex_opcode": "0x60004073", "visual_parts": [ { "raw": "011000000000", "clean": "011000000000", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "100", "clean": "100", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1110011", "clean": "1110011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Guest Address" } ], "pseudocode": "R[rd] = sext(GuestMem[R[rs1]][7:0]);", "example": "HLV.B x10, (x11)", "example_note": "Read byte from guest memory.", "description": "HLV.B performs a virtual-machine load of a byte from the address in rs1, using the virtual supervisor address space (VS-mode translation). The result is sign-extended and written to rd." }, { "mnemonic": "HLV.W", "architecture": "RISC-V", "extension": "H", "full_name": "Hypervisor Load Word", "summary": "Loads a word from Guest Physical Memory (VS-stage translation only).", "syntax": "HLV.W rd, (rs1)", "encoding": { "format": "R-Type (System)", "binary_pattern": "011010000000 | rs1 | 100 | rd | 1110011", "hex_opcode": "0x68004073", "visual_parts": [ { "raw": "011010000000", "clean": "011010000000", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "100", "clean": "100", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1110011", "clean": "1110011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Guest Address" } ], "pseudocode": "R[rd] = sext(GuestMem[R[rs1]][31:0]);", "example": "HLV.W x10, (x11)", "example_note": "Read word from guest memory.", "description": "HLV.W performs a virtual-machine load of a word using VS-mode translation. In RV64 the result is sign-extended." }, { "mnemonic": "HSV.B", "architecture": "RISC-V", "extension": "H", "full_name": "Hypervisor Store Byte", "summary": "Stores a byte to Guest Physical Memory.", "syntax": "HSV.B rs2, (rs1)", "encoding": { "format": "R-Type (System)", "binary_pattern": "0110001 | rs2 | rs1 | 100000001110011", "hex_opcode": "0x62004073", "visual_parts": [ { "raw": "0110001", "clean": "0110001", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "100000001110011", "clean": "100000001110011", "pos": "14:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:0" }, "operands": [ { "name": "rs2", "desc": "Source" }, { "name": "rs1", "desc": "Guest Address" } ], "pseudocode": "GuestMem[R[rs1]][7:0] = R[rs2][7:0];", "example": "HSV.B x10, (x11)", "example_note": "Write byte to guest memory.", "description": "HSV.B stores the least-significant byte of rs2 to the VS-mode virtual address in rs1." }, { "mnemonic": "HSV.W", "architecture": "RISC-V", "extension": "H", "full_name": "Hypervisor Store Word", "summary": "Stores a word to Guest Physical Memory.", "syntax": "HSV.W rs2, (rs1)", "encoding": { "format": "R-Type (System)", "binary_pattern": "0110101 | rs2 | rs1 | 100000001110011", "hex_opcode": "0x6A004073", "visual_parts": [ { "raw": "0110101", "clean": "0110101", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "100000001110011", "clean": "100000001110011", "pos": "14:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:0" }, "operands": [ { "name": "rs2", "desc": "Source" }, { "name": "rs1", "desc": "Guest Address" } ], "pseudocode": "GuestMem[R[rs1]][31:0] = R[rs2][31:0];", "example": "HSV.W x10, (x11)", "example_note": "Write word to guest memory.", "description": "HSV.W stores the least-significant word of rs2 to the VS-mode virtual address in rs1." }, { "mnemonic": "PREFETCH.I", "architecture": "RISC-V", "extension": "Zicbop", "full_name": "Prefetch Instruction", "summary": "Hints to hardware to bring the cache block containing the instruction at the address into the instruction cache.", "syntax": "PREFETCH.I offset(rs1)", "encoding": { "format": "S-Type (Hint)", "binary_pattern": "imm12hi | 00000 | rs1 | 110000000010011", "hex_opcode": "0x00006013", "visual_parts": [ { "raw": "imm12hi", "clean": "imm12hi", "pos": "31:25" }, { "raw": "00000", "clean": "00000", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "110000000010011", "clean": "110000000010011", "pos": "14:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:0" }, "operands": [ { "name": "rs1", "desc": "Base Address" }, { "name": "offset", "desc": "Offset" } ], "pseudocode": "Prefetch(I-Cache, R[rs1] + offset);", "example": "PREFETCH.I 0(x10)", "example_note": "Prepare I-Cache for upcoming jump.", "description": "PREFETCH.I is a hint to the memory system to prefetch the cache block at the address rs1+offset into the instruction cache." }, { "mnemonic": "PREFETCH.R", "architecture": "RISC-V", "extension": "Zicbop", "full_name": "Prefetch Read", "summary": "Hints to hardware to bring the cache block at the address into the data cache for reading.", "syntax": "PREFETCH.R offset(rs1)", "encoding": { "format": "S-Type (Hint)", "binary_pattern": "imm12hi | 00001 | rs1 | 110000000010011", "hex_opcode": "0x00106013", "visual_parts": [ { "raw": "imm12hi", "clean": "imm12hi", "pos": "31:25" }, { "raw": "00001", "clean": "00001", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "110000000010011", "clean": "110000000010011", "pos": "14:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:0" }, "operands": [ { "name": "rs1", "desc": "Base Address" }, { "name": "offset", "desc": "Offset" } ], "pseudocode": "Prefetch(D-Cache, Read, R[rs1] + offset);", "example": "PREFETCH.R 64(x10)", "example_note": "Prepare D-Cache for reading next cache line.", "description": "PREFETCH.R is a hint to the memory system to prefetch the cache block at rs1+offset into the data cache for a read access." }, { "mnemonic": "PREFETCH.W", "architecture": "RISC-V", "extension": "Zicbop", "full_name": "Prefetch Write", "summary": "Hints to hardware to bring the cache block at the address into the data cache for writing (exclusive ownership).", "syntax": "PREFETCH.W offset(rs1)", "encoding": { "format": "S-Type (Hint)", "binary_pattern": "imm12hi | 00011 | rs1 | 110000000010011", "hex_opcode": "0x00306013", "visual_parts": [ { "raw": "imm12hi", "clean": "imm12hi", "pos": "31:25" }, { "raw": "00011", "clean": "00011", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "110000000010011", "clean": "110000000010011", "pos": "14:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:0" }, "operands": [ { "name": "rs1", "desc": "Base Address" }, { "name": "offset", "desc": "Offset" } ], "pseudocode": "Prefetch(D-Cache, Write, R[rs1] + offset);", "example": "PREFETCH.W 0(x10)", "example_note": "Prepare D-Cache for writing.", "description": "PREFETCH.W is a hint to the memory system to prefetch the cache block at rs1+offset into the data cache for a write access." }, { "mnemonic": "DRET", "architecture": "RISC-V", "extension": "Privileged", "full_name": "Debug Return", "summary": "Returns from Debug Mode to the mode defined in the 'dcsr' register.", "syntax": "DRET", "encoding": { "format": "R-Type (System)", "binary_pattern": "01111011001000000000000001110011", "hex_opcode": "0x7B200073", "visual_parts": [ { "raw": "01111011001000000000000001110011", "clean": "01111011001000000000000001110011", "pos": "31:0" } ], "bit_positions": "31:0" }, "operands": [], "pseudocode": "PC = DPC; Priv = DCSR.prv;", "example": "DRET", "example_note": "Resume execution from debug break.", "description": "DRET returns from debug mode. It restores PC from dpc and restores the privilege mode recorded before entering debug mode." }, { "mnemonic": "VSETVLI", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Set VL Immediate", "summary": "Configures the vector length (vl) and vector type (vtype) based on application needs.", "syntax": "VSETVLI rd, rs1, vtypei", "encoding": { "format": "V-Type", "binary_pattern": "0 | zimm11 | rs1 | 111 | rd | 1010111", "hex_opcode": "0x00007057", "visual_parts": [ { "raw": "0", "clean": "0", "pos": "31" }, { "raw": "zimm11", "clean": "zimm11", "pos": "30:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "111", "clean": "111", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31 | 30:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Actual VL)" }, { "name": "rs1", "desc": "Req VL (Avail)" }, { "name": "vtypei", "desc": "Config (SEW/LMUL)" } ], "pseudocode": "vl = set_config(rs1, vtypei); R[rd] = vl;", "example": "VSETVLI t0, a0, e32, m1, ta, ma", "example_note": "Request VL=a0, 32-bit elements, 1 register group.", "description": "Sets the vector length (vl) and vector type (vtype) registers based on the requested application vector length (AVL) and element width/grouping. The actual vector length set is written to rd. vtype encodes SEW (element width), LMUL (register grouping), and tail/mask policies." }, { "mnemonic": "VLE32.V", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Load Element (32-bit)", "summary": "Loads a vector of 32-bit elements from memory into a vector register.", "syntax": "VLE32.V vd, (rs1), vm", "encoding": { "format": "V-Load", "binary_pattern": "000000 | vm | 00000 | rs1 | 110 | vd | 0000111", "hex_opcode": "0x00006007", "visual_parts": [ { "raw": "000000", "clean": "000000", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "00000", "clean": "00000", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "110", "clean": "110", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "0000111", "clean": "0000111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Vector Dest" }, { "name": "rs1", "desc": "Base Address" }, { "name": "vm", "desc": "Mask" } ], "pseudocode": "foreach(i < vl): vd[i] = Mem[rs1 + i*4];", "example": "VLE32.V v8, (a0)", "example_note": "Load 32-bit integers from address in a0 to v8.", "description": "Performs a vector unit-stride load of 32-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm." }, { "mnemonic": "VSE32.V", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Store Element (32-bit)", "summary": "Stores a vector of 32-bit elements from a vector register to memory.", "syntax": "VSE32.V vs3, (rs1), vm", "encoding": { "format": "V-Store", "binary_pattern": "000000 | vm | 00000 | rs1 | 110 | vs3 | 0100111", "hex_opcode": "0x00006027", "visual_parts": [ { "raw": "000000", "clean": "000000", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "00000", "clean": "00000", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "110", "clean": "110", "pos": "14:12" }, { "raw": "vs3", "clean": "vs3", "pos": "11:7" }, { "raw": "0100111", "clean": "0100111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vs3", "desc": "Vector Source" }, { "name": "rs1", "desc": "Base Address" }, { "name": "vm", "desc": "Mask" } ], "pseudocode": "foreach(i < vl): Mem[rs1 + i*4] = vs3[i];", "example": "VSE32.V v8, (a0)", "example_note": "Store v8 to memory at a0.", "description": "Performs a vector unit-stride store of 32-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm." }, { "mnemonic": "VADD.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Integer Add", "summary": "Adds elements of two vector registers.", "syntax": "VADD.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "000000 | vm | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0x00000057", "visual_parts": [ { "raw": "000000", "clean": "000000", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = vs1[i] + vs2[i];", "example": "VADD.VV v10, v8, v9", "example_note": "v10[i] = v8[i] + v9[i]", "description": "Performs element-wise integer addition on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm." }, { "mnemonic": "VMUL.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Integer Multiply", "summary": "Multiplies elements of two vector registers.", "syntax": "VMUL.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "100101 | vm | vs2 | vs1 | 010 | vd | 1010111", "hex_opcode": "0x94002057", "visual_parts": [ { "raw": "100101", "clean": "100101", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = vs1[i] * vs2[i];", "example": "VMUL.VV v10, v8, v9", "example_note": "v10[i] = v8[i] * v9[i]", "description": "Performs element-wise integer multiplication (low bits) on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm." }, { "mnemonic": "CLZ", "architecture": "RISC-V", "extension": "Zbb", "full_name": "Count Leading Zeros", "summary": "Counts the number of 0 bits at the MSB end of the register.", "syntax": "CLZ rd, rs1", "encoding": { "format": "I-Type", "binary_pattern": "011000000000 | rs1 | 001 | rd | 0010011", "hex_opcode": "0x60001013", "visual_parts": [ { "raw": "011000000000", "clean": "011000000000", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0010011", "clean": "0010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source" } ], "pseudocode": "int count = 0; while(rs1[XLEN-1-count] == 0) count++; R[rd] = count;", "example": "CLZ x10, x11", "example_note": "Find highest set bit index.", "description": "CLZ counts the number of leading (most-significant) zero bits in rs1, writing the count to rd. Returns XLEN if rs1 is zero." }, { "mnemonic": "CTZ", "architecture": "RISC-V", "extension": "Zbb", "full_name": "Count Trailing Zeros", "summary": "Counts the number of 0 bits at the LSB end of the register.", "syntax": "CTZ rd, rs1", "encoding": { "format": "I-Type", "binary_pattern": "011000000001 | rs1 | 001 | rd | 0010011", "hex_opcode": "0x60101013", "visual_parts": [ { "raw": "011000000001", "clean": "011000000001", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0010011", "clean": "0010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source" } ], "pseudocode": "int count = 0; while(rs1[count] == 0) count++; R[rd] = count;", "example": "CTZ x10, x11", "example_note": "Find lowest set bit index.", "description": "CTZ counts the number of trailing (least-significant) zero bits in rs1, writing the count to rd. Returns XLEN if rs1 is zero." }, { "mnemonic": "CPOP", "architecture": "RISC-V", "extension": "Zbb", "full_name": "Population Count", "summary": "Counts the number of set bits (1s) in the register.", "syntax": "CPOP rd, rs1", "encoding": { "format": "I-Type", "binary_pattern": "011000000010 | rs1 | 001 | rd | 0010011", "hex_opcode": "0x60201013", "visual_parts": [ { "raw": "011000000010", "clean": "011000000010", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0010011", "clean": "0010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source" } ], "pseudocode": "R[rd] = count_set_bits(R[rs1]);", "example": "CPOP x10, x11", "example_note": "Hamming weight calculation.", "description": "CPOP counts the number of set bits (population count / Hamming weight) in rs1 and writes the count to rd." }, { "mnemonic": "ANDN", "architecture": "RISC-V", "extension": "Zbb", "full_name": "AND Not", "summary": "Performs bitwise AND with the bitwise negation of rs2 (rs1 & ~rs2).", "syntax": "ANDN rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0100000 | rs2 | rs1 | 111 | rd | 0110011", "hex_opcode": "0x40007033", "visual_parts": [ { "raw": "0100000", "clean": "0100000", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "111", "clean": "111", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source 2 (Inverted)" } ], "pseudocode": "R[rd] = R[rs1] & ~R[rs2];", "example": "ANDN x10, x11, x12", "example_note": "Clear bits in x11 that are set in x12.", "description": "ANDN computes the bitwise AND of rs1 with the bitwise NOT of rs2, writing the result to rd. Equivalent to rd = rs1 & ~rs2." }, { "mnemonic": "ORN", "architecture": "RISC-V", "extension": "Zbb", "full_name": "OR Not", "summary": "Performs bitwise OR with the bitwise negation of rs2 (rs1 | ~rs2).", "syntax": "ORN rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0100000 | rs2 | rs1 | 110 | rd | 0110011", "hex_opcode": "0x40006033", "visual_parts": [ { "raw": "0100000", "clean": "0100000", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "110", "clean": "110", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source 2 (Inverted)" } ], "pseudocode": "R[rd] = R[rs1] | ~R[rs2];", "example": "ORN x10, x11, x12", "example_note": "Set bits.", "description": "ORN computes the bitwise OR of rs1 with the bitwise NOT of rs2. Equivalent to rd = rs1 | ~rs2." }, { "mnemonic": "XNOR", "architecture": "RISC-V", "extension": "Zbb", "full_name": "Exclusive NOR", "summary": "Performs bitwise exclusive-NOR (rs1 ^ ~rs2).", "syntax": "XNOR rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0100000 | rs2 | rs1 | 100 | rd | 0110011", "hex_opcode": "0x40004033", "visual_parts": [ { "raw": "0100000", "clean": "0100000", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "100", "clean": "100", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" } ], "pseudocode": "R[rd] = ~(R[rs1] ^ R[rs2]);", "example": "XNOR x10, x11, x12", "example_note": "Logical equivalence.", "description": "XNOR computes the bitwise XNOR of rs1 and rs2. Equivalent to rd = ~(rs1 ^ rs2)." }, { "mnemonic": "ROL", "architecture": "RISC-V", "extension": "Zbb", "full_name": "Rotate Left", "summary": "Rotates the bits in rs1 left by the amount in rs2.", "syntax": "ROL rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0110000 | rs2 | rs1 | 001 | rd | 0110011", "hex_opcode": "0x60001033", "visual_parts": [ { "raw": "0110000", "clean": "0110000", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source" }, { "name": "rs2", "desc": "Rotate Amount" } ], "pseudocode": "shamt = R[rs2] & (XLEN-1); R[rd] = (R[rs1] << shamt) | (R[rs1] >> (XLEN-shamt));", "example": "ROL x10, x11, x12", "example_note": "Bitwise rotation.", "description": "ROL rotates rs1 left by the shift amount in the lower log2(XLEN) bits of rs2, writing the result to rd." }, { "mnemonic": "ROR", "architecture": "RISC-V", "extension": "Zbb", "full_name": "Rotate Right", "summary": "Rotates the bits in rs1 right by the amount in rs2.", "syntax": "ROR rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0110000 | rs2 | rs1 | 101 | rd | 0110011", "hex_opcode": "0x60005033", "visual_parts": [ { "raw": "0110000", "clean": "0110000", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "101", "clean": "101", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source" }, { "name": "rs2", "desc": "Rotate Amount" } ], "pseudocode": "shamt = R[rs2] & (XLEN-1); R[rd] = (R[rs1] >> shamt) | (R[rs1] << (XLEN-shamt));", "example": "ROR x10, x11, x12", "example_note": "Bitwise rotation.", "description": "ROR rotates rs1 right by the shift amount in the lower log2(XLEN) bits of rs2, writing the result to rd." }, { "mnemonic": "MAX", "architecture": "RISC-V", "extension": "Zbb", "full_name": "Maximum", "summary": "Computes the signed maximum of two registers.", "syntax": "MAX rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000101 | rs2 | rs1 | 110 | rd | 0110011", "hex_opcode": "0x0A006033", "visual_parts": [ { "raw": "0000101", "clean": "0000101", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "110", "clean": "110", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" } ], "pseudocode": "R[rd] = (R[rs1] >s R[rs2]) ? R[rs1] : R[rs2];", "example": "MAX x10, x11, x12", "example_note": "Signed Max.", "description": "MAX computes the signed maximum of rs1 and rs2, writing the result to rd." }, { "mnemonic": "MIN", "architecture": "RISC-V", "extension": "Zbb", "full_name": "Minimum", "summary": "Computes the signed minimum of two registers.", "syntax": "MIN rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000101 | rs2 | rs1 | 100 | rd | 0110011", "hex_opcode": "0x0A004033", "visual_parts": [ { "raw": "0000101", "clean": "0000101", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "100", "clean": "100", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" } ], "pseudocode": "R[rd] = (R[rs1] > rs1) & Mask(SEW);", "description": "Performs a narrowing operation, halving the result element width relative to the source. Optionally saturates the result. Active elements are determined by vl; masking by vm.", "example": "VNSRL.WX v1, v4, a0, v0.t" }, { "mnemonic": "VNSRA.WX", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Narrowing Shift Right Arithmetic", "summary": "Arithmetically shifts 2*N-bit elements right and narrows to N-bits.", "syntax": "VNSRA.WX vd, vs2, rs1, vm", "encoding": { "format": "OPIVX", "binary_pattern": "101101 | vm | vs2 | rs1 | 100 | vd | 1010111", "hex_opcode": "0xB4004057", "visual_parts": [ { "raw": "101101", "clean": "101101", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "100", "clean": "100", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest (SEW)" }, { "name": "vs2", "desc": "Src Vector (2*SEW)" }, { "name": "rs1", "desc": "Shift Amount" } ], "pseudocode": "foreach(i < vl): vd[i] = (vs2[i] >>s rs1) & Mask(SEW);", "description": "Performs a narrowing operation, halving the result element width relative to the source. Optionally saturates the result. Active elements are determined by vl; masking by vm.", "example": "VNSRA.WX v1, v4, a0, v0.t" }, { "mnemonic": "VMERGE.VVM", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Merge", "summary": "Merges two vectors based on the mask (if mask=0, pick vs2; if mask=1, pick vs1).", "syntax": "VMERGE.VVM vd, vs2, vs1, v0", "encoding": { "format": "OPIVV", "binary_pattern": "0101110 | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0x5C000057", "visual_parts": [ { "raw": "0101110", "clean": "0101110", "pos": "31:25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "False Src" }, { "name": "vs1", "desc": "True Src" }, { "name": "v0", "desc": "Mask" } ], "pseudocode": "foreach(i < vl): vd[i] = v0[i] ? vs1[i] : vs2[i];", "description": "Merges elements from vs1 and vs2 (or an immediate) according to the mask: masked-on elements come from vs1, masked-off from vs2.", "example": "VMERGE.VVM v1, v4, v2, v0" }, { "mnemonic": "VMV.V.V", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Move", "summary": "Copies a vector register.", "syntax": "VMV.V.V vd, vs1", "encoding": { "format": "OPIVV", "binary_pattern": "010111100000 | vs1 | 000 | vd | 1010111", "hex_opcode": "0x5E000057", "visual_parts": [ { "raw": "010111100000", "clean": "010111100000", "pos": "31:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs1", "desc": "Source" } ], "pseudocode": "vd = vs1;", "description": "Copies vector vs1 to vd under mask vm.", "example": "VMV.V.V v1, v2" }, { "mnemonic": "VMV.X.S", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Move Scalar to Integer", "summary": "Copies element 0 of a vector to an integer register.", "syntax": "VMV.X.S rd, vs2", "encoding": { "format": "OPMVX", "binary_pattern": "0100001 | vs2 | 00000010 | rd | 1010111", "hex_opcode": "0x42002057", "visual_parts": [ { "raw": "0100001", "clean": "0100001", "pos": "31:25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "00000010", "clean": "00000010", "pos": "19:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Int)" }, { "name": "vs2", "desc": "Source (Vector)" } ], "pseudocode": "rd = vs2[0];", "description": "Moves element 0 of vector vs2 to GPR rd.", "example": "VMV.X.S t0, v4" }, { "mnemonic": "VMV.S.X", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Move Integer to Scalar", "summary": "Copies an integer register to element 0 of a vector.", "syntax": "VMV.S.X vd, rs1", "encoding": { "format": "OPMVX", "binary_pattern": "010000100000 | rs1 | 110 | vd | 1010111", "hex_opcode": "0x42006057", "visual_parts": [ { "raw": "010000100000", "clean": "010000100000", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "110", "clean": "110", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest (Vector)" }, { "name": "rs1", "desc": "Source (Int)" } ], "pseudocode": "vd[0] = rs1;", "description": "Moves a scalar integer value from GPR rs1 into element 0 of vd.", "example": "VMV.S.X v1, a0" }, { "mnemonic": "VMFEQ.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Float Equal", "summary": "Compares float vectors for equality, writing result to mask register.", "syntax": "VMFEQ.VV vd, vs2, vs1, vm", "encoding": { "format": "OPFVV", "binary_pattern": "011000 | vm | vs2 | vs1 | 001 | vd | 1010111", "hex_opcode": "0x60001057", "visual_parts": [ { "raw": "011000", "clean": "011000", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest Mask" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = (vs2[i] == vs1[i]) ? 1 : 0;", "description": "Compares elements element-wise for equal and writes a mask result to vd.", "example": "VMFEQ.VV v1, v4, v2, v0.t" }, { "mnemonic": "VMFLE.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Float Less or Equal", "summary": "Compares float vectors (vs2 <= vs1), writing result to mask register.", "syntax": "VMFLE.VV vd, vs2, vs1, vm", "encoding": { "format": "OPFVV", "binary_pattern": "011001 | vm | vs2 | vs1 | 001 | vd | 1010111", "hex_opcode": "0x64001057", "visual_parts": [ { "raw": "011001", "clean": "011001", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest Mask" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = (vs2[i] <= vs1[i]) ? 1 : 0;", "description": "Compares elements element-wise for less than or equal and writes a mask result to vd.", "example": "VMFLE.VV v1, v4, v2, v0.t" }, { "mnemonic": "VMFLT.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Float Less Than", "summary": "Compares float vectors (vs2 < vs1), writing result to mask register.", "syntax": "VMFLT.VV vd, vs2, vs1, vm", "encoding": { "format": "OPFVV", "binary_pattern": "011011 | vm | vs2 | vs1 | 001 | vd | 1010111", "hex_opcode": "0x6C001057", "visual_parts": [ { "raw": "011011", "clean": "011011", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest Mask" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = (vs2[i] < vs1[i]) ? 1 : 0;", "description": "Compares elements element-wise for less than and writes a mask result to vd.", "example": "VMFLT.VV v1, v4, v2, v0.t" }, { "mnemonic": "VFCLASS.V", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Float Classify", "summary": "Classifies elements of a float vector (NaN, Inf, etc.).", "syntax": "VFCLASS.V vd, vs2, vm", "encoding": { "format": "OPFVV", "binary_pattern": "010011 | vm | vs2 | 10000001 | vd | 1010111", "hex_opcode": "0x4C081057", "visual_parts": [ { "raw": "010011", "clean": "010011", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "10000001", "clean": "10000001", "pos": "19:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest (Mask Bits)" }, { "name": "vs2", "desc": "Src Vector" } ], "pseudocode": "foreach(i < vl): vd[i] = classify(vs2[i]);", "description": "Classifies each floating-point element (NaN, infinity, zero, normal, subnormal, negative/positive), writing a bitmask classification to vd.", "example": "VFCLASS.V v1, v4, v0.t" }, { "mnemonic": "VFMV.F.S", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Move Float to Scalar", "summary": "Moves element 0 of a float vector to a scalar float register.", "syntax": "VFMV.F.S fd, vs2", "encoding": { "format": "OPFVW", "binary_pattern": "0100001 | vs2 | 00000001 | rd | 1010111", "hex_opcode": "0x42001057", "visual_parts": [ { "raw": "0100001", "clean": "0100001", "pos": "31:25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "00000001", "clean": "00000001", "pos": "19:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:12 | 11:7 | 6:0" }, "operands": [ { "name": "fd", "desc": "Dest (Float)" }, { "name": "vs2", "desc": "Src Vector" } ], "pseudocode": "fd = vs2[0];", "description": "Moves element 0 of vector vs2 to floating-point register fd.", "example": "VFMV.F.S fd, v4" }, { "mnemonic": "VFMV.S.F", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Move Scalar to Float", "summary": "Moves a scalar float register to element 0 of a vector.", "syntax": "VFMV.S.F vd, fs1", "encoding": { "format": "OPFVW", "binary_pattern": "010000100000 | rs1 | 101 | vd | 1010111", "hex_opcode": "0x42005057", "visual_parts": [ { "raw": "010000100000", "clean": "010000100000", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "101", "clean": "101", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest Vector" }, { "name": "fs1", "desc": "Src Float" } ], "pseudocode": "vd[0] = fs1;", "description": "Moves floating-point scalar fs1 into element 0 of vd.", "example": "VFMV.S.F v1, fs1" }, { "mnemonic": "FLI.S", "architecture": "RISC-V", "extension": "Zfa", "full_name": "Float Load Immediate (Single)", "summary": "Loads a common floating-point constant (e.g., 1.0, 0.5, PI) into a register from a small table.", "syntax": "FLI.S rd, rs1", "encoding": { "format": "R-Type", "binary_pattern": "111100000001 | rs1 | 000 | rd | 1010011", "hex_opcode": "0xF0100053", "visual_parts": [ { "raw": "111100000001", "clean": "111100000001", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Constant Index" } ], "pseudocode": "F[rd] = FloatTable[rs1];", "description": "Loads a single-precision (32-bit) floating-point constant from a predefined lookup table (indexed by rs1) into fd. Provides common constants such as -1, 0, 1, 2, ∞, and others without a memory access.", "example": "FLI.S t0, a0" }, { "mnemonic": "FLI.D", "architecture": "RISC-V", "extension": "Zfa", "full_name": "Float Load Immediate (Double)", "summary": "Loads a common double-precision constant into a register.", "syntax": "FLI.D rd, rs1", "encoding": { "format": "R-Type", "binary_pattern": "111100100001 | rs1 | 000 | rd | 1010011", "hex_opcode": "0xF2100053", "visual_parts": [ { "raw": "111100100001", "clean": "111100100001", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Constant Index" } ], "pseudocode": "F[rd] = DoubleTable[rs1];", "description": "Loads a double-precision (64-bit) floating-point constant from a predefined lookup table (indexed by rs1) into fd. Provides common constants such as -1, 0, 1, 2, ∞, and others without a memory access.", "example": "FLI.D t0, a0" }, { "mnemonic": "FLI.H", "architecture": "RISC-V", "extension": "Zfa", "full_name": "Float Load Immediate (Half)", "summary": "Loads a common half-precision constant into a register.", "syntax": "FLI.H rd, rs1", "encoding": { "format": "R-Type", "binary_pattern": "111101000001 | rs1 | 000 | rd | 1010011", "hex_opcode": "0xF4100053", "visual_parts": [ { "raw": "111101000001", "clean": "111101000001", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Constant Index" } ], "pseudocode": "F[rd] = HalfTable[rs1];", "description": "Loads a half-precision (16-bit) floating-point constant from a predefined lookup table (indexed by rs1) into fd. Provides common constants such as -1, 0, 1, 2, ∞, and others without a memory access.", "example": "FLI.H t0, a0" }, { "mnemonic": "FMINM.S", "architecture": "RISC-V", "extension": "Zfa", "full_name": "Float Minimum (IEEE 754-2019)", "summary": "Minimum of two floats, treating -0.0 as smaller than +0.0 (canonicalize NaNs).", "syntax": "FMINM.S rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0010100 | rs2 | rs1 | 010 | rd | 1010011", "hex_opcode": "0x28002053", "visual_parts": [ { "raw": "0010100", "clean": "0010100", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" } ], "pseudocode": "F[rd] = minNum(F[rs1], F[rs2]);", "description": "Returns the single-precision (32-bit) floating-point minimum of rs1 and rs2, following IEEE 754-2019 minNum/maxNum semantics. Quiet NaN inputs return the non-NaN operand; signalling NaN inputs raise invalid-operation.", "example": "FMINM.S t0, a0, a1" }, { "mnemonic": "FMAXM.S", "architecture": "RISC-V", "extension": "Zfa", "full_name": "Float Maximum (IEEE 754-2019)", "summary": "Maximum of two floats, treating +0.0 as larger than -0.0.", "syntax": "FMAXM.S rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0010100 | rs2 | rs1 | 011 | rd | 1010011", "hex_opcode": "0x28003053", "visual_parts": [ { "raw": "0010100", "clean": "0010100", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "011", "clean": "011", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" } ], "pseudocode": "F[rd] = maxNum(F[rs1], F[rs2]);", "description": "Returns the single-precision (32-bit) floating-point maximum of rs1 and rs2, following IEEE 754-2019 minNum/maxNum semantics. Quiet NaN inputs return the non-NaN operand; signalling NaN inputs raise invalid-operation.", "example": "FMAXM.S t0, a0, a1" }, { "mnemonic": "FROUND.S", "architecture": "RISC-V", "extension": "Zfa", "full_name": "Float Round to Integer", "summary": "Rounds a float to the nearest integer value (returned as a float).", "syntax": "FROUND.S rd, rs1, rm", "encoding": { "format": "I-Type", "binary_pattern": "010000000100 | rs1 | rm | rd | 1010011", "hex_opcode": "0x40400053", "visual_parts": [ { "raw": "010000000100", "clean": "010000000100", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rm", "desc": "Mode" } ], "pseudocode": "F[rd] = round(F[rs1]);", "description": "Rounds the single-precision (32-bit) floating-point value in rs1 to an integer value (still in FP format), using the rounding mode in the rm field. The result preserves the FP type.", "example": "FROUND.S t0, a0, rm" }, { "mnemonic": "AMOCAS.W", "architecture": "RISC-V", "extension": "Zacas", "full_name": "Atomic Compare and Swap Word", "summary": "Atomically compares memory at rs1 with rd; if equal, writes rs2 to memory. Returns original value in rd.", "syntax": "AMOCAS.W rd, rs2, (rs1)", "encoding": { "format": "R-Type (Atomic)", "binary_pattern": "00101 | aq | rl | rs2 | rs1 | 010 | rd | 0101111", "hex_opcode": "0x2800202F", "visual_parts": [ { "raw": "00101", "clean": "00101", "pos": "31:27" }, { "raw": "aq", "clean": "aq", "pos": "26" }, { "raw": "rl", "clean": "rl", "pos": "25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0101111", "clean": "0101111", "pos": "6:0" } ], "bit_positions": "31:27 | 26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest/Compare" }, { "name": "rs2", "desc": "Swap Value" }, { "name": "rs1", "desc": "Address" } ], "pseudocode": "atomic { if(M[rs1]==R[rd]) M[rs1]=R[rs2]; R[rd]=M[rs1]; }", "description": "AMOCAS.W (Zacas) atomically compares the word at the address in rs1 with rs1 (the compare value), and if equal, writes rs2 to that address. The original value is returned in rd.", "example": "AMOCAS.W t0, a1, a0" }, { "mnemonic": "AMOCAS.D", "architecture": "RISC-V", "extension": "Zacas", "full_name": "Atomic Compare and Swap Doubleword", "summary": "Atomically compares 64-bit memory at rs1 with rd; if equal, writes rs2 to memory.", "syntax": "AMOCAS.D rd, rs2, (rs1)", "encoding": { "format": "R-Type (Atomic)", "binary_pattern": "00101 | aq | rl | rs2 | rs1 | 011 | rd | 0101111", "hex_opcode": "0x2800302F", "visual_parts": [ { "raw": "00101", "clean": "00101", "pos": "31:27" }, { "raw": "aq", "clean": "aq", "pos": "26" }, { "raw": "rl", "clean": "rl", "pos": "25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "011", "clean": "011", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0101111", "clean": "0101111", "pos": "6:0" } ], "bit_positions": "31:27 | 26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest/Compare" }, { "name": "rs2", "desc": "Swap Value" }, { "name": "rs1", "desc": "Address" } ], "pseudocode": "atomic { if(M[rs1]==R[rd]) M[rs1]=R[rs2]; R[rd]=M[rs1]; }", "description": "AMOCAS.D atomically compares a doubleword in memory with a register pair and conditionally swaps it with another register pair (RV64 only).", "example": "AMOCAS.D t0, a1, a0" }, { "mnemonic": "C.MUL", "architecture": "RISC-V", "extension": "Zcb", "full_name": "Compressed Multiply", "summary": "Performs 32-bit multiplication (rd = rd * rs2) in 16-bit encoding.", "syntax": "C.MUL rd', rs2'", "encoding": { "format": "CA", "binary_pattern": "? | 100111 | rd_rs1_p | 10 | rs2_p | 01", "hex_opcode": "0x00009C41", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "100111", "clean": "100111", "pos": "15:10" }, { "raw": "rd_rs1_p", "clean": "rd_rs1_p", "pos": "9:7" }, { "raw": "10", "clean": "10", "pos": "6:5" }, { "raw": "rs2_p", "clean": "rs2_p", "pos": "4:2" }, { "raw": "01", "clean": "01", "pos": "1:0" } ], "bit_positions": "31:16 | 15:10 | 9:7 | 6:5 | 4:2 | 1:0" }, "operands": [ { "name": "rd'", "desc": "Dest/Src1" }, { "name": "rs2'", "desc": "Source register 2 (3-bit compressed)" } ], "pseudocode": "R[rd'] = R[rd'] * R[rs2'];", "description": "Multiplies rd′ and rs2′, writing the lower XLEN bits of the product to rd′ (Zcb).", "example": "C.MUL rd', rs2'" }, { "mnemonic": "C.ZEXT.B", "architecture": "RISC-V", "extension": "Zcb", "full_name": "Compressed Zero Extend Byte", "summary": "Zero extends the lowest byte of rd' to XLEN.", "syntax": "C.ZEXT.B rd'", "encoding": { "format": "CR", "binary_pattern": "? | 100111 | rd_rs1_p | 1100001", "hex_opcode": "0x00009C61", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "100111", "clean": "100111", "pos": "15:10" }, { "raw": "rd_rs1_p", "clean": "rd_rs1_p", "pos": "9:7" }, { "raw": "1100001", "clean": "1100001", "pos": "6:0" } ], "bit_positions": "31:16 | 15:10 | 9:7 | 6:0" }, "operands": [ { "name": "rd'", "desc": "Dest/Src" } ], "pseudocode": "R[rd'] = zext(R[rd'][7:0]);", "description": "Zero-extends the least-significant byte of rd′ in place (Zcb).", "example": "C.ZEXT.B rd'" }, { "mnemonic": "C.SEXT.B", "architecture": "RISC-V", "extension": "Zcb", "full_name": "Compressed Sign Extend Byte", "summary": "Sign extends the lowest byte of rd' to XLEN.", "syntax": "C.SEXT.B rd'", "encoding": { "format": "CR", "binary_pattern": "? | 100111 | rd_rs1_p | 1100101", "hex_opcode": "0x00009C65", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "100111", "clean": "100111", "pos": "15:10" }, { "raw": "rd_rs1_p", "clean": "rd_rs1_p", "pos": "9:7" }, { "raw": "1100101", "clean": "1100101", "pos": "6:0" } ], "bit_positions": "31:16 | 15:10 | 9:7 | 6:0" }, "operands": [ { "name": "rd'", "desc": "Dest/Src" } ], "pseudocode": "R[rd'] = sext(R[rd'][7:0]);", "description": "Sign-extends the least-significant byte of rd′ in place (Zcb).", "example": "C.SEXT.B rd'" }, { "mnemonic": "C.NOT", "architecture": "RISC-V", "extension": "Zcb", "full_name": "Compressed Bitwise NOT", "summary": "Computes bitwise logical negation.", "syntax": "C.NOT rd'", "encoding": { "format": "CR", "binary_pattern": "? | 100111 | rd_rs1_p | 1110101", "hex_opcode": "0x00009C75", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "100111", "clean": "100111", "pos": "15:10" }, { "raw": "rd_rs1_p", "clean": "rd_rs1_p", "pos": "9:7" }, { "raw": "1110101", "clean": "1110101", "pos": "6:0" } ], "bit_positions": "31:16 | 15:10 | 9:7 | 6:0" }, "operands": [ { "name": "rd'", "desc": "Dest/Src" } ], "pseudocode": "R[rd'] = ~R[rd'];", "description": "Bitwise logical NOT of rd′; writes to rd′ (Zcb). Equivalent to XORI rd′, -1.", "example": "C.NOT rd'" }, { "mnemonic": "SM4ED", "architecture": "RISC-V", "extension": "Zksh", "full_name": "SM4 Encryption/Decryption", "summary": "Accelerates the SM4 block cipher (encryption/decryption round).", "syntax": "SM4ED rd, rs1, rs2, bs", "encoding": { "format": "R-Type", "binary_pattern": "bs | 11000 | rs2 | rs1 | 000 | rd | 0110011", "hex_opcode": "0x30000033", "visual_parts": [ { "raw": "bs", "clean": "bs", "pos": "31:30" }, { "raw": "11000", "clean": "11000", "pos": "29:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:30 | 29:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" }, { "name": "bs", "desc": "Byte Select" } ], "pseudocode": "rd = SM4_Round(rs1, rs2, bs);", "description": "SM4ED performs one round of the SM4 block cipher encryption/decryption by applying the S-box and linear transformation to four bytes from rs2, XORing with rs1, and accumulating into rd.", "example": "SM4ED t0, a0, a1, bs" }, { "mnemonic": "SM4KS", "architecture": "RISC-V", "extension": "Zksh", "full_name": "SM4 Key Schedule", "summary": "Accelerates the SM4 key schedule generation.", "syntax": "SM4KS rd, rs1, rs2, bs", "encoding": { "format": "R-Type", "binary_pattern": "bs | 11010 | rs2 | rs1 | 000 | rd | 0110011", "hex_opcode": "0x34000033", "visual_parts": [ { "raw": "bs", "clean": "bs", "pos": "31:30" }, { "raw": "11010", "clean": "11010", "pos": "29:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:30 | 29:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" }, { "name": "bs", "desc": "Byte Select" } ], "pseudocode": "rd = SM4_KeyGen(rs1, rs2, bs);", "description": "SM4KS performs one step of the SM4 key schedule by applying the S-box and key-schedule linear transformation to four bytes from rs2, XORing with rs1, and accumulating into rd.", "example": "SM4KS t0, a0, a1, bs" }, { "mnemonic": "SM3P0", "architecture": "RISC-V", "extension": "Zksh", "full_name": "SM3 P0 Transformation", "summary": "Performs the P0 permutation for the SM3 hash algorithm.", "syntax": "SM3P0 rd, rs1", "encoding": { "format": "R-Type", "binary_pattern": "000100001000 | rs1 | 001 | rd | 0010011", "hex_opcode": "0x10801013", "visual_parts": [ { "raw": "000100001000", "clean": "000100001000", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0010011", "clean": "0010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" } ], "pseudocode": "rd = P0(rs1);", "description": "SM3P0 applies the SM3 P0 permutation function to rs1 and writes to rd. Used in the key schedule and compression function of the Chinese SM3 hash algorithm.", "example": "SM3P0 t0, a0" }, { "mnemonic": "SM3P1", "architecture": "RISC-V", "extension": "Zksh", "full_name": "SM3 P1 Transformation", "summary": "Performs the P1 permutation for the SM3 hash algorithm.", "syntax": "SM3P1 rd, rs1", "encoding": { "format": "R-Type", "binary_pattern": "000100001001 | rs1 | 001 | rd | 0010011", "hex_opcode": "0x10901013", "visual_parts": [ { "raw": "000100001001", "clean": "000100001001", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0010011", "clean": "0010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" } ], "pseudocode": "rd = P1(rs1);", "description": "SM3P1 applies the SM3 P1 permutation function to rs1 and writes to rd. Used in message expansion of the SM3 hash algorithm.", "example": "SM3P1 t0, a0" }, { "mnemonic": "CM.PUSH", "architecture": "RISC-V", "extension": "Zcmp", "full_name": "Push Registers", "summary": "Pushes multiple registers (ra, s0-s11) to the stack and adjusts sp. Critical for small code size.", "syntax": "CM.PUSH {reg_list}, -stack_adj", "encoding": { "format": "Push/Pop", "binary_pattern": "? | 10111000 | c_rlist | c_spimm | 10", "hex_opcode": "0x0000B802", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "10111000", "clean": "10111000", "pos": "15:8" }, { "raw": "c_rlist", "clean": "c_rlist", "pos": "7:4" }, { "raw": "c_spimm", "clean": "c_spimm", "pos": "3:2" }, { "raw": "10", "clean": "10", "pos": "1:0" } ], "bit_positions": "31:16 | 15:8 | 7:4 | 3:2 | 1:0" }, "operands": [ { "name": "rlist", "desc": "Register List" }, { "name": "stack_adj", "desc": "Stack Adjustment" } ], "pseudocode": "SP -= adj; Mem[SP] = {regs};", "description": "CM.PUSH (Zcmp) saves a set of registers to the stack and decrements sp by a stack-frame size. The register list and stack adjustment are encoded in the instruction. Used as a function prologue.", "example": "CM.PUSH {reg_list}, -stack_adj" }, { "mnemonic": "CM.POP", "architecture": "RISC-V", "extension": "Zcmp", "full_name": "Pop Registers", "summary": "Pops multiple registers from the stack and restores sp.", "syntax": "CM.POP {reg_list}, stack_adj", "encoding": { "format": "Push/Pop", "binary_pattern": "? | 10111010 | c_rlist | c_spimm | 10", "hex_opcode": "0x0000BA02", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "10111010", "clean": "10111010", "pos": "15:8" }, { "raw": "c_rlist", "clean": "c_rlist", "pos": "7:4" }, { "raw": "c_spimm", "clean": "c_spimm", "pos": "3:2" }, { "raw": "10", "clean": "10", "pos": "1:0" } ], "bit_positions": "31:16 | 15:8 | 7:4 | 3:2 | 1:0" }, "operands": [ { "name": "rlist", "desc": "Register List" }, { "name": "stack_adj", "desc": "Stack Adjustment" } ], "pseudocode": "{regs} = Mem[SP]; SP += adj;", "description": "CM.POP (Zcmp) restores a set of registers from the stack, increments sp by the matching stack-frame size, and returns. Used as a function epilogue.", "example": "CM.POP {reg_list}, stack_adj" }, { "mnemonic": "VSETVL", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Set VL", "summary": "Sets the vector length (VL) based on the application vector length (AVL) in rs1 and configuration in rs2.", "syntax": "VSETVL rd, rs1, rs2", "encoding": { "format": "V-Type", "binary_pattern": "1000000 | rs2 | rs1 | 111 | rd | 1010111", "hex_opcode": "0x80007057", "visual_parts": [ { "raw": "1000000", "clean": "1000000", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "111", "clean": "111", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (New VL)" }, { "name": "rs1", "desc": "AVL" }, { "name": "rs2", "desc": "Config (VTYPE)" } ], "pseudocode": "vl = set_config(rs1, rs2); R[rd] = vl;", "description": "Sets the vector length (vl) and vector type (vtype) registers based on the requested application vector length (AVL) and element width/grouping. The actual vector length set is written to rd. vtype encodes SEW (element width), LMUL (register grouping), and tail/mask policies.", "example": "VSETVL t0, a0, a1" }, { "mnemonic": "CBO.ZERO", "architecture": "RISC-V", "extension": "Zicboz", "full_name": "Cache Block Zero", "summary": "Zeros a cache block corresponding to the address in rs1.", "syntax": "CBO.ZERO (rs1)", "encoding": { "format": "I-Type", "binary_pattern": "000000000100 | rs1 | 010000000001111", "hex_opcode": "0x0040200F", "visual_parts": [ { "raw": "000000000100", "clean": "000000000100", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "010000000001111", "clean": "010000000001111", "pos": "14:0" } ], "bit_positions": "31:20 | 19:15 | 14:0" }, "operands": [ { "name": "rs1", "desc": "Address" } ], "pseudocode": "memset(BlockAddr(rs1), 0, BlockSize);", "description": "CBO.ZERO writes zeros to the cache block containing the effective address. Typically faster than a sequence of store instructions for zeroing memory.", "example": "CBO.ZERO a0" }, { "mnemonic": "FCVT.W.S", "architecture": "RISC-V", "extension": "F", "full_name": "Float Convert to Word (Single)", "summary": "Converts a single-precision floating-point number to a signed 32-bit integer.", "syntax": "FCVT.W.S rd, rs1", "encoding": { "format": "I-Type (Float)", "binary_pattern": "110000000000 | rs1 | rm | rd | 1010011", "hex_opcode": "0xC0000053", "visual_parts": [ { "raw": "110000000000", "clean": "110000000000", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Integer)" }, { "name": "rs1", "desc": "Source (Float)" } ], "pseudocode": "R[rd] = sext(f32_to_i32(F[rs1]));", "example": "FCVT.W.S x10, f1", "example_note": "Convert float f1 to int x10.", "description": "Converts between floating-point types or between floating-point and integer. Result is rounded according to the dynamic rounding mode. Invalid conversions produce the IEEE default NaN or the appropriate integer saturation value." }, { "mnemonic": "FCVT.S.W", "architecture": "RISC-V", "extension": "F", "full_name": "Float Convert from Word (Single)", "summary": "Converts a signed 32-bit integer to a single-precision floating-point number.", "syntax": "FCVT.S.W rd, rs1", "encoding": { "format": "I-Type (Float)", "binary_pattern": "110100000000 | rs1 | rm | rd | 1010011", "hex_opcode": "0xD0000053", "visual_parts": [ { "raw": "110100000000", "clean": "110100000000", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Float)" }, { "name": "rs1", "desc": "Source (Integer)" } ], "pseudocode": "F[rd] = i32_to_f32(R[rs1]);", "example": "FCVT.S.W f1, x10", "example_note": "Convert int x10 to float f1.", "description": "Converts between floating-point types or between floating-point and integer. Result is rounded according to the dynamic rounding mode. Invalid conversions produce the IEEE default NaN or the appropriate integer saturation value." }, { "mnemonic": "FCVT.D.S", "architecture": "RISC-V", "extension": "D", "full_name": "Float Convert Single to Double", "summary": "Converts a single-precision float to a double-precision float.", "syntax": "FCVT.D.S rd, rs1", "encoding": { "format": "I-Type (Float)", "binary_pattern": "010000100000 | rs1 | rm | rd | 1010011", "hex_opcode": "0x42000053", "visual_parts": [ { "raw": "010000100000", "clean": "010000100000", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Double)" }, { "name": "rs1", "desc": "Source (Single)" } ], "pseudocode": "F[rd] = f32_to_f64(F[rs1]);", "example": "FCVT.D.S f0, f1", "example_note": "Promote float to double.", "description": "Converts between floating-point types or between floating-point and integer. Result is rounded according to the dynamic rounding mode. Invalid conversions produce the IEEE default NaN or the appropriate integer saturation value." }, { "mnemonic": "FCVT.S.D", "architecture": "RISC-V", "extension": "D", "full_name": "Float Convert Double to Single", "summary": "Converts a double-precision float to a single-precision float.", "syntax": "FCVT.S.D rd, rs1", "encoding": { "format": "I-Type (Float)", "binary_pattern": "010000000001 | rs1 | rm | rd | 1010011", "hex_opcode": "0x40100053", "visual_parts": [ { "raw": "010000000001", "clean": "010000000001", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Single)" }, { "name": "rs1", "desc": "Source (Double)" } ], "pseudocode": "F[rd] = f64_to_f32(F[rs1]);", "example": "FCVT.S.D f1, f0", "example_note": "Demote double to float.", "description": "Converts between floating-point types or between floating-point and integer. Result is rounded according to the dynamic rounding mode. Invalid conversions produce the IEEE default NaN or the appropriate integer saturation value." }, { "mnemonic": "FSGNJ.S", "architecture": "RISC-V", "extension": "F", "full_name": "Float Sign Injection (Single)", "summary": "Injects the sign of rs2 into rs1. Used to copy values or manipulate signs.", "syntax": "FSGNJ.S rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0010000 | rs2 | rs1 | 000 | rd | 1010011", "hex_opcode": "0x20000053", "visual_parts": [ { "raw": "0010000", "clean": "0010000", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source (Body)" }, { "name": "rs2", "desc": "Source (Sign)" } ], "pseudocode": "F[rd] = {F[rs2][31], F[rs1][30:0]};", "example": "FSGNJ.S f1, f2, f3", "example_note": "f1 gets magnitude of f2 and sign of f3.", "description": "Produces a result with the magnitude of rs1 and the sign bit taken from the source rs2. Used to implement floating-point absolute value, negate, and copy-sign." }, { "mnemonic": "FSGNJN.S", "architecture": "RISC-V", "extension": "F", "full_name": "Float Sign Injection Negate (Single)", "summary": "Injects the *negated* sign of rs2 into rs1. Used for negation and absolute value.", "syntax": "FSGNJN.S rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0010000 | rs2 | rs1 | 001 | rd | 1010011", "hex_opcode": "0x20001053", "visual_parts": [ { "raw": "0010000", "clean": "0010000", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source (Body)" }, { "name": "rs2", "desc": "Source (Sign)" } ], "pseudocode": "F[rd] = {~F[rs2][31], F[rs1][30:0]};", "example": "FSGNJN.S f1, f2, f2", "example_note": "Negates f2 (f1 = -f2).", "description": "Produces a result with the magnitude of rs1 and the sign bit taken from the source rs2. Used to implement floating-point absolute value, negate, and copy-sign." }, { "mnemonic": "FSGNJX.S", "architecture": "RISC-V", "extension": "F", "full_name": "Float Sign Injection XOR (Single)", "summary": "Injects the XOR of signs of rs1 and rs2. Used to copy sign.", "syntax": "FSGNJX.S rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0010000 | rs2 | rs1 | 010 | rd | 1010011", "hex_opcode": "0x20002053", "visual_parts": [ { "raw": "0010000", "clean": "0010000", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" } ], "pseudocode": "F[rd] = {F[rs1][31] ^ F[rs2][31], F[rs1][30:0]};", "example": "FSGNJX.S f1, f1, f2", "example_note": "Logic similar to Abs(f1) if f2 is properly set.", "description": "Produces a result with the magnitude of rs1 and the sign bit taken from the source rs2. Used to implement floating-point absolute value, negate, and copy-sign." }, { "mnemonic": "FEQ.S", "architecture": "RISC-V", "extension": "F", "full_name": "Float Equal (Single)", "summary": "Sets integer rd to 1 if float rs1 equals float rs2, else 0.", "syntax": "FEQ.S rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "1010000 | rs2 | rs1 | 010 | rd | 1010011", "hex_opcode": "0xA0002053", "visual_parts": [ { "raw": "1010000", "clean": "1010000", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Integer)" }, { "name": "rs1", "desc": "Src 1 (Float)" }, { "name": "rs2", "desc": "Src 2 (Float)" } ], "pseudocode": "R[rd] = (F[rs1] == F[rs2]) ? 1 : 0;", "example": "FEQ.S x10, f1, f2", "example_note": "x10 = (f1 == f2)", "description": "Performs a single-precision (32-bit) floating-point equality comparison and writes 1 (true) or 0 (false) to integer rd. NaN inputs produce 0 (unordered), except FEQ which raises invalid-operation if either operand is a signalling NaN." }, { "mnemonic": "FLT.S", "architecture": "RISC-V", "extension": "F", "full_name": "Float Less Than (Single)", "summary": "Sets integer rd to 1 if float rs1 is less than float rs2, else 0.", "syntax": "FLT.S rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "1010000 | rs2 | rs1 | 001 | rd | 1010011", "hex_opcode": "0xA0001053", "visual_parts": [ { "raw": "1010000", "clean": "1010000", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Integer)" }, { "name": "rs1", "desc": "Src 1 (Float)" }, { "name": "rs2", "desc": "Src 2 (Float)" } ], "pseudocode": "R[rd] = (F[rs1] < F[rs2]) ? 1 : 0;", "example": "FLT.S x10, f1, f2", "example_note": "x10 = (f1 < f2)", "description": "Performs a single-precision (32-bit) floating-point less-than comparison and writes 1 (true) or 0 (false) to integer rd. NaN inputs produce 0 (unordered), except FEQ which raises invalid-operation if either operand is a signalling NaN." }, { "mnemonic": "FLE.S", "architecture": "RISC-V", "extension": "F", "full_name": "Float Less or Equal (Single)", "summary": "Sets integer rd to 1 if float rs1 is less than or equal to float rs2, else 0.", "syntax": "FLE.S rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "1010000 | rs2 | rs1 | 000 | rd | 1010011", "hex_opcode": "0xA0000053", "visual_parts": [ { "raw": "1010000", "clean": "1010000", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Integer)" }, { "name": "rs1", "desc": "Src 1 (Float)" }, { "name": "rs2", "desc": "Src 2 (Float)" } ], "pseudocode": "R[rd] = (F[rs1] <= F[rs2]) ? 1 : 0;", "example": "FLE.S x10, f1, f2", "example_note": "x10 = (f1 <= f2)", "description": "Performs a single-precision (32-bit) floating-point less-than-or-equal comparison and writes 1 (true) or 0 (false) to integer rd. NaN inputs produce 0 (unordered), except FEQ which raises invalid-operation if either operand is a signalling NaN." }, { "mnemonic": "FMV.X.W", "architecture": "RISC-V", "extension": "F", "full_name": "Move Float to Integer", "summary": "Moves the bit pattern of a floating-point register to an integer register.", "syntax": "FMV.X.W rd, rs1", "encoding": { "format": "I-Type (Float)", "binary_pattern": "111000000000 | rs1 | 000 | rd | 1010011", "hex_opcode": "0xE0000053", "visual_parts": [ { "raw": "111000000000", "clean": "111000000000", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Integer)" }, { "name": "rs1", "desc": "Source (Float)" } ], "pseudocode": "R[rd] = sext(F[rs1]);", "example": "FMV.X.W x10, f1", "example_note": "Copy bits from f1 to x10.", "description": "Moves bits from a floating-point register to an integer register (or vice versa) without conversion. The bit pattern is preserved exactly." }, { "mnemonic": "FMV.W.X", "architecture": "RISC-V", "extension": "F", "full_name": "Move Integer to Float", "summary": "Moves the bit pattern of an integer register to a floating-point register.", "syntax": "FMV.W.X rd, rs1", "encoding": { "format": "I-Type (Float)", "binary_pattern": "111100000000 | rs1 | 000 | rd | 1010011", "hex_opcode": "0xF0000053", "visual_parts": [ { "raw": "111100000000", "clean": "111100000000", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Float)" }, { "name": "rs1", "desc": "Source (Integer)" } ], "pseudocode": "F[rd] = R[rs1];", "example": "FMV.W.X f1, x10", "example_note": "Copy bits from x10 to f1.", "description": "Moves bits from a floating-point register to an integer register (or vice versa) without conversion. The bit pattern is preserved exactly." }, { "mnemonic": "VFMUL.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Float Multiply", "summary": "Multiplies elements of two floating-point vectors.", "syntax": "VFMUL.VV vd, vs2, vs1, vm", "encoding": { "format": "OPFVV", "binary_pattern": "100100 | vm | vs2 | vs1 | 001 | vd | 1010111", "hex_opcode": "0x90001057", "visual_parts": [ { "raw": "100100", "clean": "100100", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = vs1[i] * vs2[i];", "description": "Performs element-wise floating-point multiplication on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VFMUL.VV v1, v4, v2, v0.t" }, { "mnemonic": "VFDIV.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Float Divide", "summary": "Divides elements of two floating-point vectors.", "syntax": "VFDIV.VV vd, vs2, vs1, vm", "encoding": { "format": "OPFVV", "binary_pattern": "100000 | vm | vs2 | vs1 | 001 | vd | 1010111", "hex_opcode": "0x80001057", "visual_parts": [ { "raw": "100000", "clean": "100000", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Divisor" }, { "name": "vs1", "desc": "Dividend" } ], "pseudocode": "foreach(i < vl): vd[i] = vs1[i] / vs2[i];", "description": "Performs element-wise floating-point division on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VFDIV.VV v1, v4, v2, v0.t" }, { "mnemonic": "VFSQRT.V", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Float Square Root", "summary": "Computes the square root of elements in a floating-point vector.", "syntax": "VFSQRT.V vd, vs2, vm", "encoding": { "format": "OPFVV", "binary_pattern": "010011 | vm | vs2 | 00000001 | vd | 1010111", "hex_opcode": "0x4C001057", "visual_parts": [ { "raw": "010011", "clean": "010011", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "00000001", "clean": "00000001", "pos": "19:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source" } ], "pseudocode": "foreach(i < vl): vd[i] = sqrt(vs2[i]);", "description": "Performs element-wise FP square root on operands, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VFSQRT.V v1, v4, v0.t" }, { "mnemonic": "VFMADD.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Float Fused Multiply-Add", "summary": "Computes (vs1 * vs2) + vd (overwriting vd) with single rounding.", "syntax": "VFMADD.VV vd, vs1, vs2, vm", "encoding": { "format": "OPFVV", "binary_pattern": "101000 | vm | vs2 | vs1 | 001 | vd | 1010111", "hex_opcode": "0xA0001057", "visual_parts": [ { "raw": "101000", "clean": "101000", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest/Addend" }, { "name": "vs1", "desc": "Source vector register 1" }, { "name": "vs2", "desc": "Source vector register 2" } ], "pseudocode": "foreach(i < vl): vd[i] = (vs1[i] * vs2[i]) + vd[i];", "description": "Performs element-wise FP fused multiply-add on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VFMADD.VV v1, v2, v4, v0.t" }, { "mnemonic": "VFMIN.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Float Minimum", "summary": "Writes the smaller of two floating-point vector elements to vd.", "syntax": "VFMIN.VV vd, vs2, vs1, vm", "encoding": { "format": "OPFVV", "binary_pattern": "000100 | vm | vs2 | vs1 | 001 | vd | 1010111", "hex_opcode": "0x10001057", "visual_parts": [ { "raw": "000100", "clean": "000100", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = min(vs1[i], vs2[i]);", "description": "Performs element-wise FP min on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VFMIN.VV v1, v4, v2, v0.t" }, { "mnemonic": "VFMAX.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Float Maximum", "summary": "Writes the larger of two floating-point vector elements to vd.", "syntax": "VFMAX.VV vd, vs2, vs1, vm", "encoding": { "format": "OPFVV", "binary_pattern": "000110 | vm | vs2 | vs1 | 001 | vd | 1010111", "hex_opcode": "0x18001057", "visual_parts": [ { "raw": "000110", "clean": "000110", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = max(vs1[i], vs2[i]);", "description": "Performs element-wise FP max on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VFMAX.VV v1, v4, v2, v0.t" }, { "mnemonic": "VFSGNJ.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Float Sign Injection", "summary": "Injects the sign of vs2 into vs1 (Copy Sign).", "syntax": "VFSGNJ.VV vd, vs2, vs1, vm", "encoding": { "format": "OPFVV", "binary_pattern": "001000 | vm | vs2 | vs1 | 001 | vd | 1010111", "hex_opcode": "0x20001057", "visual_parts": [ { "raw": "001000", "clean": "001000", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Sign Src" }, { "name": "vs1", "desc": "Body Src" } ], "pseudocode": "foreach(i < vl): vd[i] = copy_sign(vs1[i], vs2[i]);", "description": "Injects the sign of one FP element into the magnitude of another, implementing sign copy, negate, or XOR operations.", "example": "VFSGNJ.VV v1, v4, v2, v0.t" }, { "mnemonic": "VSADD.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Saturating Integer Add", "summary": "Adds elements with signed saturation (clips to Max/Min instead of wrapping).", "syntax": "VSADD.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "100001 | vm | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0x84000057", "visual_parts": [ { "raw": "100001", "clean": "100001", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = saturate_s(vs1[i] + vs2[i]);", "description": "Performs element-wise signed saturating add on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VSADD.VV v1, v4, v2, v0.t" }, { "mnemonic": "VSSUB.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Saturating Integer Subtract", "summary": "Subtracts elements with signed saturation.", "syntax": "VSSUB.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "100011 | vm | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0x8C000057", "visual_parts": [ { "raw": "100011", "clean": "100011", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = saturate_s(vs1[i] - vs2[i]);", "description": "Performs element-wise signed saturating subtract on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VSSUB.VV v1, v4, v2, v0.t" }, { "mnemonic": "VAADD.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Averaging Add", "summary": "Computes (vs1 + vs2) >> 1 with rounding.", "syntax": "VAADD.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "001001 | vm | vs2 | vs1 | 010 | vd | 1010111", "hex_opcode": "0x24002057", "visual_parts": [ { "raw": "001001", "clean": "001001", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = (vs1[i] + vs2[i] + 1) >> 1;", "description": "Vector Averaging Add: Computes (vs1 + vs2) >> 1 with rounding. Operation: foreach(i < vl): vd[i] = (vs1[i] + vs2[i] + 1) >> 1;.", "example": "VAADD.VV v1, v4, v2, v0.t" }, { "mnemonic": "VCOMPRESS.VM", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Compress", "summary": "Compacts elements from source vector into contiguous elements in dest where the mask is 1.", "syntax": "VCOMPRESS.VM vd, vs2, vs1", "encoding": { "format": "OPMVV", "binary_pattern": "0101111 | vs2 | vs1 | 010 | vd | 1010111", "hex_opcode": "0x5E002057", "visual_parts": [ { "raw": "0101111", "clean": "0101111", "pos": "31:25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source" }, { "name": "vs1", "desc": "Mask" } ], "pseudocode": "idx = 0; foreach(i < vl): if vs1[i]: vd[idx++] = vs2[i];", "description": "Compresses active (masked) elements of vs2 into the low elements of vd, discarding masked-off elements.", "example": "VCOMPRESS.VM v1, v4, v2" }, { "mnemonic": "FSUB.H", "architecture": "RISC-V", "extension": "Zfh", "full_name": "Float Subtract (Half)", "summary": "Performs 16-bit floating-point subtraction.", "syntax": "FSUB.H rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000110 | rs2 | rs1 | rm | rd | 1010011", "hex_opcode": "0x0C000053", "visual_parts": [ { "raw": "0000110", "clean": "0000110", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" } ], "pseudocode": "F[rd] = F[rs1] - F[rs2];", "description": "Performs half-precision (16-bit) floating-point subtraction. The operation subtracts the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.", "example": "FSUB.H t0, a0, a1" }, { "mnemonic": "FMUL.H", "architecture": "RISC-V", "extension": "Zfh", "full_name": "Float Multiply (Half)", "summary": "Performs 16-bit floating-point multiplication.", "syntax": "FMUL.H rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0001010 | rs2 | rs1 | rm | rd | 1010011", "hex_opcode": "0x14000053", "visual_parts": [ { "raw": "0001010", "clean": "0001010", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" } ], "pseudocode": "F[rd] = F[rs1] * F[rs2];", "description": "Performs half-precision (16-bit) floating-point multiplication. The operation multiplies the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.", "example": "FMUL.H t0, a0, a1" }, { "mnemonic": "FDIV.H", "architecture": "RISC-V", "extension": "Zfh", "full_name": "Float Divide (Half)", "summary": "Performs 16-bit floating-point division.", "syntax": "FDIV.H rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0001110 | rs2 | rs1 | rm | rd | 1010011", "hex_opcode": "0x1C000053", "visual_parts": [ { "raw": "0001110", "clean": "0001110", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Dividend" }, { "name": "rs2", "desc": "Divisor" } ], "pseudocode": "F[rd] = F[rs1] / F[rs2];", "description": "Performs half-precision (16-bit) floating-point division. The operation divides the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.", "example": "FDIV.H t0, a0, a1" }, { "mnemonic": "FSQRT.H", "architecture": "RISC-V", "extension": "Zfh", "full_name": "Float Square Root (Half)", "summary": "Computes the square root of a 16-bit floating-point number.", "syntax": "FSQRT.H rd, rs1", "encoding": { "format": "I-Type (Float)", "binary_pattern": "010111000000 | rs1 | rm | rd | 1010011", "hex_opcode": "0x5C000053", "visual_parts": [ { "raw": "010111000000", "clean": "010111000000", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source" } ], "pseudocode": "F[rd] = sqrt(F[rs1]);", "description": "Stores a floating-point register to memory at address rs1+sext(offset).", "example": "FSQRT.H t0, a0" }, { "mnemonic": "FMIN.H", "architecture": "RISC-V", "extension": "Zfh", "full_name": "Float Minimum (Half)", "summary": "Writes the smaller of two 16-bit floating-point values to rd.", "syntax": "FMIN.H rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0010110 | rs2 | rs1 | 000 | rd | 1010011", "hex_opcode": "0x2C000053", "visual_parts": [ { "raw": "0010110", "clean": "0010110", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" } ], "pseudocode": "F[rd] = min(F[rs1], F[rs2]);", "description": "Returns the half-precision (16-bit) floating-point minimum of rs1 and rs2, following IEEE 754-2019 minNum/maxNum semantics. Quiet NaN inputs return the non-NaN operand; signalling NaN inputs raise invalid-operation.", "example": "FMIN.H t0, a0, a1" }, { "mnemonic": "FMAX.H", "architecture": "RISC-V", "extension": "Zfh", "full_name": "Float Maximum (Half)", "summary": "Writes the larger of two 16-bit floating-point values to rd.", "syntax": "FMAX.H rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0010110 | rs2 | rs1 | 001 | rd | 1010011", "hex_opcode": "0x2C001053", "visual_parts": [ { "raw": "0010110", "clean": "0010110", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" } ], "pseudocode": "F[rd] = max(F[rs1], F[rs2]);", "description": "Returns the half-precision (16-bit) floating-point maximum of rs1 and rs2, following IEEE 754-2019 minNum/maxNum semantics. Quiet NaN inputs return the non-NaN operand; signalling NaN inputs raise invalid-operation.", "example": "FMAX.H t0, a0, a1" }, { "mnemonic": "FMADD.H", "architecture": "RISC-V", "extension": "Zfh", "full_name": "Float Fused Multiply-Add (Half)", "summary": "Computes (rs1 * rs2) + rs3 with single rounding (16-bit).", "syntax": "FMADD.H rd, rs1, rs2, rs3", "encoding": { "format": "R4-Type", "binary_pattern": "rs3 | 10 | rs2 | rs1 | rm | rd | 1000011", "hex_opcode": "0x04000043", "visual_parts": [ { "raw": "rs3", "clean": "rs3", "pos": "31:27" }, { "raw": "10", "clean": "10", "pos": "26:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1000011", "clean": "1000011", "pos": "6:0" } ], "bit_positions": "31:27 | 26:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" }, { "name": "rs3", "desc": "Src 3" } ], "pseudocode": "F[rd] = (F[rs1] * F[rs2]) + F[rs3];", "description": "Performs half-precision (16-bit) floating-point fused multiply-add. The operation computes fused multiply-add on the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.", "example": "FMADD.H t0, a0, a1, a2" }, { "mnemonic": "FMSUB.H", "architecture": "RISC-V", "extension": "Zfh", "full_name": "Float Fused Multiply-Subtract (Half)", "summary": "Computes (rs1 * rs2) - rs3 with single rounding (16-bit).", "syntax": "FMSUB.H rd, rs1, rs2, rs3", "encoding": { "format": "R4-Type", "binary_pattern": "rs3 | 10 | rs2 | rs1 | rm | rd | 1000111", "hex_opcode": "0x04000047", "visual_parts": [ { "raw": "rs3", "clean": "rs3", "pos": "31:27" }, { "raw": "10", "clean": "10", "pos": "26:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1000111", "clean": "1000111", "pos": "6:0" } ], "bit_positions": "31:27 | 26:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" }, { "name": "rs3", "desc": "Src 3" } ], "pseudocode": "F[rd] = (F[rs1] * F[rs2]) - F[rs3];", "description": "Performs half-precision (16-bit) floating-point fused multiply-subtract. The operation computes fused multiply-subtract on the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.", "example": "FMSUB.H t0, a0, a1, a2" }, { "mnemonic": "FNMADD.H", "architecture": "RISC-V", "extension": "Zfh", "full_name": "Float Negated Fused Multiply-Add (Half)", "summary": "Computes -(rs1 * rs2) - rs3 with single rounding (16-bit).", "syntax": "FNMADD.H rd, rs1, rs2, rs3", "encoding": { "format": "R4-Type", "binary_pattern": "rs3 | 10 | rs2 | rs1 | rm | rd | 1001111", "hex_opcode": "0x0400004F", "visual_parts": [ { "raw": "rs3", "clean": "rs3", "pos": "31:27" }, { "raw": "10", "clean": "10", "pos": "26:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1001111", "clean": "1001111", "pos": "6:0" } ], "bit_positions": "31:27 | 26:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" }, { "name": "rs3", "desc": "Src 3" } ], "pseudocode": "F[rd] = -((F[rs1] * F[rs2]) + F[rs3]);", "description": "Performs half-precision (16-bit) floating-point fused negate-multiply-add. The operation computes fused negate-multiply-add on the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.", "example": "FNMADD.H t0, a0, a1, a2" }, { "mnemonic": "FNMSUB.H", "architecture": "RISC-V", "extension": "Zfh", "full_name": "Float Negated Fused Multiply-Subtract (Half)", "summary": "Computes -(rs1 * rs2) + rs3 with single rounding (16-bit).", "syntax": "FNMSUB.H rd, rs1, rs2, rs3", "encoding": { "format": "R4-Type", "binary_pattern": "rs3 | 10 | rs2 | rs1 | rm | rd | 1001011", "hex_opcode": "0x0400004B", "visual_parts": [ { "raw": "rs3", "clean": "rs3", "pos": "31:27" }, { "raw": "10", "clean": "10", "pos": "26:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1001011", "clean": "1001011", "pos": "6:0" } ], "bit_positions": "31:27 | 26:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" }, { "name": "rs3", "desc": "Src 3" } ], "pseudocode": "F[rd] = -((F[rs1] * F[rs2]) - F[rs3]);", "description": "Performs half-precision (16-bit) floating-point fused negate-multiply-subtract. The operation computes fused negate-multiply-subtract on the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.", "example": "FNMSUB.H t0, a0, a1, a2" }, { "mnemonic": "FEQ.H", "architecture": "RISC-V", "extension": "Zfh", "full_name": "Float Equal (Half)", "summary": "Sets integer rd to 1 if half-precision rs1 equals rs2, else 0.", "syntax": "FEQ.H rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "1010010 | rs2 | rs1 | 010 | rd | 1010011", "hex_opcode": "0xA4002053", "visual_parts": [ { "raw": "1010010", "clean": "1010010", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Int)" }, { "name": "rs1", "desc": "Src 1 (Half)" }, { "name": "rs2", "desc": "Src 2 (Half)" } ], "pseudocode": "R[rd] = (F[rs1] == F[rs2]) ? 1 : 0;", "description": "Performs a half-precision (16-bit) floating-point equality comparison and writes 1 (true) or 0 (false) to integer rd. NaN inputs produce 0 (unordered), except FEQ which raises invalid-operation if either operand is a signalling NaN.", "example": "FEQ.H t0, a0, a1" }, { "mnemonic": "FLT.H", "architecture": "RISC-V", "extension": "Zfh", "full_name": "Float Less Than (Half)", "summary": "Sets integer rd to 1 if half-precision rs1 is less than rs2, else 0.", "syntax": "FLT.H rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "1010010 | rs2 | rs1 | 001 | rd | 1010011", "hex_opcode": "0xA4001053", "visual_parts": [ { "raw": "1010010", "clean": "1010010", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Int)" }, { "name": "rs1", "desc": "Src 1 (Half)" }, { "name": "rs2", "desc": "Src 2 (Half)" } ], "pseudocode": "R[rd] = (F[rs1] < F[rs2]) ? 1 : 0;", "description": "Performs a half-precision (16-bit) floating-point less-than comparison and writes 1 (true) or 0 (false) to integer rd. NaN inputs produce 0 (unordered), except FEQ which raises invalid-operation if either operand is a signalling NaN.", "example": "FLT.H t0, a0, a1" }, { "mnemonic": "FLE.H", "architecture": "RISC-V", "extension": "Zfh", "full_name": "Float Less or Equal (Half)", "summary": "Sets integer rd to 1 if half-precision rs1 is less than or equal to rs2, else 0.", "syntax": "FLE.H rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "1010010 | rs2 | rs1 | 000 | rd | 1010011", "hex_opcode": "0xA4000053", "visual_parts": [ { "raw": "1010010", "clean": "1010010", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Int)" }, { "name": "rs1", "desc": "Src 1 (Half)" }, { "name": "rs2", "desc": "Src 2 (Half)" } ], "pseudocode": "R[rd] = (F[rs1] <= F[rs2]) ? 1 : 0;", "description": "Performs a half-precision (16-bit) floating-point less-than-or-equal comparison and writes 1 (true) or 0 (false) to integer rd. NaN inputs produce 0 (unordered), except FEQ which raises invalid-operation if either operand is a signalling NaN.", "example": "FLE.H t0, a0, a1" }, { "mnemonic": "FCLASS.H", "architecture": "RISC-V", "extension": "Zfh", "full_name": "Float Classify (Half)", "summary": "Examines a 16-bit floating-point number and generates a classification bitmask.", "syntax": "FCLASS.H rd, rs1", "encoding": { "format": "R-Type", "binary_pattern": "111001000000 | rs1 | 001 | rd | 1010011", "hex_opcode": "0xE4001053", "visual_parts": [ { "raw": "111001000000", "clean": "111001000000", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Int)" }, { "name": "rs1", "desc": "Src (Half)" } ], "pseudocode": "R[rd] = classify_half(F[rs1]);", "description": "Classifies the half-precision (16-bit) floating-point value in rs1, writing a 10-bit one-hot result to integer rd. Bits represent: negative infinity, negative normal, negative subnormal, negative zero, positive zero, positive subnormal, positive normal, positive infinity, signalling NaN, quiet NaN.", "example": "FCLASS.H t0, a0" }, { "mnemonic": "FSGNJ.H", "architecture": "RISC-V", "extension": "Zfh", "full_name": "Float Sign Injection (Half)", "summary": "Injects the sign of rs2 into rs1 (16-bit).", "syntax": "FSGNJ.H rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0010010 | rs2 | rs1 | 000 | rd | 1010011", "hex_opcode": "0x24000053", "visual_parts": [ { "raw": "0010010", "clean": "0010010", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Sign Src" } ], "pseudocode": "F[rd] = {F[rs2][15], F[rs1][14:0]};", "description": "Produces a result with the magnitude of rs1 and the sign bit taken from the source rs2. Used to implement floating-point absolute value, negate, and copy-sign.", "example": "FSGNJ.H t0, a0, a1" }, { "mnemonic": "FSGNJN.H", "architecture": "RISC-V", "extension": "Zfh", "full_name": "Float Sign Injection Negate (Half)", "summary": "Injects the negated sign of rs2 into rs1 (16-bit).", "syntax": "FSGNJN.H rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0010010 | rs2 | rs1 | 001 | rd | 1010011", "hex_opcode": "0x24001053", "visual_parts": [ { "raw": "0010010", "clean": "0010010", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Sign Src" } ], "pseudocode": "F[rd] = {~F[rs2][15], F[rs1][14:0]};", "description": "Produces a result with the magnitude of rs1 and the sign bit taken from the source rs2. Used to implement floating-point absolute value, negate, and copy-sign.", "example": "FSGNJN.H t0, a0, a1" }, { "mnemonic": "FSGNJX.H", "architecture": "RISC-V", "extension": "Zfh", "full_name": "Float Sign Injection XOR (Half)", "summary": "Injects the XOR of signs of rs1 and rs2 (16-bit).", "syntax": "FSGNJX.H rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0010010 | rs2 | rs1 | 010 | rd | 1010011", "hex_opcode": "0x24002053", "visual_parts": [ { "raw": "0010010", "clean": "0010010", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Sign Src" } ], "pseudocode": "F[rd] = {F[rs1][15] ^ F[rs2][15], F[rs1][14:0]};", "description": "Produces a result with the magnitude of rs1 and the sign bit taken from the source rs2. Used to implement floating-point absolute value, negate, and copy-sign.", "example": "FSGNJX.H t0, a0, a1" }, { "mnemonic": "FCVT.W.H", "architecture": "RISC-V", "extension": "Zfh", "full_name": "Convert Half to Word", "summary": "Converts a 16-bit floating-point number to a 32-bit signed integer.", "syntax": "FCVT.W.H rd, rs1", "encoding": { "format": "I-Type (Float)", "binary_pattern": "110001000000 | rs1 | rm | rd | 1010011", "hex_opcode": "0xC4000053", "visual_parts": [ { "raw": "110001000000", "clean": "110001000000", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Int)" }, { "name": "rs1", "desc": "Src (Half)" } ], "pseudocode": "R[rd] = sext(f16_to_i32(F[rs1]));", "description": "Converts between floating-point types or between floating-point and integer. Result is rounded according to the dynamic rounding mode. Invalid conversions produce the IEEE default NaN or the appropriate integer saturation value.", "example": "FCVT.W.H t0, a0" }, { "mnemonic": "FCVT.WU.H", "architecture": "RISC-V", "extension": "Zfh", "full_name": "Convert Half to Unsigned Word", "summary": "Converts a 16-bit floating-point number to a 32-bit unsigned integer.", "syntax": "FCVT.WU.H rd, rs1", "encoding": { "format": "I-Type (Float)", "binary_pattern": "110001000001 | rs1 | rm | rd | 1010011", "hex_opcode": "0xC4100053", "visual_parts": [ { "raw": "110001000001", "clean": "110001000001", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (UInt)" }, { "name": "rs1", "desc": "Src (Half)" } ], "pseudocode": "R[rd] = sext(f16_to_u32(F[rs1]));", "description": "Converts between floating-point types or between floating-point and integer. Result is rounded according to the dynamic rounding mode. Invalid conversions produce the IEEE default NaN or the appropriate integer saturation value.", "example": "FCVT.WU.H t0, a0" }, { "mnemonic": "FCVT.H.W", "architecture": "RISC-V", "extension": "Zfh", "full_name": "Convert Word to Half", "summary": "Converts a 32-bit signed integer to a 16-bit floating-point number.", "syntax": "FCVT.H.W rd, rs1", "encoding": { "format": "I-Type (Float)", "binary_pattern": "110101000000 | rs1 | rm | rd | 1010011", "hex_opcode": "0xD4000053", "visual_parts": [ { "raw": "110101000000", "clean": "110101000000", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Half)" }, { "name": "rs1", "desc": "Src (Int)" } ], "pseudocode": "F[rd] = i32_to_f16(R[rs1]);", "description": "Converts between floating-point types or between floating-point and integer. Result is rounded according to the dynamic rounding mode. Invalid conversions produce the IEEE default NaN or the appropriate integer saturation value.", "example": "FCVT.H.W t0, a0" }, { "mnemonic": "FCVT.H.WU", "architecture": "RISC-V", "extension": "Zfh", "full_name": "Convert Unsigned Word to Half", "summary": "Converts a 32-bit unsigned integer to a 16-bit floating-point number.", "syntax": "FCVT.H.WU rd, rs1", "encoding": { "format": "I-Type (Float)", "binary_pattern": "110101000001 | rs1 | rm | rd | 1010011", "hex_opcode": "0xD4100053", "visual_parts": [ { "raw": "110101000001", "clean": "110101000001", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Half)" }, { "name": "rs1", "desc": "Src (UInt)" } ], "pseudocode": "F[rd] = u32_to_f16(R[rs1]);", "description": "Converts between floating-point types or between floating-point and integer. Result is rounded according to the dynamic rounding mode. Invalid conversions produce the IEEE default NaN or the appropriate integer saturation value.", "example": "FCVT.H.WU t0, a0" }, { "mnemonic": "VNCLIP.WV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Narrowing Clip (Arithmetic Shift)", "summary": "Shifts elements right, rounds, and clips (saturates) the result to the destination width. Critical for Quantization.", "syntax": "VNCLIP.WV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "101111 | vm | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0xBC000057", "visual_parts": [ { "raw": "101111", "clean": "101111", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest (Narrow)" }, { "name": "vs2", "desc": "Src Vector (Wide)" }, { "name": "vs1", "desc": "Shift Vector" } ], "pseudocode": "foreach(i < vl): vd[i] = clip(round(vs2[i] >> vs1[i]));", "description": "Performs a narrowing operation, halving the result element width relative to the source. Optionally saturates the result. Active elements are determined by vl; masking by vm.", "example": "VNCLIP.WV v1, v4, v2, v0.t" }, { "mnemonic": "VNCLIPU.WI", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Narrowing Clip Unsigned (Immediate)", "summary": "Shifts right (logical), rounds, and clips to unsigned destination. Used for pixel packing.", "syntax": "VNCLIPU.WI vd, vs2, imm, vm", "encoding": { "format": "OPIVI", "binary_pattern": "101110 | vm | vs2 | zimm5 | 011 | vd | 1010111", "hex_opcode": "0xB8003057", "visual_parts": [ { "raw": "101110", "clean": "101110", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "zimm5", "clean": "zimm5", "pos": "19:15" }, { "raw": "011", "clean": "011", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest (Narrow)" }, { "name": "vs2", "desc": "Src Vector (Wide)" }, { "name": "imm", "desc": "Shift Amount" } ], "pseudocode": "foreach(i < vl): vd[i] = clip_u(round(vs2[i] >>u imm));", "description": "Performs a narrowing operation, halving the result element width relative to the source. Optionally saturates the result. Active elements are determined by vl; masking by vm.", "example": "VNCLIPU.WI v1, v4, 16, v0.t" }, { "mnemonic": "VFCVT.X.F.V", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Float to Signed Integer Convert", "summary": "Converts floating-point elements to signed integers.", "syntax": "VFCVT.X.F.V vd, vs2, vm", "encoding": { "format": "OPFVV", "binary_pattern": "010010 | vm | vs2 | 00001001 | vd | 1010111", "hex_opcode": "0x48009057", "visual_parts": [ { "raw": "010010", "clean": "010010", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "00001001", "clean": "00001001", "pos": "19:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest (Int)" }, { "name": "vs2", "desc": "Src (Float)" } ], "pseudocode": "foreach(i < vl): vd[i] = float_to_int(vs2[i]);", "description": "Converts vector elements between floating-point and integer types, or between floating-point precisions. Conversions respect the active rounding mode.", "example": "VFCVT.X.F.V v1, v4, v0.t" }, { "mnemonic": "VFCVT.F.X.V", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Signed Integer to Float Convert", "summary": "Converts signed integer elements to floating-point.", "syntax": "VFCVT.F.X.V vd, vs2, vm", "encoding": { "format": "OPFVV", "binary_pattern": "010010 | vm | vs2 | 00011001 | vd | 1010111", "hex_opcode": "0x48019057", "visual_parts": [ { "raw": "010010", "clean": "010010", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "00011001", "clean": "00011001", "pos": "19:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest (Float)" }, { "name": "vs2", "desc": "Src (Int)" } ], "pseudocode": "foreach(i < vl): vd[i] = int_to_float(vs2[i]);", "description": "Converts vector elements between floating-point and integer types, or between floating-point precisions. Conversions respect the active rounding mode.", "example": "VFCVT.F.X.V v1, v4, v0.t" }, { "mnemonic": "VFWCVT.F.X.V", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Widening Integer to Float Convert", "summary": "Converts N-bit integers to 2*N-bit floats (e.g., Int16 -> FP32).", "syntax": "VFWCVT.F.X.V vd, vs2, vm", "encoding": { "format": "OPFVV", "binary_pattern": "010010 | vm | vs2 | 01011001 | vd | 1010111", "hex_opcode": "0x48059057", "visual_parts": [ { "raw": "010010", "clean": "010010", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "01011001", "clean": "01011001", "pos": "19:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest (Wide Float)" }, { "name": "vs2", "desc": "Src (Narrow Int)" } ], "pseudocode": "foreach(i < vl): vd[i] = int_to_wide_float(vs2[i]);", "description": "Performs a widening operation, producing results twice as wide as the source elements. Results are written to vd using 2× the element grouping (EEW). The number of elements and masking are governed by vl and vm.", "example": "VFWCVT.F.X.V v1, v4, v0.t" }, { "mnemonic": "VFNCVT.F.F.W", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Narrowing Float Convert", "summary": "Converts 2*N-bit floats to N-bit floats (e.g., FP32 -> FP16).", "syntax": "VFNCVT.F.F.W vd, vs2, vm", "encoding": { "format": "OPFVV", "binary_pattern": "010010 | vm | vs2 | 10100001 | vd | 1010111", "hex_opcode": "0x480A1057", "visual_parts": [ { "raw": "010010", "clean": "010010", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "10100001", "clean": "10100001", "pos": "19:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest (Narrow Float)" }, { "name": "vs2", "desc": "Src (Wide Float)" } ], "pseudocode": "foreach(i < vl): vd[i] = narrow_float(vs2[i]);", "description": "Converts vector elements between floating-point and integer types, or between floating-point precisions. Conversions respect the active rounding mode.", "example": "VFNCVT.F.F.W v1, v4, v0.t" }, { "mnemonic": "VFREC7.V", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Float Reciprocal Estimate 7-bit", "summary": "Computes an estimate of 1/x (7-bit precision). Used for fast division/normalization loops.", "syntax": "VFREC7.V vd, vs2, vm", "encoding": { "format": "OPFVV", "binary_pattern": "010011 | vm | vs2 | 00101001 | vd | 1010111", "hex_opcode": "0x4C029057", "visual_parts": [ { "raw": "010011", "clean": "010011", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "00101001", "clean": "00101001", "pos": "19:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source" } ], "pseudocode": "foreach(i < vl): vd[i] = approx_reciprocal(vs2[i]);", "description": "Vector Float Reciprocal Estimate 7-bit: Computes an estimate of 1/x (7-bit precision). Used for fast division/normalization loops. Operation: foreach(i < vl): vd[i] = approx_reciprocal(vs2[i]);.", "example": "VFREC7.V v1, v4, v0.t" }, { "mnemonic": "VFRSQRT7.V", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Float Reciprocal Sqrt Estimate 7-bit", "summary": "Computes an estimate of 1/sqrt(x). Critical for vector normalization.", "syntax": "VFRSQRT7.V vd, vs2, vm", "encoding": { "format": "OPFVV", "binary_pattern": "010011 | vm | vs2 | 00100001 | vd | 1010111", "hex_opcode": "0x4C021057", "visual_parts": [ { "raw": "010011", "clean": "010011", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "00100001", "clean": "00100001", "pos": "19:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source" } ], "pseudocode": "foreach(i < vl): vd[i] = approx_rsqrt(vs2[i]);", "description": "Vector Float Reciprocal Sqrt Estimate 7-bit: Computes an estimate of 1/sqrt(x). Critical for vector normalization. Operation: foreach(i < vl): vd[i] = approx_rsqrt(vs2[i]);.", "example": "VFRSQRT7.V v1, v4, v0.t" }, { "mnemonic": "VMADC.VVM", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Add with Carry (Produce Mask)", "summary": "Adds two vectors and a carry-in, producing the carry-out to the destination mask.", "syntax": "VMADC.VVM vd, vs2, vs1, v0", "encoding": { "format": "OPIVV", "binary_pattern": "0100010 | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0x44000057", "visual_parts": [ { "raw": "0100010", "clean": "0100010", "pos": "31:25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest Mask (Carry Out)" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" }, { "name": "v0", "desc": "Carry-In Mask" } ], "pseudocode": "foreach(i < vl): vd[i] = carry_out(vs1[i] + vs2[i] + v0[i]);", "description": "Vector Add with Carry (Produce Mask): Adds two vectors and a carry-in, producing the carry-out to the destination mask. Operation: foreach(i < vl): vd[i] = carry_out(vs1[i] + vs2[i] + v0[i]);.", "example": "VMADC.VVM v1, v4, v2, v0" }, { "mnemonic": "VSBC.VVM", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Subtract with Borrow", "summary": "Subtracts two vectors minus a borrow-in from the mask register.", "syntax": "VSBC.VVM vd, vs2, vs1, v0", "encoding": { "format": "OPIVV", "binary_pattern": "0100100 | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0x48000057", "visual_parts": [ { "raw": "0100100", "clean": "0100100", "pos": "31:25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" }, { "name": "v0", "desc": "Borrow-In Mask" } ], "pseudocode": "foreach(i < vl): vd[i] = vs1[i] - vs2[i] - v0[i];", "description": "Vector Subtract with Borrow: Subtracts two vectors minus a borrow-in from the mask register. Operation: foreach(i < vl): vd[i] = vs1[i] - vs2[i] - v0[i];.", "example": "VSBC.VVM v1, v4, v2, v0" }, { "mnemonic": "VMACC.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Integer Multiply-Accumulate", "summary": "Computes vd = vd + (vs1 * vs2). Essential for dot products.", "syntax": "VMACC.VV vd, vs1, vs2, vm", "encoding": { "format": "OPIVV", "binary_pattern": "101101 | vm | vs2 | vs1 | 010 | vd | 1010111", "hex_opcode": "0xB4002057", "visual_parts": [ { "raw": "101101", "clean": "101101", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest/Accumulator" }, { "name": "vs1", "desc": "Source vector register 1" }, { "name": "vs2", "desc": "Source vector register 2" } ], "pseudocode": "foreach(i < vl): vd[i] = vd[i] + (vs1[i] * vs2[i]);", "description": "Vector Integer Multiply-Accumulate: Computes vd = vd + (vs1 * vs2). Essential for dot products. Operation: foreach(i < vl): vd[i] = vd[i] + (vs1[i] * vs2[i]);.", "example": "VMACC.VV v1, v2, v4, v0.t" }, { "mnemonic": "VNMSUB.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Integer Negative Multiply-Subtract", "summary": "Computes vd = -(vd - (vs1 * vs2)).", "syntax": "VNMSUB.VV vd, vs1, vs2, vm", "encoding": { "format": "OPIVV", "binary_pattern": "101011 | vm | vs2 | vs1 | 010 | vd | 1010111", "hex_opcode": "0xAC002057", "visual_parts": [ { "raw": "101011", "clean": "101011", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest/Accumulator" }, { "name": "vs1", "desc": "Source vector register 1" }, { "name": "vs2", "desc": "Source vector register 2" } ], "pseudocode": "foreach(i < vl): vd[i] = -(vd[i] - (vs1[i] * vs2[i]));", "description": "Performs a narrowing operation, halving the result element width relative to the source. Optionally saturates the result. Active elements are determined by vl; masking by vm.", "example": "VNMSUB.VV v1, v2, v4, v0.t" }, { "mnemonic": "VSMUL.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Single-Width Saturating Multiply", "summary": "Performs signed saturating multiplication, keeping the high half of the product (Fixed-point support).", "syntax": "VSMUL.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "100111 | vm | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0x9C000057", "visual_parts": [ { "raw": "100111", "clean": "100111", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = (sext(vs1[i]) * sext(vs2[i])) >> (SEW-1);", "description": "Performs a vector mask register store of element-sized-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.", "example": "VSMUL.VV v1, v4, v2, v0.t" }, { "mnemonic": "VREDMAX.VS", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Reduction Maximum (Signed)", "summary": "Reduces a vector to a scalar by finding the maximum signed element.", "syntax": "VREDMAX.VS vd, vs2, vs1, vm", "encoding": { "format": "OPMVV", "binary_pattern": "000111 | vm | vs2 | vs1 | 010 | vd | 1010111", "hex_opcode": "0x1C002057", "visual_parts": [ { "raw": "000111", "clean": "000111", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest (Scalar)" }, { "name": "vs2", "desc": "Src Vector" }, { "name": "vs1", "desc": "Start Scalar" } ], "pseudocode": "vd[0] = max(vs1[0], max_element(vs2));", "description": "Performs a vector reduction: applies the operation across all active elements of vs2, using vs1[0] as the initial accumulator, and writes the scalar result to vd[0]. Active elements are determined by vl.", "example": "VREDMAX.VS v1, v4, v2, v0.t" }, { "mnemonic": "VREDMIN.VS", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Reduction Minimum (Signed)", "summary": "Reduces a vector to a scalar by finding the minimum signed element.", "syntax": "VREDMIN.VS vd, vs2, vs1, vm", "encoding": { "format": "OPMVV", "binary_pattern": "000101 | vm | vs2 | vs1 | 010 | vd | 1010111", "hex_opcode": "0x14002057", "visual_parts": [ { "raw": "000101", "clean": "000101", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest (Scalar)" }, { "name": "vs2", "desc": "Src Vector" }, { "name": "vs1", "desc": "Start Scalar" } ], "pseudocode": "vd[0] = min(vs1[0], min_element(vs2));", "description": "Performs a vector reduction: applies the operation across all active elements of vs2, using vs1[0] as the initial accumulator, and writes the scalar result to vd[0]. Active elements are determined by vl.", "example": "VREDMIN.VS v1, v4, v2, v0.t" }, { "mnemonic": "VREDAND.VS", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Reduction AND", "summary": "Reduces a vector to a scalar using bitwise AND.", "syntax": "VREDAND.VS vd, vs2, vs1, vm", "encoding": { "format": "OPMVV", "binary_pattern": "000001 | vm | vs2 | vs1 | 010 | vd | 1010111", "hex_opcode": "0x04002057", "visual_parts": [ { "raw": "000001", "clean": "000001", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest (Scalar)" }, { "name": "vs2", "desc": "Src Vector" }, { "name": "vs1", "desc": "Start Scalar" } ], "pseudocode": "vd[0] = vs1[0] & reduce_and(vs2);", "description": "Performs a vector reduction: applies the operation across all active elements of vs2, using vs1[0] as the initial accumulator, and writes the scalar result to vd[0]. Active elements are determined by vl.", "example": "VREDAND.VS v1, v4, v2, v0.t" }, { "mnemonic": "VREDOR.VS", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Reduction OR", "summary": "Reduces a vector to a scalar using bitwise OR.", "syntax": "VREDOR.VS vd, vs2, vs1, vm", "encoding": { "format": "OPMVV", "binary_pattern": "000010 | vm | vs2 | vs1 | 010 | vd | 1010111", "hex_opcode": "0x08002057", "visual_parts": [ { "raw": "000010", "clean": "000010", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest (Scalar)" }, { "name": "vs2", "desc": "Src Vector" }, { "name": "vs1", "desc": "Start Scalar" } ], "pseudocode": "vd[0] = vs1[0] | reduce_or(vs2);", "description": "Performs a vector reduction: applies the operation across all active elements of vs2, using vs1[0] as the initial accumulator, and writes the scalar result to vd[0]. Active elements are determined by vl.", "example": "VREDOR.VS v1, v4, v2, v0.t" }, { "mnemonic": "VFWADD.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Widening Float Add", "summary": "Adds N-bit floats to produce 2*N-bit float results (e.g., FP16 + FP16 -> FP32).", "syntax": "VFWADD.VV vd, vs2, vs1, vm", "encoding": { "format": "OPFVV", "binary_pattern": "110000 | vm | vs2 | vs1 | 001 | vd | 1010111", "hex_opcode": "0xC0001057", "visual_parts": [ { "raw": "110000", "clean": "110000", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest (2*SEW)" }, { "name": "vs2", "desc": "Src 2 (SEW)" }, { "name": "vs1", "desc": "Src 1 (SEW)" } ], "pseudocode": "foreach(i < vl): vd[i] = extend(vs1[i]) + extend(vs2[i]);", "description": "Performs a widening operation, producing results twice as wide as the source elements. Results are written to vd using 2× the element grouping (EEW). The number of elements and masking are governed by vl and vm.", "example": "VFWADD.VV v1, v4, v2, v0.t" }, { "mnemonic": "VFWMUL.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Widening Float Multiply", "summary": "Multiplies N-bit floats to produce 2*N-bit float results.", "syntax": "VFWMUL.VV vd, vs2, vs1, vm", "encoding": { "format": "OPFVV", "binary_pattern": "111000 | vm | vs2 | vs1 | 001 | vd | 1010111", "hex_opcode": "0xE0001057", "visual_parts": [ { "raw": "111000", "clean": "111000", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest (2*SEW)" }, { "name": "vs2", "desc": "Src 2 (SEW)" }, { "name": "vs1", "desc": "Src 1 (SEW)" } ], "pseudocode": "foreach(i < vl): vd[i] = extend(vs1[i]) * extend(vs2[i]);", "description": "Performs a widening operation, producing results twice as wide as the source elements. Results are written to vd using 2× the element grouping (EEW). The number of elements and masking are governed by vl and vm.", "example": "VFWMUL.VV v1, v4, v2, v0.t" }, { "mnemonic": "VFREDUSUM.VS", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Unordered Float Reduction Sum", "summary": "Reduces a float vector to a scalar by summing elements (Order not preserved, faster).", "syntax": "VFREDUSUM.VS vd, vs2, vs1, vm", "encoding": { "format": "OPFVV", "binary_pattern": "000001 | vm | vs2 | vs1 | 001 | vd | 1010111", "hex_opcode": "0x04001057", "visual_parts": [ { "raw": "000001", "clean": "000001", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest (Scalar)" }, { "name": "vs2", "desc": "Src Vector" }, { "name": "vs1", "desc": "Start Scalar" } ], "pseudocode": "vd[0] = vs1[0] + sum(vs2[*]); // Non-deterministic order", "description": "Performs a vector reduction: applies the operation across all active elements of vs2, using vs1[0] as the initial accumulator, and writes the scalar result to vd[0]. Active elements are determined by vl.", "example": "VFREDUSUM.VS v1, v4, v2, v0.t" }, { "mnemonic": "VFREDMAX.VS", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Float Reduction Maximum", "summary": "Reduces a float vector to a scalar by finding the maximum element.", "syntax": "VFREDMAX.VS vd, vs2, vs1, vm", "encoding": { "format": "OPFVV", "binary_pattern": "000111 | vm | vs2 | vs1 | 001 | vd | 1010111", "hex_opcode": "0x1C001057", "visual_parts": [ { "raw": "000111", "clean": "000111", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest (Scalar)" }, { "name": "vs2", "desc": "Src Vector" }, { "name": "vs1", "desc": "Start Scalar" } ], "pseudocode": "vd[0] = max(vs1[0], max_element(vs2));", "description": "Performs a vector reduction: applies the operation across all active elements of vs2, using vs1[0] as the initial accumulator, and writes the scalar result to vd[0]. Active elements are determined by vl.", "example": "VFREDMAX.VS v1, v4, v2, v0.t" }, { "mnemonic": "VMSBC.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Mask Set Before First", "summary": "Writes a mask where bits are 1 before the first element in vs2 that is 1.", "syntax": "VMSBC.VV vd, vs2, vs1", "encoding": { "format": "OPMVV", "binary_pattern": "0100111 | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0x4E000057", "visual_parts": [ { "raw": "0100111", "clean": "0100111", "pos": "31:25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest Mask" }, { "name": "vs2", "desc": "Src Mask" } ], "pseudocode": "Sets mask bits to 1 up to (but not including) the first set bit in vs2.", "description": "Vector Mask Set Before First: Writes a mask where bits are 1 before the first element in vs2 that is 1. Operation: Sets mask bits to 1 up to (but not including) the first set bit in vs2..", "example": "VMSBC.VV v1, v4, v2" }, { "mnemonic": "CZERO.EQZ", "architecture": "RISC-V", "extension": "Zicond", "full_name": "Conditional Zero Equal to Zero", "summary": "Moves rs1 to rd if rs2 is non-zero, otherwise sets rd to zero.", "syntax": "CZERO.EQZ rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000111 | rs2 | rs1 | 101 | rd | 0110011", "hex_opcode": "0x0E005033", "visual_parts": [ { "raw": "0000111", "clean": "0000111", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "101", "clean": "101", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source" }, { "name": "rs2", "desc": "Condition" } ], "pseudocode": "if (R[rs2] == 0) R[rd] = 0; else R[rd] = R[rs1];", "example": "CZERO.EQZ x10, x11, x12", "example_note": "If x12 is 0, x10=0. Else x10=x11.", "description": "CZERO.EQZ conditionally zeroes rd: it writes zero to rd if rs2 equals zero, otherwise writes the value of rs1 to rd. Useful for branch-free conditional selection." }, { "mnemonic": "CZERO.NEZ", "architecture": "RISC-V", "extension": "Zicond", "full_name": "Conditional Zero Not Equal to Zero", "summary": "Moves rs1 to rd if rs2 is zero, otherwise sets rd to zero.", "syntax": "CZERO.NEZ rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000111 | rs2 | rs1 | 111 | rd | 0110011", "hex_opcode": "0x0E007033", "visual_parts": [ { "raw": "0000111", "clean": "0000111", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "111", "clean": "111", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source" }, { "name": "rs2", "desc": "Condition" } ], "pseudocode": "if (R[rs2] != 0) R[rd] = 0; else R[rd] = R[rs1];", "example": "CZERO.NEZ x10, x11, x12", "example_note": "If x12 != 0, x10=0. Else x10=x11.", "description": "CZERO.NEZ conditionally zeroes rd: it writes zero to rd if rs2 is non-zero, otherwise writes rs1 to rd. Useful for branch-free conditional selection." }, { "mnemonic": "PAUSE", "architecture": "RISC-V", "extension": "Zihintpause", "full_name": "Pause", "summary": "Hints that the current hart is in a spin-wait loop, allowing the hardware to reduce power consumption or yield resources.", "syntax": "PAUSE", "encoding": { "format": "I-Type (Hint)", "binary_pattern": "00000001000000000000000000001111", "hex_opcode": "0x0100000F", "visual_parts": [ { "raw": "00000001000000000000000000001111", "clean": "00000001000000000000000000001111", "pos": "31:0" } ], "bit_positions": "31:0" }, "operands": [], "pseudocode": "// Implementation-defined delay/yield", "example": "PAUSE", "example_note": "Used inside spinlocks.", "description": "PAUSE is a hint instruction that may stall the pipeline for an implementation-defined short period. It is intended to reduce energy consumption in spin-wait loops." }, { "mnemonic": "CBO.CLEAN", "architecture": "RISC-V", "extension": "Zicbom", "full_name": "Cache Block Operation: Clean", "summary": "Performs a clean operation on the cache block containing the effective address.", "syntax": "CBO.CLEAN (rs1)", "encoding": { "format": "I-Type", "binary_pattern": "000000000001 | rs1 | 010000000001111", "hex_opcode": "0x0010200F", "visual_parts": [ { "raw": "000000000001", "clean": "000000000001", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "010000000001111", "clean": "010000000001111", "pos": "14:0" } ], "bit_positions": "31:20 | 19:15 | 14:0" }, "operands": [ { "name": "rs1", "desc": "Address" } ], "pseudocode": "CacheClean(R[rs1]);", "example": "CBO.CLEAN (x10)", "example_note": "Write back dirty data to memory.", "description": "CBO.CLEAN performs a clean operation on a cache block containing the effective address computed from rs1. It writes back the contents of the cache block to memory if dirty, but retains the block in the cache." }, { "mnemonic": "CBO.FLUSH", "architecture": "RISC-V", "extension": "Zicbom", "full_name": "Cache Block Operation: Flush", "summary": "Performs a flush (clean + invalidate) operation on the cache block.", "syntax": "CBO.FLUSH (rs1)", "encoding": { "format": "I-Type", "binary_pattern": "000000000010 | rs1 | 010000000001111", "hex_opcode": "0x0020200F", "visual_parts": [ { "raw": "000000000010", "clean": "000000000010", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "010000000001111", "clean": "010000000001111", "pos": "14:0" } ], "bit_positions": "31:20 | 19:15 | 14:0" }, "operands": [ { "name": "rs1", "desc": "Address" } ], "pseudocode": "CacheFlush(R[rs1]);", "example": "CBO.FLUSH (x10)", "example_note": "Write back and invalidate.", "description": "CBO.FLUSH cleans and then invalidates the cache block containing the effective address. The block's contents are written back to memory if dirty, then the block is evicted from the cache." }, { "mnemonic": "CBO.INVAL", "architecture": "RISC-V", "extension": "Zicbom", "full_name": "Cache Block Operation: Invalidate", "summary": "Performs an invalidate operation on the cache block.", "syntax": "CBO.INVAL (rs1)", "encoding": { "format": "I-Type", "binary_pattern": "000000000000 | rs1 | 010000000001111", "hex_opcode": "0x0000200F", "visual_parts": [ { "raw": "000000000000", "clean": "000000000000", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "010000000001111", "clean": "010000000001111", "pos": "14:0" } ], "bit_positions": "31:20 | 19:15 | 14:0" }, "operands": [ { "name": "rs1", "desc": "Address" } ], "pseudocode": "CacheInvalidate(R[rs1]);", "example": "CBO.INVAL (x10)", "example_note": "Discard cache line (data lost if dirty).", "description": "CBO.INVAL invalidates the cache block containing the effective address, removing it from the cache without writing back dirty data. This is a hint; the implementation may write back dirty data." }, { "mnemonic": "RDCYCLE", "architecture": "RISC-V", "extension": "Pseudo", "full_name": "Read Cycle Counter", "summary": "Reads the lower 32/64 bits of the cycle counter.", "syntax": "RDCYCLE rd", "encoding": { "format": "I-Type", "binary_pattern": "11000000000000000010 | rd | 1110011", "hex_opcode": "0xC0002073", "visual_parts": [ { "raw": "11000000000000000010", "clean": "11000000000000000010", "pos": "31:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1110011", "clean": "1110011", "pos": "6:0" } ], "bit_positions": "31:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" } ], "pseudocode": "R[rd] = CSR[cycle];", "example": "RDCYCLE x10", "example_note": "Get cycle count for performance timing.", "description": "RDCYCLE reads the cycle CSR, which counts the number of clock cycles executed by the processor. It is an assembler pseudoinstruction for CSRRS rd, cycle, x0." }, { "mnemonic": "RDTIME", "architecture": "RISC-V", "extension": "Pseudo", "full_name": "Read Real-Time Clock", "summary": "Reads the lower 32/64 bits of the real-time clock.", "syntax": "RDTIME rd", "encoding": { "format": "I-Type", "binary_pattern": "11000000000100000010 | rd | 1110011", "hex_opcode": "0xC0102073", "visual_parts": [ { "raw": "11000000000100000010", "clean": "11000000000100000010", "pos": "31:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1110011", "clean": "1110011", "pos": "6:0" } ], "bit_positions": "31:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" } ], "pseudocode": "R[rd] = CSR[time];", "example": "RDTIME x10", "example_note": "Get wall-clock time.", "description": "RDTIME reads the time CSR, which reflects the current value of the real-time counter. It is an assembler pseudoinstruction for CSRRS rd, time, x0." }, { "mnemonic": "RDINSTRET", "architecture": "RISC-V", "extension": "Pseudo", "full_name": "Read Instructions Retired", "summary": "Reads the count of instructions retired (completed).", "syntax": "RDINSTRET rd", "encoding": { "format": "I-Type", "binary_pattern": "11000000001000000010 | rd | 1110011", "hex_opcode": "0xC0202073", "visual_parts": [ { "raw": "11000000001000000010", "clean": "11000000001000000010", "pos": "31:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1110011", "clean": "1110011", "pos": "6:0" } ], "bit_positions": "31:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" } ], "pseudocode": "R[rd] = CSR[instret];", "example": "RDINSTRET x10", "example_note": "Get instruction count.", "description": "RDINSTRET reads the instret CSR, which counts the number of instructions retired by the processor. It is an assembler pseudoinstruction for CSRRS rd, instret, x0." }, { "mnemonic": "NOP", "architecture": "RISC-V", "extension": "Pseudo", "full_name": "No Operation", "summary": "Performs no operation. Used for alignment or timing delays.", "syntax": "NOP", "encoding": { "format": "I-Type", "binary_pattern": "00000000000000000000000000010011", "hex_opcode": "0x00000013", "visual_parts": [ { "raw": "00000000000000000000000000010011", "clean": "00000000000000000000000000010011", "pos": "31:0" } ], "bit_positions": "31:0" }, "operands": [], "pseudocode": "R[0] = R[0] + 0;", "example": "NOP", "example_note": "Does nothing.", "description": "NOP does not change any architecturally visible state except advancing the PC. It is canonically encoded as ADDI x0, x0, 0." }, { "mnemonic": "MV", "architecture": "RISC-V", "extension": "Pseudo", "full_name": "Move", "summary": "Copies the value of one register into another.", "syntax": "MV rd, rs", "encoding": { "format": "I-Type", "binary_pattern": "000000000000 | rs1 | 000 | rd | 0010011", "hex_opcode": "0x00000013", "visual_parts": [ { "raw": "000000000000", "clean": "000000000000", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0010011", "clean": "0010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs", "desc": "Source" } ], "pseudocode": "R[rd] = R[rs];", "example": "MV x10, x11", "example_note": "Copies x11 to x10.", "description": "MV copies the value of rs1 into rd. It is an assembler pseudoinstruction for ADDI rd, rs1, 0." }, { "mnemonic": "LI", "architecture": "RISC-V", "extension": "Pseudo", "full_name": "Load Immediate", "summary": "Loads an arbitrary immediate value into a register.", "syntax": "LI rd, imm", "encoding": { "format": "U-Type", "binary_pattern": "imm[31:12] | rd | 0110111", "hex_opcode": "0x00000013", "visual_parts": [ { "raw": "imm[31:12]", "clean": "imm", "pos": "31:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110111", "clean": "0110111", "pos": "6:0" } ], "bit_positions": "31:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "imm", "desc": "Immediate Value" } ], "pseudocode": "R[rd] = imm;", "example": "LI x5, 0x12345", "example_note": "Expands to: LUI x5, 0x12; ADDI x5, x5, 0x345", "description": "LI loads an arbitrary immediate value into rd using one or two instructions (LUI+ADDI for 32-bit, or longer for 64-bit). It is an assembler pseudoinstruction." }, { "mnemonic": "RET", "architecture": "RISC-V", "extension": "Pseudo", "full_name": "Return", "summary": "Returns from a subroutine call.", "syntax": "RET", "encoding": { "format": "I-Type", "binary_pattern": "00000000000000001000000001100111", "hex_opcode": "0x00008067", "visual_parts": [ { "raw": "00000000000000001000000001100111", "clean": "00000000000000001000000001100111", "pos": "31:0" } ], "bit_positions": "31:0" }, "operands": [], "pseudocode": "PC = R[1];", "example": "RET", "example_note": "Jumps to the address in the Return Address register (ra/x1).", "description": "RET returns from a subroutine by jumping to the address in x1 (ra). It is a pseudoinstruction for JALR x0, 0(x1)." }, { "mnemonic": "J", "architecture": "RISC-V", "extension": "Pseudo", "full_name": "Jump", "summary": "Unconditionally jumps to a target offset.", "syntax": "J offset", "encoding": { "format": "J-Type", "binary_pattern": "jimm20 | 000001101111", "hex_opcode": "0x0000006F", "visual_parts": [ { "raw": "jimm20", "clean": "jimm20", "pos": "31:12" }, { "raw": "000001101111", "clean": "000001101111", "pos": "11:0" } ], "bit_positions": "31:12 | 11:0" }, "operands": [ { "name": "offset", "desc": "Jump Target" } ], "pseudocode": "PC += sext(offset);", "example": "J label", "example_note": "Unconditional jump (discarding return address).", "description": "J performs an unconditional jump to a PC-relative offset. It is a pseudoinstruction for JAL x0, offset." }, { "mnemonic": "JR", "architecture": "RISC-V", "extension": "Pseudo", "full_name": "Jump Register", "summary": "Unconditionally jumps to an address held in a register.", "syntax": "JR rs", "encoding": { "format": "I-Type", "binary_pattern": "000000000000 | rs1 | 000000001100111", "hex_opcode": "0x00000067", "visual_parts": [ { "raw": "000000000000", "clean": "000000000000", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000000001100111", "clean": "000000001100111", "pos": "14:0" } ], "bit_positions": "31:20 | 19:15 | 14:0" }, "operands": [ { "name": "rs", "desc": "Address Register" } ], "pseudocode": "PC = R[rs];", "example": "JR x10", "example_note": "Jump to address stored in x10.", "description": "JR performs an unconditional indirect jump to the address in rs1. It is a pseudoinstruction for JALR x0, 0(rs1)." }, { "mnemonic": "CALL", "architecture": "RISC-V", "extension": "Pseudo", "full_name": "Call Subroutine", "summary": "Calls a function by jumping to an address and saving the return address.", "syntax": "CALL symbol", "encoding": { "format": "Pseudo", "binary_pattern": "AUIPC + JALR", "hex_opcode": "0x00000017", "visual_parts": [ { "raw": "AUIPC + JALR", "clean": "AUIPC + JALR" } ] }, "operands": [ { "name": "symbol", "desc": "Function Name" } ], "pseudocode": "x1 = PC + 4; PC = symbol;", "example": "CALL printf", "example_note": "Sets up x1 (ra) and jumps to printf.", "description": "CALL calls a far subroutine using a two-instruction AUIPC+JALR sequence, saving the return address in x1 (ra)." }, { "mnemonic": "NOT", "architecture": "RISC-V", "extension": "Pseudo", "full_name": "Bitwise NOT", "summary": "Computes the bitwise logical negation (one's complement).", "syntax": "NOT rd, rs", "encoding": { "format": "I-Type", "binary_pattern": "111111111111 | rs1 | 100 | rd | 0010011", "hex_opcode": "0xFFF04013", "visual_parts": [ { "raw": "111111111111", "clean": "111111111111", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "100", "clean": "100", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0010011", "clean": "0010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs", "desc": "Source" } ], "pseudocode": "R[rd] = ~R[rs];", "example": "NOT x10, x11", "example_note": "Inverts all bits of x11.", "description": "NOT performs a bitwise logical NOT of rs1 and writes to rd. It is a pseudoinstruction for XORI rd, rs1, -1." }, { "mnemonic": "NEG", "architecture": "RISC-V", "extension": "Pseudo", "full_name": "Negate", "summary": "Computes the two's complement negation (arithmetic negative).", "syntax": "NEG rd, rs", "encoding": { "format": "R-Type", "binary_pattern": "010000000000 | rs1 | 000 | rd | 0110011", "hex_opcode": "0x40000033", "visual_parts": [ { "raw": "010000000000", "clean": "010000000000", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs", "desc": "Source" } ], "pseudocode": "R[rd] = 0 - R[rs];", "example": "NEG x5, x6", "example_note": "x5 = -x6", "description": "NEG negates rs1 and writes to rd. It is a pseudoinstruction for SUB rd, x0, rs1." }, { "mnemonic": "BEQZ", "architecture": "RISC-V", "extension": "Pseudo", "full_name": "Branch if Equal to Zero", "summary": "Branches if the register is zero.", "syntax": "BEQZ rs, offset", "encoding": { "format": "B-Type", "binary_pattern": "bimm12hi | 00000 | rs1 | 000 | bimm12lo | 1100011", "hex_opcode": "0x00000063", "visual_parts": [ { "raw": "bimm12hi", "clean": "bimm12hi", "pos": "31:25" }, { "raw": "00000", "clean": "00000", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "bimm12lo", "clean": "bimm12lo", "pos": "11:7" }, { "raw": "1100011", "clean": "1100011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rs", "desc": "Source" }, { "name": "offset", "desc": "Label" } ], "pseudocode": "if (R[rs] == 0) PC += offset;", "example": "BEQZ x10, exit", "example_note": "Jump to exit if x10 is zero.", "description": "BEQZ branches to the target if rs1 equals zero. It is a pseudoinstruction for BEQ rs1, x0, offset." }, { "mnemonic": "BNEZ", "architecture": "RISC-V", "extension": "Pseudo", "full_name": "Branch if Not Equal to Zero", "summary": "Branches if the register is not zero.", "syntax": "BNEZ rs, offset", "encoding": { "format": "B-Type", "binary_pattern": "bimm12hi | 00000 | rs1 | 001 | bimm12lo | 1100011", "hex_opcode": "0x00001063", "visual_parts": [ { "raw": "bimm12hi", "clean": "bimm12hi", "pos": "31:25" }, { "raw": "00000", "clean": "00000", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "bimm12lo", "clean": "bimm12lo", "pos": "11:7" }, { "raw": "1100011", "clean": "1100011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rs", "desc": "Source" }, { "name": "offset", "desc": "Label" } ], "pseudocode": "if (R[rs] != 0) PC += offset;", "example": "BNEZ x10, loop", "example_note": "Jump to loop if x10 is not zero.", "description": "BNEZ branches to the target if rs1 is non-zero. It is a pseudoinstruction for BNE rs1, x0, offset." }, { "mnemonic": "SEQZ", "architecture": "RISC-V", "extension": "Pseudo", "full_name": "Set if Equal to Zero", "summary": "Sets rd to 1 if rs is zero, otherwise 0.", "syntax": "SEQZ rd, rs", "encoding": { "format": "I-Type", "binary_pattern": "000000000001 | rs1 | 011 | rd | 0010011", "hex_opcode": "0x00103013", "visual_parts": [ { "raw": "000000000001", "clean": "000000000001", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "011", "clean": "011", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0010011", "clean": "0010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs", "desc": "Source" } ], "pseudocode": "R[rd] = (R[rs] == 0) ? 1 : 0;", "example": "SEQZ x5, x10", "example_note": "Sets x5 to 1 if x10 is 0.", "description": "SEQZ writes 1 to rd if rs1 equals zero, and 0 otherwise. It is a pseudoinstruction for SLTIU rd, rs1, 1." }, { "mnemonic": "SNEZ", "architecture": "RISC-V", "extension": "Pseudo", "full_name": "Set if Not Equal to Zero", "summary": "Sets rd to 1 if rs is not zero, otherwise 0.", "syntax": "SNEZ rd, rs", "encoding": { "format": "R-Type", "binary_pattern": "0000000 | rs2 | 00000011 | rd | 0110011", "hex_opcode": "0x00003033", "visual_parts": [ { "raw": "0000000", "clean": "0000000", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "00000011", "clean": "00000011", "pos": "19:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs", "desc": "Source" } ], "pseudocode": "R[rd] = (R[rs] != 0) ? 1 : 0;", "example": "SNEZ x5, x10", "example_note": "Sets x5 to 1 if x10 is non-zero.", "description": "SNEZ writes 1 to rd if rs1 is non-zero, and 0 otherwise. It is a pseudoinstruction for SLTU rd, x0, rs1." }, { "mnemonic": "AES64ES", "architecture": "RISC-V", "extension": "Zkne", "full_name": "AES-64 Encryption Schedule", "summary": "Performs one round of AES-128 encryption key schedule generation.", "syntax": "AES64ES rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0011001 | rs2 | rs1 | 000 | rd | 0110011", "hex_opcode": "0x32000033", "visual_parts": [ { "raw": "0011001", "clean": "0011001", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" } ], "pseudocode": "R[rd] = aes_encrypt_schedule(R[rs1], R[rs2]);", "example": "AES64ES x10, x11, x12", "example_note": "AES Key Gen.", "description": "AES64ES performs two phases of the AES forward SubBytes and ShiftRows transformation. Used in AES encryption." }, { "mnemonic": "AES64DS", "architecture": "RISC-V", "extension": "Zknd", "full_name": "AES-64 Decryption Schedule", "summary": "Performs one round of AES-128 decryption key schedule generation.", "syntax": "AES64DS rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0011101 | rs2 | rs1 | 000 | rd | 0110011", "hex_opcode": "0x3A000033", "visual_parts": [ { "raw": "0011101", "clean": "0011101", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" } ], "pseudocode": "R[rd] = aes_decrypt_schedule(R[rs1], R[rs2]);", "example": "AES64DS x10, x11, x12", "example_note": "AES Decrypt Key Gen.", "description": "AES64DS performs two phases of the AES block cipher inverse SubBytes and ShiftRows transformation on 64-bit halves of the round state. Used in AES decryption." }, { "mnemonic": "SHA256SIG0", "architecture": "RISC-V", "extension": "Zk", "full_name": "SHA-256 Sigma0", "summary": "Performs the Sigma0 transformation function for SHA-256.", "syntax": "SHA256SIG0 rd, rs1", "encoding": { "format": "I-Type", "binary_pattern": "000100000010 | rs1 | 001 | rd | 0010011", "hex_opcode": "0x10201013", "visual_parts": [ { "raw": "000100000010", "clean": "000100000010", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0010011", "clean": "0010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source" } ], "pseudocode": "R[rd] = ROTR(x, 7) ^ ROTR(x, 18) ^ (x >> 3);", "example": "SHA256SIG0 x10, x11", "example_note": "SHA-256 calculation.", "description": "SHA256SIG0 computes the sigma_0 mixing function for SHA-256, applying a combination of rotate-right and shift operations to rs1." }, { "mnemonic": "SHA256SUM0", "architecture": "RISC-V", "extension": "Zk", "full_name": "SHA-256 Sum0", "summary": "Performs the Sum0 transformation function for SHA-256.", "syntax": "SHA256SUM0 rd, rs1", "encoding": { "format": "I-Type", "binary_pattern": "000100000000 | rs1 | 001 | rd | 0010011", "hex_opcode": "0x10001013", "visual_parts": [ { "raw": "000100000000", "clean": "000100000000", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0010011", "clean": "0010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source" } ], "pseudocode": "R[rd] = ROTR(x, 2) ^ ROTR(x, 13) ^ ROTR(x, 22);", "example": "SHA256SUM0 x10, x11", "example_note": "SHA-256 calculation.", "description": "SHA256SUM0 computes the sum-0 mixing function (Sigma-0 capital) for SHA-256 message scheduling." }, { "mnemonic": "FCVT.WU.S", "architecture": "RISC-V", "extension": "F", "full_name": "Convert Float to Unsigned Word", "summary": "Converts a single-precision float to a 32-bit unsigned integer.", "syntax": "FCVT.WU.S rd, rs1", "encoding": { "format": "I-Type (Float)", "binary_pattern": "110000000001 | rs1 | rm | rd | 1010011", "hex_opcode": "0xC0100053", "visual_parts": [ { "raw": "110000000001", "clean": "110000000001", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (UInt)" }, { "name": "rs1", "desc": "Source (Float)" } ], "pseudocode": "R[rd] = sext(f32_to_u32(F[rs1]));", "example": "FCVT.WU.S x10, f1", "example_note": "Float -> Unsigned Int.", "description": "Converts between floating-point types or between floating-point and integer. Result is rounded according to the dynamic rounding mode. Invalid conversions produce the IEEE default NaN or the appropriate integer saturation value." }, { "mnemonic": "FCVT.S.WU", "architecture": "RISC-V", "extension": "F", "full_name": "Convert Unsigned Word to Float", "summary": "Converts a 32-bit unsigned integer to a single-precision float.", "syntax": "FCVT.S.WU rd, rs1", "encoding": { "format": "I-Type (Float)", "binary_pattern": "110100000001 | rs1 | rm | rd | 1010011", "hex_opcode": "0xD0100053", "visual_parts": [ { "raw": "110100000001", "clean": "110100000001", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Float)" }, { "name": "rs1", "desc": "Source (UInt)" } ], "pseudocode": "F[rd] = u32_to_f32(R[rs1]);", "example": "FCVT.S.WU f1, x10", "example_note": "Unsigned Int -> Float.", "description": "Converts between floating-point types or between floating-point and integer. Result is rounded according to the dynamic rounding mode. Invalid conversions produce the IEEE default NaN or the appropriate integer saturation value." }, { "mnemonic": "FCVT.W.D", "architecture": "RISC-V", "extension": "D", "full_name": "Convert Double to Word", "summary": "Converts a double-precision float to a 32-bit signed integer.", "syntax": "FCVT.W.D rd, rs1", "encoding": { "format": "I-Type (Float)", "binary_pattern": "110000100000 | rs1 | rm | rd | 1010011", "hex_opcode": "0xC2000053", "visual_parts": [ { "raw": "110000100000", "clean": "110000100000", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Int)" }, { "name": "rs1", "desc": "Source (Double)" } ], "pseudocode": "R[rd] = sext(f64_to_i32(F[rs1]));", "example": "FCVT.W.D x10, f0", "example_note": "Double -> Int.", "description": "Converts between floating-point types or between floating-point and integer. Result is rounded according to the dynamic rounding mode. Invalid conversions produce the IEEE default NaN or the appropriate integer saturation value." }, { "mnemonic": "FCVT.D.W", "architecture": "RISC-V", "extension": "D", "full_name": "Convert Word to Double", "summary": "Converts a 32-bit signed integer to a double-precision float.", "syntax": "FCVT.D.W rd, rs1", "encoding": { "format": "I-Type (Float)", "binary_pattern": "110100100000 | rs1 | rm | rd | 1010011", "hex_opcode": "0xD2000053", "visual_parts": [ { "raw": "110100100000", "clean": "110100100000", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Double)" }, { "name": "rs1", "desc": "Source (Int)" } ], "pseudocode": "F[rd] = i32_to_f64(R[rs1]);", "example": "FCVT.D.W f0, x10", "example_note": "Int -> Double.", "description": "Converts between floating-point types or between floating-point and integer. Result is rounded according to the dynamic rounding mode. Invalid conversions produce the IEEE default NaN or the appropriate integer saturation value." }, { "mnemonic": "SH1ADD", "architecture": "RISC-V", "extension": "Zba", "full_name": "Shift Left 1 and Add", "summary": "Shifts rs1 left by 1 and adds rs2. Used for calculating addresses of 16-bit elements.", "syntax": "SH1ADD rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0010000 | rs2 | rs1 | 010 | rd | 0110011", "hex_opcode": "0x20002033", "visual_parts": [ { "raw": "0010000", "clean": "0010000", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Index" }, { "name": "rs2", "desc": "Base" } ], "pseudocode": "R[rd] = R[rs2] + (R[rs1] << 1);", "example": "SH1ADD x10, x11, x12", "example_note": "Calculate address: x12 + (x11 * 2).", "description": "SH1ADD shifts rs1 left by 1 bit, then adds the result to rs2, writing to rd. Used for stride-1 array indexing (byte element + base)." }, { "mnemonic": "SH2ADD", "architecture": "RISC-V", "extension": "Zba", "full_name": "Shift Left 2 and Add", "summary": "Shifts rs1 left by 2 and adds rs2. Used for calculating addresses of 32-bit elements.", "syntax": "SH2ADD rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0010000 | rs2 | rs1 | 100 | rd | 0110011", "hex_opcode": "0x20004033", "visual_parts": [ { "raw": "0010000", "clean": "0010000", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "100", "clean": "100", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Index" }, { "name": "rs2", "desc": "Base" } ], "pseudocode": "R[rd] = R[rs2] + (R[rs1] << 2);", "example": "SH2ADD x10, x11, x12", "example_note": "Calculate address: x12 + (x11 * 4).", "description": "SH2ADD shifts rs1 left by 2 bits, then adds to rs2, writing to rd. Used for stride-4 array indexing (e.g., int32 arrays)." }, { "mnemonic": "SH3ADD", "architecture": "RISC-V", "extension": "Zba", "full_name": "Shift Left 3 and Add", "summary": "Shifts rs1 left by 3 and adds rs2. Used for calculating addresses of 64-bit elements.", "syntax": "SH3ADD rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0010000 | rs2 | rs1 | 110 | rd | 0110011", "hex_opcode": "0x20006033", "visual_parts": [ { "raw": "0010000", "clean": "0010000", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "110", "clean": "110", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Index" }, { "name": "rs2", "desc": "Base" } ], "pseudocode": "R[rd] = R[rs2] + (R[rs1] << 3);", "example": "SH3ADD x10, x11, x12", "example_note": "Calculate address: x12 + (x11 * 8).", "description": "SH3ADD shifts rs1 left by 3 bits, then adds to rs2, writing to rd. Used for stride-8 array indexing (e.g., int64 arrays)." }, { "mnemonic": "ADD.UW", "architecture": "RISC-V", "extension": "Zba", "full_name": "Add Unsigned Word", "summary": "Zero-extends the lower 32 bits of rs1 and adds it to rs2. Useful for 64-bit address calculations with 32-bit unsigned indices.", "syntax": "ADD.UW rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000100 | rs2 | rs1 | 000 | rd | 0111011", "hex_opcode": "0x0800003B", "visual_parts": [ { "raw": "0000100", "clean": "0000100", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0111011", "clean": "0111011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Index (32-bit)" }, { "name": "rs2", "desc": "Base" } ], "pseudocode": "R[rd] = R[rs2] + zext(R[rs1][31:0]);", "example": "ADD.UW x10, x11, x12", "example_note": "x10 = x12 + (uint32_t)x11", "description": "ADD.UW zero-extends the lower 32 bits of rs1 to XLEN bits, adds the result to rs2, and writes to rd. Used for pointer arithmetic with zero-extended 32-bit offsets." }, { "mnemonic": "BSET", "architecture": "RISC-V", "extension": "Zbs", "full_name": "Bit Set", "summary": "Sets a single bit in rs1 at the index specified by rs2.", "syntax": "BSET rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0010100 | rs2 | rs1 | 001 | rd | 0110011", "hex_opcode": "0x28001033", "visual_parts": [ { "raw": "0010100", "clean": "0010100", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source" }, { "name": "rs2", "desc": "Index" } ], "pseudocode": "R[rd] = R[rs1] | (1 << (R[rs2] & (XLEN-1)));", "example": "BSET x10, x11, x12", "example_note": "Set the bit at index x12 in x11.", "description": "BSET sets the single bit of rs1 selected by the lower log2(XLEN) bits of rs2, writing the result to rd." }, { "mnemonic": "BSETI", "architecture": "RISC-V", "extension": "Zbs", "full_name": "Bit Set Immediate", "summary": "Sets a single bit in rs1 at the index specified by an immediate.", "syntax": "BSETI rd, rs1, imm", "encoding": { "format": "I-Type", "binary_pattern": "001010 | shamtd | rs1 | 001 | rd | 0010011", "hex_opcode": "0x28001013", "visual_parts": [ { "raw": "001010", "clean": "001010", "pos": "31:26" }, { "raw": "shamtd", "clean": "shamtd", "pos": "25:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0010011", "clean": "0010011", "pos": "6:0" } ], "bit_positions": "31:26 | 25:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source" }, { "name": "imm", "desc": "Index" } ], "pseudocode": "R[rd] = R[rs1] | (1 << imm);", "example": "BSETI x10, x11, 5", "example_note": "Set bit 5.", "description": "BSETI sets the single bit of rs1 selected by the immediate, writing the result to rd." }, { "mnemonic": "BCLR", "architecture": "RISC-V", "extension": "Zbs", "full_name": "Bit Clear", "summary": "Clears a single bit in rs1 at the index specified by rs2.", "syntax": "BCLR rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0100100 | rs2 | rs1 | 001 | rd | 0110011", "hex_opcode": "0x48001033", "visual_parts": [ { "raw": "0100100", "clean": "0100100", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source" }, { "name": "rs2", "desc": "Index" } ], "pseudocode": "R[rd] = R[rs1] & ~(1 << (R[rs2] & (XLEN-1)));", "example": "BCLR x10, x11, x12", "example_note": "Clear the bit at index x12.", "description": "BCLR clears the single bit of rs1 selected by the lower log2(XLEN) bits of rs2, writing the result to rd." }, { "mnemonic": "BCLRI", "architecture": "RISC-V", "extension": "Zbs", "full_name": "Bit Clear Immediate", "summary": "Clears a single bit in rs1 at the index specified by an immediate.", "syntax": "BCLRI rd, rs1, imm", "encoding": { "format": "I-Type", "binary_pattern": "010010 | shamtd | rs1 | 001 | rd | 0010011", "hex_opcode": "0x48001013", "visual_parts": [ { "raw": "010010", "clean": "010010", "pos": "31:26" }, { "raw": "shamtd", "clean": "shamtd", "pos": "25:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0010011", "clean": "0010011", "pos": "6:0" } ], "bit_positions": "31:26 | 25:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source" }, { "name": "imm", "desc": "Index" } ], "pseudocode": "R[rd] = R[rs1] & ~(1 << imm);", "example": "BCLRI x10, x11, 3", "example_note": "Clear bit 3.", "description": "BCLRI clears the single bit of rs1 selected by the immediate, writing the result to rd." }, { "mnemonic": "BINV", "architecture": "RISC-V", "extension": "Zbs", "full_name": "Bit Invert", "summary": "Inverts (toggles) a single bit in rs1 at the index specified by rs2.", "syntax": "BINV rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0110100 | rs2 | rs1 | 001 | rd | 0110011", "hex_opcode": "0x68001033", "visual_parts": [ { "raw": "0110100", "clean": "0110100", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source" }, { "name": "rs2", "desc": "Index" } ], "pseudocode": "R[rd] = R[rs1] ^ (1 << (R[rs2] & (XLEN-1)));", "example": "BINV x10, x11, x12", "example_note": "Toggle the bit at index x12.", "description": "BINV inverts the single bit of rs1 selected by the lower log2(XLEN) bits of rs2, writing the result to rd." }, { "mnemonic": "BINVI", "architecture": "RISC-V", "extension": "Zbs", "full_name": "Bit Invert Immediate", "summary": "Inverts (toggles) a single bit in rs1 at the index specified by an immediate.", "syntax": "BINVI rd, rs1, imm", "encoding": { "format": "I-Type", "binary_pattern": "011010 | shamtd | rs1 | 001 | rd | 0010011", "hex_opcode": "0x68001013", "visual_parts": [ { "raw": "011010", "clean": "011010", "pos": "31:26" }, { "raw": "shamtd", "clean": "shamtd", "pos": "25:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0010011", "clean": "0010011", "pos": "6:0" } ], "bit_positions": "31:26 | 25:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source" }, { "name": "imm", "desc": "Index" } ], "pseudocode": "R[rd] = R[rs1] ^ (1 << imm);", "example": "BINVI x10, x11, 7", "example_note": "Toggle bit 7.", "description": "BINVI inverts the single bit of rs1 selected by the immediate, writing the result to rd." }, { "mnemonic": "BEXT", "architecture": "RISC-V", "extension": "Zbs", "full_name": "Bit Extract", "summary": "Extracts the value of a single bit (0 or 1) at the index specified by rs2. The result is placed in the LSB of rd.", "syntax": "BEXT rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0100100 | rs2 | rs1 | 101 | rd | 0110011", "hex_opcode": "0x48005033", "visual_parts": [ { "raw": "0100100", "clean": "0100100", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "101", "clean": "101", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (0 or 1)" }, { "name": "rs1", "desc": "Source" }, { "name": "rs2", "desc": "Index" } ], "pseudocode": "R[rd] = (R[rs1] >> (R[rs2] & (XLEN-1))) & 1;", "example": "BEXT x10, x11, x12", "example_note": "x10 = (x11 >> x12) & 1", "description": "BEXT extracts the single bit of rs1 selected by the lower log2(XLEN) bits of rs2, zero-extending to XLEN and writing to rd." }, { "mnemonic": "BEXTI", "architecture": "RISC-V", "extension": "Zbs", "full_name": "Bit Extract Immediate", "summary": "Extracts the value of a single bit (0 or 1) at the index specified by an immediate.", "syntax": "BEXTI rd, rs1, imm", "encoding": { "format": "I-Type", "binary_pattern": "010010 | shamtd | rs1 | 101 | rd | 0010011", "hex_opcode": "0x48005013", "visual_parts": [ { "raw": "010010", "clean": "010010", "pos": "31:26" }, { "raw": "shamtd", "clean": "shamtd", "pos": "25:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "101", "clean": "101", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0010011", "clean": "0010011", "pos": "6:0" } ], "bit_positions": "31:26 | 25:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (0 or 1)" }, { "name": "rs1", "desc": "Source" }, { "name": "imm", "desc": "Index" } ], "pseudocode": "R[rd] = (R[rs1] >> imm) & 1;", "example": "BEXTI x10, x11, 31", "example_note": "Get sign bit (bit 31) of x11.", "description": "BEXTI extracts the single bit of rs1 selected by the immediate, zero-extending to XLEN and writing to rd." }, { "mnemonic": "CLMUL", "architecture": "RISC-V", "extension": "Zbc", "full_name": "Carry-less Multiply", "summary": "Performs carry-less multiplication of the lower bits of rs1 and rs2. Used for CRC and GCM (crypto).", "syntax": "CLMUL rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000101 | rs2 | rs1 | 001 | rd | 0110011", "hex_opcode": "0x0A001033", "visual_parts": [ { "raw": "0000101", "clean": "0000101", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" } ], "pseudocode": "R[rd] = clmul(R[rs1], R[rs2]);", "example": "CLMUL x10, x11, x12", "example_note": "Carry-less multiply (GF(2^n)).", "description": "CLMUL performs carry-less multiplication of rs1 and rs2, writing the lower XLEN bits of the carry-less product to rd. Used in GF(2^n) arithmetic and CRC computation." }, { "mnemonic": "VSADDU.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Saturating Integer Add Unsigned", "summary": "Adds unsigned integers with saturation (clips to max instead of wrapping).", "syntax": "VSADDU.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "100000 | vm | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0x80000057", "visual_parts": [ { "raw": "100000", "clean": "100000", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = saturate_u(vs1[i] + vs2[i]);", "description": "Performs element-wise unsigned saturating add on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VSADDU.VV v1, v4, v2, v0.t" }, { "mnemonic": "VSSUBU.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Saturating Integer Subtract Unsigned", "summary": "Subtracts unsigned integers with saturation (clips to 0 instead of wrapping).", "syntax": "VSSUBU.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "100010 | vm | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0x88000057", "visual_parts": [ { "raw": "100010", "clean": "100010", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = saturate_u(vs1[i] - vs2[i]);", "description": "Performs element-wise unsigned saturating subtract on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VSSUBU.VV v1, v4, v2, v0.t" }, { "mnemonic": "VAADDU.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Averaging Add Unsigned", "summary": "Computes (a + b + 1) >> 1 for unsigned integers.", "syntax": "VAADDU.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "001000 | vm | vs2 | vs1 | 010 | vd | 1010111", "hex_opcode": "0x20002057", "visual_parts": [ { "raw": "001000", "clean": "001000", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = (vs1[i] + vs2[i] + 1) >> 1;", "description": "Vector Averaging Add Unsigned: Computes (a + b + 1) >> 1 for unsigned integers. Operation: foreach(i < vl): vd[i] = (vs1[i] + vs2[i] + 1) >> 1;.", "example": "VAADDU.VV v1, v4, v2, v0.t" }, { "mnemonic": "VASUB.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Averaging Subtract Signed", "summary": "Computes (a - b) >> 1 for signed integers.", "syntax": "VASUB.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "001011 | vm | vs2 | vs1 | 010 | vd | 1010111", "hex_opcode": "0x2C002057", "visual_parts": [ { "raw": "001011", "clean": "001011", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = (vs1[i] - vs2[i]) >> 1;", "description": "Vector Averaging Subtract Signed: Computes (a - b) >> 1 for signed integers. Operation: foreach(i < vl): vd[i] = (vs1[i] - vs2[i]) >> 1;.", "example": "VASUB.VV v1, v4, v2, v0.t" }, { "mnemonic": "VASUBU.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Averaging Subtract Unsigned", "summary": "Computes (a - b) >> 1 for unsigned integers.", "syntax": "VASUBU.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "001010 | vm | vs2 | vs1 | 010 | vd | 1010111", "hex_opcode": "0x28002057", "visual_parts": [ { "raw": "001010", "clean": "001010", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = (vs1[i] - vs2[i]) >> 1;", "description": "Vector Averaging Subtract Unsigned: Computes (a - b) >> 1 for unsigned integers. Operation: foreach(i < vl): vd[i] = (vs1[i] - vs2[i]) >> 1;.", "example": "VASUBU.VV v1, v4, v2, v0.t" }, { "mnemonic": "VSSRA.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Saturating Shift Right Arithmetic", "summary": "Shifts right with sign extension and rounding/saturation logic.", "syntax": "VSSRA.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "101011 | vm | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0xAC000057", "visual_parts": [ { "raw": "101011", "clean": "101011", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = saturate(vs2[i] >>s vs1[i]);", "description": "Vector Saturating Shift Right Arithmetic: Shifts right with sign extension and rounding/saturation logic. Operation: foreach(i < vl): vd[i] = saturate(vs2[i] >>s vs1[i]);.", "example": "VSSRA.VV v1, v4, v2, v0.t" }, { "mnemonic": "VSSRL.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Saturating Shift Right Logical", "summary": "Shifts right with zero extension and rounding/saturation logic.", "syntax": "VSSRL.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "101010 | vm | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0xA8000057", "visual_parts": [ { "raw": "101010", "clean": "101010", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = saturate(vs2[i] >>u vs1[i]);", "description": "Vector Saturating Shift Right Logical: Shifts right with zero extension and rounding/saturation logic. Operation: foreach(i < vl): vd[i] = saturate(vs2[i] >>u vs1[i]);.", "example": "VSSRL.VV v1, v4, v2, v0.t" }, { "mnemonic": "VWREDSUM.VS", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Widening Reduction Sum Signed", "summary": "Sums N-bit elements into a 2*N-bit scalar accumulator (Signed).", "syntax": "VWREDSUM.VS vd, vs2, vs1, vm", "encoding": { "format": "OPMVV", "binary_pattern": "110001 | vm | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0xC4000057", "visual_parts": [ { "raw": "110001", "clean": "110001", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest (Scalar Wide)" }, { "name": "vs2", "desc": "Vector (Narrow)" }, { "name": "vs1", "desc": "Start (Wide)" } ], "pseudocode": "vd[0] = vs1[0] + sum(extend(vs2[*]));", "description": "Performs a widening operation, producing results twice as wide as the source elements. Results are written to vd using 2× the element grouping (EEW). The number of elements and masking are governed by vl and vm.", "example": "VWREDSUM.VS v1, v4, v2, v0.t" }, { "mnemonic": "VWREDSUMU.VS", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Widening Reduction Sum Unsigned", "summary": "Sums N-bit elements into a 2*N-bit scalar accumulator (Unsigned).", "syntax": "VWREDSUMU.VS vd, vs2, vs1, vm", "encoding": { "format": "OPMVV", "binary_pattern": "110000 | vm | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0xC0000057", "visual_parts": [ { "raw": "110000", "clean": "110000", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest (Scalar Wide)" }, { "name": "vs2", "desc": "Vector (Narrow)" }, { "name": "vs1", "desc": "Start (Wide)" } ], "pseudocode": "vd[0] = vs1[0] + sum(zext(vs2[*]));", "description": "Performs a widening operation, producing results twice as wide as the source elements. Results are written to vd using 2× the element grouping (EEW). The number of elements and masking are governed by vl and vm.", "example": "VWREDSUMU.VS v1, v4, v2, v0.t" }, { "mnemonic": "VMANDN.MM", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Mask AND NOT", "summary": "Computes vd = vs1 & ~vs2 (mask operation).", "syntax": "VMANDN.MM vd, vs2, vs1", "encoding": { "format": "OPMVV", "binary_pattern": "0110001 | vs2 | vs1 | 010 | vd | 1010111", "hex_opcode": "0x62002057", "visual_parts": [ { "raw": "0110001", "clean": "0110001", "pos": "31:25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest Mask" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "vd = vs1 & ~vs2;", "description": "Performs element-wise mask AND on the mask registers vm1 and vm2, writing to vd.", "example": "VMANDN.MM v1, v4, v2" }, { "mnemonic": "VMORN.MM", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Mask OR NOT", "summary": "Computes vd = vs1 | ~vs2 (mask operation).", "syntax": "VMORN.MM vd, vs2, vs1", "encoding": { "format": "OPMVV", "binary_pattern": "0111001 | vs2 | vs1 | 010 | vd | 1010111", "hex_opcode": "0x72002057", "visual_parts": [ { "raw": "0111001", "clean": "0111001", "pos": "31:25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest Mask" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "vd = vs1 | ~vs2;", "description": "Performs element-wise mask OR on the mask registers vm1 and vm2, writing to vd.", "example": "VMORN.MM v1, v4, v2" }, { "mnemonic": "VMXNOR.MM", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Mask XNOR", "summary": "Computes vd = ~(vs1 ^ vs2) (mask operation).", "syntax": "VMXNOR.MM vd, vs2, vs1", "encoding": { "format": "OPMVV", "binary_pattern": "0111111 | vs2 | vs1 | 010 | vd | 1010111", "hex_opcode": "0x7E002057", "visual_parts": [ { "raw": "0111111", "clean": "0111111", "pos": "31:25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest Mask" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "vd = ~(vs1 ^ vs2);", "description": "Performs element-wise mask XNOR on the mask registers vm1 and vm2, writing to vd.", "example": "VMXNOR.MM v1, v4, v2" }, { "mnemonic": "MAXU", "architecture": "RISC-V", "extension": "Zbb", "full_name": "Maximum Unsigned", "summary": "Computes the maximum of two unsigned integers.", "syntax": "MAXU rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000101 | rs2 | rs1 | 111 | rd | 0110011", "hex_opcode": "0x0A007033", "visual_parts": [ { "raw": "0000101", "clean": "0000101", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "111", "clean": "111", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" } ], "pseudocode": "R[rd] = (R[rs1] >u R[rs2]) ? R[rs1] : R[rs2];", "description": "MAXU computes the unsigned maximum of rs1 and rs2, writing the result to rd.", "example": "MAXU t0, a0, a1" }, { "mnemonic": "MINU", "architecture": "RISC-V", "extension": "Zbb", "full_name": "Minimum Unsigned", "summary": "Computes the minimum of two unsigned integers.", "syntax": "MINU rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000101 | rs2 | rs1 | 101 | rd | 0110011", "hex_opcode": "0x0A005033", "visual_parts": [ { "raw": "0000101", "clean": "0000101", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "101", "clean": "101", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" } ], "pseudocode": "R[rd] = (R[rs1] > SEW;", "description": "Performs element-wise high-half multiply signed on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VMULH.VV v1, v4, v2, v0.t" }, { "mnemonic": "VMULHU.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Multiply High Unsigned", "summary": "Multiplies unsigned integers and keeps the high N bits.", "syntax": "VMULHU.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "100100 | vm | vs2 | vs1 | 010 | vd | 1010111", "hex_opcode": "0x90002057", "visual_parts": [ { "raw": "100100", "clean": "100100", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "foreach(i < vl): vd[i] = (zext(vs1[i]) * zext(vs2[i])) >> SEW;", "description": "Performs element-wise high-half multiply unsigned on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VMULHU.VV v1, v4, v2, v0.t" }, { "mnemonic": "VDIV.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Integer Divide Signed", "summary": "Divides signed vector elements.", "syntax": "VDIV.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "100001 | vm | vs2 | vs1 | 010 | vd | 1010111", "hex_opcode": "0x84002057", "visual_parts": [ { "raw": "100001", "clean": "100001", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Divisor" }, { "name": "vs1", "desc": "Dividend" } ], "pseudocode": "foreach(i < vl): vd[i] = vs1[i] / vs2[i];", "description": "Performs element-wise signed integer division on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VDIV.VV v1, v4, v2, v0.t" }, { "mnemonic": "VDIVU.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Integer Divide Unsigned", "summary": "Divides unsigned vector elements.", "syntax": "VDIVU.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "100000 | vm | vs2 | vs1 | 010 | vd | 1010111", "hex_opcode": "0x80002057", "visual_parts": [ { "raw": "100000", "clean": "100000", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Divisor" }, { "name": "vs1", "desc": "Dividend" } ], "pseudocode": "foreach(i < vl): vd[i] = vs1[i] /u vs2[i];", "description": "Performs element-wise unsigned integer division on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VDIVU.VV v1, v4, v2, v0.t" }, { "mnemonic": "VREM.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Remainder Signed", "summary": "Computes signed remainder.", "syntax": "VREM.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "100011 | vm | vs2 | vs1 | 010 | vd | 1010111", "hex_opcode": "0x8C002057", "visual_parts": [ { "raw": "100011", "clean": "100011", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Divisor" }, { "name": "vs1", "desc": "Dividend" } ], "pseudocode": "foreach(i < vl): vd[i] = vs1[i] % vs2[i];", "description": "Performs element-wise signed remainder on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VREM.VV v1, v4, v2, v0.t" }, { "mnemonic": "VREMU.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Remainder Unsigned", "summary": "Computes unsigned remainder.", "syntax": "VREMU.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "100010 | vm | vs2 | vs1 | 010 | vd | 1010111", "hex_opcode": "0x88002057", "visual_parts": [ { "raw": "100010", "clean": "100010", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Divisor" }, { "name": "vs1", "desc": "Dividend" } ], "pseudocode": "foreach(i < vl): vd[i] = vs1[i] %u vs2[i];", "description": "Performs element-wise unsigned remainder on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VREMU.VV v1, v4, v2, v0.t" }, { "mnemonic": "VWMACC.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Widening Multiply-Accumulate", "summary": "Computes vd = vd + (vs1 * vs2) with widening (N*N -> 2N + 2N).", "syntax": "VWMACC.VV vd, vs1, vs2, vm", "encoding": { "format": "OPIVV", "binary_pattern": "111101 | vm | vs2 | vs1 | 010 | vd | 1010111", "hex_opcode": "0xF4002057", "visual_parts": [ { "raw": "111101", "clean": "111101", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest/Acc (2*SEW)" }, { "name": "vs1", "desc": "Src 1 (SEW)" }, { "name": "vs2", "desc": "Src 2 (SEW)" } ], "pseudocode": "foreach(i < vl): vd[i] = vd[i] + (sext(vs1[i]) * sext(vs2[i]));", "description": "Performs a widening operation, producing results twice as wide as the source elements. Results are written to vd using 2× the element grouping (EEW). The number of elements and masking are governed by vl and vm.", "example": "VWMACC.VV v1, v2, v4, v0.t" }, { "mnemonic": "VWMACCU.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Widening Multiply-Accumulate Unsigned", "summary": "Computes vd = vd + (vs1 * vs2) widening unsigned.", "syntax": "VWMACCU.VV vd, vs1, vs2, vm", "encoding": { "format": "OPIVV", "binary_pattern": "111100 | vm | vs2 | vs1 | 010 | vd | 1010111", "hex_opcode": "0xF0002057", "visual_parts": [ { "raw": "111100", "clean": "111100", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest/Acc (2*SEW)" }, { "name": "vs1", "desc": "Src 1 (SEW)" }, { "name": "vs2", "desc": "Src 2 (SEW)" } ], "pseudocode": "foreach(i < vl): vd[i] = vd[i] + (zext(vs1[i]) * zext(vs2[i]));", "description": "Performs a widening operation, producing results twice as wide as the source elements. Results are written to vd using 2× the element grouping (EEW). The number of elements and masking are governed by vl and vm.", "example": "VWMACCU.VV v1, v2, v4, v0.t" }, { "mnemonic": "VIOTA.M", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Iota", "summary": "Writes the index of the active element to the destination. Useful for parallel prefix sums.", "syntax": "VIOTA.M vd, vs2, vm", "encoding": { "format": "OPMVV", "binary_pattern": "010100 | vm | vs2 | 10000010 | vd | 1010111", "hex_opcode": "0x50082057", "visual_parts": [ { "raw": "010100", "clean": "010100", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "10000010", "clean": "10000010", "pos": "19:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Mask Src" } ], "pseudocode": "count = 0; foreach(i < vl): if vm[i]: vd[i] = count++;", "description": "Writes to each element of vd the sum of set mask bits in vs2 at positions less than the current element index.", "example": "VIOTA.M v1, v4, v0.t" }, { "mnemonic": "VID.V", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Element Index", "summary": "Writes the element index (0, 1, 2...) to the destination.", "syntax": "VID.V vd, vm", "encoding": { "format": "OPMVV", "binary_pattern": "010100 | vm | 0000010001010 | vd | 1010111", "hex_opcode": "0x5008A057", "visual_parts": [ { "raw": "010100", "clean": "010100", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "0000010001010", "clean": "0000010001010", "pos": "24:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" } ], "pseudocode": "foreach(i < vl): vd[i] = i;", "description": "Writes the element index (0, 1, 2, …, vl-1) to each active element of vd.", "example": "VID.V v1, v0.t" }, { "mnemonic": "VFWCVT.F.F.V", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Widening Float to Float Convert", "summary": "Converts N-bit floats to 2*N-bit floats (e.g., FP16 -> FP32).", "syntax": "VFWCVT.F.F.V vd, vs2, vm", "encoding": { "format": "OPFVV", "binary_pattern": "010010 | vm | vs2 | 01100001 | vd | 1010111", "hex_opcode": "0x48061057", "visual_parts": [ { "raw": "010010", "clean": "010010", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "01100001", "clean": "01100001", "pos": "19:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest (Wide)" }, { "name": "vs2", "desc": "Src (Narrow)" } ], "pseudocode": "foreach(i < vl): vd[i] = convert_w(vs2[i]);", "description": "Performs a widening operation, producing results twice as wide as the source elements. Results are written to vd using 2× the element grouping (EEW). The number of elements and masking are governed by vl and vm.", "example": "VFWCVT.F.F.V v1, v4, v0.t" }, { "mnemonic": "VFWCVT.X.F.V", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Widening Float to Signed Int", "summary": "Converts N-bit float to 2*N-bit signed integer.", "syntax": "VFWCVT.X.F.V vd, vs2, vm", "encoding": { "format": "OPFVV", "binary_pattern": "010010 | vm | vs2 | 01001001 | vd | 1010111", "hex_opcode": "0x48049057", "visual_parts": [ { "raw": "010010", "clean": "010010", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "01001001", "clean": "01001001", "pos": "19:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest (Wide Int)" }, { "name": "vs2", "desc": "Src (Float)" } ], "pseudocode": "foreach(i < vl): vd[i] = f_to_x_w(vs2[i]);", "description": "Performs a widening operation, producing results twice as wide as the source elements. Results are written to vd using 2× the element grouping (EEW). The number of elements and masking are governed by vl and vm.", "example": "VFWCVT.X.F.V v1, v4, v0.t" }, { "mnemonic": "VFNCVT.X.F.W", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Narrowing Float to Signed Int", "summary": "Converts 2*N-bit float to N-bit signed integer.", "syntax": "VFNCVT.X.F.W vd, vs2, vm", "encoding": { "format": "OPFVV", "binary_pattern": "010010 | vm | vs2 | 10001001 | vd | 1010111", "hex_opcode": "0x48089057", "visual_parts": [ { "raw": "010010", "clean": "010010", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "10001001", "clean": "10001001", "pos": "19:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest (Int)" }, { "name": "vs2", "desc": "Src (Wide Float)" } ], "pseudocode": "foreach(i < vl): vd[i] = f_to_x_n(vs2[i]);", "description": "Converts vector elements between floating-point and integer types, or between floating-point precisions. Conversions respect the active rounding mode.", "example": "VFNCVT.X.F.W v1, v4, v0.t" }, { "mnemonic": "VNSRL.WI", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Narrowing Shift Right Logical Immediate", "summary": "Shifts wide elements right by immediate and narrows.", "syntax": "VNSRL.WI vd, vs2, imm, vm", "encoding": { "format": "OPIVI", "binary_pattern": "101100 | vm | vs2 | zimm5 | 011 | vd | 1010111", "hex_opcode": "0xB0003057", "visual_parts": [ { "raw": "101100", "clean": "101100", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "zimm5", "clean": "zimm5", "pos": "19:15" }, { "raw": "011", "clean": "011", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest (Narrow)" }, { "name": "vs2", "desc": "Src (Wide)" }, { "name": "imm", "desc": "Signed immediate value" } ], "pseudocode": "foreach(i < vl): vd[i] = (vs2[i] >>u imm) & Mask;", "description": "Performs a narrowing operation, halving the result element width relative to the source. Optionally saturates the result. Active elements are determined by vl; masking by vm.", "example": "VNSRL.WI v1, v4, 16, v0.t" }, { "mnemonic": "VNSRA.WI", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Narrowing Shift Right Arithmetic Immediate", "summary": "Shifts wide elements right (arithmetic) by immediate and narrows.", "syntax": "VNSRA.WI vd, vs2, imm, vm", "encoding": { "format": "OPIVI", "binary_pattern": "101101 | vm | vs2 | zimm5 | 011 | vd | 1010111", "hex_opcode": "0xB4003057", "visual_parts": [ { "raw": "101101", "clean": "101101", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "zimm5", "clean": "zimm5", "pos": "19:15" }, { "raw": "011", "clean": "011", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest (Narrow)" }, { "name": "vs2", "desc": "Src (Wide)" }, { "name": "imm", "desc": "Signed immediate value" } ], "pseudocode": "foreach(i < vl): vd[i] = (vs2[i] >>s imm) & Mask;", "description": "Performs a narrowing operation, halving the result element width relative to the source. Optionally saturates the result. Active elements are determined by vl; masking by vm.", "example": "VNSRA.WI v1, v4, 16, v0.t" }, { "mnemonic": "FCLASS.S", "architecture": "RISC-V", "extension": "F", "full_name": "Float Classify (Single)", "summary": "Examines the value in a float register and generates a 10-bit bitmask indicating its class (NaN, Inf, Zero, Normal, etc.).", "syntax": "FCLASS.S rd, rs1", "encoding": { "format": "R-Type", "binary_pattern": "111000000000 | rs1 | 001 | rd | 1010011", "hex_opcode": "0xE0001053", "visual_parts": [ { "raw": "111000000000", "clean": "111000000000", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Integer Mask)" }, { "name": "rs1", "desc": "Source (Float)" } ], "pseudocode": "R[rd] = classify_float(F[rs1]);", "example": "FCLASS.S x10, f1", "example_note": "Check if f1 is NaN, Infinity, or Zero.", "description": "Classifies the single-precision (32-bit) floating-point value in rs1, writing a 10-bit one-hot result to integer rd. Bits represent: negative infinity, negative normal, negative subnormal, negative zero, positive zero, positive subnormal, positive normal, positive infinity, signalling NaN, quiet NaN." }, { "mnemonic": "FCLASS.D", "architecture": "RISC-V", "extension": "D", "full_name": "Float Classify (Double)", "summary": "Examines a double-precision register and generates a classification bitmask.", "syntax": "FCLASS.D rd, rs1", "encoding": { "format": "R-Type", "binary_pattern": "111000100000 | rs1 | 001 | rd | 1010011", "hex_opcode": "0xE2001053", "visual_parts": [ { "raw": "111000100000", "clean": "111000100000", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Integer Mask)" }, { "name": "rs1", "desc": "Source (Double)" } ], "pseudocode": "R[rd] = classify_double(F[rs1]);", "example": "FCLASS.D x10, f0", "example_note": "Check if f0 is NaN/Inf/Zero.", "description": "Classifies the double-precision (64-bit) floating-point value in rs1, writing a 10-bit one-hot result to integer rd. Bits represent: negative infinity, negative normal, negative subnormal, negative zero, positive zero, positive subnormal, positive normal, positive infinity, signalling NaN, quiet NaN." }, { "mnemonic": "FCVT.S.L", "architecture": "RISC-V", "extension": "F", "full_name": "Convert Long to Float", "summary": "Converts a 64-bit signed integer (Long) to a single-precision float.", "syntax": "FCVT.S.L rd, rs1", "encoding": { "format": "I-Type (Float)", "binary_pattern": "110100000010 | rs1 | rm | rd | 1010011", "hex_opcode": "0xD0200053", "visual_parts": [ { "raw": "110100000010", "clean": "110100000010", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Float)" }, { "name": "rs1", "desc": "Source (Long Int)" } ], "pseudocode": "F[rd] = i64_to_f32(R[rs1]);", "example": "FCVT.S.L f1, x10", "example_note": "64-bit int -> 32-bit float.", "description": "Converts between floating-point types or between floating-point and integer. Result is rounded according to the dynamic rounding mode. Invalid conversions produce the IEEE default NaN or the appropriate integer saturation value." }, { "mnemonic": "FCVT.S.LU", "architecture": "RISC-V", "extension": "F", "full_name": "Convert Unsigned Long to Float", "summary": "Converts a 64-bit unsigned integer to a single-precision float.", "syntax": "FCVT.S.LU rd, rs1", "encoding": { "format": "I-Type (Float)", "binary_pattern": "110100000011 | rs1 | rm | rd | 1010011", "hex_opcode": "0xD0300053", "visual_parts": [ { "raw": "110100000011", "clean": "110100000011", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Float)" }, { "name": "rs1", "desc": "Source (U-Long)" } ], "pseudocode": "F[rd] = u64_to_f32(R[rs1]);", "example": "FCVT.S.LU f1, x10", "example_note": "Unsigned 64-bit int -> float.", "description": "Converts between floating-point types or between floating-point and integer. Result is rounded according to the dynamic rounding mode. Invalid conversions produce the IEEE default NaN or the appropriate integer saturation value." }, { "mnemonic": "FCVT.L.S", "architecture": "RISC-V", "extension": "F", "full_name": "Convert Float to Long", "summary": "Converts a single-precision float to a 64-bit signed integer.", "syntax": "FCVT.L.S rd, rs1", "encoding": { "format": "I-Type (Float)", "binary_pattern": "110000000010 | rs1 | rm | rd | 1010011", "hex_opcode": "0xC0200053", "visual_parts": [ { "raw": "110000000010", "clean": "110000000010", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Long Int)" }, { "name": "rs1", "desc": "Source (Float)" } ], "pseudocode": "R[rd] = f32_to_i64(F[rs1]);", "example": "FCVT.L.S x10, f1", "example_note": "Float -> 64-bit signed int.", "description": "Converts between floating-point types or between floating-point and integer. Result is rounded according to the dynamic rounding mode. Invalid conversions produce the IEEE default NaN or the appropriate integer saturation value." }, { "mnemonic": "FCVT.LU.S", "architecture": "RISC-V", "extension": "F", "full_name": "Convert Float to Unsigned Long", "summary": "Converts a single-precision float to a 64-bit unsigned integer.", "syntax": "FCVT.LU.S rd, rs1", "encoding": { "format": "I-Type (Float)", "binary_pattern": "110000000011 | rs1 | rm | rd | 1010011", "hex_opcode": "0xC0300053", "visual_parts": [ { "raw": "110000000011", "clean": "110000000011", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (U-Long)" }, { "name": "rs1", "desc": "Source (Float)" } ], "pseudocode": "R[rd] = f32_to_u64(F[rs1]);", "example": "FCVT.LU.S x10, f1", "example_note": "Float -> 64-bit unsigned int.", "description": "Converts between floating-point types or between floating-point and integer. Result is rounded according to the dynamic rounding mode. Invalid conversions produce the IEEE default NaN or the appropriate integer saturation value." }, { "mnemonic": "FCVT.D.L", "architecture": "RISC-V", "extension": "D", "full_name": "Convert Long to Double", "summary": "Converts a 64-bit signed integer to a double-precision float.", "syntax": "FCVT.D.L rd, rs1", "encoding": { "format": "I-Type (Float)", "binary_pattern": "110100100010 | rs1 | rm | rd | 1010011", "hex_opcode": "0xD2200053", "visual_parts": [ { "raw": "110100100010", "clean": "110100100010", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Double)" }, { "name": "rs1", "desc": "Source (Long)" } ], "pseudocode": "F[rd] = i64_to_f64(R[rs1]);", "example": "FCVT.D.L f0, x10", "example_note": "64-bit Int -> Double.", "description": "Converts between floating-point types or between floating-point and integer. Result is rounded according to the dynamic rounding mode. Invalid conversions produce the IEEE default NaN or the appropriate integer saturation value." }, { "mnemonic": "FCVT.D.LU", "architecture": "RISC-V", "extension": "D", "full_name": "Convert Unsigned Long to Double", "summary": "Converts a 64-bit unsigned integer to a double-precision float.", "syntax": "FCVT.D.LU rd, rs1", "encoding": { "format": "I-Type (Float)", "binary_pattern": "110100100011 | rs1 | rm | rd | 1010011", "hex_opcode": "0xD2300053", "visual_parts": [ { "raw": "110100100011", "clean": "110100100011", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Double)" }, { "name": "rs1", "desc": "Source (U-Long)" } ], "pseudocode": "F[rd] = u64_to_f64(R[rs1]);", "example": "FCVT.D.LU f0, x10", "example_note": "Unsigned 64-bit Int -> Double.", "description": "Converts between floating-point types or between floating-point and integer. Result is rounded according to the dynamic rounding mode. Invalid conversions produce the IEEE default NaN or the appropriate integer saturation value." }, { "mnemonic": "FCVT.L.D", "architecture": "RISC-V", "extension": "D", "full_name": "Convert Double to Long", "summary": "Converts a double-precision float to a 64-bit signed integer.", "syntax": "FCVT.L.D rd, rs1", "encoding": { "format": "I-Type (Float)", "binary_pattern": "110000100010 | rs1 | rm | rd | 1010011", "hex_opcode": "0xC2200053", "visual_parts": [ { "raw": "110000100010", "clean": "110000100010", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Long)" }, { "name": "rs1", "desc": "Source (Double)" } ], "pseudocode": "R[rd] = f64_to_i64(F[rs1]);", "example": "FCVT.L.D x10, f0", "example_note": "Double -> 64-bit Int.", "description": "Converts between floating-point types or between floating-point and integer. Result is rounded according to the dynamic rounding mode. Invalid conversions produce the IEEE default NaN or the appropriate integer saturation value." }, { "mnemonic": "FSGNJ.D", "architecture": "RISC-V", "extension": "D", "full_name": "Float Sign Injection (Double)", "summary": "Injects the sign of rs2 into rs1 (Double Precision).", "syntax": "FSGNJ.D rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0010001 | rs2 | rs1 | 000 | rd | 1010011", "hex_opcode": "0x22000053", "visual_parts": [ { "raw": "0010001", "clean": "0010001", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source (Body)" }, { "name": "rs2", "desc": "Source (Sign)" } ], "pseudocode": "F[rd] = {F[rs2][63], F[rs1][62:0]};", "example": "FSGNJ.D f0, f1, f2", "example_note": "Copy sign of f2 to f1.", "description": "Produces a result with the magnitude of rs1 and the sign bit taken from the source rs2. Used to implement floating-point absolute value, negate, and copy-sign." }, { "mnemonic": "FSGNJN.D", "architecture": "RISC-V", "extension": "D", "full_name": "Float Sign Injection Negate (Double)", "summary": "Injects the *negated* sign of rs2 into rs1 (Double Precision).", "syntax": "FSGNJN.D rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0010001 | rs2 | rs1 | 001 | rd | 1010011", "hex_opcode": "0x22001053", "visual_parts": [ { "raw": "0010001", "clean": "0010001", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source (Body)" }, { "name": "rs2", "desc": "Source (Sign)" } ], "pseudocode": "F[rd] = {~F[rs2][63], F[rs1][62:0]};", "example": "FSGNJN.D f0, f1, f1", "example_note": "Negate f1 (f0 = -f1).", "description": "Produces a result with the magnitude of rs1 and the sign bit taken from the source rs2. Used to implement floating-point absolute value, negate, and copy-sign." }, { "mnemonic": "FEQ.D", "architecture": "RISC-V", "extension": "D", "full_name": "Float Equal (Double)", "summary": "Sets integer rd to 1 if double rs1 equals double rs2, else 0.", "syntax": "FEQ.D rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "1010001 | rs2 | rs1 | 010 | rd | 1010011", "hex_opcode": "0xA2002053", "visual_parts": [ { "raw": "1010001", "clean": "1010001", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Int)" }, { "name": "rs1", "desc": "Src 1 (Double)" }, { "name": "rs2", "desc": "Src 2 (Double)" } ], "pseudocode": "R[rd] = (F[rs1] == F[rs2]) ? 1 : 0;", "example": "FEQ.D x10, f0, f1", "example_note": "Compare equality.", "description": "Performs a double-precision (64-bit) floating-point equality comparison and writes 1 (true) or 0 (false) to integer rd. NaN inputs produce 0 (unordered), except FEQ which raises invalid-operation if either operand is a signalling NaN." }, { "mnemonic": "FLT.D", "architecture": "RISC-V", "extension": "D", "full_name": "Float Less Than (Double)", "summary": "Sets integer rd to 1 if double rs1 is less than double rs2, else 0.", "syntax": "FLT.D rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "1010001 | rs2 | rs1 | 001 | rd | 1010011", "hex_opcode": "0xA2001053", "visual_parts": [ { "raw": "1010001", "clean": "1010001", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Int)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" } ], "pseudocode": "R[rd] = (F[rs1] < F[rs2]) ? 1 : 0;", "example": "FLT.D x10, f0, f1", "example_note": "Less than check.", "description": "Performs a double-precision (64-bit) floating-point less-than comparison and writes 1 (true) or 0 (false) to integer rd. NaN inputs produce 0 (unordered), except FEQ which raises invalid-operation if either operand is a signalling NaN." }, { "mnemonic": "FLE.D", "architecture": "RISC-V", "extension": "D", "full_name": "Float Less or Equal (Double)", "summary": "Sets integer rd to 1 if double rs1 is less than or equal to double rs2, else 0.", "syntax": "FLE.D rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "1010001 | rs2 | rs1 | 000 | rd | 1010011", "hex_opcode": "0xA2000053", "visual_parts": [ { "raw": "1010001", "clean": "1010001", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Int)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" } ], "pseudocode": "R[rd] = (F[rs1] <= F[rs2]) ? 1 : 0;", "example": "FLE.D x10, f0, f1", "example_note": "Less equal check.", "description": "Performs a double-precision (64-bit) floating-point less-than-or-equal comparison and writes 1 (true) or 0 (false) to integer rd. NaN inputs produce 0 (unordered), except FEQ which raises invalid-operation if either operand is a signalling NaN." }, { "mnemonic": "VLSEG3E8.V", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Load Segment (3 fields, 8-bit)", "summary": "Loads 3 fields (e.g., RGB) of 8-bit elements into 3 vector registers.", "syntax": "VLSEG3E8.V vd, (rs1), vm", "encoding": { "format": "VL-Type", "binary_pattern": "010000 | vm | 00000 | rs1 | 000 | vd | 0000111", "hex_opcode": "0x40000007", "visual_parts": [ { "raw": "010000", "clean": "010000", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "00000", "clean": "00000", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "0000111", "clean": "0000111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest Group (3 regs)" }, { "name": "rs1", "desc": "Base Addr" } ], "pseudocode": "Load 3 interleaved 8-bit streams into 3 vector registers.", "description": "Performs a vector strided load of 3-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.", "example": "VLSEG3E8.V v1, a0, v0.t" }, { "mnemonic": "VSSEG3E8.V", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Store Segment (3 fields, 8-bit)", "summary": "Stores 3 vector registers (e.g., RGB) into memory as interleaved 8-bit fields.", "syntax": "VSSEG3E8.V vs3, (rs1), vm", "encoding": { "format": "VS-Type", "binary_pattern": "010000 | vm | 00000 | rs1 | 000 | vs3 | 0100111", "hex_opcode": "0x40000027", "visual_parts": [ { "raw": "010000", "clean": "010000", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "00000", "clean": "00000", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vs3", "clean": "vs3", "pos": "11:7" }, { "raw": "0100111", "clean": "0100111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vs3", "desc": "Src Group (3 regs)" }, { "name": "rs1", "desc": "Base Addr" } ], "pseudocode": "Store 3 vector registers as interleaved 8-bit fields.", "description": "Performs a vector strided store of 3-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.", "example": "VSSEG3E8.V v6, a0, v0.t" }, { "mnemonic": "VLSEG4E8.V", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Load Segment (4 fields, 8-bit)", "summary": "Loads 4 fields (e.g., RGBA) of 8-bit elements into 4 vector registers.", "syntax": "VLSEG4E8.V vd, (rs1), vm", "encoding": { "format": "VL-Type", "binary_pattern": "011000 | vm | 00000 | rs1 | 000 | vd | 0000111", "hex_opcode": "0x60000007", "visual_parts": [ { "raw": "011000", "clean": "011000", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "00000", "clean": "00000", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "0000111", "clean": "0000111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest Group (4 regs)" }, { "name": "rs1", "desc": "Base Addr" } ], "pseudocode": "Load 4 interleaved 8-bit streams into 4 vector registers.", "description": "Performs a vector strided load of 4-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.", "example": "VLSEG4E8.V v1, a0, v0.t" }, { "mnemonic": "VSSEG4E8.V", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Store Segment (4 fields, 8-bit)", "summary": "Stores 4 vector registers (e.g., RGBA) into memory as interleaved 8-bit fields.", "syntax": "VSSEG4E8.V vs3, (rs1), vm", "encoding": { "format": "VS-Type", "binary_pattern": "011000 | vm | 00000 | rs1 | 000 | vs3 | 0100111", "hex_opcode": "0x60000027", "visual_parts": [ { "raw": "011000", "clean": "011000", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "00000", "clean": "00000", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vs3", "clean": "vs3", "pos": "11:7" }, { "raw": "0100111", "clean": "0100111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vs3", "desc": "Src Group (4 regs)" }, { "name": "rs1", "desc": "Base Addr" } ], "pseudocode": "Store 4 vector registers as interleaved 8-bit fields.", "description": "Performs a vector strided store of 4-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.", "example": "VSSEG4E8.V v6, a0, v0.t" }, { "mnemonic": "VLSEG2E16.V", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Load Segment (2 fields, 16-bit)", "summary": "Loads 2 fields (e.g., Complex Real/Imag) of 16-bit elements.", "syntax": "VLSEG2E16.V vd, (rs1), vm", "encoding": { "format": "VL-Type", "binary_pattern": "001000 | vm | 00000 | rs1 | 101 | vd | 0000111", "hex_opcode": "0x20005007", "visual_parts": [ { "raw": "001000", "clean": "001000", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "00000", "clean": "00000", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "101", "clean": "101", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "0000111", "clean": "0000111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest Group (2 regs)" }, { "name": "rs1", "desc": "Base Addr" } ], "pseudocode": "Load 2 interleaved 16-bit streams.", "description": "Performs a vector strided load of 2-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.", "example": "VLSEG2E16.V v1, a0, v0.t" }, { "mnemonic": "VSSEG2E16.V", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Store Segment (2 fields, 16-bit)", "summary": "Stores 2 vector registers as interleaved 16-bit fields.", "syntax": "VSSEG2E16.V vs3, (rs1), vm", "encoding": { "format": "VS-Type", "binary_pattern": "001000 | vm | 00000 | rs1 | 101 | vs3 | 0100111", "hex_opcode": "0x20005027", "visual_parts": [ { "raw": "001000", "clean": "001000", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "00000", "clean": "00000", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "101", "clean": "101", "pos": "14:12" }, { "raw": "vs3", "clean": "vs3", "pos": "11:7" }, { "raw": "0100111", "clean": "0100111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vs3", "desc": "Src Group (2 regs)" }, { "name": "rs1", "desc": "Base Addr" } ], "pseudocode": "Store 2 interleaved 16-bit streams.", "description": "Performs a vector strided store of 2-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.", "example": "VSSEG2E16.V v6, a0, v0.t" }, { "mnemonic": "VLE8FF.V", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Load 8-bit Fault-Only-First", "summary": "Loads 8-bit elements, suppressing faults on elements after the first. Sets VL to number of elements loaded. Critical for strings.", "syntax": "VLE8FF.V vd, (rs1), vm", "encoding": { "format": "VL-Type", "binary_pattern": "000000 | vm | 10000 | rs1 | 000 | vd | 0000111", "hex_opcode": "0x01000007", "visual_parts": [ { "raw": "000000", "clean": "000000", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "10000", "clean": "10000", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "0000111", "clean": "0000111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "rs1", "desc": "Base Addr" } ], "pseudocode": "vl = LoadFaultFirst(vd, rs1, 1);", "description": "Performs a vector unit-stride load of 8-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.", "example": "VLE8FF.V v1, a0, v0.t" }, { "mnemonic": "VLE16FF.V", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Load 16-bit Fault-Only-First", "summary": "Loads 16-bit elements with fault suppression.", "syntax": "VLE16FF.V vd, (rs1), vm", "encoding": { "format": "VL-Type", "binary_pattern": "000000 | vm | 10000 | rs1 | 101 | vd | 0000111", "hex_opcode": "0x01005007", "visual_parts": [ { "raw": "000000", "clean": "000000", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "10000", "clean": "10000", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "101", "clean": "101", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "0000111", "clean": "0000111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "rs1", "desc": "Base Addr" } ], "pseudocode": "vl = LoadFaultFirst(vd, rs1, 2);", "description": "Performs a vector unit-stride load of 16-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.", "example": "VLE16FF.V v1, a0, v0.t" }, { "mnemonic": "VLE32FF.V", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Load 32-bit Fault-Only-First", "summary": "Loads 32-bit elements with fault suppression.", "syntax": "VLE32FF.V vd, (rs1), vm", "encoding": { "format": "VL-Type", "binary_pattern": "000000 | vm | 10000 | rs1 | 110 | vd | 0000111", "hex_opcode": "0x01006007", "visual_parts": [ { "raw": "000000", "clean": "000000", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "10000", "clean": "10000", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "110", "clean": "110", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "0000111", "clean": "0000111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "rs1", "desc": "Base Addr" } ], "pseudocode": "vl = LoadFaultFirst(vd, rs1, 4);", "description": "Performs a vector unit-stride load of 32-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.", "example": "VLE32FF.V v1, a0, v0.t" }, { "mnemonic": "VLE64FF.V", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Load 64-bit Fault-Only-First", "summary": "Loads 64-bit elements with fault suppression.", "syntax": "VLE64FF.V vd, (rs1), vm", "encoding": { "format": "VL-Type", "binary_pattern": "000000 | vm | 10000 | rs1 | 111 | vd | 0000111", "hex_opcode": "0x01007007", "visual_parts": [ { "raw": "000000", "clean": "000000", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "10000", "clean": "10000", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "111", "clean": "111", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "0000111", "clean": "0000111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "rs1", "desc": "Base Addr" } ], "pseudocode": "vl = LoadFaultFirst(vd, rs1, 8);", "description": "Performs a vector unit-stride load of 64-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.", "example": "VLE64FF.V v1, a0, v0.t" }, { "mnemonic": "VAMOADDW.V", "architecture": "RISC-V", "extension": "Zvamo (draft)", "full_name": "Vector Atomic Add Word", "summary": "Atomically adds elements from vs2 to memory addresses in rs1 (indexed by vs2? No, rs1 is base, vs2 is index).", "syntax": "VAMOADDW.V vd, (rs1), vs2, vm", "encoding": { "format": "VAMO", "binary_pattern": "00000 | wd | vm | vs2 | rs1 | 110 | vd | 0101111", "hex_opcode": "0x0000602F", "visual_parts": [ { "raw": "000001", "clean": "000001", "pos": "31:26" }, { "raw": "00000", "clean": "00000", "pos": "25:21" }, { "raw": "vm", "clean": "vm", "pos": "20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "110", "clean": "110", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "0101111", "clean": "0101111", "pos": "6:0" } ], "bit_positions": "31:26 | 25:21 | 20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest (Old Val)" }, { "name": "rs1", "desc": "Base" }, { "name": "vs2", "desc": "Index" } ], "pseudocode": "AtomicAdd(rs1 + vs2[i], vd[i]);", "description": "Vector Atomic Add Word: Atomically adds elements from vs2 to memory addresses in rs1 (indexed by vs2? No, rs1 is base, vs2 is index). Operation: AtomicAdd(rs1 + vs2[i], vd[i]);.", "example": "VAMOADDW.V v1, a0, v4, v0.t" }, { "mnemonic": "VAMOADDD.V", "architecture": "RISC-V", "extension": "Zvamo (draft)", "full_name": "Vector Atomic Add Doubleword", "summary": "Atomically adds elements from vs2 to memory addresses (64-bit).", "syntax": "VAMOADDD.V vd, (rs1), vs2, vm", "encoding": { "format": "VAMO", "binary_pattern": "00000 | wd | vm | vs2 | rs1 | 111 | vd | 0101111", "hex_opcode": "0x0000702F", "visual_parts": [ { "raw": "000001", "clean": "000001", "pos": "31:26" }, { "raw": "00000", "clean": "00000", "pos": "25:21" }, { "raw": "vm", "clean": "vm", "pos": "20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "111", "clean": "111", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "0101111", "clean": "0101111", "pos": "6:0" } ], "bit_positions": "31:26 | 25:21 | 20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Dest (Old Val)" }, { "name": "rs1", "desc": "Base" }, { "name": "vs2", "desc": "Index" } ], "pseudocode": "AtomicAdd(rs1 + vs2[i], vd[i]);", "description": "Vector Atomic Add Doubleword: Atomically adds elements from vs2 to memory addresses (64-bit). Operation: AtomicAdd(rs1 + vs2[i], vd[i]);.", "example": "VAMOADDD.V v1, a0, v4, v0.t" }, { "mnemonic": "VAMOANDW.V", "architecture": "RISC-V", "extension": "Zvamo (draft)", "full_name": "Vector Atomic AND Word", "summary": "Atomically ANDs elements.", "syntax": "VAMOANDW.V vd, (rs1), vs2, vm", "encoding": { "format": "VAMO", "binary_pattern": "01100 | wd | vm | vs2 | rs1 | 110 | vd | 0101111", "hex_opcode": "0x6000602F", "visual_parts": [ { "raw": "000001", "clean": "000001", "pos": "31:26" }, { "raw": "01100", "clean": "01100", "pos": "25:21" }, { "raw": "vm", "clean": "vm", "pos": "20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "110", "clean": "110", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "0101111", "clean": "0101111", "pos": "6:0" } ], "bit_positions": "31:26 | 25:21 | 20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "rs1", "desc": "Base" }, { "name": "vs2", "desc": "Index" } ], "pseudocode": "AtomicAnd(rs1 + vs2[i], vd[i]);", "description": "Vector Atomic AND Word: Atomically ANDs elements. Operation: AtomicAnd(rs1 + vs2[i], vd[i]);.", "example": "VAMOANDW.V v1, a0, v4, v0.t" }, { "mnemonic": "VAMOANDD.V", "architecture": "RISC-V", "extension": "Zvamo (draft)", "full_name": "Vector Atomic AND Doubleword", "summary": "Atomically ANDs elements (64-bit).", "syntax": "VAMOANDD.V vd, (rs1), vs2, vm", "encoding": { "format": "VAMO", "binary_pattern": "01100 | wd | vm | vs2 | rs1 | 111 | vd | 0101111", "hex_opcode": "0x6000702F", "visual_parts": [ { "raw": "000001", "clean": "000001", "pos": "31:26" }, { "raw": "01100", "clean": "01100", "pos": "25:21" }, { "raw": "vm", "clean": "vm", "pos": "20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "111", "clean": "111", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "0101111", "clean": "0101111", "pos": "6:0" } ], "bit_positions": "31:26 | 25:21 | 20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "rs1", "desc": "Base" }, { "name": "vs2", "desc": "Index" } ], "pseudocode": "AtomicAnd(rs1 + vs2[i], vd[i]);", "description": "Vector Atomic AND Doubleword: Atomically ANDs elements (64-bit). Operation: AtomicAnd(rs1 + vs2[i], vd[i]);.", "example": "VAMOANDD.V v1, a0, v4, v0.t" }, { "mnemonic": "VAMOORW.V", "architecture": "RISC-V", "extension": "Zvamo (draft)", "full_name": "Vector Atomic OR Word", "summary": "Atomically ORs elements.", "syntax": "VAMOORW.V vd, (rs1), vs2, vm", "encoding": { "format": "VAMO", "binary_pattern": "01000 | wd | vm | vs2 | rs1 | 110 | vd | 0101111", "hex_opcode": "0x4000602F", "visual_parts": [ { "raw": "000001", "clean": "000001", "pos": "31:26" }, { "raw": "01000", "clean": "01000", "pos": "25:21" }, { "raw": "vm", "clean": "vm", "pos": "20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "110", "clean": "110", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "0101111", "clean": "0101111", "pos": "6:0" } ], "bit_positions": "31:26 | 25:21 | 20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "rs1", "desc": "Base" }, { "name": "vs2", "desc": "Index" } ], "pseudocode": "AtomicOr(rs1 + vs2[i], vd[i]);", "description": "Vector Atomic OR Word: Atomically ORs elements. Operation: AtomicOr(rs1 + vs2[i], vd[i]);.", "example": "VAMOORW.V v1, a0, v4, v0.t" }, { "mnemonic": "VAMOORD.V", "architecture": "RISC-V", "extension": "Zvamo (draft)", "full_name": "Vector Atomic OR Doubleword", "summary": "Atomically ORs elements (64-bit).", "syntax": "VAMOORD.V vd, (rs1), vs2, vm", "encoding": { "format": "VAMO", "binary_pattern": "01000 | wd | vm | vs2 | rs1 | 111 | vd | 0101111", "hex_opcode": "0x4000702F", "visual_parts": [ { "raw": "000001", "clean": "000001", "pos": "31:26" }, { "raw": "01000", "clean": "01000", "pos": "25:21" }, { "raw": "vm", "clean": "vm", "pos": "20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "111", "clean": "111", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "0101111", "clean": "0101111", "pos": "6:0" } ], "bit_positions": "31:26 | 25:21 | 20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "rs1", "desc": "Base" }, { "name": "vs2", "desc": "Index" } ], "pseudocode": "AtomicOr(rs1 + vs2[i], vd[i]);", "description": "Vector Atomic OR Doubleword: Atomically ORs elements (64-bit). Operation: AtomicOr(rs1 + vs2[i], vd[i]);.", "example": "VAMOORD.V v1, a0, v4, v0.t" }, { "mnemonic": "VAMOXORW.V", "architecture": "RISC-V", "extension": "Zvamo (draft)", "full_name": "Vector Atomic XOR Word", "summary": "Atomically XORs elements.", "syntax": "VAMOXORW.V vd, (rs1), vs2, vm", "encoding": { "format": "VAMO", "binary_pattern": "00100 | wd | vm | vs2 | rs1 | 110 | vd | 0101111", "hex_opcode": "0x2000602F", "visual_parts": [ { "raw": "000001", "clean": "000001", "pos": "31:26" }, { "raw": "00100", "clean": "00100", "pos": "25:21" }, { "raw": "vm", "clean": "vm", "pos": "20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "110", "clean": "110", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "0101111", "clean": "0101111", "pos": "6:0" } ], "bit_positions": "31:26 | 25:21 | 20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "rs1", "desc": "Base" }, { "name": "vs2", "desc": "Index" } ], "pseudocode": "AtomicXor(rs1 + vs2[i], vd[i]);", "description": "Vector Atomic XOR Word: Atomically XORs elements. Operation: AtomicXor(rs1 + vs2[i], vd[i]);.", "example": "VAMOXORW.V v1, a0, v4, v0.t" }, { "mnemonic": "VAMOXORD.V", "architecture": "RISC-V", "extension": "Zvamo (draft)", "full_name": "Vector Atomic XOR Doubleword", "summary": "Atomically XORs elements (64-bit).", "syntax": "VAMOXORD.V vd, (rs1), vs2, vm", "encoding": { "format": "VAMO", "binary_pattern": "00100 | wd | vm | vs2 | rs1 | 111 | vd | 0101111", "hex_opcode": "0x2000702F", "visual_parts": [ { "raw": "000001", "clean": "000001", "pos": "31:26" }, { "raw": "00100", "clean": "00100", "pos": "25:21" }, { "raw": "vm", "clean": "vm", "pos": "20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "111", "clean": "111", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "0101111", "clean": "0101111", "pos": "6:0" } ], "bit_positions": "31:26 | 25:21 | 20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "rs1", "desc": "Base" }, { "name": "vs2", "desc": "Index" } ], "pseudocode": "AtomicXor(rs1 + vs2[i], vd[i]);", "description": "Vector Atomic XOR Doubleword: Atomically XORs elements (64-bit). Operation: AtomicXor(rs1 + vs2[i], vd[i]);.", "example": "VAMOXORD.V v1, a0, v4, v0.t" }, { "mnemonic": "VAMOMAXW.V", "architecture": "RISC-V", "extension": "Zvamo (draft)", "full_name": "Vector Atomic Max Word", "summary": "Atomic Max (Signed).", "syntax": "VAMOMAXW.V vd, (rs1), vs2, vm", "encoding": { "format": "VAMO", "binary_pattern": "10100 | wd | vm | vs2 | rs1 | 110 | vd | 0101111", "hex_opcode": "0xA000602F", "visual_parts": [ { "raw": "000001", "clean": "000001", "pos": "31:26" }, { "raw": "10100", "clean": "10100", "pos": "25:21" }, { "raw": "vm", "clean": "vm", "pos": "20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "110", "clean": "110", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "0101111", "clean": "0101111", "pos": "6:0" } ], "bit_positions": "31:26 | 25:21 | 20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "rs1", "desc": "Base" }, { "name": "vs2", "desc": "Index" } ], "pseudocode": "AtomicMax(rs1 + vs2[i], vd[i]);", "description": "Vector Atomic Max Word: Atomic Max (Signed). Operation: AtomicMax(rs1 + vs2[i], vd[i]);.", "example": "VAMOMAXW.V v1, a0, v4, v0.t" }, { "mnemonic": "VAMOMAXD.V", "architecture": "RISC-V", "extension": "Zvamo (draft)", "full_name": "Vector Atomic Max Doubleword", "summary": "Atomic Max (Signed, 64-bit).", "syntax": "VAMOMAXD.V vd, (rs1), vs2, vm", "encoding": { "format": "VAMO", "binary_pattern": "10100 | wd | vm | vs2 | rs1 | 111 | vd | 0101111", "hex_opcode": "0xA000702F", "visual_parts": [ { "raw": "000001", "clean": "000001", "pos": "31:26" }, { "raw": "10100", "clean": "10100", "pos": "25:21" }, { "raw": "vm", "clean": "vm", "pos": "20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "111", "clean": "111", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "0101111", "clean": "0101111", "pos": "6:0" } ], "bit_positions": "31:26 | 25:21 | 20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "rs1", "desc": "Base" }, { "name": "vs2", "desc": "Index" } ], "pseudocode": "AtomicMax(rs1 + vs2[i], vd[i]);", "description": "Vector Atomic Max Doubleword: Atomic Max (Signed, 64-bit). Operation: AtomicMax(rs1 + vs2[i], vd[i]);.", "example": "VAMOMAXD.V v1, a0, v4, v0.t" }, { "mnemonic": "VAMOMINW.V", "architecture": "RISC-V", "extension": "Zvamo (draft)", "full_name": "Vector Atomic Min Word", "summary": "Atomic Min (Signed).", "syntax": "VAMOMINW.V vd, (rs1), vs2, vm", "encoding": { "format": "VAMO", "binary_pattern": "10000 | wd | vm | vs2 | rs1 | 110 | vd | 0101111", "hex_opcode": "0x8000602F", "visual_parts": [ { "raw": "000001", "clean": "000001", "pos": "31:26" }, { "raw": "10000", "clean": "10000", "pos": "25:21" }, { "raw": "vm", "clean": "vm", "pos": "20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "110", "clean": "110", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "0101111", "clean": "0101111", "pos": "6:0" } ], "bit_positions": "31:26 | 25:21 | 20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "rs1", "desc": "Base" }, { "name": "vs2", "desc": "Index" } ], "pseudocode": "AtomicMin(rs1 + vs2[i], vd[i]);", "description": "Vector Atomic Min Word: Atomic Min (Signed). Operation: AtomicMin(rs1 + vs2[i], vd[i]);.", "example": "VAMOMINW.V v1, a0, v4, v0.t" }, { "mnemonic": "VAMOMIND.V", "architecture": "RISC-V", "extension": "Zvamo (draft)", "full_name": "Vector Atomic Min Doubleword", "summary": "Atomic Min (Signed, 64-bit).", "syntax": "VAMOMIND.V vd, (rs1), vs2, vm", "encoding": { "format": "VAMO", "binary_pattern": "10000 | wd | vm | vs2 | rs1 | 111 | vd | 0101111", "hex_opcode": "0x8000702F", "visual_parts": [ { "raw": "000001", "clean": "000001", "pos": "31:26" }, { "raw": "10000", "clean": "10000", "pos": "25:21" }, { "raw": "vm", "clean": "vm", "pos": "20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "111", "clean": "111", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "0101111", "clean": "0101111", "pos": "6:0" } ], "bit_positions": "31:26 | 25:21 | 20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "rs1", "desc": "Base" }, { "name": "vs2", "desc": "Index" } ], "pseudocode": "AtomicMin(rs1 + vs2[i], vd[i]);", "description": "Vector Atomic Min Doubleword: Atomic Min (Signed, 64-bit). Operation: AtomicMin(rs1 + vs2[i], vd[i]);.", "example": "VAMOMIND.V v1, a0, v4, v0.t" }, { "mnemonic": "VAMOMAXU.V", "architecture": "RISC-V", "extension": "Zvamo (draft)", "full_name": "Vector Atomic Max Unsigned", "summary": "Atomic Max (Unsigned, Width implicit).", "syntax": "VAMOMAXU.V vd, (rs1), vs2, vm", "encoding": { "format": "VAMO", "binary_pattern": "000001 | 11100 | vm | rs1 | width | vd | 0101111", "hex_opcode": "0xE000602F", "visual_parts": [ { "raw": "000001", "clean": "000001", "pos": "31:26" }, { "raw": "11100", "clean": "11100", "pos": "25:21" }, { "raw": "vm", "clean": "vm", "pos": "20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "width", "clean": "width", "pos": "" }, { "raw": "vd", "clean": "vd", "pos": "14:10" }, { "raw": "0101111", "clean": "0101111", "pos": "9:3" } ], "bit_positions": "31:26 | 25:21 | 20 | 19:15 | | 14:10 | 9:3" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "rs1", "desc": "Base" }, { "name": "vs2", "desc": "Index" } ], "pseudocode": "AtomicMaxU(rs1 + vs2[i], vd[i]);", "description": "Vector Atomic Max Unsigned: Atomic Max (Unsigned, Width implicit). Operation: AtomicMaxU(rs1 + vs2[i], vd[i]);.", "example": "VAMOMAXU.V v1, a0, v4, v0.t" }, { "mnemonic": "VAMOMINU.V", "architecture": "RISC-V", "extension": "Zvamo (draft)", "full_name": "Vector Atomic Min Unsigned", "summary": "Atomic Min (Unsigned, Width implicit).", "syntax": "VAMOMINU.V vd, (rs1), vs2, vm", "encoding": { "format": "VAMO", "binary_pattern": "000001 | 11000 | vm | rs1 | width | vd | 0101111", "hex_opcode": "0xC000602F", "visual_parts": [ { "raw": "000001", "clean": "000001", "pos": "31:26" }, { "raw": "11000", "clean": "11000", "pos": "25:21" }, { "raw": "vm", "clean": "vm", "pos": "20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "width", "clean": "width", "pos": "" }, { "raw": "vd", "clean": "vd", "pos": "14:10" }, { "raw": "0101111", "clean": "0101111", "pos": "9:3" } ], "bit_positions": "31:26 | 25:21 | 20 | 19:15 | | 14:10 | 9:3" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "rs1", "desc": "Base" }, { "name": "vs2", "desc": "Index" } ], "pseudocode": "AtomicMinU(rs1 + vs2[i], vd[i]);", "description": "Vector Atomic Min Unsigned: Atomic Min (Unsigned, Width implicit). Operation: AtomicMinU(rs1 + vs2[i], vd[i]);.", "example": "VAMOMINU.V v1, a0, v4, v0.t" }, { "mnemonic": "VSLIDE1UP.VX", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Slide One Element Up", "summary": "Moves elements up by 1, injecting scalar into index 0.", "syntax": "VSLIDE1UP.VX vd, vs2, rs1, vm", "encoding": { "format": "OPIVX", "binary_pattern": "001110 | vm | vs2 | rs1 | 110 | vd | 1010111", "hex_opcode": "0x38006057", "visual_parts": [ { "raw": "001110", "clean": "001110", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "110", "clean": "110", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Src Vec" }, { "name": "rs1", "desc": "Scalar" } ], "pseudocode": "vd[0] = rs1; vd[i] = vs2[i-1];", "description": "Slides vector elements up by the specified offset, filling vacated positions with zero or the value from vs1[0].", "example": "VSLIDE1UP.VX v1, v4, a0, v0.t" }, { "mnemonic": "VSLIDE1DOWN.VX", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Slide One Element Down", "summary": "Moves elements down by 1, injecting scalar into top index.", "syntax": "VSLIDE1DOWN.VX vd, vs2, rs1, vm", "encoding": { "format": "OPIVX", "binary_pattern": "001111 | vm | vs2 | rs1 | 110 | vd | 1010111", "hex_opcode": "0x3C006057", "visual_parts": [ { "raw": "001111", "clean": "001111", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "110", "clean": "110", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Src Vec" }, { "name": "rs1", "desc": "Scalar" } ], "pseudocode": "vd[i] = vs2[i+1]; vd[vl-1] = rs1;", "description": "Slides vector elements down by the specified offset, filling vacated positions with zero or the value from vs1[0].", "example": "VSLIDE1DOWN.VX v1, v4, a0, v0.t" }, { "mnemonic": "VFREDOSUM.VS", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Ordered Float Reduction Sum", "summary": "Sums float vector elements in exact order (0 to vl-1).", "syntax": "VFREDOSUM.VS vd, vs2, vs1, vm", "encoding": { "format": "OPFVV", "binary_pattern": "000011 | vm | vs2 | vs1 | 001 | vd | 1010111", "hex_opcode": "0x0C001057", "visual_parts": [ { "raw": "000011", "clean": "000011", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Scalar Dest" }, { "name": "vs2", "desc": "Vector" }, { "name": "vs1", "desc": "Start" } ], "pseudocode": "vd[0] = vs1[0]; for i in 0..vl-1: vd[0] += vs2[i];", "description": "Performs a vector reduction: applies the operation across all active elements of vs2, using vs1[0] as the initial accumulator, and writes the scalar result to vd[0]. Active elements are determined by vl.", "example": "VFREDOSUM.VS v1, v4, v2, v0.t" }, { "mnemonic": "VFWREDUSUM.VS", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Widening Unordered Float Reduction Sum", "summary": "Sums N-bit floats into 2*N-bit scalar accumulator (Unordered).", "syntax": "VFWREDUSUM.VS vd, vs2, vs1, vm", "encoding": { "format": "OPFVV", "binary_pattern": "110001 | vm | vs2 | vs1 | 001 | vd | 1010111", "hex_opcode": "0xC4001057", "visual_parts": [ { "raw": "110001", "clean": "110001", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Wide Dest" }, { "name": "vs2", "desc": "Narrow Vec" }, { "name": "vs1", "desc": "Wide Start" } ], "pseudocode": "vd[0] = vs1[0] + sum(vs2[*]);", "description": "Performs a widening operation, producing results twice as wide as the source elements. Results are written to vd using 2× the element grouping (EEW). The number of elements and masking are governed by vl and vm.", "example": "VFWREDUSUM.VS v1, v4, v2, v0.t" }, { "mnemonic": "VFWREDOSUM.VS", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Widening Ordered Float Reduction Sum", "summary": "Sums N-bit floats into 2*N-bit scalar accumulator (Ordered).", "syntax": "VFWREDOSUM.VS vd, vs2, vs1, vm", "encoding": { "format": "OPFVV", "binary_pattern": "110011 | vm | vs2 | vs1 | 001 | vd | 1010111", "hex_opcode": "0xCC001057", "visual_parts": [ { "raw": "110011", "clean": "110011", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Wide Dest" }, { "name": "vs2", "desc": "Narrow Vec" }, { "name": "vs1", "desc": "Wide Start" } ], "pseudocode": "vd[0] = vs1[0]; for i: vd[0] += extend(vs2[i]);", "description": "Performs a widening operation, producing results twice as wide as the source elements. Results are written to vd using 2× the element grouping (EEW). The number of elements and masking are governed by vl and vm.", "example": "VFWREDOSUM.VS v1, v4, v2, v0.t" }, { "mnemonic": "VMERGE.VXM", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Merge Scalar", "summary": "Merges integer scalar vs vector based on mask.", "syntax": "VMERGE.VXM vd, vs2, rs1, v0", "encoding": { "format": "OPIVX", "binary_pattern": "0101110 | vs2 | rs1 | 100 | vd | 1010111", "hex_opcode": "0x5C004057", "visual_parts": [ { "raw": "0101110", "clean": "0101110", "pos": "31:25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "100", "clean": "100", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "False" }, { "name": "rs1", "desc": "True (Scalar)" } ], "pseudocode": "vd[i] = v0[i] ? rs1 : vs2[i];", "description": "Merges elements from vs1 and vs2 (or an immediate) according to the mask: masked-on elements come from vs1, masked-off from vs2.", "example": "VMERGE.VXM v1, v4, a0, v0" }, { "mnemonic": "VMERGE.VIM", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Merge Immediate", "summary": "Merges immediate vs vector based on mask.", "syntax": "VMERGE.VIM vd, vs2, imm, v0", "encoding": { "format": "OPIVI", "binary_pattern": "0101110 | vs2 | simm5 | 011 | vd | 1010111", "hex_opcode": "0x5C003057", "visual_parts": [ { "raw": "0101110", "clean": "0101110", "pos": "31:25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "simm5", "clean": "simm5", "pos": "19:15" }, { "raw": "011", "clean": "011", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "False" }, { "name": "imm", "desc": "True (Imm)" } ], "pseudocode": "vd[i] = v0[i] ? imm : vs2[i];", "description": "Merges elements from vs1 and vs2 (or an immediate) according to the mask: masked-on elements come from vs1, masked-off from vs2.", "example": "VMERGE.VIM v1, v4, 16, v0" }, { "mnemonic": "SHA512SIG0", "architecture": "RISC-V", "extension": "Zknh", "full_name": "SHA-512 Sigma0", "summary": "Performs SHA-512 Sigma0 transformation (RV64).", "syntax": "SHA512SIG0 rd, rs1", "encoding": { "format": "R-Type", "binary_pattern": "000100000110 | rs1 | 001 | rd | 0010011", "hex_opcode": "0x10601013", "visual_parts": [ { "raw": "000100000110", "clean": "000100000110", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0010011", "clean": "0010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" } ], "pseudocode": "rd = sigma0_512(rs1);", "description": "SHA512SIG0 computes the lower 64-bit word of the sigma_0 function for SHA-512.", "example": "SHA512SIG0 t0, a0" }, { "mnemonic": "SHA512SIG1", "architecture": "RISC-V", "extension": "Zknh", "full_name": "SHA-512 Sigma1", "summary": "Performs SHA-512 Sigma1 transformation (RV64).", "syntax": "SHA512SIG1 rd, rs1", "encoding": { "format": "R-Type", "binary_pattern": "000100000111 | rs1 | 001 | rd | 0010011", "hex_opcode": "0x10701013", "visual_parts": [ { "raw": "000100000111", "clean": "000100000111", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0010011", "clean": "0010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" } ], "pseudocode": "rd = sigma1_512(rs1);", "description": "SHA512SIG1 computes the sigma_1 function for SHA-512.", "example": "SHA512SIG1 t0, a0" }, { "mnemonic": "SHA512SUM0", "architecture": "RISC-V", "extension": "Zknh", "full_name": "SHA-512 Sum0", "summary": "Performs SHA-512 Sum0 transformation (RV64).", "syntax": "SHA512SUM0 rd, rs1", "encoding": { "format": "R-Type", "binary_pattern": "000100000100 | rs1 | 001 | rd | 0010011", "hex_opcode": "0x10401013", "visual_parts": [ { "raw": "000100000100", "clean": "000100000100", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0010011", "clean": "0010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" } ], "pseudocode": "rd = sum0_512(rs1);", "description": "SHA512SUM0 computes the sum-0 (capital Sigma-0) function for SHA-512.", "example": "SHA512SUM0 t0, a0" }, { "mnemonic": "SHA512SUM1", "architecture": "RISC-V", "extension": "Zknh", "full_name": "SHA-512 Sum1", "summary": "Performs SHA-512 Sum1 transformation (RV64).", "syntax": "SHA512SUM1 rd, rs1", "encoding": { "format": "R-Type", "binary_pattern": "000100000101 | rs1 | 001 | rd | 0010011", "hex_opcode": "0x10501013", "visual_parts": [ { "raw": "000100000101", "clean": "000100000101", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0010011", "clean": "0010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" } ], "pseudocode": "rd = sum1_512(rs1);", "description": "SHA512SUM1 computes the sum-1 (capital Sigma-1) function for SHA-512.", "example": "SHA512SUM1 t0, a0" }, { "mnemonic": "C.FLD", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed Float Load Double", "summary": "Loads a double-precision float from memory (Compressed).", "syntax": "C.FLD rd', offset(rs1')", "encoding": { "format": "CL", "binary_pattern": "? | 001 | c_uimm8hi | rs1_p | c_uimm8lo | rd_p | 00", "hex_opcode": "0x00002000", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "001", "clean": "001", "pos": "15:13" }, { "raw": "c_uimm8hi", "clean": "c_uimm8hi", "pos": "12:10" }, { "raw": "rs1_p", "clean": "rs1_p", "pos": "9:7" }, { "raw": "c_uimm8lo", "clean": "c_uimm8lo", "pos": "6:5" }, { "raw": "rd_p", "clean": "rd_p", "pos": "4:2" }, { "raw": "00", "clean": "00", "pos": "1:0" } ], "bit_positions": "31:16 | 15:13 | 12:10 | 9:7 | 6:5 | 4:2 | 1:0" }, "operands": [ { "name": "rd'", "desc": "Dest (f8-f15)" }, { "name": "rs1'", "desc": "Base (x8-x15)" }, { "name": "offset", "desc": "Offset" } ], "pseudocode": "F[rd'] = M[R[rs1'] + offset][63:0];", "description": "Loads a double-precision FP value from memory into fd′. Stack-pointer relative or register-based variants.", "example": "C.FLD rd', 0(a0)" }, { "mnemonic": "C.FSD", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed Float Store Double", "summary": "Stores a double-precision float to memory (Compressed).", "syntax": "C.FSD rs2', offset(rs1')", "encoding": { "format": "CS", "binary_pattern": "? | 101 | c_uimm8hi | rs1_p | c_uimm8lo | rs2_p | 00", "hex_opcode": "0x0000A000", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "101", "clean": "101", "pos": "15:13" }, { "raw": "c_uimm8hi", "clean": "c_uimm8hi", "pos": "12:10" }, { "raw": "rs1_p", "clean": "rs1_p", "pos": "9:7" }, { "raw": "c_uimm8lo", "clean": "c_uimm8lo", "pos": "6:5" }, { "raw": "rs2_p", "clean": "rs2_p", "pos": "4:2" }, { "raw": "00", "clean": "00", "pos": "1:0" } ], "bit_positions": "31:16 | 15:13 | 12:10 | 9:7 | 6:5 | 4:2 | 1:0" }, "operands": [ { "name": "rs2'", "desc": "Source (f8-f15)" }, { "name": "rs1'", "desc": "Base (x8-x15)" }, { "name": "offset", "desc": "Offset" } ], "pseudocode": "M[R[rs1'] + offset][63:0] = F[rs2'];", "description": "Stores a double-precision FP value from fd′ to memory.", "example": "C.FSD rs2', 0(a0)" }, { "mnemonic": "C.ADDI4SPN", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed Add Immediate to Stack Pointer (Non-zero)", "summary": "Adds a zero-extended non-zero immediate to the stack pointer (x2) and stores the result in a register.", "syntax": "C.ADDI4SPN rd', uimm", "encoding": { "format": "CIW", "binary_pattern": "? | 000 | c_nzuimm10 | rd_p | 00", "hex_opcode": "0x00000000", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "000", "clean": "000", "pos": "15:13" }, { "raw": "c_nzuimm10", "clean": "c_nzuimm10", "pos": "12:5" }, { "raw": "rd_p", "clean": "rd_p", "pos": "4:2" }, { "raw": "00", "clean": "00", "pos": "1:0" } ], "bit_positions": "31:16 | 15:13 | 12:5 | 4:2 | 1:0" }, "operands": [ { "name": "rd'", "desc": "Dest (x8-x15)" }, { "name": "uimm", "desc": "Unsigned immediate value" } ], "pseudocode": "R[rd'] = R[2] + zext(uimm);", "example": "C.ADDI4SPN x8, 16", "example_note": "Load address of stack object.", "description": "Adds a zero-extended non-zero immediate to sp (x2) and writes the result to rd′ (CIW format). Used to address stack-allocated data." }, { "mnemonic": "C.LW", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed Load Word", "summary": "Loads a 32-bit word from memory using a compressed encoding.", "syntax": "C.LW rd', offset(rs1')", "encoding": { "format": "CL", "binary_pattern": "? | 010 | c_uimm7hi | rs1_p | c_uimm7lo | rd_p | 00", "hex_opcode": "0x00004000", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "010", "clean": "010", "pos": "15:13" }, { "raw": "c_uimm7hi", "clean": "c_uimm7hi", "pos": "12:10" }, { "raw": "rs1_p", "clean": "rs1_p", "pos": "9:7" }, { "raw": "c_uimm7lo", "clean": "c_uimm7lo", "pos": "6:5" }, { "raw": "rd_p", "clean": "rd_p", "pos": "4:2" }, { "raw": "00", "clean": "00", "pos": "1:0" } ], "bit_positions": "31:16 | 15:13 | 12:10 | 9:7 | 6:5 | 4:2 | 1:0" }, "operands": [ { "name": "rd'", "desc": "Dest (x8-x15)" }, { "name": "rs1'", "desc": "Base (x8-x15)" }, { "name": "offset", "desc": "Offset" } ], "pseudocode": "R[rd'] = M[R[rs1'] + offset][31:0];", "example": "C.LW x8, 4(x9)", "example_note": "16-bit encoding of LW.", "description": "Loads a 32-bit word from memory at a 6-bit unsigned offset from rs1′ into rd′." }, { "mnemonic": "C.SW", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed Store Word", "summary": "Stores a 32-bit word to memory using a compressed encoding.", "syntax": "C.SW rs2', offset(rs1')", "encoding": { "format": "CS", "binary_pattern": "? | 110 | c_uimm7hi | rs1_p | c_uimm7lo | rs2_p | 00", "hex_opcode": "0x0000C000", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "110", "clean": "110", "pos": "15:13" }, { "raw": "c_uimm7hi", "clean": "c_uimm7hi", "pos": "12:10" }, { "raw": "rs1_p", "clean": "rs1_p", "pos": "9:7" }, { "raw": "c_uimm7lo", "clean": "c_uimm7lo", "pos": "6:5" }, { "raw": "rs2_p", "clean": "rs2_p", "pos": "4:2" }, { "raw": "00", "clean": "00", "pos": "1:0" } ], "bit_positions": "31:16 | 15:13 | 12:10 | 9:7 | 6:5 | 4:2 | 1:0" }, "operands": [ { "name": "rs2'", "desc": "Source (x8-x15)" }, { "name": "rs1'", "desc": "Base (x8-x15)" }, { "name": "offset", "desc": "Offset" } ], "pseudocode": "M[R[rs1'] + offset][31:0] = R[rs2'];", "example": "C.SW x8, 4(x9)", "example_note": "16-bit encoding of SW.", "description": "Stores the low 32 bits of rs2′ to memory at a 6-bit unsigned offset from rs1′." }, { "mnemonic": "C.ADDI", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed Add Immediate", "summary": "Adds a non-zero immediate to a register.", "syntax": "C.ADDI rd, imm", "encoding": { "format": "CI", "binary_pattern": "? | 000 | c_nzimm6hi | rd_rs1_n0 | c_nzimm6lo | 01", "hex_opcode": "0x00000001", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "000", "clean": "000", "pos": "15:13" }, { "raw": "c_nzimm6hi", "clean": "c_nzimm6hi", "pos": "12" }, { "raw": "rd_rs1_n0", "clean": "rd_rs1_n0", "pos": "11:7" }, { "raw": "c_nzimm6lo", "clean": "c_nzimm6lo", "pos": "6:2" }, { "raw": "01", "clean": "01", "pos": "1:0" } ], "bit_positions": "31:16 | 15:13 | 12 | 11:7 | 6:2 | 1:0" }, "operands": [ { "name": "rd", "desc": "Dest/Source" }, { "name": "imm", "desc": "6-bit Signed Imm" } ], "pseudocode": "R[rd] = R[rd] + sext(imm);", "example": "C.ADDI x10, 1", "example_note": "Increment x10.", "description": "Adds a non-zero 6-bit sign-extended immediate to rd (≠ x0) and writes back. 16-bit encoding of ADDI." }, { "mnemonic": "C.JAL", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed Jump and Link", "summary": "Performs a PC-relative jump and stores return address in x1 (ra). RV32 only.", "syntax": "C.JAL offset", "encoding": { "format": "CJ", "binary_pattern": "? | 001 | c_imm12 | 01", "hex_opcode": "0x00002001", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "001", "clean": "001", "pos": "15:13" }, { "raw": "c_imm12", "clean": "c_imm12", "pos": "12:2" }, { "raw": "01", "clean": "01", "pos": "1:0" } ], "bit_positions": "31:16 | 15:13 | 12:2 | 1:0" }, "operands": [ { "name": "offset", "desc": "Jump Target" } ], "pseudocode": "R[1] = PC + 2; PC += sext(offset);", "example": "C.JAL func", "example_note": "Compressed function call.", "description": "Performs a PC-relative jump and saves the return address in x1 (RV32 only)." }, { "mnemonic": "C.LI", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed Load Immediate", "summary": "Loads a 6-bit signed immediate into a register.", "syntax": "C.LI rd, imm", "encoding": { "format": "CI", "binary_pattern": "? | 010 | c_imm6hi | rd_n0 | c_imm6lo | 01", "hex_opcode": "0x00004001", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "010", "clean": "010", "pos": "15:13" }, { "raw": "c_imm6hi", "clean": "c_imm6hi", "pos": "12" }, { "raw": "rd_n0", "clean": "rd_n0", "pos": "11:7" }, { "raw": "c_imm6lo", "clean": "c_imm6lo", "pos": "6:2" }, { "raw": "01", "clean": "01", "pos": "1:0" } ], "bit_positions": "31:16 | 15:13 | 12 | 11:7 | 6:2 | 1:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "imm", "desc": "Signed immediate value" } ], "pseudocode": "R[rd] = sext(imm);", "example": "C.LI x10, 1", "example_note": "Set x10 to 1.", "description": "Loads a 6-bit sign-extended immediate into rd (≠ x0). Equivalent to ADDI rd, x0, imm." }, { "mnemonic": "C.ADDI16SP", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed Add Immediate to Stack Pointer", "summary": "Adds a signed non-zero immediate to the stack pointer (x2).", "syntax": "C.ADDI16SP imm", "encoding": { "format": "CI", "binary_pattern": "? | 011 | c_nzimm10hi | 00010 | c_nzimm10lo | 01", "hex_opcode": "0x00006101", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "011", "clean": "011", "pos": "15:13" }, { "raw": "c_nzimm10hi", "clean": "c_nzimm10hi", "pos": "12" }, { "raw": "00010", "clean": "00010", "pos": "11:7" }, { "raw": "c_nzimm10lo", "clean": "c_nzimm10lo", "pos": "6:2" }, { "raw": "01", "clean": "01", "pos": "1:0" } ], "bit_positions": "31:16 | 15:13 | 12 | 11:7 | 6:2 | 1:0" }, "operands": [ { "name": "imm", "desc": "Signed Imm * 16" } ], "pseudocode": "R[2] = R[2] + sext(imm);", "example": "C.ADDI16SP -64", "example_note": "Allocate 64 bytes on stack.", "description": "Adds a non-zero 6-bit sign-extended immediate scaled by 16 to the stack pointer (x2)." }, { "mnemonic": "C.LUI", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed Load Upper Immediate", "summary": "Loads a non-zero 6-bit immediate into bits 17-12 of the destination register, clears lower 12 bits, sign-extends bit 17.", "syntax": "C.LUI rd, imm", "encoding": { "format": "CI", "binary_pattern": "? | 011 | c_nzimm18hi | rd_n2 | c_nzimm18lo | 01", "hex_opcode": "0x00006001", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "011", "clean": "011", "pos": "15:13" }, { "raw": "c_nzimm18hi", "clean": "c_nzimm18hi", "pos": "12" }, { "raw": "rd_n2", "clean": "rd_n2", "pos": "11:7" }, { "raw": "c_nzimm18lo", "clean": "c_nzimm18lo", "pos": "6:2" }, { "raw": "01", "clean": "01", "pos": "1:0" } ], "bit_positions": "31:16 | 15:13 | 12 | 11:7 | 6:2 | 1:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "imm", "desc": "Signed immediate value" } ], "pseudocode": "R[rd] = sext(imm << 12);", "example": "C.LUI x10, 1", "example_note": "Loads 0x1000 into x10.", "description": "Loads a 18-bit sign-extended value (upper 6 bits of 20-bit immediate) into rd (≠ x0, x2)." }, { "mnemonic": "C.SRLI", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed Shift Right Logical Immediate", "summary": "Logically shifts a register right by immediate.", "syntax": "C.SRLI rd', imm", "encoding": { "format": "CB", "binary_pattern": "? | 100 | c_nzuimm6hi | 00 | rd_rs1_p | c_nzuimm6lo | 01", "hex_opcode": "0x00008001", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "100", "clean": "100", "pos": "15:13" }, { "raw": "c_nzuimm6hi", "clean": "c_nzuimm6hi", "pos": "12" }, { "raw": "00", "clean": "00", "pos": "11:10" }, { "raw": "rd_rs1_p", "clean": "rd_rs1_p", "pos": "9:7" }, { "raw": "c_nzuimm6lo", "clean": "c_nzuimm6lo", "pos": "6:2" }, { "raw": "01", "clean": "01", "pos": "1:0" } ], "bit_positions": "31:16 | 15:13 | 12 | 11:10 | 9:7 | 6:2 | 1:0" }, "operands": [ { "name": "rd'", "desc": "Dest/Source (x8-x15)" }, { "name": "imm", "desc": "Shift Amount" } ], "pseudocode": "R[rd'] = R[rd'] >> imm;", "example": "C.SRLI x8, 2", "example_note": "x8 = x8 >> 2", "description": "Logical right shift of rd′ by a 5-bit immediate." }, { "mnemonic": "C.SRAI", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed Shift Right Arithmetic Immediate", "summary": "Arithmetically shifts a register right by immediate.", "syntax": "C.SRAI rd', imm", "encoding": { "format": "CB", "binary_pattern": "? | 100 | c_nzuimm6hi | 01 | rd_rs1_p | c_nzuimm6lo | 01", "hex_opcode": "0x00008401", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "100", "clean": "100", "pos": "15:13" }, { "raw": "c_nzuimm6hi", "clean": "c_nzuimm6hi", "pos": "12" }, { "raw": "01", "clean": "01", "pos": "11:10" }, { "raw": "rd_rs1_p", "clean": "rd_rs1_p", "pos": "9:7" }, { "raw": "c_nzuimm6lo", "clean": "c_nzuimm6lo", "pos": "6:2" }, { "raw": "01", "clean": "01", "pos": "1:0" } ], "bit_positions": "31:16 | 15:13 | 12 | 11:10 | 9:7 | 6:2 | 1:0" }, "operands": [ { "name": "rd'", "desc": "Dest/Source" }, { "name": "imm", "desc": "Shift Amount" } ], "pseudocode": "R[rd'] = R[rd'] >>s imm;", "example": "C.SRAI x8, 2", "example_note": "x8 = x8 >>s 2", "description": "Arithmetic right shift of rd′ by a 5-bit immediate." }, { "mnemonic": "C.ANDI", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed AND Immediate", "summary": "Computes bitwise AND with a signed immediate.", "syntax": "C.ANDI rd', imm", "encoding": { "format": "CB", "binary_pattern": "? | 100 | c_imm6hi | 10 | rd_rs1_p | c_imm6lo | 01", "hex_opcode": "0x00008801", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "100", "clean": "100", "pos": "15:13" }, { "raw": "c_imm6hi", "clean": "c_imm6hi", "pos": "12" }, { "raw": "10", "clean": "10", "pos": "11:10" }, { "raw": "rd_rs1_p", "clean": "rd_rs1_p", "pos": "9:7" }, { "raw": "c_imm6lo", "clean": "c_imm6lo", "pos": "6:2" }, { "raw": "01", "clean": "01", "pos": "1:0" } ], "bit_positions": "31:16 | 15:13 | 12 | 11:10 | 9:7 | 6:2 | 1:0" }, "operands": [ { "name": "rd'", "desc": "Dest/Source" }, { "name": "imm", "desc": "Signed Imm" } ], "pseudocode": "R[rd'] = R[rd'] & sext(imm);", "example": "C.ANDI x8, 15", "example_note": "Keep lowest 4 bits.", "description": "Computes the bitwise AND of rd′ and a 6-bit sign-extended immediate." }, { "mnemonic": "C.SUB", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed Subtract", "summary": "Subtracts two registers.", "syntax": "C.SUB rd', rs2'", "encoding": { "format": "CA", "binary_pattern": "? | 100011 | rd_rs1_p | 00 | rs2_p | 01", "hex_opcode": "0x00008C01", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "100011", "clean": "100011", "pos": "15:10" }, { "raw": "rd_rs1_p", "clean": "rd_rs1_p", "pos": "9:7" }, { "raw": "00", "clean": "00", "pos": "6:5" }, { "raw": "rs2_p", "clean": "rs2_p", "pos": "4:2" }, { "raw": "01", "clean": "01", "pos": "1:0" } ], "bit_positions": "31:16 | 15:10 | 9:7 | 6:5 | 4:2 | 1:0" }, "operands": [ { "name": "rd'", "desc": "Dest/Src1" }, { "name": "rs2'", "desc": "Source register 2 (3-bit compressed)" } ], "pseudocode": "R[rd'] = R[rd'] - R[rs2'];", "example": "C.SUB x8, x9", "example_note": "x8 = x8 - x9", "description": "Subtracts rs2′ from rd′ and writes the result to rd′." }, { "mnemonic": "C.XOR", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed XOR", "summary": "Bitwise XOR of two registers.", "syntax": "C.XOR rd', rs2'", "encoding": { "format": "CA", "binary_pattern": "? | 100011 | rd_rs1_p | 01 | rs2_p | 01", "hex_opcode": "0x00008C21", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "100011", "clean": "100011", "pos": "15:10" }, { "raw": "rd_rs1_p", "clean": "rd_rs1_p", "pos": "9:7" }, { "raw": "01", "clean": "01", "pos": "6:5" }, { "raw": "rs2_p", "clean": "rs2_p", "pos": "4:2" }, { "raw": "01", "clean": "01", "pos": "1:0" } ], "bit_positions": "31:16 | 15:10 | 9:7 | 6:5 | 4:2 | 1:0" }, "operands": [ { "name": "rd'", "desc": "Dest/Src1" }, { "name": "rs2'", "desc": "Source register 2 (3-bit compressed)" } ], "pseudocode": "R[rd'] = R[rd'] ^ R[rs2'];", "example": "C.XOR x8, x9", "example_note": "x8 = x8 ^ x9", "description": "Computes the bitwise XOR of rd′ and rs2′, writing to rd′." }, { "mnemonic": "C.OR", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed OR", "summary": "Bitwise OR of two registers.", "syntax": "C.OR rd', rs2'", "encoding": { "format": "CA", "binary_pattern": "? | 100011 | rd_rs1_p | 10 | rs2_p | 01", "hex_opcode": "0x00008C41", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "100011", "clean": "100011", "pos": "15:10" }, { "raw": "rd_rs1_p", "clean": "rd_rs1_p", "pos": "9:7" }, { "raw": "10", "clean": "10", "pos": "6:5" }, { "raw": "rs2_p", "clean": "rs2_p", "pos": "4:2" }, { "raw": "01", "clean": "01", "pos": "1:0" } ], "bit_positions": "31:16 | 15:10 | 9:7 | 6:5 | 4:2 | 1:0" }, "operands": [ { "name": "rd'", "desc": "Dest/Src1" }, { "name": "rs2'", "desc": "Source register 2 (3-bit compressed)" } ], "pseudocode": "R[rd'] = R[rd'] | R[rs2'];", "example": "C.OR x8, x9", "example_note": "x8 = x8 | x9", "description": "Computes the bitwise OR of rd′ and rs2′, writing to rd′." }, { "mnemonic": "C.AND", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed AND", "summary": "Bitwise AND of two registers.", "syntax": "C.AND rd', rs2'", "encoding": { "format": "CA", "binary_pattern": "? | 100011 | rd_rs1_p | 11 | rs2_p | 01", "hex_opcode": "0x00008C61", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "100011", "clean": "100011", "pos": "15:10" }, { "raw": "rd_rs1_p", "clean": "rd_rs1_p", "pos": "9:7" }, { "raw": "11", "clean": "11", "pos": "6:5" }, { "raw": "rs2_p", "clean": "rs2_p", "pos": "4:2" }, { "raw": "01", "clean": "01", "pos": "1:0" } ], "bit_positions": "31:16 | 15:10 | 9:7 | 6:5 | 4:2 | 1:0" }, "operands": [ { "name": "rd'", "desc": "Dest/Src1" }, { "name": "rs2'", "desc": "Source register 2 (3-bit compressed)" } ], "pseudocode": "R[rd'] = R[rd'] & R[rs2'];", "example": "C.AND x8, x9", "example_note": "x8 = x8 & x9", "description": "Computes the bitwise AND of rd′ and rs2′, writing the result to rd′." }, { "mnemonic": "C.J", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed Jump", "summary": "Unconditional PC-relative jump.", "syntax": "C.J offset", "encoding": { "format": "CJ", "binary_pattern": "? | 101 | c_imm12 | 01", "hex_opcode": "0x0000A001", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "101", "clean": "101", "pos": "15:13" }, { "raw": "c_imm12", "clean": "c_imm12", "pos": "12:2" }, { "raw": "01", "clean": "01", "pos": "1:0" } ], "bit_positions": "31:16 | 15:13 | 12:2 | 1:0" }, "operands": [ { "name": "offset", "desc": "Target" } ], "pseudocode": "PC += sext(offset);", "example": "C.J label", "example_note": "Jump to label.", "description": "Performs an unconditional PC-relative jump within an 11-bit signed offset range." }, { "mnemonic": "C.BEQZ", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed Branch if Equal to Zero", "summary": "Branches if the register is zero.", "syntax": "C.BEQZ rs1', offset", "encoding": { "format": "CB", "binary_pattern": "? | 110 | c_bimm9hi | rs1_p | c_bimm9lo | 01", "hex_opcode": "0x0000C001", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "110", "clean": "110", "pos": "15:13" }, { "raw": "c_bimm9hi", "clean": "c_bimm9hi", "pos": "12:10" }, { "raw": "rs1_p", "clean": "rs1_p", "pos": "9:7" }, { "raw": "c_bimm9lo", "clean": "c_bimm9lo", "pos": "6:2" }, { "raw": "01", "clean": "01", "pos": "1:0" } ], "bit_positions": "31:16 | 15:13 | 12:10 | 9:7 | 6:2 | 1:0" }, "operands": [ { "name": "rs1'", "desc": "Source" }, { "name": "offset", "desc": "Target" } ], "pseudocode": "if (R[rs1'] == 0) PC += sext(offset);", "example": "C.BEQZ x8, exit", "example_note": "Jump if x8 is 0.", "description": "Branches to an 8-bit PC-relative offset if rs1′ equals zero." }, { "mnemonic": "C.BNEZ", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed Branch if Not Equal to Zero", "summary": "Branches if the register is not zero.", "syntax": "C.BNEZ rs1', offset", "encoding": { "format": "CB", "binary_pattern": "? | 111 | c_bimm9hi | rs1_p | c_bimm9lo | 01", "hex_opcode": "0x0000E001", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "111", "clean": "111", "pos": "15:13" }, { "raw": "c_bimm9hi", "clean": "c_bimm9hi", "pos": "12:10" }, { "raw": "rs1_p", "clean": "rs1_p", "pos": "9:7" }, { "raw": "c_bimm9lo", "clean": "c_bimm9lo", "pos": "6:2" }, { "raw": "01", "clean": "01", "pos": "1:0" } ], "bit_positions": "31:16 | 15:13 | 12:10 | 9:7 | 6:2 | 1:0" }, "operands": [ { "name": "rs1'", "desc": "Source" }, { "name": "offset", "desc": "Target" } ], "pseudocode": "if (R[rs1'] != 0) PC += sext(offset);", "example": "C.BNEZ x8, loop", "example_note": "Jump if x8 is not 0.", "description": "Branches to an 8-bit PC-relative offset if rs1′ is non-zero." }, { "mnemonic": "C.SLLI", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed Shift Left Logical Immediate", "summary": "Logically shifts a register left by immediate.", "syntax": "C.SLLI rd, imm", "encoding": { "format": "CI", "binary_pattern": "? | 000 | c_nzuimm6hi | rd_rs1_n0 | c_nzuimm6lo | 10", "hex_opcode": "0x00000002", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "000", "clean": "000", "pos": "15:13" }, { "raw": "c_nzuimm6hi", "clean": "c_nzuimm6hi", "pos": "12" }, { "raw": "rd_rs1_n0", "clean": "rd_rs1_n0", "pos": "11:7" }, { "raw": "c_nzuimm6lo", "clean": "c_nzuimm6lo", "pos": "6:2" }, { "raw": "10", "clean": "10", "pos": "1:0" } ], "bit_positions": "31:16 | 15:13 | 12 | 11:7 | 6:2 | 1:0" }, "operands": [ { "name": "rd", "desc": "Dest/Source" }, { "name": "imm", "desc": "Shift Amount" } ], "pseudocode": "R[rd] = R[rd] << imm;", "example": "C.SLLI x10, 2", "example_note": "x10 = x10 << 2", "description": "Logical left shift of rd (≠ x0) by a 5-bit (RV32) or 6-bit (RV64) immediate." }, { "mnemonic": "C.LWSP", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed Load Word from Stack Pointer", "summary": "Loads a word from the stack pointer (x2).", "syntax": "C.LWSP rd, offset(x2)", "encoding": { "format": "CI", "binary_pattern": "? | 010 | c_uimm8sphi | rd_n0 | c_uimm8splo | 10", "hex_opcode": "0x00004002", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "010", "clean": "010", "pos": "15:13" }, { "raw": "c_uimm8sphi", "clean": "c_uimm8sphi", "pos": "12" }, { "raw": "rd_n0", "clean": "rd_n0", "pos": "11:7" }, { "raw": "c_uimm8splo", "clean": "c_uimm8splo", "pos": "6:2" }, { "raw": "10", "clean": "10", "pos": "1:0" } ], "bit_positions": "31:16 | 15:13 | 12 | 11:7 | 6:2 | 1:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "offset", "desc": "Offset" } ], "pseudocode": "R[rd] = M[R[2] + offset][31:0];", "example": "C.LWSP x10, 4(x2)", "example_note": "Load from stack.", "description": "Loads a 32-bit word from a stack-pointer-relative address into rd." }, { "mnemonic": "C.SWSP", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed Store Word to Stack Pointer", "summary": "Stores a word to the stack pointer (x2).", "syntax": "C.SWSP rs2, offset(x2)", "encoding": { "format": "CSS", "binary_pattern": "? | 110 | c_uimm8sp_s | c_rs2 | 10", "hex_opcode": "0x0000C002", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "110", "clean": "110", "pos": "15:13" }, { "raw": "c_uimm8sp_s", "clean": "c_uimm8sp_s", "pos": "12:7" }, { "raw": "c_rs2", "clean": "c_rs2", "pos": "6:2" }, { "raw": "10", "clean": "10", "pos": "1:0" } ], "bit_positions": "31:16 | 15:13 | 12:7 | 6:2 | 1:0" }, "operands": [ { "name": "rs2", "desc": "Source" }, { "name": "offset", "desc": "Offset" } ], "pseudocode": "M[R[2] + offset][31:0] = R[rs2];", "example": "C.SWSP x10, 8(x2)", "example_note": "Store to stack.", "description": "Stores the low 32 bits of rs2 to a stack-pointer-relative address." }, { "mnemonic": "C.JR", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed Jump Register", "summary": "Unconditionally jumps to address in register.", "syntax": "C.JR rs1", "encoding": { "format": "CR", "binary_pattern": "? | 1000 | rs1_n0 | 0000010", "hex_opcode": "0x00008002", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "1000", "clean": "1000", "pos": "15:12" }, { "raw": "rs1_n0", "clean": "rs1_n0", "pos": "11:7" }, { "raw": "0000010", "clean": "0000010", "pos": "6:0" } ], "bit_positions": "31:16 | 15:12 | 11:7 | 6:0" }, "operands": [ { "name": "rs1", "desc": "Address" } ], "pseudocode": "PC = R[rs1];", "example": "C.JR x1", "example_note": "Return (if x1 is ra).", "description": "Jumps to the address in rs1 without linking." }, { "mnemonic": "C.MV", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed Move", "summary": "Copies register rs2 to rd.", "syntax": "C.MV rd, rs2", "encoding": { "format": "CR", "binary_pattern": "? | 1000 | rd_n0 | c_rs2_n0 | 10", "hex_opcode": "0x00008002", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "1000", "clean": "1000", "pos": "15:12" }, { "raw": "rd_n0", "clean": "rd_n0", "pos": "11:7" }, { "raw": "c_rs2_n0", "clean": "c_rs2_n0", "pos": "6:2" }, { "raw": "10", "clean": "10", "pos": "1:0" } ], "bit_positions": "31:16 | 15:12 | 11:7 | 6:2 | 1:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs2", "desc": "Source" } ], "pseudocode": "R[rd] = R[rs2];", "example": "C.MV x10, x11", "example_note": "Copy x11 to x10.", "description": "Copies the value of rs2 (≠ x0) to rd (≠ x0). Equivalent to C.ADD rd, x0, rs2." }, { "mnemonic": "C.EBREAK", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed Environment Break", "summary": "Triggers a debugger breakpoint.", "syntax": "C.EBREAK", "encoding": { "format": "CR", "binary_pattern": "? | 1001000000000010", "hex_opcode": "0x00009002", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "1001000000000010", "clean": "1001000000000010", "pos": "15:0" } ], "bit_positions": "31:16 | 15:0" }, "operands": [], "pseudocode": "RaiseException(Breakpoint);", "example": "C.EBREAK", "example_note": "Break.", "description": "Causes a breakpoint exception. 16-bit encoding of EBREAK." }, { "mnemonic": "C.JALR", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed Jump and Link Register", "summary": "Jumps to register address and links (saves PC+2 to ra).", "syntax": "C.JALR rs1", "encoding": { "format": "CR", "binary_pattern": "? | 1001 | c_rs1_n0 | 0000010", "hex_opcode": "0x00009002", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "1001", "clean": "1001", "pos": "15:12" }, { "raw": "c_rs1_n0", "clean": "c_rs1_n0", "pos": "11:7" }, { "raw": "0000010", "clean": "0000010", "pos": "6:0" } ], "bit_positions": "31:16 | 15:12 | 11:7 | 6:0" }, "operands": [ { "name": "rs1", "desc": "Address" } ], "pseudocode": "t = PC + 2; PC = R[rs1]; R[1] = t;", "example": "C.JALR x10", "example_note": "Call function pointer in x10.", "description": "Jumps to address in rs1 and saves PC+2 in x1." }, { "mnemonic": "C.ADD", "architecture": "RISC-V", "extension": "C", "full_name": "Compressed Add", "summary": "Adds two registers.", "syntax": "C.ADD rd, rs2", "encoding": { "format": "CR", "binary_pattern": "? | 1001 | rd_rs1_n0 | c_rs2_n0 | 10", "hex_opcode": "0x00009002", "visual_parts": [ { "raw": "?", "clean": "?", "pos": "31:16" }, { "raw": "1001", "clean": "1001", "pos": "15:12" }, { "raw": "rd_rs1_n0", "clean": "rd_rs1_n0", "pos": "11:7" }, { "raw": "c_rs2_n0", "clean": "c_rs2_n0", "pos": "6:2" }, { "raw": "10", "clean": "10", "pos": "1:0" } ], "bit_positions": "31:16 | 15:12 | 11:7 | 6:2 | 1:0" }, "operands": [ { "name": "rd", "desc": "Dest/Src1" }, { "name": "rs2", "desc": "Source register 2 (integer)" } ], "pseudocode": "R[rd] = R[rd] + R[rs2];", "example": "C.ADD x10, x11", "example_note": "x10 = x10 + x11", "description": "Adds the value of a register to rd/rs1 and writes the result back to rd. 16-bit encoding of ADD." }, { "mnemonic": "BEQ", "architecture": "RISC-V", "full_name": "Branch if Equal", "summary": "Take the branch if registers rs1 and rs2 are equal.", "syntax": "BEQ rs1, rs2, offset", "encoding": { "format": "B-Type", "binary_pattern": "bimm12hi | rs2 | rs1 | 000 | bimm12lo | 1100011", "hex_opcode": "0x00000063", "visual_parts": [ { "raw": "bimm12hi", "clean": "bimm12hi", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "bimm12lo", "clean": "bimm12lo", "pos": "11:7" }, { "raw": "1100011", "clean": "1100011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" }, { "name": "offset", "desc": "PC-relative offset" } ], "pseudocode": "if (R[rs1] == R[rs2]) PC += sext(offset);", "example": "BEQ x5, x6, 100", "example_note": "Jump to PC+100 if x5 == x6.", "extension": "RV32I", "description": "BEQ takes the branch if rs1 equals rs2. The branch target is the PC of the branch plus the sign-extended B-immediate, which encodes an offset in multiples of 2 bytes within a ±4 KiB range." }, { "mnemonic": "BNE", "architecture": "RISC-V", "full_name": "Branch if Not Equal", "summary": "Take the branch if registers rs1 and rs2 are not equal.", "syntax": "BNE rs1, rs2, offset", "encoding": { "format": "B-Type", "binary_pattern": "bimm12hi | rs2 | rs1 | 001 | bimm12lo | 1100011", "hex_opcode": "0x00001063", "visual_parts": [ { "raw": "bimm12hi", "clean": "bimm12hi", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "bimm12lo", "clean": "bimm12lo", "pos": "11:7" }, { "raw": "1100011", "clean": "1100011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" }, { "name": "offset", "desc": "PC-relative offset" } ], "pseudocode": "if (R[rs1] != R[rs2]) PC += sext(offset);", "example": "BNE x5, x6, loop", "example_note": "Jump to 'loop' if x5 != x6.", "extension": "RV32I", "description": "BNE takes the branch if rs1 is not equal to rs2. The branch target is the PC of the branch plus the sign-extended B-immediate within a ±4 KiB range." }, { "mnemonic": "BLT", "architecture": "RISC-V", "full_name": "Branch if Less Than", "summary": "Take the branch if rs1 is less than rs2 (signed).", "syntax": "BLT rs1, rs2, offset", "encoding": { "format": "B-Type", "binary_pattern": "bimm12hi | rs2 | rs1 | 100 | bimm12lo | 1100011", "hex_opcode": "0x00004063", "visual_parts": [ { "raw": "bimm12hi", "clean": "bimm12hi", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "100", "clean": "100", "pos": "14:12" }, { "raw": "bimm12lo", "clean": "bimm12lo", "pos": "11:7" }, { "raw": "1100011", "clean": "1100011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" }, { "name": "offset", "desc": "Offset" } ], "pseudocode": "if (R[rs1] =s R[rs2]) PC += sext(offset);", "example": "BGE x10, x0, positive", "example_note": "Branch if x10 is positive or zero.", "extension": "RV32I", "description": "BGE takes the branch if rs1 is greater than or equal to rs2, using a signed comparison. The branch target is the PC plus the sign-extended B-immediate." }, { "mnemonic": "CSRRW", "architecture": "RISC-V", "extension": "Zicsr", "full_name": "Control Status Register Read/Write", "summary": "Atomically swaps values in the CSRs. Reads the old value of the CSR into rd, then writes rs1 to the CSR.", "syntax": "CSRRW rd, csr, rs1", "encoding": { "format": "I-Type", "binary_pattern": "csr | rs1 | 001 | rd | 1110011", "hex_opcode": "0x00001073", "visual_parts": [ { "raw": "csr", "clean": "csr", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1110011", "clean": "1110011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Old Value)" }, { "name": "csr", "desc": "CSR Address" }, { "name": "rs1", "desc": "Src (New Value)" } ], "pseudocode": "t = CSRs[csr]; CSRs[csr] = R[rs1]; R[rd] = t;", "example": "CSRRW x10, scause, x11", "example_note": "Writes x11 to 'scause' CSR and reads old 'scause' into x10.", "description": "CSRRW atomically reads the value of CSR csr into rd, then writes the value from rs1 into the CSR. If rd is x0, the read is skipped and no side-effects from reading occur." }, { "mnemonic": "CSRRS", "architecture": "RISC-V", "extension": "Zicsr", "full_name": "Control Status Register Read and Set", "summary": "Reads the value of the CSR into rd, then bitwise ORs the value in rs1 into the CSR (setting bits).", "syntax": "CSRRS rd, csr, rs1", "encoding": { "format": "I-Type", "binary_pattern": "csr | rs1 | 010 | rd | 1110011", "hex_opcode": "0x00002073", "visual_parts": [ { "raw": "csr", "clean": "csr", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1110011", "clean": "1110011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "csr", "desc": "CSR Address" }, { "name": "rs1", "desc": "Bit Mask" } ], "pseudocode": "t = CSRs[csr]; CSRs[csr] = t | R[rs1]; R[rd] = t;", "example": "CSRRS x0, sstatus, x5", "example_note": "Sets bits in 'sstatus' using mask in x5 (Result discarded).", "description": "CSRRS atomically reads CSR csr into rd, then sets the bits in the CSR that correspond to bits set in rs1. If rs1 is x0, no bits are modified." }, { "mnemonic": "DIV", "architecture": "RISC-V", "extension": "M", "full_name": "Divide", "summary": "Performs signed integer division.", "syntax": "DIV rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000001 | rs2 | rs1 | 100 | rd | 0110011", "hex_opcode": "0x02004033", "visual_parts": [ { "raw": "0000001", "clean": "0000001", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "100", "clean": "100", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Quotient)" }, { "name": "rs1", "desc": "Dividend" }, { "name": "rs2", "desc": "Divisor" } ], "pseudocode": "R[rd] = R[rs1] / R[rs2];", "example": "DIV x10, x11, x12", "example_note": "Signed division of x11 by x12.", "description": "DIV divides rs1 by rs2 using signed division and writes the quotient to rd, truncated toward zero. Division by zero yields -1; overflow (INT_MIN ÷ -1) yields INT_MIN." }, { "mnemonic": "DIVU", "architecture": "RISC-V", "extension": "M", "full_name": "Divide Unsigned", "summary": "Performs unsigned integer division.", "syntax": "DIVU rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000001 | rs2 | rs1 | 101 | rd | 0110011", "hex_opcode": "0x02005033", "visual_parts": [ { "raw": "0000001", "clean": "0000001", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "101", "clean": "101", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Dividend" }, { "name": "rs2", "desc": "Divisor" } ], "pseudocode": "R[rd] = R[rs1] /u R[rs2];", "example": "DIVU x5, x6, x7", "example_note": "Unsigned division.", "description": "DIVU divides rs1 by rs2 using unsigned division and writes the quotient to rd, truncated toward zero. Division by zero yields 2^XLEN - 1." }, { "mnemonic": "EBREAK", "architecture": "RISC-V", "full_name": "Environment Break", "summary": "Used by debuggers to cause control to be transferred back to a debugging environment.", "syntax": "EBREAK", "encoding": { "format": "I-Type", "binary_pattern": "00000000000100000000000001110011", "hex_opcode": "0x00100073", "visual_parts": [ { "raw": "00000000000100000000000001110011", "clean": "00000000000100000000000001110011", "pos": "31:0" } ], "bit_positions": "31:0" }, "operands": [], "pseudocode": "RaiseException(Breakpoint);", "example": "EBREAK", "example_note": "Triggers a debugger breakpoint.", "extension": "RV32I", "description": "EBREAK causes a breakpoint exception to be raised, intended for use by debuggers. Execution is transferred to the appropriate trap handler." }, { "mnemonic": "FENCE", "architecture": "RISC-V", "full_name": "Fence", "summary": "Orders device I/O and memory accesses.", "syntax": "FENCE pred, succ", "encoding": { "format": "I-Type", "binary_pattern": "fm | pred | succ | rs1 | 000 | rd | 0001111", "hex_opcode": "0x0000000F", "visual_parts": [ { "raw": "fm", "clean": "fm", "pos": "31:28" }, { "raw": "pred", "clean": "pred", "pos": "27:24" }, { "raw": "succ", "clean": "succ", "pos": "23:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0001111", "clean": "0001111", "pos": "6:0" } ], "bit_positions": "31:28 | 27:24 | 23:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "pred", "desc": "Predecessor Set" }, { "name": "succ", "desc": "Successor Set" } ], "pseudocode": "MemoryBarrier(pred, succ);", "example": "FENCE rw, rw", "example_note": "Ensures all previous reads/writes complete before subsequent reads/writes.", "extension": "RV32I", "description": "FENCE orders device I/O and memory accesses as viewed by other RISC-V harts and external devices. The predecessor and successor sets of operations are specified by the pred and succ fields. FENCE with all fields zero is a full memory fence." }, { "mnemonic": "FLW", "architecture": "RISC-V", "extension": "F", "full_name": "Float Load Word", "summary": "Loads a single-precision floating-point value from memory.", "syntax": "FLW rd, offset(rs1)", "encoding": { "format": "I-Type", "binary_pattern": "imm12 | rs1 | 010 | rd | 0000111", "hex_opcode": "0x00002007", "visual_parts": [ { "raw": "imm12", "clean": "imm12", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0000111", "clean": "0000111", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Float Reg)" }, { "name": "rs1", "desc": "Base Address" }, { "name": "offset", "desc": "Offset" } ], "pseudocode": "F[rd] = M[R[rs1] + sext(offset)][31:0];", "example": "FLW f1, 0(x10)", "example_note": "Loads float from address in x10 to f1.", "description": "Loads a 32-bit word from memory at address rs1+sext(offset) into floating-point register rd." }, { "mnemonic": "FSW", "architecture": "RISC-V", "extension": "F", "full_name": "Float Store Word", "summary": "Stores a single-precision floating-point value to memory.", "syntax": "FSW rs2, offset(rs1)", "encoding": { "format": "S-Type", "binary_pattern": "imm12hi | rs2 | rs1 | 010 | imm12lo | 0100111", "hex_opcode": "0x00002027", "visual_parts": [ { "raw": "imm12hi", "clean": "imm12hi", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "imm12lo", "clean": "imm12lo", "pos": "11:7" }, { "raw": "0100111", "clean": "0100111", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rs2", "desc": "Src (Float Reg)" }, { "name": "rs1", "desc": "Base Address" }, { "name": "offset", "desc": "Offset" } ], "pseudocode": "M[R[rs1] + sext(offset)] = F[rs2][31:0];", "example": "FSW f1, 4(x2)", "example_note": "Stores float in f1 to stack + 4.", "description": "Stores a floating-point register to memory at address rs1+sext(offset)." }, { "mnemonic": "FADD.S", "architecture": "RISC-V", "extension": "F", "full_name": "Float Add (Single)", "summary": "Performs single-precision floating-point addition.", "syntax": "FADD.S rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000000 | rs2 | rs1 | rm | rd | 1010011", "hex_opcode": "0x00000053", "visual_parts": [ { "raw": "0000000", "clean": "0000000", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "rm", "clean": "rm", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "1010011", "clean": "1010011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" } ], "pseudocode": "F[rd] = F[rs1] + F[rs2];", "example": "FADD.S f0, f1, f2", "example_note": "f0 = f1 + f2", "description": "Performs single-precision (32-bit) floating-point addition. The operation adds the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008." }, { "mnemonic": "MUL", "architecture": "RISC-V", "extension": "M", "full_name": "Multiply", "summary": "Performs a 32-bit (or 64-bit) multiplication of rs1 and rs2 and stores the lower bits in rd.", "syntax": "MUL rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000001 | rs2 | rs1 | 000 | rd | 0110011", "hex_opcode": "0x02000033", "visual_parts": [ { "raw": "0000001", "clean": "0000001", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Lower Bits)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" } ], "pseudocode": "R[rd] = (R[rs1] * R[rs2])[XLEN-1:0];", "example": "MUL x10, x11, x12", "example_note": "x10 = lower bits of x11 * x12.", "description": "MUL performs an XLEN-bit × XLEN-bit multiplication of rs1 and rs2 and writes the lower XLEN bits of the product to rd. Both operands are treated as signed or unsigned (the result is the same for the low bits)." }, { "mnemonic": "MULH", "architecture": "RISC-V", "extension": "M", "full_name": "Multiply High Signed", "summary": "Performs a signed multiplication and stores the upper bits of the result.", "syntax": "MULH rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000001 | rs2 | rs1 | 001 | rd | 0110011", "hex_opcode": "0x02001033", "visual_parts": [ { "raw": "0000001", "clean": "0000001", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Upper Bits)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" } ], "pseudocode": "R[rd] = (sext(R[rs1]) * sext(R[rs2])) >> XLEN;", "example": "MULH x5, x6, x7", "example_note": "Get upper bits of signed multiplication.", "description": "MULH multiplies rs1 and rs2 as signed values and writes the upper XLEN bits of the 2×XLEN-bit product to rd." }, { "mnemonic": "MRET", "architecture": "RISC-V", "extension": "Privileged", "full_name": "Machine Return", "summary": "Returns from a machine-mode trap handler.", "syntax": "MRET", "encoding": { "format": "R-Type (System)", "binary_pattern": "00110000001000000000000001110011", "hex_opcode": "0x30200073", "visual_parts": [ { "raw": "00110000001000000000000001110011", "clean": "00110000001000000000000001110011", "pos": "31:0" } ], "bit_positions": "31:0" }, "operands": [], "pseudocode": "PC = MEPC; Priv = MPP; MIE = MPIE;", "example": "MRET", "example_note": "Return to previous privilege level defined in mstatus.", "description": "MRET returns from a machine-level trap. It restores the PC from mepc, restores privilege from the MPP field of mstatus, and updates interrupt-enable and privilege fields in mstatus." }, { "mnemonic": "OR", "architecture": "RISC-V", "full_name": "Logical OR", "summary": "Performs a bitwise logical OR operation.", "syntax": "OR rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000000 | rs2 | rs1 | 110 | rd | 0110011", "hex_opcode": "0x00006033", "visual_parts": [ { "raw": "0000000", "clean": "0000000", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "110", "clean": "110", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" } ], "pseudocode": "R[rd] = R[rs1] | R[rs2];", "example": "OR x10, x11, x12", "example_note": "Bitwise OR of x11 and x12.", "extension": "RV32I", "description": "OR performs a bitwise logical OR of the values in rs1 and rs2, writing the result to rd." }, { "mnemonic": "ORI", "architecture": "RISC-V", "full_name": "Logical OR Immediate", "summary": "Performs a bitwise logical OR with a sign-extended immediate.", "syntax": "ORI rd, rs1, imm", "encoding": { "format": "I-Type", "binary_pattern": "imm12 | rs1 | 110 | rd | 0010011", "hex_opcode": "0x00006013", "visual_parts": [ { "raw": "imm12", "clean": "imm12", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "110", "clean": "110", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0010011", "clean": "0010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source" }, { "name": "imm", "desc": "Signed immediate value" } ], "pseudocode": "R[rd] = R[rs1] | sext(imm);", "example": "ORI x10, x11, 1", "example_note": "Sets the lowest bit of x11.", "extension": "RV32I", "description": "ORI performs a bitwise OR of register rs1 with the sign-extended 12-bit immediate, writing the result to rd." }, { "mnemonic": "REM", "architecture": "RISC-V", "extension": "M", "full_name": "Remainder", "summary": "Computes the signed remainder of division.", "syntax": "REM rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000001 | rs2 | rs1 | 110 | rd | 0110011", "hex_opcode": "0x02006033", "visual_parts": [ { "raw": "0000001", "clean": "0000001", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "110", "clean": "110", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Remainder)" }, { "name": "rs1", "desc": "Dividend" }, { "name": "rs2", "desc": "Divisor" } ], "pseudocode": "R[rd] = R[rs1] % R[rs2];", "example": "REM x5, x6, x7", "example_note": "Signed remainder.", "description": "REM computes the signed remainder of rs1 ÷ rs2, writing the result to rd. The sign of the result equals the sign of the dividend (rs1). Remainder by zero yields the dividend; overflow (INT_MIN % -1) yields zero." }, { "mnemonic": "SB", "architecture": "RISC-V", "full_name": "Store Byte", "summary": "Stores the lowest 8 bits of a register to memory.", "syntax": "SB rs2, offset(rs1)", "encoding": { "format": "S-Type", "binary_pattern": "imm12hi | rs2 | rs1 | 000 | imm12lo | 0100011", "hex_opcode": "0x00000023", "visual_parts": [ { "raw": "imm12hi", "clean": "imm12hi", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "imm12lo", "clean": "imm12lo", "pos": "11:7" }, { "raw": "0100011", "clean": "0100011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rs2", "desc": "Source" }, { "name": "rs1", "desc": "Base Address" }, { "name": "offset", "desc": "Offset" } ], "pseudocode": "M[R[rs1] + sext(offset)][7:0] = R[rs2][7:0];", "example": "SB x5, 0(x10)", "example_note": "Store low byte of x5 to address in x10.", "extension": "RV32I", "description": "SB stores the least-significant byte of rs2 to memory at address rs1+sext(offset)." }, { "mnemonic": "SH", "architecture": "RISC-V", "full_name": "Store Halfword", "summary": "Stores the lowest 16 bits of a register to memory.", "syntax": "SH rs2, offset(rs1)", "encoding": { "format": "S-Type", "binary_pattern": "imm12hi | rs2 | rs1 | 001 | imm12lo | 0100011", "hex_opcode": "0x00001023", "visual_parts": [ { "raw": "imm12hi", "clean": "imm12hi", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "imm12lo", "clean": "imm12lo", "pos": "11:7" }, { "raw": "0100011", "clean": "0100011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rs2", "desc": "Source" }, { "name": "rs1", "desc": "Base Address" }, { "name": "offset", "desc": "Offset" } ], "pseudocode": "M[R[rs1] + sext(offset)][15:0] = R[rs2][15:0];", "example": "SH x5, 4(x10)", "example_note": "Store halfword.", "extension": "RV32I", "description": "SH stores the least-significant halfword (16 bits) of rs2 to memory at address rs1+sext(offset)." }, { "mnemonic": "SW", "architecture": "RISC-V", "full_name": "Store Word", "summary": "Stores a 32-bit word to memory.", "syntax": "SW rs2, offset(rs1)", "encoding": { "format": "S-Type", "binary_pattern": "imm12hi | rs2 | rs1 | 010 | imm12lo | 0100011", "hex_opcode": "0x00002023", "visual_parts": [ { "raw": "imm12hi", "clean": "imm12hi", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "imm12lo", "clean": "imm12lo", "pos": "11:7" }, { "raw": "0100011", "clean": "0100011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rs2", "desc": "Source" }, { "name": "rs1", "desc": "Base Address" }, { "name": "offset", "desc": "Offset" } ], "pseudocode": "M[R[rs1] + sext(offset)][31:0] = R[rs2][31:0];", "example": "SW x5, 8(x10)", "example_note": "Store word.", "extension": "RV32I", "description": "SW stores the least-significant 32-bit word of rs2 to memory at address rs1+sext(offset)." }, { "mnemonic": "SD", "architecture": "RISC-V", "extension": "RV64I", "full_name": "Store Doubleword", "summary": "Stores a 64-bit doubleword to memory.", "syntax": "SD rs2, offset(rs1)", "encoding": { "format": "S-Type", "binary_pattern": "imm12hi | rs2 | rs1 | 011 | imm12lo | 0100011", "hex_opcode": "0x00003023", "visual_parts": [ { "raw": "imm12hi", "clean": "imm12hi", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "011", "clean": "011", "pos": "14:12" }, { "raw": "imm12lo", "clean": "imm12lo", "pos": "11:7" }, { "raw": "0100011", "clean": "0100011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rs2", "desc": "Source" }, { "name": "rs1", "desc": "Base Address" }, { "name": "offset", "desc": "Offset" } ], "pseudocode": "M[R[rs1] + sext(offset)][63:0] = R[rs2][63:0];", "example": "SD x5, 16(x10)", "example_note": "Store 64-bit value.", "description": "SD stores the 64-bit doubleword in rs2 to memory at address rs1+sext(offset)." }, { "mnemonic": "SLL", "architecture": "RISC-V", "full_name": "Shift Left Logical", "summary": "Shifts a register left by the number of bits specified in another register.", "syntax": "SLL rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000000 | rs2 | rs1 | 001 | rd | 0110011", "hex_opcode": "0x00001033", "visual_parts": [ { "raw": "0000000", "clean": "0000000", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source" }, { "name": "rs2", "desc": "Shift Amount" } ], "pseudocode": "R[rd] = R[rs1] << (R[rs2] & 0x1F);", "example": "SLL x10, x11, x12", "example_note": "Shift x11 left by x12.", "extension": "RV32I", "description": "SLL performs a logical left shift of the value in rs1 by the shift amount held in the lower 5 bits of rs2 (or 6 bits in RV64I), writing the result to rd. Zeros are shifted into the low-order bits." }, { "mnemonic": "SLLI", "architecture": "RISC-V", "full_name": "Shift Left Logical Immediate", "summary": "Shifts a register left by a constant amount.", "syntax": "SLLI rd, rs1, shamt", "encoding": { "format": "I-Type (Shift)", "binary_pattern": "000000 | shamtd | rs1 | 001 | rd | 0010011", "hex_opcode": "0x00001013", "visual_parts": [ { "raw": "000000", "clean": "000000", "pos": "31:26" }, { "raw": "shamtd", "clean": "shamtd", "pos": "25:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "001", "clean": "001", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0010011", "clean": "0010011", "pos": "6:0" } ], "bit_positions": "31:26 | 25:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source" }, { "name": "shamt", "desc": "Shift Amount" } ], "pseudocode": "R[rd] = R[rs1] << shamt;", "example": "SLLI x10, x11, 2", "example_note": "Multiply x11 by 4.", "extension": "RV32I", "description": "SLLI is a logical left shift by the constant encoded in the immediate field. The shift amount is the lower 5 bits (RV32I) or 6 bits (RV64I) of the immediate. Zeros are shifted into low-order bits." }, { "mnemonic": "SRL", "architecture": "RISC-V", "full_name": "Shift Right Logical", "summary": "Shifts a register right, shifting in zeros.", "syntax": "SRL rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000000 | rs2 | rs1 | 101 | rd | 0110011", "hex_opcode": "0x00005033", "visual_parts": [ { "raw": "0000000", "clean": "0000000", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "101", "clean": "101", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source" }, { "name": "rs2", "desc": "Shift Amount" } ], "pseudocode": "R[rd] = R[rs1] >> (R[rs2] & 0x1F);", "example": "SRL x10, x11, x12", "example_note": "Logical right shift.", "extension": "RV32I", "description": "SRL performs a logical right shift of the value in rs1 by the shift amount held in the lower 5 bits of rs2 (or 6 bits in RV64I), writing the result to rd. Zeros are shifted into the high-order bits." }, { "mnemonic": "SRA", "architecture": "RISC-V", "full_name": "Shift Right Arithmetic", "summary": "Shifts a register right, preserving the sign bit.", "syntax": "SRA rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0100000 | rs2 | rs1 | 101 | rd | 0110011", "hex_opcode": "0x40005033", "visual_parts": [ { "raw": "0100000", "clean": "0100000", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "101", "clean": "101", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source" }, { "name": "rs2", "desc": "Shift Amount" } ], "pseudocode": "R[rd] = R[rs1] >>s (R[rs2] & 0x1F);", "example": "SRA x10, x11, x12", "example_note": "Arithmetic right shift (sign preserved).", "extension": "RV32I", "description": "SRA performs an arithmetic right shift of the value in rs1 by the shift amount held in the lower 5 bits of rs2 (or 6 bits in RV64I), writing the result to rd. The original sign bit is copied into the vacated upper bits." }, { "mnemonic": "SLT", "architecture": "RISC-V", "full_name": "Set Less Than", "summary": "Sets rd to 1 if rs1 < rs2 (signed), otherwise 0.", "syntax": "SLT rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000000 | rs2 | rs1 | 010 | rd | 0110011", "hex_opcode": "0x00002033", "visual_parts": [ { "raw": "0000000", "clean": "0000000", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination register (integer)" }, { "name": "rs1", "desc": "Source register 1 (integer)" }, { "name": "rs2", "desc": "Source register 2 (integer)" } ], "pseudocode": "R[rd] = (R[rs1] vs1.", "syntax": "VMSGT.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "011011 | vm | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0x6C000057", "visual_parts": [ { "raw": "011111", "clean": "011111", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Mask" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "vd = (vs2 > vs1);", "description": "Compares elements element-wise for greater than and writes a mask result to vd.", "example": "VMSGT.VV v1, v4, v2, v0.t" }, { "mnemonic": "VMSGTU.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Mask Set Greater Than (Unsigned)", "summary": "Sets mask if vs2 > vs1 (Unsigned).", "syntax": "VMSGTU.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "011010 | vm | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0x68000057", "visual_parts": [ { "raw": "011111", "clean": "011111", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Mask" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "vd = (vs2 >u vs1);", "description": "Compares elements element-wise for greater than and writes a mask result to vd.", "example": "VMSGTU.VV v1, v4, v2, v0.t" }, { "mnemonic": "VMSLE.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Mask Set Less or Equal (Signed)", "summary": "Sets mask if vs2 <= vs1.", "syntax": "VMSLE.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "011101 | vm | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0x74000057", "visual_parts": [ { "raw": "011101", "clean": "011101", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Mask" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "vd = (vs2 <= vs1);", "description": "Compares elements element-wise for less than or equal and writes a mask result to vd.", "example": "VMSLE.VV v1, v4, v2, v0.t" }, { "mnemonic": "VMSLEU.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Mask Set Less or Equal (Unsigned)", "summary": "Sets mask if vs2 <= vs1 (Unsigned).", "syntax": "VMSLEU.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "011100 | vm | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0x70000057", "visual_parts": [ { "raw": "011100", "clean": "011100", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Mask" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "vd = (vs2 <=u vs1);", "description": "Compares elements element-wise for less than or equal and writes a mask result to vd.", "example": "VMSLEU.VV v1, v4, v2, v0.t" }, { "mnemonic": "VMSGE.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Mask Set Greater or Equal (Signed)", "summary": "Sets mask if vs2 >= vs1.", "syntax": "VMSGE.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "011101 | vm | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0x74000057", "visual_parts": [ { "raw": "011111", "clean": "011111", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Mask" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "vd = (vs2 >= vs1);", "description": "Compares elements element-wise for greater than or equal and writes a mask result to vd.", "example": "VMSGE.VV v1, v4, v2, v0.t" }, { "mnemonic": "VMSGEU.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Mask Set Greater or Equal (Unsigned)", "summary": "Sets mask if vs2 >= vs1 (Unsigned).", "syntax": "VMSGEU.VV vd, vs2, vs1, vm", "encoding": { "format": "OPIVV", "binary_pattern": "011100 | vm | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0x70000057", "visual_parts": [ { "raw": "011111", "clean": "011111", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Mask" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "vd = (vs2 >=u vs1);", "description": "Compares elements element-wise for greater than or equal and writes a mask result to vd.", "example": "VMSGEU.VV v1, v4, v2, v0.t" }, { "mnemonic": "VMADC.VIM", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Mask Add with Carry Immediate", "summary": "Add Immediate with Carry.", "syntax": "VMADC.VIM vd, vs2, imm, v0", "encoding": { "format": "OPIVI", "binary_pattern": "0100010 | vs2 | simm5 | 011 | vd | 1010111", "hex_opcode": "0x44003057", "visual_parts": [ { "raw": "0100010", "clean": "0100010", "pos": "31:25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "simm5", "clean": "simm5", "pos": "19:15" }, { "raw": "011", "clean": "011", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Carry Out" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "imm", "desc": "Imm" } ], "pseudocode": "vd = carry(vs2 + imm + v0);", "description": "Vector Mask Add with Carry Immediate: Add Immediate with Carry. Operation: vd = carry(vs2 + imm + v0);.", "example": "VMADC.VIM v1, v4, 16, v0" }, { "mnemonic": "VWMACCSU.VV", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Widening MAC (Signed * Unsigned)", "summary": "vd = vd + (signed(vs1) * unsigned(vs2)).", "syntax": "VWMACCSU.VV vd, vs1, vs2, vm", "encoding": { "format": "OPIVV", "binary_pattern": "111111 | vm | vs2 | vs1 | 010 | vd | 1010111", "hex_opcode": "0xFC002057", "visual_parts": [ { "raw": "111111", "clean": "111111", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Acc" }, { "name": "vs1", "desc": "Signed" }, { "name": "vs2", "desc": "Unsigned" } ], "pseudocode": "vd += sext(vs1) * zext(vs2);", "description": "Performs a widening operation, producing results twice as wide as the source elements. Results are written to vd using 2× the element grouping (EEW). The number of elements and masking are governed by vl and vm.", "example": "VWMACCSU.VV v1, v2, v4, v0.t" }, { "mnemonic": "VWMACCUS.VX", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Widening MAC (Unsigned * Signed)", "summary": "vd = vd + (unsigned(vs1) * signed(vs2)).", "syntax": "VWMACCUS.VX vd, rs1, vs2, vm", "encoding": { "format": "OPMVX", "binary_pattern": "111110 | vm | vs2 | rs1 | 110 | vd | 1010111", "hex_opcode": "0xF8006057", "visual_parts": [ { "raw": "111110", "clean": "111110", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Acc" }, { "name": "vs1", "desc": "Unsigned" }, { "name": "vs2", "desc": "Signed" } ], "pseudocode": "vd += zext(vs1) * sext(vs2);", "description": "Performs a widening operation, producing results twice as wide as the source elements. Results are written to vd using 2× the element grouping (EEW). The number of elements and masking are governed by vl and vm.", "example": "VWMACCUS.VX v1, x10, v2, v0.t" }, { "mnemonic": "VADC.VVM", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Add with Carry", "summary": "Computes vd = vs1 + vs2 + carry (v0).", "syntax": "VADC.VVM vd, vs2, vs1, v0", "encoding": { "format": "OPIVV", "binary_pattern": "0100000 | vs2 | vs1 | 000 | vd | 1010111", "hex_opcode": "0x40000057", "visual_parts": [ { "raw": "0100000", "clean": "0100000", "pos": "31:25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "vs1", "clean": "vs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "vs1", "desc": "Source vector register 1" } ], "pseudocode": "vd = vs1 + vs2 + v0;", "description": "Vector Add with Carry: Computes vd = vs1 + vs2 + carry (v0). Operation: vd = vs1 + vs2 + v0;.", "example": "VADC.VVM v1, v4, v2, v0" }, { "mnemonic": "VADD.VI", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Add Immediate", "summary": "Adds immediate to vector.", "syntax": "VADD.VI vd, vs2, imm, vm", "encoding": { "format": "OPIVI", "binary_pattern": "000000 | vm | vs2 | simm5 | 011 | vd | 1010111", "hex_opcode": "0x00003057", "visual_parts": [ { "raw": "000000", "clean": "000000", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "simm5", "clean": "simm5", "pos": "19:15" }, { "raw": "011", "clean": "011", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "imm", "desc": "Imm" } ], "pseudocode": "vd = vs2 + imm;", "description": "Performs element-wise integer addition on a vector and an immediate, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VADD.VI v1, v4, 16, v0.t" }, { "mnemonic": "VRSUB.VI", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Reverse Subtract Immediate", "summary": "Computes vd = imm - vs2.", "syntax": "VRSUB.VI vd, vs2, imm, vm", "encoding": { "format": "OPIVI", "binary_pattern": "000011 | vm | vs2 | simm5 | 011 | vd | 1010111", "hex_opcode": "0x0C003057", "visual_parts": [ { "raw": "000011", "clean": "000011", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "simm5", "clean": "simm5", "pos": "19:15" }, { "raw": "011", "clean": "011", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "imm", "desc": "Imm" } ], "pseudocode": "vd = imm - vs2;", "description": "Performs element-wise reverse integer subtraction on a vector and an immediate, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VRSUB.VI v1, v4, 16, v0.t" }, { "mnemonic": "VAND.VI", "architecture": "RISC-V", "extension": "V", "full_name": "Vector AND Immediate", "summary": "Bitwise AND with immediate.", "syntax": "VAND.VI vd, vs2, imm, vm", "encoding": { "format": "OPIVI", "binary_pattern": "001001 | vm | vs2 | simm5 | 011 | vd | 1010111", "hex_opcode": "0x24003057", "visual_parts": [ { "raw": "001001", "clean": "001001", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "simm5", "clean": "simm5", "pos": "19:15" }, { "raw": "011", "clean": "011", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "imm", "desc": "Imm" } ], "pseudocode": "vd = vs2 & imm;", "description": "Performs element-wise bitwise AND on a vector and an immediate, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VAND.VI v1, v4, 16, v0.t" }, { "mnemonic": "VOR.VI", "architecture": "RISC-V", "extension": "V", "full_name": "Vector OR Immediate", "summary": "Bitwise OR with immediate.", "syntax": "VOR.VI vd, vs2, imm, vm", "encoding": { "format": "OPIVI", "binary_pattern": "001010 | vm | vs2 | simm5 | 011 | vd | 1010111", "hex_opcode": "0x28003057", "visual_parts": [ { "raw": "001010", "clean": "001010", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "simm5", "clean": "simm5", "pos": "19:15" }, { "raw": "011", "clean": "011", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "imm", "desc": "Imm" } ], "pseudocode": "vd = vs2 | imm;", "description": "Performs element-wise bitwise OR on a vector and an immediate, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VOR.VI v1, v4, 16, v0.t" }, { "mnemonic": "VXOR.VI", "architecture": "RISC-V", "extension": "V", "full_name": "Vector XOR Immediate", "summary": "Bitwise XOR with immediate.", "syntax": "VXOR.VI vd, vs2, imm, vm", "encoding": { "format": "OPIVI", "binary_pattern": "001011 | vm | vs2 | simm5 | 011 | vd | 1010111", "hex_opcode": "0x2C003057", "visual_parts": [ { "raw": "001011", "clean": "001011", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "simm5", "clean": "simm5", "pos": "19:15" }, { "raw": "011", "clean": "011", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "imm", "desc": "Imm" } ], "pseudocode": "vd = vs2 ^ imm;", "description": "Performs element-wise bitwise XOR on a vector and an immediate, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VXOR.VI v1, v4, 16, v0.t" }, { "mnemonic": "VRGATHER.VI", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Register Gather Immediate", "summary": "Gathers element at index 'imm' from vs2 (splat).", "syntax": "VRGATHER.VI vd, vs2, imm, vm", "encoding": { "format": "OPIVI", "binary_pattern": "001100 | vm | vs2 | zimm5 | 011 | vd | 1010111", "hex_opcode": "0x30003057", "visual_parts": [ { "raw": "001100", "clean": "001100", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "zimm5", "clean": "zimm5", "pos": "19:15" }, { "raw": "011", "clean": "011", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Table" }, { "name": "imm", "desc": "Index" } ], "pseudocode": "vd[*] = vs2[imm];", "description": "Gathers elements from vs2 using indices in vs1 (or an immediate), writing to vd. Out-of-range indices produce zero.", "example": "VRGATHER.VI v1, v4, 16, v0.t" }, { "mnemonic": "VSLIDEUP.VI", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Slide Up Immediate", "summary": "Moves elements up by immediate amount.", "syntax": "VSLIDEUP.VI vd, vs2, imm, vm", "encoding": { "format": "OPIVI", "binary_pattern": "001110 | vm | vs2 | zimm5 | 011 | vd | 1010111", "hex_opcode": "0x38003057", "visual_parts": [ { "raw": "001110", "clean": "001110", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "zimm5", "clean": "zimm5", "pos": "19:15" }, { "raw": "011", "clean": "011", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "imm", "desc": "Signed immediate value" } ], "pseudocode": "vd[i] = vs2[i - imm];", "description": "Slides vector elements up by the specified offset, filling vacated positions with zero or the value from vs1[0].", "example": "VSLIDEUP.VI v1, v4, 16, v0.t" }, { "mnemonic": "VSLIDEDOWN.VI", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Slide Down Immediate", "summary": "Moves elements down by immediate amount.", "syntax": "VSLIDEDOWN.VI vd, vs2, imm, vm", "encoding": { "format": "OPIVI", "binary_pattern": "001111 | vm | vs2 | zimm5 | 011 | vd | 1010111", "hex_opcode": "0x3C003057", "visual_parts": [ { "raw": "001111", "clean": "001111", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "zimm5", "clean": "zimm5", "pos": "19:15" }, { "raw": "011", "clean": "011", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "imm", "desc": "Signed immediate value" } ], "pseudocode": "vd[i] = vs2[i + imm];", "description": "Slides vector elements down by the specified offset, filling vacated positions with zero or the value from vs1[0].", "example": "VSLIDEDOWN.VI v1, v4, 16, v0.t" }, { "mnemonic": "VMSEQ.VI", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Mask Set Equal Immediate", "summary": "Sets mask if element == imm.", "syntax": "VMSEQ.VI vd, vs2, imm, vm", "encoding": { "format": "OPIVI", "binary_pattern": "011000 | vm | vs2 | simm5 | 011 | vd | 1010111", "hex_opcode": "0x60003057", "visual_parts": [ { "raw": "011000", "clean": "011000", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "simm5", "clean": "simm5", "pos": "19:15" }, { "raw": "011", "clean": "011", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Mask" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "imm", "desc": "Val" } ], "pseudocode": "vd = (vs2 == imm);", "description": "Compares elements element-wise for equal and writes a mask result to vd.", "example": "VMSEQ.VI v1, v4, 16, v0.t" }, { "mnemonic": "VMSNE.VI", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Mask Set Not Equal Immediate", "summary": "Sets mask if element != imm.", "syntax": "VMSNE.VI vd, vs2, imm, vm", "encoding": { "format": "OPIVI", "binary_pattern": "011001 | vm | vs2 | simm5 | 011 | vd | 1010111", "hex_opcode": "0x64003057", "visual_parts": [ { "raw": "011001", "clean": "011001", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "simm5", "clean": "simm5", "pos": "19:15" }, { "raw": "011", "clean": "011", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Mask" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "imm", "desc": "Val" } ], "pseudocode": "vd = (vs2 != imm);", "description": "Compares elements element-wise for not equal and writes a mask result to vd.", "example": "VMSNE.VI v1, v4, 16, v0.t" }, { "mnemonic": "VMSLE.VI", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Mask Set Less or Equal Immediate", "summary": "Sets mask if element <= imm (Signed).", "syntax": "VMSLE.VI vd, vs2, imm, vm", "encoding": { "format": "OPIVI", "binary_pattern": "011101 | vm | vs2 | simm5 | 011 | vd | 1010111", "hex_opcode": "0x74003057", "visual_parts": [ { "raw": "011101", "clean": "011101", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "simm5", "clean": "simm5", "pos": "19:15" }, { "raw": "011", "clean": "011", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Mask" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "imm", "desc": "Val" } ], "pseudocode": "vd = (vs2 <= imm);", "description": "Compares elements element-wise for less than or equal and writes a mask result to vd.", "example": "VMSLE.VI v1, v4, 16, v0.t" }, { "mnemonic": "VMSLEU.VI", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Mask Set Less or Equal Unsigned Immediate", "summary": "Sets mask if element <= imm (Unsigned).", "syntax": "VMSLEU.VI vd, vs2, imm, vm", "encoding": { "format": "OPIVI", "binary_pattern": "011100 | vm | vs2 | simm5 | 011 | vd | 1010111", "hex_opcode": "0x70003057", "visual_parts": [ { "raw": "011100", "clean": "011100", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "simm5", "clean": "simm5", "pos": "19:15" }, { "raw": "011", "clean": "011", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Mask" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "imm", "desc": "Val" } ], "pseudocode": "vd = (vs2 <=u imm);", "description": "Compares elements element-wise for less than or equal and writes a mask result to vd.", "example": "VMSLEU.VI v1, v4, 16, v0.t" }, { "mnemonic": "VMSLT.VI", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Mask Set Less Than Immediate", "summary": "Sets mask if element < imm (Signed).", "syntax": "VMSLT.VI vd, vs2, imm, vm", "encoding": { "format": "OPIVI", "binary_pattern": "011011 | vm | vs2 | imm | 011 | vd | 1010111", "hex_opcode": "0x74003057", "visual_parts": [ { "raw": "011011", "clean": "011011", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "imm", "clean": "imm", "pos": "" }, { "raw": "011", "clean": "011", "pos": "19:17" }, { "raw": "vd", "clean": "vd", "pos": "16:12" }, { "raw": "1010111", "clean": "1010111", "pos": "11:5" } ], "bit_positions": "31:26 | 25 | 24:20 | | 19:17 | 16:12 | 11:5" }, "operands": [ { "name": "vd", "desc": "Mask" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "imm", "desc": "Val" } ], "pseudocode": "vd = (vs2 < imm);", "description": "Compares elements element-wise for less than and writes a mask result to vd.", "example": "VMSLT.VI v1, v4, 16, v0.t" }, { "mnemonic": "VMSLTU.VI", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Mask Set Less Than Unsigned Immediate", "summary": "Sets mask if element < imm (Unsigned).", "syntax": "VMSLTU.VI vd, vs2, imm, vm", "encoding": { "format": "OPIVI", "binary_pattern": "011010 | vm | vs2 | imm | 011 | vd | 1010111", "hex_opcode": "0x70003057", "visual_parts": [ { "raw": "011010", "clean": "011010", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "imm", "clean": "imm", "pos": "" }, { "raw": "011", "clean": "011", "pos": "19:17" }, { "raw": "vd", "clean": "vd", "pos": "16:12" }, { "raw": "1010111", "clean": "1010111", "pos": "11:5" } ], "bit_positions": "31:26 | 25 | 24:20 | | 19:17 | 16:12 | 11:5" }, "operands": [ { "name": "vd", "desc": "Mask" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "imm", "desc": "Val" } ], "pseudocode": "vd = (vs2 >u imm;", "description": "Performs element-wise right logical shift on a vector and an immediate, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VSRL.VI v1, v4, 16, v0.t" }, { "mnemonic": "VSRA.VI", "architecture": "RISC-V", "extension": "V", "full_name": "Vector Shift Right Arithmetic Immediate", "summary": "Shifts elements right (arithmetic) by immediate.", "syntax": "VSRA.VI vd, vs2, imm, vm", "encoding": { "format": "OPIVI", "binary_pattern": "101001 | vm | vs2 | zimm5 | 011 | vd | 1010111", "hex_opcode": "0xA4003057", "visual_parts": [ { "raw": "101001", "clean": "101001", "pos": "31:26" }, { "raw": "vm", "clean": "vm", "pos": "25" }, { "raw": "vs2", "clean": "vs2", "pos": "24:20" }, { "raw": "zimm5", "clean": "zimm5", "pos": "19:15" }, { "raw": "011", "clean": "011", "pos": "14:12" }, { "raw": "vd", "clean": "vd", "pos": "11:7" }, { "raw": "1010111", "clean": "1010111", "pos": "6:0" } ], "bit_positions": "31:26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "vd", "desc": "Destination vector register" }, { "name": "vs2", "desc": "Source vector register 2" }, { "name": "imm", "desc": "Signed immediate value" } ], "pseudocode": "vd = vs2 >>s imm;", "description": "Performs element-wise right arithmetic shift on a vector and an immediate, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.", "example": "VSRA.VI v1, v4, 16, v0.t" }, { "mnemonic": "ADD", "architecture": "RISC-V", "full_name": "Add Integer", "summary": "Adds the contents of two registers.", "syntax": "ADD rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000000 | rs2 | rs1 | 000 | rd | 0110011", "hex_opcode": "0x00000033", "visual_parts": [ { "raw": "0000000", "clean": "0000000", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination Register" }, { "name": "rs1", "desc": "Source Register 1" }, { "name": "rs2", "desc": "Source Register 2" } ], "pseudocode": "R[rd] = R[rs1] + R[rs2];", "example": "ADD x10, x11, x12", "example_note": "Computes x11 + x12 and stores the result in x10.", "extension": "RV32I", "description": "ADD performs an XLEN-bit addition of the values in registers rs1 and rs2, writing the result to rd. Arithmetic overflow is ignored; the result is simply the low XLEN bits of the mathematical sum." }, { "mnemonic": "ADDI", "architecture": "RISC-V", "full_name": "Add Immediate", "summary": "Adds a register and a sign-extended 12-bit immediate value.", "syntax": "ADDI rd, rs1, imm", "encoding": { "format": "I-Type", "binary_pattern": "imm12 | rs1 | 000 | rd | 0010011", "hex_opcode": "0x00000013", "visual_parts": [ { "raw": "imm12", "clean": "imm12", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0010011", "clean": "0010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination Register" }, { "name": "rs1", "desc": "Source Register" }, { "name": "imm", "desc": "12-bit Signed Immediate" } ], "pseudocode": "R[rd] = R[rs1] + sext(imm);", "example": "ADDI x5, x6, 10", "example_note": "Adds 10 to the value in x6 and stores it in x5.", "extension": "RV32I", "description": "ADDI adds the sign-extended 12-bit immediate to register rs1 and writes the low XLEN bits to rd. Arithmetic overflow is ignored. ADDI rd, rs1, 0 implements the MV assembler pseudoinstruction." }, { "mnemonic": "ADDW", "architecture": "RISC-V", "extension": "RV64I", "full_name": "Add Word", "summary": "Adds two 32-bit registers and sign-extends the result to 64 bits.", "syntax": "ADDW rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000000 | rs2 | rs1 | 000 | rd | 0111011", "hex_opcode": "0x0000003B", "visual_parts": [ { "raw": "0000000", "clean": "0000000", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0111011", "clean": "0111011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination Register" }, { "name": "rs1", "desc": "Source Register 1" }, { "name": "rs2", "desc": "Source Register 2" } ], "pseudocode": "R[rd] = sext((R[rs1] + R[rs2])[31:0]);", "example": "ADDW x10, x11, x12", "example_note": "Performs 32-bit addition of x11 and x12, result is sign-extended to 64 bits.", "description": "ADDW adds rs1 and rs2, truncates the result to 32 bits, sign-extends to 64 bits, and writes to rd. Arithmetic overflow is ignored." }, { "mnemonic": "ADDIW", "architecture": "RISC-V", "extension": "RV64I", "full_name": "Add Immediate Word", "summary": "Adds a 12-bit immediate to a register (32-bit arithmetic) and sign-extends to 64 bits.", "syntax": "ADDIW rd, rs1, imm", "encoding": { "format": "I-Type", "binary_pattern": "imm12 | rs1 | 000 | rd | 0011011", "hex_opcode": "0x0000001B", "visual_parts": [ { "raw": "imm12", "clean": "imm12", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "000", "clean": "000", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0011011", "clean": "0011011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination Register" }, { "name": "rs1", "desc": "Source Register" }, { "name": "imm", "desc": "12-bit Signed Immediate" } ], "pseudocode": "R[rd] = sext((R[rs1] + sext(imm))[31:0]);", "example": "ADDIW x5, x6, 5", "example_note": "Adds 5 to lower 32 bits of x6, sign-extends result to x5.", "description": "ADDIW adds the sign-extended 12-bit immediate to rs1, truncates to 32 bits, sign-extends to 64 bits, and writes to rd. Arithmetic overflow is ignored." }, { "mnemonic": "AND", "architecture": "RISC-V", "full_name": "Logical AND", "summary": "Performs a bitwise logical AND operation between two registers.", "syntax": "AND rd, rs1, rs2", "encoding": { "format": "R-Type", "binary_pattern": "0000000 | rs2 | rs1 | 111 | rd | 0110011", "hex_opcode": "0x00007033", "visual_parts": [ { "raw": "0000000", "clean": "0000000", "pos": "31:25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "111", "clean": "111", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0110011", "clean": "0110011", "pos": "6:0" } ], "bit_positions": "31:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination Register" }, { "name": "rs1", "desc": "Source Register 1" }, { "name": "rs2", "desc": "Source Register 2" } ], "pseudocode": "R[rd] = R[rs1] & R[rs2];", "example": "AND x10, x11, x12", "example_note": "Bitwise AND of x11 and x12.", "extension": "RV32I", "description": "AND performs a bitwise logical AND of the values in rs1 and rs2, writing the result to rd." }, { "mnemonic": "ANDI", "architecture": "RISC-V", "full_name": "Logical AND Immediate", "summary": "Performs a bitwise logical AND between a register and a sign-extended 12-bit immediate.", "syntax": "ANDI rd, rs1, imm", "encoding": { "format": "I-Type", "binary_pattern": "imm12 | rs1 | 111 | rd | 0010011", "hex_opcode": "0x00007013", "visual_parts": [ { "raw": "imm12", "clean": "imm12", "pos": "31:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "111", "clean": "111", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0010011", "clean": "0010011", "pos": "6:0" } ], "bit_positions": "31:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination Register" }, { "name": "rs1", "desc": "Source Register" }, { "name": "imm", "desc": "12-bit Signed Immediate" } ], "pseudocode": "R[rd] = R[rs1] & sext(imm);", "example": "ANDI x10, x11, 15", "example_note": "Keeps only the lowest 4 bits of x11 (mask 0xF).", "extension": "RV32I", "description": "ANDI performs a bitwise AND of register rs1 with the sign-extended 12-bit immediate, writing the result to rd." }, { "mnemonic": "AUIPC", "architecture": "RISC-V", "full_name": "Add Upper Immediate to PC", "summary": "Adds a 20-bit upper immediate to the Program Counter, used for PC-relative addressing.", "syntax": "AUIPC rd, imm", "encoding": { "format": "U-Type", "binary_pattern": "imm20 | rd | 0010111", "hex_opcode": "0x00000017", "visual_parts": [ { "raw": "imm20", "clean": "imm20", "pos": "31:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0010111", "clean": "0010111", "pos": "6:0" } ], "bit_positions": "31:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Destination Register" }, { "name": "imm", "desc": "20-bit Upper Immediate" } ], "pseudocode": "R[rd] = PC + (imm << 12);", "example": "AUIPC x10, 0x1000", "example_note": "Adds 0x1000000 to the current PC and stores in x10.", "extension": "RV32I", "description": "AUIPC (Add Upper Immediate to PC) forms a 32-bit offset from the 20-bit U-immediate (filling the low 12 bits with zeros), adds it to the PC of the AUIPC instruction, and places the result in rd. It is used for PC-relative addressing." }, { "mnemonic": "AMOADD.W", "architecture": "RISC-V", "extension": "A", "full_name": "Atomic Add Word", "summary": "Atomically adds a value to a word in memory.", "syntax": "AMOADD.W rd, rs2, (rs1)", "encoding": { "format": "R-Type (Atomic)", "binary_pattern": "00000 | aq | rl | rs2 | rs1 | 010 | rd | 0101111", "hex_opcode": "0x0000202F", "visual_parts": [ { "raw": "00000", "clean": "00000", "pos": "31:27" }, { "raw": "aq", "clean": "aq", "pos": "26" }, { "raw": "rl", "clean": "rl", "pos": "25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0101111", "clean": "0101111", "pos": "6:0" } ], "bit_positions": "31:27 | 26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Old Value)" }, { "name": "rs2", "desc": "Value to Add" }, { "name": "rs1", "desc": "Address" } ], "pseudocode": "temp = M[R[rs1]]; M[R[rs1]] = temp + R[rs2]; R[rd] = temp;", "example": "AMOADD.W x10, x11, (x12)", "example_note": "Atomically adds x11 to memory at x12. Old value stored in x10.", "description": "AMOADD.W atomically loads a word from the address in rs1 into rd, then adds rs2 to it, and stores the result back to that address." }, { "mnemonic": "AMOSWAP.W", "architecture": "RISC-V", "extension": "A", "full_name": "Atomic Swap Word", "summary": "Atomically swaps a value in memory with a register.", "syntax": "AMOSWAP.W rd, rs2, (rs1)", "encoding": { "format": "R-Type (Atomic)", "binary_pattern": "00001 | aq | rl | rs2 | rs1 | 010 | rd | 0101111", "hex_opcode": "0x0800202F", "visual_parts": [ { "raw": "00001", "clean": "00001", "pos": "31:27" }, { "raw": "aq", "clean": "aq", "pos": "26" }, { "raw": "rl", "clean": "rl", "pos": "25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0101111", "clean": "0101111", "pos": "6:0" } ], "bit_positions": "31:27 | 26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Old Value)" }, { "name": "rs2", "desc": "New Value" }, { "name": "rs1", "desc": "Address" } ], "pseudocode": "temp = M[R[rs1]]; M[R[rs1]] = R[rs2]; R[rd] = temp;", "example": "AMOSWAP.W x10, x11, (x12)", "example_note": "Writes x11 to memory at x12, loads old memory value into x10.", "description": "AMOSWAP.W atomically loads a word from the address in rs1 into rd and stores the value of rs2 to that address." }, { "mnemonic": "AMOAND.W", "architecture": "RISC-V", "extension": "A", "full_name": "Atomic AND Word", "summary": "Atomically performs bitwise AND on a word in memory.", "syntax": "AMOAND.W rd, rs2, (rs1)", "encoding": { "format": "R-Type (Atomic)", "binary_pattern": "01100 | aq | rl | rs2 | rs1 | 010 | rd | 0101111", "hex_opcode": "0x6000202F", "visual_parts": [ { "raw": "01100", "clean": "01100", "pos": "31:27" }, { "raw": "aq", "clean": "aq", "pos": "26" }, { "raw": "rl", "clean": "rl", "pos": "25" }, { "raw": "rs2", "clean": "rs2", "pos": "24:20" }, { "raw": "rs1", "clean": "rs1", "pos": "19:15" }, { "raw": "010", "clean": "010", "pos": "14:12" }, { "raw": "rd", "clean": "rd", "pos": "11:7" }, { "raw": "0101111", "clean": "0101111", "pos": "6:0" } ], "bit_positions": "31:27 | 26 | 25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:0" }, "operands": [ { "name": "rd", "desc": "Dest (Old Value)" }, { "name": "rs2", "desc": "Operand" }, { "name": "rs1", "desc": "Address" } ], "pseudocode": "temp = M[R[rs1]]; M[R[rs1]] = temp & R[rs2]; R[rd] = temp;", "example": "AMOAND.W x5, x6, (x7)", "example_note": "Atomically ANDs memory at x7 with x6.", "description": "AMOAND.W atomically loads a word from the address in rs1 into rd, ANDs it with rs2, and stores the result back." } ] }