{ "architecture": "AMDGPU", "instructions": [ { "id": "amdgpu.buffer_atomic_add_f64", "mnemonic": "buffer_atomic_add_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC ADD F64", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Add a double-precision float value in the data register to a location in a buffer surface.", "description": "Add a double-precision float value in the data register to a location in a buffer surface. Store the original value from buffer surface into a vector register iff the SC0 bit is set.", "syntax": "buffer_atomic_add_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "tmp = MEM[ADDR].f64;\nMEM[ADDR].f64 += DATA.f64;\nRETURN_DATA = tmp", "example": null, "exampleSource": null, "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "Floating-point addition handles NAN/INF/denorm.", "sourcePdfPage": 472, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.buffer_atomic_add_u32", "mnemonic": "buffer_atomic_add_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC ADD U32", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Add two unsigned 32-bit integer values stored in the data register and a location in a buffer surface.", "description": "Add two unsigned 32-bit integer values stored in the data register and a location in a buffer surface. Store the original value from buffer surface into a vector register iff the temporal hint enables atomic return.", "syntax": "buffer_atomic_add_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": "buffer_atomic_add_u32 v5, off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_atomic_add_u64", "mnemonic": "buffer_atomic_add_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC ADD U64", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Add two unsigned 64-bit integer values stored in the data register and a location in a buffer surface.", "description": "Add two unsigned 64-bit integer values stored in the data register and a location in a buffer surface. Store the original value from buffer surface into a vector register iff the temporal hint enables atomic return.", "syntax": "buffer_atomic_add_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "", "example": "buffer_atomic_add_u64 v[5:6], off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_atomic_and_b32", "mnemonic": "buffer_atomic_and_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC AND B32", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in a buffer surface.", "description": "Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in a buffer surface. Store the original value from buffer surface into a vector register iff the temporal hint enables atomic return.", "syntax": "buffer_atomic_and_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "buffer_atomic_and_b32 v5, off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_atomic_and_b64", "mnemonic": "buffer_atomic_and_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC AND B64", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Calculate bitwise AND given two unsigned 64-bit integer values stored in the data register and a location in a buffer surface.", "description": "Calculate bitwise AND given two unsigned 64-bit integer values stored in the data register and a location in a buffer surface. Store the original value from buffer surface into a vector register iff the temporal hint enables atomic return.", "syntax": "buffer_atomic_and_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "buffer_atomic_and_b64 v[5:6], off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_atomic_cmpswap_b32", "mnemonic": "buffer_atomic_cmpswap_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC CMPSWAP B32", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Compare two unsigned 32-bit integer values stored in the data comparison register and a location in a buffer surface.", "description": "Compare two unsigned 32-bit integer values stored in the data comparison register and a location in a buffer surface. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from buffer surface into a vector register iff the temporal hint enables atomic return.", "syntax": "buffer_atomic_cmpswap_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "buffer_atomic_cmpswap_b32 v[5:6], off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_atomic_cmpswap_b64", "mnemonic": "buffer_atomic_cmpswap_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC CMPSWAP B64", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Compare two unsigned 64-bit integer values stored in the data comparison register and a location in a buffer surface.", "description": "Compare two unsigned 64-bit integer values stored in the data comparison register and a location in a buffer surface. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from buffer surface into a vector register iff the temporal hint enables atomic return.", "syntax": "buffer_atomic_cmpswap_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "buffer_atomic_cmpswap_b64 v[5:8], off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_atomic_cmpswap_f32", "mnemonic": "buffer_atomic_cmpswap_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC CMPSWAP F32", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Compare two single-precision float values stored in the data comparison register and a location in a buffer surface.", "description": "Compare two single-precision float values stored in the data comparison register and a location in a buffer surface. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from buffer surface into a vector register iff the GLC bit is set.", "syntax": "buffer_atomic_cmpswap_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": "buffer_atomic_cmpswap_f32 v[5:6], off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_atomic_dec_u32", "mnemonic": "buffer_atomic_dec_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC DEC U32", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Decrement an unsigned 32-bit integer value from a location in a buffer surface with wraparound to a value in the data register if the decrement…", "description": "Decrement an unsigned 32-bit integer value from a location in a buffer surface with wraparound to a value in the data register if the decrement yields a negative value. Store the original value from buffer surface into a vector register iff the temporal hint enables atomic return.", "syntax": "buffer_atomic_dec_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": "buffer_atomic_dec_u32 v5, off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_atomic_dec_u64", "mnemonic": "buffer_atomic_dec_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC DEC U64", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Decrement an unsigned 64-bit integer value from a location in a buffer surface with wraparound to a value in the data register if the decrement…", "description": "Decrement an unsigned 64-bit integer value from a location in a buffer surface with wraparound to a value in the data register if the decrement yields a negative value. Store the original value from buffer surface into a vector register iff the temporal hint enables atomic return.", "syntax": "buffer_atomic_dec_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "", "example": "buffer_atomic_dec_u64 v[5:6], off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_atomic_fmax_x2", "mnemonic": "buffer_atomic_fmax_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC FMAX X2", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Select the maximum of two double-precision float inputs, given two values stored in the data register and a location in a buffer surface.", "description": "Select the maximum of two double-precision float inputs, given two values stored in the data register and a location in a buffer surface. Update the buffer surface with the selected value. Store the original value from buffer surface into a vector register iff the GLC bit is set.", "syntax": "buffer_atomic_fmax_x2", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.buffer_atomic_fmin_x2", "mnemonic": "buffer_atomic_fmin_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC FMIN X2", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in a buffer surface.", "description": "Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in a buffer surface. Update the buffer surface with the selected value. Store the original value from buffer surface into a vector register iff the GLC bit is set.", "syntax": "buffer_atomic_fmin_x2", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.buffer_atomic_inc_u32", "mnemonic": "buffer_atomic_inc_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC INC U32", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Increment an unsigned 32-bit integer value from a location in a buffer surface with wraparound to 0 if the value exceeds a value in the data register.", "description": "Increment an unsigned 32-bit integer value from a location in a buffer surface with wraparound to 0 if the value exceeds a value in the data register. Store the original value from buffer surface into a vector register iff the temporal hint enables atomic return.", "syntax": "buffer_atomic_inc_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": "buffer_atomic_inc_u32 v5, off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_atomic_inc_u64", "mnemonic": "buffer_atomic_inc_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC INC U64", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Increment an unsigned 64-bit integer value from a location in a buffer surface with wraparound to 0 if the value exceeds a value in the data register.", "description": "Increment an unsigned 64-bit integer value from a location in a buffer surface with wraparound to 0 if the value exceeds a value in the data register. Store the original value from buffer surface into a vector register iff the temporal hint enables atomic return.", "syntax": "buffer_atomic_inc_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "", "example": "buffer_atomic_inc_u64 v[5:6], off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_atomic_max_f64", "mnemonic": "buffer_atomic_max_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC MAX F64", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Select the maximum of two double-precision float inputs, given two values stored in the data register and a location in a buffer surface.", "description": "Select the maximum of two double-precision float inputs, given two values stored in the data register and a location in a buffer surface. Update the buffer surface with the selected value. Store the original value from buffer surface into a vector register iff the SC0 bit is set.", "syntax": "buffer_atomic_max_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);\ntmp = MEM[addr].f64;\nsrc = DATA.f64;\nMEM[addr].f64 = src > tmp ? src : tmp;\nRETURN_DATA.f64 = tmp", "example": null, "exampleSource": null, "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 473, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.buffer_atomic_max_i32", "mnemonic": "buffer_atomic_max_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC MAX I32", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Select the maximum of two signed 32-bit integer inputs, given two values stored in the data register and a location in a buffer surface.", "description": "Select the maximum of two signed 32-bit integer inputs, given two values stored in the data register and a location in a buffer surface. Update the buffer surface with the selected value. Store the original value from buffer surface into a vector register iff the temporal hint enables atomic return.", "syntax": "buffer_atomic_max_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "", "example": "buffer_atomic_max_i32 v5, off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_atomic_max_i64", "mnemonic": "buffer_atomic_max_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC MAX I64", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Select the maximum of two signed 64-bit integer inputs, given two values stored in the data register and a location in a buffer surface.", "description": "Select the maximum of two signed 64-bit integer inputs, given two values stored in the data register and a location in a buffer surface. Update the buffer surface with the selected value. Store the original value from buffer surface into a vector register iff the temporal hint enables atomic return.", "syntax": "buffer_atomic_max_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "", "example": "buffer_atomic_max_i64 v[5:6], off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_atomic_max_num_f32", "mnemonic": "buffer_atomic_max_num_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC MAX NUM F32", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Select the IEEE maximumNumber() of two single-precision float inputs, given two values stored in the data register and a location in a buffer surface.", "description": "Select the IEEE maximumNumber() of two single-precision float inputs, given two values stored in the data register and a location in a buffer surface. Update the buffer surface with the selected value. Store the original value from buffer surface into a vector register iff the temporal hint enables atomic return.", "syntax": "buffer_atomic_max_num_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.buffer_atomic_max_num_f64", "mnemonic": "buffer_atomic_max_num_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC MAX NUM F64", "category": "Buffer Memory", "instructionClass": "vector", "summary": "AMDGPU MUBUF vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "buffer_atomic_max_num_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.buffer_atomic_max_u32", "mnemonic": "buffer_atomic_max_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC MAX U32", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Select the maximum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in a buffer surface.", "description": "Select the maximum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in a buffer surface. Update the buffer surface with the selected value. Store the original value from buffer surface into a vector register iff the temporal hint enables atomic return.", "syntax": "buffer_atomic_max_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": "buffer_atomic_max_u32 v5, off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_atomic_max_u64", "mnemonic": "buffer_atomic_max_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC MAX U64", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Select the maximum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in a buffer surface.", "description": "Select the maximum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in a buffer surface. Update the buffer surface with the selected value. Store the original value from buffer surface into a vector register iff the temporal hint enables atomic return.", "syntax": "buffer_atomic_max_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "", "example": "buffer_atomic_max_u64 v[5:6], off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_atomic_min_f64", "mnemonic": "buffer_atomic_min_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC MIN F64", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in a buffer surface.", "description": "Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in a buffer surface. Update the buffer surface with the selected value. Store the original value from buffer surface into a vector register iff the SC0 bit is set.", "syntax": "buffer_atomic_min_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);\ntmp = MEM[addr].f64;\nsrc = DATA.f64;\nMEM[addr].f64 = src < tmp ? src : tmp;\nRETURN_DATA.f64 = tmp", "example": null, "exampleSource": null, "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 472, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.buffer_atomic_min_i32", "mnemonic": "buffer_atomic_min_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC MIN I32", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Select the minimum of two signed 32-bit integer inputs, given two values stored in the data register and a location in a buffer surface.", "description": "Select the minimum of two signed 32-bit integer inputs, given two values stored in the data register and a location in a buffer surface. Update the buffer surface with the selected value. Store the original value from buffer surface into a vector register iff the temporal hint enables atomic return.", "syntax": "buffer_atomic_min_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "", "example": "buffer_atomic_min_i32 v5, off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_atomic_min_i64", "mnemonic": "buffer_atomic_min_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC MIN I64", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Select the minimum of two signed 64-bit integer inputs, given two values stored in the data register and a location in a buffer surface.", "description": "Select the minimum of two signed 64-bit integer inputs, given two values stored in the data register and a location in a buffer surface. Update the buffer surface with the selected value. Store the original value from buffer surface into a vector register iff the temporal hint enables atomic return.", "syntax": "buffer_atomic_min_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "", "example": "buffer_atomic_min_i64 v[5:6], off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_atomic_min_num_f32", "mnemonic": "buffer_atomic_min_num_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC MIN NUM F32", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Select the IEEE minimumNumber() of two single-precision float inputs, given two values stored in the data register and a location in a buffer surface.", "description": "Select the IEEE minimumNumber() of two single-precision float inputs, given two values stored in the data register and a location in a buffer surface. Update the buffer surface with the selected value. Store the original value from buffer surface into a vector register iff the temporal hint enables atomic return.", "syntax": "buffer_atomic_min_num_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.buffer_atomic_min_num_f64", "mnemonic": "buffer_atomic_min_num_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC MIN NUM F64", "category": "Buffer Memory", "instructionClass": "vector", "summary": "AMDGPU MUBUF vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "buffer_atomic_min_num_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.buffer_atomic_min_u32", "mnemonic": "buffer_atomic_min_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC MIN U32", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Select the minimum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in a buffer surface.", "description": "Select the minimum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in a buffer surface. Update the buffer surface with the selected value. Store the original value from buffer surface into a vector register iff the temporal hint enables atomic return.", "syntax": "buffer_atomic_min_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": "buffer_atomic_min_u32 v5, off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_atomic_min_u64", "mnemonic": "buffer_atomic_min_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC MIN U64", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Select the minimum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in a buffer surface.", "description": "Select the minimum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in a buffer surface. Update the buffer surface with the selected value. Store the original value from buffer surface into a vector register iff the temporal hint enables atomic return.", "syntax": "buffer_atomic_min_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "", "example": "buffer_atomic_min_u64 v[5:6], off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_atomic_or_b32", "mnemonic": "buffer_atomic_or_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC OR B32", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Calculate bitwise OR given two unsigned 32-bit integer values stored in the data register and a location in a buffer surface.", "description": "Calculate bitwise OR given two unsigned 32-bit integer values stored in the data register and a location in a buffer surface. Store the original value from buffer surface into a vector register iff the temporal hint enables atomic return.", "syntax": "buffer_atomic_or_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "buffer_atomic_or_b32 v5, off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_atomic_or_b64", "mnemonic": "buffer_atomic_or_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC OR B64", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Calculate bitwise OR given two unsigned 64-bit integer values stored in the data register and a location in a buffer surface.", "description": "Calculate bitwise OR given two unsigned 64-bit integer values stored in the data register and a location in a buffer surface. Store the original value from buffer surface into a vector register iff the temporal hint enables atomic return.", "syntax": "buffer_atomic_or_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "buffer_atomic_or_b64 v[5:6], off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_atomic_rsub", "mnemonic": "buffer_atomic_rsub", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC RSUB", "category": "Buffer Memory", "instructionClass": "vector", "summary": "AMDGPU MUBUF vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "buffer_atomic_rsub", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.buffer_atomic_rsub_x2", "mnemonic": "buffer_atomic_rsub_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC RSUB X2", "category": "Buffer Memory", "instructionClass": "vector", "summary": "AMDGPU MUBUF vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "buffer_atomic_rsub_x2", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.buffer_atomic_sub_clamp_u32", "mnemonic": "buffer_atomic_sub_clamp_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC SUB CLAMP U32", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Subtract an unsigned 32-bit integer location in a buffer surface from a value in the data register and clamp the result to zero.", "description": "Subtract an unsigned 32-bit integer location in a buffer surface from a value in the data register and clamp the result to zero. Store the original value from buffer surface into a vector register iff the temporal hint enables atomic return.", "syntax": "buffer_atomic_sub_clamp_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.buffer_atomic_sub_u32", "mnemonic": "buffer_atomic_sub_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC SUB U32", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Subtract an unsigned 32-bit integer value stored in the data register from a value stored in a location in a buffer surface.", "description": "Subtract an unsigned 32-bit integer value stored in the data register from a value stored in a location in a buffer surface. Store the original value from buffer surface into a vector register iff the temporal hint enables atomic return.", "syntax": "buffer_atomic_sub_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": "buffer_atomic_sub_u32 v5, off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_atomic_sub_u64", "mnemonic": "buffer_atomic_sub_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC SUB U64", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Subtract an unsigned 64-bit integer value stored in the data register from a value stored in a location in a buffer surface.", "description": "Subtract an unsigned 64-bit integer value stored in the data register from a value stored in a location in a buffer surface. Store the original value from buffer surface into a vector register iff the temporal hint enables atomic return.", "syntax": "buffer_atomic_sub_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "", "example": "buffer_atomic_sub_u64 v[5:6], off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_atomic_swap_b32", "mnemonic": "buffer_atomic_swap_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC SWAP B32", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Swap an unsigned 32-bit integer value in the data register with a location in a buffer surface.", "description": "Swap an unsigned 32-bit integer value in the data register with a location in a buffer surface. Store the original value from buffer surface into a vector register iff the temporal hint enables atomic return.", "syntax": "buffer_atomic_swap_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "buffer_atomic_swap_b32 v5, off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_atomic_swap_b64", "mnemonic": "buffer_atomic_swap_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC SWAP B64", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Swap an unsigned 64-bit integer value in the data register with a location in a buffer surface.", "description": "Swap an unsigned 64-bit integer value in the data register with a location in a buffer surface. Store the original value from buffer surface into a vector register iff the temporal hint enables atomic return.", "syntax": "buffer_atomic_swap_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "buffer_atomic_swap_b64 v[5:6], off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_atomic_xor_b32", "mnemonic": "buffer_atomic_xor_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC XOR B32", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Calculate bitwise XOR given two unsigned 32-bit integer values stored in the data register and a location in a buffer surface.", "description": "Calculate bitwise XOR given two unsigned 32-bit integer values stored in the data register and a location in a buffer surface. Store the original value from buffer surface into a vector register iff the temporal hint enables atomic return.", "syntax": "buffer_atomic_xor_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "buffer_atomic_xor_b32 v5, off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_atomic_xor_b64", "mnemonic": "buffer_atomic_xor_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER ATOMIC XOR B64", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Calculate bitwise XOR given two unsigned 64-bit integer values stored in the data register and a location in a buffer surface.", "description": "Calculate bitwise XOR given two unsigned 64-bit integer values stored in the data register and a location in a buffer surface. Store the original value from buffer surface into a vector register iff the temporal hint enables atomic return.", "syntax": "buffer_atomic_xor_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "buffer_atomic_xor_b64 v[5:6], off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_gl0_inv", "mnemonic": "buffer_gl0_inv", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER GL0 INV", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Write back and invalidate the shader L0. Returns ACK to shader.", "description": "Write back and invalidate the shader L0. Returns ACK to shader.", "syntax": "buffer_gl0_inv", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.buffer_gl1_inv", "mnemonic": "buffer_gl1_inv", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER GL1 INV", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Invalidate the GL1 cache only. Returns ACK to shader.", "description": "Invalidate the GL1 cache only. Returns ACK to shader.", "syntax": "buffer_gl1_inv", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.buffer_inv", "mnemonic": "buffer_inv", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER INV", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Invalidate CU and/or L2 cache depending on sc0 and sc1 bits. Returns ACK to shader.", "description": "Invalidate CU and/or L2 cache depending on sc0 and sc1 bits. Returns ACK to shader.", "syntax": "buffer_inv", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 468, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.buffer_invl2", "mnemonic": "buffer_invl2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER INVL2", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Invalidate L2 cache. Returns ACK to shader.", "description": "Invalidate L2 cache. Returns ACK to shader.", "syntax": "buffer_invl2", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.buffer_load_b128", "mnemonic": "buffer_load_b128", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER LOAD B128", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Load 128 bits of data from a buffer surface into a vector register.", "description": "Load 128 bits of data from a buffer surface into a vector register.", "syntax": "buffer_load_b128", "operands": [], "dataTypes": [], "semantics": "", "example": "buffer_load_b128 v[5:8], off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_load_b32", "mnemonic": "buffer_load_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER LOAD B32", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Load 32 bits of data from a buffer surface into a vector register.", "description": "Load 32 bits of data from a buffer surface into a vector register.", "syntax": "buffer_load_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "buffer_load_b32 v5, off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_load_b64", "mnemonic": "buffer_load_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER LOAD B64", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Load 64 bits of data from a buffer surface into a vector register.", "description": "Load 64 bits of data from a buffer surface into a vector register.", "syntax": "buffer_load_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "buffer_load_b64 v[5:6], off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_load_b96", "mnemonic": "buffer_load_b96", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER LOAD B96", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Load 96 bits of data from a buffer surface into a vector register.", "description": "Load 96 bits of data from a buffer surface into a vector register.", "syntax": "buffer_load_b96", "operands": [], "dataTypes": [], "semantics": "", "example": "buffer_load_b96 v[5:7], off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_load_d16_b16", "mnemonic": "buffer_load_d16_b16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER LOAD D16 B16", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Load 16 bits of unsigned data from a buffer surface and store the result into the low 16 bits of a 32-bit vector register.", "description": "Load 16 bits of unsigned data from a buffer surface and store the result into the low 16 bits of a 32-bit vector register.", "syntax": "buffer_load_d16_b16", "operands": [], "dataTypes": [ "b16" ], "semantics": "", "example": "buffer_load_d16_b16 v5, off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_load_d16_format_x", "mnemonic": "buffer_load_d16_format_x", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER LOAD D16 FORMAT X", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Load 1-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result…", "description": "Load 1-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result into the low 16 bits of a 32-bit vector register. The resource descriptor specifies the data format of the surface.", "syntax": "buffer_load_d16_format_x", "operands": [], "dataTypes": [], "semantics": "", "example": "buffer_load_d16_format_x v5, off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_load_d16_format_xy", "mnemonic": "buffer_load_d16_format_xy", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER LOAD D16 FORMAT XY", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Load 2-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result…", "description": "Load 2-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result into a vector register. The resource descriptor specifies the data format of the surface.", "syntax": "buffer_load_d16_format_xy", "operands": [], "dataTypes": [], "semantics": "", "example": "buffer_load_d16_format_xy v5, off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_load_d16_format_xyz", "mnemonic": "buffer_load_d16_format_xyz", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER LOAD D16 FORMAT XYZ", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Load 3-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result…", "description": "Load 3-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result into a vector register. The resource descriptor specifies the data format of the surface.", "syntax": "buffer_load_d16_format_xyz", "operands": [], "dataTypes": [], "semantics": "", "example": "buffer_load_d16_format_xyz v[5:6], off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_load_d16_format_xyzw", "mnemonic": "buffer_load_d16_format_xyzw", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER LOAD D16 FORMAT XYZW", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Load 4-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result…", "description": "Load 4-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result into a vector register. The resource descriptor specifies the data format of the surface.", "syntax": "buffer_load_d16_format_xyzw", "operands": [], "dataTypes": [], "semantics": "", "example": "buffer_load_d16_format_xyzw v[5:6], off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_load_d16_hi_b16", "mnemonic": "buffer_load_d16_hi_b16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER LOAD D16 HI B16", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Load 16 bits of unsigned data from a buffer surface and store the result into the high 16 bits of a 32-bit vector register.", "description": "Load 16 bits of unsigned data from a buffer surface and store the result into the high 16 bits of a 32-bit vector register.", "syntax": "buffer_load_d16_hi_b16", "operands": [], "dataTypes": [ "b16" ], "semantics": "", "example": "buffer_load_d16_hi_b16 v5, off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_load_d16_hi_format_x", "mnemonic": "buffer_load_d16_hi_format_x", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER LOAD D16 HI FORMAT X", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Load 1-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result…", "description": "Load 1-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result into the high 16 bits of a 32-bit vector register. The resource descriptor specifies the data format of the surface.", "syntax": "buffer_load_d16_hi_format_x", "operands": [], "dataTypes": [], "semantics": "", "example": "buffer_load_d16_hi_format_x v5, off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_load_d16_hi_i8", "mnemonic": "buffer_load_d16_hi_i8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER LOAD D16 HI I8", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Load 8 bits of signed data from a buffer surface, sign extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register.", "description": "Load 8 bits of signed data from a buffer surface, sign extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register.", "syntax": "buffer_load_d16_hi_i8", "operands": [], "dataTypes": [ "i8" ], "semantics": "", "example": "buffer_load_d16_hi_i8 v5, off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_load_d16_hi_u8", "mnemonic": "buffer_load_d16_hi_u8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER LOAD D16 HI U8", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Load 8 bits of unsigned data from a buffer surface, zero extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register.", "description": "Load 8 bits of unsigned data from a buffer surface, zero extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register.", "syntax": "buffer_load_d16_hi_u8", "operands": [], "dataTypes": [ "u8" ], "semantics": "", "example": "buffer_load_d16_hi_u8 v5, off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_load_d16_i8", "mnemonic": "buffer_load_d16_i8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER LOAD D16 I8", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Load 8 bits of signed data from a buffer surface, sign extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register.", "description": "Load 8 bits of signed data from a buffer surface, sign extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register.", "syntax": "buffer_load_d16_i8", "operands": [], "dataTypes": [ "i8" ], "semantics": "", "example": "buffer_load_d16_i8 v5, off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_load_d16_u8", "mnemonic": "buffer_load_d16_u8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER LOAD D16 U8", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Load 8 bits of unsigned data from a buffer surface, zero extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register.", "description": "Load 8 bits of unsigned data from a buffer surface, zero extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register.", "syntax": "buffer_load_d16_u8", "operands": [], "dataTypes": [ "u8" ], "semantics": "", "example": "buffer_load_d16_u8 v5, off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_load_dword", "mnemonic": "buffer_load_dword", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER LOAD DWORD", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Load one 32-bit dword per lane through a buffer (raw/structured) resource descriptor.", "description": "Load 32 bits of data from a buffer surface into a vector register.", "syntax": "buffer_load_dword VDST, VADDR, SRSRC, offset", "operands": [ { "name": "VDST", "desc": "Destination VGPR" }, { "name": "VADDR", "desc": "Per-lane offset (VGPR)" }, { "name": "SRSRC", "desc": "Buffer resource descriptor (SGPR x4)" }, { "name": "offset", "desc": "Immediate offset" } ], "dataTypes": [], "semantics": "VDST[lane] = *(resource-relative address computed from SRSRC, VADDR[lane], offset) for each active lane; bounds-checked against the descriptor.", "example": "buffer_load_dword v2, v0, s[4:7], 0 offen // v2 = buffer[s[4:7]](v0)", "exampleSource": null, "encoding": { "format": "MUBUF", "widthBits": 32 }, "executionUnit": "Vector Memory Unit", "registerClasses": [ "VGPR", "SGPR" ], "memorySegment": "buffer", "supportedTargets": [ "gfx942", "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "amd-machine-readable-isa" ] }, { "id": "amdgpu.buffer_load_i16", "mnemonic": "buffer_load_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER LOAD I16", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Load 16 bits of signed data from a buffer surface, sign extend to 32 bits and store the result into a vector register.", "description": "Load 16 bits of signed data from a buffer surface, sign extend to 32 bits and store the result into a vector register.", "syntax": "buffer_load_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "", "example": "buffer_load_i16 v5, off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_load_i8", "mnemonic": "buffer_load_i8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER LOAD I8", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Load 8 bits of signed data from a buffer surface, sign extend to 32 bits and store the result into a vector register.", "description": "Load 8 bits of signed data from a buffer surface, sign extend to 32 bits and store the result into a vector register.", "syntax": "buffer_load_i8", "operands": [], "dataTypes": [ "i8" ], "semantics": "", "example": "buffer_load_i8 v5, off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_load_u16", "mnemonic": "buffer_load_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER LOAD U16", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Load 16 bits of unsigned data from a buffer surface, zero extend to 32 bits and store the result into a vector register.", "description": "Load 16 bits of unsigned data from a buffer surface, zero extend to 32 bits and store the result into a vector register.", "syntax": "buffer_load_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "", "example": "buffer_load_u16 v5, off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_load_u8", "mnemonic": "buffer_load_u8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER LOAD U8", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Load 8 bits of unsigned data from a buffer surface, zero extend to 32 bits and store the result into a vector register.", "description": "Load 8 bits of unsigned data from a buffer surface, zero extend to 32 bits and store the result into a vector register.", "syntax": "buffer_load_u8", "operands": [], "dataTypes": [ "u8" ], "semantics": "", "example": "buffer_load_u8 v5, off, s[8:11], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_store_b128", "mnemonic": "buffer_store_b128", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER STORE B128", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Store 128 bits of data from vector input registers into a buffer surface.", "description": "Store 128 bits of data from vector input registers into a buffer surface.", "syntax": "buffer_store_b128", "operands": [], "dataTypes": [], "semantics": "", "example": "buffer_store_b128 v[1:4], off, s[12:15], s4", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_store_b16", "mnemonic": "buffer_store_b16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER STORE B16", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Store 16 bits of data from a vector register into a buffer surface.", "description": "Store 16 bits of data from a vector register into a buffer surface.", "syntax": "buffer_store_b16", "operands": [], "dataTypes": [ "b16" ], "semantics": "", "example": "buffer_store_b16 v1, off, s[12:15], s4", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_store_b32", "mnemonic": "buffer_store_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER STORE B32", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Store 32 bits of data from vector input registers into a buffer surface.", "description": "Store 32 bits of data from vector input registers into a buffer surface.", "syntax": "buffer_store_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "buffer_store_b32 v1, off, s[12:15], s4", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_store_b64", "mnemonic": "buffer_store_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER STORE B64", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Store 64 bits of data from vector input registers into a buffer surface.", "description": "Store 64 bits of data from vector input registers into a buffer surface.", "syntax": "buffer_store_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "buffer_store_b64 v[1:2], off, s[12:15], s4", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_store_b8", "mnemonic": "buffer_store_b8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER STORE B8", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Store 8 bits of data from a vector register into a buffer surface.", "description": "Store 8 bits of data from a vector register into a buffer surface.", "syntax": "buffer_store_b8", "operands": [], "dataTypes": [ "b8" ], "semantics": "", "example": "buffer_store_b8 v1, off, s[12:15], s4", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_store_b96", "mnemonic": "buffer_store_b96", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER STORE B96", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Store 96 bits of data from vector input registers into a buffer surface.", "description": "Store 96 bits of data from vector input registers into a buffer surface.", "syntax": "buffer_store_b96", "operands": [], "dataTypes": [], "semantics": "", "example": "buffer_store_b96 v[1:3], off, s[12:15], s4", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_store_d16_format_x", "mnemonic": "buffer_store_d16_format_x", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER STORE D16 FORMAT X", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Convert 16 bits of data from the low 16 bits of a 32-bit vector input register into 1-component formatted data and store the data into a buffer…", "description": "Convert 16 bits of data from the low 16 bits of a 32-bit vector input register into 1-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor.", "syntax": "buffer_store_d16_format_x", "operands": [], "dataTypes": [], "semantics": "", "example": "buffer_store_d16_format_x v1, off, s[12:15], s4", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_store_d16_format_xy", "mnemonic": "buffer_store_d16_format_xy", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER STORE D16 FORMAT XY", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Convert 32 bits of data from vector input registers into 2-component formatted data and store the data into a buffer surface.", "description": "Convert 32 bits of data from vector input registers into 2-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor.", "syntax": "buffer_store_d16_format_xy", "operands": [], "dataTypes": [], "semantics": "", "example": "buffer_store_d16_format_xy v1, off, s[12:15], s4", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_store_d16_format_xyz", "mnemonic": "buffer_store_d16_format_xyz", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER STORE D16 FORMAT XYZ", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Convert 48 bits of data from vector input registers into 3-component formatted data and store the data into a buffer surface.", "description": "Convert 48 bits of data from vector input registers into 3-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor.", "syntax": "buffer_store_d16_format_xyz", "operands": [], "dataTypes": [], "semantics": "", "example": "buffer_store_d16_format_xyz v[1:2], off, s[12:15], s4", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_store_d16_format_xyzw", "mnemonic": "buffer_store_d16_format_xyzw", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER STORE D16 FORMAT XYZW", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Convert 64 bits of data from vector input registers into 4-component formatted data and store the data into a buffer surface.", "description": "Convert 64 bits of data from vector input registers into 4-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor.", "syntax": "buffer_store_d16_format_xyzw", "operands": [], "dataTypes": [], "semantics": "", "example": "buffer_store_d16_format_xyzw v[1:2], off, s[12:15], s4", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_store_d16_hi_b16", "mnemonic": "buffer_store_d16_hi_b16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER STORE D16 HI B16", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Store 16 bits of data from the high 16 bits of a 32-bit vector register into a buffer surface.", "description": "Store 16 bits of data from the high 16 bits of a 32-bit vector register into a buffer surface.", "syntax": "buffer_store_d16_hi_b16", "operands": [], "dataTypes": [ "b16" ], "semantics": "", "example": "buffer_store_d16_hi_b16 v1, off, s[12:15], s4", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_store_d16_hi_b8", "mnemonic": "buffer_store_d16_hi_b8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER STORE D16 HI B8", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Store 8 bits of data from the high 16 bits of a 32-bit vector register into a buffer surface.", "description": "Store 8 bits of data from the high 16 bits of a 32-bit vector register into a buffer surface.", "syntax": "buffer_store_d16_hi_b8", "operands": [], "dataTypes": [ "b8" ], "semantics": "", "example": "buffer_store_d16_hi_b8 v1, off, s[12:15], s4", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_store_d16_hi_format_x", "mnemonic": "buffer_store_d16_hi_format_x", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER STORE D16 HI FORMAT X", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Convert 16 bits of data from the high 16 bits of a 32-bit vector input register into 1-component formatted data and store the data into a buffer…", "description": "Convert 16 bits of data from the high 16 bits of a 32-bit vector input register into 1-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor.", "syntax": "buffer_store_d16_hi_format_x", "operands": [], "dataTypes": [], "semantics": "", "example": "buffer_store_d16_hi_format_x v1, off, s[12:15], s4", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.buffer_store_lds_dword", "mnemonic": "buffer_store_lds_dword", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER STORE LDS DWORD", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Store one DWORD from LDS memory to system memory without utilizing VGPRs.", "description": "Store one DWORD from LDS memory to system memory without utilizing VGPRs.", "syntax": "buffer_store_lds_dword", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.buffer_wbinvl1_sc", "mnemonic": "buffer_wbinvl1_sc", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER WBINVL1 SC", "category": "Buffer Memory", "instructionClass": "vector", "summary": "AMDGPU MUBUF vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "buffer_wbinvl1_sc", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.buffer_wbinvl1_vol", "mnemonic": "buffer_wbinvl1_vol", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER WBINVL1 VOL", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Write back and invalidate the shader L1 only for lines that are marked volatile. Returns ACK to shader.", "description": "Write back and invalidate the shader L1 only for lines that are marked volatile. Returns ACK to shader.", "syntax": "buffer_wbinvl1_vol", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.buffer_wbl2", "mnemonic": "buffer_wbl2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "BUFFER WBL2", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Write back L2 cache. Returns ACK to shader.", "description": "Write back L2 cache. Returns ACK to shader.", "syntax": "buffer_wbl2", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "MUBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 468, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.cluster_load_async_to_lds_b128", "mnemonic": "cluster_load_async_to_lds_b128", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "CLUSTER LOAD ASYNC TO LDS B128", "category": "Flat Memory", "instructionClass": "vector", "summary": "AMDGPU FLAT vector instruction operating on b128 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "cluster_load_async_to_lds_b128", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.cluster_load_async_to_lds_b32", "mnemonic": "cluster_load_async_to_lds_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "CLUSTER LOAD ASYNC TO LDS B32", "category": "Flat Memory", "instructionClass": "vector", "summary": "AMDGPU FLAT vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "cluster_load_async_to_lds_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.cluster_load_async_to_lds_b64", "mnemonic": "cluster_load_async_to_lds_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "CLUSTER LOAD ASYNC TO LDS B64", "category": "Flat Memory", "instructionClass": "vector", "summary": "AMDGPU FLAT vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "cluster_load_async_to_lds_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.cluster_load_async_to_lds_b8", "mnemonic": "cluster_load_async_to_lds_b8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "CLUSTER LOAD ASYNC TO LDS B8", "category": "Flat Memory", "instructionClass": "vector", "summary": "AMDGPU FLAT vector instruction operating on b8 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "cluster_load_async_to_lds_b8", "operands": [], "dataTypes": [ "b8" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.cluster_load_b128", "mnemonic": "cluster_load_b128", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "CLUSTER LOAD B128", "category": "Flat Memory", "instructionClass": "vector", "summary": "AMDGPU FLAT vector instruction operating on b128 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "cluster_load_b128", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.cluster_load_b32", "mnemonic": "cluster_load_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "CLUSTER LOAD B32", "category": "Flat Memory", "instructionClass": "vector", "summary": "AMDGPU FLAT vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "cluster_load_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.cluster_load_b64", "mnemonic": "cluster_load_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "CLUSTER LOAD B64", "category": "Flat Memory", "instructionClass": "vector", "summary": "AMDGPU FLAT vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "cluster_load_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_add_f32", "mnemonic": "ds_add_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS ADD F32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Add two single-precision float values stored in the data register and a location in a data share.", "description": "Add two single-precision float values stored in the data register and a location in a data share.", "syntax": "ds_add_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].f32;\nMEM[addr].f32 += DATA.f32;\nRETURN_DATA.f32 = tmp", "example": "ds_add_f32 v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Floating-point addition handles NAN/INF/denorm.", "sourcePdfPage": 424, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_add_f64", "mnemonic": "ds_add_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS ADD F64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Add a double-precision float value in the data register to a location in a data share.", "description": "Add a double-precision float value in the data register to a location in a data share.", "syntax": "ds_add_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "tmp = MEM[ADDR].f64;\nMEM[ADDR].f64 += DATA.f64;\nRETURN_DATA = tmp", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "Floating-point addition handles NAN/INF/denorm.", "sourcePdfPage": 445, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.ds_add_gs_reg_rtn", "mnemonic": "ds_add_gs_reg_rtn", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS ADD GS REG RTN", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Perform an atomic add to data in specific registers embedded in GDS rather than operating on GDS memory directly.", "description": "Perform an atomic add to data in specific registers embedded in GDS rather than operating on GDS memory directly. This instruction returns the pre-op value. This instruction is only used by the GS stage and is used to facilitate streamout.", "syntax": "ds_add_gs_reg_rtn", "operands": [], "dataTypes": [], "semantics": "", "example": "ds_add_gs_reg_rtn v[5:6], v1 gds", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_add_rtn_f32", "mnemonic": "ds_add_rtn_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS ADD RTN F32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Add two single-precision float values stored in the data register and a location in a data share.", "description": "Add two single-precision float values stored in the data register and a location in a data share. Store the original value from data share into a vector register.", "syntax": "ds_add_rtn_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].f32;\nMEM[addr].f32 += DATA.f32;\nRETURN_DATA.f32 = tmp", "example": "ds_add_rtn_f32 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Floating-point addition handles NAN/INF/denorm.", "sourcePdfPage": 431, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_add_rtn_f64", "mnemonic": "ds_add_rtn_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS ADD RTN F64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Add a double-precision float value in the data register to a location in a data share.", "description": "Add a double-precision float value in the data register to a location in a data share. Store the original value from data share into a vector register.", "syntax": "ds_add_rtn_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "tmp = MEM[ADDR].f64;\nMEM[ADDR].f64 += DATA.f64;\nRETURN_DATA = tmp", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "Floating-point addition handles NAN/INF/denorm.", "sourcePdfPage": 452, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.ds_add_rtn_u32", "mnemonic": "ds_add_rtn_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS ADD RTN U32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Add two unsigned 32-bit integer values stored in the data register and a location in a data share.", "description": "Add two unsigned 32-bit integer values stored in the data register and a location in a data share. Store the original value from data share into a vector register.", "syntax": "ds_add_rtn_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].u32;\nMEM[addr].u32 += DATA.u32;\nRETURN_DATA.u32 = tmp", "example": "ds_add_rtn_u32 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 425, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_add_rtn_u64", "mnemonic": "ds_add_rtn_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS ADD RTN U64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Add two unsigned 64-bit integer values stored in the data register and a location in a data share.", "description": "Add two unsigned 64-bit integer values stored in the data register and a location in a data share. Store the original value from data share into a vector register.", "syntax": "ds_add_rtn_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].u64;\nMEM[addr].u64 += DATA.u64;\nRETURN_DATA.u64 = tmp", "example": "ds_add_rtn_u64 v[5:6], v1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 445, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_add_src2_f32", "mnemonic": "ds_add_src2_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS ADD SRC2 F32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_add_src2_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_add_src2_u32", "mnemonic": "ds_add_src2_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS ADD SRC2 U32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_add_src2_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_add_src2_u64", "mnemonic": "ds_add_src2_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS ADD SRC2 U64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_add_src2_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_add_u32", "mnemonic": "ds_add_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS ADD U32", "category": "Atomics", "instructionClass": "vector", "summary": "Atomically add a per-lane value to an LDS location.", "description": "Add two unsigned 32-bit integer values stored in the data register and a location in a data share.", "syntax": "ds_add_u32 ADDR, DATA, offset", "operands": [ { "name": "ADDR", "desc": "Per-lane LDS byte address" }, { "name": "DATA", "desc": "Per-lane value to add" }, { "name": "offset", "desc": "Immediate byte offset" } ], "dataTypes": [ "u32" ], "semantics": "old = LDS[ADDR[lane] + offset]; LDS[...] = old + DATA[lane]; indivisible with respect to other lanes/waves in the workgroup.", "example": "ds_add_u32 v0, v1 // LDS[v0] += v1", "exampleSource": null, "encoding": { "format": "DS", "widthBits": 32 }, "executionUnit": "LDS Unit", "registerClasses": [ "VGPR" ], "memorySegment": "LDS/shared", "supportedTargets": [ "gfx942", "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "amd-machine-readable-isa" ] }, { "id": "amdgpu.ds_add_u64", "mnemonic": "ds_add_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS ADD U64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Add two unsigned 64-bit integer values stored in the data register and a location in a data share.", "description": "Add two unsigned 64-bit integer values stored in the data register and a location in a data share.", "syntax": "ds_add_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].u64;\nMEM[addr].u64 += DATA.u64;\nRETURN_DATA.u64 = tmp", "example": "ds_add_u64 v1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 438, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_and_b32", "mnemonic": "ds_and_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS AND B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in a data share.", "description": "Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in a data share.", "syntax": "ds_and_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].b32;\nMEM[addr].b32 = (tmp & DATA.b32);\nRETURN_DATA.b32 = tmp", "example": "ds_and_b32 v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 420, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_and_b64", "mnemonic": "ds_and_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS AND B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Calculate bitwise AND given two unsigned 64-bit integer values stored in the data register and a location in a data share.", "description": "Calculate bitwise AND given two unsigned 64-bit integer values stored in the data register and a location in a data share.", "syntax": "ds_and_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].b64;\nMEM[addr].b64 = (tmp & DATA.b64);\nRETURN_DATA.b64 = tmp", "example": "ds_and_b64 v1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 440, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_and_rtn_b32", "mnemonic": "ds_and_rtn_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS AND RTN B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in a data share.", "description": "Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in a data share. Store the original value from data share into a vector register.", "syntax": "ds_and_rtn_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].b32;\nMEM[addr].b32 = (tmp & DATA.b32);\nRETURN_DATA.b32 = tmp", "example": "ds_and_rtn_b32 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 428, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_and_rtn_b64", "mnemonic": "ds_and_rtn_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS AND RTN B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Calculate bitwise AND given two unsigned 64-bit integer values stored in the data register and a location in a data share.", "description": "Calculate bitwise AND given two unsigned 64-bit integer values stored in the data register and a location in a data share. Store the original value from data share into a vector register.", "syntax": "ds_and_rtn_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].b64;\nMEM[addr].b64 = (tmp & DATA.b64);\nRETURN_DATA.b64 = tmp", "example": "ds_and_rtn_b64 v[5:6], v1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 447, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_and_src2_b32", "mnemonic": "ds_and_src2_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS AND SRC2 B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_and_src2_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_and_src2_b64", "mnemonic": "ds_and_src2_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS AND SRC2 B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_and_src2_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_append", "mnemonic": "ds_append", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS APPEND", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Add (count_bits(exec_mask)) to the value stored in DS memory at (M0.base + instr_offset) if GDS, or at instr_offset if LDS.", "description": "Add (count_bits(exec_mask)) to the value stored in DS memory at (M0.base + instr_offset) if GDS, or at instr_offset if LDS. Return the pre-operation value to VGPRs.", "syntax": "ds_append", "operands": [], "dataTypes": [], "semantics": "", "example": "ds_append v5", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 456, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_atomic_async_barrier_arrive_b64", "mnemonic": "ds_atomic_async_barrier_arrive_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS ATOMIC ASYNC BARRIER ARRIVE B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_atomic_async_barrier_arrive_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_atomic_barrier_arrive_rtn_b64", "mnemonic": "ds_atomic_barrier_arrive_rtn_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS ATOMIC BARRIER ARRIVE RTN B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_atomic_barrier_arrive_rtn_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_bpermute_b32", "mnemonic": "ds_bpermute_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS BPERMUTE B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Backward permute.", "description": "Backward permute. This does not access LDS memory and may be called even if no LDS memory is allocated to the wave. It uses LDS hardware to implement an arbitrary swizzle across threads in a wavefront. Note the address passed in is the thread ID multiplied by 4. Note that EXEC mask is applied to both VGPR read and write. If src_lane selects a disabled thread then zero is returned. See also DS_PERMUTE_B32.", "syntax": "ds_bpermute_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "// VGPR[laneId][index] is the VGPR RAM\n// VDST, ADDR and DATA0 are from the microcode DS encoding\ndeclare tmp : 32'B[64];\ndeclare OFFSET : 16'U;\ndeclare DATA0 : 32'U;\ndeclare VDST : 32'U;\nfor i in 0 : 63 do\ntmp[i] = 0x0\nendfor;\nfor i in 0 : 63 do\n// ADDR needs to be divided by 4.\n// High-order bits are ignored.\nsrc_lane = (VGPR[i][ADDR].u32 + OFFSET.u32) / 4U % 64U;\n// EXEC is applied to the source VGPR reads.\nif EXEC[src_lane].u1 then\ntmp[i] = VGPR[src_lane][DATA0]\nendif\nendfor;\n// Copy data into destination VGPRs. Some source\n// data may be broadcast to multiple lanes.\nfor i in 0 : 63 do\nif EXEC[i].u1 then\nVGPR[i][VDST] = tmp[i]\nendif\nendfor", "example": "ds_bpermute_b32 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Examples (simplified 4-thread wavefronts): VGPR[SRC0] = { A, B, C, D }\nVGPR[ADDR] = { 0, 0, 12, 4 }\nEXEC = 0xF, OFFSET = 0\nVGPR[VDST] = { A, A, D, B }\nVGPR[SRC0] = { A, B, C, D }\nVGPR[ADDR] = { 0, 0, 12, 4 }\nEXEC = 0xA, OFFSET = 0\nVGPR[VDST] = { -, 0, -, B }", "sourcePdfPage": 437, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_bpermute_fi_b32", "mnemonic": "ds_bpermute_fi_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS BPERMUTE FI B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Backward permute and fetch data for invalid lanes.", "description": "Backward permute and fetch data for invalid lanes. This does not access LDS memory and may be called even if no LDS memory is allocated to the wave. It uses LDS hardware to implement an arbitrary swizzle across threads in a wavefront.", "syntax": "ds_bpermute_fi_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.ds_bvh_stack_rtn_b32", "mnemonic": "ds_bvh_stack_rtn_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS BVH STACK RTN B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Ray tracing involves traversing a BVH which is a kind of tree where nodes have up to 4 children.", "description": "Ray tracing involves traversing a BVH which is a kind of tree where nodes have up to 4 children. Each shader thread processes one child at a time, and overflow nodes are stored temporarily in LDS using a stack. This instruction supports pushing/popping the stack to reduce the number of VALU instructions required per traversal and reduce VMEM bandwidth requirements.", "syntax": "ds_bvh_stack_rtn_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "ds_bvh_stack_rtn_b32 v255, v254, v253, v[249:252]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_cmpst_b32", "mnemonic": "ds_cmpst_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS CMPST B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Compare an unsigned 32-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value…", "description": "Compare an unsigned 32-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value in the data source register if the comparison is equal.", "syntax": "ds_cmpst_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].b32;\nsrc = DATA2.b32;\ncmp = DATA.b32;\nMEM[addr].b32 = tmp == cmp ? src : tmp;\nRETURN_DATA.b32 = tmp", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "Caution, the order of src and cmp are the opposite of the BUFFER_ATOMIC_CMPSWAP opcode.", "sourcePdfPage": 422, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.ds_cmpst_b64", "mnemonic": "ds_cmpst_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS CMPST B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Compare an unsigned 64-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value…", "description": "Compare an unsigned 64-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value in the data source register if the comparison is equal.", "syntax": "ds_cmpst_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].b64;\nsrc = DATA2.b64;\ncmp = DATA.b64;\nMEM[addr].b64 = tmp == cmp ? src : tmp;\nRETURN_DATA.b64 = tmp", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "Caution, the order of src and cmp are the opposite of the BUFFER_ATOMIC_CMPSWAP opcode.", "sourcePdfPage": 442, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.ds_cmpst_f32", "mnemonic": "ds_cmpst_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS CMPST F32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Compare a single-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value…", "description": "Compare a single-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value in the data source register if the comparison is equal.", "syntax": "ds_cmpst_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].f32;\nsrc = DATA2.f32;\ncmp = DATA.f32;\nMEM[addr].f32 = tmp == cmp ? src : tmp;\nRETURN_DATA.f32 = tmp", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "Caution, the order of src and cmp are the opposite of the BUFFER_ATOMIC_CMPSWAP opcode.", "sourcePdfPage": 422, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.ds_cmpst_f64", "mnemonic": "ds_cmpst_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS CMPST F64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Compare a double-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value…", "description": "Compare a double-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value in the data source register if the comparison is equal.", "syntax": "ds_cmpst_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].f64;\nsrc = DATA2.f64;\ncmp = DATA.f64;\nMEM[addr].f64 = tmp == cmp ? src : tmp;\nRETURN_DATA.f64 = tmp", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "Caution, the order of src and cmp are the opposite of the BUFFER_ATOMIC_CMPSWAP opcode.", "sourcePdfPage": 442, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.ds_cmpst_rtn_b32", "mnemonic": "ds_cmpst_rtn_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS CMPST RTN B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Compare an unsigned 32-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value…", "description": "Compare an unsigned 32-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value in the data source register if the comparison is equal.", "syntax": "ds_cmpst_rtn_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].b32;\nsrc = DATA2.b32;\ncmp = DATA.b32;\nMEM[addr].b32 = tmp == cmp ? src : tmp;\nRETURN_DATA.b32 = tmp", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "Caution, the order of src and cmp are the opposite of the BUFFER_ATOMIC_CMPSWAP opcode.", "sourcePdfPage": 429, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.ds_cmpst_rtn_b64", "mnemonic": "ds_cmpst_rtn_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS CMPST RTN B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Compare an unsigned 64-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value…", "description": "Compare an unsigned 64-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value in the data source register if the comparison is equal.", "syntax": "ds_cmpst_rtn_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].b64;\nsrc = DATA2.b64;\ncmp = DATA.b64;\nMEM[addr].b64 = tmp == cmp ? src : tmp;\nRETURN_DATA.b64 = tmp", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "Caution, the order of src and cmp are the opposite of the BUFFER_ATOMIC_CMPSWAP opcode.", "sourcePdfPage": 449, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.ds_cmpst_rtn_f32", "mnemonic": "ds_cmpst_rtn_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS CMPST RTN F32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Compare a single-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value…", "description": "Compare a single-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value in the data source register if the comparison is equal.", "syntax": "ds_cmpst_rtn_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].f32;\nsrc = DATA2.f32;\ncmp = DATA.f32;\nMEM[addr].f32 = tmp == cmp ? src : tmp;\nRETURN_DATA.f32 = tmp", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "Caution, the order of src and cmp are the opposite of the BUFFER_ATOMIC_CMPSWAP opcode.", "sourcePdfPage": 430, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.ds_cmpst_rtn_f64", "mnemonic": "ds_cmpst_rtn_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS CMPST RTN F64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Compare a double-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value…", "description": "Compare a double-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value in the data source register if the comparison is equal.", "syntax": "ds_cmpst_rtn_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].f64;\nsrc = DATA2.f64;\ncmp = DATA.f64;\nMEM[addr].f64 = tmp == cmp ? src : tmp;\nRETURN_DATA.f64 = tmp", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "Caution, the order of src and cmp are the opposite of the BUFFER_ATOMIC_CMPSWAP opcode.", "sourcePdfPage": 450, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.ds_cmpstore_b32", "mnemonic": "ds_cmpstore_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS CMPSTORE B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Compare an unsigned 32-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value…", "description": "Compare an unsigned 32-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value in the data source register if the comparison is equal.", "syntax": "ds_cmpstore_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "ds_cmpstore_b32 v1, v2, v3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_cmpstore_b64", "mnemonic": "ds_cmpstore_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS CMPSTORE B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Compare an unsigned 64-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value…", "description": "Compare an unsigned 64-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value in the data source register if the comparison is equal.", "syntax": "ds_cmpstore_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "ds_cmpstore_b64 v1, v[2:3], v[3:4]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_cmpstore_f32", "mnemonic": "ds_cmpstore_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS CMPSTORE F32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Compare a single-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value…", "description": "Compare a single-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value in the data source register if the comparison is equal.", "syntax": "ds_cmpstore_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": "ds_cmpstore_f32 v1, v2, v3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_cmpstore_f64", "mnemonic": "ds_cmpstore_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS CMPSTORE F64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Compare a double-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value…", "description": "Compare a double-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value in the data source register if the comparison is equal.", "syntax": "ds_cmpstore_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": "ds_cmpstore_f64 v1, v[2:3], v[3:4]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_cmpstore_rtn_b32", "mnemonic": "ds_cmpstore_rtn_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS CMPSTORE RTN B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Compare an unsigned 32-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value…", "description": "Compare an unsigned 32-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value in the data source register if the comparison is equal.", "syntax": "ds_cmpstore_rtn_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "ds_cmpstore_rtn_b32 v5, v1, v2, v3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_cmpstore_rtn_b64", "mnemonic": "ds_cmpstore_rtn_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS CMPSTORE RTN B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Compare an unsigned 64-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value…", "description": "Compare an unsigned 64-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value in the data source register if the comparison is equal.", "syntax": "ds_cmpstore_rtn_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "ds_cmpstore_rtn_b64 v[5:6], v1, v[2:3], v[3:4]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_cmpstore_rtn_f32", "mnemonic": "ds_cmpstore_rtn_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS CMPSTORE RTN F32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Compare a single-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value…", "description": "Compare a single-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value in the data source register if the comparison is equal.", "syntax": "ds_cmpstore_rtn_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": "ds_cmpstore_rtn_f32 v5, v1, v2, v3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_cmpstore_rtn_f64", "mnemonic": "ds_cmpstore_rtn_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS CMPSTORE RTN F64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Compare a double-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value…", "description": "Compare a double-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value in the data source register if the comparison is equal.", "syntax": "ds_cmpstore_rtn_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": "ds_cmpstore_rtn_f64 v[5:6], v1, v[2:3], v[3:4]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_cond_sub_rtn_u32", "mnemonic": "ds_cond_sub_rtn_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS COND SUB RTN U32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Subtract an unsigned 32-bit integer value in the data register from a location in a data share only if the memory value is greater than or equal to…", "description": "Subtract an unsigned 32-bit integer value in the data register from a location in a data share only if the memory value is greater than or equal to the data register value. Store the original value from data share into a vector register.", "syntax": "ds_cond_sub_rtn_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.ds_cond_sub_u32", "mnemonic": "ds_cond_sub_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS COND SUB U32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Subtract an unsigned 32-bit integer value in the data register from a location in a data share only if the memory value is greater than or equal to…", "description": "Subtract an unsigned 32-bit integer value in the data register from a location in a data share only if the memory value is greater than or equal to the data register value.", "syntax": "ds_cond_sub_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.ds_condxchg32_rtn_b64", "mnemonic": "ds_condxchg32_rtn_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS CONDXCHG32 RTN B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Perform 2 conditional write exchanges, where each conditional write exchange writes a 32 bit value from a data register to a location in data share…", "description": "Perform 2 conditional write exchanges, where each conditional write exchange writes a 32 bit value from a data register to a location in data share iff the most significant bit of the data value is set.", "syntax": "ds_condxchg32_rtn_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "declare OFFSET0 : 8'U;\ndeclare OFFSET1 : 8'U;\ndeclare RETURN_DATA : 32'U[2];\nADDR = S0.u32;\nDATA = S1.u64;\noffset = { OFFSET1, OFFSET0 };\nADDR0 = ((ADDR + offset.u32) & 0xfff8U);\nADDR1 = ADDR0 + 4U;\nRETURN_DATA[0] = LDS[ADDR0].u32;\nif DATA[31] then\nLDS[ADDR0] = { 1'0, DATA[30 : 0] }\nendif;\nRETURN_DATA[1] = LDS[ADDR1].u32;\nif DATA[63] then\nLDS[ADDR1] = { 1'0, DATA[62 : 32] }\nendif", "example": "ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 452, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_consume", "mnemonic": "ds_consume", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS CONSUME", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Subtract (count_bits(exec_mask)) from the value stored in DS memory at (M0.base + instr_offset) if GDS, or at instr_offset if LDS.", "description": "Subtract (count_bits(exec_mask)) from the value stored in DS memory at (M0.base + instr_offset) if GDS, or at instr_offset if LDS. Return the pre-operation value to VGPRs.", "syntax": "ds_consume", "operands": [], "dataTypes": [], "semantics": "", "example": "ds_consume v5", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 456, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_dec_rtn_u32", "mnemonic": "ds_dec_rtn_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS DEC RTN U32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Decrement an unsigned 32-bit integer value from a location in a data share with wraparound to a value in the data register if the decrement yields a…", "description": "Decrement an unsigned 32-bit integer value from a location in a data share with wraparound to a value in the data register if the decrement yields a negative value. Store the original value from data share into a vector register.", "syntax": "ds_dec_rtn_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].u32;\nsrc = DATA.u32;\nMEM[addr].u32 = ((tmp == 0U) || (tmp > src)) ? src : tmp - 1U;\nRETURN_DATA.u32 = tmp", "example": "ds_dec_rtn_u32 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 426, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_dec_rtn_u64", "mnemonic": "ds_dec_rtn_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS DEC RTN U64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Decrement an unsigned 64-bit integer value from a location in a data share with wraparound to a value in the data register if the decrement yields a…", "description": "Decrement an unsigned 64-bit integer value from a location in a data share with wraparound to a value in the data register if the decrement yields a negative value. Store the original value from data share into a vector register.", "syntax": "ds_dec_rtn_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].u64;\nsrc = DATA.u64;\nMEM[addr].u64 = ((tmp == 0ULL) || (tmp > src)) ? src : tmp - 1ULL;\nRETURN_DATA.u64 = tmp", "example": "ds_dec_rtn_u64 v[5:6], v1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 446, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_dec_src2_u32", "mnemonic": "ds_dec_src2_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS DEC SRC2 U32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_dec_src2_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_dec_src2_u64", "mnemonic": "ds_dec_src2_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS DEC SRC2 U64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_dec_src2_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_dec_u32", "mnemonic": "ds_dec_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS DEC U32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Decrement an unsigned 32-bit integer value from a location in a data share with wraparound to a value in the data register if the decrement yields a…", "description": "Decrement an unsigned 32-bit integer value from a location in a data share with wraparound to a value in the data register if the decrement yields a negative value.", "syntax": "ds_dec_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].u32;\nsrc = DATA.u32;\nMEM[addr].u32 = ((tmp == 0U) || (tmp > src)) ? src : tmp - 1U;\nRETURN_DATA.u32 = tmp", "example": "ds_dec_u32 v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 419, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_dec_u64", "mnemonic": "ds_dec_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS DEC U64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Decrement an unsigned 64-bit integer value from a location in a data share with wraparound to a value in the data register if the decrement yields a…", "description": "Decrement an unsigned 64-bit integer value from a location in a data share with wraparound to a value in the data register if the decrement yields a negative value.", "syntax": "ds_dec_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].u64;\nsrc = DATA.u64;\nMEM[addr].u64 = ((tmp == 0ULL) || (tmp > src)) ? src : tmp - 1ULL;\nRETURN_DATA.u64 = tmp", "example": "ds_dec_u64 v1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 439, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_direct_load", "mnemonic": "ds_direct_load", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS DIRECT LOAD", "category": "LDS Direct / Parameter Fetch", "instructionClass": "vector", "summary": "Read a single 32-bit value from LDS to all lanes.", "description": "Read a single 32-bit value from LDS to all lanes. A single DWORD is read from LDS memory at ADDR[M0[15:0]], where M0[15:0] is a byte address and is dword-aligned. M0[18:16] specify the data type for the read and may be 0=UBYTE, 1=USHORT, 2=DWORD, 4=SBYTE, 5=SSHORT.", "syntax": "ds_direct_load", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DSDIR" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.ds_gws_barrier", "mnemonic": "ds_gws_barrier", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS GWS BARRIER", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "GDS Only: The GWS resource indicated processes this opcode by queueing it until barrier is satisfied.", "description": "GDS Only: The GWS resource indicated processes this opcode by queueing it until barrier is satisfied. The number of waves needed is passed in as DATA of first valid thread.", "syntax": "ds_gws_barrier", "operands": [], "dataTypes": [], "semantics": "//Determine the GWS resource to work on\nrid[5:0] = gds_base[5:0] + OFFSET0[5:0];\nindex = find first valid (vector mask);\nvalue = DATA[thread: index];\n// Input Decision Machine\nstate.type[rid] = BARRIER;\nif(state[rid].counter <= 0) then\nthread[rid].flag = state[rid].flag;\nENQUEUE;\nstate[rid].flag = !state.flag;\nstate[rid].counter = value;\nreturn rd_done;\nelse\nstate[rid].counter -= 1;\nthread.flag = state[rid].flag;\nENQUEUE;\nendif.\nSince the waves deliver the count for the next barrier, this function can have a different size barrier for each\noccurrence.\n// Release Machine\nif(state.type == BARRIER) then\nif(state.flag != thread.flag) then\nreturn rd_done;\nendif;\nendif.\nCAUTION: The VGPR operand MUST be even-aligned for this instruction. Only 32 bits are used but hardware\ntreats this instruction as a 64 bit read.", "example": "ds_gws_barrier v1 gds", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 454, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_gws_init", "mnemonic": "ds_gws_init", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS GWS INIT", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "GDS Only: Initialize a barrier or semaphore resource.", "description": "GDS Only: Initialize a barrier or semaphore resource.", "syntax": "ds_gws_init", "operands": [], "dataTypes": [], "semantics": "// Determine the GWS resource to work on\nrid[5:0] = gds_base[5:0] + offset0[5:0];\n// Get the value to use in init\nindex = find_first_valid(vector mask)\nvalue = DATA[thread: index]\n// Set the state of the resource\nstate.counter[rid] = lsb(value); //limit #waves\nstate.flag[rid] = 0;\nreturn rd_done; //release calling wave\nCAUTION: The VGPR operand MUST be even-aligned for this instruction. Only 32 bits are used but hardware\ntreats this instruction as a 64 bit read.", "example": "ds_gws_init v1 gds", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 453, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_gws_sema_br", "mnemonic": "ds_gws_sema_br", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS GWS SEMA BR", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "GDS Only: The GWS resource indicated processes this opcode by updating the counter by the bulk release delivered count and labeling the resource as a…", "description": "GDS Only: The GWS resource indicated processes this opcode by updating the counter by the bulk release delivered count and labeling the resource as a semaphore.", "syntax": "ds_gws_sema_br", "operands": [], "dataTypes": [], "semantics": "//Determine the GWS resource to work on\nrid[5:0] = gds_base[5:0] + offset0[5:0];\nindex = find first valid (vector mask)\ncount = DATA[thread: index];\n//Add count to the resource state counter\nstate.counter[rid] += count;\nstate.type = SEMAPHORE;\nreturn rd_done; //release calling wave\nThis action releases count number of waves, promptly if queued, or as they arrive from the noted resource.\nCAUTION: The VGPR operand MUST be even-aligned for this instruction. Only 32 bits are used but hardware\ntreats this instruction as a 64 bit read.", "example": "ds_gws_sema_br v1 gds", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 453, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_gws_sema_p", "mnemonic": "ds_gws_sema_p", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS GWS SEMA P", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "GDS Only: The GWS resource indicated processes this opcode by queueing it until counter enables a release and then decrementing the counter of the…", "description": "GDS Only: The GWS resource indicated processes this opcode by queueing it until counter enables a release and then decrementing the counter of the resource as a semaphore.", "syntax": "ds_gws_sema_p", "operands": [], "dataTypes": [], "semantics": "//Determine the GWS resource to work on\nrid[5:0] = gds_base[5:0] + offset0[5:0];\nstate.type = SEMAPHORE;\nENQUEUE until(state[rid].counter > 0)\nstate[rid].counter -= 1;\nreturn rd_done;", "example": "ds_gws_sema_p gds", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 454, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_gws_sema_release_all", "mnemonic": "ds_gws_sema_release_all", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS GWS SEMA RELEASE ALL", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "GDS Only: The GWS resource (rid) indicated processes this opcode by updating the counter and labeling the specified resource as a semaphore.", "description": "GDS Only: The GWS resource (rid) indicated processes this opcode by updating the counter and labeling the specified resource as a semaphore.", "syntax": "ds_gws_sema_release_all", "operands": [], "dataTypes": [], "semantics": "// Determine the GWS resource to work on\nrid[5:0] = gds_base[5:0] + offset0[5:0];\n// Incr the state counter of the resource\nstate.counter[rid] = state.wave_in_queue;\nstate.type = SEMAPHORE;\nreturn rd_done; //release calling wave\nThis action releases ALL queued waves; it has no effect if no waves are present.", "example": "ds_gws_sema_release_all gds", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 452, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_gws_sema_v", "mnemonic": "ds_gws_sema_v", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS GWS SEMA V", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "GDS Only: The GWS resource indicated processes this opcode by updating the counter and labeling the resource as a semaphore.", "description": "GDS Only: The GWS resource indicated processes this opcode by updating the counter and labeling the resource as a semaphore.", "syntax": "ds_gws_sema_v", "operands": [], "dataTypes": [], "semantics": "//Determine the GWS resource to work on\nrid[5:0] = gds_base[5:0] + offset0[5:0];\n//Incr the state counter of the resource\nstate.counter[rid] += 1;\nstate.type = SEMAPHORE;\nreturn rd_done; //release calling wave\nThis action releases one wave if any are queued in this resource.", "example": "ds_gws_sema_v gds", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 453, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_inc_rtn_u32", "mnemonic": "ds_inc_rtn_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS INC RTN U32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Increment an unsigned 32-bit integer value from a location in a data share with wraparound to 0 if the value exceeds a value in the data register.", "description": "Increment an unsigned 32-bit integer value from a location in a data share with wraparound to 0 if the value exceeds a value in the data register. Store the original value from data share into a vector register.", "syntax": "ds_inc_rtn_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].u32;\nsrc = DATA.u32;\nMEM[addr].u32 = tmp >= src ? 0U : tmp + 1U;\nRETURN_DATA.u32 = tmp", "example": "ds_inc_rtn_u32 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 426, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_inc_rtn_u64", "mnemonic": "ds_inc_rtn_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS INC RTN U64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Increment an unsigned 64-bit integer value from a location in a data share with wraparound to 0 if the value exceeds a value in the data register.", "description": "Increment an unsigned 64-bit integer value from a location in a data share with wraparound to 0 if the value exceeds a value in the data register. Store the original value from data share into a vector register.", "syntax": "ds_inc_rtn_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].u64;\nsrc = DATA.u64;\nMEM[addr].u64 = tmp >= src ? 0ULL : tmp + 1ULL;\nRETURN_DATA.u64 = tmp", "example": "ds_inc_rtn_u64 v[5:6], v1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 446, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_inc_src2_u32", "mnemonic": "ds_inc_src2_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS INC SRC2 U32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_inc_src2_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_inc_src2_u64", "mnemonic": "ds_inc_src2_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS INC SRC2 U64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_inc_src2_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_inc_u32", "mnemonic": "ds_inc_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS INC U32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Increment an unsigned 32-bit integer value from a location in a data share with wraparound to 0 if the value exceeds a value in the data register.", "description": "Increment an unsigned 32-bit integer value from a location in a data share with wraparound to 0 if the value exceeds a value in the data register.", "syntax": "ds_inc_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].u32;\nsrc = DATA.u32;\nMEM[addr].u32 = tmp >= src ? 0U : tmp + 1U;\nRETURN_DATA.u32 = tmp", "example": "ds_inc_u32 v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 419, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_inc_u64", "mnemonic": "ds_inc_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS INC U64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Increment an unsigned 64-bit integer value from a location in a data share with wraparound to 0 if the value exceeds a value in the data register.", "description": "Increment an unsigned 64-bit integer value from a location in a data share with wraparound to 0 if the value exceeds a value in the data register.", "syntax": "ds_inc_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].u64;\nsrc = DATA.u64;\nMEM[addr].u64 = tmp >= src ? 0ULL : tmp + 1ULL;\nRETURN_DATA.u64 = tmp", "example": "ds_inc_u64 v1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 438, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_load_2addr_b32", "mnemonic": "ds_load_2addr_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS LOAD 2ADDR B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 32 bits of data from one location in a data share and then 32 bits of data from a second location in a data share and store the results into a…", "description": "Load 32 bits of data from one location in a data share and then 32 bits of data from a second location in a data share and store the results into a 64-bit vector register.", "syntax": "ds_load_2addr_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "ds_load_2addr_b32 v[5:6], v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_load_2addr_b64", "mnemonic": "ds_load_2addr_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS LOAD 2ADDR B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 64 bits of data from one location in a data share and then 64 bits of data from a second location in a data share and store the results into a…", "description": "Load 64 bits of data from one location in a data share and then 64 bits of data from a second location in a data share and store the results into a 128-bit vector register.", "syntax": "ds_load_2addr_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "ds_load_2addr_b64 v[5:8], v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_load_2addr_stride64_b32", "mnemonic": "ds_load_2addr_stride64_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS LOAD 2ADDR STRIDE64 B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 32 bits of data from one location in a data share and then 32 bits of data from a second location in a data share and store the results into a…", "description": "Load 32 bits of data from one location in a data share and then 32 bits of data from a second location in a data share and store the results into a 64-bit vector register. Treat each offset as an index and multiply by a stride of 64 elements (256 bytes) to generate an offset for each DS address.", "syntax": "ds_load_2addr_stride64_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "ds_load_2addr_stride64_b32 v[5:6], v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_load_2addr_stride64_b64", "mnemonic": "ds_load_2addr_stride64_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS LOAD 2ADDR STRIDE64 B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 64 bits of data from one location in a data share and then 64 bits of data from a second location in a data share and store the results into a…", "description": "Load 64 bits of data from one location in a data share and then 64 bits of data from a second location in a data share and store the results into a 128-bit vector register. Treat each offset as an index and multiply by a stride of 64 elements (256 bytes) to generate an offset for each DS address.", "syntax": "ds_load_2addr_stride64_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "ds_load_2addr_stride64_b64 v[5:8], v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_load_addtid_b32", "mnemonic": "ds_load_addtid_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS LOAD ADDTID B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 32 bits of data from a data share into a vector register.", "description": "Load 32 bits of data from a data share into a vector register. The memory base address is provided as an immediate value and the lane ID is used as an offset.", "syntax": "ds_load_addtid_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "ds_load_addtid_b32 v5", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_load_b128", "mnemonic": "ds_load_b128", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS LOAD B128", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 128 bits of data from a data share into a vector register.", "description": "Load 128 bits of data from a data share into a vector register.", "syntax": "ds_load_b128", "operands": [], "dataTypes": [], "semantics": "", "example": "ds_load_b128 v[5:8], v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_load_b32", "mnemonic": "ds_load_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS LOAD B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 32 bits of data from a data share into a vector register.", "description": "Load 32 bits of data from a data share into a vector register.", "syntax": "ds_load_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "ds_load_b32 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_load_b64", "mnemonic": "ds_load_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS LOAD B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 64 bits of data from a data share into a vector register.", "description": "Load 64 bits of data from a data share into a vector register.", "syntax": "ds_load_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "ds_load_b64 v[5:6], v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_load_b96", "mnemonic": "ds_load_b96", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS LOAD B96", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 96 bits of data from a data share into a vector register.", "description": "Load 96 bits of data from a data share into a vector register.", "syntax": "ds_load_b96", "operands": [], "dataTypes": [], "semantics": "", "example": "ds_load_b96 v[5:7], v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_load_i16", "mnemonic": "ds_load_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS LOAD I16", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 16 bits of signed data from a data share, sign extend to 32 bits and store the result into a vector register.", "description": "Load 16 bits of signed data from a data share, sign extend to 32 bits and store the result into a vector register.", "syntax": "ds_load_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "", "example": "ds_load_i16 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_load_i8", "mnemonic": "ds_load_i8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS LOAD I8", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 8 bits of signed data from a data share, sign extend to 32 bits and store the result into a vector register.", "description": "Load 8 bits of signed data from a data share, sign extend to 32 bits and store the result into a vector register.", "syntax": "ds_load_i8", "operands": [], "dataTypes": [ "i8" ], "semantics": "", "example": "ds_load_i8 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_load_i8_d16", "mnemonic": "ds_load_i8_d16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS LOAD I8 D16", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 8 bits of signed data from a data share, sign extend to 16 bits and store the result into the low 16 bits of a vector register.", "description": "Load 8 bits of signed data from a data share, sign extend to 16 bits and store the result into the low 16 bits of a vector register.", "syntax": "ds_load_i8_d16", "operands": [], "dataTypes": [ "i8" ], "semantics": "", "example": "ds_load_i8_d16 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_load_i8_d16_hi", "mnemonic": "ds_load_i8_d16_hi", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS LOAD I8 D16 HI", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 8 bits of signed data from a data share, sign extend to 16 bits and store the result into the high 16 bits of a vector register.", "description": "Load 8 bits of signed data from a data share, sign extend to 16 bits and store the result into the high 16 bits of a vector register.", "syntax": "ds_load_i8_d16_hi", "operands": [], "dataTypes": [ "i8" ], "semantics": "", "example": "ds_load_i8_d16_hi v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_load_tr16_b128", "mnemonic": "ds_load_tr16_b128", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS LOAD TR16 B128", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on b128 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_load_tr16_b128", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_load_tr4_b64", "mnemonic": "ds_load_tr4_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS LOAD TR4 B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_load_tr4_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_load_tr6_b96", "mnemonic": "ds_load_tr6_b96", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS LOAD TR6 B96", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on b96 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_load_tr6_b96", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_load_tr8_b64", "mnemonic": "ds_load_tr8_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS LOAD TR8 B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_load_tr8_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_load_u16", "mnemonic": "ds_load_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS LOAD U16", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 16 bits of unsigned data from a data share, zero extend to 32 bits and store the result into a vector register.", "description": "Load 16 bits of unsigned data from a data share, zero extend to 32 bits and store the result into a vector register.", "syntax": "ds_load_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "", "example": "ds_load_u16 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_load_u16_d16", "mnemonic": "ds_load_u16_d16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS LOAD U16 D16", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 16 bits of unsigned data from a data share and store the result into the low 16 bits of a vector register.", "description": "Load 16 bits of unsigned data from a data share and store the result into the low 16 bits of a vector register.", "syntax": "ds_load_u16_d16", "operands": [], "dataTypes": [ "u16" ], "semantics": "", "example": "ds_load_u16_d16 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_load_u16_d16_hi", "mnemonic": "ds_load_u16_d16_hi", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS LOAD U16 D16 HI", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 16 bits of unsigned data from a data share and store the result into the high 16 bits of a vector register.", "description": "Load 16 bits of unsigned data from a data share and store the result into the high 16 bits of a vector register.", "syntax": "ds_load_u16_d16_hi", "operands": [], "dataTypes": [ "u16" ], "semantics": "", "example": "ds_load_u16_d16_hi v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_load_u8", "mnemonic": "ds_load_u8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS LOAD U8", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 8 bits of unsigned data from a data share, zero extend to 32 bits and store the result into a vector register.", "description": "Load 8 bits of unsigned data from a data share, zero extend to 32 bits and store the result into a vector register.", "syntax": "ds_load_u8", "operands": [], "dataTypes": [ "u8" ], "semantics": "", "example": "ds_load_u8 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_load_u8_d16", "mnemonic": "ds_load_u8_d16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS LOAD U8 D16", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 8 bits of unsigned data from a data share, zero extend to 16 bits and store the result into the low 16 bits of a vector register.", "description": "Load 8 bits of unsigned data from a data share, zero extend to 16 bits and store the result into the low 16 bits of a vector register.", "syntax": "ds_load_u8_d16", "operands": [], "dataTypes": [ "u8" ], "semantics": "", "example": "ds_load_u8_d16 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_load_u8_d16_hi", "mnemonic": "ds_load_u8_d16_hi", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS LOAD U8 D16 HI", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 8 bits of unsigned data from a data share, zero extend to 16 bits and store the result into the high 16 bits of a vector register.", "description": "Load 8 bits of unsigned data from a data share, zero extend to 16 bits and store the result into the high 16 bits of a vector register.", "syntax": "ds_load_u8_d16_hi", "operands": [], "dataTypes": [ "u8" ], "semantics": "", "example": "ds_load_u8_d16_hi v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_max_f32", "mnemonic": "ds_max_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MAX F32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Select the maximum of two single-precision float inputs, given two values stored in the data register and a location in a data share.", "description": "Select the maximum of two single-precision float inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value.", "syntax": "ds_max_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].f32;\nsrc = DATA.f32;\nMEM[addr].f32 = src > tmp ? src : tmp;\nRETURN_DATA.f32 = tmp", "example": "ds_max_f32 v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Floating-point compare handles NAN/INF/denorm.", "sourcePdfPage": 423, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_max_f64", "mnemonic": "ds_max_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MAX F64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Select the maximum of two double-precision float inputs, given two values stored in the data register and a location in a data share.", "description": "Select the maximum of two double-precision float inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value.", "syntax": "ds_max_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].f64;\nsrc = DATA.f64;\nMEM[addr].f64 = src > tmp ? src : tmp;\nRETURN_DATA.f64 = tmp", "example": "ds_max_f64 v1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Floating-point compare handles NAN/INF/denorm.", "sourcePdfPage": 443, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_max_i32", "mnemonic": "ds_max_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MAX I32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Select the maximum of two signed 32-bit integer inputs, given two values stored in the data register and a location in a data share.", "description": "Select the maximum of two signed 32-bit integer inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value.", "syntax": "ds_max_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].i32;\nsrc = DATA.i32;\nMEM[addr].i32 = src >= tmp ? src : tmp;\nRETURN_DATA.i32 = tmp", "example": "ds_max_i32 v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 420, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_max_i64", "mnemonic": "ds_max_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MAX I64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Select the maximum of two signed 64-bit integer inputs, given two values stored in the data register and a location in a data share.", "description": "Select the maximum of two signed 64-bit integer inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value.", "syntax": "ds_max_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].i64;\nsrc = DATA.i64;\nMEM[addr].i64 = src >= tmp ? src : tmp;\nRETURN_DATA.i64 = tmp", "example": "ds_max_i64 v1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 439, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_max_num_f32", "mnemonic": "ds_max_num_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MAX NUM F32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Select the IEEE maximumNumber() of two single-precision float inputs, given two values stored in the data register and a location in a data share.", "description": "Select the IEEE maximumNumber() of two single-precision float inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value.", "syntax": "ds_max_num_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.ds_max_num_f64", "mnemonic": "ds_max_num_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MAX NUM F64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Select the IEEE maximumNumber() of two double-precision float inputs, given two values stored in the data register and a location in a data share.", "description": "Select the IEEE maximumNumber() of two double-precision float inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value.", "syntax": "ds_max_num_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.ds_max_num_rtn_f32", "mnemonic": "ds_max_num_rtn_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MAX NUM RTN F32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Select the IEEE maximumNumber() of two single-precision float inputs, given two values stored in the data register and a location in a data share.", "description": "Select the IEEE maximumNumber() of two single-precision float inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value. Store the original value from data share into a vector register.", "syntax": "ds_max_num_rtn_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.ds_max_num_rtn_f64", "mnemonic": "ds_max_num_rtn_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MAX NUM RTN F64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Select the IEEE maximumNumber() of two double-precision float inputs, given two values stored in the data register and a location in a data share.", "description": "Select the IEEE maximumNumber() of two double-precision float inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value. Store the original value from data share into a vector register.", "syntax": "ds_max_num_rtn_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.ds_max_rtn_f32", "mnemonic": "ds_max_rtn_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MAX RTN F32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Select the maximum of two single-precision float inputs, given two values stored in the data register and a location in a data share.", "description": "Select the maximum of two single-precision float inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value. Store the original value from data share into a vector register.", "syntax": "ds_max_rtn_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].f32;\nsrc = DATA.f32;\nMEM[addr].f32 = src > tmp ? src : tmp;\nRETURN_DATA.f32 = tmp", "example": "ds_max_rtn_f32 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Floating-point compare handles NAN/INF/denorm.", "sourcePdfPage": 430, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_max_rtn_f64", "mnemonic": "ds_max_rtn_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MAX RTN F64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Select the maximum of two double-precision float inputs, given two values stored in the data register and a location in a data share.", "description": "Select the maximum of two double-precision float inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value. Store the original value from data share into a vector register.", "syntax": "ds_max_rtn_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].f64;\nsrc = DATA.f64;\nMEM[addr].f64 = src > tmp ? src : tmp;\nRETURN_DATA.f64 = tmp", "example": "ds_max_rtn_f64 v[5:6], v1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Floating-point compare handles NAN/INF/denorm.", "sourcePdfPage": 450, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_max_rtn_i32", "mnemonic": "ds_max_rtn_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MAX RTN I32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Select the maximum of two signed 32-bit integer inputs, given two values stored in the data register and a location in a data share.", "description": "Select the maximum of two signed 32-bit integer inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value. Store the original value from data share into a vector register.", "syntax": "ds_max_rtn_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].i32;\nsrc = DATA.i32;\nMEM[addr].i32 = src >= tmp ? src : tmp;\nRETURN_DATA.i32 = tmp", "example": "ds_max_rtn_i32 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 427, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_max_rtn_i64", "mnemonic": "ds_max_rtn_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MAX RTN I64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Select the maximum of two signed 64-bit integer inputs, given two values stored in the data register and a location in a data share.", "description": "Select the maximum of two signed 64-bit integer inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value. Store the original value from data share into a vector register.", "syntax": "ds_max_rtn_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].i64;\nsrc = DATA.i64;\nMEM[addr].i64 = src >= tmp ? src : tmp;\nRETURN_DATA.i64 = tmp", "example": "ds_max_rtn_i64 v[5:6], v1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 447, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_max_rtn_u32", "mnemonic": "ds_max_rtn_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MAX RTN U32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Select the maximum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in a data share.", "description": "Select the maximum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value. Store the original value from data share into a vector register.", "syntax": "ds_max_rtn_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].u32;\nsrc = DATA.u32;\nMEM[addr].u32 = src >= tmp ? src : tmp;\nRETURN_DATA.u32 = tmp", "example": "ds_max_rtn_u32 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 427, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_max_rtn_u64", "mnemonic": "ds_max_rtn_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MAX RTN U64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Select the maximum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in a data share.", "description": "Select the maximum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value. Store the original value from data share into a vector register.", "syntax": "ds_max_rtn_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].u64;\nsrc = DATA.u64;\nMEM[addr].u64 = src >= tmp ? src : tmp;\nRETURN_DATA.u64 = tmp", "example": "ds_max_rtn_u64 v[5:6], v1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 447, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_max_src2_f32", "mnemonic": "ds_max_src2_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MAX SRC2 F32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_max_src2_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_max_src2_f64", "mnemonic": "ds_max_src2_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MAX SRC2 F64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_max_src2_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_max_src2_i32", "mnemonic": "ds_max_src2_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MAX SRC2 I32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_max_src2_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_max_src2_i64", "mnemonic": "ds_max_src2_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MAX SRC2 I64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_max_src2_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_max_src2_u32", "mnemonic": "ds_max_src2_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MAX SRC2 U32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_max_src2_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_max_src2_u64", "mnemonic": "ds_max_src2_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MAX SRC2 U64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_max_src2_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_max_u32", "mnemonic": "ds_max_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MAX U32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Select the maximum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in a data share.", "description": "Select the maximum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value.", "syntax": "ds_max_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].u32;\nsrc = DATA.u32;\nMEM[addr].u32 = src >= tmp ? src : tmp;\nRETURN_DATA.u32 = tmp", "example": "ds_max_u32 v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 420, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_max_u64", "mnemonic": "ds_max_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MAX U64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Select the maximum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in a data share.", "description": "Select the maximum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value.", "syntax": "ds_max_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].u64;\nsrc = DATA.u64;\nMEM[addr].u64 = src >= tmp ? src : tmp;\nRETURN_DATA.u64 = tmp", "example": "ds_max_u64 v1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 440, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_min_f32", "mnemonic": "ds_min_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MIN F32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Select the minimum of two single-precision float inputs, given two values stored in the data register and a location in a data share.", "description": "Select the minimum of two single-precision float inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value.", "syntax": "ds_min_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].f32;\nsrc = DATA.f32;\nMEM[addr].f32 = src < tmp ? src : tmp;\nRETURN_DATA.f32 = tmp", "example": "ds_min_f32 v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Floating-point compare handles NAN/INF/denorm.", "sourcePdfPage": 423, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_min_f64", "mnemonic": "ds_min_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MIN F64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in a data share.", "description": "Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value.", "syntax": "ds_min_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].f64;\nsrc = DATA.f64;\nMEM[addr].f64 = src < tmp ? src : tmp;\nRETURN_DATA.f64 = tmp", "example": "ds_min_f64 v1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Floating-point compare handles NAN/INF/denorm.", "sourcePdfPage": 442, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_min_i32", "mnemonic": "ds_min_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MIN I32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Select the minimum of two signed 32-bit integer inputs, given two values stored in the data register and a location in a data share.", "description": "Select the minimum of two signed 32-bit integer inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value.", "syntax": "ds_min_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].i32;\nsrc = DATA.i32;\nMEM[addr].i32 = src < tmp ? src : tmp;\nRETURN_DATA.i32 = tmp", "example": "ds_min_i32 v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 419, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_min_i64", "mnemonic": "ds_min_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MIN I64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Select the minimum of two signed 64-bit integer inputs, given two values stored in the data register and a location in a data share.", "description": "Select the minimum of two signed 64-bit integer inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value.", "syntax": "ds_min_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].i64;\nsrc = DATA.i64;\nMEM[addr].i64 = src < tmp ? src : tmp;\nRETURN_DATA.i64 = tmp", "example": "ds_min_i64 v1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 439, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_min_num_f32", "mnemonic": "ds_min_num_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MIN NUM F32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Select the IEEE minimumNumber() of two single-precision float inputs, given two values stored in the data register and a location in a data share.", "description": "Select the IEEE minimumNumber() of two single-precision float inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value.", "syntax": "ds_min_num_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.ds_min_num_f64", "mnemonic": "ds_min_num_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MIN NUM F64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Select the IEEE minimumNumber() of two double-precision float inputs, given two values stored in the data register and a location in a data share.", "description": "Select the IEEE minimumNumber() of two double-precision float inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value.", "syntax": "ds_min_num_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.ds_min_num_rtn_f32", "mnemonic": "ds_min_num_rtn_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MIN NUM RTN F32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Select the IEEE minimumNumber() of two single-precision float inputs, given two values stored in the data register and a location in a data share.", "description": "Select the IEEE minimumNumber() of two single-precision float inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value. Store the original value from data share into a vector register.", "syntax": "ds_min_num_rtn_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.ds_min_num_rtn_f64", "mnemonic": "ds_min_num_rtn_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MIN NUM RTN F64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Select the IEEE minimumNumber() of two double-precision float inputs, given two values stored in the data register and a location in a data share.", "description": "Select the IEEE minimumNumber() of two double-precision float inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value. Store the original value from data share into a vector register.", "syntax": "ds_min_num_rtn_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.ds_min_rtn_f32", "mnemonic": "ds_min_rtn_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MIN RTN F32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Select the minimum of two single-precision float inputs, given two values stored in the data register and a location in a data share.", "description": "Select the minimum of two single-precision float inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value. Store the original value from data share into a vector register.", "syntax": "ds_min_rtn_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].f32;\nsrc = DATA.f32;\nMEM[addr].f32 = src < tmp ? src : tmp;\nRETURN_DATA.f32 = tmp", "example": "ds_min_rtn_f32 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Floating-point compare handles NAN/INF/denorm.", "sourcePdfPage": 430, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_min_rtn_f64", "mnemonic": "ds_min_rtn_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MIN RTN F64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in a data share.", "description": "Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value. Store the original value from data share into a vector register.", "syntax": "ds_min_rtn_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].f64;\nsrc = DATA.f64;\nMEM[addr].f64 = src < tmp ? src : tmp;\nRETURN_DATA.f64 = tmp", "example": "ds_min_rtn_f64 v[5:6], v1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Floating-point compare handles NAN/INF/denorm.", "sourcePdfPage": 450, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_min_rtn_i32", "mnemonic": "ds_min_rtn_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MIN RTN I32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Select the minimum of two signed 32-bit integer inputs, given two values stored in the data register and a location in a data share.", "description": "Select the minimum of two signed 32-bit integer inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value. Store the original value from data share into a vector register.", "syntax": "ds_min_rtn_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].i32;\nsrc = DATA.i32;\nMEM[addr].i32 = src < tmp ? src : tmp;\nRETURN_DATA.i32 = tmp", "example": "ds_min_rtn_i32 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 426, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_min_rtn_i64", "mnemonic": "ds_min_rtn_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MIN RTN I64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Select the minimum of two signed 64-bit integer inputs, given two values stored in the data register and a location in a data share.", "description": "Select the minimum of two signed 64-bit integer inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value. Store the original value from data share into a vector register.", "syntax": "ds_min_rtn_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].i64;\nsrc = DATA.i64;\nMEM[addr].i64 = src < tmp ? src : tmp;\nRETURN_DATA.i64 = tmp", "example": "ds_min_rtn_i64 v[5:6], v1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 446, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_min_rtn_u32", "mnemonic": "ds_min_rtn_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MIN RTN U32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Select the minimum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in a data share.", "description": "Select the minimum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value. Store the original value from data share into a vector register.", "syntax": "ds_min_rtn_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].u32;\nsrc = DATA.u32;\nMEM[addr].u32 = src < tmp ? src : tmp;\nRETURN_DATA.u32 = tmp", "example": "ds_min_rtn_u32 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 427, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_min_rtn_u64", "mnemonic": "ds_min_rtn_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MIN RTN U64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Select the minimum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in a data share.", "description": "Select the minimum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value. Store the original value from data share into a vector register.", "syntax": "ds_min_rtn_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].u64;\nsrc = DATA.u64;\nMEM[addr].u64 = src < tmp ? src : tmp;\nRETURN_DATA.u64 = tmp", "example": "ds_min_rtn_u64 v[5:6], v1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 447, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_min_src2_f32", "mnemonic": "ds_min_src2_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MIN SRC2 F32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_min_src2_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_min_src2_f64", "mnemonic": "ds_min_src2_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MIN SRC2 F64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_min_src2_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_min_src2_i32", "mnemonic": "ds_min_src2_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MIN SRC2 I32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_min_src2_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_min_src2_i64", "mnemonic": "ds_min_src2_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MIN SRC2 I64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_min_src2_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_min_src2_u32", "mnemonic": "ds_min_src2_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MIN SRC2 U32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_min_src2_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_min_src2_u64", "mnemonic": "ds_min_src2_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MIN SRC2 U64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_min_src2_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_min_u32", "mnemonic": "ds_min_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MIN U32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Select the minimum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in a data share.", "description": "Select the minimum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value.", "syntax": "ds_min_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].u32;\nsrc = DATA.u32;\nMEM[addr].u32 = src < tmp ? src : tmp;\nRETURN_DATA.u32 = tmp", "example": "ds_min_u32 v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 420, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_min_u64", "mnemonic": "ds_min_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MIN U64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Select the minimum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in a data share.", "description": "Select the minimum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value.", "syntax": "ds_min_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].u64;\nsrc = DATA.u64;\nMEM[addr].u64 = src < tmp ? src : tmp;\nRETURN_DATA.u64 = tmp", "example": "ds_min_u64 v1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 439, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_mskor_b32", "mnemonic": "ds_mskor_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MSKOR B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Calculate masked bitwise OR on an unsigned 32-bit integer location in a data share, given mask value and bits to OR in the data registers.", "description": "Calculate masked bitwise OR on an unsigned 32-bit integer location in a data share, given mask value and bits to OR in the data registers.", "syntax": "ds_mskor_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].b32;\nMEM[addr].b32 = ((tmp & ~DATA.b32) | DATA2.b32);\nRETURN_DATA.b32 = tmp", "example": "ds_mskor_b32 v1, v2, v3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 421, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_mskor_b64", "mnemonic": "ds_mskor_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MSKOR B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Calculate masked bitwise OR on an unsigned 64-bit integer location in a data share, given mask value and bits to OR in the data registers.", "description": "Calculate masked bitwise OR on an unsigned 64-bit integer location in a data share, given mask value and bits to OR in the data registers.", "syntax": "ds_mskor_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].b64;\nMEM[addr].b64 = ((tmp & ~DATA.b64) | DATA2.b64);\nRETURN_DATA.b64 = tmp", "example": "ds_mskor_b64 v1, v[2:3], v[3:4]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 441, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_mskor_rtn_b32", "mnemonic": "ds_mskor_rtn_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MSKOR RTN B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Calculate masked bitwise OR on an unsigned 32-bit integer location in a data share, given mask value and bits to OR in the data registers.", "description": "Calculate masked bitwise OR on an unsigned 32-bit integer location in a data share, given mask value and bits to OR in the data registers.", "syntax": "ds_mskor_rtn_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].b32;\nMEM[addr].b32 = ((tmp & ~DATA.b32) | DATA2.b32);\nRETURN_DATA.b32 = tmp", "example": "ds_mskor_rtn_b32 v5, v1, v2, v3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 428, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_mskor_rtn_b64", "mnemonic": "ds_mskor_rtn_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS MSKOR RTN B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Calculate masked bitwise OR on an unsigned 64-bit integer location in a data share, given mask value and bits to OR in the data registers.", "description": "Calculate masked bitwise OR on an unsigned 64-bit integer location in a data share, given mask value and bits to OR in the data registers.", "syntax": "ds_mskor_rtn_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].b64;\nMEM[addr].b64 = ((tmp & ~DATA.b64) | DATA2.b64);\nRETURN_DATA.b64 = tmp", "example": "ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 448, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_nop", "mnemonic": "ds_nop", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS NOP", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Do nothing.", "description": "Do nothing.", "syntax": "ds_nop", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 423, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.ds_or_b32", "mnemonic": "ds_or_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS OR B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Calculate bitwise OR given two unsigned 32-bit integer values stored in the data register and a location in a data share.", "description": "Calculate bitwise OR given two unsigned 32-bit integer values stored in the data register and a location in a data share.", "syntax": "ds_or_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].b32;\nMEM[addr].b32 = (tmp | DATA.b32);\nRETURN_DATA.b32 = tmp", "example": "ds_or_b32 v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 421, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_or_b64", "mnemonic": "ds_or_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS OR B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Calculate bitwise OR given two unsigned 64-bit integer values stored in the data register and a location in a data share.", "description": "Calculate bitwise OR given two unsigned 64-bit integer values stored in the data register and a location in a data share.", "syntax": "ds_or_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].b64;\nMEM[addr].b64 = (tmp | DATA.b64);\nRETURN_DATA.b64 = tmp", "example": "ds_or_b64 v1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 440, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_or_rtn_b32", "mnemonic": "ds_or_rtn_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS OR RTN B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Calculate bitwise OR given two unsigned 32-bit integer values stored in the data register and a location in a data share.", "description": "Calculate bitwise OR given two unsigned 32-bit integer values stored in the data register and a location in a data share. Store the original value from data share into a vector register.", "syntax": "ds_or_rtn_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].b32;\nMEM[addr].b32 = (tmp | DATA.b32);\nRETURN_DATA.b32 = tmp", "example": "ds_or_rtn_b32 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 428, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_or_rtn_b64", "mnemonic": "ds_or_rtn_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS OR RTN B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Calculate bitwise OR given two unsigned 64-bit integer values stored in the data register and a location in a data share.", "description": "Calculate bitwise OR given two unsigned 64-bit integer values stored in the data register and a location in a data share. Store the original value from data share into a vector register.", "syntax": "ds_or_rtn_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].b64;\nMEM[addr].b64 = (tmp | DATA.b64);\nRETURN_DATA.b64 = tmp", "example": "ds_or_rtn_b64 v[5:6], v1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 448, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_or_src2_b32", "mnemonic": "ds_or_src2_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS OR SRC2 B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_or_src2_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_or_src2_b64", "mnemonic": "ds_or_src2_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS OR SRC2 B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_or_src2_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_ordered_count", "mnemonic": "ds_ordered_count", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS ORDERED COUNT", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "GDS-only.", "description": "GDS-only. Add (count_bits(exec_mask)) to one of 4 dedicated ordered-count counters (aka 'packers'). Additional bits of instr.offset field are overloaded to hold packer-id, 'last'.", "syntax": "ds_ordered_count", "operands": [], "dataTypes": [], "semantics": "", "example": "ds_ordered_count v5, v1 gds", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_param_load", "mnemonic": "ds_param_load", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS PARAM LOAD", "category": "LDS Direct / Parameter Fetch", "instructionClass": "vector", "summary": "Transfer parameter data from LDS to VGPRs and expand data in LDS using the NewPrimMask (provided in M0) to place per-quad data into lanes 0-3 of each…", "description": "Transfer parameter data from LDS to VGPRs and expand data in LDS using the NewPrimMask (provided in M0) to place per-quad data into lanes 0-3 of each quad as follows:", "syntax": "ds_param_load", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DSDIR" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.ds_permute_b32", "mnemonic": "ds_permute_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS PERMUTE B32", "category": "Lane Operations", "instructionClass": "vector", "summary": "Forward-permute: each lane sends its value to a lane index computed by another lane, via the LDS crossbar (no LDS storage consumed).", "description": "Forward permute. This does not access LDS memory and may be called even if no LDS memory is allocated to the wave. It uses LDS to implement an arbitrary swizzle across threads in a wavefront.", "syntax": "ds_permute_b32 VDST, ADDR, DATA", "operands": [ { "name": "VDST", "desc": "Destination VGPR" }, { "name": "ADDR", "desc": "Per-lane destination-lane selector" }, { "name": "DATA", "desc": "Per-lane value to send" } ], "dataTypes": [ "b32" ], "semantics": "VDST[dst_lane(lane)] = DATA[lane], where dst_lane is computed per-lane from ADDR; lanes that receive no value read undefined/zero depending on target.", "example": "ds_permute_b32 v1, v0, v2 // v1[lane] = v2[dest_lane(v0[lane])]", "exampleSource": null, "encoding": { "format": "DS", "widthBits": 32 }, "executionUnit": "LDS Unit", "registerClasses": [ "VGPR" ], "memorySegment": null, "supportedTargets": [ "gfx942", "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "amd-machine-readable-isa" ] }, { "id": "amdgpu.ds_pk_add_bf16", "mnemonic": "ds_pk_add_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS PK ADD BF16", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Add a packed 2-component BF16 float value in the data register to a location in a data share.", "description": "Add a packed 2-component BF16 float value in the data register to a location in a data share.", "syntax": "ds_pk_add_bf16", "operands": [], "dataTypes": [], "semantics": "tmp = MEM[ADDR];\nsrc = DATA;\ndst[31 : 16].bf16 = tmp[31 : 16].bf16 + src[31 : 16].bf16;\ndst[15 : 0].bf16 = tmp[15 : 0].bf16 + src[15 : 0].bf16;\nMEM[ADDR] = dst.b32;\nRETURN_DATA = tmp", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "Floating-point addition handles NAN/INF/denorm.", "sourcePdfPage": 424, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.ds_pk_add_f16", "mnemonic": "ds_pk_add_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS PK ADD F16", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Add a packed 2-component half-precision float value in the data register to a location in a data share.", "description": "Add a packed 2-component half-precision float value in the data register to a location in a data share.", "syntax": "ds_pk_add_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "tmp = MEM[ADDR];\nsrc = DATA;\ndst[31 : 16].f16 = tmp[31 : 16].f16 + src[31 : 16].f16;\ndst[15 : 0].f16 = tmp[15 : 0].f16 + src[15 : 0].f16;\nMEM[ADDR] = dst.b32;\nRETURN_DATA = tmp", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "Floating-point addition handles NAN/INF/denorm.", "sourcePdfPage": 424, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.ds_pk_add_rtn_bf16", "mnemonic": "ds_pk_add_rtn_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS PK ADD RTN BF16", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Add a packed 2-component BF16 float value in the data register to a location in a data share.", "description": "Add a packed 2-component BF16 float value in the data register to a location in a data share. Store the original value from data share into a vector register.", "syntax": "ds_pk_add_rtn_bf16", "operands": [], "dataTypes": [], "semantics": "tmp = MEM[ADDR];\nsrc = DATA;\ndst[31 : 16].bf16 = tmp[31 : 16].bf16 + src[31 : 16].bf16;\ndst[15 : 0].bf16 = tmp[15 : 0].bf16 + src[15 : 0].bf16;\nMEM[ADDR] = dst.b32;\nRETURN_DATA = tmp", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "Floating-point addition handles NAN/INF/denorm.", "sourcePdfPage": 455, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.ds_pk_add_rtn_f16", "mnemonic": "ds_pk_add_rtn_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS PK ADD RTN F16", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Add a packed 2-component half-precision float value in the data register to a location in a data share.", "description": "Add a packed 2-component half-precision float value in the data register to a location in a data share. Store the original value from data share into a vector register.", "syntax": "ds_pk_add_rtn_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "tmp = MEM[ADDR];\nsrc = DATA;\ndst[31 : 16].f16 = tmp[31 : 16].f16 + src[31 : 16].f16;\ndst[15 : 0].f16 = tmp[15 : 0].f16 + src[15 : 0].f16;\nMEM[ADDR] = dst.b32;\nRETURN_DATA = tmp", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "Floating-point addition handles NAN/INF/denorm.", "sourcePdfPage": 455, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.ds_read2_b32", "mnemonic": "ds_read2_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS READ2 B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 32 bits of data from one location in a data share and then 32 bits of data from a second location in a data share and store the results into a…", "description": "Load 32 bits of data from one location in a data share and then 32 bits of data from a second location in a data share and store the results into a 64-bit vector register.", "syntax": "ds_read2_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);\nRETURN_DATA[31 : 0] = MEM[addr + OFFSET0.u32 * 4U].b32;\naddr = CalcDsAddr(ADDR.b32, 0x0, 0x0);\nRETURN_DATA[63 : 32] = MEM[addr + OFFSET1.u32 * 4U].b32", "example": "ds_read2_b32 v[5:6], v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 432, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_read2_b64", "mnemonic": "ds_read2_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS READ2 B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 64 bits of data from one location in a data share and then 64 bits of data from a second location in a data share and store the results into a…", "description": "Load 64 bits of data from one location in a data share and then 64 bits of data from a second location in a data share and store the results into a 128-bit vector register.", "syntax": "ds_read2_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);\nRETURN_DATA[31 : 0] = MEM[addr + OFFSET0.u32 * 8U].b32;\nRETURN_DATA[63 : 32] = MEM[addr + OFFSET0.u32 * 8U + 4U].b32;\naddr = CalcDsAddr(ADDR.b32, 0x0, 0x0);\nRETURN_DATA[95 : 64] = MEM[addr + OFFSET1.u32 * 8U].b32;\nRETURN_DATA[127 : 96] = MEM[addr + OFFSET1.u32 * 8U + 4U].b32", "example": "ds_read2_b64 v[5:8], v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 451, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_read2st64_b32", "mnemonic": "ds_read2st64_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS READ2ST64 B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 32 bits of data from one location in a data share and then 32 bits of data from a second location in a data share and store the results into a…", "description": "Load 32 bits of data from one location in a data share and then 32 bits of data from a second location in a data share and store the results into a 64-bit vector register. Treat each offset as an index and multiply by a stride of 64 elements (256 bytes) to generate an offset for each DS address.", "syntax": "ds_read2st64_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);\nRETURN_DATA[31 : 0] = MEM[addr + OFFSET0.u32 * 256U].b32;\naddr = CalcDsAddr(ADDR.b32, 0x0, 0x0);\nRETURN_DATA[63 : 32] = MEM[addr + OFFSET1.u32 * 256U].b32", "example": "ds_read2st64_b32 v[5:6], v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 432, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_read2st64_b64", "mnemonic": "ds_read2st64_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS READ2ST64 B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 64 bits of data from one location in a data share and then 64 bits of data from a second location in a data share and store the results into a…", "description": "Load 64 bits of data from one location in a data share and then 64 bits of data from a second location in a data share and store the results into a 128-bit vector register. Treat each offset as an index and multiply by a stride of 64 elements (256 bytes) to generate an offset for each DS address.", "syntax": "ds_read2st64_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);\nRETURN_DATA[31 : 0] = MEM[addr + OFFSET0.u32 * 512U].b32;\nRETURN_DATA[63 : 32] = MEM[addr + OFFSET0.u32 * 512U + 4U].b32;\naddr = CalcDsAddr(ADDR.b32, 0x0, 0x0);\nRETURN_DATA[95 : 64] = MEM[addr + OFFSET1.u32 * 512U].b32;\nRETURN_DATA[127 : 96] = MEM[addr + OFFSET1.u32 * 512U + 4U].b32", "example": "ds_read2st64_b64 v[5:8], v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 451, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_read_addtid_b32", "mnemonic": "ds_read_addtid_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS READ ADDTID B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 32 bits of data from a data share into a vector register.", "description": "Load 32 bits of data from a data share into a vector register. The memory base address is provided as an immediate value and the lane ID is used as an offset.", "syntax": "ds_read_addtid_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "declare OFFSET0 : 8'U;\ndeclare OFFSET1 : 8'U;\nRETURN_DATA.u32 = MEM[32'I({ OFFSET1, OFFSET0 } + M0[15 : 0]) + laneID.i32 * 4].u32", "example": "ds_read_addtid_b32 v5", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 455, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_read_b128", "mnemonic": "ds_read_b128", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS READ B128", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 128 bits of data from a data share into a vector register.", "description": "Load 128 bits of data from a data share into a vector register.", "syntax": "ds_read_b128", "operands": [], "dataTypes": [], "semantics": "addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);\nRETURN_DATA[31 : 0] = MEM[addr + OFFSET.u32].b32;\nRETURN_DATA[63 : 32] = MEM[addr + OFFSET.u32 + 4U].b32;\nRETURN_DATA[95 : 64] = MEM[addr + OFFSET.u32 + 8U].b32;\nRETURN_DATA[127 : 96] = MEM[addr + OFFSET.u32 + 12U].b32", "example": "ds_read_b128 v[5:8], v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 457, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_read_b32", "mnemonic": "ds_read_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS READ B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Read one 32-bit value per lane from the Local Data Share (LDS).", "description": "Load 32 bits of data from a data share into a vector register.", "syntax": "ds_read_b32 VDST, ADDR, offset", "operands": [ { "name": "VDST", "desc": "Destination VGPR" }, { "name": "ADDR", "desc": "Per-lane LDS byte address (VGPR)" }, { "name": "offset", "desc": "Immediate byte offset" } ], "dataTypes": [ "b32" ], "semantics": "VDST[lane] = LDS[ADDR[lane] + offset] for each active lane.", "example": "ds_read_b32 v1, v0 // v1 = LDS[v0]", "exampleSource": null, "encoding": { "format": "DS", "widthBits": 32 }, "executionUnit": "LDS Unit", "registerClasses": [ "VGPR" ], "memorySegment": "LDS/shared", "supportedTargets": [ "gfx942", "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "amd-machine-readable-isa" ] }, { "id": "amdgpu.ds_read_b64", "mnemonic": "ds_read_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS READ B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 64 bits of data from a data share into a vector register.", "description": "Load 64 bits of data from a data share into a vector register.", "syntax": "ds_read_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);\nRETURN_DATA[31 : 0] = MEM[addr + OFFSET.u32].b32;\nRETURN_DATA[63 : 32] = MEM[addr + OFFSET.u32 + 4U].b32", "example": "ds_read_b64 v[5:6], v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 451, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_read_b64_tr_b16", "mnemonic": "ds_read_b64_tr_b16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS READ B64 TR B16", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Read 64 bits of data per lane from data share.", "description": "Read 64 bits of data per lane from data share. Interpret the data as a matrix with 16 bit elements and transpose the matrix. Store the result into vector registers.", "syntax": "ds_read_b64_tr_b16", "operands": [], "dataTypes": [ "b16", "b64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.ds_read_b64_tr_b4", "mnemonic": "ds_read_b64_tr_b4", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS READ B64 TR B4", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Read 64 bits of data per lane from data share.", "description": "Read 64 bits of data per lane from data share. Interpret the data as a matrix with 4 bit elements and transpose the matrix. Store the result into vector registers.", "syntax": "ds_read_b64_tr_b4", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.ds_read_b64_tr_b8", "mnemonic": "ds_read_b64_tr_b8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS READ B64 TR B8", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Read 64 bits of data per lane from data share.", "description": "Read 64 bits of data per lane from data share. Interpret the data as a matrix with 8 bit elements and transpose the matrix. Store the result into vector registers.", "syntax": "ds_read_b64_tr_b8", "operands": [], "dataTypes": [ "b64", "b8" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.ds_read_b96", "mnemonic": "ds_read_b96", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS READ B96", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 96 bits of data from a data share into a vector register.", "description": "Load 96 bits of data from a data share into a vector register.", "syntax": "ds_read_b96", "operands": [], "dataTypes": [], "semantics": "addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);\nRETURN_DATA[31 : 0] = MEM[addr + OFFSET.u32].b32;\nRETURN_DATA[63 : 32] = MEM[addr + OFFSET.u32 + 4U].b32;\nRETURN_DATA[95 : 64] = MEM[addr + OFFSET.u32 + 8U].b32", "example": "ds_read_b96 v[5:7], v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 457, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_read_b96_tr_b6", "mnemonic": "ds_read_b96_tr_b6", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS READ B96 TR B6", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Read 96 bits of data per lane from data share.", "description": "Read 96 bits of data per lane from data share. Interpret the data as a matrix with 6 bit elements and transpose the matrix. Store the result into vector registers.", "syntax": "ds_read_b96_tr_b6", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.ds_read_i16", "mnemonic": "ds_read_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS READ I16", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 16 bits of signed data from a data share, sign extend to 32 bits and store the result into a vector register.", "description": "Load 16 bits of signed data from a data share, sign extend to 32 bits and store the result into a vector register.", "syntax": "ds_read_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "RETURN_DATA.i32 = 32'I(signext(MEM[ADDR].i16))", "example": "ds_read_i16 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 433, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_read_i8", "mnemonic": "ds_read_i8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS READ I8", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 8 bits of signed data from a data share, sign extend to 32 bits and store the result into a vector register.", "description": "Load 8 bits of signed data from a data share, sign extend to 32 bits and store the result into a vector register.", "syntax": "ds_read_i8", "operands": [], "dataTypes": [ "i8" ], "semantics": "RETURN_DATA.i32 = 32'I(signext(MEM[ADDR].i8))", "example": "ds_read_i8 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 432, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_read_i8_d16", "mnemonic": "ds_read_i8_d16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS READ I8 D16", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 8 bits of signed data from a data share, sign extend to 16 bits and store the result into the low 16 bits of a vector register.", "description": "Load 8 bits of signed data from a data share, sign extend to 16 bits and store the result into the low 16 bits of a vector register.", "syntax": "ds_read_i8_d16", "operands": [], "dataTypes": [ "i8" ], "semantics": "RETURN_DATA[15 : 0].i16 = 16'I(signext(MEM[ADDR].i8));\n// RETURN_DATA[31:16] is preserved.", "example": "ds_read_i8_d16 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 444, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_read_i8_d16_hi", "mnemonic": "ds_read_i8_d16_hi", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS READ I8 D16 HI", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 8 bits of signed data from a data share, sign extend to 16 bits and store the result into the high 16 bits of a vector register.", "description": "Load 8 bits of signed data from a data share, sign extend to 16 bits and store the result into the high 16 bits of a vector register.", "syntax": "ds_read_i8_d16_hi", "operands": [], "dataTypes": [ "i8" ], "semantics": "RETURN_DATA[31 : 16].i16 = 16'I(signext(MEM[ADDR].i8));\n// RETURN_DATA[15:0] is preserved.", "example": "ds_read_i8_d16_hi v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 444, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_read_u16", "mnemonic": "ds_read_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS READ U16", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 16 bits of unsigned data from a data share, zero extend to 32 bits and store the result into a vector register.", "description": "Load 16 bits of unsigned data from a data share, zero extend to 32 bits and store the result into a vector register.", "syntax": "ds_read_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "RETURN_DATA.u32 = 32'U({ 16'0U, MEM[ADDR].u16 })", "example": "ds_read_u16 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 433, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_read_u16_d16", "mnemonic": "ds_read_u16_d16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS READ U16 D16", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 16 bits of unsigned data from a data share and store the result into the low 16 bits of a vector register.", "description": "Load 16 bits of unsigned data from a data share and store the result into the low 16 bits of a vector register.", "syntax": "ds_read_u16_d16", "operands": [], "dataTypes": [ "u16" ], "semantics": "RETURN_DATA[15 : 0].u16 = MEM[ADDR].u16;\n// RETURN_DATA[31:16] is preserved.", "example": "ds_read_u16_d16 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 444, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_read_u16_d16_hi", "mnemonic": "ds_read_u16_d16_hi", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS READ U16 D16 HI", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 16 bits of unsigned data from a data share and store the result into the high 16 bits of a vector register.", "description": "Load 16 bits of unsigned data from a data share and store the result into the high 16 bits of a vector register.", "syntax": "ds_read_u16_d16_hi", "operands": [], "dataTypes": [ "u16" ], "semantics": "RETURN_DATA[31 : 16].u16 = MEM[ADDR].u16;\n// RETURN_DATA[15:0] is preserved.", "example": "ds_read_u16_d16_hi v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 444, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_read_u8", "mnemonic": "ds_read_u8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS READ U8", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 8 bits of unsigned data from a data share, zero extend to 32 bits and store the result into a vector register.", "description": "Load 8 bits of unsigned data from a data share, zero extend to 32 bits and store the result into a vector register.", "syntax": "ds_read_u8", "operands": [], "dataTypes": [ "u8" ], "semantics": "RETURN_DATA.u32 = 32'U({ 24'0U, MEM[ADDR].u8 })", "example": "ds_read_u8 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 432, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_read_u8_d16", "mnemonic": "ds_read_u8_d16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS READ U8 D16", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 8 bits of unsigned data from a data share, zero extend to 16 bits and store the result into the low 16 bits of a vector register.", "description": "Load 8 bits of unsigned data from a data share, zero extend to 16 bits and store the result into the low 16 bits of a vector register.", "syntax": "ds_read_u8_d16", "operands": [], "dataTypes": [ "u8" ], "semantics": "RETURN_DATA[15 : 0].u16 = 16'U({ 8'0U, MEM[ADDR].u8 });\n// RETURN_DATA[31:16] is preserved.", "example": "ds_read_u8_d16 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 443, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_read_u8_d16_hi", "mnemonic": "ds_read_u8_d16_hi", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS READ U8 D16 HI", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Load 8 bits of unsigned data from a data share, zero extend to 16 bits and store the result into the high 16 bits of a vector register.", "description": "Load 8 bits of unsigned data from a data share, zero extend to 16 bits and store the result into the high 16 bits of a vector register.", "syntax": "ds_read_u8_d16_hi", "operands": [], "dataTypes": [ "u8" ], "semantics": "RETURN_DATA[31 : 16].u16 = 16'U({ 8'0U, MEM[ADDR].u8 });\n// RETURN_DATA[15:0] is preserved.", "example": "ds_read_u8_d16_hi v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 444, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_rsub_rtn_u32", "mnemonic": "ds_rsub_rtn_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS RSUB RTN U32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Subtract an unsigned 32-bit integer value stored in a location in a data share from a value stored in the data register.", "description": "Subtract an unsigned 32-bit integer value stored in a location in a data share from a value stored in the data register. Store the original value from data share into a vector register.", "syntax": "ds_rsub_rtn_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].u32;\nMEM[addr].u32 = DATA.u32 - MEM[addr].u32;\nRETURN_DATA.u32 = tmp", "example": "ds_rsub_rtn_u32 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 426, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_rsub_rtn_u64", "mnemonic": "ds_rsub_rtn_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS RSUB RTN U64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Subtract an unsigned 64-bit integer value stored in a location in a data share from a value stored in the data register.", "description": "Subtract an unsigned 64-bit integer value stored in a location in a data share from a value stored in the data register. Store the original value from data share into a vector register.", "syntax": "ds_rsub_rtn_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].u64;\nMEM[addr].u64 = DATA.u64 - MEM[addr].u64;\nRETURN_DATA.u64 = tmp", "example": "ds_rsub_rtn_u64 v[5:6], v1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 445, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_rsub_src2_u32", "mnemonic": "ds_rsub_src2_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS RSUB SRC2 U32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_rsub_src2_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_rsub_src2_u64", "mnemonic": "ds_rsub_src2_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS RSUB SRC2 U64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_rsub_src2_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_rsub_u32", "mnemonic": "ds_rsub_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS RSUB U32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Subtract an unsigned 32-bit integer value stored in a location in a data share from a value stored in the data register.", "description": "Subtract an unsigned 32-bit integer value stored in a location in a data share from a value stored in the data register.", "syntax": "ds_rsub_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].u32;\nMEM[addr].u32 = DATA.u32 - MEM[addr].u32;\nRETURN_DATA.u32 = tmp", "example": "ds_rsub_u32 v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 419, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_rsub_u64", "mnemonic": "ds_rsub_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS RSUB U64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Subtract an unsigned 64-bit integer value stored in a location in a data share from a value stored in the data register.", "description": "Subtract an unsigned 64-bit integer value stored in a location in a data share from a value stored in the data register.", "syntax": "ds_rsub_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].u64;\nMEM[addr].u64 = DATA.u64 - MEM[addr].u64;\nRETURN_DATA.u64 = tmp", "example": "ds_rsub_u64 v1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 438, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_store_2addr_b32", "mnemonic": "ds_store_2addr_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS STORE 2ADDR B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Store 32 bits of data from one vector input register and then 32 bits of data from a second vector input register into a data share.", "description": "Store 32 bits of data from one vector input register and then 32 bits of data from a second vector input register into a data share.", "syntax": "ds_store_2addr_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "ds_store_2addr_b32 v1, v2, v3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_store_2addr_b64", "mnemonic": "ds_store_2addr_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS STORE 2ADDR B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Store 64 bits of data from one vector input register and then 64 bits of data from a second vector input register into a data share.", "description": "Store 64 bits of data from one vector input register and then 64 bits of data from a second vector input register into a data share.", "syntax": "ds_store_2addr_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "ds_store_2addr_b64 v1, v[2:3], v[3:4]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_store_2addr_stride64_b32", "mnemonic": "ds_store_2addr_stride64_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS STORE 2ADDR STRIDE64 B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Store 32 bits of data from one vector input register and then 32 bits of data from a second vector input register into a data share.", "description": "Store 32 bits of data from one vector input register and then 32 bits of data from a second vector input register into a data share. Treat each offset as an index and multiply by a stride of 64 elements (256 bytes) to generate an offset for each DS address.", "syntax": "ds_store_2addr_stride64_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "ds_store_2addr_stride64_b32 v1, v2, v3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_store_2addr_stride64_b64", "mnemonic": "ds_store_2addr_stride64_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS STORE 2ADDR STRIDE64 B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Store 64 bits of data from one vector input register and then 64 bits of data from a second vector input register into a data share.", "description": "Store 64 bits of data from one vector input register and then 64 bits of data from a second vector input register into a data share. Treat each offset as an index and multiply by a stride of 64 elements (256 bytes) to generate an offset for each DS address.", "syntax": "ds_store_2addr_stride64_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "ds_store_2addr_stride64_b64 v1, v[2:3], v[3:4]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_store_addtid_b32", "mnemonic": "ds_store_addtid_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS STORE ADDTID B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Store 32 bits of data from a vector input register into a data share.", "description": "Store 32 bits of data from a vector input register into a data share. The memory base address is provided as an immediate value and the lane ID is used as an offset.", "syntax": "ds_store_addtid_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "ds_store_addtid_b32 v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_store_b128", "mnemonic": "ds_store_b128", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS STORE B128", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Store 128 bits of data from a vector input register into a data share.", "description": "Store 128 bits of data from a vector input register into a data share.", "syntax": "ds_store_b128", "operands": [], "dataTypes": [], "semantics": "", "example": "ds_store_b128 v1, v[2:5]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_store_b16", "mnemonic": "ds_store_b16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS STORE B16", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Store 16 bits of data from a vector register into a data share.", "description": "Store 16 bits of data from a vector register into a data share.", "syntax": "ds_store_b16", "operands": [], "dataTypes": [ "b16" ], "semantics": "", "example": "ds_store_b16 v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_store_b16_d16_hi", "mnemonic": "ds_store_b16_d16_hi", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS STORE B16 D16 HI", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Store 16 bits of data from the high bits of a vector register into a data share.", "description": "Store 16 bits of data from the high bits of a vector register into a data share.", "syntax": "ds_store_b16_d16_hi", "operands": [], "dataTypes": [ "b16" ], "semantics": "", "example": "ds_store_b16_d16_hi v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_store_b32", "mnemonic": "ds_store_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS STORE B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Store 32 bits of data from a vector input register into a data share.", "description": "Store 32 bits of data from a vector input register into a data share.", "syntax": "ds_store_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "ds_store_b32 v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_store_b64", "mnemonic": "ds_store_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS STORE B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Store 64 bits of data from a vector input register into a data share.", "description": "Store 64 bits of data from a vector input register into a data share.", "syntax": "ds_store_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "ds_store_b64 v1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_store_b8", "mnemonic": "ds_store_b8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS STORE B8", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Store 8 bits of data from a vector register into a data share.", "description": "Store 8 bits of data from a vector register into a data share.", "syntax": "ds_store_b8", "operands": [], "dataTypes": [ "b8" ], "semantics": "", "example": "ds_store_b8 v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_store_b8_d16_hi", "mnemonic": "ds_store_b8_d16_hi", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS STORE B8 D16 HI", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Store 8 bits of data from the high bits of a vector register into a data share.", "description": "Store 8 bits of data from the high bits of a vector register into a data share.", "syntax": "ds_store_b8_d16_hi", "operands": [], "dataTypes": [ "b8" ], "semantics": "", "example": "ds_store_b8_d16_hi v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_store_b96", "mnemonic": "ds_store_b96", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS STORE B96", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Store 96 bits of data from a vector input register into a data share.", "description": "Store 96 bits of data from a vector input register into a data share.", "syntax": "ds_store_b96", "operands": [], "dataTypes": [], "semantics": "", "example": "ds_store_b96 v1, v[2:4]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_storexchg_2addr_rtn_b32", "mnemonic": "ds_storexchg_2addr_rtn_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS STOREXCHG 2ADDR RTN B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Swap two unsigned 32-bit integer values in the data registers with two locations in a data share.", "description": "Swap two unsigned 32-bit integer values in the data registers with two locations in a data share.", "syntax": "ds_storexchg_2addr_rtn_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "ds_storexchg_2addr_rtn_b32 v[5:6], v1, v2, v3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_storexchg_2addr_rtn_b64", "mnemonic": "ds_storexchg_2addr_rtn_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS STOREXCHG 2ADDR RTN B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Swap two unsigned 64-bit integer values in the data registers with two locations in a data share.", "description": "Swap two unsigned 64-bit integer values in the data registers with two locations in a data share.", "syntax": "ds_storexchg_2addr_rtn_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "ds_storexchg_2addr_rtn_b64 v[5:8], v1, v[2:3], v[3:4]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_storexchg_2addr_stride64_rtn_b32", "mnemonic": "ds_storexchg_2addr_stride64_rtn_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS STOREXCHG 2ADDR STRIDE64 RTN B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Swap two unsigned 32-bit integer values in the data registers with two locations in a data share.", "description": "Swap two unsigned 32-bit integer values in the data registers with two locations in a data share. Treat each offset as an index and multiply by a stride of 64 elements (256 bytes) to generate an offset for each DS address.", "syntax": "ds_storexchg_2addr_stride64_rtn_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "ds_storexchg_2addr_stride64_rtn_b32 v[5:6], v1, v2, v3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_storexchg_2addr_stride64_rtn_b64", "mnemonic": "ds_storexchg_2addr_stride64_rtn_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS STOREXCHG 2ADDR STRIDE64 RTN B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Swap two unsigned 64-bit integer values in the data registers with two locations in a data share.", "description": "Swap two unsigned 64-bit integer values in the data registers with two locations in a data share. Treat each offset as an index and multiply by a stride of 64 elements (256 bytes) to generate an offset for each DS address.", "syntax": "ds_storexchg_2addr_stride64_rtn_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "ds_storexchg_2addr_stride64_rtn_b64 v[5:8], v1, v[2:3], v[3:4]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_storexchg_rtn_b32", "mnemonic": "ds_storexchg_rtn_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS STOREXCHG RTN B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Swap an unsigned 32-bit integer value in the data register with a location in a data share.", "description": "Swap an unsigned 32-bit integer value in the data register with a location in a data share.", "syntax": "ds_storexchg_rtn_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "ds_storexchg_rtn_b32 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_storexchg_rtn_b64", "mnemonic": "ds_storexchg_rtn_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS STOREXCHG RTN B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Swap an unsigned 64-bit integer value in the data register with a location in a data share.", "description": "Swap an unsigned 64-bit integer value in the data register with a location in a data share.", "syntax": "ds_storexchg_rtn_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "ds_storexchg_rtn_b64 v[5:6], v1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_sub_clamp_rtn_u32", "mnemonic": "ds_sub_clamp_rtn_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS SUB CLAMP RTN U32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Subtract an unsigned 32-bit integer location in a data share from a value in the data register and clamp the result to zero.", "description": "Subtract an unsigned 32-bit integer location in a data share from a value in the data register and clamp the result to zero. Store the original value from data share into a vector register.", "syntax": "ds_sub_clamp_rtn_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.ds_sub_clamp_u32", "mnemonic": "ds_sub_clamp_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS SUB CLAMP U32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Subtract an unsigned 32-bit integer location in a data share from a value in the data register and clamp the result to zero.", "description": "Subtract an unsigned 32-bit integer location in a data share from a value in the data register and clamp the result to zero.", "syntax": "ds_sub_clamp_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.ds_sub_gs_reg_rtn", "mnemonic": "ds_sub_gs_reg_rtn", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS SUB GS REG RTN", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Perform an atomic subtraction from data in specific registers embedded in GDS rather than operating on GDS memory directly.", "description": "Perform an atomic subtraction from data in specific registers embedded in GDS rather than operating on GDS memory directly. This instruction returns the pre-op value. This instruction is only used by the GS stage and is used to facilitate streamout.", "syntax": "ds_sub_gs_reg_rtn", "operands": [], "dataTypes": [], "semantics": "", "example": "ds_sub_gs_reg_rtn v[5:6], v1 gds", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_sub_rtn_u32", "mnemonic": "ds_sub_rtn_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS SUB RTN U32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Subtract an unsigned 32-bit integer value stored in the data register from a value stored in a location in a data share.", "description": "Subtract an unsigned 32-bit integer value stored in the data register from a value stored in a location in a data share. Store the original value from data share into a vector register.", "syntax": "ds_sub_rtn_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].u32;\nMEM[addr].u32 -= DATA.u32;\nRETURN_DATA.u32 = tmp", "example": "ds_sub_rtn_u32 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 425, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_sub_rtn_u64", "mnemonic": "ds_sub_rtn_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS SUB RTN U64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Subtract an unsigned 64-bit integer value stored in the data register from a value stored in a location in a data share.", "description": "Subtract an unsigned 64-bit integer value stored in the data register from a value stored in a location in a data share. Store the original value from data share into a vector register.", "syntax": "ds_sub_rtn_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].u64;\nMEM[addr].u64 -= DATA.u64;\nRETURN_DATA.u64 = tmp", "example": "ds_sub_rtn_u64 v[5:6], v1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 445, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_sub_src2_u32", "mnemonic": "ds_sub_src2_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS SUB SRC2 U32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_sub_src2_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_sub_src2_u64", "mnemonic": "ds_sub_src2_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS SUB SRC2 U64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_sub_src2_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_sub_u32", "mnemonic": "ds_sub_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS SUB U32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Subtract an unsigned 32-bit integer value stored in the data register from a value stored in a location in a data share.", "description": "Subtract an unsigned 32-bit integer value stored in the data register from a value stored in a location in a data share.", "syntax": "ds_sub_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].u32;\nMEM[addr].u32 -= DATA.u32;\nRETURN_DATA.u32 = tmp", "example": "ds_sub_u32 v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 418, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_sub_u64", "mnemonic": "ds_sub_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS SUB U64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Subtract an unsigned 64-bit integer value stored in the data register from a value stored in a location in a data share.", "description": "Subtract an unsigned 64-bit integer value stored in the data register from a value stored in a location in a data share.", "syntax": "ds_sub_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].u64;\nMEM[addr].u64 -= DATA.u64;\nRETURN_DATA.u64 = tmp", "example": "ds_sub_u64 v1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 438, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_swizzle_b32", "mnemonic": "ds_swizzle_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS SWIZZLE B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Dword swizzle, no data is written to LDS memory.", "description": "Dword swizzle, no data is written to LDS memory. Swizzles input thread data based on offset mask and returns; note does not read or write the DS memory banks. Note that reading from an invalid thread results in 0x0. This opcode supports two specific modes, FFT and rotate, plus two basic modes which swizzle in groups of 4 or 32 consecutive threads.", "syntax": "ds_swizzle_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "The FFT mode (offset >= 0xe000) swizzles the input based on offset[4:0] to support FFT calculation. Example\nswizzles using input {1, 2, … 20} are:\nOffset[4:0]: Swizzle\n0x00: {1,11,9,19,5,15,d,1d,3,13,b,1b,7,17,f,1f,2,12,a,1a,6,16,e,1e,4,14,c,1c,8,18,10,20}\n0x10: {1,9,5,d,3,b,7,f,2,a,6,e,4,c,8,10,11,19,15,1d,13,1b,17,1f,12,1a,16,1e,14,1c,18,20}\n0x1f: No swizzle\nThe rotate mode (offset >= 0xc000 and offset < 0xe000) rotates the input either left (offset[10] == 0) or right\n(offset[10] == 1) a number of threads equal to offset[9:5]. The rotate mode also uses a mask value which can\nalter the rotate result. For example, mask == 1 swaps the odd threads across every other even thread (rotate\nleft), or even threads across every other odd thread (rotate right).\nOffset[9:5]: Swizzle\n0x01, mask=0, rotate left:\n{2,3,4,5,6,7,8,9,a,b,c,d,e,f,10,11,12,13,14,15,16,17,18,19,1a,1b,1c,1d,1e,1f,20,1}\n0x01, mask=0, rotate right:\n{20,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f,10,11,12,13,14,15,16,17,18,19,1a,1b,1c,1d,1e,1f}\n0x01, mask=1, rotate left:\n{1,4,3,6,5,8,7,a,9,c,b,e,d,10,f,12,11,14,13,16,15,18,17,1a,19,1c,1b,1e,1d,20,1f,2}\n0x01, mask=1, rotate right:\n{1f,2,1,4,3,6,5,8,7,a,9,c,b,e,d,10,f,12,11,14,13,16,15,18,17,1a,19,1c,1b,1e,1d,20}\nIf offset < 0xc000, one of the basic swizzle modes is used based on offset[15]. If offset[15] == 1, groups of 4\nconsecutive threads are swizzled together. If offset[15] == 0, all 32 threads are swizzled together.\nThe first basic swizzle mode (when offset[15] == 1) allows full data sharing between a group of 4 consecutive\nthreads. Any thread within the group of 4 can get data from any other thread within the group of 4, specified by\nthe corresponding offset bits --- [1:0] for the first thread, [3:2] for the second thread, [5:4] for the third thread,\n[7:6] for the fourth thread. Note that the offset bits apply to all groups of 4 within a wavefront; thus if offset[1:0]\n== 1, then thread0 grabs thread1, thread4 grabs thread5, etc.\nThe second basic swizzle mode (when offset[15] == 0) allows limited data sharing between 32 consecutive\nthreads. In this case, the offset is used to specify a 5-bit xor-mask, 5-bit or-mask, and 5-bit and-mask used to\ngenerate a thread mapping. Note that the offset bits apply to each group of 32 within a wavefront. The details of\nthe thread mapping are listed below. Some example usages:\nSWAPX16 : xor_mask = 0x10, or_mask = 0x00, and_mask = 0x1f\nSWAPX8 : xor_mask = 0x08, or_mask = 0x00, and_mask = 0x1f\nSWAPX4 : xor_mask = 0x04, or_mask = 0x00, and_mask = 0x1f\nSWAPX2 : xor_mask = 0x02, or_mask = 0x00, and_mask = 0x1f\nSWAPX1 : xor_mask = 0x01, or_mask = 0x00, and_mask = 0x1f\nREVERSEX32 : xor_mask = 0x1f, or_mask = 0x00, and_mask = 0x1f\nREVERSEX16 : xor_mask = 0x0f, or_mask = 0x00, and_mask = 0x1f\nREVERSEX8 : xor_mask = 0x07, or_mask = 0x00, and_mask = 0x1f\nREVERSEX4 : xor_mask = 0x03, or_mask = 0x00, and_mask = 0x1f\nREVERSEX2 : xor_mask = 0x01 or_mask = 0x00, and_mask = 0x1f\nBCASTX32: xor_mask = 0x00, or_mask = thread, and_mask = 0x00\nBCASTX16: xor_mask = 0x00, or_mask = thread, and_mask = 0x10\nBCASTX8: xor_mask = 0x00, or_mask = thread, and_mask = 0x18\nBCASTX4: xor_mask = 0x00, or_mask = thread, and_mask = 0x1c\nBCASTX2: xor_mask = 0x00, or_mask = thread, and_mask = 0x1e\nPseudocode follows:\noffset = offset1:offset0;\nif (offset >= 0xe000) {\n// FFT decomposition\nmask = offset[4:0];\nfor (i = 0; i < 64; i++) {\nj = reverse_bits(i & 0x1f);\nj = (j >> count_ones(mask));\nj |= (i & mask);\nj |= i & 0x20;\nthread_out[i] = thread_valid[j] ? thread_in[j] : 0;\n}\n} elsif (offset >= 0xc000) {\n// rotate\nrotate = offset[9:5];\nmask = offset[4:0];\nif (offset[10]) {\nrotate = -rotate;\n}\nfor (i = 0; i < 64; i++) {\nj = (i & mask) | ((i + rotate) & ~mask);\nj |= i & 0x20;\nthread_out[i] = thread_valid[j] ? thread_in[j] : 0;\n}\n} elsif (offset[15]) {\n// full data sharing within 4 consecutive threads\nfor (i = 0; i < 64; i+=4) {\nthread_out[i+0] = thread_valid[i+offset[1:0]]?thread_in[i+offset[1:0]]:0;\nthread_out[i+1] = thread_valid[i+offset[3:2]]?thread_in[i+offset[3:2]]:0;\nthread_out[i+2] = thread_valid[i+offset[5:4]]?thread_in[i+offset[5:4]]:0;\nthread_out[i+3] = thread_valid[i+offset[7:6]]?thread_in[i+offset[7:6]]:0;\n}\n} else { // offset[15] == 0\n// limited data sharing within 32 consecutive threads\nxor_mask = offset[14:10];\nor_mask = offset[9:5];\nand_mask = offset[4:0];\nfor (i = 0; i < 64; i++) {\nj = (((i & 0x1f) & and_mask) | or_mask) ^ xor_mask;\nj |= (i & 0x20); // which group of 32\nthread_out[i] = thread_valid[j] ? thread_in[j] : 0;\n}\n}", "example": "ds_swizzle_b32 v8, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 433, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_wrap_rtn_b32", "mnemonic": "ds_wrap_rtn_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS WRAP RTN B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Given a minuend from a location in data share and a subtrahend from a vector register, subtract the two values iff the result is nonnegative…", "description": "Given a minuend from a location in data share and a subtrahend from a vector register, subtract the two values iff the result is nonnegative; otherwise add a value from a second vector register to the memory location. This calculation provides flexible wraparound semantics for subtraction.", "syntax": "ds_wrap_rtn_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "tmp = MEM[ADDR].u32;\nMEM[ADDR].u32 = tmp >= DATA.u32 ? tmp - DATA.u32 : tmp + DATA2.u32;\nRETURN_DATA = tmp", "example": "ds_wrap_rtn_b32 v5, v1, v2, v3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "This instruction is designed to for use in ring buffer management.", "sourcePdfPage": 431, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_write2_b32", "mnemonic": "ds_write2_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS WRITE2 B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Store 32 bits of data from one vector input register and then 32 bits of data from a second vector input register into a data share.", "description": "Store 32 bits of data from one vector input register and then 32 bits of data from a second vector input register into a data share.", "syntax": "ds_write2_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);\nMEM[addr + OFFSET0.u32 * 4U].b32 = DATA[31 : 0];\naddr = CalcDsAddr(ADDR.b32, 0x0, 0x0);\nMEM[addr + OFFSET1.u32 * 4U].b32 = DATA2[31 : 0]", "example": "ds_write2_b32 v1, v2, v3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 422, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_write2_b64", "mnemonic": "ds_write2_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS WRITE2 B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Store 64 bits of data from one vector input register and then 64 bits of data from a second vector input register into a data share.", "description": "Store 64 bits of data from one vector input register and then 64 bits of data from a second vector input register into a data share.", "syntax": "ds_write2_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);\nMEM[addr + OFFSET0.u32 * 8U].b32 = DATA[31 : 0];\nMEM[addr + OFFSET0.u32 * 8U + 4U].b32 = DATA[63 : 32];\naddr = CalcDsAddr(ADDR.b32, 0x0, 0x0);\nMEM[addr + OFFSET1.u32 * 8U].b32 = DATA2[31 : 0];\nMEM[addr + OFFSET1.u32 * 8U + 4U].b32 = DATA2[63 : 32]", "example": "ds_write2_b64 v1, v[2:3], v[3:4]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 441, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_write2st64_b32", "mnemonic": "ds_write2st64_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS WRITE2ST64 B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Store 32 bits of data from one vector input register and then 32 bits of data from a second vector input register into a data share.", "description": "Store 32 bits of data from one vector input register and then 32 bits of data from a second vector input register into a data share. Treat each offset as an index and multiply by a stride of 64 elements (256 bytes) to generate an offset for each DS address.", "syntax": "ds_write2st64_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);\nMEM[addr + OFFSET0.u32 * 256U].b32 = DATA[31 : 0];\naddr = CalcDsAddr(ADDR.b32, 0x0, 0x0);\nMEM[addr + OFFSET1.u32 * 256U].b32 = DATA2[31 : 0]", "example": "ds_write2st64_b32 v1, v2, v3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 422, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_write2st64_b64", "mnemonic": "ds_write2st64_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS WRITE2ST64 B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Store 64 bits of data from one vector input register and then 64 bits of data from a second vector input register into a data share.", "description": "Store 64 bits of data from one vector input register and then 64 bits of data from a second vector input register into a data share. Treat each offset as an index and multiply by a stride of 64 elements (256 bytes) to generate an offset for each DS address.", "syntax": "ds_write2st64_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);\nMEM[addr + OFFSET0.u32 * 512U].b32 = DATA[31 : 0];\nMEM[addr + OFFSET0.u32 * 512U + 4U].b32 = DATA[63 : 32];\naddr = CalcDsAddr(ADDR.b32, 0x0, 0x0);\nMEM[addr + OFFSET1.u32 * 512U].b32 = DATA2[31 : 0];\nMEM[addr + OFFSET1.u32 * 512U + 4U].b32 = DATA2[63 : 32]", "example": "ds_write2st64_b64 v1, v[2:3], v[3:4]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 441, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_write_addtid_b32", "mnemonic": "ds_write_addtid_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS WRITE ADDTID B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Store 32 bits of data from a vector input register into a data share.", "description": "Store 32 bits of data from a vector input register into a data share. The memory base address is provided as an immediate value and the lane ID is used as an offset.", "syntax": "ds_write_addtid_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "declare OFFSET0 : 8'U;\ndeclare OFFSET1 : 8'U;\nMEM[32'I({ OFFSET1, OFFSET0 } + M0[15 : 0]) + laneID.i32 * 4].u32 = DATA0.u32", "example": "ds_write_addtid_b32 v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 425, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_write_b128", "mnemonic": "ds_write_b128", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS WRITE B128", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Store 128 bits of data from a vector input register into a data share.", "description": "Store 128 bits of data from a vector input register into a data share.", "syntax": "ds_write_b128", "operands": [], "dataTypes": [], "semantics": "addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);\nMEM[addr + OFFSET.u32].b32 = DATA[31 : 0];\nMEM[addr + OFFSET.u32 + 4U].b32 = DATA[63 : 32];\nMEM[addr + OFFSET.u32 + 8U].b32 = DATA[95 : 64];\nMEM[addr + OFFSET.u32 + 12U].b32 = DATA[127 : 96]", "example": "ds_write_b128 v1, v[2:5]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 456, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_write_b16", "mnemonic": "ds_write_b16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS WRITE B16", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Store 16 bits of data from a vector register into a data share.", "description": "Store 16 bits of data from a vector register into a data share.", "syntax": "ds_write_b16", "operands": [], "dataTypes": [ "b16" ], "semantics": "MEM[ADDR].b16 = DATA[15 : 0]", "example": "ds_write_b16 v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 425, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_write_b16_d16_hi", "mnemonic": "ds_write_b16_d16_hi", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS WRITE B16 D16 HI", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Store 16 bits of data from the high bits of a vector register into a data share.", "description": "Store 16 bits of data from the high bits of a vector register into a data share.", "syntax": "ds_write_b16_d16_hi", "operands": [], "dataTypes": [ "b16" ], "semantics": "MEM[ADDR].b16 = DATA[31 : 16]", "example": "ds_write_b16_d16_hi v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 443, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_write_b32", "mnemonic": "ds_write_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS WRITE B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Write one 32-bit value per lane to the Local Data Share (LDS).", "description": "Store 32 bits of data from a vector input register into a data share.", "syntax": "ds_write_b32 ADDR, DATA, offset", "operands": [ { "name": "ADDR", "desc": "Per-lane LDS byte address (VGPR)" }, { "name": "DATA", "desc": "Per-lane value to write (VGPR)" }, { "name": "offset", "desc": "Immediate byte offset" } ], "dataTypes": [ "b32" ], "semantics": "LDS[ADDR[lane] + offset] = DATA[lane] for each active lane.", "example": "ds_write_b32 v0, v1 // LDS[v0] = v1", "exampleSource": null, "encoding": { "format": "DS", "widthBits": 32 }, "executionUnit": "LDS Unit", "registerClasses": [ "VGPR" ], "memorySegment": "LDS/shared", "supportedTargets": [ "gfx942", "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "amd-machine-readable-isa" ] }, { "id": "amdgpu.ds_write_b64", "mnemonic": "ds_write_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS WRITE B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Store 64 bits of data from a vector input register into a data share.", "description": "Store 64 bits of data from a vector input register into a data share.", "syntax": "ds_write_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);\nMEM[addr + OFFSET.u32].b32 = DATA[31 : 0];\nMEM[addr + OFFSET.u32 + 4U].b32 = DATA[63 : 32]", "example": "ds_write_b64 v1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 441, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_write_b8", "mnemonic": "ds_write_b8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS WRITE B8", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Store 8 bits of data from a vector register into a data share.", "description": "Store 8 bits of data from a vector register into a data share.", "syntax": "ds_write_b8", "operands": [], "dataTypes": [ "b8" ], "semantics": "MEM[ADDR].b8 = DATA[7 : 0]", "example": "ds_write_b8 v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 425, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_write_b8_d16_hi", "mnemonic": "ds_write_b8_d16_hi", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS WRITE B8 D16 HI", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Store 8 bits of data from the high bits of a vector register into a data share.", "description": "Store 8 bits of data from the high bits of a vector register into a data share.", "syntax": "ds_write_b8_d16_hi", "operands": [], "dataTypes": [ "b8" ], "semantics": "MEM[ADDR].b8 = DATA[23 : 16]", "example": "ds_write_b8_d16_hi v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 443, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_write_b96", "mnemonic": "ds_write_b96", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS WRITE B96", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Store 96 bits of data from a vector input register into a data share.", "description": "Store 96 bits of data from a vector input register into a data share.", "syntax": "ds_write_b96", "operands": [], "dataTypes": [], "semantics": "addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);\nMEM[addr + OFFSET.u32].b32 = DATA[31 : 0];\nMEM[addr + OFFSET.u32 + 4U].b32 = DATA[63 : 32];\nMEM[addr + OFFSET.u32 + 8U].b32 = DATA[95 : 64]", "example": "ds_write_b96 v1, v[2:4]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 456, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_write_src2_b32", "mnemonic": "ds_write_src2_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS WRITE SRC2 B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_write_src2_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_write_src2_b64", "mnemonic": "ds_write_src2_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS WRITE SRC2 B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_write_src2_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_wrxchg2_rtn_b32", "mnemonic": "ds_wrxchg2_rtn_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS WRXCHG2 RTN B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Swap two unsigned 32-bit integer values in the data registers with two locations in a data share.", "description": "Swap two unsigned 32-bit integer values in the data registers with two locations in a data share.", "syntax": "ds_wrxchg2_rtn_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "addr1 = ADDR_BASE.u32 + OFFSET0.u32 * 4U;\naddr2 = ADDR_BASE.u32 + OFFSET1.u32 * 4U;\ntmp1 = MEM[addr1].b32;\ntmp2 = MEM[addr2].b32;\nMEM[addr1].b32 = DATA.b32;\nMEM[addr2].b32 = DATA2.b32;\n// Note DATA2 can be any other register\nRETURN_DATA[31 : 0] = tmp1;\nRETURN_DATA[63 : 32] = tmp2", "example": "ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 429, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_wrxchg2_rtn_b64", "mnemonic": "ds_wrxchg2_rtn_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS WRXCHG2 RTN B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Swap two unsigned 64-bit integer values in the data registers with two locations in a data share.", "description": "Swap two unsigned 64-bit integer values in the data registers with two locations in a data share.", "syntax": "ds_wrxchg2_rtn_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "addr1 = ADDR_BASE.u32 + OFFSET0.u32 * 8U;\naddr2 = ADDR_BASE.u32 + OFFSET1.u32 * 8U;\ntmp1 = MEM[addr1].b64;\ntmp2 = MEM[addr2].b64;\nMEM[addr1].b64 = DATA.b64;\nMEM[addr2].b64 = DATA2.b64;\n// Note DATA2 can be any other register\nRETURN_DATA[63 : 0] = tmp1;\nRETURN_DATA[127 : 64] = tmp2", "example": "ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 449, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_wrxchg2st64_rtn_b32", "mnemonic": "ds_wrxchg2st64_rtn_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS WRXCHG2ST64 RTN B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Swap two unsigned 32-bit integer values in the data registers with two locations in a data share.", "description": "Swap two unsigned 32-bit integer values in the data registers with two locations in a data share. Treat each offset as an index and multiply by a stride of 64 elements (256 bytes) to generate an offset for each DS address.", "syntax": "ds_wrxchg2st64_rtn_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "addr1 = ADDR_BASE.u32 + OFFSET0.u32 * 256U;\naddr2 = ADDR_BASE.u32 + OFFSET1.u32 * 256U;\ntmp1 = MEM[addr1].b32;\ntmp2 = MEM[addr2].b32;\nMEM[addr1].b32 = DATA.b32;\nMEM[addr2].b32 = DATA2.b32;\n// Note DATA2 can be any other register\nRETURN_DATA[31 : 0] = tmp1;\nRETURN_DATA[63 : 32] = tmp2", "example": "ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 429, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_wrxchg2st64_rtn_b64", "mnemonic": "ds_wrxchg2st64_rtn_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS WRXCHG2ST64 RTN B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Swap two unsigned 64-bit integer values in the data registers with two locations in a data share.", "description": "Swap two unsigned 64-bit integer values in the data registers with two locations in a data share. Treat each offset as an index and multiply by a stride of 64 elements (256 bytes) to generate an offset for each DS address.", "syntax": "ds_wrxchg2st64_rtn_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "addr1 = ADDR_BASE.u32 + OFFSET0.u32 * 512U;\naddr2 = ADDR_BASE.u32 + OFFSET1.u32 * 512U;\ntmp1 = MEM[addr1].b64;\ntmp2 = MEM[addr2].b64;\nMEM[addr1].b64 = DATA.b64;\nMEM[addr2].b64 = DATA2.b64;\n// Note DATA2 can be any other register\nRETURN_DATA[63 : 0] = tmp1;\nRETURN_DATA[127 : 64] = tmp2", "example": "ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 449, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_wrxchg_rtn_b32", "mnemonic": "ds_wrxchg_rtn_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS WRXCHG RTN B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Swap an unsigned 32-bit integer value in the data register with a location in a data share.", "description": "Swap an unsigned 32-bit integer value in the data register with a location in a data share.", "syntax": "ds_wrxchg_rtn_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].b32;\nMEM[addr].b32 = DATA.b32;\nRETURN_DATA.b32 = tmp", "example": "ds_wrxchg_rtn_b32 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 429, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_wrxchg_rtn_b64", "mnemonic": "ds_wrxchg_rtn_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS WRXCHG RTN B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Swap an unsigned 64-bit integer value in the data register with a location in a data share.", "description": "Swap an unsigned 64-bit integer value in the data register with a location in a data share.", "syntax": "ds_wrxchg_rtn_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].b64;\nMEM[addr].b64 = DATA.b64;\nRETURN_DATA.b64 = tmp", "example": "ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 448, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_xor_b32", "mnemonic": "ds_xor_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS XOR B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Calculate bitwise XOR given two unsigned 32-bit integer values stored in the data register and a location in a data share.", "description": "Calculate bitwise XOR given two unsigned 32-bit integer values stored in the data register and a location in a data share.", "syntax": "ds_xor_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].b32;\nMEM[addr].b32 = (tmp ^ DATA.b32);\nRETURN_DATA.b32 = tmp", "example": "ds_xor_b32 v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 421, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_xor_b64", "mnemonic": "ds_xor_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS XOR B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Calculate bitwise XOR given two unsigned 64-bit integer values stored in the data register and a location in a data share.", "description": "Calculate bitwise XOR given two unsigned 64-bit integer values stored in the data register and a location in a data share.", "syntax": "ds_xor_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].b64;\nMEM[addr].b64 = (tmp ^ DATA.b64);\nRETURN_DATA.b64 = tmp", "example": "ds_xor_b64 v1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 440, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_xor_rtn_b32", "mnemonic": "ds_xor_rtn_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS XOR RTN B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Calculate bitwise XOR given two unsigned 32-bit integer values stored in the data register and a location in a data share.", "description": "Calculate bitwise XOR given two unsigned 32-bit integer values stored in the data register and a location in a data share. Store the original value from data share into a vector register.", "syntax": "ds_xor_rtn_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].b32;\nMEM[addr].b32 = (tmp ^ DATA.b32);\nRETURN_DATA.b32 = tmp", "example": "ds_xor_rtn_b32 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 428, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_xor_rtn_b64", "mnemonic": "ds_xor_rtn_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS XOR RTN B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "Calculate bitwise XOR given two unsigned 64-bit integer values stored in the data register and a location in a data share.", "description": "Calculate bitwise XOR given two unsigned 64-bit integer values stored in the data register and a location in a data share. Store the original value from data share into a vector register.", "syntax": "ds_xor_rtn_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);\ntmp = MEM[addr].b64;\nMEM[addr].b64 = (tmp ^ DATA.b64);\nRETURN_DATA.b64 = tmp", "example": "ds_xor_rtn_b64 v[5:6], v1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 448, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.ds_xor_src2_b32", "mnemonic": "ds_xor_src2_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS XOR SRC2 B32", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_xor_src2_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.ds_xor_src2_b64", "mnemonic": "ds_xor_src2_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "DS XOR SRC2 B64", "category": "LDS / Data Share", "instructionClass": "vector", "summary": "AMDGPU DS vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "ds_xor_src2_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "DS" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.flat_atomic_add", "mnemonic": "flat_atomic_add", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC ADD", "category": "Flat Memory", "instructionClass": "vector", "summary": "Add two unsigned 32-bit integer values stored in the data register and a location in the flat aperture.", "description": "Add two unsigned 32-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the SC0 bit is set.", "syntax": "flat_atomic_add", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\ntmp = MEM[addr].u32;\nMEM[addr].u32 += DATA.u32;\nRETURN_DATA.u32 = tmp", "example": "flat_atomic_add v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 488, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_add_f32", "mnemonic": "flat_atomic_add_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC ADD F32", "category": "Flat Memory", "instructionClass": "vector", "summary": "Add a single-precision float value in the data register to a location in the flat aperture.", "description": "Add a single-precision float value in the data register to a location in the flat aperture. Store the original value from flat aperture into a vector register iff the SC0 bit is set.", "syntax": "flat_atomic_add_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "tmp = MEM[ADDR].f32;\nMEM[ADDR].f32 += DATA.f32;\nRETURN_DATA = tmp", "example": "flat_atomic_add_f32 v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Floating-point addition handles NAN/INF/denorm.", "sourcePdfPage": 490, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_add_f64", "mnemonic": "flat_atomic_add_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC ADD F64", "category": "Flat Memory", "instructionClass": "vector", "summary": "Add a double-precision float value in the data register to a location in the flat aperture.", "description": "Add a double-precision float value in the data register to a location in the flat aperture. Store the original value from flat aperture into a vector register iff the SC0 bit is set.", "syntax": "flat_atomic_add_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "tmp = MEM[ADDR].f64;\nMEM[ADDR].f64 += DATA.f64;\nRETURN_DATA = tmp", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx942" ], "unsupportedTargets": [], "architecturalNotes": "Floating-point addition handles NAN/INF/denorm.", "sourcePdfPage": 491, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.flat_atomic_add_u32", "mnemonic": "flat_atomic_add_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC ADD U32", "category": "Flat Memory", "instructionClass": "vector", "summary": "Add two unsigned 32-bit integer values stored in the data register and a location in the flat aperture.", "description": "Add two unsigned 32-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.", "syntax": "flat_atomic_add_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": "flat_atomic_add_u32 v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_add_u64", "mnemonic": "flat_atomic_add_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC ADD U64", "category": "Flat Memory", "instructionClass": "vector", "summary": "Add two unsigned 64-bit integer values stored in the data register and a location in the flat aperture.", "description": "Add two unsigned 64-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.", "syntax": "flat_atomic_add_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "", "example": "flat_atomic_add_u64 v[1:2], v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_add_x2", "mnemonic": "flat_atomic_add_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC ADD X2", "category": "Flat Memory", "instructionClass": "vector", "summary": "Add two unsigned 64-bit integer values stored in the data register and a location in the flat aperture.", "description": "Add two unsigned 64-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the SC0 bit is set.", "syntax": "flat_atomic_add_x2", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\ntmp = MEM[addr].u64;\nMEM[addr].u64 += DATA.u64;\nRETURN_DATA.u64 = tmp", "example": "flat_atomic_add_x2 v[1:2], v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 493, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_and", "mnemonic": "flat_atomic_and", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC AND", "category": "Flat Memory", "instructionClass": "vector", "summary": "Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in the flat aperture.", "description": "Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the SC0 bit is set.", "syntax": "flat_atomic_and", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\ntmp = MEM[addr].b32;\nMEM[addr].b32 = (tmp & DATA.b32);\nRETURN_DATA.b32 = tmp", "example": "flat_atomic_and v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 489, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_and_b32", "mnemonic": "flat_atomic_and_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC AND B32", "category": "Flat Memory", "instructionClass": "vector", "summary": "Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in the flat aperture.", "description": "Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.", "syntax": "flat_atomic_and_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "flat_atomic_and_b32 v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_and_b64", "mnemonic": "flat_atomic_and_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC AND B64", "category": "Flat Memory", "instructionClass": "vector", "summary": "Calculate bitwise AND given two unsigned 64-bit integer values stored in the data register and a location in the flat aperture.", "description": "Calculate bitwise AND given two unsigned 64-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.", "syntax": "flat_atomic_and_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "flat_atomic_and_b64 v[1:2], v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_and_x2", "mnemonic": "flat_atomic_and_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC AND X2", "category": "Flat Memory", "instructionClass": "vector", "summary": "Calculate bitwise AND given two unsigned 64-bit integer values stored in the data register and a location in the flat aperture.", "description": "Calculate bitwise AND given two unsigned 64-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the SC0 bit is set.", "syntax": "flat_atomic_and_x2", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\ntmp = MEM[addr].b64;\nMEM[addr].b64 = (tmp & DATA.b64);\nRETURN_DATA.b64 = tmp", "example": "flat_atomic_and_x2 v[1:2], v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 495, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_cmpswap", "mnemonic": "flat_atomic_cmpswap", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC CMPSWAP", "category": "Flat Memory", "instructionClass": "vector", "summary": "Compare two unsigned 32-bit integer values stored in the data comparison register and a location in the flat aperture.", "description": "Compare two unsigned 32-bit integer values stored in the data comparison register and a location in the flat aperture. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from flat aperture into a vector register iff the SC0 bit is set. NOTE: RETURN_DATA[1] is not modified.", "syntax": "flat_atomic_cmpswap", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\ntmp = MEM[addr].u32;\nsrc = DATA[31 : 0].u32;\ncmp = DATA[63 : 32].u32;\nMEM[addr].u32 = tmp == cmp ? src : tmp;\nRETURN_DATA.u32 = tmp", "example": "flat_atomic_cmpswap v[1:2], v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 487, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_cmpswap_b32", "mnemonic": "flat_atomic_cmpswap_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC CMPSWAP B32", "category": "Flat Memory", "instructionClass": "vector", "summary": "Compare two unsigned 32-bit integer values stored in the data comparison register and a location in the flat aperture.", "description": "Compare two unsigned 32-bit integer values stored in the data comparison register and a location in the flat aperture. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.", "syntax": "flat_atomic_cmpswap_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "flat_atomic_cmpswap_b32 v[1:2], v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_cmpswap_b64", "mnemonic": "flat_atomic_cmpswap_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC CMPSWAP B64", "category": "Flat Memory", "instructionClass": "vector", "summary": "Compare two unsigned 64-bit integer values stored in the data comparison register and a location in the flat aperture.", "description": "Compare two unsigned 64-bit integer values stored in the data comparison register and a location in the flat aperture. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.", "syntax": "flat_atomic_cmpswap_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "flat_atomic_cmpswap_b64 v[1:2], v[2:5]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_cmpswap_f32", "mnemonic": "flat_atomic_cmpswap_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC CMPSWAP F32", "category": "Flat Memory", "instructionClass": "vector", "summary": "Compare two single-precision float values stored in the data comparison register and a location in the flat aperture.", "description": "Compare two single-precision float values stored in the data comparison register and a location in the flat aperture. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from flat aperture into a vector register iff the GLC bit is set.", "syntax": "flat_atomic_cmpswap_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": "flat_atomic_cmpswap_f32 v[1:2], v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_cmpswap_x2", "mnemonic": "flat_atomic_cmpswap_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC CMPSWAP X2", "category": "Flat Memory", "instructionClass": "vector", "summary": "Compare two unsigned 64-bit integer values stored in the data comparison register and a location in the flat aperture.", "description": "Compare two unsigned 64-bit integer values stored in the data comparison register and a location in the flat aperture. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from flat aperture into a vector register iff the SC0 bit is set. NOTE: RETURN_DATA[2:3] is not modified.", "syntax": "flat_atomic_cmpswap_x2", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\ntmp = MEM[addr].u64;\nsrc = DATA[63 : 0].u64;\ncmp = DATA[127 : 64].u64;\nMEM[addr].u64 = tmp == cmp ? src : tmp;\nRETURN_DATA.u64 = tmp", "example": "flat_atomic_cmpswap_x2 v[1:2], v[2:5]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 493, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_cond_sub_u32", "mnemonic": "flat_atomic_cond_sub_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC COND SUB U32", "category": "Flat Memory", "instructionClass": "vector", "summary": "Subtract an unsigned 32-bit integer value in the data register from a location in the flat aperture only if the memory value is greater than or equal…", "description": "Subtract an unsigned 32-bit integer value in the data register from a location in the flat aperture only if the memory value is greater than or equal to the data register value. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.", "syntax": "flat_atomic_cond_sub_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.flat_atomic_csub_u32", "mnemonic": "flat_atomic_csub_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC CSUB U32", "category": "Flat Memory", "instructionClass": "vector", "summary": "AMDGPU FLAT vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "flat_atomic_csub_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.flat_atomic_dec", "mnemonic": "flat_atomic_dec", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC DEC", "category": "Flat Memory", "instructionClass": "vector", "summary": "Decrement an unsigned 32-bit integer value from a location in the flat aperture with wraparound to a value in the data register if the decrement…", "description": "Decrement an unsigned 32-bit integer value from a location in the flat aperture with wraparound to a value in the data register if the decrement yields a negative value. Store the original value from flat aperture into a vector register iff the SC0 bit is set.", "syntax": "flat_atomic_dec", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\ntmp = MEM[addr].u32;\nsrc = DATA.u32;\nMEM[addr].u32 = ((tmp == 0U) || (tmp > src)) ? src : tmp - 1U;\nRETURN_DATA.u32 = tmp", "example": "flat_atomic_dec v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 490, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_dec_u32", "mnemonic": "flat_atomic_dec_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC DEC U32", "category": "Flat Memory", "instructionClass": "vector", "summary": "Decrement an unsigned 32-bit integer value from a location in the flat aperture with wraparound to a value in the data register if the decrement…", "description": "Decrement an unsigned 32-bit integer value from a location in the flat aperture with wraparound to a value in the data register if the decrement yields a negative value. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.", "syntax": "flat_atomic_dec_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": "flat_atomic_dec_u32 v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_dec_u64", "mnemonic": "flat_atomic_dec_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC DEC U64", "category": "Flat Memory", "instructionClass": "vector", "summary": "Decrement an unsigned 64-bit integer value from a location in the flat aperture with wraparound to a value in the data register if the decrement…", "description": "Decrement an unsigned 64-bit integer value from a location in the flat aperture with wraparound to a value in the data register if the decrement yields a negative value. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.", "syntax": "flat_atomic_dec_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "", "example": "flat_atomic_dec_u64 v[1:2], v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_dec_x2", "mnemonic": "flat_atomic_dec_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC DEC X2", "category": "Flat Memory", "instructionClass": "vector", "summary": "Decrement an unsigned 64-bit integer value from a location in the flat aperture with wraparound to a value in the data register if the decrement…", "description": "Decrement an unsigned 64-bit integer value from a location in the flat aperture with wraparound to a value in the data register if the decrement yields a negative value. Store the original value from flat aperture into a vector register iff the SC0 bit is set.", "syntax": "flat_atomic_dec_x2", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\ntmp = MEM[addr].u64;\nsrc = DATA.u64;\nMEM[addr].u64 = ((tmp == 0ULL) || (tmp > src)) ? src : tmp - 1ULL;\nRETURN_DATA.u64 = tmp\naddr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nVDATA[31 : 0] = MEM[addr].b32", "example": "flat_atomic_dec_x2 v[1:2], v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 496, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_fcmpswap", "mnemonic": "flat_atomic_fcmpswap", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC FCMPSWAP", "category": "Flat Memory", "instructionClass": "vector", "summary": "Compare two single-precision float values stored in the data comparison register and a location in the flat aperture.", "description": "Compare two single-precision float values stored in the data comparison register and a location in the flat aperture. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from flat aperture into a vector register iff the GLC bit is set.", "syntax": "flat_atomic_fcmpswap", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.flat_atomic_fcmpswap_x2", "mnemonic": "flat_atomic_fcmpswap_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC FCMPSWAP X2", "category": "Flat Memory", "instructionClass": "vector", "summary": "Compare two double-precision float values stored in the data comparison register and a location in the flat aperture.", "description": "Compare two double-precision float values stored in the data comparison register and a location in the flat aperture. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from flat aperture into a vector register iff the GLC bit is set.", "syntax": "flat_atomic_fcmpswap_x2", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.flat_atomic_fmax", "mnemonic": "flat_atomic_fmax", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC FMAX", "category": "Flat Memory", "instructionClass": "vector", "summary": "Select the maximum of two single-precision float inputs, given two values stored in the data register and a location in the flat aperture.", "description": "Select the maximum of two single-precision float inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the GLC bit is set.", "syntax": "flat_atomic_fmax", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.flat_atomic_fmax_x2", "mnemonic": "flat_atomic_fmax_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC FMAX X2", "category": "Flat Memory", "instructionClass": "vector", "summary": "Select the maximum of two double-precision float inputs, given two values stored in the data register and a location in the flat aperture.", "description": "Select the maximum of two double-precision float inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the GLC bit is set.", "syntax": "flat_atomic_fmax_x2", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.flat_atomic_fmin", "mnemonic": "flat_atomic_fmin", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC FMIN", "category": "Flat Memory", "instructionClass": "vector", "summary": "Select the minimum of two single-precision float inputs, given two values stored in the data register and a location in the flat aperture.", "description": "Select the minimum of two single-precision float inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the GLC bit is set.", "syntax": "flat_atomic_fmin", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.flat_atomic_fmin_x2", "mnemonic": "flat_atomic_fmin_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC FMIN X2", "category": "Flat Memory", "instructionClass": "vector", "summary": "Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in the flat aperture.", "description": "Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the GLC bit is set.", "syntax": "flat_atomic_fmin_x2", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.flat_atomic_inc", "mnemonic": "flat_atomic_inc", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC INC", "category": "Flat Memory", "instructionClass": "vector", "summary": "Increment an unsigned 32-bit integer value from a location in the flat aperture with wraparound to 0 if the value exceeds a value in the data…", "description": "Increment an unsigned 32-bit integer value from a location in the flat aperture with wraparound to 0 if the value exceeds a value in the data register. Store the original value from flat aperture into a vector register iff the SC0 bit is set.", "syntax": "flat_atomic_inc", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\ntmp = MEM[addr].u32;\nsrc = DATA.u32;\nMEM[addr].u32 = tmp >= src ? 0U : tmp + 1U;\nRETURN_DATA.u32 = tmp", "example": "flat_atomic_inc v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 490, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_inc_u32", "mnemonic": "flat_atomic_inc_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC INC U32", "category": "Flat Memory", "instructionClass": "vector", "summary": "Increment an unsigned 32-bit integer value from a location in the flat aperture with wraparound to 0 if the value exceeds a value in the data…", "description": "Increment an unsigned 32-bit integer value from a location in the flat aperture with wraparound to 0 if the value exceeds a value in the data register. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.", "syntax": "flat_atomic_inc_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": "flat_atomic_inc_u32 v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_inc_u64", "mnemonic": "flat_atomic_inc_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC INC U64", "category": "Flat Memory", "instructionClass": "vector", "summary": "Increment an unsigned 64-bit integer value from a location in the flat aperture with wraparound to 0 if the value exceeds a value in the data…", "description": "Increment an unsigned 64-bit integer value from a location in the flat aperture with wraparound to 0 if the value exceeds a value in the data register. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.", "syntax": "flat_atomic_inc_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "", "example": "flat_atomic_inc_u64 v[1:2], v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_inc_x2", "mnemonic": "flat_atomic_inc_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC INC X2", "category": "Flat Memory", "instructionClass": "vector", "summary": "Increment an unsigned 64-bit integer value from a location in the flat aperture with wraparound to 0 if the value exceeds a value in the data…", "description": "Increment an unsigned 64-bit integer value from a location in the flat aperture with wraparound to 0 if the value exceeds a value in the data register. Store the original value from flat aperture into a vector register iff the SC0 bit is set.", "syntax": "flat_atomic_inc_x2", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\ntmp = MEM[addr].u64;\nsrc = DATA.u64;\nMEM[addr].u64 = tmp >= src ? 0ULL : tmp + 1ULL;\nRETURN_DATA.u64 = tmp", "example": "flat_atomic_inc_x2 v[1:2], v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 495, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_max_f32", "mnemonic": "flat_atomic_max_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC MAX F32", "category": "Flat Memory", "instructionClass": "vector", "summary": "Select the maximum of two single-precision float inputs, given two values stored in the data register and a location in the flat aperture.", "description": "Select the maximum of two single-precision float inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the GLC bit is set.", "syntax": "flat_atomic_max_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": "flat_atomic_max_f32 v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_max_f64", "mnemonic": "flat_atomic_max_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC MAX F64", "category": "Flat Memory", "instructionClass": "vector", "summary": "Select the maximum of two double-precision float inputs, given two values stored in the data register and a location in the flat aperture.", "description": "Select the maximum of two double-precision float inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the SC0 bit is set.", "syntax": "flat_atomic_max_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\ntmp = MEM[addr].f64;\nsrc = DATA.f64;\nMEM[addr].f64 = src > tmp ? src : tmp;\nRETURN_DATA.f64 = tmp", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx942" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 492, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.flat_atomic_max_i32", "mnemonic": "flat_atomic_max_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC MAX I32", "category": "Flat Memory", "instructionClass": "vector", "summary": "Select the maximum of two signed 32-bit integer inputs, given two values stored in the data register and a location in the flat aperture.", "description": "Select the maximum of two signed 32-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.", "syntax": "flat_atomic_max_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "", "example": "flat_atomic_max_i32 v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_max_i64", "mnemonic": "flat_atomic_max_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC MAX I64", "category": "Flat Memory", "instructionClass": "vector", "summary": "Select the maximum of two signed 64-bit integer inputs, given two values stored in the data register and a location in the flat aperture.", "description": "Select the maximum of two signed 64-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.", "syntax": "flat_atomic_max_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "", "example": "flat_atomic_max_i64 v[1:2], v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_max_u32", "mnemonic": "flat_atomic_max_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC MAX U32", "category": "Flat Memory", "instructionClass": "vector", "summary": "Select the maximum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in the flat aperture.", "description": "Select the maximum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.", "syntax": "flat_atomic_max_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": "flat_atomic_max_u32 v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_max_u64", "mnemonic": "flat_atomic_max_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC MAX U64", "category": "Flat Memory", "instructionClass": "vector", "summary": "Select the maximum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in the flat aperture.", "description": "Select the maximum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.", "syntax": "flat_atomic_max_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "", "example": "flat_atomic_max_u64 v[1:2], v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_min_f32", "mnemonic": "flat_atomic_min_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC MIN F32", "category": "Flat Memory", "instructionClass": "vector", "summary": "Select the minimum of two single-precision float inputs, given two values stored in the data register and a location in the flat aperture.", "description": "Select the minimum of two single-precision float inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the GLC bit is set.", "syntax": "flat_atomic_min_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": "flat_atomic_min_f32 v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_min_f64", "mnemonic": "flat_atomic_min_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC MIN F64", "category": "Flat Memory", "instructionClass": "vector", "summary": "Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in the flat aperture.", "description": "Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the SC0 bit is set.", "syntax": "flat_atomic_min_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\ntmp = MEM[addr].f64;\nsrc = DATA.f64;\nMEM[addr].f64 = src < tmp ? src : tmp;\nRETURN_DATA.f64 = tmp", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx942" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 491, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.flat_atomic_min_i32", "mnemonic": "flat_atomic_min_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC MIN I32", "category": "Flat Memory", "instructionClass": "vector", "summary": "Select the minimum of two signed 32-bit integer inputs, given two values stored in the data register and a location in the flat aperture.", "description": "Select the minimum of two signed 32-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.", "syntax": "flat_atomic_min_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "", "example": "flat_atomic_min_i32 v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_min_i64", "mnemonic": "flat_atomic_min_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC MIN I64", "category": "Flat Memory", "instructionClass": "vector", "summary": "Select the minimum of two signed 64-bit integer inputs, given two values stored in the data register and a location in the flat aperture.", "description": "Select the minimum of two signed 64-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.", "syntax": "flat_atomic_min_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "", "example": "flat_atomic_min_i64 v[1:2], v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_min_u32", "mnemonic": "flat_atomic_min_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC MIN U32", "category": "Flat Memory", "instructionClass": "vector", "summary": "Select the minimum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in the flat aperture.", "description": "Select the minimum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.", "syntax": "flat_atomic_min_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": "flat_atomic_min_u32 v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_min_u64", "mnemonic": "flat_atomic_min_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC MIN U64", "category": "Flat Memory", "instructionClass": "vector", "summary": "Select the minimum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in the flat aperture.", "description": "Select the minimum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.", "syntax": "flat_atomic_min_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "", "example": "flat_atomic_min_u64 v[1:2], v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_or", "mnemonic": "flat_atomic_or", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC OR", "category": "Flat Memory", "instructionClass": "vector", "summary": "Calculate bitwise OR given two unsigned 32-bit integer values stored in the data register and a location in the flat aperture.", "description": "Calculate bitwise OR given two unsigned 32-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the SC0 bit is set.", "syntax": "flat_atomic_or", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\ntmp = MEM[addr].b32;\nMEM[addr].b32 = (tmp | DATA.b32);\nRETURN_DATA.b32 = tmp", "example": "flat_atomic_or v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 489, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_or_b32", "mnemonic": "flat_atomic_or_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC OR B32", "category": "Flat Memory", "instructionClass": "vector", "summary": "Calculate bitwise OR given two unsigned 32-bit integer values stored in the data register and a location in the flat aperture.", "description": "Calculate bitwise OR given two unsigned 32-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.", "syntax": "flat_atomic_or_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "flat_atomic_or_b32 v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_or_b64", "mnemonic": "flat_atomic_or_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC OR B64", "category": "Flat Memory", "instructionClass": "vector", "summary": "Calculate bitwise OR given two unsigned 64-bit integer values stored in the data register and a location in the flat aperture.", "description": "Calculate bitwise OR given two unsigned 64-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.", "syntax": "flat_atomic_or_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "flat_atomic_or_b64 v[1:2], v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_or_x2", "mnemonic": "flat_atomic_or_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC OR X2", "category": "Flat Memory", "instructionClass": "vector", "summary": "Calculate bitwise OR given two unsigned 64-bit integer values stored in the data register and a location in the flat aperture.", "description": "Calculate bitwise OR given two unsigned 64-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the SC0 bit is set.", "syntax": "flat_atomic_or_x2", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\ntmp = MEM[addr].b64;\nMEM[addr].b64 = (tmp | DATA.b64);\nRETURN_DATA.b64 = tmp", "example": "flat_atomic_or_x2 v[1:2], v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 495, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_pk_add_bf16", "mnemonic": "flat_atomic_pk_add_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC PK ADD BF16", "category": "Flat Memory", "instructionClass": "vector", "summary": "Add a packed 2-component BF16 float value in the data register to a location in the flat aperture.", "description": "Add a packed 2-component BF16 float value in the data register to a location in the flat aperture. Store the original value from flat aperture into a vector register iff the SC0 bit is set.", "syntax": "flat_atomic_pk_add_bf16", "operands": [], "dataTypes": [], "semantics": "tmp = MEM[ADDR];\nsrc = DATA;\ndst[31 : 16].bf16 = tmp[31 : 16].bf16 + src[31 : 16].bf16;\ndst[15 : 0].bf16 = tmp[15 : 0].bf16 + src[15 : 0].bf16;\nMEM[ADDR] = dst.b32;\nRETURN_DATA = tmp", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "Floating-point addition handles NAN/INF/denorm.", "sourcePdfPage": 492, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.flat_atomic_pk_add_f16", "mnemonic": "flat_atomic_pk_add_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC PK ADD F16", "category": "Flat Memory", "instructionClass": "vector", "summary": "Add a packed 2-component half-precision float value in the data register to a location in the flat aperture.", "description": "Add a packed 2-component half-precision float value in the data register to a location in the flat aperture. Store the original value from flat aperture into a vector register iff the SC0 bit is set.", "syntax": "flat_atomic_pk_add_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "tmp = MEM[ADDR];\nsrc = DATA;\ndst[31 : 16].f16 = tmp[31 : 16].f16 + src[31 : 16].f16;\ndst[15 : 0].f16 = tmp[15 : 0].f16 + src[15 : 0].f16;\nMEM[ADDR] = dst.b32;\nRETURN_DATA = tmp", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "Floating-point addition handles NAN/INF/denorm.", "sourcePdfPage": 491, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.flat_atomic_smax", "mnemonic": "flat_atomic_smax", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC SMAX", "category": "Flat Memory", "instructionClass": "vector", "summary": "Select the maximum of two signed 32-bit integer inputs, given two values stored in the data register and a location in the flat aperture.", "description": "Select the maximum of two signed 32-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the SC0 bit is set.", "syntax": "flat_atomic_smax", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\ntmp = MEM[addr].i32;\nsrc = DATA.i32;\nMEM[addr].i32 = src >= tmp ? src : tmp;\nRETURN_DATA.i32 = tmp", "example": "flat_atomic_smax v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 489, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_smax_x2", "mnemonic": "flat_atomic_smax_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC SMAX X2", "category": "Flat Memory", "instructionClass": "vector", "summary": "Select the maximum of two signed 64-bit integer inputs, given two values stored in the data register and a location in the flat aperture.", "description": "Select the maximum of two signed 64-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the SC0 bit is set.", "syntax": "flat_atomic_smax_x2", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\ntmp = MEM[addr].i64;\nsrc = DATA.i64;\nMEM[addr].i64 = src >= tmp ? src : tmp;\nRETURN_DATA.i64 = tmp", "example": "flat_atomic_smax_x2 v[1:2], v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 494, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_smin", "mnemonic": "flat_atomic_smin", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC SMIN", "category": "Flat Memory", "instructionClass": "vector", "summary": "Select the minimum of two signed 32-bit integer inputs, given two values stored in the data register and a location in the flat aperture.", "description": "Select the minimum of two signed 32-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the SC0 bit is set.", "syntax": "flat_atomic_smin", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\ntmp = MEM[addr].i32;\nsrc = DATA.i32;\nMEM[addr].i32 = src < tmp ? src : tmp;\nRETURN_DATA.i32 = tmp", "example": "flat_atomic_smin v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 488, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_smin_x2", "mnemonic": "flat_atomic_smin_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC SMIN X2", "category": "Flat Memory", "instructionClass": "vector", "summary": "Select the minimum of two signed 64-bit integer inputs, given two values stored in the data register and a location in the flat aperture.", "description": "Select the minimum of two signed 64-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the SC0 bit is set.", "syntax": "flat_atomic_smin_x2", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\ntmp = MEM[addr].i64;\nsrc = DATA.i64;\nMEM[addr].i64 = src < tmp ? src : tmp;\nRETURN_DATA.i64 = tmp", "example": "flat_atomic_smin_x2 v[1:2], v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 493, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_sub", "mnemonic": "flat_atomic_sub", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC SUB", "category": "Flat Memory", "instructionClass": "vector", "summary": "Subtract an unsigned 32-bit integer value stored in the data register from a value stored in a location in the flat aperture.", "description": "Subtract an unsigned 32-bit integer value stored in the data register from a value stored in a location in the flat aperture. Store the original value from flat aperture into a vector register iff the SC0 bit is set.", "syntax": "flat_atomic_sub", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\ntmp = MEM[addr].u32;\nMEM[addr].u32 -= DATA.u32;\nRETURN_DATA.u32 = tmp", "example": "flat_atomic_sub v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 488, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_sub_u32", "mnemonic": "flat_atomic_sub_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC SUB U32", "category": "Flat Memory", "instructionClass": "vector", "summary": "Subtract an unsigned 32-bit integer value stored in the data register from a value stored in a location in the flat aperture.", "description": "Subtract an unsigned 32-bit integer value stored in the data register from a value stored in a location in the flat aperture. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.", "syntax": "flat_atomic_sub_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": "flat_atomic_sub_u32 v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_sub_u64", "mnemonic": "flat_atomic_sub_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC SUB U64", "category": "Flat Memory", "instructionClass": "vector", "summary": "Subtract an unsigned 64-bit integer value stored in the data register from a value stored in a location in the flat aperture.", "description": "Subtract an unsigned 64-bit integer value stored in the data register from a value stored in a location in the flat aperture. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.", "syntax": "flat_atomic_sub_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "", "example": "flat_atomic_sub_u64 v[1:2], v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_sub_x2", "mnemonic": "flat_atomic_sub_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC SUB X2", "category": "Flat Memory", "instructionClass": "vector", "summary": "Subtract an unsigned 64-bit integer value stored in the data register from a value stored in a location in the flat aperture.", "description": "Subtract an unsigned 64-bit integer value stored in the data register from a value stored in a location in the flat aperture. Store the original value from flat aperture into a vector register iff the SC0 bit is set.", "syntax": "flat_atomic_sub_x2", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\ntmp = MEM[addr].u64;\nMEM[addr].u64 -= DATA.u64;\nRETURN_DATA.u64 = tmp", "example": "flat_atomic_sub_x2 v[1:2], v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 493, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_swap", "mnemonic": "flat_atomic_swap", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC SWAP", "category": "Flat Memory", "instructionClass": "vector", "summary": "Swap an unsigned 32-bit integer value in the data register with a location in the flat aperture.", "description": "Swap an unsigned 32-bit integer value in the data register with a location in the flat aperture. Store the original value from flat aperture into a vector register iff the SC0 bit is set.", "syntax": "flat_atomic_swap", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\ntmp = MEM[addr].b32;\nMEM[addr].b32 = DATA.b32;\nRETURN_DATA.b32 = tmp", "example": "flat_atomic_swap v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 487, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_swap_b32", "mnemonic": "flat_atomic_swap_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC SWAP B32", "category": "Flat Memory", "instructionClass": "vector", "summary": "Swap an unsigned 32-bit integer value in the data register with a location in the flat aperture.", "description": "Swap an unsigned 32-bit integer value in the data register with a location in the flat aperture. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.", "syntax": "flat_atomic_swap_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "flat_atomic_swap_b32 v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_swap_b64", "mnemonic": "flat_atomic_swap_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC SWAP B64", "category": "Flat Memory", "instructionClass": "vector", "summary": "Swap an unsigned 64-bit integer value in the data register with a location in the flat aperture.", "description": "Swap an unsigned 64-bit integer value in the data register with a location in the flat aperture. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.", "syntax": "flat_atomic_swap_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "flat_atomic_swap_b64 v[1:2], v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_swap_x2", "mnemonic": "flat_atomic_swap_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC SWAP X2", "category": "Flat Memory", "instructionClass": "vector", "summary": "Swap an unsigned 64-bit integer value in the data register with a location in the flat aperture.", "description": "Swap an unsigned 64-bit integer value in the data register with a location in the flat aperture. Store the original value from flat aperture into a vector register iff the SC0 bit is set.", "syntax": "flat_atomic_swap_x2", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\ntmp = MEM[addr].b64;\nMEM[addr].b64 = DATA.b64;\nRETURN_DATA.b64 = tmp", "example": "flat_atomic_swap_x2 v[1:2], v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 492, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_umax", "mnemonic": "flat_atomic_umax", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC UMAX", "category": "Flat Memory", "instructionClass": "vector", "summary": "Select the maximum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in the flat aperture.", "description": "Select the maximum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the SC0 bit is set.", "syntax": "flat_atomic_umax", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\ntmp = MEM[addr].u32;\nsrc = DATA.u32;\nMEM[addr].u32 = src >= tmp ? src : tmp;\nRETURN_DATA.u32 = tmp", "example": "flat_atomic_umax v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 489, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_umax_x2", "mnemonic": "flat_atomic_umax_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC UMAX X2", "category": "Flat Memory", "instructionClass": "vector", "summary": "Select the maximum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in the flat aperture.", "description": "Select the maximum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the SC0 bit is set.", "syntax": "flat_atomic_umax_x2", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\ntmp = MEM[addr].u64;\nsrc = DATA.u64;\nMEM[addr].u64 = src >= tmp ? src : tmp;\nRETURN_DATA.u64 = tmp", "example": "flat_atomic_umax_x2 v[1:2], v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 494, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_umin", "mnemonic": "flat_atomic_umin", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC UMIN", "category": "Flat Memory", "instructionClass": "vector", "summary": "Select the minimum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in the flat aperture.", "description": "Select the minimum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the SC0 bit is set.", "syntax": "flat_atomic_umin", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\ntmp = MEM[addr].u32;\nsrc = DATA.u32;\nMEM[addr].u32 = src < tmp ? src : tmp;\nRETURN_DATA.u32 = tmp", "example": "flat_atomic_umin v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 488, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_umin_x2", "mnemonic": "flat_atomic_umin_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC UMIN X2", "category": "Flat Memory", "instructionClass": "vector", "summary": "Select the minimum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in the flat aperture.", "description": "Select the minimum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the SC0 bit is set.", "syntax": "flat_atomic_umin_x2", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\ntmp = MEM[addr].u64;\nsrc = DATA.u64;\nMEM[addr].u64 = src < tmp ? src : tmp;\nRETURN_DATA.u64 = tmp", "example": "flat_atomic_umin_x2 v[1:2], v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 494, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_xor", "mnemonic": "flat_atomic_xor", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC XOR", "category": "Flat Memory", "instructionClass": "vector", "summary": "Calculate bitwise XOR given two unsigned 32-bit integer values stored in the data register and a location in the flat aperture.", "description": "Calculate bitwise XOR given two unsigned 32-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the SC0 bit is set.", "syntax": "flat_atomic_xor", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\ntmp = MEM[addr].b32;\nMEM[addr].b32 = (tmp ^ DATA.b32);\nRETURN_DATA.b32 = tmp", "example": "flat_atomic_xor v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 490, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_xor_b32", "mnemonic": "flat_atomic_xor_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC XOR B32", "category": "Flat Memory", "instructionClass": "vector", "summary": "Calculate bitwise XOR given two unsigned 32-bit integer values stored in the data register and a location in the flat aperture.", "description": "Calculate bitwise XOR given two unsigned 32-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.", "syntax": "flat_atomic_xor_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "flat_atomic_xor_b32 v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_xor_b64", "mnemonic": "flat_atomic_xor_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC XOR B64", "category": "Flat Memory", "instructionClass": "vector", "summary": "Calculate bitwise XOR given two unsigned 64-bit integer values stored in the data register and a location in the flat aperture.", "description": "Calculate bitwise XOR given two unsigned 64-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the temporal hint enables atomic return.", "syntax": "flat_atomic_xor_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "flat_atomic_xor_b64 v[1:2], v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_atomic_xor_x2", "mnemonic": "flat_atomic_xor_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT ATOMIC XOR X2", "category": "Flat Memory", "instructionClass": "vector", "summary": "Calculate bitwise XOR given two unsigned 64-bit integer values stored in the data register and a location in the flat aperture.", "description": "Calculate bitwise XOR given two unsigned 64-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the SC0 bit is set.", "syntax": "flat_atomic_xor_x2", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\ntmp = MEM[addr].b64;\nMEM[addr].b64 = (tmp ^ DATA.b64);\nRETURN_DATA.b64 = tmp", "example": "flat_atomic_xor_x2 v[1:2], v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 495, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_load_b128", "mnemonic": "flat_load_b128", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT LOAD B128", "category": "Flat Memory", "instructionClass": "vector", "summary": "Load 128 bits of data from the flat aperture into a vector register.", "description": "Load 128 bits of data from the flat aperture into a vector register.", "syntax": "flat_load_b128", "operands": [], "dataTypes": [], "semantics": "", "example": "flat_load_b128 v[5:8], v[1:2]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_load_b32", "mnemonic": "flat_load_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT LOAD B32", "category": "Flat Memory", "instructionClass": "vector", "summary": "Load 32 bits of data from the flat aperture into a vector register.", "description": "Load 32 bits of data from the flat aperture into a vector register.", "syntax": "flat_load_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "flat_load_b32 v5, v[1:2]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_load_b64", "mnemonic": "flat_load_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT LOAD B64", "category": "Flat Memory", "instructionClass": "vector", "summary": "Load 64 bits of data from the flat aperture into a vector register.", "description": "Load 64 bits of data from the flat aperture into a vector register.", "syntax": "flat_load_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "flat_load_b64 v[5:6], v[1:2]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_load_b96", "mnemonic": "flat_load_b96", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT LOAD B96", "category": "Flat Memory", "instructionClass": "vector", "summary": "Load 96 bits of data from the flat aperture into a vector register.", "description": "Load 96 bits of data from the flat aperture into a vector register.", "syntax": "flat_load_b96", "operands": [], "dataTypes": [], "semantics": "", "example": "flat_load_b96 v[5:7], v[1:2]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_load_d16_b16", "mnemonic": "flat_load_d16_b16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT LOAD D16 B16", "category": "Flat Memory", "instructionClass": "vector", "summary": "Load 16 bits of unsigned data from the flat aperture and store the result into the low 16 bits of a 32-bit vector register.", "description": "Load 16 bits of unsigned data from the flat aperture and store the result into the low 16 bits of a 32-bit vector register.", "syntax": "flat_load_d16_b16", "operands": [], "dataTypes": [ "b16" ], "semantics": "", "example": "flat_load_d16_b16 v5, v[1:2]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_load_d16_hi_b16", "mnemonic": "flat_load_d16_hi_b16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT LOAD D16 HI B16", "category": "Flat Memory", "instructionClass": "vector", "summary": "Load 16 bits of unsigned data from the flat aperture and store the result into the high 16 bits of a 32-bit vector register.", "description": "Load 16 bits of unsigned data from the flat aperture and store the result into the high 16 bits of a 32-bit vector register.", "syntax": "flat_load_d16_hi_b16", "operands": [], "dataTypes": [ "b16" ], "semantics": "", "example": "flat_load_d16_hi_b16 v5, v[1:2]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_load_d16_hi_i8", "mnemonic": "flat_load_d16_hi_i8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT LOAD D16 HI I8", "category": "Flat Memory", "instructionClass": "vector", "summary": "Load 8 bits of signed data from the flat aperture, sign extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register.", "description": "Load 8 bits of signed data from the flat aperture, sign extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register.", "syntax": "flat_load_d16_hi_i8", "operands": [], "dataTypes": [ "i8" ], "semantics": "", "example": "flat_load_d16_hi_i8 v5, v[1:2]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_load_d16_hi_u8", "mnemonic": "flat_load_d16_hi_u8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT LOAD D16 HI U8", "category": "Flat Memory", "instructionClass": "vector", "summary": "Load 8 bits of unsigned data from the flat aperture, zero extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register.", "description": "Load 8 bits of unsigned data from the flat aperture, zero extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register.", "syntax": "flat_load_d16_hi_u8", "operands": [], "dataTypes": [ "u8" ], "semantics": "", "example": "flat_load_d16_hi_u8 v5, v[1:2]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_load_d16_i8", "mnemonic": "flat_load_d16_i8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT LOAD D16 I8", "category": "Flat Memory", "instructionClass": "vector", "summary": "Load 8 bits of signed data from the flat aperture, sign extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register.", "description": "Load 8 bits of signed data from the flat aperture, sign extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register.", "syntax": "flat_load_d16_i8", "operands": [], "dataTypes": [ "i8" ], "semantics": "", "example": "flat_load_d16_i8 v5, v[1:2]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_load_d16_u8", "mnemonic": "flat_load_d16_u8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT LOAD D16 U8", "category": "Flat Memory", "instructionClass": "vector", "summary": "Load 8 bits of unsigned data from the flat aperture, zero extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register.", "description": "Load 8 bits of unsigned data from the flat aperture, zero extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register.", "syntax": "flat_load_d16_u8", "operands": [], "dataTypes": [ "u8" ], "semantics": "", "example": "flat_load_d16_u8 v5, v[1:2]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_load_dword", "mnemonic": "flat_load_dword", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT LOAD DWORD", "category": "Flat Memory", "instructionClass": "vector", "summary": "Load one 32-bit dword per lane through the flat (generic) address space, resolved to global/scratch/LDS at runtime.", "description": "Load 32 bits of data from the flat aperture into a vector register.", "syntax": "flat_load_dword VDST, VADDR", "operands": [ { "name": "VDST", "desc": "Destination VGPR" }, { "name": "VADDR", "desc": "Per-lane 64-bit generic address (VGPR pair)" } ], "dataTypes": [], "semantics": "VDST[lane] = *(VADDR[lane]) for each active lane; the memory aperture (global, scratch, or LDS) is determined per-address at runtime rather than fixed by the instruction.", "example": "flat_load_dword v2, v[0:1] // v2 = *(v[0:1]), aperture resolved at runtime", "exampleSource": null, "encoding": { "format": "FLAT", "widthBits": 32 }, "executionUnit": "Vector Memory Unit", "registerClasses": [ "VGPR" ], "memorySegment": "flat/generic", "supportedTargets": [ "gfx942", "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "amd-machine-readable-isa" ] }, { "id": "amdgpu.flat_load_dwordx2", "mnemonic": "flat_load_dwordx2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT LOAD DWORDX2", "category": "Flat Memory", "instructionClass": "vector", "summary": "Load 64 bits of data from the flat aperture into a vector register.", "description": "Load 64 bits of data from the flat aperture into a vector register.", "syntax": "flat_load_dwordx2", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\nVDATA[31 : 0] = MEM[addr].b32;\nVDATA[63 : 32] = MEM[addr + 4U].b32", "example": "flat_load_dwordx2 v[5:6], v[1:2]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 483, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_load_dwordx3", "mnemonic": "flat_load_dwordx3", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT LOAD DWORDX3", "category": "Flat Memory", "instructionClass": "vector", "summary": "Load 96 bits of data from the flat aperture into a vector register.", "description": "Load 96 bits of data from the flat aperture into a vector register.", "syntax": "flat_load_dwordx3", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\nVDATA[31 : 0] = MEM[addr].b32;\nVDATA[63 : 32] = MEM[addr + 4U].b32;\nVDATA[95 : 64] = MEM[addr + 8U].b32", "example": "flat_load_dwordx3 v[5:7], v[1:2]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 483, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_load_dwordx4", "mnemonic": "flat_load_dwordx4", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT LOAD DWORDX4", "category": "Flat Memory", "instructionClass": "vector", "summary": "Load 128 bits of data from the flat aperture into a vector register.", "description": "Load 128 bits of data from the flat aperture into a vector register.", "syntax": "flat_load_dwordx4", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\nVDATA[31 : 0] = MEM[addr].b32;\nVDATA[63 : 32] = MEM[addr + 4U].b32;\nVDATA[95 : 64] = MEM[addr + 8U].b32;\nVDATA[127 : 96] = MEM[addr + 12U].b32", "example": "flat_load_dwordx4 v[5:8], v[1:2]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 484, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_load_i16", "mnemonic": "flat_load_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT LOAD I16", "category": "Flat Memory", "instructionClass": "vector", "summary": "Load 16 bits of signed data from the flat aperture, sign extend to 32 bits and store the result into a vector register.", "description": "Load 16 bits of signed data from the flat aperture, sign extend to 32 bits and store the result into a vector register.", "syntax": "flat_load_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "", "example": "flat_load_i16 v5, v[1:2]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_load_i8", "mnemonic": "flat_load_i8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT LOAD I8", "category": "Flat Memory", "instructionClass": "vector", "summary": "Load 8 bits of signed data from the flat aperture, sign extend to 32 bits and store the result into a vector register.", "description": "Load 8 bits of signed data from the flat aperture, sign extend to 32 bits and store the result into a vector register.", "syntax": "flat_load_i8", "operands": [], "dataTypes": [ "i8" ], "semantics": "", "example": "flat_load_i8 v5, v[1:2]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_load_monitor_b128", "mnemonic": "flat_load_monitor_b128", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT LOAD MONITOR B128", "category": "Flat Memory", "instructionClass": "vector", "summary": "AMDGPU FLAT vector instruction operating on b128 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "flat_load_monitor_b128", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.flat_load_monitor_b32", "mnemonic": "flat_load_monitor_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT LOAD MONITOR B32", "category": "Flat Memory", "instructionClass": "vector", "summary": "AMDGPU FLAT vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "flat_load_monitor_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.flat_load_monitor_b64", "mnemonic": "flat_load_monitor_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT LOAD MONITOR B64", "category": "Flat Memory", "instructionClass": "vector", "summary": "AMDGPU FLAT vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "flat_load_monitor_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.flat_load_sbyte", "mnemonic": "flat_load_sbyte", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT LOAD SBYTE", "category": "Flat Memory", "instructionClass": "vector", "summary": "Load 8 bits of signed data from the flat aperture, sign extend to 32 bits and store the result into a vector register.", "description": "Load 8 bits of signed data from the flat aperture, sign extend to 32 bits and store the result into a vector register.", "syntax": "flat_load_sbyte", "operands": [], "dataTypes": [], "semantics": "", "example": "flat_load_sbyte v5, v[1:2]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_load_sbyte_d16", "mnemonic": "flat_load_sbyte_d16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT LOAD SBYTE D16", "category": "Flat Memory", "instructionClass": "vector", "summary": "Load 8 bits of signed data from the flat aperture, sign extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register.", "description": "Load 8 bits of signed data from the flat aperture, sign extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register.", "syntax": "flat_load_sbyte_d16", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\nVDATA[15 : 0].i16 = 16'I(signext(MEM[addr].i8));\n// VDATA[31:16] is preserved.", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 486, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.flat_load_sbyte_d16_hi", "mnemonic": "flat_load_sbyte_d16_hi", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT LOAD SBYTE D16 HI", "category": "Flat Memory", "instructionClass": "vector", "summary": "Load 8 bits of signed data from the flat aperture, sign extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register.", "description": "Load 8 bits of signed data from the flat aperture, sign extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register.", "syntax": "flat_load_sbyte_d16_hi", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\nVDATA[31 : 16].i16 = 16'I(signext(MEM[addr].i8));\n// VDATA[15:0] is preserved.", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 486, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.flat_load_short_d16", "mnemonic": "flat_load_short_d16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT LOAD SHORT D16", "category": "Flat Memory", "instructionClass": "vector", "summary": "Load 16 bits of unsigned data from the flat aperture and store the result into the low 16 bits of a 32-bit vector register.", "description": "Load 16 bits of unsigned data from the flat aperture and store the result into the low 16 bits of a 32-bit vector register.", "syntax": "flat_load_short_d16", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\nVDATA[15 : 0].b16 = MEM[addr].b16;\n// VDATA[31:16] is preserved.", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 486, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.flat_load_short_d16_hi", "mnemonic": "flat_load_short_d16_hi", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT LOAD SHORT D16 HI", "category": "Flat Memory", "instructionClass": "vector", "summary": "Load 16 bits of unsigned data from the flat aperture and store the result into the high 16 bits of a 32-bit vector register.", "description": "Load 16 bits of unsigned data from the flat aperture and store the result into the high 16 bits of a 32-bit vector register.", "syntax": "flat_load_short_d16_hi", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\nVDATA[31 : 16].b16 = MEM[addr].b16;\n// VDATA[15:0] is preserved.", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 487, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.flat_load_sshort", "mnemonic": "flat_load_sshort", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT LOAD SSHORT", "category": "Flat Memory", "instructionClass": "vector", "summary": "Load 16 bits of signed data from the flat aperture, sign extend to 32 bits and store the result into a vector register.", "description": "Load 16 bits of signed data from the flat aperture, sign extend to 32 bits and store the result into a vector register.", "syntax": "flat_load_sshort", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\nVDATA.i32 = 32'I(signext(MEM[addr].i16))", "example": "flat_load_sshort v5, v[1:2]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 483, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_load_u16", "mnemonic": "flat_load_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT LOAD U16", "category": "Flat Memory", "instructionClass": "vector", "summary": "Load 16 bits of unsigned data from the flat aperture, zero extend to 32 bits and store the result into a vector register.", "description": "Load 16 bits of unsigned data from the flat aperture, zero extend to 32 bits and store the result into a vector register.", "syntax": "flat_load_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "", "example": "flat_load_u16 v5, v[1:2]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_load_u8", "mnemonic": "flat_load_u8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT LOAD U8", "category": "Flat Memory", "instructionClass": "vector", "summary": "Load 8 bits of unsigned data from the flat aperture, zero extend to 32 bits and store the result into a vector register.", "description": "Load 8 bits of unsigned data from the flat aperture, zero extend to 32 bits and store the result into a vector register.", "syntax": "flat_load_u8", "operands": [], "dataTypes": [ "u8" ], "semantics": "", "example": "flat_load_u8 v5, v[1:2]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_load_ubyte", "mnemonic": "flat_load_ubyte", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT LOAD UBYTE", "category": "Flat Memory", "instructionClass": "vector", "summary": "Load 8 bits of unsigned data from the flat aperture, zero extend to 32 bits and store the result into a vector register.", "description": "Load 8 bits of unsigned data from the flat aperture, zero extend to 32 bits and store the result into a vector register.", "syntax": "flat_load_ubyte", "operands": [], "dataTypes": [], "semantics": "", "example": "flat_load_ubyte v5, v[1:2]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_load_ubyte_d16", "mnemonic": "flat_load_ubyte_d16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT LOAD UBYTE D16", "category": "Flat Memory", "instructionClass": "vector", "summary": "Load 8 bits of unsigned data from the flat aperture, zero extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register.", "description": "Load 8 bits of unsigned data from the flat aperture, zero extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register.", "syntax": "flat_load_ubyte_d16", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\nVDATA[15 : 0].u16 = 16'U({ 8'0U, MEM[addr].u8 });\n// VDATA[31:16] is preserved.", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 486, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.flat_load_ubyte_d16_hi", "mnemonic": "flat_load_ubyte_d16_hi", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT LOAD UBYTE D16 HI", "category": "Flat Memory", "instructionClass": "vector", "summary": "Load 8 bits of unsigned data from the flat aperture, zero extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register.", "description": "Load 8 bits of unsigned data from the flat aperture, zero extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register.", "syntax": "flat_load_ubyte_d16_hi", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\nVDATA[31 : 16].u16 = 16'U({ 8'0U, MEM[addr].u8 });\n// VDATA[15:0] is preserved.", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 486, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.flat_load_ushort", "mnemonic": "flat_load_ushort", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT LOAD USHORT", "category": "Flat Memory", "instructionClass": "vector", "summary": "Load 16 bits of unsigned data from the flat aperture, zero extend to 32 bits and store the result into a vector register.", "description": "Load 16 bits of unsigned data from the flat aperture, zero extend to 32 bits and store the result into a vector register.", "syntax": "flat_load_ushort", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\nVDATA.u32 = 32'U({ 16'0U, MEM[addr].u16 })", "example": "flat_load_ushort v5, v[1:2]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 483, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_prefetch_b8", "mnemonic": "flat_prefetch_b8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT PREFETCH B8", "category": "Flat Memory", "instructionClass": "vector", "summary": "AMDGPU FLAT vector instruction operating on b8 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "flat_prefetch_b8", "operands": [], "dataTypes": [ "b8" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.flat_store_b128", "mnemonic": "flat_store_b128", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT STORE B128", "category": "Flat Memory", "instructionClass": "vector", "summary": "Store 128 bits of data from vector input registers into the flat aperture.", "description": "Store 128 bits of data from vector input registers into the flat aperture.", "syntax": "flat_store_b128", "operands": [], "dataTypes": [], "semantics": "", "example": "flat_store_b128 v[1:2], v[2:5]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_store_b16", "mnemonic": "flat_store_b16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT STORE B16", "category": "Flat Memory", "instructionClass": "vector", "summary": "Store 16 bits of data from a vector register into the flat aperture.", "description": "Store 16 bits of data from a vector register into the flat aperture.", "syntax": "flat_store_b16", "operands": [], "dataTypes": [ "b16" ], "semantics": "", "example": "flat_store_b16 v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_store_b32", "mnemonic": "flat_store_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT STORE B32", "category": "Flat Memory", "instructionClass": "vector", "summary": "Store 32 bits of data from vector input registers into the flat aperture.", "description": "Store 32 bits of data from vector input registers into the flat aperture.", "syntax": "flat_store_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "flat_store_b32 v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_store_b64", "mnemonic": "flat_store_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT STORE B64", "category": "Flat Memory", "instructionClass": "vector", "summary": "Store 64 bits of data from vector input registers into the flat aperture.", "description": "Store 64 bits of data from vector input registers into the flat aperture.", "syntax": "flat_store_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "flat_store_b64 v[1:2], v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_store_b8", "mnemonic": "flat_store_b8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT STORE B8", "category": "Flat Memory", "instructionClass": "vector", "summary": "Store 8 bits of data from a vector register into the flat aperture.", "description": "Store 8 bits of data from a vector register into the flat aperture.", "syntax": "flat_store_b8", "operands": [], "dataTypes": [ "b8" ], "semantics": "", "example": "flat_store_b8 v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_store_b96", "mnemonic": "flat_store_b96", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT STORE B96", "category": "Flat Memory", "instructionClass": "vector", "summary": "Store 96 bits of data from vector input registers into the flat aperture.", "description": "Store 96 bits of data from vector input registers into the flat aperture.", "syntax": "flat_store_b96", "operands": [], "dataTypes": [], "semantics": "", "example": "flat_store_b96 v[1:2], v[2:4]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_store_byte", "mnemonic": "flat_store_byte", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT STORE BYTE", "category": "Flat Memory", "instructionClass": "vector", "summary": "Store 8 bits of data from a vector register into the flat aperture.", "description": "Store 8 bits of data from a vector register into the flat aperture.", "syntax": "flat_store_byte", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\nMEM[addr].b8 = VDATA[7 : 0]", "example": "flat_store_byte v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 484, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_store_byte_d16_hi", "mnemonic": "flat_store_byte_d16_hi", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT STORE BYTE D16 HI", "category": "Flat Memory", "instructionClass": "vector", "summary": "Store 8 bits of data from the high 16 bits of a 32-bit vector register into the flat aperture.", "description": "Store 8 bits of data from the high 16 bits of a 32-bit vector register into the flat aperture.", "syntax": "flat_store_byte_d16_hi", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\nMEM[addr].b8 = VDATA[23 : 16]", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 484, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.flat_store_d16_hi_b16", "mnemonic": "flat_store_d16_hi_b16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT STORE D16 HI B16", "category": "Flat Memory", "instructionClass": "vector", "summary": "Store 16 bits of data from the high 16 bits of a 32-bit vector register into the flat aperture.", "description": "Store 16 bits of data from the high 16 bits of a 32-bit vector register into the flat aperture.", "syntax": "flat_store_d16_hi_b16", "operands": [], "dataTypes": [ "b16" ], "semantics": "", "example": "flat_store_d16_hi_b16 v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_store_d16_hi_b8", "mnemonic": "flat_store_d16_hi_b8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT STORE D16 HI B8", "category": "Flat Memory", "instructionClass": "vector", "summary": "Store 8 bits of data from the high 16 bits of a 32-bit vector register into the flat aperture.", "description": "Store 8 bits of data from the high 16 bits of a 32-bit vector register into the flat aperture.", "syntax": "flat_store_d16_hi_b8", "operands": [], "dataTypes": [ "b8" ], "semantics": "", "example": "flat_store_d16_hi_b8 v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_store_dword", "mnemonic": "flat_store_dword", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT STORE DWORD", "category": "Flat Memory", "instructionClass": "vector", "summary": "Store 32 bits of data from vector input registers into the flat aperture.", "description": "Store 32 bits of data from vector input registers into the flat aperture.", "syntax": "flat_store_dword", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\nMEM[addr].b32 = VDATA[31 : 0]", "example": "flat_store_dword v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 485, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_store_dwordx2", "mnemonic": "flat_store_dwordx2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT STORE DWORDX2", "category": "Flat Memory", "instructionClass": "vector", "summary": "Store 64 bits of data from vector input registers into the flat aperture.", "description": "Store 64 bits of data from vector input registers into the flat aperture.", "syntax": "flat_store_dwordx2", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\nMEM[addr].b32 = VDATA[31 : 0];\nMEM[addr + 4U].b32 = VDATA[63 : 32]", "example": "flat_store_dwordx2 v[1:2], v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 485, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_store_dwordx3", "mnemonic": "flat_store_dwordx3", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT STORE DWORDX3", "category": "Flat Memory", "instructionClass": "vector", "summary": "Store 96 bits of data from vector input registers into the flat aperture.", "description": "Store 96 bits of data from vector input registers into the flat aperture.", "syntax": "flat_store_dwordx3", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\nMEM[addr].b32 = VDATA[31 : 0];\nMEM[addr + 4U].b32 = VDATA[63 : 32];\nMEM[addr + 8U].b32 = VDATA[95 : 64]", "example": "flat_store_dwordx3 v[1:2], v[2:4]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 485, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_store_dwordx4", "mnemonic": "flat_store_dwordx4", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT STORE DWORDX4", "category": "Flat Memory", "instructionClass": "vector", "summary": "Store 128 bits of data from vector input registers into the flat aperture.", "description": "Store 128 bits of data from vector input registers into the flat aperture.", "syntax": "flat_store_dwordx4", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\nMEM[addr].b32 = VDATA[31 : 0];\nMEM[addr + 4U].b32 = VDATA[63 : 32];\nMEM[addr + 8U].b32 = VDATA[95 : 64];\nMEM[addr + 12U].b32 = VDATA[127 : 96]", "example": "flat_store_dwordx4 v[1:2], v[2:5]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 485, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_store_short", "mnemonic": "flat_store_short", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT STORE SHORT", "category": "Flat Memory", "instructionClass": "vector", "summary": "Store 16 bits of data from a vector register into the flat aperture.", "description": "Store 16 bits of data from a vector register into the flat aperture.", "syntax": "flat_store_short", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\nMEM[addr].b16 = VDATA[15 : 0]", "example": "flat_store_short v[1:2], v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 484, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.flat_store_short_d16_hi", "mnemonic": "flat_store_short_d16_hi", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "FLAT STORE SHORT D16 HI", "category": "Flat Memory", "instructionClass": "vector", "summary": "Store 16 bits of data from the high 16 bits of a 32-bit vector register into the flat aperture.", "description": "Store 16 bits of data from the high 16 bits of a 32-bit vector register into the flat aperture.", "syntax": "flat_store_short_d16_hi", "operands": [], "dataTypes": [], "semantics": "addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);\nMEM[addr].b16 = VDATA[31 : 16]", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 484, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.global_atomic_add", "mnemonic": "global_atomic_add", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC ADD", "category": "Atomics", "instructionClass": "vector", "summary": "Atomically add a per-lane value to a global-memory location.", "description": "Add two unsigned 32-bit integer values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the SC0 bit is set.", "syntax": "global_atomic_add VDST, VADDR, VDATA, SADDR", "operands": [ { "name": "VDST", "desc": "Optional destination VGPR (previous value)" }, { "name": "VADDR", "desc": "Per-lane 64-bit address" }, { "name": "VDATA", "desc": "Per-lane value to add" }, { "name": "SADDR", "desc": "Optional uniform base" } ], "dataTypes": [], "semantics": "old = *(VADDR[lane] + SADDR + offset); *(...) = old + VDATA[lane]; indivisible with respect to other lanes/waves targeting the same address. VDST optionally receives old.", "example": "global_atomic_add v2, v[0:1], v2, off // *(v[0:1]) += v2 per lane, v2 <- old value", "exampleSource": null, "encoding": { "format": "GLOBAL", "widthBits": 32 }, "executionUnit": "Vector Memory Unit", "registerClasses": [ "VGPR", "SGPR" ], "memorySegment": "global", "supportedTargets": [ "gfx942", "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "amd-machine-readable-isa" ] }, { "id": "amdgpu.global_atomic_add_f64", "mnemonic": "global_atomic_add_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC ADD F64", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Add a double-precision float value in the data register to a location in the global aperture.", "description": "Add a double-precision float value in the data register to a location in the global aperture. Store the original value from global aperture into a vector register iff the SC0 bit is set.", "syntax": "global_atomic_add_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "tmp = MEM[ADDR].f64;\nMEM[ADDR].f64 += DATA.f64;\nRETURN_DATA = tmp", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx942" ], "unsupportedTargets": [], "architecturalNotes": "Floating-point addition handles NAN/INF/denorm.", "sourcePdfPage": 512, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.global_atomic_add_x2", "mnemonic": "global_atomic_add_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC ADD X2", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Add two unsigned 64-bit integer values stored in the data register and a location in the global aperture.", "description": "Add two unsigned 64-bit integer values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the SC0 bit is set.", "syntax": "global_atomic_add_x2", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\ntmp = MEM[addr].u64;\nMEM[addr].u64 += DATA.u64;\nRETURN_DATA.u64 = tmp", "example": "global_atomic_add_x2 v1, v[2:3], vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 514, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_atomic_and", "mnemonic": "global_atomic_and", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC AND", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in the global aperture.", "description": "Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the SC0 bit is set.", "syntax": "global_atomic_and", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\ntmp = MEM[addr].b32;\nMEM[addr].b32 = (tmp & DATA.b32);\nRETURN_DATA.b32 = tmp", "example": "global_atomic_and v1, v2, vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 510, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_atomic_and_x2", "mnemonic": "global_atomic_and_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC AND X2", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Calculate bitwise AND given two unsigned 64-bit integer values stored in the data register and a location in the global aperture.", "description": "Calculate bitwise AND given two unsigned 64-bit integer values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the SC0 bit is set.", "syntax": "global_atomic_and_x2", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\ntmp = MEM[addr].b64;\nMEM[addr].b64 = (tmp & DATA.b64);\nRETURN_DATA.b64 = tmp", "example": "global_atomic_and_x2 v1, v[2:3], vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 516, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_atomic_cmpswap", "mnemonic": "global_atomic_cmpswap", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC CMPSWAP", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Compare two unsigned 32-bit integer values stored in the data comparison register and a location in the global aperture.", "description": "Compare two unsigned 32-bit integer values stored in the data comparison register and a location in the global aperture. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from global aperture into a vector register iff the SC0 bit is set.", "syntax": "global_atomic_cmpswap", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\ntmp = MEM[addr].u32;\nsrc = DATA[31 : 0].u32;\ncmp = DATA[63 : 32].u32;\nMEM[addr].u32 = tmp == cmp ? src : tmp;\nRETURN_DATA.u32 = tmp", "example": "global_atomic_cmpswap v1, v[2:3], vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 508, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_atomic_cmpswap_x2", "mnemonic": "global_atomic_cmpswap_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC CMPSWAP X2", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Compare two unsigned 64-bit integer values stored in the data comparison register and a location in the global aperture.", "description": "Compare two unsigned 64-bit integer values stored in the data comparison register and a location in the global aperture. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from global aperture into a vector register iff the SC0 bit is set.", "syntax": "global_atomic_cmpswap_x2", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\ntmp = MEM[addr].u64;\nsrc = DATA[63 : 0].u64;\ncmp = DATA[127 : 64].u64;\nMEM[addr].u64 = tmp == cmp ? src : tmp;\nRETURN_DATA.u64 = tmp", "example": "global_atomic_cmpswap_x2 v1, v[2:5], vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 514, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_atomic_cond_sub_u32", "mnemonic": "global_atomic_cond_sub_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC COND SUB U32", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Subtract an unsigned 32-bit integer value in the data register from a location in the global aperture only if the memory value is greater than or…", "description": "Subtract an unsigned 32-bit integer value in the data register from a location in the global aperture only if the memory value is greater than or equal to the data register value. Store the original value from global aperture into a vector register iff the temporal hint enables atomic return.", "syntax": "global_atomic_cond_sub_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.global_atomic_csub", "mnemonic": "global_atomic_csub", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC CSUB", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Subtract an unsigned 32-bit integer location in the global aperture from a value in the data register and clamp the result to zero.", "description": "Subtract an unsigned 32-bit integer location in the global aperture from a value in the data register and clamp the result to zero. Store the original value from global aperture into a vector register iff the GLC bit is set.", "syntax": "global_atomic_csub", "operands": [], "dataTypes": [], "semantics": "", "example": "global_atomic_csub v[1:2], v2, off", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_atomic_dec", "mnemonic": "global_atomic_dec", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC DEC", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Decrement an unsigned 32-bit integer value from a location in the global aperture with wraparound to a value in the data register if the decrement…", "description": "Decrement an unsigned 32-bit integer value from a location in the global aperture with wraparound to a value in the data register if the decrement yields a negative value. Store the original value from global aperture into a vector register iff the SC0 bit is set.", "syntax": "global_atomic_dec", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\ntmp = MEM[addr].u32;\nsrc = DATA.u32;\nMEM[addr].u32 = ((tmp == 0U) || (tmp > src)) ? src : tmp - 1U;\nRETURN_DATA.u32 = tmp", "example": "global_atomic_dec v1, v2, vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 511, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_atomic_dec_x2", "mnemonic": "global_atomic_dec_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC DEC X2", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Decrement an unsigned 64-bit integer value from a location in the global aperture with wraparound to a value in the data register if the decrement…", "description": "Decrement an unsigned 64-bit integer value from a location in the global aperture with wraparound to a value in the data register if the decrement yields a negative value. Store the original value from global aperture into a vector register iff the SC0 bit is set.", "syntax": "global_atomic_dec_x2", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\ntmp = MEM[addr].u64;\nsrc = DATA.u64;\nMEM[addr].u64 = ((tmp == 0ULL) || (tmp > src)) ? src : tmp - 1ULL;\nRETURN_DATA.u64 = tmp", "example": "global_atomic_dec_x2 v1, v[2:3], vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 517, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_atomic_fmax_x2", "mnemonic": "global_atomic_fmax_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC FMAX X2", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Select the maximum of two double-precision float inputs, given two values stored in the data register and a location in the global aperture.", "description": "Select the maximum of two double-precision float inputs, given two values stored in the data register and a location in the global aperture. Update the global aperture with the selected value. Store the original value from global aperture into a vector register iff the GLC bit is set.", "syntax": "global_atomic_fmax_x2", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.global_atomic_fmin_x2", "mnemonic": "global_atomic_fmin_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC FMIN X2", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in the global aperture.", "description": "Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in the global aperture. Update the global aperture with the selected value. Store the original value from global aperture into a vector register iff the GLC bit is set.", "syntax": "global_atomic_fmin_x2", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.global_atomic_inc", "mnemonic": "global_atomic_inc", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC INC", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Increment an unsigned 32-bit integer value from a location in the global aperture with wraparound to 0 if the value exceeds a value in the data…", "description": "Increment an unsigned 32-bit integer value from a location in the global aperture with wraparound to 0 if the value exceeds a value in the data register. Store the original value from global aperture into a vector register iff the SC0 bit is set.", "syntax": "global_atomic_inc", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\ntmp = MEM[addr].u32;\nsrc = DATA.u32;\nMEM[addr].u32 = tmp >= src ? 0U : tmp + 1U;\nRETURN_DATA.u32 = tmp", "example": "global_atomic_inc v1, v2, vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 511, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_atomic_inc_x2", "mnemonic": "global_atomic_inc_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC INC X2", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Increment an unsigned 64-bit integer value from a location in the global aperture with wraparound to 0 if the value exceeds a value in the data…", "description": "Increment an unsigned 64-bit integer value from a location in the global aperture with wraparound to 0 if the value exceeds a value in the data register. Store the original value from global aperture into a vector register iff the SC0 bit is set.", "syntax": "global_atomic_inc_x2", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\ntmp = MEM[addr].u64;\nsrc = DATA.u64;\nMEM[addr].u64 = tmp >= src ? 0ULL : tmp + 1ULL;\nRETURN_DATA.u64 = tmp", "example": "global_atomic_inc_x2 v1, v[2:3], vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 516, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_atomic_max_f64", "mnemonic": "global_atomic_max_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC MAX F64", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Select the maximum of two double-precision float inputs, given two values stored in the data register and a location in the global aperture.", "description": "Select the maximum of two double-precision float inputs, given two values stored in the data register and a location in the global aperture. Update the global aperture with the selected value. Store the original value from global aperture into a vector register iff the SC0 bit is set.", "syntax": "global_atomic_max_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\ntmp = MEM[addr].f64;\nsrc = DATA.f64;\nMEM[addr].f64 = src > tmp ? src : tmp;\nRETURN_DATA.f64 = tmp", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx942" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 513, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.global_atomic_min_f64", "mnemonic": "global_atomic_min_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC MIN F64", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in the global aperture.", "description": "Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in the global aperture. Update the global aperture with the selected value. Store the original value from global aperture into a vector register iff the SC0 bit is set.", "syntax": "global_atomic_min_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\ntmp = MEM[addr].f64;\nsrc = DATA.f64;\nMEM[addr].f64 = src < tmp ? src : tmp;\nRETURN_DATA.f64 = tmp", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx942" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 513, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.global_atomic_or", "mnemonic": "global_atomic_or", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC OR", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Calculate bitwise OR given two unsigned 32-bit integer values stored in the data register and a location in the global aperture.", "description": "Calculate bitwise OR given two unsigned 32-bit integer values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the SC0 bit is set.", "syntax": "global_atomic_or", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\ntmp = MEM[addr].b32;\nMEM[addr].b32 = (tmp | DATA.b32);\nRETURN_DATA.b32 = tmp", "example": "global_atomic_or v1, v2, vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 511, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_atomic_or_x2", "mnemonic": "global_atomic_or_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC OR X2", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Calculate bitwise OR given two unsigned 64-bit integer values stored in the data register and a location in the global aperture.", "description": "Calculate bitwise OR given two unsigned 64-bit integer values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the SC0 bit is set.", "syntax": "global_atomic_or_x2", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\ntmp = MEM[addr].b64;\nMEM[addr].b64 = (tmp | DATA.b64);\nRETURN_DATA.b64 = tmp", "example": "global_atomic_or_x2 v1, v[2:3], vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 516, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_atomic_ordered_add_b64", "mnemonic": "global_atomic_ordered_add_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC ORDERED ADD B64", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Given an (ID, value) pair in memory, increment the value by a given amount if the ID matches an ID provided by the shader.", "description": "Given an (ID, value) pair in memory, increment the value by a given amount if the ID matches an ID provided by the shader.", "syntax": "global_atomic_ordered_add_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.global_atomic_pk_add_bf16", "mnemonic": "global_atomic_pk_add_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC PK ADD BF16", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Add a packed 2-component BF16 float value in the data register to a location in the global aperture.", "description": "Add a packed 2-component BF16 float value in the data register to a location in the global aperture. Store the original value from global aperture into a vector register iff the SC0 bit is set.", "syntax": "global_atomic_pk_add_bf16", "operands": [], "dataTypes": [], "semantics": "tmp = MEM[ADDR];\nsrc = DATA;\ndst[31 : 16].bf16 = tmp[31 : 16].bf16 + src[31 : 16].bf16;\ndst[15 : 0].bf16 = tmp[15 : 0].bf16 + src[15 : 0].bf16;\nMEM[ADDR] = dst.b32;\nRETURN_DATA = tmp", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "Floating-point addition handles NAN/INF/denorm.", "sourcePdfPage": 513, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.global_atomic_smax", "mnemonic": "global_atomic_smax", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC SMAX", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Select the maximum of two signed 32-bit integer inputs, given two values stored in the data register and a location in the global aperture.", "description": "Select the maximum of two signed 32-bit integer inputs, given two values stored in the data register and a location in the global aperture. Update the global aperture with the selected value. Store the original value from global aperture into a vector register iff the SC0 bit is set.", "syntax": "global_atomic_smax", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\ntmp = MEM[addr].i32;\nsrc = DATA.i32;\nMEM[addr].i32 = src >= tmp ? src : tmp;\nRETURN_DATA.i32 = tmp", "example": "global_atomic_smax v1, v2, vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 510, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_atomic_smax_x2", "mnemonic": "global_atomic_smax_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC SMAX X2", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Select the maximum of two signed 64-bit integer inputs, given two values stored in the data register and a location in the global aperture.", "description": "Select the maximum of two signed 64-bit integer inputs, given two values stored in the data register and a location in the global aperture. Update the global aperture with the selected value. Store the original value from global aperture into a vector register iff the SC0 bit is set.", "syntax": "global_atomic_smax_x2", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\ntmp = MEM[addr].i64;\nsrc = DATA.i64;\nMEM[addr].i64 = src >= tmp ? src : tmp;\nRETURN_DATA.i64 = tmp", "example": "global_atomic_smax_x2 v1, v[2:3], vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 515, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_atomic_smin", "mnemonic": "global_atomic_smin", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC SMIN", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Select the minimum of two signed 32-bit integer inputs, given two values stored in the data register and a location in the global aperture.", "description": "Select the minimum of two signed 32-bit integer inputs, given two values stored in the data register and a location in the global aperture. Update the global aperture with the selected value. Store the original value from global aperture into a vector register iff the SC0 bit is set.", "syntax": "global_atomic_smin", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\ntmp = MEM[addr].i32;\nsrc = DATA.i32;\nMEM[addr].i32 = src < tmp ? src : tmp;\nRETURN_DATA.i32 = tmp", "example": "global_atomic_smin v1, v2, vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 509, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_atomic_smin_x2", "mnemonic": "global_atomic_smin_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC SMIN X2", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Select the minimum of two signed 64-bit integer inputs, given two values stored in the data register and a location in the global aperture.", "description": "Select the minimum of two signed 64-bit integer inputs, given two values stored in the data register and a location in the global aperture. Update the global aperture with the selected value. Store the original value from global aperture into a vector register iff the SC0 bit is set.", "syntax": "global_atomic_smin_x2", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\ntmp = MEM[addr].i64;\nsrc = DATA.i64;\nMEM[addr].i64 = src < tmp ? src : tmp;\nRETURN_DATA.i64 = tmp", "example": "global_atomic_smin_x2 v1, v[2:3], vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 515, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_atomic_sub", "mnemonic": "global_atomic_sub", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC SUB", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Subtract an unsigned 32-bit integer value stored in the data register from a value stored in a location in the global aperture.", "description": "Subtract an unsigned 32-bit integer value stored in the data register from a value stored in a location in the global aperture. Store the original value from global aperture into a vector register iff the SC0 bit is set.", "syntax": "global_atomic_sub", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\ntmp = MEM[addr].u32;\nMEM[addr].u32 -= DATA.u32;\nRETURN_DATA.u32 = tmp", "example": "global_atomic_sub v1, v2, vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 509, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_atomic_sub_x2", "mnemonic": "global_atomic_sub_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC SUB X2", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Subtract an unsigned 64-bit integer value stored in the data register from a value stored in a location in the global aperture.", "description": "Subtract an unsigned 64-bit integer value stored in the data register from a value stored in a location in the global aperture. Store the original value from global aperture into a vector register iff the SC0 bit is set.", "syntax": "global_atomic_sub_x2", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\ntmp = MEM[addr].u64;\nMEM[addr].u64 -= DATA.u64;\nRETURN_DATA.u64 = tmp", "example": "global_atomic_sub_x2 v1, v[2:3], vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 514, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_atomic_swap", "mnemonic": "global_atomic_swap", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC SWAP", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Swap an unsigned 32-bit integer value in the data register with a location in the global aperture.", "description": "Swap an unsigned 32-bit integer value in the data register with a location in the global aperture. Store the original value from global aperture into a vector register iff the SC0 bit is set.", "syntax": "global_atomic_swap", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\ntmp = MEM[addr].b32;\nMEM[addr].b32 = DATA.b32;\nRETURN_DATA.b32 = tmp", "example": "global_atomic_swap v1, v2, vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 508, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_atomic_swap_x2", "mnemonic": "global_atomic_swap_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC SWAP X2", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Swap an unsigned 64-bit integer value in the data register with a location in the global aperture.", "description": "Swap an unsigned 64-bit integer value in the data register with a location in the global aperture. Store the original value from global aperture into a vector register iff the SC0 bit is set.", "syntax": "global_atomic_swap_x2", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\ntmp = MEM[addr].b64;\nMEM[addr].b64 = DATA.b64;\nRETURN_DATA.b64 = tmp", "example": "global_atomic_swap_x2 v1, v[2:3], vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 513, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_atomic_umax", "mnemonic": "global_atomic_umax", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC UMAX", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Select the maximum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in the global aperture.", "description": "Select the maximum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in the global aperture. Update the global aperture with the selected value. Store the original value from global aperture into a vector register iff the SC0 bit is set.", "syntax": "global_atomic_umax", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\ntmp = MEM[addr].u32;\nsrc = DATA.u32;\nMEM[addr].u32 = src >= tmp ? src : tmp;\nRETURN_DATA.u32 = tmp", "example": "global_atomic_umax v1, v2, vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 510, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_atomic_umax_x2", "mnemonic": "global_atomic_umax_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC UMAX X2", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Select the maximum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in the global aperture.", "description": "Select the maximum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in the global aperture. Update the global aperture with the selected value. Store the original value from global aperture into a vector register iff the SC0 bit is set.", "syntax": "global_atomic_umax_x2", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\ntmp = MEM[addr].u64;\nsrc = DATA.u64;\nMEM[addr].u64 = src >= tmp ? src : tmp;\nRETURN_DATA.u64 = tmp", "example": "global_atomic_umax_x2 v1, v[2:3], vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 515, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_atomic_umin", "mnemonic": "global_atomic_umin", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC UMIN", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Select the minimum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in the global aperture.", "description": "Select the minimum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in the global aperture. Update the global aperture with the selected value. Store the original value from global aperture into a vector register iff the SC0 bit is set.", "syntax": "global_atomic_umin", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\ntmp = MEM[addr].u32;\nsrc = DATA.u32;\nMEM[addr].u32 = src < tmp ? src : tmp;\nRETURN_DATA.u32 = tmp", "example": "global_atomic_umin v1, v2, vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 509, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_atomic_umin_x2", "mnemonic": "global_atomic_umin_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC UMIN X2", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Select the minimum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in the global aperture.", "description": "Select the minimum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in the global aperture. Update the global aperture with the selected value. Store the original value from global aperture into a vector register iff the SC0 bit is set.", "syntax": "global_atomic_umin_x2", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\ntmp = MEM[addr].u64;\nsrc = DATA.u64;\nMEM[addr].u64 = src < tmp ? src : tmp;\nRETURN_DATA.u64 = tmp", "example": "global_atomic_umin_x2 v1, v[2:3], vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 515, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_atomic_xor", "mnemonic": "global_atomic_xor", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC XOR", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Calculate bitwise XOR given two unsigned 32-bit integer values stored in the data register and a location in the global aperture.", "description": "Calculate bitwise XOR given two unsigned 32-bit integer values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the SC0 bit is set.", "syntax": "global_atomic_xor", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\ntmp = MEM[addr].b32;\nMEM[addr].b32 = (tmp ^ DATA.b32);\nRETURN_DATA.b32 = tmp", "example": "global_atomic_xor v1, v2, vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 511, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_atomic_xor_x2", "mnemonic": "global_atomic_xor_x2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL ATOMIC XOR X2", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Calculate bitwise XOR given two unsigned 64-bit integer values stored in the data register and a location in the global aperture.", "description": "Calculate bitwise XOR given two unsigned 64-bit integer values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the SC0 bit is set.", "syntax": "global_atomic_xor_x2", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\ntmp = MEM[addr].b64;\nMEM[addr].b64 = (tmp ^ DATA.b64);\nRETURN_DATA.b64 = tmp", "example": "global_atomic_xor_x2 v1, v[2:3], vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 516, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_inv", "mnemonic": "global_inv", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL INV", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Invalidate cache lines based on the SCOPE field. Increments/decrements LOAD_CNT.", "description": "Invalidate cache lines based on the SCOPE field. Increments/decrements LOAD_CNT.", "syntax": "global_inv", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.global_load_async_to_lds_b128", "mnemonic": "global_load_async_to_lds_b128", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD ASYNC TO LDS B128", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "AMDGPU GLOBAL vector instruction operating on b128 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "global_load_async_to_lds_b128", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.global_load_async_to_lds_b32", "mnemonic": "global_load_async_to_lds_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD ASYNC TO LDS B32", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "AMDGPU GLOBAL vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "global_load_async_to_lds_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.global_load_async_to_lds_b64", "mnemonic": "global_load_async_to_lds_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD ASYNC TO LDS B64", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "AMDGPU GLOBAL vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "global_load_async_to_lds_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.global_load_async_to_lds_b8", "mnemonic": "global_load_async_to_lds_b8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD ASYNC TO LDS B8", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "AMDGPU GLOBAL vector instruction operating on b8 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "global_load_async_to_lds_b8", "operands": [], "dataTypes": [ "b8" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.global_load_block", "mnemonic": "global_load_block", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD BLOCK", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Load a block of data from the global aperture.", "description": "Load a block of data from the global aperture.", "syntax": "global_load_block", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.global_load_dword", "mnemonic": "global_load_dword", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD DWORD", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Load one 32-bit dword per lane from the global address space using a 64-bit per-lane address.", "description": "Load 32 bits of data from the global aperture into a vector register.", "syntax": "global_load_dword VDST, VADDR, SADDR, offset", "operands": [ { "name": "VDST", "desc": "Destination VGPR" }, { "name": "VADDR", "desc": "Per-lane 64-bit address (VGPR pair)" }, { "name": "SADDR", "desc": "Optional uniform base (SGPR pair)" }, { "name": "offset", "desc": "Immediate offset" } ], "dataTypes": [], "semantics": "VDST[lane] = *(VADDR[lane] + SADDR + offset) for each active lane.", "example": "global_load_dword v2, v[0:1], off // v2 = *(v[0:1]) per lane", "exampleSource": null, "encoding": { "format": "GLOBAL", "widthBits": 32 }, "executionUnit": "Vector Memory Unit", "registerClasses": [ "VGPR", "SGPR" ], "memorySegment": "global", "supportedTargets": [ "gfx942", "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "amd-machine-readable-isa" ] }, { "id": "amdgpu.global_load_dword_addtid", "mnemonic": "global_load_dword_addtid", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD DWORD ADDTID", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Load 32 bits of data from the global aperture into a vector register.", "description": "Load 32 bits of data from the global aperture into a vector register. The memory base address is provided in a scalar register and the lane ID is used as an offset.", "syntax": "global_load_dword_addtid", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.global_load_dwordx2", "mnemonic": "global_load_dwordx2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD DWORDX2", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Load 64 bits of data from the global aperture into a vector register.", "description": "Load 64 bits of data from the global aperture into a vector register.", "syntax": "global_load_dwordx2", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nVDATA[31 : 0] = MEM[addr].b32;\nVDATA[63 : 32] = MEM[addr + 4U].b32", "example": "global_load_dwordx2 v[5:6], v1, vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 504, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_load_dwordx3", "mnemonic": "global_load_dwordx3", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD DWORDX3", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Load 96 bits of data from the global aperture into a vector register.", "description": "Load 96 bits of data from the global aperture into a vector register.", "syntax": "global_load_dwordx3", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nVDATA[31 : 0] = MEM[addr].b32;\nVDATA[63 : 32] = MEM[addr + 4U].b32;\nVDATA[95 : 64] = MEM[addr + 8U].b32", "example": "global_load_dwordx3 v[5:7], v1, vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 504, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_load_dwordx4", "mnemonic": "global_load_dwordx4", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD DWORDX4", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Load 128 bits of data from the global aperture into a vector register.", "description": "Load 128 bits of data from the global aperture into a vector register.", "syntax": "global_load_dwordx4", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nVDATA[31 : 0] = MEM[addr].b32;\nVDATA[63 : 32] = MEM[addr + 4U].b32;\nVDATA[95 : 64] = MEM[addr + 8U].b32;\nVDATA[127 : 96] = MEM[addr + 12U].b32", "example": "global_load_dwordx4 v[5:8], v1, vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 504, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_load_lds_dword", "mnemonic": "global_load_lds_dword", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD LDS DWORD", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Load 32 bits of untyped data from the global aperture and store the result into a data share.", "description": "Load 32 bits of untyped data from the global aperture and store the result into a data share.", "syntax": "global_load_lds_dword", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 508, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.global_load_lds_dwordx3", "mnemonic": "global_load_lds_dwordx3", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD LDS DWORDX3", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Untyped buffer load 3 dwords, store result into data share.", "description": "Untyped buffer load 3 dwords, store result into data share.", "syntax": "global_load_lds_dwordx3", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.global_load_lds_dwordx4", "mnemonic": "global_load_lds_dwordx4", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD LDS DWORDX4", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Untyped buffer load 4 dwords, store result into data share.", "description": "Untyped buffer load 4 dwords, store result into data share.", "syntax": "global_load_lds_dwordx4", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.global_load_lds_sbyte", "mnemonic": "global_load_lds_sbyte", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD LDS SBYTE", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Load 8 bits of untyped data from the global aperture, sign extend to 32 bits and store the result into a data share.", "description": "Load 8 bits of untyped data from the global aperture, sign extend to 32 bits and store the result into a data share.", "syntax": "global_load_lds_sbyte", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 508, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.global_load_lds_sshort", "mnemonic": "global_load_lds_sshort", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD LDS SSHORT", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Load 16 bits of untyped data from the global aperture, sign extend to 32 bits and store the result into a data share.", "description": "Load 16 bits of untyped data from the global aperture, sign extend to 32 bits and store the result into a data share.", "syntax": "global_load_lds_sshort", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 508, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.global_load_lds_ubyte", "mnemonic": "global_load_lds_ubyte", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD LDS UBYTE", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Load 8 bits of untyped data from the global aperture, zero extend to 32 bits and store the result into a data share.", "description": "Load 8 bits of untyped data from the global aperture, zero extend to 32 bits and store the result into a data share.", "syntax": "global_load_lds_ubyte", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 507, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.global_load_lds_ushort", "mnemonic": "global_load_lds_ushort", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD LDS USHORT", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Load 16 bits of untyped data from the global aperture, zero extend to 32 bits and store the result into a data share.", "description": "Load 16 bits of untyped data from the global aperture, zero extend to 32 bits and store the result into a data share.", "syntax": "global_load_lds_ushort", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 508, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.global_load_monitor_b128", "mnemonic": "global_load_monitor_b128", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD MONITOR B128", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "AMDGPU GLOBAL vector instruction operating on b128 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "global_load_monitor_b128", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.global_load_monitor_b32", "mnemonic": "global_load_monitor_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD MONITOR B32", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "AMDGPU GLOBAL vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "global_load_monitor_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.global_load_monitor_b64", "mnemonic": "global_load_monitor_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD MONITOR B64", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "AMDGPU GLOBAL vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "global_load_monitor_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.global_load_sbyte", "mnemonic": "global_load_sbyte", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD SBYTE", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Load 8 bits of signed data from the global aperture, sign extend to 32 bits and store the result into a vector register.", "description": "Load 8 bits of signed data from the global aperture, sign extend to 32 bits and store the result into a vector register.", "syntax": "global_load_sbyte", "operands": [], "dataTypes": [], "semantics": "", "example": "global_load_sbyte v5, v1, vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_load_sbyte_d16", "mnemonic": "global_load_sbyte_d16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD SBYTE D16", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Load 8 bits of signed data from the global aperture, sign extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register.", "description": "Load 8 bits of signed data from the global aperture, sign extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register.", "syntax": "global_load_sbyte_d16", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nVDATA[15 : 0].i16 = 16'I(signext(MEM[addr].i8));\n// VDATA[31:16] is preserved.", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 506, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.global_load_sbyte_d16_hi", "mnemonic": "global_load_sbyte_d16_hi", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD SBYTE D16 HI", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Load 8 bits of signed data from the global aperture, sign extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register.", "description": "Load 8 bits of signed data from the global aperture, sign extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register.", "syntax": "global_load_sbyte_d16_hi", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nVDATA[31 : 16].i16 = 16'I(signext(MEM[addr].i8));\n// VDATA[15:0] is preserved.", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 507, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.global_load_short_d16", "mnemonic": "global_load_short_d16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD SHORT D16", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Load 16 bits of unsigned data from the global aperture and store the result into the low 16 bits of a 32-bit vector register.", "description": "Load 16 bits of unsigned data from the global aperture and store the result into the low 16 bits of a 32-bit vector register.", "syntax": "global_load_short_d16", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nVDATA[15 : 0].b16 = MEM[addr].b16;\n// VDATA[31:16] is preserved.", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 507, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.global_load_short_d16_hi", "mnemonic": "global_load_short_d16_hi", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD SHORT D16 HI", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Load 16 bits of unsigned data from the global aperture and store the result into the high 16 bits of a 32-bit vector register.", "description": "Load 16 bits of unsigned data from the global aperture and store the result into the high 16 bits of a 32-bit vector register.", "syntax": "global_load_short_d16_hi", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nVDATA[31 : 16].b16 = MEM[addr].b16;\n// VDATA[15:0] is preserved.", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 507, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.global_load_sshort", "mnemonic": "global_load_sshort", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD SSHORT", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Load 16 bits of signed data from the global aperture, sign extend to 32 bits and store the result into a vector register.", "description": "Load 16 bits of signed data from the global aperture, sign extend to 32 bits and store the result into a vector register.", "syntax": "global_load_sshort", "operands": [], "dataTypes": [], "semantics": "", "example": "global_load_sshort v5, v1, vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_load_tr4_b64", "mnemonic": "global_load_tr4_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD TR4 B64", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "AMDGPU GLOBAL vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "global_load_tr4_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.global_load_tr6_b96", "mnemonic": "global_load_tr6_b96", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD TR6 B96", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "AMDGPU GLOBAL vector instruction operating on b96 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "global_load_tr6_b96", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.global_load_tr_b128", "mnemonic": "global_load_tr_b128", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD TR B128", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Load a 16x16 matrix of 16-bit data from the global aperture, transpose data between row-major and column-major order, and store the result into a…", "description": "Load a 16x16 matrix of 16-bit data from the global aperture, transpose data between row-major and column-major order, and store the result into a 128-bit vector register.", "syntax": "global_load_tr_b128", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.global_load_tr_b128_w64", "mnemonic": "global_load_tr_b128_w64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD TR B128 W64", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "AMDGPU GLOBAL vector instruction operating on b128 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "global_load_tr_b128_w64", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.global_load_tr_b64", "mnemonic": "global_load_tr_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD TR B64", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Load a 16x16 matrix of 8-bit data from the global aperture, transpose data between row-major and column-major order, and store the result into a…", "description": "Load a 16x16 matrix of 8-bit data from the global aperture, transpose data between row-major and column-major order, and store the result into a 64-bit vector register.", "syntax": "global_load_tr_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.global_load_tr_b64_w64", "mnemonic": "global_load_tr_b64_w64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD TR B64 W64", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "AMDGPU GLOBAL vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "global_load_tr_b64_w64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.global_load_ubyte", "mnemonic": "global_load_ubyte", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD UBYTE", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Load 8 bits of unsigned data from the global aperture, zero extend to 32 bits and store the result into a vector register.", "description": "Load 8 bits of unsigned data from the global aperture, zero extend to 32 bits and store the result into a vector register.", "syntax": "global_load_ubyte", "operands": [], "dataTypes": [], "semantics": "", "example": "global_load_ubyte v5, v1, vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_load_ubyte_d16", "mnemonic": "global_load_ubyte_d16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD UBYTE D16", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Load 8 bits of unsigned data from the global aperture, zero extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register.", "description": "Load 8 bits of unsigned data from the global aperture, zero extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register.", "syntax": "global_load_ubyte_d16", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nVDATA[15 : 0].u16 = 16'U({ 8'0U, MEM[addr].u8 });\n// VDATA[31:16] is preserved.", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 506, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.global_load_ubyte_d16_hi", "mnemonic": "global_load_ubyte_d16_hi", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD UBYTE D16 HI", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Load 8 bits of unsigned data from the global aperture, zero extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register.", "description": "Load 8 bits of unsigned data from the global aperture, zero extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register.", "syntax": "global_load_ubyte_d16_hi", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nVDATA[31 : 16].u16 = 16'U({ 8'0U, MEM[addr].u8 });\n// VDATA[15:0] is preserved.", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 506, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.global_load_ushort", "mnemonic": "global_load_ushort", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL LOAD USHORT", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Load 16 bits of unsigned data from the global aperture, zero extend to 32 bits and store the result into a vector register.", "description": "Load 16 bits of unsigned data from the global aperture, zero extend to 32 bits and store the result into a vector register.", "syntax": "global_load_ushort", "operands": [], "dataTypes": [], "semantics": "", "example": "global_load_ushort v5, v1, vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_prefetch_b8", "mnemonic": "global_prefetch_b8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL PREFETCH B8", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "AMDGPU GLOBAL vector instruction operating on b8 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "global_prefetch_b8", "operands": [], "dataTypes": [ "b8" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.global_store_async_from_lds_b128", "mnemonic": "global_store_async_from_lds_b128", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL STORE ASYNC FROM LDS B128", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "AMDGPU GLOBAL vector instruction operating on b128 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "global_store_async_from_lds_b128", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.global_store_async_from_lds_b32", "mnemonic": "global_store_async_from_lds_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL STORE ASYNC FROM LDS B32", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "AMDGPU GLOBAL vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "global_store_async_from_lds_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.global_store_async_from_lds_b64", "mnemonic": "global_store_async_from_lds_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL STORE ASYNC FROM LDS B64", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "AMDGPU GLOBAL vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "global_store_async_from_lds_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.global_store_async_from_lds_b8", "mnemonic": "global_store_async_from_lds_b8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL STORE ASYNC FROM LDS B8", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "AMDGPU GLOBAL vector instruction operating on b8 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "global_store_async_from_lds_b8", "operands": [], "dataTypes": [ "b8" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.global_store_block", "mnemonic": "global_store_block", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL STORE BLOCK", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Store a block of data to the global aperture.", "description": "Store a block of data to the global aperture.", "syntax": "global_store_block", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.global_store_byte", "mnemonic": "global_store_byte", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL STORE BYTE", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Store 8 bits of data from a vector register into the global aperture.", "description": "Store 8 bits of data from a vector register into the global aperture.", "syntax": "global_store_byte", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nMEM[addr].b8 = VDATA[7 : 0]", "example": "global_store_byte v1, v2, vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 504, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_store_byte_d16_hi", "mnemonic": "global_store_byte_d16_hi", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL STORE BYTE D16 HI", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Store 8 bits of data from the high 16 bits of a 32-bit vector register into the global aperture.", "description": "Store 8 bits of data from the high 16 bits of a 32-bit vector register into the global aperture.", "syntax": "global_store_byte_d16_hi", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nMEM[addr].b8 = VDATA[23 : 16]", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 505, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.global_store_dword", "mnemonic": "global_store_dword", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL STORE DWORD", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Store one 32-bit dword per lane to the global address space using a 64-bit per-lane address.", "description": "Store 32 bits of data from vector input registers into the global aperture.", "syntax": "global_store_dword VADDR, VDATA, SADDR, offset", "operands": [ { "name": "VADDR", "desc": "Per-lane 64-bit address (VGPR pair)" }, { "name": "VDATA", "desc": "Per-lane value to store (VGPR)" }, { "name": "SADDR", "desc": "Optional uniform base (SGPR pair)" }, { "name": "offset", "desc": "Immediate offset" } ], "dataTypes": [], "semantics": "*(VADDR[lane] + SADDR + offset) = VDATA[lane] for each active lane.", "example": "global_store_dword v[0:1], v2, off // *(v[0:1]) = v2 per lane", "exampleSource": null, "encoding": { "format": "GLOBAL", "widthBits": 32 }, "executionUnit": "Vector Memory Unit", "registerClasses": [ "VGPR", "SGPR" ], "memorySegment": "global", "supportedTargets": [ "gfx942", "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "amd-machine-readable-isa" ] }, { "id": "amdgpu.global_store_dword_addtid", "mnemonic": "global_store_dword_addtid", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL STORE DWORD ADDTID", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Store 32 bits of data from a vector input register into the global aperture.", "description": "Store 32 bits of data from a vector input register into the global aperture. The memory base address is provided as an immediate value and the lane ID is used as an offset.", "syntax": "global_store_dword_addtid", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.global_store_dwordx2", "mnemonic": "global_store_dwordx2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL STORE DWORDX2", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Store 64 bits of data from vector input registers into the global aperture.", "description": "Store 64 bits of data from vector input registers into the global aperture.", "syntax": "global_store_dwordx2", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nMEM[addr].b32 = VDATA[31 : 0];\nMEM[addr + 4U].b32 = VDATA[63 : 32]", "example": "global_store_dwordx2 v1, v[2:3], vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 505, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_store_dwordx3", "mnemonic": "global_store_dwordx3", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL STORE DWORDX3", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Store 96 bits of data from vector input registers into the global aperture.", "description": "Store 96 bits of data from vector input registers into the global aperture.", "syntax": "global_store_dwordx3", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nMEM[addr].b32 = VDATA[31 : 0];\nMEM[addr + 4U].b32 = VDATA[63 : 32];\nMEM[addr + 8U].b32 = VDATA[95 : 64]", "example": "global_store_dwordx3 v1, v[2:4], vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 506, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_store_dwordx4", "mnemonic": "global_store_dwordx4", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL STORE DWORDX4", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Store 128 bits of data from vector input registers into the global aperture.", "description": "Store 128 bits of data from vector input registers into the global aperture.", "syntax": "global_store_dwordx4", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nMEM[addr].b32 = VDATA[31 : 0];\nMEM[addr + 4U].b32 = VDATA[63 : 32];\nMEM[addr + 8U].b32 = VDATA[95 : 64];\nMEM[addr + 12U].b32 = VDATA[127 : 96]", "example": "global_store_dwordx4 v1, v[2:5], vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 506, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_store_short", "mnemonic": "global_store_short", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL STORE SHORT", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Store 16 bits of data from a vector register into the global aperture.", "description": "Store 16 bits of data from a vector register into the global aperture.", "syntax": "global_store_short", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nMEM[addr].b16 = VDATA[15 : 0]", "example": "global_store_short v1, v2, vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 505, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.global_store_short_d16_hi", "mnemonic": "global_store_short_d16_hi", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL STORE SHORT D16 HI", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Store 16 bits of data from the high 16 bits of a 32-bit vector register into the global aperture.", "description": "Store 16 bits of data from the high 16 bits of a 32-bit vector register into the global aperture.", "syntax": "global_store_short_d16_hi", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nMEM[addr].b16 = VDATA[31 : 16]", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 505, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.global_wb", "mnemonic": "global_wb", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL WB", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Write back dirty cache lines based on the SCOPE field. Increments/decrements STORE_CNT.", "description": "Write back dirty cache lines based on the SCOPE field. Increments/decrements STORE_CNT.", "syntax": "global_wb", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.global_wbinv", "mnemonic": "global_wbinv", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "GLOBAL WBINV", "category": "Vector/Global Memory", "instructionClass": "vector", "summary": "Write back and invalidate cache lines based on the SCOPE field. Increments/decrements STORE_CNT.", "description": "Write back and invalidate cache lines based on the SCOPE field. Increments/decrements STORE_CNT.", "syntax": "global_wbinv", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "GLOBAL" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.image_atomic_add", "mnemonic": "image_atomic_add", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE ATOMIC ADD", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Add two unsigned 32-bit integer values stored in the data register and a location in an image surface.", "description": "Add two unsigned 32-bit integer values stored in the data register and a location in an image surface. Store the original value from image surface into a vector register iff the GLC bit is set.", "syntax": "image_atomic_add", "operands": [], "dataTypes": [], "semantics": "", "example": "image_atomic_add v0, v[10:11], s[16:23] dmask:0x1 dim:SQ_RSRC_IMG_2D", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.image_atomic_add_flt", "mnemonic": "image_atomic_add_flt", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE ATOMIC ADD FLT", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Add two single-precision float values stored in the data register and a location in an image surface.", "description": "Add two single-precision float values stored in the data register and a location in an image surface. Store the original value from image surface into a vector register iff the temporal hint enables atomic return.", "syntax": "image_atomic_add_flt", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.image_atomic_and", "mnemonic": "image_atomic_and", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE ATOMIC AND", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in an image surface.", "description": "Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in an image surface. Store the original value from image surface into a vector register iff the GLC bit is set.", "syntax": "image_atomic_and", "operands": [], "dataTypes": [], "semantics": "", "example": "image_atomic_and v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.image_atomic_cmpswap", "mnemonic": "image_atomic_cmpswap", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE ATOMIC CMPSWAP", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Compare two unsigned 32-bit integer values stored in the data comparison register and a location in an image surface.", "description": "Compare two unsigned 32-bit integer values stored in the data comparison register and a location in an image surface. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from image surface into a vector register iff the GLC bit is set.", "syntax": "image_atomic_cmpswap", "operands": [], "dataTypes": [], "semantics": "", "example": "image_atomic_cmpswap v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.image_atomic_dec", "mnemonic": "image_atomic_dec", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE ATOMIC DEC", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Decrement an unsigned 32-bit integer value from a location in an image surface with wraparound to a value in the data register if the decrement…", "description": "Decrement an unsigned 32-bit integer value from a location in an image surface with wraparound to a value in the data register if the decrement yields a negative value. Store the original value from image surface into a vector register iff the GLC bit is set.", "syntax": "image_atomic_dec", "operands": [], "dataTypes": [], "semantics": "", "example": "image_atomic_dec v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.image_atomic_fcmpswap", "mnemonic": "image_atomic_fcmpswap", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE ATOMIC FCMPSWAP", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Compare two single-precision float values stored in the data comparison register and a location in an image surface.", "description": "Compare two single-precision float values stored in the data comparison register and a location in an image surface. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from image surface into a vector register iff the GLC bit is set.", "syntax": "image_atomic_fcmpswap", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.image_atomic_fmax", "mnemonic": "image_atomic_fmax", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE ATOMIC FMAX", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Select the maximum of two single-precision float inputs, given two values stored in the data register and a location in an image surface.", "description": "Select the maximum of two single-precision float inputs, given two values stored in the data register and a location in an image surface. Update the image surface with the selected value. Store the original value from image surface into a vector register iff the GLC bit is set.", "syntax": "image_atomic_fmax", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.image_atomic_fmin", "mnemonic": "image_atomic_fmin", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE ATOMIC FMIN", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Select the minimum of two single-precision float inputs, given two values stored in the data register and a location in an image surface.", "description": "Select the minimum of two single-precision float inputs, given two values stored in the data register and a location in an image surface. Update the image surface with the selected value. Store the original value from image surface into a vector register iff the GLC bit is set.", "syntax": "image_atomic_fmin", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.image_atomic_inc", "mnemonic": "image_atomic_inc", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE ATOMIC INC", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Increment an unsigned 32-bit integer value from a location in an image surface with wraparound to 0 if the value exceeds a value in the data register.", "description": "Increment an unsigned 32-bit integer value from a location in an image surface with wraparound to 0 if the value exceeds a value in the data register. Store the original value from image surface into a vector register iff the GLC bit is set.", "syntax": "image_atomic_inc", "operands": [], "dataTypes": [], "semantics": "", "example": "image_atomic_inc v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.image_atomic_max_flt", "mnemonic": "image_atomic_max_flt", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE ATOMIC MAX FLT", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Select the IEEE maximumNumber() of two single-precision float inputs, given two values stored in the data register and a location in an image surface.", "description": "Select the IEEE maximumNumber() of two single-precision float inputs, given two values stored in the data register and a location in an image surface. Update the image surface with the selected value. Store the original value from image surface into a vector register iff the temporal hint enables atomic return.", "syntax": "image_atomic_max_flt", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.image_atomic_max_num_flt", "mnemonic": "image_atomic_max_num_flt", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE ATOMIC MAX NUM FLT", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "AMDGPU MIMG vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "image_atomic_max_num_flt", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.image_atomic_min_flt", "mnemonic": "image_atomic_min_flt", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE ATOMIC MIN FLT", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Select the IEEE minimumNumber() of two single-precision float inputs, given two values stored in the data register and a location in an image surface.", "description": "Select the IEEE minimumNumber() of two single-precision float inputs, given two values stored in the data register and a location in an image surface. Update the image surface with the selected value. Store the original value from image surface into a vector register iff the temporal hint enables atomic return.", "syntax": "image_atomic_min_flt", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.image_atomic_min_num_flt", "mnemonic": "image_atomic_min_num_flt", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE ATOMIC MIN NUM FLT", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "AMDGPU MIMG vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "image_atomic_min_num_flt", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.image_atomic_or", "mnemonic": "image_atomic_or", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE ATOMIC OR", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Calculate bitwise OR given two unsigned 32-bit integer values stored in the data register and a location in an image surface.", "description": "Calculate bitwise OR given two unsigned 32-bit integer values stored in the data register and a location in an image surface. Store the original value from image surface into a vector register iff the GLC bit is set.", "syntax": "image_atomic_or", "operands": [], "dataTypes": [], "semantics": "", "example": "image_atomic_or v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.image_atomic_pk_add_bf16", "mnemonic": "image_atomic_pk_add_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE ATOMIC PK ADD BF16", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Add a packed 2-component BF16 float value from the data register to a location in an image surface.", "description": "Add a packed 2-component BF16 float value from the data register to a location in an image surface. Store the original value from image surface into a vector register iff the temporal hint enables atomic return.", "syntax": "image_atomic_pk_add_bf16", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.image_atomic_pk_add_f16", "mnemonic": "image_atomic_pk_add_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE ATOMIC PK ADD F16", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Add a packed 2-component half-precision float value from the data register to a location in an image surface.", "description": "Add a packed 2-component half-precision float value from the data register to a location in an image surface. Store the original value from image surface into a vector register iff the temporal hint enables atomic return.", "syntax": "image_atomic_pk_add_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.image_atomic_rsub", "mnemonic": "image_atomic_rsub", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE ATOMIC RSUB", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "AMDGPU MIMG vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "image_atomic_rsub", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.image_atomic_smax", "mnemonic": "image_atomic_smax", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE ATOMIC SMAX", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Select the maximum of two signed 32-bit integer inputs, given two values stored in the data register and a location in an image surface.", "description": "Select the maximum of two signed 32-bit integer inputs, given two values stored in the data register and a location in an image surface. Update the image surface with the selected value. Store the original value from image surface into a vector register iff the GLC bit is set.", "syntax": "image_atomic_smax", "operands": [], "dataTypes": [], "semantics": "", "example": "image_atomic_smax v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.image_atomic_smin", "mnemonic": "image_atomic_smin", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE ATOMIC SMIN", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Select the minimum of two signed 32-bit integer inputs, given two values stored in the data register and a location in an image surface.", "description": "Select the minimum of two signed 32-bit integer inputs, given two values stored in the data register and a location in an image surface. Update the image surface with the selected value. Store the original value from image surface into a vector register iff the GLC bit is set.", "syntax": "image_atomic_smin", "operands": [], "dataTypes": [], "semantics": "", "example": "image_atomic_smin v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.image_atomic_sub", "mnemonic": "image_atomic_sub", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE ATOMIC SUB", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Subtract an unsigned 32-bit integer value stored in the data register from a value stored in a location in an image surface.", "description": "Subtract an unsigned 32-bit integer value stored in the data register from a value stored in a location in an image surface. Store the original value from image surface into a vector register iff the GLC bit is set.", "syntax": "image_atomic_sub", "operands": [], "dataTypes": [], "semantics": "", "example": "image_atomic_sub v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.image_atomic_swap", "mnemonic": "image_atomic_swap", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE ATOMIC SWAP", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Swap an unsigned 32-bit integer value in the data register with a location in an image surface.", "description": "Swap an unsigned 32-bit integer value in the data register with a location in an image surface. Store the original value from image surface into a vector register iff the GLC bit is set.", "syntax": "image_atomic_swap", "operands": [], "dataTypes": [], "semantics": "", "example": "image_atomic_swap v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.image_atomic_umax", "mnemonic": "image_atomic_umax", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE ATOMIC UMAX", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Select the maximum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in an image surface.", "description": "Select the maximum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in an image surface. Update the image surface with the selected value. Store the original value from image surface into a vector register iff the GLC bit is set.", "syntax": "image_atomic_umax", "operands": [], "dataTypes": [], "semantics": "", "example": "image_atomic_umax v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.image_atomic_umin", "mnemonic": "image_atomic_umin", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE ATOMIC UMIN", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Select the minimum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in an image surface.", "description": "Select the minimum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in an image surface. Update the image surface with the selected value. Store the original value from image surface into a vector register iff the GLC bit is set.", "syntax": "image_atomic_umin", "operands": [], "dataTypes": [], "semantics": "", "example": "image_atomic_umin v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.image_atomic_xor", "mnemonic": "image_atomic_xor", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE ATOMIC XOR", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Calculate bitwise XOR given two unsigned 32-bit integer values stored in the data register and a location in an image surface.", "description": "Calculate bitwise XOR given two unsigned 32-bit integer values stored in the data register and a location in an image surface. Store the original value from image surface into a vector register iff the GLC bit is set.", "syntax": "image_atomic_xor", "operands": [], "dataTypes": [], "semantics": "", "example": "image_atomic_xor v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.image_bvh64_intersect_ray", "mnemonic": "image_bvh64_intersect_ray", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE BVH64 INTERSECT RAY", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Test the intersection of rays with either box nodes or triangle nodes within a bounded volume hierarchy using 64 bit node pointers.", "description": "Test the intersection of rays with either box nodes or triangle nodes within a bounded volume hierarchy using 64 bit node pointers. Store the results of the test into a vector register. This instruction does not take a sampler constant.", "syntax": "image_bvh64_intersect_ray", "operands": [], "dataTypes": [], "semantics": "", "example": "image_bvh64_intersect_ray v[5:8], v[1:12], s[8:11]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.image_bvh8_intersect_ray", "mnemonic": "image_bvh8_intersect_ray", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE BVH8 INTERSECT RAY", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "This instruction supports testing one BVH8 node against one ray per lane using both intersection engines.", "description": "This instruction supports testing one BVH8 node against one ray per lane using both intersection engines.", "syntax": "image_bvh8_intersect_ray", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.image_bvh_dual_intersect_ray", "mnemonic": "image_bvh_dual_intersect_ray", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE BVH DUAL INTERSECT RAY", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "This instruction supports testing two QBVH nodes against the same ray per lane using both intersection engines.", "description": "This instruction supports testing two QBVH nodes against the same ray per lane using both intersection engines. It is typically used to implement the BVH4x2 traversal algorithm.", "syntax": "image_bvh_dual_intersect_ray", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.image_bvh_intersect_ray", "mnemonic": "image_bvh_intersect_ray", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE BVH INTERSECT RAY", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Test the intersection of rays with either box nodes or triangle nodes within a bounded volume hierarchy using 32 bit node pointers.", "description": "Test the intersection of rays with either box nodes or triangle nodes within a bounded volume hierarchy using 32 bit node pointers. Store the results of the test into a vector register. This instruction does not take a sampler constant.", "syntax": "image_bvh_intersect_ray", "operands": [], "dataTypes": [], "semantics": "", "example": "image_bvh_intersect_ray v[5:8], v[1:11], s[8:11]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.image_gather4h", "mnemonic": "image_gather4h", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE GATHER4H", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Gather 4 single-component texels from a 4x1 row vector on an image surface.", "description": "Gather 4 single-component texels from a 4x1 row vector on an image surface. Store the result into vector registers. The DMASK selects which channel to read from (R, G, B, A) and must only have one bit set to 1.", "syntax": "image_gather4h", "operands": [], "dataTypes": [], "semantics": "", "example": "image_gather4h v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x4 dim:SQ_RSRC_IMG_2D", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.image_get_lod", "mnemonic": "image_get_lod", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE GET LOD", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Return the calculated level of detail (LOD) for the provided input as two single-precision float values. No memory access is performed.", "description": "Return the calculated level of detail (LOD) for the provided input as two single-precision float values. No memory access is performed.", "syntax": "image_get_lod", "operands": [], "dataTypes": [], "semantics": "", "example": "image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_1D", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.image_get_resinfo", "mnemonic": "image_get_resinfo", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE GET RESINFO", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Gather resource information for a given miplevel provided in the address register.", "description": "Gather resource information for a given miplevel provided in the address register. Returns 4 integer values into registers 3:0 as { num_mip_levels, depth, height, width }. No memory access is performed.", "syntax": "image_get_resinfo", "operands": [], "dataTypes": [], "semantics": "", "example": "image_get_resinfo v[5:6], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.image_load", "mnemonic": "image_load", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE LOAD", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Load a texel from the largest miplevel in an image surface and store the result into a vector register.", "description": "Load a texel from the largest miplevel in an image surface and store the result into a vector register. Perform the format conversion specified by the resource descriptor. No sampling is performed.", "syntax": "image_load", "operands": [], "dataTypes": [], "semantics": "", "example": "image_load v[5:6], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.image_load_mip", "mnemonic": "image_load_mip", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE LOAD MIP", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Load a texel from a user-specified miplevel in an image surface and store the result into a vector register.", "description": "Load a texel from a user-specified miplevel in an image surface and store the result into a vector register. Perform the format conversion specified by the resource descriptor. No sampling is performed.", "syntax": "image_load_mip", "operands": [], "dataTypes": [], "semantics": "", "example": "image_load_mip v[5:6], v[1:2], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.image_load_mip_pck", "mnemonic": "image_load_mip_pck", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE LOAD MIP PCK", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Load a texel from a user-specified miplevel in an image surface and store the result into a vector register.", "description": "Load a texel from a user-specified miplevel in an image surface and store the result into a vector register. 8- and 16-bit components are zero-extended. The format specified in the resource descriptor is ignored. No sampling is performed.", "syntax": "image_load_mip_pck", "operands": [], "dataTypes": [], "semantics": "", "example": "image_load_mip_pck v[5:6], v[1:2], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.image_load_mip_pck_sgn", "mnemonic": "image_load_mip_pck_sgn", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE LOAD MIP PCK SGN", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Load a texel from a user-specified miplevel in an image surface and store the result into a vector register.", "description": "Load a texel from a user-specified miplevel in an image surface and store the result into a vector register. 8- and 16-bit components are sign-extended. The format specified in the resource descriptor is ignored. No sampling is performed.", "syntax": "image_load_mip_pck_sgn", "operands": [], "dataTypes": [], "semantics": "", "example": "image_load_mip_pck_sgn v[5:6], v[1:2], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.image_load_pck", "mnemonic": "image_load_pck", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE LOAD PCK", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Load a texel from the largest miplevel in an image surface and store the result into a vector register.", "description": "Load a texel from the largest miplevel in an image surface and store the result into a vector register. 8- and 16-bit components are zero-extended. The format specified in the resource descriptor is ignored. No sampling is performed.", "syntax": "image_load_pck", "operands": [], "dataTypes": [], "semantics": "", "example": "image_load_pck v[5:6], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.image_load_pck_sgn", "mnemonic": "image_load_pck_sgn", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE LOAD PCK SGN", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Load a texel from the largest miplevel in an image surface and store the result into a vector register.", "description": "Load a texel from the largest miplevel in an image surface and store the result into a vector register. 8- and 16-bit components are sign-extended. The format specified in the resource descriptor is ignored. No sampling is performed.", "syntax": "image_load_pck_sgn", "operands": [], "dataTypes": [], "semantics": "", "example": "image_load_pck_sgn v[5:6], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.image_msaa_load", "mnemonic": "image_msaa_load", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE MSAA LOAD", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Load up to 4 samples of 1 component from an MSAA resource with a user-specified fragment ID. No sampling is performed.", "description": "Load up to 4 samples of 1 component from an MSAA resource with a user-specified fragment ID. No sampling is performed.", "syntax": "image_msaa_load", "operands": [], "dataTypes": [], "semantics": "", "example": "image_msaa_load v[5:6], v[1:3], s[8:15] dmask:0x4 dim:SQ_RSRC_IMG_2D_MSAA d16", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.image_store", "mnemonic": "image_store", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE STORE", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Store a texel from a vector register to the largest miplevel in an image surface.", "description": "Store a texel from a vector register to the largest miplevel in an image surface. The texel data is converted using the format conversion specified by the resource descriptor prior to storage.", "syntax": "image_store", "operands": [], "dataTypes": [], "semantics": "", "example": "image_store v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.image_store_mip", "mnemonic": "image_store_mip", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE STORE MIP", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Store a texel from a vector register to a user-specified miplevel in an image surface.", "description": "Store a texel from a vector register to a user-specified miplevel in an image surface. The texel data is converted using the format conversion specified by the resource descriptor prior to storage.", "syntax": "image_store_mip", "operands": [], "dataTypes": [], "semantics": "", "example": "image_store_mip v[1:2], v[2:3], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.image_store_mip_pck", "mnemonic": "image_store_mip_pck", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE STORE MIP PCK", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Store a texel from a vector register to a user-specified miplevel in an image surface.", "description": "Store a texel from a vector register to a user-specified miplevel in an image surface. The texel data is already packed and the format specified in the resource descriptor is ignored.", "syntax": "image_store_mip_pck", "operands": [], "dataTypes": [], "semantics": "", "example": "image_store_mip_pck v[1:2], v[2:3], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.image_store_pck", "mnemonic": "image_store_pck", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "IMAGE STORE PCK", "category": "Image / Texture Memory", "instructionClass": "vector", "summary": "Store a texel from a vector register to the largest miplevel in an image surface.", "description": "Store a texel from a vector register to the largest miplevel in an image surface. The texel data is already packed and the format specified in the resource descriptor is ignored.", "syntax": "image_store_pck", "operands": [], "dataTypes": [], "semantics": "", "example": "image_store_pck v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MIMG" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.lds_direct_load", "mnemonic": "lds_direct_load", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "LDS DIRECT LOAD", "category": "LDS Direct / Parameter Fetch", "instructionClass": "vector", "summary": "Read a single 32-bit value from LDS to all lanes.", "description": "Read a single 32-bit value from LDS to all lanes. A single DWORD is read from LDS memory at ADDR[M0[15:0]], where M0[15:0] is a byte address and is dword-aligned. M0[18:16] specify the data type for the read and may be 0=UBYTE, 1=USHORT, 2=DWORD, 4=SBYTE, 5=SSHORT.", "syntax": "lds_direct_load", "operands": [], "dataTypes": [], "semantics": "", "example": "lds_direct_load v17", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DSDIR" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.lds_param_load", "mnemonic": "lds_param_load", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "LDS PARAM LOAD", "category": "LDS Direct / Parameter Fetch", "instructionClass": "vector", "summary": "Transfer parameter data from LDS to VGPRs and expand data in LDS using the NewPrimMask (provided in M0) to place per-quad data into lanes 0-3 of each…", "description": "Transfer parameter data from LDS to VGPRs and expand data in LDS using the NewPrimMask (provided in M0) to place per-quad data into lanes 0-3 of each quad as follows:", "syntax": "lds_param_load", "operands": [], "dataTypes": [], "semantics": "", "example": "lds_param_load v7, attr2.y wait_vdst:9", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "DSDIR" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_abs_i32", "mnemonic": "s_abs_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ABS I32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Compute the absolute value of a scalar input, store the result into a scalar register and set SCC iff the result is nonzero.", "description": "Compute the absolute value of a scalar input, store the result into a scalar register and set SCC iff the result is nonzero.", "syntax": "s_abs_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "D0.i32 = S0.i32 < 0 ? -S0.i32 : S0.i32;\nSCC = D0.i32 != 0", "example": "S_ABS_I32(0x00000001) => 0x00000001\nS_ABS_I32(0x7fffffff) => 0x7fffffff\nS_ABS_I32(0x80000000) => 0x80000000 // Note this is negative!\nS_ABS_I32(0x80000001) => 0x7fffffff", "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 129, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.s_absdiff_i32", "mnemonic": "s_absdiff_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ABSDIFF I32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate the absolute value of difference between two scalar inputs, store the result into a scalar register and set SCC iff the result is nonzero.", "description": "Calculate the absolute value of difference between two scalar inputs, store the result into a scalar register and set SCC iff the result is nonzero.", "syntax": "s_absdiff_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "D0.i32 = S0.i32 - S1.i32;\nif D0.i32 < 0 then\nD0.i32 = -D0.i32\nendif;\nSCC = D0.i32 != 0", "example": "S_ABSDIFF_I32(0x00000002, 0x00000005) => 0x00000003\nS_ABSDIFF_I32(0xffffffff, 0x00000000) => 0x00000001\nS_ABSDIFF_I32(0x80000000, 0x00000000) => 0x80000000 // Note: result is negative!\nS_ABSDIFF_I32(0x80000000, 0x00000001) => 0x7fffffff", "exampleSource": null, "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 106, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.s_add_co_ci_u32", "mnemonic": "s_add_co_ci_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ADD CO CI U32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Add two unsigned 32-bit integer inputs and a carry-in bit from SCC, store the result into a scalar register and store the carry-out bit into SCC.", "description": "Add two unsigned 32-bit integer inputs and a carry-in bit from SCC, store the result into a scalar register and store the carry-out bit into SCC.", "syntax": "s_add_co_ci_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_add_co_i32", "mnemonic": "s_add_co_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ADD CO I32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Add two signed 32-bit integer inputs, store the result into a scalar register and store the carry-out bit into SCC.", "description": "Add two signed 32-bit integer inputs, store the result into a scalar register and store the carry-out bit into SCC.", "syntax": "s_add_co_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_add_co_u32", "mnemonic": "s_add_co_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ADD CO U32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Add two unsigned 32-bit integer inputs, store the result into a scalar register and store the carry-out bit into SCC.", "description": "Add two unsigned 32-bit integer inputs, store the result into a scalar register and store the carry-out bit into SCC.", "syntax": "s_add_co_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_add_f16", "mnemonic": "s_add_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ADD F16", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Add two floating point inputs and store the result into a scalar register.", "description": "Add two floating point inputs and store the result into a scalar register.", "syntax": "s_add_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_add_f32", "mnemonic": "s_add_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ADD F32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Add two floating point inputs and store the result into a scalar register.", "description": "Add two floating point inputs and store the result into a scalar register.", "syntax": "s_add_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_add_i32", "mnemonic": "s_add_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ADD I32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Add two signed 32-bit integer inputs, store the result into a scalar register and store the carry-out bit into SCC.", "description": "Add two signed 32-bit integer inputs, store the result into a scalar register and store the carry-out bit into SCC.", "syntax": "s_add_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "tmp = S0.i32 + S1.i32;\nSCC = ((S0.u32[31] == S1.u32[31]) && (S0.u32[31] != tmp.u32[31]));\n// signed overflow.\nD0.i32 = tmp.i32", "example": "s_add_i32 s0, 0, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "This opcode is not suitable for use with S_ADDC_U32 for implementing 64-bit operations.", "sourcePdfPage": 97, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_add_nc_u64", "mnemonic": "s_add_nc_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ADD NC U64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Add two unsigned 64-bit integer inputs and store the result into a scalar register.", "description": "Add two unsigned 64-bit integer inputs and store the result into a scalar register.", "syntax": "s_add_nc_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_add_pc_i64", "mnemonic": "s_add_pc_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ADD PC I64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "AMDGPU SOP1 scalar instruction operating on i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "s_add_pc_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.s_add_u32", "mnemonic": "s_add_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ADD U32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Add two 32-bit unsigned scalar operands, wavefront-uniform.", "description": "Add two unsigned 32-bit integer inputs, store the result into a scalar register and store the carry-out bit into SCC.", "syntax": "s_add_u32 SDST, S0, S1", "operands": [ { "name": "SDST", "desc": "Destination SGPR" }, { "name": "S0", "desc": "First source SGPR/constant" }, { "name": "S1", "desc": "Second source SGPR/constant" } ], "dataTypes": [ "u32" ], "semantics": "SDST = S0.u32 + S1.u32; SCC = carry-out.", "example": "s_add_u32 s2, s0, s1 // s2 = s0 + s1 (scalar, whole wavefront)", "exampleSource": null, "encoding": { "format": "SOP2", "widthBits": 32 }, "executionUnit": "Scalar ALU", "registerClasses": [ "SGPR" ], "memorySegment": null, "supportedTargets": [ "gfx942", "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_add_u64", "mnemonic": "s_add_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ADD U64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "AMDGPU SOP2 scalar instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "s_add_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.s_addc_u32", "mnemonic": "s_addc_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ADDC U32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Add two unsigned 32-bit integer inputs and a carry-in bit from SCC, store the result into a scalar register and store the carry-out bit into SCC.", "description": "Add two unsigned 32-bit integer inputs and a carry-in bit from SCC, store the result into a scalar register and store the carry-out bit into SCC.", "syntax": "s_addc_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "tmp = 64'U(S0.u32) + 64'U(S1.u32) + SCC.u64;\nSCC = tmp >= 0x100000000ULL ? 1'1U : 1'0U;\n// unsigned overflow or carry-out for S_ADDC_U32.\nD0.u32 = tmp.u32", "example": "s_addc_u32 s0, 0, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 98, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_addk_co_i32", "mnemonic": "s_addk_co_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ADDK CO I32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Add a scalar input and the sign extension of a literal 16-bit constant, store the result into a scalar register and store the carry-out bit into SCC.", "description": "Add a scalar input and the sign extension of a literal 16-bit constant, store the result into a scalar register and store the carry-out bit into SCC.", "syntax": "s_addk_co_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPK" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_addk_i32", "mnemonic": "s_addk_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ADDK I32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Add a scalar input and the sign extension of a literal 16-bit constant, store the result into a scalar register and store the carry-out bit into SCC.", "description": "Add a scalar input and the sign extension of a literal 16-bit constant, store the result into a scalar register and store the carry-out bit into SCC.", "syntax": "s_addk_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "tmp = D0.i32;\n// Save value to check sign bits for overflow later.\nD0.i32 = D0.i32 + 32'I(signext(S0.i16));\nSCC = ((tmp[31] == S0.i16[15]) && (tmp[31] != D0.i32[31]));\n// signed overflow.", "example": "s_addk_i32 s0, 0x1234", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPK" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 111, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_alloc_vgpr", "mnemonic": "s_alloc_vgpr", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ALLOC VGPR", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Attempt to set the wave's VGPR allocation to the specified number of VGPRs (or greater).", "description": "Attempt to set the wave's VGPR allocation to the specified number of VGPRs (or greater). The desired VGPR count may be specified as a constant or in an SGPR. The request is rounded up to the next block size so a successful allocation may include more than the requested number of VGPRs.", "syntax": "s_alloc_vgpr", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_and_b32", "mnemonic": "s_and_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S AND B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise AND on two scalar inputs, store the result into a scalar register and set SCC iff the result is nonzero.", "description": "Calculate bitwise AND on two scalar inputs, store the result into a scalar register and set SCC iff the result is nonzero.", "syntax": "s_and_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.u32 = (S0.u32 & S1.u32);\nSCC = D0.u32 != 0U", "example": "s_and_b32 s0, 0, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 99, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_and_b64", "mnemonic": "s_and_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S AND B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise AND on two scalar inputs, store the result into a scalar register and set SCC iff the result is nonzero.", "description": "Calculate bitwise AND on two scalar inputs, store the result into a scalar register and set SCC iff the result is nonzero.", "syntax": "s_and_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "D0.u64 = (S0.u64 & S1.u64);\nSCC = D0.u64 != 0ULL", "example": "s_and_b64 s[0:1], 0, s[4:5]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 100, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_and_not0_saveexec_b32", "mnemonic": "s_and_not0_saveexec_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S AND NOT0 SAVEEXEC B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the…", "description": "Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register.", "syntax": "s_and_not0_saveexec_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "s_and_not0_saveexec_b32 s5, s1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_and_not0_saveexec_b64", "mnemonic": "s_and_not0_saveexec_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S AND NOT0 SAVEEXEC B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the…", "description": "Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register.", "syntax": "s_and_not0_saveexec_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "s_and_not0_saveexec_b64 vcc, 0.5", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_and_not0_wrexec_b32", "mnemonic": "s_and_not0_wrexec_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S AND NOT0 WREXEC B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask and also into the scalar…", "description": "Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask and also into the scalar destination register, and set SCC iff the calculated result is nonzero.", "syntax": "s_and_not0_wrexec_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "s_and_not0_wrexec_b32 s5, s1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_and_not0_wrexec_b64", "mnemonic": "s_and_not0_wrexec_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S AND NOT0 WREXEC B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask and also into the scalar…", "description": "Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask and also into the scalar destination register, and set SCC iff the calculated result is nonzero.", "syntax": "s_and_not0_wrexec_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "s_and_not0_wrexec_b64 vcc, 0.5", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_and_not1_b32", "mnemonic": "s_and_not1_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S AND NOT1 B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise AND with the first input and the negation of the second input, store the result into a scalar register and set SCC if the result is…", "description": "Calculate bitwise AND with the first input and the negation of the second input, store the result into a scalar register and set SCC if the result is nonzero.", "syntax": "s_and_not1_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "s_and_not1_b32 s5, s1, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_and_not1_b64", "mnemonic": "s_and_not1_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S AND NOT1 B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise AND with the first input and the negation of the second input, store the result into a scalar register and set SCC if the result is…", "description": "Calculate bitwise AND with the first input and the negation of the second input, store the result into a scalar register and set SCC if the result is nonzero.", "syntax": "s_and_not1_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "s_and_not1_b64 vcc, -1, -1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_and_not1_saveexec_b32", "mnemonic": "s_and_not1_saveexec_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S AND NOT1 SAVEEXEC B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise AND on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the…", "description": "Calculate bitwise AND on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register.", "syntax": "s_and_not1_saveexec_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "s_and_not1_saveexec_b32 s5, s1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_and_not1_saveexec_b64", "mnemonic": "s_and_not1_saveexec_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S AND NOT1 SAVEEXEC B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise AND on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the…", "description": "Calculate bitwise AND on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register.", "syntax": "s_and_not1_saveexec_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "s_and_not1_saveexec_b64 vcc, 0.5", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_and_not1_wrexec_b32", "mnemonic": "s_and_not1_wrexec_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S AND NOT1 WREXEC B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise AND on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask and also into the scalar…", "description": "Calculate bitwise AND on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask and also into the scalar destination register, and set SCC iff the calculated result is nonzero.", "syntax": "s_and_not1_wrexec_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "s_and_not1_wrexec_b32 s5, s1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_and_not1_wrexec_b64", "mnemonic": "s_and_not1_wrexec_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S AND NOT1 WREXEC B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise AND on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask and also into the scalar…", "description": "Calculate bitwise AND on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask and also into the scalar destination register, and set SCC iff the calculated result is nonzero.", "syntax": "s_and_not1_wrexec_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "s_and_not1_wrexec_b64 vcc, 0.5", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_and_saveexec_b32", "mnemonic": "s_and_saveexec_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S AND SAVEEXEC B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise AND on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is…", "description": "Calculate bitwise AND on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register.", "syntax": "s_and_saveexec_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "s_and_saveexec_b32 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_and_saveexec_b64", "mnemonic": "s_and_saveexec_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S AND SAVEEXEC B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise AND on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is…", "description": "Calculate bitwise AND on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. The original EXEC mask is saved to the destination SGPRs before the bitwise operation is performed.", "syntax": "s_and_saveexec_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "saveexec = EXEC.u64;\nEXEC.u64 = (S0.u64 & EXEC.u64);\nD0.u64 = saveexec.u64;\nSCC = EXEC.u64 != 0ULL", "example": "s_and_saveexec_b64 s[0:1], 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 124, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_andn1_saveexec_b32", "mnemonic": "s_andn1_saveexec_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ANDN1 SAVEEXEC B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the…", "description": "Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register.", "syntax": "s_andn1_saveexec_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "s_andn1_saveexec_b32 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_andn1_saveexec_b64", "mnemonic": "s_andn1_saveexec_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ANDN1 SAVEEXEC B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the…", "description": "Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. The original EXEC mask is saved to the destination SGPRs before the bitwise operation is performed.", "syntax": "s_andn1_saveexec_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "saveexec = EXEC.u64;\nEXEC.u64 = (~S0.u64 & EXEC.u64);\nD0.u64 = saveexec.u64;\nSCC = EXEC.u64 != 0ULL", "example": "s_andn1_saveexec_b64 s[0:1], 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 130, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_andn1_wrexec_b32", "mnemonic": "s_andn1_wrexec_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ANDN1 WREXEC B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask and also into the scalar…", "description": "Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask and also into the scalar destination register, and set SCC iff the calculated result is nonzero.", "syntax": "s_andn1_wrexec_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "s_andn1_wrexec_b32 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_andn1_wrexec_b64", "mnemonic": "s_andn1_wrexec_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ANDN1 WREXEC B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask and also into the scalar…", "description": "Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask and also into the scalar destination register, and set SCC iff the calculated result is nonzero. Unlike the SAVEEXEC series of opcodes, the value written to destination SGPRs is the result of the bitwise-op result. EXEC and the destination SGPRs have the same value at the end of this instruction. This instruction is intended to help accelerate waterfalling.", "syntax": "s_andn1_wrexec_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "EXEC.u64 = (~S0.u64 & EXEC.u64);\nD0.u64 = EXEC.u64;\nSCC = EXEC.u64 != 0ULL", "example": "s_andn1_wrexec_b64 s[0:1], 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 130, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_andn2_b32", "mnemonic": "s_andn2_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ANDN2 B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise AND with the first input and the negation of the second input, store the result into a scalar register and set SCC if the result is…", "description": "Calculate bitwise AND with the first input and the negation of the second input, store the result into a scalar register and set SCC if the result is nonzero.", "syntax": "s_andn2_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.u32 = (S0.u32 & ~S1.u32);\nSCC = D0.u32 != 0U", "example": "s_andn2_b32 s0, 0, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 101, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_andn2_b64", "mnemonic": "s_andn2_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ANDN2 B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise AND with the first input and the negation of the second input, store the result into a scalar register and set SCC if the result is…", "description": "Calculate bitwise AND with the first input and the negation of the second input, store the result into a scalar register and set SCC if the result is nonzero.", "syntax": "s_andn2_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "D0.u64 = (S0.u64 & ~S1.u64);\nSCC = D0.u64 != 0ULL", "example": "s_andn2_b64 s[0:1], 0, s[4:5]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 101, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_andn2_saveexec_b32", "mnemonic": "s_andn2_saveexec_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ANDN2 SAVEEXEC B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise AND on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the…", "description": "Calculate bitwise AND on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register.", "syntax": "s_andn2_saveexec_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "s_andn2_saveexec_b32 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_andn2_saveexec_b64", "mnemonic": "s_andn2_saveexec_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ANDN2 SAVEEXEC B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise AND on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the…", "description": "Calculate bitwise AND on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. The original EXEC mask is saved to the destination SGPRs before the bitwise operation is performed.", "syntax": "s_andn2_saveexec_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "saveexec = EXEC.u64;\nEXEC.u64 = (S0.u64 & ~EXEC.u64);\nD0.u64 = saveexec.u64;\nSCC = EXEC.u64 != 0ULL", "example": "s_andn2_saveexec_b64 s[0:1], 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 125, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_andn2_wrexec_b32", "mnemonic": "s_andn2_wrexec_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ANDN2 WREXEC B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise AND on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask and also into the scalar…", "description": "Calculate bitwise AND on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask and also into the scalar destination register, and set SCC iff the calculated result is nonzero.", "syntax": "s_andn2_wrexec_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "s_andn2_wrexec_b32 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_andn2_wrexec_b64", "mnemonic": "s_andn2_wrexec_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ANDN2 WREXEC B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise AND on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask and also into the scalar…", "description": "Calculate bitwise AND on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask and also into the scalar destination register, and set SCC iff the calculated result is nonzero. Unlike the SAVEEXEC series of opcodes, the value written to destination SGPRs is the result of the bitwise-op result. EXEC and the destination SGPRs have the same value at the end of this instruction. This instruction is intended to help accelerate waterfalling.", "syntax": "s_andn2_wrexec_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "EXEC.u64 = (S0.u64 & ~EXEC.u64);\nD0.u64 = EXEC.u64;\nSCC = EXEC.u64 != 0ULL", "example": "s_andn2_wrexec_b64 s[0:1], 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "In particular, the following sequence of waterfall code is optimized by using a WREXEC instead of two separate scalar ops: // V0 holds the index value per lane\n// save exec mask for restore at the end s_mov_b64 s2, exec // exec mask of remaining (unprocessed) threads s_mov_b64 s4, exec loop: // get the index value for the first active lane v_readfirstlane_b32 s0, v0 // find all other lanes with same index value v_cmpx_eq s0, v0 // do the operation using the current EXEC mask. S0 holds the index. // mask out thread that was just executed\n// s_andn2_b64 s4, s4, exec\n// s_mov_b64 exec, s4 s_andn2_wrexec_b64 s4, s4 // replaces above 2 ops // repeat until EXEC==0 s_cbranch_scc1 loop s_mov_b64 exec, s2", "sourcePdfPage": 131, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_ashr_i32", "mnemonic": "s_ashr_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ASHR I32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Given a shift count in the second scalar input, calculate the arithmetic shift right (preserving sign bit) of the first scalar input, store the…", "description": "Given a shift count in the second scalar input, calculate the arithmetic shift right (preserving sign bit) of the first scalar input, store the result into a scalar register and set SCC iff the result is nonzero.", "syntax": "s_ashr_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "D0.i32 = 32'I(signext(S0.i32) >> S1[4 : 0].u32);\nSCC = D0.i32 != 0", "example": "s_ashr_i32 s0, 0, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 104, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_ashr_i64", "mnemonic": "s_ashr_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ASHR I64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Given a shift count in the second scalar input, calculate the arithmetic shift right (preserving sign bit) of the first scalar input, store the…", "description": "Given a shift count in the second scalar input, calculate the arithmetic shift right (preserving sign bit) of the first scalar input, store the result into a scalar register and set SCC iff the result is nonzero.", "syntax": "s_ashr_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "D0.i64 = (signext(S0.i64) >> S1[5 : 0].u32);\nSCC = D0.i64 != 0LL", "example": "s_ashr_i64 s[0:1], 0, s4", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 104, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_barrier", "mnemonic": "s_barrier", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S BARRIER", "category": "Barriers", "instructionClass": "scalar", "summary": "Synchronize all waves of the executing workgroup at this point.", "description": "Synchronize waves within a threadgroup.", "syntax": "s_barrier", "operands": [], "dataTypes": [], "semantics": "Every wave belonging to the workgroup blocks until all waves of that workgroup have executed s_barrier.", "example": "s_barrier // block until every wave in the workgroup arrives here", "exampleSource": null, "encoding": { "format": "SOPP", "widthBits": 32 }, "executionUnit": "Scalar ALU", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx942", "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_barrier_init", "mnemonic": "s_barrier_init", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S BARRIER INIT", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "AMDGPU SOP1 scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "s_barrier_init", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.s_barrier_join", "mnemonic": "s_barrier_join", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S BARRIER JOIN", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "AMDGPU SOP1 scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "s_barrier_join", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.s_barrier_leave", "mnemonic": "s_barrier_leave", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S BARRIER LEAVE", "category": "Branch & Control", "instructionClass": "scalar", "summary": "AMDGPU SOPP scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "s_barrier_leave", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.s_barrier_signal", "mnemonic": "s_barrier_signal", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S BARRIER SIGNAL", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Signal that a wave has arrived at a barrier . The argument specifies which barrier to signal.", "description": "Signal that a wave has arrived at a barrier . The argument specifies which barrier to signal.", "syntax": "s_barrier_signal", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_barrier_signal_isfirst", "mnemonic": "s_barrier_signal_isfirst", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S BARRIER SIGNAL ISFIRST", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Signal that a wave has arrived at a barrier and set SCC to indicate if this is the first wave to signal the barrier.", "description": "Signal that a wave has arrived at a barrier and set SCC to indicate if this is the first wave to signal the barrier. The argument specifies which barrier to signal.", "syntax": "s_barrier_signal_isfirst", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_barrier_wait", "mnemonic": "s_barrier_wait", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S BARRIER WAIT", "category": "Branch & Control", "instructionClass": "scalar", "summary": "Wait for a barrier to complete. The SIMM16 argument specifies which barrier to wait on.", "description": "Wait for a barrier to complete. The SIMM16 argument specifies which barrier to wait on.", "syntax": "s_barrier_wait", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_bcnt0_i32_b32", "mnemonic": "s_bcnt0_i32_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S BCNT0 I32 B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Count the number of \"0\" bits in a scalar input, store the result into a scalar register and set SCC iff the result is nonzero.", "description": "Count the number of \"0\" bits in a scalar input, store the result into a scalar register and set SCC iff the result is nonzero.", "syntax": "s_bcnt0_i32_b32", "operands": [], "dataTypes": [ "b32", "i32" ], "semantics": "tmp = 0;\nfor i in 0 : 31 do\ntmp += S0.u32[i] == 1'0U ? 1 : 0\nendfor;\nD0.i32 = tmp;\nSCC = D0.u32 != 0U", "example": "S_BCNT0_I32_B32(0x00000000) => 32\nS_BCNT0_I32_B32(0xcccccccc) => 16\nS_BCNT0_I32_B32(0xffffffff) => 0", "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 117, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.s_bcnt0_i32_b64", "mnemonic": "s_bcnt0_i32_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S BCNT0 I32 B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Count the number of \"0\" bits in a scalar input, store the result into a scalar register and set SCC iff the result is nonzero.", "description": "Count the number of \"0\" bits in a scalar input, store the result into a scalar register and set SCC iff the result is nonzero.", "syntax": "s_bcnt0_i32_b64", "operands": [], "dataTypes": [ "b64", "i32" ], "semantics": "tmp = 0;\nfor i in 0 : 63 do\ntmp += S0.u64[i] == 1'0U ? 1 : 0\nendfor;\nD0.i32 = tmp;\nSCC = D0.u64 != 0ULL", "example": "s_bcnt0_i32_b64 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 117, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_bcnt1_i32_b32", "mnemonic": "s_bcnt1_i32_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S BCNT1 I32 B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Count the number of \"1\" bits in a scalar input, store the result into a scalar register and set SCC iff the result is nonzero.", "description": "Count the number of \"1\" bits in a scalar input, store the result into a scalar register and set SCC iff the result is nonzero.", "syntax": "s_bcnt1_i32_b32", "operands": [], "dataTypes": [ "b32", "i32" ], "semantics": "tmp = 0;\nfor i in 0 : 31 do\ntmp += S0.u32[i] == 1'1U ? 1 : 0\nendfor;\nD0.i32 = tmp;\nSCC = D0.u32 != 0U", "example": "S_BCNT1_I32_B32(0x00000000) => 0\nS_BCNT1_I32_B32(0xcccccccc) => 16\nS_BCNT1_I32_B32(0xffffffff) => 32", "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 118, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.s_bcnt1_i32_b64", "mnemonic": "s_bcnt1_i32_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S BCNT1 I32 B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Count the number of \"1\" bits in a scalar input, store the result into a scalar register and set SCC iff the result is nonzero.", "description": "Count the number of \"1\" bits in a scalar input, store the result into a scalar register and set SCC iff the result is nonzero.", "syntax": "s_bcnt1_i32_b64", "operands": [], "dataTypes": [ "b64", "i32" ], "semantics": "tmp = 0;\nfor i in 0 : 63 do\ntmp += S0.u64[i] == 1'1U ? 1 : 0\nendfor;\nD0.i32 = tmp;\nSCC = D0.u64 != 0ULL", "example": "s_bcnt1_i32_b64 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 118, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_bfe_i32", "mnemonic": "s_bfe_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S BFE I32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Extract a signed bitfield from the first input using field offset and size encoded in the second input, store the result into a scalar register and…", "description": "Extract a signed bitfield from the first input using field offset and size encoded in the second input, store the result into a scalar register and set SCC iff the result is nonzero.", "syntax": "s_bfe_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "tmp.i32 = ((S0.i32 >> S1[4 : 0].u32) & ((1 << S1[22 : 16].u32) - 1));\nD0.i32 = signext_from_bit(tmp.i32, S1[22 : 16].u32);\nSCC = D0.i32 != 0", "example": "s_bfe_i32 s0, 0, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 105, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_bfe_i64", "mnemonic": "s_bfe_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S BFE I64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Extract a signed bitfield from the first input using field offset and size encoded in the second input, store the result into a scalar register and…", "description": "Extract a signed bitfield from the first input using field offset and size encoded in the second input, store the result into a scalar register and set SCC iff the result is nonzero.", "syntax": "s_bfe_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "tmp.i64 = ((S0.i64 >> S1[5 : 0].u32) & ((1LL << S1[22 : 16].u32) - 1LL));\nD0.i64 = signext_from_bit(tmp.i64, S1[22 : 16].u32);\nSCC = D0.i64 != 0LL", "example": "s_bfe_i64 s[0:1], 0, s4", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 105, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_bfe_u32", "mnemonic": "s_bfe_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S BFE U32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Extract an unsigned bitfield from the first input using field offset and size encoded in the second input, store the result into a scalar register…", "description": "Extract an unsigned bitfield from the first input using field offset and size encoded in the second input, store the result into a scalar register and set SCC iff the result is nonzero.", "syntax": "s_bfe_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "D0.u32 = ((S0.u32 >> S1[4 : 0].u32) & ((1U << S1[22 : 16].u32) - 1U));\nSCC = D0.u32 != 0U", "example": "s_bfe_u32 s0, 0, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 105, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_bfe_u64", "mnemonic": "s_bfe_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S BFE U64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Extract an unsigned bitfield from the first input using field offset and size encoded in the second input, store the result into a scalar register…", "description": "Extract an unsigned bitfield from the first input using field offset and size encoded in the second input, store the result into a scalar register and set SCC iff the result is nonzero.", "syntax": "s_bfe_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "D0.u64 = ((S0.u64 >> S1[5 : 0].u32) & ((1ULL << S1[22 : 16].u32) - 1ULL));\nSCC = D0.u64 != 0ULL", "example": "s_bfe_u64 s[0:1], 0, s4", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 105, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_bfm_b32", "mnemonic": "s_bfm_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S BFM B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate a bitfield mask given a field offset and size and store the result in a scalar register.", "description": "Calculate a bitfield mask given a field offset and size and store the result in a scalar register.", "syntax": "s_bfm_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.u32 = (((1U << S0[4 : 0].u32) - 1U) << S1[4 : 0].u32)", "example": "s_bfm_b32 s0, 0, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 104, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_bfm_b64", "mnemonic": "s_bfm_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S BFM B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate a bitfield mask given a field offset and size and store the result in a scalar register.", "description": "Calculate a bitfield mask given a field offset and size and store the result in a scalar register.", "syntax": "s_bfm_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "D0.u64 = (((1ULL << S0[5 : 0].u32) - 1ULL) << S1[5 : 0].u32)", "example": "s_bfm_b64 vcc, s2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 104, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_bitcmp0_b32", "mnemonic": "s_bitcmp0_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S BITCMP0 B32", "category": "Comparison", "instructionClass": "scalar", "summary": "Extract a bit from the first scalar input based on an index in the second scalar input, and set SCC to 1 iff the extracted bit is equal to 0.", "description": "Extract a bit from the first scalar input based on an index in the second scalar input, and set SCC to 1 iff the extracted bit is equal to 0.", "syntax": "s_bitcmp0_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "SCC = S0.u32[S1.u32[4 : 0]] == 1'0U", "example": "s_bitcmp0_b32 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 135, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_bitcmp0_b64", "mnemonic": "s_bitcmp0_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S BITCMP0 B64", "category": "Comparison", "instructionClass": "scalar", "summary": "Extract a bit from the first scalar input based on an index in the second scalar input, and set SCC to 1 iff the extracted bit is equal to 0.", "description": "Extract a bit from the first scalar input based on an index in the second scalar input, and set SCC to 1 iff the extracted bit is equal to 0.", "syntax": "s_bitcmp0_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "SCC = S0.u64[S1.u32[5 : 0]] == 1'0U", "example": "s_bitcmp0_b64 vcc, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 135, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_bitcmp1_b32", "mnemonic": "s_bitcmp1_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S BITCMP1 B32", "category": "Comparison", "instructionClass": "scalar", "summary": "Extract a bit from the first scalar input based on an index in the second scalar input, and set SCC to 1 iff the extracted bit is equal to 1.", "description": "Extract a bit from the first scalar input based on an index in the second scalar input, and set SCC to 1 iff the extracted bit is equal to 1.", "syntax": "s_bitcmp1_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "SCC = S0.u32[S1.u32[4 : 0]] == 1'1U", "example": "s_bitcmp1_b32 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 135, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_bitcmp1_b64", "mnemonic": "s_bitcmp1_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S BITCMP1 B64", "category": "Comparison", "instructionClass": "scalar", "summary": "Extract a bit from the first scalar input based on an index in the second scalar input, and set SCC to 1 iff the extracted bit is equal to 1.", "description": "Extract a bit from the first scalar input based on an index in the second scalar input, and set SCC to 1 iff the extracted bit is equal to 1.", "syntax": "s_bitcmp1_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "SCC = S0.u64[S1.u32[5 : 0]] == 1'1U", "example": "s_bitcmp1_b64 vcc, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 136, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_bitreplicate_b64_b32", "mnemonic": "s_bitreplicate_b64_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S BITREPLICATE B64 B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Substitute each bit of a 32 bit scalar input with two instances of itself and store the result into a 64 bit scalar register.", "description": "Substitute each bit of a 32 bit scalar input with two instances of itself and store the result into a 64 bit scalar register.", "syntax": "s_bitreplicate_b64_b32", "operands": [], "dataTypes": [ "b32", "b64" ], "semantics": "tmp = S0.u32;\nfor i in 0 : 31 do\nD0.u64[i * 2] = tmp[i];\nD0.u64[i * 2 + 1] = tmp[i]\nendfor", "example": "s_bitreplicate_b64_b32 vcc, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "This opcode can be used to convert a quad mask into a pixel mask; given quad mask in s0, the following sequence produces a pixel mask in s2: s_bitreplicate_b64 s2, s0 s_bitreplicate_b64 s2, s2 To perform the inverse operation see S_QUADMASK_B64.", "sourcePdfPage": 131, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_bitset0_b32", "mnemonic": "s_bitset0_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S BITSET0 B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Given a bit offset in a scalar input, set the indicated bit in the destination scalar register to 0.", "description": "Given a bit offset in a scalar input, set the indicated bit in the destination scalar register to 0.", "syntax": "s_bitset0_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.u32[S0.u32[4 : 0]] = 1'0U", "example": "s_bitset0_b32 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 122, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_bitset0_b64", "mnemonic": "s_bitset0_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S BITSET0 B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Given a bit offset in a scalar input, set the indicated bit in the destination scalar register to 0.", "description": "Given a bit offset in a scalar input, set the indicated bit in the destination scalar register to 0.", "syntax": "s_bitset0_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "D0.u64[S0.u32[5 : 0]] = 1'0U", "example": "s_bitset0_b64 vcc, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 123, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_bitset1_b32", "mnemonic": "s_bitset1_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S BITSET1 B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Given a bit offset in a scalar input, set the indicated bit in the destination scalar register to 1.", "description": "Given a bit offset in a scalar input, set the indicated bit in the destination scalar register to 1.", "syntax": "s_bitset1_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.u32[S0.u32[4 : 0]] = 1'1U", "example": "s_bitset1_b32 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 123, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_bitset1_b64", "mnemonic": "s_bitset1_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S BITSET1 B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Given a bit offset in a scalar input, set the indicated bit in the destination scalar register to 1.", "description": "Given a bit offset in a scalar input, set the indicated bit in the destination scalar register to 1.", "syntax": "s_bitset1_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "D0.u64[S0.u32[5 : 0]] = 1'1U", "example": "s_bitset1_b64 vcc, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 123, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_branch", "mnemonic": "s_branch", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S BRANCH", "category": "Branch & Control", "instructionClass": "scalar", "summary": "Unconditional relative branch.", "description": "Jump to a constant offset relative to the current PC.", "syntax": "s_branch offset", "operands": [ { "name": "offset", "desc": "Signed word-granularity branch offset" } ], "dataTypes": [], "semantics": "PC = PC + 4 + signed_offset * 4.", "example": "s_branch label // unconditional jump to label", "exampleSource": null, "encoding": { "format": "SOPP", "widthBits": 32 }, "executionUnit": "Scalar ALU", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx942", "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_brev_b32", "mnemonic": "s_brev_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S BREV B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Reverse the order of bits in a scalar input and store the result into a scalar register.", "description": "Reverse the order of bits in a scalar input and store the result into a scalar register.", "syntax": "s_brev_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.u32[31 : 0] = S0.u32[0 : 31]", "example": "s_brev_b32 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 117, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_brev_b64", "mnemonic": "s_brev_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S BREV B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Reverse the order of bits in a scalar input and store the result into a scalar register.", "description": "Reverse the order of bits in a scalar input and store the result into a scalar register.", "syntax": "s_brev_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "D0.u64[63 : 0] = S0.u64[0 : 63]", "example": "s_brev_b64 s[0:1], 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 117, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_buffer_prefetch_data", "mnemonic": "s_buffer_prefetch_data", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S BUFFER PREFETCH DATA", "category": "Scalar Memory", "instructionClass": "scalar", "summary": "Prefetch data into the scalar data cache, relative to a base address provided in a resource descriptor constant.", "description": "Prefetch data into the scalar data cache, relative to a base address provided in a resource descriptor constant.", "syntax": "s_buffer_prefetch_data", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SMEM" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_call_i64", "mnemonic": "s_call_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CALL I64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "AMDGPU SOPK scalar instruction operating on i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "s_call_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPK" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.s_cbranch_join", "mnemonic": "s_cbranch_join", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CBRANCH JOIN", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Conditional branch join point (end of conditional branch block).", "description": "Conditional branch join point (end of conditional branch block). S0 is saved CSP value. See S_CBRANCH_G_FORK and S_CBRANCH_I_FORK for related instructions.", "syntax": "s_cbranch_join", "operands": [], "dataTypes": [], "semantics": "saved_csp = S0.u32;\nif WAVE_MODE.CSP.u32 == saved_csp then\nPC += 4LL;\n// Second time to JOIN: continue with program.\nelse\nWAVE_MODE.CSP -= 3'1U;\n// First time to JOIN; jump to other FORK path.\n{ PC, EXEC } = SGPR[WAVE_MODE.CSP.u32 * 4U].b128;\n// Read 128 bits from 4 consecutive SGPRs.\nendif", "example": null, "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 129, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.s_cbranch_scc1", "mnemonic": "s_cbranch_scc1", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CBRANCH SCC1", "category": "Branch & Control", "instructionClass": "scalar", "summary": "Conditional relative branch, taken when the SCC (scalar condition code) flag is set.", "description": "If SCC is 1 then jump to a constant offset relative to the current PC.", "syntax": "s_cbranch_scc1 offset", "operands": [ { "name": "offset", "desc": "Signed word-granularity branch offset" } ], "dataTypes": [], "semantics": "if (SCC == 1) PC = PC + 4 + signed_offset * 4.", "example": "s_cbranch_scc1 label // jump to label if SCC == 1", "exampleSource": null, "encoding": { "format": "SOPP", "widthBits": 32 }, "executionUnit": "Scalar ALU", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx942", "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_ceil_f16", "mnemonic": "s_ceil_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CEIL F16", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Round the half-precision float input up to next integer and store the result in floating point format into a scalar register.", "description": "Round the half-precision float input up to next integer and store the result in floating point format into a scalar register.", "syntax": "s_ceil_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_ceil_f32", "mnemonic": "s_ceil_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CEIL F32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Round the single-precision float input up to next integer and store the result in floating point format into a scalar register.", "description": "Round the single-precision float input up to next integer and store the result in floating point format into a scalar register.", "syntax": "s_ceil_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cls_i32", "mnemonic": "s_cls_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CLS I32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Count the number of leading bits that are the same as the sign bit of a scalar input and store the result into a scalar register.", "description": "Count the number of leading bits that are the same as the sign bit of a scalar input and store the result into a scalar register. Store -1 if all input bits are the same.", "syntax": "s_cls_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "", "example": "s_cls_i32 s5, s1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_cls_i32_i64", "mnemonic": "s_cls_i32_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CLS I32 I64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Count the number of leading bits that are the same as the sign bit of a scalar input and store the result into a scalar register.", "description": "Count the number of leading bits that are the same as the sign bit of a scalar input and store the result into a scalar register. Store -1 if all input bits are the same.", "syntax": "s_cls_i32_i64", "operands": [], "dataTypes": [ "i32", "i64" ], "semantics": "", "example": "s_cls_i32_i64 s105, vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_clz_i32_u32", "mnemonic": "s_clz_i32_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CLZ I32 U32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Count the number of leading \"0\" bits before the first \"1\" in a scalar input and store the result into a scalar register.", "description": "Count the number of leading \"0\" bits before the first \"1\" in a scalar input and store the result into a scalar register. Store -1 if there are no \"1\" bits.", "syntax": "s_clz_i32_u32", "operands": [], "dataTypes": [ "i32", "u32" ], "semantics": "", "example": "s_clz_i32_u32 s5, s1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_clz_i32_u64", "mnemonic": "s_clz_i32_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CLZ I32 U64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Count the number of leading \"0\" bits before the first \"1\" in a scalar input and store the result into a scalar register.", "description": "Count the number of leading \"0\" bits before the first \"1\" in a scalar input and store the result into a scalar register. Store -1 if there are no \"1\" bits.", "syntax": "s_clz_i32_u64", "operands": [], "dataTypes": [ "i32", "u64" ], "semantics": "", "example": "s_clz_i32_u64 s105, vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_cmov_b32", "mnemonic": "s_cmov_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMOV B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Move scalar input into a scalar register iff SCC is nonzero.", "description": "Move scalar input into a scalar register iff SCC is nonzero.", "syntax": "s_cmov_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "if SCC then\nD0.b32 = S0.b32\nendif", "example": "s_cmov_b32 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 115, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_cmov_b64", "mnemonic": "s_cmov_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMOV B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Move scalar input into a scalar register iff SCC is nonzero.", "description": "Move scalar input into a scalar register iff SCC is nonzero.", "syntax": "s_cmov_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "if SCC then\nD0.b64 = S0.b64\nendif", "example": "s_cmov_b64 s[0:1], 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 115, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_cmovk_i32", "mnemonic": "s_cmovk_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMOVK I32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Move the sign extension of a literal 16-bit constant into a scalar register iff SCC is nonzero.", "description": "Move the sign extension of a literal 16-bit constant into a scalar register iff SCC is nonzero.", "syntax": "s_cmovk_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "if SCC then\nD0.i32 = 32'I(signext(S0.i16))\nendif", "example": "s_cmovk_i32 s0, 0x1234", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPK" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 109, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_cmp_eq_f16", "mnemonic": "s_cmp_eq_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP EQ F16", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is equal to the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is equal to the second scalar input.", "syntax": "s_cmp_eq_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cmp_eq_f32", "mnemonic": "s_cmp_eq_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP EQ F32", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is equal to the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is equal to the second scalar input.", "syntax": "s_cmp_eq_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cmp_eq_i32", "mnemonic": "s_cmp_eq_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP EQ I32", "category": "Comparison", "instructionClass": "scalar", "summary": "Scalar signed-32-bit equality compare, result written to SCC.", "description": "Set SCC to 1 iff the first scalar input is equal to the second scalar input.", "syntax": "s_cmp_eq_i32 S0, S1", "operands": [ { "name": "S0", "desc": "First source SGPR/constant" }, { "name": "S1", "desc": "Second source SGPR/constant" } ], "dataTypes": [ "i32" ], "semantics": "SCC = (S0.i32 == S1.i32).", "example": "s_cmp_eq_i32 s0, s1 // SCC = (s0 == s1)", "exampleSource": null, "encoding": { "format": "SOPC", "widthBits": 32 }, "executionUnit": "Scalar ALU", "registerClasses": [ "SGPR" ], "memorySegment": null, "supportedTargets": [ "gfx942", "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cmp_eq_u32", "mnemonic": "s_cmp_eq_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP EQ U32", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is equal to the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is equal to the second scalar input.", "syntax": "s_cmp_eq_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "SCC = S0.u32 == S1.u32", "example": "s_cmp_eq_u32 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Note that S_CMP_EQ_I32 and S_CMP_EQ_U32 are identical opcodes, but both are provided for symmetry.", "sourcePdfPage": 134, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_cmp_eq_u64", "mnemonic": "s_cmp_eq_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP EQ U64", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is equal to the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is equal to the second scalar input.", "syntax": "s_cmp_eq_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "SCC = S0.u64 == S1.u64", "example": "s_cmp_eq_u64 s[0:1], 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 137, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_cmp_ge_f16", "mnemonic": "s_cmp_ge_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP GE F16", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is greater than or equal to the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is greater than or equal to the second scalar input.", "syntax": "s_cmp_ge_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cmp_ge_f32", "mnemonic": "s_cmp_ge_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP GE F32", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is greater than or equal to the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is greater than or equal to the second scalar input.", "syntax": "s_cmp_ge_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cmp_ge_i32", "mnemonic": "s_cmp_ge_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP GE I32", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is greater than or equal to the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is greater than or equal to the second scalar input.", "syntax": "s_cmp_ge_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "SCC = S0.i32 >= S1.i32", "example": "s_cmp_ge_i32 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 133, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_cmp_ge_u32", "mnemonic": "s_cmp_ge_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP GE U32", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is greater than or equal to the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is greater than or equal to the second scalar input.", "syntax": "s_cmp_ge_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "SCC = S0.u32 >= S1.u32", "example": "s_cmp_ge_u32 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 135, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_cmp_gt_f16", "mnemonic": "s_cmp_gt_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP GT F16", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is greater than the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is greater than the second scalar input.", "syntax": "s_cmp_gt_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cmp_gt_f32", "mnemonic": "s_cmp_gt_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP GT F32", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is greater than the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is greater than the second scalar input.", "syntax": "s_cmp_gt_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cmp_gt_i32", "mnemonic": "s_cmp_gt_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP GT I32", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is greater than the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is greater than the second scalar input.", "syntax": "s_cmp_gt_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "SCC = S0.i32 > S1.i32", "example": "s_cmp_gt_i32 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 133, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_cmp_gt_u32", "mnemonic": "s_cmp_gt_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP GT U32", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is greater than the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is greater than the second scalar input.", "syntax": "s_cmp_gt_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "SCC = S0.u32 > S1.u32", "example": "s_cmp_gt_u32 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 134, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_cmp_le_f16", "mnemonic": "s_cmp_le_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP LE F16", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is less than or equal to the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is less than or equal to the second scalar input.", "syntax": "s_cmp_le_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cmp_le_f32", "mnemonic": "s_cmp_le_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP LE F32", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is less than or equal to the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is less than or equal to the second scalar input.", "syntax": "s_cmp_le_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cmp_le_i32", "mnemonic": "s_cmp_le_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP LE I32", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is less than or equal to the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is less than or equal to the second scalar input.", "syntax": "s_cmp_le_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "SCC = S0.i32 <= S1.i32", "example": "s_cmp_le_i32 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 134, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_cmp_le_u32", "mnemonic": "s_cmp_le_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP LE U32", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is less than or equal to the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is less than or equal to the second scalar input.", "syntax": "s_cmp_le_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "SCC = S0.u32 <= S1.u32", "example": "s_cmp_le_u32 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 135, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_cmp_lg_f16", "mnemonic": "s_cmp_lg_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP LG F16", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is less than or greater than the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is less than or greater than the second scalar input.", "syntax": "s_cmp_lg_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cmp_lg_f32", "mnemonic": "s_cmp_lg_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP LG F32", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is less than or greater than the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is less than or greater than the second scalar input.", "syntax": "s_cmp_lg_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cmp_lg_i32", "mnemonic": "s_cmp_lg_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP LG I32", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is less than or greater than the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is less than or greater than the second scalar input.", "syntax": "s_cmp_lg_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "SCC = S0.i32 <> S1.i32", "example": "s_cmp_lg_i32 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Note that S_CMP_LG_I32 and S_CMP_LG_U32 are identical opcodes, but both are provided for symmetry.", "sourcePdfPage": 133, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_cmp_lg_u32", "mnemonic": "s_cmp_lg_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP LG U32", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is less than or greater than the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is less than or greater than the second scalar input.", "syntax": "s_cmp_lg_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "SCC = S0.u32 <> S1.u32", "example": "s_cmp_lg_u32 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Note that S_CMP_LG_I32 and S_CMP_LG_U32 are identical opcodes, but both are provided for symmetry.", "sourcePdfPage": 134, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_cmp_lg_u64", "mnemonic": "s_cmp_lg_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP LG U64", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is less than or greater than the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is less than or greater than the second scalar input.", "syntax": "s_cmp_lg_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "SCC = S0.u64 <> S1.u64", "example": "s_cmp_lg_u64 s[0:1], 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 137, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_cmp_lt_f16", "mnemonic": "s_cmp_lt_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP LT F16", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is less than the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is less than the second scalar input.", "syntax": "s_cmp_lt_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cmp_lt_f32", "mnemonic": "s_cmp_lt_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP LT F32", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is less than the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is less than the second scalar input.", "syntax": "s_cmp_lt_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cmp_lt_i32", "mnemonic": "s_cmp_lt_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP LT I32", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is less than the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is less than the second scalar input.", "syntax": "s_cmp_lt_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "SCC = S0.i32 < S1.i32", "example": "s_cmp_lt_i32 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], 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null, "sourcePdfPage": 135, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_cmp_neq_f16", "mnemonic": "s_cmp_neq_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP NEQ F16", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is not equal to the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is not equal to the second scalar input.", "syntax": "s_cmp_neq_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cmp_neq_f32", "mnemonic": "s_cmp_neq_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP NEQ F32", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is not equal to the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is not equal to the second scalar input.", "syntax": "s_cmp_neq_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cmp_nge_f16", "mnemonic": "s_cmp_nge_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP NGE F16", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is not greater than or equal to the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is not greater than or equal to the second scalar input.", "syntax": "s_cmp_nge_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cmp_nge_f32", "mnemonic": "s_cmp_nge_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP NGE F32", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is not greater than or equal to the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is not greater than or equal to the second scalar input.", "syntax": "s_cmp_nge_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cmp_ngt_f16", "mnemonic": "s_cmp_ngt_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP NGT F16", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is not greater than the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is not greater than the second scalar input.", "syntax": "s_cmp_ngt_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cmp_ngt_f32", "mnemonic": "s_cmp_ngt_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP NGT F32", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is not greater than the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is not greater than the second scalar input.", "syntax": "s_cmp_ngt_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cmp_nle_f16", "mnemonic": "s_cmp_nle_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP NLE F16", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is not less than or equal to the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is not less than or equal to the second scalar input.", "syntax": "s_cmp_nle_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cmp_nle_f32", "mnemonic": "s_cmp_nle_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP NLE F32", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is not less than or equal to the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is not less than or equal to the second scalar input.", "syntax": "s_cmp_nle_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cmp_nlg_f16", "mnemonic": "s_cmp_nlg_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP NLG F16", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is not less than or greater than the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is not less than or greater than the second scalar input.", "syntax": "s_cmp_nlg_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cmp_nlg_f32", "mnemonic": "s_cmp_nlg_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP NLG F32", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is not less than or greater than the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is not less than or greater than the second scalar input.", "syntax": "s_cmp_nlg_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cmp_nlt_f16", "mnemonic": "s_cmp_nlt_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP NLT F16", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is not less than the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is not less than the second scalar input.", "syntax": "s_cmp_nlt_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cmp_nlt_f32", "mnemonic": "s_cmp_nlt_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP NLT F32", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is not less than the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is not less than the second scalar input.", "syntax": "s_cmp_nlt_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cmp_o_f16", "mnemonic": "s_cmp_o_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP O F16", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is orderable to the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is orderable to the second scalar input.", "syntax": "s_cmp_o_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cmp_o_f32", "mnemonic": "s_cmp_o_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP O F32", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is orderable to the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is orderable to the second scalar input.", "syntax": "s_cmp_o_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cmp_u_f16", "mnemonic": "s_cmp_u_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP U F16", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is not orderable to the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is not orderable to the second scalar input.", "syntax": "s_cmp_u_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cmp_u_f32", "mnemonic": "s_cmp_u_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMP U F32", "category": "Comparison", "instructionClass": "scalar", "summary": "Set SCC to 1 iff the first scalar input is not orderable to the second scalar input.", "description": "Set SCC to 1 iff the first scalar input is not orderable to the second scalar input.", "syntax": "s_cmp_u_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cmpk_eq_i32", "mnemonic": "s_cmpk_eq_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMPK EQ I32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Set SCC to 1 iff scalar input is equal to the sign extension of a literal 16-bit constant.", "description": "Set SCC to 1 iff scalar input is equal to the sign extension of a literal 16-bit constant.", "syntax": "s_cmpk_eq_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "SCC = S0.i32 == 32'I(signext(S1.i16))", "example": "s_cmpk_eq_i32 s0, 0x1234", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPK" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 109, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_cmpk_eq_u32", "mnemonic": "s_cmpk_eq_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMPK EQ U32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Set SCC to 1 iff scalar input is equal to the zero extension of a literal 16-bit constant.", "description": "Set SCC to 1 iff scalar input is equal to the zero extension of a literal 16-bit constant.", "syntax": "s_cmpk_eq_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "SCC = S0.u32 == 32'U(S1.u16)", "example": "s_cmpk_eq_u32 s0, 0x1234", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPK" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 110, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_cmpk_ge_i32", "mnemonic": "s_cmpk_ge_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMPK GE I32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Set SCC to 1 iff scalar input is greater than or equal to the sign extension of a literal 16-bit constant.", "description": "Set SCC to 1 iff scalar input is greater than or equal to the sign extension of a literal 16-bit constant.", "syntax": "s_cmpk_ge_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "SCC = S0.i32 >= 32'I(signext(S1.i16))", "example": "s_cmpk_ge_i32 s0, 0x1234", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPK" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 110, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_cmpk_ge_u32", "mnemonic": "s_cmpk_ge_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMPK GE U32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Set SCC to 1 iff scalar input is greater than or equal to the zero extension of a literal 16-bit constant.", "description": "Set SCC to 1 iff scalar input is greater than or equal to the zero extension of a literal 16-bit constant.", "syntax": "s_cmpk_ge_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "SCC = S0.u32 >= 32'U(S1.u16)", "example": "s_cmpk_ge_u32 s0, 0x1234", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPK" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 111, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_cmpk_gt_i32", "mnemonic": "s_cmpk_gt_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMPK GT I32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Set SCC to 1 iff scalar input is greater than the sign extension of a literal 16-bit constant.", "description": "Set SCC to 1 iff scalar input is greater than the sign extension of a literal 16-bit constant.", "syntax": "s_cmpk_gt_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "SCC = S0.i32 > 32'I(signext(S1.i16))", "example": "s_cmpk_gt_i32 s0, 0x1234", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPK" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 109, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_cmpk_gt_u32", "mnemonic": "s_cmpk_gt_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMPK GT U32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Set SCC to 1 iff scalar input is greater than the zero extension of a literal 16-bit constant.", "description": "Set SCC to 1 iff scalar input is greater than the zero extension of a literal 16-bit constant.", "syntax": "s_cmpk_gt_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "SCC = S0.u32 > 32'U(S1.u16)", "example": "s_cmpk_gt_u32 s0, 0x1234", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPK" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 111, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_cmpk_le_i32", "mnemonic": "s_cmpk_le_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMPK LE I32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Set SCC to 1 iff scalar input is less than or equal to the sign extension of a literal 16-bit constant.", "description": "Set SCC to 1 iff scalar input is less than or equal to the sign extension of a literal 16-bit constant.", "syntax": "s_cmpk_le_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "SCC = S0.i32 <= 32'I(signext(S1.i16))", "example": "s_cmpk_le_i32 s0, 0x1234", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPK" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 110, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_cmpk_le_u32", "mnemonic": "s_cmpk_le_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMPK LE U32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Set SCC to 1 iff scalar input is less than or equal to the zero extension of a literal 16-bit constant.", "description": "Set SCC to 1 iff scalar input is less than or equal to the zero extension of a literal 16-bit constant.", "syntax": "s_cmpk_le_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "SCC = S0.u32 <= 32'U(S1.u16)", "example": "s_cmpk_le_u32 s0, 0x1234", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPK" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 111, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_cmpk_lg_i32", "mnemonic": "s_cmpk_lg_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMPK LG I32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Set SCC to 1 iff scalar input is less than or greater than the sign extension of a literal 16-bit constant.", "description": "Set SCC to 1 iff scalar input is less than or greater than the sign extension of a literal 16-bit constant.", "syntax": "s_cmpk_lg_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "SCC = S0.i32 != 32'I(signext(S1.i16))", "example": "s_cmpk_lg_i32 s0, 0x1234", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPK" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 109, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_cmpk_lg_u32", "mnemonic": "s_cmpk_lg_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMPK LG U32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Set SCC to 1 iff scalar input is less than or greater than the zero extension of a literal 16-bit constant.", "description": "Set SCC to 1 iff scalar input is less than or greater than the zero extension of a literal 16-bit constant.", "syntax": "s_cmpk_lg_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "SCC = S0.u32 != 32'U(S1.u16)", "example": "s_cmpk_lg_u32 s0, 0x1234", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPK" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 110, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_cmpk_lt_i32", "mnemonic": "s_cmpk_lt_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMPK LT I32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Set SCC to 1 iff scalar input is less than the sign extension of a literal 16-bit constant.", "description": "Set SCC to 1 iff scalar input is less than the sign extension of a literal 16-bit constant.", "syntax": "s_cmpk_lt_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "SCC = S0.i32 < 32'I(signext(S1.i16))", "example": "s_cmpk_lt_i32 s0, 0x1234", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPK" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 110, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_cmpk_lt_u32", "mnemonic": "s_cmpk_lt_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CMPK LT U32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Set SCC to 1 iff scalar input is less than the zero extension of a literal 16-bit constant.", "description": "Set SCC to 1 iff scalar input is less than the zero extension of a literal 16-bit constant.", "syntax": "s_cmpk_lt_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "SCC = S0.u32 < 32'U(S1.u16)", "example": "s_cmpk_lt_u32 s0, 0x1234", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPK" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 111, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_cselect_b32", "mnemonic": "s_cselect_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CSELECT B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Select the first input if SCC is true otherwise select the second input, then store the selected input into a scalar register.", "description": "Select the first input if SCC is true otherwise select the second input, then store the selected input into a scalar register.", "syntax": "s_cselect_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.u32 = SCC ? S0.u32 : S1.u32", "example": "s_cselect_b32 s0, 0, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 99, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_cselect_b64", "mnemonic": "s_cselect_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CSELECT B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Select the first input if SCC is true otherwise select the second input, then store the selected input into a scalar register.", "description": "Select the first input if SCC is true otherwise select the second input, then store the selected input into a scalar register.", "syntax": "s_cselect_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "D0.u64 = SCC ? S0.u64 : S1.u64", "example": "s_cselect_b64 s[0:1], 0, s[4:5]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 99, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_ctz_i32_b32", "mnemonic": "s_ctz_i32_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CTZ I32 B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Count the number of trailing \"0\" bits before the first \"1\" in a scalar input and store the result into a scalar register.", "description": "Count the number of trailing \"0\" bits before the first \"1\" in a scalar input and store the result into a scalar register. Store -1 if there are no \"1\" bits in the input.", "syntax": "s_ctz_i32_b32", "operands": [], "dataTypes": [ "b32", "i32" ], "semantics": "", "example": "s_ctz_i32_b32 s5, s1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_ctz_i32_b64", "mnemonic": "s_ctz_i32_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CTZ I32 B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Count the number of trailing \"0\" bits before the first \"1\" in a scalar input and store the result into a scalar register.", "description": "Count the number of trailing \"0\" bits before the first \"1\" in a scalar input and store the result into a scalar register. Store -1 if there are no \"1\" bits in the input.", "syntax": "s_ctz_i32_b64", "operands": [], "dataTypes": [ "b64", "i32" ], "semantics": "", "example": "s_ctz_i32_b64 s105, vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_cvt_f16_f32", "mnemonic": "s_cvt_f16_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CVT F16 F32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Convert from a single-precision float input to a half-precision float value and store the result into a scalar register.", "description": "Convert from a single-precision float input to a half-precision float value and store the result into a scalar register.", "syntax": "s_cvt_f16_f32", "operands": [], "dataTypes": [ "f16", "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cvt_f32_f16", "mnemonic": "s_cvt_f32_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CVT F32 F16", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Convert from a half-precision float input to a single-precision float value and store the result into a scalar register.", "description": "Convert from a half-precision float input to a single-precision float value and store the result into a scalar register.", "syntax": "s_cvt_f32_f16", "operands": [], "dataTypes": [ "f16", "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cvt_f32_i32", "mnemonic": "s_cvt_f32_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CVT F32 I32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Convert from a signed 32-bit integer input to a single-precision float value and store the result into a scalar register.", "description": "Convert from a signed 32-bit integer input to a single-precision float value and store the result into a scalar register.", "syntax": "s_cvt_f32_i32", "operands": [], "dataTypes": [ "f32", "i32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cvt_f32_u32", "mnemonic": "s_cvt_f32_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CVT F32 U32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Convert from an unsigned 32-bit integer input to a single-precision float value and store the result into a scalar register.", "description": "Convert from an unsigned 32-bit integer input to a single-precision float value and store the result into a scalar register.", "syntax": "s_cvt_f32_u32", "operands": [], "dataTypes": [ "f32", "u32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cvt_hi_f32_f16", "mnemonic": "s_cvt_hi_f32_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CVT HI F32 F16", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Convert from a half-precision float value in the high 16 bits of a scalar input to a single-precision float value and store the result into a scalar…", "description": "Convert from a half-precision float value in the high 16 bits of a scalar input to a single-precision float value and store the result into a scalar register.", "syntax": "s_cvt_hi_f32_f16", "operands": [], "dataTypes": [ "f16", "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cvt_i32_f32", "mnemonic": "s_cvt_i32_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CVT I32 F32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Convert from a single-precision float input to a signed 32-bit integer value and store the result into a scalar register.", "description": "Convert from a single-precision float input to a signed 32-bit integer value and store the result into a scalar register.", "syntax": "s_cvt_i32_f32", "operands": [], "dataTypes": [ "f32", "i32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cvt_pk_rtz_f16_f32", "mnemonic": "s_cvt_pk_rtz_f16_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CVT PK RTZ F16 F32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Convert two single-precision float inputs into a packed half-precision float result using round toward zero semantics (ignore the current rounding…", "description": "Convert two single-precision float inputs into a packed half-precision float result using round toward zero semantics (ignore the current rounding mode), and store the result into a scalar register.", "syntax": "s_cvt_pk_rtz_f16_f32", "operands": [], "dataTypes": [ "f16", "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_cvt_u32_f32", "mnemonic": "s_cvt_u32_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S CVT U32 F32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Convert from a single-precision float input to an unsigned 32-bit integer value and store the result into a scalar register.", "description": "Convert from a single-precision float input to an unsigned 32-bit integer value and store the result into a scalar register.", "syntax": "s_cvt_u32_f32", "operands": [], "dataTypes": [ "f32", "u32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_dcache_inv", "mnemonic": "s_dcache_inv", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S DCACHE INV", "category": "Scalar Memory", "instructionClass": "scalar", "summary": "Invalidate the scalar (L0) data cache.", "description": "Invalidate the scalar (L0) data cache.", "syntax": "s_dcache_inv", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SMEM" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 154, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.s_dcache_inv_vol", "mnemonic": "s_dcache_inv_vol", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S DCACHE INV VOL", "category": "Scalar Memory", "instructionClass": "scalar", "summary": "Invalidate the scalar (L0) data cache volatile lines.", "description": "Invalidate the scalar (L0) data cache volatile lines.", "syntax": "s_dcache_inv_vol", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SMEM" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 154, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.s_dcache_wb", "mnemonic": "s_dcache_wb", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S DCACHE WB", "category": "Scalar Memory", "instructionClass": "scalar", "summary": "Write back dirty data in the scalar (L0) data cache.", "description": "Write back dirty data in the scalar (L0) data cache.", "syntax": "s_dcache_wb", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SMEM" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 154, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.s_dcache_wb_vol", "mnemonic": "s_dcache_wb_vol", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S DCACHE WB VOL", "category": "Scalar Memory", "instructionClass": "scalar", "summary": "Write back dirty data in the scalar (L0) data cache volatile lines.", "description": "Write back dirty data in the scalar (L0) data cache volatile lines.", "syntax": "s_dcache_wb_vol", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SMEM" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 154, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.s_decperflevel", "mnemonic": "s_decperflevel", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S DECPERFLEVEL", "category": "Branch & Control", "instructionClass": "scalar", "summary": "Decrement performance counter specified in SIMM16[3:0] by 1.", "description": "Decrement performance counter specified in SIMM16[3:0] by 1.", "syntax": "s_decperflevel", "operands": [], "dataTypes": [], "semantics": "", "example": "s_decperflevel 0x0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 143, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_delay_alu", "mnemonic": "s_delay_alu", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S DELAY ALU", "category": "Branch & Control", "instructionClass": "scalar", "summary": "Insert delay between dependent SALU/VALU instructions.", "description": "Insert delay between dependent SALU/VALU instructions.", "syntax": "s_delay_alu", "operands": [], "dataTypes": [], "semantics": "", "example": "s_delay_alu 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_endpgm", "mnemonic": "s_endpgm", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ENDPGM", "category": "Branch & Control", "instructionClass": "scalar", "summary": "End of program; terminate wavefront.", "description": "End of program; terminate wavefront. The hardware implicitly executes S_WAITCNT 0 before executing this instruction. See S_ENDPGM_SAVED for the context-switch version of this instruction.", "syntax": "s_endpgm", "operands": [], "dataTypes": [], "semantics": "", "example": "s_endpgm 1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 138, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_endpgm_saved", "mnemonic": "s_endpgm_saved", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ENDPGM SAVED", "category": "Branch & Control", "instructionClass": "scalar", "summary": "End of program; signal that a wave has been saved by the context-switch trap handler and terminate wavefront.", "description": "End of program; signal that a wave has been saved by the context-switch trap handler and terminate wavefront. The hardware implicitly executes S_WAITCNT 0 before executing this instruction. See S_ENDPGM for additional variants.", "syntax": "s_endpgm_saved", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 144, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.s_ff0_i32_b32", "mnemonic": "s_ff0_i32_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S FF0 I32 B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Count the number of trailing \"1\" bits before the first \"0\" in a scalar input and store the result into a scalar register.", "description": "Count the number of trailing \"1\" bits before the first \"0\" in a scalar input and store the result into a scalar register. Store -1 if there are no \"0\" bits in the input.", "syntax": "s_ff0_i32_b32", "operands": [], "dataTypes": [ "b32", "i32" ], "semantics": "tmp = -1;\n// Set if no zeros are found\nfor i in 0 : 31 do\n// Search from LSB\nif S0.u32[i] == 1'0U then\ntmp = i;\nbreak\nendif\nendfor;\nD0.i32 = tmp", "example": "S_FF0_I32_B32(0xaaaaaaaa) => 0\nS_FF0_I32_B32(0x55555555) => 1\nS_FF0_I32_B32(0x00000000) => 0\nS_FF0_I32_B32(0xffffffff) => 0xffffffff", "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 118, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.s_ff0_i32_b64", "mnemonic": "s_ff0_i32_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S FF0 I32 B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Count the number of trailing \"1\" bits before the first \"0\" in a scalar input and store the result into a scalar register.", "description": "Count the number of trailing \"1\" bits before the first \"0\" in a scalar input and store the result into a scalar register. Store -1 if there are no \"0\" bits in the input.", "syntax": "s_ff0_i32_b64", "operands": [], "dataTypes": [ "b64", "i32" ], "semantics": "tmp = -1;\n// Set if no zeros are found\nfor i in 0 : 63 do\n// Search from LSB\nif S0.u64[i] == 1'0U then\ntmp = i;\nbreak\nendif\nendfor;\nD0.i32 = tmp", "example": null, "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 119, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.s_ff1_i32_b32", "mnemonic": "s_ff1_i32_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S FF1 I32 B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Count the number of trailing \"0\" bits before the first \"1\" in a scalar input and store the result into a scalar register.", "description": "Count the number of trailing \"0\" bits before the first \"1\" in a scalar input and store the result into a scalar register. Store -1 if there are no \"1\" bits in the input.", "syntax": "s_ff1_i32_b32", "operands": [], "dataTypes": [ "b32", "i32" ], "semantics": "tmp = -1;\n// Set if no ones are found\nfor i in 0 : 31 do\n// Search from LSB\nif S0.u32[i] == 1'1U then\ntmp = i;\nbreak\nendif\nendfor;\nD0.i32 = tmp", "example": "S_FF1_I32_B32(0xaaaaaaaa) => 1\nS_FF1_I32_B32(0x55555555) => 0\nS_FF1_I32_B32(0x00000000) => 0xffffffff\nS_FF1_I32_B32(0xffffffff) => 0", "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 119, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.s_ff1_i32_b64", "mnemonic": "s_ff1_i32_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S FF1 I32 B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Count the number of trailing \"0\" bits before the first \"1\" in a scalar input and store the result into a scalar register.", "description": "Count the number of trailing \"0\" bits before the first \"1\" in a scalar input and store the result into a scalar register. Store -1 if there are no \"1\" bits in the input.", "syntax": "s_ff1_i32_b64", "operands": [], "dataTypes": [ "b64", "i32" ], "semantics": "tmp = -1;\n// Set if no ones are found\nfor i in 0 : 63 do\n// Search from LSB\nif S0.u64[i] == 1'1U then\ntmp = i;\nbreak\nendif\nendfor;\nD0.i32 = tmp", "example": "s_ff1_i32_b64 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 120, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_flbit_i32", "mnemonic": "s_flbit_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S FLBIT I32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Count the number of leading bits that are the same as the sign bit of a scalar input and store the result into a scalar register.", "description": "Count the number of leading bits that are the same as the sign bit of a scalar input and store the result into a scalar register. Store -1 if all input bits are the same.", "syntax": "s_flbit_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "tmp = -1;\n// Set if all bits are the same\nfor i in 1 : 31 do\n// Search from MSB\nif S0.u32[31 - i] != S0.u32[31] then\ntmp = i;\nbreak\nendif\nendfor;\nD0.i32 = tmp", "example": "S_FLBIT_I32(0x00000000) => 0xffffffff\nS_FLBIT_I32(0x0000cccc) => 16\nS_FLBIT_I32(0xffff3333) => 16\nS_FLBIT_I32(0x7fffffff) => 1", "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 121, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.s_flbit_i32_b32", "mnemonic": "s_flbit_i32_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S FLBIT I32 B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Count the number of leading \"0\" bits before the first \"1\" in a scalar input and store the result into a scalar register.", "description": "Count the number of leading \"0\" bits before the first \"1\" in a scalar input and store the result into a scalar register. Store -1 if there are no \"1\" bits.", "syntax": "s_flbit_i32_b32", "operands": [], "dataTypes": [ "b32", "i32" ], "semantics": "tmp = -1;\n// Set if no ones are found\nfor i in 0 : 31 do\n// Search from MSB\nif S0.u32[31 - i] == 1'1U then\ntmp = i;\nbreak\nendif\nendfor;\nD0.i32 = tmp", "example": "S_FLBIT_I32_B32(0x00000000) => 0xffffffff\nS_FLBIT_I32_B32(0x0000cccc) => 16\nS_FLBIT_I32_B32(0xffff3333) => 0\nS_FLBIT_I32_B32(0x7fffffff) => 1", "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 120, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.s_flbit_i32_b64", "mnemonic": "s_flbit_i32_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S FLBIT I32 B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Count the number of leading \"0\" bits before the first \"1\" in a scalar input and store the result into a scalar register.", "description": "Count the number of leading \"0\" bits before the first \"1\" in a scalar input and store the result into a scalar register. Store -1 if there are no \"1\" bits.", "syntax": "s_flbit_i32_b64", "operands": [], "dataTypes": [ "b64", "i32" ], "semantics": "tmp = -1;\n// Set if no ones are found\nfor i in 0 : 63 do\n// Search from MSB\nif S0.u64[63 - i] == 1'1U then\ntmp = i;\nbreak\nendif\nendfor;\nD0.i32 = tmp", "example": "s_flbit_i32_b64 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 121, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_flbit_i32_i64", "mnemonic": "s_flbit_i32_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S FLBIT I32 I64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Count the number of leading bits that are the same as the sign bit of a scalar input and store the result into a scalar register.", "description": "Count the number of leading bits that are the same as the sign bit of a scalar input and store the result into a scalar register. Store -1 if all input bits are the same.", "syntax": "s_flbit_i32_i64", "operands": [], "dataTypes": [ "i32", "i64" ], "semantics": "tmp = -1;\n// Set if all bits are the same\nfor i in 1 : 63 do\n// Search from MSB\nif S0.u64[63 - i] != S0.u64[63] then\ntmp = i;\nbreak\nendif\nendfor;\nD0.i32 = tmp", "example": "s_flbit_i32_i64 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 122, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_floor_f16", "mnemonic": "s_floor_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S FLOOR F16", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Round the half-precision float input down to previous integer and store the result in floating point format into a scalar register.", "description": "Round the half-precision float input down to previous integer and store the result in floating point format into a scalar register.", "syntax": "s_floor_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_floor_f32", "mnemonic": "s_floor_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S FLOOR F32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Round the single-precision float input down to previous integer and store the result in floating point format into a scalar register.", "description": "Round the single-precision float input down to previous integer and store the result in floating point format into a scalar register.", "syntax": "s_floor_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_get_barrier_state", "mnemonic": "s_get_barrier_state", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S GET BARRIER STATE", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "AMDGPU SOP1 scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "s_get_barrier_state", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.s_get_pc_i64", "mnemonic": "s_get_pc_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S GET PC I64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "AMDGPU SOP1 scalar instruction operating on i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "s_get_pc_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.s_get_shader_cycles_u64", "mnemonic": "s_get_shader_cycles_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S GET SHADER CYCLES U64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "AMDGPU SOP1 scalar instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "s_get_shader_cycles_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.s_get_waveid_in_workgroup", "mnemonic": "s_get_waveid_in_workgroup", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S GET WAVEID IN WORKGROUP", "category": "Scalar Memory", "instructionClass": "scalar", "summary": "Return the wave's ID within a workgroup 0-(N-1).", "description": "Return the wave's ID within a workgroup 0-(N-1). Return zero if wave is not in a workgroup. ID reflects the order in which waves were created within each workgroup.", "syntax": "s_get_waveid_in_workgroup", "operands": [], "dataTypes": [], "semantics": "", "example": "s_get_waveid_in_workgroup s0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SMEM" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_getpc_b64", "mnemonic": "s_getpc_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S GETPC B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Store the address of the next instruction to a scalar register.", "description": "Store the address of the next instruction to a scalar register. The byte address of the instruction immediately following this instruction is saved to the destination.", "syntax": "s_getpc_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "D0.i64 = PC + 4LL", "example": "s_getpc_b64 vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "This instruction must be 4 bytes.", "sourcePdfPage": 123, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_gl1_inv", "mnemonic": "s_gl1_inv", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S GL1 INV", "category": "Scalar Memory", "instructionClass": "scalar", "summary": "Invalidate the GL1 cache only.", "description": "Invalidate the GL1 cache only.", "syntax": "s_gl1_inv", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SMEM" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_icache_inv", "mnemonic": "s_icache_inv", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ICACHE INV", "category": "Branch & Control", "instructionClass": "scalar", "summary": "Invalidate entire first level instruction cache.", "description": "Invalidate entire first level instruction cache. There must be 16 separate S_NOP instructions or a jump/branch instruction after this instruction to ensure the internal instruction buffers are also invalidated.", "syntax": "s_icache_inv", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 143, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.s_incperflevel", "mnemonic": "s_incperflevel", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S INCPERFLEVEL", "category": "Branch & Control", "instructionClass": "scalar", "summary": "Increment performance counter specified in SIMM16[3:0] by 1.", "description": "Increment performance counter specified in SIMM16[3:0] by 1.", "syntax": "s_incperflevel", "operands": [], "dataTypes": [], "semantics": "", "example": "s_incperflevel 0x0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 143, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_load_dword", "mnemonic": "s_load_dword", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S LOAD DWORD", "category": "Scalar Memory", "instructionClass": "scalar", "summary": "Load one 32-bit dword from memory into a scalar register, wavefront-uniform.", "description": "Load 32 bits of data from the scalar memory into a scalar register.", "syntax": "s_load_dword SDST, SBASE, offset", "operands": [ { "name": "SDST", "desc": "Destination SGPR" }, { "name": "SBASE", "desc": "Base address (SGPR pair)" }, { "name": "offset", "desc": "Immediate or SGPR offset" } ], "dataTypes": [], "semantics": "SDST = *(SBASE + offset); intended for uniform (not per-lane-varying) addresses such as descriptors and kernel arguments.", "example": "s_load_dword s4, s[8:9], 0x10 // s4 = *(s[8:9] + 0x10)", "exampleSource": null, "encoding": { "format": "SMEM", "widthBits": 32 }, "executionUnit": "Scalar Memory Unit", "registerClasses": [ "SGPR" ], "memorySegment": "uniform/constant", "supportedTargets": [ "gfx942", "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_lshl1_add_u32", "mnemonic": "s_lshl1_add_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S LSHL1 ADD U32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate the logical shift left of the first input by 1, then add the second input, store the result into a scalar register and set SCC iff the…", "description": "Calculate the logical shift left of the first input by 1, then add the second input, store the result into a scalar register and set SCC iff the summation results in an unsigned overflow.", "syntax": "s_lshl1_add_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "tmp = (64'U(S0.u32) << 1U) + 64'U(S1.u32);\nSCC = tmp >= 0x100000000ULL ? 1'1U : 1'0U;\n// unsigned overflow.\nD0.u32 = tmp.u32", "example": "s_lshl1_add_u32 s0, 0, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 107, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_lshl2_add_u32", "mnemonic": "s_lshl2_add_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S LSHL2 ADD U32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate the logical shift left of the first input by 2, then add the second input, store the result into a scalar register and set SCC iff the…", "description": "Calculate the logical shift left of the first input by 2, then add the second input, store the result into a scalar register and set SCC iff the summation results in an unsigned overflow.", "syntax": "s_lshl2_add_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "tmp = (64'U(S0.u32) << 2U) + 64'U(S1.u32);\nSCC = tmp >= 0x100000000ULL ? 1'1U : 1'0U;\n// unsigned overflow.\nD0.u32 = tmp.u32", "example": "s_lshl2_add_u32 s0, 0, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 107, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_lshl3_add_u32", "mnemonic": "s_lshl3_add_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S LSHL3 ADD U32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate the logical shift left of the first input by 3, then add the second input, store the result into a scalar register and set SCC iff the…", "description": "Calculate the logical shift left of the first input by 3, then add the second input, store the result into a scalar register and set SCC iff the summation results in an unsigned overflow.", "syntax": "s_lshl3_add_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "tmp = (64'U(S0.u32) << 3U) + 64'U(S1.u32);\nSCC = tmp >= 0x100000000ULL ? 1'1U : 1'0U;\n// unsigned overflow.\nD0.u32 = tmp.u32", "example": "s_lshl3_add_u32 s0, 0, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 107, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_lshl4_add_u32", "mnemonic": "s_lshl4_add_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S LSHL4 ADD U32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate the logical shift left of the first input by 4, then add the second input, store the result into a scalar register and set SCC iff the…", "description": "Calculate the logical shift left of the first input by 4, then add the second input, store the result into a scalar register and set SCC iff the summation results in an unsigned overflow.", "syntax": "s_lshl4_add_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "tmp = (64'U(S0.u32) << 4U) + 64'U(S1.u32);\nSCC = tmp >= 0x100000000ULL ? 1'1U : 1'0U;\n// unsigned overflow.\nD0.u32 = tmp.u32", "example": "s_lshl4_add_u32 s0, 0, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 108, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_lshl_b32", "mnemonic": "s_lshl_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S LSHL B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Given a shift count in the second scalar input, calculate the logical shift left of the first scalar input, store the result into a scalar register…", "description": "Given a shift count in the second scalar input, calculate the logical shift left of the first scalar input, store the result into a scalar register and set SCC iff the result is nonzero.", "syntax": "s_lshl_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.u32 = (S0.u32 << S1[4 : 0].u32);\nSCC = D0.u32 != 0U", "example": "s_lshl_b32 s0, 0, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 103, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_lshl_b64", "mnemonic": "s_lshl_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S LSHL B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Given a shift count in the second scalar input, calculate the logical shift left of the first scalar input, store the result into a scalar register…", "description": "Given a shift count in the second scalar input, calculate the logical shift left of the first scalar input, store the result into a scalar register and set SCC iff the result is nonzero.", "syntax": "s_lshl_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "D0.u64 = (S0.u64 << S1[5 : 0].u32);\nSCC = D0.u64 != 0ULL", "example": "s_lshl_b64 s[0:1], 0, s4", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 103, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_lshr_b32", "mnemonic": "s_lshr_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S LSHR B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Given a shift count in the second scalar input, calculate the logical shift right of the first scalar input, store the result into a scalar register…", "description": "Given a shift count in the second scalar input, calculate the logical shift right of the first scalar input, store the result into a scalar register and set SCC iff the result is nonzero.", "syntax": "s_lshr_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.u32 = (S0.u32 >> S1[4 : 0].u32);\nSCC = D0.u32 != 0U", "example": "s_lshr_b32 s0, 0, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 103, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_lshr_b64", "mnemonic": "s_lshr_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S LSHR B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Given a shift count in the second scalar input, calculate the logical shift right of the first scalar input, store the result into a scalar register…", "description": "Given a shift count in the second scalar input, calculate the logical shift right of the first scalar input, store the result into a scalar register and set SCC iff the result is nonzero.", "syntax": "s_lshr_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "D0.u64 = (S0.u64 >> S1[5 : 0].u32);\nSCC = D0.u64 != 0ULL", "example": "s_lshr_b64 s[0:1], 0, s4", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 103, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_max_f16", "mnemonic": "s_max_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MAX F16", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Select the maximum of two half-precision float inputs and store the selected value into a scalar register.", "description": "Select the maximum of two half-precision float inputs and store the selected value into a scalar register.", "syntax": "s_max_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_max_f32", "mnemonic": "s_max_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MAX F32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Select the maximum of two single-precision float inputs and store the selected value into a scalar register.", "description": "Select the maximum of two single-precision float inputs and store the selected value into a scalar register.", "syntax": "s_max_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_max_i32", "mnemonic": "s_max_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MAX I32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Select the maximum of two signed 32-bit integer inputs, store the selected value into a scalar register and set SCC iff the first value is selected.", "description": "Select the maximum of two signed 32-bit integer inputs, store the selected value into a scalar register and set SCC iff the first value is selected.", "syntax": "s_max_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "SCC = S0.i32 >= S1.i32;\nD0.i32 = SCC ? S0.i32 : S1.i32", "example": "s_max_i32 s0, 0, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 98, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_max_num_f16", "mnemonic": "s_max_num_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MAX NUM F16", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Select the IEEE maximumNumber() of two half-precision float inputs and store the selected value into a scalar register.", "description": "Select the IEEE maximumNumber() of two half-precision float inputs and store the selected value into a scalar register.", "syntax": "s_max_num_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_max_num_f32", "mnemonic": "s_max_num_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MAX NUM F32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Select the IEEE maximumNumber() of two single-precision float inputs and store the selected value into a scalar register.", "description": "Select the IEEE maximumNumber() of two single-precision float inputs and store the selected value into a scalar register.", "syntax": "s_max_num_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_max_u32", "mnemonic": "s_max_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MAX U32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Select the maximum of two unsigned 32-bit integer inputs, store the selected value into a scalar register and set SCC iff the first value is selected.", "description": "Select the maximum of two unsigned 32-bit integer inputs, store the selected value into a scalar register and set SCC iff the first value is selected.", "syntax": "s_max_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "SCC = S0.u32 >= S1.u32;\nD0.u32 = SCC ? S0.u32 : S1.u32", "example": "s_max_u32 s0, 0, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 99, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_maximum_f16", "mnemonic": "s_maximum_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MAXIMUM F16", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Select the IEEE maximum() of two half-precision float inputs and store the selected value into a scalar register.", "description": "Select the IEEE maximum() of two half-precision float inputs and store the selected value into a scalar register.", "syntax": "s_maximum_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_maximum_f32", "mnemonic": "s_maximum_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MAXIMUM F32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Select the IEEE maximum() of two single-precision float inputs and store the selected value into a scalar register.", "description": "Select the IEEE maximum() of two single-precision float inputs and store the selected value into a scalar register.", "syntax": "s_maximum_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_memrealtime", "mnemonic": "s_memrealtime", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MEMREALTIME", "category": "Scalar Memory", "instructionClass": "scalar", "summary": "Return current 64-bit RTC.", "description": "Return current 64-bit RTC.", "syntax": "s_memrealtime", "operands": [], "dataTypes": [], "semantics": "", "example": "s_memrealtime vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SMEM" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 155, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_memtime", "mnemonic": "s_memtime", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MEMTIME", "category": "Scalar Memory", "instructionClass": "scalar", "summary": "Return current 64-bit timestamp.", "description": "Return current 64-bit timestamp.", "syntax": "s_memtime", "operands": [], "dataTypes": [], "semantics": "", "example": "s_memtime vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SMEM" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 154, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_min_f16", "mnemonic": "s_min_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MIN F16", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Select the minimum of two half-precision float inputs and store the selected value into a scalar register.", "description": "Select the minimum of two half-precision float inputs and store the selected value into a scalar register.", "syntax": "s_min_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_min_f32", "mnemonic": "s_min_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MIN F32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Select the minimum of two single-precision float inputs and store the selected value into a scalar register.", "description": "Select the minimum of two single-precision float inputs and store the selected value into a scalar register.", "syntax": "s_min_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_min_i32", "mnemonic": "s_min_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MIN I32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Select the minimum of two signed 32-bit integer inputs, store the selected value into a scalar register and set SCC iff the first value is selected.", "description": "Select the minimum of two signed 32-bit integer inputs, store the selected value into a scalar register and set SCC iff the first value is selected.", "syntax": "s_min_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "SCC = S0.i32 < S1.i32;\nD0.i32 = SCC ? S0.i32 : S1.i32", "example": "s_min_i32 s0, 0, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 98, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_min_num_f16", "mnemonic": "s_min_num_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MIN NUM F16", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Select the IEEE minimumNumber() of two half-precision float inputs and store the selected value into a scalar register.", "description": "Select the IEEE minimumNumber() of two half-precision float inputs and store the selected value into a scalar register.", "syntax": "s_min_num_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_min_num_f32", "mnemonic": "s_min_num_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MIN NUM F32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Select the IEEE minimumNumber() of two single-precision float inputs and store the selected value into a scalar register.", "description": "Select the IEEE minimumNumber() of two single-precision float inputs and store the selected value into a scalar register.", "syntax": "s_min_num_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_min_u32", "mnemonic": "s_min_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MIN U32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Select the minimum of two unsigned 32-bit integer inputs, store the selected value into a scalar register and set SCC iff the first value is selected.", "description": "Select the minimum of two unsigned 32-bit integer inputs, store the selected value into a scalar register and set SCC iff the first value is selected.", "syntax": "s_min_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "SCC = S0.u32 < S1.u32;\nD0.u32 = SCC ? S0.u32 : S1.u32", "example": "s_min_u32 s0, 0, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 98, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_minimum_f16", "mnemonic": "s_minimum_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MINIMUM F16", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Select the IEEE minimum() of two half-precision float inputs and store the selected value into a scalar register.", "description": "Select the IEEE minimum() of two half-precision float inputs and store the selected value into a scalar register.", "syntax": "s_minimum_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_minimum_f32", "mnemonic": "s_minimum_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MINIMUM F32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Select the IEEE minimum() of two single-precision float inputs and store the selected value into a scalar register.", "description": "Select the IEEE minimum() of two single-precision float inputs and store the selected value into a scalar register.", "syntax": "s_minimum_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_monitor_sleep", "mnemonic": "s_monitor_sleep", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MONITOR SLEEP", "category": "Branch & Control", "instructionClass": "scalar", "summary": "AMDGPU SOPP scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "s_monitor_sleep", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.s_mov_b32", "mnemonic": "s_mov_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MOV B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Move scalar input into a scalar register.", "description": "Move scalar input into a scalar register.", "syntax": "s_mov_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.b32 = S0.b32", "example": "s_mov_b32 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 115, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_mov_b64", "mnemonic": "s_mov_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MOV B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Move scalar input into a scalar register.", "description": "Move scalar input into a scalar register.", "syntax": "s_mov_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "D0.b64 = S0.b64", "example": "s_mov_b64 s[0:1], 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 115, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_movk_i32", "mnemonic": "s_movk_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MOVK I32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Sign extend a literal 16-bit constant and store the result into a scalar register.", "description": "Sign extend a literal 16-bit constant and store the result into a scalar register.", "syntax": "s_movk_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "D0.i32 = 32'I(signext(S0.i16))", "example": "s_movk_i32 s0, 0x1234", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPK" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 109, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_movreld_b32", "mnemonic": "s_movreld_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MOVRELD B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Move data from a scalar input into a relatively-indexed scalar register.", "description": "Move data from a scalar input into a relatively-indexed scalar register.", "syntax": "s_movreld_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "addr = DST.u32;\n// Raw value from instruction\naddr += M0.u32[31 : 0];\nSGPR[addr].b32 = S0.b32", "example": "s_movreld_b32 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Example: The following instruction sequence performs the move s15 <= s7: s_mov_b32 m0, 10 s_movreld_b32 s5, s7", "sourcePdfPage": 128, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_movreld_b64", "mnemonic": "s_movreld_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MOVRELD B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Move data from a scalar input into a relatively-indexed scalar register.", "description": "Move data from a scalar input into a relatively-indexed scalar register. The index in M0.u and the operand address in DST.u must be even for this operation.", "syntax": "s_movreld_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "addr = DST.u32;\n// Raw value from instruction\naddr += M0.u32[31 : 0];\nSGPR[addr].b64 = S0.b64", "example": "s_movreld_b64 s[0:1], 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 128, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_movrels_b32", "mnemonic": "s_movrels_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MOVRELS B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Move data from a relatively-indexed scalar register into another scalar register.", "description": "Move data from a relatively-indexed scalar register into another scalar register.", "syntax": "s_movrels_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "addr = SRC0.u32;\n// Raw value from instruction\naddr += M0.u32[31 : 0];\nD0.b32 = SGPR[addr].b32", "example": "s_movrels_b32 s0, s1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Example: The following instruction sequence performs the move s5 <= s17: s_mov_b32 m0, 10 s_movrels_b32 s5, s7", "sourcePdfPage": 127, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_movrels_b64", "mnemonic": "s_movrels_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MOVRELS B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Move data from a relatively-indexed scalar register into another scalar register.", "description": "Move data from a relatively-indexed scalar register into another scalar register. The index in M0.u and the operand address in SRC0.u must be even for this operation.", "syntax": "s_movrels_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "addr = SRC0.u32;\n// Raw value from instruction\naddr += M0.u32[31 : 0];\nD0.b64 = SGPR[addr].b64", "example": "s_movrels_b64 s[0:1], vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 128, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_movrelsd_2_b32", "mnemonic": "s_movrelsd_2_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MOVRELSD 2 B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Move data from a relatively-indexed scalar register into another relatively-indexed scalar register, using different offsets for each index.", "description": "Move data from a relatively-indexed scalar register into another relatively-indexed scalar register, using different offsets for each index.", "syntax": "s_movrelsd_2_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "s_movrelsd_2_b32 s0, s1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_mul_f16", "mnemonic": "s_mul_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MUL F16", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Multiply two floating point inputs and store the result into a scalar register.", "description": "Multiply two floating point inputs and store the result into a scalar register.", "syntax": "s_mul_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_mul_f32", "mnemonic": "s_mul_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MUL F32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Multiply two floating point inputs and store the result into a scalar register.", "description": "Multiply two floating point inputs and store the result into a scalar register.", "syntax": "s_mul_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_mul_hi_i32", "mnemonic": "s_mul_hi_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MUL HI I32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Multiply two signed integers and store the high 32 bits of the result into a scalar register.", "description": "Multiply two signed integers and store the high 32 bits of the result into a scalar register.", "syntax": "s_mul_hi_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "D0.i32 = 32'I((64'I(S0.i32) * 64'I(S1.i32)) >> 32U)", "example": "s_mul_hi_i32 s0, 0, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 107, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_mul_hi_u32", "mnemonic": "s_mul_hi_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MUL HI U32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Multiply two unsigned integers and store the high 32 bits of the result into a scalar register.", "description": "Multiply two unsigned integers and store the high 32 bits of the result into a scalar register.", "syntax": "s_mul_hi_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "D0.u32 = 32'U((64'U(S0.u32) * 64'U(S1.u32)) >> 32U)", "example": "s_mul_hi_u32 s0, 0, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 106, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_mul_i32", "mnemonic": "s_mul_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MUL I32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Multiply two 32-bit signed scalar operands, wavefront-uniform, low 32 bits of the product.", "description": "Multiply two signed 32-bit integer inputs and store the result into a scalar register.", "syntax": "s_mul_i32 SDST, S0, S1", "operands": [ { "name": "SDST", "desc": "Destination SGPR" }, { "name": "S0", "desc": "First source SGPR/constant" }, { "name": "S1", "desc": "Second source SGPR/constant" } ], "dataTypes": [ "i32" ], "semantics": "SDST = lo32(S0.i32 * S1.i32).", "example": "s_mul_i32 s2, s0, s1 // s2 = low32(s0 * s1)", "exampleSource": null, "encoding": { "format": "SOP2", "widthBits": 32 }, "executionUnit": "Scalar ALU", "registerClasses": [ "SGPR" ], "memorySegment": null, "supportedTargets": [ "gfx942", "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_mul_u64", "mnemonic": "s_mul_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MUL U64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Multiply two unsigned 64-bit integer inputs and store the result into a scalar register.", "description": "Multiply two unsigned 64-bit integer inputs and store the result into a scalar register.", "syntax": "s_mul_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_mulk_i32", "mnemonic": "s_mulk_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S MULK I32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Multiply a scalar input with the sign extension of a literal 16-bit constant and store the result into a scalar register.", "description": "Multiply a scalar input with the sign extension of a literal 16-bit constant and store the result into a scalar register.", "syntax": "s_mulk_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "D0.i32 = D0.i32 * 32'I(signext(S0.i16))", "example": "s_mulk_i32 s0, 0x1234", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPK" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 111, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_nand_b32", "mnemonic": "s_nand_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S NAND B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise NAND on two scalar inputs, store the result into a scalar register and set SCC if the result is nonzero.", "description": "Calculate bitwise NAND on two scalar inputs, store the result into a scalar register and set SCC if the result is nonzero.", "syntax": "s_nand_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.u32 = ~(S0.u32 & S1.u32);\nSCC = D0.u32 != 0U", "example": "s_nand_b32 s0, 0, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 101, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_nand_b64", "mnemonic": "s_nand_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S NAND B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise NAND on two scalar inputs, store the result into a scalar register and set SCC if the result is nonzero.", "description": "Calculate bitwise NAND on two scalar inputs, store the result into a scalar register and set SCC if the result is nonzero.", "syntax": "s_nand_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "D0.u64 = ~(S0.u64 & S1.u64);\nSCC = D0.u64 != 0ULL", "example": "s_nand_b64 s[0:1], 0, s[4:5]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 102, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_nand_saveexec_b32", "mnemonic": "s_nand_saveexec_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S NAND SAVEEXEC B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise NAND on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is…", "description": "Calculate bitwise NAND on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register.", "syntax": "s_nand_saveexec_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "s_nand_saveexec_b32 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_nand_saveexec_b64", "mnemonic": "s_nand_saveexec_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S NAND SAVEEXEC B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise NAND on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is…", "description": "Calculate bitwise NAND on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register.", "syntax": "s_nand_saveexec_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "saveexec = EXEC.u64;\nEXEC.u64 = ~(S0.u64 & EXEC.u64);\nD0.u64 = saveexec.u64;\nSCC = EXEC.u64 != 0ULL", "example": "s_nand_saveexec_b64 s[0:1], 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 126, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_nop", "mnemonic": "s_nop", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S NOP", "category": "Branch & Control", "instructionClass": "scalar", "summary": "Do nothing.", "description": "Do nothing. Delay issue of next instruction by a small, fixed amount. Insert 0..15 wait states based on SIMM16[3:0]. 0x0 means the next instruction can issue on the next clock, 0xf means the next instruction can issue 16 clocks later.", "syntax": "s_nop", "operands": [], "dataTypes": [], "semantics": "for i in 0U : SIMM16.u16[3 : 0].u32 do\nnop()\nendfor", "example": "s_nop 0x0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Examples: s_nop 0 // Wait 1 cycle. s_nop 0xf // Wait 16 cycles.", "sourcePdfPage": 138, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_nor_b32", "mnemonic": "s_nor_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S NOR B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise NOR on two scalar inputs, store the result into a scalar register and set SCC if the result is nonzero.", "description": "Calculate bitwise NOR on two scalar inputs, store the result into a scalar register and set SCC if the result is nonzero.", "syntax": "s_nor_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.u32 = ~(S0.u32 | S1.u32);\nSCC = D0.u32 != 0U", "example": "s_nor_b32 s0, 0, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 102, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_nor_b64", "mnemonic": "s_nor_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S NOR B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise NOR on two scalar inputs, store the result into a scalar register and set SCC if the result is nonzero.", "description": "Calculate bitwise NOR on two scalar inputs, store the result into a scalar register and set SCC if the result is nonzero.", "syntax": "s_nor_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "D0.u64 = ~(S0.u64 | S1.u64);\nSCC = D0.u64 != 0ULL", "example": "s_nor_b64 s[0:1], 0, s[4:5]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 102, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_nor_saveexec_b32", "mnemonic": "s_nor_saveexec_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S NOR SAVEEXEC B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise NOR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is…", "description": "Calculate bitwise NOR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register.", "syntax": "s_nor_saveexec_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "s_nor_saveexec_b32 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_nor_saveexec_b64", "mnemonic": "s_nor_saveexec_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S NOR SAVEEXEC B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise NOR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is…", "description": "Calculate bitwise NOR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register.", "syntax": "s_nor_saveexec_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "saveexec = EXEC.u64;\nEXEC.u64 = ~(S0.u64 | EXEC.u64);\nD0.u64 = saveexec.u64;\nSCC = EXEC.u64 != 0ULL", "example": "s_nor_saveexec_b64 s[0:1], 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 126, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_not_b32", "mnemonic": "s_not_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S NOT B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise negation on a scalar input, store the result into a scalar register and set SCC iff the result is nonzero.", "description": "Calculate bitwise negation on a scalar input, store the result into a scalar register and set SCC iff the result is nonzero.", "syntax": "s_not_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.u32 = ~S0.u32;\nSCC = D0.u32 != 0U", "example": "s_not_b32 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 115, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_not_b64", "mnemonic": "s_not_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S NOT B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise negation on a scalar input, store the result into a scalar register and set SCC iff the result is nonzero.", "description": "Calculate bitwise negation on a scalar input, store the result into a scalar register and set SCC iff the result is nonzero.", "syntax": "s_not_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "D0.u64 = ~S0.u64;\nSCC = D0.u64 != 0ULL", "example": "s_not_b64 s[0:1], 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 116, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_or_b32", "mnemonic": "s_or_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S OR B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise OR on two scalar inputs, store the result into a scalar register and set SCC iff the result is nonzero.", "description": "Calculate bitwise OR on two scalar inputs, store the result into a scalar register and set SCC iff the result is nonzero.", "syntax": "s_or_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.u32 = (S0.u32 | S1.u32);\nSCC = D0.u32 != 0U", "example": "s_or_b32 s0, 0, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 100, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_or_b64", "mnemonic": "s_or_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S OR B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise OR on two scalar inputs, store the result into a scalar register and set SCC iff the result is nonzero.", "description": "Calculate bitwise OR on two scalar inputs, store the result into a scalar register and set SCC iff the result is nonzero.", "syntax": "s_or_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "D0.u64 = (S0.u64 | S1.u64);\nSCC = D0.u64 != 0ULL", "example": "s_or_b64 s[0:1], 0, s[4:5]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 100, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_or_not0_saveexec_b32", "mnemonic": "s_or_not0_saveexec_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S OR NOT0 SAVEEXEC B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise OR on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the…", "description": "Calculate bitwise OR on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register.", "syntax": "s_or_not0_saveexec_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "s_or_not0_saveexec_b32 s5, s1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_or_not0_saveexec_b64", "mnemonic": "s_or_not0_saveexec_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S OR NOT0 SAVEEXEC B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise OR on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the…", "description": "Calculate bitwise OR on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register.", "syntax": "s_or_not0_saveexec_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "s_or_not0_saveexec_b64 vcc, 0.5", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_or_not1_b32", "mnemonic": "s_or_not1_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S OR NOT1 B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise OR with the first input and the negation of the second input, store the result into a scalar register and set SCC if the result is…", "description": "Calculate bitwise OR with the first input and the negation of the second input, store the result into a scalar register and set SCC if the result is nonzero.", "syntax": "s_or_not1_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "s_or_not1_b32 s5, s1, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_or_not1_b64", "mnemonic": "s_or_not1_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S OR NOT1 B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise OR with the first input and the negation of the second input, store the result into a scalar register and set SCC if the result is…", "description": "Calculate bitwise OR with the first input and the negation of the second input, store the result into a scalar register and set SCC if the result is nonzero.", "syntax": "s_or_not1_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "s_or_not1_b64 vcc, -1, -1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_or_not1_saveexec_b32", "mnemonic": "s_or_not1_saveexec_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S OR NOT1 SAVEEXEC B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise OR on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the…", "description": "Calculate bitwise OR on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register.", "syntax": "s_or_not1_saveexec_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "s_or_not1_saveexec_b32 s5, s1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_or_not1_saveexec_b64", "mnemonic": "s_or_not1_saveexec_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S OR NOT1 SAVEEXEC B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise OR on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the…", "description": "Calculate bitwise OR on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register.", "syntax": "s_or_not1_saveexec_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "s_or_not1_saveexec_b64 vcc, 0.5", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_or_saveexec_b32", "mnemonic": "s_or_saveexec_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S OR SAVEEXEC B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise OR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is…", "description": "Calculate bitwise OR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register.", "syntax": "s_or_saveexec_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "s_or_saveexec_b32 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_or_saveexec_b64", "mnemonic": "s_or_saveexec_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S OR SAVEEXEC B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise OR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is…", "description": "Calculate bitwise OR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. The original EXEC mask is saved to the destination SGPRs before the bitwise operation is performed.", "syntax": "s_or_saveexec_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "saveexec = EXEC.u64;\nEXEC.u64 = (S0.u64 | EXEC.u64);\nD0.u64 = saveexec.u64;\nSCC = EXEC.u64 != 0ULL", "example": "s_or_saveexec_b64 s[0:1], 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 125, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_orn1_saveexec_b32", "mnemonic": "s_orn1_saveexec_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ORN1 SAVEEXEC B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise OR on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the…", "description": "Calculate bitwise OR on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register.", "syntax": "s_orn1_saveexec_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "s_orn1_saveexec_b32 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_orn1_saveexec_b64", "mnemonic": "s_orn1_saveexec_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ORN1 SAVEEXEC B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise OR on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the…", "description": "Calculate bitwise OR on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. The original EXEC mask is saved to the destination SGPRs before the bitwise operation is performed.", "syntax": "s_orn1_saveexec_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "saveexec = EXEC.u64;\nEXEC.u64 = (~S0.u64 | EXEC.u64);\nD0.u64 = saveexec.u64;\nSCC = EXEC.u64 != 0ULL", "example": "s_orn1_saveexec_b64 s[0:1], 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 130, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_orn2_b32", "mnemonic": "s_orn2_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ORN2 B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise OR with the first input and the negation of the second input, store the result into a scalar register and set SCC if the result is…", "description": "Calculate bitwise OR with the first input and the negation of the second input, store the result into a scalar register and set SCC if the result is nonzero.", "syntax": "s_orn2_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.u32 = (S0.u32 | ~S1.u32);\nSCC = D0.u32 != 0U", "example": "s_orn2_b32 s0, 0, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 101, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_orn2_b64", "mnemonic": "s_orn2_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ORN2 B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise OR with the first input and the negation of the second input, store the result into a scalar register and set SCC if the result is…", "description": "Calculate bitwise OR with the first input and the negation of the second input, store the result into a scalar register and set SCC if the result is nonzero.", "syntax": "s_orn2_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "D0.u64 = (S0.u64 | ~S1.u64);\nSCC = D0.u64 != 0ULL", "example": "s_orn2_b64 s[0:1], 0, s[4:5]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 101, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_orn2_saveexec_b32", "mnemonic": "s_orn2_saveexec_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ORN2 SAVEEXEC B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise OR on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the…", "description": "Calculate bitwise OR on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register.", "syntax": "s_orn2_saveexec_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "s_orn2_saveexec_b32 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_orn2_saveexec_b64", "mnemonic": "s_orn2_saveexec_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S ORN2 SAVEEXEC B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise OR on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the…", "description": "Calculate bitwise OR on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. The original EXEC mask is saved to the destination SGPRs before the bitwise operation is performed.", "syntax": "s_orn2_saveexec_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "saveexec = EXEC.u64;\nEXEC.u64 = (S0.u64 | ~EXEC.u64);\nD0.u64 = saveexec.u64;\nSCC = EXEC.u64 != 0ULL", "example": "s_orn2_saveexec_b64 s[0:1], 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 126, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_pack_hh_b32_b16", "mnemonic": "s_pack_hh_b32_b16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S PACK HH B32 B16", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Pack two 16-bit scalar values into a scalar register.", "description": "Pack two 16-bit scalar values into a scalar register.", "syntax": "s_pack_hh_b32_b16", "operands": [], "dataTypes": [ "b16", "b32" ], "semantics": "D0 = { S1[31 : 16].u16, S0[31 : 16].u16 }", "example": "s_pack_hh_b32_b16 s0, 0, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 108, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_pack_hl_b32_b16", "mnemonic": "s_pack_hl_b32_b16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S PACK HL B32 B16", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Pack two 16-bit scalar values into a scalar register.", "description": "Pack two 16-bit scalar values into a scalar register.", "syntax": "s_pack_hl_b32_b16", "operands": [], "dataTypes": [ "b16", "b32" ], "semantics": "", "example": "s_pack_hl_b32_b16 s5, s1, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_pack_lh_b32_b16", "mnemonic": "s_pack_lh_b32_b16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S PACK LH B32 B16", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Pack two 16-bit scalar values into a scalar register.", "description": "Pack two 16-bit scalar values into a scalar register.", "syntax": "s_pack_lh_b32_b16", "operands": [], "dataTypes": [ "b16", "b32" ], "semantics": "D0 = { S1[31 : 16].u16, S0[15 : 0].u16 }", "example": "s_pack_lh_b32_b16 s0, 0, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 108, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_pack_ll_b32_b16", "mnemonic": "s_pack_ll_b32_b16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S PACK LL B32 B16", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Pack two 16-bit scalar values into a scalar register.", "description": "Pack two 16-bit scalar values into a scalar register.", "syntax": "s_pack_ll_b32_b16", "operands": [], "dataTypes": [ "b16", "b32" ], "semantics": "D0 = { S1[15 : 0].u16, S0[15 : 0].u16 }", "example": "s_pack_ll_b32_b16 s0, 0, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 108, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_prefetch_data", "mnemonic": "s_prefetch_data", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S PREFETCH DATA", "category": "Scalar Memory", "instructionClass": "scalar", "summary": "Prefetch data into the scalar data cache, relative to a base address provided.", "description": "Prefetch data into the scalar data cache, relative to a base address provided.", "syntax": "s_prefetch_data", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SMEM" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_prefetch_data_pc_rel", "mnemonic": "s_prefetch_data_pc_rel", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S PREFETCH DATA PC REL", "category": "Scalar Memory", "instructionClass": "scalar", "summary": "Prefetch data into the scalar data cache, relative to the current PC address.", "description": "Prefetch data into the scalar data cache, relative to the current PC address.", "syntax": "s_prefetch_data_pc_rel", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SMEM" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_prefetch_inst", "mnemonic": "s_prefetch_inst", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S PREFETCH INST", "category": "Scalar Memory", "instructionClass": "scalar", "summary": "Prefetch instructions into the shader instruction cache, relative to a base address provided.", "description": "Prefetch instructions into the shader instruction cache, relative to a base address provided.", "syntax": "s_prefetch_inst", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SMEM" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_prefetch_inst_pc_rel", "mnemonic": "s_prefetch_inst_pc_rel", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S PREFETCH INST PC REL", "category": "Scalar Memory", "instructionClass": "scalar", "summary": "Prefetch instructions into the shader instruction cache, relative to the current PC address.", "description": "Prefetch instructions into the shader instruction cache, relative to the current PC address.", "syntax": "s_prefetch_inst_pc_rel", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SMEM" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_quadmask_b32", "mnemonic": "s_quadmask_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S QUADMASK B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Reduce a pixel mask from the scalar input into a quad mask, store the result in a scalar register and set SCC iff the result is nonzero.", "description": "Reduce a pixel mask from the scalar input into a quad mask, store the result in a scalar register and set SCC iff the result is nonzero.", "syntax": "s_quadmask_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "tmp = 0U;\nfor i in 0 : 7 do\ntmp[i] = S0.u32[i * 4 +: 4] != 0U\nendfor;\nD0.u32 = tmp;\nSCC = D0.u32 != 0U", "example": "s_quadmask_b32 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "To perform the inverse operation see S_BITREPLICATE_B64_B32.", "sourcePdfPage": 127, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_quadmask_b64", "mnemonic": "s_quadmask_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S QUADMASK B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Reduce a pixel mask from the scalar input into a quad mask, store the result in a scalar register and set SCC iff the result is nonzero.", "description": "Reduce a pixel mask from the scalar input into a quad mask, store the result in a scalar register and set SCC iff the result is nonzero.", "syntax": "s_quadmask_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "tmp = 0ULL;\nfor i in 0 : 15 do\ntmp[i] = S0.u64[i * 4 +: 4] != 0ULL\nendfor;\nD0.u64 = tmp;\nSCC = D0.u64 != 0ULL", "example": "s_quadmask_b64 s[0:1], 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "To perform the inverse operation see S_BITREPLICATE_B64_B32.", "sourcePdfPage": 127, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_rfe_b64", "mnemonic": "s_rfe_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S RFE B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Return from the exception handler.", "description": "Return from the exception handler. Clear the wave's PRIV bit and then jump to an address specified by the scalar input. The argument is a byte address of the instruction to jump to; this address is likely derived from the state passed into the trap handler. This instruction may only be used within a trap handler.", "syntax": "s_rfe_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "WAVE_STATUS.PRIV = 1'0U;\nPC = S0.i64", "example": "s_rfe_b64 vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 124, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_rfe_i64", "mnemonic": "s_rfe_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S RFE I64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "AMDGPU SOP1 scalar instruction operating on i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "s_rfe_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.s_rndne_f16", "mnemonic": "s_rndne_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S RNDNE F16", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Round the half-precision float input to the nearest even integer and store the result in floating point format into a scalar register.", "description": "Round the half-precision float input to the nearest even integer and store the result in floating point format into a scalar register.", "syntax": "s_rndne_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_rndne_f32", "mnemonic": "s_rndne_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S RNDNE F32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Round the single-precision float input to the nearest even integer and store the result in floating point format into a scalar register.", "description": "Round the single-precision float input to the nearest even integer and store the result in floating point format into a scalar register.", "syntax": "s_rndne_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_sendmsg", "mnemonic": "s_sendmsg", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SENDMSG", "category": "Branch & Control", "instructionClass": "scalar", "summary": "Send a message upstream to graphics control hardware. SIMM16[9:0] contains the message type.", "description": "Send a message upstream to graphics control hardware. SIMM16[9:0] contains the message type.", "syntax": "s_sendmsg", "operands": [], "dataTypes": [], "semantics": "", "example": "s_sendmsg 2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 142, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_sendmsghalt", "mnemonic": "s_sendmsghalt", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SENDMSGHALT", "category": "Branch & Control", "instructionClass": "scalar", "summary": "Send a message to upstream control hardware and then HALT the wavefront; see S_SENDMSG for details.", "description": "Send a message to upstream control hardware and then HALT the wavefront; see S_SENDMSG for details.", "syntax": "s_sendmsghalt", "operands": [], "dataTypes": [], "semantics": "", "example": "s_sendmsghalt 0x0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 142, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_set_gpr_idx_idx", "mnemonic": "s_set_gpr_idx_idx", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SET GPR IDX IDX", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Set the index used in vector GPR indexing. S_SET_GPR_IDX_ON, S_SET_GPR_IDX_OFF, S_SET_GPR_IDX_MODE and S_SET_GPR_IDX_IDX are related instructions.", "description": "Set the index used in vector GPR indexing. S_SET_GPR_IDX_ON, S_SET_GPR_IDX_OFF, S_SET_GPR_IDX_MODE and S_SET_GPR_IDX_IDX are related instructions.", "syntax": "s_set_gpr_idx_idx", "operands": [], "dataTypes": [], "semantics": "M0[7 : 0] = S0.u32[7 : 0].b8", "example": null, "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 130, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.s_set_gpr_idx_mode", "mnemonic": "s_set_gpr_idx_mode", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SET GPR IDX MODE", "category": "Branch & Control", "instructionClass": "scalar", "summary": "Modify the mode used for vector GPR indexing.", "description": "Modify the mode used for vector GPR indexing.", "syntax": "s_set_gpr_idx_mode", "operands": [], "dataTypes": [], "semantics": "The raw contents of the source field are read and used to set the enable bits. SIMM16[0] = VSRC0_REL,\nSIMM16[1] = VSRC1_REL, SIMM16[2] = VSRC2_REL and SIMM16[3] = VDST_REL.\nS_SET_GPR_IDX_ON, S_SET_GPR_IDX_OFF, S_SET_GPR_IDX_MODE and S_SET_GPR_IDX_IDX are related\ninstructions.\nM0[15 : 12] = SIMM16.u16[3 : 0].b4", "example": null, "exampleSource": null, "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 145, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.s_set_gpr_idx_off", "mnemonic": "s_set_gpr_idx_off", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SET GPR IDX OFF", "category": "Branch & Control", "instructionClass": "scalar", "summary": "Clear GPR indexing mode.", "description": "Clear GPR indexing mode. Vector operations after this do not perform relative GPR addressing regardless of the contents of M0. This instruction does not modify M0. S_SET_GPR_IDX_ON, S_SET_GPR_IDX_OFF, S_SET_GPR_IDX_MODE and S_SET_GPR_IDX_IDX are related instructions.", "syntax": "s_set_gpr_idx_off", "operands": [], "dataTypes": [], "semantics": "WAVE_MODE.GPR_IDX_EN = 1'0U", "example": null, "exampleSource": null, "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 145, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.s_set_inst_prefetch_distance", "mnemonic": "s_set_inst_prefetch_distance", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SET INST PREFETCH DISTANCE", "category": "Branch & Control", "instructionClass": "scalar", "summary": "Change instruction prefetch mode. This controls how many cachelines ahead of the current PC the shader attempts to prefetch.", "description": "Change instruction prefetch mode. This controls how many cachelines ahead of the current PC the shader attempts to prefetch.", "syntax": "s_set_inst_prefetch_distance", "operands": [], "dataTypes": [], "semantics": "", "example": "s_set_inst_prefetch_distance 0xc1d1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_set_pc_i64", "mnemonic": "s_set_pc_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SET PC I64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "AMDGPU SOP1 scalar instruction operating on i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "s_set_pc_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.s_set_vgpr_msb", "mnemonic": "s_set_vgpr_msb", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SET VGPR MSB", "category": "Branch & Control", "instructionClass": "scalar", "summary": "AMDGPU SOPP scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "s_set_vgpr_msb", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.s_sethalt", "mnemonic": "s_sethalt", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SETHALT", "category": "Branch & Control", "instructionClass": "scalar", "summary": "Set or clear the HALT status bit.", "description": "Set or clear the HALT status bit.", "syntax": "s_sethalt", "operands": [], "dataTypes": [], "semantics": "Set HALT bit to value of SIMM16[0]; 1 = halt, 0 = clear HALT bit. The halt flag is ignored while PRIV == 1 (inside\ntrap handlers) but the shader halts after the handler returns if HALT is still set at that time.", "example": "s_sethalt 0x0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 141, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_setkill", "mnemonic": "s_setkill", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SETKILL", "category": "Branch & Control", "instructionClass": "scalar", "summary": "Kill this wave if the least significant bit of the immediate constant is 1. Used primarily for debugging kill wave host command behavior.", "description": "Kill this wave if the least significant bit of the immediate constant is 1. Used primarily for debugging kill wave host command behavior.", "syntax": "s_setkill", "operands": [], "dataTypes": [], "semantics": "", "example": "s_setkill 0x0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 141, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_setpc_b64", "mnemonic": "s_setpc_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SETPC B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Jump to an address specified in a scalar register. The argument is a byte address of the instruction to jump to.", "description": "Jump to an address specified in a scalar register. The argument is a byte address of the instruction to jump to.", "syntax": "s_setpc_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "PC = S0.i64", "example": "s_setpc_b64 vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 123, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_setprio", "mnemonic": "s_setprio", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SETPRIO", "category": "Branch & Control", "instructionClass": "scalar", "summary": "Change wave user priority.", "description": "Change wave user priority.", "syntax": "s_setprio", "operands": [], "dataTypes": [], "semantics": "User settable wave priority is set to SIMM16[1:0]. 0 = lowest, 3 = highest. The overall wave priority is\n{SPIPrio[1:0], UserPrio[1:0], WaveAge[3:0]}.", "example": "s_setprio 0x0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 142, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_setprio_inc_wg", "mnemonic": "s_setprio_inc_wg", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SETPRIO INC WG", "category": "Branch & Control", "instructionClass": "scalar", "summary": "AMDGPU SOPP scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "s_setprio_inc_wg", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.s_setvskip", "mnemonic": "s_setvskip", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SETVSKIP", "category": "Comparison", "instructionClass": "scalar", "summary": "Enables or disables VSKIP mode.", "description": "Enables or disables VSKIP mode. When VSKIP is enabled, no VOP*/M*BUF/MIMG/DS/FLAT instructions are issued. Note that VSKIPped memory instructions do not manipulate the waitcnt counters; as a result, if there are outstanding memory requests the shader may want to issue S_WAITCNT 0 prior to enabling VSKIP, otherwise the shader must be careful not to count VSKIPped instructions in waitcnt calculations.", "syntax": "s_setvskip", "operands": [], "dataTypes": [], "semantics": "VSKIP = S0.u32[S1.u32[4 : 0]]", "example": "s_setvskip 1, 0 // Enable vskip mode.\ns_setvskip 0, 0 // Disable vskip mode.", "exampleSource": null, "encoding": { "format": "SOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 136, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.s_sext_i32_i16", "mnemonic": "s_sext_i32_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SEXT I32 I16", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Sign extend a signed 16 bit scalar input to 32 bits and store the result into a scalar register.", "description": "Sign extend a signed 16 bit scalar input to 32 bits and store the result into a scalar register.", "syntax": "s_sext_i32_i16", "operands": [], "dataTypes": [ "i16", "i32" ], "semantics": "D0.i32 = 32'I(signext(S0.i16))", "example": "s_sext_i32_i16 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 122, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_sext_i32_i8", "mnemonic": "s_sext_i32_i8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SEXT I32 I8", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Sign extend a signed 8 bit scalar input to 32 bits and store the result into a scalar register.", "description": "Sign extend a signed 8 bit scalar input to 32 bits and store the result into a scalar register.", "syntax": "s_sext_i32_i8", "operands": [], "dataTypes": [ "i32", "i8" ], "semantics": "D0.i32 = 32'I(signext(S0.i8))", "example": "s_sext_i32_i8 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 122, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_sleep", "mnemonic": "s_sleep", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SLEEP", "category": "Branch & Control", "instructionClass": "scalar", "summary": "Cause a wave to sleep for up to ~8000 clocks.", "description": "Cause a wave to sleep for up to ~8000 clocks. The wave sleeps for (64*(SIMM16[6:0]-1) .. 64*SIMM16[6:0]) clocks. The exact amount of delay is approximate. Compare with S_NOP. When SIMM16[6:0] is zero then no sleep occurs.", "syntax": "s_sleep", "operands": [], "dataTypes": [], "semantics": "", "example": "s_sleep 0x0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Examples: s_sleep 0 // Wait for 0 clocks. s_sleep 1 // Wait for 1-64 clocks. s_sleep 2 // Wait for 65-128 clocks.", "sourcePdfPage": 142, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_sleep_var", "mnemonic": "s_sleep_var", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SLEEP VAR", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Cause a wave to sleep for up to ~8000 clocks, or to sleep until an external event wakes the wave up.", "description": "Cause a wave to sleep for up to ~8000 clocks, or to sleep until an external event wakes the wave up.", "syntax": "s_sleep_var", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_soft_wait_bvhcnt", "mnemonic": "s_soft_wait_bvhcnt", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SOFT WAIT BVHCNT", "category": "Branch & Control", "instructionClass": "scalar", "summary": "AMDGPU SOPP scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "s_soft_wait_bvhcnt", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.s_soft_wait_dscnt", "mnemonic": "s_soft_wait_dscnt", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SOFT WAIT DSCNT", "category": "Branch & Control", "instructionClass": "scalar", "summary": "AMDGPU SOPP scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "s_soft_wait_dscnt", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.s_soft_wait_kmcnt", "mnemonic": "s_soft_wait_kmcnt", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SOFT WAIT KMCNT", "category": "Branch & Control", "instructionClass": "scalar", "summary": "AMDGPU SOPP scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "s_soft_wait_kmcnt", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.s_soft_wait_loadcnt", "mnemonic": "s_soft_wait_loadcnt", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SOFT WAIT LOADCNT", "category": "Branch & Control", "instructionClass": "scalar", "summary": "AMDGPU SOPP scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "s_soft_wait_loadcnt", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.s_soft_wait_samplecnt", "mnemonic": "s_soft_wait_samplecnt", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SOFT WAIT SAMPLECNT", "category": "Branch & Control", "instructionClass": "scalar", "summary": "AMDGPU SOPP scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "s_soft_wait_samplecnt", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.s_soft_wait_storecnt", "mnemonic": "s_soft_wait_storecnt", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SOFT WAIT STORECNT", "category": "Branch & Control", "instructionClass": "scalar", "summary": "AMDGPU SOPP scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "s_soft_wait_storecnt", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.s_soft_waitcnt", "mnemonic": "s_soft_waitcnt", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SOFT WAITCNT", "category": "Branch & Control", "instructionClass": "scalar", "summary": "AMDGPU SOPP scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "s_soft_waitcnt", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.s_soft_waitcnt_vscnt", "mnemonic": "s_soft_waitcnt_vscnt", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SOFT WAITCNT VSCNT", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "AMDGPU SOPK scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "s_soft_waitcnt_vscnt", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPK" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.s_sub_co_ci_u32", "mnemonic": "s_sub_co_ci_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SUB CO CI U32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Subtract the second unsigned 32-bit integer input from the first input, subtract the carry-in bit, store the result into a scalar register and store…", "description": "Subtract the second unsigned 32-bit integer input from the first input, subtract the carry-in bit, store the result into a scalar register and store the carry-out bit into SCC.", "syntax": "s_sub_co_ci_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_sub_co_i32", "mnemonic": "s_sub_co_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SUB CO I32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Subtract the second signed 32-bit integer input from the first input, store the result into a scalar register and store the carry-out bit into SCC.", "description": "Subtract the second signed 32-bit integer input from the first input, store the result into a scalar register and store the carry-out bit into SCC.", "syntax": "s_sub_co_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_sub_co_u32", "mnemonic": "s_sub_co_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SUB CO U32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Subtract the second unsigned 32-bit integer input from the first input, store the result into a scalar register and store the carry-out bit into SCC.", "description": "Subtract the second unsigned 32-bit integer input from the first input, store the result into a scalar register and store the carry-out bit into SCC.", "syntax": "s_sub_co_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_sub_f16", "mnemonic": "s_sub_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SUB F16", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Subtract the second floating point input from the first input and store the result in a scalar register.", "description": "Subtract the second floating point input from the first input and store the result in a scalar register.", "syntax": "s_sub_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_sub_f32", "mnemonic": "s_sub_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SUB F32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Subtract the second floating point input from the first input and store the result in a scalar register.", "description": "Subtract the second floating point input from the first input and store the result in a scalar register.", "syntax": "s_sub_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_sub_i32", "mnemonic": "s_sub_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SUB I32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Subtract the second signed 32-bit integer input from the first input, store the result into a scalar register and store the carry-out bit into SCC.", "description": "Subtract the second signed 32-bit integer input from the first input, store the result into a scalar register and store the carry-out bit into SCC.", "syntax": "s_sub_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "tmp = S0.i32 - S1.i32;\nSCC = ((S0.u32[31] != S1.u32[31]) && (S0.u32[31] != tmp.u32[31]));\n// signed overflow.\nD0.i32 = tmp.i32", "example": "s_sub_i32 s0, 0, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "This opcode is not suitable for use with S_SUBB_U32 for implementing 64-bit operations.", "sourcePdfPage": 97, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_sub_nc_u64", "mnemonic": "s_sub_nc_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SUB NC U64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Subtract the second unsigned 64-bit integer input from the first input and store the result into a scalar register.", "description": "Subtract the second unsigned 64-bit integer input from the first input and store the result into a scalar register.", "syntax": "s_sub_nc_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_sub_u32", "mnemonic": "s_sub_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SUB U32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Subtract two 32-bit unsigned scalar operands, wavefront-uniform.", "description": "Subtract the second unsigned 32-bit integer input from the first input, store the result into a scalar register and store the carry-out bit into SCC.", "syntax": "s_sub_u32 SDST, S0, S1", "operands": [ { "name": "SDST", "desc": "Destination SGPR" }, { "name": "S0", "desc": "Minuend SGPR/constant" }, { "name": "S1", "desc": "Subtrahend SGPR/constant" } ], "dataTypes": [ "u32" ], "semantics": "SDST = S0.u32 - S1.u32; SCC = borrow-out.", "example": "s_sub_u32 s2, s0, s1 // s2 = s0 - s1", "exampleSource": null, "encoding": { "format": "SOP2", "widthBits": 32 }, "executionUnit": "Scalar ALU", "registerClasses": [ "SGPR" ], "memorySegment": null, "supportedTargets": [ "gfx942", "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_sub_u64", "mnemonic": "s_sub_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SUB U64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "AMDGPU SOP2 scalar instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "s_sub_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.s_subb_u32", "mnemonic": "s_subb_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SUBB U32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Subtract the second unsigned 32-bit integer input from the first input, subtract the carry-in bit, store the result into a scalar register and store…", "description": "Subtract the second unsigned 32-bit integer input from the first input, subtract the carry-in bit, store the result into a scalar register and store the carry-out bit into SCC.", "syntax": "s_subb_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "tmp = S0.u32 - S1.u32 - SCC.u32;\nSCC = 64'U(S1.u32) + SCC.u64 > 64'U(S0.u32) ? 1'1U : 1'0U;\n// unsigned overflow or carry-out for S_SUBB_U32.\nD0.u32 = tmp.u32", "example": "s_subb_u32 s0, 0, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 98, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_subvector_loop_begin", "mnemonic": "s_subvector_loop_begin", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SUBVECTOR LOOP BEGIN", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Begin execution of a subvector block of code.", "description": "Begin execution of a subvector block of code.", "syntax": "s_subvector_loop_begin", "operands": [], "dataTypes": [], "semantics": "", "example": "s_subvector_loop_begin s0, 0x1234", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPK" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_subvector_loop_end", "mnemonic": "s_subvector_loop_end", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SUBVECTOR LOOP END", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "End execution of a subvector block of code.", "description": "End execution of a subvector block of code.", "syntax": "s_subvector_loop_end", "operands": [], "dataTypes": [], "semantics": "", "example": "s_subvector_loop_end s0, 0x1234", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPK" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_swap_pc_i64", "mnemonic": "s_swap_pc_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SWAP PC I64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "AMDGPU SOP1 scalar instruction operating on i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "s_swap_pc_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.s_swappc_b64", "mnemonic": "s_swappc_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S SWAPPC B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Store the address of the next instruction to a scalar register and then jump to an address specified in the scalar input.", "description": "Store the address of the next instruction to a scalar register and then jump to an address specified in the scalar input. The argument is a byte address of the instruction to jump to. The byte address of the instruction immediately following this instruction is saved to the destination.", "syntax": "s_swappc_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "jump_addr = S0.i64;\nD0.i64 = PC + 4LL;\nPC = jump_addr.i64", "example": "s_swappc_b64 s[0:1], vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "This instruction must be 4 bytes.", "sourcePdfPage": 124, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_trap", "mnemonic": "s_trap", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S TRAP", "category": "Branch & Control", "instructionClass": "scalar", "summary": "Enter the trap handler.", "description": "Enter the trap handler.", "syntax": "s_trap", "operands": [], "dataTypes": [], "semantics": "This instruction may be generated internally as well in response to a host trap (HT = 1) or an exception. TrapID\n0 is reserved for hardware use and should not be used in a shader-generated trap.\nTrapID = SIMM16.u16[7 : 0];\n\"Wait for all instructions to complete\";\n// PC passed into trap handler points to S_TRAP itself,\n// *not* to the next instruction.\n{ TTMP[1], TTMP[0] } = { 3'0, PCRewind[3 : 0], HT[0], TrapID[7 : 0], PC[47 : 0] };\nPC = TBA.i64;\n// trap base address\nWAVE_STATUS.PRIV = 1'1U", "example": "s_trap 0x0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 142, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_trunc_f16", "mnemonic": "s_trunc_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S TRUNC F16", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Compute the integer part of a half-precision float input using round toward zero semantics and store the result in floating point format into a…", "description": "Compute the integer part of a half-precision float input using round toward zero semantics and store the result in floating point format into a scalar register.", "syntax": "s_trunc_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_trunc_f32", "mnemonic": "s_trunc_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S TRUNC F32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Compute the integer part of a single-precision float input using round toward zero semantics and store the result in floating point format into a…", "description": "Compute the integer part of a single-precision float input using round toward zero semantics and store the result in floating point format into a scalar register.", "syntax": "s_trunc_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_ttracedata", "mnemonic": "s_ttracedata", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S TTRACEDATA", "category": "Branch & Control", "instructionClass": "scalar", "summary": "Send M0 as user data to the thread trace stream.", "description": "Send M0 as user data to the thread trace stream.", "syntax": "s_ttracedata", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 143, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.s_wait_alu", "mnemonic": "s_wait_alu", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S WAIT ALU", "category": "Branch & Control", "instructionClass": "scalar", "summary": "Wait for one or more ALU-centric counters to fall below specified values.", "description": "Wait for one or more ALU-centric counters to fall below specified values.", "syntax": "s_wait_alu", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.s_wait_event", "mnemonic": "s_wait_event", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S WAIT EVENT", "category": "Branch & Control", "instructionClass": "scalar", "summary": "Wait for an event to occur or a condition to be satisfied before continuing. The SIMM16 argument specifies which event(s) to wait on.", "description": "Wait for an event to occur or a condition to be satisfied before continuing. The SIMM16 argument specifies which event(s) to wait on.", "syntax": "s_wait_event", "operands": [], "dataTypes": [], "semantics": "", "example": "s_wait_event 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_waitcnt", "mnemonic": "s_waitcnt", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S WAITCNT", "category": "Branch & Control", "instructionClass": "scalar", "summary": "Wait for the counts of outstanding local data share, vector memory and export instructions to be at or below the specified levels.", "description": "Wait for the counts of outstanding local data share, vector memory and export instructions to be at or below the specified levels.", "syntax": "s_waitcnt", "operands": [], "dataTypes": [], "semantics": "SIMM16[3:0] = vmcount (vector memory operations) lower bits [3:0],\nSIMM16[6:4] = export/mem-write-data count,\nSIMM16[11:8] = LGKMcnt (scalar-mem/GDS/LDS count),\nSIMM16[15:14] = vmcount (vector memory operations) upper bits [5:4].", "example": "s_waitcnt 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 141, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_waitcnt_expcnt", "mnemonic": "s_waitcnt_expcnt", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S WAITCNT EXPCNT", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Wait for the EXPCNT counter to be at or below the specified level. The EXPCNT counter tracks the number of outstanding export events.", "description": "Wait for the EXPCNT counter to be at or below the specified level. The EXPCNT counter tracks the number of outstanding export events.", "syntax": "s_waitcnt_expcnt", "operands": [], "dataTypes": [], "semantics": "", "example": "s_waitcnt_expcnt null, 0x1234", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPK" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_waitcnt_lgkmcnt", "mnemonic": "s_waitcnt_lgkmcnt", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S WAITCNT LGKMCNT", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Wait for the LGKMCNT counter to be at or below the specified level.", "description": "Wait for the LGKMCNT counter to be at or below the specified level. The LGKMCNT counter tracks the number of outstanding local data share (L), global data share (G), scalar memory (K) and message (M) events.", "syntax": "s_waitcnt_lgkmcnt", "operands": [], "dataTypes": [], "semantics": "", "example": "s_waitcnt_lgkmcnt null, 0x1234", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPK" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_waitcnt_vmcnt", "mnemonic": "s_waitcnt_vmcnt", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S WAITCNT VMCNT", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Wait for the VMCNT counter to be at or below the specified level.", "description": "Wait for the VMCNT counter to be at or below the specified level. The VMCNT counter tracks the number of outstanding vector memory loads and atomics that do return data. When in 'all-in-order' mode, wait for all load and store vector memory events.", "syntax": "s_waitcnt_vmcnt", "operands": [], "dataTypes": [], "semantics": "", "example": "s_waitcnt_vmcnt null, 0x1234", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPK" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_waitcnt_vscnt", "mnemonic": "s_waitcnt_vscnt", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S WAITCNT VSCNT", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Wait for the VSCNT counter to be at or below the specified level.", "description": "Wait for the VSCNT counter to be at or below the specified level. The VSCNT counter tracks the number of outstanding vector memory stores and atomics that do not return data. This counter is not used in 'all-in-order' mode.", "syntax": "s_waitcnt_vscnt", "operands": [], "dataTypes": [], "semantics": "", "example": "s_waitcnt_vscnt null, 0x1234", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOPK" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_wakeup", "mnemonic": "s_wakeup", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S WAKEUP", "category": "Branch & Control", "instructionClass": "scalar", "summary": "Allow a wave to 'ping' all the other waves in its threadgroup to force them to wake up early from an S_SLEEP instruction.", "description": "Allow a wave to 'ping' all the other waves in its threadgroup to force them to wake up early from an S_SLEEP instruction. The ping is ignored if the waves are not sleeping. This allows for efficient polling on a memory location. The waves which are polling can sit in a long S_SLEEP between memory reads, but the wave which writes the value can tell them all to wake up early now that the data is available. This method is also safe from races since any waves that miss the ping resume when they complete their S_SLEEP. If the wave executing S_WAKEUP is in a threadgroup (in_tg set), then it wakes up all waves associated with the same threadgroup ID. Otherwise, S_WAKEUP is treated as an S_NOP.", "syntax": "s_wakeup", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOPP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 139, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.s_wakeup_barrier", "mnemonic": "s_wakeup_barrier", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S WAKEUP BARRIER", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "AMDGPU SOP1 scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "s_wakeup_barrier", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.s_wqm_b32", "mnemonic": "s_wqm_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S WQM B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Given an active pixel mask in a scalar input, calculate whole quad mode mask for that input, store the result into a scalar register and set SCC iff…", "description": "Given an active pixel mask in a scalar input, calculate whole quad mode mask for that input, store the result into a scalar register and set SCC iff the result is nonzero. In whole quad mode, if any pixel in a quad is active then all pixels of the quad are marked active.", "syntax": "s_wqm_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "tmp = 0U;\ndeclare i : 6'U;\nfor i in 6'0U : 6'31U do\ntmp[i] = S0.u32[i & 6'60U +: 6'4U] != 0U\nendfor;\nD0.u32 = tmp;\nSCC = D0.u32 != 0U", "example": "s_wqm_b32 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 116, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_wqm_b64", "mnemonic": "s_wqm_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S WQM B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Given an active pixel mask in a scalar input, calculate whole quad mode mask for that input, store the result into a scalar register and set SCC iff…", "description": "Given an active pixel mask in a scalar input, calculate whole quad mode mask for that input, store the result into a scalar register and set SCC iff the result is nonzero. In whole quad mode, if any pixel in a quad is active then all pixels of the quad are marked active.", "syntax": "s_wqm_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "tmp = 0ULL;\ndeclare i : 6'U;\nfor i in 6'0U : 6'63U do\ntmp[i] = S0.u64[i & 6'60U +: 6'4U] != 0ULL\nendfor;\nD0.u64 = tmp;\nSCC = D0.u64 != 0ULL", "example": "s_wqm_b64 s[0:1], 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 116, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_xnor_b32", "mnemonic": "s_xnor_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S XNOR B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise XNOR on two scalar inputs, store the result into a scalar register and set SCC if the result is nonzero.", "description": "Calculate bitwise XNOR on two scalar inputs, store the result into a scalar register and set SCC if the result is nonzero.", "syntax": "s_xnor_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.u32 = ~(S0.u32 ^ S1.u32);\nSCC = D0.u32 != 0U", "example": "s_xnor_b32 s0, 0, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 102, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_xnor_b64", "mnemonic": "s_xnor_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S XNOR B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise XNOR on two scalar inputs, store the result into a scalar register and set SCC if the result is nonzero.", "description": "Calculate bitwise XNOR on two scalar inputs, store the result into a scalar register and set SCC if the result is nonzero.", "syntax": "s_xnor_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "D0.u64 = ~(S0.u64 ^ S1.u64);\nSCC = D0.u64 != 0ULL", "example": "s_xnor_b64 s[0:1], 0, s[4:5]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 103, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_xnor_saveexec_b32", "mnemonic": "s_xnor_saveexec_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S XNOR SAVEEXEC B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise XNOR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is…", "description": "Calculate bitwise XNOR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register.", "syntax": "s_xnor_saveexec_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "s_xnor_saveexec_b32 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_xnor_saveexec_b64", "mnemonic": "s_xnor_saveexec_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S XNOR SAVEEXEC B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise XNOR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is…", "description": "Calculate bitwise XNOR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register.", "syntax": "s_xnor_saveexec_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "saveexec = EXEC.u64;\nEXEC.u64 = ~(S0.u64 ^ EXEC.u64);\nD0.u64 = saveexec.u64;\nSCC = EXEC.u64 != 0ULL", "example": "s_xnor_saveexec_b64 s[0:1], 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 126, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_xor_b32", "mnemonic": "s_xor_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S XOR B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise XOR on two scalar inputs, store the result into a scalar register and set SCC iff the result is nonzero.", "description": "Calculate bitwise XOR on two scalar inputs, store the result into a scalar register and set SCC iff the result is nonzero.", "syntax": "s_xor_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.u32 = (S0.u32 ^ S1.u32);\nSCC = D0.u32 != 0U", "example": "s_xor_b32 s0, 0, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 100, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_xor_b64", "mnemonic": "s_xor_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S XOR B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise XOR on two scalar inputs, store the result into a scalar register and set SCC iff the result is nonzero.", "description": "Calculate bitwise XOR on two scalar inputs, store the result into a scalar register and set SCC iff the result is nonzero.", "syntax": "s_xor_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "D0.u64 = (S0.u64 ^ S1.u64);\nSCC = D0.u64 != 0ULL", "example": "s_xor_b64 s[0:1], 0, s[4:5]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 100, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_xor_saveexec_b32", "mnemonic": "s_xor_saveexec_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S XOR SAVEEXEC B32", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise XOR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is…", "description": "Calculate bitwise XOR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register.", "syntax": "s_xor_saveexec_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "s_xor_saveexec_b32 s0, 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.s_xor_saveexec_b64", "mnemonic": "s_xor_saveexec_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "S XOR SAVEEXEC B64", "category": "Scalar Arithmetic", "instructionClass": "scalar", "summary": "Calculate bitwise XOR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is…", "description": "Calculate bitwise XOR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. The original EXEC mask is saved to the destination SGPRs before the bitwise operation is performed.", "syntax": "s_xor_saveexec_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "saveexec = EXEC.u64;\nEXEC.u64 = (S0.u64 ^ EXEC.u64);\nD0.u64 = saveexec.u64;\nSCC = EXEC.u64 != 0ULL", "example": "s_xor_saveexec_b64 s[0:1], 0", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 125, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.scratch_load_block", "mnemonic": "scratch_load_block", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "SCRATCH LOAD BLOCK", "category": "Scratch Memory", "instructionClass": "vector", "summary": "Load a block of data from the scratch aperture.", "description": "Load a block of data from the scratch aperture.", "syntax": "scratch_load_block", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SCRATCH" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.scratch_load_dword", "mnemonic": "scratch_load_dword", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "SCRATCH LOAD DWORD", "category": "Scratch Memory", "instructionClass": "vector", "summary": "Load 32 bits of data from the scratch aperture into a vector register.", "description": "Load 32 bits of data from the scratch aperture into a vector register.", "syntax": "scratch_load_dword", "operands": [], "dataTypes": [], "semantics": "", "example": "scratch_load_dword v5, v1, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SCRATCH" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.scratch_load_dwordx2", "mnemonic": "scratch_load_dwordx2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "SCRATCH LOAD DWORDX2", "category": "Scratch Memory", "instructionClass": "vector", "summary": "Load 64 bits of data from the scratch aperture into a vector register.", "description": "Load 64 bits of data from the scratch aperture into a vector register.", "syntax": "scratch_load_dwordx2", "operands": [], "dataTypes": [], "semantics": "addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nVDATA[31 : 0] = MEM[addr].b32;\nVDATA[63 : 32] = MEM[addr + 4U].b32", "example": "scratch_load_dwordx2 v[5:6], v1, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SCRATCH" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 498, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.scratch_load_dwordx3", "mnemonic": "scratch_load_dwordx3", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "SCRATCH LOAD DWORDX3", "category": "Scratch Memory", "instructionClass": "vector", "summary": "Load 96 bits of data from the scratch aperture into a vector register.", "description": "Load 96 bits of data from the scratch aperture into a vector register.", "syntax": "scratch_load_dwordx3", "operands": [], "dataTypes": [], "semantics": "addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nVDATA[31 : 0] = MEM[addr].b32;\nVDATA[63 : 32] = MEM[addr + 4U].b32;\nVDATA[95 : 64] = MEM[addr + 8U].b32", "example": "scratch_load_dwordx3 v[5:7], v1, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SCRATCH" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 498, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.scratch_load_dwordx4", "mnemonic": "scratch_load_dwordx4", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "SCRATCH LOAD DWORDX4", "category": "Scratch Memory", "instructionClass": "vector", "summary": "Load 128 bits of data from the scratch aperture into a vector register.", "description": "Load 128 bits of data from the scratch aperture into a vector register.", "syntax": "scratch_load_dwordx4", "operands": [], "dataTypes": [], "semantics": "addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nVDATA[31 : 0] = MEM[addr].b32;\nVDATA[63 : 32] = MEM[addr + 4U].b32;\nVDATA[95 : 64] = MEM[addr + 8U].b32;\nVDATA[127 : 96] = MEM[addr + 12U].b32", "example": "scratch_load_dwordx4 v[5:8], v1, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SCRATCH" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 498, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.scratch_load_lds_dword", "mnemonic": "scratch_load_lds_dword", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "SCRATCH LOAD LDS DWORD", "category": "Scratch Memory", "instructionClass": "vector", "summary": "Load 32 bits of untyped data from the scratch aperture and store the result into a data share.", "description": "Load 32 bits of untyped data from the scratch aperture and store the result into a data share.", "syntax": "scratch_load_lds_dword", "operands": [], "dataTypes": [], "semantics": "addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nVDATA[31 : 0] = MEM[addr].b32", "example": null, "exampleSource": null, "encoding": { "format": "SCRATCH" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 502, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.scratch_load_lds_sbyte", "mnemonic": "scratch_load_lds_sbyte", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "SCRATCH LOAD LDS SBYTE", "category": "Scratch Memory", "instructionClass": "vector", "summary": "Load 8 bits of untyped data from the scratch aperture, sign extend to 32 bits and store the result into a data share.", "description": "Load 8 bits of untyped data from the scratch aperture, sign extend to 32 bits and store the result into a data share.", "syntax": "scratch_load_lds_sbyte", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SCRATCH" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 502, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.scratch_load_lds_sshort", "mnemonic": "scratch_load_lds_sshort", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "SCRATCH LOAD LDS SSHORT", "category": "Scratch Memory", "instructionClass": "vector", "summary": "Load 16 bits of untyped data from the scratch aperture, sign extend to 32 bits and store the result into a data share.", "description": "Load 16 bits of untyped data from the scratch aperture, sign extend to 32 bits and store the result into a data share.", "syntax": "scratch_load_lds_sshort", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SCRATCH" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 502, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.scratch_load_lds_ubyte", "mnemonic": "scratch_load_lds_ubyte", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "SCRATCH LOAD LDS UBYTE", "category": "Scratch Memory", "instructionClass": "vector", "summary": "Load 8 bits of untyped data from the scratch aperture, zero extend to 32 bits and store the result into a data share.", "description": "Load 8 bits of untyped data from the scratch aperture, zero extend to 32 bits and store the result into a data share.", "syntax": "scratch_load_lds_ubyte", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SCRATCH" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 501, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.scratch_load_lds_ushort", "mnemonic": "scratch_load_lds_ushort", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "SCRATCH LOAD LDS USHORT", "category": "Scratch Memory", "instructionClass": "vector", "summary": "Load 16 bits of untyped data from the scratch aperture, zero extend to 32 bits and store the result into a data share.", "description": "Load 16 bits of untyped data from the scratch aperture, zero extend to 32 bits and store the result into a data share.", "syntax": "scratch_load_lds_ushort", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SCRATCH" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 502, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.scratch_load_sbyte", "mnemonic": "scratch_load_sbyte", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "SCRATCH LOAD SBYTE", "category": "Scratch Memory", "instructionClass": "vector", "summary": "Load 8 bits of signed data from the scratch aperture, sign extend to 32 bits and store the result into a vector register.", "description": "Load 8 bits of signed data from the scratch aperture, sign extend to 32 bits and store the result into a vector register.", "syntax": "scratch_load_sbyte", "operands": [], "dataTypes": [], "semantics": "", "example": "scratch_load_sbyte v5, v1, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SCRATCH" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.scratch_load_sbyte_d16", "mnemonic": "scratch_load_sbyte_d16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "SCRATCH LOAD SBYTE D16", "category": "Scratch Memory", "instructionClass": "vector", "summary": "Load 8 bits of signed data from the scratch aperture, sign extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register.", "description": "Load 8 bits of signed data from the scratch aperture, sign extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register.", "syntax": "scratch_load_sbyte_d16", "operands": [], "dataTypes": [], "semantics": "addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nVDATA[15 : 0].i16 = 16'I(signext(MEM[addr].i8));\n// VDATA[31:16] is preserved.", "example": null, "exampleSource": null, "encoding": { "format": "SCRATCH" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 500, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.scratch_load_sbyte_d16_hi", "mnemonic": "scratch_load_sbyte_d16_hi", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "SCRATCH LOAD SBYTE D16 HI", "category": "Scratch Memory", "instructionClass": "vector", "summary": "Load 8 bits of signed data from the scratch aperture, sign extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register.", "description": "Load 8 bits of signed data from the scratch aperture, sign extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register.", "syntax": "scratch_load_sbyte_d16_hi", "operands": [], "dataTypes": [], "semantics": "addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nVDATA[31 : 16].i16 = 16'I(signext(MEM[addr].i8));\n// VDATA[15:0] is preserved.", "example": null, "exampleSource": null, "encoding": { "format": "SCRATCH" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 501, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.scratch_load_short_d16", "mnemonic": "scratch_load_short_d16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "SCRATCH LOAD SHORT D16", "category": "Scratch Memory", "instructionClass": "vector", "summary": "Load 16 bits of unsigned data from the scratch aperture and store the result into the low 16 bits of a 32-bit vector register.", "description": "Load 16 bits of unsigned data from the scratch aperture and store the result into the low 16 bits of a 32-bit vector register.", "syntax": "scratch_load_short_d16", "operands": [], "dataTypes": [], "semantics": "addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nVDATA[15 : 0].b16 = MEM[addr].b16;\n// VDATA[31:16] is preserved.", "example": null, "exampleSource": null, "encoding": { "format": "SCRATCH" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 501, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.scratch_load_short_d16_hi", "mnemonic": "scratch_load_short_d16_hi", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "SCRATCH LOAD SHORT D16 HI", "category": "Scratch Memory", "instructionClass": "vector", "summary": "Load 16 bits of unsigned data from the scratch aperture and store the result into the high 16 bits of a 32-bit vector register.", "description": "Load 16 bits of unsigned data from the scratch aperture and store the result into the high 16 bits of a 32-bit vector register.", "syntax": "scratch_load_short_d16_hi", "operands": [], "dataTypes": [], "semantics": "addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nVDATA[31 : 16].b16 = MEM[addr].b16;\n// VDATA[15:0] is preserved.", "example": null, "exampleSource": null, "encoding": { "format": "SCRATCH" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 501, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.scratch_load_sshort", "mnemonic": "scratch_load_sshort", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "SCRATCH LOAD SSHORT", "category": "Scratch Memory", "instructionClass": "vector", "summary": "Load 16 bits of signed data from the scratch aperture, sign extend to 32 bits and store the result into a vector register.", "description": "Load 16 bits of signed data from the scratch aperture, sign extend to 32 bits and store the result into a vector register.", "syntax": "scratch_load_sshort", "operands": [], "dataTypes": [], "semantics": "", "example": "scratch_load_sshort v5, v1, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SCRATCH" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.scratch_load_ubyte", "mnemonic": "scratch_load_ubyte", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "SCRATCH LOAD UBYTE", "category": "Scratch Memory", "instructionClass": "vector", "summary": "Load 8 bits of unsigned data from the scratch aperture, zero extend to 32 bits and store the result into a vector register.", "description": "Load 8 bits of unsigned data from the scratch aperture, zero extend to 32 bits and store the result into a vector register.", "syntax": "scratch_load_ubyte", "operands": [], "dataTypes": [], "semantics": "", "example": "scratch_load_ubyte v5, v1, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SCRATCH" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.scratch_load_ubyte_d16", "mnemonic": "scratch_load_ubyte_d16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "SCRATCH LOAD UBYTE D16", "category": "Scratch Memory", "instructionClass": "vector", "summary": "Load 8 bits of unsigned data from the scratch aperture, zero extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register.", "description": "Load 8 bits of unsigned data from the scratch aperture, zero extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register.", "syntax": "scratch_load_ubyte_d16", "operands": [], "dataTypes": [], "semantics": "addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nVDATA[15 : 0].u16 = 16'U({ 8'0U, MEM[addr].u8 });\n// VDATA[31:16] is preserved.", "example": null, "exampleSource": null, "encoding": { "format": "SCRATCH" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 500, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.scratch_load_ubyte_d16_hi", "mnemonic": "scratch_load_ubyte_d16_hi", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "SCRATCH LOAD UBYTE D16 HI", "category": "Scratch Memory", "instructionClass": "vector", "summary": "Load 8 bits of unsigned data from the scratch aperture, zero extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register.", "description": "Load 8 bits of unsigned data from the scratch aperture, zero extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register.", "syntax": "scratch_load_ubyte_d16_hi", "operands": [], "dataTypes": [], "semantics": "addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nVDATA[31 : 16].u16 = 16'U({ 8'0U, MEM[addr].u8 });\n// VDATA[15:0] is preserved.", "example": null, "exampleSource": null, "encoding": { "format": "SCRATCH" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 500, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.scratch_load_ushort", "mnemonic": "scratch_load_ushort", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "SCRATCH LOAD USHORT", "category": "Scratch Memory", "instructionClass": "vector", "summary": "Load 16 bits of unsigned data from the scratch aperture, zero extend to 32 bits and store the result into a vector register.", "description": "Load 16 bits of unsigned data from the scratch aperture, zero extend to 32 bits and store the result into a vector register.", "syntax": "scratch_load_ushort", "operands": [], "dataTypes": [], "semantics": "", "example": "scratch_load_ushort v5, v1, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SCRATCH" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.scratch_store_block", "mnemonic": "scratch_store_block", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "SCRATCH STORE BLOCK", "category": "Scratch Memory", "instructionClass": "vector", "summary": "Store a block of data to the scratch aperture.", "description": "Store a block of data to the scratch aperture.", "syntax": "scratch_store_block", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "SCRATCH" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.scratch_store_byte", "mnemonic": "scratch_store_byte", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "SCRATCH STORE BYTE", "category": "Scratch Memory", "instructionClass": "vector", "summary": "Store 8 bits of data from a vector register into the scratch aperture.", "description": "Store 8 bits of data from a vector register into the scratch aperture.", "syntax": "scratch_store_byte", "operands": [], "dataTypes": [], "semantics": "addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nMEM[addr].b8 = VDATA[7 : 0]", "example": "scratch_store_byte v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SCRATCH" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 498, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.scratch_store_byte_d16_hi", "mnemonic": "scratch_store_byte_d16_hi", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "SCRATCH STORE BYTE D16 HI", "category": "Scratch Memory", "instructionClass": "vector", "summary": "Store 8 bits of data from the high 16 bits of a 32-bit vector register into the scratch aperture.", "description": "Store 8 bits of data from the high 16 bits of a 32-bit vector register into the scratch aperture.", "syntax": "scratch_store_byte_d16_hi", "operands": [], "dataTypes": [], "semantics": "addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nMEM[addr].b8 = VDATA[23 : 16]", "example": null, "exampleSource": null, "encoding": { "format": "SCRATCH" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 499, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.scratch_store_dword", "mnemonic": "scratch_store_dword", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "SCRATCH STORE DWORD", "category": "Scratch Memory", "instructionClass": "vector", "summary": "Store 32 bits of data from vector input registers into the scratch aperture.", "description": "Store 32 bits of data from vector input registers into the scratch aperture.", "syntax": "scratch_store_dword", "operands": [], "dataTypes": [], "semantics": "addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nMEM[addr].b32 = VDATA[31 : 0]", "example": "scratch_store_dword v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SCRATCH" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 499, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.scratch_store_dwordx2", "mnemonic": "scratch_store_dwordx2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "SCRATCH STORE DWORDX2", "category": "Scratch Memory", "instructionClass": "vector", "summary": "Store 64 bits of data from vector input registers into the scratch aperture.", "description": "Store 64 bits of data from vector input registers into the scratch aperture.", "syntax": "scratch_store_dwordx2", "operands": [], "dataTypes": [], "semantics": "addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nMEM[addr].b32 = VDATA[31 : 0];\nMEM[addr + 4U].b32 = VDATA[63 : 32]", "example": "scratch_store_dwordx2 v1, v[2:3], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SCRATCH" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 499, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.scratch_store_dwordx3", "mnemonic": "scratch_store_dwordx3", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "SCRATCH STORE DWORDX3", "category": "Scratch Memory", "instructionClass": "vector", "summary": "Store 96 bits of data from vector input registers into the scratch aperture.", "description": "Store 96 bits of data from vector input registers into the scratch aperture.", "syntax": "scratch_store_dwordx3", "operands": [], "dataTypes": [], "semantics": "addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nMEM[addr].b32 = VDATA[31 : 0];\nMEM[addr + 4U].b32 = VDATA[63 : 32];\nMEM[addr + 8U].b32 = VDATA[95 : 64]", "example": "scratch_store_dwordx3 v1, v[2:4], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SCRATCH" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 500, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.scratch_store_dwordx4", "mnemonic": "scratch_store_dwordx4", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "SCRATCH STORE DWORDX4", "category": "Scratch Memory", "instructionClass": "vector", "summary": "Store 128 bits of data from vector input registers into the scratch aperture.", "description": "Store 128 bits of data from vector input registers into the scratch aperture.", "syntax": "scratch_store_dwordx4", "operands": [], "dataTypes": [], "semantics": "addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nMEM[addr].b32 = VDATA[31 : 0];\nMEM[addr + 4U].b32 = VDATA[63 : 32];\nMEM[addr + 8U].b32 = VDATA[95 : 64];\nMEM[addr + 12U].b32 = VDATA[127 : 96]", "example": "scratch_store_dwordx4 v1, v[2:5], s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SCRATCH" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 500, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.scratch_store_short", "mnemonic": "scratch_store_short", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "SCRATCH STORE SHORT", "category": "Scratch Memory", "instructionClass": "vector", "summary": "Store 16 bits of data from a vector register into the scratch aperture.", "description": "Store 16 bits of data from a vector register into the scratch aperture.", "syntax": "scratch_store_short", "operands": [], "dataTypes": [], "semantics": "addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nMEM[addr].b16 = VDATA[15 : 0]", "example": "scratch_store_short v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "SCRATCH" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 499, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.scratch_store_short_d16_hi", "mnemonic": "scratch_store_short_d16_hi", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "SCRATCH STORE SHORT D16 HI", "category": "Scratch Memory", "instructionClass": "vector", "summary": "Store 16 bits of data from the high 16 bits of a 32-bit vector register into the scratch aperture.", "description": "Store 16 bits of data from the high 16 bits of a 32-bit vector register into the scratch aperture.", "syntax": "scratch_store_short_d16_hi", "operands": [], "dataTypes": [], "semantics": "addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);\nMEM[addr].b16 = VDATA[31 : 16]", "example": null, "exampleSource": null, "encoding": { "format": "SCRATCH" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 499, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.tbuffer_load_d16_format_x", "mnemonic": "tbuffer_load_d16_format_x", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "TBUFFER LOAD D16 FORMAT X", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Load 1-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result…", "description": "Load 1-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result into a vector register. The instruction specifies the data format of the surface, overriding the resource descriptor.", "syntax": "tbuffer_load_d16_format_x", "operands": [], "dataTypes": [], "semantics": "", "example": "tbuffer_load_d16_format_x v255, off, s[8:11], s3, format:1 offset:4095", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MTBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.tbuffer_load_d16_format_xy", "mnemonic": "tbuffer_load_d16_format_xy", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "TBUFFER LOAD D16 FORMAT XY", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Load 2-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result…", "description": "Load 2-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result into a vector register. The instruction specifies the data format of the surface, overriding the resource descriptor.", "syntax": "tbuffer_load_d16_format_xy", "operands": [], "dataTypes": [], "semantics": "", "example": "tbuffer_load_d16_format_xy v255, off, s[8:11], s3, format:6 offset:4095", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MTBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.tbuffer_load_d16_format_xyz", "mnemonic": "tbuffer_load_d16_format_xyz", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "TBUFFER LOAD D16 FORMAT XYZ", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Load 3-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result…", "description": "Load 3-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result into a vector register. The instruction specifies the data format of the surface, overriding the resource descriptor.", "syntax": "tbuffer_load_d16_format_xyz", "operands": [], "dataTypes": [], "semantics": "", "example": "tbuffer_load_d16_format_xyz v[4:5], off, ttmp[4:7], 61, format:13 offset:4095", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MTBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.tbuffer_load_d16_format_xyzw", "mnemonic": "tbuffer_load_d16_format_xyzw", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "TBUFFER LOAD D16 FORMAT XYZW", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Load 4-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result…", "description": "Load 4-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result into a vector register. The instruction specifies the data format of the surface, overriding the resource descriptor.", "syntax": "tbuffer_load_d16_format_xyzw", "operands": [], "dataTypes": [], "semantics": "", "example": "tbuffer_load_d16_format_xyzw v[4:5], off, ttmp[4:7], 61, format:18 offset:4095", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MTBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.tbuffer_load_format_d16_x", "mnemonic": "tbuffer_load_format_d16_x", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "TBUFFER LOAD FORMAT D16 X", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Load 1-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result…", "description": "Load 1-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result into a vector register. The instruction specifies the data format of the surface, overriding the resource descriptor.", "syntax": "tbuffer_load_format_d16_x", "operands": [], "dataTypes": [], "semantics": "addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);\nVDATA[15 : 0].b16 = 16'B(ConvertFromFormat(MEM[addr + ChannelOffsetX()]));\n// Mem access size depends on format\n// VDATA[31:16].b16 is preserved.", "example": null, "exampleSource": null, "encoding": { "format": "MTBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 479, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.tbuffer_load_format_d16_xy", "mnemonic": "tbuffer_load_format_d16_xy", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "TBUFFER LOAD FORMAT D16 XY", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Load 2-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result…", "description": "Load 2-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result into a vector register. The instruction specifies the data format of the surface, overriding the resource descriptor.", "syntax": "tbuffer_load_format_d16_xy", "operands": [], "dataTypes": [], "semantics": "addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);\nVDATA[15 : 0].b16 = 16'B(ConvertFromFormat(MEM[addr + ChannelOffsetX()]));\n// Mem access size depends on format\nVDATA[31 : 16].b16 = 16'B(ConvertFromFormat(MEM[addr + ChannelOffsetY()]))", "example": null, "exampleSource": null, "encoding": { "format": "MTBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 479, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.tbuffer_load_format_d16_xyz", "mnemonic": "tbuffer_load_format_d16_xyz", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "TBUFFER LOAD FORMAT D16 XYZ", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Load 3-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result…", "description": "Load 3-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result into a vector register. The instruction specifies the data format of the surface, overriding the resource descriptor.", "syntax": "tbuffer_load_format_d16_xyz", "operands": [], "dataTypes": [], "semantics": "addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);\nVDATA[15 : 0].b16 = 16'B(ConvertFromFormat(MEM[addr + ChannelOffsetX()]));\n// Mem access size depends on format\nVDATA[31 : 16].b16 = 16'B(ConvertFromFormat(MEM[addr + ChannelOffsetY()]));\nVDATA[47 : 32].b16 = 16'B(ConvertFromFormat(MEM[addr + ChannelOffsetZ()]));\n// VDATA[63:48].b16 is preserved.", "example": null, "exampleSource": null, "encoding": { "format": "MTBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 480, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.tbuffer_load_format_d16_xyzw", "mnemonic": "tbuffer_load_format_d16_xyzw", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "TBUFFER LOAD FORMAT D16 XYZW", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Load 4-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result…", "description": "Load 4-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result into a vector register. The instruction specifies the data format of the surface, overriding the resource descriptor.", "syntax": "tbuffer_load_format_d16_xyzw", "operands": [], "dataTypes": [], "semantics": "addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);\nVDATA[15 : 0].b16 = 16'B(ConvertFromFormat(MEM[addr + ChannelOffsetX()]));\n// Mem access size depends on format\nVDATA[31 : 16].b16 = 16'B(ConvertFromFormat(MEM[addr + ChannelOffsetY()]));\nVDATA[47 : 32].b16 = 16'B(ConvertFromFormat(MEM[addr + ChannelOffsetZ()]));\nVDATA[63 : 48].b16 = 16'B(ConvertFromFormat(MEM[addr + ChannelOffsetW()]))", "example": null, "exampleSource": null, "encoding": { "format": "MTBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 480, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.tbuffer_load_format_x", "mnemonic": "tbuffer_load_format_x", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "TBUFFER LOAD FORMAT X", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Load 1-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a…", "description": "Load 1-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a vector register. The instruction specifies the data format of the surface, overriding the resource descriptor.", "syntax": "tbuffer_load_format_x", "operands": [], "dataTypes": [], "semantics": "addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);\nVDATA[31 : 0].b32 = ConvertFromFormat(MEM[addr + ChannelOffsetX()]);\n// Mem access size depends on format", "example": "tbuffer_load_format_x v255, off, s[8:11], s3, format:21 offset:4095", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MTBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 477, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.tbuffer_load_format_xy", "mnemonic": "tbuffer_load_format_xy", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "TBUFFER LOAD FORMAT XY", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Load 2-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a…", "description": "Load 2-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a vector register. The instruction specifies the data format of the surface, overriding the resource descriptor.", "syntax": "tbuffer_load_format_xy", "operands": [], "dataTypes": [], "semantics": "addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);\nVDATA[31 : 0].b32 = ConvertFromFormat(MEM[addr + ChannelOffsetX()]);\n// Mem access size depends on format\nVDATA[63 : 32].b32 = ConvertFromFormat(MEM[addr + ChannelOffsetY()])", "example": "tbuffer_load_format_xy v[4:5], off, ttmp[4:7], 61, format:28 offset:4095", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MTBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 477, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.tbuffer_load_format_xyz", "mnemonic": "tbuffer_load_format_xyz", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "TBUFFER LOAD FORMAT XYZ", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Load 3-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a…", "description": "Load 3-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a vector register. The instruction specifies the data format of the surface, overriding the resource descriptor.", "syntax": "tbuffer_load_format_xyz", "operands": [], "dataTypes": [], "semantics": "addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);\nVDATA[31 : 0].b32 = ConvertFromFormat(MEM[addr + ChannelOffsetX()]);\n// Mem access size depends on format\nVDATA[63 : 32].b32 = ConvertFromFormat(MEM[addr + ChannelOffsetY()]);\nVDATA[95 : 64].b32 = ConvertFromFormat(MEM[addr + ChannelOffsetZ()])", "example": "tbuffer_load_format_xyz v[4:6], off, ttmp[4:7], 61, format:33 offset:4095", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MTBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 478, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.tbuffer_load_format_xyzw", "mnemonic": "tbuffer_load_format_xyzw", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "TBUFFER LOAD FORMAT XYZW", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Load 4-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a…", "description": "Load 4-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a vector register. The instruction specifies the data format of the surface, overriding the resource descriptor.", "syntax": "tbuffer_load_format_xyzw", "operands": [], "dataTypes": [], "semantics": "addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);\nVDATA[31 : 0].b32 = ConvertFromFormat(MEM[addr + ChannelOffsetX()]);\n// Mem access size depends on format\nVDATA[63 : 32].b32 = ConvertFromFormat(MEM[addr + ChannelOffsetY()]);\nVDATA[95 : 64].b32 = ConvertFromFormat(MEM[addr + ChannelOffsetZ()]);\nVDATA[127 : 96].b32 = ConvertFromFormat(MEM[addr + ChannelOffsetW()])", "example": "tbuffer_load_format_xyzw v[4:7], off, ttmp[4:7], 61, format:38 offset:4095", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MTBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 478, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.tbuffer_store_d16_format_x", "mnemonic": "tbuffer_store_d16_format_x", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "TBUFFER STORE D16 FORMAT X", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Convert 16 bits of data from vector input registers into 1-component formatted data and store the data into a buffer surface.", "description": "Convert 16 bits of data from vector input registers into 1-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor.", "syntax": "tbuffer_store_d16_format_x", "operands": [], "dataTypes": [], "semantics": "", "example": "tbuffer_store_d16_format_x v255, off, s[8:11], s3, format:41 offset:4095", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MTBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.tbuffer_store_d16_format_xy", "mnemonic": "tbuffer_store_d16_format_xy", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "TBUFFER STORE D16 FORMAT XY", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Convert 32 bits of data from vector input registers into 2-component formatted data and store the data into a buffer surface.", "description": "Convert 32 bits of data from vector input registers into 2-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor.", "syntax": "tbuffer_store_d16_format_xy", "operands": [], "dataTypes": [], "semantics": "", "example": "tbuffer_store_d16_format_xy v255, off, s[8:11], s3, format:46 offset:4095", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MTBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.tbuffer_store_d16_format_xyz", "mnemonic": "tbuffer_store_d16_format_xyz", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "TBUFFER STORE D16 FORMAT XYZ", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Convert 48 bits of data from vector input registers into 3-component formatted data and store the data into a buffer surface.", "description": "Convert 48 bits of data from vector input registers into 3-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor.", "syntax": "tbuffer_store_d16_format_xyz", "operands": [], "dataTypes": [], "semantics": "", "example": "tbuffer_store_d16_format_xyz v[4:5], off, ttmp[4:7], 61, format:53 offset:4095", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MTBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.tbuffer_store_d16_format_xyzw", "mnemonic": "tbuffer_store_d16_format_xyzw", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "TBUFFER STORE D16 FORMAT XYZW", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Convert 64 bits of data from vector input registers into 4-component formatted data and store the data into a buffer surface.", "description": "Convert 64 bits of data from vector input registers into 4-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor.", "syntax": "tbuffer_store_d16_format_xyzw", "operands": [], "dataTypes": [], "semantics": "", "example": "tbuffer_store_d16_format_xyzw v[4:5], off, ttmp[4:7], 61, format:58 offset:4095", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MTBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.tbuffer_store_format_d16_x", "mnemonic": "tbuffer_store_format_d16_x", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "TBUFFER STORE FORMAT D16 X", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Convert 16 bits of data from vector input registers into 1-component formatted data and store the data into a buffer surface.", "description": "Convert 16 bits of data from vector input registers into 1-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor.", "syntax": "tbuffer_store_format_d16_x", "operands": [], "dataTypes": [], "semantics": "addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);\nMEM[addr + ChannelOffsetX()] = ConvertToFormat(32'B(VDATA[15 : 0].b16));\n// Mem access size depends on format", "example": null, "exampleSource": null, "encoding": { "format": "MTBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 480, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.tbuffer_store_format_d16_xy", "mnemonic": "tbuffer_store_format_d16_xy", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "TBUFFER STORE FORMAT D16 XY", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Convert 32 bits of data from vector input registers into 2-component formatted data and store the data into a buffer surface.", "description": "Convert 32 bits of data from vector input registers into 2-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor.", "syntax": "tbuffer_store_format_d16_xy", "operands": [], "dataTypes": [], "semantics": "addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);\nMEM[addr + ChannelOffsetX()] = ConvertToFormat(32'B(VDATA[15 : 0].b16));\n// Mem access size depends on format\nMEM[addr + ChannelOffsetY()] = ConvertToFormat(32'B(VDATA[31 : 16].b16))", "example": null, "exampleSource": null, "encoding": { "format": "MTBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 481, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.tbuffer_store_format_d16_xyz", "mnemonic": "tbuffer_store_format_d16_xyz", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "TBUFFER STORE FORMAT D16 XYZ", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Convert 48 bits of data from vector input registers into 3-component formatted data and store the data into a buffer surface.", "description": "Convert 48 bits of data from vector input registers into 3-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor.", "syntax": "tbuffer_store_format_d16_xyz", "operands": [], "dataTypes": [], "semantics": "addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);\nMEM[addr + ChannelOffsetX()] = ConvertToFormat(32'B(VDATA[15 : 0].b16));\n// Mem access size depends on format\nMEM[addr + ChannelOffsetY()] = ConvertToFormat(32'B(VDATA[31 : 16].b16));\nMEM[addr + ChannelOffsetZ()] = ConvertToFormat(32'B(VDATA[47 : 32].b16))", "example": null, "exampleSource": null, "encoding": { "format": "MTBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 481, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.tbuffer_store_format_d16_xyzw", "mnemonic": "tbuffer_store_format_d16_xyzw", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "TBUFFER STORE FORMAT D16 XYZW", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Convert 64 bits of data from vector input registers into 4-component formatted data and store the data into a buffer surface.", "description": "Convert 64 bits of data from vector input registers into 4-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor.", "syntax": "tbuffer_store_format_d16_xyzw", "operands": [], "dataTypes": [], "semantics": "addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);\nMEM[addr + ChannelOffsetX()] = ConvertToFormat(32'B(VDATA[15 : 0].b16));\n// Mem access size depends on format\nMEM[addr + ChannelOffsetY()] = ConvertToFormat(32'B(VDATA[31 : 16].b16));\nMEM[addr + ChannelOffsetZ()] = ConvertToFormat(32'B(VDATA[47 : 32].b16));\nMEM[addr + ChannelOffsetW()] = ConvertToFormat(32'B(VDATA[63 : 48].b16))", "example": null, "exampleSource": null, "encoding": { "format": "MTBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 481, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.tbuffer_store_format_x", "mnemonic": "tbuffer_store_format_x", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "TBUFFER STORE FORMAT X", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Convert 32 bits of data from vector input registers into 1-component formatted data and store the data into a buffer surface.", "description": "Convert 32 bits of data from vector input registers into 1-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor.", "syntax": "tbuffer_store_format_x", "operands": [], "dataTypes": [], "semantics": "addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);\nMEM[addr + ChannelOffsetX()] = ConvertToFormat(VDATA[31 : 0].b32);\n// Mem access size depends on format", "example": "tbuffer_store_format_x v255, off, s[8:11], s3, format:61 offset:4095", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MTBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 478, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.tbuffer_store_format_xy", "mnemonic": "tbuffer_store_format_xy", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "TBUFFER STORE FORMAT XY", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Convert 64 bits of data from vector input registers into 2-component formatted data and store the data into a buffer surface.", "description": "Convert 64 bits of data from vector input registers into 2-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor.", "syntax": "tbuffer_store_format_xy", "operands": [], "dataTypes": [], "semantics": "addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);\nMEM[addr + ChannelOffsetX()] = ConvertToFormat(VDATA[31 : 0].b32);\n// Mem access size depends on format\nMEM[addr + ChannelOffsetY()] = ConvertToFormat(VDATA[63 : 32].b32)", "example": "tbuffer_store_format_xy v[4:5], off, s[8:11], 0, format:[BUF_FMT_16_SINT] offset:4095", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MTBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 478, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.tbuffer_store_format_xyz", "mnemonic": "tbuffer_store_format_xyz", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "TBUFFER STORE FORMAT XYZ", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Convert 96 bits of data from vector input registers into 3-component formatted data and store the data into a buffer surface.", "description": "Convert 96 bits of data from vector input registers into 3-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor.", "syntax": "tbuffer_store_format_xyz", "operands": [], "dataTypes": [], "semantics": "addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);\nMEM[addr + ChannelOffsetX()] = ConvertToFormat(VDATA[31 : 0].b32);\n// Mem access size depends on format\nMEM[addr + ChannelOffsetY()] = ConvertToFormat(VDATA[63 : 32].b32);\nMEM[addr + ChannelOffsetZ()] = ConvertToFormat(VDATA[95 : 64].b32)", "example": "tbuffer_store_format_xyz v[4:6], off, s[8:11], s3, format:[BUF_FMT_32_FLOAT] offset:4095", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MTBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 479, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.tbuffer_store_format_xyzw", "mnemonic": "tbuffer_store_format_xyzw", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "TBUFFER STORE FORMAT XYZW", "category": "Buffer Memory", "instructionClass": "vector", "summary": "Convert 128 bits of data from vector input registers into 4-component formatted data and store the data into a buffer surface.", "description": "Convert 128 bits of data from vector input registers into 4-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor.", "syntax": "tbuffer_store_format_xyzw", "operands": [], "dataTypes": [], "semantics": "addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);\nMEM[addr + ChannelOffsetX()] = ConvertToFormat(VDATA[31 : 0].b32);\n// Mem access size depends on format\nMEM[addr + ChannelOffsetY()] = ConvertToFormat(VDATA[63 : 32].b32);\nMEM[addr + ChannelOffsetZ()] = ConvertToFormat(VDATA[95 : 64].b32);\nMEM[addr + ChannelOffsetW()] = ConvertToFormat(VDATA[127 : 96].b32)", "example": "tbuffer_store_format_xyzw v[4:7], off, s[8:11], 0, format:[BUF_FMT_8_8_8_8_UNORM] offset:4095", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "MTBUF" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 479, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.tensor_save", "mnemonic": "tensor_save", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "TENSOR SAVE", "category": "Flat Memory", "instructionClass": "vector", "summary": "AMDGPU FLAT vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "tensor_save", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.tensor_stop", "mnemonic": "tensor_stop", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "TENSOR STOP", "category": "Flat Memory", "instructionClass": "vector", "summary": "AMDGPU FLAT vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "tensor_stop", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "FLAT" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_accvgpr_mov_b32", "mnemonic": "v_accvgpr_mov_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ACCVGPR MOV B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Move data from one accumulator register to another accumulator register.", "description": "Move data from one accumulator register to another accumulator register.", "syntax": "v_accvgpr_mov_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 211, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_accvgpr_read_b32", "mnemonic": "v_accvgpr_read_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ACCVGPR READ B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_accvgpr_read_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_accvgpr_write_b32", "mnemonic": "v_accvgpr_write_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ACCVGPR WRITE B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_accvgpr_write_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_add3_u32", "mnemonic": "v_add3_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ADD3 U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Add three unsigned inputs and store the result into a vector register. No carry-in or carry-out support.", "description": "Add three unsigned inputs and store the result into a vector register. No carry-in or carry-out support.", "syntax": "v_add3_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "D0.u32 = S0.u32 + S1.u32 + S2.u32", "example": "v_add3_u32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 356, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_add_co_u32", "mnemonic": "v_add_co_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ADD CO U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Add two unsigned 32-bit integer inputs, store the result into a vector register and store the carry-out mask into a scalar register.", "description": "Add two unsigned 32-bit integer inputs, store the result into a vector register and store the carry-out mask into a scalar register.", "syntax": "v_add_co_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "tmp = 64'U(S0.u32) + 64'U(S1.u32);\nVCC.u64[laneId] = tmp >= 0x100000000ULL ? 1'1U : 1'0U;\n// VCC is an UNSIGNED overflow/carry-out for V_ADDC_CO_U32.\nD0.u32 = tmp.u32", "example": "v_add_co_u32 v5, s6, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "In VOP3 the VCC destination may be an arbitrary SGPR-pair. Supports saturation (unsigned 32-bit integer domain).", "sourcePdfPage": 175, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_add_f16", "mnemonic": "v_add_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ADD F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Add two floating point inputs and store the result into a vector register.", "description": "Add two floating point inputs and store the result into a vector register.", "syntax": "v_add_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.f16 = S0.f16 + S1.f16", "example": "v_add_f16 v5, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "0.5ULP precision. Supports denormals, round mode, exception flags and saturation.", "sourcePdfPage": 177, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_add_f32", "mnemonic": "v_add_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ADD F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Per-lane single-precision floating-point add.", "description": "Add two floating point inputs and store the result into a vector register.", "syntax": "v_add_f32 VDST, S0, S1", "operands": [ { "name": "VDST", "desc": "Destination VGPR" }, { "name": "S0", "desc": "First source (VGPR/SGPR/constant)" }, { "name": "S1", "desc": "Second source VGPR" } ], "dataTypes": [ "f32" ], "semantics": "VDST[lane] = S0[lane].f32 + S1[lane].f32 for each active lane, per the EXEC mask.", "example": "v_add_f32 v2, v0, v1 // per-lane v2 = v0 + v1 (f32)", "exampleSource": null, "encoding": { "format": "VOP2", "widthBits": 32 }, "executionUnit": "Vector ALU", "registerClasses": [ "VGPR" ], "memorySegment": null, "supportedTargets": [ "gfx942", "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_add_f64", "mnemonic": "v_add_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ADD F64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Add two floating point inputs and store the result into a vector register.", "description": "Add two floating point inputs and store the result into a vector register.", "syntax": "v_add_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": "v_add_f64 v[5:6], -1, -1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_add_f64_pseudo", "mnemonic": "v_add_f64_pseudo", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ADD F64 PSEUDO", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP2 vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_add_f64_pseudo", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_add_i16", "mnemonic": "v_add_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ADD I16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Add two signed 16-bit integer inputs and store the result into a vector register. No carry-in or carry-out support.", "description": "Add two signed 16-bit integer inputs and store the result into a vector register. No carry-in or carry-out support.", "syntax": "v_add_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "D0.i16 = S0.i16 + S1.i16", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "Supports saturation (signed 16-bit integer domain).", "sourcePdfPage": 368, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_add_i32", "mnemonic": "v_add_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ADD I32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Add two signed 32-bit integer inputs and store the result into a vector register. No carry-in or carry-out support.", "description": "Add two signed 32-bit integer inputs and store the result into a vector register. No carry-in or carry-out support.", "syntax": "v_add_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_add_lshl_u32", "mnemonic": "v_add_lshl_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ADD LSHL U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Add the first two integer inputs, then given a shift count in the third input, calculate the logical shift left of the intermediate result, then…", "description": "Add the first two integer inputs, then given a shift count in the third input, calculate the logical shift left of the intermediate result, then store the final result into a vector register.", "syntax": "v_add_lshl_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "D0.u32 = ((S0.u32 + S1.u32) << S2.u32[4 : 0].u32)", "example": "v_add_lshl_u32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 356, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_add_max_i32", "mnemonic": "v_add_max_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ADD MAX I32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_add_max_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_add_max_u32", "mnemonic": "v_add_max_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ADD MAX U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_add_max_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_add_min_i32", "mnemonic": "v_add_min_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ADD MIN I32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_add_min_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_add_min_u32", "mnemonic": "v_add_min_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ADD MIN U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_add_min_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_add_nc_i16", "mnemonic": "v_add_nc_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ADD NC I16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Add two signed 16-bit integer inputs and store the result into a vector register. No carry-in or carry-out support.", "description": "Add two signed 16-bit integer inputs and store the result into a vector register. No carry-in or carry-out support.", "syntax": "v_add_nc_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "", "example": "v_add_nc_i16 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_add_nc_i32", "mnemonic": "v_add_nc_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ADD NC I32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Add two signed 32-bit integer inputs and store the result into a vector register. No carry-in or carry-out support.", "description": "Add two signed 32-bit integer inputs and store the result into a vector register. No carry-in or carry-out support.", "syntax": "v_add_nc_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "", "example": "v_add_nc_i32 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_add_nc_u16", "mnemonic": "v_add_nc_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ADD NC U16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Add two unsigned 16-bit integer inputs and store the result into a vector register. No carry-in or carry-out support.", "description": "Add two unsigned 16-bit integer inputs and store the result into a vector register. No carry-in or carry-out support.", "syntax": "v_add_nc_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "", "example": "v_add_nc_u16 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_add_nc_u64", "mnemonic": "v_add_nc_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ADD NC U64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP2 vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_add_nc_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_add_u16", "mnemonic": "v_add_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ADD U16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Add two unsigned 16-bit integer inputs and store the result into a vector register. No carry-in or carry-out support.", "description": "Add two unsigned 16-bit integer inputs and store the result into a vector register. No carry-in or carry-out support.", "syntax": "v_add_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "D0.u16 = S0.u16 + S1.u16", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "Supports saturation (unsigned 16-bit integer domain).", "sourcePdfPage": 179, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_add_u32", "mnemonic": "v_add_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ADD U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Per-lane add of two 32-bit unsigned vector operands.", "description": "Add two unsigned 32-bit integer inputs and store the result into a vector register. No carry-in or carry-out support.", "syntax": "v_add_u32 VDST, S0, S1", "operands": [ { "name": "VDST", "desc": "Destination VGPR" }, { "name": "S0", "desc": "First source (VGPR/SGPR/constant)" }, { "name": "S1", "desc": "Second source VGPR" } ], "dataTypes": [ "u32" ], "semantics": "VDST[lane] = S0[lane].u32 + S1[lane].u32 for each active lane, per the EXEC mask.", "example": "v_add_u32 v2, v0, v1 // per-lane v2 = v0 + v1", "exampleSource": null, "encoding": { "format": "VOP2", "widthBits": 32 }, "executionUnit": "Vector ALU", "registerClasses": [ "VGPR" ], "memorySegment": null, "supportedTargets": [ "gfx942", "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_addc_co_u32", "mnemonic": "v_addc_co_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ADDC CO U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Add two unsigned 32-bit integer inputs and a bit from a carry-in mask, store the result into a vector register and store the carry-out mask into a…", "description": "Add two unsigned 32-bit integer inputs and a bit from a carry-in mask, store the result into a vector register and store the carry-out mask into a scalar register.", "syntax": "v_addc_co_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "tmp = 64'U(S0.u32) + 64'U(S1.u32) + VCC.u64[laneId].u64;\nVCC.u64[laneId] = tmp >= 0x100000000ULL ? 1'1U : 1'0U;\n// VCC is an UNSIGNED overflow/carry-out for V_ADDC_CO_U32.\nD0.u32 = tmp.u32", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "In VOP3 the VCC destination may be an arbitrary SGPR-pair, and the VCC source comes from the SGPR-pair at S2.u. Supports saturation (unsigned 32-bit integer domain).", "sourcePdfPage": 176, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_addc_u32", "mnemonic": "v_addc_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ADDC U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP2 vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_addc_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_alignbit_b32", "mnemonic": "v_alignbit_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ALIGNBIT B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Align a 64-bit value encoded in the first two inputs to a bit position specified in the third input, then store the result into a 32-bit vector…", "description": "Align a 64-bit value encoded in the first two inputs to a bit position specified in the third input, then store the result into a 32-bit vector register.", "syntax": "v_alignbit_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.u32 = 32'U(({ S0.u32, S1.u32 } >> S2.u32[4 : 0]) & 0xffffffffLL)", "example": "v_alignbit_b32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": " S0 carries the MSBs and S1 carries the LSBs of the value being aligned.", "sourcePdfPage": 339, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_alignbit_b32_opsel", "mnemonic": "v_alignbit_b32_opsel", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ALIGNBIT B32 OPSEL", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_alignbit_b32_opsel", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_alignbyte_b32", "mnemonic": "v_alignbyte_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ALIGNBYTE B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Align a 64-bit value encoded in the first two inputs to a byte position specified in the third input, then store the result into a 32-bit vector…", "description": "Align a 64-bit value encoded in the first two inputs to a byte position specified in the third input, then store the result into a 32-bit vector register.", "syntax": "v_alignbyte_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.u32 = 32'U(({ S0.u32, S1.u32 } >> (S2.u32[1 : 0] * 8U)) & 0xffffffffLL)", "example": "v_alignbyte_b32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": " S0 carries the MSBs and S1 carries the LSBs of the value being aligned.", "sourcePdfPage": 340, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_alignbyte_b32_fake16", "mnemonic": "v_alignbyte_b32_fake16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ALIGNBYTE B32 FAKE16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_alignbyte_b32_fake16", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_alignbyte_b32_opsel", "mnemonic": "v_alignbyte_b32_opsel", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ALIGNBYTE B32 OPSEL", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_alignbyte_b32_opsel", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_alignbyte_b32_t16", "mnemonic": "v_alignbyte_b32_t16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ALIGNBYTE B32 T16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_alignbyte_b32_t16", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_and_b16", "mnemonic": "v_and_b16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V AND B16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate bitwise AND on two vector inputs and store the result into a vector register.", "description": "Calculate bitwise AND on two vector inputs and store the result into a vector register.", "syntax": "v_and_b16", "operands": [], "dataTypes": [ "b16" ], "semantics": "", "example": "v_and_b16 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_and_b16_fake16", "mnemonic": "v_and_b16_fake16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V AND B16 FAKE16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_and_b16_fake16", "operands": [], "dataTypes": [ "b16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_and_b16_t16", "mnemonic": "v_and_b16_t16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V AND B16 T16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_and_b16_t16", "operands": [], "dataTypes": [ "b16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_and_b32", "mnemonic": "v_and_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V AND B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate bitwise AND on two vector inputs and store the result into a vector register.", "description": "Calculate bitwise AND on two vector inputs and store the result into a vector register.", "syntax": "v_and_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.u32 = (S0.u32 & S1.u32)", "example": "v_and_b32 v5, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Input and output modifiers not supported.", "sourcePdfPage": 174, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_and_or_b32", "mnemonic": "v_and_or_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V AND OR B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate bitwise AND on the first two vector inputs, then compute the bitwise OR of the intermediate result and the third vector input, then store…", "description": "Calculate bitwise AND on the first two vector inputs, then compute the bitwise OR of the intermediate result and the third vector input, then store the final result into a vector register.", "syntax": "v_and_or_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.u32 = ((S0.u32 & S1.u32) | S2.u32)", "example": "v_and_or_b32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Input and output modifiers not supported.", "sourcePdfPage": 356, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_ashr_i32", "mnemonic": "v_ashr_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ASHR I32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP2 vector instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_ashr_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_ashr_i64", "mnemonic": "v_ashr_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ASHR I64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_ashr_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_ashr_pk_i8_i32", "mnemonic": "v_ashr_pk_i8_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ASHR PK I8 I32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Given two signed 32-bit integers and a shift count, calculate the arithmetic shift right (preserving sign bit) of the two integers, saturate the two…", "description": "Given two signed 32-bit integers and a shift count, calculate the arithmetic shift right (preserving sign bit) of the two integers, saturate the two results in the signed 8-bit interval [-128, 127], pack the bytes and store the result into a vector register.", "syntax": "v_ashr_pk_i8_i32", "operands": [], "dataTypes": [ "i32", "i8" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_ashr_pk_u8_i32", "mnemonic": "v_ashr_pk_u8_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ASHR PK U8 I32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Given two signed 32-bit integers and a shift count, calculate the arithmetic shift right (preserving sign bit) of the two integers, saturate the two…", "description": "Given two signed 32-bit integers and a shift count, calculate the arithmetic shift right (preserving sign bit) of the two integers, saturate the two results in the unsigned 8-bit interval [0, 255], pack the bytes and store the result into a vector register.", "syntax": "v_ashr_pk_u8_i32", "operands": [], "dataTypes": [ "i32", "u8" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_ashrrev_i16", "mnemonic": "v_ashrrev_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ASHRREV I16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Given a shift count in the first vector input, calculate the arithmetic shift right (preserving sign bit) of the second vector input and store the…", "description": "Given a shift count in the first vector input, calculate the arithmetic shift right (preserving sign bit) of the second vector input and store the result into a vector register.", "syntax": "v_ashrrev_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "D0.i16 = (S1.i16 >> S0[3 : 0].u32)", "example": "v_ashrrev_i16 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 180, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_ashrrev_i32", "mnemonic": "v_ashrrev_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ASHRREV I32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Given a shift count in the first vector input, calculate the arithmetic shift right (preserving sign bit) of the second vector input and store the…", "description": "Given a shift count in the first vector input, calculate the arithmetic shift right (preserving sign bit) of the second vector input and store the result into a vector register.", "syntax": "v_ashrrev_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "D0.i32 = (S1.i32 >> S0[4 : 0].u32)", "example": "v_ashrrev_i32 v5, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 173, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_ashrrev_i64", "mnemonic": "v_ashrrev_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V ASHRREV I64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Given a shift count in the first vector input, calculate the arithmetic shift right (preserving sign bit) of the second vector input and store the…", "description": "Given a shift count in the first vector input, calculate the arithmetic shift right (preserving sign bit) of the second vector input and store the result into a vector register.", "syntax": "v_ashrrev_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "D0.i64 = (S1.i64 >> S0[5 : 0].u32)", "example": "v_ashrrev_i64 v[5:6], -1, -1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 365, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_bcnt_u32_b32", "mnemonic": "v_bcnt_u32_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V BCNT U32 B32", "category": "Lane Operations", "instructionClass": "vector", "summary": "Per-lane accumulating population count.", "description": "Count the number of \"1\" bits in the vector input and store the result into a vector register.", "syntax": "v_bcnt_u32_b32 VDST, S0, S1", "operands": [ { "name": "VDST", "desc": "Destination VGPR" }, { "name": "S0", "desc": "Value to count bits in" }, { "name": "S1", "desc": "Accumulator operand" } ], "dataTypes": [ "b32", "u32" ], "semantics": "VDST[lane] = popcount(S0[lane]) + S1[lane] for each active lane; pass a zero S1 to match a plain population count.", "example": "v_bcnt_u32_b32 v1, v0, 0 // v1 = popcount(v0) + 0", "exampleSource": null, "encoding": { "format": "VOP3", "widthBits": 32 }, "executionUnit": "Vector ALU", "registerClasses": [ "VGPR" ], "memorySegment": null, "supportedTargets": [ "gfx942", "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_bfe_i32", "mnemonic": "v_bfe_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V BFE I32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Extract a signed bitfield from the first input using field offset from the second input and size from the third input, then store the result into a…", "description": "Extract a signed bitfield from the first input using field offset from the second input and size from the third input, then store the result into a vector register.", "syntax": "v_bfe_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "tmp.i32 = ((S0.i32 >> S1[4 : 0].u32) & ((1 << S2[4 : 0].u32) - 1));\nD0.i32 = signext_from_bit(tmp.i32, S2[4 : 0].u32)", "example": "v_bfe_i32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 338, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_bfe_u32", "mnemonic": "v_bfe_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V BFE U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Extract an unsigned bitfield from the first input using field offset from the second input and size from the third input, then store the result into…", "description": "Extract an unsigned bitfield from the first input using field offset from the second input and size from the third input, then store the result into a vector register.", "syntax": "v_bfe_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "D0.u32 = ((S0.u32 >> S1[4 : 0].u32) & ((1U << S2[4 : 0].u32) - 1U))", "example": "v_bfe_u32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 338, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_bfi_b32", "mnemonic": "v_bfi_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V BFI B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Overwrite a bitfield in the third input with a bitfield from the second input using a mask from the first input, then store the result into a vector…", "description": "Overwrite a bitfield in the third input with a bitfield from the second input using a mask from the first input, then store the result into a vector register.", "syntax": "v_bfi_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.u32 = ((S0.u32 & S1.u32) | (~S0.u32 & S2.u32))", "example": "v_bfi_b32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 338, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_bfm_b32", "mnemonic": "v_bfm_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V BFM B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate a bitfield mask given a field offset and size and store the result into a vector register.", "description": "Calculate a bitfield mask given a field offset and size and store the result into a vector register.", "syntax": "v_bfm_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "v_bfm_b32 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_bfrev_b32", "mnemonic": "v_bfrev_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V BFREV B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Reverse the order of bits in a vector input and store the result into a vector register.", "description": "Reverse the order of bits in a vector input and store the result into a vector register.", "syntax": "v_bfrev_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.u32[31 : 0] = S0.u32[0 : 31]", "example": "v_bfrev_b32 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Input and output modifiers not supported.", "sourcePdfPage": 199, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_bitop3_b16", "mnemonic": "v_bitop3_b16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V BITOP3 B16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate the generic bitwise operation of three 16-bit vector inputs using a truth table encoded in the instruction and store the result into a…", "description": "Calculate the generic bitwise operation of three 16-bit vector inputs using a truth table encoded in the instruction and store the result into a vector register.", "syntax": "v_bitop3_b16", "operands": [], "dataTypes": [ "b16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_bitop3_b16_gfx1250", "mnemonic": "v_bitop3_b16_gfx1250", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V BITOP3 B16 GFX1250", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_bitop3_b16_gfx1250", "operands": [], "dataTypes": [ "b16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_bitop3_b32", "mnemonic": "v_bitop3_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V BITOP3 B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate the generic bitwise operation of three 32-bit vector inputs using a truth table encoded in the instruction and store the result into a…", "description": "Calculate the generic bitwise operation of three 32-bit vector inputs using a truth table encoded in the instruction and store the result into a vector register.", "syntax": "v_bitop3_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_ceil_f16", "mnemonic": "v_ceil_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CEIL F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Round the half-precision float input up to next integer and store the result in floating point format into a vector register.", "description": "Round the half-precision float input up to next integer and store the result in floating point format into a vector register.", "syntax": "v_ceil_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.f16 = trunc(S0.f16);\nif ((S0.f16 > 16'0.0) && (S0.f16 != D0.f16)) then\nD0.f16 += 16'1.0\nendif", "example": "v_ceil_f16 v5, -1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 208, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_ceil_f32", "mnemonic": "v_ceil_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CEIL F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Round the single-precision float input up to next integer and store the result in floating point format into a vector register.", "description": "Round the single-precision float input up to next integer and store the result in floating point format into a vector register.", "syntax": "v_ceil_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.f32 = trunc(S0.f32);\nif ((S0.f32 > 0.0F) && (S0.f32 != D0.f32)) then\nD0.f32 += 1.0F\nendif", "example": "v_ceil_f32 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 194, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_ceil_f64", "mnemonic": "v_ceil_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CEIL F64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Round the double-precision float input up to next integer and store the result in floating point format into a vector register.", "description": "Round the double-precision float input up to next integer and store the result in floating point format into a vector register.", "syntax": "v_ceil_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "D0.f64 = trunc(S0.f64);\nif ((S0.f64 > 0.0) && (S0.f64 != D0.f64)) then\nD0.f64 += 1.0\nendif", "example": "v_ceil_f64 v[5:6], -1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 193, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_clrexcp", "mnemonic": "v_clrexcp", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CLREXCP", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Clear this wave's exception state in the vector ALU.", "description": "Clear this wave's exception state in the vector ALU.", "syntax": "v_clrexcp", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 203, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_cmp_class_f16", "mnemonic": "v_cmp_class_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP CLASS F16", "category": "Comparison", "instructionClass": "vector", "summary": "Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a half-precision float, and set the…", "description": "Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a half-precision float, and set the per-lane condition code to the result. Store the result into VCC or a scalar register. The function reports true if the floating point value is any of the numeric types selected in the 10 bit mask according to the following list: S1.u[0] value is a signaling NAN. S1.u[1] value is a quiet NAN. S1.u[2] value is negative infinity. S1.u[3] value is a negative normal value. S1.u[4] value is a negative denormal value. S1.u[5] value is negative zero. S1.u[6] value is positive zero. S1.u[7] value is a positive denormal value. S1.u[8] value is a positive normal value. S1.u[9] value is positive infinity.", "syntax": "v_cmp_class_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "declare result : 1'U;\nif isSignalNAN(64'F(S0.f16)) then\nresult = S1.u32[0]\nelsif isQuietNAN(64'F(S0.f16)) then\nresult = S1.u32[1]\nelsif exponent(S0.f16) == 31 then\n// +-INF\nresult = S1.u32[sign(S0.f16) ? 2 : 9]\nelsif exponent(S0.f16) > 0 then\n// +-normal value\nresult = S1.u32[sign(S0.f16) ? 3 : 8]\nelsif 64'F(abs(S0.f16)) > 0.0 then\n// +-denormal value\nresult = S1.u32[sign(S0.f16) ? 4 : 7]\nelse\n// +-0.0\nresult = S1.u32[sign(S0.f16) ? 5 : 6]\nendif;\nD0.u64[laneId] = result;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_class_f16 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Note that the S1 has a format of f16 since floating point literal constants are interpreted as 16 bit value for this opcode.", "sourcePdfPage": 219, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_class_f32", "mnemonic": "v_cmp_class_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP CLASS F32", "category": "Comparison", "instructionClass": "vector", "summary": "Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a single-precision float, and set the…", "description": "Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a single-precision float, and set the per-lane condition code to the result. Store the result into VCC or a scalar register. The function reports true if the floating point value is any of the numeric types selected in the 10 bit mask according to the following list: S1.u[0] value is a signaling NAN. S1.u[1] value is a quiet NAN. S1.u[2] value is negative infinity. S1.u[3] value is a negative normal value. S1.u[4] value is a negative denormal value. S1.u[5] value is negative zero. S1.u[6] value is positive zero. S1.u[7] value is a positive denormal value. S1.u[8] value is a positive normal value. S1.u[9] value is positive infinity.", "syntax": "v_cmp_class_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "declare result : 1'U;\nif isSignalNAN(64'F(S0.f32)) then\nresult = S1.u32[0]\nelsif isQuietNAN(64'F(S0.f32)) then\nresult = S1.u32[1]\nelsif exponent(S0.f32) == 255 then\n// +-INF\nresult = S1.u32[sign(S0.f32) ? 2 : 9]\nelsif exponent(S0.f32) > 0 then\n// +-normal value\nresult = S1.u32[sign(S0.f32) ? 3 : 8]\nelsif 64'F(abs(S0.f32)) > 0.0 then\n// +-denormal value\nresult = S1.u32[sign(S0.f32) ? 4 : 7]\nelse\n// +-0.0\nresult = S1.u32[sign(S0.f32) ? 5 : 6]\nendif;\nD0.u64[laneId] = result;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_class_f32 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 216, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_class_f64", "mnemonic": "v_cmp_class_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP CLASS F64", "category": "Comparison", "instructionClass": "vector", "summary": "Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a double-precision float, and set the…", "description": "Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a double-precision float, and set the per-lane condition code to the result. Store the result into VCC or a scalar register. The function reports true if the floating point value is any of the numeric types selected in the 10 bit mask according to the following list: S1.u[0] value is a signaling NAN. S1.u[1] value is a quiet NAN. S1.u[2] value is negative infinity. S1.u[3] value is a negative normal value. S1.u[4] value is a negative denormal value. S1.u[5] value is negative zero. S1.u[6] value is positive zero. S1.u[7] value is a positive denormal value. S1.u[8] value is a positive normal value. S1.u[9] value is positive infinity.", "syntax": "v_cmp_class_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "declare result : 1'U;\nif isSignalNAN(S0.f64) then\nresult = S1.u32[0]\nelsif isQuietNAN(S0.f64) then\nresult = S1.u32[1]\nelsif exponent(S0.f64) == 2047 then\n// +-INF\nresult = S1.u32[sign(S0.f64) ? 2 : 9]\nelsif exponent(S0.f64) > 0 then\n// +-normal value\nresult = S1.u32[sign(S0.f64) ? 3 : 8]\nelsif abs(S0.f64) > 0.0 then\n// +-denormal value\nresult = S1.u32[sign(S0.f64) ? 4 : 7]\nelse\n// +-0.0\nresult = S1.u32[sign(S0.f64) ? 5 : 6]\nendif;\nD0.u64[laneId] = result;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_class_f64 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 217, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_eq_f16", "mnemonic": "v_cmp_eq_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP EQ F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_eq_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.u64[laneId] = S0.f16 == S1.f16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_eq_f16 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 221, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_eq_f32", "mnemonic": "v_cmp_eq_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP EQ F32", "category": "Comparison", "instructionClass": "vector", "summary": "Per-lane single-precision equality compare, result written as an execution-mask-width bitmask.", "description": "Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_eq_f32 VCC, S0, S1", "operands": [ { "name": "VCC", "desc": "Destination mask (VCC, or an arbitrary SGPR pair for the _e64 encoding)" }, { "name": "S0", "desc": "First source" }, { "name": "S1", "desc": "Second source" } ], "dataTypes": [ "f32" ], "semantics": "VCC[lane] = (S0[lane].f32 == S1[lane].f32) for each active lane; VCC is 32 bits wide in wave32 mode, 64 bits in wave64 mode.", "example": "v_cmp_eq_f32 vcc, v0, v1 // vcc[lane] = (v0[lane] == v1[lane])", "exampleSource": null, "encoding": { "format": "VOPC", "widthBits": 32 }, "executionUnit": "Vector ALU", "registerClasses": [ "VGPR", "VCC" ], "memorySegment": null, "supportedTargets": [ "gfx942", "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_cmp_eq_f64", "mnemonic": "v_cmp_eq_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP EQ F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_eq_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "D0.u64[laneId] = S0.f64 == S1.f64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_eq_f64 vcc, -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 235, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_eq_i16", "mnemonic": "v_cmp_eq_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP EQ I16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_eq_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "D0.u64[laneId] = S0.i16 == S1.i16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_eq_i16 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 242, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_eq_i32", "mnemonic": "v_cmp_eq_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP EQ I32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_eq_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "D0.u64[laneId] = S0.i32 == S1.i32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_eq_i32 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 249, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_eq_i64", "mnemonic": "v_cmp_eq_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP EQ I64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_eq_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "D0.u64[laneId] = S0.i64 == S1.i64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_eq_i64 vcc, -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 255, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_eq_u16", "mnemonic": "v_cmp_eq_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP EQ U16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_eq_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "D0.u64[laneId] = S0.u16 == S1.u16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_eq_u16 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 244, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_eq_u32", "mnemonic": "v_cmp_eq_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP EQ U32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_eq_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "D0.u64[laneId] = S0.u32 == S1.u32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_eq_u32 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 250, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_eq_u64", "mnemonic": "v_cmp_eq_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP EQ U64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_eq_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "D0.u64[laneId] = S0.u64 == S1.u64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_eq_u64 vcc, -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 257, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_f_f16", "mnemonic": "v_cmp_f_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP F F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 0. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 0. Store the result into VCC or a scalar register.", "syntax": "v_cmp_f_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.u64[laneId] = 1'0U;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_f_f16 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 221, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_f_f32", "mnemonic": "v_cmp_f_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP F F32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 0. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 0. Store the result into VCC or a scalar register.", "syntax": "v_cmp_f_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.u64[laneId] = 1'0U;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_f_f32 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 227, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_f_f64", "mnemonic": "v_cmp_f_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP F F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 0. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 0. Store the result into VCC or a scalar register.", "syntax": "v_cmp_f_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "D0.u64[laneId] = 1'0U;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_f_f64 vcc, -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 234, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_f_i16", "mnemonic": "v_cmp_f_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP F I16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 0. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 0. Store the result into VCC or a scalar register.", "syntax": "v_cmp_f_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "D0.u64[laneId] = 1'0U;\n// D0 = VCC in VOPC encoding.", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 241, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_cmp_f_i32", "mnemonic": "v_cmp_f_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP F I32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 0. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 0. Store the result into VCC or a scalar register.", "syntax": "v_cmp_f_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "D0.u64[laneId] = 1'0U;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_f_i32 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 248, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_f_i64", "mnemonic": "v_cmp_f_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP F I64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 0. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 0. Store the result into VCC or a scalar register.", "syntax": "v_cmp_f_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "D0.u64[laneId] = 1'0U;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_f_i64 vcc, -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 255, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_f_u16", "mnemonic": "v_cmp_f_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP F U16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 0. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 0. Store the result into VCC or a scalar register.", "syntax": "v_cmp_f_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "D0.u64[laneId] = 1'0U;\n// D0 = VCC in VOPC encoding.", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 243, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_cmp_f_u32", "mnemonic": "v_cmp_f_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP F U32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 0. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 0. Store the result into VCC or a scalar register.", "syntax": "v_cmp_f_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "D0.u64[laneId] = 1'0U;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_f_u32 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 250, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_f_u64", "mnemonic": "v_cmp_f_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP F U64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 0. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 0. Store the result into VCC or a scalar register.", "syntax": "v_cmp_f_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "D0.u64[laneId] = 1'0U;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_f_u64 vcc, -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 257, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_ge_f16", "mnemonic": "v_cmp_ge_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP GE F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_ge_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.u64[laneId] = S0.f16 >= S1.f16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_ge_f16 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 222, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_ge_f32", "mnemonic": "v_cmp_ge_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP GE F32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_ge_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.u64[laneId] = S0.f32 >= S1.f32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_ge_f32 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 229, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_ge_f64", "mnemonic": "v_cmp_ge_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP GE F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_ge_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "D0.u64[laneId] = S0.f64 >= S1.f64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_ge_f64 vcc, -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 236, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_ge_i16", "mnemonic": "v_cmp_ge_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP GE I16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_ge_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "D0.u64[laneId] = S0.i16 >= S1.i16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_ge_i16 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 243, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_ge_i32", "mnemonic": "v_cmp_ge_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP GE I32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_ge_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "D0.u64[laneId] = S0.i32 >= S1.i32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_ge_i32 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 249, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_ge_i64", "mnemonic": "v_cmp_ge_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP GE I64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_ge_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "D0.u64[laneId] = S0.i64 >= S1.i64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_ge_i64 vcc, -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 256, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_ge_u16", "mnemonic": "v_cmp_ge_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP GE U16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_ge_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "D0.u64[laneId] = S0.u16 >= S1.u16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_ge_u16 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 244, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_ge_u32", "mnemonic": "v_cmp_ge_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP GE U32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_ge_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "D0.u64[laneId] = S0.u32 >= S1.u32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_ge_u32 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 251, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_ge_u64", "mnemonic": "v_cmp_ge_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP GE U64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_ge_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "D0.u64[laneId] = S0.u64 >= S1.u64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_ge_u64 vcc, -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 258, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_gt_f16", "mnemonic": "v_cmp_gt_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP GT F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_gt_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.u64[laneId] = S0.f16 > S1.f16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_gt_f16 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 221, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_gt_f32", "mnemonic": "v_cmp_gt_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP GT F32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_gt_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.u64[laneId] = S0.f32 > S1.f32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_gt_f32 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 228, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_gt_f64", "mnemonic": "v_cmp_gt_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP GT F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_gt_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "D0.u64[laneId] = S0.f64 > S1.f64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_gt_f64 vcc, -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 235, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_gt_i16", "mnemonic": "v_cmp_gt_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP GT I16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_gt_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "D0.u64[laneId] = S0.i16 > S1.i16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_gt_i16 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 242, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_gt_i32", "mnemonic": "v_cmp_gt_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP GT I32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_gt_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "D0.u64[laneId] = S0.i32 > S1.i32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_gt_i32 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 249, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_gt_i64", "mnemonic": "v_cmp_gt_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP GT I64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_gt_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "D0.u64[laneId] = S0.i64 > S1.i64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_gt_i64 vcc, -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 256, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_gt_u16", "mnemonic": "v_cmp_gt_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP GT U16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_gt_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "D0.u64[laneId] = S0.u16 > S1.u16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_gt_u16 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 244, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_gt_u32", "mnemonic": "v_cmp_gt_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP GT U32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_gt_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "D0.u64[laneId] = S0.u32 > S1.u32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_gt_u32 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 251, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_gt_u64", "mnemonic": "v_cmp_gt_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP GT U64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_gt_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "D0.u64[laneId] = S0.u64 > S1.u64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_gt_u64 vcc, -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 257, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_le_f16", "mnemonic": "v_cmp_le_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP LE F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_le_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.u64[laneId] = S0.f16 <= S1.f16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_le_f16 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 221, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_le_f32", "mnemonic": "v_cmp_le_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP LE F32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_le_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.u64[laneId] = S0.f32 <= S1.f32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_le_f32 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 228, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_le_f64", "mnemonic": "v_cmp_le_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP LE F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_le_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "D0.u64[laneId] = S0.f64 <= S1.f64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_le_f64 vcc, -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 235, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_le_i16", "mnemonic": "v_cmp_le_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP LE I16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_le_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "D0.u64[laneId] = S0.i16 <= S1.i16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_le_i16 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 242, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_le_i32", "mnemonic": "v_cmp_le_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP LE I32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_le_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "D0.u64[laneId] = S0.i32 <= S1.i32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_le_i32 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 249, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_le_i64", "mnemonic": "v_cmp_le_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP LE I64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_le_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "D0.u64[laneId] = S0.i64 <= S1.i64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_le_i64 vcc, -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 255, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_le_u16", "mnemonic": "v_cmp_le_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP LE U16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_le_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "D0.u64[laneId] = S0.u16 <= S1.u16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_le_u16 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 244, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_le_u32", "mnemonic": "v_cmp_le_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP LE U32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_le_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "D0.u64[laneId] = S0.u32 <= S1.u32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_le_u32 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 250, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_le_u64", "mnemonic": "v_cmp_le_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP LE U64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_le_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "D0.u64[laneId] = S0.u64 <= S1.u64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_le_u64 vcc, -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 257, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_lg_f16", "mnemonic": "v_cmp_lg_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP LG F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than or greater than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is less than or greater than the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_lg_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.u64[laneId] = S0.f16 <> S1.f16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_lg_f16 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 222, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_lg_f32", "mnemonic": "v_cmp_lg_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP LG F32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than or greater than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is less than or greater than the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_lg_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.u64[laneId] = S0.f32 <> S1.f32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_lg_f32 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 229, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_lg_f64", "mnemonic": "v_cmp_lg_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP LG F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than or greater than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is less than or greater than the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_lg_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "D0.u64[laneId] = S0.f64 <> S1.f64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_lg_f64 vcc, -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 236, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_lt_f16", "mnemonic": "v_cmp_lt_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP LT F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_lt_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.u64[laneId] = S0.f16 < S1.f16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_lt_f16 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 221, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_lt_f32", "mnemonic": "v_cmp_lt_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP LT F32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_lt_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.u64[laneId] = S0.f32 < S1.f32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_lt_f32 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 228, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_lt_f64", "mnemonic": "v_cmp_lt_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP LT F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_lt_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "D0.u64[laneId] = S0.f64 < S1.f64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_lt_f64 vcc, -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 235, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_lt_i16", "mnemonic": "v_cmp_lt_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP LT I16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_lt_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "D0.u64[laneId] = S0.i16 < S1.i16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_lt_i16 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 242, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_lt_i32", "mnemonic": "v_cmp_lt_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP LT I32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_lt_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "D0.u64[laneId] = S0.i32 < S1.i32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_lt_i32 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 248, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_lt_i64", "mnemonic": "v_cmp_lt_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP LT I64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_lt_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "D0.u64[laneId] = S0.i64 < S1.i64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_lt_i64 vcc, -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 255, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_lt_u16", "mnemonic": "v_cmp_lt_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP LT U16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_lt_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "D0.u64[laneId] = S0.u16 < S1.u16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_lt_u16 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 243, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_lt_u32", "mnemonic": "v_cmp_lt_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP LT U32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_lt_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "D0.u64[laneId] = S0.u32 < S1.u32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_lt_u32 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 250, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_lt_u64", "mnemonic": "v_cmp_lt_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP LT U64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_lt_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "D0.u64[laneId] = S0.u64 < S1.u64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_lt_u64 vcc, -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 257, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_ne_i16", "mnemonic": "v_cmp_ne_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP NE I16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_ne_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "D0.u64[laneId] = S0.i16 <> S1.i16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_ne_i16 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 243, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_ne_i32", "mnemonic": "v_cmp_ne_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP NE I32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_ne_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "D0.u64[laneId] = S0.i32 <> S1.i32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_ne_i32 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 249, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_ne_i64", "mnemonic": "v_cmp_ne_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP NE I64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_ne_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "D0.u64[laneId] = S0.i64 <> S1.i64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_ne_i64 vcc, -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 256, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_ne_u16", "mnemonic": "v_cmp_ne_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP NE U16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_ne_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "D0.u64[laneId] = S0.u16 <> S1.u16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_ne_u16 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 244, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_ne_u32", "mnemonic": "v_cmp_ne_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP NE U32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_ne_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "D0.u64[laneId] = S0.u32 <> S1.u32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_ne_u32 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 251, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_ne_u64", "mnemonic": "v_cmp_ne_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP NE U64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_ne_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "D0.u64[laneId] = S0.u64 <> S1.u64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_ne_u64 vcc, -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 258, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_neq_f16", "mnemonic": "v_cmp_neq_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP NEQ F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_neq_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.u64[laneId] = !(S0.f16 == S1.f16);\n// With NAN inputs this is not the same operation as !=\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_neq_f16 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 223, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_neq_f32", "mnemonic": "v_cmp_neq_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP NEQ F32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_neq_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.u64[laneId] = !(S0.f32 == S1.f32);\n// With NAN inputs this is not the same operation as !=\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_neq_f32 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 230, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_neq_f64", "mnemonic": "v_cmp_neq_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP NEQ F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_neq_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "D0.u64[laneId] = !(S0.f64 == S1.f64);\n// With NAN inputs this is not the same operation as !=\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_neq_f64 vcc, -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 237, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_nge_f16", "mnemonic": "v_cmp_nge_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP NGE F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not greater than or equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not greater than or equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_nge_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.u64[laneId] = !(S0.f16 >= S1.f16);\n// With NAN inputs this is not the same operation as <\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_nge_f16 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 222, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_nge_f32", "mnemonic": "v_cmp_nge_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP NGE F32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not greater than or equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not greater than or equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_nge_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.u64[laneId] = !(S0.f32 >= S1.f32);\n// With NAN inputs this is not the same operation as <\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_nge_f32 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 229, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_nge_f64", "mnemonic": "v_cmp_nge_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP NGE F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not greater than or equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not greater than or equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_nge_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "D0.u64[laneId] = !(S0.f64 >= S1.f64);\n// With NAN inputs this is not the same operation as <\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_nge_f64 vcc, -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 236, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_ngt_f16", "mnemonic": "v_cmp_ngt_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP NGT F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not greater than the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is not greater than the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_ngt_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.u64[laneId] = !(S0.f16 > S1.f16);\n// With NAN inputs this is not the same operation as <=\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_ngt_f16 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 223, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_ngt_f32", "mnemonic": "v_cmp_ngt_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP NGT F32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not greater than the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is not greater than the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_ngt_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.u64[laneId] = !(S0.f32 > S1.f32);\n// With NAN inputs this is not the same operation as <=\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_ngt_f32 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 230, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_ngt_f64", "mnemonic": "v_cmp_ngt_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP NGT F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not greater than the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is not greater than the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_ngt_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "D0.u64[laneId] = !(S0.f64 > S1.f64);\n// With NAN inputs this is not the same operation as <=\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_ngt_f64 vcc, -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 237, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_nle_f16", "mnemonic": "v_cmp_nle_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP NLE F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not less than or equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not less than or equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_nle_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.u64[laneId] = !(S0.f16 <= S1.f16);\n// With NAN inputs this is not the same operation as >\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_nle_f16 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 223, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_nle_f32", "mnemonic": "v_cmp_nle_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP NLE F32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not less than or equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not less than or equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_nle_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.u64[laneId] = !(S0.f32 <= S1.f32);\n// With NAN inputs this is not the same operation as >\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_nle_f32 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 230, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_nle_f64", "mnemonic": "v_cmp_nle_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP NLE F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not less than or equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not less than or equal to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_nle_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "D0.u64[laneId] = !(S0.f64 <= S1.f64);\n// With NAN inputs this is not the same operation as >\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_nle_f64 vcc, -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 237, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_nlg_f16", "mnemonic": "v_cmp_nlg_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP NLG F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not less than or greater than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not less than or greater than the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_nlg_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.u64[laneId] = !(S0.f16 <> S1.f16);\n// With NAN inputs this is not the same operation as ==\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_nlg_f16 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 223, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_nlg_f32", "mnemonic": "v_cmp_nlg_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP NLG F32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not less than or greater than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not less than or greater than the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_nlg_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.u64[laneId] = !(S0.f32 <> S1.f32);\n// With NAN inputs this is not the same operation as ==\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_nlg_f32 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 230, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_nlg_f64", "mnemonic": "v_cmp_nlg_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP NLG F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not less than or greater than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not less than or greater than the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_nlg_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "D0.u64[laneId] = !(S0.f64 <> S1.f64);\n// With NAN inputs this is not the same operation as ==\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_nlg_f64 vcc, -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 237, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_nlt_f16", "mnemonic": "v_cmp_nlt_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP NLT F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not less than the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is not less than the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_nlt_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.u64[laneId] = !(S0.f16 < S1.f16);\n// With NAN inputs this is not the same operation as >=\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_nlt_f16 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 224, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_nlt_f32", "mnemonic": "v_cmp_nlt_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP NLT F32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not less than the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is not less than the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_nlt_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.u64[laneId] = !(S0.f32 < S1.f32);\n// With NAN inputs this is not the same operation as >=\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_nlt_f32 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 231, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_nlt_f64", "mnemonic": "v_cmp_nlt_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP NLT F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not less than the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is not less than the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_nlt_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "D0.u64[laneId] = !(S0.f64 < S1.f64);\n// With NAN inputs this is not the same operation as >=\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_nlt_f64 vcc, -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 238, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_o_f16", "mnemonic": "v_cmp_o_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP O F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is orderable to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is orderable to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_o_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.u64[laneId] = (!isNAN(64'F(S0.f16)) && !isNAN(64'F(S1.f16)));\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_o_f16 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 222, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_o_f32", "mnemonic": "v_cmp_o_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP O F32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is orderable to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is orderable to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_o_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.u64[laneId] = (!isNAN(64'F(S0.f32)) && !isNAN(64'F(S1.f32)));\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_o_f32 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 229, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_o_f64", "mnemonic": "v_cmp_o_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP O F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is orderable to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is orderable to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_o_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "D0.u64[laneId] = (!isNAN(S0.f64) && !isNAN(S1.f64));\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_o_f64 vcc, -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 236, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_t_f16", "mnemonic": "v_cmp_t_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP T F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1. Store the result into VCC or a scalar register.", "syntax": "v_cmp_t_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": "v_cmp_t_f16 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_t_f32", "mnemonic": "v_cmp_t_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP T F32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1. Store the result into VCC or a scalar register.", "syntax": "v_cmp_t_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": "v_cmp_t_f32 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_t_f64", "mnemonic": "v_cmp_t_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP T F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1. Store the result into VCC or a scalar register.", "syntax": "v_cmp_t_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": "v_cmp_t_f64 vcc, -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_t_i16", "mnemonic": "v_cmp_t_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP T I16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1. Store the result into VCC or a scalar register.", "syntax": "v_cmp_t_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "D0.u64[laneId] = 1'1U;\n// D0 = VCC in VOPC encoding.", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 243, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_cmp_t_i32", "mnemonic": "v_cmp_t_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP T I32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1. Store the result into VCC or a scalar register.", "syntax": "v_cmp_t_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "D0.u64[laneId] = 1'1U;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_t_i32 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 250, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_t_i64", "mnemonic": "v_cmp_t_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP T I64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1. Store the result into VCC or a scalar register.", "syntax": "v_cmp_t_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "D0.u64[laneId] = 1'1U;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_t_i64 vcc, -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 256, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_t_u16", "mnemonic": "v_cmp_t_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP T U16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1. Store the result into VCC or a scalar register.", "syntax": "v_cmp_t_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "D0.u64[laneId] = 1'1U;\n// D0 = VCC in VOPC encoding.", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 245, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_cmp_t_u32", "mnemonic": "v_cmp_t_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP T U32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1. Store the result into VCC or a scalar register.", "syntax": "v_cmp_t_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "D0.u64[laneId] = 1'1U;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_t_u32 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 251, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_t_u64", "mnemonic": "v_cmp_t_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP T U64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1. Store the result into VCC or a scalar register.", "syntax": "v_cmp_t_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "D0.u64[laneId] = 1'1U;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_t_u64 vcc, -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 258, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_tru_f16", "mnemonic": "v_cmp_tru_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP TRU F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1. Store the result into VCC or a scalar register.", "syntax": "v_cmp_tru_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.u64[laneId] = 1'1U;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_tru_f16 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 224, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_tru_f32", "mnemonic": "v_cmp_tru_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP TRU F32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1. Store the result into VCC or a scalar register.", "syntax": "v_cmp_tru_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.u64[laneId] = 1'1U;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_tru_f32 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 231, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_tru_f64", "mnemonic": "v_cmp_tru_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP TRU F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1. Store the result into VCC or a scalar register.", "syntax": "v_cmp_tru_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "D0.u64[laneId] = 1'1U;\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_tru_f64 vcc, -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 238, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_u_f16", "mnemonic": "v_cmp_u_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP U F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not orderable to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is not orderable to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_u_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.u64[laneId] = (isNAN(64'F(S0.f16)) || isNAN(64'F(S1.f16)));\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_u_f16 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 222, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_u_f32", "mnemonic": "v_cmp_u_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP U F32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not orderable to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is not orderable to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_u_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.u64[laneId] = (isNAN(64'F(S0.f32)) || isNAN(64'F(S1.f32)));\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_u_f32 vcc, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 229, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmp_u_f64", "mnemonic": "v_cmp_u_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMP U F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not orderable to the second input. Store the result into VCC or a scalar register.", "description": "Set the per-lane condition code to 1 iff the first input is not orderable to the second input. Store the result into VCC or a scalar register.", "syntax": "v_cmp_u_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "D0.u64[laneId] = (isNAN(S0.f64) || isNAN(S1.f64));\n// D0 = VCC in VOPC encoding.", "example": "v_cmp_u_f64 vcc, -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 236, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmps_eq_f32", "mnemonic": "v_cmps_eq_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPS EQ F32", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmps_eq_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmps_eq_f64", "mnemonic": "v_cmps_eq_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPS EQ F64", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmps_eq_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmps_f_f32", "mnemonic": "v_cmps_f_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPS F F32", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmps_f_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmps_f_f64", "mnemonic": "v_cmps_f_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPS F F64", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmps_f_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmps_ge_f32", "mnemonic": "v_cmps_ge_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPS GE F32", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmps_ge_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmps_ge_f64", "mnemonic": "v_cmps_ge_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPS GE F64", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmps_ge_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmps_gt_f32", "mnemonic": "v_cmps_gt_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPS GT F32", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmps_gt_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmps_gt_f64", "mnemonic": "v_cmps_gt_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPS GT F64", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmps_gt_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmps_le_f32", "mnemonic": "v_cmps_le_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPS LE F32", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmps_le_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmps_le_f64", "mnemonic": "v_cmps_le_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPS LE F64", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmps_le_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmps_lg_f32", "mnemonic": "v_cmps_lg_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPS LG F32", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmps_lg_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmps_lg_f64", "mnemonic": "v_cmps_lg_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPS LG F64", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmps_lg_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmps_lt_f32", "mnemonic": "v_cmps_lt_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPS LT F32", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmps_lt_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmps_lt_f64", "mnemonic": "v_cmps_lt_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPS LT F64", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmps_lt_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmps_neq_f32", "mnemonic": "v_cmps_neq_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPS NEQ F32", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmps_neq_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmps_neq_f64", "mnemonic": "v_cmps_neq_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPS NEQ F64", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmps_neq_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmps_nge_f32", "mnemonic": "v_cmps_nge_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPS NGE F32", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmps_nge_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmps_nge_f64", "mnemonic": "v_cmps_nge_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPS NGE F64", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmps_nge_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmps_ngt_f32", "mnemonic": "v_cmps_ngt_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPS NGT F32", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmps_ngt_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmps_ngt_f64", "mnemonic": "v_cmps_ngt_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPS NGT F64", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmps_ngt_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmps_nle_f32", "mnemonic": "v_cmps_nle_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPS NLE F32", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmps_nle_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmps_nle_f64", "mnemonic": "v_cmps_nle_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPS NLE F64", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmps_nle_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmps_nlg_f32", "mnemonic": "v_cmps_nlg_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPS NLG F32", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmps_nlg_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmps_nlg_f64", "mnemonic": "v_cmps_nlg_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPS NLG F64", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmps_nlg_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmps_nlt_f32", "mnemonic": "v_cmps_nlt_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPS NLT F32", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmps_nlt_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmps_nlt_f64", "mnemonic": "v_cmps_nlt_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPS NLT F64", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmps_nlt_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmps_o_f32", "mnemonic": "v_cmps_o_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPS O F32", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmps_o_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmps_o_f64", "mnemonic": "v_cmps_o_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPS O F64", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmps_o_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmps_tru_f32", "mnemonic": "v_cmps_tru_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPS TRU F32", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmps_tru_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmps_tru_f64", "mnemonic": "v_cmps_tru_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPS TRU F64", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmps_tru_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmps_u_f32", "mnemonic": "v_cmps_u_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPS U F32", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmps_u_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmps_u_f64", "mnemonic": "v_cmps_u_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPS U F64", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmps_u_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmpsx_eq_f32", "mnemonic": "v_cmpsx_eq_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPSX EQ F32", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f32 data. 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(Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmpsx_eq_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmpsx_f_f32", "mnemonic": "v_cmpsx_f_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPSX F F32", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmpsx_f_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmpsx_f_f64", "mnemonic": "v_cmpsx_f_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPSX F F64", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmpsx_f_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmpsx_ge_f32", "mnemonic": "v_cmpsx_ge_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPSX GE F32", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmpsx_ge_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmpsx_ge_f64", "mnemonic": "v_cmpsx_ge_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPSX GE F64", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmpsx_ge_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmpsx_gt_f32", "mnemonic": "v_cmpsx_gt_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPSX GT F32", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f32 data. 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(Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmpsx_gt_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmpsx_le_f32", "mnemonic": "v_cmpsx_le_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPSX LE F32", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmpsx_le_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmpsx_le_f64", "mnemonic": "v_cmpsx_le_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPSX LE F64", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmpsx_le_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmpsx_lg_f32", "mnemonic": "v_cmpsx_lg_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPSX LG F32", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmpsx_lg_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmpsx_lg_f64", "mnemonic": "v_cmpsx_lg_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPSX LG F64", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmpsx_lg_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmpsx_lt_f32", "mnemonic": "v_cmpsx_lt_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPSX LT F32", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f32 data. 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(Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmpsx_neq_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmpsx_nge_f32", "mnemonic": "v_cmpsx_nge_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPSX NGE F32", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f32 data. 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(Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmpsx_nge_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmpsx_ngt_f32", "mnemonic": "v_cmpsx_ngt_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPSX NGT F32", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmpsx_ngt_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmpsx_ngt_f64", "mnemonic": "v_cmpsx_ngt_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPSX NGT F64", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmpsx_ngt_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmpsx_nle_f32", "mnemonic": "v_cmpsx_nle_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPSX NLE F32", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmpsx_nle_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmpsx_nle_f64", "mnemonic": "v_cmpsx_nle_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPSX NLE F64", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmpsx_nle_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmpsx_nlg_f32", "mnemonic": "v_cmpsx_nlg_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPSX NLG F32", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmpsx_nlg_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmpsx_nlg_f64", "mnemonic": "v_cmpsx_nlg_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPSX NLG F64", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmpsx_nlg_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmpsx_nlt_f32", "mnemonic": "v_cmpsx_nlt_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPSX NLT F32", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmpsx_nlt_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmpsx_nlt_f64", "mnemonic": "v_cmpsx_nlt_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPSX NLT F64", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmpsx_nlt_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmpsx_o_f32", "mnemonic": "v_cmpsx_o_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPSX O F32", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmpsx_o_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmpsx_o_f64", "mnemonic": "v_cmpsx_o_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPSX O F64", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmpsx_o_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmpsx_tru_f32", "mnemonic": "v_cmpsx_tru_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPSX TRU F32", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmpsx_tru_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmpsx_tru_f64", "mnemonic": "v_cmpsx_tru_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPSX TRU F64", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmpsx_tru_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmpsx_u_f32", "mnemonic": "v_cmpsx_u_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPSX U F32", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmpsx_u_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmpsx_u_f64", "mnemonic": "v_cmpsx_u_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPSX U F64", "category": "Comparison", "instructionClass": "vector", "summary": "AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cmpsx_u_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cmpx_class_f16", "mnemonic": "v_cmpx_class_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX CLASS F16", "category": "Comparison", "instructionClass": "vector", "summary": "Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a half-precision float, and set the…", "description": "Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a half-precision float, and set the per-lane condition code to the result. Store the result into the EXEC mask and to VCC or a scalar register. The function reports true if the floating point value is any of the numeric types selected in the 10 bit mask according to the following list: S1.u[0] value is a signaling NAN. S1.u[1] value is a quiet NAN. S1.u[2] value is negative infinity. S1.u[3] value is a negative normal value. S1.u[4] value is a negative denormal value. S1.u[5] value is negative zero. S1.u[6] value is positive zero. S1.u[7] value is a positive denormal value. S1.u[8] value is a positive normal value. S1.u[9] value is positive infinity.", "syntax": "v_cmpx_class_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "declare result : 1'U;\nif isSignalNAN(64'F(S0.f16)) then\nresult = S1.u32[0]\nelsif isQuietNAN(64'F(S0.f16)) then\nresult = S1.u32[1]\nelsif exponent(S0.f16) == 31 then\n// +-INF\nresult = S1.u32[sign(S0.f16) ? 2 : 9]\nelsif exponent(S0.f16) > 0 then\n// +-normal value\nresult = S1.u32[sign(S0.f16) ? 3 : 8]\nelsif 64'F(abs(S0.f16)) > 0.0 then\n// +-denormal value\nresult = S1.u32[sign(S0.f16) ? 4 : 7]\nelse\n// +-0.0\nresult = S1.u32[sign(S0.f16) ? 5 : 6]\nendif;\nEXEC.u64[laneId] = D0.u64[laneId] = result", "example": "v_cmpx_class_f16 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Note that the S1 has a format of f16 since floating point literal constants are interpreted as 16 bit value for this opcode.", "sourcePdfPage": 220, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_class_f32", "mnemonic": "v_cmpx_class_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX CLASS F32", "category": "Comparison", "instructionClass": "vector", "summary": "Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a single-precision float, and set the…", "description": "Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a single-precision float, and set the per-lane condition code to the result. Store the result into the EXEC mask and to VCC or a scalar register. The function reports true if the floating point value is any of the numeric types selected in the 10 bit mask according to the following list: S1.u[0] value is a signaling NAN. S1.u[1] value is a quiet NAN. S1.u[2] value is negative infinity. S1.u[3] value is a negative normal value. S1.u[4] value is a negative denormal value. S1.u[5] value is negative zero. S1.u[6] value is positive zero. S1.u[7] value is a positive denormal value. S1.u[8] value is a positive normal value. S1.u[9] value is positive infinity.", "syntax": "v_cmpx_class_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "declare result : 1'U;\nif isSignalNAN(64'F(S0.f32)) then\nresult = S1.u32[0]\nelsif isQuietNAN(64'F(S0.f32)) then\nresult = S1.u32[1]\nelsif exponent(S0.f32) == 255 then\n// +-INF\nresult = S1.u32[sign(S0.f32) ? 2 : 9]\nelsif exponent(S0.f32) > 0 then\n// +-normal value\nresult = S1.u32[sign(S0.f32) ? 3 : 8]\nelsif 64'F(abs(S0.f32)) > 0.0 then\n// +-denormal value\nresult = S1.u32[sign(S0.f32) ? 4 : 7]\nelse\n// +-0.0\nresult = S1.u32[sign(S0.f32) ? 5 : 6]\nendif;\nEXEC.u64[laneId] = D0.u64[laneId] = result", "example": "v_cmpx_class_f32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 216, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_class_f64", "mnemonic": "v_cmpx_class_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX CLASS F64", "category": "Comparison", "instructionClass": "vector", "summary": "Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a double-precision float, and set the…", "description": "Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a double-precision float, and set the per-lane condition code to the result. Store the result into the EXEC mask and to VCC or a scalar register. The function reports true if the floating point value is any of the numeric types selected in the 10 bit mask according to the following list: S1.u[0] value is a signaling NAN. S1.u[1] value is a quiet NAN. S1.u[2] value is negative infinity. S1.u[3] value is a negative normal value. S1.u[4] value is a negative denormal value. S1.u[5] value is negative zero. S1.u[6] value is positive zero. S1.u[7] value is a positive denormal value. S1.u[8] value is a positive normal value. S1.u[9] value is positive infinity.", "syntax": "v_cmpx_class_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "declare result : 1'U;\nif isSignalNAN(S0.f64) then\nresult = S1.u32[0]\nelsif isQuietNAN(S0.f64) then\nresult = S1.u32[1]\nelsif exponent(S0.f64) == 2047 then\n// +-INF\nresult = S1.u32[sign(S0.f64) ? 2 : 9]\nelsif exponent(S0.f64) > 0 then\n// +-normal value\nresult = S1.u32[sign(S0.f64) ? 3 : 8]\nelsif abs(S0.f64) > 0.0 then\n// +-denormal value\nresult = S1.u32[sign(S0.f64) ? 4 : 7]\nelse\n// +-0.0\nresult = S1.u32[sign(S0.f64) ? 5 : 6]\nendif;\nEXEC.u64[laneId] = D0.u64[laneId] = result", "example": "v_cmpx_class_f64 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 218, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_eq_f16", "mnemonic": "v_cmpx_eq_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX EQ F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_eq_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.f16 == S1.f16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_eq_f16 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 224, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_eq_f32", "mnemonic": "v_cmpx_eq_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX EQ F32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_eq_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.f32 == S1.f32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_eq_f32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 231, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_eq_f64", "mnemonic": "v_cmpx_eq_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX EQ F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_eq_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.f64 == S1.f64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_eq_f64 -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 238, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_eq_i16", "mnemonic": "v_cmpx_eq_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX EQ I16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_eq_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.i16 == S1.i16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_eq_i16 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 245, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_eq_i32", "mnemonic": "v_cmpx_eq_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX EQ I32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_eq_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.i32 == S1.i32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_eq_i32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 252, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_eq_i64", "mnemonic": "v_cmpx_eq_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX EQ I64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_eq_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.i64 == S1.i64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_eq_i64 -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 259, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_eq_u16", "mnemonic": "v_cmpx_eq_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX EQ U16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_eq_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.u16 == S1.u16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_eq_u16 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 247, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_eq_u32", "mnemonic": "v_cmpx_eq_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX EQ U32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_eq_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.u32 == S1.u32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_eq_u32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 254, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_eq_u64", "mnemonic": "v_cmpx_eq_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX EQ U64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_eq_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.u64 == S1.u64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_eq_u64 -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 260, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_f_f16", "mnemonic": "v_cmpx_f_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX F F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 0. Store the result into the EXEC mask and to VCC or a scalar register.", "description": "Set the per-lane condition code to 0. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_f_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = 1'0U;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_f_f16 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 224, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_f_f32", "mnemonic": "v_cmpx_f_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX F F32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 0. Store the result into the EXEC mask and to VCC or a scalar register.", "description": "Set the per-lane condition code to 0. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_f_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = 1'0U;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_f_f32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 231, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_f_f64", "mnemonic": "v_cmpx_f_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX F F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 0. Store the result into the EXEC mask and to VCC or a scalar register.", "description": "Set the per-lane condition code to 0. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_f_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = 1'0U;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_f_f64 -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 238, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_f_i16", "mnemonic": "v_cmpx_f_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX F I16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 0. Store the result into the EXEC mask and to VCC or a scalar register.", "description": "Set the per-lane condition code to 0. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_f_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = 1'0U;\n// D0 = VCC in VOPC encoding.", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 245, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_cmpx_f_i32", "mnemonic": "v_cmpx_f_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX F I32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 0. Store the result into the EXEC mask and to VCC or a scalar register.", "description": "Set the per-lane condition code to 0. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_f_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = 1'0U;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_f_i32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 252, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_f_i64", "mnemonic": "v_cmpx_f_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX F I64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 0. Store the result into the EXEC mask and to VCC or a scalar register.", "description": "Set the per-lane condition code to 0. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_f_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = 1'0U;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_f_i64 -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 258, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_f_u16", "mnemonic": "v_cmpx_f_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX F U16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 0. Store the result into the EXEC mask and to VCC or a scalar register.", "description": "Set the per-lane condition code to 0. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_f_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = 1'0U;\n// D0 = VCC in VOPC encoding.", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 247, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_cmpx_f_u32", "mnemonic": "v_cmpx_f_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX F U32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 0. Store the result into the EXEC mask and to VCC or a scalar register.", "description": "Set the per-lane condition code to 0. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_f_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = 1'0U;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_f_u32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 253, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_f_u64", "mnemonic": "v_cmpx_f_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX F U64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 0. Store the result into the EXEC mask and to VCC or a scalar register.", "description": "Set the per-lane condition code to 0. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_f_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = 1'0U;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_f_u64 -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 260, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_ge_f16", "mnemonic": "v_cmpx_ge_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX GE F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_ge_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.f16 >= S1.f16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_ge_f16 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 225, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_ge_f32", "mnemonic": "v_cmpx_ge_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX GE F32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_ge_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.f32 >= S1.f32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_ge_f32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 232, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_ge_f64", "mnemonic": "v_cmpx_ge_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX GE F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_ge_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.f64 >= S1.f64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_ge_f64 -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 239, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_ge_i16", "mnemonic": "v_cmpx_ge_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX GE I16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_ge_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.i16 >= S1.i16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_ge_i16 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 246, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_ge_i32", "mnemonic": "v_cmpx_ge_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX GE I32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_ge_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.i32 >= S1.i32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_ge_i32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 253, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_ge_i64", "mnemonic": "v_cmpx_ge_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX GE I64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_ge_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.i64 >= S1.i64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_ge_i64 -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 259, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_ge_u16", "mnemonic": "v_cmpx_ge_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX GE U16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_ge_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.u16 >= S1.u16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_ge_u16 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 248, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_ge_u32", "mnemonic": "v_cmpx_ge_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX GE U32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_ge_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.u32 >= S1.u32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_ge_u32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 254, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_ge_u64", "mnemonic": "v_cmpx_ge_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX GE U64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_ge_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.u64 >= S1.u64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_ge_u64 -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 261, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_gt_f16", "mnemonic": "v_cmpx_gt_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX GT F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_gt_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.f16 > S1.f16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_gt_f16 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 225, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_gt_f32", "mnemonic": "v_cmpx_gt_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX GT F32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_gt_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.f32 > S1.f32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_gt_f32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 232, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_gt_f64", "mnemonic": "v_cmpx_gt_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX GT F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_gt_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.f64 > S1.f64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_gt_f64 -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 239, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_gt_i16", "mnemonic": "v_cmpx_gt_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX GT I16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_gt_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.i16 > S1.i16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_gt_i16 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 246, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_gt_i32", "mnemonic": "v_cmpx_gt_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX GT I32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_gt_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.i32 > S1.i32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_gt_i32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 252, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_gt_i64", "mnemonic": "v_cmpx_gt_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX GT I64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_gt_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.i64 > S1.i64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_gt_i64 -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 259, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_gt_u16", "mnemonic": "v_cmpx_gt_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX GT U16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_gt_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.u16 > S1.u16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_gt_u16 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 247, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_gt_u32", "mnemonic": "v_cmpx_gt_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX GT U32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_gt_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.u32 > S1.u32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_gt_u32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 254, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_gt_u64", "mnemonic": "v_cmpx_gt_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX GT U64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is greater than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_gt_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.u64 > S1.u64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_gt_u64 -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 261, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_le_f16", "mnemonic": "v_cmpx_le_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX LE F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_le_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.f16 <= S1.f16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_le_f16 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 225, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_le_f32", "mnemonic": "v_cmpx_le_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX LE F32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_le_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.f32 <= S1.f32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_le_f32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 232, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_le_f64", "mnemonic": "v_cmpx_le_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX LE F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_le_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.f64 <= S1.f64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_le_f64 -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 239, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_le_i16", "mnemonic": "v_cmpx_le_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX LE I16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_le_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.i16 <= S1.i16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_le_i16 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 245, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_le_i32", "mnemonic": "v_cmpx_le_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX LE I32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_le_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.i32 <= S1.i32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_le_i32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 252, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_le_i64", "mnemonic": "v_cmpx_le_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX LE I64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_le_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.i64 <= S1.i64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_le_i64 -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 259, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_le_u16", "mnemonic": "v_cmpx_le_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX LE U16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_le_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.u16 <= S1.u16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_le_u16 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 247, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_le_u32", "mnemonic": "v_cmpx_le_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX LE U32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_le_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.u32 <= S1.u32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_le_u32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 254, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_le_u64", "mnemonic": "v_cmpx_le_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX LE U64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_le_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.u64 <= S1.u64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_le_u64 -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 260, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_lg_f16", "mnemonic": "v_cmpx_lg_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX LG F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than or greater than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is less than or greater than the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_lg_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.f16 <> S1.f16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_lg_f16 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 225, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_lg_f32", "mnemonic": "v_cmpx_lg_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX LG F32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than or greater than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is less than or greater than the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_lg_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.f32 <> S1.f32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_lg_f32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 232, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_lg_f64", "mnemonic": "v_cmpx_lg_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX LG F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than or greater than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is less than or greater than the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_lg_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.f64 <> S1.f64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_lg_f64 -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 239, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_lt_f16", "mnemonic": "v_cmpx_lt_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX LT F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_lt_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.f16 < S1.f16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_lt_f16 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 224, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_lt_f32", "mnemonic": "v_cmpx_lt_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX LT F32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_lt_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.f32 < S1.f32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_lt_f32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 231, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_lt_f64", "mnemonic": "v_cmpx_lt_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX LT F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_lt_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.f64 < S1.f64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_lt_f64 -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 238, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_lt_i16", "mnemonic": "v_cmpx_lt_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX LT I16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_lt_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.i16 < S1.i16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_lt_i16 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 245, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_lt_i32", "mnemonic": "v_cmpx_lt_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX LT I32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_lt_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.i32 < S1.i32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_lt_i32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 252, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_lt_i64", "mnemonic": "v_cmpx_lt_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX LT I64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_lt_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.i64 < S1.i64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_lt_i64 -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 258, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_lt_u16", "mnemonic": "v_cmpx_lt_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX LT U16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_lt_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.u16 < S1.u16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_lt_u16 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 247, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_lt_u32", "mnemonic": "v_cmpx_lt_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX LT U32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_lt_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.u32 < S1.u32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_lt_u32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 253, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_lt_u64", "mnemonic": "v_cmpx_lt_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX LT U64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is less than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_lt_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.u64 < S1.u64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_lt_u64 -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 260, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_ne_i16", "mnemonic": "v_cmpx_ne_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX NE I16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_ne_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.i16 <> S1.i16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_ne_i16 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 246, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_ne_i32", "mnemonic": "v_cmpx_ne_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX NE I32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_ne_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.i32 <> S1.i32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_ne_i32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 253, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_ne_i64", "mnemonic": "v_cmpx_ne_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX NE I64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_ne_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.i64 <> S1.i64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_ne_i64 -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 259, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_ne_u16", "mnemonic": "v_cmpx_ne_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX NE U16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_ne_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.u16 <> S1.u16;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_ne_u16 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 248, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_ne_u32", "mnemonic": "v_cmpx_ne_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX NE U32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_ne_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.u32 <> S1.u32;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_ne_u32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 254, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_ne_u64", "mnemonic": "v_cmpx_ne_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX NE U64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_ne_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = S0.u64 <> S1.u64;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_ne_u64 -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 261, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_neq_f16", "mnemonic": "v_cmpx_neq_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX NEQ F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_neq_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f16 == S1.f16);\n// With NAN inputs this is not the same operation as !=\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_neq_f16 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 227, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_neq_f32", "mnemonic": "v_cmpx_neq_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX NEQ F32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_neq_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f32 == S1.f32);\n// With NAN inputs this is not the same operation as !=\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_neq_f32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 234, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_neq_f64", "mnemonic": "v_cmpx_neq_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX NEQ F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_neq_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f64 == S1.f64);\n// With NAN inputs this is not the same operation as !=\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_neq_f64 -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 241, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_nge_f16", "mnemonic": "v_cmpx_nge_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX NGE F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not greater than or equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not greater than or equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_nge_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f16 >= S1.f16);\n// With NAN inputs this is not the same operation as <\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_nge_f16 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 226, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_nge_f32", "mnemonic": "v_cmpx_nge_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX NGE F32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not greater than or equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not greater than or equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_nge_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f32 >= S1.f32);\n// With NAN inputs this is not the same operation as <\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_nge_f32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 233, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_nge_f64", "mnemonic": "v_cmpx_nge_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX NGE F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not greater than or equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not greater than or equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_nge_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f64 >= S1.f64);\n// With NAN inputs this is not the same operation as <\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_nge_f64 -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 240, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_ngt_f16", "mnemonic": "v_cmpx_ngt_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX NGT F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not greater than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not greater than the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_ngt_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f16 > S1.f16);\n// With NAN inputs this is not the same operation as <=\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_ngt_f16 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 226, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_ngt_f32", "mnemonic": "v_cmpx_ngt_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX NGT F32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not greater than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not greater than the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_ngt_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f32 > S1.f32);\n// With NAN inputs this is not the same operation as <=\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_ngt_f32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 233, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_ngt_f64", "mnemonic": "v_cmpx_ngt_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX NGT F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not greater than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not greater than the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_ngt_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f64 > S1.f64);\n// With NAN inputs this is not the same operation as <=\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_ngt_f64 -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 240, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_nle_f16", "mnemonic": "v_cmpx_nle_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX NLE F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not less than or equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not less than or equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_nle_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f16 <= S1.f16);\n// With NAN inputs this is not the same operation as >\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_nle_f16 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 227, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_nle_f32", "mnemonic": "v_cmpx_nle_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX NLE F32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not less than or equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not less than or equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_nle_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f32 <= S1.f32);\n// With NAN inputs this is not the same operation as >\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_nle_f32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 234, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_nle_f64", "mnemonic": "v_cmpx_nle_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX NLE F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not less than or equal to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not less than or equal to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_nle_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f64 <= S1.f64);\n// With NAN inputs this is not the same operation as >\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_nle_f64 -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 241, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_nlg_f16", "mnemonic": "v_cmpx_nlg_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX NLG F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not less than or greater than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not less than or greater than the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_nlg_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f16 <> S1.f16);\n// With NAN inputs this is not the same operation as ==\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_nlg_f16 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 226, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_nlg_f32", "mnemonic": "v_cmpx_nlg_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX NLG F32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not less than or greater than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not less than or greater than the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_nlg_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f32 <> S1.f32);\n// With NAN inputs this is not the same operation as ==\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_nlg_f32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 233, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_nlg_f64", "mnemonic": "v_cmpx_nlg_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX NLG F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not less than or greater than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not less than or greater than the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_nlg_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f64 <> S1.f64);\n// With NAN inputs this is not the same operation as ==\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_nlg_f64 -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 240, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_nlt_f16", "mnemonic": "v_cmpx_nlt_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX NLT F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not less than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not less than the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_nlt_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f16 < S1.f16);\n// With NAN inputs this is not the same operation as >=\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_nlt_f16 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 227, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_nlt_f32", "mnemonic": "v_cmpx_nlt_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX NLT F32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not less than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not less than the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_nlt_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f32 < S1.f32);\n// With NAN inputs this is not the same operation as >=\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_nlt_f32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 234, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_nlt_f64", "mnemonic": "v_cmpx_nlt_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX NLT F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not less than the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not less than the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_nlt_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = !(S0.f64 < S1.f64);\n// With NAN inputs this is not the same operation as >=\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_nlt_f64 -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 241, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_o_f16", "mnemonic": "v_cmpx_o_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX O F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is orderable to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is orderable to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_o_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = (!isNAN(64'F(S0.f16)) && !isNAN(64'F(S1.f16)));\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_o_f16 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 225, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_o_f32", "mnemonic": "v_cmpx_o_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX O F32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is orderable to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is orderable to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_o_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = (!isNAN(64'F(S0.f32)) && !isNAN(64'F(S1.f32)));\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_o_f32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 232, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_o_f64", "mnemonic": "v_cmpx_o_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX O F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is orderable to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is orderable to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_o_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = (!isNAN(S0.f64) && !isNAN(S1.f64));\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_o_f64 -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 239, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_t_f16", "mnemonic": "v_cmpx_t_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX T F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1. Store the result into the EXEC mask.", "description": "Set the per-lane condition code to 1. Store the result into the EXEC mask.", "syntax": "v_cmpx_t_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": "v_cmpx_t_f16 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_t_f32", "mnemonic": "v_cmpx_t_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX T F32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1. Store the result into the EXEC mask.", "description": "Set the per-lane condition code to 1. Store the result into the EXEC mask.", "syntax": "v_cmpx_t_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": "v_cmpx_t_f32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_t_f64", "mnemonic": "v_cmpx_t_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX T F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1. Store the result into the EXEC mask.", "description": "Set the per-lane condition code to 1. Store the result into the EXEC mask.", "syntax": "v_cmpx_t_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": "v_cmpx_t_f64 -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_t_i16", "mnemonic": "v_cmpx_t_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX T I16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register.", "description": "Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_t_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = 1'1U;\n// D0 = VCC in VOPC encoding.", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 246, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_cmpx_t_i32", "mnemonic": "v_cmpx_t_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX T I32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register.", "description": "Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_t_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = 1'1U;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_t_i32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 253, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_t_i64", "mnemonic": "v_cmpx_t_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX T I64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register.", "description": "Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_t_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = 1'1U;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_t_i64 -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 260, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_t_u16", "mnemonic": "v_cmpx_t_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX T U16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register.", "description": "Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_t_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = 1'1U;\n// D0 = VCC in VOPC encoding.", "example": null, "exampleSource": null, "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 248, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_cmpx_t_u32", "mnemonic": "v_cmpx_t_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX T U32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register.", "description": "Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_t_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = 1'1U;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_t_u32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 255, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_t_u64", "mnemonic": "v_cmpx_t_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX T U64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register.", "description": "Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_t_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = 1'1U;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_t_u64 -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 261, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_tru_f16", "mnemonic": "v_cmpx_tru_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX TRU F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register.", "description": "Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_tru_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = 1'1U;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_tru_f16 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 227, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_tru_f32", "mnemonic": "v_cmpx_tru_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX TRU F32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register.", "description": "Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_tru_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = 1'1U;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_tru_f32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 234, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_tru_f64", "mnemonic": "v_cmpx_tru_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX TRU F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register.", "description": "Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_tru_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = 1'1U;\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_tru_f64 -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 241, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_u_f16", "mnemonic": "v_cmpx_u_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX U F16", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not orderable to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not orderable to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_u_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = (isNAN(64'F(S0.f16)) || isNAN(64'F(S1.f16)));\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_u_f16 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 226, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_u_f32", "mnemonic": "v_cmpx_u_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX U F32", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not orderable to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not orderable to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_u_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = (isNAN(64'F(S0.f32)) || isNAN(64'F(S1.f32)));\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_u_f32 -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 233, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cmpx_u_f64", "mnemonic": "v_cmpx_u_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CMPX U F64", "category": "Comparison", "instructionClass": "vector", "summary": "Set the per-lane condition code to 1 iff the first input is not orderable to the second input.", "description": "Set the per-lane condition code to 1 iff the first input is not orderable to the second input. Store the result into the EXEC mask and to VCC or a scalar register.", "syntax": "v_cmpx_u_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "EXEC.u64[laneId] = D0.u64[laneId] = (isNAN(S0.f64) || isNAN(S1.f64));\n// D0 = VCC in VOPC encoding.", "example": "v_cmpx_u_f64 -1, v[2:3]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOPC" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 240, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cndmask_b16", "mnemonic": "v_cndmask_b16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CNDMASK B16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Copy data from one of two inputs based on the per-lane condition code and store the result into a vector register.", "description": "Copy data from one of two inputs based on the per-lane condition code and store the result into a vector register.", "syntax": "v_cndmask_b16", "operands": [], "dataTypes": [ "b16" ], "semantics": "", "example": "v_cndmask_b16 v5, 0.5, -1, vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cndmask_b16_fake16", "mnemonic": "v_cndmask_b16_fake16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CNDMASK B16 FAKE16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cndmask_b16_fake16", "operands": [], "dataTypes": [ "b16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cndmask_b16_t16", "mnemonic": "v_cndmask_b16_t16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CNDMASK B16 T16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cndmask_b16_t16", "operands": [], "dataTypes": [ "b16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cndmask_b32", "mnemonic": "v_cndmask_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CNDMASK B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Copy data from one of two inputs based on the per-lane condition code and store the result into a vector register.", "description": "Copy data from one of two inputs based on the per-lane condition code and store the result into a vector register.", "syntax": "v_cndmask_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.u32 = VCC.u64[laneId] ? S1.u32 : S0.u32", "example": "v_cndmask_b32 v5, -1, v2, vcc", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "In VOP3 the VCC source may be a scalar GPR specified in S2. Floating-point modifiers are valid for this instruction if S0 and S1 are 32-bit floating point values. This instruction is suitable for negating or taking the absolute value of a floating-point value.", "sourcePdfPage": 169, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cos_bf16", "mnemonic": "v_cos_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V COS BF16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cos_bf16", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cos_f16", "mnemonic": "v_cos_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V COS F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate the trigonometric cosine of a half-precision float value using IEEE rules and store the result into a vector register.", "description": "Calculate the trigonometric cosine of a half-precision float value using IEEE rules and store the result into a vector register. The operand is calculated by scaling the vector input by 2 PI.", "syntax": "v_cos_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.f16 = cos(S0.f16 * 16'F(PI * 2.0))", "example": "V_COS_F16(0xfc00) => 0xfe00 // cos(-INF) = NAN\nV_COS_F16(0xfbff) => 0x3c00 // Most negative finite FP16\nV_COS_F16(0x8000) => 0x3c00 // cos(-0.0) = 1\nV_COS_F16(0x3400) => 0x0000 // cos(0.25) = 0", "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Denormals are supported. Full range input is supported.", "sourcePdfPage": 210, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_cos_f32", "mnemonic": "v_cos_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V COS F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate the trigonometric cosine of a single-precision float value using IEEE rules and store the result into a vector register.", "description": "Calculate the trigonometric cosine of a single-precision float value using IEEE rules and store the result into a vector register. The operand is calculated by scaling the vector input by 2 PI.", "syntax": "v_cos_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.f32 = cos(S0.f32 * 32'F(PI * 2.0))", "example": "V_COS_F32(0xff800000) => 0xffc00000 // cos(-INF) = NAN\nV_COS_F32(0xff7fffff) => 0x3f800000 // -MaxFloat, finite\nV_COS_F32(0x80000000) => 0x3f800000 // cos(-0.0) = 1\nV_COS_F32(0x3e800000) => 0x00000000 // cos(0.25) = 0", "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Denormals are supported. Full range input is supported.", "sourcePdfPage": 199, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_cubeid_f32", "mnemonic": "v_cubeid_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CUBEID F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Compute the cubemap face ID of a 3D coordinate specified as three single-precision float inputs.", "description": "Compute the cubemap face ID of a 3D coordinate specified as three single-precision float inputs. Store the result in single-precision float format into a vector register.", "syntax": "v_cubeid_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "// Set D0.f = cubemap face ID ({0.0, 1.0, ..., 5.0}).\n// XYZ coordinate is given in (S0.f, S1.f, S2.f).\n// S0.f = x\n// S1.f = y\n// S2.f = z\nif ((abs(S2.f32) >= abs(S0.f32)) && (abs(S2.f32) >= abs(S1.f32))) then\nif S2.f32 < 0.0F then\nD0.f32 = 5.0F\nelse\nD0.f32 = 4.0F\nendif\nelsif abs(S1.f32) >= abs(S0.f32) then\nif S1.f32 < 0.0F then\nD0.f32 = 3.0F\nelse\nD0.f32 = 2.0F\nendif\nelse\nif S0.f32 < 0.0F then\nD0.f32 = 1.0F\nelse\nD0.f32 = 0.0F\nendif\nendif", "example": "v_cubeid_f32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 336, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cubema_f32", "mnemonic": "v_cubema_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CUBEMA F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Compute the cubemap major axis of a 3D coordinate specified as three single-precision float inputs.", "description": "Compute the cubemap major axis of a 3D coordinate specified as three single-precision float inputs. Store the result in single-precision float format into a vector register.", "syntax": "v_cubema_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "// D0.f = 2.0 * cubemap major axis.\n// XYZ coordinate is given in (S0.f, S1.f, S2.f).\n// S0.f = x\n// S1.f = y\n// S2.f = z\nif ((abs(S2.f32) >= abs(S0.f32)) && (abs(S2.f32) >= abs(S1.f32))) then\nD0.f32 = S2.f32 * 2.0F\nelsif abs(S1.f32) >= abs(S0.f32) then\nD0.f32 = S1.f32 * 2.0F\nelse\nD0.f32 = S0.f32 * 2.0F\nendif", "example": "v_cubema_f32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 337, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cubesc_f32", "mnemonic": "v_cubesc_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CUBESC F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Compute the cubemap S coordinate of a 3D coordinate specified as three single-precision float inputs.", "description": "Compute the cubemap S coordinate of a 3D coordinate specified as three single-precision float inputs. Store the result in single-precision float format into a vector register.", "syntax": "v_cubesc_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "// D0.f = cubemap S coordinate.\n// XYZ coordinate is given in (S0.f, S1.f, S2.f).\n// S0.f = x\n// S1.f = y\n// S2.f = z\nif ((abs(S2.f32) >= abs(S0.f32)) && (abs(S2.f32) >= abs(S1.f32))) then\nif S2.f32 < 0.0F then\nD0.f32 = -S0.f32\nelse\nD0.f32 = S0.f32\nendif\nelsif abs(S1.f32) >= abs(S0.f32) then\nD0.f32 = S0.f32\nelse\nif S0.f32 < 0.0F then\nD0.f32 = S2.f32\nelse\nD0.f32 = -S2.f32\nendif\nendif", "example": "v_cubesc_f32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 336, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cubetc_f32", "mnemonic": "v_cubetc_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CUBETC F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Compute the cubemap T coordinate of a 3D coordinate specified as three single-precision float inputs.", "description": "Compute the cubemap T coordinate of a 3D coordinate specified as three single-precision float inputs. Store the result in single-precision float format into a vector register.", "syntax": "v_cubetc_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "// D0.f = cubemap T coordinate.\n// XYZ coordinate is given in (S0.f, S1.f, S2.f).\n// S0.f = x\n// S1.f = y\n// S2.f = z\nif ((abs(S2.f32) >= abs(S0.f32)) && (abs(S2.f32) >= abs(S1.f32))) then\nD0.f32 = -S1.f32\nelsif abs(S1.f32) >= abs(S0.f32) then\nif S1.f32 < 0.0F then\nD0.f32 = -S2.f32\nelse\nD0.f32 = S2.f32\nendif\nelse\nD0.f32 = -S1.f32\nendif", "example": "v_cubetc_f32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 337, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_f16_bf8", "mnemonic": "v_cvt_f16_bf8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT F16 BF8", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP1 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_f16_bf8", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_f16_f32", "mnemonic": "v_cvt_f16_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT F16 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a single-precision float input to a half-precision float value and store the result into a vector register.", "description": "Convert from a single-precision float input to a half-precision float value and store the result into a vector register.", "syntax": "v_cvt_f16_f32", "operands": [], "dataTypes": [ "f16", "f32" ], "semantics": "D0.f16 = f32_to_f16(S0.f32)", "example": "v_cvt_f16_f32 v5.l, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "0.5ULP accuracy, supports input modifiers and creates FP16 denormals when appropriate. Flush denorms on output if specified based on DP denorm mode. Output rounding based on DP rounding mode.", "sourcePdfPage": 189, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_f16_f32_fake16", "mnemonic": "v_cvt_f16_f32_fake16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT F16 F32 FAKE16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP1 vector instruction operating on f16/f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_f16_f32_fake16", "operands": [], "dataTypes": [ "f16", "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_f16_f32_t16", "mnemonic": "v_cvt_f16_f32_t16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT F16 F32 T16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP1 vector instruction operating on f16/f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_f16_f32_t16", "operands": [], "dataTypes": [ "f16", "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_f16_fp8", "mnemonic": "v_cvt_f16_fp8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT F16 FP8", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP1 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_f16_fp8", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_f16_i16", "mnemonic": "v_cvt_f16_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT F16 I16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a signed 16-bit integer input to a half-precision float value and store the result into a vector register.", "description": "Convert from a signed 16-bit integer input to a half-precision float value and store the result into a vector register.", "syntax": "v_cvt_f16_i16", "operands": [], "dataTypes": [ "f16", "i16" ], "semantics": "D0.f16 = i16_to_f16(S0.i16)", "example": "v_cvt_f16_i16 v5.l, s1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "0.5ULP accuracy, supports denormals, rounding, exception flags and saturation.", "sourcePdfPage": 204, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_f16_u16", "mnemonic": "v_cvt_f16_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT F16 U16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from an unsigned 16-bit integer input to a half-precision float value and store the result into a vector register.", "description": "Convert from an unsigned 16-bit integer input to a half-precision float value and store the result into a vector register.", "syntax": "v_cvt_f16_u16", "operands": [], "dataTypes": [ "f16", "u16" ], "semantics": "D0.f16 = u16_to_f16(S0.u16)", "example": "v_cvt_f16_u16 v5.l, s1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "0.5ULP accuracy, supports denormals, rounding, exception flags and saturation.", "sourcePdfPage": 204, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_f32_bf16", "mnemonic": "v_cvt_f32_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT F32 BF16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a BF16 float input to a single-precision float value and store the result into a vector register.", "description": "Convert from a BF16 float input to a single-precision float value and store the result into a vector register.", "syntax": "v_cvt_f32_bf16", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_cvt_f32_bf8", "mnemonic": "v_cvt_f32_bf8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT F32 BF8", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a BF8 float input to a single-precision float value and store the result into a vector register.", "description": "Convert from a BF8 float input to a single-precision float value and store the result into a vector register.", "syntax": "v_cvt_f32_bf8", "operands": [], "dataTypes": [ "f32" ], "semantics": "if SDWA_SRC0_SEL == BYTE1.b3 then\nD0.f32 = bf8_to_f32(S0[15 : 8].bf8)\nelsif SDWA_SRC0_SEL == BYTE2.b3 then\nD0.f32 = bf8_to_f32(S0[23 : 16].bf8)\nelsif SDWA_SRC0_SEL == BYTE3.b3 then\nD0.f32 = bf8_to_f32(S0[31 : 24].bf8)\nelse\n// BYTE0 implied\nD0.f32 = bf8_to_f32(S0[7 : 0].bf8)\nendif", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "SDWA encoding allows SRC0_SEL to control which byte of S0 is converted. Only the BYTE selects of SRC0_SEL are legal. If this instruction is not encoded in SDWA then BYTE0 is implied.", "sourcePdfPage": 212, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_cvt_f32_bf8_op_sel", "mnemonic": "v_cvt_f32_bf8_op_sel", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT F32 BF8 OP SEL", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_f32_bf8_op_sel", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_f32_f16", "mnemonic": "v_cvt_f32_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT F32 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a half-precision float input to a single-precision float value and store the result into a vector register.", "description": "Convert from a half-precision float input to a single-precision float value and store the result into a vector register.", "syntax": "v_cvt_f32_f16", "operands": [], "dataTypes": [ "f16", "f32" ], "semantics": "D0.f32 = f16_to_f32(S0.f16)", "example": "v_cvt_f32_f16 v5, s1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "0ULP accuracy, FP16 denormal inputs are accepted. Flush denorms on input if specified based on DP denorm mode.", "sourcePdfPage": 189, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_f32_f16_fake16", "mnemonic": "v_cvt_f32_f16_fake16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT F32 F16 FAKE16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP1 vector instruction operating on f16/f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_f32_f16_fake16", "operands": [], "dataTypes": [ "f16", "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_f32_f16_t16", "mnemonic": "v_cvt_f32_f16_t16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT F32 F16 T16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP1 vector instruction operating on f16/f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_f32_f16_t16", "operands": [], "dataTypes": [ "f16", "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_f32_f64", "mnemonic": "v_cvt_f32_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT F32 F64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a double-precision float input to a single-precision float value and store the result into a vector register.", "description": "Convert from a double-precision float input to a single-precision float value and store the result into a vector register.", "syntax": "v_cvt_f32_f64", "operands": [], "dataTypes": [ "f32", "f64" ], "semantics": "D0.f32 = f64_to_f32(S0.f64)", "example": "v_cvt_f32_f64 v5, -1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "0.5ULP accuracy, denormals are supported.", "sourcePdfPage": 191, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_f32_fp8", "mnemonic": "v_cvt_f32_fp8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT F32 FP8", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from an FP8 float input to a single-precision float value and store the result into a vector register.", "description": "Convert from an FP8 float input to a single-precision float value and store the result into a vector register.", "syntax": "v_cvt_f32_fp8", "operands": [], "dataTypes": [ "f32" ], "semantics": "if SDWA_SRC0_SEL == BYTE1.b3 then\nD0.f32 = fp8_to_f32(S0[15 : 8].fp8)\nelsif SDWA_SRC0_SEL == BYTE2.b3 then\nD0.f32 = fp8_to_f32(S0[23 : 16].fp8)\nelsif SDWA_SRC0_SEL == BYTE3.b3 then\nD0.f32 = fp8_to_f32(S0[31 : 24].fp8)\nelse\n// BYTE0 implied\nD0.f32 = fp8_to_f32(S0[7 : 0].fp8)\nendif", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "SDWA encoding allows SRC0_SEL to control which byte of S0 is converted. Only the BYTE selects of SRC0_SEL are legal. If this instruction is not encoded in SDWA then BYTE0 is implied.", "sourcePdfPage": 211, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_cvt_f32_fp8_gfx1250", "mnemonic": "v_cvt_f32_fp8_gfx1250", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT F32 FP8 GFX1250", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_f32_fp8_gfx1250", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_f32_fp8_op_sel", "mnemonic": "v_cvt_f32_fp8_op_sel", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT F32 FP8 OP SEL", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_f32_fp8_op_sel", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_f32_i32", "mnemonic": "v_cvt_f32_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT F32 I32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Per-lane conversion from signed 32-bit integer to single-precision float.", "description": "Convert from a signed 32-bit integer input to a single-precision float value and store the result into a vector register.", "syntax": "v_cvt_f32_i32 VDST, S0", "operands": [ { "name": "VDST", "desc": "Destination VGPR" }, { "name": "S0", "desc": "Source VGPR (i32)" } ], "dataTypes": [ "f32", "i32" ], "semantics": "VDST[lane] = convert_i32_to_f32(S0[lane]) for each active lane.", "example": "v_cvt_f32_i32 v1, v0 // per-lane v1 = (float) v0", "exampleSource": null, "encoding": { "format": "VOP1", "widthBits": 32 }, "executionUnit": "Vector ALU", "registerClasses": [ "VGPR" ], "memorySegment": null, "supportedTargets": [ "gfx942", "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_cvt_f32_u32", "mnemonic": "v_cvt_f32_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT F32 U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from an unsigned 32-bit integer input to a single-precision float value and store the result into a vector register.", "description": "Convert from an unsigned 32-bit integer input to a single-precision float value and store the result into a vector register.", "syntax": "v_cvt_f32_u32", "operands": [], "dataTypes": [ "f32", "u32" ], "semantics": "D0.f32 = u32_to_f32(S0.u32)", "example": "v_cvt_f32_u32 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "0.5ULP accuracy.", "sourcePdfPage": 188, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_f32_ubyte0", "mnemonic": "v_cvt_f32_ubyte0", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT F32 UBYTE0", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert an unsigned byte in byte 0 of the input to a single-precision float value and store the result into a vector register.", "description": "Convert an unsigned byte in byte 0 of the input to a single-precision float value and store the result into a vector register.", "syntax": "v_cvt_f32_ubyte0", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.f32 = u32_to_f32(S0[7 : 0].u32)", "example": "v_cvt_f32_ubyte0 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 191, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_f32_ubyte1", "mnemonic": "v_cvt_f32_ubyte1", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT F32 UBYTE1", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert an unsigned byte in byte 1 of the input to a single-precision float value and store the result into a vector register.", "description": "Convert an unsigned byte in byte 1 of the input to a single-precision float value and store the result into a vector register.", "syntax": "v_cvt_f32_ubyte1", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.f32 = u32_to_f32(S0[15 : 8].u32)", "example": "v_cvt_f32_ubyte1 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 191, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_f32_ubyte2", "mnemonic": "v_cvt_f32_ubyte2", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT F32 UBYTE2", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert an unsigned byte in byte 2 of the input to a single-precision float value and store the result into a vector register.", "description": "Convert an unsigned byte in byte 2 of the input to a single-precision float value and store the result into a vector register.", "syntax": "v_cvt_f32_ubyte2", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.f32 = u32_to_f32(S0[23 : 16].u32)", "example": "v_cvt_f32_ubyte2 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 191, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_f32_ubyte3", "mnemonic": "v_cvt_f32_ubyte3", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT F32 UBYTE3", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert an unsigned byte in byte 3 of the input to a single-precision float value and store the result into a vector register.", "description": "Convert an unsigned byte in byte 3 of the input to a single-precision float value and store the result into a vector register.", "syntax": "v_cvt_f32_ubyte3", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.f32 = u32_to_f32(S0[31 : 24].u32)", "example": "v_cvt_f32_ubyte3 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 192, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_f64_f32", "mnemonic": "v_cvt_f64_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT F64 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a single-precision float input to a double-precision float value and store the result into a vector register.", "description": "Convert from a single-precision float input to a double-precision float value and store the result into a vector register.", "syntax": "v_cvt_f64_f32", "operands": [], "dataTypes": [ "f32", "f64" ], "semantics": "D0.f64 = f32_to_f64(S0.f32)", "example": "v_cvt_f64_f32 v[5:6], v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "0ULP accuracy, denormals are supported.", "sourcePdfPage": 191, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_f64_i32", "mnemonic": "v_cvt_f64_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT F64 I32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a signed 32-bit integer input to a double-precision float value and store the result into a vector register.", "description": "Convert from a signed 32-bit integer input to a double-precision float value and store the result into a vector register.", "syntax": "v_cvt_f64_i32", "operands": [], "dataTypes": [ "f64", "i32" ], "semantics": "D0.f64 = i32_to_f64(S0.i32)", "example": "v_cvt_f64_i32 v[5:6], v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "0ULP accuracy.", "sourcePdfPage": 187, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_f64_u32", "mnemonic": "v_cvt_f64_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT F64 U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from an unsigned 32-bit integer input to a double-precision float value and store the result into a vector register.", "description": "Convert from an unsigned 32-bit integer input to a double-precision float value and store the result into a vector register.", "syntax": "v_cvt_f64_u32", "operands": [], "dataTypes": [ "f64", "u32" ], "semantics": "D0.f64 = u32_to_f64(S0.u32)", "example": "v_cvt_f64_u32 v[5:6], v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "0ULP accuracy.", "sourcePdfPage": 192, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_flr_i32_f32", "mnemonic": "v_cvt_flr_i32_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT FLR I32 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a single-precision float input to a signed 32-bit integer value using round-down semantics (ignore the default rounding mode) and store…", "description": "Convert from a single-precision float input to a signed 32-bit integer value using round-down semantics (ignore the default rounding mode) and store the result into a vector register.", "syntax": "v_cvt_flr_i32_f32", "operands": [], "dataTypes": [ "f32", "i32" ], "semantics": "D0.i32 = f32_to_i32(floor(S0.f32))", "example": "v_cvt_flr_i32_f32 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "1ULP accuracy, denormals are supported.", "sourcePdfPage": 190, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_i16_f16", "mnemonic": "v_cvt_i16_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT I16 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a half-precision float input to a signed 16-bit integer value and store the result into a vector register.", "description": "Convert from a half-precision float input to a signed 16-bit integer value and store the result into a vector register.", "syntax": "v_cvt_i16_f16", "operands": [], "dataTypes": [ "f16", "i16" ], "semantics": "D0.i16 = f16_to_i16(S0.f16)", "example": "v_cvt_i16_f16 v5.l, s1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "1ULP accuracy, supports rounding, exception flags and saturation. FP16 denormals are accepted. Conversion is done with truncation. Generation of the INEXACT exception is controlled by the CLAMP bit. INEXACT exceptions are enabled for this conversion iff CLAMP == 1.", "sourcePdfPage": 205, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_i32_f32", "mnemonic": "v_cvt_i32_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT I32 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a single-precision float input to a signed 32-bit integer value and store the result into a vector register.", "description": "Convert from a single-precision float input to a signed 32-bit integer value and store the result into a vector register.", "syntax": "v_cvt_i32_f32", "operands": [], "dataTypes": [ "f32", "i32" ], "semantics": "D0.i32 = f32_to_i32(S0.f32)", "example": "v_cvt_i32_f32 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "1ULP accuracy, out-of-range floating point values (including infinity) saturate. NAN is converted to 0. Generation of the INEXACT exception is controlled by the CLAMP bit. INEXACT exceptions are enabled for this conversion iff CLAMP == 1.", "sourcePdfPage": 189, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_i32_f64", "mnemonic": "v_cvt_i32_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT I32 F64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a double-precision float input to a signed 32-bit integer value and store the result into a vector register.", "description": "Convert from a double-precision float input to a signed 32-bit integer value and store the result into a vector register.", "syntax": "v_cvt_i32_f64", "operands": [], "dataTypes": [ "f64", "i32" ], "semantics": "D0.i32 = f64_to_i32(S0.f64)", "example": "v_cvt_i32_f64 v5, -1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "0.5ULP accuracy, out-of-range floating point values (including infinity) saturate. NAN is converted to 0. Generation of the INEXACT exception is controlled by the CLAMP bit. INEXACT exceptions are enabled for this conversion iff CLAMP == 1.", "sourcePdfPage": 187, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_i32_i16", "mnemonic": "v_cvt_i32_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT I32 I16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a signed 16-bit integer input to a signed 32-bit integer value using sign extension and store the result into a vector register.", "description": "Convert from a signed 16-bit integer input to a signed 32-bit integer value using sign extension and store the result into a vector register.", "syntax": "v_cvt_i32_i16", "operands": [], "dataTypes": [ "i16", "i32" ], "semantics": "", "example": "v_cvt_i32_i16 v5, s1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_norm_i16_f16", "mnemonic": "v_cvt_norm_i16_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT NORM I16 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a half-precision float input to a signed normalized short and store the result into a vector register.", "description": "Convert from a half-precision float input to a signed normalized short and store the result into a vector register.", "syntax": "v_cvt_norm_i16_f16", "operands": [], "dataTypes": [ "f16", "i16" ], "semantics": "D0.i16 = f16_to_snorm(S0.f16)", "example": "v_cvt_norm_i16_f16 v5.l, s1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "0.5ULP accuracy, supports rounding, exception flags and saturation, denormals are supported.", "sourcePdfPage": 210, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_norm_u16_f16", "mnemonic": "v_cvt_norm_u16_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT NORM U16 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a half-precision float input to an unsigned normalized short and store the result into a vector register.", "description": "Convert from a half-precision float input to an unsigned normalized short and store the result into a vector register.", "syntax": "v_cvt_norm_u16_f16", "operands": [], "dataTypes": [ "f16", "u16" ], "semantics": "D0.u16 = f16_to_unorm(S0.f16)", "example": "v_cvt_norm_u16_f16 v5.l, s1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "0.5ULP accuracy, supports rounding, exception flags and saturation, denormals are supported.", "sourcePdfPage": 210, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_off_f32_i4", "mnemonic": "v_cvt_off_f32_i4", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT OFF F32 I4", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a signed 4-bit integer input to a single-precision float value using an offset table and store the result into a vector register.", "description": "Convert from a signed 4-bit integer input to a single-precision float value using an offset table and store the result into a vector register. Used for interpolation in shader. Lookup table on S0[3:0]: S0 binary Result 1000 -0.5000f 1001 -0.4375f 1010 -0.3750f 1011 -0.3125f 1100 -0.2500f 1101 -0.1875f 1110 -0.1250f 1111 -0.0625f 0000 +0.0000f 0001 +0.0625f 0010 +0.1250f 0011 +0.1875f 0100 +0.2500f 0101 +0.3125f 0110 +0.3750f 0111 +0.4375f", "syntax": "v_cvt_off_f32_i4", "operands": [], "dataTypes": [ "f32" ], "semantics": "declare CVT_OFF_TABLE : 32'F[16];\nD0.f32 = CVT_OFF_TABLE[S0.u32[3 : 0]]", "example": "v_cvt_off_f32_i4 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 190, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_pk_bf16_f32", "mnemonic": "v_cvt_pk_bf16_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT PK BF16 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from two single-precision float inputs to a packed BF16 value and store the result into a vector register.", "description": "Convert from two single-precision float inputs to a packed BF16 value and store the result into a vector register.", "syntax": "v_cvt_pk_bf16_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_cvt_pk_bf8_f16", "mnemonic": "v_cvt_pk_bf8_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT PK BF8 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP1 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_pk_bf8_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_pk_bf8_f32", "mnemonic": "v_cvt_pk_bf8_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT PK BF8 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from two single-precision float inputs to a packed BF8 float value with round to nearest even semantics and store the result into 16 bits of…", "description": "Convert from two single-precision float inputs to a packed BF8 float value with round to nearest even semantics and store the result into 16 bits of a vector register using OPSEL.", "syntax": "v_cvt_pk_bf8_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "prev_mode = ROUND_MODE;\nROUND_MODE = ROUND_NEAREST_EVEN;\nif OPSEL[3].u32 == 0U then\nVGPR[laneId][VDST.u32][15 : 0].b16 = { f32_to_bf8(S1.f32), f32_to_bf8(S0.f32) };\n// D0[31:16] are preserved\nelse\nVGPR[laneId][VDST.u32][31 : 16].b16 = { f32_to_bf8(S1.f32), f32_to_bf8(S0.f32) };\n// D0[15:0] are preserved\nendif;\nROUND_MODE = prev_mode", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Round to nearest even. Ignores OMOD and clamp.", "sourcePdfPage": 370, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_cvt_pk_f16_bf8", "mnemonic": "v_cvt_pk_f16_bf8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT PK F16 BF8", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP1 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_pk_f16_bf8", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_pk_f16_f32", "mnemonic": "v_cvt_pk_f16_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT PK F16 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from two single-precision float inputs to a packed half-precision value and store the result into a vector register.", "description": "Convert from two single-precision float inputs to a packed half-precision value and store the result into a vector register.", "syntax": "v_cvt_pk_f16_f32", "operands": [], "dataTypes": [ "f16", "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_cvt_pk_f16_fp8", "mnemonic": "v_cvt_pk_f16_fp8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT PK F16 FP8", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP1 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_pk_f16_fp8", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_pk_f32_bf8", "mnemonic": "v_cvt_pk_f32_bf8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT PK F32 BF8", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a packed 2-component BF8 float input to a packed single-precision float value and store the result into a vector register.", "description": "Convert from a packed 2-component BF8 float input to a packed single-precision float value and store the result into a vector register.", "syntax": "v_cvt_pk_f32_bf8", "operands": [], "dataTypes": [ "f32" ], "semantics": "tmp = SDWA_SRC0_SEL[1 : 0] == WORD1.b2 ? S0[31 : 16] : S0[15 : 0];\nD0[31 : 0].f32 = bf8_to_f32(tmp[7 : 0].bf8);\nD0[63 : 32].f32 = bf8_to_f32(tmp[15 : 8].bf8)", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "SDWA encoding allows SRC0_SEL to control which word of S0 is converted. Only the WORD selects of SRC0_SEL are legal. If this instruction is not encoded in SDWA then WORD0 is implied.", "sourcePdfPage": 213, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_cvt_pk_f32_bf8_fake16", "mnemonic": "v_cvt_pk_f32_bf8_fake16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT PK F32 BF8 FAKE16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_pk_f32_bf8_fake16", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_pk_f32_bf8_t16", "mnemonic": "v_cvt_pk_f32_bf8_t16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT PK F32 BF8 T16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_pk_f32_bf8_t16", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_pk_f32_fp8", "mnemonic": "v_cvt_pk_f32_fp8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT PK F32 FP8", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a packed 2-component FP8 float input to a packed single-precision float value and store the result into a vector register.", "description": "Convert from a packed 2-component FP8 float input to a packed single-precision float value and store the result into a vector register.", "syntax": "v_cvt_pk_f32_fp8", "operands": [], "dataTypes": [ "f32" ], "semantics": "tmp = SDWA_SRC0_SEL[1 : 0] == WORD1.b2 ? S0[31 : 16] : S0[15 : 0];\nD0[31 : 0].f32 = fp8_to_f32(tmp[7 : 0].fp8);\nD0[63 : 32].f32 = fp8_to_f32(tmp[15 : 8].fp8)", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "SDWA encoding allows SRC0_SEL to control which word of S0 is converted. Only the WORD selects of SRC0_SEL are legal. If this instruction is not encoded in SDWA then WORD0 is implied.", "sourcePdfPage": 212, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_cvt_pk_f32_fp8_fake16", "mnemonic": "v_cvt_pk_f32_fp8_fake16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT PK F32 FP8 FAKE16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_pk_f32_fp8_fake16", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_pk_f32_fp8_t16", "mnemonic": "v_cvt_pk_f32_fp8_t16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT PK F32 FP8 T16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_pk_f32_fp8_t16", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_pk_fp8_f16", "mnemonic": "v_cvt_pk_fp8_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT PK FP8 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP1 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_pk_fp8_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_pk_fp8_f32", "mnemonic": "v_cvt_pk_fp8_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT PK FP8 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from two single-precision float inputs to a packed FP8 float value with round to nearest even semantics and store the result into 16 bits of…", "description": "Convert from two single-precision float inputs to a packed FP8 float value with round to nearest even semantics and store the result into 16 bits of a vector register using OPSEL.", "syntax": "v_cvt_pk_fp8_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "prev_mode = ROUND_MODE;\nROUND_MODE = ROUND_NEAREST_EVEN;\nif OPSEL[3].u32 == 0U then\nVGPR[laneId][VDST.u32][15 : 0].b16 = { f32_to_fp8(S1.f32), f32_to_fp8(S0.f32) };\n// D0[31:16] are preserved\nelse\nVGPR[laneId][VDST.u32][31 : 16].b16 = { f32_to_fp8(S1.f32), f32_to_fp8(S0.f32) };\n// D0[15:0] are preserved\nendif;\nROUND_MODE = prev_mode", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Round to nearest even. Ignores OMOD and clamp.", "sourcePdfPage": 369, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_cvt_pk_fp8_f32_gfx1250", "mnemonic": "v_cvt_pk_fp8_f32_gfx1250", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT PK FP8 F32 GFX1250", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_pk_fp8_f32_gfx1250", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_pk_i16_f32", "mnemonic": "v_cvt_pk_i16_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT PK I16 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert two single-precision float inputs into a packed signed 16-bit integer value and store the result into a vector register.", "description": "Convert two single-precision float inputs into a packed signed 16-bit integer value and store the result into a vector register.", "syntax": "v_cvt_pk_i16_f32", "operands": [], "dataTypes": [ "f32", "i16" ], "semantics": "", "example": "v_cvt_pk_i16_f32 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_pk_i16_i32", "mnemonic": "v_cvt_pk_i16_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT PK I16 I32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from two signed 32-bit integer inputs to a packed signed 16-bit integer value and store the result into a vector register.", "description": "Convert from two signed 32-bit integer inputs to a packed signed 16-bit integer value and store the result into a vector register.", "syntax": "v_cvt_pk_i16_i32", "operands": [], "dataTypes": [ "i16", "i32" ], "semantics": "", "example": "v_cvt_pk_i16_i32 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_pk_norm_i16_f16", "mnemonic": "v_cvt_pk_norm_i16_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT PK NORM I16 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from two half-precision float inputs to a packed signed normalized short and store the result into a vector register.", "description": "Convert from two half-precision float inputs to a packed signed normalized short and store the result into a vector register.", "syntax": "v_cvt_pk_norm_i16_f16", "operands": [], "dataTypes": [ "f16", "i16" ], "semantics": "", "example": "v_cvt_pk_norm_i16_f16 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_pk_norm_i16_f32", "mnemonic": "v_cvt_pk_norm_i16_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT PK NORM I16 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from two single-precision float inputs to a packed signed normalized short and store the result into a vector register.", "description": "Convert from two single-precision float inputs to a packed signed normalized short and store the result into a vector register.", "syntax": "v_cvt_pk_norm_i16_f32", "operands": [], "dataTypes": [ "f32", "i16" ], "semantics": "", "example": "v_cvt_pk_norm_i16_f32 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_pk_norm_u16_f16", "mnemonic": "v_cvt_pk_norm_u16_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT PK NORM U16 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from two half-precision float inputs to a packed unsigned normalized short and store the result into a vector register.", "description": "Convert from two half-precision float inputs to a packed unsigned normalized short and store the result into a vector register.", "syntax": "v_cvt_pk_norm_u16_f16", "operands": [], "dataTypes": [ "f16", "u16" ], "semantics": "", "example": "v_cvt_pk_norm_u16_f16 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_pk_norm_u16_f32", "mnemonic": "v_cvt_pk_norm_u16_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT PK NORM U16 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from two single-precision float inputs to a packed unsigned normalized short and store the result into a vector register.", "description": "Convert from two single-precision float inputs to a packed unsigned normalized short and store the result into a vector register.", "syntax": "v_cvt_pk_norm_u16_f32", "operands": [], "dataTypes": [ "f32", "u16" ], "semantics": "", "example": "v_cvt_pk_norm_u16_f32 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_pk_u16_f32", "mnemonic": "v_cvt_pk_u16_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT PK U16 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert two single-precision float inputs into a packed unsigned 16-bit integer value and store the result into a vector register.", "description": "Convert two single-precision float inputs into a packed unsigned 16-bit integer value and store the result into a vector register.", "syntax": "v_cvt_pk_u16_f32", "operands": [], "dataTypes": [ "f32", "u16" ], "semantics": "", "example": "v_cvt_pk_u16_f32 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_pk_u16_u32", "mnemonic": "v_cvt_pk_u16_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT PK U16 U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from two unsigned 32-bit integer inputs to a packed unsigned 16-bit integer value and store the result into a vector register.", "description": "Convert from two unsigned 32-bit integer inputs to a packed unsigned 16-bit integer value and store the result into a vector register.", "syntax": "v_cvt_pk_u16_u32", "operands": [], "dataTypes": [ "u16", "u32" ], "semantics": "", "example": "v_cvt_pk_u16_u32 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_pk_u8_f32", "mnemonic": "v_cvt_pk_u8_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT PK U8 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert a single-precision float value from the first input to an unsigned 8-bit integer value and pack the result into one byte of the third input…", "description": "Convert a single-precision float value from the first input to an unsigned 8-bit integer value and pack the result into one byte of the third input using the second input as a byte select. Store the result into a vector register.", "syntax": "v_cvt_pk_u8_f32", "operands": [], "dataTypes": [ "f32", "u8" ], "semantics": "tmp = (S2.u32 & 32'U(~(0xff << (S1.u32[1 : 0].u32 * 8U))));\ntmp = (tmp | ((32'U(f32_to_u8(S0.f32)) & 255U) << (S1.u32[1 : 0].u32 * 8U)));\nD0.u32 = tmp", "example": "v_cvt_pk_u8_f32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 343, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_pkaccum_u8_f32", "mnemonic": "v_cvt_pkaccum_u8_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT PKACCUM U8 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert a single-precision float value in the first input to an unsigned 8-bit integer value and store the result into one byte of the destination…", "description": "Convert a single-precision float value in the first input to an unsigned 8-bit integer value and store the result into one byte of the destination register using the second input as a byte select.", "syntax": "v_cvt_pkaccum_u8_f32", "operands": [], "dataTypes": [ "f32", "u8" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_cvt_pknorm_i16_f16", "mnemonic": "v_cvt_pknorm_i16_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT PKNORM I16 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from two half-precision float inputs to a packed signed normalized short and store the result into a vector register.", "description": "Convert from two half-precision float inputs to a packed signed normalized short and store the result into a vector register.", "syntax": "v_cvt_pknorm_i16_f16", "operands": [], "dataTypes": [ "f16", "i16" ], "semantics": "declare tmp : 32'B;\ntmp[15 : 0].i16 = f16_to_snorm(S0.f16);\ntmp[31 : 16].i16 = f16_to_snorm(S1.f16);\nD0 = tmp.b32", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 367, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_cvt_pknorm_i16_f32", "mnemonic": "v_cvt_pknorm_i16_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT PKNORM I16 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from two single-precision float inputs to a packed signed normalized short and store the result into a vector register.", "description": "Convert from two single-precision float inputs to a packed signed normalized short and store the result into a vector register.", "syntax": "v_cvt_pknorm_i16_f32", "operands": [], "dataTypes": [ "f32", "i16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_cvt_pknorm_u16_f16", "mnemonic": "v_cvt_pknorm_u16_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT PKNORM U16 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from two half-precision float inputs to a packed unsigned normalized short and store the result into a vector register.", "description": "Convert from two half-precision float inputs to a packed unsigned normalized short and store the result into a vector register.", "syntax": "v_cvt_pknorm_u16_f16", "operands": [], "dataTypes": [ "f16", "u16" ], "semantics": "declare tmp : 32'B;\ntmp[15 : 0].u16 = f16_to_unorm(S0.f16);\ntmp[31 : 16].u16 = f16_to_unorm(S1.f16);\nD0 = tmp.b32", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 367, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_cvt_pknorm_u16_f32", "mnemonic": "v_cvt_pknorm_u16_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT PKNORM U16 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from two single-precision float inputs to a packed unsigned normalized short and store the result into a vector register.", "description": "Convert from two single-precision float inputs to a packed unsigned normalized short and store the result into a vector register.", "syntax": "v_cvt_pknorm_u16_f32", "operands": [], "dataTypes": [ "f32", "u16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_cvt_pkrtz_f16_f32", "mnemonic": "v_cvt_pkrtz_f16_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT PKRTZ F16 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert two single-precision float inputs to a packed half-precision float value using round toward zero semantics (ignore the current rounding…", "description": "Convert two single-precision float inputs to a packed half-precision float value using round toward zero semantics (ignore the current rounding mode), and store the result into a vector register.", "syntax": "v_cvt_pkrtz_f16_f32", "operands": [], "dataTypes": [ "f16", "f32" ], "semantics": "", "example": "v_cvt_pkrtz_f16_f32 v5, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_rpi_i32_f32", "mnemonic": "v_cvt_rpi_i32_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT RPI I32 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a single-precision float input to a signed 32-bit integer value using round to nearest integer semantics (ignore the default rounding…", "description": "Convert from a single-precision float input to a signed 32-bit integer value using round to nearest integer semantics (ignore the default rounding mode) and store the result into a vector register.", "syntax": "v_cvt_rpi_i32_f32", "operands": [], "dataTypes": [ "f32", "i32" ], "semantics": "D0.i32 = f32_to_i32(floor(S0.f32 + 0.5F))", "example": "v_cvt_rpi_i32_f32 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "0.5ULP accuracy, denormals are supported.", "sourcePdfPage": 189, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_scale_pk16_bf16_bf6", "mnemonic": "v_cvt_scale_pk16_bf16_bf6", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALE PK16 BF16 BF6", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scale_pk16_bf16_bf6", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scale_pk16_bf16_fp6", "mnemonic": "v_cvt_scale_pk16_bf16_fp6", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALE PK16 BF16 FP6", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scale_pk16_bf16_fp6", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scale_pk16_f16_bf6", "mnemonic": "v_cvt_scale_pk16_f16_bf6", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALE PK16 F16 BF6", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scale_pk16_f16_bf6", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scale_pk16_f16_fp6", "mnemonic": "v_cvt_scale_pk16_f16_fp6", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALE PK16 F16 FP6", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scale_pk16_f16_fp6", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scale_pk16_f32_bf6", "mnemonic": "v_cvt_scale_pk16_f32_bf6", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALE PK16 F32 BF6", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scale_pk16_f32_bf6", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scale_pk16_f32_fp6", "mnemonic": "v_cvt_scale_pk16_f32_fp6", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALE PK16 F32 FP6", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scale_pk16_f32_fp6", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scale_pk8_bf16_bf8", "mnemonic": "v_cvt_scale_pk8_bf16_bf8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALE PK8 BF16 BF8", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scale_pk8_bf16_bf8", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scale_pk8_bf16_fp4", "mnemonic": "v_cvt_scale_pk8_bf16_fp4", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALE PK8 BF16 FP4", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scale_pk8_bf16_fp4", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scale_pk8_bf16_fp8", "mnemonic": "v_cvt_scale_pk8_bf16_fp8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALE PK8 BF16 FP8", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scale_pk8_bf16_fp8", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scale_pk8_f16_bf8", "mnemonic": "v_cvt_scale_pk8_f16_bf8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALE PK8 F16 BF8", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scale_pk8_f16_bf8", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scale_pk8_f16_fp4", "mnemonic": "v_cvt_scale_pk8_f16_fp4", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALE PK8 F16 FP4", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scale_pk8_f16_fp4", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scale_pk8_f16_fp8", "mnemonic": "v_cvt_scale_pk8_f16_fp8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALE PK8 F16 FP8", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scale_pk8_f16_fp8", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scale_pk8_f32_bf8", "mnemonic": "v_cvt_scale_pk8_f32_bf8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALE PK8 F32 BF8", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scale_pk8_f32_bf8", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scale_pk8_f32_fp4", "mnemonic": "v_cvt_scale_pk8_f32_fp4", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALE PK8 F32 FP4", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scale_pk8_f32_fp4", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scale_pk8_f32_fp8", "mnemonic": "v_cvt_scale_pk8_f32_fp8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALE PK8 F32 FP8", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scale_pk8_f32_fp8", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scalef32_2xpk16_bf6_f32", "mnemonic": "v_cvt_scalef32_2xpk16_bf6_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 2XPK16 BF6 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Scale packed 16-component single-precision float vectors from two source inputs using the exponent provided by the third single-precision float…", "description": "Scale packed 16-component single-precision float vectors from two source inputs using the exponent provided by the third single-precision float input, then convert the values to a packed 32-component BF6 float value. Store the result into a vector register.", "syntax": "v_cvt_scalef32_2xpk16_bf6_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_cvt_scalef32_2xpk16_fp6_f32", "mnemonic": "v_cvt_scalef32_2xpk16_fp6_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 2XPK16 FP6 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Scale packed 16-component single-precision float vectors from two source inputs using the exponent provided by the third single-precision float…", "description": "Scale packed 16-component single-precision float vectors from two source inputs using the exponent provided by the third single-precision float input, then convert the values to a packed 32-component FP6 float value. Store the result into a vector register.", "syntax": "v_cvt_scalef32_2xpk16_fp6_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_cvt_scalef32_f16_bf8", "mnemonic": "v_cvt_scalef32_f16_bf8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 F16 BF8", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a BF8 float input to a half-precision float value, then scale the value using the exponent provided by the second single-precision float…", "description": "Convert from a BF8 float input to a half-precision float value, then scale the value using the exponent provided by the second single-precision float input. Store the result into a vector register. The value to convert is loaded from 8 bits of the input using OPSEL[1:0] to determine which byte to read.", "syntax": "v_cvt_scalef32_f16_bf8", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_cvt_scalef32_f16_fp8", "mnemonic": "v_cvt_scalef32_f16_fp8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 F16 FP8", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from an FP8 float input to a half-precision float value, then scale the value using the exponent provided by the second single-precision…", "description": "Convert from an FP8 float input to a half-precision float value, then scale the value using the exponent provided by the second single-precision float input. Store the result into a vector register. The value to convert is loaded from 8 bits of the input using OPSEL[1:0] to determine which byte to read.", "syntax": "v_cvt_scalef32_f16_fp8", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_cvt_scalef32_f32_bf8", "mnemonic": "v_cvt_scalef32_f32_bf8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 F32 BF8", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a BF8 float input to a single-precision float value, then scale the value using the exponent provided by the second single-precision…", "description": "Convert from a BF8 float input to a single-precision float value, then scale the value using the exponent provided by the second single-precision float input. Store the result into a vector register. The value to convert is loaded from 8 bits of the input using OPSEL[1:0] to determine which byte to read.", "syntax": "v_cvt_scalef32_f32_bf8", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_cvt_scalef32_f32_fp8", "mnemonic": "v_cvt_scalef32_f32_fp8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 F32 FP8", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from an FP8 float input to a single-precision float value, then scale the value using the exponent provided by the second single-precision…", "description": "Convert from an FP8 float input to a single-precision float value, then scale the value using the exponent provided by the second single-precision float input. Store the result into a vector register. The value to convert is loaded from 8 bits of the input using OPSEL[1:0] to determine which byte to read.", "syntax": "v_cvt_scalef32_f32_fp8", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_cvt_scalef32_pk16_bf6_bf16", "mnemonic": "v_cvt_scalef32_pk16_bf6_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 PK16 BF6 BF16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scalef32_pk16_bf6_bf16", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scalef32_pk16_bf6_f16", "mnemonic": "v_cvt_scalef32_pk16_bf6_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 PK16 BF6 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scalef32_pk16_bf6_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scalef32_pk16_bf6_f32", "mnemonic": "v_cvt_scalef32_pk16_bf6_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 PK16 BF6 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scalef32_pk16_bf6_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scalef32_pk16_fp6_bf16", "mnemonic": "v_cvt_scalef32_pk16_fp6_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 PK16 FP6 BF16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scalef32_pk16_fp6_bf16", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scalef32_pk16_fp6_f16", "mnemonic": "v_cvt_scalef32_pk16_fp6_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 PK16 FP6 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scalef32_pk16_fp6_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scalef32_pk16_fp6_f32", "mnemonic": "v_cvt_scalef32_pk16_fp6_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 PK16 FP6 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scalef32_pk16_fp6_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scalef32_pk32_bf16_bf6", "mnemonic": "v_cvt_scalef32_pk32_bf16_bf6", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 PK32 BF16 BF6", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a packed 32-component BF6 float input to a packed BF16 float value, then scale the packed values using the exponent provided by the…", "description": "Convert from a packed 32-component BF6 float input to a packed BF16 float value, then scale the packed values using the exponent provided by the second single-precision float input. Store the result into a vector register.", "syntax": "v_cvt_scalef32_pk32_bf16_bf6", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_cvt_scalef32_pk32_bf16_fp6", "mnemonic": "v_cvt_scalef32_pk32_bf16_fp6", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 PK32 BF16 FP6", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a packed 32-component FP6 float input to a packed BF16 float value, then scale the packed values using the exponent provided by the…", "description": "Convert from a packed 32-component FP6 float input to a packed BF16 float value, then scale the packed values using the exponent provided by the second single-precision float input. Store the result into a vector register.", "syntax": "v_cvt_scalef32_pk32_bf16_fp6", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_cvt_scalef32_pk32_bf6_bf16", "mnemonic": "v_cvt_scalef32_pk32_bf6_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 PK32 BF6 BF16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Scale a packed 32-component BF16 float input using the exponent provided by the second single-precision float input, then convert the values to a…", "description": "Scale a packed 32-component BF16 float input using the exponent provided by the second single-precision float input, then convert the values to a packed 32-component BF6 float value. Store the result into a vector register.", "syntax": "v_cvt_scalef32_pk32_bf6_bf16", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_cvt_scalef32_pk32_bf6_f16", "mnemonic": "v_cvt_scalef32_pk32_bf6_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 PK32 BF6 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Scale a packed 32-component half-precision float input using the exponent provided by the second single-precision float input, then convert the…", "description": "Scale a packed 32-component half-precision float input using the exponent provided by the second single-precision float input, then convert the values to a packed 32-component BF6 float value. Store the result into a vector register.", "syntax": "v_cvt_scalef32_pk32_bf6_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_cvt_scalef32_pk32_bf6_f32", "mnemonic": "v_cvt_scalef32_pk32_bf6_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 PK32 BF6 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f32 data. 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Store the result into a vector register.", "syntax": "v_cvt_scalef32_pk32_f16_bf6", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_cvt_scalef32_pk32_f16_fp6", "mnemonic": "v_cvt_scalef32_pk32_f16_fp6", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 PK32 F16 FP6", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a packed 32-component FP6 float input to a packed half-precision float value, then scale the packed values using the exponent provided…", "description": "Convert from a packed 32-component FP6 float input to a packed half-precision float value, then scale the packed values using the exponent provided by the second single-precision float input. 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(Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scalef32_pk8_bf8_bf16", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scalef32_pk8_bf8_f16", "mnemonic": "v_cvt_scalef32_pk8_bf8_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 PK8 BF8 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scalef32_pk8_bf8_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scalef32_pk8_bf8_f32", "mnemonic": "v_cvt_scalef32_pk8_bf8_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 PK8 BF8 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f32 data. 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(Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scalef32_pk8_fp4_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scalef32_pk8_fp4_f32", "mnemonic": "v_cvt_scalef32_pk8_fp4_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 PK8 FP4 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scalef32_pk8_fp4_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scalef32_pk8_fp8_bf16", "mnemonic": "v_cvt_scalef32_pk8_fp8_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 PK8 FP8 BF16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scalef32_pk8_fp8_bf16", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scalef32_pk8_fp8_f16", "mnemonic": "v_cvt_scalef32_pk8_fp8_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 PK8 FP8 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scalef32_pk8_fp8_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scalef32_pk8_fp8_f32", "mnemonic": "v_cvt_scalef32_pk8_fp8_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 PK8 FP8 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scalef32_pk8_fp8_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scalef32_pk_bf16_bf8", "mnemonic": "v_cvt_scalef32_pk_bf16_bf8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 PK BF16 BF8", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a packed 2-component BF8 float input to a packed BF16 float value, then scale the packed values using the exponent provided by the…", "description": "Convert from a packed 2-component BF8 float input to a packed BF16 float value, then scale the packed values using the exponent provided by the second single-precision float input. Store the result into a vector register.", "syntax": "v_cvt_scalef32_pk_bf16_bf8", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_cvt_scalef32_pk_bf16_fp4", "mnemonic": "v_cvt_scalef32_pk_bf16_fp4", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 PK BF16 FP4", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a packed 2-component FP4 float input to a packed BF16 float value, then scale the packed values using the exponent provided by the…", "description": "Convert from a packed 2-component FP4 float input to a packed BF16 float value, then scale the packed values using the exponent provided by the second single-precision float input. Store the result into a vector register. The value to convert is loaded from 8 bits of the input using OPSEL[1:0] to determine which byte to read.", "syntax": "v_cvt_scalef32_pk_bf16_fp4", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_cvt_scalef32_pk_bf16_fp8", "mnemonic": "v_cvt_scalef32_pk_bf16_fp8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 PK BF16 FP8", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a packed 2-component FP8 float input to a packed BF16 float value, then scale the packed values using the exponent provided by the…", "description": "Convert from a packed 2-component FP8 float input to a packed BF16 float value, then scale the packed values using the exponent provided by the second single-precision float input. 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(Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scalef32_sr_pk16_bf6_bf16", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scalef32_sr_pk16_bf6_f16", "mnemonic": "v_cvt_scalef32_sr_pk16_bf6_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 SR PK16 BF6 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scalef32_sr_pk16_bf6_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scalef32_sr_pk16_bf6_f32", "mnemonic": "v_cvt_scalef32_sr_pk16_bf6_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 SR PK16 BF6 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scalef32_sr_pk16_bf6_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scalef32_sr_pk16_fp6_bf16", "mnemonic": "v_cvt_scalef32_sr_pk16_fp6_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 SR PK16 FP6 BF16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction. 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(Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scalef32_sr_pk16_fp6_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scalef32_sr_pk32_bf6_bf16", "mnemonic": "v_cvt_scalef32_sr_pk32_bf6_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 SR PK32 BF6 BF16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Scale a packed 32-component BF16 float input using the exponent provided by the third single-precision float input, then convert the values to a…", "description": "Scale a packed 32-component BF16 float input using the exponent provided by the third single-precision float input, then convert the values to a packed 32-component BF6 float value with stochastic rounding using seed data from the second input. Store the result into a vector register.", "syntax": "v_cvt_scalef32_sr_pk32_bf6_bf16", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_cvt_scalef32_sr_pk32_bf6_f16", "mnemonic": "v_cvt_scalef32_sr_pk32_bf6_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 SR PK32 BF6 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Scale a packed 32-component half-precision float input using the exponent provided by the third single-precision float input, then convert the values…", "description": "Scale a packed 32-component half-precision float input using the exponent provided by the third single-precision float input, then convert the values to a packed 32-component BF6 float value with stochastic rounding using seed data from the second input. Store the result into a vector register.", "syntax": "v_cvt_scalef32_sr_pk32_bf6_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_cvt_scalef32_sr_pk32_bf6_f32", "mnemonic": "v_cvt_scalef32_sr_pk32_bf6_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 SR PK32 BF6 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Scale a packed 32-component single-precision float input using the exponent provided by the third single-precision float input, then convert the…", "description": "Scale a packed 32-component single-precision float input using the exponent provided by the third single-precision float input, then convert the values to a packed 32-component BF6 float value with stochastic rounding using seed data from the second input. Store the result into a vector register.", "syntax": "v_cvt_scalef32_sr_pk32_bf6_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_cvt_scalef32_sr_pk32_fp6_bf16", "mnemonic": "v_cvt_scalef32_sr_pk32_fp6_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 SR PK32 FP6 BF16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Scale a packed 32-component BF16 float input using the exponent provided by the third single-precision float input, then convert the values to a…", "description": "Scale a packed 32-component BF16 float input using the exponent provided by the third single-precision float input, then convert the values to a packed 32-component FP6 float value with stochastic rounding using seed data from the second input. Store the result into a vector register.", "syntax": "v_cvt_scalef32_sr_pk32_fp6_bf16", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_cvt_scalef32_sr_pk32_fp6_f16", "mnemonic": "v_cvt_scalef32_sr_pk32_fp6_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 SR PK32 FP6 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Scale a packed 32-component half-precision float input using the exponent provided by the third single-precision float input, then convert the values…", "description": "Scale a packed 32-component half-precision float input using the exponent provided by the third single-precision float input, then convert the values to a packed 32-component FP6 float value with stochastic rounding using seed data from the second input. Store the result into a vector register.", "syntax": "v_cvt_scalef32_sr_pk32_fp6_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_cvt_scalef32_sr_pk32_fp6_f32", "mnemonic": "v_cvt_scalef32_sr_pk32_fp6_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 SR PK32 FP6 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Scale a packed 32-component single-precision float input using the exponent provided by the third single-precision float input, then convert the…", "description": "Scale a packed 32-component single-precision float input using the exponent provided by the third single-precision float input, then convert the values to a packed 32-component FP6 float value with stochastic rounding using seed data from the second input. Store the result into a vector register.", "syntax": "v_cvt_scalef32_sr_pk32_fp6_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_cvt_scalef32_sr_pk8_bf8_bf16", "mnemonic": "v_cvt_scalef32_sr_pk8_bf8_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 SR PK8 BF8 BF16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction. 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(Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scalef32_sr_pk8_fp4_bf16", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scalef32_sr_pk8_fp4_f16", "mnemonic": "v_cvt_scalef32_sr_pk8_fp4_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 SR PK8 FP4 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scalef32_sr_pk8_fp4_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scalef32_sr_pk8_fp4_f32", "mnemonic": "v_cvt_scalef32_sr_pk8_fp4_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 SR PK8 FP4 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scalef32_sr_pk8_fp4_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scalef32_sr_pk8_fp8_bf16", "mnemonic": "v_cvt_scalef32_sr_pk8_fp8_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 SR PK8 FP8 BF16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scalef32_sr_pk8_fp8_bf16", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scalef32_sr_pk8_fp8_f16", "mnemonic": "v_cvt_scalef32_sr_pk8_fp8_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 SR PK8 FP8 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scalef32_sr_pk8_fp8_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scalef32_sr_pk8_fp8_f32", "mnemonic": "v_cvt_scalef32_sr_pk8_fp8_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 SR PK8 FP8 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_scalef32_sr_pk8_fp8_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_scalef32_sr_pk_fp4_bf16", "mnemonic": "v_cvt_scalef32_sr_pk_fp4_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 SR PK FP4 BF16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Scale a packed 2-component BF16 float input using the exponent provided by the third single-precision float input, then convert the values to a…", "description": "Scale a packed 2-component BF16 float input using the exponent provided by the third single-precision float input, then convert the values to a packed FP4 float value with stochastic rounding using seed data from the second input. Store the result into 8 bits of a vector register using OPSEL[3:2] to determine which byte of the destination to overwrite.", "syntax": "v_cvt_scalef32_sr_pk_fp4_bf16", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_cvt_scalef32_sr_pk_fp4_f16", "mnemonic": "v_cvt_scalef32_sr_pk_fp4_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SCALEF32 SR PK FP4 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Scale a packed 2-component half-precision float input using the exponent provided by the third single-precision float input, then convert the values…", "description": "Scale a packed 2-component half-precision float input using the exponent provided by the third single-precision float input, then convert the values to a packed FP4 float value with stochastic rounding using seed data from the second input. Store the result into 8 bits of a vector register using OPSEL[3:2] to determine which byte of the destination to overwrite.", "syntax": "v_cvt_scalef32_sr_pk_fp4_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_cvt_sr_bf16_f32", "mnemonic": "v_cvt_sr_bf16_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SR BF16 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a single-precision float input to a BF16 value with stochastic rounding using seed data from the second input.", "description": "Convert from a single-precision float input to a BF16 value with stochastic rounding using seed data from the second input. Store the result into 16 bits of a vector register using OPSEL to determine which word of the destination to overwrite.", "syntax": "v_cvt_sr_bf16_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_cvt_sr_bf8_f16", "mnemonic": "v_cvt_sr_bf8_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SR BF8 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_sr_bf8_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_sr_bf8_f32", "mnemonic": "v_cvt_sr_bf8_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SR BF8 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a single-precision float input to a BF8 value with stochastic rounding using seed data from the second input.", "description": "Convert from a single-precision float input to a BF8 value with stochastic rounding using seed data from the second input. Store the result into 8 bits of a vector register using OPSEL to determine which byte of the destination to overwrite.", "syntax": "v_cvt_sr_bf8_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "prev_mode = ROUND_MODE;\nROUND_MODE = ROUND_NEAREST_EVEN;\ns = sign(S0.f32);\ne = exponent(S0.f32);\nm = 23'U(32'U(23'B(mantissa(S0.f32))) + S1[31 : 11].u32);\ntmp = float32(s, e, m);\n// Add stochastic value to mantissa, wrap around on overflow\nif OPSEL[3 : 2].u2 == 2'0U then\nVGPR[laneId][VDST.u32][7 : 0].bf8 = f32_to_bf8(tmp.f32)\nelsif OPSEL[3 : 2].u2 == 2'1U then\nVGPR[laneId][VDST.u32][15 : 8].bf8 = f32_to_bf8(tmp.f32)\nelsif OPSEL[3 : 2].u2 == 2'2U then\nVGPR[laneId][VDST.u32][23 : 16].bf8 = f32_to_bf8(tmp.f32)\nelse\nVGPR[laneId][VDST.u32][31 : 24].bf8 = f32_to_bf8(tmp.f32)\nendif;\n// Unwritten bytes of D are preserved.\nROUND_MODE = prev_mode", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "Stochastic rounding. Ignores OMOD and clamp.", "sourcePdfPage": 371, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_cvt_sr_bf8_f32_gfx12", "mnemonic": "v_cvt_sr_bf8_f32_gfx12", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SR BF8 F32 GFX12", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_sr_bf8_f32_gfx12", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_sr_f16_f32", "mnemonic": "v_cvt_sr_f16_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SR F16 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a single-precision float input to a half-precision value with stochastic rounding using seed data from the second input.", "description": "Convert from a single-precision float input to a half-precision value with stochastic rounding using seed data from the second input. Store the result into 16 bits of a vector register using OPSEL to determine which word of the destination to overwrite.", "syntax": "v_cvt_sr_f16_f32", "operands": [], "dataTypes": [ "f16", "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_cvt_sr_fp8_f16", "mnemonic": "v_cvt_sr_fp8_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SR FP8 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_sr_fp8_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_sr_fp8_f32", "mnemonic": "v_cvt_sr_fp8_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SR FP8 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a single-precision float input to an FP8 value with stochastic rounding using seed data from the second input.", "description": "Convert from a single-precision float input to an FP8 value with stochastic rounding using seed data from the second input. Store the result into 8 bits of a vector register using OPSEL to determine which byte of the destination to overwrite.", "syntax": "v_cvt_sr_fp8_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "prev_mode = ROUND_MODE;\nROUND_MODE = ROUND_NEAREST_EVEN;\ns = sign(S0.f32);\ne = exponent(S0.f32);\nm = 23'U(32'U(23'B(mantissa(S0.f32))) + S1[31 : 12].u32);\ntmp = float32(s, e, m);\n// Add stochastic value to mantissa, wrap around on overflow\nif OPSEL[3 : 2].u2 == 2'0U then\nVGPR[laneId][VDST.u32][7 : 0].fp8 = f32_to_fp8(tmp.f32)\nelsif OPSEL[3 : 2].u2 == 2'1U then\nVGPR[laneId][VDST.u32][15 : 8].fp8 = f32_to_fp8(tmp.f32)\nelsif OPSEL[3 : 2].u2 == 2'2U then\nVGPR[laneId][VDST.u32][23 : 16].fp8 = f32_to_fp8(tmp.f32)\nelse\nVGPR[laneId][VDST.u32][31 : 24].fp8 = f32_to_fp8(tmp.f32)\nendif;\n// Unwritten bytes of D are preserved.\nROUND_MODE = prev_mode", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "Stochastic rounding. Ignores OMOD and clamp.", "sourcePdfPage": 370, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_cvt_sr_fp8_f32_gfx12", "mnemonic": "v_cvt_sr_fp8_f32_gfx12", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SR FP8 F32 GFX12", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_sr_fp8_f32_gfx12", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_sr_fp8_f32_gfx1250", "mnemonic": "v_cvt_sr_fp8_f32_gfx1250", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SR FP8 F32 GFX1250", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_sr_fp8_f32_gfx1250", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_sr_pk_bf16_f32", "mnemonic": "v_cvt_sr_pk_bf16_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SR PK BF16 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_sr_pk_bf16_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_sr_pk_f16_f32", "mnemonic": "v_cvt_sr_pk_f16_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT SR PK F16 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f16/f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_cvt_sr_pk_f16_f32", "operands": [], "dataTypes": [ "f16", "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_cvt_u16_f16", "mnemonic": "v_cvt_u16_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT U16 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a half-precision float input to an unsigned 16-bit integer value and store the result into a vector register.", "description": "Convert from a half-precision float input to an unsigned 16-bit integer value and store the result into a vector register.", "syntax": "v_cvt_u16_f16", "operands": [], "dataTypes": [ "f16", "u16" ], "semantics": "D0.u16 = f16_to_u16(S0.f16)", "example": "v_cvt_u16_f16 v5.l, s1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "1ULP accuracy, supports rounding, exception flags and saturation. FP16 denormals are accepted. Conversion is done with truncation. Generation of the INEXACT exception is controlled by the CLAMP bit. INEXACT exceptions are enabled for this conversion iff CLAMP == 1.", "sourcePdfPage": 204, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_u32_f32", "mnemonic": "v_cvt_u32_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT U32 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a single-precision float input to an unsigned 32-bit integer value and store the result into a vector register.", "description": "Convert from a single-precision float input to an unsigned 32-bit integer value and store the result into a vector register.", "syntax": "v_cvt_u32_f32", "operands": [], "dataTypes": [ "f32", "u32" ], "semantics": "D0.u32 = f32_to_u32(S0.f32)", "example": "v_cvt_u32_f32 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "1ULP accuracy, out-of-range floating point values (including infinity) saturate. NAN is converted to 0. Generation of the INEXACT exception is controlled by the CLAMP bit. INEXACT exceptions are enabled for this conversion iff CLAMP == 1.", "sourcePdfPage": 188, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_u32_f64", "mnemonic": "v_cvt_u32_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT U32 F64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from a double-precision float input to an unsigned 32-bit integer value and store the result into a vector register.", "description": "Convert from a double-precision float input to an unsigned 32-bit integer value and store the result into a vector register.", "syntax": "v_cvt_u32_f64", "operands": [], "dataTypes": [ "f64", "u32" ], "semantics": "D0.u32 = f64_to_u32(S0.f64)", "example": "v_cvt_u32_f64 v5, -1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "0.5ULP accuracy, out-of-range floating point values (including infinity) saturate. NAN is converted to 0. Generation of the INEXACT exception is controlled by the CLAMP bit. INEXACT exceptions are enabled for this conversion iff CLAMP == 1.", "sourcePdfPage": 192, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_cvt_u32_u16", "mnemonic": "v_cvt_u32_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V CVT U32 U16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Convert from an unsigned 16-bit integer input to an unsigned 32-bit integer value using zero extension and store the result into a vector register.", "description": "Convert from an unsigned 16-bit integer input to an unsigned 32-bit integer value using zero extension and store the result into a vector register.", "syntax": "v_cvt_u32_u16", "operands": [], "dataTypes": [ "u16", "u32" ], "semantics": "", "example": "v_cvt_u32_u16 v5, s1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_div_fixup_f16", "mnemonic": "v_div_fixup_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V DIV FIXUP F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Given a half-precision float quotient in the first input, a denominator in the second input and a numerator in the third input, detect and apply…", "description": "Given a half-precision float quotient in the first input, a denominator in the second input and a numerator in the third input, detect and apply corner cases related to division, including divide by zero, NaN inputs and overflow, and modify the quotient accordingly. Generate any invalid, denormal and divide-by-zero exceptions that are a result of the division. Store the modified quotient into a vector register. This operation handles corner cases in a division macro such as divide by zero and NaN inputs. This operation is well defined when the quotient is approximately equal to the numerator divided by the denominator. Other inputs produce a predictable result but may not be mathematically useful.", "syntax": "v_div_fixup_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "sign_out = (sign(S1.f16) ^ sign(S2.f16));\nif isNAN(64'F(S2.f16)) then\nD0.f16 = 16'F(cvtToQuietNAN(64'F(S2.f16)))\nelsif isNAN(64'F(S1.f16)) then\nD0.f16 = 16'F(cvtToQuietNAN(64'F(S1.f16)))\nelsif ((64'F(S1.f16) == 0.0) && (64'F(S2.f16) == 0.0)) then\n// 0/0\nD0.f16 = 16'F(0xfe00)\nelsif ((64'F(abs(S1.f16)) == +INF) && (64'F(abs(S2.f16)) == +INF)) then\n// inf/inf\nD0.f16 = 16'F(0xfe00)\nelsif ((64'F(S1.f16) == 0.0) || (64'F(abs(S2.f16)) == +INF)) then\n// x/0, or inf/y\nD0.f16 = sign_out ? -INF.f16 : +INF.f16\nelsif ((64'F(abs(S1.f16)) == +INF) || (64'F(S2.f16) == 0.0)) then\n// x/inf, 0/y\nD0.f16 = sign_out ? -16'0.0 : 16'0.0\nelse\nD0.f16 = sign_out ? -abs(S0.f16) : abs(S0.f16)\nendif", "example": "v_div_fixup_f16 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "This operation is the final step of a high precision division macro and handles all exceptional cases of division. If OPSEL[3] is 0 Result is written to 16 LSBs of destination VGPR and hi 16 bits are preserved. If OPSEL[3] is 1 Result is written to 16 MSBs of destination VGPR and lo 16 bits are preserved.", "sourcePdfPage": 358, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_div_fixup_f16_gfx9", "mnemonic": "v_div_fixup_f16_gfx9", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V DIV FIXUP F16 GFX9", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_div_fixup_f16_gfx9", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_div_fixup_f32", "mnemonic": "v_div_fixup_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V DIV FIXUP F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Given a single-precision float quotient in the first input, a denominator in the second input and a numerator in the third input, detect and apply…", "description": "Given a single-precision float quotient in the first input, a denominator in the second input and a numerator in the third input, detect and apply corner cases related to division, including divide by zero, NaN inputs and overflow, and modify the quotient accordingly. Generate any invalid, denormal and divide-by-zero exceptions that are a result of the division. Store the modified quotient into a vector register. This operation handles corner cases in a division macro such as divide by zero and NaN inputs. This operation is well defined when the quotient is approximately equal to the numerator divided by the denominator. Other inputs produce a predictable result but may not be mathematically useful.", "syntax": "v_div_fixup_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "sign_out = (sign(S1.f32) ^ sign(S2.f32));\nif isNAN(64'F(S2.f32)) then\nD0.f32 = 32'F(cvtToQuietNAN(64'F(S2.f32)))\nelsif isNAN(64'F(S1.f32)) then\nD0.f32 = 32'F(cvtToQuietNAN(64'F(S1.f32)))\nelsif ((64'F(S1.f32) == 0.0) && (64'F(S2.f32) == 0.0)) then\n// 0/0\nD0.f32 = 32'F(0xffc00000)\nelsif ((64'F(abs(S1.f32)) == +INF) && (64'F(abs(S2.f32)) == +INF)) then\n// inf/inf\nD0.f32 = 32'F(0xffc00000)\nelsif ((64'F(S1.f32) == 0.0) || (64'F(abs(S2.f32)) == +INF)) then\n// x/0, or inf/y\nD0.f32 = sign_out ? -INF.f32 : +INF.f32\nelsif ((64'F(abs(S1.f32)) == +INF) || (64'F(S2.f32) == 0.0)) then\n// x/inf, 0/y\nD0.f32 = sign_out ? -0.0F : 0.0F\nelsif exponent(S2.f32) - exponent(S1.f32) < -150 then\nD0.f32 = sign_out ? -UNDERFLOW_F32 : UNDERFLOW_F32\nelsif exponent(S1.f32) == 255 then\nD0.f32 = sign_out ? -OVERFLOW_F32 : OVERFLOW_F32\nelse\nD0.f32 = sign_out ? -abs(S0.f32) : abs(S0.f32)\nendif", "example": "v_div_fixup_f32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "This operation is the final step of a high precision division macro and handles all exceptional cases of division.", "sourcePdfPage": 343, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_div_fixup_f64", "mnemonic": "v_div_fixup_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V DIV FIXUP F64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Given a double-precision float quotient in the first input, a denominator in the second input and a numerator in the third input, detect and apply…", "description": "Given a double-precision float quotient in the first input, a denominator in the second input and a numerator in the third input, detect and apply corner cases related to division, including divide by zero, NaN inputs and overflow, and modify the quotient accordingly. Generate any invalid, denormal and divide-by-zero exceptions that are a result of the division. Store the modified quotient into a vector register. This operation handles corner cases in a division macro such as divide by zero and NaN inputs. This operation is well defined when the quotient is approximately equal to the numerator divided by the denominator. Other inputs produce a predictable result but may not be mathematically useful.", "syntax": "v_div_fixup_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "sign_out = (sign(S1.f64) ^ sign(S2.f64));\nif isNAN(S2.f64) then\nD0.f64 = cvtToQuietNAN(S2.f64)\nelsif isNAN(S1.f64) then\nD0.f64 = cvtToQuietNAN(S1.f64)\nelsif ((S1.f64 == 0.0) && (S2.f64 == 0.0)) then\n// 0/0\nD0.f64 = 64'F(0xfff8000000000000LL)\nelsif ((abs(S1.f64) == +INF) && (abs(S2.f64) == +INF)) then\n// inf/inf\nD0.f64 = 64'F(0xfff8000000000000LL)\nelsif ((S1.f64 == 0.0) || (abs(S2.f64) == +INF)) then\n// x/0, or inf/y\nD0.f64 = sign_out ? -INF : +INF\nelsif ((abs(S1.f64) == +INF) || (S2.f64 == 0.0)) then\n// x/inf, 0/y\nD0.f64 = sign_out ? -0.0 : 0.0\nelsif exponent(S2.f64) - exponent(S1.f64) < -1075 then\nD0.f64 = sign_out ? -UNDERFLOW_F64 : UNDERFLOW_F64\nelsif exponent(S1.f64) == 2047 then\nD0.f64 = sign_out ? -OVERFLOW_F64 : OVERFLOW_F64\nelse\nD0.f64 = sign_out ? -abs(S0.f64) : abs(S0.f64)\nendif", "example": "v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "This operation is the final step of a high precision division macro and handles all exceptional cases of division.", "sourcePdfPage": 344, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_div_fixup_legacy_f16", "mnemonic": "v_div_fixup_legacy_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V DIV FIXUP LEGACY F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Half precision division fixup. Has non-standard rule for OPSEL.", "description": "Half precision division fixup. Has non-standard rule for OPSEL.", "syntax": "v_div_fixup_legacy_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "S0 = Quotient, S1 = Denominator, S2 = Numerator.\nGiven a numerator, denominator, and quotient from a divide, this opcode detects and applies specific case\nnumerics, touching up the quotient if necessary. This opcode also generates invalid, denorm and divide by\nzero exceptions caused by the division.\nsign_out = (sign(S1.f16) ^ sign(S2.f16));\nif isNAN(64'F(S2.f16)) then\ntmp = cvtToQuietNAN(64'F(S2.f16))\nelsif isNAN(64'F(S1.f16)) then\ntmp = cvtToQuietNAN(64'F(S1.f16))\nelsif ((64'F(S1.f16) == 0.0) && (64'F(S2.f16) == 0.0)) then\n// 0/0\ntmp = 16'F(0xfe00)\nelsif ((64'F(abs(S1.f16)) == +INF) && (64'F(abs(S2.f16)) == +INF)) then\n// inf/inf\ntmp = 16'F(0xfe00)\nelsif ((64'F(S1.f16) == 0.0) || (64'F(abs(S2.f16)) == +INF)) then\n// x/0, or inf/y\ntmp = sign_out ? -INF : +INF\nelsif ((64'F(abs(S1.f16)) == +INF) || (64'F(S2.f16) == 0.0)) then\n// x/inf, 0/y\ntmp = sign_out ? -0.0 : 0.0\nelse\ntmp = sign_out ? -abs(S0.f16) : abs(S0.f16)\nendif;\nif OPSEL.u4[3] then\nD0 = { tmp.f16, D0[15 : 0] }\nelse\nD0 = { 16'0, tmp.f16 }\nendif", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 352, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_div_fmas_f32", "mnemonic": "v_div_fmas_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V DIV FMAS F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two single-precision float inputs and add a third input using fused multiply add, then scale the exponent of the result by a fixed factor if…", "description": "Multiply two single-precision float inputs and add a third input using fused multiply add, then scale the exponent of the result by a fixed factor if the vector condition code is set. Store the result into a vector register. This operation is designed for use in floating point division macros and relies on V_DIV_SCALE_F32 to set the vector condition code iff the quotient requires post-scaling.", "syntax": "v_div_fmas_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "if VCC.u64[laneId] then\nD0.f32 = 2.0F ** 32 * fma(S0.f32, S1.f32, S2.f32)\nelse\nD0.f32 = fma(S0.f32, S1.f32, S2.f32)\nendif", "example": "v_div_fmas_f32 v5, s105, s105, s105", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Input denormals are not flushed but output flushing is allowed. V_DIV_SCALE_F32, V_DIV_FMAS_F32 and V_DIV_FIXUP_F32 are all designed for use in a high precision division macro that utilizes V_RCP_F32 and V_MUL_F32 to compute the approximate result and then applies two steps of the Newton-Raphson method to converge to the quotient. If subnormal terms appear during this calculation then a loss of precision occurs. This loss of precision can be avoided by scaling the inputs and then post-scaling the quotient after Newton-Raphson is applied.", "sourcePdfPage": 347, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_div_fmas_f64", "mnemonic": "v_div_fmas_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V DIV FMAS F64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two double-precision float inputs and add a third input using fused multiply add, then scale the exponent of the result by a fixed factor if…", "description": "Multiply two double-precision float inputs and add a third input using fused multiply add, then scale the exponent of the result by a fixed factor if the vector condition code is set. Store the result into a vector register. This operation is designed for use in floating point division macros and relies on V_DIV_SCALE_F64 to set the vector condition code iff the quotient requires post-scaling.", "syntax": "v_div_fmas_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "if VCC.u64[laneId] then\nD0.f64 = 2.0 ** 64 * fma(S0.f64, S1.f64, S2.f64)\nelse\nD0.f64 = fma(S0.f64, S1.f64, S2.f64)\nendif", "example": "v_div_fmas_f64 v[5:6], -1, -exec, |exec|", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Input denormals are not flushed but output flushing is allowed. V_DIV_SCALE_F64, V_DIV_FMAS_F64 and V_DIV_FIXUP_F64 are all designed for use in a high precision division macro that utilizes V_RCP_F64 and V_MUL_F64 to compute the approximate result and then applies two steps of the Newton-Raphson method to converge to the quotient. If subnormal terms appear during this calculation then a loss of precision occurs. This loss of precision can be avoided by scaling the inputs and then post-scaling the quotient after Newton-Raphson is applied.", "sourcePdfPage": 347, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_div_scale_f32", "mnemonic": "v_div_scale_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V DIV SCALE F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Given a single-precision float value to scale in the first input, a denominator in the second input and a numerator in the third input, scale the…", "description": "Given a single-precision float value to scale in the first input, a denominator in the second input and a numerator in the third input, scale the first input for division if required to avoid subnormal terms appearing during application of the Newton-Raphson correction method. Store the scaled result into a vector register and set the vector condition code iff post-scaling is required. This operation is designed for use in a high precision division macro. The first input should be the same value as either the second or third input; other scale values produce predictable results but may not be mathematically useful. The vector condition code is used by V_DIV_FMAS_F32 to determine if the quotient requires post-scaling.", "syntax": "v_div_scale_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "VCC = 0x0LL;\nif ((64'F(S2.f32) == 0.0) || (64'F(S1.f32) == 0.0)) then\nD0.f32 = NAN.f32\nelsif exponent(S2.f32) - exponent(S1.f32) >= 96 then\n// N/D near MAX_FLOAT_F32\nVCC = 0x1LL;\nif S0.f32 == S1.f32 then\n// Only scale the denominator\nD0.f32 = ldexp(S0.f32, 64)\nendif\nelsif S1.f32 == DENORM.f32 then\nD0.f32 = ldexp(S0.f32, 64)\nelsif ((1.0 / 64'F(S1.f32) == DENORM.f64) && (S2.f32 / S1.f32 == DENORM.f32)) then\nVCC = 0x1LL;\nif S0.f32 == S1.f32 then\n// Only scale the denominator\nD0.f32 = ldexp(S0.f32, 64)\nendif\nelsif 1.0 / 64'F(S1.f32) == DENORM.f64 then\nD0.f32 = ldexp(S0.f32, -64)\nelsif S2.f32 / S1.f32 == DENORM.f32 then\nVCC = 0x1LL;\nif S0.f32 == S2.f32 then\n// Only scale the numerator\nD0.f32 = ldexp(S0.f32, 64)\nendif\nelsif exponent(S2.f32) <= 23 then\n// Numerator is tiny\nD0.f32 = ldexp(S0.f32, 64)\nendif", "example": "v_div_scale_f32 v5, vcc, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "V_DIV_SCALE_F32, V_DIV_FMAS_F32 and V_DIV_FIXUP_F32 are all designed for use in a high precision division macro that utilizes V_RCP_F32 and V_MUL_F32 to compute the approximate result and then applies two steps of the Newton-Raphson method to converge to the quotient. If subnormal terms appear during this calculation then a loss of precision occurs. This loss of precision can be avoided by scaling the inputs and then post-scaling the quotient after Newton-Raphson is applied.", "sourcePdfPage": 345, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_div_scale_f64", "mnemonic": "v_div_scale_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V DIV SCALE F64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Given a double-precision float value to scale in the first input, a denominator in the second input and a numerator in the third input, scale the…", "description": "Given a double-precision float value to scale in the first input, a denominator in the second input and a numerator in the third input, scale the first input for division if required to avoid subnormal terms appearing during application of the Newton-Raphson correction method. Store the scaled result into a vector register and set the vector condition code iff post-scaling is required. This operation is designed for use in a high precision division macro. The first input should be the same value as either the second or third input; other scale values produce predictable results but may not be mathematically useful. The vector condition code is used by V_DIV_FMAS_F64 to determine if the quotient requires post-scaling.", "syntax": "v_div_scale_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "VCC = 0x0LL;\nif ((S2.f64 == 0.0) || (S1.f64 == 0.0)) then\nD0.f64 = NAN.f64\nelsif exponent(S2.f64) - exponent(S1.f64) >= 768 then\n// N/D near MAX_FLOAT_F64\nVCC = 0x1LL;\nif S0.f64 == S1.f64 then\n// Only scale the denominator\nD0.f64 = ldexp(S0.f64, 128)\nendif\nelsif S1.f64 == DENORM.f64 then\nD0.f64 = ldexp(S0.f64, 128)\nelsif ((1.0 / S1.f64 == DENORM.f64) && (S2.f64 / S1.f64 == DENORM.f64)) then\nVCC = 0x1LL;\nif S0.f64 == S1.f64 then\n// Only scale the denominator\nD0.f64 = ldexp(S0.f64, 128)\nendif\nelsif 1.0 / S1.f64 == DENORM.f64 then\nD0.f64 = ldexp(S0.f64, -128)\nelsif S2.f64 / S1.f64 == DENORM.f64 then\nVCC = 0x1LL;\nif S0.f64 == S2.f64 then\n// Only scale the numerator\nD0.f64 = ldexp(S0.f64, 128)\nendif\nelsif exponent(S2.f64) <= 53 then\n// Numerator is tiny\nD0.f64 = ldexp(S0.f64, 128)\nendif", "example": "v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], v[3:4]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "V_DIV_SCALE_F64, V_DIV_FMAS_F64 and V_DIV_FIXUP_F64 are all designed for use in a high precision division macro that utilizes V_RCP_F64 and V_MUL_F64 to compute the approximate result and then applies two steps of the Newton-Raphson method to converge to the quotient. If subnormal terms appear during this calculation then a loss of precision occurs. This loss of precision can be avoided by scaling the inputs and then post-scaling the quotient after Newton-Raphson is applied.", "sourcePdfPage": 346, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_dot2_bf16_bf16", "mnemonic": "v_dot2_bf16_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V DOT2 BF16 BF16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Compute the dot product of two packed 2-D BF16 float inputs, add the third input and store the result into a vector register.", "description": "Compute the dot product of two packed 2-D BF16 float inputs, add the third input and store the result into a vector register.", "syntax": "v_dot2_bf16_bf16", "operands": [], "dataTypes": [], "semantics": "", "example": "v_dot2_bf16_bf16 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_dot2_f16_f16", "mnemonic": "v_dot2_f16_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V DOT2 F16 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Compute the dot product of two packed 2-D half-precision float inputs, add the third input and store the result into a vector register.", "description": "Compute the dot product of two packed 2-D half-precision float inputs, add the third input and store the result into a vector register.", "syntax": "v_dot2_f16_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": "v_dot2_f16_f16 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_dot2_i32_i16", "mnemonic": "v_dot2_i32_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V DOT2 I32 I16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Compute the dot product of two packed 2-D signed 16-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from…", "description": "Compute the dot product of two packed 2-D signed 16-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from the third input and store the result into a vector register.", "syntax": "v_dot2_i32_i16", "operands": [], "dataTypes": [ "i16", "i32" ], "semantics": "tmp = S2.i32;\ntmp += i16_to_i32(S0[15 : 0].i16) * i16_to_i32(S1[15 : 0].i16);\ntmp += i16_to_i32(S0[31 : 16].i16) * i16_to_i32(S1[31 : 16].i16);\nD0.i32 = tmp", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 269, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_dot2_u32_u16", "mnemonic": "v_dot2_u32_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V DOT2 U32 U16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Compute the dot product of two packed 2-D unsigned 16-bit integer inputs in the unsigned 32-bit integer domain, add an unsigned 32-bit integer value…", "description": "Compute the dot product of two packed 2-D unsigned 16-bit integer inputs in the unsigned 32-bit integer domain, add an unsigned 32-bit integer value from the third input and store the result into a vector register.", "syntax": "v_dot2_u32_u16", "operands": [], "dataTypes": [ "u16", "u32" ], "semantics": "tmp = S2.u32;\ntmp += u16_to_u32(S0[15 : 0].u16) * u16_to_u32(S1[15 : 0].u16);\ntmp += u16_to_u32(S0[31 : 16].u16) * u16_to_u32(S1[31 : 16].u16);\nD0.u32 = tmp", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 269, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_dot2c_f32_bf16", "mnemonic": "v_dot2c_f32_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V DOT2C F32 BF16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Compute the dot product of two packed 2-D BF16 float inputs in the single-precision float domain and accumulate with the single-precision float value…", "description": "Compute the dot product of two packed 2-D BF16 float inputs in the single-precision float domain and accumulate with the single-precision float value in the destination register.", "syntax": "v_dot2c_f32_bf16", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_dot2c_f32_f16", "mnemonic": "v_dot2c_f32_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V DOT2C F32 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Compute the dot product of two packed 2-D half-precision float inputs in the single-precision float domain and accumulate with the single-precision…", "description": "Compute the dot product of two packed 2-D half-precision float inputs in the single-precision float domain and accumulate with the single-precision float value in the destination register.", "syntax": "v_dot2c_f32_f16", "operands": [], "dataTypes": [ "f16", "f32" ], "semantics": "tmp = D0.f32;\ntmp += f16_to_f32(S0[15 : 0].f16) * f16_to_f32(S1[15 : 0].f16);\ntmp += f16_to_f32(S0[31 : 16].f16) * f16_to_f32(S1[31 : 16].f16);\nD0.f32 = tmp", "example": "v_dot2c_f32_f16 v5, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 184, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_dot2c_i32_i16", "mnemonic": "v_dot2c_i32_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V DOT2C I32 I16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Compute the dot product of two packed 2-D signed 16-bit integer inputs in the signed 32-bit integer domain and accumulate with the signed 32-bit…", "description": "Compute the dot product of two packed 2-D signed 16-bit integer inputs in the signed 32-bit integer domain and accumulate with the signed 32-bit integer value in the destination register.", "syntax": "v_dot2c_i32_i16", "operands": [], "dataTypes": [ "i16", "i32" ], "semantics": "tmp = D0.i32;\ntmp += i16_to_i32(S0[15 : 0].i16) * i16_to_i32(S1[15 : 0].i16);\ntmp += i16_to_i32(S0[31 : 16].i16) * i16_to_i32(S1[31 : 16].i16);\nD0.i32 = tmp", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 184, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_dot4_f32_bf8_bf8", "mnemonic": "v_dot4_f32_bf8_bf8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V DOT4 F32 BF8 BF8", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Compute the dot product of two packed 4-D BF8 float inputs in the single-precision float domain, add a single-precision float value from the third…", "description": "Compute the dot product of two packed 4-D BF8 float inputs in the single-precision float domain, add a single-precision float value from the third input and store the result into a vector register.", "syntax": "v_dot4_f32_bf8_bf8", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_dot4_f32_bf8_fp8", "mnemonic": "v_dot4_f32_bf8_fp8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V DOT4 F32 BF8 FP8", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Compute the dot product of a packed 4-D BF8 float input and a packed 4-D FP8 float input in the single-precision float domain, add a single-precision…", "description": "Compute the dot product of a packed 4-D BF8 float input and a packed 4-D FP8 float input in the single-precision float domain, add a single-precision float value from the third input and store the result into a vector register.", "syntax": "v_dot4_f32_bf8_fp8", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_dot4_f32_fp8_bf8", "mnemonic": "v_dot4_f32_fp8_bf8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V DOT4 F32 FP8 BF8", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Compute the dot product of a packed 4-D FP8 float input and a packed 4-D BF8 float input in the single-precision float domain, add a single-precision…", "description": "Compute the dot product of a packed 4-D FP8 float input and a packed 4-D BF8 float input in the single-precision float domain, add a single-precision float value from the third input and store the result into a vector register.", "syntax": "v_dot4_f32_fp8_bf8", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_dot4_f32_fp8_fp8", "mnemonic": "v_dot4_f32_fp8_fp8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V DOT4 F32 FP8 FP8", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Compute the dot product of two packed 4-D FP8 float inputs in the single-precision float domain, add a single-precision float value from the third…", "description": "Compute the dot product of two packed 4-D FP8 float inputs in the single-precision float domain, add a single-precision float value from the third input and store the result into a vector register.", "syntax": "v_dot4_f32_fp8_fp8", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_dot4_i32_i8", "mnemonic": "v_dot4_i32_i8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V DOT4 I32 I8", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Compute the dot product of two packed 4-D signed 8-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from the…", "description": "Compute the dot product of two packed 4-D signed 8-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from the third input and store the result into a vector register.", "syntax": "v_dot4_i32_i8", "operands": [], "dataTypes": [ "i32", "i8" ], "semantics": "tmp = S2.i32;\ntmp += i8_to_i32(S0[7 : 0].i8) * i8_to_i32(S1[7 : 0].i8);\ntmp += i8_to_i32(S0[15 : 8].i8) * i8_to_i32(S1[15 : 8].i8);\ntmp += i8_to_i32(S0[23 : 16].i8) * i8_to_i32(S1[23 : 16].i8);\ntmp += i8_to_i32(S0[31 : 24].i8) * i8_to_i32(S1[31 : 24].i8);\nD0.i32 = tmp", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 269, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_dot4_i32_iu8", "mnemonic": "v_dot4_i32_iu8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V DOT4 I32 IU8", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Compute the dot product of two packed 4-D signed or unsigned 8-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer…", "description": "Compute the dot product of two packed 4-D signed or unsigned 8-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from the third input and store the result into a vector register.", "syntax": "v_dot4_i32_iu8", "operands": [], "dataTypes": [ "i32" ], "semantics": "", "example": "v_dot4_i32_iu8 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_dot4_u32_u8", "mnemonic": "v_dot4_u32_u8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V DOT4 U32 U8", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Compute the dot product of two packed 4-D unsigned 8-bit integer inputs in the unsigned 32-bit integer domain, add an unsigned 32-bit integer value…", "description": "Compute the dot product of two packed 4-D unsigned 8-bit integer inputs in the unsigned 32-bit integer domain, add an unsigned 32-bit integer value from the third input and store the result into a vector register.", "syntax": "v_dot4_u32_u8", "operands": [], "dataTypes": [ "u32", "u8" ], "semantics": "tmp = S2.u32;\ntmp += u8_to_u32(S0[7 : 0].u8) * u8_to_u32(S1[7 : 0].u8);\ntmp += u8_to_u32(S0[15 : 8].u8) * u8_to_u32(S1[15 : 8].u8);\ntmp += u8_to_u32(S0[23 : 16].u8) * u8_to_u32(S1[23 : 16].u8);\ntmp += u8_to_u32(S0[31 : 24].u8) * u8_to_u32(S1[31 : 24].u8);\nD0.u32 = tmp", "example": "v_dot4_u32_u8 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 269, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_dot4c_i32_i8", "mnemonic": "v_dot4c_i32_i8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V DOT4C I32 I8", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Compute the dot product of two packed 4-D signed 8-bit integer inputs in the signed 32-bit integer domain and accumulate with the signed 32-bit…", "description": "Compute the dot product of two packed 4-D signed 8-bit integer inputs in the signed 32-bit integer domain and accumulate with the signed 32-bit integer value in the destination register.", "syntax": "v_dot4c_i32_i8", "operands": [], "dataTypes": [ "i32", "i8" ], "semantics": "tmp = D0.i32;\ntmp += i8_to_i32(S0[7 : 0].i8) * i8_to_i32(S1[7 : 0].i8);\ntmp += i8_to_i32(S0[15 : 8].i8) * i8_to_i32(S1[15 : 8].i8);\ntmp += i8_to_i32(S0[23 : 16].i8) * i8_to_i32(S1[23 : 16].i8);\ntmp += i8_to_i32(S0[31 : 24].i8) * i8_to_i32(S1[31 : 24].i8);\nD0.i32 = tmp", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 184, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_dot8_i32_i4", "mnemonic": "v_dot8_i32_i4", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V DOT8 I32 I4", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Compute the dot product of two packed 8-D signed 4-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from the…", "description": "Compute the dot product of two packed 8-D signed 4-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from the third input and store the result into a vector register.", "syntax": "v_dot8_i32_i4", "operands": [], "dataTypes": [ "i32" ], "semantics": "tmp = S2.i32;\ntmp += i4_to_i32(S0[3 : 0].i4) * i4_to_i32(S1[3 : 0].i4);\ntmp += i4_to_i32(S0[7 : 4].i4) * i4_to_i32(S1[7 : 4].i4);\ntmp += i4_to_i32(S0[11 : 8].i4) * i4_to_i32(S1[11 : 8].i4);\ntmp += i4_to_i32(S0[15 : 12].i4) * i4_to_i32(S1[15 : 12].i4);\ntmp += i4_to_i32(S0[19 : 16].i4) * i4_to_i32(S1[19 : 16].i4);\ntmp += i4_to_i32(S0[23 : 20].i4) * i4_to_i32(S1[23 : 20].i4);\ntmp += i4_to_i32(S0[27 : 24].i4) * i4_to_i32(S1[27 : 24].i4);\ntmp += i4_to_i32(S0[31 : 28].i4) * i4_to_i32(S1[31 : 28].i4);\nD0.i32 = tmp", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 270, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_dot8_i32_iu4", "mnemonic": "v_dot8_i32_iu4", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V DOT8 I32 IU4", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Compute the dot product of two packed 8-D signed or unsigned 4-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer…", "description": "Compute the dot product of two packed 8-D signed or unsigned 4-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from the third input and store the result into a vector register.", "syntax": "v_dot8_i32_iu4", "operands": [], "dataTypes": [ "i32" ], "semantics": "", "example": "v_dot8_i32_iu4 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_dot8_u32_u4", "mnemonic": "v_dot8_u32_u4", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V DOT8 U32 U4", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Compute the dot product of two packed 8-D unsigned 4-bit integer inputs in the unsigned 32-bit integer domain, add an unsigned 32-bit integer value…", "description": "Compute the dot product of two packed 8-D unsigned 4-bit integer inputs in the unsigned 32-bit integer domain, add an unsigned 32-bit integer value from the third input and store the result into a vector register.", "syntax": "v_dot8_u32_u4", "operands": [], "dataTypes": [ "u32" ], "semantics": "tmp = S2.u32;\ntmp += u4_to_u32(S0[3 : 0].u4) * u4_to_u32(S1[3 : 0].u4);\ntmp += u4_to_u32(S0[7 : 4].u4) * u4_to_u32(S1[7 : 4].u4);\ntmp += u4_to_u32(S0[11 : 8].u4) * u4_to_u32(S1[11 : 8].u4);\ntmp += u4_to_u32(S0[15 : 12].u4) * u4_to_u32(S1[15 : 12].u4);\ntmp += u4_to_u32(S0[19 : 16].u4) * u4_to_u32(S1[19 : 16].u4);\ntmp += u4_to_u32(S0[23 : 20].u4) * u4_to_u32(S1[23 : 20].u4);\ntmp += u4_to_u32(S0[27 : 24].u4) * u4_to_u32(S1[27 : 24].u4);\ntmp += u4_to_u32(S0[31 : 28].u4) * u4_to_u32(S1[31 : 28].u4);\nD0.u32 = tmp", "example": "v_dot8_u32_u4 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 270, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_dot8c_i32_i4", "mnemonic": "v_dot8c_i32_i4", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V DOT8C I32 I4", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Compute the dot product of two packed 8-D signed 4-bit integer inputs in the signed 32-bit integer domain and accumulate with the signed 32-bit…", "description": "Compute the dot product of two packed 8-D signed 4-bit integer inputs in the signed 32-bit integer domain and accumulate with the signed 32-bit integer value in the destination register.", "syntax": "v_dot8c_i32_i4", "operands": [], "dataTypes": [ "i32" ], "semantics": "tmp = D0.i32;\ntmp += i4_to_i32(S0[3 : 0].i4) * i4_to_i32(S1[3 : 0].i4);\ntmp += i4_to_i32(S0[7 : 4].i4) * i4_to_i32(S1[7 : 4].i4);\ntmp += i4_to_i32(S0[11 : 8].i4) * i4_to_i32(S1[11 : 8].i4);\ntmp += i4_to_i32(S0[15 : 12].i4) * i4_to_i32(S1[15 : 12].i4);\ntmp += i4_to_i32(S0[19 : 16].i4) * i4_to_i32(S1[19 : 16].i4);\ntmp += i4_to_i32(S0[23 : 20].i4) * i4_to_i32(S1[23 : 20].i4);\ntmp += i4_to_i32(S0[27 : 24].i4) * i4_to_i32(S1[27 : 24].i4);\ntmp += i4_to_i32(S0[31 : 28].i4) * i4_to_i32(S1[31 : 28].i4);\nD0.i32 = tmp", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 184, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_exp_bf16", "mnemonic": "v_exp_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V EXP BF16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_exp_bf16", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_exp_f16", "mnemonic": "v_exp_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V EXP F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate 2 raised to the power of the half-precision float input and store the result into a vector register.", "description": "Calculate 2 raised to the power of the half-precision float input and store the result into a vector register.", "syntax": "v_exp_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.f16 = pow(16'2.0, S0.f16)", "example": "V_EXP_F16(0xfc00) => 0x0000 // exp(-INF) = 0\nV_EXP_F16(0x8000) => 0x3c00 // exp(-0.0) = 1\nV_EXP_F16(0x7c00) => 0x7c00 // exp(+INF) = +INF", "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "1ULP accuracy, denormals are supported.", "sourcePdfPage": 207, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_exp_f32", "mnemonic": "v_exp_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V EXP F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate 2 raised to the power of the single-precision float input and store the result into a vector register.", "description": "Calculate 2 raised to the power of the single-precision float input and store the result into a vector register.", "syntax": "v_exp_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.f32 = pow(2.0F, S0.f32)", "example": "V_EXP_F32(0xff800000) => 0x00000000 // exp(-INF) = 0\nV_EXP_F32(0x80000000) => 0x3f800000 // exp(-0.0) = 1\nV_EXP_F32(0x7f800000) => 0x7f800000 // exp(+INF) = +INF", "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "1ULP accuracy, denormals are flushed.", "sourcePdfPage": 195, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_exp_legacy_f32", "mnemonic": "v_exp_legacy_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V EXP LEGACY F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_exp_legacy_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_ffbh_i32", "mnemonic": "v_ffbh_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FFBH I32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Count the number of leading bits that are the same as the sign bit of a vector input and store the result into a vector register.", "description": "Count the number of leading bits that are the same as the sign bit of a vector input and store the result into a vector register. Store -1 if all input bits are the same.", "syntax": "v_ffbh_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "D0.i32 = -1;\n// Set if all bits are the same\nfor i in 1 : 31 do\n// Search from MSB\nif S0.i32[31 - i] != S0.i32[31] then\nD0.i32 = i;\nbreak\nendif\nendfor", "example": "V_FFBH_I32(0x00000000) => 0xffffffff\nV_FFBH_I32(0x40000000) => 1\nV_FFBH_I32(0x80000000) => 1\nV_FFBH_I32(0x0fffffff) => 4", "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 201, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_ffbh_u32", "mnemonic": "v_ffbh_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FFBH U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Count the number of leading \"0\" bits before the first \"1\" in a vector input and store the result into a vector register.", "description": "Count the number of leading \"0\" bits before the first \"1\" in a vector input and store the result into a vector register. Store -1 if there are no \"1\" bits.", "syntax": "v_ffbh_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "D0.i32 = -1;\n// Set if no ones are found\nfor i in 0 : 31 do\n// Search from MSB\nif S0.u32[31 - i] == 1'1U then\nD0.i32 = i;\nbreak\nendif\nendfor", "example": "V_FFBH_U32(0x00000000) => 0xffffffff\nV_FFBH_U32(0x800000ff) => 0\nV_FFBH_U32(0x100000ff) => 3\nV_FFBH_U32(0x0000ffff) => 16", "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 200, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_ffbl_b32", "mnemonic": "v_ffbl_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FFBL B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Count the number of trailing \"0\" bits before the first \"1\" in a vector input and store the result into a vector register.", "description": "Count the number of trailing \"0\" bits before the first \"1\" in a vector input and store the result into a vector register. Store -1 if there are no \"1\" bits in the input.", "syntax": "v_ffbl_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.i32 = -1;\n// Set if no ones are found\nfor i in 0 : 31 do\n// Search from LSB\nif S0.u32[i] == 1'1U then\nD0.i32 = i;\nbreak\nendif\nendfor", "example": "V_FFBL_B32(0x00000000) => 0xffffffff\nV_FFBL_B32(0xff000001) => 0\nV_FFBL_B32(0xff000008) => 3\nV_FFBL_B32(0xffff0000) => 16", "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 200, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_floor_f16", "mnemonic": "v_floor_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FLOOR F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Round the half-precision float input down to previous integer and store the result in floating point format into a vector register.", "description": "Round the half-precision float input down to previous integer and store the result in floating point format into a vector register.", "syntax": "v_floor_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.f16 = trunc(S0.f16);\nif ((S0.f16 < 16'0.0) && (S0.f16 != D0.f16)) then\nD0.f16 += -16'1.0\nendif", "example": "v_floor_f16 v5, -1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 208, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_floor_f32", "mnemonic": "v_floor_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FLOOR F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Round the single-precision float input down to previous integer and store the result in floating point format into a vector register.", "description": "Round the single-precision float input down to previous integer and store the result in floating point format into a vector register.", "syntax": "v_floor_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.f32 = trunc(S0.f32);\nif ((S0.f32 < 0.0F) && (S0.f32 != D0.f32)) then\nD0.f32 += -1.0F\nendif", "example": "v_floor_f32 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 195, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_floor_f64", "mnemonic": "v_floor_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FLOOR F64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Round the double-precision float input down to previous integer and store the result in floating point format into a vector register.", "description": "Round the double-precision float input down to previous integer and store the result in floating point format into a vector register.", "syntax": "v_floor_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "D0.f64 = trunc(S0.f64);\nif ((S0.f64 < 0.0) && (S0.f64 != D0.f64)) then\nD0.f64 += -1.0\nendif", "example": "v_floor_f64 v[5:6], -1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 193, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_fma_dx9_zero_f32", "mnemonic": "v_fma_dx9_zero_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FMA DX9 ZERO F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply and add single-precision values. Follows DX9 rules where 0.0 times anything produces 0.0.", "description": "Multiply and add single-precision values. Follows DX9 rules where 0.0 times anything produces 0.0.", "syntax": "v_fma_dx9_zero_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": "v_fma_dx9_zero_f32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_fma_f16", "mnemonic": "v_fma_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FMA F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two half-precision float inputs and add a third input using fused multiply add, and store the result into a vector register.", "description": "Multiply two half-precision float inputs and add a third input using fused multiply add, and store the result into a vector register.", "syntax": "v_fma_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.f16 = fma(S0.f16, S1.f16, S2.f16)", "example": "v_fma_f16 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "0.5ULP accuracy, denormals are supported. If OPSEL[3] is 0 Result is written to 16 LSBs of destination VGPR and hi 16 bits are preserved. If OPSEL[3] is 1 Result is written to 16 MSBs of destination VGPR and lo 16 bits are preserved.", "sourcePdfPage": 358, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_fma_f16_gfx9", "mnemonic": "v_fma_f16_gfx9", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FMA F16 GFX9", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_fma_f16_gfx9", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_fma_f32", "mnemonic": "v_fma_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FMA F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Per-lane single-precision fused multiply-add.", "description": "Multiply two single-precision float inputs and add a third input using fused multiply add, and store the result into a vector register.", "syntax": "v_fma_f32 VDST, S0, S1, S2", "operands": [ { "name": "VDST", "desc": "Destination VGPR" }, { "name": "S0", "desc": "Multiplicand" }, { "name": "S1", "desc": "Multiplier" }, { "name": "S2", "desc": "Addend" } ], "dataTypes": [ "f32" ], "semantics": "VDST[lane] = round_once(S0[lane].f32 * S1[lane].f32 + S2[lane].f32) for each active lane.", "example": "v_fma_f32 v3, v0, v1, v2 // per-lane v3 = v0 * v1 + v2", "exampleSource": null, "encoding": { "format": "VOP3", "widthBits": 32 }, "executionUnit": "Vector ALU", "registerClasses": [ "VGPR" ], "memorySegment": null, "supportedTargets": [ "gfx942", "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_fma_f64", "mnemonic": "v_fma_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FMA F64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two double-precision float inputs and add a third input using fused multiply add, and store the result into a vector register.", "description": "Multiply two double-precision float inputs and add a third input using fused multiply add, and store the result into a vector register.", "syntax": "v_fma_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "D0.f64 = fma(S0.f64, S1.f64, S2.f64)", "example": "v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "0.5ULP accuracy, denormals are supported.", "sourcePdfPage": 339, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_fma_legacy_f16", "mnemonic": "v_fma_legacy_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FMA LEGACY F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Fused half precision multiply add. Implements IEEE rules and non-standard rule for OPSEL.", "description": "Fused half precision multiply add. Implements IEEE rules and non-standard rule for OPSEL.", "syntax": "v_fma_legacy_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "tmp = fma(S0.f16, S1.f16, S2.f16);\nif OPSEL.u4[3] then\nD0 = { tmp.f16, D0[15 : 0] }\nelse\nD0 = { 16'0, tmp.f16 }\nendif", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 352, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_fma_legacy_f32", "mnemonic": "v_fma_legacy_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FMA LEGACY F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply and add single-precision values. Follows DX9 rules where 0.0 times anything produces 0.0.", "description": "Multiply and add single-precision values. Follows DX9 rules where 0.0 times anything produces 0.0.", "syntax": "v_fma_legacy_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": "v_fma_legacy_f32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_fma_mix_bf16_t16", "mnemonic": "v_fma_mix_bf16_t16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FMA MIX BF16 T16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3P vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_fma_mix_bf16_t16", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_fma_mix_f16_t16", "mnemonic": "v_fma_mix_f16_t16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FMA MIX F16 T16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3P vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_fma_mix_f16_t16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_fma_mix_f32", "mnemonic": "v_fma_mix_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FMA MIX F32", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Multiply two inputs and add a third input using fused multiply add where the inputs are a mix of half-precision float and single-precision float…", "description": "Multiply two inputs and add a third input using fused multiply add where the inputs are a mix of half-precision float and single-precision float values. Store the result into a vector register.", "syntax": "v_fma_mix_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": "v_fma_mix_f32 v5, s1, s2, v3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_fma_mix_f32_bf16", "mnemonic": "v_fma_mix_f32_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FMA MIX F32 BF16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3P vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_fma_mix_f32_bf16", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_fma_mixhi_bf16", "mnemonic": "v_fma_mixhi_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FMA MIXHI BF16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3P vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_fma_mixhi_bf16", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_fma_mixhi_f16", "mnemonic": "v_fma_mixhi_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FMA MIXHI F16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Multiply two inputs and add a third input using fused multiply add where the inputs are a mix of half-precision float and single-precision float…", "description": "Multiply two inputs and add a third input using fused multiply add where the inputs are a mix of half-precision float and single-precision float values. Convert the result to a half-precision float. Store the result into the high bits of a vector register.", "syntax": "v_fma_mixhi_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": "v_fma_mixhi_f16 v5, s1, s2, v3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_fma_mixlo_bf16", "mnemonic": "v_fma_mixlo_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FMA MIXLO BF16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3P vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_fma_mixlo_bf16", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_fma_mixlo_f16", "mnemonic": "v_fma_mixlo_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FMA MIXLO F16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Multiply two inputs and add a third input using fused multiply add where the inputs are a mix of half-precision float and single-precision float…", "description": "Multiply two inputs and add a third input using fused multiply add where the inputs are a mix of half-precision float and single-precision float values. Convert the result to a half-precision float. Store the result into the low bits of a vector register.", "syntax": "v_fma_mixlo_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": "v_fma_mixlo_f16 v5, s1, s2, v3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_fmaak_f16", "mnemonic": "v_fmaak_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FMAAK F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two half-precision float inputs and add a literal constant using fused multiply add, and store the result into a vector register.", "description": "Multiply two half-precision float inputs and add a literal constant using fused multiply add, and store the result into a vector register.", "syntax": "v_fmaak_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": "v_fmaak_f16 v5, -1, v2, 0xfe0b", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_fmaak_f16_fake16", "mnemonic": "v_fmaak_f16_fake16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FMAAK F16 FAKE16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP2 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_fmaak_f16_fake16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_fmaak_f16_t16", "mnemonic": "v_fmaak_f16_t16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FMAAK F16 T16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP2 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_fmaak_f16_t16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_fmaak_f32", "mnemonic": "v_fmaak_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FMAAK F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two single-precision float inputs and add a literal constant using fused multiply add, and store the result into a vector register.", "description": "Multiply two single-precision float inputs and add a literal constant using fused multiply add, and store the result into a vector register.", "syntax": "v_fmaak_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.f32 = fma(S0.f32, S1.f32, SIMM32.f32)", "example": "v_fmaak_f32 v5, -1, v2, 0xaf123456", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100", "gfx942" ], "unsupportedTargets": [], "architecturalNotes": "This opcode cannot use the VOP3 encoding and cannot use input/output modifiers.", "sourcePdfPage": 175, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_fmaak_f64", "mnemonic": "v_fmaak_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FMAAK F64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP2 vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_fmaak_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_fmac_f16", "mnemonic": "v_fmac_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FMAC F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two half-precision float inputs and accumulate the result into the destination register using fused multiply add.", "description": "Multiply two half-precision float inputs and accumulate the result into the destination register using fused multiply add.", "syntax": "v_fmac_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": "v_fmac_f16 v5, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_fmac_f16_fake16", "mnemonic": "v_fmac_f16_fake16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FMAC F16 FAKE16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP2 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_fmac_f16_fake16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_fmac_f16_t16", "mnemonic": "v_fmac_f16_t16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FMAC F16 T16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP2 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_fmac_f16_t16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_fmac_f32", "mnemonic": "v_fmac_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FMAC F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two floating point inputs and accumulate the result into the destination register using fused multiply add.", "description": "Multiply two floating point inputs and accumulate the result into the destination register using fused multiply add.", "syntax": "v_fmac_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.f32 = fma(S0.f32, S1.f32, D0.f32)", "example": "v_fmac_f32 v5, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 185, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_fmac_f64", "mnemonic": "v_fmac_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FMAC F64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two floating point inputs and accumulate the result into the destination register using fused multiply add.", "description": "Multiply two floating point inputs and accumulate the result into the destination register using fused multiply add.", "syntax": "v_fmac_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "D0.f64 = fma(S0.f64, S1.f64, D0.f64)", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 170, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_fmac_legacy_f32", "mnemonic": "v_fmac_legacy_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FMAC LEGACY F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two single-precision values and accumulate the result with the destination. Follows DX9 rules where 0.0 times anything produces 0.0.", "description": "Multiply two single-precision values and accumulate the result with the destination. Follows DX9 rules where 0.0 times anything produces 0.0.", "syntax": "v_fmac_legacy_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": "v_fmac_legacy_f32 v5, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_fmamk_f16", "mnemonic": "v_fmamk_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FMAMK F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply a half-precision float input with a literal constant and add a second half-precision float input using fused multiply add, and store the…", "description": "Multiply a half-precision float input with a literal constant and add a second half-precision float input using fused multiply add, and store the result into a vector register.", "syntax": "v_fmamk_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": "v_fmamk_f16 v5, -1, 0xfe0b, v3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_fmamk_f16_fake16", "mnemonic": "v_fmamk_f16_fake16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FMAMK F16 FAKE16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP2 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_fmamk_f16_fake16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_fmamk_f16_t16", "mnemonic": "v_fmamk_f16_t16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FMAMK F16 T16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP2 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_fmamk_f16_t16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_fmamk_f32", "mnemonic": "v_fmamk_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FMAMK F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply a single-precision float input with a literal constant and add a second single-precision float input using fused multiply add, and store the…", "description": "Multiply a single-precision float input with a literal constant and add a second single-precision float input using fused multiply add, and store the result into a vector register.", "syntax": "v_fmamk_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.f32 = fma(S0.f32, SIMM32.f32, S1.f32)", "example": "v_fmamk_f32 v5, -1, 0xaf123456, v3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100", "gfx942" ], "unsupportedTargets": [], "architecturalNotes": "This opcode cannot use the VOP3 encoding and cannot use input/output modifiers.", "sourcePdfPage": 174, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_fmamk_f64", "mnemonic": "v_fmamk_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FMAMK F64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP2 vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_fmamk_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_fract_f16", "mnemonic": "v_fract_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FRACT F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Compute the fractional portion of a half-precision float input and store the result in floating point format into a vector register.", "description": "Compute the fractional portion of a half-precision float input and store the result in floating point format into a vector register.", "syntax": "v_fract_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.f16 = S0.f16 + -floor(S0.f16)", "example": "v_fract_f16 v5.l, s1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "0.5ULP accuracy, denormals are accepted. This is intended to comply with the DX specification of fract where the function behaves like an extension of integer modulus; be aware this may differ from how fract() is defined in other domains. For example: fract(- 1.2) = 0.8 in DX.", "sourcePdfPage": 209, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_fract_f32", "mnemonic": "v_fract_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FRACT F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Compute the fractional portion of a single-precision float input and store the result in floating point format into a vector register.", "description": "Compute the fractional portion of a single-precision float input and store the result in floating point format into a vector register.", "syntax": "v_fract_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.f32 = S0.f32 + -floor(S0.f32)", "example": "v_fract_f32 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "0.5ULP accuracy, denormals are accepted. This is intended to comply with the DX specification of fract where the function behaves like an extension of integer modulus; be aware this may differ from how fract() is defined in other domains. For example: fract(- 1.2) = 0.8 in DX. Obey round mode, result clamped to 0x3f7fffff.", "sourcePdfPage": 193, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_fract_f64", "mnemonic": "v_fract_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FRACT F64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Compute the fractional portion of a double-precision float input and store the result in floating point format into a vector register.", "description": "Compute the fractional portion of a double-precision float input and store the result in floating point format into a vector register.", "syntax": "v_fract_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "D0.f64 = S0.f64 + -floor(S0.f64)", "example": "v_fract_f64 v[5:6], -1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "0.5ULP accuracy, denormals are accepted. This is intended to comply with the DX specification of fract where the function behaves like an extension of integer modulus; be aware this may differ from how fract() is defined in other domains. For example: fract(- 1.2) = 0.8 in DX. Obey round mode, result clamped to 0x3fefffffffffffff.", "sourcePdfPage": 202, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_frexp_exp_i16_f16", "mnemonic": "v_frexp_exp_i16_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FREXP EXP I16 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Extract the exponent of a half-precision float input and store the result as a signed 16-bit integer into a vector register.", "description": "Extract the exponent of a half-precision float input and store the result as a signed 16-bit integer into a vector register.", "syntax": "v_frexp_exp_i16_f16", "operands": [], "dataTypes": [ "f16", "i16" ], "semantics": "if ((64'F(S0.f16) == +INF) || (64'F(S0.f16) == -INF) || isNAN(64'F(S0.f16))) then\nD0.i16 = 16'0\nelse\nD0.i16 = 16'I(exponent(S0.f16) - 15 + 1)\nendif", "example": "v_frexp_exp_i16_f16 v5.l, s1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "This operation satisfies the invariant S0.f16 = significand * (2 ** exponent). See also V_FREXP_MANT_F16, which returns the significand. See the C library function frexp() for more information.", "sourcePdfPage": 207, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_frexp_exp_i32_f32", "mnemonic": "v_frexp_exp_i32_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FREXP EXP I32 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Extract the exponent of a single-precision float input and store the result as a signed 32-bit integer into a vector register.", "description": "Extract the exponent of a single-precision float input and store the result as a signed 32-bit integer into a vector register.", "syntax": "v_frexp_exp_i32_f32", "operands": [], "dataTypes": [ "f32", "i32" ], "semantics": "if ((64'F(S0.f32) == +INF) || (64'F(S0.f32) == -INF) || isNAN(64'F(S0.f32))) then\nD0.i32 = 0\nelse\nD0.i32 = exponent(S0.f32) - 127 + 1\nendif", "example": "v_frexp_exp_i32_f32 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "This operation satisfies the invariant S0.f32 = significand * (2 ** exponent). See also V_FREXP_MANT_F32, which returns the significand. See the C library function frexp() for more information.", "sourcePdfPage": 203, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_frexp_exp_i32_f64", "mnemonic": "v_frexp_exp_i32_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FREXP EXP I32 F64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Extract the exponent of a double-precision float input and store the result as a signed 32-bit integer into a vector register.", "description": "Extract the exponent of a double-precision float input and store the result as a signed 32-bit integer into a vector register.", "syntax": "v_frexp_exp_i32_f64", "operands": [], "dataTypes": [ "f64", "i32" ], "semantics": "if ((S0.f64 == +INF) || (S0.f64 == -INF) || isNAN(S0.f64)) then\nD0.i32 = 0\nelse\nD0.i32 = exponent(S0.f64) - 1023 + 1\nendif", "example": "v_frexp_exp_i32_f64 v5, -1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "This operation satisfies the invariant S0.f64 = significand * (2 ** exponent). See also V_FREXP_MANT_F64, which returns the significand. See the C library function frexp() for more information.", "sourcePdfPage": 201, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_frexp_mant_f16", "mnemonic": "v_frexp_mant_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FREXP MANT F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Extract the binary significand, or mantissa, of a half-precision float input and store the result as a half- precision float into a vector register.", "description": "Extract the binary significand, or mantissa, of a half-precision float input and store the result as a half- precision float into a vector register.", "syntax": "v_frexp_mant_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "if ((64'F(S0.f16) == +INF) || (64'F(S0.f16) == -INF) || isNAN(64'F(S0.f16))) then\nD0.f16 = S0.f16\nelse\nD0.f16 = mantissa(S0.f16)\nendif", "example": "v_frexp_mant_f16 v5.l, s1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "This operation satisfies the invariant S0.f16 = significand * (2 ** exponent). Result range is in (-1.0,-0.5][0.5,1.0) in normal cases. See also V_FREXP_EXP_I16_F16, which returns integer exponent. See the C library function frexp() for more information.", "sourcePdfPage": 207, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_frexp_mant_f32", "mnemonic": "v_frexp_mant_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FREXP MANT F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Extract the binary significand, or mantissa, of a single-precision float input and store the result as a single- precision float into a vector…", "description": "Extract the binary significand, or mantissa, of a single-precision float input and store the result as a single- precision float into a vector register.", "syntax": "v_frexp_mant_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "if ((64'F(S0.f32) == +INF) || (64'F(S0.f32) == -INF) || isNAN(64'F(S0.f32))) then\nD0.f32 = S0.f32\nelse\nD0.f32 = mantissa(S0.f32)\nendif", "example": "v_frexp_mant_f32 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "This operation satisfies the invariant S0.f32 = significand * (2 ** exponent). Result range is in (-1.0,-0.5][0.5,1.0) in normal cases. See also V_FREXP_EXP_I32_F32, which returns integer exponent. See the C library function frexp() for more information.", "sourcePdfPage": 203, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_frexp_mant_f64", "mnemonic": "v_frexp_mant_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V FREXP MANT F64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Extract the binary significand, or mantissa, of a double-precision float input and store the result as a double- precision float into a vector…", "description": "Extract the binary significand, or mantissa, of a double-precision float input and store the result as a double- precision float into a vector register.", "syntax": "v_frexp_mant_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "if ((S0.f64 == +INF) || (S0.f64 == -INF) || isNAN(S0.f64)) then\nD0.f64 = S0.f64\nelse\nD0.f64 = mantissa(S0.f64)\nendif", "example": "v_frexp_mant_f64 v[5:6], -1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "This operation satisfies the invariant S0.f64 = significand * (2 ** exponent). Result range is in (-1.0,-0.5][0.5,1.0) in normal cases. See also V_FREXP_EXP_I32_F64, which returns integer exponent. See the C library function frexp() for more information.", "sourcePdfPage": 202, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_interp_mov_f32", "mnemonic": "v_interp_mov_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V INTERP MOV F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Given an attribute specifier and a parameter ID (P0, P10 or P20), load one of the parameter values from the local data share into a vector register.", "description": "Given an attribute specifier and a parameter ID (P0, P10 or P20), load one of the parameter values from the local data share into a vector register.", "syntax": "v_interp_mov_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_interp_p10_f16_f32", "mnemonic": "v_interp_p10_f16_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V INTERP P10 F16 F32", "category": "Vector Interpolation", "instructionClass": "vector", "summary": "Given a half-precision float P10 parameter of an attribute, a single-precision float I coordinate and a half-precision float P0 parameter as inputs…", "description": "Given a half-precision float P10 parameter of an attribute, a single-precision float I coordinate and a half-precision float P0 parameter as inputs, compute the first part of parameter interpolation and store the intermediate result in single-precision float format into a vector register. Use V_INTERP_P2_F16_F32 to complete the operation.", "syntax": "v_interp_p10_f16_f32", "operands": [], "dataTypes": [ "f16", "f32" ], "semantics": "", "example": "v_interp_p10_f16_f32 v0, -v1.l, v2, v3.l", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VINTERP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_interp_p10_f32", "mnemonic": "v_interp_p10_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V INTERP P10 F32", "category": "Vector Interpolation", "instructionClass": "vector", "summary": "Given the P10 parameter of an attribute, the I coordinate and the P0 parameter as single-precision float inputs, compute the first part of parameter…", "description": "Given the P10 parameter of an attribute, the I coordinate and the P0 parameter as single-precision float inputs, compute the first part of parameter interpolation and store the intermediate result into a vector register. Use V_INTERP_P2_F32 to complete the operation.", "syntax": "v_interp_p10_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": "v_interp_p10_f32 v0, -v1, v2, v3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VINTERP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_interp_p10_rtz_f16_f32", "mnemonic": "v_interp_p10_rtz_f16_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V INTERP P10 RTZ F16 F32", "category": "Vector Interpolation", "instructionClass": "vector", "summary": "Given a half-precision float P10 parameter of an attribute, a single-precision float I coordinate and a half-precision float P0 parameter as inputs…", "description": "Given a half-precision float P10 parameter of an attribute, a single-precision float I coordinate and a half-precision float P0 parameter as inputs, compute the first part of parameter interpolation using round toward zero semantics and store the intermediate result in single-precision float format into a vector register. Use V_INTERP_P2_RTZ_F16_F32 to complete the operation.", "syntax": "v_interp_p10_rtz_f16_f32", "operands": [], "dataTypes": [ "f16", "f32" ], "semantics": "", "example": "v_interp_p10_rtz_f16_f32 v0, -v1.l, v2, v3.l", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VINTERP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_interp_p1_f32", "mnemonic": "v_interp_p1_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V INTERP P1 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Given the I coordinate in a vector register and an attribute specifier, load parameter data from the local data share, compute the first part of…", "description": "Given the I coordinate in a vector register and an attribute specifier, load parameter data from the local data share, compute the first part of parameter interpolation and store the intermediate result into a vector register. Use V_INTERP_P2_F32 to complete the operation.", "syntax": "v_interp_p1_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_interp_p1ll_f16", "mnemonic": "v_interp_p1ll_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V INTERP P1LL F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Given a single-precision float I coordinate in a vector register and an attribute specifier, load two half-precision float parameter values from the…", "description": "Given a single-precision float I coordinate in a vector register and an attribute specifier, load two half-precision float parameter values from the local data share, compute the first part of parameter interpolation and store the intermediate result into a vector register. Use V_INTERP_P2_F16 to complete the operation.", "syntax": "v_interp_p1ll_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_interp_p1lv_f16", "mnemonic": "v_interp_p1lv_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V INTERP P1LV F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Given a single-precision float I coordinate in a vector register, a half-precision float P0 value in another vector register, and an attribute…", "description": "Given a single-precision float I coordinate in a vector register, a half-precision float P0 value in another vector register, and an attribute specifier, load a half-precision float parameter value from the local data share, compute the first part of parameter interpolation and store the intermediate result into a vector register. Use V_INTERP_P2_F16 to complete the operation.", "syntax": "v_interp_p1lv_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_interp_p2_f16", "mnemonic": "v_interp_p2_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V INTERP P2 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Given a single-precision float J coordinate in a vector register, an attribute specifier and the result of a prior V_INTERP_P1_F32 in another vector…", "description": "Given a single-precision float J coordinate in a vector register, an attribute specifier and the result of a prior V_INTERP_P1_F32 in another vector register, load a half-precision float parameter value from the local data share, compute the second part of parameter interpolation and store the final result as a half-precision float value into a vector register.", "syntax": "v_interp_p2_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_interp_p2_f16_f32", "mnemonic": "v_interp_p2_f16_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V INTERP P2 F16 F32", "category": "Vector Interpolation", "instructionClass": "vector", "summary": "Given a half-precision float P20 parameter of an attribute, a single-precision float J coordinate and the result of a prior V_INTERP_P10_F16_F32…", "description": "Given a half-precision float P20 parameter of an attribute, a single-precision float J coordinate and the result of a prior V_INTERP_P10_F16_F32 instruction as inputs, compute the second part of parameter interpolation and store the final result into a vector register.", "syntax": "v_interp_p2_f16_f32", "operands": [], "dataTypes": [ "f16", "f32" ], "semantics": "", "example": "v_interp_p2_f16_f32 v0.l, -v1.l, v2, v3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VINTERP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_interp_p2_f16_opsel", "mnemonic": "v_interp_p2_f16_opsel", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V INTERP P2 F16 OPSEL", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_interp_p2_f16_opsel", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_interp_p2_f32", "mnemonic": "v_interp_p2_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V INTERP P2 F32", "category": "Vector Interpolation", "instructionClass": "vector", "summary": "Given the J coordinate in a vector register, an attribute specifier and the result of a prior V_INTERP_P1_F32 in the destination vector register…", "description": "Given the J coordinate in a vector register, an attribute specifier and the result of a prior V_INTERP_P1_F32 in the destination vector register, load parameter data from the local data share, compute the second part of parameter interpolation and store the final result into a vector register.", "syntax": "v_interp_p2_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": "v_interp_p2_f32 v0, -v1, v2, v3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VINTERP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_interp_p2_legacy_f16", "mnemonic": "v_interp_p2_legacy_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V INTERP P2 LEGACY F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Half-precision interpolation.", "description": "Half-precision interpolation.", "syntax": "v_interp_p2_legacy_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_interp_p2_rtz_f16_f32", "mnemonic": "v_interp_p2_rtz_f16_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V INTERP P2 RTZ F16 F32", "category": "Vector Interpolation", "instructionClass": "vector", "summary": "Given a half-precision float P20 parameter of an attribute, a single-precision float J coordinate and the result of a prior V_INTERP_P10_RTZ_F16_F32…", "description": "Given a half-precision float P20 parameter of an attribute, a single-precision float J coordinate and the result of a prior V_INTERP_P10_RTZ_F16_F32 instruction as inputs, compute the second part of parameter interpolation using round toward zero semantics and store the final result into a vector register.", "syntax": "v_interp_p2_rtz_f16_f32", "operands": [], "dataTypes": [ "f16", "f32" ], "semantics": "", "example": "v_interp_p2_rtz_f16_f32 v0.l, -v1.l, v2, v3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VINTERP" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_ldexp_f16", "mnemonic": "v_ldexp_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V LDEXP F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply the first input, a floating point value, by an integral power of 2 specified in the second input, a signed integer value, and store the…", "description": "Multiply the first input, a floating point value, by an integral power of 2 specified in the second input, a signed integer value, and store the floating point result into a vector register.", "syntax": "v_ldexp_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.f16 = S0.f16 * 16'F(2.0F ** 32'I(S1.i16))", "example": "v_ldexp_f16 v5, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Compare with the ldexp() function in C. Note that the S1 has a format of f16 since floating point literal constants are interpreted as 16 bit value for this opcode.", "sourcePdfPage": 182, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_ldexp_f16_fake16", "mnemonic": "v_ldexp_f16_fake16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V LDEXP F16 FAKE16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP2 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_ldexp_f16_fake16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_ldexp_f16_t16", "mnemonic": "v_ldexp_f16_t16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V LDEXP F16 T16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP2 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_ldexp_f16_t16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_ldexp_f32", "mnemonic": "v_ldexp_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V LDEXP F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply the first input, a floating point value, by an integral power of 2 specified in the second input, a signed integer value, and store the…", "description": "Multiply the first input, a floating point value, by an integral power of 2 specified in the second input, a signed integer value, and store the floating point result into a vector register.", "syntax": "v_ldexp_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": "v_ldexp_f32 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_ldexp_f64", "mnemonic": "v_ldexp_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V LDEXP F64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply the first input, a floating point value, by an integral power of 2 specified in the second input, a signed integer value, and store the…", "description": "Multiply the first input, a floating point value, by an integral power of 2 specified in the second input, a signed integer value, and store the floating point result into a vector register.", "syntax": "v_ldexp_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "D0.f64 = S0.f64 * 2.0 ** S1.i32", "example": "v_ldexp_f64 v[5:6], -1, -1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Compare with the ldexp() function in C.", "sourcePdfPage": 361, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_lerp_u8", "mnemonic": "v_lerp_u8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V LERP U8", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Average two 4-D vectors stored as packed bytes in the first two inputs with rounding control provided by the third input, then store the result into…", "description": "Average two 4-D vectors stored as packed bytes in the first two inputs with rounding control provided by the third input, then store the result into a vector register. Each byte in the third input acts as a rounding mode for the corresponding element; if the LSB is set then 0.5 rounds up, otherwise 0.5 truncates.", "syntax": "v_lerp_u8", "operands": [], "dataTypes": [ "u8" ], "semantics": "tmp = ((S0.u32[31 : 24] + S1.u32[31 : 24] + S2.u32[24].u8) >> 1U << 24U);\ntmp += ((S0.u32[23 : 16] + S1.u32[23 : 16] + S2.u32[16].u8) >> 1U << 16U);\ntmp += ((S0.u32[15 : 8] + S1.u32[15 : 8] + S2.u32[8].u8) >> 1U << 8U);\ntmp += ((S0.u32[7 : 0] + S1.u32[7 : 0] + S2.u32[0].u8) >> 1U);\nD0.u32 = tmp.u32", "example": "v_lerp_u8 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 339, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_log_bf16", "mnemonic": "v_log_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V LOG BF16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_log_bf16", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_log_f16", "mnemonic": "v_log_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V LOG F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate the base 2 logarithm of the half-precision float input and store the result into a vector register.", "description": "Calculate the base 2 logarithm of the half-precision float input and store the result into a vector register.", "syntax": "v_log_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.f16 = log2(S0.f16)", "example": "V_LOG_F16(0xfc00) => 0xfe00 // log(-INF) = NAN\nV_LOG_F16(0xbc00) => 0xfe00 // log(-1.0) = NAN\nV_LOG_F16(0x8000) => 0xfc00 // log(-0.0) = -INF\nV_LOG_F16(0x0000) => 0xfc00 // log(+0.0) = -INF", "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "1ULP accuracy, denormals are supported.", "sourcePdfPage": 206, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_log_f32", "mnemonic": "v_log_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V LOG F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate the base 2 logarithm of the single-precision float input and store the result into a vector register.", "description": "Calculate the base 2 logarithm of the single-precision float input and store the result into a vector register.", "syntax": "v_log_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.f32 = log2(S0.f32)", "example": "V_LOG_F32(0xff800000) => 0xffc00000 // log(-INF) = NAN\nV_LOG_F32(0xbf800000) => 0xffc00000 // log(-1.0) = NAN\nV_LOG_F32(0x80000000) => 0xff800000 // log(-0.0) = -INF\nV_LOG_F32(0x00000000) => 0xff800000 // log(+0.0) = -INF", "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "1ULP accuracy, denormals are flushed.", "sourcePdfPage": 195, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_log_legacy_f32", "mnemonic": "v_log_legacy_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V LOG LEGACY F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_log_legacy_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_lshl_add_u32", "mnemonic": "v_lshl_add_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V LSHL ADD U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Given a shift count in the second input, calculate the logical shift left of the first input, then add the third input to the intermediate result…", "description": "Given a shift count in the second input, calculate the logical shift left of the first input, then add the third input to the intermediate result, then store the final result into a vector register.", "syntax": "v_lshl_add_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "D0.u32 = (S0.u32 << S1.u32[4 : 0].u32) + S2.u32", "example": "v_lshl_add_u32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 356, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_lshl_add_u64", "mnemonic": "v_lshl_add_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V LSHL ADD U64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Given a shift count in the second input, calculate the logical shift left of the first input, then add the third input to the intermediate result…", "description": "Given a shift count in the second input, calculate the logical shift left of the first input, then add the third input to the intermediate result, then store the final result into a vector register. For this opcode the shift count must be between 0 and 4, higher shift counts are unsupported.", "syntax": "v_lshl_add_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "D0.u64 = (S0.u64 << S1.u32[2 : 0].u32) + S2.u64", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "The design treats unsupported shift counts as a shift of zero.", "sourcePdfPage": 359, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_lshl_b32", "mnemonic": "v_lshl_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V LSHL B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP2 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_lshl_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_lshl_b64", "mnemonic": "v_lshl_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V LSHL B64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_lshl_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_lshl_or_b32", "mnemonic": "v_lshl_or_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V LSHL OR B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Given a shift count in the second input, calculate the logical shift left of the first input, then calculate the bitwise OR of the intermediate…", "description": "Given a shift count in the second input, calculate the logical shift left of the first input, then calculate the bitwise OR of the intermediate result and the third input, then store the final result into a vector register.", "syntax": "v_lshl_or_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.u32 = ((S0.u32 << S1.u32[4 : 0].u32) | S2.u32)", "example": "v_lshl_or_b32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 356, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_lshlrev_b16", "mnemonic": "v_lshlrev_b16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V LSHLREV B16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Given a shift count in the first vector input, calculate the logical shift left of the second vector input and store the result into a vector…", "description": "Given a shift count in the first vector input, calculate the logical shift left of the second vector input and store the result into a vector register.", "syntax": "v_lshlrev_b16", "operands": [], "dataTypes": [ "b16" ], "semantics": "D0.u16 = (S1.u16 << S0[3 : 0].u32)", "example": "v_lshlrev_b16 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 180, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_lshlrev_b32", "mnemonic": "v_lshlrev_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V LSHLREV B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Given a shift count in the first vector input, calculate the logical shift left of the second vector input and store the result into a vector…", "description": "Given a shift count in the first vector input, calculate the logical shift left of the second vector input and store the result into a vector register.", "syntax": "v_lshlrev_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.u32 = (S1.u32 << S0[4 : 0].u32)", "example": "v_lshlrev_b32 v5, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 173, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_lshlrev_b64", "mnemonic": "v_lshlrev_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V LSHLREV B64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Given a shift count in the first vector input, calculate the logical shift left of the second vector input and store the result into a vector…", "description": "Given a shift count in the first vector input, calculate the logical shift left of the second vector input and store the result into a vector register.", "syntax": "v_lshlrev_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": "v_lshlrev_b64 v[5:6], -1, -1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_lshlrev_b64_pseudo", "mnemonic": "v_lshlrev_b64_pseudo", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V LSHLREV B64 PSEUDO", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP2 vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_lshlrev_b64_pseudo", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_lshr_b32", "mnemonic": "v_lshr_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V LSHR B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP2 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_lshr_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_lshr_b64", "mnemonic": "v_lshr_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V LSHR B64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_lshr_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_lshrrev_b16", "mnemonic": "v_lshrrev_b16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V LSHRREV B16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Given a shift count in the first vector input, calculate the logical shift right of the second vector input and store the result into a vector…", "description": "Given a shift count in the first vector input, calculate the logical shift right of the second vector input and store the result into a vector register.", "syntax": "v_lshrrev_b16", "operands": [], "dataTypes": [ "b16" ], "semantics": "D0.u16 = (S1.u16 >> S0[3 : 0].u32)", "example": "v_lshrrev_b16 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 180, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_lshrrev_b32", "mnemonic": "v_lshrrev_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V LSHRREV B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Given a shift count in the first vector input, calculate the logical shift right of the second vector input and store the result into a vector…", "description": "Given a shift count in the first vector input, calculate the logical shift right of the second vector input and store the result into a vector register.", "syntax": "v_lshrrev_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.u32 = (S1.u32 >> S0[4 : 0].u32)", "example": "v_lshrrev_b32 v5, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 173, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_lshrrev_b64", "mnemonic": "v_lshrrev_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V LSHRREV B64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Given a shift count in the first vector input, calculate the logical shift right of the second vector input and store the result into a vector…", "description": "Given a shift count in the first vector input, calculate the logical shift right of the second vector input and store the result into a vector register.", "syntax": "v_lshrrev_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "D0.u64 = (S1.u64 >> S0[5 : 0].u32)", "example": "v_lshrrev_b64 v[5:6], -1, -1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 364, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_mac_f16", "mnemonic": "v_mac_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAC F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two floating point inputs and accumulate the result into the destination register. Implements IEEE rules and non-standard rule for OPSEL.", "description": "Multiply two floating point inputs and accumulate the result into the destination register. Implements IEEE rules and non-standard rule for OPSEL.", "syntax": "v_mac_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "tmp = S0.f16 * S1.f16 + D0.f16;\nif OPSEL.u4[3] then\nD0 = { tmp.f16, D0[15 : 0] }\nelse\nD0 = { 16'0, tmp.f16 }\nendif", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "Supports round mode, exception flags, saturation.", "sourcePdfPage": 178, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_mac_f32", "mnemonic": "v_mac_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAC F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two floating point inputs and accumulate the result into the destination register.", "description": "Multiply two floating point inputs and accumulate the result into the destination register.", "syntax": "v_mac_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_mac_legacy_f32", "mnemonic": "v_mac_legacy_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAC LEGACY F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply and add single-precision values, accumulate with destination. Follows DX9 rules where 0.0 times anything produces 0.0.", "description": "Multiply and add single-precision values, accumulate with destination. Follows DX9 rules where 0.0 times anything produces 0.0.", "syntax": "v_mac_legacy_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_mad_co_i64_i32", "mnemonic": "v_mad_co_i64_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAD CO I64 I32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two signed integer inputs, add a third signed integer input, store the result into a 64-bit vector register and store the overflow/carryout…", "description": "Multiply two signed integer inputs, add a third signed integer input, store the result into a 64-bit vector register and store the overflow/carryout into a scalar mask register.", "syntax": "v_mad_co_i64_i32", "operands": [], "dataTypes": [ "i32", "i64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_mad_co_u64_u32", "mnemonic": "v_mad_co_u64_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAD CO U64 U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two unsigned integer inputs, add a third unsigned integer input, store the result into a 64-bit vector register and store the…", "description": "Multiply two unsigned integer inputs, add a third unsigned integer input, store the result into a 64-bit vector register and store the overflow/carryout into a scalar mask register.", "syntax": "v_mad_co_u64_u32", "operands": [], "dataTypes": [ "u32", "u64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_mad_f16", "mnemonic": "v_mad_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAD F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two half-precision float inputs and add a third input, and store the result into a vector register.", "description": "Multiply two half-precision float inputs and add a third input, and store the result into a vector register.", "syntax": "v_mad_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.f16 = S0.f16 * S1.f16 + S2.f16", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "Supports round mode, exception flags, saturation. 1ULP accuracy, denormals are flushed. If OPSEL[3] is 0 Result is written to 16 LSBs of destination VGPR and hi 16 bits are preserved. If OPSEL[3] is 1 Result is written to 16 MSBs of destination VGPR and lo 16 bits are preserved.", "sourcePdfPage": 357, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_mad_f16_gfx9", "mnemonic": "v_mad_f16_gfx9", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAD F16 GFX9", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_mad_f16_gfx9", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_mad_f32", "mnemonic": "v_mad_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAD F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two single-precision float inputs and add a third input, and store the result into a vector register.", "description": "Multiply two single-precision float inputs and add a third input, and store the result into a vector register.", "syntax": "v_mad_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_mad_i16", "mnemonic": "v_mad_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAD I16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two signed 16-bit integer inputs, add a signed 16-bit integer value from a third input, and store the result into a vector register.", "description": "Multiply two signed 16-bit integer inputs, add a signed 16-bit integer value from a third input, and store the result into a vector register.", "syntax": "v_mad_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "D0.i16 = S0.i16 * S1.i16 + S2.i16", "example": "v_mad_i16 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Supports saturation (signed 16-bit integer domain). If OPSEL[3] is 0 the result is written to 16 LSBs of destination VGPR and the high 16 bits are preserved. If OPSEL[3] is 1 the result is written to 16 MSBs of destination VGPR and the low 16 bits are preserved.", "sourcePdfPage": 358, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_mad_i16_gfx9", "mnemonic": "v_mad_i16_gfx9", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAD I16 GFX9", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on i16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_mad_i16_gfx9", "operands": [], "dataTypes": [ "i16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_mad_i32_i16", "mnemonic": "v_mad_i32_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAD I32 I16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two signed 16-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from a third input, and store the…", "description": "Multiply two signed 16-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from a third input, and store the result as a signed 32-bit integer into a vector register.", "syntax": "v_mad_i32_i16", "operands": [], "dataTypes": [ "i16", "i32" ], "semantics": "D0.i32 = 32'I(S0.i16) * 32'I(S1.i16) + S2.i32", "example": "v_mad_i32_i16 v5, v1, v2, v3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 353, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_mad_i32_i24", "mnemonic": "v_mad_i32_i24", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAD I32 I24", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two signed 24-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from a third input, and store the…", "description": "Multiply two signed 24-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from a third input, and store the result as a signed 32-bit integer into a vector register.", "syntax": "v_mad_i32_i24", "operands": [], "dataTypes": [ "i32" ], "semantics": "D0.i32 = 32'I(S0.i24) * 32'I(S1.i24) + S2.i32", "example": "v_mad_i32_i24 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 335, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_mad_i64_i32", "mnemonic": "v_mad_i64_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAD I64 I32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two signed integer inputs, add a third signed integer input, store the result into a 64-bit vector register and store the overflow/carryout…", "description": "Multiply two signed integer inputs, add a third signed integer input, store the result into a 64-bit vector register and store the overflow/carryout into a scalar mask register.", "syntax": "v_mad_i64_i32", "operands": [], "dataTypes": [ "i32", "i64" ], "semantics": "{ D1.i1, D0.i64 } = 65'B(65'I(S0.i32) * 65'I(S1.i32) + 65'I(S2.i64))", "example": "v_mad_i64_i32 v[5:6], s6, s105, s105, s[6:7]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "In VOP3 the VCC destination may be an arbitrary SGPR-pair.", "sourcePdfPage": 349, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_mad_legacy_f16", "mnemonic": "v_mad_legacy_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAD LEGACY F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply add of FP16 values. Implements IEEE rules and non-standard rule for OPSEL.", "description": "Multiply add of FP16 values. Implements IEEE rules and non-standard rule for OPSEL.", "syntax": "v_mad_legacy_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "tmp = S0.f16 * S1.f16 + S2.f16;\nif OPSEL.u4[3] then\nD0 = { tmp.f16, D0[15 : 0] }\nelse\nD0 = { 16'0, tmp.f16 }\nendif", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "Supports round mode, exception flags, saturation. If OPSEL[3] is 0 Result is written to 16 LSBs of destination VGPR and hi 16 bits are written as 0 (this is different from V_MAD_F16). If OPSEL[3] is 1 Result is written to 16 MSBs of destination VGPR and lo 16 bits are preserved.", "sourcePdfPage": 350, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_mad_legacy_f32", "mnemonic": "v_mad_legacy_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAD LEGACY F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply and add single-precision values. Follows DX9 rules where 0.0 times anything produces 0.0.", "description": "Multiply and add single-precision values. Follows DX9 rules where 0.0 times anything produces 0.0.", "syntax": "v_mad_legacy_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_mad_legacy_i16", "mnemonic": "v_mad_legacy_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAD LEGACY I16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply add of signed short values. Has non-standard rule for OPSEL.", "description": "Multiply add of signed short values. Has non-standard rule for OPSEL.", "syntax": "v_mad_legacy_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "tmp = S0.i16 * S1.i16 + S2.i16;\nif OPSEL.u4[3] then\nD0 = { tmp.i16, D0[15 : 0] }\nelse\nD0 = { 16'0, tmp.i16 }\nendif", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "Supports saturation (signed 16-bit integer domain). If OPSEL[3] is 0 Result is written to 16 LSBs of destination VGPR and hi 16 bits are written as 0 (this is different from V_MAD_I16). If OPSEL[3] is 1 Result is written to 16 MSBs of destination VGPR and lo 16 bits are preserved.", "sourcePdfPage": 351, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_mad_legacy_u16", "mnemonic": "v_mad_legacy_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAD LEGACY U16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply add of unsigned short values. Has non-standard rule for OPSEL.", "description": "Multiply add of unsigned short values. Has non-standard rule for OPSEL.", "syntax": "v_mad_legacy_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "tmp = S0.u16 * S1.u16 + S2.u16;\nif OPSEL.u4[3] then\nD0 = { tmp.u16, D0[15 : 0] }\nelse\nD0 = { 16'0, tmp.u16 }\nendif", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "Supports saturation (unsigned 16-bit integer domain). If OPSEL[3] is 0 Result is written to 16 LSBs of destination VGPR and hi 16 bits are written as 0 (this is different from V_MAD_U16). If OPSEL[3] is 1 Result is written to 16 MSBs of destination VGPR and lo 16 bits are preserved.", "sourcePdfPage": 350, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_mad_mix_f32", "mnemonic": "v_mad_mix_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAD MIX F32", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Multiply two inputs and add a third input where the inputs are a mix of half-precision float and single- precision float values.", "description": "Multiply two inputs and add a third input where the inputs are a mix of half-precision float and single- precision float values. Store the result into a vector register.", "syntax": "v_mad_mix_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "Size and location of the three inputs are controlled by { OPSEL_HI[i], OPSEL[i] }: 0=src[31:0], 1=src[31:0],\n2=src[15:0], 3=src[31:16]. For MIX opcodes the NEG_HI instruction field acts as an absolute-value modifier\nfor the three inputs.\ndeclare in : 32'F[3];\ndeclare S : 32'B[3];\nfor i in 0 : 2 do\nif !OPSEL_HI.u3[i] then\nin[i] = S[i].f32\nelsif OPSEL.u3[i] then\nin[i] = f16_to_f32(S[i][31 : 16].f16)\nelse\nin[i] = f16_to_f32(S[i][15 : 0].f16)\nendif\nendfor;\nD0[31 : 0].f32 = in[0] * in[1] + in[2]", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 267, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_mad_mixhi_f16", "mnemonic": "v_mad_mixhi_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAD MIXHI F16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Multiply two inputs and add a third input where the inputs are a mix of half-precision float and single- precision float values.", "description": "Multiply two inputs and add a third input where the inputs are a mix of half-precision float and single- precision float values. Convert the result to a half-precision float. Store the result into the high bits of a vector register.", "syntax": "v_mad_mixhi_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "Size and location of the three inputs are controlled by { OPSEL_HI[i], OPSEL[i] }: 0=src[31:0], 1=src[31:0],\n2=src[15:0], 3=src[31:16]. For MIX opcodes the NEG_HI instruction field acts as an absolute-value modifier\nfor the three inputs.\ndeclare in : 32'F[3];\ndeclare S : 32'B[3];\nfor i in 0 : 2 do\nif !OPSEL_HI.u3[i] then\nin[i] = S[i].f32\nelsif OPSEL.u3[i] then\nin[i] = f16_to_f32(S[i][31 : 16].f16)\nelse\nin[i] = f16_to_f32(S[i][15 : 0].f16)\nendif\nendfor;\nD0[31 : 16].f16 = f32_to_f16(in[0] * in[1] + in[2])", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 268, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_mad_mixlo_f16", "mnemonic": "v_mad_mixlo_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAD MIXLO F16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Multiply two inputs and add a third input where the inputs are a mix of half-precision float and single- precision float values.", "description": "Multiply two inputs and add a third input where the inputs are a mix of half-precision float and single- precision float values. Convert the result to a half-precision float. Store the result into the low bits of a vector register.", "syntax": "v_mad_mixlo_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "Size and location of the three inputs are controlled by { OPSEL_HI[i], OPSEL[i] }: 0=src[31:0], 1=src[31:0],\n2=src[15:0], 3=src[31:16]. For MIX opcodes the NEG_HI instruction field acts as an absolute-value modifier\nfor the three inputs.\ndeclare in : 32'F[3];\ndeclare S : 32'B[3];\nfor i in 0 : 2 do\nif !OPSEL_HI.u3[i] then\nin[i] = S[i].f32\nelsif OPSEL.u3[i] then\nin[i] = f16_to_f32(S[i][31 : 16].f16)\nelse\nin[i] = f16_to_f32(S[i][15 : 0].f16)\nendif\nendfor;\nD0[15 : 0].f16 = f32_to_f16(in[0] * in[1] + in[2])", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 267, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_mad_nc_i64_i32", "mnemonic": "v_mad_nc_i64_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAD NC I64 I32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on i32/i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_mad_nc_i64_i32", "operands": [], "dataTypes": [ "i32", "i64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_mad_nc_u64_u32", "mnemonic": "v_mad_nc_u64_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAD NC U64 U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on u32/u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_mad_nc_u64_u32", "operands": [], "dataTypes": [ "u32", "u64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_mad_u16", "mnemonic": "v_mad_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAD U16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two unsigned 16-bit integer inputs, add an unsigned 16-bit integer value from a third input, and store the result into a vector register.", "description": "Multiply two unsigned 16-bit integer inputs, add an unsigned 16-bit integer value from a third input, and store the result into a vector register.", "syntax": "v_mad_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "D0.u16 = S0.u16 * S1.u16 + S2.u16", "example": "v_mad_u16 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Supports saturation (unsigned 16-bit integer domain). If OPSEL[3] is 0 the result is written to 16 LSBs of destination VGPR and the high 16 bits are preserved. If OPSEL[3] is 1 the result is written to 16 MSBs of destination VGPR and the low 16 bits are preserved.", "sourcePdfPage": 357, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_mad_u16_gfx9", "mnemonic": "v_mad_u16_gfx9", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAD U16 GFX9", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on u16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_mad_u16_gfx9", "operands": [], "dataTypes": [ "u16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_mad_u32", "mnemonic": "v_mad_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAD U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_mad_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_mad_u32_u16", "mnemonic": "v_mad_u32_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAD U32 U16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two unsigned 16-bit integer inputs in the unsigned 32-bit integer domain, add an unsigned 32-bit integer value from a third input, and store…", "description": "Multiply two unsigned 16-bit integer inputs in the unsigned 32-bit integer domain, add an unsigned 32-bit integer value from a third input, and store the result as an unsigned 32-bit integer into a vector register.", "syntax": "v_mad_u32_u16", "operands": [], "dataTypes": [ "u16", "u32" ], "semantics": "D0.u32 = 32'U(S0.u16) * 32'U(S1.u16) + S2.u32", "example": "v_mad_u32_u16 v5, v1, v2, v3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 353, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_mad_u32_u24", "mnemonic": "v_mad_u32_u24", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAD U32 U24", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two unsigned 24-bit integer inputs in the unsigned 32-bit integer domain, add a unsigned 32-bit integer value from a third input, and store…", "description": "Multiply two unsigned 24-bit integer inputs in the unsigned 32-bit integer domain, add a unsigned 32-bit integer value from a third input, and store the result as an unsigned 32-bit integer into a vector register.", "syntax": "v_mad_u32_u24", "operands": [], "dataTypes": [ "u32" ], "semantics": "D0.u32 = 32'U(S0.u24) * 32'U(S1.u24) + S2.u32", "example": "v_mad_u32_u24 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 336, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_mad_u64_u32", "mnemonic": "v_mad_u64_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAD U64 U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two unsigned integer inputs, add a third unsigned integer input, store the result into a 64-bit vector register and store the…", "description": "Multiply two unsigned integer inputs, add a third unsigned integer input, store the result into a 64-bit vector register and store the overflow/carryout into a scalar mask register.", "syntax": "v_mad_u64_u32", "operands": [], "dataTypes": [ "u32", "u64" ], "semantics": "{ D1.u1, D0.u64 } = 65'B(65'U(S0.u32) * 65'U(S1.u32) + 65'U(S2.u64))", "example": "v_mad_u64_u32 v[5:6], s6, s105, s105, s[6:7]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "In VOP3 the VCC destination may be an arbitrary SGPR-pair.", "sourcePdfPage": 349, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_madak_f16", "mnemonic": "v_madak_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MADAK F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two floating point inputs and add a literal constant, and store the result into a vector register. Implements IEEE rules.", "description": "Multiply two floating point inputs and add a literal constant, and store the result into a vector register. Implements IEEE rules.", "syntax": "v_madak_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "tmp = S0.f16 * S1.f16 + SIMM16.f16;\nD0 = { 16'0, tmp.f16 }", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "This opcode cannot use the VOP3 encoding and cannot use input/output modifiers. Supports round mode, exception flags, saturation.", "sourcePdfPage": 179, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_madak_f32", "mnemonic": "v_madak_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MADAK F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two floating point inputs and add a literal constant, and store the result into a vector register.", "description": "Multiply two floating point inputs and add a literal constant, and store the result into a vector register.", "syntax": "v_madak_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_madmk_f16", "mnemonic": "v_madmk_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MADMK F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply a floating point input with a literal constant and add a second floating point input, and store the result into a vector register.", "description": "Multiply a floating point input with a literal constant and add a second floating point input, and store the result into a vector register. Implements IEEE rules.", "syntax": "v_madmk_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "tmp = S0.f16 * SIMM16.f16 + S1.f16;\nD0 = { 16'0, tmp.f16 }", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "This opcode cannot use the VOP3 encoding and cannot use input/output modifiers. Supports round mode, exception flags, saturation.", "sourcePdfPage": 178, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_madmk_f32", "mnemonic": "v_madmk_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MADMK F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply a floating point input with a literal constant and add a second floating point input, and store the result into a vector register.", "description": "Multiply a floating point input with a literal constant and add a second floating point input, and store the result into a vector register.", "syntax": "v_madmk_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_max3_f16", "mnemonic": "v_max3_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAX3 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the maximum of three half-precision float inputs and store the selected value into a vector register.", "description": "Select the maximum of three half-precision float inputs and store the selected value into a vector register.", "syntax": "v_max3_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.f16 = v_max_f16(v_max_f16(S0.f16, S1.f16), S2.f16)", "example": "v_max3_f16 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 354, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_max3_f32", "mnemonic": "v_max3_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAX3 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the maximum of three single-precision float inputs and store the selected value into a vector register.", "description": "Select the maximum of three single-precision float inputs and store the selected value into a vector register.", "syntax": "v_max3_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.f32 = v_max_f32(v_max_f32(S0.f32, S1.f32), S2.f32)", "example": "v_max3_f32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 340, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_max3_i16", "mnemonic": "v_max3_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAX3 I16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the maximum of three signed 16-bit integer inputs and store the selected value into a vector register.", "description": "Select the maximum of three signed 16-bit integer inputs and store the selected value into a vector register.", "syntax": "v_max3_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "D0.i16 = v_max_i16(v_max_i16(S0.i16, S1.i16), S2.i16)", "example": "v_max3_i16 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 354, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_max3_i32", "mnemonic": "v_max3_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAX3 I32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the maximum of three signed 32-bit integer inputs and store the selected value into a vector register.", "description": "Select the maximum of three signed 32-bit integer inputs and store the selected value into a vector register.", "syntax": "v_max3_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "D0.i32 = v_max_i32(v_max_i32(S0.i32, S1.i32), S2.i32)", "example": "v_max3_i32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 341, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_max3_num_f16", "mnemonic": "v_max3_num_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAX3 NUM F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the IEEE maximumNumber() of three half-precision float inputs and store the selected value into a vector register.", "description": "Select the IEEE maximumNumber() of three half-precision float inputs and store the selected value into a vector register.", "syntax": "v_max3_num_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_max3_num_f32", "mnemonic": "v_max3_num_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAX3 NUM F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the IEEE maximumNumber() of three single-precision float inputs and store the selected value into a vector register.", "description": "Select the IEEE maximumNumber() of three single-precision float inputs and store the selected value into a vector register.", "syntax": "v_max3_num_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_max3_u16", "mnemonic": "v_max3_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAX3 U16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the maximum of three unsigned 16-bit integer inputs and store the selected value into a vector register.", "description": "Select the maximum of three unsigned 16-bit integer inputs and store the selected value into a vector register.", "syntax": "v_max3_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "D0.u16 = v_max_u16(v_max_u16(S0.u16, S1.u16), S2.u16)", "example": "v_max3_u16 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 355, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_max3_u32", "mnemonic": "v_max3_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAX3 U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the maximum of three unsigned 32-bit integer inputs and store the selected value into a vector register.", "description": "Select the maximum of three unsigned 32-bit integer inputs and store the selected value into a vector register.", "syntax": "v_max3_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "D0.u32 = v_max_u32(v_max_u32(S0.u32, S1.u32), S2.u32)", "example": "v_max3_u32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 341, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_max_bf16", "mnemonic": "v_max_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAX BF16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_max_bf16", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_max_f16", "mnemonic": "v_max_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAX F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the maximum of two half-precision float inputs and store the result into a vector register.", "description": "Select the maximum of two half-precision float inputs and store the result into a vector register.", "syntax": "v_max_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "if (WAVE_MODE.IEEE && isSignalNAN(64'F(S0.f16))) then\nD0.f16 = 16'F(cvtToQuietNAN(64'F(S0.f16)))\nelsif (WAVE_MODE.IEEE && isSignalNAN(64'F(S1.f16))) then\nD0.f16 = 16'F(cvtToQuietNAN(64'F(S1.f16)))\nelsif isNAN(64'F(S0.f16)) then\nD0.f16 = S1.f16\nelsif isNAN(64'F(S1.f16)) then\nD0.f16 = S0.f16\nelsif ((64'F(S0.f16) == +0.0) && (64'F(S1.f16) == -0.0)) then\nD0.f16 = S0.f16\nelsif ((64'F(S0.f16) == -0.0) && (64'F(S1.f16) == +0.0)) then\nD0.f16 = S1.f16\nelsif WAVE_MODE.IEEE then\nD0.f16 = S0.f16 >= S1.f16 ? S0.f16 : S1.f16\nelse\nD0.f16 = S0.f16 > S1.f16 ? S0.f16 : S1.f16\nendif", "example": "v_max_f16 v5, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "IEEE compliant. Supports denormals, round mode, exception flags, saturation.", "sourcePdfPage": 181, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_max_f32", "mnemonic": "v_max_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAX F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the maximum of two single-precision float inputs and store the result into a vector register.", "description": "Select the maximum of two single-precision float inputs and store the result into a vector register.", "syntax": "v_max_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "if (WAVE_MODE.IEEE && isSignalNAN(64'F(S0.f32))) then\nD0.f32 = 32'F(cvtToQuietNAN(64'F(S0.f32)))\nelsif (WAVE_MODE.IEEE && isSignalNAN(64'F(S1.f32))) then\nD0.f32 = 32'F(cvtToQuietNAN(64'F(S1.f32)))\nelsif isNAN(64'F(S0.f32)) then\nD0.f32 = S1.f32\nelsif isNAN(64'F(S1.f32)) then\nD0.f32 = S0.f32\nelsif ((64'F(S0.f32) == +0.0) && (64'F(S1.f32) == -0.0)) then\nD0.f32 = S0.f32\nelsif ((64'F(S0.f32) == -0.0) && (64'F(S1.f32) == +0.0)) then\nD0.f32 = S1.f32\nelsif WAVE_MODE.IEEE then\nD0.f32 = S0.f32 >= S1.f32 ? S0.f32 : S1.f32\nelse\nD0.f32 = S0.f32 > S1.f32 ? S0.f32 : S1.f32\nendif", "example": "v_max_f32 v5, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 172, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_max_f64", "mnemonic": "v_max_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAX F64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the maximum of two double-precision float inputs and store the selected value into a vector register.", "description": "Select the maximum of two double-precision float inputs and store the selected value into a vector register.", "syntax": "v_max_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": "v_max_f64 v[5:6], -1, -1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_max_i16", "mnemonic": "v_max_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAX I16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the maximum of two signed 16-bit integer inputs and store the selected value into a vector register.", "description": "Select the maximum of two signed 16-bit integer inputs and store the selected value into a vector register.", "syntax": "v_max_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "D0.i16 = S0.i16 >= S1.i16 ? S0.i16 : S1.i16", "example": "v_max_i16 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 182, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_max_i32", "mnemonic": "v_max_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAX I32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the maximum of two signed 32-bit integer inputs and store the selected value into a vector register.", "description": "Select the maximum of two signed 32-bit integer inputs and store the selected value into a vector register.", "syntax": "v_max_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "D0.i32 = S0.i32 >= S1.i32 ? S0.i32 : S1.i32", "example": "v_max_i32 v5, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 172, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_max_i64", "mnemonic": "v_max_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAX I64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_max_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_max_legacy_f32", "mnemonic": "v_max_legacy_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAX LEGACY F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP2 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_max_legacy_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_max_num_f16", "mnemonic": "v_max_num_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAX NUM F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the IEEE maximumNumber() of two half-precision float inputs and store the selected value into a vector register.", "description": "Select the IEEE maximumNumber() of two half-precision float inputs and store the selected value into a vector register.", "syntax": "v_max_num_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": "v_max_num_f16 v255, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_max_num_f32", "mnemonic": "v_max_num_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAX NUM F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the IEEE maximumNumber() of two single-precision float inputs and store the selected value into a vector register.", "description": "Select the IEEE maximumNumber() of two single-precision float inputs and store the selected value into a vector register.", "syntax": "v_max_num_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_max_num_f64", "mnemonic": "v_max_num_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAX NUM F64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the IEEE maximumNumber() of two double-precision float inputs and store the selected value into a vector register.", "description": "Select the IEEE maximumNumber() of two double-precision float inputs and store the selected value into a vector register.", "syntax": "v_max_num_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_max_u16", "mnemonic": "v_max_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAX U16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the maximum of two unsigned 16-bit integer inputs and store the selected value into a vector register.", "description": "Select the maximum of two unsigned 16-bit integer inputs and store the selected value into a vector register.", "syntax": "v_max_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "D0.u16 = S0.u16 >= S1.u16 ? S0.u16 : S1.u16", "example": "v_max_u16 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 182, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_max_u32", "mnemonic": "v_max_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAX U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the maximum of two unsigned 32-bit integer inputs and store the selected value into a vector register.", "description": "Select the maximum of two unsigned 32-bit integer inputs and store the selected value into a vector register.", "syntax": "v_max_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "D0.u32 = S0.u32 >= S1.u32 ? S0.u32 : S1.u32", "example": "v_max_u32 v5, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 173, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_max_u64", "mnemonic": "v_max_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAX U64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_max_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_maximum3_f16", "mnemonic": "v_maximum3_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAXIMUM3 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the IEEE maximum() of three half-precision float inputs and store the selected value into a vector register.", "description": "Select the IEEE maximum() of three half-precision float inputs and store the selected value into a vector register.", "syntax": "v_maximum3_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_maximum3_f32", "mnemonic": "v_maximum3_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAXIMUM3 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the IEEE maximum() of three single-precision float inputs and store the result into a vector register.", "description": "Select the IEEE maximum() of three single-precision float inputs and store the result into a vector register.", "syntax": "v_maximum3_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_maximum_f16", "mnemonic": "v_maximum_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAXIMUM F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the IEEE maximum() of two half-precision float inputs and store the selected value into a vector register.", "description": "Select the IEEE maximum() of two half-precision float inputs and store the selected value into a vector register.", "syntax": "v_maximum_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_maximum_f32", "mnemonic": "v_maximum_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAXIMUM F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the IEEE maximum() of two single-precision float inputs and store the selected value into a vector register.", "description": "Select the IEEE maximum() of two single-precision float inputs and store the selected value into a vector register.", "syntax": "v_maximum_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_maximum_f64", "mnemonic": "v_maximum_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAXIMUM F64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the IEEE maximum() of two double-precision float inputs and store the selected value into a vector register.", "description": "Select the IEEE maximum() of two double-precision float inputs and store the selected value into a vector register.", "syntax": "v_maximum_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_maximumminimum_f16", "mnemonic": "v_maximumminimum_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAXIMUMMINIMUM F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the IEEE maximum() of the first two half-precision float inputs and then select the IEEE minimum() of that result and third half-precision…", "description": "Select the IEEE maximum() of the first two half-precision float inputs and then select the IEEE minimum() of that result and third half-precision float input. Store the final result into a vector register.", "syntax": "v_maximumminimum_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_maximumminimum_f32", "mnemonic": "v_maximumminimum_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAXIMUMMINIMUM F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the IEEE maximum() of the first two single-precision float inputs and then select the IEEE minimum() of that result and third single-precision…", "description": "Select the IEEE maximum() of the first two single-precision float inputs and then select the IEEE minimum() of that result and third single-precision float input. Store the final result into a vector register.", "syntax": "v_maximumminimum_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_maxmin_f16", "mnemonic": "v_maxmin_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAXMIN F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the maximum of the first two half-precision float inputs and then select the minimum of that result and third half-precision float input.", "description": "Select the maximum of the first two half-precision float inputs and then select the minimum of that result and third half-precision float input. Store the final result into a vector register.", "syntax": "v_maxmin_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": "v_maxmin_f16 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_maxmin_f32", "mnemonic": "v_maxmin_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAXMIN F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the maximum of the first two single-precision float inputs and then select the minimum of that result and third single-precision float input.", "description": "Select the maximum of the first two single-precision float inputs and then select the minimum of that result and third single-precision float input. Store the final result into a vector register.", "syntax": "v_maxmin_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": "v_maxmin_f32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_maxmin_i32", "mnemonic": "v_maxmin_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAXMIN I32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the maximum of the first two signed 32-bit integer inputs and then select the minimum of that result and third signed 32-bit integer input.", "description": "Select the maximum of the first two signed 32-bit integer inputs and then select the minimum of that result and third signed 32-bit integer input. Store the final result into a vector register.", "syntax": "v_maxmin_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "", "example": "v_maxmin_i32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_maxmin_num_f16", "mnemonic": "v_maxmin_num_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAXMIN NUM F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the IEEE maximumNumber() of the first two half-precision float inputs and then select the IEEE minimumNumber() of that result and third…", "description": "Select the IEEE maximumNumber() of the first two half-precision float inputs and then select the IEEE minimumNumber() of that result and third half-precision float input. Store the final result into a vector register.", "syntax": "v_maxmin_num_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_maxmin_num_f32", "mnemonic": "v_maxmin_num_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAXMIN NUM F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the IEEE maximumNumber() of the first two single-precision float inputs and then select the IEEE minimumNumber() of that result and third…", "description": "Select the IEEE maximumNumber() of the first two single-precision float inputs and then select the IEEE minimumNumber() of that result and third single-precision float input. Store the final result into a vector register.", "syntax": "v_maxmin_num_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_maxmin_u32", "mnemonic": "v_maxmin_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MAXMIN U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the maximum of the first two unsigned 32-bit integer inputs and then select the minimum of that result and third unsigned 32-bit integer input.", "description": "Select the maximum of the first two unsigned 32-bit integer inputs and then select the minimum of that result and third unsigned 32-bit integer input. Store the final result into a vector register.", "syntax": "v_maxmin_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": "v_maxmin_u32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_mbcnt_hi_u32_b32", "mnemonic": "v_mbcnt_hi_u32_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MBCNT HI U32 B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "For each lane 32 <= N < 64, examine the N least significant bits of the first input and count how many of those bits are \"1\".", "description": "For each lane 32 <= N < 64, examine the N least significant bits of the first input and count how many of those bits are \"1\". For lane positions 0 <= N < 32 no bits are examined and the count is zero. Add this count to the value in the second input and store the result into a vector register.", "syntax": "v_mbcnt_hi_u32_b32", "operands": [], "dataTypes": [ "b32", "u32" ], "semantics": "", "example": "v_mbcnt_hi_u32_b32 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_mbcnt_lo_u32_b32", "mnemonic": "v_mbcnt_lo_u32_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MBCNT LO U32 B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "For each lane 0 <= N < 32, examine the N least significant bits of the first input and count how many of those bits are \"1\".", "description": "For each lane 0 <= N < 32, examine the N least significant bits of the first input and count how many of those bits are \"1\". For each lane 32 <= N < 64, all \"1\" bits in the first input are counted. Add this count to the value in the second input and store the result into a vector register.", "syntax": "v_mbcnt_lo_u32_b32", "operands": [], "dataTypes": [ "b32", "u32" ], "semantics": "", "example": "v_mbcnt_lo_u32_b32 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_med3_f16", "mnemonic": "v_med3_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MED3 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the median of three half-precision float values and store the selected value into a vector register.", "description": "Select the median of three half-precision float values and store the selected value into a vector register.", "syntax": "v_med3_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "if (isNAN(64'F(S0.f16)) || isNAN(64'F(S1.f16)) || isNAN(64'F(S2.f16))) then\nD0.f16 = v_min3_f16(S0.f16, S1.f16, S2.f16)\nelsif v_max3_f16(S0.f16, S1.f16, S2.f16) == S0.f16 then\nD0.f16 = v_max_f16(S1.f16, S2.f16)\nelsif v_max3_f16(S0.f16, S1.f16, S2.f16) == S1.f16 then\nD0.f16 = v_max_f16(S0.f16, S2.f16)\nelse\nD0.f16 = v_max_f16(S0.f16, S1.f16)\nendif", "example": "v_med3_f16 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 355, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_med3_f32", "mnemonic": "v_med3_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MED3 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the median of three single-precision float values and store the selected value into a vector register.", "description": "Select the median of three single-precision float values and store the selected value into a vector register.", "syntax": "v_med3_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "if (isNAN(64'F(S0.f32)) || isNAN(64'F(S1.f32)) || isNAN(64'F(S2.f32))) then\nD0.f32 = v_min3_f32(S0.f32, S1.f32, S2.f32)\nelsif v_max3_f32(S0.f32, S1.f32, S2.f32) == S0.f32 then\nD0.f32 = v_max_f32(S1.f32, S2.f32)\nelsif v_max3_f32(S0.f32, S1.f32, S2.f32) == S1.f32 then\nD0.f32 = v_max_f32(S0.f32, S2.f32)\nelse\nD0.f32 = v_max_f32(S0.f32, S1.f32)\nendif", "example": "v_med3_f32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 341, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_med3_i16", "mnemonic": "v_med3_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MED3 I16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the median of three signed 16-bit integer values and store the selected value into a vector register.", "description": "Select the median of three signed 16-bit integer values and store the selected value into a vector register.", "syntax": "v_med3_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "if v_max3_i16(S0.i16, S1.i16, S2.i16) == S0.i16 then\nD0.i16 = v_max_i16(S1.i16, S2.i16)\nelsif v_max3_i16(S0.i16, S1.i16, S2.i16) == S1.i16 then\nD0.i16 = v_max_i16(S0.i16, S2.i16)\nelse\nD0.i16 = v_max_i16(S0.i16, S1.i16)\nendif", "example": "v_med3_i16 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 355, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_med3_i32", "mnemonic": "v_med3_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MED3 I32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the median of three signed 32-bit integer values and store the selected value into a vector register.", "description": "Select the median of three signed 32-bit integer values and store the selected value into a vector register.", "syntax": "v_med3_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "if v_max3_i32(S0.i32, S1.i32, S2.i32) == S0.i32 then\nD0.i32 = v_max_i32(S1.i32, S2.i32)\nelsif v_max3_i32(S0.i32, S1.i32, S2.i32) == S1.i32 then\nD0.i32 = v_max_i32(S0.i32, S2.i32)\nelse\nD0.i32 = v_max_i32(S0.i32, S1.i32)\nendif", "example": "v_med3_i32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 341, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_med3_num_f16", "mnemonic": "v_med3_num_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MED3 NUM F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the median of three half-precision float inputs and store the selected value into a vector register.", "description": "Select the median of three half-precision float inputs and store the selected value into a vector register.", "syntax": "v_med3_num_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_med3_num_f32", "mnemonic": "v_med3_num_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MED3 NUM F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the median of three single-precision float inputs and store the selected value into a vector register.", "description": "Select the median of three single-precision float inputs and store the selected value into a vector register.", "syntax": "v_med3_num_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_med3_u16", "mnemonic": "v_med3_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MED3 U16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the median of three unsigned 16-bit integer values and store the selected value into a vector register.", "description": "Select the median of three unsigned 16-bit integer values and store the selected value into a vector register.", "syntax": "v_med3_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "if v_max3_u16(S0.u16, S1.u16, S2.u16) == S0.u16 then\nD0.u16 = v_max_u16(S1.u16, S2.u16)\nelsif v_max3_u16(S0.u16, S1.u16, S2.u16) == S1.u16 then\nD0.u16 = v_max_u16(S0.u16, S2.u16)\nelse\nD0.u16 = v_max_u16(S0.u16, S1.u16)\nendif", "example": "v_med3_u16 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 355, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_med3_u32", "mnemonic": "v_med3_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MED3 U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the median of three unsigned 32-bit integer values and store the selected value into a vector register.", "description": "Select the median of three unsigned 32-bit integer values and store the selected value into a vector register.", "syntax": "v_med3_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "if v_max3_u32(S0.u32, S1.u32, S2.u32) == S0.u32 then\nD0.u32 = v_max_u32(S1.u32, S2.u32)\nelsif v_max3_u32(S0.u32, S1.u32, S2.u32) == S1.u32 then\nD0.u32 = v_max_u32(S0.u32, S2.u32)\nelse\nD0.u32 = v_max_u32(S0.u32, S1.u32)\nendif", "example": "v_med3_u32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 341, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_mfma_f32_16x16x128_f8f6f4", "mnemonic": "v_mfma_f32_16x16x128_f8f6f4", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA F32 16X16X128 F8F6F4", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 16x128 matrix in the first input by the 128x16 matrix in the second input and add the 16x16 matrix in the third input using fused…", "description": "Multiply the 16x128 matrix in the first input by the 128x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.", "syntax": "v_mfma_f32_16x16x128_f8f6f4", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_mfma_f32_16x16x16_bf16", "mnemonic": "v_mfma_f32_16x16x16_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA F32 16X16X16 BF16", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 16x16 matrix in the first input by the 16x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply…", "description": "Multiply the 16x16 matrix in the first input by the 16x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.", "syntax": "v_mfma_f32_16x16x16_bf16", "operands": [], "dataTypes": [ "f32" ], "semantics": "D = A (16x16) * B (16x16) + C (16x16)\nEach operand contains a single matrix whose elements are distributed across all lanes of the wave. A single\nmatrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher\nperformance.\nMatrices A and B are BF16 float format. Matrices C and D are single-precision float format.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx942" ], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 4 passes.", "sourcePdfPage": 280, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_mfma_f32_16x16x16_f16", "mnemonic": "v_mfma_f32_16x16x16_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA F32 16X16X16 F16", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 16x16 matrix in the first input by the 16x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply…", "description": "Multiply the 16x16 matrix in the first input by the 16x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.", "syntax": "v_mfma_f32_16x16x16_f16", "operands": [], "dataTypes": [ "f16", "f32" ], "semantics": "D = A (16x16) * B (16x16) + C (16x16)\nEach operand contains a single matrix whose elements are distributed across all lanes of the wave. A single\nmatrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher\nperformance.\nMatrices A and B are half-precision float format. Matrices C and D are single-precision float format.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 4 passes.", "sourcePdfPage": 276, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_mfma_f32_16x16x16f16", "mnemonic": "v_mfma_f32_16x16x16f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA F32 16X16X16F16", "category": "Matrix Core Operations", "instructionClass": "matrix", "summary": "Matrix-fused-multiply-add: cooperative 16x16x16 matrix-multiply-accumulate on matrix-core hardware, fp16 inputs, fp32 accumulate.", "description": "Multiply the 16x16 matrix in the first input by the 16x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.", "syntax": "v_mfma_f32_16x16x16f16 D, A, B, C", "operands": [ { "name": "D", "desc": "Accumulator fragment (destination, VGPR range)" }, { "name": "A", "desc": "Matrix A fragment (VGPR range)" }, { "name": "B", "desc": "Matrix B fragment (VGPR range)" }, { "name": "C", "desc": "Accumulator fragment (input, VGPR range)" } ], "dataTypes": [ "f32" ], "semantics": "D = A * B + C for a 16x16x16 tile, computed cooperatively across the wavefront; operand fragments are distributed across lanes per a hardware-defined layout specific to the MFMA family and target.", "example": "v_mfma_f32_16x16x16f16 a[0:3], v[0:3], v[4:7], a[0:3] // 16x16x16 MFMA accumulate", "exampleSource": null, "encoding": { "format": "VOP3P-MAI", "widthBits": 32 }, "executionUnit": "Matrix Core Unit", "registerClasses": [ "VGPR", "AGPR" ], "memorySegment": null, "supportedTargets": [ "gfx942" ], "unsupportedTargets": [ "gfx1100" ], "architecturalNotes": "Matrix-core (MFMA) instructions are a CDNA-family feature; gfx1100 (RDNA3) does not implement this specific MFMA variant - see the AMDGPU landing page's target compatibility notes.", "sourcePdfPage": null, "sourceIds": [ "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_mfma_f32_16x16x1_4b_f32", "mnemonic": "v_mfma_f32_16x16x1_4b_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA F32 16X16X1 4B F32", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 16x1 matrix in the first input by the 1x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply…", "description": "Multiply the 16x1 matrix in the first input by the 1x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.", "syntax": "v_mfma_f32_16x16x1_4b_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D = A (16x1) * B (1x16) + C (16x16)\nThis instruction performs 4 matrix multiplies. Each operand contains 4 matrices back to back, and each matrix\nhas elements distributed across all lanes of the wave. Each matrix multiple is computed and the row-column\ndot products are distributed across the vector ALU for higher performance. The result matrices are stored\nback-to-back in the destination vector registers.\nMatrices A and B are single-precision float format. Matrices C and D are single-precision float format.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 8 passes.", "sourcePdfPage": 273, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_mfma_f32_16x16x32_bf16", "mnemonic": "v_mfma_f32_16x16x32_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA F32 16X16X32 BF16", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 16x32 matrix in the first input by the 32x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply…", "description": "Multiply the 16x32 matrix in the first input by the 32x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.", "syntax": "v_mfma_f32_16x16x32_bf16", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_mfma_f32_16x16x32_f16", "mnemonic": "v_mfma_f32_16x16x32_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA F32 16X16X32 F16", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 16x32 matrix in the first input by the 32x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply…", "description": "Multiply the 16x32 matrix in the first input by the 32x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.", "syntax": "v_mfma_f32_16x16x32_f16", "operands": [], "dataTypes": [ "f16", "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_mfma_f32_16x16x4_4b_bf16", "mnemonic": "v_mfma_f32_16x16x4_4b_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA F32 16X16X4 4B BF16", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 16x4 matrix in the first input by the 4x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply…", "description": "Multiply the 16x4 matrix in the first input by the 4x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.", "syntax": "v_mfma_f32_16x16x4_4b_bf16", "operands": [], "dataTypes": [ "f32" ], "semantics": "D = A (16x4) * B (4x16) + C (16x16)\nThis instruction performs 4 matrix multiplies. Each operand contains 4 matrices back to back, and each matrix\nhas elements distributed across all lanes of the wave. Each matrix multiple is computed and the row-column\ndot products are distributed across the vector ALU for higher performance. The result matrices are stored\nback-to-back in the destination vector registers.\nMatrices A and B are BF16 float format. Matrices C and D are single-precision float format.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx942" ], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 8 passes.", "sourcePdfPage": 279, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_mfma_f32_16x16x4_4b_f16", "mnemonic": "v_mfma_f32_16x16x4_4b_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA F32 16X16X4 4B F16", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 16x4 matrix in the first input by the 4x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply…", "description": "Multiply the 16x4 matrix in the first input by the 4x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.", "syntax": "v_mfma_f32_16x16x4_4b_f16", "operands": [], "dataTypes": [ "f16", "f32" ], "semantics": "D = A (16x4) * B (4x16) + C (16x16)\nThis instruction performs 4 matrix multiplies. Each operand contains 4 matrices back to back, and each matrix\nhas elements distributed across all lanes of the wave. Each matrix multiple is computed and the row-column\ndot products are distributed across the vector ALU for higher performance. The result matrices are stored\nback-to-back in the destination vector registers.\nMatrices A and B are half-precision float format. Matrices C and D are single-precision float format.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 8 passes.", "sourcePdfPage": 275, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_mfma_f32_16x16x4_f32", "mnemonic": "v_mfma_f32_16x16x4_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA F32 16X16X4 F32", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 16x4 matrix in the first input by the 4x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply…", "description": "Multiply the 16x4 matrix in the first input by the 4x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.", "syntax": "v_mfma_f32_16x16x4_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D = A (16x4) * B (4x16) + C (16x16)\nEach operand contains a single matrix whose elements are distributed across all lanes of the wave. A single\nmatrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher\nperformance.\nMatrices A and B are single-precision float format. Matrices C and D are single-precision float format.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 8 passes.", "sourcePdfPage": 274, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_mfma_f32_16x16x8_xf32", "mnemonic": "v_mfma_f32_16x16x8_xf32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA F32 16X16X8 XF32", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 16x8 matrix in the first input by the 8x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply…", "description": "Multiply the 16x8 matrix in the first input by the 8x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.", "syntax": "v_mfma_f32_16x16x8_xf32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D = A (16x8) * B (8x16) + C (16x16)\nEach operand contains a single matrix whose elements are distributed across all lanes of the wave. A single\nmatrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher\nperformance.\nMatrices A and B are single-precision float format. Matrices C and D are single-precision float format. XF32 is a\nFP32 operation with FP32 inputs and outputs but implemented at reduced intermediate precision where\nmantissa is truncated to 10 bits (not including leading 1 for non-zero values) and results are accumulated into\nFP32 value with 23 bit mantissa.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx942" ], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 4 passes.", "sourcePdfPage": 272, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_mfma_f32_32x32x16_bf16", "mnemonic": "v_mfma_f32_32x32x16_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA F32 32X32X16 BF16", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 32x16 matrix in the first input by the 16x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply…", "description": "Multiply the 32x16 matrix in the first input by the 16x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.", "syntax": "v_mfma_f32_32x32x16_bf16", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_mfma_f32_32x32x16_f16", "mnemonic": "v_mfma_f32_32x32x16_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA F32 32X32X16 F16", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 32x16 matrix in the first input by the 16x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply…", "description": "Multiply the 32x16 matrix in the first input by the 16x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.", "syntax": "v_mfma_f32_32x32x16_f16", "operands": [], "dataTypes": [ "f16", "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_mfma_f32_32x32x1_2b_f32", "mnemonic": "v_mfma_f32_32x32x1_2b_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA F32 32X32X1 2B F32", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 32x1 matrix in the first input by the 1x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply…", "description": "Multiply the 32x1 matrix in the first input by the 1x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.", "syntax": "v_mfma_f32_32x32x1_2b_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D = A (32x1) * B (1x32) + C (32x32)\nThis instruction performs 2 matrix multiplies. Each operand contains 2 matrices back to back, and each matrix\nhas elements distributed across all lanes of the wave. Each matrix multiple is computed and the row-column\ndot products are distributed across the vector ALU for higher performance. The result matrices are stored\nback-to-back in the destination vector registers.\nMatrices A and B are single-precision float format. Matrices C and D are single-precision float format.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 16 passes.", "sourcePdfPage": 273, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_mfma_f32_32x32x2_f32", "mnemonic": "v_mfma_f32_32x32x2_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA F32 32X32X2 F32", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 32x2 matrix in the first input by the 2x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply…", "description": "Multiply the 32x2 matrix in the first input by the 2x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.", "syntax": "v_mfma_f32_32x32x2_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D = A (32x2) * B (2x32) + C (32x32)\nEach operand contains a single matrix whose elements are distributed across all lanes of the wave. A single\nmatrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher\nperformance.\nMatrices A and B are single-precision float format. Matrices C and D are single-precision float format.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 16 passes.", "sourcePdfPage": 274, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_mfma_f32_32x32x4_2b_bf16", "mnemonic": "v_mfma_f32_32x32x4_2b_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA F32 32X32X4 2B BF16", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 32x4 matrix in the first input by the 4x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply…", "description": "Multiply the 32x4 matrix in the first input by the 4x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.", "syntax": "v_mfma_f32_32x32x4_2b_bf16", "operands": [], "dataTypes": [ "f32" ], "semantics": "D = A (32x4) * B (4x32) + C (32x32)\nThis instruction performs 2 matrix multiplies. Each operand contains 2 matrices back to back, and each matrix\nhas elements distributed across all lanes of the wave. Each matrix multiple is computed and the row-column\ndot products are distributed across the vector ALU for higher performance. The result matrices are stored\nback-to-back in the destination vector registers.\nMatrices A and B are BF16 float format. Matrices C and D are single-precision float format.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx942" ], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 16 passes.", "sourcePdfPage": 279, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_mfma_f32_32x32x4_2b_f16", "mnemonic": "v_mfma_f32_32x32x4_2b_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA F32 32X32X4 2B F16", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 32x4 matrix in the first input by the 4x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply…", "description": "Multiply the 32x4 matrix in the first input by the 4x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.", "syntax": "v_mfma_f32_32x32x4_2b_f16", "operands": [], "dataTypes": [ "f16", "f32" ], "semantics": "D = A (32x4) * B (4x32) + C (32x32)\nThis instruction performs 2 matrix multiplies. Each operand contains 2 matrices back to back, and each matrix\nhas elements distributed across all lanes of the wave. Each matrix multiple is computed and the row-column\ndot products are distributed across the vector ALU for higher performance. The result matrices are stored\nback-to-back in the destination vector registers.\nMatrices A and B are half-precision float format. Matrices C and D are single-precision float format.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 16 passes.", "sourcePdfPage": 275, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_mfma_f32_32x32x4_xf32", "mnemonic": "v_mfma_f32_32x32x4_xf32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA F32 32X32X4 XF32", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 32x4 matrix in the first input by the 4x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply…", "description": "Multiply the 32x4 matrix in the first input by the 4x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.", "syntax": "v_mfma_f32_32x32x4_xf32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D = A (32x4) * B (4x32) + C (32x32)\nEach operand contains a single matrix whose elements are distributed across all lanes of the wave. A single\nmatrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher\nperformance.\nMatrices A and B are single-precision float format. Matrices C and D are single-precision float format.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx942" ], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 8 passes.", "sourcePdfPage": 272, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_mfma_f32_32x32x64_f8f6f4", "mnemonic": "v_mfma_f32_32x32x64_f8f6f4", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA F32 32X32X64 F8F6F4", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 32x64 matrix in the first input by the 64x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply…", "description": "Multiply the 32x64 matrix in the first input by the 64x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.", "syntax": "v_mfma_f32_32x32x64_f8f6f4", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_mfma_f32_32x32x8_bf16", "mnemonic": "v_mfma_f32_32x32x8_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA F32 32X32X8 BF16", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 32x8 matrix in the first input by the 8x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply…", "description": "Multiply the 32x8 matrix in the first input by the 8x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.", "syntax": "v_mfma_f32_32x32x8_bf16", "operands": [], "dataTypes": [ "f32" ], "semantics": "D = A (32x8) * B (8x32) + C (32x32)\nEach operand contains a single matrix whose elements are distributed across all lanes of the wave. A single\nmatrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher\nperformance.\nMatrices A and B are BF16 float format. Matrices C and D are single-precision float format.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx942" ], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 8 passes.", "sourcePdfPage": 280, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_mfma_f32_32x32x8_f16", "mnemonic": "v_mfma_f32_32x32x8_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA F32 32X32X8 F16", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 32x8 matrix in the first input by the 8x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply…", "description": "Multiply the 32x8 matrix in the first input by the 8x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.", "syntax": "v_mfma_f32_32x32x8_f16", "operands": [], "dataTypes": [ "f16", "f32" ], "semantics": "D = A (32x8) * B (8x32) + C (32x32)\nEach operand contains a single matrix whose elements are distributed across all lanes of the wave. A single\nmatrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher\nperformance.\nMatrices A and B are half-precision float format. Matrices C and D are single-precision float format.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 8 passes.", "sourcePdfPage": 276, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_mfma_f32_4x4x1_16b_f32", "mnemonic": "v_mfma_f32_4x4x1_16b_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA F32 4X4X1 16B F32", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 4x1 matrix in the first input by the 1x4 matrix in the second input and add the 4x4 matrix in the third input using fused multiply add.", "description": "Multiply the 4x1 matrix in the first input by the 1x4 matrix in the second input and add the 4x4 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.", "syntax": "v_mfma_f32_4x4x1_16b_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D = A (4x1) * B (1x4) + C (4x4)\nThis instruction performs 16 matrix multiplies. Each operand contains 16 matrices back to back, and each\nmatrix has elements distributed across all lanes of the wave. Each matrix multiple is computed and the row-column dot products are distributed across the vector ALU for higher performance. The result matrices are\nstored back-to-back in the destination vector registers.\nMatrices A and B are single-precision float format. Matrices C and D are single-precision float format.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 2 passes.", "sourcePdfPage": 273, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_mfma_f32_4x4x4_16b_bf16", "mnemonic": "v_mfma_f32_4x4x4_16b_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA F32 4X4X4 16B BF16", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 4x4 matrix in the first input by the 4x4 matrix in the second input and add the 4x4 matrix in the third input using fused multiply add.", "description": "Multiply the 4x4 matrix in the first input by the 4x4 matrix in the second input and add the 4x4 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.", "syntax": "v_mfma_f32_4x4x4_16b_bf16", "operands": [], "dataTypes": [ "f32" ], "semantics": "D = A (4x4) * B (4x4) + C (4x4)\nThis instruction performs 16 matrix multiplies. Each operand contains 16 matrices back to back, and each\nmatrix has elements distributed across all lanes of the wave. Each matrix multiple is computed and the row-column dot products are distributed across the vector ALU for higher performance. The result matrices are\nstored back-to-back in the destination vector registers.\nMatrices A and B are BF16 float format. Matrices C and D are single-precision float format.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx942" ], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 2 passes.", "sourcePdfPage": 280, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_mfma_f32_4x4x4_16b_f16", "mnemonic": "v_mfma_f32_4x4x4_16b_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA F32 4X4X4 16B F16", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 4x4 matrix in the first input by the 4x4 matrix in the second input and add the 4x4 matrix in the third input using fused multiply add.", "description": "Multiply the 4x4 matrix in the first input by the 4x4 matrix in the second input and add the 4x4 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.", "syntax": "v_mfma_f32_4x4x4_16b_f16", "operands": [], "dataTypes": [ "f16", "f32" ], "semantics": "D = A (4x4) * B (4x4) + C (4x4)\nThis instruction performs 16 matrix multiplies. Each operand contains 16 matrices back to back, and each\nmatrix has elements distributed across all lanes of the wave. Each matrix multiple is computed and the row-column dot products are distributed across the vector ALU for higher performance. The result matrices are\nstored back-to-back in the destination vector registers.\nMatrices A and B are half-precision float format. Matrices C and D are single-precision float format.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 2 passes.", "sourcePdfPage": 275, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_mfma_f64_16x16x4_f64", "mnemonic": "v_mfma_f64_16x16x4_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA F64 16X16X4 F64", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 16x4 matrix in the first input by the 4x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply…", "description": "Multiply the 16x4 matrix in the first input by the 4x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.", "syntax": "v_mfma_f64_16x16x4_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "D = A (16x4) * B (4x16) + C (16x16)\nEach operand contains a single matrix whose elements are distributed across all lanes of the wave. A single\nmatrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher\nperformance.\nMatrices A and B are double-precision float format. Matrices C and D are double-precision float format.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx942" ], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 8 passes.", "sourcePdfPage": 284, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_mfma_f64_4x4x4_4b_f64", "mnemonic": "v_mfma_f64_4x4x4_4b_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA F64 4X4X4 4B F64", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 4x4 matrix in the first input by the 4x4 matrix in the second input and add the 4x4 matrix in the third input using fused multiply add.", "description": "Multiply the 4x4 matrix in the first input by the 4x4 matrix in the second input and add the 4x4 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.", "syntax": "v_mfma_f64_4x4x4_4b_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "D = A (4x4) * B (4x4) + C (4x4)\nThis instruction performs 4 matrix multiplies. Each operand contains 4 matrices back to back, and each matrix\nhas elements distributed across all lanes of the wave. Each matrix multiple is computed and the row-column\ndot products are distributed across the vector ALU for higher performance. The result matrices are stored\nback-to-back in the destination vector registers.\nMatrices A and B are double-precision float format. Matrices C and D are double-precision float format.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx942" ], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 4 passes.", "sourcePdfPage": 284, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_mfma_i32_16x16x32_i8", "mnemonic": "v_mfma_i32_16x16x32_i8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA I32 16X16X32 I8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 16x32 matrix in the first input by the 32x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply…", "description": "Multiply the 16x32 matrix in the first input by the 32x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.", "syntax": "v_mfma_i32_16x16x32_i8", "operands": [], "dataTypes": [ "i32", "i8" ], "semantics": "D = A (16x32) * B (32x16) + C (16x16)\nEach operand contains a single matrix whose elements are distributed across all lanes of the wave. A single\nmatrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher\nperformance.\nMatrices A and B are signed 8-bit integer format. Matrices C and D are signed 32-bit integer format.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx942" ], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 4 passes.", "sourcePdfPage": 278, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_mfma_i32_16x16x4_4b_i8", "mnemonic": "v_mfma_i32_16x16x4_4b_i8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA I32 16X16X4 4B I8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 16x4 matrix in the first input by the 4x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply…", "description": "Multiply the 16x4 matrix in the first input by the 4x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.", "syntax": "v_mfma_i32_16x16x4_4b_i8", "operands": [], "dataTypes": [ "i32", "i8" ], "semantics": "D = A (16x4) * B (4x16) + C (16x16)\nThis instruction performs 4 matrix multiplies. Each operand contains 4 matrices back to back, and each matrix\nhas elements distributed across all lanes of the wave. Each matrix multiple is computed and the row-column\ndot products are distributed across the vector ALU for higher performance. The result matrices are stored\nback-to-back in the destination vector registers.\nMatrices A and B are signed 8-bit integer format. Matrices C and D are signed 32-bit integer format.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 8 passes.", "sourcePdfPage": 277, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_mfma_i32_16x16x64_i8", "mnemonic": "v_mfma_i32_16x16x64_i8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA I32 16X16X64 I8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 16x64 matrix in the first input by the 64x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply…", "description": "Multiply the 16x64 matrix in the first input by the 64x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.", "syntax": "v_mfma_i32_16x16x64_i8", "operands": [], "dataTypes": [ "i32", "i8" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_mfma_i32_32x32x16_i8", "mnemonic": "v_mfma_i32_32x32x16_i8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA I32 32X32X16 I8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 32x16 matrix in the first input by the 16x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply…", "description": "Multiply the 32x16 matrix in the first input by the 16x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.", "syntax": "v_mfma_i32_32x32x16_i8", "operands": [], "dataTypes": [ "i32", "i8" ], "semantics": "D = A (32x16) * B (16x32) + C (32x32)\nEach operand contains a single matrix whose elements are distributed across all lanes of the wave. A single\nmatrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher\nperformance.\nMatrices A and B are signed 8-bit integer format. Matrices C and D are signed 32-bit integer format.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx942" ], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 8 passes.", "sourcePdfPage": 278, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_mfma_i32_32x32x32_i8", "mnemonic": "v_mfma_i32_32x32x32_i8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA I32 32X32X32 I8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 32x32 matrix in the first input by the 32x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply…", "description": "Multiply the 32x32 matrix in the first input by the 32x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.", "syntax": "v_mfma_i32_32x32x32_i8", "operands": [], "dataTypes": [ "i32", "i8" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_mfma_i32_32x32x4_2b_i8", "mnemonic": "v_mfma_i32_32x32x4_2b_i8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA I32 32X32X4 2B I8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 32x4 matrix in the first input by the 4x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply…", "description": "Multiply the 32x4 matrix in the first input by the 4x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.", "syntax": "v_mfma_i32_32x32x4_2b_i8", "operands": [], "dataTypes": [ "i32", "i8" ], "semantics": "D = A (32x4) * B (4x32) + C (32x32)\nThis instruction performs 2 matrix multiplies. Each operand contains 2 matrices back to back, and each matrix\nhas elements distributed across all lanes of the wave. Each matrix multiple is computed and the row-column\ndot products are distributed across the vector ALU for higher performance. The result matrices are stored\nback-to-back in the destination vector registers.\nMatrices A and B are signed 8-bit integer format. Matrices C and D are signed 32-bit integer format.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 16 passes.", "sourcePdfPage": 277, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_mfma_i32_4x4x4_16b_i8", "mnemonic": "v_mfma_i32_4x4x4_16b_i8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA I32 4X4X4 16B I8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 4x4 matrix in the first input by the 4x4 matrix in the second input and add the 4x4 matrix in the third input using fused multiply add.", "description": "Multiply the 4x4 matrix in the first input by the 4x4 matrix in the second input and add the 4x4 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.", "syntax": "v_mfma_i32_4x4x4_16b_i8", "operands": [], "dataTypes": [ "i32", "i8" ], "semantics": "D = A (4x4) * B (4x4) + C (4x4)\nThis instruction performs 16 matrix multiplies. Each operand contains 16 matrices back to back, and each\nmatrix has elements distributed across all lanes of the wave. Each matrix multiple is computed and the row-column dot products are distributed across the vector ALU for higher performance. The result matrices are\nstored back-to-back in the destination vector registers.\nMatrices A and B are signed 8-bit integer format. Matrices C and D are signed 32-bit integer format.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 2 passes.", "sourcePdfPage": 277, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_mfma_ld_scale_b32", "mnemonic": "v_mfma_ld_scale_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MFMA LD SCALE B32", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "AMDGPU VOP3P matrix instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_mfma_ld_scale_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_min3_f16", "mnemonic": "v_min3_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MIN3 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the minimum of three half-precision float inputs and store the selected value into a vector register.", "description": "Select the minimum of three half-precision float inputs and store the selected value into a vector register.", "syntax": "v_min3_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.f16 = v_min_f16(v_min_f16(S0.f16, S1.f16), S2.f16)", "example": "v_min3_f16 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 354, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_min3_f32", "mnemonic": "v_min3_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MIN3 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the minimum of three single-precision float inputs and store the selected value into a vector register.", "description": "Select the minimum of three single-precision float inputs and store the selected value into a vector register.", "syntax": "v_min3_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.f32 = v_min_f32(v_min_f32(S0.f32, S1.f32), S2.f32)", "example": "v_min3_f32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 340, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_min3_i16", "mnemonic": "v_min3_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MIN3 I16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the minimum of three signed 16-bit integer inputs and store the selected value into a vector register.", "description": "Select the minimum of three signed 16-bit integer inputs and store the selected value into a vector register.", "syntax": "v_min3_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "D0.i16 = v_min_i16(v_min_i16(S0.i16, S1.i16), S2.i16)", "example": "v_min3_i16 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 354, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_min3_i32", "mnemonic": "v_min3_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MIN3 I32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the minimum of three signed 32-bit integer inputs and store the selected value into a vector register.", "description": "Select the minimum of three signed 32-bit integer inputs and store the selected value into a vector register.", "syntax": "v_min3_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "D0.i32 = v_min_i32(v_min_i32(S0.i32, S1.i32), S2.i32)", "example": "v_min3_i32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 340, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_min3_num_f16", "mnemonic": "v_min3_num_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MIN3 NUM F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the IEEE minimumNumber() of three half-precision float inputs and store the selected value into a vector register.", "description": "Select the IEEE minimumNumber() of three half-precision float inputs and store the selected value into a vector register.", "syntax": "v_min3_num_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_min3_num_f32", "mnemonic": "v_min3_num_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MIN3 NUM F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the IEEE minimumNumber() of three single-precision float inputs and store the selected value into a vector register.", "description": "Select the IEEE minimumNumber() of three single-precision float inputs and store the selected value into a vector register.", "syntax": "v_min3_num_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_min3_u16", "mnemonic": "v_min3_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MIN3 U16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the minimum of three unsigned 16-bit integer inputs and store the selected value into a vector register.", "description": "Select the minimum of three unsigned 16-bit integer inputs and store the selected value into a vector register.", "syntax": "v_min3_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "D0.u16 = v_min_u16(v_min_u16(S0.u16, S1.u16), S2.u16)", "example": "v_min3_u16 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 354, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_min3_u32", "mnemonic": "v_min3_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MIN3 U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the minimum of three unsigned 32-bit integer inputs and store the selected value into a vector register.", "description": "Select the minimum of three unsigned 32-bit integer inputs and store the selected value into a vector register.", "syntax": "v_min3_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "D0.u32 = v_min_u32(v_min_u32(S0.u32, S1.u32), S2.u32)", "example": "v_min3_u32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 340, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_min_f16", "mnemonic": "v_min_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MIN F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the minimum of two half-precision float inputs and store the result into a vector register.", "description": "Select the minimum of two half-precision float inputs and store the result into a vector register.", "syntax": "v_min_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "if (WAVE_MODE.IEEE && isSignalNAN(64'F(S0.f16))) then\nD0.f16 = 16'F(cvtToQuietNAN(64'F(S0.f16)))\nelsif (WAVE_MODE.IEEE && isSignalNAN(64'F(S1.f16))) then\nD0.f16 = 16'F(cvtToQuietNAN(64'F(S1.f16)))\nelsif isNAN(64'F(S0.f16)) then\nD0.f16 = S1.f16\nelsif isNAN(64'F(S1.f16)) then\nD0.f16 = S0.f16\nelsif ((64'F(S0.f16) == +0.0) && (64'F(S1.f16) == -0.0)) then\nD0.f16 = S1.f16\nelsif ((64'F(S0.f16) == -0.0) && (64'F(S1.f16) == +0.0)) then\nD0.f16 = S0.f16\nelse\n// Note: there's no IEEE case here like there is for V_MAX_F16.\nD0.f16 = S0.f16 < S1.f16 ? S0.f16 : S1.f16\nendif", "example": "v_min_f16 v5, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "IEEE compliant. Supports denormals, round mode, exception flags, saturation.", "sourcePdfPage": 181, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_min_f32", "mnemonic": "v_min_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MIN F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the minimum of two single-precision float inputs and store the result into a vector register.", "description": "Select the minimum of two single-precision float inputs and store the result into a vector register.", "syntax": "v_min_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "if (WAVE_MODE.IEEE && isSignalNAN(64'F(S0.f32))) then\nD0.f32 = 32'F(cvtToQuietNAN(64'F(S0.f32)))\nelsif (WAVE_MODE.IEEE && isSignalNAN(64'F(S1.f32))) then\nD0.f32 = 32'F(cvtToQuietNAN(64'F(S1.f32)))\nelsif isNAN(64'F(S0.f32)) then\nD0.f32 = S1.f32\nelsif isNAN(64'F(S1.f32)) then\nD0.f32 = S0.f32\nelsif ((64'F(S0.f32) == +0.0) && (64'F(S1.f32) == -0.0)) then\nD0.f32 = S1.f32\nelsif ((64'F(S0.f32) == -0.0) && (64'F(S1.f32) == +0.0)) then\nD0.f32 = S0.f32\nelse\n// Note: there's no IEEE case here like there is for V_MAX_F32.\nD0.f32 = S0.f32 < S1.f32 ? S0.f32 : S1.f32\nendif", "example": "v_min_f32 v5, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 171, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_min_f64", "mnemonic": "v_min_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MIN F64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the minimum of two double-precision float inputs and store the selected value into a vector register.", "description": "Select the minimum of two double-precision float inputs and store the selected value into a vector register.", "syntax": "v_min_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": "v_min_f64 v[5:6], -1, -1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_min_i16", "mnemonic": "v_min_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MIN I16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the minimum of two signed 16-bit integer inputs and store the selected value into a vector register.", "description": "Select the minimum of two signed 16-bit integer inputs and store the selected value into a vector register.", "syntax": "v_min_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "D0.i16 = S0.i16 < S1.i16 ? S0.i16 : S1.i16", "example": "v_min_i16 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 182, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_min_i32", "mnemonic": "v_min_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MIN I32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the minimum of two signed 32-bit integer inputs and store the selected value into a vector register.", "description": "Select the minimum of two signed 32-bit integer inputs and store the selected value into a vector register.", "syntax": "v_min_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "D0.i32 = S0.i32 < S1.i32 ? S0.i32 : S1.i32", "example": "v_min_i32 v5, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 172, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_min_i64", "mnemonic": "v_min_i64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MIN I64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_min_i64", "operands": [], "dataTypes": [ "i64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_min_legacy_f32", "mnemonic": "v_min_legacy_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MIN LEGACY F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP2 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_min_legacy_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_min_num_f16", "mnemonic": "v_min_num_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MIN NUM F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the IEEE minimumNumber() of two half-precision float inputs and store the selected value into a vector register.", "description": "Select the IEEE minimumNumber() of two half-precision float inputs and store the selected value into a vector register.", "syntax": "v_min_num_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": "v_min_num_f16 v255, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_min_num_f32", "mnemonic": "v_min_num_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MIN NUM F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the IEEE minimumNumber() of two single-precision float inputs and store the selected value into a vector register.", "description": "Select the IEEE minimumNumber() of two single-precision float inputs and store the selected value into a vector register.", "syntax": "v_min_num_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_min_num_f64", "mnemonic": "v_min_num_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MIN NUM F64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the IEEE minimumNumber() of two double-precision float inputs and store the selected value into a vector register.", "description": "Select the IEEE minimumNumber() of two double-precision float inputs and store the selected value into a vector register.", "syntax": "v_min_num_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_min_u16", "mnemonic": "v_min_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MIN U16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the minimum of two unsigned 16-bit integer inputs and store the selected value into a vector register.", "description": "Select the minimum of two unsigned 16-bit integer inputs and store the selected value into a vector register.", "syntax": "v_min_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "D0.u16 = S0.u16 < S1.u16 ? S0.u16 : S1.u16", "example": "v_min_u16 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 182, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_min_u32", "mnemonic": "v_min_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MIN U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the minimum of two unsigned 32-bit integer inputs and store the selected value into a vector register.", "description": "Select the minimum of two unsigned 32-bit integer inputs and store the selected value into a vector register.", "syntax": "v_min_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "D0.u32 = S0.u32 < S1.u32 ? S0.u32 : S1.u32", "example": "v_min_u32 v5, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 173, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_min_u64", "mnemonic": "v_min_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MIN U64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_min_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_minimum3_f16", "mnemonic": "v_minimum3_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MINIMUM3 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the IEEE minimum() of three half-precision float inputs and store the selected value into a vector register.", "description": "Select the IEEE minimum() of three half-precision float inputs and store the selected value into a vector register.", "syntax": "v_minimum3_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_minimum3_f32", "mnemonic": "v_minimum3_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MINIMUM3 F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the IEEE minimum() of three single-precision float inputs and store the result into a vector register.", "description": "Select the IEEE minimum() of three single-precision float inputs and store the result into a vector register.", "syntax": "v_minimum3_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_minimum_f16", "mnemonic": "v_minimum_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MINIMUM F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the IEEE minimum() of two half-precision float inputs and store the selected value into a vector register.", "description": "Select the IEEE minimum() of two half-precision float inputs and store the selected value into a vector register.", "syntax": "v_minimum_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_minimum_f32", "mnemonic": "v_minimum_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MINIMUM F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the IEEE minimum() of two single-precision float inputs and store the selected value into a vector register.", "description": "Select the IEEE minimum() of two single-precision float inputs and store the selected value into a vector register.", "syntax": "v_minimum_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_minimum_f64", "mnemonic": "v_minimum_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MINIMUM F64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the IEEE minimum() of two double-precision float inputs and store the selected value into a vector register.", "description": "Select the IEEE minimum() of two double-precision float inputs and store the selected value into a vector register.", "syntax": "v_minimum_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_minimummaximum_f16", "mnemonic": "v_minimummaximum_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MINIMUMMAXIMUM F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the IEEE minimum() of the first two half-precision float inputs and then select the IEEE maximum() of that result and third half-precision…", "description": "Select the IEEE minimum() of the first two half-precision float inputs and then select the IEEE maximum() of that result and third half-precision float input. Store the final result into a vector register.", "syntax": "v_minimummaximum_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_minimummaximum_f32", "mnemonic": "v_minimummaximum_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MINIMUMMAXIMUM F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the IEEE minimum() of the first two single-precision float inputs and then select the IEEE maximum() of that result and third single-precision…", "description": "Select the IEEE minimum() of the first two single-precision float inputs and then select the IEEE maximum() of that result and third single-precision float input. Store the final result into a vector register.", "syntax": "v_minimummaximum_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_minmax_f16", "mnemonic": "v_minmax_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MINMAX F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the minimum of the first two half-precision float inputs and then select the maximum of that result and third half-precision float input.", "description": "Select the minimum of the first two half-precision float inputs and then select the maximum of that result and third half-precision float input. Store the final result into a vector register.", "syntax": "v_minmax_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": "v_minmax_f16 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_minmax_f32", "mnemonic": "v_minmax_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MINMAX F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the minimum of the first two single-precision float inputs and then select the maximum of that result and third single-precision float input.", "description": "Select the minimum of the first two single-precision float inputs and then select the maximum of that result and third single-precision float input. Store the final result into a vector register.", "syntax": "v_minmax_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": "v_minmax_f32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_minmax_i32", "mnemonic": "v_minmax_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MINMAX I32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the minimum of the first two signed 32-bit integer inputs and then select the maximum of that result and third signed 32-bit integer input.", "description": "Select the minimum of the first two signed 32-bit integer inputs and then select the maximum of that result and third signed 32-bit integer input. Store the final result into a vector register.", "syntax": "v_minmax_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "", "example": "v_minmax_i32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_minmax_num_f16", "mnemonic": "v_minmax_num_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MINMAX NUM F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the IEEE minimumNumber() of the first two half-precision float inputs and then select the IEEE maximumNumber() of that result and third…", "description": "Select the IEEE minimumNumber() of the first two half-precision float inputs and then select the IEEE maximumNumber() of that result and third half-precision float input. Store the final result into a vector register.", "syntax": "v_minmax_num_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_minmax_num_f32", "mnemonic": "v_minmax_num_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MINMAX NUM F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the IEEE minimumNumber() of the first two single-precision float inputs and then select the IEEE maximumNumber() of that result and third…", "description": "Select the IEEE minimumNumber() of the first two single-precision float inputs and then select the IEEE maximumNumber() of that result and third single-precision float input. Store the final result into a vector register.", "syntax": "v_minmax_num_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_minmax_u32", "mnemonic": "v_minmax_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MINMAX U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Select the minimum of the first two unsigned 32-bit integer inputs and then select the maximum of that result and third unsigned 32-bit integer input.", "description": "Select the minimum of the first two unsigned 32-bit integer inputs and then select the maximum of that result and third unsigned 32-bit integer input. Store the final result into a vector register.", "syntax": "v_minmax_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": "v_minmax_u32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_mov_b16", "mnemonic": "v_mov_b16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MOV B16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Move 16-bit data from a vector input into a vector register.", "description": "Move 16-bit data from a vector input into a vector register.", "syntax": "v_mov_b16", "operands": [], "dataTypes": [ "b16" ], "semantics": "", "example": "v_mov_b16_e32 v5.l, s1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_mov_b32", "mnemonic": "v_mov_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MOV B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Move 32-bit data from a vector input into a vector register.", "description": "Move 32-bit data from a vector input into a vector register.", "syntax": "v_mov_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.b32 = S0.b32", "example": "v_mov_b32 v0, v1 // Move into v0 from v1\nv_mov_b32 v0, -v1 // Set v0 to the negation of v1\nv_mov_b32 v0, abs(v1) // Set v0 to the absolute value of v1", "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Floating-point modifiers are valid for this instruction if S0 is a 32-bit floating point value. This instruction is suitable for negating or taking the absolute value of a floating-point value.", "sourcePdfPage": 186, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_mov_b64", "mnemonic": "v_mov_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MOV B64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Move data from a 64-bit vector input into a vector register.", "description": "Move data from a 64-bit vector input into a vector register.", "syntax": "v_mov_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "D0.b64 = S0.b64", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "Floating-point modifiers are valid for this instruction if S0.u64 is a 64-bit floating point value. This instruction is suitable for negating or taking the absolute value of a floating-point value.", "sourcePdfPage": 203, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_movreld_b32", "mnemonic": "v_movreld_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MOVRELD B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Move data from a vector input into a relatively-indexed vector register.", "description": "Move data from a vector input into a relatively-indexed vector register.", "syntax": "v_movreld_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "v_movreld_b32 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_movrels_b32", "mnemonic": "v_movrels_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MOVRELS B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Move data from a relatively-indexed vector register into another vector register.", "description": "Move data from a relatively-indexed vector register into another vector register.", "syntax": "v_movrels_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "v_movrels_b32 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_movrelsd_b32", "mnemonic": "v_movrelsd_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MOVRELSD B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Move data from a relatively-indexed vector register into another relatively-indexed vector register.", "description": "Move data from a relatively-indexed vector register into another relatively-indexed vector register.", "syntax": "v_movrelsd_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "v_movrelsd_b32 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_mqsad_pk_u16_u8", "mnemonic": "v_mqsad_pk_u16_u8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MQSAD PK U16 U8", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Perform the V_MSAD_U8 operation four times using different slices of the first array, all entries of the second array and each entry of the third…", "description": "Perform the V_MSAD_U8 operation four times using different slices of the first array, all entries of the second array and each entry of the third array. Truncate each result to 16 bits, pack the values into a 4-entry array and store the array into a vector register. The first input is an 8-entry array of unsigned 8-bit integers, the second input is a 4-entry array of unsigned 8-bit integers and the third input is a 4-entry array of unsigned 16-bit integers.", "syntax": "v_mqsad_pk_u16_u8", "operands": [], "dataTypes": [ "u16", "u8" ], "semantics": "tmp[63 : 48] = 16'B(v_msad_u8(S0[55 : 24], S1[31 : 0], S2[63 : 48].u32));\ntmp[47 : 32] = 16'B(v_msad_u8(S0[47 : 16], S1[31 : 0], S2[47 : 32].u32));\ntmp[31 : 16] = 16'B(v_msad_u8(S0[39 : 8], S1[31 : 0], S2[31 : 16].u32));\ntmp[15 : 0] = 16'B(v_msad_u8(S0[31 : 0], S1[31 : 0], S2[15 : 0].u32));\nD0.b64 = tmp.b64", "example": "v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, ttmp[14:15]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 349, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_mqsad_u32_u8", "mnemonic": "v_mqsad_u32_u8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MQSAD U32 U8", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Perform the V_MSAD_U8 operation four times using different slices of the first array, all entries of the second array and each entry of the third…", "description": "Perform the V_MSAD_U8 operation four times using different slices of the first array, all entries of the second array and each entry of the third array. Pack each 32-bit value into a 4-entry array and store the array into a vector register. The first input is an 8-entry array of unsigned 8-bit integers, the second input is a 4-entry array of unsigned 8-bit integers and the third input is a 4-entry array of unsigned 32-bit integers.", "syntax": "v_mqsad_u32_u8", "operands": [], "dataTypes": [ "u32", "u8" ], "semantics": "tmp[127 : 96] = 32'B(v_msad_u8(S0[55 : 24], S1[31 : 0], S2[127 : 96].u32));\ntmp[95 : 64] = 32'B(v_msad_u8(S0[47 : 16], S1[31 : 0], S2[95 : 64].u32));\ntmp[63 : 32] = 32'B(v_msad_u8(S0[39 : 8], S1[31 : 0], S2[63 : 32].u32));\ntmp[31 : 0] = 32'B(v_msad_u8(S0[31 : 0], S1[31 : 0], S2[31 : 0].u32));\nD0.b128 = tmp.b128", "example": "v_mqsad_u32_u8 v[5:8], -1, -1, v[252:255]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 349, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_msad_u8", "mnemonic": "v_msad_u8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MSAD U8", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate the sum of absolute differences of elements in two packed 4-component unsigned 8-bit integer inputs, except that elements where the second…", "description": "Calculate the sum of absolute differences of elements in two packed 4-component unsigned 8-bit integer inputs, except that elements where the second input (known as the reference input) is zero are not included in the sum. Add an unsigned 32-bit integer value from the third input and store the result into a vector register.", "syntax": "v_msad_u8", "operands": [], "dataTypes": [ "u8" ], "semantics": "ABSDIFF = lambda(x, y) (\nx > y ? x - y : y - x);\n// UNSIGNED comparison\ntmp = S2.u32;\ntmp += S1.u32[7 : 0] == 8'0U ? 0U : 32'U(ABSDIFF(S0.u32[7 : 0], S1.u32[7 : 0]));\ntmp += S1.u32[15 : 8] == 8'0U ? 0U : 32'U(ABSDIFF(S0.u32[15 : 8], S1.u32[15 : 8]));\ntmp += S1.u32[23 : 16] == 8'0U ? 0U : 32'U(ABSDIFF(S0.u32[23 : 16], S1.u32[23 : 16]));\ntmp += S1.u32[31 : 24] == 8'0U ? 0U : 32'U(ABSDIFF(S0.u32[31 : 24], S1.u32[31 : 24]));\nD0.u32 = tmp", "example": "v_msad_u8 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Overflow into the upper bits is allowed.", "sourcePdfPage": 348, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_mul_f16", "mnemonic": "v_mul_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MUL F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two floating point inputs and store the result into a vector register.", "description": "Multiply two floating point inputs and store the result into a vector register.", "syntax": "v_mul_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.f16 = S0.f16 * S1.f16", "example": "v_mul_f16 v5, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "0.5ULP precision. Supports denormals, round mode, exception flags and saturation.", "sourcePdfPage": 178, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_mul_f32", "mnemonic": "v_mul_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MUL F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Per-lane single-precision floating-point multiply.", "description": "Multiply two floating point inputs and store the result into a vector register.", "syntax": "v_mul_f32 VDST, S0, S1", "operands": [ { "name": "VDST", "desc": "Destination VGPR" }, { "name": "S0", "desc": "First source" }, { "name": "S1", "desc": "Second source" } ], "dataTypes": [ "f32" ], "semantics": "VDST[lane] = S0[lane].f32 * S1[lane].f32 for each active lane.", "example": "v_mul_f32 v2, v0, v1 // per-lane v2 = v0 * v1", "exampleSource": null, "encoding": { "format": "VOP2", "widthBits": 32 }, "executionUnit": "Vector ALU", "registerClasses": [ "VGPR" ], "memorySegment": null, "supportedTargets": [ "gfx942", "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_mul_f64", "mnemonic": "v_mul_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MUL F64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two floating point inputs and store the result into a vector register.", "description": "Multiply two floating point inputs and store the result into a vector register.", "syntax": "v_mul_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": "v_mul_f64 v[5:6], -1, -1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_mul_f64_pseudo", "mnemonic": "v_mul_f64_pseudo", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MUL F64 PSEUDO", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP2 vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_mul_f64_pseudo", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_mul_hi_i32", "mnemonic": "v_mul_hi_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MUL HI I32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two signed 32-bit integer inputs and store the high 32 bits of the result into a vector register.", "description": "Multiply two signed 32-bit integer inputs and store the high 32 bits of the result into a vector register.", "syntax": "v_mul_hi_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "D0.i32 = 32'I((64'I(S0.i32) * 64'I(S1.i32)) >> 32U)", "example": "v_mul_hi_i32 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "To multiply integers with small magnitudes consider V_MUL_HI_I32_I24, which is intended to be a more efficient implementation.", "sourcePdfPage": 362, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_mul_hi_i32_i24", "mnemonic": "v_mul_hi_i32_i24", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MUL HI I32 I24", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two signed 24-bit integer inputs and store the high 32 bits of the result as a signed 32-bit integer into a vector register.", "description": "Multiply two signed 24-bit integer inputs and store the high 32 bits of the result as a signed 32-bit integer into a vector register.", "syntax": "v_mul_hi_i32_i24", "operands": [], "dataTypes": [ "i32" ], "semantics": "D0.i32 = 32'I((64'I(S0.i24) * 64'I(S1.i24)) >> 32U)", "example": "v_mul_hi_i32_i24 v5, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "See also V_MUL_I32_I24.", "sourcePdfPage": 170, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_mul_hi_u32", "mnemonic": "v_mul_hi_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MUL HI U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two unsigned 32-bit integer inputs and store the high 32 bits of the result into a vector register.", "description": "Multiply two unsigned 32-bit integer inputs and store the high 32 bits of the result into a vector register.", "syntax": "v_mul_hi_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "D0.u32 = 32'U((64'U(S0.u32) * 64'U(S1.u32)) >> 32U)", "example": "v_mul_hi_u32 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "To multiply integers with small magnitudes consider V_MUL_HI_U32_U24, which is intended to be a more efficient implementation.", "sourcePdfPage": 361, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_mul_hi_u32_u24", "mnemonic": "v_mul_hi_u32_u24", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MUL HI U32 U24", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two unsigned 24-bit integer inputs and store the high 32 bits of the result as an unsigned 32-bit integer into a vector register.", "description": "Multiply two unsigned 24-bit integer inputs and store the high 32 bits of the result as an unsigned 32-bit integer into a vector register.", "syntax": "v_mul_hi_u32_u24", "operands": [], "dataTypes": [ "u32" ], "semantics": "D0.u32 = 32'U((64'U(S0.u24) * 64'U(S1.u24)) >> 32U)", "example": "v_mul_hi_u32_u24 v5, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "See also V_MUL_U32_U24.", "sourcePdfPage": 171, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_mul_i32_i24", "mnemonic": "v_mul_i32_i24", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MUL I32 I24", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two signed 24-bit integer inputs and store the result as a signed 32-bit integer into a vector register.", "description": "Multiply two signed 24-bit integer inputs and store the result as a signed 32-bit integer into a vector register.", "syntax": "v_mul_i32_i24", "operands": [], "dataTypes": [ "i32" ], "semantics": "D0.i32 = 32'I(S0.i24) * 32'I(S1.i24)", "example": "v_mul_i32_i24 v5, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "This opcode is expected to be as efficient as basic single-precision opcodes since it utilizes the single-precision floating point multiplier. See also V_MUL_HI_I32_I24.", "sourcePdfPage": 170, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_mul_legacy_f32", "mnemonic": "v_mul_legacy_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MUL LEGACY F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two floating point inputs and store the result into a vector register.", "description": "Multiply two floating point inputs and store the result into a vector register. Follows DX9 rules where 0.0 times anything produces 0.0 (this differs from other APIs when the other input is infinity or NaN).", "syntax": "v_mul_legacy_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": "v_mul_legacy_f32 v5, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_mul_lo_i32", "mnemonic": "v_mul_lo_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MUL LO I32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_mul_lo_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_mul_lo_u16", "mnemonic": "v_mul_lo_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MUL LO U16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two unsigned 16-bit integer inputs and store the low bits of the result into a vector register.", "description": "Multiply two unsigned 16-bit integer inputs and store the low bits of the result into a vector register.", "syntax": "v_mul_lo_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "D0.u16 = S0.u16 * S1.u16", "example": "v_mul_lo_u16 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Supports saturation (unsigned 16-bit integer domain).", "sourcePdfPage": 180, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_mul_lo_u32", "mnemonic": "v_mul_lo_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MUL LO U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Per-lane 32-bit unsigned multiply, low half of the product.", "description": "Multiply two unsigned 32-bit integer inputs and store the result into a vector register.", "syntax": "v_mul_lo_u32 VDST, S0, S1", "operands": [ { "name": "VDST", "desc": "Destination VGPR" }, { "name": "S0", "desc": "First source" }, { "name": "S1", "desc": "Second source" } ], "dataTypes": [ "u32" ], "semantics": "VDST[lane] = lo32(S0[lane].u32 * S1[lane].u32) for each active lane.", "example": "v_mul_lo_u32 v2, v0, v1 // per-lane low 32 bits of v0 * v1", "exampleSource": null, "encoding": { "format": "VOP3", "widthBits": 32 }, "executionUnit": "Vector ALU", "registerClasses": [ "VGPR" ], "memorySegment": null, "supportedTargets": [ "gfx942", "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_mul_u32_u24", "mnemonic": "v_mul_u32_u24", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MUL U32 U24", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two unsigned 24-bit integer inputs and store the result as an unsigned 32-bit integer into a vector register.", "description": "Multiply two unsigned 24-bit integer inputs and store the result as an unsigned 32-bit integer into a vector register.", "syntax": "v_mul_u32_u24", "operands": [], "dataTypes": [ "u32" ], "semantics": "D0.u32 = 32'U(S0.u24) * 32'U(S1.u24)", "example": "v_mul_u32_u24 v5, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "This opcode is expected to be as efficient as basic single-precision opcodes since it utilizes the single-precision floating point multiplier. See also V_MUL_HI_U32_U24.", "sourcePdfPage": 171, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_mul_u64", "mnemonic": "v_mul_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MUL U64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP2 vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_mul_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_mullit_f32", "mnemonic": "v_mullit_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V MULLIT F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two floating point inputs and store the result into a vector register.", "description": "Multiply two floating point inputs and store the result into a vector register. Specific rules apply to accommodate lighting calculations: 0.0 * x = 0.0 and alternate INF, NAN, overflow rules apply.", "syntax": "v_mullit_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": "v_mullit_f32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_nop", "mnemonic": "v_nop", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V NOP", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Do nothing.", "description": "Do nothing.", "syntax": "v_nop", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "This instruction can be used to insert a single-cycle bubble in the vector ALU pipeline. For multiple cycles repeat this opcode.", "sourcePdfPage": 186, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_not_b16", "mnemonic": "v_not_b16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V NOT B16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate bitwise negation on a vector input and store the result into a vector register.", "description": "Calculate bitwise negation on a vector input and store the result into a vector register.", "syntax": "v_not_b16", "operands": [], "dataTypes": [ "b16" ], "semantics": "", "example": "v_not_b16 v5.l, s1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_not_b32", "mnemonic": "v_not_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V NOT B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate bitwise negation on a vector input and store the result into a vector register.", "description": "Calculate bitwise negation on a vector input and store the result into a vector register.", "syntax": "v_not_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.u32 = ~S0.u32", "example": "v_not_b32 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Input and output modifiers not supported.", "sourcePdfPage": 199, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_or3_b32", "mnemonic": "v_or3_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V OR3 B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate the bitwise OR of three vector inputs and store the result into a vector register.", "description": "Calculate the bitwise OR of three vector inputs and store the result into a vector register.", "syntax": "v_or3_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.u32 = (S0.u32 | S1.u32 | S2.u32)", "example": "v_or3_b32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Input and output modifiers not supported.", "sourcePdfPage": 357, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_or_b16", "mnemonic": "v_or_b16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V OR B16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate bitwise OR on two vector inputs and store the result into a vector register.", "description": "Calculate bitwise OR on two vector inputs and store the result into a vector register.", "syntax": "v_or_b16", "operands": [], "dataTypes": [ "b16" ], "semantics": "", "example": "v_or_b16 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_or_b16_fake16", "mnemonic": "v_or_b16_fake16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V OR B16 FAKE16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_or_b16_fake16", "operands": [], "dataTypes": [ "b16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_or_b16_t16", "mnemonic": "v_or_b16_t16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V OR B16 T16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_or_b16_t16", "operands": [], "dataTypes": [ "b16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_or_b32", "mnemonic": "v_or_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V OR B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate bitwise OR on two vector inputs and store the result into a vector register.", "description": "Calculate bitwise OR on two vector inputs and store the result into a vector register.", "syntax": "v_or_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.u32 = (S0.u32 | S1.u32)", "example": "v_or_b32 v5, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Input and output modifiers not supported.", "sourcePdfPage": 174, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_pack_b32_f16", "mnemonic": "v_pack_b32_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PACK B32 F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Pack two half-precision float values into a single 32-bit value and store the result into a vector register.", "description": "Pack two half-precision float values into a single 32-bit value and store the result into a vector register.", "syntax": "v_pack_b32_f16", "operands": [], "dataTypes": [ "b32", "f16" ], "semantics": "D0[31 : 16].f16 = S1.f16;\nD0[15 : 0].f16 = S0.f16", "example": "v_pack_b32_f16 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 369, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_perm_b32", "mnemonic": "v_perm_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PERM B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Permute a 64-bit value constructed from two vector inputs (most significant bits come from the first input) using a per-lane selector from the third…", "description": "Permute a 64-bit value constructed from two vector inputs (most significant bits come from the first input) using a per-lane selector from the third input. The lane selector allows each byte of the result to choose from any of the 8 input bytes, perform sign extension or pad with 0/1 bits. Store the result into a vector register.", "syntax": "v_perm_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "BYTE_PERMUTE = lambda(data, sel) (\ndeclare in : 8'B[8];\nfor i in 0 : 7 do\nin[i] = data[i * 8 + 7 : i * 8].b8\nendfor;\nif sel.u32 >= 13U then\nreturn 8'0xff\nelsif sel.u32 == 12U then\nreturn 8'0x0\nelsif sel.u32 == 11U then\nreturn in[7][7].b8 * 8'0xff\nelsif sel.u32 == 10U then\nreturn in[5][7].b8 * 8'0xff\nelsif sel.u32 == 9U then\nreturn in[3][7].b8 * 8'0xff\nelsif sel.u32 == 8U then\nreturn in[1][7].b8 * 8'0xff\nelse\nreturn in[sel]\nendif);\nD0[31 : 24] = BYTE_PERMUTE({ S0.u32, S1.u32 }, S2.u32[31 : 24]);\nD0[23 : 16] = BYTE_PERMUTE({ S0.u32, S1.u32 }, S2.u32[23 : 16]);\nD0[15 : 8] = BYTE_PERMUTE({ S0.u32, S1.u32 }, S2.u32[15 : 8]);\nD0[7 : 0] = BYTE_PERMUTE({ S0.u32, S1.u32 }, S2.u32[7 : 0])", "example": "v_perm_b32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Selects 0 through 7 select the corresponding byte of the 64-bit input value. Selects 8 through 11 are useful in modeling sign extension of a smaller-precision signed integer to a larger- precision result by replicating the leading bit of a selected byte. Selects 12 and 13 return padding values of 0 and 1 bits respectively. Note the MSBs of the 64-bit value being selected are stored in S0. This is counterintuitive for a little-endian architecture.", "sourcePdfPage": 351, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_perm_pk16_b4_u4", "mnemonic": "v_perm_pk16_b4_u4", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PERM PK16 B4 U4", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_perm_pk16_b4_u4", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_perm_pk16_b6_u4", "mnemonic": "v_perm_pk16_b6_u4", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PERM PK16 B6 U4", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_perm_pk16_b6_u4", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_perm_pk16_b8_u4", "mnemonic": "v_perm_pk16_b8_u4", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PERM PK16 B8 U4", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on b8 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_perm_pk16_b8_u4", "operands": [], "dataTypes": [ "b8" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_permlane16_b32", "mnemonic": "v_permlane16_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PERMLANE16 B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Perform arbitrary gather-style operation within a row (16 contiguous lanes).", "description": "Perform arbitrary gather-style operation within a row (16 contiguous lanes).", "syntax": "v_permlane16_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "v_permlane16_b32 v5, v1, s2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_permlane16_swap_b32", "mnemonic": "v_permlane16_swap_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PERMLANE16 SWAP B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Swap data between two vector registers. Odd rows of the first operand are swapped with even rows of the second operand (one row is 16 lanes).", "description": "Swap data between two vector registers. Odd rows of the first operand are swapped with even rows of the second operand (one row is 16 lanes).", "syntax": "v_permlane16_swap_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_permlane16_var_b32", "mnemonic": "v_permlane16_var_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PERMLANE16 VAR B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Perform arbitrary gather-style operation within a row (16 contiguous lanes).", "description": "Perform arbitrary gather-style operation within a row (16 contiguous lanes).", "syntax": "v_permlane16_var_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_permlane32_swap_b32", "mnemonic": "v_permlane32_swap_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PERMLANE32 SWAP B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Swap data between two vector registers. Rows 2 and 3 of the first operand are swapped with rows 0 and 1 of the second operand (one row is 16 lanes).", "description": "Swap data between two vector registers. Rows 2 and 3 of the first operand are swapped with rows 0 and 1 of the second operand (one row is 16 lanes).", "syntax": "v_permlane32_swap_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_permlane64_b32", "mnemonic": "v_permlane64_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PERMLANE64 B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Perform a specific permutation across lanes where the high half and low half of a wave64 are swapped. Performs no operation in wave32 mode.", "description": "Perform a specific permutation across lanes where the high half and low half of a wave64 are swapped. Performs no operation in wave32 mode.", "syntax": "v_permlane64_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "v_permlane64_b32 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_permlane_bcast_b32", "mnemonic": "v_permlane_bcast_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PERMLANE BCAST B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_permlane_bcast_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_permlane_down_b32", "mnemonic": "v_permlane_down_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PERMLANE DOWN B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_permlane_down_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_permlane_idx_gen_b32", "mnemonic": "v_permlane_idx_gen_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PERMLANE IDX GEN B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_permlane_idx_gen_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_permlane_up_b32", "mnemonic": "v_permlane_up_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PERMLANE UP B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_permlane_up_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_permlane_xor_b32", "mnemonic": "v_permlane_xor_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PERMLANE XOR B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_permlane_xor_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_permlanex16_b32", "mnemonic": "v_permlanex16_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PERMLANEX16 B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Perform arbitrary gather-style operation across two rows (each row is 16 contiguous lanes).", "description": "Perform arbitrary gather-style operation across two rows (each row is 16 contiguous lanes).", "syntax": "v_permlanex16_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "v_permlanex16_b32 v5, v1, s2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_permlanex16_var_b32", "mnemonic": "v_permlanex16_var_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PERMLANEX16 VAR B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Perform arbitrary gather-style operation across two rows (each row is 16 contiguous lanes).", "description": "Perform arbitrary gather-style operation across two rows (each row is 16 contiguous lanes).", "syntax": "v_permlanex16_var_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_pipeflush", "mnemonic": "v_pipeflush", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PIPEFLUSH", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Flush the vector ALU pipeline through the destination cache.", "description": "Flush the vector ALU pipeline through the destination cache.", "syntax": "v_pipeflush", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_pk_add_bf16", "mnemonic": "v_pk_add_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK ADD BF16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3P vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_pk_add_bf16", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_pk_add_f16", "mnemonic": "v_pk_add_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK ADD F16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Add two packed half-precision float inputs component-wise and store the result into a vector register. No carry- in or carry-out support.", "description": "Add two packed half-precision float inputs component-wise and store the result into a vector register. No carry- in or carry-out support.", "syntax": "v_pk_add_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "declare tmp : 32'B;\ntmp[15 : 0].f16 = S0[15 : 0].f16 + S1[15 : 0].f16;\ntmp[31 : 16].f16 = S0[31 : 16].f16 + S1[31 : 16].f16;\nD0.b32 = tmp", "example": "v_pk_add_f16 v5, s1, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 266, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_pk_add_f32", "mnemonic": "v_pk_add_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK ADD F32", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Add two packed single-precision float inputs component-wise and store the result into a vector register. No carry-in or carry-out support.", "description": "Add two packed single-precision float inputs component-wise and store the result into a vector register. No carry-in or carry-out support.", "syntax": "v_pk_add_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "declare tmp : 64'B;\ntmp[31 : 0].f32 = S0[31 : 0].f32 + S1[31 : 0].f32;\ntmp[63 : 32].f32 = S0[63 : 32].f32 + S1[63 : 32].f32;\nD0.b64 = tmp", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 271, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_pk_add_f64", "mnemonic": "v_pk_add_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK ADD F64", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3P vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_pk_add_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_pk_add_i16", "mnemonic": "v_pk_add_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK ADD I16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Add two packed signed 16-bit integer inputs component-wise and store the result into a vector register. No carry-in or carry-out support.", "description": "Add two packed signed 16-bit integer inputs component-wise and store the result into a vector register. No carry-in or carry-out support.", "syntax": "v_pk_add_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "declare tmp : 32'B;\ntmp[15 : 0].i16 = S0[15 : 0].i16 + S1[15 : 0].i16;\ntmp[31 : 16].i16 = S0[31 : 16].i16 + S1[31 : 16].i16;\nD0.b32 = tmp", "example": "v_pk_add_i16 v5, s1, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 263, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_pk_add_max_i16", "mnemonic": "v_pk_add_max_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK ADD MAX I16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3P vector instruction operating on i16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_pk_add_max_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_pk_add_max_u16", "mnemonic": "v_pk_add_max_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK ADD MAX U16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3P vector instruction operating on u16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_pk_add_max_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_pk_add_min_i16", "mnemonic": "v_pk_add_min_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK ADD MIN I16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3P vector instruction operating on i16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_pk_add_min_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_pk_add_min_u16", "mnemonic": "v_pk_add_min_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK ADD MIN U16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3P vector instruction operating on u16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_pk_add_min_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_pk_add_nc_u64", "mnemonic": "v_pk_add_nc_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK ADD NC U64", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3P vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_pk_add_nc_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_pk_add_u16", "mnemonic": "v_pk_add_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK ADD U16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Add two packed unsigned 16-bit integer inputs component-wise and store the result into a vector register. No carry-in or carry-out support.", "description": "Add two packed unsigned 16-bit integer inputs component-wise and store the result into a vector register. No carry-in or carry-out support.", "syntax": "v_pk_add_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "declare tmp : 32'B;\ntmp[15 : 0].u16 = S0[15 : 0].u16 + S1[15 : 0].u16;\ntmp[31 : 16].u16 = S0[31 : 16].u16 + S1[31 : 16].u16;\nD0.b32 = tmp", "example": "v_pk_add_u16 v5, s1, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 265, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_pk_ashrrev_i16", "mnemonic": "v_pk_ashrrev_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK ASHRREV I16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Given a packed shift count in the first vector input, calculate the component-wise arithmetic shift right (preserving sign bit) of the second packed…", "description": "Given a packed shift count in the first vector input, calculate the component-wise arithmetic shift right (preserving sign bit) of the second packed vector input and store the result into a vector register.", "syntax": "v_pk_ashrrev_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "tmp[31 : 16].i16 = (S1[31 : 16].i16 >> S0.u32[19 : 16].u32);\ntmp[15 : 0].i16 = (S1[15 : 0].i16 >> S0.u32[3 : 0].u32);\nD0.b32 = tmp.b32", "example": "v_pk_ashrrev_i16 v5, s1, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 264, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_pk_fma_bf16", "mnemonic": "v_pk_fma_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK FMA BF16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3P vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_pk_fma_bf16", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_pk_fma_f16", "mnemonic": "v_pk_fma_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK FMA F16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Multiply two packed half-precision float inputs component-wise and add a third input component-wise using fused multiply add, and store the result…", "description": "Multiply two packed half-precision float inputs component-wise and add a third input component-wise using fused multiply add, and store the result into a vector register.", "syntax": "v_pk_fma_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "declare tmp : 32'B;\ntmp[15 : 0].f16 = fma(S0[15 : 0].f16, S1[15 : 0].f16, S2[15 : 0].f16);\ntmp[31 : 16].f16 = fma(S0[31 : 16].f16, S1[31 : 16].f16, S2[31 : 16].f16);\nD0.b32 = tmp", "example": "v_pk_fma_f16 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 266, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_pk_fma_f32", "mnemonic": "v_pk_fma_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK FMA F32", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Multiply two packed single-precision float inputs component-wise and add a third input component-wise using fused multiply add, and store the result…", "description": "Multiply two packed single-precision float inputs component-wise and add a third input component-wise using fused multiply add, and store the result into a vector register.", "syntax": "v_pk_fma_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "declare tmp : 64'B;\ntmp[31 : 0].f32 = fma(S0[31 : 0].f32, S1[31 : 0].f32, S2[31 : 0].f32);\ntmp[63 : 32].f32 = fma(S0[63 : 32].f32, S1[63 : 32].f32, S2[63 : 32].f32);\nD0.b64 = tmp", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 270, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_pk_fma_f64", "mnemonic": "v_pk_fma_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK FMA F64", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3P vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_pk_fma_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_pk_fmac_f16", "mnemonic": "v_pk_fmac_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK FMAC F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Multiply two packed half-precision float inputs component-wise and accumulate the result into the destination register using fused multiply add.", "description": "Multiply two packed half-precision float inputs component-wise and accumulate the result into the destination register using fused multiply add.", "syntax": "v_pk_fmac_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0[15 : 0].f16 = fma(S0[15 : 0].f16, S1[15 : 0].f16, D0[15 : 0].f16);\nD0[31 : 16].f16 = fma(S0[31 : 16].f16, S1[31 : 16].f16, D0[31 : 16].f16)", "example": "v_pk_fmac_f16 v5, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 185, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_pk_lshl_add_u64", "mnemonic": "v_pk_lshl_add_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK LSHL ADD U64", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3P vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_pk_lshl_add_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_pk_lshlrev_b16", "mnemonic": "v_pk_lshlrev_b16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK LSHLREV B16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Given a packed shift count in the first vector input, calculate the component-wise logical shift left of the second packed vector input and store the…", "description": "Given a packed shift count in the first vector input, calculate the component-wise logical shift left of the second packed vector input and store the result into a vector register.", "syntax": "v_pk_lshlrev_b16", "operands": [], "dataTypes": [ "b16" ], "semantics": "tmp[31 : 16].u16 = (S1[31 : 16].u16 << S0.u32[19 : 16].u32);\ntmp[15 : 0].u16 = (S1[15 : 0].u16 << S0.u32[3 : 0].u32);\nD0.b32 = tmp.b32", "example": "v_pk_lshlrev_b16 v5, s1, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 263, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_pk_lshrrev_b16", "mnemonic": "v_pk_lshrrev_b16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK LSHRREV B16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Given a packed shift count in the first vector input, calculate the component-wise logical shift right of the second packed vector input and store…", "description": "Given a packed shift count in the first vector input, calculate the component-wise logical shift right of the second packed vector input and store the result into a vector register.", "syntax": "v_pk_lshrrev_b16", "operands": [], "dataTypes": [ "b16" ], "semantics": "tmp[31 : 16].u16 = (S1[31 : 16].u16 >> S0.u32[19 : 16].u32);\ntmp[15 : 0].u16 = (S1[15 : 0].u16 >> S0.u32[3 : 0].u32);\nD0.b32 = tmp.b32", "example": "v_pk_lshrrev_b16 v5, s1, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 263, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_pk_mad_i16", "mnemonic": "v_pk_mad_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK MAD I16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Multiply two packed signed 16-bit integer inputs component-wise, add a packed signed 16-bit integer value from a third input component-wise, and…", "description": "Multiply two packed signed 16-bit integer inputs component-wise, add a packed signed 16-bit integer value from a third input component-wise, and store the result into a vector register.", "syntax": "v_pk_mad_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "declare tmp : 32'B;\ntmp[15 : 0].i16 = S0[15 : 0].i16 * S1[15 : 0].i16 + S2[15 : 0].i16;\ntmp[31 : 16].i16 = S0[31 : 16].i16 * S1[31 : 16].i16 + S2[31 : 16].i16;\nD0.b32 = tmp", "example": "v_pk_mad_i16 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 262, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_pk_mad_u16", "mnemonic": "v_pk_mad_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK MAD U16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Multiply two packed unsigned 16-bit integer inputs component-wise, add a packed unsigned 16-bit integer value from a third input component-wise, and…", "description": "Multiply two packed unsigned 16-bit integer inputs component-wise, add a packed unsigned 16-bit integer value from a third input component-wise, and store the result into a vector register.", "syntax": "v_pk_mad_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "declare tmp : 32'B;\ntmp[15 : 0].u16 = S0[15 : 0].u16 * S1[15 : 0].u16 + S2[15 : 0].u16;\ntmp[31 : 16].u16 = S0[31 : 16].u16 * S1[31 : 16].u16 + S2[31 : 16].u16;\nD0.b32 = tmp", "example": "v_pk_mad_u16 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 264, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_pk_max3_i16", "mnemonic": "v_pk_max3_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK MAX3 I16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3P vector instruction operating on i16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_pk_max3_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_pk_max3_num_f16", "mnemonic": "v_pk_max3_num_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK MAX3 NUM F16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3P vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_pk_max3_num_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_pk_max3_u16", "mnemonic": "v_pk_max3_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK MAX3 U16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3P vector instruction operating on u16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_pk_max3_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_pk_max_f16", "mnemonic": "v_pk_max_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK MAX F16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Select the component-wise maximum of two packed half-precision float inputs and store the result into a vector register.", "description": "Select the component-wise maximum of two packed half-precision float inputs and store the result into a vector register.", "syntax": "v_pk_max_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "declare tmp : 32'B;\ntmp[15 : 0].f16 = v_max_f16(S0[15 : 0].f16, S1[15 : 0].f16);\ntmp[31 : 16].f16 = v_max_f16(S0[31 : 16].f16, S1[31 : 16].f16);\nD0.b32 = tmp", "example": "v_pk_max_f16 v5, s1, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 267, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_pk_max_i16", "mnemonic": "v_pk_max_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK MAX I16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Select the component-wise maximum of two packed signed 16-bit integer inputs and store the selected values into a vector register.", "description": "Select the component-wise maximum of two packed signed 16-bit integer inputs and store the selected values into a vector register.", "syntax": "v_pk_max_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "declare tmp : 32'B;\ntmp[15 : 0].i16 = S0[15 : 0].i16 >= S1[15 : 0].i16 ? S0[15 : 0].i16 : S1[15 : 0].i16;\ntmp[31 : 16].i16 = S0[31 : 16].i16 >= S1[31 : 16].i16 ? S0[31 : 16].i16 : S1[31 : 16].i16;\nD0.b32 = tmp", "example": "v_pk_max_i16 v5, s1, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 264, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_pk_max_num_bf16", "mnemonic": "v_pk_max_num_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK MAX NUM BF16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3P vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_pk_max_num_bf16", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_pk_max_num_f16", "mnemonic": "v_pk_max_num_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK MAX NUM F16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Select the component-wise IEEE maximumNumber() of two packed half-precision float inputs and store the selected values into a vector register.", "description": "Select the component-wise IEEE maximumNumber() of two packed half-precision float inputs and store the selected values into a vector register.", "syntax": "v_pk_max_num_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_pk_max_num_f64", "mnemonic": "v_pk_max_num_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK MAX NUM F64", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3P vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_pk_max_num_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_pk_max_u16", "mnemonic": "v_pk_max_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK MAX U16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Select the component-wise maximum of two packed unsigned 16-bit integer inputs and store the selected values into a vector register.", "description": "Select the component-wise maximum of two packed unsigned 16-bit integer inputs and store the selected values into a vector register.", "syntax": "v_pk_max_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "declare tmp : 32'B;\ntmp[15 : 0].u16 = S0[15 : 0].u16 >= S1[15 : 0].u16 ? S0[15 : 0].u16 : S1[15 : 0].u16;\ntmp[31 : 16].u16 = S0[31 : 16].u16 >= S1[31 : 16].u16 ? S0[31 : 16].u16 : S1[31 : 16].u16;\nD0.b32 = tmp", "example": "v_pk_max_u16 v5, s1, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 265, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_pk_maximum3_f16", "mnemonic": "v_pk_maximum3_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK MAXIMUM3 F16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Select the component-wise IEEE maximum() of three half-precision float inputs and store the result into a vector register.", "description": "Select the component-wise IEEE maximum() of three half-precision float inputs and store the result into a vector register.", "syntax": "v_pk_maximum3_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_pk_maximum_f16", "mnemonic": "v_pk_maximum_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK MAXIMUM F16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Select the component-wise IEEE maximum() of two packed half-precision float inputs and store the selected values into a vector register.", "description": "Select the component-wise IEEE maximum() of two packed half-precision float inputs and store the selected values into a vector register.", "syntax": "v_pk_maximum_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_pk_min3_i16", "mnemonic": "v_pk_min3_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK MIN3 I16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3P vector instruction operating on i16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_pk_min3_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_pk_min3_num_f16", "mnemonic": "v_pk_min3_num_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK MIN3 NUM F16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3P vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_pk_min3_num_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_pk_min3_u16", "mnemonic": "v_pk_min3_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK MIN3 U16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3P vector instruction operating on u16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_pk_min3_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_pk_min_f16", "mnemonic": "v_pk_min_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK MIN F16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Select the component-wise minimum of two packed half-precision float inputs and store the result into a vector register.", "description": "Select the component-wise minimum of two packed half-precision float inputs and store the result into a vector register.", "syntax": "v_pk_min_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "declare tmp : 32'B;\ntmp[15 : 0].f16 = v_min_f16(S0[15 : 0].f16, S1[15 : 0].f16);\ntmp[31 : 16].f16 = v_min_f16(S0[31 : 16].f16, S1[31 : 16].f16);\nD0.b32 = tmp", "example": "v_pk_min_f16 v5, s1, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 266, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_pk_min_i16", "mnemonic": "v_pk_min_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK MIN I16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Select the component-wise minimum of two packed signed 16-bit integer inputs and store the selected values into a vector register.", "description": "Select the component-wise minimum of two packed signed 16-bit integer inputs and store the selected values into a vector register.", "syntax": "v_pk_min_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "declare tmp : 32'B;\ntmp[15 : 0].i16 = S0[15 : 0].i16 < S1[15 : 0].i16 ? S0[15 : 0].i16 : S1[15 : 0].i16;\ntmp[31 : 16].i16 = S0[31 : 16].i16 < S1[31 : 16].i16 ? S0[31 : 16].i16 : S1[31 : 16].i16;\nD0.b32 = tmp", "example": "v_pk_min_i16 v5, s1, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 264, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_pk_min_num_bf16", "mnemonic": "v_pk_min_num_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK MIN NUM BF16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3P vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_pk_min_num_bf16", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_pk_min_num_f16", "mnemonic": "v_pk_min_num_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK MIN NUM F16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Select the component-wise IEEE minimumNumber() of two packed half-precision float inputs and store the selected values into a vector register.", "description": "Select the component-wise IEEE minimumNumber() of two packed half-precision float inputs and store the selected values into a vector register.", "syntax": "v_pk_min_num_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_pk_min_num_f64", "mnemonic": "v_pk_min_num_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK MIN NUM F64", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3P vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_pk_min_num_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_pk_min_u16", "mnemonic": "v_pk_min_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK MIN U16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Select the component-wise minimum of two packed unsigned 16-bit integer inputs and store the selected values into a vector register.", "description": "Select the component-wise minimum of two packed unsigned 16-bit integer inputs and store the selected values into a vector register.", "syntax": "v_pk_min_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "declare tmp : 32'B;\ntmp[15 : 0].u16 = S0[15 : 0].u16 < S1[15 : 0].u16 ? S0[15 : 0].u16 : S1[15 : 0].u16;\ntmp[31 : 16].u16 = S0[31 : 16].u16 < S1[31 : 16].u16 ? S0[31 : 16].u16 : S1[31 : 16].u16;\nD0.b32 = tmp", "example": "v_pk_min_u16 v5, s1, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 265, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_pk_minimum3_f16", "mnemonic": "v_pk_minimum3_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK MINIMUM3 F16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Select the component-wise IEEE minimum() of three half-precision float inputs and store the result into a vector register.", "description": "Select the component-wise IEEE minimum() of three half-precision float inputs and store the result into a vector register.", "syntax": "v_pk_minimum3_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_pk_minimum_f16", "mnemonic": "v_pk_minimum_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK MINIMUM F16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Select the component-wise IEEE minimum() of two packed half-precision float inputs and store the selected values into a vector register.", "description": "Select the component-wise IEEE minimum() of two packed half-precision float inputs and store the selected values into a vector register.", "syntax": "v_pk_minimum_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_pk_mov_b32", "mnemonic": "v_pk_mov_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK MOV B32", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Move data from two vector inputs into two vector registers.", "description": "Move data from two vector inputs into two vector registers.", "syntax": "v_pk_mov_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "tmp0.u32 = S0.u32[OPSEL[0].i32 * 32 + 31 : OPSEL[0].i32 * 32];\ntmp1.u32 = S1.u32[OPSEL[1].i32 * 32 + 31 : OPSEL[1].i32 * 32];\nD0.u32[31 : 0] = tmp0.u32;\nD0.u32[63 : 32] = tmp1.u32", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "The source operands are treated as 64 bit and are subject to alignment restrictions for both SGPR and VGPR. For two VGPR inputs this opcode can be used as an arbitrary gather by using OP_SEL to select either the even VGPR specified or the next odd VGPR. v_pk_mov_b32 v0, v2, v4 op_sel:[0,1] // evaluates v0 <- v2 and v1 <- v5. Due to scalar broadcast restrictions if two SGPRs are specified as operands, they must be the same SGPR. v_pk_mov_b32 v0, s6, s6 op_sel:[0,1] // 64-bit move from scalar s[6:7].", "sourcePdfPage": 271, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_pk_mul_bf16", "mnemonic": "v_pk_mul_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK MUL BF16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3P vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_pk_mul_bf16", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_pk_mul_f16", "mnemonic": "v_pk_mul_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK MUL F16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Multiply two packed half-precision float inputs component-wise and store the result into a vector register.", "description": "Multiply two packed half-precision float inputs component-wise and store the result into a vector register.", "syntax": "v_pk_mul_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "declare tmp : 32'B;\ntmp[15 : 0].f16 = S0[15 : 0].f16 * S1[15 : 0].f16;\ntmp[31 : 16].f16 = S0[31 : 16].f16 * S1[31 : 16].f16;\nD0.b32 = tmp", "example": "v_pk_mul_f16 v5, s1, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 266, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_pk_mul_f32", "mnemonic": "v_pk_mul_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK MUL F32", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Multiply two packed single-precision float inputs component-wise and store the result into a vector register.", "description": "Multiply two packed single-precision float inputs component-wise and store the result into a vector register.", "syntax": "v_pk_mul_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "declare tmp : 64'B;\ntmp[31 : 0].f32 = S0[31 : 0].f32 * S1[31 : 0].f32;\ntmp[63 : 32].f32 = S0[63 : 32].f32 * S1[63 : 32].f32;\nD0.b64 = tmp", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 271, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_pk_mul_f64", "mnemonic": "v_pk_mul_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK MUL F64", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3P vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_pk_mul_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_pk_mul_lo_u16", "mnemonic": "v_pk_mul_lo_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK MUL LO U16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Multiply two packed unsigned 16-bit integer inputs component-wise and store the low bits of each resulting component into a vector register.", "description": "Multiply two packed unsigned 16-bit integer inputs component-wise and store the low bits of each resulting component into a vector register.", "syntax": "v_pk_mul_lo_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "tmp[31 : 16].u16 = S0[31 : 16].u16 * S1[31 : 16].u16;\ntmp[15 : 0].u16 = S0[15 : 0].u16 * S1[15 : 0].u16;\nD0.b32 = tmp.b32", "example": "v_pk_mul_lo_u16 v5, s1, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 263, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_pk_sub_i16", "mnemonic": "v_pk_sub_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK SUB I16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Subtract the second packed signed 16-bit integer input from the first input component-wise and store the result into a vector register.", "description": "Subtract the second packed signed 16-bit integer input from the first input component-wise and store the result into a vector register. No carry-in or carry-out support.", "syntax": "v_pk_sub_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "declare tmp : 32'B;\ntmp[15 : 0].i16 = S0[15 : 0].i16 - S1[15 : 0].i16;\ntmp[31 : 16].i16 = S0[31 : 16].i16 - S1[31 : 16].i16;\nD0.b32 = tmp", "example": "v_pk_sub_i16 v5, s1, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 263, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_pk_sub_nc_u64", "mnemonic": "v_pk_sub_nc_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK SUB NC U64", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP3P vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_pk_sub_nc_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_pk_sub_u16", "mnemonic": "v_pk_sub_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PK SUB U16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Subtract the second packed unsigned 16-bit integer input from the first input component-wise and store the result into a vector register.", "description": "Subtract the second packed unsigned 16-bit integer input from the first input component-wise and store the result into a vector register. No carry-in or carry-out support.", "syntax": "v_pk_sub_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "declare tmp : 32'B;\ntmp[15 : 0].u16 = S0[15 : 0].u16 - S1[15 : 0].u16;\ntmp[31 : 16].u16 = S0[31 : 16].u16 - S1[31 : 16].u16;\nD0.b32 = tmp", "example": "v_pk_sub_u16 v5, s1, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 265, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_prng_b32", "mnemonic": "v_prng_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V PRNG B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Generate a pseudorandom number using an LFSR (linear feedback shift register) seeded with the vector input, then store the result into a vector…", "description": "Generate a pseudorandom number using an LFSR (linear feedback shift register) seeded with the vector input, then store the result into a vector register.", "syntax": "v_prng_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_qsad_pk_u16_u8", "mnemonic": "v_qsad_pk_u16_u8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V QSAD PK U16 U8", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Perform the V_SAD_U8 operation four times using different slices of the first array, all entries of the second array and each entry of the third…", "description": "Perform the V_SAD_U8 operation four times using different slices of the first array, all entries of the second array and each entry of the third array. Truncate each result to 16 bits, pack the values into a 4-entry array and store the array into a vector register. The first input is an 8-entry array of unsigned 8-bit integers, the second input is a 4-entry array of unsigned 8-bit integers and the third input is a 4-entry array of unsigned 16-bit integers.", "syntax": "v_qsad_pk_u16_u8", "operands": [], "dataTypes": [ "u16", "u8" ], "semantics": "tmp[63 : 48] = 16'B(v_sad_u8(S0[55 : 24], S1[31 : 0], S2[63 : 48].u32));\ntmp[47 : 32] = 16'B(v_sad_u8(S0[47 : 16], S1[31 : 0], S2[47 : 32].u32));\ntmp[31 : 16] = 16'B(v_sad_u8(S0[39 : 8], S1[31 : 0], S2[31 : 16].u32));\ntmp[15 : 0] = 16'B(v_sad_u8(S0[31 : 0], S1[31 : 0], S2[15 : 0].u32));\nD0.b64 = tmp.b64", "example": "v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, ttmp[14:15]", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 348, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_rcp_bf16", "mnemonic": "v_rcp_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V RCP BF16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_rcp_bf16", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_rcp_f16", "mnemonic": "v_rcp_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V RCP F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate the reciprocal of the half-precision float input using IEEE rules and store the result into a vector register.", "description": "Calculate the reciprocal of the half-precision float input using IEEE rules and store the result into a vector register.", "syntax": "v_rcp_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.f16 = 16'1.0 / S0.f16", "example": "V_RCP_F16(0xfc00) => 0x8000 // rcp(-INF) = -0\nV_RCP_F16(0xc000) => 0xb800 // rcp(-2.0) = -0.5\nV_RCP_F16(0x8000) => 0xfc00 // rcp(-0.0) = -INF\nV_RCP_F16(0x0000) => 0x7c00 // rcp(+0.0) = +INF", "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "1ULP accuracy.", "sourcePdfPage": 205, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_rcp_f32", "mnemonic": "v_rcp_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V RCP F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate the reciprocal of the single-precision float input using IEEE rules and store the result into a vector register.", "description": "Calculate the reciprocal of the single-precision float input using IEEE rules and store the result into a vector register.", "syntax": "v_rcp_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.f32 = 1.0F / S0.f32", "example": "V_RCP_F32(0xff800000) => 0x80000000 // rcp(-INF) = -0\nV_RCP_F32(0xc0000000) => 0xbf000000 // rcp(-2.0) = -0.5\nV_RCP_F32(0x80000000) => 0xff800000 // rcp(-0.0) = -INF\nV_RCP_F32(0x00000000) => 0x7f800000 // rcp(+0.0) = +INF", "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "1ULP accuracy. Accuracy converges to < 0.5ULP when using the Newton-Raphson method and 2 FMA operations. Denormals are flushed.", "sourcePdfPage": 196, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_rcp_f64", "mnemonic": "v_rcp_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V RCP F64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate the reciprocal of the double-precision float input using IEEE rules and store the result into a vector register.", "description": "Calculate the reciprocal of the double-precision float input using IEEE rules and store the result into a vector register.", "syntax": "v_rcp_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "D0.f64 = 1.0 / S0.f64", "example": "v_rcp_f64 v[5:6], -1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "This opcode has (2**29)ULP accuracy and supports denormals.", "sourcePdfPage": 197, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_rcp_iflag_f32", "mnemonic": "v_rcp_iflag_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V RCP IFLAG F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate the reciprocal of the vector float input in a manner suitable for integer division and store the result into a vector register.", "description": "Calculate the reciprocal of the vector float input in a manner suitable for integer division and store the result into a vector register. This opcode is intended for use as part of an integer division macro.", "syntax": "v_rcp_iflag_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.f32 = 1.0F / S0.f32;\n// Can only raise integer DIV_BY_ZERO exception", "example": "v_rcp_iflag_f32 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Can raise integer DIV_BY_ZERO exception but cannot raise floating-point exceptions. To be used in an integer reciprocal macro by the compiler with one of the sequences listed below (depending on signed or unsigned operation). Unsigned usage: CVT_F32_U32 RCP_IFLAG_F32 MUL_F32 (2**32 - 1) CVT_U32_F32 Signed usage: CVT_F32_I32 RCP_IFLAG_F32 MUL_F32 (2**31 - 1) CVT_I32_F32", "sourcePdfPage": 196, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_readfirstlane_b32", "mnemonic": "v_readfirstlane_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V READFIRSTLANE B32", "category": "Lane Operations", "instructionClass": "vector", "summary": "Read the value of a VGPR from the first active lane into a scalar register.", "description": "Read the scalar value in the lowest active lane of the input vector register and store it into a scalar register.", "syntax": "v_readfirstlane_b32 SDST, S0", "operands": [ { "name": "SDST", "desc": "Destination SGPR" }, { "name": "S0", "desc": "Source VGPR" } ], "dataTypes": [ "b32" ], "semantics": "SDST = S0[first active lane in EXEC]; used to move a per-lane value into scalar (wavefront-uniform) state when all active lanes are known to agree.", "example": "v_readfirstlane_b32 s0, v0 // s0 = v0 from the first active lane", "exampleSource": null, "encoding": { "format": "VOP1", "widthBits": 32 }, "executionUnit": "Vector ALU", "registerClasses": [ "VGPR", "SGPR" ], "memorySegment": null, "supportedTargets": [ "gfx942", "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_readlane_b32", "mnemonic": "v_readlane_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V READLANE B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Read the scalar value in the specified lane of the first input where the lane select is in the second input. Store the result into a scalar register.", "description": "Read the scalar value in the specified lane of the first input where the lane select is in the second input. Store the result into a scalar register.", "syntax": "v_readlane_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "v_readlane_b32 s5, v1, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_rndne_f16", "mnemonic": "v_rndne_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V RNDNE F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Round the half-precision float input to the nearest even integer and store the result in floating point format into a vector register.", "description": "Round the half-precision float input to the nearest even integer and store the result in floating point format into a vector register.", "syntax": "v_rndne_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.f16 = floor(S0.f16 + 16'0.5);\nif (isEven(64'F(floor(S0.f16))) && (fract(S0.f16) == 16'0.5)) then\nD0.f16 -= 16'1.0\nendif", "example": "v_rndne_f16 v5.l, s1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 208, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_rndne_f32", "mnemonic": "v_rndne_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V RNDNE F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Round the single-precision float input to the nearest even integer and store the result in floating point format into a vector register.", "description": "Round the single-precision float input to the nearest even integer and store the result in floating point format into a vector register.", "syntax": "v_rndne_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.f32 = floor(S0.f32 + 0.5F);\nif (isEven(64'F(floor(S0.f32))) && (fract(S0.f32) == 0.5F)) then\nD0.f32 -= 1.0F\nendif", "example": "v_rndne_f32 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 194, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_rndne_f64", "mnemonic": "v_rndne_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V RNDNE F64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Round the double-precision float input to the nearest even integer and store the result in floating point format into a vector register.", "description": "Round the double-precision float input to the nearest even integer and store the result in floating point format into a vector register.", "syntax": "v_rndne_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "D0.f64 = floor(S0.f64 + 0.5);\nif (isEven(floor(S0.f64)) && (fract(S0.f64) == 0.5)) then\nD0.f64 -= 1.0\nendif", "example": "v_rndne_f64 v[5:6], -1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 193, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_rsq_bf16", "mnemonic": "v_rsq_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V RSQ BF16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_rsq_bf16", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_rsq_f16", "mnemonic": "v_rsq_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V RSQ F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate the reciprocal of the square root of the half-precision float input using IEEE rules and store the result into a vector register.", "description": "Calculate the reciprocal of the square root of the half-precision float input using IEEE rules and store the result into a vector register.", "syntax": "v_rsq_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.f16 = 16'1.0 / sqrt(S0.f16)", "example": "V_RSQ_F16(0xfc00) => 0xfe00 // rsq(-INF) = NAN\nV_RSQ_F16(0x8000) => 0xfc00 // rsq(-0.0) = -INF\nV_RSQ_F16(0x0000) => 0x7c00 // rsq(+0.0) = +INF\nV_RSQ_F16(0x4400) => 0x3800 // rsq(+4.0) = +0.5", "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "1ULP accuracy, denormals are supported.", "sourcePdfPage": 206, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_rsq_f32", "mnemonic": "v_rsq_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V RSQ F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Per-lane fast approximate reciprocal square root.", "description": "Calculate the reciprocal of the square root of the single-precision float input using IEEE rules and store the result into a vector register.", "syntax": "v_rsq_f32 VDST, S0", "operands": [ { "name": "VDST", "desc": "Destination VGPR" }, { "name": "S0", "desc": "Source operand" } ], "dataTypes": [ "f32" ], "semantics": "VDST[lane] ≈ 1 / sqrt(S0[lane].f32) for each active lane, with a hardware-specific ULP error bound.", "example": "v_rsq_f32 v1, v0 // v1 = approx(1 / sqrt(v0))", "exampleSource": null, "encoding": { "format": "VOP1", "widthBits": 32 }, "executionUnit": "Vector ALU", "registerClasses": [ "VGPR" ], "memorySegment": null, "supportedTargets": [ "gfx942", "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_rsq_f64", "mnemonic": "v_rsq_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V RSQ F64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate the reciprocal of the square root of the double-precision float input using IEEE rules and store the result into a vector register.", "description": "Calculate the reciprocal of the square root of the double-precision float input using IEEE rules and store the result into a vector register.", "syntax": "v_rsq_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "D0.f64 = 1.0 / sqrt(S0.f64)", "example": "v_rsq_f64 v[5:6], -1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "This opcode has (2**29)ULP accuracy and supports denormals.", "sourcePdfPage": 197, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_s_exp_f16", "mnemonic": "v_s_exp_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V S EXP F16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Calculate 2 raised to the power of the half-precision float input and store the result into a scalar register.", "description": "Calculate 2 raised to the power of the half-precision float input and store the result into a scalar register.", "syntax": "v_s_exp_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_s_exp_f32", "mnemonic": "v_s_exp_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V S EXP F32", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Calculate 2 raised to the power of the single-precision float input and store the result into a scalar register.", "description": "Calculate 2 raised to the power of the single-precision float input and store the result into a scalar register.", "syntax": "v_s_exp_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_s_log_f16", "mnemonic": "v_s_log_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V S LOG F16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Calculate the base 2 logarithm of the half-precision float input and store the result into a scalar register.", "description": "Calculate the base 2 logarithm of the half-precision float input and store the result into a scalar register.", "syntax": "v_s_log_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_s_log_f32", "mnemonic": "v_s_log_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V S LOG F32", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Calculate the base 2 logarithm of the single-precision float input and store the result into a scalar register.", "description": "Calculate the base 2 logarithm of the single-precision float input and store the result into a scalar register.", "syntax": "v_s_log_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_s_rcp_f16", "mnemonic": "v_s_rcp_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V S RCP F16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Calculate the reciprocal of the half-precision float input using IEEE rules and store the result into a scalar register.", "description": "Calculate the reciprocal of the half-precision float input using IEEE rules and store the result into a scalar register.", "syntax": "v_s_rcp_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_s_rcp_f32", "mnemonic": "v_s_rcp_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V S RCP F32", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Calculate the reciprocal of the single-precision float input using IEEE rules and store the result into a scalar register.", "description": "Calculate the reciprocal of the single-precision float input using IEEE rules and store the result into a scalar register.", "syntax": "v_s_rcp_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_s_rsq_f16", "mnemonic": "v_s_rsq_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V S RSQ F16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Calculate the reciprocal of the square root of the half-precision float input using IEEE rules and store the result into a scalar register.", "description": "Calculate the reciprocal of the square root of the half-precision float input using IEEE rules and store the result into a scalar register.", "syntax": "v_s_rsq_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_s_rsq_f32", "mnemonic": "v_s_rsq_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V S RSQ F32", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Calculate the reciprocal of the square root of the single-precision float input using IEEE rules and store the result into a scalar register.", "description": "Calculate the reciprocal of the square root of the single-precision float input using IEEE rules and store the result into a scalar register.", "syntax": "v_s_rsq_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_s_sqrt_f16", "mnemonic": "v_s_sqrt_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V S SQRT F16", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Calculate the square root of the half-precision float input using IEEE rules and store the result into a scalar register.", "description": "Calculate the square root of the half-precision float input using IEEE rules and store the result into a scalar register.", "syntax": "v_s_sqrt_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_s_sqrt_f32", "mnemonic": "v_s_sqrt_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V S SQRT F32", "category": "Vector Packed Arithmetic", "instructionClass": "vector", "summary": "Calculate the square root of the single-precision float input using IEEE rules and store the result into a scalar register.", "description": "Calculate the square root of the single-precision float input using IEEE rules and store the result into a scalar register.", "syntax": "v_s_sqrt_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_sad_hi_u8", "mnemonic": "v_sad_hi_u8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SAD HI U8", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate the sum of absolute differences of elements in two packed 4-component unsigned 8-bit integer inputs, shift the sum left by 16 bits, add an…", "description": "Calculate the sum of absolute differences of elements in two packed 4-component unsigned 8-bit integer inputs, shift the sum left by 16 bits, add an unsigned 32-bit integer value from the third input and store the result into a vector register.", "syntax": "v_sad_hi_u8", "operands": [], "dataTypes": [ "u8" ], "semantics": "D0.u32 = (32'U(v_sad_u8(S0, S1, 0U)) << 16U) + S2.u32", "example": "v_sad_hi_u8 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Overflow into the upper bits is allowed.", "sourcePdfPage": 342, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_sad_u16", "mnemonic": "v_sad_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SAD U16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate the sum of absolute differences of elements in two packed 2-component unsigned 16-bit integer inputs, add an unsigned 32-bit integer value…", "description": "Calculate the sum of absolute differences of elements in two packed 2-component unsigned 16-bit integer inputs, add an unsigned 32-bit integer value from the third input and store the result into a vector register.", "syntax": "v_sad_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "ABSDIFF = lambda(x, y) (\nx > y ? x - y : y - x);\n// UNSIGNED comparison\ntmp = S2.u32;\ntmp += ABSDIFF(S0[15 : 0].u16, S1[15 : 0].u16);\ntmp += ABSDIFF(S0[31 : 16].u16, S1[31 : 16].u16);\nD0.u32 = tmp", "example": "v_sad_u16 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 342, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_sad_u32", "mnemonic": "v_sad_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SAD U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate the absolute difference of two unsigned 32-bit integer inputs, add an unsigned 32-bit integer value from the third input and store the…", "description": "Calculate the absolute difference of two unsigned 32-bit integer inputs, add an unsigned 32-bit integer value from the third input and store the result into a vector register.", "syntax": "v_sad_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "ABSDIFF = lambda(x, y) (\nx > y ? x - y : y - x);\n// UNSIGNED comparison\nD0.u32 = ABSDIFF(S0.u32, S1.u32) + S2.u32", "example": "v_sad_u32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 343, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_sad_u8", "mnemonic": "v_sad_u8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SAD U8", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate the sum of absolute differences of elements in two packed 4-component unsigned 8-bit integer inputs, add an unsigned 32-bit integer value…", "description": "Calculate the sum of absolute differences of elements in two packed 4-component unsigned 8-bit integer inputs, add an unsigned 32-bit integer value from the third input and store the result into a vector register.", "syntax": "v_sad_u8", "operands": [], "dataTypes": [ "u8" ], "semantics": "ABSDIFF = lambda(x, y) (\nx > y ? x - y : y - x);\n// UNSIGNED comparison\ntmp = S2.u32;\ntmp += 32'U(ABSDIFF(S0.u32[7 : 0], S1.u32[7 : 0]));\ntmp += 32'U(ABSDIFF(S0.u32[15 : 8], S1.u32[15 : 8]));\ntmp += 32'U(ABSDIFF(S0.u32[23 : 16], S1.u32[23 : 16]));\ntmp += 32'U(ABSDIFF(S0.u32[31 : 24], S1.u32[31 : 24]));\nD0.u32 = tmp", "example": "v_sad_u8 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Overflow into the upper bits is allowed.", "sourcePdfPage": 342, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_sat_pk4_i4_i8", "mnemonic": "v_sat_pk4_i4_i8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SAT PK4 I4 I8", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP1 vector instruction operating on i8 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_sat_pk4_i4_i8", "operands": [], "dataTypes": [ "i8" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_sat_pk4_u4_u8", "mnemonic": "v_sat_pk4_u4_u8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SAT PK4 U4 U8", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP1 vector instruction operating on u8 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_sat_pk4_u4_u8", "operands": [], "dataTypes": [ "u8" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_sat_pk_u8_i16", "mnemonic": "v_sat_pk_u8_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SAT PK U8 I16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Given 2 signed 16-bit integer inputs, saturate each input over an unsigned 8-bit integer range, pack the resulting values into a packed 16-bit value…", "description": "Given 2 signed 16-bit integer inputs, saturate each input over an unsigned 8-bit integer range, pack the resulting values into a packed 16-bit value and store the result into a vector register.", "syntax": "v_sat_pk_u8_i16", "operands": [], "dataTypes": [ "i16", "u8" ], "semantics": "SAT8 = lambda(n) (\nif n <= 16'0 then\nreturn 8'0U\nelsif n >= 16'255 then\nreturn 8'255U\nelse\nreturn n[7 : 0].u8\nendif);\ntmp = 16'0;\ntmp[7 : 0].u8 = SAT8(S0[15 : 0].i16);\ntmp[15 : 8].u8 = SAT8(S0[31 : 16].i16);\nD0.b16 = tmp.b16", "example": "v_sat_pk_u8_i16 v5.l, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Used for 4x16bit data packed as 4x8bit data.", "sourcePdfPage": 211, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_screen_partition_4se_b32", "mnemonic": "v_screen_partition_4se_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SCREEN PARTITION 4SE B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "4SE version of LUT instruction for screen partitioning/filtering.", "description": "4SE version of LUT instruction for screen partitioning/filtering. This opcode is intended to help accelerate screen partitioning in the 4SE case only. 2SE and 1SE cases use normal ALU instructions.", "syntax": "v_screen_partition_4se_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_sin_bf16", "mnemonic": "v_sin_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SIN BF16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_sin_bf16", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_sin_f16", "mnemonic": "v_sin_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SIN F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate the trigonometric sine of a half-precision float value using IEEE rules and store the result into a vector register.", "description": "Calculate the trigonometric sine of a half-precision float value using IEEE rules and store the result into a vector register. The operand is calculated by scaling the vector input by 2 PI.", "syntax": "v_sin_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.f16 = sin(S0.f16 * 16'F(PI * 2.0))", "example": "V_SIN_F16(0xfc00) => 0xfe00 // sin(-INF) = NAN\nV_SIN_F16(0xfbff) => 0x0000 // Most negative finite FP16\nV_SIN_F16(0x8000) => 0x8000 // sin(-0.0) = -0\nV_SIN_F16(0x3400) => 0x3c00 // sin(0.25) = 1", "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Denormals are supported. Full range input is supported.", "sourcePdfPage": 209, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_sin_f32", "mnemonic": "v_sin_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SIN F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Per-lane fast approximate sine.", "description": "Calculate the trigonometric sine of a single-precision float value using IEEE rules and store the result into a vector register. The operand is calculated by scaling the vector input by 2 PI.", "syntax": "v_sin_f32 VDST, S0", "operands": [ { "name": "VDST", "desc": "Destination VGPR" }, { "name": "S0", "desc": "Source operand (radians, pre-scaled per hardware convention)" } ], "dataTypes": [ "f32" ], "semantics": "VDST[lane] ≈ sin(S0[lane].f32) for each active lane, valid over a hardware-defined input range.", "example": "v_sin_f32 v1, v0 // v1 = approx(sin(v0))", "exampleSource": null, "encoding": { "format": "VOP1", "widthBits": 32 }, "executionUnit": "Vector ALU", "registerClasses": [ "VGPR" ], "memorySegment": null, "supportedTargets": [ "gfx942", "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_smfmac_f32_16x16x128_bf8_bf8", "mnemonic": "v_smfmac_f32_16x16x128_bf8_bf8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 16X16X128 BF8 BF8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 16x128 sparse matrix in the first input by the 128x16 matrix in the second input and accumulate the result into the 16x16 matrix stored…", "description": "Multiply the 16x128 sparse matrix in the first input by the 128x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.", "syntax": "v_smfmac_f32_16x16x128_bf8_bf8", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_smfmac_f32_16x16x128_bf8_fp8", "mnemonic": "v_smfmac_f32_16x16x128_bf8_fp8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 16X16X128 BF8 FP8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 16x128 sparse matrix in the first input by the 128x16 matrix in the second input and accumulate the result into the 16x16 matrix stored…", "description": "Multiply the 16x128 sparse matrix in the first input by the 128x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.", "syntax": "v_smfmac_f32_16x16x128_bf8_fp8", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_smfmac_f32_16x16x128_fp8_bf8", "mnemonic": "v_smfmac_f32_16x16x128_fp8_bf8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 16X16X128 FP8 BF8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 16x128 sparse matrix in the first input by the 128x16 matrix in the second input and accumulate the result into the 16x16 matrix stored…", "description": "Multiply the 16x128 sparse matrix in the first input by the 128x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.", "syntax": "v_smfmac_f32_16x16x128_fp8_bf8", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_smfmac_f32_16x16x128_fp8_fp8", "mnemonic": "v_smfmac_f32_16x16x128_fp8_fp8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 16X16X128 FP8 FP8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 16x128 sparse matrix in the first input by the 128x16 matrix in the second input and accumulate the result into the 16x16 matrix stored…", "description": "Multiply the 16x128 sparse matrix in the first input by the 128x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.", "syntax": "v_smfmac_f32_16x16x128_fp8_fp8", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_smfmac_f32_16x16x128bf8bf8", "mnemonic": "v_smfmac_f32_16x16x128bf8bf8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 16X16X128BF8BF8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_smfmac_f32_16x16x128bf8bf8", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_smfmac_f32_16x16x128bf8fp8", "mnemonic": "v_smfmac_f32_16x16x128bf8fp8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 16X16X128BF8FP8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_smfmac_f32_16x16x128bf8fp8", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_smfmac_f32_16x16x128fp8bf8", "mnemonic": "v_smfmac_f32_16x16x128fp8bf8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 16X16X128FP8BF8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_smfmac_f32_16x16x128fp8bf8", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_smfmac_f32_16x16x128fp8fp8", "mnemonic": "v_smfmac_f32_16x16x128fp8fp8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 16X16X128FP8FP8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_smfmac_f32_16x16x128fp8fp8", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_smfmac_f32_16x16x32_bf16", "mnemonic": "v_smfmac_f32_16x16x32_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 16X16X32 BF16", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 16x32 sparse matrix in the first input by the 32x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in…", "description": "Multiply the 16x32 sparse matrix in the first input by the 32x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.", "syntax": "v_smfmac_f32_16x16x32_bf16", "operands": [], "dataTypes": [ "f32" ], "semantics": "D = A (sparse 16x32) * B (32x16) + D (16x16)\nEach operand contains a single matrix whose elements are distributed across all lanes of the wave. A single\nmatrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher\nperformance.\nMatrix A is a sparse matrix in BF16 float format, consuming half the physical storage of a dense matrix with\nsame dimensions. Matrix B is a dense matrix in BF16 float format. Matrix D is single-precision float format and\nis both the output and the accumulate input.\n2 out of every 4 elements on the K axis of matrix A are zero. The sparse indexes are used to determine which 2\nelements are zero.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 4 passes.", "sourcePdfPage": 282, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_smfmac_f32_16x16x32_f16", "mnemonic": "v_smfmac_f32_16x16x32_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 16X16X32 F16", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 16x32 sparse matrix in the first input by the 32x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in…", "description": "Multiply the 16x32 sparse matrix in the first input by the 32x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.", "syntax": "v_smfmac_f32_16x16x32_f16", "operands": [], "dataTypes": [ "f16", "f32" ], "semantics": "D = A (sparse 16x32) * B (32x16) + D (16x16)\nEach operand contains a single matrix whose elements are distributed across all lanes of the wave. A single\nmatrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher\nperformance.\nMatrix A is a sparse matrix in half-precision float format, consuming half the physical storage of a dense\nmatrix with same dimensions. Matrix B is a dense matrix in half-precision float format. Matrix D is single-precision float format and is both the output and the accumulate input.\n2 out of every 4 elements on the K axis of matrix A are zero. The sparse indexes are used to determine which 2\nelements are zero.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 4 passes.", "sourcePdfPage": 281, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_smfmac_f32_16x16x32bf16", "mnemonic": "v_smfmac_f32_16x16x32bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 16X16X32BF16", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_smfmac_f32_16x16x32bf16", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_smfmac_f32_16x16x32f16", "mnemonic": "v_smfmac_f32_16x16x32f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 16X16X32F16", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_smfmac_f32_16x16x32f16", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_smfmac_f32_16x16x64_bf16", "mnemonic": "v_smfmac_f32_16x16x64_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 16X16X64 BF16", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 16x64 sparse matrix in the first input by the 64x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in…", "description": "Multiply the 16x64 sparse matrix in the first input by the 64x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.", "syntax": "v_smfmac_f32_16x16x64_bf16", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_smfmac_f32_16x16x64_bf8_bf8", "mnemonic": "v_smfmac_f32_16x16x64_bf8_bf8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 16X16X64 BF8 BF8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 16x64 sparse matrix in the first input by the 64x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in…", "description": "Multiply the 16x64 sparse matrix in the first input by the 64x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.", "syntax": "v_smfmac_f32_16x16x64_bf8_bf8", "operands": [], "dataTypes": [ "f32" ], "semantics": "D = A (sparse 16x64) * B (64x16) + D (16x16)\nEach operand contains a single matrix whose elements are distributed across all lanes of the wave. A single\nmatrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher\nperformance.\nMatrix A is a sparse matrix in BF8 float format, consuming half the physical storage of a dense matrix with\nsame dimensions. Matrix B is a dense matrix in BF8 float format. Matrix D is single-precision float format and\nis both the output and the accumulate input.\n2 out of every 4 elements on the K axis of matrix A are zero. The sparse indexes are used to determine which 2\nelements are zero.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 4 passes.", "sourcePdfPage": 288, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_smfmac_f32_16x16x64_bf8_fp8", "mnemonic": "v_smfmac_f32_16x16x64_bf8_fp8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 16X16X64 BF8 FP8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 16x64 sparse matrix in the first input by the 64x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in…", "description": "Multiply the 16x64 sparse matrix in the first input by the 64x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.", "syntax": "v_smfmac_f32_16x16x64_bf8_fp8", "operands": [], "dataTypes": [ "f32" ], "semantics": "D = A (sparse 16x64) * B (64x16) + D (16x16)\nEach operand contains a single matrix whose elements are distributed across all lanes of the wave. A single\nmatrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher\nperformance.\nMatrix A is a sparse matrix in BF8 float format, consuming half the physical storage of a dense matrix with\nsame dimensions. Matrix B is a dense matrix in FP8 float format. Matrix D is single-precision float format and\nis both the output and the accumulate input.\n2 out of every 4 elements on the K axis of matrix A are zero. The sparse indexes are used to determine which 2\nelements are zero.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 4 passes.", "sourcePdfPage": 288, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_smfmac_f32_16x16x64_f16", "mnemonic": "v_smfmac_f32_16x16x64_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 16X16X64 F16", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 16x64 sparse matrix in the first input by the 64x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in…", "description": "Multiply the 16x64 sparse matrix in the first input by the 64x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.", "syntax": "v_smfmac_f32_16x16x64_f16", "operands": [], "dataTypes": [ "f16", "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_smfmac_f32_16x16x64_fp8_bf8", "mnemonic": "v_smfmac_f32_16x16x64_fp8_bf8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 16X16X64 FP8 BF8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 16x64 sparse matrix in the first input by the 64x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in…", "description": "Multiply the 16x64 sparse matrix in the first input by the 64x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.", "syntax": "v_smfmac_f32_16x16x64_fp8_bf8", "operands": [], "dataTypes": [ "f32" ], "semantics": "D = A (sparse 16x64) * B (64x16) + D (16x16)\nEach operand contains a single matrix whose elements are distributed across all lanes of the wave. A single\nmatrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher\nperformance.\nMatrix A is a sparse matrix in FP8 float format, consuming half the physical storage of a dense matrix with\nsame dimensions. Matrix B is a dense matrix in BF8 float format. Matrix D is single-precision float format and\nis both the output and the accumulate input.\n2 out of every 4 elements on the K axis of matrix A are zero. The sparse indexes are used to determine which 2\nelements are zero.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 4 passes.", "sourcePdfPage": 289, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_smfmac_f32_16x16x64_fp8_fp8", "mnemonic": "v_smfmac_f32_16x16x64_fp8_fp8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 16X16X64 FP8 FP8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 16x64 sparse matrix in the first input by the 64x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in…", "description": "Multiply the 16x64 sparse matrix in the first input by the 64x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.", "syntax": "v_smfmac_f32_16x16x64_fp8_fp8", "operands": [], "dataTypes": [ "f32" ], "semantics": "D = A (sparse 16x64) * B (64x16) + D (16x16)\nEach operand contains a single matrix whose elements are distributed across all lanes of the wave. A single\nmatrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher\nperformance.\nMatrix A is a sparse matrix in FP8 float format, consuming half the physical storage of a dense matrix with\nsame dimensions. Matrix B is a dense matrix in FP8 float format. Matrix D is single-precision float format and\nis both the output and the accumulate input.\n2 out of every 4 elements on the K axis of matrix A are zero. The sparse indexes are used to determine which 2\nelements are zero.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 4 passes.", "sourcePdfPage": 289, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_smfmac_f32_16x16x64bf16", "mnemonic": "v_smfmac_f32_16x16x64bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 16X16X64BF16", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_smfmac_f32_16x16x64bf16", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_smfmac_f32_16x16x64bf8bf8", "mnemonic": "v_smfmac_f32_16x16x64bf8bf8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 16X16X64BF8BF8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_smfmac_f32_16x16x64bf8bf8", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_smfmac_f32_16x16x64bf8fp8", "mnemonic": "v_smfmac_f32_16x16x64bf8fp8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 16X16X64BF8FP8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_smfmac_f32_16x16x64bf8fp8", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_smfmac_f32_16x16x64f16", "mnemonic": "v_smfmac_f32_16x16x64f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 16X16X64F16", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_smfmac_f32_16x16x64f16", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_smfmac_f32_16x16x64fp8bf8", "mnemonic": "v_smfmac_f32_16x16x64fp8bf8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 16X16X64FP8BF8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_smfmac_f32_16x16x64fp8bf8", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_smfmac_f32_16x16x64fp8fp8", "mnemonic": "v_smfmac_f32_16x16x64fp8fp8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 16X16X64FP8FP8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_smfmac_f32_16x16x64fp8fp8", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_smfmac_f32_32x32x16_bf16", "mnemonic": "v_smfmac_f32_32x32x16_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 32X32X16 BF16", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 32x16 sparse matrix in the first input by the 16x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in…", "description": "Multiply the 32x16 sparse matrix in the first input by the 16x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.", "syntax": "v_smfmac_f32_32x32x16_bf16", "operands": [], "dataTypes": [ "f32" ], "semantics": "D = A (sparse 32x16) * B (16x32) + D (32x32)\nEach operand contains a single matrix whose elements are distributed across all lanes of the wave. A single\nmatrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher\nperformance.\nMatrix A is a sparse matrix in BF16 float format, consuming half the physical storage of a dense matrix with\nsame dimensions. Matrix B is a dense matrix in BF16 float format. Matrix D is single-precision float format and\nis both the output and the accumulate input.\n2 out of every 4 elements on the K axis of matrix A are zero. The sparse indexes are used to determine which 2\nelements are zero.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 8 passes.", "sourcePdfPage": 282, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_smfmac_f32_32x32x16_f16", "mnemonic": "v_smfmac_f32_32x32x16_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 32X32X16 F16", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 32x16 sparse matrix in the first input by the 16x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in…", "description": "Multiply the 32x16 sparse matrix in the first input by the 16x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.", "syntax": "v_smfmac_f32_32x32x16_f16", "operands": [], "dataTypes": [ "f16", "f32" ], "semantics": "D = A (sparse 32x16) * B (16x32) + D (32x32)\nEach operand contains a single matrix whose elements are distributed across all lanes of the wave. A single\nmatrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher\nperformance.\nMatrix A is a sparse matrix in half-precision float format, consuming half the physical storage of a dense\nmatrix with same dimensions. Matrix B is a dense matrix in half-precision float format. Matrix D is single-precision float format and is both the output and the accumulate input.\n2 out of every 4 elements on the K axis of matrix A are zero. The sparse indexes are used to determine which 2\nelements are zero.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 8 passes.", "sourcePdfPage": 281, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_smfmac_f32_32x32x16bf16", "mnemonic": "v_smfmac_f32_32x32x16bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 32X32X16BF16", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_smfmac_f32_32x32x16bf16", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_smfmac_f32_32x32x16f16", "mnemonic": "v_smfmac_f32_32x32x16f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 32X32X16F16", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_smfmac_f32_32x32x16f16", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_smfmac_f32_32x32x32_bf16", "mnemonic": "v_smfmac_f32_32x32x32_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 32X32X32 BF16", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 32x32 sparse matrix in the first input by the 32x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in…", "description": "Multiply the 32x32 sparse matrix in the first input by the 32x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.", "syntax": "v_smfmac_f32_32x32x32_bf16", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_smfmac_f32_32x32x32_bf8_bf8", "mnemonic": "v_smfmac_f32_32x32x32_bf8_bf8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 32X32X32 BF8 BF8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 32x32 sparse matrix in the first input by the 32x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in…", "description": "Multiply the 32x32 sparse matrix in the first input by the 32x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.", "syntax": "v_smfmac_f32_32x32x32_bf8_bf8", "operands": [], "dataTypes": [ "f32" ], "semantics": "D = A (sparse 32x32) * B (32x32) + D (32x32)\nEach operand contains a single matrix whose elements are distributed across all lanes of the wave. A single\nmatrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher\nperformance.\nMatrix A is a sparse matrix in BF8 float format, consuming half the physical storage of a dense matrix with\nsame dimensions. Matrix B is a dense matrix in BF8 float format. Matrix D is single-precision float format and\nis both the output and the accumulate input.\n2 out of every 4 elements on the K axis of matrix A are zero. The sparse indexes are used to determine which 2\nelements are zero.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 8 passes.", "sourcePdfPage": 290, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_smfmac_f32_32x32x32_bf8_fp8", "mnemonic": "v_smfmac_f32_32x32x32_bf8_fp8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 32X32X32 BF8 FP8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 32x32 sparse matrix in the first input by the 32x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in…", "description": "Multiply the 32x32 sparse matrix in the first input by the 32x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.", "syntax": "v_smfmac_f32_32x32x32_bf8_fp8", "operands": [], "dataTypes": [ "f32" ], "semantics": "D = A (sparse 32x32) * B (32x32) + D (32x32)\nEach operand contains a single matrix whose elements are distributed across all lanes of the wave. A single\nmatrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher\nperformance.\nMatrix A is a sparse matrix in BF8 float format, consuming half the physical storage of a dense matrix with\nsame dimensions. Matrix B is a dense matrix in FP8 float format. Matrix D is single-precision float format and\nis both the output and the accumulate input.\n2 out of every 4 elements on the K axis of matrix A are zero. The sparse indexes are used to determine which 2\nelements are zero.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 8 passes.", "sourcePdfPage": 290, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_smfmac_f32_32x32x32_f16", "mnemonic": "v_smfmac_f32_32x32x32_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 32X32X32 F16", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 32x32 sparse matrix in the first input by the 32x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in…", "description": "Multiply the 32x32 sparse matrix in the first input by the 32x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.", "syntax": "v_smfmac_f32_32x32x32_f16", "operands": [], "dataTypes": [ "f16", "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_smfmac_f32_32x32x32_fp8_bf8", "mnemonic": "v_smfmac_f32_32x32x32_fp8_bf8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 32X32X32 FP8 BF8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 32x32 sparse matrix in the first input by the 32x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in…", "description": "Multiply the 32x32 sparse matrix in the first input by the 32x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.", "syntax": "v_smfmac_f32_32x32x32_fp8_bf8", "operands": [], "dataTypes": [ "f32" ], "semantics": "D = A (sparse 32x32) * B (32x32) + D (32x32)\nEach operand contains a single matrix whose elements are distributed across all lanes of the wave. A single\nmatrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher\nperformance.\nMatrix A is a sparse matrix in FP8 float format, consuming half the physical storage of a dense matrix with\nsame dimensions. Matrix B is a dense matrix in BF8 float format. Matrix D is single-precision float format and\nis both the output and the accumulate input.\n2 out of every 4 elements on the K axis of matrix A are zero. The sparse indexes are used to determine which 2\nelements are zero.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 8 passes.", "sourcePdfPage": 291, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_smfmac_f32_32x32x32_fp8_fp8", "mnemonic": "v_smfmac_f32_32x32x32_fp8_fp8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 32X32X32 FP8 FP8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 32x32 sparse matrix in the first input by the 32x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in…", "description": "Multiply the 32x32 sparse matrix in the first input by the 32x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.", "syntax": "v_smfmac_f32_32x32x32_fp8_fp8", "operands": [], "dataTypes": [ "f32" ], "semantics": "D = A (sparse 32x32) * B (32x32) + D (32x32)\nEach operand contains a single matrix whose elements are distributed across all lanes of the wave. A single\nmatrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher\nperformance.\nMatrix A is a sparse matrix in FP8 float format, consuming half the physical storage of a dense matrix with\nsame dimensions. Matrix B is a dense matrix in FP8 float format. Matrix D is single-precision float format and\nis both the output and the accumulate input.\n2 out of every 4 elements on the K axis of matrix A are zero. The sparse indexes are used to determine which 2\nelements are zero.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 8 passes.", "sourcePdfPage": 291, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_smfmac_f32_32x32x32bf16", "mnemonic": "v_smfmac_f32_32x32x32bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 32X32X32BF16", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_smfmac_f32_32x32x32bf16", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_smfmac_f32_32x32x32bf8bf8", "mnemonic": "v_smfmac_f32_32x32x32bf8bf8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 32X32X32BF8BF8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_smfmac_f32_32x32x32bf8bf8", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_smfmac_f32_32x32x32bf8fp8", "mnemonic": "v_smfmac_f32_32x32x32bf8fp8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 32X32X32BF8FP8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_smfmac_f32_32x32x32bf8fp8", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_smfmac_f32_32x32x32f16", "mnemonic": "v_smfmac_f32_32x32x32f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 32X32X32F16", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_smfmac_f32_32x32x32f16", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_smfmac_f32_32x32x32fp8bf8", "mnemonic": "v_smfmac_f32_32x32x32fp8bf8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 32X32X32FP8BF8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_smfmac_f32_32x32x32fp8bf8", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_smfmac_f32_32x32x32fp8fp8", "mnemonic": "v_smfmac_f32_32x32x32fp8fp8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 32X32X32FP8FP8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_smfmac_f32_32x32x32fp8fp8", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_smfmac_f32_32x32x64_bf8_bf8", "mnemonic": "v_smfmac_f32_32x32x64_bf8_bf8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 32X32X64 BF8 BF8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 32x64 sparse matrix in the first input by the 64x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in…", "description": "Multiply the 32x64 sparse matrix in the first input by the 64x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.", "syntax": "v_smfmac_f32_32x32x64_bf8_bf8", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_smfmac_f32_32x32x64_bf8_fp8", "mnemonic": "v_smfmac_f32_32x32x64_bf8_fp8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 32X32X64 BF8 FP8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 32x64 sparse matrix in the first input by the 64x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in…", "description": "Multiply the 32x64 sparse matrix in the first input by the 64x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.", "syntax": "v_smfmac_f32_32x32x64_bf8_fp8", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_smfmac_f32_32x32x64_fp8_bf8", "mnemonic": "v_smfmac_f32_32x32x64_fp8_bf8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 32X32X64 FP8 BF8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 32x64 sparse matrix in the first input by the 64x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in…", "description": "Multiply the 32x64 sparse matrix in the first input by the 64x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.", "syntax": "v_smfmac_f32_32x32x64_fp8_bf8", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_smfmac_f32_32x32x64_fp8_fp8", "mnemonic": "v_smfmac_f32_32x32x64_fp8_fp8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 32X32X64 FP8 FP8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 32x64 sparse matrix in the first input by the 64x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in…", "description": "Multiply the 32x64 sparse matrix in the first input by the 64x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.", "syntax": "v_smfmac_f32_32x32x64_fp8_fp8", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_smfmac_f32_32x32x64bf8bf8", "mnemonic": "v_smfmac_f32_32x32x64bf8bf8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 32X32X64BF8BF8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_smfmac_f32_32x32x64bf8bf8", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_smfmac_f32_32x32x64bf8fp8", "mnemonic": "v_smfmac_f32_32x32x64bf8fp8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 32X32X64BF8FP8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_smfmac_f32_32x32x64bf8fp8", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_smfmac_f32_32x32x64fp8bf8", "mnemonic": "v_smfmac_f32_32x32x64fp8bf8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 32X32X64FP8BF8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_smfmac_f32_32x32x64fp8bf8", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_smfmac_f32_32x32x64fp8fp8", "mnemonic": "v_smfmac_f32_32x32x64fp8fp8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC F32 32X32X64FP8FP8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_smfmac_f32_32x32x64fp8fp8", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_smfmac_i32_16x16x128_i8", "mnemonic": "v_smfmac_i32_16x16x128_i8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC I32 16X16X128 I8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 16x128 sparse matrix in the first input by the 128x16 matrix in the second input and accumulate the result into the 16x16 matrix stored…", "description": "Multiply the 16x128 sparse matrix in the first input by the 128x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.", "syntax": "v_smfmac_i32_16x16x128_i8", "operands": [], "dataTypes": [ "i32", "i8" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_smfmac_i32_16x16x128i8", "mnemonic": "v_smfmac_i32_16x16x128i8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC I32 16X16X128I8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "AMDGPU VOP3P matrix instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_smfmac_i32_16x16x128i8", "operands": [], "dataTypes": [ "i32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_smfmac_i32_16x16x64_i8", "mnemonic": "v_smfmac_i32_16x16x64_i8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC I32 16X16X64 I8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 16x64 sparse matrix in the first input by the 64x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in…", "description": "Multiply the 16x64 sparse matrix in the first input by the 64x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.", "syntax": "v_smfmac_i32_16x16x64_i8", "operands": [], "dataTypes": [ "i32", "i8" ], "semantics": "D = A (sparse 16x64) * B (64x16) + D (16x16)\nEach operand contains a single matrix whose elements are distributed across all lanes of the wave. A single\nmatrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher\nperformance.\nMatrix A is a sparse matrix in signed 8-bit integer format, consuming half the physical storage of a dense\nmatrix with same dimensions. Matrix B is a dense matrix in signed 8-bit integer format. Matrix D is signed 32-\nbit integer format and is both the output and the accumulate input.\n2 out of every 4 elements on the K axis of matrix A are zero. The sparse indexes are used to determine which 2\nelements are zero.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 4 passes.", "sourcePdfPage": 283, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_smfmac_i32_16x16x64i8", "mnemonic": "v_smfmac_i32_16x16x64i8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC I32 16X16X64I8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "AMDGPU VOP3P matrix instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_smfmac_i32_16x16x64i8", "operands": [], "dataTypes": [ "i32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_smfmac_i32_32x32x32_i8", "mnemonic": "v_smfmac_i32_32x32x32_i8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC I32 32X32X32 I8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 32x32 sparse matrix in the first input by the 32x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in…", "description": "Multiply the 32x32 sparse matrix in the first input by the 32x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.", "syntax": "v_smfmac_i32_32x32x32_i8", "operands": [], "dataTypes": [ "i32", "i8" ], "semantics": "D = A (sparse 32x32) * B (32x32) + D (32x32)\nEach operand contains a single matrix whose elements are distributed across all lanes of the wave. A single\nmatrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher\nperformance.\nMatrix A is a sparse matrix in signed 8-bit integer format, consuming half the physical storage of a dense\nmatrix with same dimensions. Matrix B is a dense matrix in signed 8-bit integer format. Matrix D is signed 32-\nbit integer format and is both the output and the accumulate input.\n2 out of every 4 elements on the K axis of matrix A are zero. The sparse indexes are used to determine which 2\nelements are zero.", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "This instruction performs 8 passes.", "sourcePdfPage": 283, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_smfmac_i32_32x32x32i8", "mnemonic": "v_smfmac_i32_32x32x32i8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC I32 32X32X32I8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "AMDGPU VOP3P matrix instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_smfmac_i32_32x32x32i8", "operands": [], "dataTypes": [ "i32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_smfmac_i32_32x32x64_i8", "mnemonic": "v_smfmac_i32_32x32x64_i8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC I32 32X32X64 I8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "Multiply the 32x64 sparse matrix in the first input by the 64x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in…", "description": "Multiply the 32x64 sparse matrix in the first input by the 64x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.", "syntax": "v_smfmac_i32_32x32x64_i8", "operands": [], "dataTypes": [ "i32", "i8" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_smfmac_i32_32x32x64i8", "mnemonic": "v_smfmac_i32_32x32x64i8", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SMFMAC I32 32X32X64I8", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "AMDGPU VOP3P matrix instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_smfmac_i32_32x32x64i8", "operands": [], "dataTypes": [ "i32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_sqrt_bf16", "mnemonic": "v_sqrt_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SQRT BF16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_sqrt_bf16", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_sqrt_f16", "mnemonic": "v_sqrt_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SQRT F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate the square root of the half-precision float input using IEEE rules and store the result into a vector register.", "description": "Calculate the square root of the half-precision float input using IEEE rules and store the result into a vector register.", "syntax": "v_sqrt_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.f16 = sqrt(S0.f16)", "example": "V_SQRT_F16(0xfc00) => 0xfe00 // sqrt(-INF) = NAN\nV_SQRT_F16(0x8000) => 0x8000 // sqrt(-0.0) = -0\nV_SQRT_F16(0x0000) => 0x0000 // sqrt(+0.0) = +0\nV_SQRT_F16(0x4400) => 0x4000 // sqrt(+4.0) = +2.0", "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "1ULP accuracy, denormals are supported.", "sourcePdfPage": 205, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_sqrt_f32", "mnemonic": "v_sqrt_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SQRT F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate the square root of the single-precision float input using IEEE rules and store the result into a vector register.", "description": "Calculate the square root of the single-precision float input using IEEE rules and store the result into a vector register.", "syntax": "v_sqrt_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.f32 = sqrt(S0.f32)", "example": "V_SQRT_F32(0xff800000) => 0xffc00000 // sqrt(-INF) = NAN\nV_SQRT_F32(0x80000000) => 0x80000000 // sqrt(-0.0) = -0\nV_SQRT_F32(0x00000000) => 0x00000000 // sqrt(+0.0) = +0\nV_SQRT_F32(0x40800000) => 0x40000000 // sqrt(+4.0) = +2.0", "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "1ULP accuracy, denormals are flushed.", "sourcePdfPage": 198, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_sqrt_f64", "mnemonic": "v_sqrt_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SQRT F64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate the square root of the double-precision float input using IEEE rules and store the result into a vector register.", "description": "Calculate the square root of the double-precision float input using IEEE rules and store the result into a vector register.", "syntax": "v_sqrt_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "D0.f64 = sqrt(S0.f64)", "example": "v_sqrt_f64 v[5:6], -1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "This opcode has (2**29)ULP accuracy and supports denormals.", "sourcePdfPage": 198, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_sub_co_u32", "mnemonic": "v_sub_co_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SUB CO U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Subtract the second unsigned 32-bit integer input from the first input, store the result into a vector register and store the carry-out mask into a…", "description": "Subtract the second unsigned 32-bit integer input from the first input, store the result into a vector register and store the carry-out mask into a scalar register.", "syntax": "v_sub_co_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "tmp = S0.u32 - S1.u32;\nVCC.u64[laneId] = S1.u32 > S0.u32 ? 1'1U : 1'0U;\n// VCC is an UNSIGNED overflow/carry-out for V_SUBB_CO_U32.\nD0.u32 = tmp.u32", "example": "v_sub_co_u32 v5, s6, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "In VOP3 the VCC destination may be an arbitrary SGPR-pair. Supports saturation (unsigned 32-bit integer domain).", "sourcePdfPage": 175, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_sub_f16", "mnemonic": "v_sub_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SUB F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Subtract the second floating point input from the first input and store the result into a vector register.", "description": "Subtract the second floating point input from the first input and store the result into a vector register.", "syntax": "v_sub_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.f16 = S0.f16 - S1.f16", "example": "v_sub_f16 v5, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "0.5ULP precision. Supports denormals, round mode, exception flags and saturation.", "sourcePdfPage": 177, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_sub_f32", "mnemonic": "v_sub_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SUB F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Per-lane single-precision floating-point subtract.", "description": "Subtract the second floating point input from the first input and store the result into a vector register.", "syntax": "v_sub_f32 VDST, S0, S1", "operands": [ { "name": "VDST", "desc": "Destination VGPR" }, { "name": "S0", "desc": "Minuend" }, { "name": "S1", "desc": "Subtrahend" } ], "dataTypes": [ "f32" ], "semantics": "VDST[lane] = S0[lane].f32 - S1[lane].f32 for each active lane.", "example": "v_sub_f32 v2, v0, v1 // per-lane v2 = v0 - v1", "exampleSource": null, "encoding": { "format": "VOP2", "widthBits": 32 }, "executionUnit": "Vector ALU", "registerClasses": [ "VGPR" ], "memorySegment": null, "supportedTargets": [ "gfx942", "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_sub_i16", "mnemonic": "v_sub_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SUB I16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Subtract the second signed 16-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support.", "description": "Subtract the second signed 16-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support.", "syntax": "v_sub_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "D0.i16 = S0.i16 - S1.i16", "example": null, "exampleSource": null, "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "Supports saturation (signed 16-bit integer domain).", "sourcePdfPage": 368, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_sub_i32", "mnemonic": "v_sub_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SUB I32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Subtract the second signed 32-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support.", "description": "Subtract the second signed 32-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support.", "syntax": "v_sub_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa" ] }, { "id": "amdgpu.v_sub_nc_i16", "mnemonic": "v_sub_nc_i16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SUB NC I16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Subtract the second signed 16-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support.", "description": "Subtract the second signed 16-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support.", "syntax": "v_sub_nc_i16", "operands": [], "dataTypes": [ "i16" ], "semantics": "", "example": "v_sub_nc_i16 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_sub_nc_i32", "mnemonic": "v_sub_nc_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SUB NC I32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Subtract the second signed 32-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support.", "description": "Subtract the second signed 32-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support.", "syntax": "v_sub_nc_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "", "example": "v_sub_nc_i32 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_sub_nc_u16", "mnemonic": "v_sub_nc_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SUB NC U16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Subtract the second unsigned 16-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support.", "description": "Subtract the second unsigned 16-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support.", "syntax": "v_sub_nc_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "", "example": "v_sub_nc_u16 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_sub_nc_u64", "mnemonic": "v_sub_nc_u64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SUB NC U64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP2 vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_sub_nc_u64", "operands": [], "dataTypes": [ "u64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_sub_u16", "mnemonic": "v_sub_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SUB U16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Subtract the second unsigned 16-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support.", "description": "Subtract the second unsigned 16-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support.", "syntax": "v_sub_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "D0.u16 = S0.u16 - S1.u16", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "Supports saturation (unsigned 16-bit integer domain).", "sourcePdfPage": 179, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_sub_u32", "mnemonic": "v_sub_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SUB U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Subtract the second unsigned 32-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support.", "description": "Subtract the second unsigned 32-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support.", "syntax": "v_sub_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "D0.u32 = S0.u32 - S1.u32", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "Supports saturation (unsigned 32-bit integer domain).", "sourcePdfPage": 183, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_subb_co_u32", "mnemonic": "v_subb_co_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SUBB CO U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Subtract the second unsigned 32-bit integer input from the first input, subtract a bit from the carry-in mask, store the result into a vector…", "description": "Subtract the second unsigned 32-bit integer input from the first input, subtract a bit from the carry-in mask, store the result into a vector register and store the carry-out mask into a scalar register.", "syntax": "v_subb_co_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "tmp = S0.u32 - S1.u32 - VCC.u64[laneId].u32;\nVCC.u64[laneId] = 64'U(S1.u32) + VCC.u64[laneId].u64 > 64'U(S0.u32) ? 1'1U : 1'0U;\n// VCC is an UNSIGNED overflow/carry-out for V_SUBB_CO_U32.\nD0.u32 = tmp.u32", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "In VOP3 the VCC destination may be an arbitrary SGPR-pair, and the VCC source comes from the SGPR-pair at S2.u. Supports saturation (unsigned 32-bit integer domain).", "sourcePdfPage": 176, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_subb_u32", "mnemonic": "v_subb_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SUBB U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP2 vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_subb_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_subbrev_co_u32", "mnemonic": "v_subbrev_co_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SUBBREV CO U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Subtract the first unsigned 32-bit integer input from the second input, subtract a bit from the carry-in mask, store the result into a vector…", "description": "Subtract the first unsigned 32-bit integer input from the second input, subtract a bit from the carry-in mask, store the result into a vector register and store the carry-out mask into a scalar register.", "syntax": "v_subbrev_co_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "tmp = S1.u32 - S0.u32 - VCC.u64[laneId].u32;\nVCC.u64[laneId] = 64'U(S0.u32) + VCC.u64[laneId].u64 > 64'U(S1.u32) ? 1'1U : 1'0U;\n// VCC is an UNSIGNED overflow/carry-out for V_SUBB_CO_U32.\nD0.u32 = tmp.u32", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "In VOP3 the VCC destination may be an arbitrary SGPR-pair, and the VCC source comes from the SGPR-pair at S2.u. Supports saturation (unsigned 32-bit integer domain).", "sourcePdfPage": 177, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_subbrev_u32", "mnemonic": "v_subbrev_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SUBBREV U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP2 vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_subbrev_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_subrev_co_u32", "mnemonic": "v_subrev_co_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SUBREV CO U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Subtract the first unsigned 32-bit integer input from the second input, store the result into a vector register and store the carry-out mask into a…", "description": "Subtract the first unsigned 32-bit integer input from the second input, store the result into a vector register and store the carry-out mask into a scalar register.", "syntax": "v_subrev_co_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "tmp = S1.u32 - S0.u32;\nVCC.u64[laneId] = S0.u32 > S1.u32 ? 1'1U : 1'0U;\n// VCC is an UNSIGNED overflow/carry-out for V_SUBB_CO_U32.\nD0.u32 = tmp.u32", "example": "v_subrev_co_u32 v5, s6, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "In VOP3 the VCC destination may be an arbitrary SGPR-pair. Supports saturation (unsigned 32-bit integer domain).", "sourcePdfPage": 176, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_subrev_f16", "mnemonic": "v_subrev_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SUBREV F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Subtract the first floating point input from the second input and store the result into a vector register.", "description": "Subtract the first floating point input from the second input and store the result into a vector register.", "syntax": "v_subrev_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.f16 = S1.f16 - S0.f16", "example": "v_subrev_f16 v5, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "0.5ULP precision. Supports denormals, round mode, exception flags and saturation.", "sourcePdfPage": 178, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_subrev_f32", "mnemonic": "v_subrev_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SUBREV F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Subtract the first floating point input from the second input and store the result into a vector register.", "description": "Subtract the first floating point input from the second input and store the result into a vector register.", "syntax": "v_subrev_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.f32 = S1.f32 - S0.f32", "example": "v_subrev_f32 v5, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "0.5ULP precision, denormals are supported.", "sourcePdfPage": 170, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_subrev_i32", "mnemonic": "v_subrev_i32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SUBREV I32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP2 vector instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_subrev_i32", "operands": [], "dataTypes": [ "i32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_subrev_u16", "mnemonic": "v_subrev_u16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SUBREV U16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Subtract the first unsigned 16-bit integer input from the second input and store the result into a vector register. No carry-in or carry-out support.", "description": "Subtract the first unsigned 16-bit integer input from the second input and store the result into a vector register. No carry-in or carry-out support.", "syntax": "v_subrev_u16", "operands": [], "dataTypes": [ "u16" ], "semantics": "D0.u16 = S1.u16 - S0.u16", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "Supports saturation (unsigned 16-bit integer domain).", "sourcePdfPage": 180, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_subrev_u32", "mnemonic": "v_subrev_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SUBREV U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Subtract the first unsigned 32-bit integer input from the second input and store the result into a vector register. No carry-in or carry-out support.", "description": "Subtract the first unsigned 32-bit integer input from the second input and store the result into a vector register. No carry-in or carry-out support.", "syntax": "v_subrev_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "D0.u32 = S1.u32 - S0.u32", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": "Supports saturation (unsigned 32-bit integer domain).", "sourcePdfPage": 183, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa" ] }, { "id": "amdgpu.v_swap_b16", "mnemonic": "v_swap_b16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SWAP B16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Swap the values in two vector registers.", "description": "Swap the values in two vector registers.", "syntax": "v_swap_b16", "operands": [], "dataTypes": [ "b16" ], "semantics": "", "example": "v_swap_b16 v5.l, v1.h", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_swap_b32", "mnemonic": "v_swap_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SWAP B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Swap the values in two vector registers.", "description": "Swap the values in two vector registers.", "syntax": "v_swap_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "tmp = D0.b32;\nD0.b32 = S0.b32;\nS0.b32 = tmp", "example": "v_swap_b32 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Input and output modifiers not supported; this is an untyped operation.", "sourcePdfPage": 211, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_swaprel_b32", "mnemonic": "v_swaprel_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V SWAPREL B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Swap the values in two relatively-indexed vector registers.", "description": "Swap the values in two relatively-indexed vector registers.", "syntax": "v_swaprel_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "v_swaprel_b32 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_tanh_bf16", "mnemonic": "v_tanh_bf16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V TANH BF16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_tanh_bf16", "operands": [], "dataTypes": [], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_tanh_f16", "mnemonic": "v_tanh_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V TANH F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP1 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_tanh_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_tanh_f32", "mnemonic": "v_tanh_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V TANH F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_tanh_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_trig_preop_f64", "mnemonic": "v_trig_preop_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V TRIG PREOP F64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Look up a 53-bit segment of 2/PI using an integer segment select in the second input.", "description": "Look up a 53-bit segment of 2/PI using an integer segment select in the second input. Scale the intermediate result by the exponent from the first double-precision float input and store the double-precision float result into a vector register. This operation returns an aligned, double precision segment of 2/PI needed to do trigonometric argument reduction on the floating point input. Multiple segments can be accessed using the first input. Rounding is toward zero. Large floating point inputs (with an exponent > 1968) are scaled to avoid loss of precision through denormalization.", "syntax": "v_trig_preop_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "shift = 32'I(S1[4 : 0].u32) * 53;\nif exponent(S0.f64) > 1077 then\nshift += exponent(S0.f64) - 1077\nendif;\n// (2.0/PI) == 0.{b_1200, b_1199, b_1198, ..., b_1, b_0}\n// b_1200 is the MSB of the fractional part of 2.0/PI\n// Left shift operation indicates which bits are brought\n// into the whole part of the number.\n// Only whole part of result is kept.\nresult = 64'F((1201'B(2.0 / PI)[1200 : 0] << shift.u32) & 1201'0x1fffffffffffff);\nscale = -53 - shift;\nif exponent(S0.f64) >= 1968 then\nscale += 128\nendif;\nD0.f64 = ldexp(result, scale)", "example": "v_trig_preop_f64 v[5:6], -1, -1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "For a more complete treatment of trigonometric argument reduction refer to Argument Reduction for Huge Arguments: Good to the Last Bit, K. C. Ng et.al., March 1992, available online.", "sourcePdfPage": 365, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_trunc_f16", "mnemonic": "v_trunc_f16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V TRUNC F16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Compute the integer part of a half-precision float input using round toward zero semantics and store the result in floating point format into a…", "description": "Compute the integer part of a half-precision float input using round toward zero semantics and store the result in floating point format into a vector register.", "syntax": "v_trunc_f16", "operands": [], "dataTypes": [ "f16" ], "semantics": "D0.f16 = trunc(S0.f16)", "example": "v_trunc_f16 v5.l, s1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 208, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_trunc_f32", "mnemonic": "v_trunc_f32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V TRUNC F32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Compute the integer part of a single-precision float input using round toward zero semantics and store the result in floating point format into a…", "description": "Compute the integer part of a single-precision float input using round toward zero semantics and store the result in floating point format into a vector register.", "syntax": "v_trunc_f32", "operands": [], "dataTypes": [ "f32" ], "semantics": "D0.f32 = trunc(S0.f32)", "example": "v_trunc_f32 v5, v1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 194, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_trunc_f64", "mnemonic": "v_trunc_f64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V TRUNC F64", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Compute the integer part of a double-precision float input using round toward zero semantics and store the result in floating point format into a…", "description": "Compute the integer part of a double-precision float input using round toward zero semantics and store the result in floating point format into a vector register.", "syntax": "v_trunc_f64", "operands": [], "dataTypes": [ "f64" ], "semantics": "D0.f64 = trunc(S0.f64)", "example": "v_trunc_f64 v[5:6], -1", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP1" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": 192, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_wmma_ld_scale16_paired_b64", "mnemonic": "v_wmma_ld_scale16_paired_b64", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V WMMA LD SCALE16 PAIRED B64", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "AMDGPU VOP3P matrix instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_wmma_ld_scale16_paired_b64", "operands": [], "dataTypes": [ "b64" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_wmma_ld_scale_paired_b32", "mnemonic": "v_wmma_ld_scale_paired_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V WMMA LD SCALE PAIRED B32", "category": "Vector Packed Arithmetic", "instructionClass": "matrix", "summary": "AMDGPU VOP3P matrix instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_wmma_ld_scale_paired_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP3P" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_writelane_b32", "mnemonic": "v_writelane_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V WRITELANE B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Write the scalar value in the first input into the specified lane of a vector register where the lane select is in the second input.", "description": "Write the scalar value in the first input into the specified lane of a vector register where the lane select is in the second input.", "syntax": "v_writelane_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "v_writelane_b32 v5, s1, s2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_xad_u32", "mnemonic": "v_xad_u32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V XAD U32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate bitwise XOR of the first two vector inputs, then add the third vector input to the intermediate result, then store the final result into a…", "description": "Calculate bitwise XOR of the first two vector inputs, then add the third vector input to the intermediate result, then store the final result into a vector register.", "syntax": "v_xad_u32", "operands": [], "dataTypes": [ "u32" ], "semantics": "D0.u32 = (S0.u32 ^ S1.u32) + S2.u32", "example": "v_xad_u32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "No carryin/carryout and no saturation. This opcode is designed to help accelerate the SHA256 hash algorithm.", "sourcePdfPage": 353, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_xnor_b32", "mnemonic": "v_xnor_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V XNOR B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate bitwise XNOR on two vector inputs and store the result into a vector register.", "description": "Calculate bitwise XNOR on two vector inputs and store the result into a vector register.", "syntax": "v_xnor_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.u32 = ~(S0.u32 ^ S1.u32)", "example": "v_xnor_b32 v5, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Input and output modifiers not supported.", "sourcePdfPage": 185, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_xor3_b32", "mnemonic": "v_xor3_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V XOR3 B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate the bitwise XOR of three vector inputs and store the result into a vector register.", "description": "Calculate the bitwise XOR of three vector inputs and store the result into a vector register.", "syntax": "v_xor3_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "", "example": "v_xor3_b32 v5, v1, v2, s3", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_xor_b16", "mnemonic": "v_xor_b16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V XOR B16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate bitwise XOR on two vector inputs and store the result into a vector register.", "description": "Calculate bitwise XOR on two vector inputs and store the result into a vector register.", "syntax": "v_xor_b16", "operands": [], "dataTypes": [ "b16" ], "semantics": "", "example": "v_xor_b16 v5, v1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP3" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage", "amd-machine-readable-isa", "llvm-mc-amdgpu-tests" ] }, { "id": "amdgpu.v_xor_b16_fake16", "mnemonic": "v_xor_b16_fake16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V XOR B16 FAKE16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_xor_b16_fake16", "operands": [], "dataTypes": [ "b16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_xor_b16_t16", "mnemonic": "v_xor_b16_t16", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V XOR B16 T16", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)", "description": "", "syntax": "v_xor_b16_t16", "operands": [], "dataTypes": [ "b16" ], "semantics": "", "example": null, "exampleSource": null, "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [], "unsupportedTargets": [], "architecturalNotes": null, "sourcePdfPage": null, "sourceIds": [ "llvm-amdgpu-usage" ] }, { "id": "amdgpu.v_xor_b32", "mnemonic": "v_xor_b32", "architecture": "AMDGPU", "vendor": "AMD", "processorClass": "gpu", "isaLayer": "native", "executionModel": "Wavefront-based SIMT/SIMD", "full_name": "V XOR B32", "category": "Vector Arithmetic", "instructionClass": "vector", "summary": "Calculate bitwise XOR on two vector inputs and store the result into a vector register.", "description": "Calculate bitwise XOR on two vector inputs and store the result into a vector register.", "syntax": "v_xor_b32", "operands": [], "dataTypes": [ "b32" ], "semantics": "D0.u32 = (S0.u32 ^ S1.u32)", "example": "v_xor_b32 v5, -1, v2", "exampleSource": "llvm-mc-amdgpu-tests", "encoding": { "format": "VOP2" }, "executionUnit": "", "registerClasses": [], "memorySegment": null, "supportedTargets": [ "gfx1100" ], "unsupportedTargets": [], "architecturalNotes": "Input and output modifiers not supported.", "sourcePdfPage": 174, "sourceIds": [ "llvm-amdgpu-usage", "amd-instinct-mi300-isa", "llvm-mc-amdgpu-tests" ] } ] }