v_add_u32 GPU Native ISA AMD Vector

Vector Arithmetic

v_add_u32 VDST, S0, S1

Per-lane add of two 32-bit unsigned vector operands.

Encoding

Binary Layout (AMD CDNA 4)
0
31
110100
30:25
VDST
24:17
VSRC1
16:9
SRC0
8:0
 

The ENC_VOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 52 in OP rebuilds 0x68000000, an identifier AMD lists for this encoding. The same in the other 3 generations that define it.

Format VOP2
Width 32 bits
Opcode 52
Identifier 0x68000000
Execution Unit Vector ALU
Register Classes VGPR

Operands

  • VDST
    Destination VGPR
  • S0
    First source (VGPR/SGPR/constant)
  • S1
    Second source VGPR

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Integer Addition ↗
equivalent with restrictions
add (PTX)

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Add two unsigned 32-bit integer inputs and store the result into a vector register. No carry-in or carry-out support.

Semantics

VDST[lane] = S0[lane].u32 + S1[lane].u32 for each active lane, per the EXEC mask.

Example

v_add_u32  v2, v0, v1   // per-lane v2 = v0 + v1

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources