v_add_u32 GPU Native ISA AMD Vector

V ADD U32 Vector Arithmetic

v_add_u32 VDST, S0, S1

Per-lane add of two 32-bit unsigned vector operands.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP2) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP2
Width 32 bits
Execution Unit Vector ALU
Register Classes VGPR

Operands

  • VDST
    Destination VGPR
  • S0
    First source (VGPR/SGPR/constant)
  • S1
    Second source VGPR

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Integer Addition ↗
equivalent with restrictions
add (PTX)

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Add two unsigned 32-bit integer inputs and store the result into a vector register. No carry-in or carry-out support.

Semantics

VDST[lane] = S0[lane].u32 + S1[lane].u32 for each active lane, per the EXEC mask.

Example

v_add_u32  v2, v0, v1   // per-lane v2 = v0 + v1

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources