v_accvgpr_mov_b32 GPU Native ISA AMD Vector

Vector Arithmetic

v_accvgpr_mov_b32

Move data from one accumulator register to another accumulator register.

Encoding

Binary Layout (AMD CDNA 4)
0111111
31:25
VDST
24:17
01010010
16:9
SRC0
8:0
 

The ENC_VOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 82 in OP rebuilds 0x7E00A400, an identifier AMD lists for this encoding. The same in the other 2 generations that define it.

Format VOP1
Width 32 bits
Opcode 82
Identifier 0x7E00A400

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_ACCVGPR, FMT_NUM_B32)
  • SRC0
    Read. N/A Data format: N/A (OPR_SRC_ACCVGPR, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP1 encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Example

v_accvgpr_mov_b32 a1, a2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (mai-gfx90a.s). Not from an AMD document, and not authored here.

Sources