v_accvgpr_read_b32 GPU Native ISA AMD Vector

Vector Arithmetic

v_accvgpr_read_b32

AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)

Also written as v_accvgpr_read. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

AMD's machine-readable ISA specification lists this instruction as v_accvgpr_read. The operands and layout below are from that entry.

Binary Layout (AMD CDNA 4)
NEG
63:61
OP_SEL_HI[1:0]
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110100111
31:23
1011000
22:16
CLAMP
15
OP_SEL_HI[2]
14
OP_SEL
13:11
NEG_HI
10:8
VDST
7:0
 

The ENC_VOP3P layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 88 in OP rebuilds 0x00000000D3D80000, an identifier AMD lists for this encoding. The same in the other 3 generations that define it.

Format VOP3
Width 64 bits
Opcode 88
Identifier 0x00000000D3D80000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR, FMT_NUM_B32)
  • SRC0
    Read. N/A Data format: N/A (OPR_SRC_ACCVGPR, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3P encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Example

v_accvgpr_read_b32 v2, a0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (mai-gfx90a.s). Not from an AMD document, and not authored here.

Sources