v_ashrrev_i32 GPU Native ISA AMD Vector

Vector Arithmetic

v_ashrrev_i32

Given a shift count in the first vector input, calculate the arithmetic shift right (preserving sign bit) of the second vector input and store the…

Encoding

Binary Layout (AMD CDNA 5)
0
31
011010
30:25
VDST
24:17
VSRC1
16:9
SRC0
8:0
 

The ENC_VOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 26 in OP rebuilds 0x34000000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 17), AMD CDNA 3 (opcode 17), AMD CDNA 2 (opcode 17), AMD CDNA 1 (opcode 17), AMD RDNA 2 (opcode 24), AMD RDNA 1 (opcode 24). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format VOP2
Width 32 bits
Opcode 26
Identifier 0x34000000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Signed 32-bit integral data. (OPR_VGPR, FMT_NUM_I32)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: Unsigned 32-bit integral data. (OPR_SRC, FMT_NUM_U32)
  • VSRC1
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Signed 32-bit integral data. (OPR_VGPR, FMT_NUM_I32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP2 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related PTX Concepts

Arithmetic Shift Right ↗
equivalent with restrictions
shr (PTX)

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Given a shift count in the first vector input, calculate the arithmetic shift right (preserving sign bit) of the second vector input and store the result into a vector register.

Semantics

D0.i32 = (S1.i32 >> S0[4 : 0].u32)

Example

v_ashrrev_i32 v5, -1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources