v_ashrrev_i32 GPU Native ISA AMD Vector

V ASHRREV I32 Vector Arithmetic

v_ashrrev_i32

Given a shift count in the first vector input, calculate the arithmetic shift right (preserving sign bit) of the second vector input and store the…

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP2) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP2
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related PTX Concepts

Arithmetic Shift Right ↗
equivalent with restrictions
shr (PTX)

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Given a shift count in the first vector input, calculate the arithmetic shift right (preserving sign bit) of the second vector input and store the result into a vector register.

Semantics

D0.i32 = (S1.i32 >> S0[4 : 0].u32)

Example

v_ashrrev_i32 v5, -1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources