shr GPU Virtual ISA NVIDIA

Shift Right Logic & Shift

shr.type d, a, b;

Shift bits right, arithmetic or logical depending on the operand's signedness.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding — the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 1.0
Minimum Target sm_10

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations — each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
shr.type d, a, b; s16, s32, s64, u16, u32, u64 sm_10 Right shift: arithmetic (sign-extending) for signed types, logical for unsigned types.

Operands

  • d
    Destination register
  • a
    Value to shift
  • b
    Shift amount (u32)

At a Glance

Data Types s16, s32, s64, u16, u32, u64

Reference

NVIDIA PTX ISA

Semantics

d = a >> b.

Sources