shl GPU Virtual ISA NVIDIA

Shift Left Logic and Shift Instructions

shl.type d, a, b;

Shift bits left, filling with zero.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 1.0
Minimum Target sm_10

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
shl.type d, a, b; b16, b32, b64 sm_10 Logical left shift by an unsigned shift amount b.

Operands

  • d
    Destination register
  • a
    Value to shift
  • b
    Shift amount (u32)

At a Glance

Data Types b16, b32, b64

Related AMDGPU Concepts

Logical Shift Left ↗
equivalent with restrictions
v_lshlrev_b32 (AMDGPU)
s_lshl_b32 (AMDGPU)

Related

More in Logic and Shift Instructions

Reference

NVIDIA PTX ISA

Description

Shift a left by the amount specified by unsigned 32-bit value in b.

Semantics

d = a << b.

Sources