not GPU Virtual ISA NVIDIA

Bitwise NOT Logic and Shift Instructions

not.type d, a;

Bitwise complement of an operand.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 1.0
Minimum Target sm_10

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
not.type d, a; b16, b32, b64, pred sm_10 Bitwise complement, including a predicate form.

Operands

  • d
    Destination register
  • a
    Source operand

At a Glance

Data Types b16, b32, b64, pred

Related AMDGPU Concepts

Bitwise NOT ↗
equivalent with restrictions
v_not_b32 (AMDGPU)
s_not_b32 (AMDGPU)

Related

More in Logic and Shift Instructions

Reference

NVIDIA PTX ISA

Description

Invert the bits in a.

Semantics

d = ~a (bitwise).

Examples

not.b32  mask,mask;
not.pred  p,q;

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources