Bitwise NOT Logic & Shift
Compute the bitwise complement of an operand.
Vendor-Neutral Definition
d = ~a, evaluated bit-by-bit at the operand's width.
⚠️ Cross-vendor mappings describe semantic relationships and are not guaranteed one-to-one compiler
translations.
equivalent with restrictions
Both compute the bitwise complement of an operand; AMDGPU splits scalar and vector forms where PTX has one generic not.
| Property | NVIDIA PTX | AMDGPU |
|---|---|---|
| Instruction | not | v_not_b32, s_not_b32 |
| ISA Layer | Virtual | Native |
| Data Types | b16, b32, b64, pred | b32 |
| Version / Target Introduced | PTX ISA 1.0 | gfx1100, gfx1100 |
Important Differences
- AMDGPU's s_not_b32 additionally sets SCC to indicate a nonzero result - a side effect PTX's not has no equivalent for.
- PTX's not also has a .pred form operating on a single predicate bit; AMDGPU's predicate/EXEC-mask negation is a distinct operation from the general-purpose scalar/vector not instructions cited here.
Source Evidence
- Parallel Thread Execution ISA ↗ - NVIDIA Corporation
- "AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗ - Advanced Micro Devices, Inc.
Verification method: documentation