Logical Shift Right Logic & Shift

Shift an unsigned operand's bits right by a given count, filling vacated high bits with zero.

Vendor-Neutral Definition

d = a >> b (unsigned), with zero-fill on the high end.
⚠️ Cross-vendor mappings describe semantic relationships and are not guaranteed one-to-one compiler translations.
equivalent with restrictions Both shift right with zero-fill for unsigned operands; PTX's shr covers this only when its type modifier is unsigned (u16/u32/u64) - see the arithmetic-shift-right concept for its signed forms.
Property NVIDIA PTX AMDGPU
Instruction shr v_lshrrev_b32, s_lshr_b32
ISA Layer Virtual Native
Data Types s16, s32, s64, u16, u32, u64 b32
Version / Target Introduced PTX ISA 1.0 gfx1100, gfx1100

Important Differences

  • PTX's shr is ONE family whose signedness (and therefore logical vs. arithmetic behavior) is selected by a '.u*' or '.s*' type modifier per instantiation; AMDGPU exposes logical and arithmetic shift-right as separate, differently-named instructions (v_lshrrev_b32 vs v_ashrrev_i32).
  • AMDGPU's vector v_lshrrev_b32 takes the shift amount as SRC0, the reverse of PTX's shr d, a, b operand order.

Source Evidence

Verification method: documentation