Arithmetic Shift Right Logic & Shift

Shift a signed operand's bits right by a given count, filling vacated high bits with the sign bit.

Vendor-Neutral Definition

d = a >> b (signed), with sign-extension on the high end.
⚠️ Cross-vendor mappings describe semantic relationships and are not guaranteed one-to-one compiler translations.
equivalent with restrictions Both shift right with sign-extension for signed operands; PTX's shr covers this only when its type modifier is signed (s16/s32/s64) - see the logical-shift-right concept for its unsigned forms.
Property NVIDIA PTX AMDGPU
Instruction shr v_ashrrev_i32, s_ashr_i32
ISA Layer Virtual Native
Data Types s16, s32, s64, u16, u32, u64 i32
Version / Target Introduced PTX ISA 1.0 gfx1100, gfx1100

Important Differences

  • PTX's shr is ONE family whose signedness is selected by a type modifier; AMDGPU exposes arithmetic shift-right as a separate, differently-named instruction (v_ashrrev_i32) from its logical counterpart (v_lshrrev_b32).
  • AMDGPU's vector v_ashrrev_i32 takes the shift amount as SRC0, the reverse of PTX's shr d, a, b operand order.

Source Evidence

Verification method: documentation