v_cubesc_f32 GPU Native ISA AMD Vector

Vector Arithmetic

v_cubesc_f32

Compute the cubemap S coordinate of a 3D coordinate specified as three single-precision float inputs.

Encoding

Binary Layout (AMD CDNA 5)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110101
31:26
1000001101
25:16
CLAMP
15
OPSEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 525 in OP rebuilds 0x00000000D60D0000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 453, field layout), AMD CDNA 3 (opcode 453, field layout), AMD CDNA 2 (opcode 453, field layout), AMD CDNA 1 (opcode 453, field layout), AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout), AMD RDNA 2 (opcode 325, field layout), AMD RDNA 1 (opcode 325, field layout). The same in AMD RDNA 4.

Format VOP3
Width 64 bits
Opcode 525
Identifier 0x00000000D60D0000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32-bit single-precision floating point value. (OPR_VGPR, FMT_NUM_F32)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 32-bit single-precision floating point value. (OPR_SRC, FMT_NUM_F32)
  • SRC1
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 32-bit single-precision floating point value. (OPR_SRC, FMT_NUM_F32)
  • SRC2
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 32-bit single-precision floating point value. (OPR_SRC, FMT_NUM_F32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Compute the cubemap S coordinate of a 3D coordinate specified as three single-precision float inputs. Store the result in single-precision float format into a vector register.

Semantics

// D0.f = cubemap S coordinate. // XYZ coordinate is given in (S0.f, S1.f, S2.f). // S0.f = x // S1.f = y // S2.f = z if ((abs(S2.f32) >= abs(S0.f32)) && (abs(S2.f32) >= abs(S1.f32))) then if S2.f32 < 0.0F then D0.f32 = -S0.f32 else D0.f32 = S0.f32 endif elsif abs(S1.f32) >= abs(S0.f32) then D0.f32 = S0.f32 else if S0.f32 < 0.0F then D0.f32 = S2.f32 else D0.f32 = -S2.f32 endif endif

Example

v_cubesc_f32 v5, v1, v2, s3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources