v_cvt_f16_f32 GPU Native ISA AMD Vector

V CVT F16 F32 Vector Arithmetic

v_cvt_f16_f32

Convert from a single-precision float input to a half-precision float value and store the result into a vector register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP1) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP1
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

0.5ULP accuracy, supports input modifiers and creates FP16 denormals when appropriate. Flush denorms on output if specified based on DP denorm mode. Output rounding based on DP rounding mode.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

D0.f16 = f32_to_f16(S0.f32)

Example

v_cvt_f16_f32 v5.l, v1

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources