v_bfe_u32 GPU Native ISA AMD Vector

V BFE U32 Vector Arithmetic

v_bfe_u32

Extract an unsigned bitfield from the first input using field offset from the second input and size from the third input, then store the result into…

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP3) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP3
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related PTX Concepts

Bit-Field Extract ↗
equivalent with restrictions
bfe (PTX)

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Extract an unsigned bitfield from the first input using field offset from the second input and size from the third input, then store the result into a vector register.

Semantics

D0.u32 = ((S0.u32 >> S1[4 : 0].u32) & ((1U << S2[4 : 0].u32) - 1U))

Example

v_bfe_u32 v5, v1, v2, s3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources