v_cndmask_b32 GPU Native ISA AMD Vector

Vector Arithmetic

v_cndmask_b32

Copy data from one of two inputs based on the per-lane condition code and store the result into a vector register.

Encoding

Binary Layout (AMD CDNA 5)
0
31
000001
30:25
VDST
24:17
VSRC1
16:9
SRC0
8:0
 

The ENC_VOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 1 in OP rebuilds 0x02000000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 0), AMD CDNA 3 (opcode 0), AMD CDNA 2 (opcode 0), AMD CDNA 1 (opcode 0). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3, AMD RDNA 2, AMD RDNA 1.

Format VOP2
Width 32 bits
Opcode 1
Identifier 0x02000000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32 bits of arbitrary data. (OPR_VGPR, FMT_NUM_B32)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 32 bits of arbitrary data. (OPR_SRC, FMT_NUM_B32)
  • VSRC1
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32 bits of arbitrary data. (OPR_VGPR, FMT_NUM_B32)
  • vcc
    Read. Written in the assembly; this encoding has no field for it. 64-bit vector condition code. Data format: 64-bit mask value, read or written to a consecutive run of GPRs. The first GPR contains the least significant dword of the data. This format is generally used for lane masks and may be truncated to 32 bits when running in wave32 mode. Scalar operands with the M64 format do not have an alignment restriction when running in wave32 mode. (OPR_VCC, FMT_NUM_M64)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP2 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

In VOP3 the VCC source may be a scalar GPR specified in S2. Floating-point modifiers are valid for this instruction if S0 and S1 are 32-bit floating point values. This instruction is suitable for negating or taking the absolute value of a floating-point value.

Related PTX Concepts

Predicated Select ↗
equivalent with restrictions
selp (PTX)

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

D0.u32 = VCC.u64[laneId] ? S1.u32 : S0.u32

Example

v_cndmask_b32 v5, -1, v2, vcc

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources