v_cndmask_b32 GPU Native ISA AMD Vector

V CNDMASK B32 Vector Arithmetic

v_cndmask_b32

Copy data from one of two inputs based on the per-lane condition code and store the result into a vector register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP2) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP2
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

In VOP3 the VCC source may be a scalar GPR specified in S2. Floating-point modifiers are valid for this instruction if S0 and S1 are 32-bit floating point values. This instruction is suitable for negating or taking the absolute value of a floating-point value.

Related PTX Concepts

Predicated Select ↗
equivalent with restrictions
selp (PTX)

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

D0.u32 = VCC.u64[laneId] ? S1.u32 : S0.u32

Example

v_cndmask_b32 v5, -1, v2, vcc

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources