v_cvt_f16_bf8 GPU Native ISA AMD Vector

Vector Arithmetic

v_cvt_f16_bf8

AMDGPU VOP1 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)

Encoding

Binary Layout (AMD CDNA 5)
0111111
31:25
VDST
24:17
unassigned
16
1111000
15:9
SRC0
8:0
 

The ENC_VOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 120 in OP rebuilds 0x7E00F000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. No other generation in the specification defines this instruction.

Format VOP1
Width 32 bits
Opcode 120
Identifier 0x7E00F000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 16-bit half-precision floating point value. (OPR_VGPR, FMT_NUM_F16)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: N/A (OPR_SRC, FMT_NUM_BF8)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Example

v_cvt_f16_bf8 v1, 2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx1250_asm_vop1-fake16.s). Not from an AMD document, and not authored here.

Sources