Vector Arithmetic Instructions
558 AMDGPU instructions in this category - showing 100 per page, page 1 of 6 - click any row for encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Summary |
|---|---|---|---|
| v_accvgpr_mov_b32 | v_accvgpr_mov_b32 | VOP1 | Move data from one accumulator register to another accumulator register. |
| v_accvgpr_read_b32 | v_accvgpr_read_b32 | VOP3 | AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_accvgpr_write_b32 | v_accvgpr_write_b32 | VOP3 | AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_add3_u32 | v_add3_u32 | VOP3 | Add three unsigned inputs and store the result into a vector register. No carry-in or carry-out support. |
| v_add_co_u32 | v_add_co_u32 | VOP2 | Add two unsigned 32-bit integer inputs, store the result into a vector register and store the carry-out mask into a scalar register. |
| v_add_f16 | v_add_f16 | VOP2 | Add two floating point inputs and store the result into a vector register. |
| v_add_f32 | v_add_f32 VDST, S0, S1 | VOP2 | Per-lane single-precision floating-point add. |
| v_add_f64 | v_add_f64 | VOP2 | Add two floating point inputs and store the result into a vector register. |
| v_add_f64_pseudo | v_add_f64_pseudo | VOP2 | AMDGPU VOP2 vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_add_i16 | v_add_i16 | VOP3 | Add two signed 16-bit integer inputs and store the result into a vector register. No carry-in or carry-out support. |
| v_add_i32 | v_add_i32 | VOP2 | Add two signed 32-bit integer inputs and store the result into a vector register. No carry-in or carry-out support. |
| v_add_lshl_u32 | v_add_lshl_u32 | VOP3 | Add the first two integer inputs, then given a shift count in the third input, calculate the logical shift left of the intermediate result, then… |
| v_add_max_i32 | v_add_max_i32 | VOP3 | AMDGPU VOP3 vector instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_add_max_u32 | v_add_max_u32 | VOP3 | AMDGPU VOP3 vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_add_min_i32 | v_add_min_i32 | VOP3 | AMDGPU VOP3 vector instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_add_min_u32 | v_add_min_u32 | VOP3 | AMDGPU VOP3 vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_add_nc_i16 | v_add_nc_i16 | VOP3 | Add two signed 16-bit integer inputs and store the result into a vector register. No carry-in or carry-out support. |
| v_add_nc_i32 | v_add_nc_i32 | VOP3 | Add two signed 32-bit integer inputs and store the result into a vector register. No carry-in or carry-out support. |
| v_add_nc_u16 | v_add_nc_u16 | VOP3 | Add two unsigned 16-bit integer inputs and store the result into a vector register. No carry-in or carry-out support. |
| v_add_nc_u64 | v_add_nc_u64 | VOP2 | AMDGPU VOP2 vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_add_u16 | v_add_u16 | VOP2 | Add two unsigned 16-bit integer inputs and store the result into a vector register. No carry-in or carry-out support. |
| v_add_u32 | v_add_u32 VDST, S0, S1 | VOP2 | Per-lane add of two 32-bit unsigned vector operands. |
| v_addc_co_u32 | v_addc_co_u32 | VOP2 | Add two unsigned 32-bit integer inputs and a bit from a carry-in mask, store the result into a vector register and store the carry-out mask into a… |
| v_addc_u32 | v_addc_u32 | VOP2 | AMDGPU VOP2 vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_alignbit_b32 | v_alignbit_b32 | VOP3 | Align a 64-bit value encoded in the first two inputs to a bit position specified in the third input, then store the result into a 32-bit vector… |
| v_alignbit_b32_opsel | v_alignbit_b32_opsel | VOP3 | AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_alignbyte_b32 | v_alignbyte_b32 | VOP3 | Align a 64-bit value encoded in the first two inputs to a byte position specified in the third input, then store the result into a 32-bit vector… |
| v_alignbyte_b32_fake16 | v_alignbyte_b32_fake16 | VOP3 | AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_alignbyte_b32_opsel | v_alignbyte_b32_opsel | VOP3 | AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_alignbyte_b32_t16 | v_alignbyte_b32_t16 | VOP3 | AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_and_b16 | v_and_b16 | VOP3 | Calculate bitwise AND on two vector inputs and store the result into a vector register. |
| v_and_b16_fake16 | v_and_b16_fake16 | VOP2 | AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_and_b16_t16 | v_and_b16_t16 | VOP2 | AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_and_b32 | v_and_b32 | VOP2 | Calculate bitwise AND on two vector inputs and store the result into a vector register. |
| v_and_or_b32 | v_and_or_b32 | VOP3 | Calculate bitwise AND on the first two vector inputs, then compute the bitwise OR of the intermediate result and the third vector input, then store… |
| v_ashr_i32 | v_ashr_i32 | VOP2 | AMDGPU VOP2 vector instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_ashr_i64 | v_ashr_i64 | VOP3 | AMDGPU VOP3 vector instruction operating on i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_ashr_pk_i8_i32 | v_ashr_pk_i8_i32 | VOP3 | Given two signed 32-bit integers and a shift count, calculate the arithmetic shift right (preserving sign bit) of the two integers, saturate the two… |
| v_ashr_pk_u8_i32 | v_ashr_pk_u8_i32 | VOP3 | Given two signed 32-bit integers and a shift count, calculate the arithmetic shift right (preserving sign bit) of the two integers, saturate the two… |
| v_ashrrev_i16 | v_ashrrev_i16 | VOP2 | Given a shift count in the first vector input, calculate the arithmetic shift right (preserving sign bit) of the second vector input and store the… |
| v_ashrrev_i32 | v_ashrrev_i32 | VOP2 | Given a shift count in the first vector input, calculate the arithmetic shift right (preserving sign bit) of the second vector input and store the… |
| v_ashrrev_i64 | v_ashrrev_i64 | VOP3 | Given a shift count in the first vector input, calculate the arithmetic shift right (preserving sign bit) of the second vector input and store the… |
| v_bfe_i32 | v_bfe_i32 | VOP3 | Extract a signed bitfield from the first input using field offset from the second input and size from the third input, then store the result into a… |
| v_bfe_u32 | v_bfe_u32 | VOP3 | Extract an unsigned bitfield from the first input using field offset from the second input and size from the third input, then store the result into… |
| v_bfi_b32 | v_bfi_b32 | VOP3 | Overwrite a bitfield in the third input with a bitfield from the second input using a mask from the first input, then store the result into a vector… |
| v_bfm_b32 | v_bfm_b32 | VOP2 | Calculate a bitfield mask given a field offset and size and store the result into a vector register. |
| v_bfrev_b32 | v_bfrev_b32 | VOP1 | Reverse the order of bits in a vector input and store the result into a vector register. |
| v_bitop3_b16 | v_bitop3_b16 | VOP3 | Calculate the generic bitwise operation of three 16-bit vector inputs using a truth table encoded in the instruction and store the result into a… |
| v_bitop3_b16_gfx1250 | v_bitop3_b16_gfx1250 | VOP3 | AMDGPU VOP3 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_bitop3_b32 | v_bitop3_b32 | VOP3 | Calculate the generic bitwise operation of three 32-bit vector inputs using a truth table encoded in the instruction and store the result into a… |
| v_ceil_f16 | v_ceil_f16 | VOP1 | Round the half-precision float input up to next integer and store the result in floating point format into a vector register. |
| v_ceil_f32 | v_ceil_f32 | VOP1 | Round the single-precision float input up to next integer and store the result in floating point format into a vector register. |
| v_ceil_f64 | v_ceil_f64 | VOP1 | Round the double-precision float input up to next integer and store the result in floating point format into a vector register. |
| v_clrexcp | v_clrexcp | VOP1 | Clear this wave's exception state in the vector ALU. |
| v_cndmask_b16 | v_cndmask_b16 | VOP3 | Copy data from one of two inputs based on the per-lane condition code and store the result into a vector register. |
| v_cndmask_b16_fake16 | v_cndmask_b16_fake16 | VOP2 | AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cndmask_b16_t16 | v_cndmask_b16_t16 | VOP2 | AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cndmask_b32 | v_cndmask_b32 | VOP2 | Copy data from one of two inputs based on the per-lane condition code and store the result into a vector register. |
| v_cos_bf16 | v_cos_bf16 | VOP1 | AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cos_f16 | v_cos_f16 | VOP1 | Calculate the trigonometric cosine of a half-precision float value using IEEE rules and store the result into a vector register. |
| v_cos_f32 | v_cos_f32 | VOP1 | Calculate the trigonometric cosine of a single-precision float value using IEEE rules and store the result into a vector register. |
| v_cubeid_f32 | v_cubeid_f32 | VOP3 | Compute the cubemap face ID of a 3D coordinate specified as three single-precision float inputs. |
| v_cubema_f32 | v_cubema_f32 | VOP3 | Compute the cubemap major axis of a 3D coordinate specified as three single-precision float inputs. |
| v_cubesc_f32 | v_cubesc_f32 | VOP3 | Compute the cubemap S coordinate of a 3D coordinate specified as three single-precision float inputs. |
| v_cubetc_f32 | v_cubetc_f32 | VOP3 | Compute the cubemap T coordinate of a 3D coordinate specified as three single-precision float inputs. |
| v_cvt_f16_bf8 | v_cvt_f16_bf8 | VOP1 | AMDGPU VOP1 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cvt_f16_f32 | v_cvt_f16_f32 | VOP1 | Convert from a single-precision float input to a half-precision float value and store the result into a vector register. |
| v_cvt_f16_f32_fake16 | v_cvt_f16_f32_fake16 | VOP1 | AMDGPU VOP1 vector instruction operating on f16/f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cvt_f16_f32_t16 | v_cvt_f16_f32_t16 | VOP1 | AMDGPU VOP1 vector instruction operating on f16/f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cvt_f16_fp8 | v_cvt_f16_fp8 | VOP1 | AMDGPU VOP1 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cvt_f16_i16 | v_cvt_f16_i16 | VOP1 | Convert from a signed 16-bit integer input to a half-precision float value and store the result into a vector register. |
| v_cvt_f16_u16 | v_cvt_f16_u16 | VOP1 | Convert from an unsigned 16-bit integer input to a half-precision float value and store the result into a vector register. |
| v_cvt_f32_bf16 | v_cvt_f32_bf16 | VOP1 | Convert from a BF16 float input to a single-precision float value and store the result into a vector register. |
| v_cvt_f32_bf8 | v_cvt_f32_bf8 | VOP1 | Convert from a BF8 float input to a single-precision float value and store the result into a vector register. |
| v_cvt_f32_bf8_op_sel | v_cvt_f32_bf8_op_sel | VOP1 | AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cvt_f32_f16 | v_cvt_f32_f16 | VOP1 | Convert from a half-precision float input to a single-precision float value and store the result into a vector register. |
| v_cvt_f32_f16_fake16 | v_cvt_f32_f16_fake16 | VOP1 | AMDGPU VOP1 vector instruction operating on f16/f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cvt_f32_f16_t16 | v_cvt_f32_f16_t16 | VOP1 | AMDGPU VOP1 vector instruction operating on f16/f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cvt_f32_f64 | v_cvt_f32_f64 | VOP1 | Convert from a double-precision float input to a single-precision float value and store the result into a vector register. |
| v_cvt_f32_fp8 | v_cvt_f32_fp8 | VOP1 | Convert from an FP8 float input to a single-precision float value and store the result into a vector register. |
| v_cvt_f32_fp8_gfx1250 | v_cvt_f32_fp8_gfx1250 | VOP1 | AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cvt_f32_fp8_op_sel | v_cvt_f32_fp8_op_sel | VOP1 | AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cvt_f32_i32 | v_cvt_f32_i32 VDST, S0 | VOP1 | Per-lane conversion from signed 32-bit integer to single-precision float. |
| v_cvt_f32_u32 | v_cvt_f32_u32 | VOP1 | Convert from an unsigned 32-bit integer input to a single-precision float value and store the result into a vector register. |
| v_cvt_f32_ubyte0 | v_cvt_f32_ubyte0 | VOP1 | Convert an unsigned byte in byte 0 of the input to a single-precision float value and store the result into a vector register. |
| v_cvt_f32_ubyte1 | v_cvt_f32_ubyte1 | VOP1 | Convert an unsigned byte in byte 1 of the input to a single-precision float value and store the result into a vector register. |
| v_cvt_f32_ubyte2 | v_cvt_f32_ubyte2 | VOP1 | Convert an unsigned byte in byte 2 of the input to a single-precision float value and store the result into a vector register. |
| v_cvt_f32_ubyte3 | v_cvt_f32_ubyte3 | VOP1 | Convert an unsigned byte in byte 3 of the input to a single-precision float value and store the result into a vector register. |
| v_cvt_f64_f32 | v_cvt_f64_f32 | VOP1 | Convert from a single-precision float input to a double-precision float value and store the result into a vector register. |
| v_cvt_f64_i32 | v_cvt_f64_i32 | VOP1 | Convert from a signed 32-bit integer input to a double-precision float value and store the result into a vector register. |
| v_cvt_f64_u32 | v_cvt_f64_u32 | VOP1 | Convert from an unsigned 32-bit integer input to a double-precision float value and store the result into a vector register. |
| v_cvt_flr_i32_f32 | v_cvt_flr_i32_f32 | VOP1 | Convert from a single-precision float input to a signed 32-bit integer value using round-down semantics (ignore the default rounding mode) and store… |
| v_cvt_i16_f16 | v_cvt_i16_f16 | VOP1 | Convert from a half-precision float input to a signed 16-bit integer value and store the result into a vector register. |
| v_cvt_i32_f32 | v_cvt_i32_f32 | VOP1 | Convert from a single-precision float input to a signed 32-bit integer value and store the result into a vector register. |
| v_cvt_i32_f64 | v_cvt_i32_f64 | VOP1 | Convert from a double-precision float input to a signed 32-bit integer value and store the result into a vector register. |
| v_cvt_i32_i16 | v_cvt_i32_i16 | VOP1 | Convert from a signed 16-bit integer input to a signed 32-bit integer value using sign extension and store the result into a vector register. |
| v_cvt_norm_i16_f16 | v_cvt_norm_i16_f16 | VOP1 | Convert from a half-precision float input to a signed normalized short and store the result into a vector register. |
| v_cvt_norm_u16_f16 | v_cvt_norm_u16_f16 | VOP1 | Convert from a half-precision float input to an unsigned normalized short and store the result into a vector register. |
| v_cvt_off_f32_i4 | v_cvt_off_f32_i4 | VOP1 | Convert from a signed 4-bit integer input to a single-precision float value using an offset table and store the result into a vector register. |
| v_cvt_pk_bf16_f32 | v_cvt_pk_bf16_f32 | VOP3 | Convert from two single-precision float inputs to a packed BF16 value and store the result into a vector register. |