v_cvt_f32_fp8 GPU Native ISA AMD Vector

Vector Arithmetic

v_cvt_f32_fp8

Convert from an FP8 float input to a single-precision float value and store the result into a vector register.

Encoding

Binary Layout (AMD CDNA 5)
0111111
31:25
VDST
24:17
unassigned
16
1101100
15:9
SRC0
8:0
 

The ENC_VOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 108 in OP rebuilds 0x7E00D800, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD CDNA 4 (opcode 84, field layout), AMD CDNA 3 (opcode 84, field layout). The same in AMD RDNA 4.

Format VOP1
Width 32 bits
Opcode 108
Identifier 0x7E00D800

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32-bit single-precision floating point value. (OPR_VGPR, FMT_NUM_F32)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: N/A (OPR_SRC, FMT_NUM_FP8)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

SDWA encoding allows SRC0_SEL to control which byte of S0 is converted. Only the BYTE selects of SRC0_SEL are legal. If this instruction is not encoded in SDWA then BYTE0 is implied.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

if SDWA_SRC0_SEL == BYTE1.b3 then D0.f32 = fp8_to_f32(S0[15 : 8].fp8) elsif SDWA_SRC0_SEL == BYTE2.b3 then D0.f32 = fp8_to_f32(S0[23 : 16].fp8) elsif SDWA_SRC0_SEL == BYTE3.b3 then D0.f32 = fp8_to_f32(S0[31 : 24].fp8) else // BYTE0 implied D0.f32 = fp8_to_f32(S0[7 : 0].fp8) endif

Example

v_cvt_f32_fp8 v5, v1 dpp8:[0,1,2,3,4,5,6,7]

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx1170_asm_vop1_dpp8-fake16.s). Not from an AMD document, and not authored here.

Sources