v_cvt_flr_i32_f32 GPU Native ISA AMD Vector

V CVT FLR I32 F32 Vector Arithmetic

v_cvt_flr_i32_f32

Convert from a single-precision float input to a signed 32-bit integer value using round-down semantics (ignore the default rounding mode) and store…

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP1) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP1
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

1ULP accuracy, denormals are supported.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Convert from a single-precision float input to a signed 32-bit integer value using round-down semantics (ignore the default rounding mode) and store the result into a vector register.

Semantics

D0.i32 = f32_to_i32(floor(S0.f32))

Example

v_cvt_flr_i32_f32 v5, v1

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources