v_cvt_flr_i32_f32 GPU Native ISA AMD Vector

Vector Arithmetic

v_cvt_flr_i32_f32

Convert from a single-precision float input to a signed 32-bit integer value using round-down semantics (ignore the default rounding mode) and store…

Also written as v_cvt_floor_i32_f32. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
0111111
31:25
VDST
24:17
00001101
16:9
SRC0
8:0
 

The ENC_VOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 13 in OP rebuilds 0x7E001A00, an identifier AMD lists for this encoding. The same in the other 5 generations that define it.

Format VOP1
Width 32 bits
Opcode 13
Identifier 0x7E001A00

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR, FMT_NUM_I32)
  • SRC0
    Read. N/A Data format: N/A (OPR_SRC, FMT_NUM_F32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP1 encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

1ULP accuracy, denormals are supported.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Convert from a single-precision float input to a signed 32-bit integer value using round-down semantics (ignore the default rounding mode) and store the result into a vector register.

Semantics

D0.i32 = f32_to_i32(floor(S0.f32))

Example

v_cvt_flr_i32_f32 v5, v1

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources